[mirror_ubuntu-artful-kernel.git] / drivers / infiniband / hw / bnxt_re / qplib_res.h

/*
 * Broadcom NetXtreme-E RoCE driver.
 *
 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * BSD license below:
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Description: QPLib resource manager (header)
 */

#ifndef __BNXT_QPLIB_RES_H__
#define __BNXT_QPLIB_RES_H__

extern const struct bnxt_qplib_gid bnxt_qplib_gid_zero;

#define PTR_CNT_PER_PG		(PAGE_SIZE / sizeof(void *))
#define PTR_MAX_IDX_PER_PG	(PTR_CNT_PER_PG - 1)
#define PTR_PG(x)		(((x) & ~PTR_MAX_IDX_PER_PG) / PTR_CNT_PER_PG)
#define PTR_IDX(x)		((x) & PTR_MAX_IDX_PER_PG)

#define HWQ_CMP(idx, hwq)	((idx) & ((hwq)->max_elements - 1))

#define HWQ_FREE_SLOTS(hwq)	(hwq->max_elements - \
				((HWQ_CMP(hwq->prod, hwq)\
				- HWQ_CMP(hwq->cons, hwq))\
				& (hwq->max_elements - 1)))
enum bnxt_qplib_hwq_type {
	HWQ_TYPE_CTX,
	HWQ_TYPE_QUEUE,
	HWQ_TYPE_L2_CMPL
};

#define MAX_PBL_LVL_0_PGS		1
#define MAX_PBL_LVL_1_PGS		512
#define MAX_PBL_LVL_1_PGS_SHIFT		9
#define MAX_PBL_LVL_1_PGS_FOR_LVL_2	256
#define MAX_PBL_LVL_2_PGS		(256 * 512)

enum bnxt_qplib_pbl_lvl {
	PBL_LVL_0,
	PBL_LVL_1,
	PBL_LVL_2,
	PBL_LVL_MAX
};

#define ROCE_PG_SIZE_4K		(4 * 1024)
#define ROCE_PG_SIZE_8K		(8 * 1024)
#define ROCE_PG_SIZE_64K	(64 * 1024)
#define ROCE_PG_SIZE_2M		(2 * 1024 * 1024)
#define ROCE_PG_SIZE_8M		(8 * 1024 * 1024)
#define ROCE_PG_SIZE_1G		(1024 * 1024 * 1024)

struct bnxt_qplib_pbl {
	u32				pg_count;
	u32				pg_size;
	void				**pg_arr;
	dma_addr_t			*pg_map_arr;
};

struct bnxt_qplib_hwq {
	struct pci_dev			*pdev;
	/* lock to protect qplib_hwq */
	spinlock_t			lock;
	struct bnxt_qplib_pbl		pbl[PBL_LVL_MAX];
	enum bnxt_qplib_pbl_lvl		level;		/* 0, 1, or 2 */
	/* ptr for easy access to the PBL entries */
	void				**pbl_ptr;
	/* ptr for easy access to the dma_addr */
	dma_addr_t			*pbl_dma_ptr;
	u32				max_elements;
	u16				element_size;	/* Size of each entry */

	u32				prod;		/* raw */
	u32				cons;		/* raw */
	u8				cp_bit;
	u8				is_user;
};

/* Tables */
struct bnxt_qplib_pd_tbl {
	unsigned long			*tbl;
	u32				max;
};

struct bnxt_qplib_sgid_tbl {
	struct bnxt_qplib_gid		*tbl;
	u16				*hw_id;
	u16				max;
	u16				active;
	void				*ctx;
};

struct bnxt_qplib_pkey_tbl {
	u16				*tbl;
	u16				max;
	u16				active;
};

struct bnxt_qplib_dpi {
	u32				dpi;
	void __iomem			*dbr;
	u64				umdbr;
};

struct bnxt_qplib_dpi_tbl {
	void				**app_tbl;
	unsigned long			*tbl;
	u16				max;
	void __iomem			*dbr_bar_reg_iomem;
	u64				unmapped_dbr;
};

struct bnxt_qplib_stats {
	dma_addr_t			dma_map;
	void				*dma;
	u32				size;
	u32				fw_id;
};

struct bnxt_qplib_vf_res {
	u32 max_qp_per_vf;
	u32 max_mrw_per_vf;
	u32 max_srq_per_vf;
	u32 max_cq_per_vf;
	u32 max_gid_per_vf;
};

#define BNXT_QPLIB_MAX_QP_CTX_ENTRY_SIZE	448
#define BNXT_QPLIB_MAX_SRQ_CTX_ENTRY_SIZE	64
#define BNXT_QPLIB_MAX_CQ_CTX_ENTRY_SIZE	64
#define BNXT_QPLIB_MAX_MRW_CTX_ENTRY_SIZE	128

struct bnxt_qplib_ctx {
	u32				qpc_count;
	struct bnxt_qplib_hwq		qpc_tbl;
	u32				mrw_count;
	struct bnxt_qplib_hwq		mrw_tbl;
	u32				srqc_count;
	struct bnxt_qplib_hwq		srqc_tbl;
	u32				cq_count;
	struct bnxt_qplib_hwq		cq_tbl;
	struct bnxt_qplib_hwq		tim_tbl;
#define MAX_TQM_ALLOC_REQ		32
#define MAX_TQM_ALLOC_BLK_SIZE		8
	u8				tqm_count[MAX_TQM_ALLOC_REQ];
	struct bnxt_qplib_hwq		tqm_pde;
	u32				tqm_pde_level;
	struct bnxt_qplib_hwq		tqm_tbl[MAX_TQM_ALLOC_REQ];
	struct bnxt_qplib_stats		stats;
	struct bnxt_qplib_vf_res	vf_res;
};

struct bnxt_qplib_res {
	struct pci_dev			*pdev;
	struct net_device		*netdev;

	struct bnxt_qplib_rcfw		*rcfw;

	struct bnxt_qplib_pd_tbl	pd_tbl;
	struct bnxt_qplib_sgid_tbl	sgid_tbl;
	struct bnxt_qplib_pkey_tbl	pkey_tbl;
	struct bnxt_qplib_dpi_tbl	dpi_tbl;
};

#define to_bnxt_qplib(ptr, type, member)	\
	container_of(ptr, type, member)

struct bnxt_qplib_pd;
struct bnxt_qplib_dev_attr;

void bnxt_qplib_free_hwq(struct pci_dev *pdev, struct bnxt_qplib_hwq *hwq);
int bnxt_qplib_alloc_init_hwq(struct pci_dev *pdev, struct bnxt_qplib_hwq *hwq,
			      struct scatterlist *sl, int nmap, u32 *elements,
			      u32 elements_per_page, u32 aux, u32 pg_size,
			      enum bnxt_qplib_hwq_type hwq_type);
void bnxt_qplib_get_guid(u8 *dev_addr, u8 *guid);
int bnxt_qplib_alloc_pd(struct bnxt_qplib_pd_tbl *pd_tbl,
			struct bnxt_qplib_pd *pd);
int bnxt_qplib_dealloc_pd(struct bnxt_qplib_res *res,
			  struct bnxt_qplib_pd_tbl *pd_tbl,
			  struct bnxt_qplib_pd *pd);
int bnxt_qplib_alloc_dpi(struct bnxt_qplib_dpi_tbl *dpit,
			 struct bnxt_qplib_dpi     *dpi,
			 void                      *app);
int bnxt_qplib_dealloc_dpi(struct bnxt_qplib_res *res,
			   struct bnxt_qplib_dpi_tbl *dpi_tbl,
			   struct bnxt_qplib_dpi *dpi);
void bnxt_qplib_cleanup_res(struct bnxt_qplib_res *res);
int bnxt_qplib_init_res(struct bnxt_qplib_res *res);
void bnxt_qplib_free_res(struct bnxt_qplib_res *res);
int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev,
			 struct net_device *netdev,
			 struct bnxt_qplib_dev_attr *dev_attr);
void bnxt_qplib_free_ctx(struct pci_dev *pdev,
			 struct bnxt_qplib_ctx *ctx);
int bnxt_qplib_alloc_ctx(struct pci_dev *pdev,
			 struct bnxt_qplib_ctx *ctx,
			 bool virt_fn);
#endif /* __BNXT_QPLIB_RES_H__ */
Commit	Line	Data
1ac5a404 SX	1	/*
	2	* Broadcom NetXtreme-E RoCE driver.
	3	*
	4	* Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
	5	* Broadcom refers to Broadcom Limited and/or its subsidiaries.
	6	*
	7	* This software is available to you under a choice of one of two
	8	* licenses. You may choose to be licensed under the terms of the GNU
	9	* General Public License (GPL) Version 2, available from the file
	10	* COPYING in the main directory of this source tree, or the
	11	* BSD license below:
	12	*
	13	* Redistribution and use in source and binary forms, with or without
	14	* modification, are permitted provided that the following conditions
	15	* are met:
	16	*
	17	* 1. Redistributions of source code must retain the above copyright
	18	* notice, this list of conditions and the following disclaimer.
	19	* 2. Redistributions in binary form must reproduce the above copyright
	20	* notice, this list of conditions and the following disclaimer in
	21	* the documentation and/or other materials provided with the
	22	* distribution.
	23	*
	24	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
	26	* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
	27	* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
	28	* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	29	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	30	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
	31	* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
	32	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
	33	* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
	34	* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	35	*
	36	* Description: QPLib resource manager (header)
	37	*/
	38
	39	#ifndef __BNXT_QPLIB_RES_H__
	40	#define __BNXT_QPLIB_RES_H__
	41
	42	extern const struct bnxt_qplib_gid bnxt_qplib_gid_zero;
	43
	44	#define PTR_CNT_PER_PG (PAGE_SIZE / sizeof(void *))
	45	#define PTR_MAX_IDX_PER_PG (PTR_CNT_PER_PG - 1)
	46	#define PTR_PG(x) (((x) & ~PTR_MAX_IDX_PER_PG) / PTR_CNT_PER_PG)
	47	#define PTR_IDX(x) ((x) & PTR_MAX_IDX_PER_PG)
	48
	49	#define HWQ_CMP(idx, hwq) ((idx) & ((hwq)->max_elements - 1))
	50
cc1ec769 DS	51	#define HWQ_FREE_SLOTS(hwq) (hwq->max_elements - \
	52	((HWQ_CMP(hwq->prod, hwq)\
	53	- HWQ_CMP(hwq->cons, hwq))\
	54	& (hwq->max_elements - 1)))
1ac5a404 SX	55	enum bnxt_qplib_hwq_type {
	56	HWQ_TYPE_CTX,
	57	HWQ_TYPE_QUEUE,
	58	HWQ_TYPE_L2_CMPL
	59	};
	60
	61	#define MAX_PBL_LVL_0_PGS 1
	62	#define MAX_PBL_LVL_1_PGS 512
	63	#define MAX_PBL_LVL_1_PGS_SHIFT 9
	64	#define MAX_PBL_LVL_1_PGS_FOR_LVL_2 256
	65	#define MAX_PBL_LVL_2_PGS (256 * 512)
	66
	67	enum bnxt_qplib_pbl_lvl {
	68	PBL_LVL_0,
	69	PBL_LVL_1,
	70	PBL_LVL_2,
	71	PBL_LVL_MAX
	72	};
	73
	74	#define ROCE_PG_SIZE_4K (4 * 1024)
	75	#define ROCE_PG_SIZE_8K (8 * 1024)
	76	#define ROCE_PG_SIZE_64K (64 * 1024)
	77	#define ROCE_PG_SIZE_2M (2 * 1024 * 1024)
	78	#define ROCE_PG_SIZE_8M (8 * 1024 * 1024)
	79	#define ROCE_PG_SIZE_1G (1024 * 1024 * 1024)
	80
	81	struct bnxt_qplib_pbl {
	82	u32 pg_count;
	83	u32 pg_size;
	84	void **pg_arr;
	85	dma_addr_t *pg_map_arr;
	86	};
	87
	88	struct bnxt_qplib_hwq {
	89	struct pci_dev *pdev;
	90	/* lock to protect qplib_hwq */
	91	spinlock_t lock;
	92	struct bnxt_qplib_pbl pbl[PBL_LVL_MAX];
	93	enum bnxt_qplib_pbl_lvl level; /* 0, 1, or 2 */
	94	/* ptr for easy access to the PBL entries */
	95	void **pbl_ptr;
	96	/* ptr for easy access to the dma_addr */
	97	dma_addr_t *pbl_dma_ptr;
	98	u32 max_elements;
	99	u16 element_size; /* Size of each entry */
	100
	101	u32 prod; /* raw */
	102	u32 cons; /* raw */
	103	u8 cp_bit;
	104	u8 is_user;
	105	};
	106
	107	/* Tables */
	108	struct bnxt_qplib_pd_tbl {
	109	unsigned long *tbl;
	110	u32 max;
	111	};
	112
	113	struct bnxt_qplib_sgid_tbl {
	114	struct bnxt_qplib_gid *tbl;
	115	u16 *hw_id;
	116	u16 max;
	117	u16 active;
	118	void *ctx;
119	};
120
121	struct bnxt_qplib_pkey_tbl {
122	u16 *tbl;
123	u16 max;
124	u16 active;
125	};
126
127	struct bnxt_qplib_dpi {
128	u32 dpi;
129	void __iomem *dbr;
130	u64 umdbr;
131	};
132
133	struct bnxt_qplib_dpi_tbl {
134	void **app_tbl;
135	unsigned long *tbl;
136	u16 max;
137	void __iomem *dbr_bar_reg_iomem;
138	u64 unmapped_dbr;
139	};
140
141	struct bnxt_qplib_stats {
142	dma_addr_t dma_map;
143	void *dma;
144	u32 size;
145	u32 fw_id;
146	};
147
148	struct bnxt_qplib_vf_res {
149	u32 max_qp_per_vf;
150	u32 max_mrw_per_vf;
151	u32 max_srq_per_vf;
152	u32 max_cq_per_vf;
153	u32 max_gid_per_vf;
154	};
155
156	#define BNXT_QPLIB_MAX_QP_CTX_ENTRY_SIZE 448
157	#define BNXT_QPLIB_MAX_SRQ_CTX_ENTRY_SIZE 64
158	#define BNXT_QPLIB_MAX_CQ_CTX_ENTRY_SIZE 64
159	#define BNXT_QPLIB_MAX_MRW_CTX_ENTRY_SIZE 128
160
161	struct bnxt_qplib_ctx {
162	u32 qpc_count;
163	struct bnxt_qplib_hwq qpc_tbl;
164	u32 mrw_count;
165	struct bnxt_qplib_hwq mrw_tbl;
166	u32 srqc_count;
167	struct bnxt_qplib_hwq srqc_tbl;
168	u32 cq_count;
169	struct bnxt_qplib_hwq cq_tbl;
170	struct bnxt_qplib_hwq tim_tbl;
171	#define MAX_TQM_ALLOC_REQ 32
172	#define MAX_TQM_ALLOC_BLK_SIZE 8
173	u8 tqm_count[MAX_TQM_ALLOC_REQ];
174	struct bnxt_qplib_hwq tqm_pde;
175	u32 tqm_pde_level;
176	struct bnxt_qplib_hwq tqm_tbl[MAX_TQM_ALLOC_REQ];
177	struct bnxt_qplib_stats stats;
178	struct bnxt_qplib_vf_res vf_res;
179	};
180
181	struct bnxt_qplib_res {
182	struct pci_dev *pdev;
183	struct net_device *netdev;
184
185	struct bnxt_qplib_rcfw *rcfw;
186
187	struct bnxt_qplib_pd_tbl pd_tbl;
188	struct bnxt_qplib_sgid_tbl sgid_tbl;
189	struct bnxt_qplib_pkey_tbl pkey_tbl;
190	struct bnxt_qplib_dpi_tbl dpi_tbl;
191	};
192
193	#define to_bnxt_qplib(ptr, type, member) \
194	container_of(ptr, type, member)
195
196	struct bnxt_qplib_pd;
197	struct bnxt_qplib_dev_attr;
198
199	void bnxt_qplib_free_hwq(struct pci_dev pdev, struct bnxt_qplib_hwq hwq);
200	int bnxt_qplib_alloc_init_hwq(struct pci_dev pdev, struct bnxt_qplib_hwq hwq,
201	struct scatterlist sl, int nmap, u32 elements,
202	u32 elements_per_page, u32 aux, u32 pg_size,
203	enum bnxt_qplib_hwq_type hwq_type);
204	void bnxt_qplib_get_guid(u8 dev_addr, u8 guid);
205	int bnxt_qplib_alloc_pd(struct bnxt_qplib_pd_tbl *pd_tbl,
206	struct bnxt_qplib_pd *pd);
207	int bnxt_qplib_dealloc_pd(struct bnxt_qplib_res *res,
208	struct bnxt_qplib_pd_tbl *pd_tbl,
209	struct bnxt_qplib_pd *pd);
210	int bnxt_qplib_alloc_dpi(struct bnxt_qplib_dpi_tbl *dpit,
211	struct bnxt_qplib_dpi *dpi,
212	void *app);
213	int bnxt_qplib_dealloc_dpi(struct bnxt_qplib_res *res,
214	struct bnxt_qplib_dpi_tbl *dpi_tbl,
215	struct bnxt_qplib_dpi *dpi);
216	void bnxt_qplib_cleanup_res(struct bnxt_qplib_res *res);
217	int bnxt_qplib_init_res(struct bnxt_qplib_res *res);
218	void bnxt_qplib_free_res(struct bnxt_qplib_res *res);
219	int bnxt_qplib_alloc_res(struct bnxt_qplib_res res, struct pci_dev pdev,
220	struct net_device *netdev,
221	struct bnxt_qplib_dev_attr *dev_attr);
222	void bnxt_qplib_free_ctx(struct pci_dev *pdev,
223	struct bnxt_qplib_ctx *ctx);
224	int bnxt_qplib_alloc_ctx(struct pci_dev *pdev,
225	struct bnxt_qplib_ctx *ctx,
226	bool virt_fn);
227	#endif /* __BNXT_QPLIB_RES_H__ */