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b038ced7 SW |
1 | /* |
2 | * Copyright (c) 2006 Chelsio, Inc. All rights reserved. | |
b038ced7 SW |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | #include <asm/delay.h> | |
33 | ||
34 | #include <linux/mutex.h> | |
35 | #include <linux/netdevice.h> | |
36 | #include <linux/sched.h> | |
37 | #include <linux/spinlock.h> | |
38 | #include <linux/pci.h> | |
c3bb1092 | 39 | #include <linux/dma-mapping.h> |
881d966b | 40 | #include <net/net_namespace.h> |
b038ced7 SW |
41 | |
42 | #include "cxio_resource.h" | |
43 | #include "cxio_hal.h" | |
44 | #include "cxgb3_offload.h" | |
45 | #include "sge_defs.h" | |
46 | ||
47 | static LIST_HEAD(rdev_list); | |
48 | static cxio_hal_ev_callback_func_t cxio_ev_cb = NULL; | |
49 | ||
2b540355 | 50 | static struct cxio_rdev *cxio_hal_find_rdev_by_name(char *dev_name) |
b038ced7 SW |
51 | { |
52 | struct cxio_rdev *rdev; | |
53 | ||
54 | list_for_each_entry(rdev, &rdev_list, entry) | |
55 | if (!strcmp(rdev->dev_name, dev_name)) | |
56 | return rdev; | |
57 | return NULL; | |
58 | } | |
59 | ||
2b540355 | 60 | static struct cxio_rdev *cxio_hal_find_rdev_by_t3cdev(struct t3cdev *tdev) |
b038ced7 SW |
61 | { |
62 | struct cxio_rdev *rdev; | |
63 | ||
64 | list_for_each_entry(rdev, &rdev_list, entry) | |
65 | if (rdev->t3cdev_p == tdev) | |
66 | return rdev; | |
67 | return NULL; | |
68 | } | |
69 | ||
70 | int cxio_hal_cq_op(struct cxio_rdev *rdev_p, struct t3_cq *cq, | |
71 | enum t3_cq_opcode op, u32 credit) | |
72 | { | |
73 | int ret; | |
74 | struct t3_cqe *cqe; | |
75 | u32 rptr; | |
76 | ||
77 | struct rdma_cq_op setup; | |
78 | setup.id = cq->cqid; | |
79 | setup.credits = (op == CQ_CREDIT_UPDATE) ? credit : 0; | |
80 | setup.op = op; | |
81 | ret = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_OP, &setup); | |
82 | ||
83 | if ((ret < 0) || (op == CQ_CREDIT_UPDATE)) | |
84 | return ret; | |
85 | ||
86 | /* | |
87 | * If the rearm returned an index other than our current index, | |
88 | * then there might be CQE's in flight (being DMA'd). We must wait | |
89 | * here for them to complete or the consumer can miss a notification. | |
90 | */ | |
91 | if (Q_PTR2IDX((cq->rptr), cq->size_log2) != ret) { | |
92 | int i=0; | |
93 | ||
94 | rptr = cq->rptr; | |
95 | ||
96 | /* | |
97 | * Keep the generation correct by bumping rptr until it | |
98 | * matches the index returned by the rearm - 1. | |
99 | */ | |
100 | while (Q_PTR2IDX((rptr+1), cq->size_log2) != ret) | |
101 | rptr++; | |
102 | ||
103 | /* | |
104 | * Now rptr is the index for the (last) cqe that was | |
105 | * in-flight at the time the HW rearmed the CQ. We | |
106 | * spin until that CQE is valid. | |
107 | */ | |
108 | cqe = cq->queue + Q_PTR2IDX(rptr, cq->size_log2); | |
109 | while (!CQ_VLD_ENTRY(rptr, cq->size_log2, cqe)) { | |
110 | udelay(1); | |
111 | if (i++ > 1000000) { | |
112 | BUG_ON(1); | |
113 | printk(KERN_ERR "%s: stalled rnic\n", | |
114 | rdev_p->dev_name); | |
115 | return -EIO; | |
116 | } | |
117 | } | |
ed23a727 RD |
118 | |
119 | return 1; | |
b038ced7 | 120 | } |
ed23a727 | 121 | |
b038ced7 SW |
122 | return 0; |
123 | } | |
124 | ||
2b540355 | 125 | static int cxio_hal_clear_cq_ctx(struct cxio_rdev *rdev_p, u32 cqid) |
b038ced7 SW |
126 | { |
127 | struct rdma_cq_setup setup; | |
128 | setup.id = cqid; | |
129 | setup.base_addr = 0; /* NULL address */ | |
130 | setup.size = 0; /* disaable the CQ */ | |
131 | setup.credits = 0; | |
132 | setup.credit_thres = 0; | |
133 | setup.ovfl_mode = 0; | |
134 | return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup)); | |
135 | } | |
136 | ||
2b540355 | 137 | static int cxio_hal_clear_qp_ctx(struct cxio_rdev *rdev_p, u32 qpid) |
b038ced7 SW |
138 | { |
139 | u64 sge_cmd; | |
140 | struct t3_modify_qp_wr *wqe; | |
141 | struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_KERNEL); | |
142 | if (!skb) { | |
143 | PDBG("%s alloc_skb failed\n", __FUNCTION__); | |
144 | return -ENOMEM; | |
145 | } | |
146 | wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe)); | |
147 | memset(wqe, 0, sizeof(*wqe)); | |
6eda48d1 | 148 | build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD, 3, 0, qpid, 7); |
b038ced7 SW |
149 | wqe->flags = cpu_to_be32(MODQP_WRITE_EC); |
150 | sge_cmd = qpid << 8 | 3; | |
151 | wqe->sge_cmd = cpu_to_be64(sge_cmd); | |
152 | skb->priority = CPL_PRIORITY_CONTROL; | |
153 | return (cxgb3_ofld_send(rdev_p->t3cdev_p, skb)); | |
154 | } | |
155 | ||
156 | int cxio_create_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq) | |
157 | { | |
158 | struct rdma_cq_setup setup; | |
159 | int size = (1UL << (cq->size_log2)) * sizeof(struct t3_cqe); | |
160 | ||
161 | cq->cqid = cxio_hal_get_cqid(rdev_p->rscp); | |
162 | if (!cq->cqid) | |
163 | return -ENOMEM; | |
164 | cq->sw_queue = kzalloc(size, GFP_KERNEL); | |
165 | if (!cq->sw_queue) | |
166 | return -ENOMEM; | |
167 | cq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev), | |
168 | (1UL << (cq->size_log2)) * | |
169 | sizeof(struct t3_cqe), | |
170 | &(cq->dma_addr), GFP_KERNEL); | |
171 | if (!cq->queue) { | |
172 | kfree(cq->sw_queue); | |
173 | return -ENOMEM; | |
174 | } | |
175 | pci_unmap_addr_set(cq, mapping, cq->dma_addr); | |
176 | memset(cq->queue, 0, size); | |
177 | setup.id = cq->cqid; | |
178 | setup.base_addr = (u64) (cq->dma_addr); | |
179 | setup.size = 1UL << cq->size_log2; | |
180 | setup.credits = 65535; | |
181 | setup.credit_thres = 1; | |
182 | if (rdev_p->t3cdev_p->type == T3B) | |
183 | setup.ovfl_mode = 0; | |
184 | else | |
185 | setup.ovfl_mode = 1; | |
186 | return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup)); | |
187 | } | |
188 | ||
189 | int cxio_resize_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq) | |
190 | { | |
191 | struct rdma_cq_setup setup; | |
192 | setup.id = cq->cqid; | |
193 | setup.base_addr = (u64) (cq->dma_addr); | |
194 | setup.size = 1UL << cq->size_log2; | |
195 | setup.credits = setup.size; | |
196 | setup.credit_thres = setup.size; /* TBD: overflow recovery */ | |
197 | setup.ovfl_mode = 1; | |
198 | return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup)); | |
199 | } | |
200 | ||
201 | static u32 get_qpid(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx) | |
202 | { | |
203 | struct cxio_qpid_list *entry; | |
204 | u32 qpid; | |
205 | int i; | |
206 | ||
207 | mutex_lock(&uctx->lock); | |
208 | if (!list_empty(&uctx->qpids)) { | |
209 | entry = list_entry(uctx->qpids.next, struct cxio_qpid_list, | |
210 | entry); | |
211 | list_del(&entry->entry); | |
212 | qpid = entry->qpid; | |
213 | kfree(entry); | |
214 | } else { | |
215 | qpid = cxio_hal_get_qpid(rdev_p->rscp); | |
216 | if (!qpid) | |
217 | goto out; | |
218 | for (i = qpid+1; i & rdev_p->qpmask; i++) { | |
219 | entry = kmalloc(sizeof *entry, GFP_KERNEL); | |
220 | if (!entry) | |
221 | break; | |
222 | entry->qpid = i; | |
223 | list_add_tail(&entry->entry, &uctx->qpids); | |
224 | } | |
225 | } | |
226 | out: | |
227 | mutex_unlock(&uctx->lock); | |
228 | PDBG("%s qpid 0x%x\n", __FUNCTION__, qpid); | |
229 | return qpid; | |
230 | } | |
231 | ||
232 | static void put_qpid(struct cxio_rdev *rdev_p, u32 qpid, | |
233 | struct cxio_ucontext *uctx) | |
234 | { | |
235 | struct cxio_qpid_list *entry; | |
236 | ||
237 | entry = kmalloc(sizeof *entry, GFP_KERNEL); | |
238 | if (!entry) | |
239 | return; | |
240 | PDBG("%s qpid 0x%x\n", __FUNCTION__, qpid); | |
241 | entry->qpid = qpid; | |
242 | mutex_lock(&uctx->lock); | |
243 | list_add_tail(&entry->entry, &uctx->qpids); | |
244 | mutex_unlock(&uctx->lock); | |
245 | } | |
246 | ||
247 | void cxio_release_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx) | |
248 | { | |
249 | struct list_head *pos, *nxt; | |
250 | struct cxio_qpid_list *entry; | |
251 | ||
252 | mutex_lock(&uctx->lock); | |
253 | list_for_each_safe(pos, nxt, &uctx->qpids) { | |
254 | entry = list_entry(pos, struct cxio_qpid_list, entry); | |
255 | list_del_init(&entry->entry); | |
256 | if (!(entry->qpid & rdev_p->qpmask)) | |
257 | cxio_hal_put_qpid(rdev_p->rscp, entry->qpid); | |
258 | kfree(entry); | |
259 | } | |
260 | mutex_unlock(&uctx->lock); | |
261 | } | |
262 | ||
263 | void cxio_init_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx) | |
264 | { | |
265 | INIT_LIST_HEAD(&uctx->qpids); | |
266 | mutex_init(&uctx->lock); | |
267 | } | |
268 | ||
269 | int cxio_create_qp(struct cxio_rdev *rdev_p, u32 kernel_domain, | |
270 | struct t3_wq *wq, struct cxio_ucontext *uctx) | |
271 | { | |
272 | int depth = 1UL << wq->size_log2; | |
273 | int rqsize = 1UL << wq->rq_size_log2; | |
274 | ||
275 | wq->qpid = get_qpid(rdev_p, uctx); | |
276 | if (!wq->qpid) | |
277 | return -ENOMEM; | |
278 | ||
279 | wq->rq = kzalloc(depth * sizeof(u64), GFP_KERNEL); | |
280 | if (!wq->rq) | |
281 | goto err1; | |
282 | ||
283 | wq->rq_addr = cxio_hal_rqtpool_alloc(rdev_p, rqsize); | |
284 | if (!wq->rq_addr) | |
285 | goto err2; | |
286 | ||
287 | wq->sq = kzalloc(depth * sizeof(struct t3_swsq), GFP_KERNEL); | |
288 | if (!wq->sq) | |
289 | goto err3; | |
290 | ||
291 | wq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev), | |
292 | depth * sizeof(union t3_wr), | |
293 | &(wq->dma_addr), GFP_KERNEL); | |
294 | if (!wq->queue) | |
295 | goto err4; | |
296 | ||
297 | memset(wq->queue, 0, depth * sizeof(union t3_wr)); | |
298 | pci_unmap_addr_set(wq, mapping, wq->dma_addr); | |
299 | wq->doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr; | |
300 | if (!kernel_domain) | |
301 | wq->udb = (u64)rdev_p->rnic_info.udbell_physbase + | |
302 | (wq->qpid << rdev_p->qpshift); | |
303 | PDBG("%s qpid 0x%x doorbell 0x%p udb 0x%llx\n", __FUNCTION__, | |
304 | wq->qpid, wq->doorbell, (unsigned long long) wq->udb); | |
305 | return 0; | |
306 | err4: | |
307 | kfree(wq->sq); | |
308 | err3: | |
309 | cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, rqsize); | |
310 | err2: | |
311 | kfree(wq->rq); | |
312 | err1: | |
313 | put_qpid(rdev_p, wq->qpid, uctx); | |
314 | return -ENOMEM; | |
315 | } | |
316 | ||
317 | int cxio_destroy_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq) | |
318 | { | |
319 | int err; | |
320 | err = cxio_hal_clear_cq_ctx(rdev_p, cq->cqid); | |
321 | kfree(cq->sw_queue); | |
322 | dma_free_coherent(&(rdev_p->rnic_info.pdev->dev), | |
323 | (1UL << (cq->size_log2)) | |
324 | * sizeof(struct t3_cqe), cq->queue, | |
325 | pci_unmap_addr(cq, mapping)); | |
326 | cxio_hal_put_cqid(rdev_p->rscp, cq->cqid); | |
327 | return err; | |
328 | } | |
329 | ||
330 | int cxio_destroy_qp(struct cxio_rdev *rdev_p, struct t3_wq *wq, | |
331 | struct cxio_ucontext *uctx) | |
332 | { | |
333 | dma_free_coherent(&(rdev_p->rnic_info.pdev->dev), | |
334 | (1UL << (wq->size_log2)) | |
335 | * sizeof(union t3_wr), wq->queue, | |
336 | pci_unmap_addr(wq, mapping)); | |
337 | kfree(wq->sq); | |
338 | cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, (1UL << wq->rq_size_log2)); | |
339 | kfree(wq->rq); | |
340 | put_qpid(rdev_p, wq->qpid, uctx); | |
341 | return 0; | |
342 | } | |
343 | ||
344 | static void insert_recv_cqe(struct t3_wq *wq, struct t3_cq *cq) | |
345 | { | |
346 | struct t3_cqe cqe; | |
347 | ||
348 | PDBG("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __FUNCTION__, | |
349 | wq, cq, cq->sw_rptr, cq->sw_wptr); | |
350 | memset(&cqe, 0, sizeof(cqe)); | |
351 | cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) | | |
352 | V_CQE_OPCODE(T3_SEND) | | |
353 | V_CQE_TYPE(0) | | |
354 | V_CQE_SWCQE(1) | | |
355 | V_CQE_QPID(wq->qpid) | | |
356 | V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr, | |
357 | cq->size_log2))); | |
358 | *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe; | |
359 | cq->sw_wptr++; | |
360 | } | |
361 | ||
362 | void cxio_flush_rq(struct t3_wq *wq, struct t3_cq *cq, int count) | |
363 | { | |
364 | u32 ptr; | |
365 | ||
366 | PDBG("%s wq %p cq %p\n", __FUNCTION__, wq, cq); | |
367 | ||
368 | /* flush RQ */ | |
369 | PDBG("%s rq_rptr %u rq_wptr %u skip count %u\n", __FUNCTION__, | |
370 | wq->rq_rptr, wq->rq_wptr, count); | |
371 | ptr = wq->rq_rptr + count; | |
372 | while (ptr++ != wq->rq_wptr) | |
373 | insert_recv_cqe(wq, cq); | |
374 | } | |
375 | ||
376 | static void insert_sq_cqe(struct t3_wq *wq, struct t3_cq *cq, | |
377 | struct t3_swsq *sqp) | |
378 | { | |
379 | struct t3_cqe cqe; | |
380 | ||
381 | PDBG("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __FUNCTION__, | |
382 | wq, cq, cq->sw_rptr, cq->sw_wptr); | |
383 | memset(&cqe, 0, sizeof(cqe)); | |
384 | cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) | | |
385 | V_CQE_OPCODE(sqp->opcode) | | |
386 | V_CQE_TYPE(1) | | |
387 | V_CQE_SWCQE(1) | | |
388 | V_CQE_QPID(wq->qpid) | | |
389 | V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr, | |
390 | cq->size_log2))); | |
391 | cqe.u.scqe.wrid_hi = sqp->sq_wptr; | |
392 | ||
393 | *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe; | |
394 | cq->sw_wptr++; | |
395 | } | |
396 | ||
397 | void cxio_flush_sq(struct t3_wq *wq, struct t3_cq *cq, int count) | |
398 | { | |
399 | __u32 ptr; | |
400 | struct t3_swsq *sqp = wq->sq + Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2); | |
401 | ||
402 | ptr = wq->sq_rptr + count; | |
403 | sqp += count; | |
404 | while (ptr != wq->sq_wptr) { | |
405 | insert_sq_cqe(wq, cq, sqp); | |
406 | sqp++; | |
407 | ptr++; | |
408 | } | |
409 | } | |
410 | ||
411 | /* | |
412 | * Move all CQEs from the HWCQ into the SWCQ. | |
413 | */ | |
414 | void cxio_flush_hw_cq(struct t3_cq *cq) | |
415 | { | |
416 | struct t3_cqe *cqe, *swcqe; | |
417 | ||
418 | PDBG("%s cq %p cqid 0x%x\n", __FUNCTION__, cq, cq->cqid); | |
419 | cqe = cxio_next_hw_cqe(cq); | |
420 | while (cqe) { | |
421 | PDBG("%s flushing hwcq rptr 0x%x to swcq wptr 0x%x\n", | |
422 | __FUNCTION__, cq->rptr, cq->sw_wptr); | |
423 | swcqe = cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2); | |
424 | *swcqe = *cqe; | |
425 | swcqe->header |= cpu_to_be32(V_CQE_SWCQE(1)); | |
426 | cq->sw_wptr++; | |
427 | cq->rptr++; | |
428 | cqe = cxio_next_hw_cqe(cq); | |
429 | } | |
430 | } | |
431 | ||
2b540355 | 432 | static int cqe_completes_wr(struct t3_cqe *cqe, struct t3_wq *wq) |
b038ced7 SW |
433 | { |
434 | if (CQE_OPCODE(*cqe) == T3_TERMINATE) | |
435 | return 0; | |
436 | ||
437 | if ((CQE_OPCODE(*cqe) == T3_RDMA_WRITE) && RQ_TYPE(*cqe)) | |
438 | return 0; | |
439 | ||
440 | if ((CQE_OPCODE(*cqe) == T3_READ_RESP) && SQ_TYPE(*cqe)) | |
441 | return 0; | |
442 | ||
443 | if ((CQE_OPCODE(*cqe) == T3_SEND) && RQ_TYPE(*cqe) && | |
444 | Q_EMPTY(wq->rq_rptr, wq->rq_wptr)) | |
445 | return 0; | |
446 | ||
447 | return 1; | |
448 | } | |
449 | ||
450 | void cxio_count_scqes(struct t3_cq *cq, struct t3_wq *wq, int *count) | |
451 | { | |
452 | struct t3_cqe *cqe; | |
453 | u32 ptr; | |
454 | ||
455 | *count = 0; | |
456 | ptr = cq->sw_rptr; | |
457 | while (!Q_EMPTY(ptr, cq->sw_wptr)) { | |
458 | cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2)); | |
459 | if ((SQ_TYPE(*cqe) || (CQE_OPCODE(*cqe) == T3_READ_RESP)) && | |
460 | (CQE_QPID(*cqe) == wq->qpid)) | |
461 | (*count)++; | |
462 | ptr++; | |
463 | } | |
464 | PDBG("%s cq %p count %d\n", __FUNCTION__, cq, *count); | |
465 | } | |
466 | ||
467 | void cxio_count_rcqes(struct t3_cq *cq, struct t3_wq *wq, int *count) | |
468 | { | |
469 | struct t3_cqe *cqe; | |
470 | u32 ptr; | |
471 | ||
472 | *count = 0; | |
473 | PDBG("%s count zero %d\n", __FUNCTION__, *count); | |
474 | ptr = cq->sw_rptr; | |
475 | while (!Q_EMPTY(ptr, cq->sw_wptr)) { | |
476 | cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2)); | |
477 | if (RQ_TYPE(*cqe) && (CQE_OPCODE(*cqe) != T3_READ_RESP) && | |
478 | (CQE_QPID(*cqe) == wq->qpid) && cqe_completes_wr(cqe, wq)) | |
479 | (*count)++; | |
480 | ptr++; | |
481 | } | |
482 | PDBG("%s cq %p count %d\n", __FUNCTION__, cq, *count); | |
483 | } | |
484 | ||
485 | static int cxio_hal_init_ctrl_cq(struct cxio_rdev *rdev_p) | |
486 | { | |
487 | struct rdma_cq_setup setup; | |
488 | setup.id = 0; | |
489 | setup.base_addr = 0; /* NULL address */ | |
490 | setup.size = 1; /* enable the CQ */ | |
491 | setup.credits = 0; | |
492 | ||
493 | /* force SGE to redirect to RspQ and interrupt */ | |
494 | setup.credit_thres = 0; | |
495 | setup.ovfl_mode = 1; | |
496 | return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup)); | |
497 | } | |
498 | ||
499 | static int cxio_hal_init_ctrl_qp(struct cxio_rdev *rdev_p) | |
500 | { | |
501 | int err; | |
502 | u64 sge_cmd, ctx0, ctx1; | |
503 | u64 base_addr; | |
504 | struct t3_modify_qp_wr *wqe; | |
ed6ee517 | 505 | struct sk_buff *skb; |
b038ced7 | 506 | |
ed6ee517 | 507 | skb = alloc_skb(sizeof(*wqe), GFP_KERNEL); |
b038ced7 SW |
508 | if (!skb) { |
509 | PDBG("%s alloc_skb failed\n", __FUNCTION__); | |
510 | return -ENOMEM; | |
511 | } | |
512 | err = cxio_hal_init_ctrl_cq(rdev_p); | |
513 | if (err) { | |
514 | PDBG("%s err %d initializing ctrl_cq\n", __FUNCTION__, err); | |
ed6ee517 | 515 | goto err; |
b038ced7 SW |
516 | } |
517 | rdev_p->ctrl_qp.workq = dma_alloc_coherent( | |
518 | &(rdev_p->rnic_info.pdev->dev), | |
519 | (1 << T3_CTRL_QP_SIZE_LOG2) * | |
520 | sizeof(union t3_wr), | |
521 | &(rdev_p->ctrl_qp.dma_addr), | |
522 | GFP_KERNEL); | |
523 | if (!rdev_p->ctrl_qp.workq) { | |
524 | PDBG("%s dma_alloc_coherent failed\n", __FUNCTION__); | |
ed6ee517 SW |
525 | err = -ENOMEM; |
526 | goto err; | |
b038ced7 SW |
527 | } |
528 | pci_unmap_addr_set(&rdev_p->ctrl_qp, mapping, | |
529 | rdev_p->ctrl_qp.dma_addr); | |
530 | rdev_p->ctrl_qp.doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr; | |
531 | memset(rdev_p->ctrl_qp.workq, 0, | |
532 | (1 << T3_CTRL_QP_SIZE_LOG2) * sizeof(union t3_wr)); | |
533 | ||
534 | mutex_init(&rdev_p->ctrl_qp.lock); | |
535 | init_waitqueue_head(&rdev_p->ctrl_qp.waitq); | |
536 | ||
537 | /* update HW Ctrl QP context */ | |
538 | base_addr = rdev_p->ctrl_qp.dma_addr; | |
539 | base_addr >>= 12; | |
540 | ctx0 = (V_EC_SIZE((1 << T3_CTRL_QP_SIZE_LOG2)) | | |
541 | V_EC_BASE_LO((u32) base_addr & 0xffff)); | |
542 | ctx0 <<= 32; | |
543 | ctx0 |= V_EC_CREDITS(FW_WR_NUM); | |
544 | base_addr >>= 16; | |
545 | ctx1 = (u32) base_addr; | |
546 | base_addr >>= 32; | |
547 | ctx1 |= ((u64) (V_EC_BASE_HI((u32) base_addr & 0xf) | V_EC_RESPQ(0) | | |
548 | V_EC_TYPE(0) | V_EC_GEN(1) | | |
549 | V_EC_UP_TOKEN(T3_CTL_QP_TID) | F_EC_VALID)) << 32; | |
550 | wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe)); | |
551 | memset(wqe, 0, sizeof(*wqe)); | |
6eda48d1 | 552 | build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD, 0, 0, |
b038ced7 SW |
553 | T3_CTL_QP_TID, 7); |
554 | wqe->flags = cpu_to_be32(MODQP_WRITE_EC); | |
555 | sge_cmd = (3ULL << 56) | FW_RI_SGEEC_START << 8 | 3; | |
556 | wqe->sge_cmd = cpu_to_be64(sge_cmd); | |
557 | wqe->ctx1 = cpu_to_be64(ctx1); | |
558 | wqe->ctx0 = cpu_to_be64(ctx0); | |
559 | PDBG("CtrlQP dma_addr 0x%llx workq %p size %d\n", | |
560 | (unsigned long long) rdev_p->ctrl_qp.dma_addr, | |
561 | rdev_p->ctrl_qp.workq, 1 << T3_CTRL_QP_SIZE_LOG2); | |
562 | skb->priority = CPL_PRIORITY_CONTROL; | |
563 | return (cxgb3_ofld_send(rdev_p->t3cdev_p, skb)); | |
ed6ee517 SW |
564 | err: |
565 | kfree_skb(skb); | |
566 | return err; | |
b038ced7 SW |
567 | } |
568 | ||
569 | static int cxio_hal_destroy_ctrl_qp(struct cxio_rdev *rdev_p) | |
570 | { | |
571 | dma_free_coherent(&(rdev_p->rnic_info.pdev->dev), | |
572 | (1UL << T3_CTRL_QP_SIZE_LOG2) | |
573 | * sizeof(union t3_wr), rdev_p->ctrl_qp.workq, | |
574 | pci_unmap_addr(&rdev_p->ctrl_qp, mapping)); | |
575 | return cxio_hal_clear_qp_ctx(rdev_p, T3_CTRL_QP_ID); | |
576 | } | |
577 | ||
578 | /* write len bytes of data into addr (32B aligned address) | |
579 | * If data is NULL, clear len byte of memory to zero. | |
580 | * caller aquires the ctrl_qp lock before the call | |
581 | */ | |
582 | static int cxio_hal_ctrl_qp_write_mem(struct cxio_rdev *rdev_p, u32 addr, | |
583 | u32 len, void *data, int completion) | |
584 | { | |
585 | u32 i, nr_wqe, copy_len; | |
586 | u8 *copy_data; | |
587 | u8 wr_len, utx_len; /* lenght in 8 byte flit */ | |
588 | enum t3_wr_flags flag; | |
589 | __be64 *wqe; | |
590 | u64 utx_cmd; | |
591 | addr &= 0x7FFFFFF; | |
592 | nr_wqe = len % 96 ? len / 96 + 1 : len / 96; /* 96B max per WQE */ | |
593 | PDBG("%s wptr 0x%x rptr 0x%x len %d, nr_wqe %d data %p addr 0x%0x\n", | |
594 | __FUNCTION__, rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, len, | |
595 | nr_wqe, data, addr); | |
596 | utx_len = 3; /* in 32B unit */ | |
597 | for (i = 0; i < nr_wqe; i++) { | |
598 | if (Q_FULL(rdev_p->ctrl_qp.rptr, rdev_p->ctrl_qp.wptr, | |
599 | T3_CTRL_QP_SIZE_LOG2)) { | |
600 | PDBG("%s ctrl_qp full wtpr 0x%0x rptr 0x%0x, " | |
601 | "wait for more space i %d\n", __FUNCTION__, | |
602 | rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, i); | |
603 | if (wait_event_interruptible(rdev_p->ctrl_qp.waitq, | |
604 | !Q_FULL(rdev_p->ctrl_qp.rptr, | |
605 | rdev_p->ctrl_qp.wptr, | |
606 | T3_CTRL_QP_SIZE_LOG2))) { | |
607 | PDBG("%s ctrl_qp workq interrupted\n", | |
608 | __FUNCTION__); | |
609 | return -ERESTARTSYS; | |
610 | } | |
611 | PDBG("%s ctrl_qp wakeup, continue posting work request " | |
612 | "i %d\n", __FUNCTION__, i); | |
613 | } | |
614 | wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr % | |
615 | (1 << T3_CTRL_QP_SIZE_LOG2))); | |
616 | flag = 0; | |
617 | if (i == (nr_wqe - 1)) { | |
618 | /* last WQE */ | |
619 | flag = completion ? T3_COMPLETION_FLAG : 0; | |
620 | if (len % 32) | |
621 | utx_len = len / 32 + 1; | |
622 | else | |
623 | utx_len = len / 32; | |
624 | } | |
625 | ||
626 | /* | |
627 | * Force a CQE to return the credit to the workq in case | |
628 | * we posted more than half the max QP size of WRs | |
629 | */ | |
630 | if ((i != 0) && | |
631 | (i % (((1 << T3_CTRL_QP_SIZE_LOG2)) >> 1) == 0)) { | |
632 | flag = T3_COMPLETION_FLAG; | |
633 | PDBG("%s force completion at i %d\n", __FUNCTION__, i); | |
634 | } | |
635 | ||
636 | /* build the utx mem command */ | |
637 | wqe += (sizeof(struct t3_bypass_wr) >> 3); | |
638 | utx_cmd = (T3_UTX_MEM_WRITE << 28) | (addr + i * 3); | |
639 | utx_cmd <<= 32; | |
640 | utx_cmd |= (utx_len << 28) | ((utx_len << 2) + 1); | |
641 | *wqe = cpu_to_be64(utx_cmd); | |
642 | wqe++; | |
643 | copy_data = (u8 *) data + i * 96; | |
644 | copy_len = len > 96 ? 96 : len; | |
645 | ||
646 | /* clear memory content if data is NULL */ | |
647 | if (data) | |
648 | memcpy(wqe, copy_data, copy_len); | |
649 | else | |
650 | memset(wqe, 0, copy_len); | |
651 | if (copy_len % 32) | |
652 | memset(((u8 *) wqe) + copy_len, 0, | |
653 | 32 - (copy_len % 32)); | |
654 | wr_len = ((sizeof(struct t3_bypass_wr)) >> 3) + 1 + | |
655 | (utx_len << 2); | |
656 | wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr % | |
657 | (1 << T3_CTRL_QP_SIZE_LOG2))); | |
658 | ||
659 | /* wptr in the WRID[31:0] */ | |
660 | ((union t3_wrid *)(wqe+1))->id0.low = rdev_p->ctrl_qp.wptr; | |
661 | ||
662 | /* | |
663 | * This must be the last write with a memory barrier | |
664 | * for the genbit | |
665 | */ | |
666 | build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_BP, flag, | |
667 | Q_GENBIT(rdev_p->ctrl_qp.wptr, | |
668 | T3_CTRL_QP_SIZE_LOG2), T3_CTRL_QP_ID, | |
669 | wr_len); | |
670 | if (flag == T3_COMPLETION_FLAG) | |
671 | ring_doorbell(rdev_p->ctrl_qp.doorbell, T3_CTRL_QP_ID); | |
672 | len -= 96; | |
673 | rdev_p->ctrl_qp.wptr++; | |
674 | } | |
675 | return 0; | |
676 | } | |
677 | ||
678 | /* IN: stag key, pdid, perm, zbva, to, len, page_size, pbl, and pbl_size | |
679 | * OUT: stag index, actual pbl_size, pbl_addr allocated. | |
680 | * TBD: shared memory region support | |
681 | */ | |
682 | static int __cxio_tpt_op(struct cxio_rdev *rdev_p, u32 reset_tpt_entry, | |
683 | u32 *stag, u8 stag_state, u32 pdid, | |
684 | enum tpt_mem_type type, enum tpt_mem_perm perm, | |
685 | u32 zbva, u64 to, u32 len, u8 page_size, __be64 *pbl, | |
686 | u32 *pbl_size, u32 *pbl_addr) | |
687 | { | |
688 | int err; | |
689 | struct tpt_entry tpt; | |
690 | u32 stag_idx; | |
691 | u32 wptr; | |
692 | int rereg = (*stag != T3_STAG_UNSET); | |
693 | ||
694 | stag_state = stag_state > 0; | |
695 | stag_idx = (*stag) >> 8; | |
696 | ||
697 | if ((!reset_tpt_entry) && !(*stag != T3_STAG_UNSET)) { | |
698 | stag_idx = cxio_hal_get_stag(rdev_p->rscp); | |
699 | if (!stag_idx) | |
700 | return -ENOMEM; | |
701 | *stag = (stag_idx << 8) | ((*stag) & 0xFF); | |
702 | } | |
703 | PDBG("%s stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n", | |
704 | __FUNCTION__, stag_state, type, pdid, stag_idx); | |
705 | ||
706 | if (reset_tpt_entry) | |
707 | cxio_hal_pblpool_free(rdev_p, *pbl_addr, *pbl_size << 3); | |
708 | else if (!rereg) { | |
709 | *pbl_addr = cxio_hal_pblpool_alloc(rdev_p, *pbl_size << 3); | |
710 | if (!*pbl_addr) { | |
711 | return -ENOMEM; | |
712 | } | |
713 | } | |
714 | ||
715 | mutex_lock(&rdev_p->ctrl_qp.lock); | |
716 | ||
717 | /* write PBL first if any - update pbl only if pbl list exist */ | |
718 | if (pbl) { | |
719 | ||
720 | PDBG("%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n", | |
721 | __FUNCTION__, *pbl_addr, rdev_p->rnic_info.pbl_base, | |
722 | *pbl_size); | |
723 | err = cxio_hal_ctrl_qp_write_mem(rdev_p, | |
724 | (*pbl_addr >> 5), | |
725 | (*pbl_size << 3), pbl, 0); | |
726 | if (err) | |
727 | goto ret; | |
728 | } | |
729 | ||
730 | /* write TPT entry */ | |
731 | if (reset_tpt_entry) | |
732 | memset(&tpt, 0, sizeof(tpt)); | |
733 | else { | |
734 | tpt.valid_stag_pdid = cpu_to_be32(F_TPT_VALID | | |
735 | V_TPT_STAG_KEY((*stag) & M_TPT_STAG_KEY) | | |
736 | V_TPT_STAG_STATE(stag_state) | | |
737 | V_TPT_STAG_TYPE(type) | V_TPT_PDID(pdid)); | |
738 | BUG_ON(page_size >= 28); | |
739 | tpt.flags_pagesize_qpid = cpu_to_be32(V_TPT_PERM(perm) | | |
740 | F_TPT_MW_BIND_ENABLE | | |
741 | V_TPT_ADDR_TYPE((zbva ? TPT_ZBTO : TPT_VATO)) | | |
742 | V_TPT_PAGE_SIZE(page_size)); | |
743 | tpt.rsvd_pbl_addr = reset_tpt_entry ? 0 : | |
744 | cpu_to_be32(V_TPT_PBL_ADDR(PBL_OFF(rdev_p, *pbl_addr)>>3)); | |
745 | tpt.len = cpu_to_be32(len); | |
746 | tpt.va_hi = cpu_to_be32((u32) (to >> 32)); | |
747 | tpt.va_low_or_fbo = cpu_to_be32((u32) (to & 0xFFFFFFFFULL)); | |
748 | tpt.rsvd_bind_cnt_or_pstag = 0; | |
749 | tpt.rsvd_pbl_size = reset_tpt_entry ? 0 : | |
750 | cpu_to_be32(V_TPT_PBL_SIZE((*pbl_size) >> 2)); | |
751 | } | |
752 | err = cxio_hal_ctrl_qp_write_mem(rdev_p, | |
753 | stag_idx + | |
754 | (rdev_p->rnic_info.tpt_base >> 5), | |
755 | sizeof(tpt), &tpt, 1); | |
756 | ||
757 | /* release the stag index to free pool */ | |
758 | if (reset_tpt_entry) | |
759 | cxio_hal_put_stag(rdev_p->rscp, stag_idx); | |
760 | ret: | |
761 | wptr = rdev_p->ctrl_qp.wptr; | |
762 | mutex_unlock(&rdev_p->ctrl_qp.lock); | |
763 | if (!err) | |
764 | if (wait_event_interruptible(rdev_p->ctrl_qp.waitq, | |
765 | SEQ32_GE(rdev_p->ctrl_qp.rptr, | |
766 | wptr))) | |
767 | return -ERESTARTSYS; | |
768 | return err; | |
769 | } | |
770 | ||
b038ced7 SW |
771 | int cxio_register_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid, |
772 | enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len, | |
773 | u8 page_size, __be64 *pbl, u32 *pbl_size, | |
774 | u32 *pbl_addr) | |
775 | { | |
776 | *stag = T3_STAG_UNSET; | |
777 | return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm, | |
778 | zbva, to, len, page_size, pbl, pbl_size, pbl_addr); | |
779 | } | |
780 | ||
781 | int cxio_reregister_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid, | |
782 | enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len, | |
783 | u8 page_size, __be64 *pbl, u32 *pbl_size, | |
784 | u32 *pbl_addr) | |
785 | { | |
786 | return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm, | |
787 | zbva, to, len, page_size, pbl, pbl_size, pbl_addr); | |
788 | } | |
789 | ||
790 | int cxio_dereg_mem(struct cxio_rdev *rdev_p, u32 stag, u32 pbl_size, | |
791 | u32 pbl_addr) | |
792 | { | |
793 | return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0, NULL, | |
794 | &pbl_size, &pbl_addr); | |
795 | } | |
796 | ||
797 | int cxio_allocate_window(struct cxio_rdev *rdev_p, u32 * stag, u32 pdid) | |
798 | { | |
799 | u32 pbl_size = 0; | |
800 | *stag = T3_STAG_UNSET; | |
801 | return __cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_MW, 0, 0, 0ULL, 0, 0, | |
802 | NULL, &pbl_size, NULL); | |
803 | } | |
804 | ||
805 | int cxio_deallocate_window(struct cxio_rdev *rdev_p, u32 stag) | |
806 | { | |
807 | return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0, NULL, | |
808 | NULL, NULL); | |
809 | } | |
810 | ||
811 | int cxio_rdma_init(struct cxio_rdev *rdev_p, struct t3_rdma_init_attr *attr) | |
812 | { | |
813 | struct t3_rdma_init_wr *wqe; | |
814 | struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_ATOMIC); | |
815 | if (!skb) | |
816 | return -ENOMEM; | |
817 | PDBG("%s rdev_p %p\n", __FUNCTION__, rdev_p); | |
818 | wqe = (struct t3_rdma_init_wr *) __skb_put(skb, sizeof(*wqe)); | |
819 | wqe->wrh.op_seop_flags = cpu_to_be32(V_FW_RIWR_OP(T3_WR_INIT)); | |
820 | wqe->wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(attr->tid) | | |
821 | V_FW_RIWR_LEN(sizeof(*wqe) >> 3)); | |
822 | wqe->wrid.id1 = 0; | |
823 | wqe->qpid = cpu_to_be32(attr->qpid); | |
824 | wqe->pdid = cpu_to_be32(attr->pdid); | |
825 | wqe->scqid = cpu_to_be32(attr->scqid); | |
826 | wqe->rcqid = cpu_to_be32(attr->rcqid); | |
827 | wqe->rq_addr = cpu_to_be32(attr->rq_addr - rdev_p->rnic_info.rqt_base); | |
828 | wqe->rq_size = cpu_to_be32(attr->rq_size); | |
829 | wqe->mpaattrs = attr->mpaattrs; | |
830 | wqe->qpcaps = attr->qpcaps; | |
831 | wqe->ulpdu_size = cpu_to_be16(attr->tcp_emss); | |
832 | wqe->flags = cpu_to_be32(attr->flags); | |
833 | wqe->ord = cpu_to_be32(attr->ord); | |
834 | wqe->ird = cpu_to_be32(attr->ird); | |
835 | wqe->qp_dma_addr = cpu_to_be64(attr->qp_dma_addr); | |
836 | wqe->qp_dma_size = cpu_to_be32(attr->qp_dma_size); | |
de3d3530 | 837 | wqe->irs = cpu_to_be32(attr->irs); |
b038ced7 SW |
838 | skb->priority = 0; /* 0=>ToeQ; 1=>CtrlQ */ |
839 | return (cxgb3_ofld_send(rdev_p->t3cdev_p, skb)); | |
840 | } | |
841 | ||
842 | void cxio_register_ev_cb(cxio_hal_ev_callback_func_t ev_cb) | |
843 | { | |
844 | cxio_ev_cb = ev_cb; | |
845 | } | |
846 | ||
847 | void cxio_unregister_ev_cb(cxio_hal_ev_callback_func_t ev_cb) | |
848 | { | |
849 | cxio_ev_cb = NULL; | |
850 | } | |
851 | ||
852 | static int cxio_hal_ev_handler(struct t3cdev *t3cdev_p, struct sk_buff *skb) | |
853 | { | |
854 | static int cnt; | |
855 | struct cxio_rdev *rdev_p = NULL; | |
856 | struct respQ_msg_t *rsp_msg = (struct respQ_msg_t *) skb->data; | |
857 | PDBG("%d: %s cq_id 0x%x cq_ptr 0x%x genbit %0x overflow %0x an %0x" | |
858 | " se %0x notify %0x cqbranch %0x creditth %0x\n", | |
859 | cnt, __FUNCTION__, RSPQ_CQID(rsp_msg), RSPQ_CQPTR(rsp_msg), | |
860 | RSPQ_GENBIT(rsp_msg), RSPQ_OVERFLOW(rsp_msg), RSPQ_AN(rsp_msg), | |
861 | RSPQ_SE(rsp_msg), RSPQ_NOTIFY(rsp_msg), RSPQ_CQBRANCH(rsp_msg), | |
862 | RSPQ_CREDIT_THRESH(rsp_msg)); | |
863 | PDBG("CQE: QPID 0x%0x genbit %0x type 0x%0x status 0x%0x opcode %d " | |
864 | "len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n", | |
865 | CQE_QPID(rsp_msg->cqe), CQE_GENBIT(rsp_msg->cqe), | |
866 | CQE_TYPE(rsp_msg->cqe), CQE_STATUS(rsp_msg->cqe), | |
867 | CQE_OPCODE(rsp_msg->cqe), CQE_LEN(rsp_msg->cqe), | |
868 | CQE_WRID_HI(rsp_msg->cqe), CQE_WRID_LOW(rsp_msg->cqe)); | |
869 | rdev_p = (struct cxio_rdev *)t3cdev_p->ulp; | |
870 | if (!rdev_p) { | |
871 | PDBG("%s called by t3cdev %p with null ulp\n", __FUNCTION__, | |
872 | t3cdev_p); | |
873 | return 0; | |
874 | } | |
875 | if (CQE_QPID(rsp_msg->cqe) == T3_CTRL_QP_ID) { | |
876 | rdev_p->ctrl_qp.rptr = CQE_WRID_LOW(rsp_msg->cqe) + 1; | |
877 | wake_up_interruptible(&rdev_p->ctrl_qp.waitq); | |
878 | dev_kfree_skb_irq(skb); | |
879 | } else if (CQE_QPID(rsp_msg->cqe) == 0xfff8) | |
880 | dev_kfree_skb_irq(skb); | |
881 | else if (cxio_ev_cb) | |
882 | (*cxio_ev_cb) (rdev_p, skb); | |
883 | else | |
884 | dev_kfree_skb_irq(skb); | |
885 | cnt++; | |
886 | return 0; | |
887 | } | |
888 | ||
889 | /* Caller takes care of locking if needed */ | |
890 | int cxio_rdev_open(struct cxio_rdev *rdev_p) | |
891 | { | |
892 | struct net_device *netdev_p = NULL; | |
893 | int err = 0; | |
894 | if (strlen(rdev_p->dev_name)) { | |
895 | if (cxio_hal_find_rdev_by_name(rdev_p->dev_name)) { | |
896 | return -EBUSY; | |
897 | } | |
881d966b | 898 | netdev_p = dev_get_by_name(&init_net, rdev_p->dev_name); |
b038ced7 SW |
899 | if (!netdev_p) { |
900 | return -EINVAL; | |
901 | } | |
902 | dev_put(netdev_p); | |
903 | } else if (rdev_p->t3cdev_p) { | |
904 | if (cxio_hal_find_rdev_by_t3cdev(rdev_p->t3cdev_p)) { | |
905 | return -EBUSY; | |
906 | } | |
907 | netdev_p = rdev_p->t3cdev_p->lldev; | |
908 | strncpy(rdev_p->dev_name, rdev_p->t3cdev_p->name, | |
909 | T3_MAX_DEV_NAME_LEN); | |
910 | } else { | |
911 | PDBG("%s t3cdev_p or dev_name must be set\n", __FUNCTION__); | |
912 | return -EINVAL; | |
913 | } | |
914 | ||
915 | list_add_tail(&rdev_p->entry, &rdev_list); | |
916 | ||
917 | PDBG("%s opening rnic dev %s\n", __FUNCTION__, rdev_p->dev_name); | |
918 | memset(&rdev_p->ctrl_qp, 0, sizeof(rdev_p->ctrl_qp)); | |
919 | if (!rdev_p->t3cdev_p) | |
5fbf816f | 920 | rdev_p->t3cdev_p = dev2t3cdev(netdev_p); |
b038ced7 SW |
921 | rdev_p->t3cdev_p->ulp = (void *) rdev_p; |
922 | err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_GET_PARAMS, | |
923 | &(rdev_p->rnic_info)); | |
924 | if (err) { | |
925 | printk(KERN_ERR "%s t3cdev_p(%p)->ctl returned error %d.\n", | |
926 | __FUNCTION__, rdev_p->t3cdev_p, err); | |
927 | goto err1; | |
928 | } | |
929 | err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, GET_PORTS, | |
930 | &(rdev_p->port_info)); | |
931 | if (err) { | |
932 | printk(KERN_ERR "%s t3cdev_p(%p)->ctl returned error %d.\n", | |
933 | __FUNCTION__, rdev_p->t3cdev_p, err); | |
934 | goto err1; | |
935 | } | |
936 | ||
937 | /* | |
938 | * qpshift is the number of bits to shift the qpid left in order | |
939 | * to get the correct address of the doorbell for that qp. | |
940 | */ | |
941 | cxio_init_ucontext(rdev_p, &rdev_p->uctx); | |
942 | rdev_p->qpshift = PAGE_SHIFT - | |
943 | ilog2(65536 >> | |
944 | ilog2(rdev_p->rnic_info.udbell_len >> | |
945 | PAGE_SHIFT)); | |
946 | rdev_p->qpnr = rdev_p->rnic_info.udbell_len >> PAGE_SHIFT; | |
947 | rdev_p->qpmask = (65536 >> ilog2(rdev_p->qpnr)) - 1; | |
948 | PDBG("%s rnic %s info: tpt_base 0x%0x tpt_top 0x%0x num stags %d " | |
949 | "pbl_base 0x%0x pbl_top 0x%0x rqt_base 0x%0x, rqt_top 0x%0x\n", | |
950 | __FUNCTION__, rdev_p->dev_name, rdev_p->rnic_info.tpt_base, | |
951 | rdev_p->rnic_info.tpt_top, cxio_num_stags(rdev_p), | |
952 | rdev_p->rnic_info.pbl_base, | |
953 | rdev_p->rnic_info.pbl_top, rdev_p->rnic_info.rqt_base, | |
954 | rdev_p->rnic_info.rqt_top); | |
955 | PDBG("udbell_len 0x%0x udbell_physbase 0x%lx kdb_addr %p qpshift %lu " | |
956 | "qpnr %d qpmask 0x%x\n", | |
957 | rdev_p->rnic_info.udbell_len, | |
958 | rdev_p->rnic_info.udbell_physbase, rdev_p->rnic_info.kdb_addr, | |
959 | rdev_p->qpshift, rdev_p->qpnr, rdev_p->qpmask); | |
960 | ||
961 | err = cxio_hal_init_ctrl_qp(rdev_p); | |
962 | if (err) { | |
963 | printk(KERN_ERR "%s error %d initializing ctrl_qp.\n", | |
964 | __FUNCTION__, err); | |
965 | goto err1; | |
966 | } | |
967 | err = cxio_hal_init_resource(rdev_p, cxio_num_stags(rdev_p), 0, | |
968 | 0, T3_MAX_NUM_QP, T3_MAX_NUM_CQ, | |
969 | T3_MAX_NUM_PD); | |
970 | if (err) { | |
971 | printk(KERN_ERR "%s error %d initializing hal resources.\n", | |
972 | __FUNCTION__, err); | |
973 | goto err2; | |
974 | } | |
975 | err = cxio_hal_pblpool_create(rdev_p); | |
976 | if (err) { | |
977 | printk(KERN_ERR "%s error %d initializing pbl mem pool.\n", | |
978 | __FUNCTION__, err); | |
979 | goto err3; | |
980 | } | |
981 | err = cxio_hal_rqtpool_create(rdev_p); | |
982 | if (err) { | |
983 | printk(KERN_ERR "%s error %d initializing rqt mem pool.\n", | |
984 | __FUNCTION__, err); | |
985 | goto err4; | |
986 | } | |
987 | return 0; | |
988 | err4: | |
989 | cxio_hal_pblpool_destroy(rdev_p); | |
990 | err3: | |
991 | cxio_hal_destroy_resource(rdev_p->rscp); | |
992 | err2: | |
993 | cxio_hal_destroy_ctrl_qp(rdev_p); | |
994 | err1: | |
995 | list_del(&rdev_p->entry); | |
996 | return err; | |
997 | } | |
998 | ||
999 | void cxio_rdev_close(struct cxio_rdev *rdev_p) | |
1000 | { | |
1001 | if (rdev_p) { | |
1002 | cxio_hal_pblpool_destroy(rdev_p); | |
1003 | cxio_hal_rqtpool_destroy(rdev_p); | |
1004 | list_del(&rdev_p->entry); | |
1005 | rdev_p->t3cdev_p->ulp = NULL; | |
1006 | cxio_hal_destroy_ctrl_qp(rdev_p); | |
1007 | cxio_hal_destroy_resource(rdev_p->rscp); | |
1008 | } | |
1009 | } | |
1010 | ||
1011 | int __init cxio_hal_init(void) | |
1012 | { | |
1013 | if (cxio_hal_init_rhdl_resource(T3_MAX_NUM_RI)) | |
1014 | return -ENOMEM; | |
1015 | t3_register_cpl_handler(CPL_ASYNC_NOTIF, cxio_hal_ev_handler); | |
1016 | return 0; | |
1017 | } | |
1018 | ||
1019 | void __exit cxio_hal_exit(void) | |
1020 | { | |
1021 | struct cxio_rdev *rdev, *tmp; | |
1022 | ||
1023 | t3_register_cpl_handler(CPL_ASYNC_NOTIF, NULL); | |
1024 | list_for_each_entry_safe(rdev, tmp, &rdev_list, entry) | |
1025 | cxio_rdev_close(rdev); | |
1026 | cxio_hal_destroy_rhdl_resource(); | |
1027 | } | |
1028 | ||
2b540355 | 1029 | static void flush_completed_wrs(struct t3_wq *wq, struct t3_cq *cq) |
b038ced7 SW |
1030 | { |
1031 | struct t3_swsq *sqp; | |
1032 | __u32 ptr = wq->sq_rptr; | |
1033 | int count = Q_COUNT(wq->sq_rptr, wq->sq_wptr); | |
1034 | ||
1035 | sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2); | |
1036 | while (count--) | |
1037 | if (!sqp->signaled) { | |
1038 | ptr++; | |
1039 | sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2); | |
1040 | } else if (sqp->complete) { | |
1041 | ||
1042 | /* | |
1043 | * Insert this completed cqe into the swcq. | |
1044 | */ | |
1045 | PDBG("%s moving cqe into swcq sq idx %ld cq idx %ld\n", | |
1046 | __FUNCTION__, Q_PTR2IDX(ptr, wq->sq_size_log2), | |
1047 | Q_PTR2IDX(cq->sw_wptr, cq->size_log2)); | |
1048 | sqp->cqe.header |= htonl(V_CQE_SWCQE(1)); | |
1049 | *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) | |
1050 | = sqp->cqe; | |
1051 | cq->sw_wptr++; | |
1052 | sqp->signaled = 0; | |
1053 | break; | |
1054 | } else | |
1055 | break; | |
1056 | } | |
1057 | ||
2b540355 AB |
1058 | static void create_read_req_cqe(struct t3_wq *wq, struct t3_cqe *hw_cqe, |
1059 | struct t3_cqe *read_cqe) | |
b038ced7 SW |
1060 | { |
1061 | read_cqe->u.scqe.wrid_hi = wq->oldest_read->sq_wptr; | |
1062 | read_cqe->len = wq->oldest_read->read_len; | |
1063 | read_cqe->header = htonl(V_CQE_QPID(CQE_QPID(*hw_cqe)) | | |
1064 | V_CQE_SWCQE(SW_CQE(*hw_cqe)) | | |
1065 | V_CQE_OPCODE(T3_READ_REQ) | | |
1066 | V_CQE_TYPE(1)); | |
1067 | } | |
1068 | ||
1069 | /* | |
1070 | * Return a ptr to the next read wr in the SWSQ or NULL. | |
1071 | */ | |
2b540355 | 1072 | static void advance_oldest_read(struct t3_wq *wq) |
b038ced7 SW |
1073 | { |
1074 | ||
1075 | u32 rptr = wq->oldest_read - wq->sq + 1; | |
1076 | u32 wptr = Q_PTR2IDX(wq->sq_wptr, wq->sq_size_log2); | |
1077 | ||
1078 | while (Q_PTR2IDX(rptr, wq->sq_size_log2) != wptr) { | |
1079 | wq->oldest_read = wq->sq + Q_PTR2IDX(rptr, wq->sq_size_log2); | |
1080 | ||
1081 | if (wq->oldest_read->opcode == T3_READ_REQ) | |
1082 | return; | |
1083 | rptr++; | |
1084 | } | |
1085 | wq->oldest_read = NULL; | |
1086 | } | |
1087 | ||
1088 | /* | |
1089 | * cxio_poll_cq | |
1090 | * | |
1091 | * Caller must: | |
1092 | * check the validity of the first CQE, | |
1093 | * supply the wq assicated with the qpid. | |
1094 | * | |
1095 | * credit: cq credit to return to sge. | |
1096 | * cqe_flushed: 1 iff the CQE is flushed. | |
1097 | * cqe: copy of the polled CQE. | |
1098 | * | |
1099 | * return value: | |
1100 | * 0 CQE returned, | |
1101 | * -1 CQE skipped, try again. | |
1102 | */ | |
1103 | int cxio_poll_cq(struct t3_wq *wq, struct t3_cq *cq, struct t3_cqe *cqe, | |
1104 | u8 *cqe_flushed, u64 *cookie, u32 *credit) | |
1105 | { | |
1106 | int ret = 0; | |
1107 | struct t3_cqe *hw_cqe, read_cqe; | |
1108 | ||
1109 | *cqe_flushed = 0; | |
1110 | *credit = 0; | |
1111 | hw_cqe = cxio_next_cqe(cq); | |
1112 | ||
1113 | PDBG("%s CQE OOO %d qpid 0x%0x genbit %d type %d status 0x%0x" | |
1114 | " opcode 0x%0x len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n", | |
1115 | __FUNCTION__, CQE_OOO(*hw_cqe), CQE_QPID(*hw_cqe), | |
1116 | CQE_GENBIT(*hw_cqe), CQE_TYPE(*hw_cqe), CQE_STATUS(*hw_cqe), | |
1117 | CQE_OPCODE(*hw_cqe), CQE_LEN(*hw_cqe), CQE_WRID_HI(*hw_cqe), | |
1118 | CQE_WRID_LOW(*hw_cqe)); | |
1119 | ||
1120 | /* | |
1121 | * skip cqe's not affiliated with a QP. | |
1122 | */ | |
1123 | if (wq == NULL) { | |
1124 | ret = -1; | |
1125 | goto skip_cqe; | |
1126 | } | |
1127 | ||
1128 | /* | |
1129 | * Gotta tweak READ completions: | |
1130 | * 1) the cqe doesn't contain the sq_wptr from the wr. | |
1131 | * 2) opcode not reflected from the wr. | |
1132 | * 3) read_len not reflected from the wr. | |
1133 | * 4) cq_type is RQ_TYPE not SQ_TYPE. | |
1134 | */ | |
1135 | if (RQ_TYPE(*hw_cqe) && (CQE_OPCODE(*hw_cqe) == T3_READ_RESP)) { | |
1136 | ||
1137 | /* | |
1138 | * Don't write to the HWCQ, so create a new read req CQE | |
1139 | * in local memory. | |
1140 | */ | |
1141 | create_read_req_cqe(wq, hw_cqe, &read_cqe); | |
1142 | hw_cqe = &read_cqe; | |
1143 | advance_oldest_read(wq); | |
1144 | } | |
1145 | ||
1146 | /* | |
1147 | * T3A: Discard TERMINATE CQEs. | |
1148 | */ | |
1149 | if (CQE_OPCODE(*hw_cqe) == T3_TERMINATE) { | |
1150 | ret = -1; | |
1151 | wq->error = 1; | |
1152 | goto skip_cqe; | |
1153 | } | |
1154 | ||
1155 | if (CQE_STATUS(*hw_cqe) || wq->error) { | |
1156 | *cqe_flushed = wq->error; | |
1157 | wq->error = 1; | |
1158 | ||
1159 | /* | |
1160 | * T3A inserts errors into the CQE. We cannot return | |
1161 | * these as work completions. | |
1162 | */ | |
1163 | /* incoming write failures */ | |
1164 | if ((CQE_OPCODE(*hw_cqe) == T3_RDMA_WRITE) | |
1165 | && RQ_TYPE(*hw_cqe)) { | |
1166 | ret = -1; | |
1167 | goto skip_cqe; | |
1168 | } | |
1169 | /* incoming read request failures */ | |
1170 | if ((CQE_OPCODE(*hw_cqe) == T3_READ_RESP) && SQ_TYPE(*hw_cqe)) { | |
1171 | ret = -1; | |
1172 | goto skip_cqe; | |
1173 | } | |
1174 | ||
1175 | /* incoming SEND with no receive posted failures */ | |
1176 | if ((CQE_OPCODE(*hw_cqe) == T3_SEND) && RQ_TYPE(*hw_cqe) && | |
1177 | Q_EMPTY(wq->rq_rptr, wq->rq_wptr)) { | |
1178 | ret = -1; | |
1179 | goto skip_cqe; | |
1180 | } | |
1181 | goto proc_cqe; | |
1182 | } | |
1183 | ||
1184 | /* | |
1185 | * RECV completion. | |
1186 | */ | |
1187 | if (RQ_TYPE(*hw_cqe)) { | |
1188 | ||
1189 | /* | |
1190 | * HW only validates 4 bits of MSN. So we must validate that | |
1191 | * the MSN in the SEND is the next expected MSN. If its not, | |
1192 | * then we complete this with TPT_ERR_MSN and mark the wq in | |
1193 | * error. | |
1194 | */ | |
1195 | if (unlikely((CQE_WRID_MSN(*hw_cqe) != (wq->rq_rptr + 1)))) { | |
1196 | wq->error = 1; | |
1197 | hw_cqe->header |= htonl(V_CQE_STATUS(TPT_ERR_MSN)); | |
1198 | goto proc_cqe; | |
1199 | } | |
1200 | goto proc_cqe; | |
1201 | } | |
1202 | ||
1203 | /* | |
1204 | * If we get here its a send completion. | |
1205 | * | |
1206 | * Handle out of order completion. These get stuffed | |
1207 | * in the SW SQ. Then the SW SQ is walked to move any | |
1208 | * now in-order completions into the SW CQ. This handles | |
1209 | * 2 cases: | |
1210 | * 1) reaping unsignaled WRs when the first subsequent | |
1211 | * signaled WR is completed. | |
1212 | * 2) out of order read completions. | |
1213 | */ | |
1214 | if (!SW_CQE(*hw_cqe) && (CQE_WRID_SQ_WPTR(*hw_cqe) != wq->sq_rptr)) { | |
1215 | struct t3_swsq *sqp; | |
1216 | ||
1217 | PDBG("%s out of order completion going in swsq at idx %ld\n", | |
1218 | __FUNCTION__, | |
1219 | Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe), wq->sq_size_log2)); | |
1220 | sqp = wq->sq + | |
1221 | Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe), wq->sq_size_log2); | |
1222 | sqp->cqe = *hw_cqe; | |
1223 | sqp->complete = 1; | |
1224 | ret = -1; | |
1225 | goto flush_wq; | |
1226 | } | |
1227 | ||
1228 | proc_cqe: | |
1229 | *cqe = *hw_cqe; | |
1230 | ||
1231 | /* | |
1232 | * Reap the associated WR(s) that are freed up with this | |
1233 | * completion. | |
1234 | */ | |
1235 | if (SQ_TYPE(*hw_cqe)) { | |
1236 | wq->sq_rptr = CQE_WRID_SQ_WPTR(*hw_cqe); | |
1237 | PDBG("%s completing sq idx %ld\n", __FUNCTION__, | |
1238 | Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2)); | |
1239 | *cookie = (wq->sq + | |
1240 | Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2))->wr_id; | |
1241 | wq->sq_rptr++; | |
1242 | } else { | |
1243 | PDBG("%s completing rq idx %ld\n", __FUNCTION__, | |
1244 | Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2)); | |
1245 | *cookie = *(wq->rq + Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2)); | |
1246 | wq->rq_rptr++; | |
1247 | } | |
1248 | ||
1249 | flush_wq: | |
1250 | /* | |
1251 | * Flush any completed cqes that are now in-order. | |
1252 | */ | |
1253 | flush_completed_wrs(wq, cq); | |
1254 | ||
1255 | skip_cqe: | |
1256 | if (SW_CQE(*hw_cqe)) { | |
1257 | PDBG("%s cq %p cqid 0x%x skip sw cqe sw_rptr 0x%x\n", | |
1258 | __FUNCTION__, cq, cq->cqid, cq->sw_rptr); | |
1259 | ++cq->sw_rptr; | |
1260 | } else { | |
1261 | PDBG("%s cq %p cqid 0x%x skip hw cqe rptr 0x%x\n", | |
1262 | __FUNCTION__, cq, cq->cqid, cq->rptr); | |
1263 | ++cq->rptr; | |
1264 | ||
1265 | /* | |
1266 | * T3A: compute credits. | |
1267 | */ | |
1268 | if (((cq->rptr - cq->wptr) > (1 << (cq->size_log2 - 1))) | |
1269 | || ((cq->rptr - cq->wptr) >= 128)) { | |
1270 | *credit = cq->rptr - cq->wptr; | |
1271 | cq->wptr = cq->rptr; | |
1272 | } | |
1273 | } | |
1274 | return ret; | |
1275 | } |