[mirror_ubuntu-artful-kernel.git] / drivers / infiniband / hw / cxgb3 / iwch.c

/*
 * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */
#include <linux/module.h>
#include <linux/moduleparam.h>

#include <rdma/ib_verbs.h>

#include "cxgb3_offload.h"
#include "iwch_provider.h"
#include "iwch_user.h"
#include "iwch.h"
#include "iwch_cm.h"

#define DRV_VERSION "1.1"

MODULE_AUTHOR("Boyd Faulkner, Steve Wise");
MODULE_DESCRIPTION("Chelsio T3 RDMA Driver");
MODULE_LICENSE("Dual BSD/GPL");
MODULE_VERSION(DRV_VERSION);

cxgb3_cpl_handler_func t3c_handlers[NUM_CPL_CMDS];

static void open_rnic_dev(struct t3cdev *);
static void close_rnic_dev(struct t3cdev *);
static void iwch_err_handler(struct t3cdev *, u32, u32);

struct cxgb3_client t3c_client = {
	.name = "iw_cxgb3",
	.add = open_rnic_dev,
	.remove = close_rnic_dev,
	.handlers = t3c_handlers,
	.redirect = iwch_ep_redirect,
	.err_handler = iwch_err_handler
};

static LIST_HEAD(dev_list);
static DEFINE_MUTEX(dev_mutex);

static void rnic_init(struct iwch_dev *rnicp)
{
	PDBG("%s iwch_dev %p\n", __func__,  rnicp);
	idr_init(&rnicp->cqidr);
	idr_init(&rnicp->qpidr);
	idr_init(&rnicp->mmidr);
	spin_lock_init(&rnicp->lock);

	rnicp->attr.max_qps = T3_MAX_NUM_QP - 32;
	rnicp->attr.max_wrs = T3_MAX_QP_DEPTH;
	rnicp->attr.max_sge_per_wr = T3_MAX_SGE;
	rnicp->attr.max_sge_per_rdma_write_wr = T3_MAX_SGE;
	rnicp->attr.max_cqs = T3_MAX_NUM_CQ - 1;
	rnicp->attr.max_cqes_per_cq = T3_MAX_CQ_DEPTH;
	rnicp->attr.max_mem_regs = cxio_num_stags(&rnicp->rdev);
	rnicp->attr.max_phys_buf_entries = T3_MAX_PBL_SIZE;
	rnicp->attr.max_pds = T3_MAX_NUM_PD - 1;
	rnicp->attr.mem_pgsizes_bitmask = T3_PAGESIZE_MASK;
	rnicp->attr.max_mr_size = T3_MAX_MR_SIZE;
	rnicp->attr.can_resize_wq = 0;
	rnicp->attr.max_rdma_reads_per_qp = 8;
	rnicp->attr.max_rdma_read_resources =
	    rnicp->attr.max_rdma_reads_per_qp * rnicp->attr.max_qps;
	rnicp->attr.max_rdma_read_qp_depth = 8;	/* IRD */
	rnicp->attr.max_rdma_read_depth =
	    rnicp->attr.max_rdma_read_qp_depth * rnicp->attr.max_qps;
	rnicp->attr.rq_overflow_handled = 0;
	rnicp->attr.can_modify_ird = 0;
	rnicp->attr.can_modify_ord = 0;
	rnicp->attr.max_mem_windows = rnicp->attr.max_mem_regs - 1;
	rnicp->attr.stag0_value = 1;
	rnicp->attr.zbva_support = 1;
	rnicp->attr.local_invalidate_fence = 1;
	rnicp->attr.cq_overflow_detection = 1;
	return;
}

static void open_rnic_dev(struct t3cdev *tdev)
{
	struct iwch_dev *rnicp;
	static int vers_printed;

	PDBG("%s t3cdev %p\n", __func__,  tdev);
	if (!vers_printed++)
		printk(KERN_INFO MOD "Chelsio T3 RDMA Driver - version %s\n",
		       DRV_VERSION);
	rnicp = (struct iwch_dev *)ib_alloc_device(sizeof(*rnicp));
	if (!rnicp) {
		printk(KERN_ERR MOD "Cannot allocate ib device\n");
		return;
	}
	rnicp->rdev.ulp = rnicp;
	rnicp->rdev.t3cdev_p = tdev;

	mutex_lock(&dev_mutex);

	if (cxio_rdev_open(&rnicp->rdev)) {
		mutex_unlock(&dev_mutex);
		printk(KERN_ERR MOD "Unable to open CXIO rdev\n");
		ib_dealloc_device(&rnicp->ibdev);
		return;
	}

	rnic_init(rnicp);

	list_add_tail(&rnicp->entry, &dev_list);
	mutex_unlock(&dev_mutex);

	if (iwch_register_device(rnicp)) {
		printk(KERN_ERR MOD "Unable to register device\n");
		close_rnic_dev(tdev);
	}
	printk(KERN_INFO MOD "Initialized device %s\n",
	       pci_name(rnicp->rdev.rnic_info.pdev));
	return;
}

static void close_rnic_dev(struct t3cdev *tdev)
{
	struct iwch_dev *dev, *tmp;
	PDBG("%s t3cdev %p\n", __func__,  tdev);
	mutex_lock(&dev_mutex);
	list_for_each_entry_safe(dev, tmp, &dev_list, entry) {
		if (dev->rdev.t3cdev_p == tdev) {
			list_del(&dev->entry);
			iwch_unregister_device(dev);
			cxio_rdev_close(&dev->rdev);
			idr_destroy(&dev->cqidr);
			idr_destroy(&dev->qpidr);
			idr_destroy(&dev->mmidr);
			ib_dealloc_device(&dev->ibdev);
			break;
		}
	}
	mutex_unlock(&dev_mutex);
}

static void iwch_err_handler(struct t3cdev *tdev, u32 status, u32 error)
{
	struct cxio_rdev *rdev = tdev->ulp;
	struct iwch_dev *rnicp = rdev_to_iwch_dev(rdev);
	struct ib_event event;

	if (status == OFFLOAD_STATUS_DOWN) {
		rdev->flags = CXIO_ERROR_FATAL;

		event.device = &rnicp->ibdev;
		event.event  = IB_EVENT_DEVICE_FATAL;
		event.element.port_num = 0;
		ib_dispatch_event(&event);
	}

	return;
}

static int __init iwch_init_module(void)
{
	int err;

	err = cxio_hal_init();
	if (err)
		return err;
	err = iwch_cm_init();
	if (err)
		return err;
	cxio_register_ev_cb(iwch_ev_dispatch);
	cxgb3_register_client(&t3c_client);
	return 0;
}

static void __exit iwch_exit_module(void)
{
	cxgb3_unregister_client(&t3c_client);
	cxio_unregister_ev_cb(iwch_ev_dispatch);
	iwch_cm_term();
	cxio_hal_exit();
}

module_init(iwch_init_module);
module_exit(iwch_exit_module);
Commit	Line	Data
b038ced7 SW	1	/*
b038ced7 SW	2	* Copyright (c) 2006 Chelsio, Inc. All rights reserved.
b038ced7 SW	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32	#include <linux/module.h>
	33	#include <linux/moduleparam.h>
	34
	35	#include <rdma/ib_verbs.h>
	36
	37	#include "cxgb3_offload.h"
	38	#include "iwch_provider.h"
	39	#include "iwch_user.h"
	40	#include "iwch.h"
	41	#include "iwch_cm.h"
	42
	43	#define DRV_VERSION "1.1"
	44
	45	MODULE_AUTHOR("Boyd Faulkner, Steve Wise");
	46	MODULE_DESCRIPTION("Chelsio T3 RDMA Driver");
	47	MODULE_LICENSE("Dual BSD/GPL");
	48	MODULE_VERSION(DRV_VERSION);
	49
	50	cxgb3_cpl_handler_func t3c_handlers[NUM_CPL_CMDS];
	51
	52	static void open_rnic_dev(struct t3cdev *);
	53	static void close_rnic_dev(struct t3cdev *);
a73efd0a	54	static void iwch_err_handler(struct t3cdev *, u32, u32);
b038ced7 SW	55
	56	struct cxgb3_client t3c_client = {
	57	.name = "iw_cxgb3",
	58	.add = open_rnic_dev,
	59	.remove = close_rnic_dev,
	60	.handlers = t3c_handlers,
a73efd0a DLR	61	.redirect = iwch_ep_redirect,
a73efd0a DLR	62	.err_handler = iwch_err_handler
b038ced7 SW	63	};
	64
	65	static LIST_HEAD(dev_list);
	66	static DEFINE_MUTEX(dev_mutex);
	67
	68	static void rnic_init(struct iwch_dev *rnicp)
	69	{
33718363	70	PDBG("%s iwch_dev %p\n", __func__, rnicp);
b038ced7 SW	71	idr_init(&rnicp->cqidr);
	72	idr_init(&rnicp->qpidr);
	73	idr_init(&rnicp->mmidr);
	74	spin_lock_init(&rnicp->lock);
	75
b038ced7	76	rnicp->attr.max_qps = T3_MAX_NUM_QP - 32;
97d1cc80	77	rnicp->attr.max_wrs = T3_MAX_QP_DEPTH;
b038ced7 SW	78	rnicp->attr.max_sge_per_wr = T3_MAX_SGE;
	79	rnicp->attr.max_sge_per_rdma_write_wr = T3_MAX_SGE;
	80	rnicp->attr.max_cqs = T3_MAX_NUM_CQ - 1;
97d1cc80	81	rnicp->attr.max_cqes_per_cq = T3_MAX_CQ_DEPTH;
b038ced7 SW	82	rnicp->attr.max_mem_regs = cxio_num_stags(&rnicp->rdev);
	83	rnicp->attr.max_phys_buf_entries = T3_MAX_PBL_SIZE;
	84	rnicp->attr.max_pds = T3_MAX_NUM_PD - 1;
52c8084b	85	rnicp->attr.mem_pgsizes_bitmask = T3_PAGESIZE_MASK;
ccaf10d0	86	rnicp->attr.max_mr_size = T3_MAX_MR_SIZE;
b038ced7 SW	87	rnicp->attr.can_resize_wq = 0;
	88	rnicp->attr.max_rdma_reads_per_qp = 8;
	89	rnicp->attr.max_rdma_read_resources =
	90	rnicp->attr.max_rdma_reads_per_qp * rnicp->attr.max_qps;
	91	rnicp->attr.max_rdma_read_qp_depth = 8; /* IRD */
	92	rnicp->attr.max_rdma_read_depth =
	93	rnicp->attr.max_rdma_read_qp_depth * rnicp->attr.max_qps;
	94	rnicp->attr.rq_overflow_handled = 0;
	95	rnicp->attr.can_modify_ird = 0;
	96	rnicp->attr.can_modify_ord = 0;
	97	rnicp->attr.max_mem_windows = rnicp->attr.max_mem_regs - 1;
	98	rnicp->attr.stag0_value = 1;
	99	rnicp->attr.zbva_support = 1;
	100	rnicp->attr.local_invalidate_fence = 1;
	101	rnicp->attr.cq_overflow_detection = 1;
	102	return;
	103	}
	104
	105	static void open_rnic_dev(struct t3cdev *tdev)
	106	{
	107	struct iwch_dev *rnicp;
	108	static int vers_printed;
	109
33718363	110	PDBG("%s t3cdev %p\n", __func__, tdev);
b038ced7 SW	111	if (!vers_printed++)
	112	printk(KERN_INFO MOD "Chelsio T3 RDMA Driver - version %s\n",
	113	DRV_VERSION);
	114	rnicp = (struct iwch_dev )ib_alloc_device(sizeof(rnicp));
	115	if (!rnicp) {
	116	printk(KERN_ERR MOD "Cannot allocate ib device\n");
	117	return;
	118	}
	119	rnicp->rdev.ulp = rnicp;
	120	rnicp->rdev.t3cdev_p = tdev;
	121
	122	mutex_lock(&dev_mutex);
	123
	124	if (cxio_rdev_open(&rnicp->rdev)) {
	125	mutex_unlock(&dev_mutex);
	126	printk(KERN_ERR MOD "Unable to open CXIO rdev\n");
	127	ib_dealloc_device(&rnicp->ibdev);
	128	return;
	129	}
	130
	131	rnic_init(rnicp);
	132
	133	list_add_tail(&rnicp->entry, &dev_list);
	134	mutex_unlock(&dev_mutex);
	135
	136	if (iwch_register_device(rnicp)) {
	137	printk(KERN_ERR MOD "Unable to register device\n");
	138	close_rnic_dev(tdev);
	139	}
	140	printk(KERN_INFO MOD "Initialized device %s\n",
	141	pci_name(rnicp->rdev.rnic_info.pdev));
	142	return;
	143	}
	144
	145	static void close_rnic_dev(struct t3cdev *tdev)
	146	{
	147	struct iwch_dev dev, tmp;
33718363	148	PDBG("%s t3cdev %p\n", __func__, tdev);
b038ced7 SW	149	mutex_lock(&dev_mutex);
	150	list_for_each_entry_safe(dev, tmp, &dev_list, entry) {
	151	if (dev->rdev.t3cdev_p == tdev) {
	152	list_del(&dev->entry);
	153	iwch_unregister_device(dev);
	154	cxio_rdev_close(&dev->rdev);
	155	idr_destroy(&dev->cqidr);
	156	idr_destroy(&dev->qpidr);
	157	idr_destroy(&dev->mmidr);
	158	ib_dealloc_device(&dev->ibdev);
	159	break;
	160	}
	161	}
	162	mutex_unlock(&dev_mutex);
	163	}
	164
a73efd0a DLR	165	static void iwch_err_handler(struct t3cdev *tdev, u32 status, u32 error)
	166	{
	167	struct cxio_rdev *rdev = tdev->ulp;
04b5d028 SW	168	struct iwch_dev *rnicp = rdev_to_iwch_dev(rdev);
04b5d028 SW	169	struct ib_event event;
a73efd0a	170
04b5d028	171	if (status == OFFLOAD_STATUS_DOWN) {
a73efd0a DLR	172	rdev->flags = CXIO_ERROR_FATAL;
a73efd0a DLR	173
04b5d028 SW	174	event.device = &rnicp->ibdev;
	175	event.event = IB_EVENT_DEVICE_FATAL;
	176	event.element.port_num = 0;
	177	ib_dispatch_event(&event);
	178	}
a73efd0a	179
04b5d028	180	return;
a73efd0a DLR	181	}
a73efd0a DLR	182
b038ced7 SW	183	static int __init iwch_init_module(void)
	184	{
	185	int err;
	186
	187	err = cxio_hal_init();
	188	if (err)
	189	return err;
	190	err = iwch_cm_init();
	191	if (err)
	192	return err;
	193	cxio_register_ev_cb(iwch_ev_dispatch);
	194	cxgb3_register_client(&t3c_client);
	195	return 0;
	196	}
	197
	198	static void __exit iwch_exit_module(void)
	199	{
	200	cxgb3_unregister_client(&t3c_client);
	201	cxio_unregister_ev_cb(iwch_ev_dispatch);
	202	iwch_cm_term();
	203	cxio_hal_exit();
	204	}
	205
	206	module_init(iwch_init_module);
	207	module_exit(iwch_exit_module);