[mirror_ubuntu-artful-kernel.git] / drivers / infiniband / hw / cxgb3 / iwch_provider.h

/*
 * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */
#ifndef __IWCH_PROVIDER_H__
#define __IWCH_PROVIDER_H__

#include <linux/list.h>
#include <linux/spinlock.h>
#include <rdma/ib_verbs.h>
#include <asm/types.h>
#include "t3cdev.h"
#include "iwch.h"
#include "cxio_wr.h"
#include "cxio_hal.h"

struct iwch_pd {
	struct ib_pd ibpd;
	u32 pdid;
	struct iwch_dev *rhp;
};

static inline struct iwch_pd *to_iwch_pd(struct ib_pd *ibpd)
{
	return container_of(ibpd, struct iwch_pd, ibpd);
}

struct tpt_attributes {
	u32 stag;
	u32 state:1;
	u32 type:2;
	u32 rsvd:1;
	enum tpt_mem_perm perms;
	u32 remote_invaliate_disable:1;
	u32 zbva:1;
	u32 mw_bind_enable:1;
	u32 page_size:5;

	u32 pdid;
	u32 qpid;
	u32 pbl_addr;
	u32 len;
	u64 va_fbo;
	u32 pbl_size;
};

struct iwch_mr {
	struct ib_mr ibmr;
	struct ib_umem *umem;
	struct iwch_dev *rhp;
	u64 kva;
	struct tpt_attributes attr;
};

typedef struct iwch_mw iwch_mw_handle;

static inline struct iwch_mr *to_iwch_mr(struct ib_mr *ibmr)
{
	return container_of(ibmr, struct iwch_mr, ibmr);
}

struct iwch_mw {
	struct ib_mw ibmw;
	struct iwch_dev *rhp;
	u64 kva;
	struct tpt_attributes attr;
};

static inline struct iwch_mw *to_iwch_mw(struct ib_mw *ibmw)
{
	return container_of(ibmw, struct iwch_mw, ibmw);
}

struct iwch_cq {
	struct ib_cq ibcq;
	struct iwch_dev *rhp;
	struct t3_cq cq;
	spinlock_t lock;
	spinlock_t comp_handler_lock;
	atomic_t refcnt;
	wait_queue_head_t wait;
	u32 __user *user_rptr_addr;
};

static inline struct iwch_cq *to_iwch_cq(struct ib_cq *ibcq)
{
	return container_of(ibcq, struct iwch_cq, ibcq);
}

enum IWCH_QP_FLAGS {
	QP_QUIESCED = 0x01
};

struct iwch_mpa_attributes {
	u8 initiator;
	u8 recv_marker_enabled;
	u8 xmit_marker_enabled;	/* iWARP: enable inbound Read Resp. */
	u8 crc_enabled;
	u8 version;	/* 0 or 1 */
};

struct iwch_qp_attributes {
	u32 scq;
	u32 rcq;
	u32 sq_num_entries;
	u32 rq_num_entries;
	u32 sq_max_sges;
	u32 sq_max_sges_rdma_write;
	u32 rq_max_sges;
	u32 state;
	u8 enable_rdma_read;
	u8 enable_rdma_write;	/* enable inbound Read Resp. */
	u8 enable_bind;
	u8 enable_mmid0_fastreg;	/* Enable STAG0 + Fast-register */
	/*
	 * Next QP state. If specify the current state, only the
	 * QP attributes will be modified.
	 */
	u32 max_ord;
	u32 max_ird;
	u32 pd;	/* IN */
	u32 next_state;
	char terminate_buffer[52];
	u32 terminate_msg_len;
	u8 is_terminate_local;
	struct iwch_mpa_attributes mpa_attr;	/* IN-OUT */
	struct iwch_ep *llp_stream_handle;
	char *stream_msg_buf;	/* Last stream msg. before Idle -> RTS */
	u32 stream_msg_buf_len;	/* Only on Idle -> RTS */
};

struct iwch_qp {
	struct ib_qp ibqp;
	struct iwch_dev *rhp;
	struct iwch_ep *ep;
	struct iwch_qp_attributes attr;
	struct t3_wq wq;
	spinlock_t lock;
	atomic_t refcnt;
	wait_queue_head_t wait;
	enum IWCH_QP_FLAGS flags;
	struct timer_list timer;
};

static inline int qp_quiesced(struct iwch_qp *qhp)
{
	return qhp->flags & QP_QUIESCED;
}

static inline struct iwch_qp *to_iwch_qp(struct ib_qp *ibqp)
{
	return container_of(ibqp, struct iwch_qp, ibqp);
}

void iwch_qp_add_ref(struct ib_qp *qp);
void iwch_qp_rem_ref(struct ib_qp *qp);

struct iwch_ucontext {
	struct ib_ucontext ibucontext;
	struct cxio_ucontext uctx;
	u32 key;
	spinlock_t mmap_lock;
	struct list_head mmaps;
};

static inline struct iwch_ucontext *to_iwch_ucontext(struct ib_ucontext *c)
{
	return container_of(c, struct iwch_ucontext, ibucontext);
}

struct iwch_mm_entry {
	struct list_head entry;
	u64 addr;
	u32 key;
	unsigned len;
};

static inline struct iwch_mm_entry *remove_mmap(struct iwch_ucontext *ucontext,
						u32 key, unsigned len)
{
	struct list_head *pos, *nxt;
	struct iwch_mm_entry *mm;

	spin_lock(&ucontext->mmap_lock);
	list_for_each_safe(pos, nxt, &ucontext->mmaps) {

		mm = list_entry(pos, struct iwch_mm_entry, entry);
		if (mm->key == key && mm->len == len) {
			list_del_init(&mm->entry);
			spin_unlock(&ucontext->mmap_lock);
			PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
			     key, (unsigned long long) mm->addr, mm->len);
			return mm;
		}
	}
	spin_unlock(&ucontext->mmap_lock);
	return NULL;
}

static inline void insert_mmap(struct iwch_ucontext *ucontext,
			       struct iwch_mm_entry *mm)
{
	spin_lock(&ucontext->mmap_lock);
	PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
	     mm->key, (unsigned long long) mm->addr, mm->len);
	list_add_tail(&mm->entry, &ucontext->mmaps);
	spin_unlock(&ucontext->mmap_lock);
}

enum iwch_qp_attr_mask {
	IWCH_QP_ATTR_NEXT_STATE = 1 << 0,
	IWCH_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
	IWCH_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
	IWCH_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
	IWCH_QP_ATTR_MAX_ORD = 1 << 11,
	IWCH_QP_ATTR_MAX_IRD = 1 << 12,
	IWCH_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
	IWCH_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
	IWCH_QP_ATTR_MPA_ATTR = 1 << 24,
	IWCH_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
	IWCH_QP_ATTR_VALID_MODIFY = (IWCH_QP_ATTR_ENABLE_RDMA_READ |
				     IWCH_QP_ATTR_ENABLE_RDMA_WRITE |
				     IWCH_QP_ATTR_MAX_ORD |
				     IWCH_QP_ATTR_MAX_IRD |
				     IWCH_QP_ATTR_LLP_STREAM_HANDLE |
				     IWCH_QP_ATTR_STREAM_MSG_BUFFER |
				     IWCH_QP_ATTR_MPA_ATTR |
				     IWCH_QP_ATTR_QP_CONTEXT_ACTIVATE)
};

int iwch_modify_qp(struct iwch_dev *rhp,
				struct iwch_qp *qhp,
				enum iwch_qp_attr_mask mask,
				struct iwch_qp_attributes *attrs,
				int internal);

enum iwch_qp_state {
	IWCH_QP_STATE_IDLE,
	IWCH_QP_STATE_RTS,
	IWCH_QP_STATE_ERROR,
	IWCH_QP_STATE_TERMINATE,
	IWCH_QP_STATE_CLOSING,
	IWCH_QP_STATE_TOT
};

static inline int iwch_convert_state(enum ib_qp_state ib_state)
{
	switch (ib_state) {
	case IB_QPS_RESET:
	case IB_QPS_INIT:
		return IWCH_QP_STATE_IDLE;
	case IB_QPS_RTS:
		return IWCH_QP_STATE_RTS;
	case IB_QPS_SQD:
		return IWCH_QP_STATE_CLOSING;
	case IB_QPS_SQE:
		return IWCH_QP_STATE_TERMINATE;
	case IB_QPS_ERR:
		return IWCH_QP_STATE_ERROR;
	default:
		return -1;
	}
}

static inline u32 iwch_ib_to_tpt_access(int acc)
{
	return (acc & IB_ACCESS_REMOTE_WRITE ? TPT_REMOTE_WRITE : 0) |
	       (acc & IB_ACCESS_REMOTE_READ ? TPT_REMOTE_READ : 0) |
	       (acc & IB_ACCESS_LOCAL_WRITE ? TPT_LOCAL_WRITE : 0) |
	       (acc & IB_ACCESS_MW_BIND ? TPT_MW_BIND : 0) |
	       TPT_LOCAL_READ;
}

static inline u32 iwch_ib_to_tpt_bind_access(int acc)
{
	return (acc & IB_ACCESS_REMOTE_WRITE ? TPT_REMOTE_WRITE : 0) |
	       (acc & IB_ACCESS_REMOTE_READ ? TPT_REMOTE_READ : 0);
}

enum iwch_mmid_state {
	IWCH_STAG_STATE_VALID,
	IWCH_STAG_STATE_INVALID
};

enum iwch_qp_query_flags {
	IWCH_QP_QUERY_CONTEXT_NONE = 0x0,	/* No ctx; Only attrs */
	IWCH_QP_QUERY_CONTEXT_GET = 0x1,	/* Get ctx + attrs */
	IWCH_QP_QUERY_CONTEXT_SUSPEND = 0x2,	/* Not Supported */

	/*
	 * Quiesce QP context; Consumer
	 * will NOT replay outstanding WR
	 */
	IWCH_QP_QUERY_CONTEXT_QUIESCE = 0x4,
	IWCH_QP_QUERY_CONTEXT_REMOVE = 0x8,
	IWCH_QP_QUERY_TEST_USERWRITE = 0x32	/* Test special */
};

u16 iwch_rqes_posted(struct iwch_qp *qhp);
int iwch_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
		      struct ib_send_wr **bad_wr);
int iwch_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
		      struct ib_recv_wr **bad_wr);
int iwch_bind_mw(struct ib_qp *qp,
			     struct ib_mw *mw,
			     struct ib_mw_bind *mw_bind);
int iwch_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
int iwch_post_terminate(struct iwch_qp *qhp, struct respQ_msg_t *rsp_msg);
int iwch_post_zb_read(struct iwch_ep *ep);
int iwch_register_device(struct iwch_dev *dev);
void iwch_unregister_device(struct iwch_dev *dev);
void stop_read_rep_timer(struct iwch_qp *qhp);
int iwch_register_mem(struct iwch_dev *rhp, struct iwch_pd *php,
		      struct iwch_mr *mhp, int shift);
int iwch_reregister_mem(struct iwch_dev *rhp, struct iwch_pd *php,
					struct iwch_mr *mhp,
					int shift,
					int npages);
int iwch_alloc_pbl(struct iwch_mr *mhp, int npages);
void iwch_free_pbl(struct iwch_mr *mhp);
int iwch_write_pbl(struct iwch_mr *mhp, __be64 *pages, int npages, int offset);
int build_phys_page_list(struct ib_phys_buf *buffer_list,
					int num_phys_buf,
					u64 *iova_start,
					u64 *total_size,
					int *npages,
					int *shift,
					__be64 **page_list);


#define IWCH_NODE_DESC "cxgb3 Chelsio Communications"

#endif
Commit	Line	Data
b038ced7 SW	1	/*
b038ced7 SW	2	* Copyright (c) 2006 Chelsio, Inc. All rights reserved.
b038ced7 SW	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32	#ifndef __IWCH_PROVIDER_H__
	33	#define __IWCH_PROVIDER_H__
	34
	35	#include <linux/list.h>
	36	#include <linux/spinlock.h>
	37	#include <rdma/ib_verbs.h>
	38	#include <asm/types.h>
	39	#include "t3cdev.h"
	40	#include "iwch.h"
	41	#include "cxio_wr.h"
	42	#include "cxio_hal.h"
	43
	44	struct iwch_pd {
	45	struct ib_pd ibpd;
	46	u32 pdid;
	47	struct iwch_dev *rhp;
	48	};
	49
	50	static inline struct iwch_pd to_iwch_pd(struct ib_pd ibpd)
	51	{
	52	return container_of(ibpd, struct iwch_pd, ibpd);
	53	}
	54
	55	struct tpt_attributes {
	56	u32 stag;
	57	u32 state:1;
	58	u32 type:2;
	59	u32 rsvd:1;
	60	enum tpt_mem_perm perms;
	61	u32 remote_invaliate_disable:1;
	62	u32 zbva:1;
	63	u32 mw_bind_enable:1;
	64	u32 page_size:5;
	65
	66	u32 pdid;
67	u32 qpid;
68	u32 pbl_addr;
69	u32 len;
70	u64 va_fbo;
71	u32 pbl_size;
72	};
73
74	struct iwch_mr {
75	struct ib_mr ibmr;
f7c6a7b5	76	struct ib_umem *umem;
b038ced7 SW	77	struct iwch_dev *rhp;
	78	u64 kva;
	79	struct tpt_attributes attr;
	80	};
	81
	82	typedef struct iwch_mw iwch_mw_handle;
	83
	84	static inline struct iwch_mr to_iwch_mr(struct ib_mr ibmr)
	85	{
	86	return container_of(ibmr, struct iwch_mr, ibmr);
	87	}
	88
	89	struct iwch_mw {
	90	struct ib_mw ibmw;
	91	struct iwch_dev *rhp;
	92	u64 kva;
	93	struct tpt_attributes attr;
	94	};
	95
	96	static inline struct iwch_mw to_iwch_mw(struct ib_mw ibmw)
	97	{
	98	return container_of(ibmw, struct iwch_mw, ibmw);
	99	}
	100
	101	struct iwch_cq {
	102	struct ib_cq ibcq;
	103	struct iwch_dev *rhp;
	104	struct t3_cq cq;
	105	spinlock_t lock;
f7cc25d0	106	spinlock_t comp_handler_lock;
b038ced7 SW	107	atomic_t refcnt;
	108	wait_queue_head_t wait;
	109	u32 __user *user_rptr_addr;
	110	};
	111
	112	static inline struct iwch_cq to_iwch_cq(struct ib_cq ibcq)
	113	{
	114	return container_of(ibcq, struct iwch_cq, ibcq);
	115	}
	116
	117	enum IWCH_QP_FLAGS {
	118	QP_QUIESCED = 0x01
	119	};
	120
	121	struct iwch_mpa_attributes {
f8b0dfd1	122	u8 initiator;
b038ced7 SW	123	u8 recv_marker_enabled;
	124	u8 xmit_marker_enabled; /* iWARP: enable inbound Read Resp. */
	125	u8 crc_enabled;
	126	u8 version; /* 0 or 1 */
	127	};
	128
	129	struct iwch_qp_attributes {
	130	u32 scq;
	131	u32 rcq;
	132	u32 sq_num_entries;
	133	u32 rq_num_entries;
	134	u32 sq_max_sges;
	135	u32 sq_max_sges_rdma_write;
	136	u32 rq_max_sges;
	137	u32 state;
	138	u8 enable_rdma_read;
	139	u8 enable_rdma_write; /* enable inbound Read Resp. */
	140	u8 enable_bind;
	141	u8 enable_mmid0_fastreg; /* Enable STAG0 + Fast-register */
	142	/*
	143	* Next QP state. If specify the current state, only the
	144	* QP attributes will be modified.
	145	*/
	146	u32 max_ord;
	147	u32 max_ird;
	148	u32 pd; /* IN */
	149	u32 next_state;
	150	char terminate_buffer[52];
	151	u32 terminate_msg_len;
	152	u8 is_terminate_local;
	153	struct iwch_mpa_attributes mpa_attr; /* IN-OUT */
	154	struct iwch_ep *llp_stream_handle;
	155	char stream_msg_buf; / Last stream msg. before Idle -> RTS */
	156	u32 stream_msg_buf_len; /* Only on Idle -> RTS */
	157	};
	158
	159	struct iwch_qp {
	160	struct ib_qp ibqp;
	161	struct iwch_dev *rhp;
	162	struct iwch_ep *ep;
	163	struct iwch_qp_attributes attr;
	164	struct t3_wq wq;
	165	spinlock_t lock;
	166	atomic_t refcnt;
	167	wait_queue_head_t wait;
	168	enum IWCH_QP_FLAGS flags;
	169	struct timer_list timer;
	170	};
	171
	172	static inline int qp_quiesced(struct iwch_qp *qhp)
	173	{
	174	return qhp->flags & QP_QUIESCED;
	175	}
	176
	177	static inline struct iwch_qp to_iwch_qp(struct ib_qp ibqp)
	178	{
	179	return container_of(ibqp, struct iwch_qp, ibqp);
	180	}
	181
	182	void iwch_qp_add_ref(struct ib_qp *qp);
	183	void iwch_qp_rem_ref(struct ib_qp *qp);
b038ced7 SW	184
	185	struct iwch_ucontext {
	186	struct ib_ucontext ibucontext;
	187	struct cxio_ucontext uctx;
	188	u32 key;
	189	spinlock_t mmap_lock;
	190	struct list_head mmaps;
	191	};
	192
	193	static inline struct iwch_ucontext to_iwch_ucontext(struct ib_ucontext c)
	194	{
	195	return container_of(c, struct iwch_ucontext, ibucontext);
	196	}
	197
	198	struct iwch_mm_entry {
	199	struct list_head entry;
	200	u64 addr;
	201	u32 key;
	202	unsigned len;
	203	};
	204
	205	static inline struct iwch_mm_entry remove_mmap(struct iwch_ucontext ucontext,
	206	u32 key, unsigned len)
	207	{
	208	struct list_head pos, nxt;
	209	struct iwch_mm_entry *mm;
	210
	211	spin_lock(&ucontext->mmap_lock);
	212	list_for_each_safe(pos, nxt, &ucontext->mmaps) {
	213
	214	mm = list_entry(pos, struct iwch_mm_entry, entry);
	215	if (mm->key == key && mm->len == len) {
	216	list_del_init(&mm->entry);
	217	spin_unlock(&ucontext->mmap_lock);
33718363	218	PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
b038ced7 SW	219	key, (unsigned long long) mm->addr, mm->len);
	220	return mm;
	221	}
	222	}
	223	spin_unlock(&ucontext->mmap_lock);
	224	return NULL;
	225	}
	226
	227	static inline void insert_mmap(struct iwch_ucontext *ucontext,
	228	struct iwch_mm_entry *mm)
	229	{
	230	spin_lock(&ucontext->mmap_lock);
33718363	231	PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
b038ced7 SW	232	mm->key, (unsigned long long) mm->addr, mm->len);
	233	list_add_tail(&mm->entry, &ucontext->mmaps);
	234	spin_unlock(&ucontext->mmap_lock);
	235	}
	236
	237	enum iwch_qp_attr_mask {
	238	IWCH_QP_ATTR_NEXT_STATE = 1 << 0,
	239	IWCH_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
	240	IWCH_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
	241	IWCH_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
	242	IWCH_QP_ATTR_MAX_ORD = 1 << 11,
	243	IWCH_QP_ATTR_MAX_IRD = 1 << 12,
	244	IWCH_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
	245	IWCH_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
	246	IWCH_QP_ATTR_MPA_ATTR = 1 << 24,
	247	IWCH_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
	248	IWCH_QP_ATTR_VALID_MODIFY = (IWCH_QP_ATTR_ENABLE_RDMA_READ \|
	249	IWCH_QP_ATTR_ENABLE_RDMA_WRITE \|
	250	IWCH_QP_ATTR_MAX_ORD \|
	251	IWCH_QP_ATTR_MAX_IRD \|
	252	IWCH_QP_ATTR_LLP_STREAM_HANDLE \|
	253	IWCH_QP_ATTR_STREAM_MSG_BUFFER \|
	254	IWCH_QP_ATTR_MPA_ATTR \|
	255	IWCH_QP_ATTR_QP_CONTEXT_ACTIVATE)
	256	};
	257
	258	int iwch_modify_qp(struct iwch_dev *rhp,
	259	struct iwch_qp *qhp,
	260	enum iwch_qp_attr_mask mask,
	261	struct iwch_qp_attributes *attrs,
	262	int internal);
	263
	264	enum iwch_qp_state {
	265	IWCH_QP_STATE_IDLE,
	266	IWCH_QP_STATE_RTS,
	267	IWCH_QP_STATE_ERROR,
	268	IWCH_QP_STATE_TERMINATE,
	269	IWCH_QP_STATE_CLOSING,
	270	IWCH_QP_STATE_TOT
	271	};
	272
	273	static inline int iwch_convert_state(enum ib_qp_state ib_state)
	274	{
	275	switch (ib_state) {
	276	case IB_QPS_RESET:
	277	case IB_QPS_INIT:
	278	return IWCH_QP_STATE_IDLE;
	279	case IB_QPS_RTS:
	280	return IWCH_QP_STATE_RTS;
	281	case IB_QPS_SQD:
	282	return IWCH_QP_STATE_CLOSING;
	283	case IB_QPS_SQE:
	284	return IWCH_QP_STATE_TERMINATE;
	285	case IB_QPS_ERR:
	286	return IWCH_QP_STATE_ERROR;
	287	default:
	288	return -1;
	289	}
	290	}
	291
e64518f3	292	static inline u32 iwch_ib_to_tpt_access(int acc)
b038ced7	293	{
e64518f3 SW	294	return (acc & IB_ACCESS_REMOTE_WRITE ? TPT_REMOTE_WRITE : 0) \|
	295	(acc & IB_ACCESS_REMOTE_READ ? TPT_REMOTE_READ : 0) \|
	296	(acc & IB_ACCESS_LOCAL_WRITE ? TPT_LOCAL_WRITE : 0) \|
1c355a6e	297	(acc & IB_ACCESS_MW_BIND ? TPT_MW_BIND : 0) \|
e64518f3 SW	298	TPT_LOCAL_READ;
	299	}
	300
1c355a6e SW	301	static inline u32 iwch_ib_to_tpt_bind_access(int acc)
	302	{
	303	return (acc & IB_ACCESS_REMOTE_WRITE ? TPT_REMOTE_WRITE : 0) \|
	304	(acc & IB_ACCESS_REMOTE_READ ? TPT_REMOTE_READ : 0);
	305	}
	306
b038ced7 SW	307	enum iwch_mmid_state {
	308	IWCH_STAG_STATE_VALID,
	309	IWCH_STAG_STATE_INVALID
	310	};
	311
	312	enum iwch_qp_query_flags {
	313	IWCH_QP_QUERY_CONTEXT_NONE = 0x0, /* No ctx; Only attrs */
	314	IWCH_QP_QUERY_CONTEXT_GET = 0x1, /* Get ctx + attrs */
	315	IWCH_QP_QUERY_CONTEXT_SUSPEND = 0x2, /* Not Supported */
	316
	317	/*
	318	* Quiesce QP context; Consumer
	319	* will NOT replay outstanding WR
	320	*/
	321	IWCH_QP_QUERY_CONTEXT_QUIESCE = 0x4,
	322	IWCH_QP_QUERY_CONTEXT_REMOVE = 0x8,
	323	IWCH_QP_QUERY_TEST_USERWRITE = 0x32 /* Test special */
	324	};
	325
f8b0dfd1	326	u16 iwch_rqes_posted(struct iwch_qp *qhp);
b038ced7 SW	327	int iwch_post_send(struct ib_qp ibqp, struct ib_send_wr wr,
	328	struct ib_send_wr **bad_wr);
	329	int iwch_post_receive(struct ib_qp ibqp, struct ib_recv_wr wr,
	330	struct ib_recv_wr **bad_wr);
	331	int iwch_bind_mw(struct ib_qp *qp,
	332	struct ib_mw *mw,
	333	struct ib_mw_bind *mw_bind);
	334	int iwch_poll_cq(struct ib_cq ibcq, int num_entries, struct ib_wc wc);
	335	int iwch_post_terminate(struct iwch_qp qhp, struct respQ_msg_t rsp_msg);
80783868	336	int iwch_post_zb_read(struct iwch_ep *ep);
b038ced7 SW	337	int iwch_register_device(struct iwch_dev *dev);
b038ced7 SW	338	void iwch_unregister_device(struct iwch_dev *dev);
b038ced7 SW	339	void stop_read_rep_timer(struct iwch_qp *qhp);
b038ced7 SW	340	int iwch_register_mem(struct iwch_dev rhp, struct iwch_pd php,
273748cc	341	struct iwch_mr *mhp, int shift);
b038ced7 SW	342	int iwch_reregister_mem(struct iwch_dev rhp, struct iwch_pd php,
	343	struct iwch_mr *mhp,
	344	int shift,
b038ced7	345	int npages);
273748cc RD	346	int iwch_alloc_pbl(struct iwch_mr *mhp, int npages);
	347	void iwch_free_pbl(struct iwch_mr *mhp);
	348	int iwch_write_pbl(struct iwch_mr mhp, __be64 pages, int npages, int offset);
b038ced7 SW	349	int build_phys_page_list(struct ib_phys_buf *buffer_list,
	350	int num_phys_buf,
	351	u64 *iova_start,
	352	u64 *total_size,
	353	int *npages,
	354	int *shift,
	355	__be64 **page_list);
	356
	357
	358	#define IWCH_NODE_DESC "cxgb3 Chelsio Communications"
	359
	360	#endif