[mirror_ubuntu-artful-kernel.git] / drivers / infiniband / hw / cxgb3 / iwch_provider.h

/*
 * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */
#ifndef __IWCH_PROVIDER_H__
#define __IWCH_PROVIDER_H__

#include <linux/list.h>
#include <linux/spinlock.h>
#include <rdma/ib_verbs.h>
#include <asm/types.h>
#include "t3cdev.h"
#include "iwch.h"
#include "cxio_wr.h"
#include "cxio_hal.h"

struct iwch_pd {
	struct ib_pd ibpd;
	u32 pdid;
	struct iwch_dev *rhp;
};

static inline struct iwch_pd *to_iwch_pd(struct ib_pd *ibpd)
{
	return container_of(ibpd, struct iwch_pd, ibpd);
}

struct tpt_attributes {
	u32 stag;
	u32 state:1;
	u32 type:2;
	u32 rsvd:1;
	enum tpt_mem_perm perms;
	u32 remote_invaliate_disable:1;
	u32 zbva:1;
	u32 mw_bind_enable:1;
	u32 page_size:5;

	u32 pdid;
	u32 qpid;
	u32 pbl_addr;
	u32 len;
	u64 va_fbo;
	u32 pbl_size;
};

struct iwch_mr {
	struct ib_mr ibmr;
	struct iwch_dev *rhp;
	u64 kva;
	struct tpt_attributes attr;
};

typedef struct iwch_mw iwch_mw_handle;

static inline struct iwch_mr *to_iwch_mr(struct ib_mr *ibmr)
{
	return container_of(ibmr, struct iwch_mr, ibmr);
}

struct iwch_mw {
	struct ib_mw ibmw;
	struct iwch_dev *rhp;
	u64 kva;
	struct tpt_attributes attr;
};

static inline struct iwch_mw *to_iwch_mw(struct ib_mw *ibmw)
{
	return container_of(ibmw, struct iwch_mw, ibmw);
}

struct iwch_cq {
	struct ib_cq ibcq;
	struct iwch_dev *rhp;
	struct t3_cq cq;
	spinlock_t lock;
	atomic_t refcnt;
	wait_queue_head_t wait;
	u32 __user *user_rptr_addr;
};

static inline struct iwch_cq *to_iwch_cq(struct ib_cq *ibcq)
{
	return container_of(ibcq, struct iwch_cq, ibcq);
}

enum IWCH_QP_FLAGS {
	QP_QUIESCED = 0x01
};

struct iwch_mpa_attributes {
	u8 recv_marker_enabled;
	u8 xmit_marker_enabled;	/* iWARP: enable inbound Read Resp. */
	u8 crc_enabled;
	u8 version;	/* 0 or 1 */
};

struct iwch_qp_attributes {
	u32 scq;
	u32 rcq;
	u32 sq_num_entries;
	u32 rq_num_entries;
	u32 sq_max_sges;
	u32 sq_max_sges_rdma_write;
	u32 rq_max_sges;
	u32 state;
	u8 enable_rdma_read;
	u8 enable_rdma_write;	/* enable inbound Read Resp. */
	u8 enable_bind;
	u8 enable_mmid0_fastreg;	/* Enable STAG0 + Fast-register */
	/*
	 * Next QP state. If specify the current state, only the
	 * QP attributes will be modified.
	 */
	u32 max_ord;
	u32 max_ird;
	u32 pd;	/* IN */
	u32 next_state;
	char terminate_buffer[52];
	u32 terminate_msg_len;
	u8 is_terminate_local;
	struct iwch_mpa_attributes mpa_attr;	/* IN-OUT */
	struct iwch_ep *llp_stream_handle;
	char *stream_msg_buf;	/* Last stream msg. before Idle -> RTS */
	u32 stream_msg_buf_len;	/* Only on Idle -> RTS */
};

struct iwch_qp {
	struct ib_qp ibqp;
	struct iwch_dev *rhp;
	struct iwch_ep *ep;
	struct iwch_qp_attributes attr;
	struct t3_wq wq;
	spinlock_t lock;
	atomic_t refcnt;
	wait_queue_head_t wait;
	enum IWCH_QP_FLAGS flags;
	struct timer_list timer;
};

static inline int qp_quiesced(struct iwch_qp *qhp)
{
	return qhp->flags & QP_QUIESCED;
}

static inline struct iwch_qp *to_iwch_qp(struct ib_qp *ibqp)
{
	return container_of(ibqp, struct iwch_qp, ibqp);
}

void iwch_qp_add_ref(struct ib_qp *qp);
void iwch_qp_rem_ref(struct ib_qp *qp);

struct iwch_ucontext {
	struct ib_ucontext ibucontext;
	struct cxio_ucontext uctx;
	u32 key;
	spinlock_t mmap_lock;
	struct list_head mmaps;
};

static inline struct iwch_ucontext *to_iwch_ucontext(struct ib_ucontext *c)
{
	return container_of(c, struct iwch_ucontext, ibucontext);
}

struct iwch_mm_entry {
	struct list_head entry;
	u64 addr;
	u32 key;
	unsigned len;
};

static inline struct iwch_mm_entry *remove_mmap(struct iwch_ucontext *ucontext,
						u32 key, unsigned len)
{
	struct list_head *pos, *nxt;
	struct iwch_mm_entry *mm;

	spin_lock(&ucontext->mmap_lock);
	list_for_each_safe(pos, nxt, &ucontext->mmaps) {

		mm = list_entry(pos, struct iwch_mm_entry, entry);
		if (mm->key == key && mm->len == len) {
			list_del_init(&mm->entry);
			spin_unlock(&ucontext->mmap_lock);
			PDBG("%s key 0x%x addr 0x%llx len %d\n", __FUNCTION__,
			     key, (unsigned long long) mm->addr, mm->len);
			return mm;
		}
	}
	spin_unlock(&ucontext->mmap_lock);
	return NULL;
}

static inline void insert_mmap(struct iwch_ucontext *ucontext,
			       struct iwch_mm_entry *mm)
{
	spin_lock(&ucontext->mmap_lock);
	PDBG("%s key 0x%x addr 0x%llx len %d\n", __FUNCTION__,
	     mm->key, (unsigned long long) mm->addr, mm->len);
	list_add_tail(&mm->entry, &ucontext->mmaps);
	spin_unlock(&ucontext->mmap_lock);
}

enum iwch_qp_attr_mask {
	IWCH_QP_ATTR_NEXT_STATE = 1 << 0,
	IWCH_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
	IWCH_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
	IWCH_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
	IWCH_QP_ATTR_MAX_ORD = 1 << 11,
	IWCH_QP_ATTR_MAX_IRD = 1 << 12,
	IWCH_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
	IWCH_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
	IWCH_QP_ATTR_MPA_ATTR = 1 << 24,
	IWCH_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
	IWCH_QP_ATTR_VALID_MODIFY = (IWCH_QP_ATTR_ENABLE_RDMA_READ |
				     IWCH_QP_ATTR_ENABLE_RDMA_WRITE |
				     IWCH_QP_ATTR_MAX_ORD |
				     IWCH_QP_ATTR_MAX_IRD |
				     IWCH_QP_ATTR_LLP_STREAM_HANDLE |
				     IWCH_QP_ATTR_STREAM_MSG_BUFFER |
				     IWCH_QP_ATTR_MPA_ATTR |
				     IWCH_QP_ATTR_QP_CONTEXT_ACTIVATE)
};

int iwch_modify_qp(struct iwch_dev *rhp,
				struct iwch_qp *qhp,
				enum iwch_qp_attr_mask mask,
				struct iwch_qp_attributes *attrs,
				int internal);

enum iwch_qp_state {
	IWCH_QP_STATE_IDLE,
	IWCH_QP_STATE_RTS,
	IWCH_QP_STATE_ERROR,
	IWCH_QP_STATE_TERMINATE,
	IWCH_QP_STATE_CLOSING,
	IWCH_QP_STATE_TOT
};

static inline int iwch_convert_state(enum ib_qp_state ib_state)
{
	switch (ib_state) {
	case IB_QPS_RESET:
	case IB_QPS_INIT:
		return IWCH_QP_STATE_IDLE;
	case IB_QPS_RTS:
		return IWCH_QP_STATE_RTS;
	case IB_QPS_SQD:
		return IWCH_QP_STATE_CLOSING;
	case IB_QPS_SQE:
		return IWCH_QP_STATE_TERMINATE;
	case IB_QPS_ERR:
		return IWCH_QP_STATE_ERROR;
	default:
		return -1;
	}
}

static inline u32 iwch_ib_to_tpt_access(int acc)
{
	return (acc & IB_ACCESS_REMOTE_WRITE ? TPT_REMOTE_WRITE : 0) |
	       (acc & IB_ACCESS_REMOTE_READ ? TPT_REMOTE_READ : 0) |
	       (acc & IB_ACCESS_LOCAL_WRITE ? TPT_LOCAL_WRITE : 0) |
	       TPT_LOCAL_READ;
}

static inline u32 iwch_ib_to_mwbind_access(int acc)
{
	return (acc & IB_ACCESS_REMOTE_WRITE ? T3_MEM_ACCESS_REM_WRITE : 0) |
	       (acc & IB_ACCESS_REMOTE_READ ? T3_MEM_ACCESS_REM_READ : 0) |
	       (acc & IB_ACCESS_LOCAL_WRITE ? T3_MEM_ACCESS_LOCAL_WRITE : 0) |
	       T3_MEM_ACCESS_LOCAL_READ;
}

enum iwch_mmid_state {
	IWCH_STAG_STATE_VALID,
	IWCH_STAG_STATE_INVALID
};

enum iwch_qp_query_flags {
	IWCH_QP_QUERY_CONTEXT_NONE = 0x0,	/* No ctx; Only attrs */
	IWCH_QP_QUERY_CONTEXT_GET = 0x1,	/* Get ctx + attrs */
	IWCH_QP_QUERY_CONTEXT_SUSPEND = 0x2,	/* Not Supported */

	/*
	 * Quiesce QP context; Consumer
	 * will NOT replay outstanding WR
	 */
	IWCH_QP_QUERY_CONTEXT_QUIESCE = 0x4,
	IWCH_QP_QUERY_CONTEXT_REMOVE = 0x8,
	IWCH_QP_QUERY_TEST_USERWRITE = 0x32	/* Test special */
};

int iwch_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
		      struct ib_send_wr **bad_wr);
int iwch_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
		      struct ib_recv_wr **bad_wr);
int iwch_bind_mw(struct ib_qp *qp,
			     struct ib_mw *mw,
			     struct ib_mw_bind *mw_bind);
int iwch_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
int iwch_post_terminate(struct iwch_qp *qhp, struct respQ_msg_t *rsp_msg);
int iwch_register_device(struct iwch_dev *dev);
void iwch_unregister_device(struct iwch_dev *dev);
int iwch_quiesce_qps(struct iwch_cq *chp);
int iwch_resume_qps(struct iwch_cq *chp);
void stop_read_rep_timer(struct iwch_qp *qhp);
int iwch_register_mem(struct iwch_dev *rhp, struct iwch_pd *php,
					struct iwch_mr *mhp,
					int shift,
					__be64 *page_list);
int iwch_reregister_mem(struct iwch_dev *rhp, struct iwch_pd *php,
					struct iwch_mr *mhp,
					int shift,
					__be64 *page_list,
					int npages);
int build_phys_page_list(struct ib_phys_buf *buffer_list,
					int num_phys_buf,
					u64 *iova_start,
					u64 *total_size,
					int *npages,
					int *shift,
					__be64 **page_list);


#define IWCH_NODE_DESC "cxgb3 Chelsio Communications"

#endif
Commit	Line	Data
b038ced7 SW	1	/*
b038ced7 SW	2	* Copyright (c) 2006 Chelsio, Inc. All rights reserved.
b038ced7 SW	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32	#ifndef __IWCH_PROVIDER_H__
	33	#define __IWCH_PROVIDER_H__
	34
	35	#include <linux/list.h>
	36	#include <linux/spinlock.h>
	37	#include <rdma/ib_verbs.h>
	38	#include <asm/types.h>
	39	#include "t3cdev.h"
	40	#include "iwch.h"
	41	#include "cxio_wr.h"
	42	#include "cxio_hal.h"
	43
	44	struct iwch_pd {
	45	struct ib_pd ibpd;
	46	u32 pdid;
	47	struct iwch_dev *rhp;
	48	};
	49
	50	static inline struct iwch_pd to_iwch_pd(struct ib_pd ibpd)
	51	{
	52	return container_of(ibpd, struct iwch_pd, ibpd);
	53	}
	54
	55	struct tpt_attributes {
	56	u32 stag;
	57	u32 state:1;
	58	u32 type:2;
	59	u32 rsvd:1;
	60	enum tpt_mem_perm perms;
	61	u32 remote_invaliate_disable:1;
	62	u32 zbva:1;
	63	u32 mw_bind_enable:1;
	64	u32 page_size:5;
	65
	66	u32 pdid;
67	u32 qpid;
68	u32 pbl_addr;
69	u32 len;
70	u64 va_fbo;
71	u32 pbl_size;
72	};
73
74	struct iwch_mr {
75	struct ib_mr ibmr;
76	struct iwch_dev *rhp;
77	u64 kva;
78	struct tpt_attributes attr;
79	};
80
81	typedef struct iwch_mw iwch_mw_handle;
82
83	static inline struct iwch_mr to_iwch_mr(struct ib_mr ibmr)
84	{
85	return container_of(ibmr, struct iwch_mr, ibmr);
86	}
87
88	struct iwch_mw {
89	struct ib_mw ibmw;
90	struct iwch_dev *rhp;
91	u64 kva;
92	struct tpt_attributes attr;
93	};
94
95	static inline struct iwch_mw to_iwch_mw(struct ib_mw ibmw)
96	{
97	return container_of(ibmw, struct iwch_mw, ibmw);
98	}
99
100	struct iwch_cq {
101	struct ib_cq ibcq;
102	struct iwch_dev *rhp;
103	struct t3_cq cq;
104	spinlock_t lock;
105	atomic_t refcnt;
106	wait_queue_head_t wait;
107	u32 __user *user_rptr_addr;
108	};
109
110	static inline struct iwch_cq to_iwch_cq(struct ib_cq ibcq)
111	{
112	return container_of(ibcq, struct iwch_cq, ibcq);
113	}
114
115	enum IWCH_QP_FLAGS {
116	QP_QUIESCED = 0x01
117	};
118
119	struct iwch_mpa_attributes {
120	u8 recv_marker_enabled;
121	u8 xmit_marker_enabled; /* iWARP: enable inbound Read Resp. */
122	u8 crc_enabled;
123	u8 version; /* 0 or 1 */
124	};
125
126	struct iwch_qp_attributes {
127	u32 scq;
128	u32 rcq;
129	u32 sq_num_entries;
130	u32 rq_num_entries;
131	u32 sq_max_sges;
132	u32 sq_max_sges_rdma_write;
133	u32 rq_max_sges;
134	u32 state;
135	u8 enable_rdma_read;
136	u8 enable_rdma_write; /* enable inbound Read Resp. */
137	u8 enable_bind;
138	u8 enable_mmid0_fastreg; /* Enable STAG0 + Fast-register */
139	/*
140	* Next QP state. If specify the current state, only the
141	* QP attributes will be modified.
142	*/
143	u32 max_ord;
144	u32 max_ird;
145	u32 pd; /* IN */
146	u32 next_state;
147	char terminate_buffer[52];
148	u32 terminate_msg_len;
149	u8 is_terminate_local;
150	struct iwch_mpa_attributes mpa_attr; /* IN-OUT */
151	struct iwch_ep *llp_stream_handle;
152	char stream_msg_buf; / Last stream msg. before Idle -> RTS */
153	u32 stream_msg_buf_len; /* Only on Idle -> RTS */
154	};
155
156	struct iwch_qp {
157	struct ib_qp ibqp;
158	struct iwch_dev *rhp;
159	struct iwch_ep *ep;
160	struct iwch_qp_attributes attr;
161	struct t3_wq wq;
162	spinlock_t lock;
163	atomic_t refcnt;
164	wait_queue_head_t wait;
165	enum IWCH_QP_FLAGS flags;
166	struct timer_list timer;
167	};
168
169	static inline int qp_quiesced(struct iwch_qp *qhp)
170	{
171	return qhp->flags & QP_QUIESCED;
172	}
173
174	static inline struct iwch_qp to_iwch_qp(struct ib_qp ibqp)
175	{
176	return container_of(ibqp, struct iwch_qp, ibqp);
177	}
178
179	void iwch_qp_add_ref(struct ib_qp *qp);
180	void iwch_qp_rem_ref(struct ib_qp *qp);
b038ced7 SW	181
	182	struct iwch_ucontext {
	183	struct ib_ucontext ibucontext;
	184	struct cxio_ucontext uctx;
	185	u32 key;
	186	spinlock_t mmap_lock;
	187	struct list_head mmaps;
	188	};
	189
	190	static inline struct iwch_ucontext to_iwch_ucontext(struct ib_ucontext c)
	191	{
	192	return container_of(c, struct iwch_ucontext, ibucontext);
	193	}
	194
	195	struct iwch_mm_entry {
	196	struct list_head entry;
	197	u64 addr;
	198	u32 key;
	199	unsigned len;
	200	};
	201
	202	static inline struct iwch_mm_entry remove_mmap(struct iwch_ucontext ucontext,
	203	u32 key, unsigned len)
	204	{
	205	struct list_head pos, nxt;
	206	struct iwch_mm_entry *mm;
	207
	208	spin_lock(&ucontext->mmap_lock);
	209	list_for_each_safe(pos, nxt, &ucontext->mmaps) {
	210
	211	mm = list_entry(pos, struct iwch_mm_entry, entry);
	212	if (mm->key == key && mm->len == len) {
	213	list_del_init(&mm->entry);
	214	spin_unlock(&ucontext->mmap_lock);
	215	PDBG("%s key 0x%x addr 0x%llx len %d\n", __FUNCTION__,
	216	key, (unsigned long long) mm->addr, mm->len);
	217	return mm;
	218	}
	219	}
	220	spin_unlock(&ucontext->mmap_lock);
	221	return NULL;
	222	}
	223
	224	static inline void insert_mmap(struct iwch_ucontext *ucontext,
	225	struct iwch_mm_entry *mm)
	226	{
	227	spin_lock(&ucontext->mmap_lock);
	228	PDBG("%s key 0x%x addr 0x%llx len %d\n", __FUNCTION__,
	229	mm->key, (unsigned long long) mm->addr, mm->len);
	230	list_add_tail(&mm->entry, &ucontext->mmaps);
	231	spin_unlock(&ucontext->mmap_lock);
	232	}
	233
	234	enum iwch_qp_attr_mask {
	235	IWCH_QP_ATTR_NEXT_STATE = 1 << 0,
	236	IWCH_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
	237	IWCH_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
	238	IWCH_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
	239	IWCH_QP_ATTR_MAX_ORD = 1 << 11,
	240	IWCH_QP_ATTR_MAX_IRD = 1 << 12,
	241	IWCH_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
	242	IWCH_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
	243	IWCH_QP_ATTR_MPA_ATTR = 1 << 24,
	244	IWCH_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
245	IWCH_QP_ATTR_VALID_MODIFY = (IWCH_QP_ATTR_ENABLE_RDMA_READ \|
246	IWCH_QP_ATTR_ENABLE_RDMA_WRITE \|
247	IWCH_QP_ATTR_MAX_ORD \|
248	IWCH_QP_ATTR_MAX_IRD \|
249	IWCH_QP_ATTR_LLP_STREAM_HANDLE \|
250	IWCH_QP_ATTR_STREAM_MSG_BUFFER \|
251	IWCH_QP_ATTR_MPA_ATTR \|
252	IWCH_QP_ATTR_QP_CONTEXT_ACTIVATE)
253	};
254
255	int iwch_modify_qp(struct iwch_dev *rhp,
256	struct iwch_qp *qhp,
257	enum iwch_qp_attr_mask mask,
258	struct iwch_qp_attributes *attrs,
259	int internal);
260
261	enum iwch_qp_state {
262	IWCH_QP_STATE_IDLE,
263	IWCH_QP_STATE_RTS,
264	IWCH_QP_STATE_ERROR,
265	IWCH_QP_STATE_TERMINATE,
266	IWCH_QP_STATE_CLOSING,
267	IWCH_QP_STATE_TOT
268	};
269
270	static inline int iwch_convert_state(enum ib_qp_state ib_state)
271	{
272	switch (ib_state) {
273	case IB_QPS_RESET:
274	case IB_QPS_INIT:
275	return IWCH_QP_STATE_IDLE;
276	case IB_QPS_RTS:
277	return IWCH_QP_STATE_RTS;
278	case IB_QPS_SQD:
279	return IWCH_QP_STATE_CLOSING;
280	case IB_QPS_SQE:
281	return IWCH_QP_STATE_TERMINATE;
282	case IB_QPS_ERR:
283	return IWCH_QP_STATE_ERROR;
284	default:
285	return -1;
286	}
287	}
288
e64518f3	289	static inline u32 iwch_ib_to_tpt_access(int acc)
b038ced7	290	{
e64518f3 SW	291	return (acc & IB_ACCESS_REMOTE_WRITE ? TPT_REMOTE_WRITE : 0) \|
	292	(acc & IB_ACCESS_REMOTE_READ ? TPT_REMOTE_READ : 0) \|
	293	(acc & IB_ACCESS_LOCAL_WRITE ? TPT_LOCAL_WRITE : 0) \|
	294	TPT_LOCAL_READ;
	295	}
	296
	297	static inline u32 iwch_ib_to_mwbind_access(int acc)
	298	{
	299	return (acc & IB_ACCESS_REMOTE_WRITE ? T3_MEM_ACCESS_REM_WRITE : 0) \|
	300	(acc & IB_ACCESS_REMOTE_READ ? T3_MEM_ACCESS_REM_READ : 0) \|
	301	(acc & IB_ACCESS_LOCAL_WRITE ? T3_MEM_ACCESS_LOCAL_WRITE : 0) \|
	302	T3_MEM_ACCESS_LOCAL_READ;
b038ced7 SW	303	}
	304
	305	enum iwch_mmid_state {
	306	IWCH_STAG_STATE_VALID,
	307	IWCH_STAG_STATE_INVALID
	308	};
	309
	310	enum iwch_qp_query_flags {
	311	IWCH_QP_QUERY_CONTEXT_NONE = 0x0, /* No ctx; Only attrs */
	312	IWCH_QP_QUERY_CONTEXT_GET = 0x1, /* Get ctx + attrs */
	313	IWCH_QP_QUERY_CONTEXT_SUSPEND = 0x2, /* Not Supported */
	314
	315	/*
	316	* Quiesce QP context; Consumer
	317	* will NOT replay outstanding WR
	318	*/
	319	IWCH_QP_QUERY_CONTEXT_QUIESCE = 0x4,
	320	IWCH_QP_QUERY_CONTEXT_REMOVE = 0x8,
	321	IWCH_QP_QUERY_TEST_USERWRITE = 0x32 /* Test special */
	322	};
	323
	324	int iwch_post_send(struct ib_qp ibqp, struct ib_send_wr wr,
	325	struct ib_send_wr **bad_wr);
	326	int iwch_post_receive(struct ib_qp ibqp, struct ib_recv_wr wr,
	327	struct ib_recv_wr **bad_wr);
	328	int iwch_bind_mw(struct ib_qp *qp,
	329	struct ib_mw *mw,
	330	struct ib_mw_bind *mw_bind);
	331	int iwch_poll_cq(struct ib_cq ibcq, int num_entries, struct ib_wc wc);
	332	int iwch_post_terminate(struct iwch_qp qhp, struct respQ_msg_t rsp_msg);
	333	int iwch_register_device(struct iwch_dev *dev);
	334	void iwch_unregister_device(struct iwch_dev *dev);
	335	int iwch_quiesce_qps(struct iwch_cq *chp);
	336	int iwch_resume_qps(struct iwch_cq *chp);
	337	void stop_read_rep_timer(struct iwch_qp *qhp);
	338	int iwch_register_mem(struct iwch_dev rhp, struct iwch_pd php,
	339	struct iwch_mr *mhp,
	340	int shift,
	341	__be64 *page_list);
	342	int iwch_reregister_mem(struct iwch_dev rhp, struct iwch_pd php,
	343	struct iwch_mr *mhp,
	344	int shift,
	345	__be64 *page_list,
	346	int npages);
	347	int build_phys_page_list(struct ib_phys_buf *buffer_list,
	348	int num_phys_buf,
	349	u64 *iova_start,
	350	u64 *total_size,
	351	int *npages,
	352	int *shift,
	353	__be64 **page_list);
	354
	355
	356	#define IWCH_NODE_DESC "cxgb3 Chelsio Communications"
	357
	358	#endif