[mirror_ubuntu-artful-kernel.git] / drivers / infiniband / hw / cxgb4 / t4.h

/*
 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */
#ifndef __T4_H__
#define __T4_H__

#include "t4_hw.h"
#include "t4_regs.h"
#include "t4_msg.h"
#include "t4fw_ri_api.h"

#define T4_MAX_NUM_PD 65536
#define T4_MAX_MR_SIZE (~0ULL)
#define T4_PAGESIZE_MASK 0xffff000  /* 4KB-128MB */
#define T4_STAG_UNSET 0xffffffff
#define T4_FW_MAJ 0
#define PCIE_MA_SYNC_A 0x30b4

struct t4_status_page {
	__be32 rsvd1;	/* flit 0 - hw owns */
	__be16 rsvd2;
	__be16 qid;
	__be16 cidx;
	__be16 pidx;
	u8 qp_err;	/* flit 1 - sw owns */
	u8 db_off;
	u8 pad;
	u16 host_wq_pidx;
	u16 host_cidx;
	u16 host_pidx;
};

#define T4_EQ_ENTRY_SIZE 64

#define T4_SQ_NUM_SLOTS 5
#define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS)
#define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
			sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
#define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
			sizeof(struct fw_ri_immd)))
#define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \
			sizeof(struct fw_ri_rdma_write_wr) - \
			sizeof(struct fw_ri_immd)))
#define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \
			sizeof(struct fw_ri_rdma_write_wr) - \
			sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
#define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
			sizeof(struct fw_ri_immd)) & ~31UL)
#define T4_MAX_FR_IMMD_DEPTH (T4_MAX_FR_IMMD / sizeof(u64))
#define T4_MAX_FR_DSGL 1024
#define T4_MAX_FR_DSGL_DEPTH (T4_MAX_FR_DSGL / sizeof(u64))

static inline int t4_max_fr_depth(int use_dsgl)
{
	return use_dsgl ? T4_MAX_FR_DSGL_DEPTH : T4_MAX_FR_IMMD_DEPTH;
}

#define T4_RQ_NUM_SLOTS 2
#define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS)
#define T4_MAX_RECV_SGE 4

union t4_wr {
	struct fw_ri_res_wr res;
	struct fw_ri_wr ri;
	struct fw_ri_rdma_write_wr write;
	struct fw_ri_send_wr send;
	struct fw_ri_rdma_read_wr read;
	struct fw_ri_bind_mw_wr bind;
	struct fw_ri_fr_nsmr_wr fr;
	struct fw_ri_inv_lstag_wr inv;
	struct t4_status_page status;
	__be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS];
};

union t4_recv_wr {
	struct fw_ri_recv_wr recv;
	struct t4_status_page status;
	__be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS];
};

static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid,
			       enum fw_wr_opcodes opcode, u8 flags, u8 len16)
{
	wqe->send.opcode = (u8)opcode;
	wqe->send.flags = flags;
	wqe->send.wrid = wrid;
	wqe->send.r1[0] = 0;
	wqe->send.r1[1] = 0;
	wqe->send.r1[2] = 0;
	wqe->send.len16 = len16;
}

/* CQE/AE status codes */
#define T4_ERR_SUCCESS                     0x0
#define T4_ERR_STAG                        0x1	/* STAG invalid: either the */
						/* STAG is offlimt, being 0, */
						/* or STAG_key mismatch */
#define T4_ERR_PDID                        0x2	/* PDID mismatch */
#define T4_ERR_QPID                        0x3	/* QPID mismatch */
#define T4_ERR_ACCESS                      0x4	/* Invalid access right */
#define T4_ERR_WRAP                        0x5	/* Wrap error */
#define T4_ERR_BOUND                       0x6	/* base and bounds voilation */
#define T4_ERR_INVALIDATE_SHARED_MR        0x7	/* attempt to invalidate a  */
						/* shared memory region */
#define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8	/* attempt to invalidate a  */
						/* shared memory region */
#define T4_ERR_ECC                         0x9	/* ECC error detected */
#define T4_ERR_ECC_PSTAG                   0xA	/* ECC error detected when  */
						/* reading PSTAG for a MW  */
						/* Invalidate */
#define T4_ERR_PBL_ADDR_BOUND              0xB	/* pbl addr out of bounds:  */
						/* software error */
#define T4_ERR_SWFLUSH			   0xC	/* SW FLUSHED */
#define T4_ERR_CRC                         0x10 /* CRC error */
#define T4_ERR_MARKER                      0x11 /* Marker error */
#define T4_ERR_PDU_LEN_ERR                 0x12 /* invalid PDU length */
#define T4_ERR_OUT_OF_RQE                  0x13 /* out of RQE */
#define T4_ERR_DDP_VERSION                 0x14 /* wrong DDP version */
#define T4_ERR_RDMA_VERSION                0x15 /* wrong RDMA version */
#define T4_ERR_OPCODE                      0x16 /* invalid rdma opcode */
#define T4_ERR_DDP_QUEUE_NUM               0x17 /* invalid ddp queue number */
#define T4_ERR_MSN                         0x18 /* MSN error */
#define T4_ERR_TBIT                        0x19 /* tag bit not set correctly */
#define T4_ERR_MO                          0x1A /* MO not 0 for TERMINATE  */
						/* or READ_REQ */
#define T4_ERR_MSN_GAP                     0x1B
#define T4_ERR_MSN_RANGE                   0x1C
#define T4_ERR_IRD_OVERFLOW                0x1D
#define T4_ERR_RQE_ADDR_BOUND              0x1E /* RQE addr out of bounds:  */
						/* software error */
#define T4_ERR_INTERNAL_ERR                0x1F /* internal error (opcode  */
						/* mismatch) */
/*
 * CQE defs
 */
struct t4_cqe {
	__be32 header;
	__be32 len;
	union {
		struct {
			__be32 stag;
			__be32 msn;
		} rcqe;
		struct {
			u32 nada1;
			u16 nada2;
			u16 cidx;
		} scqe;
		struct {
			__be32 wrid_hi;
			__be32 wrid_low;
		} gen;
	} u;
	__be64 reserved;
	__be64 bits_type_ts;
};

/* macros for flit 0 of the cqe */

#define CQE_QPID_S        12
#define CQE_QPID_M        0xFFFFF
#define CQE_QPID_G(x)     ((((x) >> CQE_QPID_S)) & CQE_QPID_M)
#define CQE_QPID_V(x)	  ((x)<<CQE_QPID_S)

#define CQE_SWCQE_S       11
#define CQE_SWCQE_M       0x1
#define CQE_SWCQE_G(x)    ((((x) >> CQE_SWCQE_S)) & CQE_SWCQE_M)
#define CQE_SWCQE_V(x)	  ((x)<<CQE_SWCQE_S)

#define CQE_STATUS_S      5
#define CQE_STATUS_M      0x1F
#define CQE_STATUS_G(x)   ((((x) >> CQE_STATUS_S)) & CQE_STATUS_M)
#define CQE_STATUS_V(x)   ((x)<<CQE_STATUS_S)

#define CQE_TYPE_S        4
#define CQE_TYPE_M        0x1
#define CQE_TYPE_G(x)     ((((x) >> CQE_TYPE_S)) & CQE_TYPE_M)
#define CQE_TYPE_V(x)     ((x)<<CQE_TYPE_S)

#define CQE_OPCODE_S      0
#define CQE_OPCODE_M      0xF
#define CQE_OPCODE_G(x)   ((((x) >> CQE_OPCODE_S)) & CQE_OPCODE_M)
#define CQE_OPCODE_V(x)   ((x)<<CQE_OPCODE_S)

#define SW_CQE(x)         (CQE_SWCQE_G(be32_to_cpu((x)->header)))
#define CQE_QPID(x)       (CQE_QPID_G(be32_to_cpu((x)->header)))
#define CQE_TYPE(x)       (CQE_TYPE_G(be32_to_cpu((x)->header)))
#define SQ_TYPE(x)	  (CQE_TYPE((x)))
#define RQ_TYPE(x)	  (!CQE_TYPE((x)))
#define CQE_STATUS(x)     (CQE_STATUS_G(be32_to_cpu((x)->header)))
#define CQE_OPCODE(x)     (CQE_OPCODE_G(be32_to_cpu((x)->header)))

#define CQE_SEND_OPCODE(x)( \
	(CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND) || \
	(CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \
	(CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \
	(CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV))

#define CQE_LEN(x)        (be32_to_cpu((x)->len))

/* used for RQ completion processing */
#define CQE_WRID_STAG(x)  (be32_to_cpu((x)->u.rcqe.stag))
#define CQE_WRID_MSN(x)   (be32_to_cpu((x)->u.rcqe.msn))

/* used for SQ completion processing */
#define CQE_WRID_SQ_IDX(x)	((x)->u.scqe.cidx)

/* generic accessor macros */
#define CQE_WRID_HI(x)		(be32_to_cpu((x)->u.gen.wrid_hi))
#define CQE_WRID_LOW(x)		(be32_to_cpu((x)->u.gen.wrid_low))

/* macros for flit 3 of the cqe */
#define CQE_GENBIT_S	63
#define CQE_GENBIT_M	0x1
#define CQE_GENBIT_G(x)	(((x) >> CQE_GENBIT_S) & CQE_GENBIT_M)
#define CQE_GENBIT_V(x) ((x)<<CQE_GENBIT_S)

#define CQE_OVFBIT_S	62
#define CQE_OVFBIT_M	0x1
#define CQE_OVFBIT_G(x)	((((x) >> CQE_OVFBIT_S)) & CQE_OVFBIT_M)

#define CQE_IQTYPE_S	60
#define CQE_IQTYPE_M	0x3
#define CQE_IQTYPE_G(x)	((((x) >> CQE_IQTYPE_S)) & CQE_IQTYPE_M)

#define CQE_TS_M	0x0fffffffffffffffULL
#define CQE_TS_G(x)	((x) & CQE_TS_M)

#define CQE_OVFBIT(x)	((unsigned)CQE_OVFBIT_G(be64_to_cpu((x)->bits_type_ts)))
#define CQE_GENBIT(x)	((unsigned)CQE_GENBIT_G(be64_to_cpu((x)->bits_type_ts)))
#define CQE_TS(x)	(CQE_TS_G(be64_to_cpu((x)->bits_type_ts)))

struct t4_swsqe {
	u64			wr_id;
	struct t4_cqe		cqe;
	int			read_len;
	int			opcode;
	int			complete;
	int			signaled;
	u16			idx;
	int                     flushed;
	struct timespec         host_ts;
	u64                     sge_ts;
};

static inline pgprot_t t4_pgprot_wc(pgprot_t prot)
{
#if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64)
	return pgprot_writecombine(prot);
#else
	return pgprot_noncached(prot);
#endif
}

enum {
	T4_SQ_ONCHIP = (1<<0),
};

struct t4_sq {
	union t4_wr *queue;
	dma_addr_t dma_addr;
	DEFINE_DMA_UNMAP_ADDR(mapping);
	unsigned long phys_addr;
	struct t4_swsqe *sw_sq;
	struct t4_swsqe *oldest_read;
	u64 __iomem *udb;
	size_t memsize;
	u32 qid;
	u16 in_use;
	u16 size;
	u16 cidx;
	u16 pidx;
	u16 wq_pidx;
	u16 wq_pidx_inc;
	u16 flags;
	short flush_cidx;
};

struct t4_swrqe {
	u64 wr_id;
	struct timespec host_ts;
	u64 sge_ts;
};

struct t4_rq {
	union  t4_recv_wr *queue;
	dma_addr_t dma_addr;
	DEFINE_DMA_UNMAP_ADDR(mapping);
	struct t4_swrqe *sw_rq;
	u64 __iomem *udb;
	size_t memsize;
	u32 qid;
	u32 msn;
	u32 rqt_hwaddr;
	u16 rqt_size;
	u16 in_use;
	u16 size;
	u16 cidx;
	u16 pidx;
	u16 wq_pidx;
	u16 wq_pidx_inc;
};

struct t4_wq {
	struct t4_sq sq;
	struct t4_rq rq;
	void __iomem *db;
	void __iomem *gts;
	struct c4iw_rdev *rdev;
	int flushed;
};

static inline int t4_rqes_posted(struct t4_wq *wq)
{
	return wq->rq.in_use;
}

static inline int t4_rq_empty(struct t4_wq *wq)
{
	return wq->rq.in_use == 0;
}

static inline int t4_rq_full(struct t4_wq *wq)
{
	return wq->rq.in_use == (wq->rq.size - 1);
}

static inline u32 t4_rq_avail(struct t4_wq *wq)
{
	return wq->rq.size - 1 - wq->rq.in_use;
}

static inline void t4_rq_produce(struct t4_wq *wq, u8 len16)
{
	wq->rq.in_use++;
	if (++wq->rq.pidx == wq->rq.size)
		wq->rq.pidx = 0;
	wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
	if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS)
		wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS;
}

static inline void t4_rq_consume(struct t4_wq *wq)
{
	wq->rq.in_use--;
	wq->rq.msn++;
	if (++wq->rq.cidx == wq->rq.size)
		wq->rq.cidx = 0;
}

static inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq)
{
	return wq->rq.queue[wq->rq.size].status.host_wq_pidx;
}

static inline u16 t4_rq_wq_size(struct t4_wq *wq)
{
		return wq->rq.size * T4_RQ_NUM_SLOTS;
}

static inline int t4_sq_onchip(struct t4_sq *sq)
{
	return sq->flags & T4_SQ_ONCHIP;
}

static inline int t4_sq_empty(struct t4_wq *wq)
{
	return wq->sq.in_use == 0;
}

static inline int t4_sq_full(struct t4_wq *wq)
{
	return wq->sq.in_use == (wq->sq.size - 1);
}

static inline u32 t4_sq_avail(struct t4_wq *wq)
{
	return wq->sq.size - 1 - wq->sq.in_use;
}

static inline void t4_sq_produce(struct t4_wq *wq, u8 len16)
{
	wq->sq.in_use++;
	if (++wq->sq.pidx == wq->sq.size)
		wq->sq.pidx = 0;
	wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
	if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS)
		wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS;
}

static inline void t4_sq_consume(struct t4_wq *wq)
{
	BUG_ON(wq->sq.in_use < 1);
	if (wq->sq.cidx == wq->sq.flush_cidx)
		wq->sq.flush_cidx = -1;
	wq->sq.in_use--;
	if (++wq->sq.cidx == wq->sq.size)
		wq->sq.cidx = 0;
}

static inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq)
{
	return wq->sq.queue[wq->sq.size].status.host_wq_pidx;
}

static inline u16 t4_sq_wq_size(struct t4_wq *wq)
{
		return wq->sq.size * T4_SQ_NUM_SLOTS;
}

/* This function copies 64 byte coalesced work request to memory
 * mapped BAR2 space. For coalesced WRs, the SGE fetches data
 * from the FIFO instead of from Host.
 */
static inline void pio_copy(u64 __iomem *dst, u64 *src)
{
	int count = 8;

	while (count) {
		writeq(*src, dst);
		src++;
		dst++;
		count--;
	}
}

static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, u8 t5,
				 union t4_wr *wqe)
{

	/* Flush host queue memory writes. */
	wmb();
	if (t5) {
		if (inc == 1 && wqe) {
			PDBG("%s: WC wq->sq.pidx = %d\n",
			     __func__, wq->sq.pidx);
			pio_copy(wq->sq.udb + 7, (void *)wqe);
		} else {
			PDBG("%s: DB wq->sq.pidx = %d\n",
			     __func__, wq->sq.pidx);
			writel(PIDX_T5_V(inc), wq->sq.udb);
		}

		/* Flush user doorbell area writes. */
		wmb();
		return;
	}
	writel(QID_V(wq->sq.qid) | PIDX_V(inc), wq->db);
}

static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc, u8 t5,
				 union t4_recv_wr *wqe)
{

	/* Flush host queue memory writes. */
	wmb();
	if (t5) {
		if (inc == 1 && wqe) {
			PDBG("%s: WC wq->rq.pidx = %d\n",
			     __func__, wq->rq.pidx);
			pio_copy(wq->rq.udb + 7, (void *)wqe);
		} else {
			PDBG("%s: DB wq->rq.pidx = %d\n",
			     __func__, wq->rq.pidx);
			writel(PIDX_T5_V(inc), wq->rq.udb);
		}

		/* Flush user doorbell area writes. */
		wmb();
		return;
	}
	writel(QID_V(wq->rq.qid) | PIDX_V(inc), wq->db);
}

static inline int t4_wq_in_error(struct t4_wq *wq)
{
	return wq->rq.queue[wq->rq.size].status.qp_err;
}

static inline void t4_set_wq_in_error(struct t4_wq *wq)
{
	wq->rq.queue[wq->rq.size].status.qp_err = 1;
}

static inline void t4_disable_wq_db(struct t4_wq *wq)
{
	wq->rq.queue[wq->rq.size].status.db_off = 1;
}

static inline void t4_enable_wq_db(struct t4_wq *wq)
{
	wq->rq.queue[wq->rq.size].status.db_off = 0;
}

static inline int t4_wq_db_enabled(struct t4_wq *wq)
{
	return !wq->rq.queue[wq->rq.size].status.db_off;
}

enum t4_cq_flags {
	CQ_ARMED	= 1,
};

struct t4_cq {
	struct t4_cqe *queue;
	dma_addr_t dma_addr;
	DEFINE_DMA_UNMAP_ADDR(mapping);
	struct t4_cqe *sw_queue;
	void __iomem *gts;
	struct c4iw_rdev *rdev;
	u64 ugts;
	size_t memsize;
	__be64 bits_type_ts;
	u32 cqid;
	u32 qid_mask;
	int vector;
	u16 size; /* including status page */
	u16 cidx;
	u16 sw_pidx;
	u16 sw_cidx;
	u16 sw_in_use;
	u16 cidx_inc;
	u8 gen;
	u8 error;
	unsigned long flags;
};

static inline int t4_clear_cq_armed(struct t4_cq *cq)
{
	return test_and_clear_bit(CQ_ARMED, &cq->flags);
}

static inline int t4_arm_cq(struct t4_cq *cq, int se)
{
	u32 val;

	set_bit(CQ_ARMED, &cq->flags);
	while (cq->cidx_inc > CIDXINC_M) {
		val = SEINTARM_V(0) | CIDXINC_V(CIDXINC_M) | TIMERREG_V(7) |
		      INGRESSQID_V(cq->cqid & cq->qid_mask);
		writel(val, cq->gts);
		cq->cidx_inc -= CIDXINC_M;
	}
	val = SEINTARM_V(se) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(6) |
	      INGRESSQID_V(cq->cqid & cq->qid_mask);
	writel(val, cq->gts);
	cq->cidx_inc = 0;
	return 0;
}

static inline void t4_swcq_produce(struct t4_cq *cq)
{
	cq->sw_in_use++;
	if (cq->sw_in_use == cq->size) {
		PDBG("%s cxgb4 sw cq overflow cqid %u\n", __func__, cq->cqid);
		cq->error = 1;
		BUG_ON(1);
	}
	if (++cq->sw_pidx == cq->size)
		cq->sw_pidx = 0;
}

static inline void t4_swcq_consume(struct t4_cq *cq)
{
	BUG_ON(cq->sw_in_use < 1);
	cq->sw_in_use--;
	if (++cq->sw_cidx == cq->size)
		cq->sw_cidx = 0;
}

static inline void t4_hwcq_consume(struct t4_cq *cq)
{
	cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts;
	if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == CIDXINC_M) {
		u32 val;

		val = SEINTARM_V(0) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(7) |
		      INGRESSQID_V(cq->cqid & cq->qid_mask);
		writel(val, cq->gts);
		cq->cidx_inc = 0;
	}
	if (++cq->cidx == cq->size) {
		cq->cidx = 0;
		cq->gen ^= 1;
	}
}

static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe)
{
	return (CQE_GENBIT(cqe) == cq->gen);
}

static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
{
	int ret;
	u16 prev_cidx;

	if (cq->cidx == 0)
		prev_cidx = cq->size - 1;
	else
		prev_cidx = cq->cidx - 1;

	if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) {
		ret = -EOVERFLOW;
		cq->error = 1;
		printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid);
		BUG_ON(1);
	} else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) {

		/* Ensure CQE is flushed to memory */
		rmb();
		*cqe = &cq->queue[cq->cidx];
		ret = 0;
	} else
		ret = -ENODATA;
	return ret;
}

static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq)
{
	if (cq->sw_in_use == cq->size) {
		PDBG("%s cxgb4 sw cq overflow cqid %u\n", __func__, cq->cqid);
		cq->error = 1;
		BUG_ON(1);
		return NULL;
	}
	if (cq->sw_in_use)
		return &cq->sw_queue[cq->sw_cidx];
	return NULL;
}

static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
{
	int ret = 0;

	if (cq->error)
		ret = -ENODATA;
	else if (cq->sw_in_use)
		*cqe = &cq->sw_queue[cq->sw_cidx];
	else
		ret = t4_next_hw_cqe(cq, cqe);
	return ret;
}

static inline int t4_cq_in_error(struct t4_cq *cq)
{
	return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err;
}

static inline void t4_set_cq_in_error(struct t4_cq *cq)
{
	((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1;
}
#endif

struct t4_dev_status_page {
	u8 db_off;
};
Commit	Line	Data
cfdda9d7 SW	1	/*
	2	* Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	* - Redistributions in binary form must reproduce the above
	18	* copyright notice, this list of conditions and the following
	19	* disclaimer in the documentation and/or other materials
	20	* provided with the distribution.
	21	*
	22	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	23	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	24	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	25	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	26	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	27	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	28	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	29	* SOFTWARE.
	30	*/
	31	#ifndef __T4_H__
	32	#define __T4_H__
	33
	34	#include "t4_hw.h"
	35	#include "t4_regs.h"
	36	#include "t4_msg.h"
	37	#include "t4fw_ri_api.h"
	38
1cf24dce	39	#define T4_MAX_NUM_PD 65536
a2de1499	40	#define T4_MAX_MR_SIZE (~0ULL)
cfdda9d7 SW	41	#define T4_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */
	42	#define T4_STAG_UNSET 0xffffffff
	43	#define T4_FW_MAJ 0
a56c66e8	44	#define PCIE_MA_SYNC_A 0x30b4
cfdda9d7 SW	45
	46	struct t4_status_page {
	47	__be32 rsvd1; /* flit 0 - hw owns */
	48	__be16 rsvd2;
	49	__be16 qid;
	50	__be16 cidx;
	51	__be16 pidx;
	52	u8 qp_err; /* flit 1 - sw owns */
	53	u8 db_off;
422eea0a VP	54	u8 pad;
	55	u16 host_wq_pidx;
	56	u16 host_cidx;
	57	u16 host_pidx;
cfdda9d7 SW	58	};
cfdda9d7 SW	59
d37ac31d	60	#define T4_EQ_ENTRY_SIZE 64
cfdda9d7	61
40dbf6ee	62	#define T4_SQ_NUM_SLOTS 5
d37ac31d	63	#define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS)
cfdda9d7 SW	64	#define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
	65	sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
	66	#define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
	67	sizeof(struct fw_ri_immd)))
	68	#define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \
	69	sizeof(struct fw_ri_rdma_write_wr) - \
	70	sizeof(struct fw_ri_immd)))
	71	#define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \
	72	sizeof(struct fw_ri_rdma_write_wr) - \
	73	sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
	74	#define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
40dbf6ee	75	sizeof(struct fw_ri_immd)) & ~31UL)
a03d9f94 SW	76	#define T4_MAX_FR_IMMD_DEPTH (T4_MAX_FR_IMMD / sizeof(u64))
	77	#define T4_MAX_FR_DSGL 1024
	78	#define T4_MAX_FR_DSGL_DEPTH (T4_MAX_FR_DSGL / sizeof(u64))
	79
	80	static inline int t4_max_fr_depth(int use_dsgl)
	81	{
	82	return use_dsgl ? T4_MAX_FR_DSGL_DEPTH : T4_MAX_FR_IMMD_DEPTH;
	83	}
cfdda9d7 SW	84
cfdda9d7 SW	85	#define T4_RQ_NUM_SLOTS 2
d37ac31d	86	#define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS)
f64b8843	87	#define T4_MAX_RECV_SGE 4
cfdda9d7 SW	88
	89	union t4_wr {
	90	struct fw_ri_res_wr res;
	91	struct fw_ri_wr ri;
	92	struct fw_ri_rdma_write_wr write;
	93	struct fw_ri_send_wr send;
	94	struct fw_ri_rdma_read_wr read;
	95	struct fw_ri_bind_mw_wr bind;
	96	struct fw_ri_fr_nsmr_wr fr;
	97	struct fw_ri_inv_lstag_wr inv;
	98	struct t4_status_page status;
d37ac31d	99	__be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS];
cfdda9d7 SW	100	};
	101
	102	union t4_recv_wr {
	103	struct fw_ri_recv_wr recv;
	104	struct t4_status_page status;
d37ac31d	105	__be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS];
cfdda9d7 SW	106	};
	107
	108	static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid,
	109	enum fw_wr_opcodes opcode, u8 flags, u8 len16)
	110	{
cfdda9d7 SW	111	wqe->send.opcode = (u8)opcode;
	112	wqe->send.flags = flags;
	113	wqe->send.wrid = wrid;
	114	wqe->send.r1[0] = 0;
	115	wqe->send.r1[1] = 0;
	116	wqe->send.r1[2] = 0;
	117	wqe->send.len16 = len16;
cfdda9d7 SW	118	}
	119
	120	/* CQE/AE status codes */
	121	#define T4_ERR_SUCCESS 0x0
	122	#define T4_ERR_STAG 0x1 /* STAG invalid: either the */
	123	/* STAG is offlimt, being 0, */
	124	/* or STAG_key mismatch */
	125	#define T4_ERR_PDID 0x2 /* PDID mismatch */
	126	#define T4_ERR_QPID 0x3 /* QPID mismatch */
	127	#define T4_ERR_ACCESS 0x4 /* Invalid access right */
	128	#define T4_ERR_WRAP 0x5 /* Wrap error */
	129	#define T4_ERR_BOUND 0x6 /* base and bounds voilation */
	130	#define T4_ERR_INVALIDATE_SHARED_MR 0x7 /* attempt to invalidate a */
	131	/* shared memory region */
	132	#define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8 /* attempt to invalidate a */
	133	/* shared memory region */
	134	#define T4_ERR_ECC 0x9 /* ECC error detected */
	135	#define T4_ERR_ECC_PSTAG 0xA /* ECC error detected when */
	136	/* reading PSTAG for a MW */
	137	/* Invalidate */
	138	#define T4_ERR_PBL_ADDR_BOUND 0xB /* pbl addr out of bounds: */
	139	/* software error */
	140	#define T4_ERR_SWFLUSH 0xC /* SW FLUSHED */
	141	#define T4_ERR_CRC 0x10 /* CRC error */
	142	#define T4_ERR_MARKER 0x11 /* Marker error */
	143	#define T4_ERR_PDU_LEN_ERR 0x12 /* invalid PDU length */
	144	#define T4_ERR_OUT_OF_RQE 0x13 /* out of RQE */
	145	#define T4_ERR_DDP_VERSION 0x14 /* wrong DDP version */
	146	#define T4_ERR_RDMA_VERSION 0x15 /* wrong RDMA version */
	147	#define T4_ERR_OPCODE 0x16 /* invalid rdma opcode */
	148	#define T4_ERR_DDP_QUEUE_NUM 0x17 /* invalid ddp queue number */
	149	#define T4_ERR_MSN 0x18 /* MSN error */
	150	#define T4_ERR_TBIT 0x19 /* tag bit not set correctly */
	151	#define T4_ERR_MO 0x1A /* MO not 0 for TERMINATE */
	152	/* or READ_REQ */
	153	#define T4_ERR_MSN_GAP 0x1B
	154	#define T4_ERR_MSN_RANGE 0x1C
	155	#define T4_ERR_IRD_OVERFLOW 0x1D
	156	#define T4_ERR_RQE_ADDR_BOUND 0x1E /* RQE addr out of bounds: */
	157	/* software error */
	158	#define T4_ERR_INTERNAL_ERR 0x1F /* internal error (opcode */
	159	/* mismatch) */
	160	/*
	161	* CQE defs
	162	*/
	163	struct t4_cqe {
	164	__be32 header;
	165	__be32 len;
	166	union {
	167	struct {
	168	__be32 stag;
	169	__be32 msn;
	170	} rcqe;
	171	struct {
	172	u32 nada1;
	173	u16 nada2;
	174	u16 cidx;
	175	} scqe;
	176	struct {
	177	__be32 wrid_hi;
	178	__be32 wrid_low;
	179	} gen;
	180	} u;
	181	__be64 reserved;
182	__be64 bits_type_ts;
183	};
184
185	/* macros for flit 0 of the cqe */
186
a56c66e8 HS	187	#define CQE_QPID_S 12
	188	#define CQE_QPID_M 0xFFFFF
	189	#define CQE_QPID_G(x) ((((x) >> CQE_QPID_S)) & CQE_QPID_M)
	190	#define CQE_QPID_V(x) ((x)<<CQE_QPID_S)
cfdda9d7	191
a56c66e8 HS	192	#define CQE_SWCQE_S 11
	193	#define CQE_SWCQE_M 0x1
	194	#define CQE_SWCQE_G(x) ((((x) >> CQE_SWCQE_S)) & CQE_SWCQE_M)
	195	#define CQE_SWCQE_V(x) ((x)<<CQE_SWCQE_S)
cfdda9d7	196
a56c66e8 HS	197	#define CQE_STATUS_S 5
	198	#define CQE_STATUS_M 0x1F
	199	#define CQE_STATUS_G(x) ((((x) >> CQE_STATUS_S)) & CQE_STATUS_M)
	200	#define CQE_STATUS_V(x) ((x)<<CQE_STATUS_S)
cfdda9d7	201
a56c66e8 HS	202	#define CQE_TYPE_S 4
	203	#define CQE_TYPE_M 0x1
	204	#define CQE_TYPE_G(x) ((((x) >> CQE_TYPE_S)) & CQE_TYPE_M)
	205	#define CQE_TYPE_V(x) ((x)<<CQE_TYPE_S)
cfdda9d7	206
a56c66e8 HS	207	#define CQE_OPCODE_S 0
	208	#define CQE_OPCODE_M 0xF
	209	#define CQE_OPCODE_G(x) ((((x) >> CQE_OPCODE_S)) & CQE_OPCODE_M)
	210	#define CQE_OPCODE_V(x) ((x)<<CQE_OPCODE_S)
cfdda9d7	211
a56c66e8 HS	212	#define SW_CQE(x) (CQE_SWCQE_G(be32_to_cpu((x)->header)))
	213	#define CQE_QPID(x) (CQE_QPID_G(be32_to_cpu((x)->header)))
	214	#define CQE_TYPE(x) (CQE_TYPE_G(be32_to_cpu((x)->header)))
cfdda9d7 SW	215	#define SQ_TYPE(x) (CQE_TYPE((x)))
cfdda9d7 SW	216	#define RQ_TYPE(x) (!CQE_TYPE((x)))
a56c66e8 HS	217	#define CQE_STATUS(x) (CQE_STATUS_G(be32_to_cpu((x)->header)))
a56c66e8 HS	218	#define CQE_OPCODE(x) (CQE_OPCODE_G(be32_to_cpu((x)->header)))
cfdda9d7 SW	219
cfdda9d7 SW	220	#define CQE_SEND_OPCODE(x)( \
a56c66e8 HS	221	(CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND) \|\| \
	222	(CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) \|\| \
	223	(CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) \|\| \
	224	(CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV))
cfdda9d7 SW	225
	226	#define CQE_LEN(x) (be32_to_cpu((x)->len))
	227
	228	/* used for RQ completion processing */
	229	#define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag))
	230	#define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn))
	231
	232	/* used for SQ completion processing */
	233	#define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx)
	234
	235	/* generic accessor macros */
031cf476 HS	236	#define CQE_WRID_HI(x) (be32_to_cpu((x)->u.gen.wrid_hi))
031cf476 HS	237	#define CQE_WRID_LOW(x) (be32_to_cpu((x)->u.gen.wrid_low))
cfdda9d7 SW	238
cfdda9d7 SW	239	/* macros for flit 3 of the cqe */
a56c66e8 HS	240	#define CQE_GENBIT_S 63
	241	#define CQE_GENBIT_M 0x1
	242	#define CQE_GENBIT_G(x) (((x) >> CQE_GENBIT_S) & CQE_GENBIT_M)
	243	#define CQE_GENBIT_V(x) ((x)<<CQE_GENBIT_S)
cfdda9d7	244
a56c66e8 HS	245	#define CQE_OVFBIT_S 62
	246	#define CQE_OVFBIT_M 0x1
	247	#define CQE_OVFBIT_G(x) ((((x) >> CQE_OVFBIT_S)) & CQE_OVFBIT_M)
cfdda9d7	248
a56c66e8 HS	249	#define CQE_IQTYPE_S 60
	250	#define CQE_IQTYPE_M 0x3
	251	#define CQE_IQTYPE_G(x) ((((x) >> CQE_IQTYPE_S)) & CQE_IQTYPE_M)
cfdda9d7	252
a56c66e8 HS	253	#define CQE_TS_M 0x0fffffffffffffffULL
a56c66e8 HS	254	#define CQE_TS_G(x) ((x) & CQE_TS_M)
cfdda9d7	255
a56c66e8 HS	256	#define CQE_OVFBIT(x) ((unsigned)CQE_OVFBIT_G(be64_to_cpu((x)->bits_type_ts)))
	257	#define CQE_GENBIT(x) ((unsigned)CQE_GENBIT_G(be64_to_cpu((x)->bits_type_ts)))
	258	#define CQE_TS(x) (CQE_TS_G(be64_to_cpu((x)->bits_type_ts)))
cfdda9d7 SW	259
	260	struct t4_swsqe {
	261	u64 wr_id;
	262	struct t4_cqe cqe;
	263	int read_len;
	264	int opcode;
	265	int complete;
	266	int signaled;
	267	u16 idx;
1cf24dce	268	int flushed;
7730b4c7 HS	269	struct timespec host_ts;
7730b4c7 HS	270	u64 sge_ts;
cfdda9d7 SW	271	};
cfdda9d7 SW	272
c6d7b267 SW	273	static inline pgprot_t t4_pgprot_wc(pgprot_t prot)
c6d7b267 SW	274	{
e297d9dd	275	#if defined(__i386__) \|\| defined(__x86_64__) \|\| defined(CONFIG_PPC64)
c6d7b267	276	return pgprot_writecombine(prot);
c6d7b267 SW	277	#else
	278	return pgprot_noncached(prot);
	279	#endif
	280	}
	281
c6d7b267 SW	282	enum {
	283	T4_SQ_ONCHIP = (1<<0),
	284	};
	285
cfdda9d7 SW	286	struct t4_sq {
	287	union t4_wr *queue;
	288	dma_addr_t dma_addr;
f38926aa	289	DEFINE_DMA_UNMAP_ADDR(mapping);
c6d7b267	290	unsigned long phys_addr;
cfdda9d7 SW	291	struct t4_swsqe *sw_sq;
cfdda9d7 SW	292	struct t4_swsqe *oldest_read;
fa658a98	293	u64 __iomem *udb;
cfdda9d7 SW	294	size_t memsize;
	295	u32 qid;
	296	u16 in_use;
	297	u16 size;
	298	u16 cidx;
	299	u16 pidx;
d37ac31d	300	u16 wq_pidx;
05eb2389	301	u16 wq_pidx_inc;
c6d7b267	302	u16 flags;
1cf24dce	303	short flush_cidx;
cfdda9d7 SW	304	};
	305
	306	struct t4_swrqe {
	307	u64 wr_id;
7730b4c7 HS	308	struct timespec host_ts;
7730b4c7 HS	309	u64 sge_ts;
cfdda9d7 SW	310	};
	311
	312	struct t4_rq {
	313	union t4_recv_wr *queue;
	314	dma_addr_t dma_addr;
f38926aa	315	DEFINE_DMA_UNMAP_ADDR(mapping);
cfdda9d7	316	struct t4_swrqe *sw_rq;
fa658a98	317	u64 __iomem *udb;
cfdda9d7 SW	318	size_t memsize;
	319	u32 qid;
	320	u32 msn;
	321	u32 rqt_hwaddr;
	322	u16 rqt_size;
	323	u16 in_use;
	324	u16 size;
	325	u16 cidx;
	326	u16 pidx;
d37ac31d	327	u16 wq_pidx;
05eb2389	328	u16 wq_pidx_inc;
cfdda9d7 SW	329	};
	330
	331	struct t4_wq {
	332	struct t4_sq sq;
	333	struct t4_rq rq;
	334	void __iomem *db;
	335	void __iomem *gts;
	336	struct c4iw_rdev *rdev;
1cf24dce	337	int flushed;
cfdda9d7 SW	338	};
	339
	340	static inline int t4_rqes_posted(struct t4_wq *wq)
	341	{
	342	return wq->rq.in_use;
	343	}
	344
	345	static inline int t4_rq_empty(struct t4_wq *wq)
	346	{
	347	return wq->rq.in_use == 0;
	348	}
	349
	350	static inline int t4_rq_full(struct t4_wq *wq)
	351	{
	352	return wq->rq.in_use == (wq->rq.size - 1);
	353	}
	354
	355	static inline u32 t4_rq_avail(struct t4_wq *wq)
	356	{
	357	return wq->rq.size - 1 - wq->rq.in_use;
	358	}
	359
d37ac31d	360	static inline void t4_rq_produce(struct t4_wq *wq, u8 len16)
cfdda9d7 SW	361	{
	362	wq->rq.in_use++;
	363	if (++wq->rq.pidx == wq->rq.size)
	364	wq->rq.pidx = 0;
d37ac31d SW	365	wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
	366	if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS)
	367	wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS;
cfdda9d7 SW	368	}
	369
	370	static inline void t4_rq_consume(struct t4_wq *wq)
	371	{
	372	wq->rq.in_use--;
	373	wq->rq.msn++;
	374	if (++wq->rq.cidx == wq->rq.size)
	375	wq->rq.cidx = 0;
	376	}
	377
422eea0a VP	378	static inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq)
	379	{
	380	return wq->rq.queue[wq->rq.size].status.host_wq_pidx;
	381	}
	382
	383	static inline u16 t4_rq_wq_size(struct t4_wq *wq)
	384	{
	385	return wq->rq.size * T4_RQ_NUM_SLOTS;
	386	}
	387
c6d7b267 SW	388	static inline int t4_sq_onchip(struct t4_sq *sq)
	389	{
	390	return sq->flags & T4_SQ_ONCHIP;
	391	}
	392
cfdda9d7 SW	393	static inline int t4_sq_empty(struct t4_wq *wq)
	394	{
	395	return wq->sq.in_use == 0;
	396	}
	397
	398	static inline int t4_sq_full(struct t4_wq *wq)
	399	{
	400	return wq->sq.in_use == (wq->sq.size - 1);
	401	}
	402
	403	static inline u32 t4_sq_avail(struct t4_wq *wq)
	404	{
	405	return wq->sq.size - 1 - wq->sq.in_use;
	406	}
	407
d37ac31d	408	static inline void t4_sq_produce(struct t4_wq *wq, u8 len16)
cfdda9d7 SW	409	{
	410	wq->sq.in_use++;
	411	if (++wq->sq.pidx == wq->sq.size)
	412	wq->sq.pidx = 0;
d37ac31d SW	413	wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
	414	if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS)
	415	wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS;
cfdda9d7 SW	416	}
	417
	418	static inline void t4_sq_consume(struct t4_wq *wq)
	419	{
1cf24dce SW	420	BUG_ON(wq->sq.in_use < 1);
	421	if (wq->sq.cidx == wq->sq.flush_cidx)
	422	wq->sq.flush_cidx = -1;
cfdda9d7 SW	423	wq->sq.in_use--;
	424	if (++wq->sq.cidx == wq->sq.size)
	425	wq->sq.cidx = 0;
	426	}
	427
422eea0a VP	428	static inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq)
	429	{
	430	return wq->sq.queue[wq->sq.size].status.host_wq_pidx;
	431	}
	432
	433	static inline u16 t4_sq_wq_size(struct t4_wq *wq)
	434	{
	435	return wq->sq.size * T4_SQ_NUM_SLOTS;
	436	}
	437
fa658a98 SW	438	/* This function copies 64 byte coalesced work request to memory
	439	* mapped BAR2 space. For coalesced WRs, the SGE fetches data
	440	* from the FIFO instead of from Host.
	441	*/
	442	static inline void pio_copy(u64 __iomem dst, u64 src)
	443	{
	444	int count = 8;
	445
	446	while (count) {
	447	writeq(*src, dst);
	448	src++;
	449	dst++;
	450	count--;
	451	}
	452	}
	453
	454	static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, u8 t5,
	455	union t4_wr *wqe)
cfdda9d7	456	{
fa658a98 SW	457
fa658a98 SW	458	/* Flush host queue memory writes. */
cfdda9d7	459	wmb();
fa658a98 SW	460	if (t5) {
	461	if (inc == 1 && wqe) {
	462	PDBG("%s: WC wq->sq.pidx = %d\n",
	463	__func__, wq->sq.pidx);
	464	pio_copy(wq->sq.udb + 7, (void *)wqe);
	465	} else {
	466	PDBG("%s: DB wq->sq.pidx = %d\n",
	467	__func__, wq->sq.pidx);
f612b815	468	writel(PIDX_T5_V(inc), wq->sq.udb);
fa658a98 SW	469	}
	470
	471	/* Flush user doorbell area writes. */
	472	wmb();
	473	return;
	474	}
f612b815	475	writel(QID_V(wq->sq.qid) \| PIDX_V(inc), wq->db);
cfdda9d7 SW	476	}
cfdda9d7 SW	477
fa658a98 SW	478	static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc, u8 t5,
fa658a98 SW	479	union t4_recv_wr *wqe)
cfdda9d7	480	{
fa658a98 SW	481
fa658a98 SW	482	/* Flush host queue memory writes. */
cfdda9d7	483	wmb();
fa658a98 SW	484	if (t5) {
	485	if (inc == 1 && wqe) {
	486	PDBG("%s: WC wq->rq.pidx = %d\n",
	487	__func__, wq->rq.pidx);
	488	pio_copy(wq->rq.udb + 7, (void *)wqe);
	489	} else {
	490	PDBG("%s: DB wq->rq.pidx = %d\n",
	491	__func__, wq->rq.pidx);
f612b815	492	writel(PIDX_T5_V(inc), wq->rq.udb);
fa658a98 SW	493	}
	494
	495	/* Flush user doorbell area writes. */
	496	wmb();
	497	return;
	498	}
f612b815	499	writel(QID_V(wq->rq.qid) \| PIDX_V(inc), wq->db);
cfdda9d7 SW	500	}
	501
	502	static inline int t4_wq_in_error(struct t4_wq *wq)
	503	{
c6d7b267	504	return wq->rq.queue[wq->rq.size].status.qp_err;
cfdda9d7 SW	505	}
	506
	507	static inline void t4_set_wq_in_error(struct t4_wq *wq)
	508	{
cfdda9d7 SW	509	wq->rq.queue[wq->rq.size].status.qp_err = 1;
	510	}
	511
	512	static inline void t4_disable_wq_db(struct t4_wq *wq)
	513	{
cfdda9d7 SW	514	wq->rq.queue[wq->rq.size].status.db_off = 1;
	515	}
	516
	517	static inline void t4_enable_wq_db(struct t4_wq *wq)
	518	{
cfdda9d7 SW	519	wq->rq.queue[wq->rq.size].status.db_off = 0;
	520	}
	521
	522	static inline int t4_wq_db_enabled(struct t4_wq *wq)
	523	{
c6d7b267	524	return !wq->rq.queue[wq->rq.size].status.db_off;
cfdda9d7 SW	525	}
cfdda9d7 SW	526
678ea9b5 SW	527	enum t4_cq_flags {
	528	CQ_ARMED = 1,
	529	};
	530
cfdda9d7 SW	531	struct t4_cq {
	532	struct t4_cqe *queue;
	533	dma_addr_t dma_addr;
f38926aa	534	DEFINE_DMA_UNMAP_ADDR(mapping);
cfdda9d7 SW	535	struct t4_cqe *sw_queue;
	536	void __iomem *gts;
	537	struct c4iw_rdev *rdev;
	538	u64 ugts;
	539	size_t memsize;
84172dee	540	__be64 bits_type_ts;
cfdda9d7	541	u32 cqid;
09ece8b9	542	u32 qid_mask;
cf38be6d	543	int vector;
cfdda9d7 SW	544	u16 size; /* including status page */
	545	u16 cidx;
	546	u16 sw_pidx;
	547	u16 sw_cidx;
	548	u16 sw_in_use;
	549	u16 cidx_inc;
	550	u8 gen;
	551	u8 error;
678ea9b5	552	unsigned long flags;
cfdda9d7 SW	553	};
cfdda9d7 SW	554
678ea9b5 SW	555	static inline int t4_clear_cq_armed(struct t4_cq *cq)
	556	{
	557	return test_and_clear_bit(CQ_ARMED, &cq->flags);
	558	}
	559
cfdda9d7 SW	560	static inline int t4_arm_cq(struct t4_cq *cq, int se)
	561	{
	562	u32 val;
7ec45b92	563
678ea9b5	564	set_bit(CQ_ARMED, &cq->flags);
f612b815 HS	565	while (cq->cidx_inc > CIDXINC_M) {
f612b815 HS	566	val = SEINTARM_V(0) \| CIDXINC_V(CIDXINC_M) \| TIMERREG_V(7) \|
09ece8b9	567	INGRESSQID_V(cq->cqid & cq->qid_mask);
be4c9bad	568	writel(val, cq->gts);
f612b815	569	cq->cidx_inc -= CIDXINC_M;
7ec45b92	570	}
f612b815	571	val = SEINTARM_V(se) \| CIDXINC_V(cq->cidx_inc) \| TIMERREG_V(6) \|
09ece8b9	572	INGRESSQID_V(cq->cqid & cq->qid_mask);
7ec45b92 SW	573	writel(val, cq->gts);
7ec45b92 SW	574	cq->cidx_inc = 0;
cfdda9d7 SW	575	return 0;
	576	}
	577
	578	static inline void t4_swcq_produce(struct t4_cq *cq)
	579	{
	580	cq->sw_in_use++;
1cf24dce SW	581	if (cq->sw_in_use == cq->size) {
	582	PDBG("%s cxgb4 sw cq overflow cqid %u\n", __func__, cq->cqid);
	583	cq->error = 1;
	584	BUG_ON(1);
	585	}
cfdda9d7 SW	586	if (++cq->sw_pidx == cq->size)
	587	cq->sw_pidx = 0;
	588	}
	589
	590	static inline void t4_swcq_consume(struct t4_cq *cq)
	591	{
1cf24dce	592	BUG_ON(cq->sw_in_use < 1);
cfdda9d7 SW	593	cq->sw_in_use--;
	594	if (++cq->sw_cidx == cq->size)
	595	cq->sw_cidx = 0;
	596	}
	597
	598	static inline void t4_hwcq_consume(struct t4_cq *cq)
	599	{
84172dee	600	cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts;
f612b815	601	if (++cq->cidx_inc == (cq->size >> 4) \|\| cq->cidx_inc == CIDXINC_M) {
ffc3f748 SW	602	u32 val;
ffc3f748 SW	603
f612b815	604	val = SEINTARM_V(0) \| CIDXINC_V(cq->cidx_inc) \| TIMERREG_V(7) \|
09ece8b9	605	INGRESSQID_V(cq->cqid & cq->qid_mask);
ffc3f748	606	writel(val, cq->gts);
7ec45b92	607	cq->cidx_inc = 0;
ffc3f748	608	}
cfdda9d7 SW	609	if (++cq->cidx == cq->size) {
	610	cq->cidx = 0;
	611	cq->gen ^= 1;
	612	}
	613	}
	614
	615	static inline int t4_valid_cqe(struct t4_cq cq, struct t4_cqe cqe)
	616	{
	617	return (CQE_GENBIT(cqe) == cq->gen);
	618	}
	619
	620	static inline int t4_next_hw_cqe(struct t4_cq cq, struct t4_cqe *cqe)
	621	{
84172dee SW	622	int ret;
84172dee SW	623	u16 prev_cidx;
cfdda9d7	624
84172dee SW	625	if (cq->cidx == 0)
84172dee SW	626	prev_cidx = cq->size - 1;
cfdda9d7	627	else
84172dee SW	628	prev_cidx = cq->cidx - 1;
	629
	630	if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) {
	631	ret = -EOVERFLOW;
cfdda9d7	632	cq->error = 1;
84172dee	633	printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid);
1cf24dce	634	BUG_ON(1);
84172dee	635	} else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) {
def4771f SW	636
	637	/* Ensure CQE is flushed to memory */
	638	rmb();
84172dee SW	639	*cqe = &cq->queue[cq->cidx];
	640	ret = 0;
	641	} else
	642	ret = -ENODATA;
cfdda9d7 SW	643	return ret;
	644	}
	645
	646	static inline struct t4_cqe t4_next_sw_cqe(struct t4_cq cq)
	647	{
1cf24dce SW	648	if (cq->sw_in_use == cq->size) {
	649	PDBG("%s cxgb4 sw cq overflow cqid %u\n", __func__, cq->cqid);
	650	cq->error = 1;
	651	BUG_ON(1);
	652	return NULL;
	653	}
cfdda9d7 SW	654	if (cq->sw_in_use)
	655	return &cq->sw_queue[cq->sw_cidx];
	656	return NULL;
	657	}
	658
	659	static inline int t4_next_cqe(struct t4_cq cq, struct t4_cqe *cqe)
	660	{
	661	int ret = 0;
	662
	663	if (cq->error)
	664	ret = -ENODATA;
	665	else if (cq->sw_in_use)
	666	*cqe = &cq->sw_queue[cq->sw_cidx];
	667	else
	668	ret = t4_next_hw_cqe(cq, cqe);
	669	return ret;
	670	}
	671
	672	static inline int t4_cq_in_error(struct t4_cq *cq)
	673	{
	674	return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err;
	675	}
	676
	677	static inline void t4_set_cq_in_error(struct t4_cq *cq)
	678	{
	679	((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1;
	680	}
	681	#endif
05eb2389 SW	682
	683	struct t4_dev_status_page {
	684	u8 db_off;
	685	};