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IB/hfi1: Disable external device configuration requests
[mirror_ubuntu-jammy-kernel.git] / drivers / infiniband / hw / hfi1 / chip.c
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77241056 1/*
05d6ac1d 2 * Copyright(c) 2015, 2016 Intel Corporation.
77241056
MM		 3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
77241056
MM		 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * BSD LICENSE
19 *
77241056
MM		 20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 *
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
29 * distribution.
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 */
47
48/*
49 * This file contains all of the code that is specific to the HFI chip
50 */
51
52#include <linux/pci.h>
53#include <linux/delay.h>
54#include <linux/interrupt.h>
55#include <linux/module.h>
56
57#include "hfi.h"
58#include "trace.h"
59#include "mad.h"
60#include "pio.h"
61#include "sdma.h"
62#include "eprom.h"
5d9157aa 63#include "efivar.h"
8ebd4cf1 64#include "platform.h"
affa48de 65#include "aspm.h"
4197344b 66#include "affinity.h"
77241056
MM		 67
68#define NUM_IB_PORTS 1
69
70uint kdeth_qp;
71module_param_named(kdeth_qp, kdeth_qp, uint, S_IRUGO);
72MODULE_PARM_DESC(kdeth_qp, "Set the KDETH queue pair prefix");
73
74uint num_vls = HFI1_MAX_VLS_SUPPORTED;
75module_param(num_vls, uint, S_IRUGO);
76MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
77
78/*
79 * Default time to aggregate two 10K packets from the idle state
80 * (timer not running). The timer starts at the end of the first packet,
81 * so only the time for one 10K packet and header plus a bit extra is needed.
82 * 10 * 1024 + 64 header byte = 10304 byte
83 * 10304 byte / 12.5 GB/s = 824.32ns
84 */
85uint rcv_intr_timeout = (824 + 16); /* 16 is for coalescing interrupt */
86module_param(rcv_intr_timeout, uint, S_IRUGO);
87MODULE_PARM_DESC(rcv_intr_timeout, "Receive interrupt mitigation timeout in ns");
88
89uint rcv_intr_count = 16; /* same as qib */
90module_param(rcv_intr_count, uint, S_IRUGO);
91MODULE_PARM_DESC(rcv_intr_count, "Receive interrupt mitigation count");
92
93ushort link_crc_mask = SUPPORTED_CRCS;
94module_param(link_crc_mask, ushort, S_IRUGO);
95MODULE_PARM_DESC(link_crc_mask, "CRCs to use on the link");
96
97uint loopback;
98module_param_named(loopback, loopback, uint, S_IRUGO);
99MODULE_PARM_DESC(loopback, "Put into loopback mode (1 = serdes, 3 = external cable");
100
101/* Other driver tunables */
102uint rcv_intr_dynamic = 1; /* enable dynamic mode for rcv int mitigation*/
103static ushort crc_14b_sideband = 1;
104static uint use_flr = 1;
105uint quick_linkup; /* skip LNI */
106
107struct flag_table {
108 u64 flag; /* the flag */
109 char *str; /* description string */
110 u16 extra; /* extra information */
111 u16 unused0;
112 u32 unused1;
113};
114
115/* str must be a string constant */
116#define FLAG_ENTRY(str, extra, flag) {flag, str, extra}
117#define FLAG_ENTRY0(str, flag) {flag, str, 0}
118
119/* Send Error Consequences */
120#define SEC_WRITE_DROPPED 0x1
121#define SEC_PACKET_DROPPED 0x2
122#define SEC_SC_HALTED 0x4 /* per-context only */
123#define SEC_SPC_FREEZE 0x8 /* per-HFI only */
124
8784ac02 125#define DEFAULT_KRCVQS 2
77241056 126#define MIN_KERNEL_KCTXTS 2
82c2611d 127#define FIRST_KERNEL_KCTXT 1
372cc85a
DL		 128/* sizes for both the QP and RSM map tables */
129#define NUM_MAP_ENTRIES 256
77241056
MM		 130#define NUM_MAP_REGS 32
131
132/* Bit offset into the GUID which carries HFI id information */
133#define GUID_HFI_INDEX_SHIFT 39
134
135/* extract the emulation revision */
136#define emulator_rev(dd) ((dd)->irev >> 8)
137/* parallel and serial emulation versions are 3 and 4 respectively */
138#define is_emulator_p(dd) ((((dd)->irev) & 0xf) == 3)
139#define is_emulator_s(dd) ((((dd)->irev) & 0xf) == 4)
140
141/* RSM fields */
142
143/* packet type */
144#define IB_PACKET_TYPE 2ull
145#define QW_SHIFT 6ull
146/* QPN[7..1] */
147#define QPN_WIDTH 7ull
148
149/* LRH.BTH: QW 0, OFFSET 48 - for match */
150#define LRH_BTH_QW 0ull
151#define LRH_BTH_BIT_OFFSET 48ull
152#define LRH_BTH_OFFSET(off) ((LRH_BTH_QW << QW_SHIFT) | (off))
153#define LRH_BTH_MATCH_OFFSET LRH_BTH_OFFSET(LRH_BTH_BIT_OFFSET)
154#define LRH_BTH_SELECT
155#define LRH_BTH_MASK 3ull
156#define LRH_BTH_VALUE 2ull
157
158/* LRH.SC[3..0] QW 0, OFFSET 56 - for match */
159#define LRH_SC_QW 0ull
160#define LRH_SC_BIT_OFFSET 56ull
161#define LRH_SC_OFFSET(off) ((LRH_SC_QW << QW_SHIFT) | (off))
162#define LRH_SC_MATCH_OFFSET LRH_SC_OFFSET(LRH_SC_BIT_OFFSET)
163#define LRH_SC_MASK 128ull
164#define LRH_SC_VALUE 0ull
165
166/* SC[n..0] QW 0, OFFSET 60 - for select */
167#define LRH_SC_SELECT_OFFSET ((LRH_SC_QW << QW_SHIFT) | (60ull))
168
169/* QPN[m+n:1] QW 1, OFFSET 1 */
170#define QPN_SELECT_OFFSET ((1ull << QW_SHIFT) | (1ull))
171
172/* defines to build power on SC2VL table */
173#define SC2VL_VAL( \
174 num, \
175 sc0, sc0val, \
176 sc1, sc1val, \
177 sc2, sc2val, \
178 sc3, sc3val, \
179 sc4, sc4val, \
180 sc5, sc5val, \
181 sc6, sc6val, \
182 sc7, sc7val) \
183( \
184 ((u64)(sc0val) << SEND_SC2VLT##num##_SC##sc0##_SHIFT) | \
185 ((u64)(sc1val) << SEND_SC2VLT##num##_SC##sc1##_SHIFT) | \
186 ((u64)(sc2val) << SEND_SC2VLT##num##_SC##sc2##_SHIFT) | \
187 ((u64)(sc3val) << SEND_SC2VLT##num##_SC##sc3##_SHIFT) | \
188 ((u64)(sc4val) << SEND_SC2VLT##num##_SC##sc4##_SHIFT) | \
189 ((u64)(sc5val) << SEND_SC2VLT##num##_SC##sc5##_SHIFT) | \
190 ((u64)(sc6val) << SEND_SC2VLT##num##_SC##sc6##_SHIFT) | \
191 ((u64)(sc7val) << SEND_SC2VLT##num##_SC##sc7##_SHIFT) \
192)
193
194#define DC_SC_VL_VAL( \
195 range, \
196 e0, e0val, \
197 e1, e1val, \
198 e2, e2val, \
199 e3, e3val, \
200 e4, e4val, \
201 e5, e5val, \
202 e6, e6val, \
203 e7, e7val, \
204 e8, e8val, \
205 e9, e9val, \
206 e10, e10val, \
207 e11, e11val, \
208 e12, e12val, \
209 e13, e13val, \
210 e14, e14val, \
211 e15, e15val) \
212( \
213 ((u64)(e0val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e0##_SHIFT) | \
214 ((u64)(e1val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e1##_SHIFT) | \
215 ((u64)(e2val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e2##_SHIFT) | \
216 ((u64)(e3val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e3##_SHIFT) | \
217 ((u64)(e4val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e4##_SHIFT) | \
218 ((u64)(e5val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e5##_SHIFT) | \
219 ((u64)(e6val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e6##_SHIFT) | \
220 ((u64)(e7val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e7##_SHIFT) | \
221 ((u64)(e8val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e8##_SHIFT) | \
222 ((u64)(e9val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e9##_SHIFT) | \
223 ((u64)(e10val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e10##_SHIFT) | \
224 ((u64)(e11val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e11##_SHIFT) | \
225 ((u64)(e12val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e12##_SHIFT) | \
226 ((u64)(e13val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e13##_SHIFT) | \
227 ((u64)(e14val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e14##_SHIFT) | \
228 ((u64)(e15val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e15##_SHIFT) \
229)
230
231/* all CceStatus sub-block freeze bits */
232#define ALL_FROZE (CCE_STATUS_SDMA_FROZE_SMASK \
233 | CCE_STATUS_RXE_FROZE_SMASK \
234 | CCE_STATUS_TXE_FROZE_SMASK \
235 | CCE_STATUS_TXE_PIO_FROZE_SMASK)
236/* all CceStatus sub-block TXE pause bits */
237#define ALL_TXE_PAUSE (CCE_STATUS_TXE_PIO_PAUSED_SMASK \
238 | CCE_STATUS_TXE_PAUSED_SMASK \
239 | CCE_STATUS_SDMA_PAUSED_SMASK)
240/* all CceStatus sub-block RXE pause bits */
241#define ALL_RXE_PAUSE CCE_STATUS_RXE_PAUSED_SMASK
242
2b719046
JP		 243#define CNTR_MAX 0xFFFFFFFFFFFFFFFFULL
244#define CNTR_32BIT_MAX 0x00000000FFFFFFFF
245
77241056
MM		 246/*
247 * CCE Error flags.
248 */
249static struct flag_table cce_err_status_flags[] = {
250/* 0*/ FLAG_ENTRY0("CceCsrParityErr",
251 CCE_ERR_STATUS_CCE_CSR_PARITY_ERR_SMASK),
252/* 1*/ FLAG_ENTRY0("CceCsrReadBadAddrErr",
253 CCE_ERR_STATUS_CCE_CSR_READ_BAD_ADDR_ERR_SMASK),
254/* 2*/ FLAG_ENTRY0("CceCsrWriteBadAddrErr",
255 CCE_ERR_STATUS_CCE_CSR_WRITE_BAD_ADDR_ERR_SMASK),
256/* 3*/ FLAG_ENTRY0("CceTrgtAsyncFifoParityErr",
257 CCE_ERR_STATUS_CCE_TRGT_ASYNC_FIFO_PARITY_ERR_SMASK),
258/* 4*/ FLAG_ENTRY0("CceTrgtAccessErr",
259 CCE_ERR_STATUS_CCE_TRGT_ACCESS_ERR_SMASK),
260/* 5*/ FLAG_ENTRY0("CceRspdDataParityErr",
261 CCE_ERR_STATUS_CCE_RSPD_DATA_PARITY_ERR_SMASK),
262/* 6*/ FLAG_ENTRY0("CceCli0AsyncFifoParityErr",
263 CCE_ERR_STATUS_CCE_CLI0_ASYNC_FIFO_PARITY_ERR_SMASK),
264/* 7*/ FLAG_ENTRY0("CceCsrCfgBusParityErr",
265 CCE_ERR_STATUS_CCE_CSR_CFG_BUS_PARITY_ERR_SMASK),
266/* 8*/ FLAG_ENTRY0("CceCli2AsyncFifoParityErr",
267 CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK),
268/* 9*/ FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr",
269 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR_SMASK),
270/*10*/ FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr",
271 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR_SMASK),
272/*11*/ FLAG_ENTRY0("CceCli1AsyncFifoRxdmaParityError",
273 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERROR_SMASK),
274/*12*/ FLAG_ENTRY0("CceCli1AsyncFifoDbgParityError",
275 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERROR_SMASK),
276/*13*/ FLAG_ENTRY0("PcicRetryMemCorErr",
277 CCE_ERR_STATUS_PCIC_RETRY_MEM_COR_ERR_SMASK),
278/*14*/ FLAG_ENTRY0("PcicRetryMemCorErr",
279 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_COR_ERR_SMASK),
280/*15*/ FLAG_ENTRY0("PcicPostHdQCorErr",
281 CCE_ERR_STATUS_PCIC_POST_HD_QCOR_ERR_SMASK),
282/*16*/ FLAG_ENTRY0("PcicPostHdQCorErr",
283 CCE_ERR_STATUS_PCIC_POST_DAT_QCOR_ERR_SMASK),
284/*17*/ FLAG_ENTRY0("PcicPostHdQCorErr",
285 CCE_ERR_STATUS_PCIC_CPL_HD_QCOR_ERR_SMASK),
286/*18*/ FLAG_ENTRY0("PcicCplDatQCorErr",
287 CCE_ERR_STATUS_PCIC_CPL_DAT_QCOR_ERR_SMASK),
288/*19*/ FLAG_ENTRY0("PcicNPostHQParityErr",
289 CCE_ERR_STATUS_PCIC_NPOST_HQ_PARITY_ERR_SMASK),
290/*20*/ FLAG_ENTRY0("PcicNPostDatQParityErr",
291 CCE_ERR_STATUS_PCIC_NPOST_DAT_QPARITY_ERR_SMASK),
292/*21*/ FLAG_ENTRY0("PcicRetryMemUncErr",
293 CCE_ERR_STATUS_PCIC_RETRY_MEM_UNC_ERR_SMASK),
294/*22*/ FLAG_ENTRY0("PcicRetrySotMemUncErr",
295 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_UNC_ERR_SMASK),
296/*23*/ FLAG_ENTRY0("PcicPostHdQUncErr",
297 CCE_ERR_STATUS_PCIC_POST_HD_QUNC_ERR_SMASK),
298/*24*/ FLAG_ENTRY0("PcicPostDatQUncErr",
299 CCE_ERR_STATUS_PCIC_POST_DAT_QUNC_ERR_SMASK),
300/*25*/ FLAG_ENTRY0("PcicCplHdQUncErr",
301 CCE_ERR_STATUS_PCIC_CPL_HD_QUNC_ERR_SMASK),
302/*26*/ FLAG_ENTRY0("PcicCplDatQUncErr",
303 CCE_ERR_STATUS_PCIC_CPL_DAT_QUNC_ERR_SMASK),
304/*27*/ FLAG_ENTRY0("PcicTransmitFrontParityErr",
305 CCE_ERR_STATUS_PCIC_TRANSMIT_FRONT_PARITY_ERR_SMASK),
306/*28*/ FLAG_ENTRY0("PcicTransmitBackParityErr",
307 CCE_ERR_STATUS_PCIC_TRANSMIT_BACK_PARITY_ERR_SMASK),
308/*29*/ FLAG_ENTRY0("PcicReceiveParityErr",
309 CCE_ERR_STATUS_PCIC_RECEIVE_PARITY_ERR_SMASK),
310/*30*/ FLAG_ENTRY0("CceTrgtCplTimeoutErr",
311 CCE_ERR_STATUS_CCE_TRGT_CPL_TIMEOUT_ERR_SMASK),
312/*31*/ FLAG_ENTRY0("LATriggered",
313 CCE_ERR_STATUS_LA_TRIGGERED_SMASK),
314/*32*/ FLAG_ENTRY0("CceSegReadBadAddrErr",
315 CCE_ERR_STATUS_CCE_SEG_READ_BAD_ADDR_ERR_SMASK),
316/*33*/ FLAG_ENTRY0("CceSegWriteBadAddrErr",
317 CCE_ERR_STATUS_CCE_SEG_WRITE_BAD_ADDR_ERR_SMASK),
318/*34*/ FLAG_ENTRY0("CceRcplAsyncFifoParityErr",
319 CCE_ERR_STATUS_CCE_RCPL_ASYNC_FIFO_PARITY_ERR_SMASK),
320/*35*/ FLAG_ENTRY0("CceRxdmaConvFifoParityErr",
321 CCE_ERR_STATUS_CCE_RXDMA_CONV_FIFO_PARITY_ERR_SMASK),
322/*36*/ FLAG_ENTRY0("CceMsixTableCorErr",
323 CCE_ERR_STATUS_CCE_MSIX_TABLE_COR_ERR_SMASK),
324/*37*/ FLAG_ENTRY0("CceMsixTableUncErr",
325 CCE_ERR_STATUS_CCE_MSIX_TABLE_UNC_ERR_SMASK),
326/*38*/ FLAG_ENTRY0("CceIntMapCorErr",
327 CCE_ERR_STATUS_CCE_INT_MAP_COR_ERR_SMASK),
328/*39*/ FLAG_ENTRY0("CceIntMapUncErr",
329 CCE_ERR_STATUS_CCE_INT_MAP_UNC_ERR_SMASK),
330/*40*/ FLAG_ENTRY0("CceMsixCsrParityErr",
331 CCE_ERR_STATUS_CCE_MSIX_CSR_PARITY_ERR_SMASK),
332/*41-63 reserved*/
333};
334
335/*
336 * Misc Error flags
337 */
338#define MES(text) MISC_ERR_STATUS_MISC_##text##_ERR_SMASK
339static struct flag_table misc_err_status_flags[] = {
340/* 0*/ FLAG_ENTRY0("CSR_PARITY", MES(CSR_PARITY)),
341/* 1*/ FLAG_ENTRY0("CSR_READ_BAD_ADDR", MES(CSR_READ_BAD_ADDR)),
342/* 2*/ FLAG_ENTRY0("CSR_WRITE_BAD_ADDR", MES(CSR_WRITE_BAD_ADDR)),
343/* 3*/ FLAG_ENTRY0("SBUS_WRITE_FAILED", MES(SBUS_WRITE_FAILED)),
344/* 4*/ FLAG_ENTRY0("KEY_MISMATCH", MES(KEY_MISMATCH)),
345/* 5*/ FLAG_ENTRY0("FW_AUTH_FAILED", MES(FW_AUTH_FAILED)),
346/* 6*/ FLAG_ENTRY0("EFUSE_CSR_PARITY", MES(EFUSE_CSR_PARITY)),
347/* 7*/ FLAG_ENTRY0("EFUSE_READ_BAD_ADDR", MES(EFUSE_READ_BAD_ADDR)),
348/* 8*/ FLAG_ENTRY0("EFUSE_WRITE", MES(EFUSE_WRITE)),
349/* 9*/ FLAG_ENTRY0("EFUSE_DONE_PARITY", MES(EFUSE_DONE_PARITY)),
350/*10*/ FLAG_ENTRY0("INVALID_EEP_CMD", MES(INVALID_EEP_CMD)),
351/*11*/ FLAG_ENTRY0("MBIST_FAIL", MES(MBIST_FAIL)),
352/*12*/ FLAG_ENTRY0("PLL_LOCK_FAIL", MES(PLL_LOCK_FAIL))
353};
354
355/*
356 * TXE PIO Error flags and consequences
357 */
358static struct flag_table pio_err_status_flags[] = {
359/* 0*/ FLAG_ENTRY("PioWriteBadCtxt",
360 SEC_WRITE_DROPPED,
361 SEND_PIO_ERR_STATUS_PIO_WRITE_BAD_CTXT_ERR_SMASK),
362/* 1*/ FLAG_ENTRY("PioWriteAddrParity",
363 SEC_SPC_FREEZE,
364 SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK),
365/* 2*/ FLAG_ENTRY("PioCsrParity",
366 SEC_SPC_FREEZE,
367 SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK),
368/* 3*/ FLAG_ENTRY("PioSbMemFifo0",
369 SEC_SPC_FREEZE,
370 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK),
371/* 4*/ FLAG_ENTRY("PioSbMemFifo1",
372 SEC_SPC_FREEZE,
373 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK),
374/* 5*/ FLAG_ENTRY("PioPccFifoParity",
375 SEC_SPC_FREEZE,
376 SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK),
377/* 6*/ FLAG_ENTRY("PioPecFifoParity",
378 SEC_SPC_FREEZE,
379 SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK),
380/* 7*/ FLAG_ENTRY("PioSbrdctlCrrelParity",
381 SEC_SPC_FREEZE,
382 SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK),
383/* 8*/ FLAG_ENTRY("PioSbrdctrlCrrelFifoParity",
384 SEC_SPC_FREEZE,
385 SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK),
386/* 9*/ FLAG_ENTRY("PioPktEvictFifoParityErr",
387 SEC_SPC_FREEZE,
388 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK),
389/*10*/ FLAG_ENTRY("PioSmPktResetParity",
390 SEC_SPC_FREEZE,
391 SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK),
392/*11*/ FLAG_ENTRY("PioVlLenMemBank0Unc",
393 SEC_SPC_FREEZE,
394 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK),
395/*12*/ FLAG_ENTRY("PioVlLenMemBank1Unc",
396 SEC_SPC_FREEZE,
397 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK),
398/*13*/ FLAG_ENTRY("PioVlLenMemBank0Cor",
399 0,
400 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_COR_ERR_SMASK),
401/*14*/ FLAG_ENTRY("PioVlLenMemBank1Cor",
402 0,
403 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_COR_ERR_SMASK),
404/*15*/ FLAG_ENTRY("PioCreditRetFifoParity",
405 SEC_SPC_FREEZE,
406 SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK),
407/*16*/ FLAG_ENTRY("PioPpmcPblFifo",
408 SEC_SPC_FREEZE,
409 SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK),
410/*17*/ FLAG_ENTRY("PioInitSmIn",
411 0,
412 SEND_PIO_ERR_STATUS_PIO_INIT_SM_IN_ERR_SMASK),
413/*18*/ FLAG_ENTRY("PioPktEvictSmOrArbSm",
414 SEC_SPC_FREEZE,
415 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK),
416/*19*/ FLAG_ENTRY("PioHostAddrMemUnc",
417 SEC_SPC_FREEZE,
418 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK),
419/*20*/ FLAG_ENTRY("PioHostAddrMemCor",
420 0,
421 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_COR_ERR_SMASK),
422/*21*/ FLAG_ENTRY("PioWriteDataParity",
423 SEC_SPC_FREEZE,
424 SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK),
425/*22*/ FLAG_ENTRY("PioStateMachine",
426 SEC_SPC_FREEZE,
427 SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK),
428/*23*/ FLAG_ENTRY("PioWriteQwValidParity",
8638b77f 429 SEC_WRITE_DROPPED | SEC_SPC_FREEZE,
77241056
MM		 430 SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK),
431/*24*/ FLAG_ENTRY("PioBlockQwCountParity",
8638b77f 432 SEC_WRITE_DROPPED | SEC_SPC_FREEZE,
77241056
MM		 433 SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK),
434/*25*/ FLAG_ENTRY("PioVlfVlLenParity",
435 SEC_SPC_FREEZE,
436 SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK),
437/*26*/ FLAG_ENTRY("PioVlfSopParity",
438 SEC_SPC_FREEZE,
439 SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK),
440/*27*/ FLAG_ENTRY("PioVlFifoParity",
441 SEC_SPC_FREEZE,
442 SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK),
443/*28*/ FLAG_ENTRY("PioPpmcBqcMemParity",
444 SEC_SPC_FREEZE,
445 SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK),
446/*29*/ FLAG_ENTRY("PioPpmcSopLen",
447 SEC_SPC_FREEZE,
448 SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK),
449/*30-31 reserved*/
450/*32*/ FLAG_ENTRY("PioCurrentFreeCntParity",
451 SEC_SPC_FREEZE,
452 SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK),
453/*33*/ FLAG_ENTRY("PioLastReturnedCntParity",
454 SEC_SPC_FREEZE,
455 SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK),
456/*34*/ FLAG_ENTRY("PioPccSopHeadParity",
457 SEC_SPC_FREEZE,
458 SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK),
459/*35*/ FLAG_ENTRY("PioPecSopHeadParityErr",
460 SEC_SPC_FREEZE,
461 SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK),
462/*36-63 reserved*/
463};
464
465/* TXE PIO errors that cause an SPC freeze */
466#define ALL_PIO_FREEZE_ERR \
467 (SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK \
468 | SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK \
469 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK \
470 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK \
471 | SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK \
472 | SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK \
473 | SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK \
474 | SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK \
475 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK \
476 | SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK \
477 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK \
478 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK \
479 | SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK \
480 | SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK \
481 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK \
482 | SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK \
483 | SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK \
484 | SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK \
485 | SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK \
486 | SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK \
487 | SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK \
488 | SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK \
489 | SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK \
490 | SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK \
491 | SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK \
492 | SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK \
493 | SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK \
494 | SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK \
495 | SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK)
496
497/*
498 * TXE SDMA Error flags
499 */
500static struct flag_table sdma_err_status_flags[] = {
501/* 0*/ FLAG_ENTRY0("SDmaRpyTagErr",
502 SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK),
503/* 1*/ FLAG_ENTRY0("SDmaCsrParityErr",
504 SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK),
505/* 2*/ FLAG_ENTRY0("SDmaPcieReqTrackingUncErr",
506 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK),
507/* 3*/ FLAG_ENTRY0("SDmaPcieReqTrackingCorErr",
508 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_COR_ERR_SMASK),
509/*04-63 reserved*/
510};
511
512/* TXE SDMA errors that cause an SPC freeze */
513#define ALL_SDMA_FREEZE_ERR \
514 (SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK \
515 | SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK \
516 | SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK)
517
69a00b8e
MM		 518/* SendEgressErrInfo bits that correspond to a PortXmitDiscard counter */
519#define PORT_DISCARD_EGRESS_ERRS \
520 (SEND_EGRESS_ERR_INFO_TOO_LONG_IB_PACKET_ERR_SMASK \
521 | SEND_EGRESS_ERR_INFO_VL_MAPPING_ERR_SMASK \
522 | SEND_EGRESS_ERR_INFO_VL_ERR_SMASK)
523
77241056
MM		 524/*
525 * TXE Egress Error flags
526 */
527#define SEES(text) SEND_EGRESS_ERR_STATUS_##text##_ERR_SMASK
528static struct flag_table egress_err_status_flags[] = {
529/* 0*/ FLAG_ENTRY0("TxPktIntegrityMemCorErr", SEES(TX_PKT_INTEGRITY_MEM_COR)),
530/* 1*/ FLAG_ENTRY0("TxPktIntegrityMemUncErr", SEES(TX_PKT_INTEGRITY_MEM_UNC)),
531/* 2 reserved */
532/* 3*/ FLAG_ENTRY0("TxEgressFifoUnderrunOrParityErr",
533 SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY)),
534/* 4*/ FLAG_ENTRY0("TxLinkdownErr", SEES(TX_LINKDOWN)),
535/* 5*/ FLAG_ENTRY0("TxIncorrectLinkStateErr", SEES(TX_INCORRECT_LINK_STATE)),
536/* 6 reserved */
537/* 7*/ FLAG_ENTRY0("TxPioLaunchIntfParityErr",
538 SEES(TX_PIO_LAUNCH_INTF_PARITY)),
539/* 8*/ FLAG_ENTRY0("TxSdmaLaunchIntfParityErr",
540 SEES(TX_SDMA_LAUNCH_INTF_PARITY)),
541/* 9-10 reserved */
542/*11*/ FLAG_ENTRY0("TxSbrdCtlStateMachineParityErr",
543 SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY)),
544/*12*/ FLAG_ENTRY0("TxIllegalVLErr", SEES(TX_ILLEGAL_VL)),
545/*13*/ FLAG_ENTRY0("TxLaunchCsrParityErr", SEES(TX_LAUNCH_CSR_PARITY)),
546/*14*/ FLAG_ENTRY0("TxSbrdCtlCsrParityErr", SEES(TX_SBRD_CTL_CSR_PARITY)),
547/*15*/ FLAG_ENTRY0("TxConfigParityErr", SEES(TX_CONFIG_PARITY)),
548/*16*/ FLAG_ENTRY0("TxSdma0DisallowedPacketErr",
549 SEES(TX_SDMA0_DISALLOWED_PACKET)),
550/*17*/ FLAG_ENTRY0("TxSdma1DisallowedPacketErr",
551 SEES(TX_SDMA1_DISALLOWED_PACKET)),
552/*18*/ FLAG_ENTRY0("TxSdma2DisallowedPacketErr",
553 SEES(TX_SDMA2_DISALLOWED_PACKET)),
554/*19*/ FLAG_ENTRY0("TxSdma3DisallowedPacketErr",
555 SEES(TX_SDMA3_DISALLOWED_PACKET)),
556/*20*/ FLAG_ENTRY0("TxSdma4DisallowedPacketErr",
557 SEES(TX_SDMA4_DISALLOWED_PACKET)),
558/*21*/ FLAG_ENTRY0("TxSdma5DisallowedPacketErr",
559 SEES(TX_SDMA5_DISALLOWED_PACKET)),
560/*22*/ FLAG_ENTRY0("TxSdma6DisallowedPacketErr",
561 SEES(TX_SDMA6_DISALLOWED_PACKET)),
562/*23*/ FLAG_ENTRY0("TxSdma7DisallowedPacketErr",
563 SEES(TX_SDMA7_DISALLOWED_PACKET)),
564/*24*/ FLAG_ENTRY0("TxSdma8DisallowedPacketErr",
565 SEES(TX_SDMA8_DISALLOWED_PACKET)),
566/*25*/ FLAG_ENTRY0("TxSdma9DisallowedPacketErr",
567 SEES(TX_SDMA9_DISALLOWED_PACKET)),
568/*26*/ FLAG_ENTRY0("TxSdma10DisallowedPacketErr",
569 SEES(TX_SDMA10_DISALLOWED_PACKET)),
570/*27*/ FLAG_ENTRY0("TxSdma11DisallowedPacketErr",
571 SEES(TX_SDMA11_DISALLOWED_PACKET)),
572/*28*/ FLAG_ENTRY0("TxSdma12DisallowedPacketErr",
573 SEES(TX_SDMA12_DISALLOWED_PACKET)),
574/*29*/ FLAG_ENTRY0("TxSdma13DisallowedPacketErr",
575 SEES(TX_SDMA13_DISALLOWED_PACKET)),
576/*30*/ FLAG_ENTRY0("TxSdma14DisallowedPacketErr",
577 SEES(TX_SDMA14_DISALLOWED_PACKET)),
578/*31*/ FLAG_ENTRY0("TxSdma15DisallowedPacketErr",
579 SEES(TX_SDMA15_DISALLOWED_PACKET)),
580/*32*/ FLAG_ENTRY0("TxLaunchFifo0UncOrParityErr",
581 SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY)),
582/*33*/ FLAG_ENTRY0("TxLaunchFifo1UncOrParityErr",
583 SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY)),
584/*34*/ FLAG_ENTRY0("TxLaunchFifo2UncOrParityErr",
585 SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY)),
586/*35*/ FLAG_ENTRY0("TxLaunchFifo3UncOrParityErr",
587 SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY)),
588/*36*/ FLAG_ENTRY0("TxLaunchFifo4UncOrParityErr",
589 SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY)),
590/*37*/ FLAG_ENTRY0("TxLaunchFifo5UncOrParityErr",
591 SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY)),
592/*38*/ FLAG_ENTRY0("TxLaunchFifo6UncOrParityErr",
593 SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY)),
594/*39*/ FLAG_ENTRY0("TxLaunchFifo7UncOrParityErr",
595 SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY)),
596/*40*/ FLAG_ENTRY0("TxLaunchFifo8UncOrParityErr",
597 SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY)),
598/*41*/ FLAG_ENTRY0("TxCreditReturnParityErr", SEES(TX_CREDIT_RETURN_PARITY)),
599/*42*/ FLAG_ENTRY0("TxSbHdrUncErr", SEES(TX_SB_HDR_UNC)),
600/*43*/ FLAG_ENTRY0("TxReadSdmaMemoryUncErr", SEES(TX_READ_SDMA_MEMORY_UNC)),
601/*44*/ FLAG_ENTRY0("TxReadPioMemoryUncErr", SEES(TX_READ_PIO_MEMORY_UNC)),
602/*45*/ FLAG_ENTRY0("TxEgressFifoUncErr", SEES(TX_EGRESS_FIFO_UNC)),
603/*46*/ FLAG_ENTRY0("TxHcrcInsertionErr", SEES(TX_HCRC_INSERTION)),
604/*47*/ FLAG_ENTRY0("TxCreditReturnVLErr", SEES(TX_CREDIT_RETURN_VL)),
605/*48*/ FLAG_ENTRY0("TxLaunchFifo0CorErr", SEES(TX_LAUNCH_FIFO0_COR)),
606/*49*/ FLAG_ENTRY0("TxLaunchFifo1CorErr", SEES(TX_LAUNCH_FIFO1_COR)),
607/*50*/ FLAG_ENTRY0("TxLaunchFifo2CorErr", SEES(TX_LAUNCH_FIFO2_COR)),
608/*51*/ FLAG_ENTRY0("TxLaunchFifo3CorErr", SEES(TX_LAUNCH_FIFO3_COR)),
609/*52*/ FLAG_ENTRY0("TxLaunchFifo4CorErr", SEES(TX_LAUNCH_FIFO4_COR)),
610/*53*/ FLAG_ENTRY0("TxLaunchFifo5CorErr", SEES(TX_LAUNCH_FIFO5_COR)),
611/*54*/ FLAG_ENTRY0("TxLaunchFifo6CorErr", SEES(TX_LAUNCH_FIFO6_COR)),
612/*55*/ FLAG_ENTRY0("TxLaunchFifo7CorErr", SEES(TX_LAUNCH_FIFO7_COR)),
613/*56*/ FLAG_ENTRY0("TxLaunchFifo8CorErr", SEES(TX_LAUNCH_FIFO8_COR)),
614/*57*/ FLAG_ENTRY0("TxCreditOverrunErr", SEES(TX_CREDIT_OVERRUN)),
615/*58*/ FLAG_ENTRY0("TxSbHdrCorErr", SEES(TX_SB_HDR_COR)),
616/*59*/ FLAG_ENTRY0("TxReadSdmaMemoryCorErr", SEES(TX_READ_SDMA_MEMORY_COR)),
617/*60*/ FLAG_ENTRY0("TxReadPioMemoryCorErr", SEES(TX_READ_PIO_MEMORY_COR)),
618/*61*/ FLAG_ENTRY0("TxEgressFifoCorErr", SEES(TX_EGRESS_FIFO_COR)),
619/*62*/ FLAG_ENTRY0("TxReadSdmaMemoryCsrUncErr",
620 SEES(TX_READ_SDMA_MEMORY_CSR_UNC)),
621/*63*/ FLAG_ENTRY0("TxReadPioMemoryCsrUncErr",
622 SEES(TX_READ_PIO_MEMORY_CSR_UNC)),
623};
624
625/*
626 * TXE Egress Error Info flags
627 */
628#define SEEI(text) SEND_EGRESS_ERR_INFO_##text##_ERR_SMASK
629static struct flag_table egress_err_info_flags[] = {
630/* 0*/ FLAG_ENTRY0("Reserved", 0ull),
631/* 1*/ FLAG_ENTRY0("VLErr", SEEI(VL)),
632/* 2*/ FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)),
633/* 3*/ FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)),
634/* 4*/ FLAG_ENTRY0("PartitionKeyErr", SEEI(PARTITION_KEY)),
635/* 5*/ FLAG_ENTRY0("SLIDErr", SEEI(SLID)),
636/* 6*/ FLAG_ENTRY0("OpcodeErr", SEEI(OPCODE)),
637/* 7*/ FLAG_ENTRY0("VLMappingErr", SEEI(VL_MAPPING)),
638/* 8*/ FLAG_ENTRY0("RawErr", SEEI(RAW)),
639/* 9*/ FLAG_ENTRY0("RawIPv6Err", SEEI(RAW_IPV6)),
640/*10*/ FLAG_ENTRY0("GRHErr", SEEI(GRH)),
641/*11*/ FLAG_ENTRY0("BypassErr", SEEI(BYPASS)),
642/*12*/ FLAG_ENTRY0("KDETHPacketsErr", SEEI(KDETH_PACKETS)),
643/*13*/ FLAG_ENTRY0("NonKDETHPacketsErr", SEEI(NON_KDETH_PACKETS)),
644/*14*/ FLAG_ENTRY0("TooSmallIBPacketsErr", SEEI(TOO_SMALL_IB_PACKETS)),
645/*15*/ FLAG_ENTRY0("TooSmallBypassPacketsErr", SEEI(TOO_SMALL_BYPASS_PACKETS)),
646/*16*/ FLAG_ENTRY0("PbcTestErr", SEEI(PBC_TEST)),
647/*17*/ FLAG_ENTRY0("BadPktLenErr", SEEI(BAD_PKT_LEN)),
648/*18*/ FLAG_ENTRY0("TooLongIBPacketErr", SEEI(TOO_LONG_IB_PACKET)),
649/*19*/ FLAG_ENTRY0("TooLongBypassPacketsErr", SEEI(TOO_LONG_BYPASS_PACKETS)),
650/*20*/ FLAG_ENTRY0("PbcStaticRateControlErr", SEEI(PBC_STATIC_RATE_CONTROL)),
651/*21*/ FLAG_ENTRY0("BypassBadPktLenErr", SEEI(BAD_PKT_LEN)),
652};
653
654/* TXE Egress errors that cause an SPC freeze */
655#define ALL_TXE_EGRESS_FREEZE_ERR \
656 (SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY) \
657 | SEES(TX_PIO_LAUNCH_INTF_PARITY) \
658 | SEES(TX_SDMA_LAUNCH_INTF_PARITY) \
659 | SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY) \
660 | SEES(TX_LAUNCH_CSR_PARITY) \
661 | SEES(TX_SBRD_CTL_CSR_PARITY) \
662 | SEES(TX_CONFIG_PARITY) \
663 | SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY) \
664 | SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY) \
665 | SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY) \
666 | SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY) \
667 | SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY) \
668 | SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY) \
669 | SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY) \
670 | SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY) \
671 | SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY) \
672 | SEES(TX_CREDIT_RETURN_PARITY))
673
674/*
675 * TXE Send error flags
676 */
677#define SES(name) SEND_ERR_STATUS_SEND_##name##_ERR_SMASK
678static struct flag_table send_err_status_flags[] = {
2c5b521a 679/* 0*/ FLAG_ENTRY0("SendCsrParityErr", SES(CSR_PARITY)),
77241056
MM		 680/* 1*/ FLAG_ENTRY0("SendCsrReadBadAddrErr", SES(CSR_READ_BAD_ADDR)),
681/* 2*/ FLAG_ENTRY0("SendCsrWriteBadAddrErr", SES(CSR_WRITE_BAD_ADDR))
682};
683
684/*
685 * TXE Send Context Error flags and consequences
686 */
687static struct flag_table sc_err_status_flags[] = {
688/* 0*/ FLAG_ENTRY("InconsistentSop",
689 SEC_PACKET_DROPPED | SEC_SC_HALTED,
690 SEND_CTXT_ERR_STATUS_PIO_INCONSISTENT_SOP_ERR_SMASK),
691/* 1*/ FLAG_ENTRY("DisallowedPacket",
692 SEC_PACKET_DROPPED | SEC_SC_HALTED,
693 SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK),
694/* 2*/ FLAG_ENTRY("WriteCrossesBoundary",
695 SEC_WRITE_DROPPED | SEC_SC_HALTED,
696 SEND_CTXT_ERR_STATUS_PIO_WRITE_CROSSES_BOUNDARY_ERR_SMASK),
697/* 3*/ FLAG_ENTRY("WriteOverflow",
698 SEC_WRITE_DROPPED | SEC_SC_HALTED,
699 SEND_CTXT_ERR_STATUS_PIO_WRITE_OVERFLOW_ERR_SMASK),
700/* 4*/ FLAG_ENTRY("WriteOutOfBounds",
701 SEC_WRITE_DROPPED | SEC_SC_HALTED,
702 SEND_CTXT_ERR_STATUS_PIO_WRITE_OUT_OF_BOUNDS_ERR_SMASK),
703/* 5-63 reserved*/
704};
705
706/*
707 * RXE Receive Error flags
708 */
709#define RXES(name) RCV_ERR_STATUS_RX_##name##_ERR_SMASK
710static struct flag_table rxe_err_status_flags[] = {
711/* 0*/ FLAG_ENTRY0("RxDmaCsrCorErr", RXES(DMA_CSR_COR)),
712/* 1*/ FLAG_ENTRY0("RxDcIntfParityErr", RXES(DC_INTF_PARITY)),
713/* 2*/ FLAG_ENTRY0("RxRcvHdrUncErr", RXES(RCV_HDR_UNC)),
714/* 3*/ FLAG_ENTRY0("RxRcvHdrCorErr", RXES(RCV_HDR_COR)),
715/* 4*/ FLAG_ENTRY0("RxRcvDataUncErr", RXES(RCV_DATA_UNC)),
716/* 5*/ FLAG_ENTRY0("RxRcvDataCorErr", RXES(RCV_DATA_COR)),
717/* 6*/ FLAG_ENTRY0("RxRcvQpMapTableUncErr", RXES(RCV_QP_MAP_TABLE_UNC)),
718/* 7*/ FLAG_ENTRY0("RxRcvQpMapTableCorErr", RXES(RCV_QP_MAP_TABLE_COR)),
719/* 8*/ FLAG_ENTRY0("RxRcvCsrParityErr", RXES(RCV_CSR_PARITY)),
720/* 9*/ FLAG_ENTRY0("RxDcSopEopParityErr", RXES(DC_SOP_EOP_PARITY)),
721/*10*/ FLAG_ENTRY0("RxDmaFlagUncErr", RXES(DMA_FLAG_UNC)),
722/*11*/ FLAG_ENTRY0("RxDmaFlagCorErr", RXES(DMA_FLAG_COR)),
723/*12*/ FLAG_ENTRY0("RxRcvFsmEncodingErr", RXES(RCV_FSM_ENCODING)),
724/*13*/ FLAG_ENTRY0("RxRbufFreeListUncErr", RXES(RBUF_FREE_LIST_UNC)),
725/*14*/ FLAG_ENTRY0("RxRbufFreeListCorErr", RXES(RBUF_FREE_LIST_COR)),
726/*15*/ FLAG_ENTRY0("RxRbufLookupDesRegUncErr", RXES(RBUF_LOOKUP_DES_REG_UNC)),
727/*16*/ FLAG_ENTRY0("RxRbufLookupDesRegUncCorErr",
728 RXES(RBUF_LOOKUP_DES_REG_UNC_COR)),
729/*17*/ FLAG_ENTRY0("RxRbufLookupDesUncErr", RXES(RBUF_LOOKUP_DES_UNC)),
730/*18*/ FLAG_ENTRY0("RxRbufLookupDesCorErr", RXES(RBUF_LOOKUP_DES_COR)),
731/*19*/ FLAG_ENTRY0("RxRbufBlockListReadUncErr",
732 RXES(RBUF_BLOCK_LIST_READ_UNC)),
733/*20*/ FLAG_ENTRY0("RxRbufBlockListReadCorErr",
734 RXES(RBUF_BLOCK_LIST_READ_COR)),
735/*21*/ FLAG_ENTRY0("RxRbufCsrQHeadBufNumParityErr",
736 RXES(RBUF_CSR_QHEAD_BUF_NUM_PARITY)),
737/*22*/ FLAG_ENTRY0("RxRbufCsrQEntCntParityErr",
738 RXES(RBUF_CSR_QENT_CNT_PARITY)),
739/*23*/ FLAG_ENTRY0("RxRbufCsrQNextBufParityErr",
740 RXES(RBUF_CSR_QNEXT_BUF_PARITY)),
741/*24*/ FLAG_ENTRY0("RxRbufCsrQVldBitParityErr",
742 RXES(RBUF_CSR_QVLD_BIT_PARITY)),
743/*25*/ FLAG_ENTRY0("RxRbufCsrQHdPtrParityErr", RXES(RBUF_CSR_QHD_PTR_PARITY)),
744/*26*/ FLAG_ENTRY0("RxRbufCsrQTlPtrParityErr", RXES(RBUF_CSR_QTL_PTR_PARITY)),
745/*27*/ FLAG_ENTRY0("RxRbufCsrQNumOfPktParityErr",
746 RXES(RBUF_CSR_QNUM_OF_PKT_PARITY)),
747/*28*/ FLAG_ENTRY0("RxRbufCsrQEOPDWParityErr", RXES(RBUF_CSR_QEOPDW_PARITY)),
748/*29*/ FLAG_ENTRY0("RxRbufCtxIdParityErr", RXES(RBUF_CTX_ID_PARITY)),
749/*30*/ FLAG_ENTRY0("RxRBufBadLookupErr", RXES(RBUF_BAD_LOOKUP)),
750/*31*/ FLAG_ENTRY0("RxRbufFullErr", RXES(RBUF_FULL)),
751/*32*/ FLAG_ENTRY0("RxRbufEmptyErr", RXES(RBUF_EMPTY)),
752/*33*/ FLAG_ENTRY0("RxRbufFlRdAddrParityErr", RXES(RBUF_FL_RD_ADDR_PARITY)),
753/*34*/ FLAG_ENTRY0("RxRbufFlWrAddrParityErr", RXES(RBUF_FL_WR_ADDR_PARITY)),
754/*35*/ FLAG_ENTRY0("RxRbufFlInitdoneParityErr",
755 RXES(RBUF_FL_INITDONE_PARITY)),
756/*36*/ FLAG_ENTRY0("RxRbufFlInitWrAddrParityErr",
757 RXES(RBUF_FL_INIT_WR_ADDR_PARITY)),
758/*37*/ FLAG_ENTRY0("RxRbufNextFreeBufUncErr", RXES(RBUF_NEXT_FREE_BUF_UNC)),
759/*38*/ FLAG_ENTRY0("RxRbufNextFreeBufCorErr", RXES(RBUF_NEXT_FREE_BUF_COR)),
760/*39*/ FLAG_ENTRY0("RxLookupDesPart1UncErr", RXES(LOOKUP_DES_PART1_UNC)),
761/*40*/ FLAG_ENTRY0("RxLookupDesPart1UncCorErr",
762 RXES(LOOKUP_DES_PART1_UNC_COR)),
763/*41*/ FLAG_ENTRY0("RxLookupDesPart2ParityErr",
764 RXES(LOOKUP_DES_PART2_PARITY)),
765/*42*/ FLAG_ENTRY0("RxLookupRcvArrayUncErr", RXES(LOOKUP_RCV_ARRAY_UNC)),
766/*43*/ FLAG_ENTRY0("RxLookupRcvArrayCorErr", RXES(LOOKUP_RCV_ARRAY_COR)),
767/*44*/ FLAG_ENTRY0("RxLookupCsrParityErr", RXES(LOOKUP_CSR_PARITY)),
768/*45*/ FLAG_ENTRY0("RxHqIntrCsrParityErr", RXES(HQ_INTR_CSR_PARITY)),
769/*46*/ FLAG_ENTRY0("RxHqIntrFsmErr", RXES(HQ_INTR_FSM)),
770/*47*/ FLAG_ENTRY0("RxRbufDescPart1UncErr", RXES(RBUF_DESC_PART1_UNC)),
771/*48*/ FLAG_ENTRY0("RxRbufDescPart1CorErr", RXES(RBUF_DESC_PART1_COR)),
772/*49*/ FLAG_ENTRY0("RxRbufDescPart2UncErr", RXES(RBUF_DESC_PART2_UNC)),
773/*50*/ FLAG_ENTRY0("RxRbufDescPart2CorErr", RXES(RBUF_DESC_PART2_COR)),
774/*51*/ FLAG_ENTRY0("RxDmaHdrFifoRdUncErr", RXES(DMA_HDR_FIFO_RD_UNC)),
775/*52*/ FLAG_ENTRY0("RxDmaHdrFifoRdCorErr", RXES(DMA_HDR_FIFO_RD_COR)),
776/*53*/ FLAG_ENTRY0("RxDmaDataFifoRdUncErr", RXES(DMA_DATA_FIFO_RD_UNC)),
777/*54*/ FLAG_ENTRY0("RxDmaDataFifoRdCorErr", RXES(DMA_DATA_FIFO_RD_COR)),
778/*55*/ FLAG_ENTRY0("RxRbufDataUncErr", RXES(RBUF_DATA_UNC)),
779/*56*/ FLAG_ENTRY0("RxRbufDataCorErr", RXES(RBUF_DATA_COR)),
780/*57*/ FLAG_ENTRY0("RxDmaCsrParityErr", RXES(DMA_CSR_PARITY)),
781/*58*/ FLAG_ENTRY0("RxDmaEqFsmEncodingErr", RXES(DMA_EQ_FSM_ENCODING)),
782/*59*/ FLAG_ENTRY0("RxDmaDqFsmEncodingErr", RXES(DMA_DQ_FSM_ENCODING)),
783/*60*/ FLAG_ENTRY0("RxDmaCsrUncErr", RXES(DMA_CSR_UNC)),
784/*61*/ FLAG_ENTRY0("RxCsrReadBadAddrErr", RXES(CSR_READ_BAD_ADDR)),
785/*62*/ FLAG_ENTRY0("RxCsrWriteBadAddrErr", RXES(CSR_WRITE_BAD_ADDR)),
786/*63*/ FLAG_ENTRY0("RxCsrParityErr", RXES(CSR_PARITY))
787};
788
789/* RXE errors that will trigger an SPC freeze */
790#define ALL_RXE_FREEZE_ERR \
791 (RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_UNC_ERR_SMASK \
792 | RCV_ERR_STATUS_RX_RCV_CSR_PARITY_ERR_SMASK \
793 | RCV_ERR_STATUS_RX_DMA_FLAG_UNC_ERR_SMASK \
794 | RCV_ERR_STATUS_RX_RCV_FSM_ENCODING_ERR_SMASK \
795 | RCV_ERR_STATUS_RX_RBUF_FREE_LIST_UNC_ERR_SMASK \
796 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_ERR_SMASK \
797 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR_SMASK \
798 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_UNC_ERR_SMASK \
799 | RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_UNC_ERR_SMASK \
800 | RCV_ERR_STATUS_RX_RBUF_CSR_QHEAD_BUF_NUM_PARITY_ERR_SMASK \
801 | RCV_ERR_STATUS_RX_RBUF_CSR_QENT_CNT_PARITY_ERR_SMASK \
802 | RCV_ERR_STATUS_RX_RBUF_CSR_QNEXT_BUF_PARITY_ERR_SMASK \
803 | RCV_ERR_STATUS_RX_RBUF_CSR_QVLD_BIT_PARITY_ERR_SMASK \
804 | RCV_ERR_STATUS_RX_RBUF_CSR_QHD_PTR_PARITY_ERR_SMASK \
805 | RCV_ERR_STATUS_RX_RBUF_CSR_QTL_PTR_PARITY_ERR_SMASK \
806 | RCV_ERR_STATUS_RX_RBUF_CSR_QNUM_OF_PKT_PARITY_ERR_SMASK \
807 | RCV_ERR_STATUS_RX_RBUF_CSR_QEOPDW_PARITY_ERR_SMASK \
808 | RCV_ERR_STATUS_RX_RBUF_CTX_ID_PARITY_ERR_SMASK \
809 | RCV_ERR_STATUS_RX_RBUF_BAD_LOOKUP_ERR_SMASK \
810 | RCV_ERR_STATUS_RX_RBUF_FULL_ERR_SMASK \
811 | RCV_ERR_STATUS_RX_RBUF_EMPTY_ERR_SMASK \
812 | RCV_ERR_STATUS_RX_RBUF_FL_RD_ADDR_PARITY_ERR_SMASK \
813 | RCV_ERR_STATUS_RX_RBUF_FL_WR_ADDR_PARITY_ERR_SMASK \
814 | RCV_ERR_STATUS_RX_RBUF_FL_INITDONE_PARITY_ERR_SMASK \
815 | RCV_ERR_STATUS_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR_SMASK \
816 | RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_UNC_ERR_SMASK \
817 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_ERR_SMASK \
818 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_COR_ERR_SMASK \
819 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART2_PARITY_ERR_SMASK \
820 | RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_UNC_ERR_SMASK \
821 | RCV_ERR_STATUS_RX_LOOKUP_CSR_PARITY_ERR_SMASK \
822 | RCV_ERR_STATUS_RX_HQ_INTR_CSR_PARITY_ERR_SMASK \
823 | RCV_ERR_STATUS_RX_HQ_INTR_FSM_ERR_SMASK \
824 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_UNC_ERR_SMASK \
825 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_COR_ERR_SMASK \
826 | RCV_ERR_STATUS_RX_RBUF_DESC_PART2_UNC_ERR_SMASK \
827 | RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK \
828 | RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK \
829 | RCV_ERR_STATUS_RX_RBUF_DATA_UNC_ERR_SMASK \
830 | RCV_ERR_STATUS_RX_DMA_CSR_PARITY_ERR_SMASK \
831 | RCV_ERR_STATUS_RX_DMA_EQ_FSM_ENCODING_ERR_SMASK \
832 | RCV_ERR_STATUS_RX_DMA_DQ_FSM_ENCODING_ERR_SMASK \
833 | RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK \
834 | RCV_ERR_STATUS_RX_CSR_PARITY_ERR_SMASK)
835
836#define RXE_FREEZE_ABORT_MASK \
837 (RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK | \
838 RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK | \
839 RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK)
840
841/*
842 * DCC Error Flags
843 */
844#define DCCE(name) DCC_ERR_FLG_##name##_SMASK
845static struct flag_table dcc_err_flags[] = {
846 FLAG_ENTRY0("bad_l2_err", DCCE(BAD_L2_ERR)),
847 FLAG_ENTRY0("bad_sc_err", DCCE(BAD_SC_ERR)),
848 FLAG_ENTRY0("bad_mid_tail_err", DCCE(BAD_MID_TAIL_ERR)),
849 FLAG_ENTRY0("bad_preemption_err", DCCE(BAD_PREEMPTION_ERR)),
850 FLAG_ENTRY0("preemption_err", DCCE(PREEMPTION_ERR)),
851 FLAG_ENTRY0("preemptionvl15_err", DCCE(PREEMPTIONVL15_ERR)),
852 FLAG_ENTRY0("bad_vl_marker_err", DCCE(BAD_VL_MARKER_ERR)),
853 FLAG_ENTRY0("bad_dlid_target_err", DCCE(BAD_DLID_TARGET_ERR)),
854 FLAG_ENTRY0("bad_lver_err", DCCE(BAD_LVER_ERR)),
855 FLAG_ENTRY0("uncorrectable_err", DCCE(UNCORRECTABLE_ERR)),
856 FLAG_ENTRY0("bad_crdt_ack_err", DCCE(BAD_CRDT_ACK_ERR)),
857 FLAG_ENTRY0("unsup_pkt_type", DCCE(UNSUP_PKT_TYPE)),
858 FLAG_ENTRY0("bad_ctrl_flit_err", DCCE(BAD_CTRL_FLIT_ERR)),
859 FLAG_ENTRY0("event_cntr_parity_err", DCCE(EVENT_CNTR_PARITY_ERR)),
860 FLAG_ENTRY0("event_cntr_rollover_err", DCCE(EVENT_CNTR_ROLLOVER_ERR)),
861 FLAG_ENTRY0("link_err", DCCE(LINK_ERR)),
862 FLAG_ENTRY0("misc_cntr_rollover_err", DCCE(MISC_CNTR_ROLLOVER_ERR)),
863 FLAG_ENTRY0("bad_ctrl_dist_err", DCCE(BAD_CTRL_DIST_ERR)),
864 FLAG_ENTRY0("bad_tail_dist_err", DCCE(BAD_TAIL_DIST_ERR)),
865 FLAG_ENTRY0("bad_head_dist_err", DCCE(BAD_HEAD_DIST_ERR)),
866 FLAG_ENTRY0("nonvl15_state_err", DCCE(NONVL15_STATE_ERR)),
867 FLAG_ENTRY0("vl15_multi_err", DCCE(VL15_MULTI_ERR)),
868 FLAG_ENTRY0("bad_pkt_length_err", DCCE(BAD_PKT_LENGTH_ERR)),
869 FLAG_ENTRY0("unsup_vl_err", DCCE(UNSUP_VL_ERR)),
870 FLAG_ENTRY0("perm_nvl15_err", DCCE(PERM_NVL15_ERR)),
871 FLAG_ENTRY0("slid_zero_err", DCCE(SLID_ZERO_ERR)),
872 FLAG_ENTRY0("dlid_zero_err", DCCE(DLID_ZERO_ERR)),
873 FLAG_ENTRY0("length_mtu_err", DCCE(LENGTH_MTU_ERR)),
874 FLAG_ENTRY0("rx_early_drop_err", DCCE(RX_EARLY_DROP_ERR)),
875 FLAG_ENTRY0("late_short_err", DCCE(LATE_SHORT_ERR)),
876 FLAG_ENTRY0("late_long_err", DCCE(LATE_LONG_ERR)),
877 FLAG_ENTRY0("late_ebp_err", DCCE(LATE_EBP_ERR)),
878 FLAG_ENTRY0("fpe_tx_fifo_ovflw_err", DCCE(FPE_TX_FIFO_OVFLW_ERR)),
879 FLAG_ENTRY0("fpe_tx_fifo_unflw_err", DCCE(FPE_TX_FIFO_UNFLW_ERR)),
880 FLAG_ENTRY0("csr_access_blocked_host", DCCE(CSR_ACCESS_BLOCKED_HOST)),
881 FLAG_ENTRY0("csr_access_blocked_uc", DCCE(CSR_ACCESS_BLOCKED_UC)),
882 FLAG_ENTRY0("tx_ctrl_parity_err", DCCE(TX_CTRL_PARITY_ERR)),
883 FLAG_ENTRY0("tx_ctrl_parity_mbe_err", DCCE(TX_CTRL_PARITY_MBE_ERR)),
884 FLAG_ENTRY0("tx_sc_parity_err", DCCE(TX_SC_PARITY_ERR)),
885 FLAG_ENTRY0("rx_ctrl_parity_mbe_err", DCCE(RX_CTRL_PARITY_MBE_ERR)),
886 FLAG_ENTRY0("csr_parity_err", DCCE(CSR_PARITY_ERR)),
887 FLAG_ENTRY0("csr_inval_addr", DCCE(CSR_INVAL_ADDR)),
888 FLAG_ENTRY0("tx_byte_shft_parity_err", DCCE(TX_BYTE_SHFT_PARITY_ERR)),
889 FLAG_ENTRY0("rx_byte_shft_parity_err", DCCE(RX_BYTE_SHFT_PARITY_ERR)),
890 FLAG_ENTRY0("fmconfig_err", DCCE(FMCONFIG_ERR)),
891 FLAG_ENTRY0("rcvport_err", DCCE(RCVPORT_ERR)),
892};
893
894/*
895 * LCB error flags
896 */
897#define LCBE(name) DC_LCB_ERR_FLG_##name##_SMASK
898static struct flag_table lcb_err_flags[] = {
899/* 0*/ FLAG_ENTRY0("CSR_PARITY_ERR", LCBE(CSR_PARITY_ERR)),
900/* 1*/ FLAG_ENTRY0("INVALID_CSR_ADDR", LCBE(INVALID_CSR_ADDR)),
901/* 2*/ FLAG_ENTRY0("RST_FOR_FAILED_DESKEW", LCBE(RST_FOR_FAILED_DESKEW)),
902/* 3*/ FLAG_ENTRY0("ALL_LNS_FAILED_REINIT_TEST",
903 LCBE(ALL_LNS_FAILED_REINIT_TEST)),
904/* 4*/ FLAG_ENTRY0("LOST_REINIT_STALL_OR_TOS", LCBE(LOST_REINIT_STALL_OR_TOS)),
905/* 5*/ FLAG_ENTRY0("TX_LESS_THAN_FOUR_LNS", LCBE(TX_LESS_THAN_FOUR_LNS)),
906/* 6*/ FLAG_ENTRY0("RX_LESS_THAN_FOUR_LNS", LCBE(RX_LESS_THAN_FOUR_LNS)),
907/* 7*/ FLAG_ENTRY0("SEQ_CRC_ERR", LCBE(SEQ_CRC_ERR)),
908/* 8*/ FLAG_ENTRY0("REINIT_FROM_PEER", LCBE(REINIT_FROM_PEER)),
909/* 9*/ FLAG_ENTRY0("REINIT_FOR_LN_DEGRADE", LCBE(REINIT_FOR_LN_DEGRADE)),
910/*10*/ FLAG_ENTRY0("CRC_ERR_CNT_HIT_LIMIT", LCBE(CRC_ERR_CNT_HIT_LIMIT)),
911/*11*/ FLAG_ENTRY0("RCLK_STOPPED", LCBE(RCLK_STOPPED)),
912/*12*/ FLAG_ENTRY0("UNEXPECTED_REPLAY_MARKER", LCBE(UNEXPECTED_REPLAY_MARKER)),
913/*13*/ FLAG_ENTRY0("UNEXPECTED_ROUND_TRIP_MARKER",
914 LCBE(UNEXPECTED_ROUND_TRIP_MARKER)),
915/*14*/ FLAG_ENTRY0("ILLEGAL_NULL_LTP", LCBE(ILLEGAL_NULL_LTP)),
916/*15*/ FLAG_ENTRY0("ILLEGAL_FLIT_ENCODING", LCBE(ILLEGAL_FLIT_ENCODING)),
917/*16*/ FLAG_ENTRY0("FLIT_INPUT_BUF_OFLW", LCBE(FLIT_INPUT_BUF_OFLW)),
918/*17*/ FLAG_ENTRY0("VL_ACK_INPUT_BUF_OFLW", LCBE(VL_ACK_INPUT_BUF_OFLW)),
919/*18*/ FLAG_ENTRY0("VL_ACK_INPUT_PARITY_ERR", LCBE(VL_ACK_INPUT_PARITY_ERR)),
920/*19*/ FLAG_ENTRY0("VL_ACK_INPUT_WRONG_CRC_MODE",
921 LCBE(VL_ACK_INPUT_WRONG_CRC_MODE)),
922/*20*/ FLAG_ENTRY0("FLIT_INPUT_BUF_MBE", LCBE(FLIT_INPUT_BUF_MBE)),
923/*21*/ FLAG_ENTRY0("FLIT_INPUT_BUF_SBE", LCBE(FLIT_INPUT_BUF_SBE)),
924/*22*/ FLAG_ENTRY0("REPLAY_BUF_MBE", LCBE(REPLAY_BUF_MBE)),
925/*23*/ FLAG_ENTRY0("REPLAY_BUF_SBE", LCBE(REPLAY_BUF_SBE)),
926/*24*/ FLAG_ENTRY0("CREDIT_RETURN_FLIT_MBE", LCBE(CREDIT_RETURN_FLIT_MBE)),
927/*25*/ FLAG_ENTRY0("RST_FOR_LINK_TIMEOUT", LCBE(RST_FOR_LINK_TIMEOUT)),
928/*26*/ FLAG_ENTRY0("RST_FOR_INCOMPLT_RND_TRIP",
929 LCBE(RST_FOR_INCOMPLT_RND_TRIP)),
930/*27*/ FLAG_ENTRY0("HOLD_REINIT", LCBE(HOLD_REINIT)),
931/*28*/ FLAG_ENTRY0("NEG_EDGE_LINK_TRANSFER_ACTIVE",
932 LCBE(NEG_EDGE_LINK_TRANSFER_ACTIVE)),
933/*29*/ FLAG_ENTRY0("REDUNDANT_FLIT_PARITY_ERR",
934 LCBE(REDUNDANT_FLIT_PARITY_ERR))
935};
936
937/*
938 * DC8051 Error Flags
939 */
940#define D8E(name) DC_DC8051_ERR_FLG_##name##_SMASK
941static struct flag_table dc8051_err_flags[] = {
942 FLAG_ENTRY0("SET_BY_8051", D8E(SET_BY_8051)),
943 FLAG_ENTRY0("LOST_8051_HEART_BEAT", D8E(LOST_8051_HEART_BEAT)),
944 FLAG_ENTRY0("CRAM_MBE", D8E(CRAM_MBE)),
945 FLAG_ENTRY0("CRAM_SBE", D8E(CRAM_SBE)),
946 FLAG_ENTRY0("DRAM_MBE", D8E(DRAM_MBE)),
947 FLAG_ENTRY0("DRAM_SBE", D8E(DRAM_SBE)),
948 FLAG_ENTRY0("IRAM_MBE", D8E(IRAM_MBE)),
949 FLAG_ENTRY0("IRAM_SBE", D8E(IRAM_SBE)),
950 FLAG_ENTRY0("UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES",
17fb4f29 951 D8E(UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES)),
77241056
MM		 952 FLAG_ENTRY0("INVALID_CSR_ADDR", D8E(INVALID_CSR_ADDR)),
953};
954
955/*
956 * DC8051 Information Error flags
957 *
958 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.ERROR field.
959 */
960static struct flag_table dc8051_info_err_flags[] = {
961 FLAG_ENTRY0("Spico ROM check failed", SPICO_ROM_FAILED),
962 FLAG_ENTRY0("Unknown frame received", UNKNOWN_FRAME),
963 FLAG_ENTRY0("Target BER not met", TARGET_BER_NOT_MET),
964 FLAG_ENTRY0("Serdes internal loopback failure",
17fb4f29 965 FAILED_SERDES_INTERNAL_LOOPBACK),
77241056
MM		 966 FLAG_ENTRY0("Failed SerDes init", FAILED_SERDES_INIT),
967 FLAG_ENTRY0("Failed LNI(Polling)", FAILED_LNI_POLLING),
968 FLAG_ENTRY0("Failed LNI(Debounce)", FAILED_LNI_DEBOUNCE),
969 FLAG_ENTRY0("Failed LNI(EstbComm)", FAILED_LNI_ESTBCOMM),
970 FLAG_ENTRY0("Failed LNI(OptEq)", FAILED_LNI_OPTEQ),
971 FLAG_ENTRY0("Failed LNI(VerifyCap_1)", FAILED_LNI_VERIFY_CAP1),
972 FLAG_ENTRY0("Failed LNI(VerifyCap_2)", FAILED_LNI_VERIFY_CAP2),
8fefef12
JJ		 973 FLAG_ENTRY0("Failed LNI(ConfigLT)", FAILED_LNI_CONFIGLT),
974 FLAG_ENTRY0("Host Handshake Timeout", HOST_HANDSHAKE_TIMEOUT)
77241056
MM		 975};
976
977/*
978 * DC8051 Information Host Information flags
979 *
980 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.HOST_MSG field.
981 */
982static struct flag_table dc8051_info_host_msg_flags[] = {
983 FLAG_ENTRY0("Host request done", 0x0001),
984 FLAG_ENTRY0("BC SMA message", 0x0002),
985 FLAG_ENTRY0("BC PWR_MGM message", 0x0004),
986 FLAG_ENTRY0("BC Unknown message (BCC)", 0x0008),
987 FLAG_ENTRY0("BC Unknown message (LCB)", 0x0010),
988 FLAG_ENTRY0("External device config request", 0x0020),
989 FLAG_ENTRY0("VerifyCap all frames received", 0x0040),
990 FLAG_ENTRY0("LinkUp achieved", 0x0080),
991 FLAG_ENTRY0("Link going down", 0x0100),
992};
993
77241056
MM		 994static u32 encoded_size(u32 size);
995static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate);
996static int set_physical_link_state(struct hfi1_devdata *dd, u64 state);
997static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management,
998 u8 *continuous);
999static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z,
1000 u8 *vcu, u16 *vl15buf, u8 *crc_sizes);
1001static void read_vc_remote_link_width(struct hfi1_devdata *dd,
1002 u8 *remote_tx_rate, u16 *link_widths);
1003static void read_vc_local_link_width(struct hfi1_devdata *dd, u8 *misc_bits,
1004 u8 *flag_bits, u16 *link_widths);
1005static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id,
1006 u8 *device_rev);
1007static void read_mgmt_allowed(struct hfi1_devdata *dd, u8 *mgmt_allowed);
1008static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx);
1009static int read_tx_settings(struct hfi1_devdata *dd, u8 *enable_lane_tx,
1010 u8 *tx_polarity_inversion,
1011 u8 *rx_polarity_inversion, u8 *max_rate);
1012static void handle_sdma_eng_err(struct hfi1_devdata *dd,
1013 unsigned int context, u64 err_status);
1014static void handle_qsfp_int(struct hfi1_devdata *dd, u32 source, u64 reg);
1015static void handle_dcc_err(struct hfi1_devdata *dd,
1016 unsigned int context, u64 err_status);
1017static void handle_lcb_err(struct hfi1_devdata *dd,
1018 unsigned int context, u64 err_status);
1019static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg);
1020static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1021static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1022static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1023static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1024static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1025static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1026static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1027static void set_partition_keys(struct hfi1_pportdata *);
1028static const char *link_state_name(u32 state);
1029static const char *link_state_reason_name(struct hfi1_pportdata *ppd,
1030 u32 state);
1031static int do_8051_command(struct hfi1_devdata *dd, u32 type, u64 in_data,
1032 u64 *out_data);
1033static int read_idle_sma(struct hfi1_devdata *dd, u64 *data);
1034static int thermal_init(struct hfi1_devdata *dd);
1035
1036static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state,
1037 int msecs);
1038static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc);
feb831dd 1039static void read_link_down_reason(struct hfi1_devdata *dd, u8 *ldr);
77241056
MM		 1040static void handle_temp_err(struct hfi1_devdata *);
1041static void dc_shutdown(struct hfi1_devdata *);
1042static void dc_start(struct hfi1_devdata *);
8f000f7f
DL		 1043static int qos_rmt_entries(struct hfi1_devdata *dd, unsigned int *mp,
1044 unsigned int *np);
3ec5fa28 1045static void clear_full_mgmt_pkey(struct hfi1_pportdata *ppd);
77241056
MM		 1046
1047/*
1048 * Error interrupt table entry. This is used as input to the interrupt
1049 * "clear down" routine used for all second tier error interrupt register.
1050 * Second tier interrupt registers have a single bit representing them
1051 * in the top-level CceIntStatus.
1052 */
1053struct err_reg_info {
1054 u32 status; /* status CSR offset */
1055 u32 clear; /* clear CSR offset */
1056 u32 mask; /* mask CSR offset */
1057 void (*handler)(struct hfi1_devdata *dd, u32 source, u64 reg);
1058 const char *desc;
1059};
1060
1061#define NUM_MISC_ERRS (IS_GENERAL_ERR_END - IS_GENERAL_ERR_START)
1062#define NUM_DC_ERRS (IS_DC_END - IS_DC_START)
1063#define NUM_VARIOUS (IS_VARIOUS_END - IS_VARIOUS_START)
1064
1065/*
1066 * Helpers for building HFI and DC error interrupt table entries. Different
1067 * helpers are needed because of inconsistent register names.
1068 */
1069#define EE(reg, handler, desc) \
1070 { reg##_STATUS, reg##_CLEAR, reg##_MASK, \
1071 handler, desc }
1072#define DC_EE1(reg, handler, desc) \
1073 { reg##_FLG, reg##_FLG_CLR, reg##_FLG_EN, handler, desc }
1074#define DC_EE2(reg, handler, desc) \
1075 { reg##_FLG, reg##_CLR, reg##_EN, handler, desc }
1076
1077/*
1078 * Table of the "misc" grouping of error interrupts. Each entry refers to
1079 * another register containing more information.
1080 */
1081static const struct err_reg_info misc_errs[NUM_MISC_ERRS] = {
1082/* 0*/ EE(CCE_ERR, handle_cce_err, "CceErr"),
1083/* 1*/ EE(RCV_ERR, handle_rxe_err, "RxeErr"),
1084/* 2*/ EE(MISC_ERR, handle_misc_err, "MiscErr"),
1085/* 3*/ { 0, 0, 0, NULL }, /* reserved */
1086/* 4*/ EE(SEND_PIO_ERR, handle_pio_err, "PioErr"),
1087/* 5*/ EE(SEND_DMA_ERR, handle_sdma_err, "SDmaErr"),
1088/* 6*/ EE(SEND_EGRESS_ERR, handle_egress_err, "EgressErr"),
1089/* 7*/ EE(SEND_ERR, handle_txe_err, "TxeErr")
1090 /* the rest are reserved */
1091};
1092
1093/*
1094 * Index into the Various section of the interrupt sources
1095 * corresponding to the Critical Temperature interrupt.
1096 */
1097#define TCRIT_INT_SOURCE 4
1098
1099/*
1100 * SDMA error interrupt entry - refers to another register containing more
1101 * information.
1102 */
1103static const struct err_reg_info sdma_eng_err =
1104 EE(SEND_DMA_ENG_ERR, handle_sdma_eng_err, "SDmaEngErr");
1105
1106static const struct err_reg_info various_err[NUM_VARIOUS] = {
1107/* 0*/ { 0, 0, 0, NULL }, /* PbcInt */
1108/* 1*/ { 0, 0, 0, NULL }, /* GpioAssertInt */
1109/* 2*/ EE(ASIC_QSFP1, handle_qsfp_int, "QSFP1"),
1110/* 3*/ EE(ASIC_QSFP2, handle_qsfp_int, "QSFP2"),
1111/* 4*/ { 0, 0, 0, NULL }, /* TCritInt */
1112 /* rest are reserved */
1113};
1114
1115/*
1116 * The DC encoding of mtu_cap for 10K MTU in the DCC_CFG_PORT_CONFIG
1117 * register can not be derived from the MTU value because 10K is not
1118 * a power of 2. Therefore, we need a constant. Everything else can
1119 * be calculated.
1120 */
1121#define DCC_CFG_PORT_MTU_CAP_10240 7
1122
1123/*
1124 * Table of the DC grouping of error interrupts. Each entry refers to
1125 * another register containing more information.
1126 */
1127static const struct err_reg_info dc_errs[NUM_DC_ERRS] = {
1128/* 0*/ DC_EE1(DCC_ERR, handle_dcc_err, "DCC Err"),
1129/* 1*/ DC_EE2(DC_LCB_ERR, handle_lcb_err, "LCB Err"),
1130/* 2*/ DC_EE2(DC_DC8051_ERR, handle_8051_interrupt, "DC8051 Interrupt"),
1131/* 3*/ /* dc_lbm_int - special, see is_dc_int() */
1132 /* the rest are reserved */
1133};
1134
1135struct cntr_entry {
1136 /*
1137 * counter name
1138 */
1139 char *name;
1140
1141 /*
1142 * csr to read for name (if applicable)
1143 */
1144 u64 csr;
1145
1146 /*
1147 * offset into dd or ppd to store the counter's value
1148 */
1149 int offset;
1150
1151 /*
1152 * flags
1153 */
1154 u8 flags;
1155
1156 /*
1157 * accessor for stat element, context either dd or ppd
1158 */
17fb4f29
JJ		 1159 u64 (*rw_cntr)(const struct cntr_entry *, void *context, int vl,
1160 int mode, u64 data);
77241056
MM		 1161};
1162
1163#define C_RCV_HDR_OVF_FIRST C_RCV_HDR_OVF_0
1164#define C_RCV_HDR_OVF_LAST C_RCV_HDR_OVF_159
1165
1166#define CNTR_ELEM(name, csr, offset, flags, accessor) \
1167{ \
1168 name, \
1169 csr, \
1170 offset, \
1171 flags, \
1172 accessor \
1173}
1174
1175/* 32bit RXE */
1176#define RXE32_PORT_CNTR_ELEM(name, counter, flags) \
1177CNTR_ELEM(#name, \
1178 (counter * 8 + RCV_COUNTER_ARRAY32), \
1179 0, flags | CNTR_32BIT, \
1180 port_access_u32_csr)
1181
1182#define RXE32_DEV_CNTR_ELEM(name, counter, flags) \
1183CNTR_ELEM(#name, \
1184 (counter * 8 + RCV_COUNTER_ARRAY32), \
1185 0, flags | CNTR_32BIT, \
1186 dev_access_u32_csr)
1187
1188/* 64bit RXE */
1189#define RXE64_PORT_CNTR_ELEM(name, counter, flags) \
1190CNTR_ELEM(#name, \
1191 (counter * 8 + RCV_COUNTER_ARRAY64), \
1192 0, flags, \
1193 port_access_u64_csr)
1194
1195#define RXE64_DEV_CNTR_ELEM(name, counter, flags) \
1196CNTR_ELEM(#name, \
1197 (counter * 8 + RCV_COUNTER_ARRAY64), \
1198 0, flags, \
1199 dev_access_u64_csr)
1200
1201#define OVR_LBL(ctx) C_RCV_HDR_OVF_ ## ctx
1202#define OVR_ELM(ctx) \
1203CNTR_ELEM("RcvHdrOvr" #ctx, \
8638b77f 1204 (RCV_HDR_OVFL_CNT + ctx * 0x100), \
77241056
MM		 1205 0, CNTR_NORMAL, port_access_u64_csr)
1206
1207/* 32bit TXE */
1208#define TXE32_PORT_CNTR_ELEM(name, counter, flags) \
1209CNTR_ELEM(#name, \
1210 (counter * 8 + SEND_COUNTER_ARRAY32), \
1211 0, flags | CNTR_32BIT, \
1212 port_access_u32_csr)
1213
1214/* 64bit TXE */
1215#define TXE64_PORT_CNTR_ELEM(name, counter, flags) \
1216CNTR_ELEM(#name, \
1217 (counter * 8 + SEND_COUNTER_ARRAY64), \
1218 0, flags, \
1219 port_access_u64_csr)
1220
1221# define TX64_DEV_CNTR_ELEM(name, counter, flags) \
1222CNTR_ELEM(#name,\
1223 counter * 8 + SEND_COUNTER_ARRAY64, \
1224 0, \
1225 flags, \
1226 dev_access_u64_csr)
1227
1228/* CCE */
1229#define CCE_PERF_DEV_CNTR_ELEM(name, counter, flags) \
1230CNTR_ELEM(#name, \
1231 (counter * 8 + CCE_COUNTER_ARRAY32), \
1232 0, flags | CNTR_32BIT, \
1233 dev_access_u32_csr)
1234
1235#define CCE_INT_DEV_CNTR_ELEM(name, counter, flags) \
1236CNTR_ELEM(#name, \
1237 (counter * 8 + CCE_INT_COUNTER_ARRAY32), \
1238 0, flags | CNTR_32BIT, \
1239 dev_access_u32_csr)
1240
1241/* DC */
1242#define DC_PERF_CNTR(name, counter, flags) \
1243CNTR_ELEM(#name, \
1244 counter, \
1245 0, \
1246 flags, \
1247 dev_access_u64_csr)
1248
1249#define DC_PERF_CNTR_LCB(name, counter, flags) \
1250CNTR_ELEM(#name, \
1251 counter, \
1252 0, \
1253 flags, \
1254 dc_access_lcb_cntr)
1255
1256/* ibp counters */
1257#define SW_IBP_CNTR(name, cntr) \
1258CNTR_ELEM(#name, \
1259 0, \
1260 0, \
1261 CNTR_SYNTH, \
1262 access_ibp_##cntr)
1263
1264u64 read_csr(const struct hfi1_devdata *dd, u32 offset)
1265{
77241056 1266 if (dd->flags & HFI1_PRESENT) {
6d210eef 1267 return readq((void __iomem *)dd->kregbase + offset);
77241056
MM		 1268 }
1269 return -1;
1270}
1271
1272void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value)
1273{
1274 if (dd->flags & HFI1_PRESENT)
1275 writeq(value, (void __iomem *)dd->kregbase + offset);
1276}
1277
1278void __iomem *get_csr_addr(
1279 struct hfi1_devdata *dd,
1280 u32 offset)
1281{
1282 return (void __iomem *)dd->kregbase + offset;
1283}
1284
1285static inline u64 read_write_csr(const struct hfi1_devdata *dd, u32 csr,
1286 int mode, u64 value)
1287{
1288 u64 ret;
1289
77241056
MM		 1290 if (mode == CNTR_MODE_R) {
1291 ret = read_csr(dd, csr);
1292 } else if (mode == CNTR_MODE_W) {
1293 write_csr(dd, csr, value);
1294 ret = value;
1295 } else {
1296 dd_dev_err(dd, "Invalid cntr register access mode");
1297 return 0;
1298 }
1299
1300 hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, ret, mode);
1301 return ret;
1302}
1303
1304/* Dev Access */
1305static u64 dev_access_u32_csr(const struct cntr_entry *entry,
17fb4f29 1306 void *context, int vl, int mode, u64 data)
77241056 1307{
a787bde8 1308 struct hfi1_devdata *dd = context;
a699c6c2 1309 u64 csr = entry->csr;
77241056 1310
a699c6c2
VM		 1311 if (entry->flags & CNTR_SDMA) {
1312 if (vl == CNTR_INVALID_VL)
1313 return 0;
1314 csr += 0x100 * vl;
1315 } else {
1316 if (vl != CNTR_INVALID_VL)
1317 return 0;
1318 }
1319 return read_write_csr(dd, csr, mode, data);
1320}
1321
1322static u64 access_sde_err_cnt(const struct cntr_entry *entry,
1323 void *context, int idx, int mode, u64 data)
1324{
1325 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1326
1327 if (dd->per_sdma && idx < dd->num_sdma)
1328 return dd->per_sdma[idx].err_cnt;
1329 return 0;
1330}
1331
1332static u64 access_sde_int_cnt(const struct cntr_entry *entry,
1333 void *context, int idx, int mode, u64 data)
1334{
1335 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1336
1337 if (dd->per_sdma && idx < dd->num_sdma)
1338 return dd->per_sdma[idx].sdma_int_cnt;
1339 return 0;
1340}
1341
1342static u64 access_sde_idle_int_cnt(const struct cntr_entry *entry,
1343 void *context, int idx, int mode, u64 data)
1344{
1345 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1346
1347 if (dd->per_sdma && idx < dd->num_sdma)
1348 return dd->per_sdma[idx].idle_int_cnt;
1349 return 0;
1350}
1351
1352static u64 access_sde_progress_int_cnt(const struct cntr_entry *entry,
1353 void *context, int idx, int mode,
1354 u64 data)
1355{
1356 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1357
1358 if (dd->per_sdma && idx < dd->num_sdma)
1359 return dd->per_sdma[idx].progress_int_cnt;
1360 return 0;
77241056
MM		 1361}
1362
1363static u64 dev_access_u64_csr(const struct cntr_entry *entry, void *context,
17fb4f29 1364 int vl, int mode, u64 data)
77241056 1365{
a787bde8 1366 struct hfi1_devdata *dd = context;
77241056
MM		 1367
1368 u64 val = 0;
1369 u64 csr = entry->csr;
1370
1371 if (entry->flags & CNTR_VL) {
1372 if (vl == CNTR_INVALID_VL)
1373 return 0;
1374 csr += 8 * vl;
1375 } else {
1376 if (vl != CNTR_INVALID_VL)
1377 return 0;
1378 }
1379
1380 val = read_write_csr(dd, csr, mode, data);
1381 return val;
1382}
1383
1384static u64 dc_access_lcb_cntr(const struct cntr_entry *entry, void *context,
17fb4f29 1385 int vl, int mode, u64 data)
77241056 1386{
a787bde8 1387 struct hfi1_devdata *dd = context;
77241056
MM		 1388 u32 csr = entry->csr;
1389 int ret = 0;
1390
1391 if (vl != CNTR_INVALID_VL)
1392 return 0;
1393 if (mode == CNTR_MODE_R)
1394 ret = read_lcb_csr(dd, csr, &data);
1395 else if (mode == CNTR_MODE_W)
1396 ret = write_lcb_csr(dd, csr, data);
1397
1398 if (ret) {
1399 dd_dev_err(dd, "Could not acquire LCB for counter 0x%x", csr);
1400 return 0;
1401 }
1402
1403 hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, data, mode);
1404 return data;
1405}
1406
1407/* Port Access */
1408static u64 port_access_u32_csr(const struct cntr_entry *entry, void *context,
17fb4f29 1409 int vl, int mode, u64 data)
77241056 1410{
a787bde8 1411 struct hfi1_pportdata *ppd = context;
77241056
MM		 1412
1413 if (vl != CNTR_INVALID_VL)
1414 return 0;
1415 return read_write_csr(ppd->dd, entry->csr, mode, data);
1416}
1417
1418static u64 port_access_u64_csr(const struct cntr_entry *entry,
17fb4f29 1419 void *context, int vl, int mode, u64 data)
77241056 1420{
a787bde8 1421 struct hfi1_pportdata *ppd = context;
77241056
MM		 1422 u64 val;
1423 u64 csr = entry->csr;
1424
1425 if (entry->flags & CNTR_VL) {
1426 if (vl == CNTR_INVALID_VL)
1427 return 0;
1428 csr += 8 * vl;
1429 } else {
1430 if (vl != CNTR_INVALID_VL)
1431 return 0;
1432 }
1433 val = read_write_csr(ppd->dd, csr, mode, data);
1434 return val;
1435}
1436
1437/* Software defined */
1438static inline u64 read_write_sw(struct hfi1_devdata *dd, u64 *cntr, int mode,
1439 u64 data)
1440{
1441 u64 ret;
1442
1443 if (mode == CNTR_MODE_R) {
1444 ret = *cntr;
1445 } else if (mode == CNTR_MODE_W) {
1446 *cntr = data;
1447 ret = data;
1448 } else {
1449 dd_dev_err(dd, "Invalid cntr sw access mode");
1450 return 0;
1451 }
1452
1453 hfi1_cdbg(CNTR, "val 0x%llx mode %d", ret, mode);
1454
1455 return ret;
1456}
1457
1458static u64 access_sw_link_dn_cnt(const struct cntr_entry *entry, void *context,
17fb4f29 1459 int vl, int mode, u64 data)
77241056 1460{
a787bde8 1461 struct hfi1_pportdata *ppd = context;
77241056
MM		 1462
1463 if (vl != CNTR_INVALID_VL)
1464 return 0;
1465 return read_write_sw(ppd->dd, &ppd->link_downed, mode, data);
1466}
1467
1468static u64 access_sw_link_up_cnt(const struct cntr_entry *entry, void *context,
17fb4f29 1469 int vl, int mode, u64 data)
77241056 1470{
a787bde8 1471 struct hfi1_pportdata *ppd = context;
77241056
MM		 1472
1473 if (vl != CNTR_INVALID_VL)
1474 return 0;
1475 return read_write_sw(ppd->dd, &ppd->link_up, mode, data);
1476}
1477
6d014530
DL		 1478static u64 access_sw_unknown_frame_cnt(const struct cntr_entry *entry,
1479 void *context, int vl, int mode,
1480 u64 data)
1481{
1482 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;
1483
1484 if (vl != CNTR_INVALID_VL)
1485 return 0;
1486 return read_write_sw(ppd->dd, &ppd->unknown_frame_count, mode, data);
1487}
1488
77241056 1489static u64 access_sw_xmit_discards(const struct cntr_entry *entry,
17fb4f29 1490 void *context, int vl, int mode, u64 data)
77241056 1491{
69a00b8e
MM		 1492 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;
1493 u64 zero = 0;
1494 u64 *counter;
77241056 1495
69a00b8e
MM		 1496 if (vl == CNTR_INVALID_VL)
1497 counter = &ppd->port_xmit_discards;
1498 else if (vl >= 0 && vl < C_VL_COUNT)
1499 counter = &ppd->port_xmit_discards_vl[vl];
1500 else
1501 counter = &zero;
77241056 1502
69a00b8e 1503 return read_write_sw(ppd->dd, counter, mode, data);
77241056
MM		 1504}
1505
1506static u64 access_xmit_constraint_errs(const struct cntr_entry *entry,
17fb4f29
JJ		 1507 void *context, int vl, int mode,
1508 u64 data)
77241056 1509{
a787bde8 1510 struct hfi1_pportdata *ppd = context;
77241056
MM		 1511
1512 if (vl != CNTR_INVALID_VL)
1513 return 0;
1514
1515 return read_write_sw(ppd->dd, &ppd->port_xmit_constraint_errors,
1516 mode, data);
1517}
1518
1519static u64 access_rcv_constraint_errs(const struct cntr_entry *entry,
17fb4f29 1520 void *context, int vl, int mode, u64 data)
77241056 1521{
a787bde8 1522 struct hfi1_pportdata *ppd = context;
77241056
MM		 1523
1524 if (vl != CNTR_INVALID_VL)
1525 return 0;
1526
1527 return read_write_sw(ppd->dd, &ppd->port_rcv_constraint_errors,
1528 mode, data);
1529}
1530
1531u64 get_all_cpu_total(u64 __percpu *cntr)
1532{
1533 int cpu;
1534 u64 counter = 0;
1535
1536 for_each_possible_cpu(cpu)
1537 counter += *per_cpu_ptr(cntr, cpu);
1538 return counter;
1539}
1540
1541static u64 read_write_cpu(struct hfi1_devdata *dd, u64 *z_val,
1542 u64 __percpu *cntr,
1543 int vl, int mode, u64 data)
1544{
77241056
MM		 1545 u64 ret = 0;
1546
1547 if (vl != CNTR_INVALID_VL)
1548 return 0;
1549
1550 if (mode == CNTR_MODE_R) {
1551 ret = get_all_cpu_total(cntr) - *z_val;
1552 } else if (mode == CNTR_MODE_W) {
1553 /* A write can only zero the counter */
1554 if (data == 0)
1555 *z_val = get_all_cpu_total(cntr);
1556 else
1557 dd_dev_err(dd, "Per CPU cntrs can only be zeroed");
1558 } else {
1559 dd_dev_err(dd, "Invalid cntr sw cpu access mode");
1560 return 0;
1561 }
1562
1563 return ret;
1564}
1565
1566static u64 access_sw_cpu_intr(const struct cntr_entry *entry,
1567 void *context, int vl, int mode, u64 data)
1568{
a787bde8 1569 struct hfi1_devdata *dd = context;
77241056
MM		 1570
1571 return read_write_cpu(dd, &dd->z_int_counter, dd->int_counter, vl,
1572 mode, data);
1573}
1574
1575static u64 access_sw_cpu_rcv_limit(const struct cntr_entry *entry,
17fb4f29 1576 void *context, int vl, int mode, u64 data)
77241056 1577{
a787bde8 1578 struct hfi1_devdata *dd = context;
77241056
MM		 1579
1580 return read_write_cpu(dd, &dd->z_rcv_limit, dd->rcv_limit, vl,
1581 mode, data);
1582}
1583
1584static u64 access_sw_pio_wait(const struct cntr_entry *entry,
1585 void *context, int vl, int mode, u64 data)
1586{
a787bde8 1587 struct hfi1_devdata *dd = context;
77241056
MM		 1588
1589 return dd->verbs_dev.n_piowait;
1590}
1591
14553ca1
MM		 1592static u64 access_sw_pio_drain(const struct cntr_entry *entry,
1593 void *context, int vl, int mode, u64 data)
1594{
1595 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1596
1597 return dd->verbs_dev.n_piodrain;
1598}
1599
77241056
MM		 1600static u64 access_sw_vtx_wait(const struct cntr_entry *entry,
1601 void *context, int vl, int mode, u64 data)
1602{
a787bde8 1603 struct hfi1_devdata *dd = context;
77241056
MM		 1604
1605 return dd->verbs_dev.n_txwait;
1606}
1607
1608static u64 access_sw_kmem_wait(const struct cntr_entry *entry,
1609 void *context, int vl, int mode, u64 data)
1610{
a787bde8 1611 struct hfi1_devdata *dd = context;
77241056
MM		 1612
1613 return dd->verbs_dev.n_kmem_wait;
1614}
1615
b421922e 1616static u64 access_sw_send_schedule(const struct cntr_entry *entry,
17fb4f29 1617 void *context, int vl, int mode, u64 data)
b421922e
DL		 1618{
1619 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1620
89abfc8d
VM		 1621 return read_write_cpu(dd, &dd->z_send_schedule, dd->send_schedule, vl,
1622 mode, data);
b421922e
DL		 1623}
1624
2c5b521a
JR		 1625/* Software counters for the error status bits within MISC_ERR_STATUS */
1626static u64 access_misc_pll_lock_fail_err_cnt(const struct cntr_entry *entry,
1627 void *context, int vl, int mode,
1628 u64 data)
1629{
1630 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1631
1632 return dd->misc_err_status_cnt[12];
1633}
1634
1635static u64 access_misc_mbist_fail_err_cnt(const struct cntr_entry *entry,
1636 void *context, int vl, int mode,
1637 u64 data)
1638{
1639 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1640
1641 return dd->misc_err_status_cnt[11];
1642}
1643
1644static u64 access_misc_invalid_eep_cmd_err_cnt(const struct cntr_entry *entry,
1645 void *context, int vl, int mode,
1646 u64 data)
1647{
1648 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1649
1650 return dd->misc_err_status_cnt[10];
1651}
1652
1653static u64 access_misc_efuse_done_parity_err_cnt(const struct cntr_entry *entry,
1654 void *context, int vl,
1655 int mode, u64 data)
1656{
1657 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1658
1659 return dd->misc_err_status_cnt[9];
1660}
1661
1662static u64 access_misc_efuse_write_err_cnt(const struct cntr_entry *entry,
1663 void *context, int vl, int mode,
1664 u64 data)
1665{
1666 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1667
1668 return dd->misc_err_status_cnt[8];
1669}
1670
1671static u64 access_misc_efuse_read_bad_addr_err_cnt(
1672 const struct cntr_entry *entry,
1673 void *context, int vl, int mode, u64 data)
1674{
1675 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1676
1677 return dd->misc_err_status_cnt[7];
1678}
1679
1680static u64 access_misc_efuse_csr_parity_err_cnt(const struct cntr_entry *entry,
1681 void *context, int vl,
1682 int mode, u64 data)
1683{
1684 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1685
1686 return dd->misc_err_status_cnt[6];
1687}
1688
1689static u64 access_misc_fw_auth_failed_err_cnt(const struct cntr_entry *entry,
1690 void *context, int vl, int mode,
1691 u64 data)
1692{
1693 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1694
1695 return dd->misc_err_status_cnt[5];
1696}
1697
1698static u64 access_misc_key_mismatch_err_cnt(const struct cntr_entry *entry,
1699 void *context, int vl, int mode,
1700 u64 data)
1701{
1702 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1703
1704 return dd->misc_err_status_cnt[4];
1705}
1706
1707static u64 access_misc_sbus_write_failed_err_cnt(const struct cntr_entry *entry,
1708 void *context, int vl,
1709 int mode, u64 data)
1710{
1711 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1712
1713 return dd->misc_err_status_cnt[3];
1714}
1715
1716static u64 access_misc_csr_write_bad_addr_err_cnt(
1717 const struct cntr_entry *entry,
1718 void *context, int vl, int mode, u64 data)
1719{
1720 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1721
1722 return dd->misc_err_status_cnt[2];
1723}
1724
1725static u64 access_misc_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
1726 void *context, int vl,
1727 int mode, u64 data)
1728{
1729 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1730
1731 return dd->misc_err_status_cnt[1];
1732}
1733
1734static u64 access_misc_csr_parity_err_cnt(const struct cntr_entry *entry,
1735 void *context, int vl, int mode,
1736 u64 data)
1737{
1738 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1739
1740 return dd->misc_err_status_cnt[0];
1741}
1742
1743/*
1744 * Software counter for the aggregate of
1745 * individual CceErrStatus counters
1746 */
1747static u64 access_sw_cce_err_status_aggregated_cnt(
1748 const struct cntr_entry *entry,
1749 void *context, int vl, int mode, u64 data)
1750{
1751 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1752
1753 return dd->sw_cce_err_status_aggregate;
1754}
1755
1756/*
1757 * Software counters corresponding to each of the
1758 * error status bits within CceErrStatus
1759 */
1760static u64 access_cce_msix_csr_parity_err_cnt(const struct cntr_entry *entry,
1761 void *context, int vl, int mode,
1762 u64 data)
1763{
1764 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1765
1766 return dd->cce_err_status_cnt[40];
1767}
1768
1769static u64 access_cce_int_map_unc_err_cnt(const struct cntr_entry *entry,
1770 void *context, int vl, int mode,
1771 u64 data)
1772{
1773 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1774
1775 return dd->cce_err_status_cnt[39];
1776}
1777
1778static u64 access_cce_int_map_cor_err_cnt(const struct cntr_entry *entry,
1779 void *context, int vl, int mode,
1780 u64 data)
1781{
1782 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1783
1784 return dd->cce_err_status_cnt[38];
1785}
1786
1787static u64 access_cce_msix_table_unc_err_cnt(const struct cntr_entry *entry,
1788 void *context, int vl, int mode,
1789 u64 data)
1790{
1791 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1792
1793 return dd->cce_err_status_cnt[37];
1794}
1795
1796static u64 access_cce_msix_table_cor_err_cnt(const struct cntr_entry *entry,
1797 void *context, int vl, int mode,
1798 u64 data)
1799{
1800 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1801
1802 return dd->cce_err_status_cnt[36];
1803}
1804
1805static u64 access_cce_rxdma_conv_fifo_parity_err_cnt(
1806 const struct cntr_entry *entry,
1807 void *context, int vl, int mode, u64 data)
1808{
1809 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1810
1811 return dd->cce_err_status_cnt[35];
1812}
1813
1814static u64 access_cce_rcpl_async_fifo_parity_err_cnt(
1815 const struct cntr_entry *entry,
1816 void *context, int vl, int mode, u64 data)
1817{
1818 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1819
1820 return dd->cce_err_status_cnt[34];
1821}
1822
1823static u64 access_cce_seg_write_bad_addr_err_cnt(const struct cntr_entry *entry,
1824 void *context, int vl,
1825 int mode, u64 data)
1826{
1827 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1828
1829 return dd->cce_err_status_cnt[33];
1830}
1831
1832static u64 access_cce_seg_read_bad_addr_err_cnt(const struct cntr_entry *entry,
1833 void *context, int vl, int mode,
1834 u64 data)
1835{
1836 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1837
1838 return dd->cce_err_status_cnt[32];
1839}
1840
1841static u64 access_la_triggered_cnt(const struct cntr_entry *entry,
1842 void *context, int vl, int mode, u64 data)
1843{
1844 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1845
1846 return dd->cce_err_status_cnt[31];
1847}
1848
1849static u64 access_cce_trgt_cpl_timeout_err_cnt(const struct cntr_entry *entry,
1850 void *context, int vl, int mode,
1851 u64 data)
1852{
1853 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1854
1855 return dd->cce_err_status_cnt[30];
1856}
1857
1858static u64 access_pcic_receive_parity_err_cnt(const struct cntr_entry *entry,
1859 void *context, int vl, int mode,
1860 u64 data)
1861{
1862 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1863
1864 return dd->cce_err_status_cnt[29];
1865}
1866
1867static u64 access_pcic_transmit_back_parity_err_cnt(
1868 const struct cntr_entry *entry,
1869 void *context, int vl, int mode, u64 data)
1870{
1871 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1872
1873 return dd->cce_err_status_cnt[28];
1874}
1875
1876static u64 access_pcic_transmit_front_parity_err_cnt(
1877 const struct cntr_entry *entry,
1878 void *context, int vl, int mode, u64 data)
1879{
1880 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1881
1882 return dd->cce_err_status_cnt[27];
1883}
1884
1885static u64 access_pcic_cpl_dat_q_unc_err_cnt(const struct cntr_entry *entry,
1886 void *context, int vl, int mode,
1887 u64 data)
1888{
1889 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1890
1891 return dd->cce_err_status_cnt[26];
1892}
1893
1894static u64 access_pcic_cpl_hd_q_unc_err_cnt(const struct cntr_entry *entry,
1895 void *context, int vl, int mode,
1896 u64 data)
1897{
1898 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1899
1900 return dd->cce_err_status_cnt[25];
1901}
1902
1903static u64 access_pcic_post_dat_q_unc_err_cnt(const struct cntr_entry *entry,
1904 void *context, int vl, int mode,
1905 u64 data)
1906{
1907 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1908
1909 return dd->cce_err_status_cnt[24];
1910}
1911
1912static u64 access_pcic_post_hd_q_unc_err_cnt(const struct cntr_entry *entry,
1913 void *context, int vl, int mode,
1914 u64 data)
1915{
1916 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1917
1918 return dd->cce_err_status_cnt[23];
1919}
1920
1921static u64 access_pcic_retry_sot_mem_unc_err_cnt(const struct cntr_entry *entry,
1922 void *context, int vl,
1923 int mode, u64 data)
1924{
1925 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1926
1927 return dd->cce_err_status_cnt[22];
1928}
1929
1930static u64 access_pcic_retry_mem_unc_err(const struct cntr_entry *entry,
1931 void *context, int vl, int mode,
1932 u64 data)
1933{
1934 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1935
1936 return dd->cce_err_status_cnt[21];
1937}
1938
1939static u64 access_pcic_n_post_dat_q_parity_err_cnt(
1940 const struct cntr_entry *entry,
1941 void *context, int vl, int mode, u64 data)
1942{
1943 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1944
1945 return dd->cce_err_status_cnt[20];
1946}
1947
1948static u64 access_pcic_n_post_h_q_parity_err_cnt(const struct cntr_entry *entry,
1949 void *context, int vl,
1950 int mode, u64 data)
1951{
1952 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1953
1954 return dd->cce_err_status_cnt[19];
1955}
1956
1957static u64 access_pcic_cpl_dat_q_cor_err_cnt(const struct cntr_entry *entry,
1958 void *context, int vl, int mode,
1959 u64 data)
1960{
1961 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1962
1963 return dd->cce_err_status_cnt[18];
1964}
1965
1966static u64 access_pcic_cpl_hd_q_cor_err_cnt(const struct cntr_entry *entry,
1967 void *context, int vl, int mode,
1968 u64 data)
1969{
1970 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1971
1972 return dd->cce_err_status_cnt[17];
1973}
1974
1975static u64 access_pcic_post_dat_q_cor_err_cnt(const struct cntr_entry *entry,
1976 void *context, int vl, int mode,
1977 u64 data)
1978{
1979 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1980
1981 return dd->cce_err_status_cnt[16];
1982}
1983
1984static u64 access_pcic_post_hd_q_cor_err_cnt(const struct cntr_entry *entry,
1985 void *context, int vl, int mode,
1986 u64 data)
1987{
1988 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1989
1990 return dd->cce_err_status_cnt[15];
1991}
1992
1993static u64 access_pcic_retry_sot_mem_cor_err_cnt(const struct cntr_entry *entry,
1994 void *context, int vl,
1995 int mode, u64 data)
1996{
1997 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1998
1999 return dd->cce_err_status_cnt[14];
2000}
2001
2002static u64 access_pcic_retry_mem_cor_err_cnt(const struct cntr_entry *entry,
2003 void *context, int vl, int mode,
2004 u64 data)
2005{
2006 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2007
2008 return dd->cce_err_status_cnt[13];
2009}
2010
2011static u64 access_cce_cli1_async_fifo_dbg_parity_err_cnt(
2012 const struct cntr_entry *entry,
2013 void *context, int vl, int mode, u64 data)
2014{
2015 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2016
2017 return dd->cce_err_status_cnt[12];
2018}
2019
2020static u64 access_cce_cli1_async_fifo_rxdma_parity_err_cnt(
2021 const struct cntr_entry *entry,
2022 void *context, int vl, int mode, u64 data)
2023{
2024 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2025
2026 return dd->cce_err_status_cnt[11];
2027}
2028
2029static u64 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt(
2030 const struct cntr_entry *entry,
2031 void *context, int vl, int mode, u64 data)
2032{
2033 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2034
2035 return dd->cce_err_status_cnt[10];
2036}
2037
2038static u64 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt(
2039 const struct cntr_entry *entry,
2040 void *context, int vl, int mode, u64 data)
2041{
2042 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2043
2044 return dd->cce_err_status_cnt[9];
2045}
2046
2047static u64 access_cce_cli2_async_fifo_parity_err_cnt(
2048 const struct cntr_entry *entry,
2049 void *context, int vl, int mode, u64 data)
2050{
2051 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2052
2053 return dd->cce_err_status_cnt[8];
2054}
2055
2056static u64 access_cce_csr_cfg_bus_parity_err_cnt(const struct cntr_entry *entry,
2057 void *context, int vl,
2058 int mode, u64 data)
2059{
2060 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2061
2062 return dd->cce_err_status_cnt[7];
2063}
2064
2065static u64 access_cce_cli0_async_fifo_parity_err_cnt(
2066 const struct cntr_entry *entry,
2067 void *context, int vl, int mode, u64 data)
2068{
2069 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2070
2071 return dd->cce_err_status_cnt[6];
2072}
2073
2074static u64 access_cce_rspd_data_parity_err_cnt(const struct cntr_entry *entry,
2075 void *context, int vl, int mode,
2076 u64 data)
2077{
2078 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2079
2080 return dd->cce_err_status_cnt[5];
2081}
2082
2083static u64 access_cce_trgt_access_err_cnt(const struct cntr_entry *entry,
2084 void *context, int vl, int mode,
2085 u64 data)
2086{
2087 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2088
2089 return dd->cce_err_status_cnt[4];
2090}
2091
2092static u64 access_cce_trgt_async_fifo_parity_err_cnt(
2093 const struct cntr_entry *entry,
2094 void *context, int vl, int mode, u64 data)
2095{
2096 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2097
2098 return dd->cce_err_status_cnt[3];
2099}
2100
2101static u64 access_cce_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry,
2102 void *context, int vl,
2103 int mode, u64 data)
2104{
2105 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2106
2107 return dd->cce_err_status_cnt[2];
2108}
2109
2110static u64 access_cce_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
2111 void *context, int vl,
2112 int mode, u64 data)
2113{
2114 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2115
2116 return dd->cce_err_status_cnt[1];
2117}
2118
2119static u64 access_ccs_csr_parity_err_cnt(const struct cntr_entry *entry,
2120 void *context, int vl, int mode,
2121 u64 data)
2122{
2123 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2124
2125 return dd->cce_err_status_cnt[0];
2126}
2127
2128/*
2129 * Software counters corresponding to each of the
2130 * error status bits within RcvErrStatus
2131 */
2132static u64 access_rx_csr_parity_err_cnt(const struct cntr_entry *entry,
2133 void *context, int vl, int mode,
2134 u64 data)
2135{
2136 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2137
2138 return dd->rcv_err_status_cnt[63];
2139}
2140
2141static u64 access_rx_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry,
2142 void *context, int vl,
2143 int mode, u64 data)
2144{
2145 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2146
2147 return dd->rcv_err_status_cnt[62];
2148}
2149
2150static u64 access_rx_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
2151 void *context, int vl, int mode,
2152 u64 data)
2153{
2154 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2155
2156 return dd->rcv_err_status_cnt[61];
2157}
2158
2159static u64 access_rx_dma_csr_unc_err_cnt(const struct cntr_entry *entry,
2160 void *context, int vl, int mode,
2161 u64 data)
2162{
2163 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2164
2165 return dd->rcv_err_status_cnt[60];
2166}
2167
2168static u64 access_rx_dma_dq_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2169 void *context, int vl,
2170 int mode, u64 data)
2171{
2172 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2173
2174 return dd->rcv_err_status_cnt[59];
2175}
2176
2177static u64 access_rx_dma_eq_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2178 void *context, int vl,
2179 int mode, u64 data)
2180{
2181 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2182
2183 return dd->rcv_err_status_cnt[58];
2184}
2185
2186static u64 access_rx_dma_csr_parity_err_cnt(const struct cntr_entry *entry,
2187 void *context, int vl, int mode,
2188 u64 data)
2189{
2190 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2191
2192 return dd->rcv_err_status_cnt[57];
2193}
2194
2195static u64 access_rx_rbuf_data_cor_err_cnt(const struct cntr_entry *entry,
2196 void *context, int vl, int mode,
2197 u64 data)
2198{
2199 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2200
2201 return dd->rcv_err_status_cnt[56];
2202}
2203
2204static u64 access_rx_rbuf_data_unc_err_cnt(const struct cntr_entry *entry,
2205 void *context, int vl, int mode,
2206 u64 data)
2207{
2208 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2209
2210 return dd->rcv_err_status_cnt[55];
2211}
2212
2213static u64 access_rx_dma_data_fifo_rd_cor_err_cnt(
2214 const struct cntr_entry *entry,
2215 void *context, int vl, int mode, u64 data)
2216{
2217 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2218
2219 return dd->rcv_err_status_cnt[54];
2220}
2221
2222static u64 access_rx_dma_data_fifo_rd_unc_err_cnt(
2223 const struct cntr_entry *entry,
2224 void *context, int vl, int mode, u64 data)
2225{
2226 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2227
2228 return dd->rcv_err_status_cnt[53];
2229}
2230
2231static u64 access_rx_dma_hdr_fifo_rd_cor_err_cnt(const struct cntr_entry *entry,
2232 void *context, int vl,
2233 int mode, u64 data)
2234{
2235 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2236
2237 return dd->rcv_err_status_cnt[52];
2238}
2239
2240static u64 access_rx_dma_hdr_fifo_rd_unc_err_cnt(const struct cntr_entry *entry,
2241 void *context, int vl,
2242 int mode, u64 data)
2243{
2244 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2245
2246 return dd->rcv_err_status_cnt[51];
2247}
2248
2249static u64 access_rx_rbuf_desc_part2_cor_err_cnt(const struct cntr_entry *entry,
2250 void *context, int vl,
2251 int mode, u64 data)
2252{
2253 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2254
2255 return dd->rcv_err_status_cnt[50];
2256}
2257
2258static u64 access_rx_rbuf_desc_part2_unc_err_cnt(const struct cntr_entry *entry,
2259 void *context, int vl,
2260 int mode, u64 data)
2261{
2262 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2263
2264 return dd->rcv_err_status_cnt[49];
2265}
2266
2267static u64 access_rx_rbuf_desc_part1_cor_err_cnt(const struct cntr_entry *entry,
2268 void *context, int vl,
2269 int mode, u64 data)
2270{
2271 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2272
2273 return dd->rcv_err_status_cnt[48];
2274}
2275
2276static u64 access_rx_rbuf_desc_part1_unc_err_cnt(const struct cntr_entry *entry,
2277 void *context, int vl,
2278 int mode, u64 data)
2279{
2280 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2281
2282 return dd->rcv_err_status_cnt[47];
2283}
2284
2285static u64 access_rx_hq_intr_fsm_err_cnt(const struct cntr_entry *entry,
2286 void *context, int vl, int mode,
2287 u64 data)
2288{
2289 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2290
2291 return dd->rcv_err_status_cnt[46];
2292}
2293
2294static u64 access_rx_hq_intr_csr_parity_err_cnt(
2295 const struct cntr_entry *entry,
2296 void *context, int vl, int mode, u64 data)
2297{
2298 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2299
2300 return dd->rcv_err_status_cnt[45];
2301}
2302
2303static u64 access_rx_lookup_csr_parity_err_cnt(
2304 const struct cntr_entry *entry,
2305 void *context, int vl, int mode, u64 data)
2306{
2307 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2308
2309 return dd->rcv_err_status_cnt[44];
2310}
2311
2312static u64 access_rx_lookup_rcv_array_cor_err_cnt(
2313 const struct cntr_entry *entry,
2314 void *context, int vl, int mode, u64 data)
2315{
2316 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2317
2318 return dd->rcv_err_status_cnt[43];
2319}
2320
2321static u64 access_rx_lookup_rcv_array_unc_err_cnt(
2322 const struct cntr_entry *entry,
2323 void *context, int vl, int mode, u64 data)
2324{
2325 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2326
2327 return dd->rcv_err_status_cnt[42];
2328}
2329
2330static u64 access_rx_lookup_des_part2_parity_err_cnt(
2331 const struct cntr_entry *entry,
2332 void *context, int vl, int mode, u64 data)
2333{
2334 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2335
2336 return dd->rcv_err_status_cnt[41];
2337}
2338
2339static u64 access_rx_lookup_des_part1_unc_cor_err_cnt(
2340 const struct cntr_entry *entry,
2341 void *context, int vl, int mode, u64 data)
2342{
2343 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2344
2345 return dd->rcv_err_status_cnt[40];
2346}
2347
2348static u64 access_rx_lookup_des_part1_unc_err_cnt(
2349 const struct cntr_entry *entry,
2350 void *context, int vl, int mode, u64 data)
2351{
2352 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2353
2354 return dd->rcv_err_status_cnt[39];
2355}
2356
2357static u64 access_rx_rbuf_next_free_buf_cor_err_cnt(
2358 const struct cntr_entry *entry,
2359 void *context, int vl, int mode, u64 data)
2360{
2361 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2362
2363 return dd->rcv_err_status_cnt[38];
2364}
2365
2366static u64 access_rx_rbuf_next_free_buf_unc_err_cnt(
2367 const struct cntr_entry *entry,
2368 void *context, int vl, int mode, u64 data)
2369{
2370 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2371
2372 return dd->rcv_err_status_cnt[37];
2373}
2374
2375static u64 access_rbuf_fl_init_wr_addr_parity_err_cnt(
2376 const struct cntr_entry *entry,
2377 void *context, int vl, int mode, u64 data)
2378{
2379 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2380
2381 return dd->rcv_err_status_cnt[36];
2382}
2383
2384static u64 access_rx_rbuf_fl_initdone_parity_err_cnt(
2385 const struct cntr_entry *entry,
2386 void *context, int vl, int mode, u64 data)
2387{
2388 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2389
2390 return dd->rcv_err_status_cnt[35];
2391}
2392
2393static u64 access_rx_rbuf_fl_write_addr_parity_err_cnt(
2394 const struct cntr_entry *entry,
2395 void *context, int vl, int mode, u64 data)
2396{
2397 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2398
2399 return dd->rcv_err_status_cnt[34];
2400}
2401
2402static u64 access_rx_rbuf_fl_rd_addr_parity_err_cnt(
2403 const struct cntr_entry *entry,
2404 void *context, int vl, int mode, u64 data)
2405{
2406 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2407
2408 return dd->rcv_err_status_cnt[33];
2409}
2410
2411static u64 access_rx_rbuf_empty_err_cnt(const struct cntr_entry *entry,
2412 void *context, int vl, int mode,
2413 u64 data)
2414{
2415 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2416
2417 return dd->rcv_err_status_cnt[32];
2418}
2419
2420static u64 access_rx_rbuf_full_err_cnt(const struct cntr_entry *entry,
2421 void *context, int vl, int mode,
2422 u64 data)
2423{
2424 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2425
2426 return dd->rcv_err_status_cnt[31];
2427}
2428
2429static u64 access_rbuf_bad_lookup_err_cnt(const struct cntr_entry *entry,
2430 void *context, int vl, int mode,
2431 u64 data)
2432{
2433 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2434
2435 return dd->rcv_err_status_cnt[30];
2436}
2437
2438static u64 access_rbuf_ctx_id_parity_err_cnt(const struct cntr_entry *entry,
2439 void *context, int vl, int mode,
2440 u64 data)
2441{
2442 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2443
2444 return dd->rcv_err_status_cnt[29];
2445}
2446
2447static u64 access_rbuf_csr_qeopdw_parity_err_cnt(const struct cntr_entry *entry,
2448 void *context, int vl,
2449 int mode, u64 data)
2450{
2451 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2452
2453 return dd->rcv_err_status_cnt[28];
2454}
2455
2456static u64 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt(
2457 const struct cntr_entry *entry,
2458 void *context, int vl, int mode, u64 data)
2459{
2460 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2461
2462 return dd->rcv_err_status_cnt[27];
2463}
2464
2465static u64 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt(
2466 const struct cntr_entry *entry,
2467 void *context, int vl, int mode, u64 data)
2468{
2469 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2470
2471 return dd->rcv_err_status_cnt[26];
2472}
2473
2474static u64 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt(
2475 const struct cntr_entry *entry,
2476 void *context, int vl, int mode, u64 data)
2477{
2478 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2479
2480 return dd->rcv_err_status_cnt[25];
2481}
2482
2483static u64 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt(
2484 const struct cntr_entry *entry,
2485 void *context, int vl, int mode, u64 data)
2486{
2487 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2488
2489 return dd->rcv_err_status_cnt[24];
2490}
2491
2492static u64 access_rx_rbuf_csr_q_next_buf_parity_err_cnt(
2493 const struct cntr_entry *entry,
2494 void *context, int vl, int mode, u64 data)
2495{
2496 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2497
2498 return dd->rcv_err_status_cnt[23];
2499}
2500
2501static u64 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt(
2502 const struct cntr_entry *entry,
2503 void *context, int vl, int mode, u64 data)
2504{
2505 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2506
2507 return dd->rcv_err_status_cnt[22];
2508}
2509
2510static u64 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt(
2511 const struct cntr_entry *entry,
2512 void *context, int vl, int mode, u64 data)
2513{
2514 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2515
2516 return dd->rcv_err_status_cnt[21];
2517}
2518
2519static u64 access_rx_rbuf_block_list_read_cor_err_cnt(
2520 const struct cntr_entry *entry,
2521 void *context, int vl, int mode, u64 data)
2522{
2523 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2524
2525 return dd->rcv_err_status_cnt[20];
2526}
2527
2528static u64 access_rx_rbuf_block_list_read_unc_err_cnt(
2529 const struct cntr_entry *entry,
2530 void *context, int vl, int mode, u64 data)
2531{
2532 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2533
2534 return dd->rcv_err_status_cnt[19];
2535}
2536
2537static u64 access_rx_rbuf_lookup_des_cor_err_cnt(const struct cntr_entry *entry,
2538 void *context, int vl,
2539 int mode, u64 data)
2540{
2541 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2542
2543 return dd->rcv_err_status_cnt[18];
2544}
2545
2546static u64 access_rx_rbuf_lookup_des_unc_err_cnt(const struct cntr_entry *entry,
2547 void *context, int vl,
2548 int mode, u64 data)
2549{
2550 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2551
2552 return dd->rcv_err_status_cnt[17];
2553}
2554
2555static u64 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt(
2556 const struct cntr_entry *entry,
2557 void *context, int vl, int mode, u64 data)
2558{
2559 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2560
2561 return dd->rcv_err_status_cnt[16];
2562}
2563
2564static u64 access_rx_rbuf_lookup_des_reg_unc_err_cnt(
2565 const struct cntr_entry *entry,
2566 void *context, int vl, int mode, u64 data)
2567{
2568 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2569
2570 return dd->rcv_err_status_cnt[15];
2571}
2572
2573static u64 access_rx_rbuf_free_list_cor_err_cnt(const struct cntr_entry *entry,
2574 void *context, int vl,
2575 int mode, u64 data)
2576{
2577 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2578
2579 return dd->rcv_err_status_cnt[14];
2580}
2581
2582static u64 access_rx_rbuf_free_list_unc_err_cnt(const struct cntr_entry *entry,
2583 void *context, int vl,
2584 int mode, u64 data)
2585{
2586 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2587
2588 return dd->rcv_err_status_cnt[13];
2589}
2590
2591static u64 access_rx_rcv_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2592 void *context, int vl, int mode,
2593 u64 data)
2594{
2595 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2596
2597 return dd->rcv_err_status_cnt[12];
2598}
2599
2600static u64 access_rx_dma_flag_cor_err_cnt(const struct cntr_entry *entry,
2601 void *context, int vl, int mode,
2602 u64 data)
2603{
2604 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2605
2606 return dd->rcv_err_status_cnt[11];
2607}
2608
2609static u64 access_rx_dma_flag_unc_err_cnt(const struct cntr_entry *entry,
2610 void *context, int vl, int mode,
2611 u64 data)
2612{
2613 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2614
2615 return dd->rcv_err_status_cnt[10];
2616}
2617
2618static u64 access_rx_dc_sop_eop_parity_err_cnt(const struct cntr_entry *entry,
2619 void *context, int vl, int mode,
2620 u64 data)
2621{
2622 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2623
2624 return dd->rcv_err_status_cnt[9];
2625}
2626
2627static u64 access_rx_rcv_csr_parity_err_cnt(const struct cntr_entry *entry,
2628 void *context, int vl, int mode,
2629 u64 data)
2630{
2631 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2632
2633 return dd->rcv_err_status_cnt[8];
2634}
2635
2636static u64 access_rx_rcv_qp_map_table_cor_err_cnt(
2637 const struct cntr_entry *entry,
2638 void *context, int vl, int mode, u64 data)
2639{
2640 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2641
2642 return dd->rcv_err_status_cnt[7];
2643}
2644
2645static u64 access_rx_rcv_qp_map_table_unc_err_cnt(
2646 const struct cntr_entry *entry,
2647 void *context, int vl, int mode, u64 data)
2648{
2649 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2650
2651 return dd->rcv_err_status_cnt[6];
2652}
2653
2654static u64 access_rx_rcv_data_cor_err_cnt(const struct cntr_entry *entry,
2655 void *context, int vl, int mode,
2656 u64 data)
2657{
2658 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2659
2660 return dd->rcv_err_status_cnt[5];
2661}
2662
2663static u64 access_rx_rcv_data_unc_err_cnt(const struct cntr_entry *entry,
2664 void *context, int vl, int mode,
2665 u64 data)
2666{
2667 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2668
2669 return dd->rcv_err_status_cnt[4];
2670}
2671
2672static u64 access_rx_rcv_hdr_cor_err_cnt(const struct cntr_entry *entry,
2673 void *context, int vl, int mode,
2674 u64 data)
2675{
2676 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2677
2678 return dd->rcv_err_status_cnt[3];
2679}
2680
2681static u64 access_rx_rcv_hdr_unc_err_cnt(const struct cntr_entry *entry,
2682 void *context, int vl, int mode,
2683 u64 data)
2684{
2685 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2686
2687 return dd->rcv_err_status_cnt[2];
2688}
2689
2690static u64 access_rx_dc_intf_parity_err_cnt(const struct cntr_entry *entry,
2691 void *context, int vl, int mode,
2692 u64 data)
2693{
2694 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2695
2696 return dd->rcv_err_status_cnt[1];
2697}
2698
2699static u64 access_rx_dma_csr_cor_err_cnt(const struct cntr_entry *entry,
2700 void *context, int vl, int mode,
2701 u64 data)
2702{
2703 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2704
2705 return dd->rcv_err_status_cnt[0];
2706}
2707
2708/*
2709 * Software counters corresponding to each of the
2710 * error status bits within SendPioErrStatus
2711 */
2712static u64 access_pio_pec_sop_head_parity_err_cnt(
2713 const struct cntr_entry *entry,
2714 void *context, int vl, int mode, u64 data)
2715{
2716 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2717
2718 return dd->send_pio_err_status_cnt[35];
2719}
2720
2721static u64 access_pio_pcc_sop_head_parity_err_cnt(
2722 const struct cntr_entry *entry,
2723 void *context, int vl, int mode, u64 data)
2724{
2725 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2726
2727 return dd->send_pio_err_status_cnt[34];
2728}
2729
2730static u64 access_pio_last_returned_cnt_parity_err_cnt(
2731 const struct cntr_entry *entry,
2732 void *context, int vl, int mode, u64 data)
2733{
2734 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2735
2736 return dd->send_pio_err_status_cnt[33];
2737}
2738
2739static u64 access_pio_current_free_cnt_parity_err_cnt(
2740 const struct cntr_entry *entry,
2741 void *context, int vl, int mode, u64 data)
2742{
2743 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2744
2745 return dd->send_pio_err_status_cnt[32];
2746}
2747
2748static u64 access_pio_reserved_31_err_cnt(const struct cntr_entry *entry,
2749 void *context, int vl, int mode,
2750 u64 data)
2751{
2752 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2753
2754 return dd->send_pio_err_status_cnt[31];
2755}
2756
2757static u64 access_pio_reserved_30_err_cnt(const struct cntr_entry *entry,
2758 void *context, int vl, int mode,
2759 u64 data)
2760{
2761 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2762
2763 return dd->send_pio_err_status_cnt[30];
2764}
2765
2766static u64 access_pio_ppmc_sop_len_err_cnt(const struct cntr_entry *entry,
2767 void *context, int vl, int mode,
2768 u64 data)
2769{
2770 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2771
2772 return dd->send_pio_err_status_cnt[29];
2773}
2774
2775static u64 access_pio_ppmc_bqc_mem_parity_err_cnt(
2776 const struct cntr_entry *entry,
2777 void *context, int vl, int mode, u64 data)
2778{
2779 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2780
2781 return dd->send_pio_err_status_cnt[28];
2782}
2783
2784static u64 access_pio_vl_fifo_parity_err_cnt(const struct cntr_entry *entry,
2785 void *context, int vl, int mode,
2786 u64 data)
2787{
2788 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2789
2790 return dd->send_pio_err_status_cnt[27];
2791}
2792
2793static u64 access_pio_vlf_sop_parity_err_cnt(const struct cntr_entry *entry,
2794 void *context, int vl, int mode,
2795 u64 data)
2796{
2797 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2798
2799 return dd->send_pio_err_status_cnt[26];
2800}
2801
2802static u64 access_pio_vlf_v1_len_parity_err_cnt(const struct cntr_entry *entry,
2803 void *context, int vl,
2804 int mode, u64 data)
2805{
2806 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2807
2808 return dd->send_pio_err_status_cnt[25];
2809}
2810
2811static u64 access_pio_block_qw_count_parity_err_cnt(
2812 const struct cntr_entry *entry,
2813 void *context, int vl, int mode, u64 data)
2814{
2815 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2816
2817 return dd->send_pio_err_status_cnt[24];
2818}
2819
2820static u64 access_pio_write_qw_valid_parity_err_cnt(
2821 const struct cntr_entry *entry,
2822 void *context, int vl, int mode, u64 data)
2823{
2824 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2825
2826 return dd->send_pio_err_status_cnt[23];
2827}
2828
2829static u64 access_pio_state_machine_err_cnt(const struct cntr_entry *entry,
2830 void *context, int vl, int mode,
2831 u64 data)
2832{
2833 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2834
2835 return dd->send_pio_err_status_cnt[22];
2836}
2837
2838static u64 access_pio_write_data_parity_err_cnt(const struct cntr_entry *entry,
2839 void *context, int vl,
2840 int mode, u64 data)
2841{
2842 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2843
2844 return dd->send_pio_err_status_cnt[21];
2845}
2846
2847static u64 access_pio_host_addr_mem_cor_err_cnt(const struct cntr_entry *entry,
2848 void *context, int vl,
2849 int mode, u64 data)
2850{
2851 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2852
2853 return dd->send_pio_err_status_cnt[20];
2854}
2855
2856static u64 access_pio_host_addr_mem_unc_err_cnt(const struct cntr_entry *entry,
2857 void *context, int vl,
2858 int mode, u64 data)
2859{
2860 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2861
2862 return dd->send_pio_err_status_cnt[19];
2863}
2864
2865static u64 access_pio_pkt_evict_sm_or_arb_sm_err_cnt(
2866 const struct cntr_entry *entry,
2867 void *context, int vl, int mode, u64 data)
2868{
2869 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2870
2871 return dd->send_pio_err_status_cnt[18];
2872}
2873
2874static u64 access_pio_init_sm_in_err_cnt(const struct cntr_entry *entry,
2875 void *context, int vl, int mode,
2876 u64 data)
2877{
2878 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2879
2880 return dd->send_pio_err_status_cnt[17];
2881}
2882
2883static u64 access_pio_ppmc_pbl_fifo_err_cnt(const struct cntr_entry *entry,
2884 void *context, int vl, int mode,
2885 u64 data)
2886{
2887 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2888
2889 return dd->send_pio_err_status_cnt[16];
2890}
2891
2892static u64 access_pio_credit_ret_fifo_parity_err_cnt(
2893 const struct cntr_entry *entry,
2894 void *context, int vl, int mode, u64 data)
2895{
2896 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2897
2898 return dd->send_pio_err_status_cnt[15];
2899}
2900
2901static u64 access_pio_v1_len_mem_bank1_cor_err_cnt(
2902 const struct cntr_entry *entry,
2903 void *context, int vl, int mode, u64 data)
2904{
2905 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2906
2907 return dd->send_pio_err_status_cnt[14];
2908}
2909
2910static u64 access_pio_v1_len_mem_bank0_cor_err_cnt(
2911 const struct cntr_entry *entry,
2912 void *context, int vl, int mode, u64 data)
2913{
2914 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2915
2916 return dd->send_pio_err_status_cnt[13];
2917}
2918
2919static u64 access_pio_v1_len_mem_bank1_unc_err_cnt(
2920 const struct cntr_entry *entry,
2921 void *context, int vl, int mode, u64 data)
2922{
2923 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2924
2925 return dd->send_pio_err_status_cnt[12];
2926}
2927
2928static u64 access_pio_v1_len_mem_bank0_unc_err_cnt(
2929 const struct cntr_entry *entry,
2930 void *context, int vl, int mode, u64 data)
2931{
2932 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2933
2934 return dd->send_pio_err_status_cnt[11];
2935}
2936
2937static u64 access_pio_sm_pkt_reset_parity_err_cnt(
2938 const struct cntr_entry *entry,
2939 void *context, int vl, int mode, u64 data)
2940{
2941 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2942
2943 return dd->send_pio_err_status_cnt[10];
2944}
2945
2946static u64 access_pio_pkt_evict_fifo_parity_err_cnt(
2947 const struct cntr_entry *entry,
2948 void *context, int vl, int mode, u64 data)
2949{
2950 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2951
2952 return dd->send_pio_err_status_cnt[9];
2953}
2954
2955static u64 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt(
2956 const struct cntr_entry *entry,
2957 void *context, int vl, int mode, u64 data)
2958{
2959 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2960
2961 return dd->send_pio_err_status_cnt[8];
2962}
2963
2964static u64 access_pio_sbrdctl_crrel_parity_err_cnt(
2965 const struct cntr_entry *entry,
2966 void *context, int vl, int mode, u64 data)
2967{
2968 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2969
2970 return dd->send_pio_err_status_cnt[7];
2971}
2972
2973static u64 access_pio_pec_fifo_parity_err_cnt(const struct cntr_entry *entry,
2974 void *context, int vl, int mode,
2975 u64 data)
2976{
2977 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2978
2979 return dd->send_pio_err_status_cnt[6];
2980}
2981
2982static u64 access_pio_pcc_fifo_parity_err_cnt(const struct cntr_entry *entry,
2983 void *context, int vl, int mode,
2984 u64 data)
2985{
2986 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2987
2988 return dd->send_pio_err_status_cnt[5];
2989}
2990
2991static u64 access_pio_sb_mem_fifo1_err_cnt(const struct cntr_entry *entry,
2992 void *context, int vl, int mode,
2993 u64 data)
2994{
2995 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2996
2997 return dd->send_pio_err_status_cnt[4];
2998}
2999
3000static u64 access_pio_sb_mem_fifo0_err_cnt(const struct cntr_entry *entry,
3001 void *context, int vl, int mode,
3002 u64 data)
3003{
3004 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3005
3006 return dd->send_pio_err_status_cnt[3];
3007}
3008
3009static u64 access_pio_csr_parity_err_cnt(const struct cntr_entry *entry,
3010 void *context, int vl, int mode,
3011 u64 data)
3012{
3013 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3014
3015 return dd->send_pio_err_status_cnt[2];
3016}
3017
3018static u64 access_pio_write_addr_parity_err_cnt(const struct cntr_entry *entry,
3019 void *context, int vl,
3020 int mode, u64 data)
3021{
3022 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3023
3024 return dd->send_pio_err_status_cnt[1];
3025}
3026
3027static u64 access_pio_write_bad_ctxt_err_cnt(const struct cntr_entry *entry,
3028 void *context, int vl, int mode,
3029 u64 data)
3030{
3031 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3032
3033 return dd->send_pio_err_status_cnt[0];
3034}
3035
3036/*
3037 * Software counters corresponding to each of the
3038 * error status bits within SendDmaErrStatus
3039 */
3040static u64 access_sdma_pcie_req_tracking_cor_err_cnt(
3041 const struct cntr_entry *entry,
3042 void *context, int vl, int mode, u64 data)
3043{
3044 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3045
3046 return dd->send_dma_err_status_cnt[3];
3047}
3048
3049static u64 access_sdma_pcie_req_tracking_unc_err_cnt(
3050 const struct cntr_entry *entry,
3051 void *context, int vl, int mode, u64 data)
3052{
3053 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3054
3055 return dd->send_dma_err_status_cnt[2];
3056}
3057
3058static u64 access_sdma_csr_parity_err_cnt(const struct cntr_entry *entry,
3059 void *context, int vl, int mode,
3060 u64 data)
3061{
3062 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3063
3064 return dd->send_dma_err_status_cnt[1];
3065}
3066
3067static u64 access_sdma_rpy_tag_err_cnt(const struct cntr_entry *entry,
3068 void *context, int vl, int mode,
3069 u64 data)
3070{
3071 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3072
3073 return dd->send_dma_err_status_cnt[0];
3074}
3075
3076/*
3077 * Software counters corresponding to each of the
3078 * error status bits within SendEgressErrStatus
3079 */
3080static u64 access_tx_read_pio_memory_csr_unc_err_cnt(
3081 const struct cntr_entry *entry,
3082 void *context, int vl, int mode, u64 data)
3083{
3084 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3085
3086 return dd->send_egress_err_status_cnt[63];
3087}
3088
3089static u64 access_tx_read_sdma_memory_csr_err_cnt(
3090 const struct cntr_entry *entry,
3091 void *context, int vl, int mode, u64 data)
3092{
3093 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3094
3095 return dd->send_egress_err_status_cnt[62];
3096}
3097
3098static u64 access_tx_egress_fifo_cor_err_cnt(const struct cntr_entry *entry,
3099 void *context, int vl, int mode,
3100 u64 data)
3101{
3102 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3103
3104 return dd->send_egress_err_status_cnt[61];
3105}
3106
3107static u64 access_tx_read_pio_memory_cor_err_cnt(const struct cntr_entry *entry,
3108 void *context, int vl,
3109 int mode, u64 data)
3110{
3111 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3112
3113 return dd->send_egress_err_status_cnt[60];
3114}
3115
3116static u64 access_tx_read_sdma_memory_cor_err_cnt(
3117 const struct cntr_entry *entry,
3118 void *context, int vl, int mode, u64 data)
3119{
3120 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3121
3122 return dd->send_egress_err_status_cnt[59];
3123}
3124
3125static u64 access_tx_sb_hdr_cor_err_cnt(const struct cntr_entry *entry,
3126 void *context, int vl, int mode,
3127 u64 data)
3128{
3129 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3130
3131 return dd->send_egress_err_status_cnt[58];
3132}
3133
3134static u64 access_tx_credit_overrun_err_cnt(const struct cntr_entry *entry,
3135 void *context, int vl, int mode,
3136 u64 data)
3137{
3138 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3139
3140 return dd->send_egress_err_status_cnt[57];
3141}
3142
3143static u64 access_tx_launch_fifo8_cor_err_cnt(const struct cntr_entry *entry,
3144 void *context, int vl, int mode,
3145 u64 data)
3146{
3147 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3148
3149 return dd->send_egress_err_status_cnt[56];
3150}
3151
3152static u64 access_tx_launch_fifo7_cor_err_cnt(const struct cntr_entry *entry,
3153 void *context, int vl, int mode,
3154 u64 data)
3155{
3156 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3157
3158 return dd->send_egress_err_status_cnt[55];
3159}
3160
3161static u64 access_tx_launch_fifo6_cor_err_cnt(const struct cntr_entry *entry,
3162 void *context, int vl, int mode,
3163 u64 data)
3164{
3165 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3166
3167 return dd->send_egress_err_status_cnt[54];
3168}
3169
3170static u64 access_tx_launch_fifo5_cor_err_cnt(const struct cntr_entry *entry,
3171 void *context, int vl, int mode,
3172 u64 data)
3173{
3174 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3175
3176 return dd->send_egress_err_status_cnt[53];
3177}
3178
3179static u64 access_tx_launch_fifo4_cor_err_cnt(const struct cntr_entry *entry,
3180 void *context, int vl, int mode,
3181 u64 data)
3182{
3183 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3184
3185 return dd->send_egress_err_status_cnt[52];
3186}
3187
3188static u64 access_tx_launch_fifo3_cor_err_cnt(const struct cntr_entry *entry,
3189 void *context, int vl, int mode,
3190 u64 data)
3191{
3192 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3193
3194 return dd->send_egress_err_status_cnt[51];
3195}
3196
3197static u64 access_tx_launch_fifo2_cor_err_cnt(const struct cntr_entry *entry,
3198 void *context, int vl, int mode,
3199 u64 data)
3200{
3201 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3202
3203 return dd->send_egress_err_status_cnt[50];
3204}
3205
3206static u64 access_tx_launch_fifo1_cor_err_cnt(const struct cntr_entry *entry,
3207 void *context, int vl, int mode,
3208 u64 data)
3209{
3210 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3211
3212 return dd->send_egress_err_status_cnt[49];
3213}
3214
3215static u64 access_tx_launch_fifo0_cor_err_cnt(const struct cntr_entry *entry,
3216 void *context, int vl, int mode,
3217 u64 data)
3218{
3219 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3220
3221 return dd->send_egress_err_status_cnt[48];
3222}
3223
3224static u64 access_tx_credit_return_vl_err_cnt(const struct cntr_entry *entry,
3225 void *context, int vl, int mode,
3226 u64 data)
3227{
3228 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3229
3230 return dd->send_egress_err_status_cnt[47];
3231}
3232
3233static u64 access_tx_hcrc_insertion_err_cnt(const struct cntr_entry *entry,
3234 void *context, int vl, int mode,
3235 u64 data)
3236{
3237 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3238
3239 return dd->send_egress_err_status_cnt[46];
3240}
3241
3242static u64 access_tx_egress_fifo_unc_err_cnt(const struct cntr_entry *entry,
3243 void *context, int vl, int mode,
3244 u64 data)
3245{
3246 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3247
3248 return dd->send_egress_err_status_cnt[45];
3249}
3250
3251static u64 access_tx_read_pio_memory_unc_err_cnt(const struct cntr_entry *entry,
3252 void *context, int vl,
3253 int mode, u64 data)
3254{
3255 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3256
3257 return dd->send_egress_err_status_cnt[44];
3258}
3259
3260static u64 access_tx_read_sdma_memory_unc_err_cnt(
3261 const struct cntr_entry *entry,
3262 void *context, int vl, int mode, u64 data)
3263{
3264 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3265
3266 return dd->send_egress_err_status_cnt[43];
3267}
3268
3269static u64 access_tx_sb_hdr_unc_err_cnt(const struct cntr_entry *entry,
3270 void *context, int vl, int mode,
3271 u64 data)
3272{
3273 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3274
3275 return dd->send_egress_err_status_cnt[42];
3276}
3277
3278static u64 access_tx_credit_return_partiy_err_cnt(
3279 const struct cntr_entry *entry,
3280 void *context, int vl, int mode, u64 data)
3281{
3282 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3283
3284 return dd->send_egress_err_status_cnt[41];
3285}
3286
3287static u64 access_tx_launch_fifo8_unc_or_parity_err_cnt(
3288 const struct cntr_entry *entry,
3289 void *context, int vl, int mode, u64 data)
3290{
3291 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3292
3293 return dd->send_egress_err_status_cnt[40];
3294}
3295
3296static u64 access_tx_launch_fifo7_unc_or_parity_err_cnt(
3297 const struct cntr_entry *entry,
3298 void *context, int vl, int mode, u64 data)
3299{
3300 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3301
3302 return dd->send_egress_err_status_cnt[39];
3303}
3304
3305static u64 access_tx_launch_fifo6_unc_or_parity_err_cnt(
3306 const struct cntr_entry *entry,
3307 void *context, int vl, int mode, u64 data)
3308{
3309 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3310
3311 return dd->send_egress_err_status_cnt[38];
3312}
3313
3314static u64 access_tx_launch_fifo5_unc_or_parity_err_cnt(
3315 const struct cntr_entry *entry,
3316 void *context, int vl, int mode, u64 data)
3317{
3318 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3319
3320 return dd->send_egress_err_status_cnt[37];
3321}
3322
3323static u64 access_tx_launch_fifo4_unc_or_parity_err_cnt(
3324 const struct cntr_entry *entry,
3325 void *context, int vl, int mode, u64 data)
3326{
3327 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3328
3329 return dd->send_egress_err_status_cnt[36];
3330}
3331
3332static u64 access_tx_launch_fifo3_unc_or_parity_err_cnt(
3333 const struct cntr_entry *entry,
3334 void *context, int vl, int mode, u64 data)
3335{
3336 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3337
3338 return dd->send_egress_err_status_cnt[35];
3339}
3340
3341static u64 access_tx_launch_fifo2_unc_or_parity_err_cnt(
3342 const struct cntr_entry *entry,
3343 void *context, int vl, int mode, u64 data)
3344{
3345 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3346
3347 return dd->send_egress_err_status_cnt[34];
3348}
3349
3350static u64 access_tx_launch_fifo1_unc_or_parity_err_cnt(
3351 const struct cntr_entry *entry,
3352 void *context, int vl, int mode, u64 data)
3353{
3354 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3355
3356 return dd->send_egress_err_status_cnt[33];
3357}
3358
3359static u64 access_tx_launch_fifo0_unc_or_parity_err_cnt(
3360 const struct cntr_entry *entry,
3361 void *context, int vl, int mode, u64 data)
3362{
3363 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3364
3365 return dd->send_egress_err_status_cnt[32];
3366}
3367
3368static u64 access_tx_sdma15_disallowed_packet_err_cnt(
3369 const struct cntr_entry *entry,
3370 void *context, int vl, int mode, u64 data)
3371{
3372 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3373
3374 return dd->send_egress_err_status_cnt[31];
3375}
3376
3377static u64 access_tx_sdma14_disallowed_packet_err_cnt(
3378 const struct cntr_entry *entry,
3379 void *context, int vl, int mode, u64 data)
3380{
3381 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3382
3383 return dd->send_egress_err_status_cnt[30];
3384}
3385
3386static u64 access_tx_sdma13_disallowed_packet_err_cnt(
3387 const struct cntr_entry *entry,
3388 void *context, int vl, int mode, u64 data)
3389{
3390 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3391
3392 return dd->send_egress_err_status_cnt[29];
3393}
3394
3395static u64 access_tx_sdma12_disallowed_packet_err_cnt(
3396 const struct cntr_entry *entry,
3397 void *context, int vl, int mode, u64 data)
3398{
3399 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3400
3401 return dd->send_egress_err_status_cnt[28];
3402}
3403
3404static u64 access_tx_sdma11_disallowed_packet_err_cnt(
3405 const struct cntr_entry *entry,
3406 void *context, int vl, int mode, u64 data)
3407{
3408 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3409
3410 return dd->send_egress_err_status_cnt[27];
3411}
3412
3413static u64 access_tx_sdma10_disallowed_packet_err_cnt(
3414 const struct cntr_entry *entry,
3415 void *context, int vl, int mode, u64 data)
3416{
3417 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3418
3419 return dd->send_egress_err_status_cnt[26];
3420}
3421
3422static u64 access_tx_sdma9_disallowed_packet_err_cnt(
3423 const struct cntr_entry *entry,
3424 void *context, int vl, int mode, u64 data)
3425{
3426 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3427
3428 return dd->send_egress_err_status_cnt[25];
3429}
3430
3431static u64 access_tx_sdma8_disallowed_packet_err_cnt(
3432 const struct cntr_entry *entry,
3433 void *context, int vl, int mode, u64 data)
3434{
3435 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3436
3437 return dd->send_egress_err_status_cnt[24];
3438}
3439
3440static u64 access_tx_sdma7_disallowed_packet_err_cnt(
3441 const struct cntr_entry *entry,
3442 void *context, int vl, int mode, u64 data)
3443{
3444 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3445
3446 return dd->send_egress_err_status_cnt[23];
3447}
3448
3449static u64 access_tx_sdma6_disallowed_packet_err_cnt(
3450 const struct cntr_entry *entry,
3451 void *context, int vl, int mode, u64 data)
3452{
3453 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3454
3455 return dd->send_egress_err_status_cnt[22];
3456}
3457
3458static u64 access_tx_sdma5_disallowed_packet_err_cnt(
3459 const struct cntr_entry *entry,
3460 void *context, int vl, int mode, u64 data)
3461{
3462 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3463
3464 return dd->send_egress_err_status_cnt[21];
3465}
3466
3467static u64 access_tx_sdma4_disallowed_packet_err_cnt(
3468 const struct cntr_entry *entry,
3469 void *context, int vl, int mode, u64 data)
3470{
3471 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3472
3473 return dd->send_egress_err_status_cnt[20];
3474}
3475
3476static u64 access_tx_sdma3_disallowed_packet_err_cnt(
3477 const struct cntr_entry *entry,
3478 void *context, int vl, int mode, u64 data)
3479{
3480 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3481
3482 return dd->send_egress_err_status_cnt[19];
3483}
3484
3485static u64 access_tx_sdma2_disallowed_packet_err_cnt(
3486 const struct cntr_entry *entry,
3487 void *context, int vl, int mode, u64 data)
3488{
3489 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3490
3491 return dd->send_egress_err_status_cnt[18];
3492}
3493
3494static u64 access_tx_sdma1_disallowed_packet_err_cnt(
3495 const struct cntr_entry *entry,
3496 void *context, int vl, int mode, u64 data)
3497{
3498 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3499
3500 return dd->send_egress_err_status_cnt[17];
3501}
3502
3503static u64 access_tx_sdma0_disallowed_packet_err_cnt(
3504 const struct cntr_entry *entry,
3505 void *context, int vl, int mode, u64 data)
3506{
3507 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3508
3509 return dd->send_egress_err_status_cnt[16];
3510}
3511
3512static u64 access_tx_config_parity_err_cnt(const struct cntr_entry *entry,
3513 void *context, int vl, int mode,
3514 u64 data)
3515{
3516 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3517
3518 return dd->send_egress_err_status_cnt[15];
3519}
3520
3521static u64 access_tx_sbrd_ctl_csr_parity_err_cnt(const struct cntr_entry *entry,
3522 void *context, int vl,
3523 int mode, u64 data)
3524{
3525 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3526
3527 return dd->send_egress_err_status_cnt[14];
3528}
3529
3530static u64 access_tx_launch_csr_parity_err_cnt(const struct cntr_entry *entry,
3531 void *context, int vl, int mode,
3532 u64 data)
3533{
3534 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3535
3536 return dd->send_egress_err_status_cnt[13];
3537}
3538
3539static u64 access_tx_illegal_vl_err_cnt(const struct cntr_entry *entry,
3540 void *context, int vl, int mode,
3541 u64 data)
3542{
3543 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3544
3545 return dd->send_egress_err_status_cnt[12];
3546}
3547
3548static u64 access_tx_sbrd_ctl_state_machine_parity_err_cnt(
3549 const struct cntr_entry *entry,
3550 void *context, int vl, int mode, u64 data)
3551{
3552 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3553
3554 return dd->send_egress_err_status_cnt[11];
3555}
3556
3557static u64 access_egress_reserved_10_err_cnt(const struct cntr_entry *entry,
3558 void *context, int vl, int mode,
3559 u64 data)
3560{
3561 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3562
3563 return dd->send_egress_err_status_cnt[10];
3564}
3565
3566static u64 access_egress_reserved_9_err_cnt(const struct cntr_entry *entry,
3567 void *context, int vl, int mode,
3568 u64 data)
3569{
3570 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3571
3572 return dd->send_egress_err_status_cnt[9];
3573}
3574
3575static u64 access_tx_sdma_launch_intf_parity_err_cnt(
3576 const struct cntr_entry *entry,
3577 void *context, int vl, int mode, u64 data)
3578{
3579 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3580
3581 return dd->send_egress_err_status_cnt[8];
3582}
3583
3584static u64 access_tx_pio_launch_intf_parity_err_cnt(
3585 const struct cntr_entry *entry,
3586 void *context, int vl, int mode, u64 data)
3587{
3588 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3589
3590 return dd->send_egress_err_status_cnt[7];
3591}
3592
3593static u64 access_egress_reserved_6_err_cnt(const struct cntr_entry *entry,
3594 void *context, int vl, int mode,
3595 u64 data)
3596{
3597 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3598
3599 return dd->send_egress_err_status_cnt[6];
3600}
3601
3602static u64 access_tx_incorrect_link_state_err_cnt(
3603 const struct cntr_entry *entry,
3604 void *context, int vl, int mode, u64 data)
3605{
3606 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3607
3608 return dd->send_egress_err_status_cnt[5];
3609}
3610
3611static u64 access_tx_linkdown_err_cnt(const struct cntr_entry *entry,
3612 void *context, int vl, int mode,
3613 u64 data)
3614{
3615 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3616
3617 return dd->send_egress_err_status_cnt[4];
3618}
3619
3620static u64 access_tx_egress_fifi_underrun_or_parity_err_cnt(
3621 const struct cntr_entry *entry,
3622 void *context, int vl, int mode, u64 data)
3623{
3624 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3625
3626 return dd->send_egress_err_status_cnt[3];
3627}
3628
3629static u64 access_egress_reserved_2_err_cnt(const struct cntr_entry *entry,
3630 void *context, int vl, int mode,
3631 u64 data)
3632{
3633 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3634
3635 return dd->send_egress_err_status_cnt[2];
3636}
3637
3638static u64 access_tx_pkt_integrity_mem_unc_err_cnt(
3639 const struct cntr_entry *entry,
3640 void *context, int vl, int mode, u64 data)
3641{
3642 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3643
3644 return dd->send_egress_err_status_cnt[1];
3645}
3646
3647static u64 access_tx_pkt_integrity_mem_cor_err_cnt(
3648 const struct cntr_entry *entry,
3649 void *context, int vl, int mode, u64 data)
3650{
3651 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3652
3653 return dd->send_egress_err_status_cnt[0];
3654}
3655
3656/*
3657 * Software counters corresponding to each of the
3658 * error status bits within SendErrStatus
3659 */
3660static u64 access_send_csr_write_bad_addr_err_cnt(
3661 const struct cntr_entry *entry,
3662 void *context, int vl, int mode, u64 data)
3663{
3664 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3665
3666 return dd->send_err_status_cnt[2];
3667}
3668
3669static u64 access_send_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
3670 void *context, int vl,
3671 int mode, u64 data)
3672{
3673 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3674
3675 return dd->send_err_status_cnt[1];
3676}
3677
3678static u64 access_send_csr_parity_cnt(const struct cntr_entry *entry,
3679 void *context, int vl, int mode,
3680 u64 data)
3681{
3682 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3683
3684 return dd->send_err_status_cnt[0];
3685}
3686
3687/*
3688 * Software counters corresponding to each of the
3689 * error status bits within SendCtxtErrStatus
3690 */
3691static u64 access_pio_write_out_of_bounds_err_cnt(
3692 const struct cntr_entry *entry,
3693 void *context, int vl, int mode, u64 data)
3694{
3695 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3696
3697 return dd->sw_ctxt_err_status_cnt[4];
3698}
3699
3700static u64 access_pio_write_overflow_err_cnt(const struct cntr_entry *entry,
3701 void *context, int vl, int mode,
3702 u64 data)
3703{
3704 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3705
3706 return dd->sw_ctxt_err_status_cnt[3];
3707}
3708
3709static u64 access_pio_write_crosses_boundary_err_cnt(
3710 const struct cntr_entry *entry,
3711 void *context, int vl, int mode, u64 data)
3712{
3713 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3714
3715 return dd->sw_ctxt_err_status_cnt[2];
3716}
3717
3718static u64 access_pio_disallowed_packet_err_cnt(const struct cntr_entry *entry,
3719 void *context, int vl,
3720 int mode, u64 data)
3721{
3722 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3723
3724 return dd->sw_ctxt_err_status_cnt[1];
3725}
3726
3727static u64 access_pio_inconsistent_sop_err_cnt(const struct cntr_entry *entry,
3728 void *context, int vl, int mode,
3729 u64 data)
3730{
3731 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3732
3733 return dd->sw_ctxt_err_status_cnt[0];
3734}
3735
3736/*
3737 * Software counters corresponding to each of the
3738 * error status bits within SendDmaEngErrStatus
3739 */
3740static u64 access_sdma_header_request_fifo_cor_err_cnt(
3741 const struct cntr_entry *entry,
3742 void *context, int vl, int mode, u64 data)
3743{
3744 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3745
3746 return dd->sw_send_dma_eng_err_status_cnt[23];
3747}
3748
3749static u64 access_sdma_header_storage_cor_err_cnt(
3750 const struct cntr_entry *entry,
3751 void *context, int vl, int mode, u64 data)
3752{
3753 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3754
3755 return dd->sw_send_dma_eng_err_status_cnt[22];
3756}
3757
3758static u64 access_sdma_packet_tracking_cor_err_cnt(
3759 const struct cntr_entry *entry,
3760 void *context, int vl, int mode, u64 data)
3761{
3762 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3763
3764 return dd->sw_send_dma_eng_err_status_cnt[21];
3765}
3766
3767static u64 access_sdma_assembly_cor_err_cnt(const struct cntr_entry *entry,
3768 void *context, int vl, int mode,
3769 u64 data)
3770{
3771 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3772
3773 return dd->sw_send_dma_eng_err_status_cnt[20];
3774}
3775
3776static u64 access_sdma_desc_table_cor_err_cnt(const struct cntr_entry *entry,
3777 void *context, int vl, int mode,
3778 u64 data)
3779{
3780 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3781
3782 return dd->sw_send_dma_eng_err_status_cnt[19];
3783}
3784
3785static u64 access_sdma_header_request_fifo_unc_err_cnt(
3786 const struct cntr_entry *entry,
3787 void *context, int vl, int mode, u64 data)
3788{
3789 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3790
3791 return dd->sw_send_dma_eng_err_status_cnt[18];
3792}
3793
3794static u64 access_sdma_header_storage_unc_err_cnt(
3795 const struct cntr_entry *entry,
3796 void *context, int vl, int mode, u64 data)
3797{
3798 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3799
3800 return dd->sw_send_dma_eng_err_status_cnt[17];
3801}
3802
3803static u64 access_sdma_packet_tracking_unc_err_cnt(
3804 const struct cntr_entry *entry,
3805 void *context, int vl, int mode, u64 data)
3806{
3807 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3808
3809 return dd->sw_send_dma_eng_err_status_cnt[16];
3810}
3811
3812static u64 access_sdma_assembly_unc_err_cnt(const struct cntr_entry *entry,
3813 void *context, int vl, int mode,
3814 u64 data)
3815{
3816 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3817
3818 return dd->sw_send_dma_eng_err_status_cnt[15];
3819}
3820
3821static u64 access_sdma_desc_table_unc_err_cnt(const struct cntr_entry *entry,
3822 void *context, int vl, int mode,
3823 u64 data)
3824{
3825 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3826
3827 return dd->sw_send_dma_eng_err_status_cnt[14];
3828}
3829
3830static u64 access_sdma_timeout_err_cnt(const struct cntr_entry *entry,
3831 void *context, int vl, int mode,
3832 u64 data)
3833{
3834 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3835
3836 return dd->sw_send_dma_eng_err_status_cnt[13];
3837}
3838
3839static u64 access_sdma_header_length_err_cnt(const struct cntr_entry *entry,
3840 void *context, int vl, int mode,
3841 u64 data)
3842{
3843 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3844
3845 return dd->sw_send_dma_eng_err_status_cnt[12];
3846}
3847
3848static u64 access_sdma_header_address_err_cnt(const struct cntr_entry *entry,
3849 void *context, int vl, int mode,
3850 u64 data)
3851{
3852 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3853
3854 return dd->sw_send_dma_eng_err_status_cnt[11];
3855}
3856
3857static u64 access_sdma_header_select_err_cnt(const struct cntr_entry *entry,
3858 void *context, int vl, int mode,
3859 u64 data)
3860{
3861 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3862
3863 return dd->sw_send_dma_eng_err_status_cnt[10];
3864}
3865
3866static u64 access_sdma_reserved_9_err_cnt(const struct cntr_entry *entry,
3867 void *context, int vl, int mode,
3868 u64 data)
3869{
3870 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3871
3872 return dd->sw_send_dma_eng_err_status_cnt[9];
3873}
3874
3875static u64 access_sdma_packet_desc_overflow_err_cnt(
3876 const struct cntr_entry *entry,
3877 void *context, int vl, int mode, u64 data)
3878{
3879 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3880
3881 return dd->sw_send_dma_eng_err_status_cnt[8];
3882}
3883
3884static u64 access_sdma_length_mismatch_err_cnt(const struct cntr_entry *entry,
3885 void *context, int vl,
3886 int mode, u64 data)
3887{
3888 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3889
3890 return dd->sw_send_dma_eng_err_status_cnt[7];
3891}
3892
3893static u64 access_sdma_halt_err_cnt(const struct cntr_entry *entry,
3894 void *context, int vl, int mode, u64 data)
3895{
3896 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3897
3898 return dd->sw_send_dma_eng_err_status_cnt[6];
3899}
3900
3901static u64 access_sdma_mem_read_err_cnt(const struct cntr_entry *entry,
3902 void *context, int vl, int mode,
3903 u64 data)
3904{
3905 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3906
3907 return dd->sw_send_dma_eng_err_status_cnt[5];
3908}
3909
3910static u64 access_sdma_first_desc_err_cnt(const struct cntr_entry *entry,
3911 void *context, int vl, int mode,
3912 u64 data)
3913{
3914 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3915
3916 return dd->sw_send_dma_eng_err_status_cnt[4];
3917}
3918
3919static u64 access_sdma_tail_out_of_bounds_err_cnt(
3920 const struct cntr_entry *entry,
3921 void *context, int vl, int mode, u64 data)
3922{
3923 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3924
3925 return dd->sw_send_dma_eng_err_status_cnt[3];
3926}
3927
3928static u64 access_sdma_too_long_err_cnt(const struct cntr_entry *entry,
3929 void *context, int vl, int mode,
3930 u64 data)
3931{
3932 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3933
3934 return dd->sw_send_dma_eng_err_status_cnt[2];
3935}
3936
3937static u64 access_sdma_gen_mismatch_err_cnt(const struct cntr_entry *entry,
3938 void *context, int vl, int mode,
3939 u64 data)
3940{
3941 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3942
3943 return dd->sw_send_dma_eng_err_status_cnt[1];
3944}
3945
3946static u64 access_sdma_wrong_dw_err_cnt(const struct cntr_entry *entry,
3947 void *context, int vl, int mode,
3948 u64 data)
3949{
3950 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3951
3952 return dd->sw_send_dma_eng_err_status_cnt[0];
3953}
3954
2b719046
JP		 3955static u64 access_dc_rcv_err_cnt(const struct cntr_entry *entry,
3956 void *context, int vl, int mode,
3957 u64 data)
3958{
3959 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3960
3961 u64 val = 0;
3962 u64 csr = entry->csr;
3963
3964 val = read_write_csr(dd, csr, mode, data);
3965 if (mode == CNTR_MODE_R) {
3966 val = val > CNTR_MAX - dd->sw_rcv_bypass_packet_errors ?
3967 CNTR_MAX : val + dd->sw_rcv_bypass_packet_errors;
3968 } else if (mode == CNTR_MODE_W) {
3969 dd->sw_rcv_bypass_packet_errors = 0;
3970 } else {
3971 dd_dev_err(dd, "Invalid cntr register access mode");
3972 return 0;
3973 }
3974 return val;
3975}
3976
77241056
MM		 3977#define def_access_sw_cpu(cntr) \
3978static u64 access_sw_cpu_##cntr(const struct cntr_entry *entry, \
3979 void *context, int vl, int mode, u64 data) \
3980{ \
3981 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \
4eb06882
DD		 3982 return read_write_cpu(ppd->dd, &ppd->ibport_data.rvp.z_ ##cntr, \
3983 ppd->ibport_data.rvp.cntr, vl, \
77241056
MM		 3984 mode, data); \
3985}
3986
3987def_access_sw_cpu(rc_acks);
3988def_access_sw_cpu(rc_qacks);
3989def_access_sw_cpu(rc_delayed_comp);
3990
3991#define def_access_ibp_counter(cntr) \
3992static u64 access_ibp_##cntr(const struct cntr_entry *entry, \
3993 void *context, int vl, int mode, u64 data) \
3994{ \
3995 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \
3996 \
3997 if (vl != CNTR_INVALID_VL) \
3998 return 0; \
3999 \
4eb06882 4000 return read_write_sw(ppd->dd, &ppd->ibport_data.rvp.n_ ##cntr, \
77241056
MM		 4001 mode, data); \
4002}
4003
4004def_access_ibp_counter(loop_pkts);
4005def_access_ibp_counter(rc_resends);
4006def_access_ibp_counter(rnr_naks);
4007def_access_ibp_counter(other_naks);
4008def_access_ibp_counter(rc_timeouts);
4009def_access_ibp_counter(pkt_drops);
4010def_access_ibp_counter(dmawait);
4011def_access_ibp_counter(rc_seqnak);
4012def_access_ibp_counter(rc_dupreq);
4013def_access_ibp_counter(rdma_seq);
4014def_access_ibp_counter(unaligned);
4015def_access_ibp_counter(seq_naks);
4016
4017static struct cntr_entry dev_cntrs[DEV_CNTR_LAST] = {
4018[C_RCV_OVF] = RXE32_DEV_CNTR_ELEM(RcvOverflow, RCV_BUF_OVFL_CNT, CNTR_SYNTH),
4019[C_RX_TID_FULL] = RXE32_DEV_CNTR_ELEM(RxTIDFullEr, RCV_TID_FULL_ERR_CNT,
4020 CNTR_NORMAL),
4021[C_RX_TID_INVALID] = RXE32_DEV_CNTR_ELEM(RxTIDInvalid, RCV_TID_VALID_ERR_CNT,
4022 CNTR_NORMAL),
4023[C_RX_TID_FLGMS] = RXE32_DEV_CNTR_ELEM(RxTidFLGMs,
4024 RCV_TID_FLOW_GEN_MISMATCH_CNT,
4025 CNTR_NORMAL),
77241056
MM		 4026[C_RX_CTX_EGRS] = RXE32_DEV_CNTR_ELEM(RxCtxEgrS, RCV_CONTEXT_EGR_STALL,
4027 CNTR_NORMAL),
4028[C_RCV_TID_FLSMS] = RXE32_DEV_CNTR_ELEM(RxTidFLSMs,
4029 RCV_TID_FLOW_SEQ_MISMATCH_CNT, CNTR_NORMAL),
4030[C_CCE_PCI_CR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciCrSt,
4031 CCE_PCIE_POSTED_CRDT_STALL_CNT, CNTR_NORMAL),
4032[C_CCE_PCI_TR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciTrSt, CCE_PCIE_TRGT_STALL_CNT,
4033 CNTR_NORMAL),
4034[C_CCE_PIO_WR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePioWrSt, CCE_PIO_WR_STALL_CNT,
4035 CNTR_NORMAL),
4036[C_CCE_ERR_INT] = CCE_INT_DEV_CNTR_ELEM(CceErrInt, CCE_ERR_INT_CNT,
4037 CNTR_NORMAL),
4038[C_CCE_SDMA_INT] = CCE_INT_DEV_CNTR_ELEM(CceSdmaInt, CCE_SDMA_INT_CNT,
4039 CNTR_NORMAL),
4040[C_CCE_MISC_INT] = CCE_INT_DEV_CNTR_ELEM(CceMiscInt, CCE_MISC_INT_CNT,
4041 CNTR_NORMAL),
4042[C_CCE_RCV_AV_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvAvInt, CCE_RCV_AVAIL_INT_CNT,
4043 CNTR_NORMAL),
4044[C_CCE_RCV_URG_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvUrgInt,
4045 CCE_RCV_URGENT_INT_CNT, CNTR_NORMAL),
4046[C_CCE_SEND_CR_INT] = CCE_INT_DEV_CNTR_ELEM(CceSndCrInt,
4047 CCE_SEND_CREDIT_INT_CNT, CNTR_NORMAL),
4048[C_DC_UNC_ERR] = DC_PERF_CNTR(DcUnctblErr, DCC_ERR_UNCORRECTABLE_CNT,
4049 CNTR_SYNTH),
2b719046
JP		 4050[C_DC_RCV_ERR] = CNTR_ELEM("DcRecvErr", DCC_ERR_PORTRCV_ERR_CNT, 0, CNTR_SYNTH,
4051 access_dc_rcv_err_cnt),
77241056
MM		 4052[C_DC_FM_CFG_ERR] = DC_PERF_CNTR(DcFmCfgErr, DCC_ERR_FMCONFIG_ERR_CNT,
4053 CNTR_SYNTH),
4054[C_DC_RMT_PHY_ERR] = DC_PERF_CNTR(DcRmtPhyErr, DCC_ERR_RCVREMOTE_PHY_ERR_CNT,
4055 CNTR_SYNTH),
4056[C_DC_DROPPED_PKT] = DC_PERF_CNTR(DcDroppedPkt, DCC_ERR_DROPPED_PKT_CNT,
4057 CNTR_SYNTH),
4058[C_DC_MC_XMIT_PKTS] = DC_PERF_CNTR(DcMcXmitPkts,
4059 DCC_PRF_PORT_XMIT_MULTICAST_CNT, CNTR_SYNTH),
4060[C_DC_MC_RCV_PKTS] = DC_PERF_CNTR(DcMcRcvPkts,
4061 DCC_PRF_PORT_RCV_MULTICAST_PKT_CNT,
4062 CNTR_SYNTH),
4063[C_DC_XMIT_CERR] = DC_PERF_CNTR(DcXmitCorr,
4064 DCC_PRF_PORT_XMIT_CORRECTABLE_CNT, CNTR_SYNTH),
4065[C_DC_RCV_CERR] = DC_PERF_CNTR(DcRcvCorrCnt, DCC_PRF_PORT_RCV_CORRECTABLE_CNT,
4066 CNTR_SYNTH),
4067[C_DC_RCV_FCC] = DC_PERF_CNTR(DcRxFCntl, DCC_PRF_RX_FLOW_CRTL_CNT,
4068 CNTR_SYNTH),
4069[C_DC_XMIT_FCC] = DC_PERF_CNTR(DcXmitFCntl, DCC_PRF_TX_FLOW_CRTL_CNT,
4070 CNTR_SYNTH),
4071[C_DC_XMIT_FLITS] = DC_PERF_CNTR(DcXmitFlits, DCC_PRF_PORT_XMIT_DATA_CNT,
4072 CNTR_SYNTH),
4073[C_DC_RCV_FLITS] = DC_PERF_CNTR(DcRcvFlits, DCC_PRF_PORT_RCV_DATA_CNT,
4074 CNTR_SYNTH),
4075[C_DC_XMIT_PKTS] = DC_PERF_CNTR(DcXmitPkts, DCC_PRF_PORT_XMIT_PKTS_CNT,
4076 CNTR_SYNTH),
4077[C_DC_RCV_PKTS] = DC_PERF_CNTR(DcRcvPkts, DCC_PRF_PORT_RCV_PKTS_CNT,
4078 CNTR_SYNTH),
4079[C_DC_RX_FLIT_VL] = DC_PERF_CNTR(DcRxFlitVl, DCC_PRF_PORT_VL_RCV_DATA_CNT,
4080 CNTR_SYNTH | CNTR_VL),
4081[C_DC_RX_PKT_VL] = DC_PERF_CNTR(DcRxPktVl, DCC_PRF_PORT_VL_RCV_PKTS_CNT,
4082 CNTR_SYNTH | CNTR_VL),
4083[C_DC_RCV_FCN] = DC_PERF_CNTR(DcRcvFcn, DCC_PRF_PORT_RCV_FECN_CNT, CNTR_SYNTH),
4084[C_DC_RCV_FCN_VL] = DC_PERF_CNTR(DcRcvFcnVl, DCC_PRF_PORT_VL_RCV_FECN_CNT,
4085 CNTR_SYNTH | CNTR_VL),
4086[C_DC_RCV_BCN] = DC_PERF_CNTR(DcRcvBcn, DCC_PRF_PORT_RCV_BECN_CNT, CNTR_SYNTH),
4087[C_DC_RCV_BCN_VL] = DC_PERF_CNTR(DcRcvBcnVl, DCC_PRF_PORT_VL_RCV_BECN_CNT,
4088 CNTR_SYNTH | CNTR_VL),
4089[C_DC_RCV_BBL] = DC_PERF_CNTR(DcRcvBbl, DCC_PRF_PORT_RCV_BUBBLE_CNT,
4090 CNTR_SYNTH),
4091[C_DC_RCV_BBL_VL] = DC_PERF_CNTR(DcRcvBblVl, DCC_PRF_PORT_VL_RCV_BUBBLE_CNT,
4092 CNTR_SYNTH | CNTR_VL),
4093[C_DC_MARK_FECN] = DC_PERF_CNTR(DcMarkFcn, DCC_PRF_PORT_MARK_FECN_CNT,
4094 CNTR_SYNTH),
4095[C_DC_MARK_FECN_VL] = DC_PERF_CNTR(DcMarkFcnVl, DCC_PRF_PORT_VL_MARK_FECN_CNT,
4096 CNTR_SYNTH | CNTR_VL),
4097[C_DC_TOTAL_CRC] =
4098 DC_PERF_CNTR_LCB(DcTotCrc, DC_LCB_ERR_INFO_TOTAL_CRC_ERR,
4099 CNTR_SYNTH),
4100[C_DC_CRC_LN0] = DC_PERF_CNTR_LCB(DcCrcLn0, DC_LCB_ERR_INFO_CRC_ERR_LN0,
4101 CNTR_SYNTH),
4102[C_DC_CRC_LN1] = DC_PERF_CNTR_LCB(DcCrcLn1, DC_LCB_ERR_INFO_CRC_ERR_LN1,
4103 CNTR_SYNTH),
4104[C_DC_CRC_LN2] = DC_PERF_CNTR_LCB(DcCrcLn2, DC_LCB_ERR_INFO_CRC_ERR_LN2,
4105 CNTR_SYNTH),
4106[C_DC_CRC_LN3] = DC_PERF_CNTR_LCB(DcCrcLn3, DC_LCB_ERR_INFO_CRC_ERR_LN3,
4107 CNTR_SYNTH),
4108[C_DC_CRC_MULT_LN] =
4109 DC_PERF_CNTR_LCB(DcMultLn, DC_LCB_ERR_INFO_CRC_ERR_MULTI_LN,
4110 CNTR_SYNTH),
4111[C_DC_TX_REPLAY] = DC_PERF_CNTR_LCB(DcTxReplay, DC_LCB_ERR_INFO_TX_REPLAY_CNT,
4112 CNTR_SYNTH),
4113[C_DC_RX_REPLAY] = DC_PERF_CNTR_LCB(DcRxReplay, DC_LCB_ERR_INFO_RX_REPLAY_CNT,
4114 CNTR_SYNTH),
4115[C_DC_SEQ_CRC_CNT] =
4116 DC_PERF_CNTR_LCB(DcLinkSeqCrc, DC_LCB_ERR_INFO_SEQ_CRC_CNT,
4117 CNTR_SYNTH),
4118[C_DC_ESC0_ONLY_CNT] =
4119 DC_PERF_CNTR_LCB(DcEsc0, DC_LCB_ERR_INFO_ESCAPE_0_ONLY_CNT,
4120 CNTR_SYNTH),
4121[C_DC_ESC0_PLUS1_CNT] =
4122 DC_PERF_CNTR_LCB(DcEsc1, DC_LCB_ERR_INFO_ESCAPE_0_PLUS1_CNT,
4123 CNTR_SYNTH),
4124[C_DC_ESC0_PLUS2_CNT] =
4125 DC_PERF_CNTR_LCB(DcEsc0Plus2, DC_LCB_ERR_INFO_ESCAPE_0_PLUS2_CNT,
4126 CNTR_SYNTH),
4127[C_DC_REINIT_FROM_PEER_CNT] =
4128 DC_PERF_CNTR_LCB(DcReinitPeer, DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT,
4129 CNTR_SYNTH),
4130[C_DC_SBE_CNT] = DC_PERF_CNTR_LCB(DcSbe, DC_LCB_ERR_INFO_SBE_CNT,
4131 CNTR_SYNTH),
4132[C_DC_MISC_FLG_CNT] =
4133 DC_PERF_CNTR_LCB(DcMiscFlg, DC_LCB_ERR_INFO_MISC_FLG_CNT,
4134 CNTR_SYNTH),
4135[C_DC_PRF_GOOD_LTP_CNT] =
4136 DC_PERF_CNTR_LCB(DcGoodLTP, DC_LCB_PRF_GOOD_LTP_CNT, CNTR_SYNTH),
4137[C_DC_PRF_ACCEPTED_LTP_CNT] =
4138 DC_PERF_CNTR_LCB(DcAccLTP, DC_LCB_PRF_ACCEPTED_LTP_CNT,
4139 CNTR_SYNTH),
4140[C_DC_PRF_RX_FLIT_CNT] =
4141 DC_PERF_CNTR_LCB(DcPrfRxFlit, DC_LCB_PRF_RX_FLIT_CNT, CNTR_SYNTH),
4142[C_DC_PRF_TX_FLIT_CNT] =
4143 DC_PERF_CNTR_LCB(DcPrfTxFlit, DC_LCB_PRF_TX_FLIT_CNT, CNTR_SYNTH),
4144[C_DC_PRF_CLK_CNTR] =
4145 DC_PERF_CNTR_LCB(DcPrfClk, DC_LCB_PRF_CLK_CNTR, CNTR_SYNTH),
4146[C_DC_PG_DBG_FLIT_CRDTS_CNT] =
4147 DC_PERF_CNTR_LCB(DcFltCrdts, DC_LCB_PG_DBG_FLIT_CRDTS_CNT, CNTR_SYNTH),
4148[C_DC_PG_STS_PAUSE_COMPLETE_CNT] =
4149 DC_PERF_CNTR_LCB(DcPauseComp, DC_LCB_PG_STS_PAUSE_COMPLETE_CNT,
4150 CNTR_SYNTH),
4151[C_DC_PG_STS_TX_SBE_CNT] =
4152 DC_PERF_CNTR_LCB(DcStsTxSbe, DC_LCB_PG_STS_TX_SBE_CNT, CNTR_SYNTH),
4153[C_DC_PG_STS_TX_MBE_CNT] =
4154 DC_PERF_CNTR_LCB(DcStsTxMbe, DC_LCB_PG_STS_TX_MBE_CNT,
4155 CNTR_SYNTH),
4156[C_SW_CPU_INTR] = CNTR_ELEM("Intr", 0, 0, CNTR_NORMAL,
4157 access_sw_cpu_intr),
4158[C_SW_CPU_RCV_LIM] = CNTR_ELEM("RcvLimit", 0, 0, CNTR_NORMAL,
4159 access_sw_cpu_rcv_limit),
4160[C_SW_VTX_WAIT] = CNTR_ELEM("vTxWait", 0, 0, CNTR_NORMAL,
4161 access_sw_vtx_wait),
4162[C_SW_PIO_WAIT] = CNTR_ELEM("PioWait", 0, 0, CNTR_NORMAL,
4163 access_sw_pio_wait),
14553ca1
MM		 4164[C_SW_PIO_DRAIN] = CNTR_ELEM("PioDrain", 0, 0, CNTR_NORMAL,
4165 access_sw_pio_drain),
77241056
MM		 4166[C_SW_KMEM_WAIT] = CNTR_ELEM("KmemWait", 0, 0, CNTR_NORMAL,
4167 access_sw_kmem_wait),
b421922e
DL		 4168[C_SW_SEND_SCHED] = CNTR_ELEM("SendSched", 0, 0, CNTR_NORMAL,
4169 access_sw_send_schedule),
a699c6c2
VM		 4170[C_SDMA_DESC_FETCHED_CNT] = CNTR_ELEM("SDEDscFdCn",
4171 SEND_DMA_DESC_FETCHED_CNT, 0,
4172 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4173 dev_access_u32_csr),
4174[C_SDMA_INT_CNT] = CNTR_ELEM("SDMAInt", 0, 0,
4175 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4176 access_sde_int_cnt),
4177[C_SDMA_ERR_CNT] = CNTR_ELEM("SDMAErrCt", 0, 0,
4178 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4179 access_sde_err_cnt),
4180[C_SDMA_IDLE_INT_CNT] = CNTR_ELEM("SDMAIdInt", 0, 0,
4181 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4182 access_sde_idle_int_cnt),
4183[C_SDMA_PROGRESS_INT_CNT] = CNTR_ELEM("SDMAPrIntCn", 0, 0,
4184 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4185 access_sde_progress_int_cnt),
2c5b521a
JR		 4186/* MISC_ERR_STATUS */
4187[C_MISC_PLL_LOCK_FAIL_ERR] = CNTR_ELEM("MISC_PLL_LOCK_FAIL_ERR", 0, 0,
4188 CNTR_NORMAL,
4189 access_misc_pll_lock_fail_err_cnt),
4190[C_MISC_MBIST_FAIL_ERR] = CNTR_ELEM("MISC_MBIST_FAIL_ERR", 0, 0,
4191 CNTR_NORMAL,
4192 access_misc_mbist_fail_err_cnt),
4193[C_MISC_INVALID_EEP_CMD_ERR] = CNTR_ELEM("MISC_INVALID_EEP_CMD_ERR", 0, 0,
4194 CNTR_NORMAL,
4195 access_misc_invalid_eep_cmd_err_cnt),
4196[C_MISC_EFUSE_DONE_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_DONE_PARITY_ERR", 0, 0,
4197 CNTR_NORMAL,
4198 access_misc_efuse_done_parity_err_cnt),
4199[C_MISC_EFUSE_WRITE_ERR] = CNTR_ELEM("MISC_EFUSE_WRITE_ERR", 0, 0,
4200 CNTR_NORMAL,
4201 access_misc_efuse_write_err_cnt),
4202[C_MISC_EFUSE_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_EFUSE_READ_BAD_ADDR_ERR", 0,
4203 0, CNTR_NORMAL,
4204 access_misc_efuse_read_bad_addr_err_cnt),
4205[C_MISC_EFUSE_CSR_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_CSR_PARITY_ERR", 0, 0,
4206 CNTR_NORMAL,
4207 access_misc_efuse_csr_parity_err_cnt),
4208[C_MISC_FW_AUTH_FAILED_ERR] = CNTR_ELEM("MISC_FW_AUTH_FAILED_ERR", 0, 0,
4209 CNTR_NORMAL,
4210 access_misc_fw_auth_failed_err_cnt),
4211[C_MISC_KEY_MISMATCH_ERR] = CNTR_ELEM("MISC_KEY_MISMATCH_ERR", 0, 0,
4212 CNTR_NORMAL,
4213 access_misc_key_mismatch_err_cnt),
4214[C_MISC_SBUS_WRITE_FAILED_ERR] = CNTR_ELEM("MISC_SBUS_WRITE_FAILED_ERR", 0, 0,
4215 CNTR_NORMAL,
4216 access_misc_sbus_write_failed_err_cnt),
4217[C_MISC_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_WRITE_BAD_ADDR_ERR", 0, 0,
4218 CNTR_NORMAL,
4219 access_misc_csr_write_bad_addr_err_cnt),
4220[C_MISC_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_READ_BAD_ADDR_ERR", 0, 0,
4221 CNTR_NORMAL,
4222 access_misc_csr_read_bad_addr_err_cnt),
4223[C_MISC_CSR_PARITY_ERR] = CNTR_ELEM("MISC_CSR_PARITY_ERR", 0, 0,
4224 CNTR_NORMAL,
4225 access_misc_csr_parity_err_cnt),
4226/* CceErrStatus */
4227[C_CCE_ERR_STATUS_AGGREGATED_CNT] = CNTR_ELEM("CceErrStatusAggregatedCnt", 0, 0,
4228 CNTR_NORMAL,
4229 access_sw_cce_err_status_aggregated_cnt),
4230[C_CCE_MSIX_CSR_PARITY_ERR] = CNTR_ELEM("CceMsixCsrParityErr", 0, 0,
4231 CNTR_NORMAL,
4232 access_cce_msix_csr_parity_err_cnt),
4233[C_CCE_INT_MAP_UNC_ERR] = CNTR_ELEM("CceIntMapUncErr", 0, 0,
4234 CNTR_NORMAL,
4235 access_cce_int_map_unc_err_cnt),
4236[C_CCE_INT_MAP_COR_ERR] = CNTR_ELEM("CceIntMapCorErr", 0, 0,
4237 CNTR_NORMAL,
4238 access_cce_int_map_cor_err_cnt),
4239[C_CCE_MSIX_TABLE_UNC_ERR] = CNTR_ELEM("CceMsixTableUncErr", 0, 0,
4240 CNTR_NORMAL,
4241 access_cce_msix_table_unc_err_cnt),
4242[C_CCE_MSIX_TABLE_COR_ERR] = CNTR_ELEM("CceMsixTableCorErr", 0, 0,
4243 CNTR_NORMAL,
4244 access_cce_msix_table_cor_err_cnt),
4245[C_CCE_RXDMA_CONV_FIFO_PARITY_ERR] = CNTR_ELEM("CceRxdmaConvFifoParityErr", 0,
4246 0, CNTR_NORMAL,
4247 access_cce_rxdma_conv_fifo_parity_err_cnt),
4248[C_CCE_RCPL_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceRcplAsyncFifoParityErr", 0,
4249 0, CNTR_NORMAL,
4250 access_cce_rcpl_async_fifo_parity_err_cnt),
4251[C_CCE_SEG_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceSegWriteBadAddrErr", 0, 0,
4252 CNTR_NORMAL,
4253 access_cce_seg_write_bad_addr_err_cnt),
4254[C_CCE_SEG_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceSegReadBadAddrErr", 0, 0,
4255 CNTR_NORMAL,
4256 access_cce_seg_read_bad_addr_err_cnt),
4257[C_LA_TRIGGERED] = CNTR_ELEM("Cce LATriggered", 0, 0,
4258 CNTR_NORMAL,
4259 access_la_triggered_cnt),
4260[C_CCE_TRGT_CPL_TIMEOUT_ERR] = CNTR_ELEM("CceTrgtCplTimeoutErr", 0, 0,
4261 CNTR_NORMAL,
4262 access_cce_trgt_cpl_timeout_err_cnt),
4263[C_PCIC_RECEIVE_PARITY_ERR] = CNTR_ELEM("PcicReceiveParityErr", 0, 0,
4264 CNTR_NORMAL,
4265 access_pcic_receive_parity_err_cnt),
4266[C_PCIC_TRANSMIT_BACK_PARITY_ERR] = CNTR_ELEM("PcicTransmitBackParityErr", 0, 0,
4267 CNTR_NORMAL,
4268 access_pcic_transmit_back_parity_err_cnt),
4269[C_PCIC_TRANSMIT_FRONT_PARITY_ERR] = CNTR_ELEM("PcicTransmitFrontParityErr", 0,
4270 0, CNTR_NORMAL,
4271 access_pcic_transmit_front_parity_err_cnt),
4272[C_PCIC_CPL_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicCplDatQUncErr", 0, 0,
4273 CNTR_NORMAL,
4274 access_pcic_cpl_dat_q_unc_err_cnt),
4275[C_PCIC_CPL_HD_Q_UNC_ERR] = CNTR_ELEM("PcicCplHdQUncErr", 0, 0,
4276 CNTR_NORMAL,
4277 access_pcic_cpl_hd_q_unc_err_cnt),
4278[C_PCIC_POST_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicPostDatQUncErr", 0, 0,
4279 CNTR_NORMAL,
4280 access_pcic_post_dat_q_unc_err_cnt),
4281[C_PCIC_POST_HD_Q_UNC_ERR] = CNTR_ELEM("PcicPostHdQUncErr", 0, 0,
4282 CNTR_NORMAL,
4283 access_pcic_post_hd_q_unc_err_cnt),
4284[C_PCIC_RETRY_SOT_MEM_UNC_ERR] = CNTR_ELEM("PcicRetrySotMemUncErr", 0, 0,
4285 CNTR_NORMAL,
4286 access_pcic_retry_sot_mem_unc_err_cnt),
4287[C_PCIC_RETRY_MEM_UNC_ERR] = CNTR_ELEM("PcicRetryMemUncErr", 0, 0,
4288 CNTR_NORMAL,
4289 access_pcic_retry_mem_unc_err),
4290[C_PCIC_N_POST_DAT_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostDatQParityErr", 0, 0,
4291 CNTR_NORMAL,
4292 access_pcic_n_post_dat_q_parity_err_cnt),
4293[C_PCIC_N_POST_H_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostHQParityErr", 0, 0,
4294 CNTR_NORMAL,
4295 access_pcic_n_post_h_q_parity_err_cnt),
4296[C_PCIC_CPL_DAT_Q_COR_ERR] = CNTR_ELEM("PcicCplDatQCorErr", 0, 0,
4297 CNTR_NORMAL,
4298 access_pcic_cpl_dat_q_cor_err_cnt),
4299[C_PCIC_CPL_HD_Q_COR_ERR] = CNTR_ELEM("PcicCplHdQCorErr", 0, 0,
4300 CNTR_NORMAL,
4301 access_pcic_cpl_hd_q_cor_err_cnt),
4302[C_PCIC_POST_DAT_Q_COR_ERR] = CNTR_ELEM("PcicPostDatQCorErr", 0, 0,
4303 CNTR_NORMAL,
4304 access_pcic_post_dat_q_cor_err_cnt),
4305[C_PCIC_POST_HD_Q_COR_ERR] = CNTR_ELEM("PcicPostHdQCorErr", 0, 0,
4306 CNTR_NORMAL,
4307 access_pcic_post_hd_q_cor_err_cnt),
4308[C_PCIC_RETRY_SOT_MEM_COR_ERR] = CNTR_ELEM("PcicRetrySotMemCorErr", 0, 0,
4309 CNTR_NORMAL,
4310 access_pcic_retry_sot_mem_cor_err_cnt),
4311[C_PCIC_RETRY_MEM_COR_ERR] = CNTR_ELEM("PcicRetryMemCorErr", 0, 0,
4312 CNTR_NORMAL,
4313 access_pcic_retry_mem_cor_err_cnt),
4314[C_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERR] = CNTR_ELEM(
4315 "CceCli1AsyncFifoDbgParityError", 0, 0,
4316 CNTR_NORMAL,
4317 access_cce_cli1_async_fifo_dbg_parity_err_cnt),
4318[C_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERR] = CNTR_ELEM(
4319 "CceCli1AsyncFifoRxdmaParityError", 0, 0,
4320 CNTR_NORMAL,
4321 access_cce_cli1_async_fifo_rxdma_parity_err_cnt
4322 ),
4323[C_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR] = CNTR_ELEM(
4324 "CceCli1AsyncFifoSdmaHdParityErr", 0, 0,
4325 CNTR_NORMAL,
4326 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt),
4327[C_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR] = CNTR_ELEM(
4328 "CceCli1AsyncFifoPioCrdtParityErr", 0, 0,
4329 CNTR_NORMAL,
4330 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt),
4331[C_CCE_CLI2_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceCli2AsyncFifoParityErr", 0,
4332 0, CNTR_NORMAL,
4333 access_cce_cli2_async_fifo_parity_err_cnt),
4334[C_CCE_CSR_CFG_BUS_PARITY_ERR] = CNTR_ELEM("CceCsrCfgBusParityErr", 0, 0,
4335 CNTR_NORMAL,
4336 access_cce_csr_cfg_bus_parity_err_cnt),
4337[C_CCE_CLI0_ASYNC_FIFO_PARTIY_ERR] = CNTR_ELEM("CceCli0AsyncFifoParityErr", 0,
4338 0, CNTR_NORMAL,
4339 access_cce_cli0_async_fifo_parity_err_cnt),
4340[C_CCE_RSPD_DATA_PARITY_ERR] = CNTR_ELEM("CceRspdDataParityErr", 0, 0,
4341 CNTR_NORMAL,
4342 access_cce_rspd_data_parity_err_cnt),
4343[C_CCE_TRGT_ACCESS_ERR] = CNTR_ELEM("CceTrgtAccessErr", 0, 0,
4344 CNTR_NORMAL,
4345 access_cce_trgt_access_err_cnt),
4346[C_CCE_TRGT_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceTrgtAsyncFifoParityErr", 0,
4347 0, CNTR_NORMAL,
4348 access_cce_trgt_async_fifo_parity_err_cnt),
4349[C_CCE_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrWriteBadAddrErr", 0, 0,
4350 CNTR_NORMAL,
4351 access_cce_csr_write_bad_addr_err_cnt),
4352[C_CCE_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrReadBadAddrErr", 0, 0,
4353 CNTR_NORMAL,
4354 access_cce_csr_read_bad_addr_err_cnt),
4355[C_CCE_CSR_PARITY_ERR] = CNTR_ELEM("CceCsrParityErr", 0, 0,
4356 CNTR_NORMAL,
4357 access_ccs_csr_parity_err_cnt),
4358
4359/* RcvErrStatus */
4360[C_RX_CSR_PARITY_ERR] = CNTR_ELEM("RxCsrParityErr", 0, 0,
4361 CNTR_NORMAL,
4362 access_rx_csr_parity_err_cnt),
4363[C_RX_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrWriteBadAddrErr", 0, 0,
4364 CNTR_NORMAL,
4365 access_rx_csr_write_bad_addr_err_cnt),
4366[C_RX_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrReadBadAddrErr", 0, 0,
4367 CNTR_NORMAL,
4368 access_rx_csr_read_bad_addr_err_cnt),
4369[C_RX_DMA_CSR_UNC_ERR] = CNTR_ELEM("RxDmaCsrUncErr", 0, 0,
4370 CNTR_NORMAL,
4371 access_rx_dma_csr_unc_err_cnt),
4372[C_RX_DMA_DQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaDqFsmEncodingErr", 0, 0,
4373 CNTR_NORMAL,
4374 access_rx_dma_dq_fsm_encoding_err_cnt),
4375[C_RX_DMA_EQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaEqFsmEncodingErr", 0, 0,
4376 CNTR_NORMAL,
4377 access_rx_dma_eq_fsm_encoding_err_cnt),
4378[C_RX_DMA_CSR_PARITY_ERR] = CNTR_ELEM("RxDmaCsrParityErr", 0, 0,
4379 CNTR_NORMAL,
4380 access_rx_dma_csr_parity_err_cnt),
4381[C_RX_RBUF_DATA_COR_ERR] = CNTR_ELEM("RxRbufDataCorErr", 0, 0,
4382 CNTR_NORMAL,
4383 access_rx_rbuf_data_cor_err_cnt),
4384[C_RX_RBUF_DATA_UNC_ERR] = CNTR_ELEM("RxRbufDataUncErr", 0, 0,
4385 CNTR_NORMAL,
4386 access_rx_rbuf_data_unc_err_cnt),
4387[C_RX_DMA_DATA_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaDataFifoRdCorErr", 0, 0,
4388 CNTR_NORMAL,
4389 access_rx_dma_data_fifo_rd_cor_err_cnt),
4390[C_RX_DMA_DATA_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaDataFifoRdUncErr", 0, 0,
4391 CNTR_NORMAL,
4392 access_rx_dma_data_fifo_rd_unc_err_cnt),
4393[C_RX_DMA_HDR_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaHdrFifoRdCorErr", 0, 0,
4394 CNTR_NORMAL,
4395 access_rx_dma_hdr_fifo_rd_cor_err_cnt),
4396[C_RX_DMA_HDR_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaHdrFifoRdUncErr", 0, 0,
4397 CNTR_NORMAL,
4398 access_rx_dma_hdr_fifo_rd_unc_err_cnt),
4399[C_RX_RBUF_DESC_PART2_COR_ERR] = CNTR_ELEM("RxRbufDescPart2CorErr", 0, 0,
4400 CNTR_NORMAL,
4401 access_rx_rbuf_desc_part2_cor_err_cnt),
4402[C_RX_RBUF_DESC_PART2_UNC_ERR] = CNTR_ELEM("RxRbufDescPart2UncErr", 0, 0,
4403 CNTR_NORMAL,
4404 access_rx_rbuf_desc_part2_unc_err_cnt),
4405[C_RX_RBUF_DESC_PART1_COR_ERR] = CNTR_ELEM("RxRbufDescPart1CorErr", 0, 0,
4406 CNTR_NORMAL,
4407 access_rx_rbuf_desc_part1_cor_err_cnt),
4408[C_RX_RBUF_DESC_PART1_UNC_ERR] = CNTR_ELEM("RxRbufDescPart1UncErr", 0, 0,
4409 CNTR_NORMAL,
4410 access_rx_rbuf_desc_part1_unc_err_cnt),
4411[C_RX_HQ_INTR_FSM_ERR] = CNTR_ELEM("RxHqIntrFsmErr", 0, 0,
4412 CNTR_NORMAL,
4413 access_rx_hq_intr_fsm_err_cnt),
4414[C_RX_HQ_INTR_CSR_PARITY_ERR] = CNTR_ELEM("RxHqIntrCsrParityErr", 0, 0,
4415 CNTR_NORMAL,
4416 access_rx_hq_intr_csr_parity_err_cnt),
4417[C_RX_LOOKUP_CSR_PARITY_ERR] = CNTR_ELEM("RxLookupCsrParityErr", 0, 0,
4418 CNTR_NORMAL,
4419 access_rx_lookup_csr_parity_err_cnt),
4420[C_RX_LOOKUP_RCV_ARRAY_COR_ERR] = CNTR_ELEM("RxLookupRcvArrayCorErr", 0, 0,
4421 CNTR_NORMAL,
4422 access_rx_lookup_rcv_array_cor_err_cnt),
4423[C_RX_LOOKUP_RCV_ARRAY_UNC_ERR] = CNTR_ELEM("RxLookupRcvArrayUncErr", 0, 0,
4424 CNTR_NORMAL,
4425 access_rx_lookup_rcv_array_unc_err_cnt),
4426[C_RX_LOOKUP_DES_PART2_PARITY_ERR] = CNTR_ELEM("RxLookupDesPart2ParityErr", 0,
4427 0, CNTR_NORMAL,
4428 access_rx_lookup_des_part2_parity_err_cnt),
4429[C_RX_LOOKUP_DES_PART1_UNC_COR_ERR] = CNTR_ELEM("RxLookupDesPart1UncCorErr", 0,
4430 0, CNTR_NORMAL,
4431 access_rx_lookup_des_part1_unc_cor_err_cnt),
4432[C_RX_LOOKUP_DES_PART1_UNC_ERR] = CNTR_ELEM("RxLookupDesPart1UncErr", 0, 0,
4433 CNTR_NORMAL,
4434 access_rx_lookup_des_part1_unc_err_cnt),
4435[C_RX_RBUF_NEXT_FREE_BUF_COR_ERR] = CNTR_ELEM("RxRbufNextFreeBufCorErr", 0, 0,
4436 CNTR_NORMAL,
4437 access_rx_rbuf_next_free_buf_cor_err_cnt),
4438[C_RX_RBUF_NEXT_FREE_BUF_UNC_ERR] = CNTR_ELEM("RxRbufNextFreeBufUncErr", 0, 0,
4439 CNTR_NORMAL,
4440 access_rx_rbuf_next_free_buf_unc_err_cnt),
4441[C_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR] = CNTR_ELEM(
4442 "RxRbufFlInitWrAddrParityErr", 0, 0,
4443 CNTR_NORMAL,
4444 access_rbuf_fl_init_wr_addr_parity_err_cnt),
4445[C_RX_RBUF_FL_INITDONE_PARITY_ERR] = CNTR_ELEM("RxRbufFlInitdoneParityErr", 0,
4446 0, CNTR_NORMAL,
4447 access_rx_rbuf_fl_initdone_parity_err_cnt),
4448[C_RX_RBUF_FL_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlWrAddrParityErr", 0,
4449 0, CNTR_NORMAL,
4450 access_rx_rbuf_fl_write_addr_parity_err_cnt),
4451[C_RX_RBUF_FL_RD_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlRdAddrParityErr", 0, 0,
4452 CNTR_NORMAL,
4453 access_rx_rbuf_fl_rd_addr_parity_err_cnt),
4454[C_RX_RBUF_EMPTY_ERR] = CNTR_ELEM("RxRbufEmptyErr", 0, 0,
4455 CNTR_NORMAL,
4456 access_rx_rbuf_empty_err_cnt),
4457[C_RX_RBUF_FULL_ERR] = CNTR_ELEM("RxRbufFullErr", 0, 0,
4458 CNTR_NORMAL,
4459 access_rx_rbuf_full_err_cnt),
4460[C_RX_RBUF_BAD_LOOKUP_ERR] = CNTR_ELEM("RxRBufBadLookupErr", 0, 0,
4461 CNTR_NORMAL,
4462 access_rbuf_bad_lookup_err_cnt),
4463[C_RX_RBUF_CTX_ID_PARITY_ERR] = CNTR_ELEM("RxRbufCtxIdParityErr", 0, 0,
4464 CNTR_NORMAL,
4465 access_rbuf_ctx_id_parity_err_cnt),
4466[C_RX_RBUF_CSR_QEOPDW_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEOPDWParityErr", 0, 0,
4467 CNTR_NORMAL,
4468 access_rbuf_csr_qeopdw_parity_err_cnt),
4469[C_RX_RBUF_CSR_Q_NUM_OF_PKT_PARITY_ERR] = CNTR_ELEM(
4470 "RxRbufCsrQNumOfPktParityErr", 0, 0,
4471 CNTR_NORMAL,
4472 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt),
4473[C_RX_RBUF_CSR_Q_T1_PTR_PARITY_ERR] = CNTR_ELEM(
4474 "RxRbufCsrQTlPtrParityErr", 0, 0,
4475 CNTR_NORMAL,
4476 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt),
4477[C_RX_RBUF_CSR_Q_HD_PTR_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQHdPtrParityErr", 0,
4478 0, CNTR_NORMAL,
4479 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt),
4480[C_RX_RBUF_CSR_Q_VLD_BIT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQVldBitParityErr", 0,
4481 0, CNTR_NORMAL,
4482 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt),
4483[C_RX_RBUF_CSR_Q_NEXT_BUF_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQNextBufParityErr",
4484 0, 0, CNTR_NORMAL,
4485 access_rx_rbuf_csr_q_next_buf_parity_err_cnt),
4486[C_RX_RBUF_CSR_Q_ENT_CNT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEntCntParityErr", 0,
4487 0, CNTR_NORMAL,
4488 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt),
4489[C_RX_RBUF_CSR_Q_HEAD_BUF_NUM_PARITY_ERR] = CNTR_ELEM(
4490 "RxRbufCsrQHeadBufNumParityErr", 0, 0,
4491 CNTR_NORMAL,
4492 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt),
4493[C_RX_RBUF_BLOCK_LIST_READ_COR_ERR] = CNTR_ELEM("RxRbufBlockListReadCorErr", 0,
4494 0, CNTR_NORMAL,
4495 access_rx_rbuf_block_list_read_cor_err_cnt),
4496[C_RX_RBUF_BLOCK_LIST_READ_UNC_ERR] = CNTR_ELEM("RxRbufBlockListReadUncErr", 0,
4497 0, CNTR_NORMAL,
4498 access_rx_rbuf_block_list_read_unc_err_cnt),
4499[C_RX_RBUF_LOOKUP_DES_COR_ERR] = CNTR_ELEM("RxRbufLookupDesCorErr", 0, 0,
4500 CNTR_NORMAL,
4501 access_rx_rbuf_lookup_des_cor_err_cnt),
4502[C_RX_RBUF_LOOKUP_DES_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesUncErr", 0, 0,
4503 CNTR_NORMAL,
4504 access_rx_rbuf_lookup_des_unc_err_cnt),
4505[C_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR] = CNTR_ELEM(
4506 "RxRbufLookupDesRegUncCorErr", 0, 0,
4507 CNTR_NORMAL,
4508 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt),
4509[C_RX_RBUF_LOOKUP_DES_REG_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesRegUncErr", 0, 0,
4510 CNTR_NORMAL,
4511 access_rx_rbuf_lookup_des_reg_unc_err_cnt),
4512[C_RX_RBUF_FREE_LIST_COR_ERR] = CNTR_ELEM("RxRbufFreeListCorErr", 0, 0,
4513 CNTR_NORMAL,
4514 access_rx_rbuf_free_list_cor_err_cnt),
4515[C_RX_RBUF_FREE_LIST_UNC_ERR] = CNTR_ELEM("RxRbufFreeListUncErr", 0, 0,
4516 CNTR_NORMAL,
4517 access_rx_rbuf_free_list_unc_err_cnt),
4518[C_RX_RCV_FSM_ENCODING_ERR] = CNTR_ELEM("RxRcvFsmEncodingErr", 0, 0,
4519 CNTR_NORMAL,
4520 access_rx_rcv_fsm_encoding_err_cnt),
4521[C_RX_DMA_FLAG_COR_ERR] = CNTR_ELEM("RxDmaFlagCorErr", 0, 0,
4522 CNTR_NORMAL,
4523 access_rx_dma_flag_cor_err_cnt),
4524[C_RX_DMA_FLAG_UNC_ERR] = CNTR_ELEM("RxDmaFlagUncErr", 0, 0,
4525 CNTR_NORMAL,
4526 access_rx_dma_flag_unc_err_cnt),
4527[C_RX_DC_SOP_EOP_PARITY_ERR] = CNTR_ELEM("RxDcSopEopParityErr", 0, 0,
4528 CNTR_NORMAL,
4529 access_rx_dc_sop_eop_parity_err_cnt),
4530[C_RX_RCV_CSR_PARITY_ERR] = CNTR_ELEM("RxRcvCsrParityErr", 0, 0,
4531 CNTR_NORMAL,
4532 access_rx_rcv_csr_parity_err_cnt),
4533[C_RX_RCV_QP_MAP_TABLE_COR_ERR] = CNTR_ELEM("RxRcvQpMapTableCorErr", 0, 0,
4534 CNTR_NORMAL,
4535 access_rx_rcv_qp_map_table_cor_err_cnt),
4536[C_RX_RCV_QP_MAP_TABLE_UNC_ERR] = CNTR_ELEM("RxRcvQpMapTableUncErr", 0, 0,
4537 CNTR_NORMAL,
4538 access_rx_rcv_qp_map_table_unc_err_cnt),
4539[C_RX_RCV_DATA_COR_ERR] = CNTR_ELEM("RxRcvDataCorErr", 0, 0,
4540 CNTR_NORMAL,
4541 access_rx_rcv_data_cor_err_cnt),
4542[C_RX_RCV_DATA_UNC_ERR] = CNTR_ELEM("RxRcvDataUncErr", 0, 0,
4543 CNTR_NORMAL,
4544 access_rx_rcv_data_unc_err_cnt),
4545[C_RX_RCV_HDR_COR_ERR] = CNTR_ELEM("RxRcvHdrCorErr", 0, 0,
4546 CNTR_NORMAL,
4547 access_rx_rcv_hdr_cor_err_cnt),
4548[C_RX_RCV_HDR_UNC_ERR] = CNTR_ELEM("RxRcvHdrUncErr", 0, 0,
4549 CNTR_NORMAL,
4550 access_rx_rcv_hdr_unc_err_cnt),
4551[C_RX_DC_INTF_PARITY_ERR] = CNTR_ELEM("RxDcIntfParityErr", 0, 0,
4552 CNTR_NORMAL,
4553 access_rx_dc_intf_parity_err_cnt),
4554[C_RX_DMA_CSR_COR_ERR] = CNTR_ELEM("RxDmaCsrCorErr", 0, 0,
4555 CNTR_NORMAL,
4556 access_rx_dma_csr_cor_err_cnt),
4557/* SendPioErrStatus */
4558[C_PIO_PEC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPecSopHeadParityErr", 0, 0,
4559 CNTR_NORMAL,
4560 access_pio_pec_sop_head_parity_err_cnt),
4561[C_PIO_PCC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPccSopHeadParityErr", 0, 0,
4562 CNTR_NORMAL,
4563 access_pio_pcc_sop_head_parity_err_cnt),
4564[C_PIO_LAST_RETURNED_CNT_PARITY_ERR] = CNTR_ELEM("PioLastReturnedCntParityErr",
4565 0, 0, CNTR_NORMAL,
4566 access_pio_last_returned_cnt_parity_err_cnt),
4567[C_PIO_CURRENT_FREE_CNT_PARITY_ERR] = CNTR_ELEM("PioCurrentFreeCntParityErr", 0,
4568 0, CNTR_NORMAL,
4569 access_pio_current_free_cnt_parity_err_cnt),
4570[C_PIO_RSVD_31_ERR] = CNTR_ELEM("Pio Reserved 31", 0, 0,
4571 CNTR_NORMAL,
4572 access_pio_reserved_31_err_cnt),
4573[C_PIO_RSVD_30_ERR] = CNTR_ELEM("Pio Reserved 30", 0, 0,
4574 CNTR_NORMAL,
4575 access_pio_reserved_30_err_cnt),
4576[C_PIO_PPMC_SOP_LEN_ERR] = CNTR_ELEM("PioPpmcSopLenErr", 0, 0,
4577 CNTR_NORMAL,
4578 access_pio_ppmc_sop_len_err_cnt),
4579[C_PIO_PPMC_BQC_MEM_PARITY_ERR] = CNTR_ELEM("PioPpmcBqcMemParityErr", 0, 0,
4580 CNTR_NORMAL,
4581 access_pio_ppmc_bqc_mem_parity_err_cnt),
4582[C_PIO_VL_FIFO_PARITY_ERR] = CNTR_ELEM("PioVlFifoParityErr", 0, 0,
4583 CNTR_NORMAL,
4584 access_pio_vl_fifo_parity_err_cnt),
4585[C_PIO_VLF_SOP_PARITY_ERR] = CNTR_ELEM("PioVlfSopParityErr", 0, 0,
4586 CNTR_NORMAL,
4587 access_pio_vlf_sop_parity_err_cnt),
4588[C_PIO_VLF_V1_LEN_PARITY_ERR] = CNTR_ELEM("PioVlfVlLenParityErr", 0, 0,
4589 CNTR_NORMAL,
4590 access_pio_vlf_v1_len_parity_err_cnt),
4591[C_PIO_BLOCK_QW_COUNT_PARITY_ERR] = CNTR_ELEM("PioBlockQwCountParityErr", 0, 0,
4592 CNTR_NORMAL,
4593 access_pio_block_qw_count_parity_err_cnt),
4594[C_PIO_WRITE_QW_VALID_PARITY_ERR] = CNTR_ELEM("PioWriteQwValidParityErr", 0, 0,
4595 CNTR_NORMAL,
4596 access_pio_write_qw_valid_parity_err_cnt),
4597[C_PIO_STATE_MACHINE_ERR] = CNTR_ELEM("PioStateMachineErr", 0, 0,
4598 CNTR_NORMAL,
4599 access_pio_state_machine_err_cnt),
4600[C_PIO_WRITE_DATA_PARITY_ERR] = CNTR_ELEM("PioWriteDataParityErr", 0, 0,
4601 CNTR_NORMAL,
4602 access_pio_write_data_parity_err_cnt),
4603[C_PIO_HOST_ADDR_MEM_COR_ERR] = CNTR_ELEM("PioHostAddrMemCorErr", 0, 0,
4604 CNTR_NORMAL,
4605 access_pio_host_addr_mem_cor_err_cnt),
4606[C_PIO_HOST_ADDR_MEM_UNC_ERR] = CNTR_ELEM("PioHostAddrMemUncErr", 0, 0,
4607 CNTR_NORMAL,
4608 access_pio_host_addr_mem_unc_err_cnt),
4609[C_PIO_PKT_EVICT_SM_OR_ARM_SM_ERR] = CNTR_ELEM("PioPktEvictSmOrArbSmErr", 0, 0,
4610 CNTR_NORMAL,
4611 access_pio_pkt_evict_sm_or_arb_sm_err_cnt),
4612[C_PIO_INIT_SM_IN_ERR] = CNTR_ELEM("PioInitSmInErr", 0, 0,
4613 CNTR_NORMAL,
4614 access_pio_init_sm_in_err_cnt),
4615[C_PIO_PPMC_PBL_FIFO_ERR] = CNTR_ELEM("PioPpmcPblFifoErr", 0, 0,
4616 CNTR_NORMAL,
4617 access_pio_ppmc_pbl_fifo_err_cnt),
4618[C_PIO_CREDIT_RET_FIFO_PARITY_ERR] = CNTR_ELEM("PioCreditRetFifoParityErr", 0,
4619 0, CNTR_NORMAL,
4620 access_pio_credit_ret_fifo_parity_err_cnt),
4621[C_PIO_V1_LEN_MEM_BANK1_COR_ERR] = CNTR_ELEM("PioVlLenMemBank1CorErr", 0, 0,
4622 CNTR_NORMAL,
4623 access_pio_v1_len_mem_bank1_cor_err_cnt),
4624[C_PIO_V1_LEN_MEM_BANK0_COR_ERR] = CNTR_ELEM("PioVlLenMemBank0CorErr", 0, 0,
4625 CNTR_NORMAL,
4626 access_pio_v1_len_mem_bank0_cor_err_cnt),
4627[C_PIO_V1_LEN_MEM_BANK1_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank1UncErr", 0, 0,
4628 CNTR_NORMAL,
4629 access_pio_v1_len_mem_bank1_unc_err_cnt),
4630[C_PIO_V1_LEN_MEM_BANK0_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank0UncErr", 0, 0,
4631 CNTR_NORMAL,
4632 access_pio_v1_len_mem_bank0_unc_err_cnt),
4633[C_PIO_SM_PKT_RESET_PARITY_ERR] = CNTR_ELEM("PioSmPktResetParityErr", 0, 0,
4634 CNTR_NORMAL,
4635 access_pio_sm_pkt_reset_parity_err_cnt),
4636[C_PIO_PKT_EVICT_FIFO_PARITY_ERR] = CNTR_ELEM("PioPktEvictFifoParityErr", 0, 0,
4637 CNTR_NORMAL,
4638 access_pio_pkt_evict_fifo_parity_err_cnt),
4639[C_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR] = CNTR_ELEM(
4640 "PioSbrdctrlCrrelFifoParityErr", 0, 0,
4641 CNTR_NORMAL,
4642 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt),
4643[C_PIO_SBRDCTL_CRREL_PARITY_ERR] = CNTR_ELEM("PioSbrdctlCrrelParityErr", 0, 0,
4644 CNTR_NORMAL,
4645 access_pio_sbrdctl_crrel_parity_err_cnt),
4646[C_PIO_PEC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPecFifoParityErr", 0, 0,
4647 CNTR_NORMAL,
4648 access_pio_pec_fifo_parity_err_cnt),
4649[C_PIO_PCC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPccFifoParityErr", 0, 0,
4650 CNTR_NORMAL,
4651 access_pio_pcc_fifo_parity_err_cnt),
4652[C_PIO_SB_MEM_FIFO1_ERR] = CNTR_ELEM("PioSbMemFifo1Err", 0, 0,
4653 CNTR_NORMAL,
4654 access_pio_sb_mem_fifo1_err_cnt),
4655[C_PIO_SB_MEM_FIFO0_ERR] = CNTR_ELEM("PioSbMemFifo0Err", 0, 0,
4656 CNTR_NORMAL,
4657 access_pio_sb_mem_fifo0_err_cnt),
4658[C_PIO_CSR_PARITY_ERR] = CNTR_ELEM("PioCsrParityErr", 0, 0,
4659 CNTR_NORMAL,
4660 access_pio_csr_parity_err_cnt),
4661[C_PIO_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("PioWriteAddrParityErr", 0, 0,
4662 CNTR_NORMAL,
4663 access_pio_write_addr_parity_err_cnt),
4664[C_PIO_WRITE_BAD_CTXT_ERR] = CNTR_ELEM("PioWriteBadCtxtErr", 0, 0,
4665 CNTR_NORMAL,
4666 access_pio_write_bad_ctxt_err_cnt),
4667/* SendDmaErrStatus */
4668[C_SDMA_PCIE_REQ_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPcieReqTrackingCorErr", 0,
4669 0, CNTR_NORMAL,
4670 access_sdma_pcie_req_tracking_cor_err_cnt),
4671[C_SDMA_PCIE_REQ_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPcieReqTrackingUncErr", 0,
4672 0, CNTR_NORMAL,
4673 access_sdma_pcie_req_tracking_unc_err_cnt),
4674[C_SDMA_CSR_PARITY_ERR] = CNTR_ELEM("SDmaCsrParityErr", 0, 0,
4675 CNTR_NORMAL,
4676 access_sdma_csr_parity_err_cnt),
4677[C_SDMA_RPY_TAG_ERR] = CNTR_ELEM("SDmaRpyTagErr", 0, 0,
4678 CNTR_NORMAL,
4679 access_sdma_rpy_tag_err_cnt),
4680/* SendEgressErrStatus */
4681[C_TX_READ_PIO_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryCsrUncErr", 0, 0,
4682 CNTR_NORMAL,
4683 access_tx_read_pio_memory_csr_unc_err_cnt),
4684[C_TX_READ_SDMA_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryCsrUncErr", 0,
4685 0, CNTR_NORMAL,
4686 access_tx_read_sdma_memory_csr_err_cnt),
4687[C_TX_EGRESS_FIFO_COR_ERR] = CNTR_ELEM("TxEgressFifoCorErr", 0, 0,
4688 CNTR_NORMAL,
4689 access_tx_egress_fifo_cor_err_cnt),
4690[C_TX_READ_PIO_MEMORY_COR_ERR] = CNTR_ELEM("TxReadPioMemoryCorErr", 0, 0,
4691 CNTR_NORMAL,
4692 access_tx_read_pio_memory_cor_err_cnt),
4693[C_TX_READ_SDMA_MEMORY_COR_ERR] = CNTR_ELEM("TxReadSdmaMemoryCorErr", 0, 0,
4694 CNTR_NORMAL,
4695 access_tx_read_sdma_memory_cor_err_cnt),
4696[C_TX_SB_HDR_COR_ERR] = CNTR_ELEM("TxSbHdrCorErr", 0, 0,
4697 CNTR_NORMAL,
4698 access_tx_sb_hdr_cor_err_cnt),
4699[C_TX_CREDIT_OVERRUN_ERR] = CNTR_ELEM("TxCreditOverrunErr", 0, 0,
4700 CNTR_NORMAL,
4701 access_tx_credit_overrun_err_cnt),
4702[C_TX_LAUNCH_FIFO8_COR_ERR] = CNTR_ELEM("TxLaunchFifo8CorErr", 0, 0,
4703 CNTR_NORMAL,
4704 access_tx_launch_fifo8_cor_err_cnt),
4705[C_TX_LAUNCH_FIFO7_COR_ERR] = CNTR_ELEM("TxLaunchFifo7CorErr", 0, 0,
4706 CNTR_NORMAL,
4707 access_tx_launch_fifo7_cor_err_cnt),
4708[C_TX_LAUNCH_FIFO6_COR_ERR] = CNTR_ELEM("TxLaunchFifo6CorErr", 0, 0,
4709 CNTR_NORMAL,
4710 access_tx_launch_fifo6_cor_err_cnt),
4711[C_TX_LAUNCH_FIFO5_COR_ERR] = CNTR_ELEM("TxLaunchFifo5CorErr", 0, 0,
4712 CNTR_NORMAL,
4713 access_tx_launch_fifo5_cor_err_cnt),
4714[C_TX_LAUNCH_FIFO4_COR_ERR] = CNTR_ELEM("TxLaunchFifo4CorErr", 0, 0,
4715 CNTR_NORMAL,
4716 access_tx_launch_fifo4_cor_err_cnt),
4717[C_TX_LAUNCH_FIFO3_COR_ERR] = CNTR_ELEM("TxLaunchFifo3CorErr", 0, 0,
4718 CNTR_NORMAL,
4719 access_tx_launch_fifo3_cor_err_cnt),
4720[C_TX_LAUNCH_FIFO2_COR_ERR] = CNTR_ELEM("TxLaunchFifo2CorErr", 0, 0,
4721 CNTR_NORMAL,
4722 access_tx_launch_fifo2_cor_err_cnt),
4723[C_TX_LAUNCH_FIFO1_COR_ERR] = CNTR_ELEM("TxLaunchFifo1CorErr", 0, 0,
4724 CNTR_NORMAL,
4725 access_tx_launch_fifo1_cor_err_cnt),
4726[C_TX_LAUNCH_FIFO0_COR_ERR] = CNTR_ELEM("TxLaunchFifo0CorErr", 0, 0,
4727 CNTR_NORMAL,
4728 access_tx_launch_fifo0_cor_err_cnt),
4729[C_TX_CREDIT_RETURN_VL_ERR] = CNTR_ELEM("TxCreditReturnVLErr", 0, 0,
4730 CNTR_NORMAL,
4731 access_tx_credit_return_vl_err_cnt),
4732[C_TX_HCRC_INSERTION_ERR] = CNTR_ELEM("TxHcrcInsertionErr", 0, 0,
4733 CNTR_NORMAL,
4734 access_tx_hcrc_insertion_err_cnt),
4735[C_TX_EGRESS_FIFI_UNC_ERR] = CNTR_ELEM("TxEgressFifoUncErr", 0, 0,
4736 CNTR_NORMAL,
4737 access_tx_egress_fifo_unc_err_cnt),
4738[C_TX_READ_PIO_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryUncErr", 0, 0,
4739 CNTR_NORMAL,
4740 access_tx_read_pio_memory_unc_err_cnt),
4741[C_TX_READ_SDMA_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryUncErr", 0, 0,
4742 CNTR_NORMAL,
4743 access_tx_read_sdma_memory_unc_err_cnt),
4744[C_TX_SB_HDR_UNC_ERR] = CNTR_ELEM("TxSbHdrUncErr", 0, 0,
4745 CNTR_NORMAL,
4746 access_tx_sb_hdr_unc_err_cnt),
4747[C_TX_CREDIT_RETURN_PARITY_ERR] = CNTR_ELEM("TxCreditReturnParityErr", 0, 0,
4748 CNTR_NORMAL,
4749 access_tx_credit_return_partiy_err_cnt),
4750[C_TX_LAUNCH_FIFO8_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo8UncOrParityErr",
4751 0, 0, CNTR_NORMAL,
4752 access_tx_launch_fifo8_unc_or_parity_err_cnt),
4753[C_TX_LAUNCH_FIFO7_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo7UncOrParityErr",
4754 0, 0, CNTR_NORMAL,
4755 access_tx_launch_fifo7_unc_or_parity_err_cnt),
4756[C_TX_LAUNCH_FIFO6_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo6UncOrParityErr",
4757 0, 0, CNTR_NORMAL,
4758 access_tx_launch_fifo6_unc_or_parity_err_cnt),
4759[C_TX_LAUNCH_FIFO5_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo5UncOrParityErr",
4760 0, 0, CNTR_NORMAL,
4761 access_tx_launch_fifo5_unc_or_parity_err_cnt),
4762[C_TX_LAUNCH_FIFO4_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo4UncOrParityErr",
4763 0, 0, CNTR_NORMAL,
4764 access_tx_launch_fifo4_unc_or_parity_err_cnt),
4765[C_TX_LAUNCH_FIFO3_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo3UncOrParityErr",
4766 0, 0, CNTR_NORMAL,
4767 access_tx_launch_fifo3_unc_or_parity_err_cnt),
4768[C_TX_LAUNCH_FIFO2_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo2UncOrParityErr",
4769 0, 0, CNTR_NORMAL,
4770 access_tx_launch_fifo2_unc_or_parity_err_cnt),
4771[C_TX_LAUNCH_FIFO1_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo1UncOrParityErr",
4772 0, 0, CNTR_NORMAL,
4773 access_tx_launch_fifo1_unc_or_parity_err_cnt),
4774[C_TX_LAUNCH_FIFO0_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo0UncOrParityErr",
4775 0, 0, CNTR_NORMAL,
4776 access_tx_launch_fifo0_unc_or_parity_err_cnt),
4777[C_TX_SDMA15_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma15DisallowedPacketErr",
4778 0, 0, CNTR_NORMAL,
4779 access_tx_sdma15_disallowed_packet_err_cnt),
4780[C_TX_SDMA14_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma14DisallowedPacketErr",
4781 0, 0, CNTR_NORMAL,
4782 access_tx_sdma14_disallowed_packet_err_cnt),
4783[C_TX_SDMA13_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma13DisallowedPacketErr",
4784 0, 0, CNTR_NORMAL,
4785 access_tx_sdma13_disallowed_packet_err_cnt),
4786[C_TX_SDMA12_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma12DisallowedPacketErr",
4787 0, 0, CNTR_NORMAL,
4788 access_tx_sdma12_disallowed_packet_err_cnt),
4789[C_TX_SDMA11_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma11DisallowedPacketErr",
4790 0, 0, CNTR_NORMAL,
4791 access_tx_sdma11_disallowed_packet_err_cnt),
4792[C_TX_SDMA10_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma10DisallowedPacketErr",
4793 0, 0, CNTR_NORMAL,
4794 access_tx_sdma10_disallowed_packet_err_cnt),
4795[C_TX_SDMA9_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma9DisallowedPacketErr",
4796 0, 0, CNTR_NORMAL,
4797 access_tx_sdma9_disallowed_packet_err_cnt),
4798[C_TX_SDMA8_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma8DisallowedPacketErr",
4799 0, 0, CNTR_NORMAL,
4800 access_tx_sdma8_disallowed_packet_err_cnt),
4801[C_TX_SDMA7_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma7DisallowedPacketErr",
4802 0, 0, CNTR_NORMAL,
4803 access_tx_sdma7_disallowed_packet_err_cnt),
4804[C_TX_SDMA6_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma6DisallowedPacketErr",
4805 0, 0, CNTR_NORMAL,
4806 access_tx_sdma6_disallowed_packet_err_cnt),
4807[C_TX_SDMA5_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma5DisallowedPacketErr",
4808 0, 0, CNTR_NORMAL,
4809 access_tx_sdma5_disallowed_packet_err_cnt),
4810[C_TX_SDMA4_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma4DisallowedPacketErr",
4811 0, 0, CNTR_NORMAL,
4812 access_tx_sdma4_disallowed_packet_err_cnt),
4813[C_TX_SDMA3_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma3DisallowedPacketErr",
4814 0, 0, CNTR_NORMAL,
4815 access_tx_sdma3_disallowed_packet_err_cnt),
4816[C_TX_SDMA2_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma2DisallowedPacketErr",
4817 0, 0, CNTR_NORMAL,
4818 access_tx_sdma2_disallowed_packet_err_cnt),
4819[C_TX_SDMA1_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma1DisallowedPacketErr",
4820 0, 0, CNTR_NORMAL,
4821 access_tx_sdma1_disallowed_packet_err_cnt),
4822[C_TX_SDMA0_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma0DisallowedPacketErr",
4823 0, 0, CNTR_NORMAL,
4824 access_tx_sdma0_disallowed_packet_err_cnt),
4825[C_TX_CONFIG_PARITY_ERR] = CNTR_ELEM("TxConfigParityErr", 0, 0,
4826 CNTR_NORMAL,
4827 access_tx_config_parity_err_cnt),
4828[C_TX_SBRD_CTL_CSR_PARITY_ERR] = CNTR_ELEM("TxSbrdCtlCsrParityErr", 0, 0,
4829 CNTR_NORMAL,
4830 access_tx_sbrd_ctl_csr_parity_err_cnt),
4831[C_TX_LAUNCH_CSR_PARITY_ERR] = CNTR_ELEM("TxLaunchCsrParityErr", 0, 0,
4832 CNTR_NORMAL,
4833 access_tx_launch_csr_parity_err_cnt),
4834[C_TX_ILLEGAL_CL_ERR] = CNTR_ELEM("TxIllegalVLErr", 0, 0,
4835 CNTR_NORMAL,
4836 access_tx_illegal_vl_err_cnt),
4837[C_TX_SBRD_CTL_STATE_MACHINE_PARITY_ERR] = CNTR_ELEM(
4838 "TxSbrdCtlStateMachineParityErr", 0, 0,
4839 CNTR_NORMAL,
4840 access_tx_sbrd_ctl_state_machine_parity_err_cnt),
4841[C_TX_RESERVED_10] = CNTR_ELEM("Tx Egress Reserved 10", 0, 0,
4842 CNTR_NORMAL,
4843 access_egress_reserved_10_err_cnt),
4844[C_TX_RESERVED_9] = CNTR_ELEM("Tx Egress Reserved 9", 0, 0,
4845 CNTR_NORMAL,
4846 access_egress_reserved_9_err_cnt),
4847[C_TX_SDMA_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxSdmaLaunchIntfParityErr",
4848 0, 0, CNTR_NORMAL,
4849 access_tx_sdma_launch_intf_parity_err_cnt),
4850[C_TX_PIO_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxPioLaunchIntfParityErr", 0, 0,
4851 CNTR_NORMAL,
4852 access_tx_pio_launch_intf_parity_err_cnt),
4853[C_TX_RESERVED_6] = CNTR_ELEM("Tx Egress Reserved 6", 0, 0,
4854 CNTR_NORMAL,
4855 access_egress_reserved_6_err_cnt),
4856[C_TX_INCORRECT_LINK_STATE_ERR] = CNTR_ELEM("TxIncorrectLinkStateErr", 0, 0,
4857 CNTR_NORMAL,
4858 access_tx_incorrect_link_state_err_cnt),
4859[C_TX_LINK_DOWN_ERR] = CNTR_ELEM("TxLinkdownErr", 0, 0,
4860 CNTR_NORMAL,
4861 access_tx_linkdown_err_cnt),
4862[C_TX_EGRESS_FIFO_UNDERRUN_OR_PARITY_ERR] = CNTR_ELEM(
4863 "EgressFifoUnderrunOrParityErr", 0, 0,
4864 CNTR_NORMAL,
4865 access_tx_egress_fifi_underrun_or_parity_err_cnt),
4866[C_TX_RESERVED_2] = CNTR_ELEM("Tx Egress Reserved 2", 0, 0,
4867 CNTR_NORMAL,
4868 access_egress_reserved_2_err_cnt),
4869[C_TX_PKT_INTEGRITY_MEM_UNC_ERR] = CNTR_ELEM("TxPktIntegrityMemUncErr", 0, 0,
4870 CNTR_NORMAL,
4871 access_tx_pkt_integrity_mem_unc_err_cnt),
4872[C_TX_PKT_INTEGRITY_MEM_COR_ERR] = CNTR_ELEM("TxPktIntegrityMemCorErr", 0, 0,
4873 CNTR_NORMAL,
4874 access_tx_pkt_integrity_mem_cor_err_cnt),
4875/* SendErrStatus */
4876[C_SEND_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("SendCsrWriteBadAddrErr", 0, 0,
4877 CNTR_NORMAL,
4878 access_send_csr_write_bad_addr_err_cnt),
4879[C_SEND_CSR_READ_BAD_ADD_ERR] = CNTR_ELEM("SendCsrReadBadAddrErr", 0, 0,
4880 CNTR_NORMAL,
4881 access_send_csr_read_bad_addr_err_cnt),
4882[C_SEND_CSR_PARITY_ERR] = CNTR_ELEM("SendCsrParityErr", 0, 0,
4883 CNTR_NORMAL,
4884 access_send_csr_parity_cnt),
4885/* SendCtxtErrStatus */
4886[C_PIO_WRITE_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("PioWriteOutOfBoundsErr", 0, 0,
4887 CNTR_NORMAL,
4888 access_pio_write_out_of_bounds_err_cnt),
4889[C_PIO_WRITE_OVERFLOW_ERR] = CNTR_ELEM("PioWriteOverflowErr", 0, 0,
4890 CNTR_NORMAL,
4891 access_pio_write_overflow_err_cnt),
4892[C_PIO_WRITE_CROSSES_BOUNDARY_ERR] = CNTR_ELEM("PioWriteCrossesBoundaryErr",
4893 0, 0, CNTR_NORMAL,
4894 access_pio_write_crosses_boundary_err_cnt),
4895[C_PIO_DISALLOWED_PACKET_ERR] = CNTR_ELEM("PioDisallowedPacketErr", 0, 0,
4896 CNTR_NORMAL,
4897 access_pio_disallowed_packet_err_cnt),
4898[C_PIO_INCONSISTENT_SOP_ERR] = CNTR_ELEM("PioInconsistentSopErr", 0, 0,
4899 CNTR_NORMAL,
4900 access_pio_inconsistent_sop_err_cnt),
4901/* SendDmaEngErrStatus */
4902[C_SDMA_HEADER_REQUEST_FIFO_COR_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoCorErr",
4903 0, 0, CNTR_NORMAL,
4904 access_sdma_header_request_fifo_cor_err_cnt),
4905[C_SDMA_HEADER_STORAGE_COR_ERR] = CNTR_ELEM("SDmaHeaderStorageCorErr", 0, 0,
4906 CNTR_NORMAL,
4907 access_sdma_header_storage_cor_err_cnt),
4908[C_SDMA_PACKET_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPacketTrackingCorErr", 0, 0,
4909 CNTR_NORMAL,
4910 access_sdma_packet_tracking_cor_err_cnt),
4911[C_SDMA_ASSEMBLY_COR_ERR] = CNTR_ELEM("SDmaAssemblyCorErr", 0, 0,
4912 CNTR_NORMAL,
4913 access_sdma_assembly_cor_err_cnt),
4914[C_SDMA_DESC_TABLE_COR_ERR] = CNTR_ELEM("SDmaDescTableCorErr", 0, 0,
4915 CNTR_NORMAL,
4916 access_sdma_desc_table_cor_err_cnt),
4917[C_SDMA_HEADER_REQUEST_FIFO_UNC_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoUncErr",
4918 0, 0, CNTR_NORMAL,
4919 access_sdma_header_request_fifo_unc_err_cnt),
4920[C_SDMA_HEADER_STORAGE_UNC_ERR] = CNTR_ELEM("SDmaHeaderStorageUncErr", 0, 0,
4921 CNTR_NORMAL,
4922 access_sdma_header_storage_unc_err_cnt),
4923[C_SDMA_PACKET_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPacketTrackingUncErr", 0, 0,
4924 CNTR_NORMAL,
4925 access_sdma_packet_tracking_unc_err_cnt),
4926[C_SDMA_ASSEMBLY_UNC_ERR] = CNTR_ELEM("SDmaAssemblyUncErr", 0, 0,
4927 CNTR_NORMAL,
4928 access_sdma_assembly_unc_err_cnt),
4929[C_SDMA_DESC_TABLE_UNC_ERR] = CNTR_ELEM("SDmaDescTableUncErr", 0, 0,
4930 CNTR_NORMAL,
4931 access_sdma_desc_table_unc_err_cnt),
4932[C_SDMA_TIMEOUT_ERR] = CNTR_ELEM("SDmaTimeoutErr", 0, 0,
4933 CNTR_NORMAL,
4934 access_sdma_timeout_err_cnt),
4935[C_SDMA_HEADER_LENGTH_ERR] = CNTR_ELEM("SDmaHeaderLengthErr", 0, 0,
4936 CNTR_NORMAL,
4937 access_sdma_header_length_err_cnt),
4938[C_SDMA_HEADER_ADDRESS_ERR] = CNTR_ELEM("SDmaHeaderAddressErr", 0, 0,
4939 CNTR_NORMAL,
4940 access_sdma_header_address_err_cnt),
4941[C_SDMA_HEADER_SELECT_ERR] = CNTR_ELEM("SDmaHeaderSelectErr", 0, 0,
4942 CNTR_NORMAL,
4943 access_sdma_header_select_err_cnt),
4944[C_SMDA_RESERVED_9] = CNTR_ELEM("SDma Reserved 9", 0, 0,
4945 CNTR_NORMAL,
4946 access_sdma_reserved_9_err_cnt),
4947[C_SDMA_PACKET_DESC_OVERFLOW_ERR] = CNTR_ELEM("SDmaPacketDescOverflowErr", 0, 0,
4948 CNTR_NORMAL,
4949 access_sdma_packet_desc_overflow_err_cnt),
4950[C_SDMA_LENGTH_MISMATCH_ERR] = CNTR_ELEM("SDmaLengthMismatchErr", 0, 0,
4951 CNTR_NORMAL,
4952 access_sdma_length_mismatch_err_cnt),
4953[C_SDMA_HALT_ERR] = CNTR_ELEM("SDmaHaltErr", 0, 0,
4954 CNTR_NORMAL,
4955 access_sdma_halt_err_cnt),
4956[C_SDMA_MEM_READ_ERR] = CNTR_ELEM("SDmaMemReadErr", 0, 0,
4957 CNTR_NORMAL,
4958 access_sdma_mem_read_err_cnt),
4959[C_SDMA_FIRST_DESC_ERR] = CNTR_ELEM("SDmaFirstDescErr", 0, 0,
4960 CNTR_NORMAL,
4961 access_sdma_first_desc_err_cnt),
4962[C_SDMA_TAIL_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("SDmaTailOutOfBoundsErr", 0, 0,
4963 CNTR_NORMAL,
4964 access_sdma_tail_out_of_bounds_err_cnt),
4965[C_SDMA_TOO_LONG_ERR] = CNTR_ELEM("SDmaTooLongErr", 0, 0,
4966 CNTR_NORMAL,
4967 access_sdma_too_long_err_cnt),
4968[C_SDMA_GEN_MISMATCH_ERR] = CNTR_ELEM("SDmaGenMismatchErr", 0, 0,
4969 CNTR_NORMAL,
4970 access_sdma_gen_mismatch_err_cnt),
4971[C_SDMA_WRONG_DW_ERR] = CNTR_ELEM("SDmaWrongDwErr", 0, 0,
4972 CNTR_NORMAL,
4973 access_sdma_wrong_dw_err_cnt),
77241056
MM		 4974};
4975
4976static struct cntr_entry port_cntrs[PORT_CNTR_LAST] = {
4977[C_TX_UNSUP_VL] = TXE32_PORT_CNTR_ELEM(TxUnVLErr, SEND_UNSUP_VL_ERR_CNT,
4978 CNTR_NORMAL),
4979[C_TX_INVAL_LEN] = TXE32_PORT_CNTR_ELEM(TxInvalLen, SEND_LEN_ERR_CNT,
4980 CNTR_NORMAL),
4981[C_TX_MM_LEN_ERR] = TXE32_PORT_CNTR_ELEM(TxMMLenErr, SEND_MAX_MIN_LEN_ERR_CNT,
4982 CNTR_NORMAL),
4983[C_TX_UNDERRUN] = TXE32_PORT_CNTR_ELEM(TxUnderrun, SEND_UNDERRUN_CNT,
4984 CNTR_NORMAL),
4985[C_TX_FLOW_STALL] = TXE32_PORT_CNTR_ELEM(TxFlowStall, SEND_FLOW_STALL_CNT,
4986 CNTR_NORMAL),
4987[C_TX_DROPPED] = TXE32_PORT_CNTR_ELEM(TxDropped, SEND_DROPPED_PKT_CNT,
4988 CNTR_NORMAL),
4989[C_TX_HDR_ERR] = TXE32_PORT_CNTR_ELEM(TxHdrErr, SEND_HEADERS_ERR_CNT,
4990 CNTR_NORMAL),
4991[C_TX_PKT] = TXE64_PORT_CNTR_ELEM(TxPkt, SEND_DATA_PKT_CNT, CNTR_NORMAL),
4992[C_TX_WORDS] = TXE64_PORT_CNTR_ELEM(TxWords, SEND_DWORD_CNT, CNTR_NORMAL),
4993[C_TX_WAIT] = TXE64_PORT_CNTR_ELEM(TxWait, SEND_WAIT_CNT, CNTR_SYNTH),
4994[C_TX_FLIT_VL] = TXE64_PORT_CNTR_ELEM(TxFlitVL, SEND_DATA_VL0_CNT,
17fb4f29 4995 CNTR_SYNTH | CNTR_VL),
77241056 4996[C_TX_PKT_VL] = TXE64_PORT_CNTR_ELEM(TxPktVL, SEND_DATA_PKT_VL0_CNT,
17fb4f29 4997 CNTR_SYNTH | CNTR_VL),
77241056 4998[C_TX_WAIT_VL] = TXE64_PORT_CNTR_ELEM(TxWaitVL, SEND_WAIT_VL0_CNT,
17fb4f29 4999 CNTR_SYNTH | CNTR_VL),
77241056
MM		 5000[C_RX_PKT] = RXE64_PORT_CNTR_ELEM(RxPkt, RCV_DATA_PKT_CNT, CNTR_NORMAL),
5001[C_RX_WORDS] = RXE64_PORT_CNTR_ELEM(RxWords, RCV_DWORD_CNT, CNTR_NORMAL),
5002[C_SW_LINK_DOWN] = CNTR_ELEM("SwLinkDown", 0, 0, CNTR_SYNTH | CNTR_32BIT,
17fb4f29 5003 access_sw_link_dn_cnt),
77241056 5004[C_SW_LINK_UP] = CNTR_ELEM("SwLinkUp", 0, 0, CNTR_SYNTH | CNTR_32BIT,
17fb4f29 5005 access_sw_link_up_cnt),
6d014530
DL		 5006[C_SW_UNKNOWN_FRAME] = CNTR_ELEM("UnknownFrame", 0, 0, CNTR_NORMAL,
5007 access_sw_unknown_frame_cnt),
77241056 5008[C_SW_XMIT_DSCD] = CNTR_ELEM("XmitDscd", 0, 0, CNTR_SYNTH | CNTR_32BIT,
17fb4f29 5009 access_sw_xmit_discards),
77241056 5010[C_SW_XMIT_DSCD_VL] = CNTR_ELEM("XmitDscdVl", 0, 0,
17fb4f29
JJ		 5011 CNTR_SYNTH | CNTR_32BIT | CNTR_VL,
5012 access_sw_xmit_discards),
77241056 5013[C_SW_XMIT_CSTR_ERR] = CNTR_ELEM("XmitCstrErr", 0, 0, CNTR_SYNTH,
17fb4f29 5014 access_xmit_constraint_errs),
77241056 5015[C_SW_RCV_CSTR_ERR] = CNTR_ELEM("RcvCstrErr", 0, 0, CNTR_SYNTH,
17fb4f29 5016 access_rcv_constraint_errs),
77241056
MM		 5017[C_SW_IBP_LOOP_PKTS] = SW_IBP_CNTR(LoopPkts, loop_pkts),
5018[C_SW_IBP_RC_RESENDS] = SW_IBP_CNTR(RcResend, rc_resends),
5019[C_SW_IBP_RNR_NAKS] = SW_IBP_CNTR(RnrNak, rnr_naks),
5020[C_SW_IBP_OTHER_NAKS] = SW_IBP_CNTR(OtherNak, other_naks),
5021[C_SW_IBP_RC_TIMEOUTS] = SW_IBP_CNTR(RcTimeOut, rc_timeouts),
5022[C_SW_IBP_PKT_DROPS] = SW_IBP_CNTR(PktDrop, pkt_drops),
5023[C_SW_IBP_DMA_WAIT] = SW_IBP_CNTR(DmaWait, dmawait),
5024[C_SW_IBP_RC_SEQNAK] = SW_IBP_CNTR(RcSeqNak, rc_seqnak),
5025[C_SW_IBP_RC_DUPREQ] = SW_IBP_CNTR(RcDupRew, rc_dupreq),
5026[C_SW_IBP_RDMA_SEQ] = SW_IBP_CNTR(RdmaSeq, rdma_seq),
5027[C_SW_IBP_UNALIGNED] = SW_IBP_CNTR(Unaligned, unaligned),
5028[C_SW_IBP_SEQ_NAK] = SW_IBP_CNTR(SeqNak, seq_naks),
5029[C_SW_CPU_RC_ACKS] = CNTR_ELEM("RcAcks", 0, 0, CNTR_NORMAL,
5030 access_sw_cpu_rc_acks),
5031[C_SW_CPU_RC_QACKS] = CNTR_ELEM("RcQacks", 0, 0, CNTR_NORMAL,
17fb4f29 5032 access_sw_cpu_rc_qacks),
77241056 5033[C_SW_CPU_RC_DELAYED_COMP] = CNTR_ELEM("RcDelayComp", 0, 0, CNTR_NORMAL,
17fb4f29 5034 access_sw_cpu_rc_delayed_comp),
77241056
MM		 5035[OVR_LBL(0)] = OVR_ELM(0), [OVR_LBL(1)] = OVR_ELM(1),
5036[OVR_LBL(2)] = OVR_ELM(2), [OVR_LBL(3)] = OVR_ELM(3),
5037[OVR_LBL(4)] = OVR_ELM(4), [OVR_LBL(5)] = OVR_ELM(5),
5038[OVR_LBL(6)] = OVR_ELM(6), [OVR_LBL(7)] = OVR_ELM(7),
5039[OVR_LBL(8)] = OVR_ELM(8), [OVR_LBL(9)] = OVR_ELM(9),
5040[OVR_LBL(10)] = OVR_ELM(10), [OVR_LBL(11)] = OVR_ELM(11),
5041[OVR_LBL(12)] = OVR_ELM(12), [OVR_LBL(13)] = OVR_ELM(13),
5042[OVR_LBL(14)] = OVR_ELM(14), [OVR_LBL(15)] = OVR_ELM(15),
5043[OVR_LBL(16)] = OVR_ELM(16), [OVR_LBL(17)] = OVR_ELM(17),
5044[OVR_LBL(18)] = OVR_ELM(18), [OVR_LBL(19)] = OVR_ELM(19),
5045[OVR_LBL(20)] = OVR_ELM(20), [OVR_LBL(21)] = OVR_ELM(21),
5046[OVR_LBL(22)] = OVR_ELM(22), [OVR_LBL(23)] = OVR_ELM(23),
5047[OVR_LBL(24)] = OVR_ELM(24), [OVR_LBL(25)] = OVR_ELM(25),
5048[OVR_LBL(26)] = OVR_ELM(26), [OVR_LBL(27)] = OVR_ELM(27),
5049[OVR_LBL(28)] = OVR_ELM(28), [OVR_LBL(29)] = OVR_ELM(29),
5050[OVR_LBL(30)] = OVR_ELM(30), [OVR_LBL(31)] = OVR_ELM(31),
5051[OVR_LBL(32)] = OVR_ELM(32), [OVR_LBL(33)] = OVR_ELM(33),
5052[OVR_LBL(34)] = OVR_ELM(34), [OVR_LBL(35)] = OVR_ELM(35),
5053[OVR_LBL(36)] = OVR_ELM(36), [OVR_LBL(37)] = OVR_ELM(37),
5054[OVR_LBL(38)] = OVR_ELM(38), [OVR_LBL(39)] = OVR_ELM(39),
5055[OVR_LBL(40)] = OVR_ELM(40), [OVR_LBL(41)] = OVR_ELM(41),
5056[OVR_LBL(42)] = OVR_ELM(42), [OVR_LBL(43)] = OVR_ELM(43),
5057[OVR_LBL(44)] = OVR_ELM(44), [OVR_LBL(45)] = OVR_ELM(45),
5058[OVR_LBL(46)] = OVR_ELM(46), [OVR_LBL(47)] = OVR_ELM(47),
5059[OVR_LBL(48)] = OVR_ELM(48), [OVR_LBL(49)] = OVR_ELM(49),
5060[OVR_LBL(50)] = OVR_ELM(50), [OVR_LBL(51)] = OVR_ELM(51),
5061[OVR_LBL(52)] = OVR_ELM(52), [OVR_LBL(53)] = OVR_ELM(53),
5062[OVR_LBL(54)] = OVR_ELM(54), [OVR_LBL(55)] = OVR_ELM(55),
5063[OVR_LBL(56)] = OVR_ELM(56), [OVR_LBL(57)] = OVR_ELM(57),
5064[OVR_LBL(58)] = OVR_ELM(58), [OVR_LBL(59)] = OVR_ELM(59),
5065[OVR_LBL(60)] = OVR_ELM(60), [OVR_LBL(61)] = OVR_ELM(61),
5066[OVR_LBL(62)] = OVR_ELM(62), [OVR_LBL(63)] = OVR_ELM(63),
5067[OVR_LBL(64)] = OVR_ELM(64), [OVR_LBL(65)] = OVR_ELM(65),
5068[OVR_LBL(66)] = OVR_ELM(66), [OVR_LBL(67)] = OVR_ELM(67),
5069[OVR_LBL(68)] = OVR_ELM(68), [OVR_LBL(69)] = OVR_ELM(69),
5070[OVR_LBL(70)] = OVR_ELM(70), [OVR_LBL(71)] = OVR_ELM(71),
5071[OVR_LBL(72)] = OVR_ELM(72), [OVR_LBL(73)] = OVR_ELM(73),
5072[OVR_LBL(74)] = OVR_ELM(74), [OVR_LBL(75)] = OVR_ELM(75),
5073[OVR_LBL(76)] = OVR_ELM(76), [OVR_LBL(77)] = OVR_ELM(77),
5074[OVR_LBL(78)] = OVR_ELM(78), [OVR_LBL(79)] = OVR_ELM(79),
5075[OVR_LBL(80)] = OVR_ELM(80), [OVR_LBL(81)] = OVR_ELM(81),
5076[OVR_LBL(82)] = OVR_ELM(82), [OVR_LBL(83)] = OVR_ELM(83),
5077[OVR_LBL(84)] = OVR_ELM(84), [OVR_LBL(85)] = OVR_ELM(85),
5078[OVR_LBL(86)] = OVR_ELM(86), [OVR_LBL(87)] = OVR_ELM(87),
5079[OVR_LBL(88)] = OVR_ELM(88), [OVR_LBL(89)] = OVR_ELM(89),
5080[OVR_LBL(90)] = OVR_ELM(90), [OVR_LBL(91)] = OVR_ELM(91),
5081[OVR_LBL(92)] = OVR_ELM(92), [OVR_LBL(93)] = OVR_ELM(93),
5082[OVR_LBL(94)] = OVR_ELM(94), [OVR_LBL(95)] = OVR_ELM(95),
5083[OVR_LBL(96)] = OVR_ELM(96), [OVR_LBL(97)] = OVR_ELM(97),
5084[OVR_LBL(98)] = OVR_ELM(98), [OVR_LBL(99)] = OVR_ELM(99),
5085[OVR_LBL(100)] = OVR_ELM(100), [OVR_LBL(101)] = OVR_ELM(101),
5086[OVR_LBL(102)] = OVR_ELM(102), [OVR_LBL(103)] = OVR_ELM(103),
5087[OVR_LBL(104)] = OVR_ELM(104), [OVR_LBL(105)] = OVR_ELM(105),
5088[OVR_LBL(106)] = OVR_ELM(106), [OVR_LBL(107)] = OVR_ELM(107),
5089[OVR_LBL(108)] = OVR_ELM(108), [OVR_LBL(109)] = OVR_ELM(109),
5090[OVR_LBL(110)] = OVR_ELM(110), [OVR_LBL(111)] = OVR_ELM(111),
5091[OVR_LBL(112)] = OVR_ELM(112), [OVR_LBL(113)] = OVR_ELM(113),
5092[OVR_LBL(114)] = OVR_ELM(114), [OVR_LBL(115)] = OVR_ELM(115),
5093[OVR_LBL(116)] = OVR_ELM(116), [OVR_LBL(117)] = OVR_ELM(117),
5094[OVR_LBL(118)] = OVR_ELM(118), [OVR_LBL(119)] = OVR_ELM(119),
5095[OVR_LBL(120)] = OVR_ELM(120), [OVR_LBL(121)] = OVR_ELM(121),
5096[OVR_LBL(122)] = OVR_ELM(122), [OVR_LBL(123)] = OVR_ELM(123),
5097[OVR_LBL(124)] = OVR_ELM(124), [OVR_LBL(125)] = OVR_ELM(125),
5098[OVR_LBL(126)] = OVR_ELM(126), [OVR_LBL(127)] = OVR_ELM(127),
5099[OVR_LBL(128)] = OVR_ELM(128), [OVR_LBL(129)] = OVR_ELM(129),
5100[OVR_LBL(130)] = OVR_ELM(130), [OVR_LBL(131)] = OVR_ELM(131),
5101[OVR_LBL(132)] = OVR_ELM(132), [OVR_LBL(133)] = OVR_ELM(133),
5102[OVR_LBL(134)] = OVR_ELM(134), [OVR_LBL(135)] = OVR_ELM(135),
5103[OVR_LBL(136)] = OVR_ELM(136), [OVR_LBL(137)] = OVR_ELM(137),
5104[OVR_LBL(138)] = OVR_ELM(138), [OVR_LBL(139)] = OVR_ELM(139),
5105[OVR_LBL(140)] = OVR_ELM(140), [OVR_LBL(141)] = OVR_ELM(141),
5106[OVR_LBL(142)] = OVR_ELM(142), [OVR_LBL(143)] = OVR_ELM(143),
5107[OVR_LBL(144)] = OVR_ELM(144), [OVR_LBL(145)] = OVR_ELM(145),
5108[OVR_LBL(146)] = OVR_ELM(146), [OVR_LBL(147)] = OVR_ELM(147),
5109[OVR_LBL(148)] = OVR_ELM(148), [OVR_LBL(149)] = OVR_ELM(149),
5110[OVR_LBL(150)] = OVR_ELM(150), [OVR_LBL(151)] = OVR_ELM(151),
5111[OVR_LBL(152)] = OVR_ELM(152), [OVR_LBL(153)] = OVR_ELM(153),
5112[OVR_LBL(154)] = OVR_ELM(154), [OVR_LBL(155)] = OVR_ELM(155),
5113[OVR_LBL(156)] = OVR_ELM(156), [OVR_LBL(157)] = OVR_ELM(157),
5114[OVR_LBL(158)] = OVR_ELM(158), [OVR_LBL(159)] = OVR_ELM(159),
5115};
5116
5117/* ======================================================================== */
5118
77241056
MM		 5119/* return true if this is chip revision revision a */
5120int is_ax(struct hfi1_devdata *dd)
5121{
5122 u8 chip_rev_minor =
5123 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT
5124 & CCE_REVISION_CHIP_REV_MINOR_MASK;
5125 return (chip_rev_minor & 0xf0) == 0;
5126}
5127
5128/* return true if this is chip revision revision b */
5129int is_bx(struct hfi1_devdata *dd)
5130{
5131 u8 chip_rev_minor =
5132 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT
5133 & CCE_REVISION_CHIP_REV_MINOR_MASK;
995deafa 5134 return (chip_rev_minor & 0xF0) == 0x10;
77241056
MM		 5135}
5136
5137/*
5138 * Append string s to buffer buf. Arguments curp and len are the current
5139 * position and remaining length, respectively.
5140 *
5141 * return 0 on success, 1 on out of room
5142 */
5143static int append_str(char *buf, char **curp, int *lenp, const char *s)
5144{
5145 char *p = *curp;
5146 int len = *lenp;
5147 int result = 0; /* success */
5148 char c;
5149
5150 /* add a comma, if first in the buffer */
5151 if (p != buf) {
5152 if (len == 0) {
5153 result = 1; /* out of room */
5154 goto done;
5155 }
5156 *p++ = ',';
5157 len--;
5158 }
5159
5160 /* copy the string */
5161 while ((c = *s++) != 0) {
5162 if (len == 0) {
5163 result = 1; /* out of room */
5164 goto done;
5165 }
5166 *p++ = c;
5167 len--;
5168 }
5169
5170done:
5171 /* write return values */
5172 *curp = p;
5173 *lenp = len;
5174
5175 return result;
5176}
5177
5178/*
5179 * Using the given flag table, print a comma separated string into
5180 * the buffer. End in '*' if the buffer is too short.
5181 */
5182static char *flag_string(char *buf, int buf_len, u64 flags,
17fb4f29 5183 struct flag_table *table, int table_size)
77241056
MM		 5184{
5185 char extra[32];
5186 char *p = buf;
5187 int len = buf_len;
5188 int no_room = 0;
5189 int i;
5190
5191 /* make sure there is at least 2 so we can form "*" */
5192 if (len < 2)
5193 return "";
5194
5195 len--; /* leave room for a nul */
5196 for (i = 0; i < table_size; i++) {
5197 if (flags & table[i].flag) {
5198 no_room = append_str(buf, &p, &len, table[i].str);
5199 if (no_room)
5200 break;
5201 flags &= ~table[i].flag;
5202 }
5203 }
5204
5205 /* any undocumented bits left? */
5206 if (!no_room && flags) {
5207 snprintf(extra, sizeof(extra), "bits 0x%llx", flags);
5208 no_room = append_str(buf, &p, &len, extra);
5209 }
5210
5211 /* add * if ran out of room */
5212 if (no_room) {
5213 /* may need to back up to add space for a '*' */
5214 if (len == 0)
5215 --p;
5216 *p++ = '*';
5217 }
5218
5219 /* add final nul - space already allocated above */
5220 *p = 0;
5221 return buf;
5222}
5223
5224/* first 8 CCE error interrupt source names */
5225static const char * const cce_misc_names[] = {
5226 "CceErrInt", /* 0 */
5227 "RxeErrInt", /* 1 */
5228 "MiscErrInt", /* 2 */
5229 "Reserved3", /* 3 */
5230 "PioErrInt", /* 4 */
5231 "SDmaErrInt", /* 5 */
5232 "EgressErrInt", /* 6 */
5233 "TxeErrInt" /* 7 */
5234};
5235
5236/*
5237 * Return the miscellaneous error interrupt name.
5238 */
5239static char *is_misc_err_name(char *buf, size_t bsize, unsigned int source)
5240{
5241 if (source < ARRAY_SIZE(cce_misc_names))
5242 strncpy(buf, cce_misc_names[source], bsize);
5243 else
17fb4f29
JJ		 5244 snprintf(buf, bsize, "Reserved%u",
5245 source + IS_GENERAL_ERR_START);
77241056
MM		 5246
5247 return buf;
5248}
5249
5250/*
5251 * Return the SDMA engine error interrupt name.
5252 */
5253static char *is_sdma_eng_err_name(char *buf, size_t bsize, unsigned int source)
5254{
5255 snprintf(buf, bsize, "SDmaEngErrInt%u", source);
5256 return buf;
5257}
5258
5259/*
5260 * Return the send context error interrupt name.
5261 */
5262static char *is_sendctxt_err_name(char *buf, size_t bsize, unsigned int source)
5263{
5264 snprintf(buf, bsize, "SendCtxtErrInt%u", source);
5265 return buf;
5266}
5267
5268static const char * const various_names[] = {
5269 "PbcInt",
5270 "GpioAssertInt",
5271 "Qsfp1Int",
5272 "Qsfp2Int",
5273 "TCritInt"
5274};
5275
5276/*
5277 * Return the various interrupt name.
5278 */
5279static char *is_various_name(char *buf, size_t bsize, unsigned int source)
5280{
5281 if (source < ARRAY_SIZE(various_names))
5282 strncpy(buf, various_names[source], bsize);
5283 else
8638b77f 5284 snprintf(buf, bsize, "Reserved%u", source + IS_VARIOUS_START);
77241056
MM		 5285 return buf;
5286}
5287
5288/*
5289 * Return the DC interrupt name.
5290 */
5291static char *is_dc_name(char *buf, size_t bsize, unsigned int source)
5292{
5293 static const char * const dc_int_names[] = {
5294 "common",
5295 "lcb",
5296 "8051",
5297 "lbm" /* local block merge */
5298 };
5299
5300 if (source < ARRAY_SIZE(dc_int_names))
5301 snprintf(buf, bsize, "dc_%s_int", dc_int_names[source]);
5302 else
5303 snprintf(buf, bsize, "DCInt%u", source);
5304 return buf;
5305}
5306
5307static const char * const sdma_int_names[] = {
5308 "SDmaInt",
5309 "SdmaIdleInt",
5310 "SdmaProgressInt",
5311};
5312
5313/*
5314 * Return the SDMA engine interrupt name.
5315 */
5316static char *is_sdma_eng_name(char *buf, size_t bsize, unsigned int source)
5317{
5318 /* what interrupt */
5319 unsigned int what = source / TXE_NUM_SDMA_ENGINES;
5320 /* which engine */
5321 unsigned int which = source % TXE_NUM_SDMA_ENGINES;
5322
5323 if (likely(what < 3))
5324 snprintf(buf, bsize, "%s%u", sdma_int_names[what], which);
5325 else
5326 snprintf(buf, bsize, "Invalid SDMA interrupt %u", source);
5327 return buf;
5328}
5329
5330/*
5331 * Return the receive available interrupt name.
5332 */
5333static char *is_rcv_avail_name(char *buf, size_t bsize, unsigned int source)
5334{
5335 snprintf(buf, bsize, "RcvAvailInt%u", source);
5336 return buf;
5337}
5338
5339/*
5340 * Return the receive urgent interrupt name.
5341 */
5342static char *is_rcv_urgent_name(char *buf, size_t bsize, unsigned int source)
5343{
5344 snprintf(buf, bsize, "RcvUrgentInt%u", source);
5345 return buf;
5346}
5347
5348/*
5349 * Return the send credit interrupt name.
5350 */
5351static char *is_send_credit_name(char *buf, size_t bsize, unsigned int source)
5352{
5353 snprintf(buf, bsize, "SendCreditInt%u", source);
5354 return buf;
5355}
5356
5357/*
5358 * Return the reserved interrupt name.
5359 */
5360static char *is_reserved_name(char *buf, size_t bsize, unsigned int source)
5361{
5362 snprintf(buf, bsize, "Reserved%u", source + IS_RESERVED_START);
5363 return buf;
5364}
5365
5366static char *cce_err_status_string(char *buf, int buf_len, u64 flags)
5367{
5368 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5369 cce_err_status_flags,
5370 ARRAY_SIZE(cce_err_status_flags));
77241056
MM		 5371}
5372
5373static char *rxe_err_status_string(char *buf, int buf_len, u64 flags)
5374{
5375 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5376 rxe_err_status_flags,
5377 ARRAY_SIZE(rxe_err_status_flags));
77241056
MM		 5378}
5379
5380static char *misc_err_status_string(char *buf, int buf_len, u64 flags)
5381{
5382 return flag_string(buf, buf_len, flags, misc_err_status_flags,
17fb4f29 5383 ARRAY_SIZE(misc_err_status_flags));
77241056
MM		 5384}
5385
5386static char *pio_err_status_string(char *buf, int buf_len, u64 flags)
5387{
5388 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5389 pio_err_status_flags,
5390 ARRAY_SIZE(pio_err_status_flags));
77241056
MM		 5391}
5392
5393static char *sdma_err_status_string(char *buf, int buf_len, u64 flags)
5394{
5395 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5396 sdma_err_status_flags,
5397 ARRAY_SIZE(sdma_err_status_flags));
77241056
MM		 5398}
5399
5400static char *egress_err_status_string(char *buf, int buf_len, u64 flags)
5401{
5402 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5403 egress_err_status_flags,
5404 ARRAY_SIZE(egress_err_status_flags));
77241056
MM		 5405}
5406
5407static char *egress_err_info_string(char *buf, int buf_len, u64 flags)
5408{
5409 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5410 egress_err_info_flags,
5411 ARRAY_SIZE(egress_err_info_flags));
77241056
MM		 5412}
5413
5414static char *send_err_status_string(char *buf, int buf_len, u64 flags)
5415{
5416 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5417 send_err_status_flags,
5418 ARRAY_SIZE(send_err_status_flags));
77241056
MM		 5419}
5420
5421static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5422{
5423 char buf[96];
2c5b521a 5424 int i = 0;
77241056
MM		 5425
5426 /*
5427 * For most these errors, there is nothing that can be done except
5428 * report or record it.
5429 */
5430 dd_dev_info(dd, "CCE Error: %s\n",
17fb4f29 5431 cce_err_status_string(buf, sizeof(buf), reg));
77241056 5432
995deafa
MM		 5433 if ((reg & CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK) &&
5434 is_ax(dd) && (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)) {
77241056
MM		 5435 /* this error requires a manual drop into SPC freeze mode */
5436 /* then a fix up */
5437 start_freeze_handling(dd->pport, FREEZE_SELF);
5438 }
2c5b521a
JR		 5439
5440 for (i = 0; i < NUM_CCE_ERR_STATUS_COUNTERS; i++) {
5441 if (reg & (1ull << i)) {
5442 incr_cntr64(&dd->cce_err_status_cnt[i]);
5443 /* maintain a counter over all cce_err_status errors */
5444 incr_cntr64(&dd->sw_cce_err_status_aggregate);
5445 }
5446 }
77241056
MM		 5447}
5448
5449/*
5450 * Check counters for receive errors that do not have an interrupt
5451 * associated with them.
5452 */
5453#define RCVERR_CHECK_TIME 10
5454static void update_rcverr_timer(unsigned long opaque)
5455{
5456 struct hfi1_devdata *dd = (struct hfi1_devdata *)opaque;
5457 struct hfi1_pportdata *ppd = dd->pport;
5458 u32 cur_ovfl_cnt = read_dev_cntr(dd, C_RCV_OVF, CNTR_INVALID_VL);
5459
5460 if (dd->rcv_ovfl_cnt < cur_ovfl_cnt &&
17fb4f29 5461 ppd->port_error_action & OPA_PI_MASK_EX_BUFFER_OVERRUN) {
77241056 5462 dd_dev_info(dd, "%s: PortErrorAction bounce\n", __func__);
17fb4f29
JJ		 5463 set_link_down_reason(
5464 ppd, OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN, 0,
5465 OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN);
77241056
MM		 5466 queue_work(ppd->hfi1_wq, &ppd->link_bounce_work);
5467 }
50e5dcbe 5468 dd->rcv_ovfl_cnt = (u32)cur_ovfl_cnt;
77241056
MM		 5469
5470 mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME);
5471}
5472
5473static int init_rcverr(struct hfi1_devdata *dd)
5474{
24523a94 5475 setup_timer(&dd->rcverr_timer, update_rcverr_timer, (unsigned long)dd);
77241056
MM		 5476 /* Assume the hardware counter has been reset */
5477 dd->rcv_ovfl_cnt = 0;
5478 return mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME);
5479}
5480
5481static void free_rcverr(struct hfi1_devdata *dd)
5482{
5483 if (dd->rcverr_timer.data)
5484 del_timer_sync(&dd->rcverr_timer);
5485 dd->rcverr_timer.data = 0;
5486}
5487
5488static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5489{
5490 char buf[96];
2c5b521a 5491 int i = 0;
77241056
MM		 5492
5493 dd_dev_info(dd, "Receive Error: %s\n",
17fb4f29 5494 rxe_err_status_string(buf, sizeof(buf), reg));
77241056
MM		 5495
5496 if (reg & ALL_RXE_FREEZE_ERR) {
5497 int flags = 0;
5498
5499 /*
5500 * Freeze mode recovery is disabled for the errors
5501 * in RXE_FREEZE_ABORT_MASK
5502 */
995deafa 5503 if (is_ax(dd) && (reg & RXE_FREEZE_ABORT_MASK))
77241056
MM		 5504 flags = FREEZE_ABORT;
5505
5506 start_freeze_handling(dd->pport, flags);
5507 }
2c5b521a
JR		 5508
5509 for (i = 0; i < NUM_RCV_ERR_STATUS_COUNTERS; i++) {
5510 if (reg & (1ull << i))
5511 incr_cntr64(&dd->rcv_err_status_cnt[i]);
5512 }
77241056
MM		 5513}
5514
5515static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5516{
5517 char buf[96];
2c5b521a 5518 int i = 0;
77241056
MM		 5519
5520 dd_dev_info(dd, "Misc Error: %s",
17fb4f29 5521 misc_err_status_string(buf, sizeof(buf), reg));
2c5b521a
JR		 5522 for (i = 0; i < NUM_MISC_ERR_STATUS_COUNTERS; i++) {
5523 if (reg & (1ull << i))
5524 incr_cntr64(&dd->misc_err_status_cnt[i]);
5525 }
77241056
MM		 5526}
5527
5528static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5529{
5530 char buf[96];
2c5b521a 5531 int i = 0;
77241056
MM		 5532
5533 dd_dev_info(dd, "PIO Error: %s\n",
17fb4f29 5534 pio_err_status_string(buf, sizeof(buf), reg));
77241056
MM		 5535
5536 if (reg & ALL_PIO_FREEZE_ERR)
5537 start_freeze_handling(dd->pport, 0);
2c5b521a
JR		 5538
5539 for (i = 0; i < NUM_SEND_PIO_ERR_STATUS_COUNTERS; i++) {
5540 if (reg & (1ull << i))
5541 incr_cntr64(&dd->send_pio_err_status_cnt[i]);
5542 }
77241056
MM		 5543}
5544
5545static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5546{
5547 char buf[96];
2c5b521a 5548 int i = 0;
77241056
MM		 5549
5550 dd_dev_info(dd, "SDMA Error: %s\n",
17fb4f29 5551 sdma_err_status_string(buf, sizeof(buf), reg));
77241056
MM		 5552
5553 if (reg & ALL_SDMA_FREEZE_ERR)
5554 start_freeze_handling(dd->pport, 0);
2c5b521a
JR		 5555
5556 for (i = 0; i < NUM_SEND_DMA_ERR_STATUS_COUNTERS; i++) {
5557 if (reg & (1ull << i))
5558 incr_cntr64(&dd->send_dma_err_status_cnt[i]);
5559 }
77241056
MM		 5560}
5561
69a00b8e 5562static inline void __count_port_discards(struct hfi1_pportdata *ppd)
77241056 5563{
69a00b8e
MM		 5564 incr_cntr64(&ppd->port_xmit_discards);
5565}
77241056 5566
69a00b8e
MM		 5567static void count_port_inactive(struct hfi1_devdata *dd)
5568{
5569 __count_port_discards(dd->pport);
77241056
MM		 5570}
5571
5572/*
5573 * We have had a "disallowed packet" error during egress. Determine the
5574 * integrity check which failed, and update relevant error counter, etc.
5575 *
5576 * Note that the SEND_EGRESS_ERR_INFO register has only a single
5577 * bit of state per integrity check, and so we can miss the reason for an
5578 * egress error if more than one packet fails the same integrity check
5579 * since we cleared the corresponding bit in SEND_EGRESS_ERR_INFO.
5580 */
69a00b8e
MM		 5581static void handle_send_egress_err_info(struct hfi1_devdata *dd,
5582 int vl)
77241056
MM		 5583{
5584 struct hfi1_pportdata *ppd = dd->pport;
5585 u64 src = read_csr(dd, SEND_EGRESS_ERR_SOURCE); /* read first */
5586 u64 info = read_csr(dd, SEND_EGRESS_ERR_INFO);
5587 char buf[96];
5588
5589 /* clear down all observed info as quickly as possible after read */
5590 write_csr(dd, SEND_EGRESS_ERR_INFO, info);
5591
5592 dd_dev_info(dd,
17fb4f29
JJ		 5593 "Egress Error Info: 0x%llx, %s Egress Error Src 0x%llx\n",
5594 info, egress_err_info_string(buf, sizeof(buf), info), src);
77241056
MM		 5595
5596 /* Eventually add other counters for each bit */
69a00b8e
MM		 5597 if (info & PORT_DISCARD_EGRESS_ERRS) {
5598 int weight, i;
77241056 5599
69a00b8e 5600 /*
4c9e7aac
DL		 5601 * Count all applicable bits as individual errors and
5602 * attribute them to the packet that triggered this handler.
5603 * This may not be completely accurate due to limitations
5604 * on the available hardware error information. There is
5605 * a single information register and any number of error
5606 * packets may have occurred and contributed to it before
5607 * this routine is called. This means that:
5608 * a) If multiple packets with the same error occur before
5609 * this routine is called, earlier packets are missed.
5610 * There is only a single bit for each error type.
5611 * b) Errors may not be attributed to the correct VL.
5612 * The driver is attributing all bits in the info register
5613 * to the packet that triggered this call, but bits
5614 * could be an accumulation of different packets with
5615 * different VLs.
5616 * c) A single error packet may have multiple counts attached
5617 * to it. There is no way for the driver to know if
5618 * multiple bits set in the info register are due to a
5619 * single packet or multiple packets. The driver assumes
5620 * multiple packets.
69a00b8e 5621 */
4c9e7aac 5622 weight = hweight64(info & PORT_DISCARD_EGRESS_ERRS);
69a00b8e
MM		 5623 for (i = 0; i < weight; i++) {
5624 __count_port_discards(ppd);
5625 if (vl >= 0 && vl < TXE_NUM_DATA_VL)
5626 incr_cntr64(&ppd->port_xmit_discards_vl[vl]);
5627 else if (vl == 15)
5628 incr_cntr64(&ppd->port_xmit_discards_vl
5629 [C_VL_15]);
5630 }
77241056
MM		 5631 }
5632}
5633
5634/*
5635 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5636 * register. Does it represent a 'port inactive' error?
5637 */
5638static inline int port_inactive_err(u64 posn)
5639{
5640 return (posn >= SEES(TX_LINKDOWN) &&
5641 posn <= SEES(TX_INCORRECT_LINK_STATE));
5642}
5643
5644/*
5645 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5646 * register. Does it represent a 'disallowed packet' error?
5647 */
69a00b8e 5648static inline int disallowed_pkt_err(int posn)
77241056
MM		 5649{
5650 return (posn >= SEES(TX_SDMA0_DISALLOWED_PACKET) &&
5651 posn <= SEES(TX_SDMA15_DISALLOWED_PACKET));
5652}
5653
69a00b8e
MM		 5654/*
5655 * Input value is a bit position of one of the SDMA engine disallowed
5656 * packet errors. Return which engine. Use of this must be guarded by
5657 * disallowed_pkt_err().
5658 */
5659static inline int disallowed_pkt_engine(int posn)
5660{
5661 return posn - SEES(TX_SDMA0_DISALLOWED_PACKET);
5662}
5663
5664/*
5665 * Translate an SDMA engine to a VL. Return -1 if the tranlation cannot
5666 * be done.
5667 */
5668static int engine_to_vl(struct hfi1_devdata *dd, int engine)
5669{
5670 struct sdma_vl_map *m;
5671 int vl;
5672
5673 /* range check */
5674 if (engine < 0 || engine >= TXE_NUM_SDMA_ENGINES)
5675 return -1;
5676
5677 rcu_read_lock();
5678 m = rcu_dereference(dd->sdma_map);
5679 vl = m->engine_to_vl[engine];
5680 rcu_read_unlock();
5681
5682 return vl;
5683}
5684
5685/*
5686 * Translate the send context (sofware index) into a VL. Return -1 if the
5687 * translation cannot be done.
5688 */
5689static int sc_to_vl(struct hfi1_devdata *dd, int sw_index)
5690{
5691 struct send_context_info *sci;
5692 struct send_context *sc;
5693 int i;
5694
5695 sci = &dd->send_contexts[sw_index];
5696
5697 /* there is no information for user (PSM) and ack contexts */
44306f15 5698 if ((sci->type != SC_KERNEL) && (sci->type != SC_VL15))
69a00b8e
MM		 5699 return -1;
5700
5701 sc = sci->sc;
5702 if (!sc)
5703 return -1;
5704 if (dd->vld[15].sc == sc)
5705 return 15;
5706 for (i = 0; i < num_vls; i++)
5707 if (dd->vld[i].sc == sc)
5708 return i;
5709
5710 return -1;
5711}
5712
77241056
MM		 5713static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5714{
5715 u64 reg_copy = reg, handled = 0;
5716 char buf[96];
2c5b521a 5717 int i = 0;
77241056
MM		 5718
5719 if (reg & ALL_TXE_EGRESS_FREEZE_ERR)
5720 start_freeze_handling(dd->pport, 0);
69a00b8e
MM		 5721 else if (is_ax(dd) &&
5722 (reg & SEND_EGRESS_ERR_STATUS_TX_CREDIT_RETURN_VL_ERR_SMASK) &&
5723 (dd->icode != ICODE_FUNCTIONAL_SIMULATOR))
77241056
MM		 5724 start_freeze_handling(dd->pport, 0);
5725
5726 while (reg_copy) {
5727 int posn = fls64(reg_copy);
69a00b8e 5728 /* fls64() returns a 1-based offset, we want it zero based */
77241056 5729 int shift = posn - 1;
69a00b8e 5730 u64 mask = 1ULL << shift;
77241056
MM		 5731
5732 if (port_inactive_err(shift)) {
5733 count_port_inactive(dd);
69a00b8e 5734 handled |= mask;
77241056 5735 } else if (disallowed_pkt_err(shift)) {
69a00b8e
MM		 5736 int vl = engine_to_vl(dd, disallowed_pkt_engine(shift));
5737
5738 handle_send_egress_err_info(dd, vl);
5739 handled |= mask;
77241056 5740 }
69a00b8e 5741 reg_copy &= ~mask;
77241056
MM		 5742 }
5743
5744 reg &= ~handled;
5745
5746 if (reg)
5747 dd_dev_info(dd, "Egress Error: %s\n",
17fb4f29 5748 egress_err_status_string(buf, sizeof(buf), reg));
2c5b521a
JR		 5749
5750 for (i = 0; i < NUM_SEND_EGRESS_ERR_STATUS_COUNTERS; i++) {
5751 if (reg & (1ull << i))
5752 incr_cntr64(&dd->send_egress_err_status_cnt[i]);
5753 }
77241056
MM		 5754}
5755
5756static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5757{
5758 char buf[96];
2c5b521a 5759 int i = 0;
77241056
MM		 5760
5761 dd_dev_info(dd, "Send Error: %s\n",
17fb4f29 5762 send_err_status_string(buf, sizeof(buf), reg));
77241056 5763
2c5b521a
JR		 5764 for (i = 0; i < NUM_SEND_ERR_STATUS_COUNTERS; i++) {
5765 if (reg & (1ull << i))
5766 incr_cntr64(&dd->send_err_status_cnt[i]);
5767 }
77241056
MM		 5768}
5769
5770/*
5771 * The maximum number of times the error clear down will loop before
5772 * blocking a repeating error. This value is arbitrary.
5773 */
5774#define MAX_CLEAR_COUNT 20
5775
5776/*
5777 * Clear and handle an error register. All error interrupts are funneled
5778 * through here to have a central location to correctly handle single-
5779 * or multi-shot errors.
5780 *
5781 * For non per-context registers, call this routine with a context value
5782 * of 0 so the per-context offset is zero.
5783 *
5784 * If the handler loops too many times, assume that something is wrong
5785 * and can't be fixed, so mask the error bits.
5786 */
5787static void interrupt_clear_down(struct hfi1_devdata *dd,
5788 u32 context,
5789 const struct err_reg_info *eri)
5790{
5791 u64 reg;
5792 u32 count;
5793
5794 /* read in a loop until no more errors are seen */
5795 count = 0;
5796 while (1) {
5797 reg = read_kctxt_csr(dd, context, eri->status);
5798 if (reg == 0)
5799 break;
5800 write_kctxt_csr(dd, context, eri->clear, reg);
5801 if (likely(eri->handler))
5802 eri->handler(dd, context, reg);
5803 count++;
5804 if (count > MAX_CLEAR_COUNT) {
5805 u64 mask;
5806
5807 dd_dev_err(dd, "Repeating %s bits 0x%llx - masking\n",
17fb4f29 5808 eri->desc, reg);
77241056
MM		 5809 /*
5810 * Read-modify-write so any other masked bits
5811 * remain masked.
5812 */
5813 mask = read_kctxt_csr(dd, context, eri->mask);
5814 mask &= ~reg;
5815 write_kctxt_csr(dd, context, eri->mask, mask);
5816 break;
5817 }
5818 }
5819}
5820
5821/*
5822 * CCE block "misc" interrupt. Source is < 16.
5823 */
5824static void is_misc_err_int(struct hfi1_devdata *dd, unsigned int source)
5825{
5826 const struct err_reg_info *eri = &misc_errs[source];
5827
5828 if (eri->handler) {
5829 interrupt_clear_down(dd, 0, eri);
5830 } else {
5831 dd_dev_err(dd, "Unexpected misc interrupt (%u) - reserved\n",
17fb4f29 5832 source);
77241056
MM		 5833 }
5834}
5835
5836static char *send_context_err_status_string(char *buf, int buf_len, u64 flags)
5837{
5838 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5839 sc_err_status_flags,
5840 ARRAY_SIZE(sc_err_status_flags));
77241056
MM		 5841}
5842
5843/*
5844 * Send context error interrupt. Source (hw_context) is < 160.
5845 *
5846 * All send context errors cause the send context to halt. The normal
5847 * clear-down mechanism cannot be used because we cannot clear the
5848 * error bits until several other long-running items are done first.
5849 * This is OK because with the context halted, nothing else is going
5850 * to happen on it anyway.
5851 */
5852static void is_sendctxt_err_int(struct hfi1_devdata *dd,
5853 unsigned int hw_context)
5854{
5855 struct send_context_info *sci;
5856 struct send_context *sc;
5857 char flags[96];
5858 u64 status;
5859 u32 sw_index;
2c5b521a 5860 int i = 0;
77241056
MM		 5861
5862 sw_index = dd->hw_to_sw[hw_context];
5863 if (sw_index >= dd->num_send_contexts) {
5864 dd_dev_err(dd,
17fb4f29
JJ		 5865 "out of range sw index %u for send context %u\n",
5866 sw_index, hw_context);
77241056
MM		 5867 return;
5868 }
5869 sci = &dd->send_contexts[sw_index];
5870 sc = sci->sc;
5871 if (!sc) {
5872 dd_dev_err(dd, "%s: context %u(%u): no sc?\n", __func__,
17fb4f29 5873 sw_index, hw_context);
77241056
MM		 5874 return;
5875 }
5876
5877 /* tell the software that a halt has begun */
5878 sc_stop(sc, SCF_HALTED);
5879
5880 status = read_kctxt_csr(dd, hw_context, SEND_CTXT_ERR_STATUS);
5881
5882 dd_dev_info(dd, "Send Context %u(%u) Error: %s\n", sw_index, hw_context,
17fb4f29
JJ		 5883 send_context_err_status_string(flags, sizeof(flags),
5884 status));
77241056
MM		 5885
5886 if (status & SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK)
69a00b8e 5887 handle_send_egress_err_info(dd, sc_to_vl(dd, sw_index));
77241056
MM		 5888
5889 /*
5890 * Automatically restart halted kernel contexts out of interrupt
5891 * context. User contexts must ask the driver to restart the context.
5892 */
5893 if (sc->type != SC_USER)
5894 queue_work(dd->pport->hfi1_wq, &sc->halt_work);
2c5b521a
JR		 5895
5896 /*
5897 * Update the counters for the corresponding status bits.
5898 * Note that these particular counters are aggregated over all
5899 * 160 contexts.
5900 */
5901 for (i = 0; i < NUM_SEND_CTXT_ERR_STATUS_COUNTERS; i++) {
5902 if (status & (1ull << i))
5903 incr_cntr64(&dd->sw_ctxt_err_status_cnt[i]);
5904 }
77241056
MM		 5905}
5906
5907static void handle_sdma_eng_err(struct hfi1_devdata *dd,
5908 unsigned int source, u64 status)
5909{
5910 struct sdma_engine *sde;
2c5b521a 5911 int i = 0;
77241056
MM		 5912
5913 sde = &dd->per_sdma[source];
5914#ifdef CONFIG_SDMA_VERBOSITY
5915 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
5916 slashstrip(__FILE__), __LINE__, __func__);
5917 dd_dev_err(sde->dd, "CONFIG SDMA(%u) source: %u status 0x%llx\n",
5918 sde->this_idx, source, (unsigned long long)status);
5919#endif
a699c6c2 5920 sde->err_cnt++;
77241056 5921 sdma_engine_error(sde, status);
2c5b521a
JR		 5922
5923 /*
5924 * Update the counters for the corresponding status bits.
5925 * Note that these particular counters are aggregated over
5926 * all 16 DMA engines.
5927 */
5928 for (i = 0; i < NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS; i++) {
5929 if (status & (1ull << i))
5930 incr_cntr64(&dd->sw_send_dma_eng_err_status_cnt[i]);
5931 }
77241056
MM		 5932}
5933
5934/*
5935 * CCE block SDMA error interrupt. Source is < 16.
5936 */
5937static void is_sdma_eng_err_int(struct hfi1_devdata *dd, unsigned int source)
5938{
5939#ifdef CONFIG_SDMA_VERBOSITY
5940 struct sdma_engine *sde = &dd->per_sdma[source];
5941
5942 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
5943 slashstrip(__FILE__), __LINE__, __func__);
5944 dd_dev_err(dd, "CONFIG SDMA(%u) source: %u\n", sde->this_idx,
5945 source);
5946 sdma_dumpstate(sde);
5947#endif
5948 interrupt_clear_down(dd, source, &sdma_eng_err);
5949}
5950
5951/*
5952 * CCE block "various" interrupt. Source is < 8.
5953 */
5954static void is_various_int(struct hfi1_devdata *dd, unsigned int source)
5955{
5956 const struct err_reg_info *eri = &various_err[source];
5957
5958 /*
5959 * TCritInt cannot go through interrupt_clear_down()
5960 * because it is not a second tier interrupt. The handler
5961 * should be called directly.
5962 */
5963 if (source == TCRIT_INT_SOURCE)
5964 handle_temp_err(dd);
5965 else if (eri->handler)
5966 interrupt_clear_down(dd, 0, eri);
5967 else
5968 dd_dev_info(dd,
17fb4f29
JJ		 5969 "%s: Unimplemented/reserved interrupt %d\n",
5970 __func__, source);
77241056
MM		 5971}
5972
5973static void handle_qsfp_int(struct hfi1_devdata *dd, u32 src_ctx, u64 reg)
5974{
8ebd4cf1 5975 /* src_ctx is always zero */
77241056
MM		 5976 struct hfi1_pportdata *ppd = dd->pport;
5977 unsigned long flags;
5978 u64 qsfp_int_mgmt = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N);
5979
5980 if (reg & QSFP_HFI0_MODPRST_N) {
77241056 5981 if (!qsfp_mod_present(ppd)) {
e8aa284b
EH		 5982 dd_dev_info(dd, "%s: QSFP module removed\n",
5983 __func__);
5984
77241056
MM		 5985 ppd->driver_link_ready = 0;
5986 /*
5987 * Cable removed, reset all our information about the
5988 * cache and cable capabilities
5989 */
5990
5991 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
5992 /*
5993 * We don't set cache_refresh_required here as we expect
5994 * an interrupt when a cable is inserted
5995 */
5996 ppd->qsfp_info.cache_valid = 0;
8ebd4cf1
EH		 5997 ppd->qsfp_info.reset_needed = 0;
5998 ppd->qsfp_info.limiting_active = 0;
77241056 5999 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
17fb4f29 6000 flags);
8ebd4cf1
EH		 6001 /* Invert the ModPresent pin now to detect plug-in */
6002 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
6003 ASIC_QSFP1_INVERT, qsfp_int_mgmt);
a9c05e35
BM		 6004
6005 if ((ppd->offline_disabled_reason >
6006 HFI1_ODR_MASK(
e1bf0d5e 6007 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED)) ||
a9c05e35
BM		 6008 (ppd->offline_disabled_reason ==
6009 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE)))
6010 ppd->offline_disabled_reason =
6011 HFI1_ODR_MASK(
e1bf0d5e 6012 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED);
a9c05e35 6013
77241056
MM		 6014 if (ppd->host_link_state == HLS_DN_POLL) {
6015 /*
6016 * The link is still in POLL. This means
6017 * that the normal link down processing
6018 * will not happen. We have to do it here
6019 * before turning the DC off.
6020 */
6021 queue_work(ppd->hfi1_wq, &ppd->link_down_work);
6022 }
6023 } else {
e8aa284b
EH		 6024 dd_dev_info(dd, "%s: QSFP module inserted\n",
6025 __func__);
6026
77241056
MM		 6027 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
6028 ppd->qsfp_info.cache_valid = 0;
6029 ppd->qsfp_info.cache_refresh_required = 1;
6030 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
17fb4f29 6031 flags);
77241056 6032
8ebd4cf1
EH		 6033 /*
6034 * Stop inversion of ModPresent pin to detect
6035 * removal of the cable
6036 */
77241056 6037 qsfp_int_mgmt &= ~(u64)QSFP_HFI0_MODPRST_N;
8ebd4cf1
EH		 6038 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
6039 ASIC_QSFP1_INVERT, qsfp_int_mgmt);
6040
6041 ppd->offline_disabled_reason =
6042 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT);
77241056
MM		 6043 }
6044 }
6045
6046 if (reg & QSFP_HFI0_INT_N) {
e8aa284b 6047 dd_dev_info(dd, "%s: Interrupt received from QSFP module\n",
17fb4f29 6048 __func__);
77241056
MM		 6049 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
6050 ppd->qsfp_info.check_interrupt_flags = 1;
77241056
MM		 6051 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, flags);
6052 }
6053
6054 /* Schedule the QSFP work only if there is a cable attached. */
6055 if (qsfp_mod_present(ppd))
6056 queue_work(ppd->hfi1_wq, &ppd->qsfp_info.qsfp_work);
6057}
6058
6059static int request_host_lcb_access(struct hfi1_devdata *dd)
6060{
6061 int ret;
6062
6063 ret = do_8051_command(dd, HCMD_MISC,
17fb4f29
JJ		 6064 (u64)HCMD_MISC_REQUEST_LCB_ACCESS <<
6065 LOAD_DATA_FIELD_ID_SHIFT, NULL);
77241056
MM		 6066 if (ret != HCMD_SUCCESS) {
6067 dd_dev_err(dd, "%s: command failed with error %d\n",
17fb4f29 6068 __func__, ret);
77241056
MM		 6069 }
6070 return ret == HCMD_SUCCESS ? 0 : -EBUSY;
6071}
6072
6073static int request_8051_lcb_access(struct hfi1_devdata *dd)
6074{
6075 int ret;
6076
6077 ret = do_8051_command(dd, HCMD_MISC,
17fb4f29
JJ		 6078 (u64)HCMD_MISC_GRANT_LCB_ACCESS <<
6079 LOAD_DATA_FIELD_ID_SHIFT, NULL);
77241056
MM		 6080 if (ret != HCMD_SUCCESS) {
6081 dd_dev_err(dd, "%s: command failed with error %d\n",
17fb4f29 6082 __func__, ret);
77241056
MM		 6083 }
6084 return ret == HCMD_SUCCESS ? 0 : -EBUSY;
6085}
6086
6087/*
6088 * Set the LCB selector - allow host access. The DCC selector always
6089 * points to the host.
6090 */
6091static inline void set_host_lcb_access(struct hfi1_devdata *dd)
6092{
6093 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
17fb4f29
JJ		 6094 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK |
6095 DC_DC8051_CFG_CSR_ACCESS_SEL_LCB_SMASK);
77241056
MM		 6096}
6097
6098/*
6099 * Clear the LCB selector - allow 8051 access. The DCC selector always
6100 * points to the host.
6101 */
6102static inline void set_8051_lcb_access(struct hfi1_devdata *dd)
6103{
6104 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
17fb4f29 6105 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK);
77241056
MM		 6106}
6107
6108/*
6109 * Acquire LCB access from the 8051. If the host already has access,
6110 * just increment a counter. Otherwise, inform the 8051 that the
6111 * host is taking access.
6112 *
6113 * Returns:
6114 * 0 on success
6115 * -EBUSY if the 8051 has control and cannot be disturbed
6116 * -errno if unable to acquire access from the 8051
6117 */
6118int acquire_lcb_access(struct hfi1_devdata *dd, int sleep_ok)
6119{
6120 struct hfi1_pportdata *ppd = dd->pport;
6121 int ret = 0;
6122
6123 /*
6124 * Use the host link state lock so the operation of this routine
6125 * { link state check, selector change, count increment } can occur
6126 * as a unit against a link state change. Otherwise there is a
6127 * race between the state change and the count increment.
6128 */
6129 if (sleep_ok) {
6130 mutex_lock(&ppd->hls_lock);
6131 } else {
951842b0 6132 while (!mutex_trylock(&ppd->hls_lock))
77241056
MM		 6133 udelay(1);
6134 }
6135
6136 /* this access is valid only when the link is up */
0c7f77af 6137 if (ppd->host_link_state & HLS_DOWN) {
77241056 6138 dd_dev_info(dd, "%s: link state %s not up\n",
17fb4f29 6139 __func__, link_state_name(ppd->host_link_state));
77241056
MM		 6140 ret = -EBUSY;
6141 goto done;
6142 }
6143
6144 if (dd->lcb_access_count == 0) {
6145 ret = request_host_lcb_access(dd);
6146 if (ret) {
6147 dd_dev_err(dd,
17fb4f29
JJ		 6148 "%s: unable to acquire LCB access, err %d\n",
6149 __func__, ret);
77241056
MM		 6150 goto done;
6151 }
6152 set_host_lcb_access(dd);
6153 }
6154 dd->lcb_access_count++;
6155done:
6156 mutex_unlock(&ppd->hls_lock);
6157 return ret;
6158}
6159
6160/*
6161 * Release LCB access by decrementing the use count. If the count is moving
6162 * from 1 to 0, inform 8051 that it has control back.
6163 *
6164 * Returns:
6165 * 0 on success
6166 * -errno if unable to release access to the 8051
6167 */
6168int release_lcb_access(struct hfi1_devdata *dd, int sleep_ok)
6169{
6170 int ret = 0;
6171
6172 /*
6173 * Use the host link state lock because the acquire needed it.
6174 * Here, we only need to keep { selector change, count decrement }
6175 * as a unit.
6176 */
6177 if (sleep_ok) {
6178 mutex_lock(&dd->pport->hls_lock);
6179 } else {
951842b0 6180 while (!mutex_trylock(&dd->pport->hls_lock))
77241056
MM		 6181 udelay(1);
6182 }
6183
6184 if (dd->lcb_access_count == 0) {
6185 dd_dev_err(dd, "%s: LCB access count is zero. Skipping.\n",
17fb4f29 6186 __func__);
77241056
MM		 6187 goto done;
6188 }
6189
6190 if (dd->lcb_access_count == 1) {
6191 set_8051_lcb_access(dd);
6192 ret = request_8051_lcb_access(dd);
6193 if (ret) {
6194 dd_dev_err(dd,
17fb4f29
JJ		 6195 "%s: unable to release LCB access, err %d\n",
6196 __func__, ret);
77241056
MM		 6197 /* restore host access if the grant didn't work */
6198 set_host_lcb_access(dd);
6199 goto done;
6200 }
6201 }
6202 dd->lcb_access_count--;
6203done:
6204 mutex_unlock(&dd->pport->hls_lock);
6205 return ret;
6206}
6207
6208/*
6209 * Initialize LCB access variables and state. Called during driver load,
6210 * after most of the initialization is finished.
6211 *
6212 * The DC default is LCB access on for the host. The driver defaults to
6213 * leaving access to the 8051. Assign access now - this constrains the call
6214 * to this routine to be after all LCB set-up is done. In particular, after
6215 * hf1_init_dd() -> set_up_interrupts() -> clear_all_interrupts()
6216 */
6217static void init_lcb_access(struct hfi1_devdata *dd)
6218{
6219 dd->lcb_access_count = 0;
6220}
6221
6222/*
6223 * Write a response back to a 8051 request.
6224 */
6225static void hreq_response(struct hfi1_devdata *dd, u8 return_code, u16 rsp_data)
6226{
6227 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0,
17fb4f29
JJ		 6228 DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK |
6229 (u64)return_code <<
6230 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT |
6231 (u64)rsp_data << DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT);
77241056
MM		 6232}
6233
6234/*
cbac386a 6235 * Handle host requests from the 8051.
77241056 6236 */
145dd2b3 6237static void handle_8051_request(struct hfi1_pportdata *ppd)
77241056 6238{
cbac386a 6239 struct hfi1_devdata *dd = ppd->dd;
77241056 6240 u64 reg;
cbac386a 6241 u16 data = 0;
145dd2b3 6242 u8 type;
77241056
MM		 6243
6244 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_1);
6245 if ((reg & DC_DC8051_CFG_EXT_DEV_1_REQ_NEW_SMASK) == 0)
6246 return; /* no request */
6247
6248 /* zero out COMPLETED so the response is seen */
6249 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 0);
6250
6251 /* extract request details */
6252 type = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_SHIFT)
6253 & DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_MASK;
6254 data = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT)
6255 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_MASK;
6256
6257 switch (type) {
6258 case HREQ_LOAD_CONFIG:
6259 case HREQ_SAVE_CONFIG:
6260 case HREQ_READ_CONFIG:
6261 case HREQ_SET_TX_EQ_ABS:
6262 case HREQ_SET_TX_EQ_REL:
145dd2b3 6263 case HREQ_ENABLE:
77241056 6264 dd_dev_info(dd, "8051 request: request 0x%x not supported\n",
17fb4f29 6265 type);
77241056
MM		 6266 hreq_response(dd, HREQ_NOT_SUPPORTED, 0);
6267 break;
77241056
MM		 6268 case HREQ_CONFIG_DONE:
6269 hreq_response(dd, HREQ_SUCCESS, 0);
6270 break;
6271
6272 case HREQ_INTERFACE_TEST:
6273 hreq_response(dd, HREQ_SUCCESS, data);
6274 break;
77241056
MM		 6275 default:
6276 dd_dev_err(dd, "8051 request: unknown request 0x%x\n", type);
6277 hreq_response(dd, HREQ_NOT_SUPPORTED, 0);
6278 break;
6279 }
6280}
6281
6282static void write_global_credit(struct hfi1_devdata *dd,
6283 u8 vau, u16 total, u16 shared)
6284{
6285 write_csr(dd, SEND_CM_GLOBAL_CREDIT,
17fb4f29
JJ		 6286 ((u64)total <<
6287 SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT) |
6288 ((u64)shared <<
6289 SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT) |
6290 ((u64)vau << SEND_CM_GLOBAL_CREDIT_AU_SHIFT));
77241056
MM		 6291}
6292
6293/*
6294 * Set up initial VL15 credits of the remote. Assumes the rest of
6295 * the CM credit registers are zero from a previous global or credit reset .
6296 */
6297void set_up_vl15(struct hfi1_devdata *dd, u8 vau, u16 vl15buf)
6298{
6299 /* leave shared count at zero for both global and VL15 */
6300 write_global_credit(dd, vau, vl15buf, 0);
6301
6302 /* We may need some credits for another VL when sending packets
6303 * with the snoop interface. Dividing it down the middle for VL15
6304 * and VL0 should suffice.
6305 */
6306 if (unlikely(dd->hfi1_snoop.mode_flag == HFI1_PORT_SNOOP_MODE)) {
6307 write_csr(dd, SEND_CM_CREDIT_VL15, (u64)(vl15buf >> 1)
6308 << SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT);
6309 write_csr(dd, SEND_CM_CREDIT_VL, (u64)(vl15buf >> 1)
6310 << SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT);
6311 } else {
6312 write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf
6313 << SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT);
6314 }
6315}
6316
6317/*
6318 * Zero all credit details from the previous connection and
6319 * reset the CM manager's internal counters.
6320 */
6321void reset_link_credits(struct hfi1_devdata *dd)
6322{
6323 int i;
6324
6325 /* remove all previous VL credit limits */
6326 for (i = 0; i < TXE_NUM_DATA_VL; i++)
8638b77f 6327 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
77241056
MM		 6328 write_csr(dd, SEND_CM_CREDIT_VL15, 0);
6329 write_global_credit(dd, 0, 0, 0);
6330 /* reset the CM block */
6331 pio_send_control(dd, PSC_CM_RESET);
6332}
6333
6334/* convert a vCU to a CU */
6335static u32 vcu_to_cu(u8 vcu)
6336{
6337 return 1 << vcu;
6338}
6339
6340/* convert a CU to a vCU */
6341static u8 cu_to_vcu(u32 cu)
6342{
6343 return ilog2(cu);
6344}
6345
6346/* convert a vAU to an AU */
6347static u32 vau_to_au(u8 vau)
6348{
6349 return 8 * (1 << vau);
6350}
6351
6352static void set_linkup_defaults(struct hfi1_pportdata *ppd)
6353{
6354 ppd->sm_trap_qp = 0x0;
6355 ppd->sa_qp = 0x1;
6356}
6357
6358/*
6359 * Graceful LCB shutdown. This leaves the LCB FIFOs in reset.
6360 */
6361static void lcb_shutdown(struct hfi1_devdata *dd, int abort)
6362{
6363 u64 reg;
6364
6365 /* clear lcb run: LCB_CFG_RUN.EN = 0 */
6366 write_csr(dd, DC_LCB_CFG_RUN, 0);
6367 /* set tx fifo reset: LCB_CFG_TX_FIFOS_RESET.VAL = 1 */
6368 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET,
17fb4f29 6369 1ull << DC_LCB_CFG_TX_FIFOS_RESET_VAL_SHIFT);
77241056
MM		 6370 /* set dcc reset csr: DCC_CFG_RESET.{reset_lcb,reset_rx_fpe} = 1 */
6371 dd->lcb_err_en = read_csr(dd, DC_LCB_ERR_EN);
6372 reg = read_csr(dd, DCC_CFG_RESET);
17fb4f29
JJ		 6373 write_csr(dd, DCC_CFG_RESET, reg |
6374 (1ull << DCC_CFG_RESET_RESET_LCB_SHIFT) |
6375 (1ull << DCC_CFG_RESET_RESET_RX_FPE_SHIFT));
50e5dcbe 6376 (void)read_csr(dd, DCC_CFG_RESET); /* make sure the write completed */
77241056
MM		 6377 if (!abort) {
6378 udelay(1); /* must hold for the longer of 16cclks or 20ns */
6379 write_csr(dd, DCC_CFG_RESET, reg);
6380 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
6381 }
6382}
6383
6384/*
6385 * This routine should be called after the link has been transitioned to
6386 * OFFLINE (OFFLINE state has the side effect of putting the SerDes into
6387 * reset).
6388 *
6389 * The expectation is that the caller of this routine would have taken
6390 * care of properly transitioning the link into the correct state.
6391 */
6392static void dc_shutdown(struct hfi1_devdata *dd)
6393{
6394 unsigned long flags;
6395
6396 spin_lock_irqsave(&dd->dc8051_lock, flags);
6397 if (dd->dc_shutdown) {
6398 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
6399 return;
6400 }
6401 dd->dc_shutdown = 1;
6402 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
6403 /* Shutdown the LCB */
6404 lcb_shutdown(dd, 1);
4d114fdd
JJ		 6405 /*
6406 * Going to OFFLINE would have causes the 8051 to put the
77241056 6407 * SerDes into reset already. Just need to shut down the 8051,
4d114fdd
JJ		 6408 * itself.
6409 */
77241056
MM		 6410 write_csr(dd, DC_DC8051_CFG_RST, 0x1);
6411}
6412
4d114fdd
JJ		 6413/*
6414 * Calling this after the DC has been brought out of reset should not
6415 * do any damage.
6416 */
77241056
MM		 6417static void dc_start(struct hfi1_devdata *dd)
6418{
6419 unsigned long flags;
6420 int ret;
6421
6422 spin_lock_irqsave(&dd->dc8051_lock, flags);
6423 if (!dd->dc_shutdown)
6424 goto done;
6425 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
6426 /* Take the 8051 out of reset */
6427 write_csr(dd, DC_DC8051_CFG_RST, 0ull);
6428 /* Wait until 8051 is ready */
6429 ret = wait_fm_ready(dd, TIMEOUT_8051_START);
6430 if (ret) {
6431 dd_dev_err(dd, "%s: timeout starting 8051 firmware\n",
17fb4f29 6432 __func__);
77241056
MM		 6433 }
6434 /* Take away reset for LCB and RX FPE (set in lcb_shutdown). */
6435 write_csr(dd, DCC_CFG_RESET, 0x10);
6436 /* lcb_shutdown() with abort=1 does not restore these */
6437 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
6438 spin_lock_irqsave(&dd->dc8051_lock, flags);
6439 dd->dc_shutdown = 0;
6440done:
6441 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
6442}
6443
6444/*
6445 * These LCB adjustments are for the Aurora SerDes core in the FPGA.
6446 */
6447static void adjust_lcb_for_fpga_serdes(struct hfi1_devdata *dd)
6448{
6449 u64 rx_radr, tx_radr;
6450 u32 version;
6451
6452 if (dd->icode != ICODE_FPGA_EMULATION)
6453 return;
6454
6455 /*
6456 * These LCB defaults on emulator _s are good, nothing to do here:
6457 * LCB_CFG_TX_FIFOS_RADR
6458 * LCB_CFG_RX_FIFOS_RADR
6459 * LCB_CFG_LN_DCLK
6460 * LCB_CFG_IGNORE_LOST_RCLK
6461 */
6462 if (is_emulator_s(dd))
6463 return;
6464 /* else this is _p */
6465
6466 version = emulator_rev(dd);
995deafa 6467 if (!is_ax(dd))
77241056
MM		 6468 version = 0x2d; /* all B0 use 0x2d or higher settings */
6469
6470 if (version <= 0x12) {
6471 /* release 0x12 and below */
6472
6473 /*
6474 * LCB_CFG_RX_FIFOS_RADR.RST_VAL = 0x9
6475 * LCB_CFG_RX_FIFOS_RADR.OK_TO_JUMP_VAL = 0x9
6476 * LCB_CFG_RX_FIFOS_RADR.DO_NOT_JUMP_VAL = 0xa
6477 */
6478 rx_radr =
6479 0xaull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6480 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6481 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6482 /*
6483 * LCB_CFG_TX_FIFOS_RADR.ON_REINIT = 0 (default)
6484 * LCB_CFG_TX_FIFOS_RADR.RST_VAL = 6
6485 */
6486 tx_radr = 6ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6487 } else if (version <= 0x18) {
6488 /* release 0x13 up to 0x18 */
6489 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6490 rx_radr =
6491 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6492 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6493 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6494 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6495 } else if (version == 0x19) {
6496 /* release 0x19 */
6497 /* LCB_CFG_RX_FIFOS_RADR = 0xa99 */
6498 rx_radr =
6499 0xAull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6500 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6501 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6502 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6503 } else if (version == 0x1a) {
6504 /* release 0x1a */
6505 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6506 rx_radr =
6507 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6508 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6509 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6510 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6511 write_csr(dd, DC_LCB_CFG_LN_DCLK, 1ull);
6512 } else {
6513 /* release 0x1b and higher */
6514 /* LCB_CFG_RX_FIFOS_RADR = 0x877 */
6515 rx_radr =
6516 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6517 | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6518 | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6519 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6520 }
6521
6522 write_csr(dd, DC_LCB_CFG_RX_FIFOS_RADR, rx_radr);
6523 /* LCB_CFG_IGNORE_LOST_RCLK.EN = 1 */
6524 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK,
17fb4f29 6525 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK);
77241056
MM		 6526 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RADR, tx_radr);
6527}
6528
6529/*
6530 * Handle a SMA idle message
6531 *
6532 * This is a work-queue function outside of the interrupt.
6533 */
6534void handle_sma_message(struct work_struct *work)
6535{
6536 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6537 sma_message_work);
6538 struct hfi1_devdata *dd = ppd->dd;
6539 u64 msg;
6540 int ret;
6541
4d114fdd
JJ		 6542 /*
6543 * msg is bytes 1-4 of the 40-bit idle message - the command code
6544 * is stripped off
6545 */
77241056
MM		 6546 ret = read_idle_sma(dd, &msg);
6547 if (ret)
6548 return;
6549 dd_dev_info(dd, "%s: SMA message 0x%llx\n", __func__, msg);
6550 /*
6551 * React to the SMA message. Byte[1] (0 for us) is the command.
6552 */
6553 switch (msg & 0xff) {
6554 case SMA_IDLE_ARM:
6555 /*
6556 * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6557 * State Transitions
6558 *
6559 * Only expected in INIT or ARMED, discard otherwise.
6560 */
6561 if (ppd->host_link_state & (HLS_UP_INIT | HLS_UP_ARMED))
6562 ppd->neighbor_normal = 1;
6563 break;
6564 case SMA_IDLE_ACTIVE:
6565 /*
6566 * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6567 * State Transitions
6568 *
6569 * Can activate the node. Discard otherwise.
6570 */
d0d236ea
JJ		 6571 if (ppd->host_link_state == HLS_UP_ARMED &&
6572 ppd->is_active_optimize_enabled) {
77241056
MM		 6573 ppd->neighbor_normal = 1;
6574 ret = set_link_state(ppd, HLS_UP_ACTIVE);
6575 if (ret)
6576 dd_dev_err(
6577 dd,
6578 "%s: received Active SMA idle message, couldn't set link to Active\n",
6579 __func__);
6580 }
6581 break;
6582 default:
6583 dd_dev_err(dd,
17fb4f29
JJ		 6584 "%s: received unexpected SMA idle message 0x%llx\n",
6585 __func__, msg);
77241056
MM		 6586 break;
6587 }
6588}
6589
6590static void adjust_rcvctrl(struct hfi1_devdata *dd, u64 add, u64 clear)
6591{
6592 u64 rcvctrl;
6593 unsigned long flags;
6594
6595 spin_lock_irqsave(&dd->rcvctrl_lock, flags);
6596 rcvctrl = read_csr(dd, RCV_CTRL);
6597 rcvctrl |= add;
6598 rcvctrl &= ~clear;
6599 write_csr(dd, RCV_CTRL, rcvctrl);
6600 spin_unlock_irqrestore(&dd->rcvctrl_lock, flags);
6601}
6602
6603static inline void add_rcvctrl(struct hfi1_devdata *dd, u64 add)
6604{
6605 adjust_rcvctrl(dd, add, 0);
6606}
6607
6608static inline void clear_rcvctrl(struct hfi1_devdata *dd, u64 clear)
6609{
6610 adjust_rcvctrl(dd, 0, clear);
6611}
6612
6613/*
6614 * Called from all interrupt handlers to start handling an SPC freeze.
6615 */
6616void start_freeze_handling(struct hfi1_pportdata *ppd, int flags)
6617{
6618 struct hfi1_devdata *dd = ppd->dd;
6619 struct send_context *sc;
6620 int i;
6621
6622 if (flags & FREEZE_SELF)
6623 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
6624
6625 /* enter frozen mode */
6626 dd->flags |= HFI1_FROZEN;
6627
6628 /* notify all SDMA engines that they are going into a freeze */
6629 sdma_freeze_notify(dd, !!(flags & FREEZE_LINK_DOWN));
6630
6631 /* do halt pre-handling on all enabled send contexts */
6632 for (i = 0; i < dd->num_send_contexts; i++) {
6633 sc = dd->send_contexts[i].sc;
6634 if (sc && (sc->flags & SCF_ENABLED))
6635 sc_stop(sc, SCF_FROZEN | SCF_HALTED);
6636 }
6637
6638 /* Send context are frozen. Notify user space */
6639 hfi1_set_uevent_bits(ppd, _HFI1_EVENT_FROZEN_BIT);
6640
6641 if (flags & FREEZE_ABORT) {
6642 dd_dev_err(dd,
6643 "Aborted freeze recovery. Please REBOOT system\n");
6644 return;
6645 }
6646 /* queue non-interrupt handler */
6647 queue_work(ppd->hfi1_wq, &ppd->freeze_work);
6648}
6649
6650/*
6651 * Wait until all 4 sub-blocks indicate that they have frozen or unfrozen,
6652 * depending on the "freeze" parameter.
6653 *
6654 * No need to return an error if it times out, our only option
6655 * is to proceed anyway.
6656 */
6657static void wait_for_freeze_status(struct hfi1_devdata *dd, int freeze)
6658{
6659 unsigned long timeout;
6660 u64 reg;
6661
6662 timeout = jiffies + msecs_to_jiffies(FREEZE_STATUS_TIMEOUT);
6663 while (1) {
6664 reg = read_csr(dd, CCE_STATUS);
6665 if (freeze) {
6666 /* waiting until all indicators are set */
6667 if ((reg & ALL_FROZE) == ALL_FROZE)
6668 return; /* all done */
6669 } else {
6670 /* waiting until all indicators are clear */
6671 if ((reg & ALL_FROZE) == 0)
6672 return; /* all done */
6673 }
6674
6675 if (time_after(jiffies, timeout)) {
6676 dd_dev_err(dd,
17fb4f29
JJ		 6677 "Time out waiting for SPC %sfreeze, bits 0x%llx, expecting 0x%llx, continuing",
6678 freeze ? "" : "un", reg & ALL_FROZE,
6679 freeze ? ALL_FROZE : 0ull);
77241056
MM		 6680 return;
6681 }
6682 usleep_range(80, 120);
6683 }
6684}
6685
6686/*
6687 * Do all freeze handling for the RXE block.
6688 */
6689static void rxe_freeze(struct hfi1_devdata *dd)
6690{
6691 int i;
6692
6693 /* disable port */
6694 clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
6695
6696 /* disable all receive contexts */
6697 for (i = 0; i < dd->num_rcv_contexts; i++)
6698 hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS, i);
6699}
6700
6701/*
6702 * Unfreeze handling for the RXE block - kernel contexts only.
6703 * This will also enable the port. User contexts will do unfreeze
6704 * handling on a per-context basis as they call into the driver.
6705 *
6706 */
6707static void rxe_kernel_unfreeze(struct hfi1_devdata *dd)
6708{
566c157c 6709 u32 rcvmask;
77241056
MM		 6710 int i;
6711
6712 /* enable all kernel contexts */
566c157c
MH		 6713 for (i = 0; i < dd->n_krcv_queues; i++) {
6714 rcvmask = HFI1_RCVCTRL_CTXT_ENB;
6715 /* HFI1_RCVCTRL_TAILUPD_[ENB|DIS] needs to be set explicitly */
6716 rcvmask |= HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, DMA_RTAIL) ?
6717 HFI1_RCVCTRL_TAILUPD_ENB : HFI1_RCVCTRL_TAILUPD_DIS;
6718 hfi1_rcvctrl(dd, rcvmask, i);
6719 }
77241056
MM		 6720
6721 /* enable port */
6722 add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
6723}
6724
6725/*
6726 * Non-interrupt SPC freeze handling.
6727 *
6728 * This is a work-queue function outside of the triggering interrupt.
6729 */
6730void handle_freeze(struct work_struct *work)
6731{
6732 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6733 freeze_work);
6734 struct hfi1_devdata *dd = ppd->dd;
6735
6736 /* wait for freeze indicators on all affected blocks */
77241056
MM		 6737 wait_for_freeze_status(dd, 1);
6738
6739 /* SPC is now frozen */
6740
6741 /* do send PIO freeze steps */
6742 pio_freeze(dd);
6743
6744 /* do send DMA freeze steps */
6745 sdma_freeze(dd);
6746
6747 /* do send egress freeze steps - nothing to do */
6748
6749 /* do receive freeze steps */
6750 rxe_freeze(dd);
6751
6752 /*
6753 * Unfreeze the hardware - clear the freeze, wait for each
6754 * block's frozen bit to clear, then clear the frozen flag.
6755 */
6756 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
6757 wait_for_freeze_status(dd, 0);
6758
995deafa 6759 if (is_ax(dd)) {
77241056
MM		 6760 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
6761 wait_for_freeze_status(dd, 1);
6762 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
6763 wait_for_freeze_status(dd, 0);
6764 }
6765
6766 /* do send PIO unfreeze steps for kernel contexts */
6767 pio_kernel_unfreeze(dd);
6768
6769 /* do send DMA unfreeze steps */
6770 sdma_unfreeze(dd);
6771
6772 /* do send egress unfreeze steps - nothing to do */
6773
6774 /* do receive unfreeze steps for kernel contexts */
6775 rxe_kernel_unfreeze(dd);
6776
6777 /*
6778 * The unfreeze procedure touches global device registers when
6779 * it disables and re-enables RXE. Mark the device unfrozen
6780 * after all that is done so other parts of the driver waiting
6781 * for the device to unfreeze don't do things out of order.
6782 *
6783 * The above implies that the meaning of HFI1_FROZEN flag is
6784 * "Device has gone into freeze mode and freeze mode handling
6785 * is still in progress."
6786 *
6787 * The flag will be removed when freeze mode processing has
6788 * completed.
6789 */
6790 dd->flags &= ~HFI1_FROZEN;
6791 wake_up(&dd->event_queue);
6792
6793 /* no longer frozen */
77241056
MM		 6794}
6795
6796/*
6797 * Handle a link up interrupt from the 8051.
6798 *
6799 * This is a work-queue function outside of the interrupt.
6800 */
6801void handle_link_up(struct work_struct *work)
6802{
6803 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
17fb4f29 6804 link_up_work);
77241056
MM		 6805 set_link_state(ppd, HLS_UP_INIT);
6806
6807 /* cache the read of DC_LCB_STS_ROUND_TRIP_LTP_CNT */
6808 read_ltp_rtt(ppd->dd);
6809 /*
6810 * OPA specifies that certain counters are cleared on a transition
6811 * to link up, so do that.
6812 */
6813 clear_linkup_counters(ppd->dd);
6814 /*
6815 * And (re)set link up default values.
6816 */
6817 set_linkup_defaults(ppd);
6818
6819 /* enforce link speed enabled */
6820 if ((ppd->link_speed_active & ppd->link_speed_enabled) == 0) {
6821 /* oops - current speed is not enabled, bounce */
6822 dd_dev_err(ppd->dd,
17fb4f29
JJ		 6823 "Link speed active 0x%x is outside enabled 0x%x, downing link\n",
6824 ppd->link_speed_active, ppd->link_speed_enabled);
77241056 6825 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_SPEED_POLICY, 0,
17fb4f29 6826 OPA_LINKDOWN_REASON_SPEED_POLICY);
77241056 6827 set_link_state(ppd, HLS_DN_OFFLINE);
8ebd4cf1 6828 tune_serdes(ppd);
77241056
MM		 6829 start_link(ppd);
6830 }
6831}
6832
4d114fdd
JJ		 6833/*
6834 * Several pieces of LNI information were cached for SMA in ppd.
6835 * Reset these on link down
6836 */
77241056
MM		 6837static void reset_neighbor_info(struct hfi1_pportdata *ppd)
6838{
6839 ppd->neighbor_guid = 0;
6840 ppd->neighbor_port_number = 0;
6841 ppd->neighbor_type = 0;
6842 ppd->neighbor_fm_security = 0;
6843}
6844
feb831dd
DL		 6845static const char * const link_down_reason_strs[] = {
6846 [OPA_LINKDOWN_REASON_NONE] = "None",
6847 [OPA_LINKDOWN_REASON_RCV_ERROR_0] = "Recive error 0",
6848 [OPA_LINKDOWN_REASON_BAD_PKT_LEN] = "Bad packet length",
6849 [OPA_LINKDOWN_REASON_PKT_TOO_LONG] = "Packet too long",
6850 [OPA_LINKDOWN_REASON_PKT_TOO_SHORT] = "Packet too short",
6851 [OPA_LINKDOWN_REASON_BAD_SLID] = "Bad SLID",
6852 [OPA_LINKDOWN_REASON_BAD_DLID] = "Bad DLID",
6853 [OPA_LINKDOWN_REASON_BAD_L2] = "Bad L2",
6854 [OPA_LINKDOWN_REASON_BAD_SC] = "Bad SC",
6855 [OPA_LINKDOWN_REASON_RCV_ERROR_8] = "Receive error 8",
6856 [OPA_LINKDOWN_REASON_BAD_MID_TAIL] = "Bad mid tail",
6857 [OPA_LINKDOWN_REASON_RCV_ERROR_10] = "Receive error 10",
6858 [OPA_LINKDOWN_REASON_PREEMPT_ERROR] = "Preempt error",
6859 [OPA_LINKDOWN_REASON_PREEMPT_VL15] = "Preempt vl15",
6860 [OPA_LINKDOWN_REASON_BAD_VL_MARKER] = "Bad VL marker",
6861 [OPA_LINKDOWN_REASON_RCV_ERROR_14] = "Receive error 14",
6862 [OPA_LINKDOWN_REASON_RCV_ERROR_15] = "Receive error 15",
6863 [OPA_LINKDOWN_REASON_BAD_HEAD_DIST] = "Bad head distance",
6864 [OPA_LINKDOWN_REASON_BAD_TAIL_DIST] = "Bad tail distance",
6865 [OPA_LINKDOWN_REASON_BAD_CTRL_DIST] = "Bad control distance",
6866 [OPA_LINKDOWN_REASON_BAD_CREDIT_ACK] = "Bad credit ack",
6867 [OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER] = "Unsupported VL marker",
6868 [OPA_LINKDOWN_REASON_BAD_PREEMPT] = "Bad preempt",
6869 [OPA_LINKDOWN_REASON_BAD_CONTROL_FLIT] = "Bad control flit",
6870 [OPA_LINKDOWN_REASON_EXCEED_MULTICAST_LIMIT] = "Exceed multicast limit",
6871 [OPA_LINKDOWN_REASON_RCV_ERROR_24] = "Receive error 24",
6872 [OPA_LINKDOWN_REASON_RCV_ERROR_25] = "Receive error 25",
6873 [OPA_LINKDOWN_REASON_RCV_ERROR_26] = "Receive error 26",
6874 [OPA_LINKDOWN_REASON_RCV_ERROR_27] = "Receive error 27",
6875 [OPA_LINKDOWN_REASON_RCV_ERROR_28] = "Receive error 28",
6876 [OPA_LINKDOWN_REASON_RCV_ERROR_29] = "Receive error 29",
6877 [OPA_LINKDOWN_REASON_RCV_ERROR_30] = "Receive error 30",
6878 [OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN] =
6879 "Excessive buffer overrun",
6880 [OPA_LINKDOWN_REASON_UNKNOWN] = "Unknown",
6881 [OPA_LINKDOWN_REASON_REBOOT] = "Reboot",
6882 [OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN] = "Neighbor unknown",
6883 [OPA_LINKDOWN_REASON_FM_BOUNCE] = "FM bounce",
6884 [OPA_LINKDOWN_REASON_SPEED_POLICY] = "Speed policy",
6885 [OPA_LINKDOWN_REASON_WIDTH_POLICY] = "Width policy",
6886 [OPA_LINKDOWN_REASON_DISCONNECTED] = "Disconnected",
6887 [OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED] =
6888 "Local media not installed",
6889 [OPA_LINKDOWN_REASON_NOT_INSTALLED] = "Not installed",
6890 [OPA_LINKDOWN_REASON_CHASSIS_CONFIG] = "Chassis config",
6891 [OPA_LINKDOWN_REASON_END_TO_END_NOT_INSTALLED] =
6892 "End to end not installed",
6893 [OPA_LINKDOWN_REASON_POWER_POLICY] = "Power policy",
6894 [OPA_LINKDOWN_REASON_LINKSPEED_POLICY] = "Link speed policy",
6895 [OPA_LINKDOWN_REASON_LINKWIDTH_POLICY] = "Link width policy",
6896 [OPA_LINKDOWN_REASON_SWITCH_MGMT] = "Switch management",
6897 [OPA_LINKDOWN_REASON_SMA_DISABLED] = "SMA disabled",
6898 [OPA_LINKDOWN_REASON_TRANSIENT] = "Transient"
6899};
6900
6901/* return the neighbor link down reason string */
6902static const char *link_down_reason_str(u8 reason)
6903{
6904 const char *str = NULL;
6905
6906 if (reason < ARRAY_SIZE(link_down_reason_strs))
6907 str = link_down_reason_strs[reason];
6908 if (!str)
6909 str = "(invalid)";
6910
6911 return str;
6912}
6913
77241056
MM		 6914/*
6915 * Handle a link down interrupt from the 8051.
6916 *
6917 * This is a work-queue function outside of the interrupt.
6918 */
6919void handle_link_down(struct work_struct *work)
6920{
6921 u8 lcl_reason, neigh_reason = 0;
feb831dd 6922 u8 link_down_reason;
77241056 6923 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
feb831dd
DL		 6924 link_down_work);
6925 int was_up;
6926 static const char ldr_str[] = "Link down reason: ";
77241056 6927
8ebd4cf1
EH		 6928 if ((ppd->host_link_state &
6929 (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) &&
6930 ppd->port_type == PORT_TYPE_FIXED)
6931 ppd->offline_disabled_reason =
6932 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NOT_INSTALLED);
6933
6934 /* Go offline first, then deal with reading/writing through 8051 */
feb831dd 6935 was_up = !!(ppd->host_link_state & HLS_UP);
77241056
MM		 6936 set_link_state(ppd, HLS_DN_OFFLINE);
6937
feb831dd
DL		 6938 if (was_up) {
6939 lcl_reason = 0;
6940 /* link down reason is only valid if the link was up */
6941 read_link_down_reason(ppd->dd, &link_down_reason);
6942 switch (link_down_reason) {
6943 case LDR_LINK_TRANSFER_ACTIVE_LOW:
6944 /* the link went down, no idle message reason */
6945 dd_dev_info(ppd->dd, "%sUnexpected link down\n",
6946 ldr_str);
6947 break;
6948 case LDR_RECEIVED_LINKDOWN_IDLE_MSG:
6949 /*
6950 * The neighbor reason is only valid if an idle message
6951 * was received for it.
6952 */
6953 read_planned_down_reason_code(ppd->dd, &neigh_reason);
6954 dd_dev_info(ppd->dd,
6955 "%sNeighbor link down message %d, %s\n",
6956 ldr_str, neigh_reason,
6957 link_down_reason_str(neigh_reason));
6958 break;
6959 case LDR_RECEIVED_HOST_OFFLINE_REQ:
6960 dd_dev_info(ppd->dd,
6961 "%sHost requested link to go offline\n",
6962 ldr_str);
6963 break;
6964 default:
6965 dd_dev_info(ppd->dd, "%sUnknown reason 0x%x\n",
6966 ldr_str, link_down_reason);
6967 break;
6968 }
77241056 6969
feb831dd
DL		 6970 /*
6971 * If no reason, assume peer-initiated but missed
6972 * LinkGoingDown idle flits.
6973 */
6974 if (neigh_reason == 0)
6975 lcl_reason = OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN;
6976 } else {
6977 /* went down while polling or going up */
6978 lcl_reason = OPA_LINKDOWN_REASON_TRANSIENT;
6979 }
77241056
MM		 6980
6981 set_link_down_reason(ppd, lcl_reason, neigh_reason, 0);
6982
015e91fb
DL		 6983 /* inform the SMA when the link transitions from up to down */
6984 if (was_up && ppd->local_link_down_reason.sma == 0 &&
6985 ppd->neigh_link_down_reason.sma == 0) {
6986 ppd->local_link_down_reason.sma =
6987 ppd->local_link_down_reason.latest;
6988 ppd->neigh_link_down_reason.sma =
6989 ppd->neigh_link_down_reason.latest;
6990 }
6991
77241056
MM		 6992 reset_neighbor_info(ppd);
6993
6994 /* disable the port */
6995 clear_rcvctrl(ppd->dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
6996
4d114fdd
JJ		 6997 /*
6998 * If there is no cable attached, turn the DC off. Otherwise,
6999 * start the link bring up.
7000 */
623bba2d 7001 if (ppd->port_type == PORT_TYPE_QSFP && !qsfp_mod_present(ppd)) {
77241056 7002 dc_shutdown(ppd->dd);
8ebd4cf1
EH		 7003 } else {
7004 tune_serdes(ppd);
77241056 7005 start_link(ppd);
8ebd4cf1 7006 }
77241056
MM		 7007}
7008
7009void handle_link_bounce(struct work_struct *work)
7010{
7011 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7012 link_bounce_work);
7013
7014 /*
7015 * Only do something if the link is currently up.
7016 */
7017 if (ppd->host_link_state & HLS_UP) {
7018 set_link_state(ppd, HLS_DN_OFFLINE);
8ebd4cf1 7019 tune_serdes(ppd);
77241056
MM		 7020 start_link(ppd);
7021 } else {
7022 dd_dev_info(ppd->dd, "%s: link not up (%s), nothing to do\n",
17fb4f29 7023 __func__, link_state_name(ppd->host_link_state));
77241056
MM		 7024 }
7025}
7026
7027/*
7028 * Mask conversion: Capability exchange to Port LTP. The capability
7029 * exchange has an implicit 16b CRC that is mandatory.
7030 */
7031static int cap_to_port_ltp(int cap)
7032{
7033 int port_ltp = PORT_LTP_CRC_MODE_16; /* this mode is mandatory */
7034
7035 if (cap & CAP_CRC_14B)
7036 port_ltp |= PORT_LTP_CRC_MODE_14;
7037 if (cap & CAP_CRC_48B)
7038 port_ltp |= PORT_LTP_CRC_MODE_48;
7039 if (cap & CAP_CRC_12B_16B_PER_LANE)
7040 port_ltp |= PORT_LTP_CRC_MODE_PER_LANE;
7041
7042 return port_ltp;
7043}
7044
7045/*
7046 * Convert an OPA Port LTP mask to capability mask
7047 */
7048int port_ltp_to_cap(int port_ltp)
7049{
7050 int cap_mask = 0;
7051
7052 if (port_ltp & PORT_LTP_CRC_MODE_14)
7053 cap_mask |= CAP_CRC_14B;
7054 if (port_ltp & PORT_LTP_CRC_MODE_48)
7055 cap_mask |= CAP_CRC_48B;
7056 if (port_ltp & PORT_LTP_CRC_MODE_PER_LANE)
7057 cap_mask |= CAP_CRC_12B_16B_PER_LANE;
7058
7059 return cap_mask;
7060}
7061
7062/*
7063 * Convert a single DC LCB CRC mode to an OPA Port LTP mask.
7064 */
7065static int lcb_to_port_ltp(int lcb_crc)
7066{
7067 int port_ltp = 0;
7068
7069 if (lcb_crc == LCB_CRC_12B_16B_PER_LANE)
7070 port_ltp = PORT_LTP_CRC_MODE_PER_LANE;
7071 else if (lcb_crc == LCB_CRC_48B)
7072 port_ltp = PORT_LTP_CRC_MODE_48;
7073 else if (lcb_crc == LCB_CRC_14B)
7074 port_ltp = PORT_LTP_CRC_MODE_14;
7075 else
7076 port_ltp = PORT_LTP_CRC_MODE_16;
7077
7078 return port_ltp;
7079}
7080
7081/*
7082 * Our neighbor has indicated that we are allowed to act as a fabric
7083 * manager, so place the full management partition key in the second
7084 * (0-based) pkey array position (see OPAv1, section 20.2.2.6.8). Note
7085 * that we should already have the limited management partition key in
7086 * array element 1, and also that the port is not yet up when
7087 * add_full_mgmt_pkey() is invoked.
7088 */
7089static void add_full_mgmt_pkey(struct hfi1_pportdata *ppd)
7090{
7091 struct hfi1_devdata *dd = ppd->dd;
7092
8764522e
DL		 7093 /* Sanity check - ppd->pkeys[2] should be 0, or already initalized */
7094 if (!((ppd->pkeys[2] == 0) || (ppd->pkeys[2] == FULL_MGMT_P_KEY)))
7095 dd_dev_warn(dd, "%s pkey[2] already set to 0x%x, resetting it to 0x%x\n",
7096 __func__, ppd->pkeys[2], FULL_MGMT_P_KEY);
77241056
MM		 7097 ppd->pkeys[2] = FULL_MGMT_P_KEY;
7098 (void)hfi1_set_ib_cfg(ppd, HFI1_IB_CFG_PKEYS, 0);
34d351f8 7099 hfi1_event_pkey_change(ppd->dd, ppd->port);
77241056
MM		 7100}
7101
3ec5fa28 7102static void clear_full_mgmt_pkey(struct hfi1_pportdata *ppd)
ce8b2fd0 7103{
3ec5fa28
SS		 7104 if (ppd->pkeys[2] != 0) {
7105 ppd->pkeys[2] = 0;
7106 (void)hfi1_set_ib_cfg(ppd, HFI1_IB_CFG_PKEYS, 0);
34d351f8 7107 hfi1_event_pkey_change(ppd->dd, ppd->port);
3ec5fa28 7108 }
ce8b2fd0
SS		 7109}
7110
77241056
MM		 7111/*
7112 * Convert the given link width to the OPA link width bitmask.
7113 */
7114static u16 link_width_to_bits(struct hfi1_devdata *dd, u16 width)
7115{
7116 switch (width) {
7117 case 0:
7118 /*
7119 * Simulator and quick linkup do not set the width.
7120 * Just set it to 4x without complaint.
7121 */
7122 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR || quick_linkup)
7123 return OPA_LINK_WIDTH_4X;
7124 return 0; /* no lanes up */
7125 case 1: return OPA_LINK_WIDTH_1X;
7126 case 2: return OPA_LINK_WIDTH_2X;
7127 case 3: return OPA_LINK_WIDTH_3X;
7128 default:
7129 dd_dev_info(dd, "%s: invalid width %d, using 4\n",
17fb4f29 7130 __func__, width);
77241056
MM		 7131 /* fall through */
7132 case 4: return OPA_LINK_WIDTH_4X;
7133 }
7134}
7135
7136/*
7137 * Do a population count on the bottom nibble.
7138 */
7139static const u8 bit_counts[16] = {
7140 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4
7141};
f4d507cd 7142
77241056
MM		 7143static inline u8 nibble_to_count(u8 nibble)
7144{
7145 return bit_counts[nibble & 0xf];
7146}
7147
7148/*
7149 * Read the active lane information from the 8051 registers and return
7150 * their widths.
7151 *
7152 * Active lane information is found in these 8051 registers:
7153 * enable_lane_tx
7154 * enable_lane_rx
7155 */
7156static void get_link_widths(struct hfi1_devdata *dd, u16 *tx_width,
7157 u16 *rx_width)
7158{
7159 u16 tx, rx;
7160 u8 enable_lane_rx;
7161 u8 enable_lane_tx;
7162 u8 tx_polarity_inversion;
7163 u8 rx_polarity_inversion;
7164 u8 max_rate;
7165
7166 /* read the active lanes */
7167 read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion,
17fb4f29 7168 &rx_polarity_inversion, &max_rate);
77241056
MM		 7169 read_local_lni(dd, &enable_lane_rx);
7170
7171 /* convert to counts */
7172 tx = nibble_to_count(enable_lane_tx);
7173 rx = nibble_to_count(enable_lane_rx);
7174
7175 /*
7176 * Set link_speed_active here, overriding what was set in
7177 * handle_verify_cap(). The ASIC 8051 firmware does not correctly
7178 * set the max_rate field in handle_verify_cap until v0.19.
7179 */
d0d236ea
JJ		 7180 if ((dd->icode == ICODE_RTL_SILICON) &&
7181 (dd->dc8051_ver < dc8051_ver(0, 19))) {
77241056
MM		 7182 /* max_rate: 0 = 12.5G, 1 = 25G */
7183 switch (max_rate) {
7184 case 0:
7185 dd->pport[0].link_speed_active = OPA_LINK_SPEED_12_5G;
7186 break;
7187 default:
7188 dd_dev_err(dd,
17fb4f29
JJ		 7189 "%s: unexpected max rate %d, using 25Gb\n",
7190 __func__, (int)max_rate);
77241056
MM		 7191 /* fall through */
7192 case 1:
7193 dd->pport[0].link_speed_active = OPA_LINK_SPEED_25G;
7194 break;
7195 }
7196 }
7197
7198 dd_dev_info(dd,
17fb4f29
JJ		 7199 "Fabric active lanes (width): tx 0x%x (%d), rx 0x%x (%d)\n",
7200 enable_lane_tx, tx, enable_lane_rx, rx);
77241056
MM		 7201 *tx_width = link_width_to_bits(dd, tx);
7202 *rx_width = link_width_to_bits(dd, rx);
7203}
7204
7205/*
7206 * Read verify_cap_local_fm_link_width[1] to obtain the link widths.
7207 * Valid after the end of VerifyCap and during LinkUp. Does not change
7208 * after link up. I.e. look elsewhere for downgrade information.
7209 *
7210 * Bits are:
7211 * + bits [7:4] contain the number of active transmitters
7212 * + bits [3:0] contain the number of active receivers
7213 * These are numbers 1 through 4 and can be different values if the
7214 * link is asymmetric.
7215 *
7216 * verify_cap_local_fm_link_width[0] retains its original value.
7217 */
7218static void get_linkup_widths(struct hfi1_devdata *dd, u16 *tx_width,
7219 u16 *rx_width)
7220{
7221 u16 widths, tx, rx;
7222 u8 misc_bits, local_flags;
7223 u16 active_tx, active_rx;
7224
7225 read_vc_local_link_width(dd, &misc_bits, &local_flags, &widths);
7226 tx = widths >> 12;
7227 rx = (widths >> 8) & 0xf;
7228
7229 *tx_width = link_width_to_bits(dd, tx);
7230 *rx_width = link_width_to_bits(dd, rx);
7231
7232 /* print the active widths */
7233 get_link_widths(dd, &active_tx, &active_rx);
7234}
7235
7236/*
7237 * Set ppd->link_width_active and ppd->link_width_downgrade_active using
7238 * hardware information when the link first comes up.
7239 *
7240 * The link width is not available until after VerifyCap.AllFramesReceived
7241 * (the trigger for handle_verify_cap), so this is outside that routine
7242 * and should be called when the 8051 signals linkup.
7243 */
7244void get_linkup_link_widths(struct hfi1_pportdata *ppd)
7245{
7246 u16 tx_width, rx_width;
7247
7248 /* get end-of-LNI link widths */
7249 get_linkup_widths(ppd->dd, &tx_width, &rx_width);
7250
7251 /* use tx_width as the link is supposed to be symmetric on link up */
7252 ppd->link_width_active = tx_width;
7253 /* link width downgrade active (LWD.A) starts out matching LW.A */
7254 ppd->link_width_downgrade_tx_active = ppd->link_width_active;
7255 ppd->link_width_downgrade_rx_active = ppd->link_width_active;
7256 /* per OPA spec, on link up LWD.E resets to LWD.S */
7257 ppd->link_width_downgrade_enabled = ppd->link_width_downgrade_supported;
7258 /* cache the active egress rate (units {10^6 bits/sec]) */
7259 ppd->current_egress_rate = active_egress_rate(ppd);
7260}
7261
7262/*
7263 * Handle a verify capabilities interrupt from the 8051.
7264 *
7265 * This is a work-queue function outside of the interrupt.
7266 */
7267void handle_verify_cap(struct work_struct *work)
7268{
7269 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7270 link_vc_work);
7271 struct hfi1_devdata *dd = ppd->dd;
7272 u64 reg;
7273 u8 power_management;
7274 u8 continious;
7275 u8 vcu;
7276 u8 vau;
7277 u8 z;
7278 u16 vl15buf;
7279 u16 link_widths;
7280 u16 crc_mask;
7281 u16 crc_val;
7282 u16 device_id;
7283 u16 active_tx, active_rx;
7284 u8 partner_supported_crc;
7285 u8 remote_tx_rate;
7286 u8 device_rev;
7287
7288 set_link_state(ppd, HLS_VERIFY_CAP);
7289
7290 lcb_shutdown(dd, 0);
7291 adjust_lcb_for_fpga_serdes(dd);
7292
7293 /*
7294 * These are now valid:
7295 * remote VerifyCap fields in the general LNI config
7296 * CSR DC8051_STS_REMOTE_GUID
7297 * CSR DC8051_STS_REMOTE_NODE_TYPE
7298 * CSR DC8051_STS_REMOTE_FM_SECURITY
7299 * CSR DC8051_STS_REMOTE_PORT_NO
7300 */
7301
7302 read_vc_remote_phy(dd, &power_management, &continious);
17fb4f29
JJ		 7303 read_vc_remote_fabric(dd, &vau, &z, &vcu, &vl15buf,
7304 &partner_supported_crc);
77241056
MM		 7305 read_vc_remote_link_width(dd, &remote_tx_rate, &link_widths);
7306 read_remote_device_id(dd, &device_id, &device_rev);
7307 /*
7308 * And the 'MgmtAllowed' information, which is exchanged during
7309 * LNI, is also be available at this point.
7310 */
7311 read_mgmt_allowed(dd, &ppd->mgmt_allowed);
7312 /* print the active widths */
7313 get_link_widths(dd, &active_tx, &active_rx);
7314 dd_dev_info(dd,
17fb4f29
JJ		 7315 "Peer PHY: power management 0x%x, continuous updates 0x%x\n",
7316 (int)power_management, (int)continious);
77241056 7317 dd_dev_info(dd,
17fb4f29
JJ		 7318 "Peer Fabric: vAU %d, Z %d, vCU %d, vl15 credits 0x%x, CRC sizes 0x%x\n",
7319 (int)vau, (int)z, (int)vcu, (int)vl15buf,
7320 (int)partner_supported_crc);
77241056 7321 dd_dev_info(dd, "Peer Link Width: tx rate 0x%x, widths 0x%x\n",
17fb4f29 7322 (u32)remote_tx_rate, (u32)link_widths);
77241056 7323 dd_dev_info(dd, "Peer Device ID: 0x%04x, Revision 0x%02x\n",
17fb4f29 7324 (u32)device_id, (u32)device_rev);
77241056
MM		 7325 /*
7326 * The peer vAU value just read is the peer receiver value. HFI does
7327 * not support a transmit vAU of 0 (AU == 8). We advertised that
7328 * with Z=1 in the fabric capabilities sent to the peer. The peer
7329 * will see our Z=1, and, if it advertised a vAU of 0, will move its
7330 * receive to vAU of 1 (AU == 16). Do the same here. We do not care
7331 * about the peer Z value - our sent vAU is 3 (hardwired) and is not
7332 * subject to the Z value exception.
7333 */
7334 if (vau == 0)
7335 vau = 1;
7336 set_up_vl15(dd, vau, vl15buf);
7337
7338 /* set up the LCB CRC mode */
7339 crc_mask = ppd->port_crc_mode_enabled & partner_supported_crc;
7340
7341 /* order is important: use the lowest bit in common */
7342 if (crc_mask & CAP_CRC_14B)
7343 crc_val = LCB_CRC_14B;
7344 else if (crc_mask & CAP_CRC_48B)
7345 crc_val = LCB_CRC_48B;
7346 else if (crc_mask & CAP_CRC_12B_16B_PER_LANE)
7347 crc_val = LCB_CRC_12B_16B_PER_LANE;
7348 else
7349 crc_val = LCB_CRC_16B;
7350
7351 dd_dev_info(dd, "Final LCB CRC mode: %d\n", (int)crc_val);
7352 write_csr(dd, DC_LCB_CFG_CRC_MODE,
7353 (u64)crc_val << DC_LCB_CFG_CRC_MODE_TX_VAL_SHIFT);
7354
7355 /* set (14b only) or clear sideband credit */
7356 reg = read_csr(dd, SEND_CM_CTRL);
7357 if (crc_val == LCB_CRC_14B && crc_14b_sideband) {
7358 write_csr(dd, SEND_CM_CTRL,
17fb4f29 7359 reg | SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK);
77241056
MM		 7360 } else {
7361 write_csr(dd, SEND_CM_CTRL,
17fb4f29 7362 reg & ~SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK);
77241056
MM		 7363 }
7364
7365 ppd->link_speed_active = 0; /* invalid value */
7366 if (dd->dc8051_ver < dc8051_ver(0, 20)) {
7367 /* remote_tx_rate: 0 = 12.5G, 1 = 25G */
7368 switch (remote_tx_rate) {
7369 case 0:
7370 ppd->link_speed_active = OPA_LINK_SPEED_12_5G;
7371 break;
7372 case 1:
7373 ppd->link_speed_active = OPA_LINK_SPEED_25G;
7374 break;
7375 }
7376 } else {
7377 /* actual rate is highest bit of the ANDed rates */
7378 u8 rate = remote_tx_rate & ppd->local_tx_rate;
7379
7380 if (rate & 2)
7381 ppd->link_speed_active = OPA_LINK_SPEED_25G;
7382 else if (rate & 1)
7383 ppd->link_speed_active = OPA_LINK_SPEED_12_5G;
7384 }
7385 if (ppd->link_speed_active == 0) {
7386 dd_dev_err(dd, "%s: unexpected remote tx rate %d, using 25Gb\n",
17fb4f29 7387 __func__, (int)remote_tx_rate);
77241056
MM		 7388 ppd->link_speed_active = OPA_LINK_SPEED_25G;
7389 }
7390
7391 /*
7392 * Cache the values of the supported, enabled, and active
7393 * LTP CRC modes to return in 'portinfo' queries. But the bit
7394 * flags that are returned in the portinfo query differ from
7395 * what's in the link_crc_mask, crc_sizes, and crc_val
7396 * variables. Convert these here.
7397 */
7398 ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8;
7399 /* supported crc modes */
7400 ppd->port_ltp_crc_mode |=
7401 cap_to_port_ltp(ppd->port_crc_mode_enabled) << 4;
7402 /* enabled crc modes */
7403 ppd->port_ltp_crc_mode |= lcb_to_port_ltp(crc_val);
7404 /* active crc mode */
7405
7406 /* set up the remote credit return table */
7407 assign_remote_cm_au_table(dd, vcu);
7408
7409 /*
7410 * The LCB is reset on entry to handle_verify_cap(), so this must
7411 * be applied on every link up.
7412 *
7413 * Adjust LCB error kill enable to kill the link if
7414 * these RBUF errors are seen:
7415 * REPLAY_BUF_MBE_SMASK
7416 * FLIT_INPUT_BUF_MBE_SMASK
7417 */
995deafa 7418 if (is_ax(dd)) { /* fixed in B0 */
77241056
MM		 7419 reg = read_csr(dd, DC_LCB_CFG_LINK_KILL_EN);
7420 reg |= DC_LCB_CFG_LINK_KILL_EN_REPLAY_BUF_MBE_SMASK
7421 | DC_LCB_CFG_LINK_KILL_EN_FLIT_INPUT_BUF_MBE_SMASK;
7422 write_csr(dd, DC_LCB_CFG_LINK_KILL_EN, reg);
7423 }
7424
7425 /* pull LCB fifos out of reset - all fifo clocks must be stable */
7426 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
7427
7428 /* give 8051 access to the LCB CSRs */
7429 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
7430 set_8051_lcb_access(dd);
7431
7432 ppd->neighbor_guid =
7433 read_csr(dd, DC_DC8051_STS_REMOTE_GUID);
7434 ppd->neighbor_port_number = read_csr(dd, DC_DC8051_STS_REMOTE_PORT_NO) &
7435 DC_DC8051_STS_REMOTE_PORT_NO_VAL_SMASK;
7436 ppd->neighbor_type =
7437 read_csr(dd, DC_DC8051_STS_REMOTE_NODE_TYPE) &
7438 DC_DC8051_STS_REMOTE_NODE_TYPE_VAL_MASK;
7439 ppd->neighbor_fm_security =
7440 read_csr(dd, DC_DC8051_STS_REMOTE_FM_SECURITY) &
7441 DC_DC8051_STS_LOCAL_FM_SECURITY_DISABLED_MASK;
7442 dd_dev_info(dd,
17fb4f29
JJ		 7443 "Neighbor Guid: %llx Neighbor type %d MgmtAllowed %d FM security bypass %d\n",
7444 ppd->neighbor_guid, ppd->neighbor_type,
7445 ppd->mgmt_allowed, ppd->neighbor_fm_security);
77241056
MM		 7446 if (ppd->mgmt_allowed)
7447 add_full_mgmt_pkey(ppd);
7448
7449 /* tell the 8051 to go to LinkUp */
7450 set_link_state(ppd, HLS_GOING_UP);
7451}
7452
7453/*
7454 * Apply the link width downgrade enabled policy against the current active
7455 * link widths.
7456 *
7457 * Called when the enabled policy changes or the active link widths change.
7458 */
7459void apply_link_downgrade_policy(struct hfi1_pportdata *ppd, int refresh_widths)
7460{
77241056 7461 int do_bounce = 0;
323fd785
DL		 7462 int tries;
7463 u16 lwde;
77241056
MM		 7464 u16 tx, rx;
7465
323fd785
DL		 7466 /* use the hls lock to avoid a race with actual link up */
7467 tries = 0;
7468retry:
77241056
MM		 7469 mutex_lock(&ppd->hls_lock);
7470 /* only apply if the link is up */
0c7f77af 7471 if (ppd->host_link_state & HLS_DOWN) {
323fd785
DL		 7472 /* still going up..wait and retry */
7473 if (ppd->host_link_state & HLS_GOING_UP) {
7474 if (++tries < 1000) {
7475 mutex_unlock(&ppd->hls_lock);
7476 usleep_range(100, 120); /* arbitrary */
7477 goto retry;
7478 }
7479 dd_dev_err(ppd->dd,
7480 "%s: giving up waiting for link state change\n",
7481 __func__);
7482 }
7483 goto done;
7484 }
7485
7486 lwde = ppd->link_width_downgrade_enabled;
77241056
MM		 7487
7488 if (refresh_widths) {
7489 get_link_widths(ppd->dd, &tx, &rx);
7490 ppd->link_width_downgrade_tx_active = tx;
7491 ppd->link_width_downgrade_rx_active = rx;
7492 }
7493
f9b5635c
DL		 7494 if (ppd->link_width_downgrade_tx_active == 0 ||
7495 ppd->link_width_downgrade_rx_active == 0) {
7496 /* the 8051 reported a dead link as a downgrade */
7497 dd_dev_err(ppd->dd, "Link downgrade is really a link down, ignoring\n");
7498 } else if (lwde == 0) {
77241056
MM		 7499 /* downgrade is disabled */
7500
7501 /* bounce if not at starting active width */
7502 if ((ppd->link_width_active !=
17fb4f29
JJ		 7503 ppd->link_width_downgrade_tx_active) ||
7504 (ppd->link_width_active !=
7505 ppd->link_width_downgrade_rx_active)) {
77241056 7506 dd_dev_err(ppd->dd,
17fb4f29 7507 "Link downgrade is disabled and link has downgraded, downing link\n");
77241056 7508 dd_dev_err(ppd->dd,
17fb4f29
JJ		 7509 " original 0x%x, tx active 0x%x, rx active 0x%x\n",
7510 ppd->link_width_active,
7511 ppd->link_width_downgrade_tx_active,
7512 ppd->link_width_downgrade_rx_active);
77241056
MM		 7513 do_bounce = 1;
7514 }
d0d236ea
JJ		 7515 } else if ((lwde & ppd->link_width_downgrade_tx_active) == 0 ||
7516 (lwde & ppd->link_width_downgrade_rx_active) == 0) {
77241056
MM		 7517 /* Tx or Rx is outside the enabled policy */
7518 dd_dev_err(ppd->dd,
17fb4f29 7519 "Link is outside of downgrade allowed, downing link\n");
77241056 7520 dd_dev_err(ppd->dd,
17fb4f29
JJ		 7521 " enabled 0x%x, tx active 0x%x, rx active 0x%x\n",
7522 lwde, ppd->link_width_downgrade_tx_active,
7523 ppd->link_width_downgrade_rx_active);
77241056
MM		 7524 do_bounce = 1;
7525 }
7526
323fd785
DL		 7527done:
7528 mutex_unlock(&ppd->hls_lock);
7529
77241056
MM		 7530 if (do_bounce) {
7531 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_WIDTH_POLICY, 0,
17fb4f29 7532 OPA_LINKDOWN_REASON_WIDTH_POLICY);
77241056 7533 set_link_state(ppd, HLS_DN_OFFLINE);
8ebd4cf1 7534 tune_serdes(ppd);
77241056
MM		 7535 start_link(ppd);
7536 }
7537}
7538
7539/*
7540 * Handle a link downgrade interrupt from the 8051.
7541 *
7542 * This is a work-queue function outside of the interrupt.
7543 */
7544void handle_link_downgrade(struct work_struct *work)
7545{
7546 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7547 link_downgrade_work);
7548
7549 dd_dev_info(ppd->dd, "8051: Link width downgrade\n");
7550 apply_link_downgrade_policy(ppd, 1);
7551}
7552
7553static char *dcc_err_string(char *buf, int buf_len, u64 flags)
7554{
7555 return flag_string(buf, buf_len, flags, dcc_err_flags,
7556 ARRAY_SIZE(dcc_err_flags));
7557}
7558
7559static char *lcb_err_string(char *buf, int buf_len, u64 flags)
7560{
7561 return flag_string(buf, buf_len, flags, lcb_err_flags,
7562 ARRAY_SIZE(lcb_err_flags));
7563}
7564
7565static char *dc8051_err_string(char *buf, int buf_len, u64 flags)
7566{
7567 return flag_string(buf, buf_len, flags, dc8051_err_flags,
7568 ARRAY_SIZE(dc8051_err_flags));
7569}
7570
7571static char *dc8051_info_err_string(char *buf, int buf_len, u64 flags)
7572{
7573 return flag_string(buf, buf_len, flags, dc8051_info_err_flags,
7574 ARRAY_SIZE(dc8051_info_err_flags));
7575}
7576
7577static char *dc8051_info_host_msg_string(char *buf, int buf_len, u64 flags)
7578{
7579 return flag_string(buf, buf_len, flags, dc8051_info_host_msg_flags,
7580 ARRAY_SIZE(dc8051_info_host_msg_flags));
7581}
7582
7583static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg)
7584{
7585 struct hfi1_pportdata *ppd = dd->pport;
7586 u64 info, err, host_msg;
7587 int queue_link_down = 0;
7588 char buf[96];
7589
7590 /* look at the flags */
7591 if (reg & DC_DC8051_ERR_FLG_SET_BY_8051_SMASK) {
7592 /* 8051 information set by firmware */
7593 /* read DC8051_DBG_ERR_INFO_SET_BY_8051 for details */
7594 info = read_csr(dd, DC_DC8051_DBG_ERR_INFO_SET_BY_8051);
7595 err = (info >> DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_SHIFT)
7596 & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_MASK;
7597 host_msg = (info >>
7598 DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_SHIFT)
7599 & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_MASK;
7600
7601 /*
7602 * Handle error flags.
7603 */
7604 if (err & FAILED_LNI) {
7605 /*
7606 * LNI error indications are cleared by the 8051
7607 * only when starting polling. Only pay attention
7608 * to them when in the states that occur during
7609 * LNI.
7610 */
7611 if (ppd->host_link_state
7612 & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) {
7613 queue_link_down = 1;
7614 dd_dev_info(dd, "Link error: %s\n",
17fb4f29
JJ		 7615 dc8051_info_err_string(buf,
7616 sizeof(buf),
7617 err &
7618 FAILED_LNI));
77241056
MM		 7619 }
7620 err &= ~(u64)FAILED_LNI;
7621 }
6d014530
DL		 7622 /* unknown frames can happen durning LNI, just count */
7623 if (err & UNKNOWN_FRAME) {
7624 ppd->unknown_frame_count++;
7625 err &= ~(u64)UNKNOWN_FRAME;
7626 }
77241056
MM		 7627 if (err) {
7628 /* report remaining errors, but do not do anything */
7629 dd_dev_err(dd, "8051 info error: %s\n",
17fb4f29
JJ		 7630 dc8051_info_err_string(buf, sizeof(buf),
7631 err));
77241056
MM		 7632 }
7633
7634 /*
7635 * Handle host message flags.
7636 */
7637 if (host_msg & HOST_REQ_DONE) {
7638 /*
7639 * Presently, the driver does a busy wait for
7640 * host requests to complete. This is only an
7641 * informational message.
7642 * NOTE: The 8051 clears the host message
7643 * information *on the next 8051 command*.
7644 * Therefore, when linkup is achieved,
7645 * this flag will still be set.
7646 */
7647 host_msg &= ~(u64)HOST_REQ_DONE;
7648 }
7649 if (host_msg & BC_SMA_MSG) {
7650 queue_work(ppd->hfi1_wq, &ppd->sma_message_work);
7651 host_msg &= ~(u64)BC_SMA_MSG;
7652 }
7653 if (host_msg & LINKUP_ACHIEVED) {
7654 dd_dev_info(dd, "8051: Link up\n");
7655 queue_work(ppd->hfi1_wq, &ppd->link_up_work);
7656 host_msg &= ~(u64)LINKUP_ACHIEVED;
7657 }
7658 if (host_msg & EXT_DEVICE_CFG_REQ) {
145dd2b3 7659 handle_8051_request(ppd);
77241056
MM		 7660 host_msg &= ~(u64)EXT_DEVICE_CFG_REQ;
7661 }
7662 if (host_msg & VERIFY_CAP_FRAME) {
7663 queue_work(ppd->hfi1_wq, &ppd->link_vc_work);
7664 host_msg &= ~(u64)VERIFY_CAP_FRAME;
7665 }
7666 if (host_msg & LINK_GOING_DOWN) {
7667 const char *extra = "";
7668 /* no downgrade action needed if going down */
7669 if (host_msg & LINK_WIDTH_DOWNGRADED) {
7670 host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED;
7671 extra = " (ignoring downgrade)";
7672 }
7673 dd_dev_info(dd, "8051: Link down%s\n", extra);
7674 queue_link_down = 1;
7675 host_msg &= ~(u64)LINK_GOING_DOWN;
7676 }
7677 if (host_msg & LINK_WIDTH_DOWNGRADED) {
7678 queue_work(ppd->hfi1_wq, &ppd->link_downgrade_work);
7679 host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED;
7680 }
7681 if (host_msg) {
7682 /* report remaining messages, but do not do anything */
7683 dd_dev_info(dd, "8051 info host message: %s\n",
17fb4f29
JJ		 7684 dc8051_info_host_msg_string(buf,
7685 sizeof(buf),
7686 host_msg));
77241056
MM		 7687 }
7688
7689 reg &= ~DC_DC8051_ERR_FLG_SET_BY_8051_SMASK;
7690 }
7691 if (reg & DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK) {
7692 /*
7693 * Lost the 8051 heartbeat. If this happens, we
7694 * receive constant interrupts about it. Disable
7695 * the interrupt after the first.
7696 */
7697 dd_dev_err(dd, "Lost 8051 heartbeat\n");
7698 write_csr(dd, DC_DC8051_ERR_EN,
17fb4f29
JJ		 7699 read_csr(dd, DC_DC8051_ERR_EN) &
7700 ~DC_DC8051_ERR_EN_LOST_8051_HEART_BEAT_SMASK);
77241056
MM		 7701
7702 reg &= ~DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK;
7703 }
7704 if (reg) {
7705 /* report the error, but do not do anything */
7706 dd_dev_err(dd, "8051 error: %s\n",
17fb4f29 7707 dc8051_err_string(buf, sizeof(buf), reg));
77241056
MM		 7708 }
7709
7710 if (queue_link_down) {
4d114fdd
JJ		 7711 /*
7712 * if the link is already going down or disabled, do not
7713 * queue another
7714 */
d0d236ea
JJ		 7715 if ((ppd->host_link_state &
7716 (HLS_GOING_OFFLINE | HLS_LINK_COOLDOWN)) ||
7717 ppd->link_enabled == 0) {
77241056 7718 dd_dev_info(dd, "%s: not queuing link down\n",
17fb4f29 7719 __func__);
77241056
MM		 7720 } else {
7721 queue_work(ppd->hfi1_wq, &ppd->link_down_work);
7722 }
7723 }
7724}
7725
7726static const char * const fm_config_txt[] = {
7727[0] =
7728 "BadHeadDist: Distance violation between two head flits",
7729[1] =
7730 "BadTailDist: Distance violation between two tail flits",
7731[2] =
7732 "BadCtrlDist: Distance violation between two credit control flits",
7733[3] =
7734 "BadCrdAck: Credits return for unsupported VL",
7735[4] =
7736 "UnsupportedVLMarker: Received VL Marker",
7737[5] =
7738 "BadPreempt: Exceeded the preemption nesting level",
7739[6] =
7740 "BadControlFlit: Received unsupported control flit",
7741/* no 7 */
7742[8] =
7743 "UnsupportedVLMarker: Received VL Marker for unconfigured or disabled VL",
7744};
7745
7746static const char * const port_rcv_txt[] = {
7747[1] =
7748 "BadPktLen: Illegal PktLen",
7749[2] =
7750 "PktLenTooLong: Packet longer than PktLen",
7751[3] =
7752 "PktLenTooShort: Packet shorter than PktLen",
7753[4] =
7754 "BadSLID: Illegal SLID (0, using multicast as SLID, does not include security validation of SLID)",
7755[5] =
7756 "BadDLID: Illegal DLID (0, doesn't match HFI)",
7757[6] =
7758 "BadL2: Illegal L2 opcode",
7759[7] =
7760 "BadSC: Unsupported SC",
7761[9] =
7762 "BadRC: Illegal RC",
7763[11] =
7764 "PreemptError: Preempting with same VL",
7765[12] =
7766 "PreemptVL15: Preempting a VL15 packet",
7767};
7768
7769#define OPA_LDR_FMCONFIG_OFFSET 16
7770#define OPA_LDR_PORTRCV_OFFSET 0
7771static void handle_dcc_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
7772{
7773 u64 info, hdr0, hdr1;
7774 const char *extra;
7775 char buf[96];
7776 struct hfi1_pportdata *ppd = dd->pport;
7777 u8 lcl_reason = 0;
7778 int do_bounce = 0;
7779
7780 if (reg & DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK) {
7781 if (!(dd->err_info_uncorrectable & OPA_EI_STATUS_SMASK)) {
7782 info = read_csr(dd, DCC_ERR_INFO_UNCORRECTABLE);
7783 dd->err_info_uncorrectable = info & OPA_EI_CODE_SMASK;
7784 /* set status bit */
7785 dd->err_info_uncorrectable |= OPA_EI_STATUS_SMASK;
7786 }
7787 reg &= ~DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK;
7788 }
7789
7790 if (reg & DCC_ERR_FLG_LINK_ERR_SMASK) {
7791 struct hfi1_pportdata *ppd = dd->pport;
7792 /* this counter saturates at (2^32) - 1 */
7793 if (ppd->link_downed < (u32)UINT_MAX)
7794 ppd->link_downed++;
7795 reg &= ~DCC_ERR_FLG_LINK_ERR_SMASK;
7796 }
7797
7798 if (reg & DCC_ERR_FLG_FMCONFIG_ERR_SMASK) {
7799 u8 reason_valid = 1;
7800
7801 info = read_csr(dd, DCC_ERR_INFO_FMCONFIG);
7802 if (!(dd->err_info_fmconfig & OPA_EI_STATUS_SMASK)) {
7803 dd->err_info_fmconfig = info & OPA_EI_CODE_SMASK;
7804 /* set status bit */
7805 dd->err_info_fmconfig |= OPA_EI_STATUS_SMASK;
7806 }
7807 switch (info) {
7808 case 0:
7809 case 1:
7810 case 2:
7811 case 3:
7812 case 4:
7813 case 5:
7814 case 6:
7815 extra = fm_config_txt[info];
7816 break;
7817 case 8:
7818 extra = fm_config_txt[info];
7819 if (ppd->port_error_action &
7820 OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER) {
7821 do_bounce = 1;
7822 /*
7823 * lcl_reason cannot be derived from info
7824 * for this error
7825 */
7826 lcl_reason =
7827 OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER;
7828 }
7829 break;
7830 default:
7831 reason_valid = 0;
7832 snprintf(buf, sizeof(buf), "reserved%lld", info);
7833 extra = buf;
7834 break;
7835 }
7836
7837 if (reason_valid && !do_bounce) {
7838 do_bounce = ppd->port_error_action &
7839 (1 << (OPA_LDR_FMCONFIG_OFFSET + info));
7840 lcl_reason = info + OPA_LINKDOWN_REASON_BAD_HEAD_DIST;
7841 }
7842
7843 /* just report this */
7844 dd_dev_info(dd, "DCC Error: fmconfig error: %s\n", extra);
7845 reg &= ~DCC_ERR_FLG_FMCONFIG_ERR_SMASK;
7846 }
7847
7848 if (reg & DCC_ERR_FLG_RCVPORT_ERR_SMASK) {
7849 u8 reason_valid = 1;
7850
7851 info = read_csr(dd, DCC_ERR_INFO_PORTRCV);
7852 hdr0 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR0);
7853 hdr1 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR1);
7854 if (!(dd->err_info_rcvport.status_and_code &
7855 OPA_EI_STATUS_SMASK)) {
7856 dd->err_info_rcvport.status_and_code =
7857 info & OPA_EI_CODE_SMASK;
7858 /* set status bit */
7859 dd->err_info_rcvport.status_and_code |=
7860 OPA_EI_STATUS_SMASK;
4d114fdd
JJ		 7861 /*
7862 * save first 2 flits in the packet that caused
7863 * the error
7864 */
48a0cc13
BVA		 7865 dd->err_info_rcvport.packet_flit1 = hdr0;
7866 dd->err_info_rcvport.packet_flit2 = hdr1;
77241056
MM		 7867 }
7868 switch (info) {
7869 case 1:
7870 case 2:
7871 case 3:
7872 case 4:
7873 case 5:
7874 case 6:
7875 case 7:
7876 case 9:
7877 case 11:
7878 case 12:
7879 extra = port_rcv_txt[info];
7880 break;
7881 default:
7882 reason_valid = 0;
7883 snprintf(buf, sizeof(buf), "reserved%lld", info);
7884 extra = buf;
7885 break;
7886 }
7887
7888 if (reason_valid && !do_bounce) {
7889 do_bounce = ppd->port_error_action &
7890 (1 << (OPA_LDR_PORTRCV_OFFSET + info));
7891 lcl_reason = info + OPA_LINKDOWN_REASON_RCV_ERROR_0;
7892 }
7893
7894 /* just report this */
7895 dd_dev_info(dd, "DCC Error: PortRcv error: %s\n", extra);
7896 dd_dev_info(dd, " hdr0 0x%llx, hdr1 0x%llx\n",
17fb4f29 7897 hdr0, hdr1);
77241056
MM		 7898
7899 reg &= ~DCC_ERR_FLG_RCVPORT_ERR_SMASK;
7900 }
7901
7902 if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK) {
7903 /* informative only */
7904 dd_dev_info(dd, "8051 access to LCB blocked\n");
7905 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK;
7906 }
7907 if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK) {
7908 /* informative only */
7909 dd_dev_info(dd, "host access to LCB blocked\n");
7910 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK;
7911 }
7912
7913 /* report any remaining errors */
7914 if (reg)
7915 dd_dev_info(dd, "DCC Error: %s\n",
17fb4f29 7916 dcc_err_string(buf, sizeof(buf), reg));
77241056
MM		 7917
7918 if (lcl_reason == 0)
7919 lcl_reason = OPA_LINKDOWN_REASON_UNKNOWN;
7920
7921 if (do_bounce) {
7922 dd_dev_info(dd, "%s: PortErrorAction bounce\n", __func__);
7923 set_link_down_reason(ppd, lcl_reason, 0, lcl_reason);
7924 queue_work(ppd->hfi1_wq, &ppd->link_bounce_work);
7925 }
7926}
7927
7928static void handle_lcb_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
7929{
7930 char buf[96];
7931
7932 dd_dev_info(dd, "LCB Error: %s\n",
17fb4f29 7933 lcb_err_string(buf, sizeof(buf), reg));
77241056
MM		 7934}
7935
7936/*
7937 * CCE block DC interrupt. Source is < 8.
7938 */
7939static void is_dc_int(struct hfi1_devdata *dd, unsigned int source)
7940{
7941 const struct err_reg_info *eri = &dc_errs[source];
7942
7943 if (eri->handler) {
7944 interrupt_clear_down(dd, 0, eri);
7945 } else if (source == 3 /* dc_lbm_int */) {
7946 /*
7947 * This indicates that a parity error has occurred on the
7948 * address/control lines presented to the LBM. The error
7949 * is a single pulse, there is no associated error flag,
7950 * and it is non-maskable. This is because if a parity
7951 * error occurs on the request the request is dropped.
7952 * This should never occur, but it is nice to know if it
7953 * ever does.
7954 */
7955 dd_dev_err(dd, "Parity error in DC LBM block\n");
7956 } else {
7957 dd_dev_err(dd, "Invalid DC interrupt %u\n", source);
7958 }
7959}
7960
7961/*
7962 * TX block send credit interrupt. Source is < 160.
7963 */
7964static void is_send_credit_int(struct hfi1_devdata *dd, unsigned int source)
7965{
7966 sc_group_release_update(dd, source);
7967}
7968
7969/*
7970 * TX block SDMA interrupt. Source is < 48.
7971 *
7972 * SDMA interrupts are grouped by type:
7973 *
7974 * 0 - N-1 = SDma
7975 * N - 2N-1 = SDmaProgress
7976 * 2N - 3N-1 = SDmaIdle
7977 */
7978static void is_sdma_eng_int(struct hfi1_devdata *dd, unsigned int source)
7979{
7980 /* what interrupt */
7981 unsigned int what = source / TXE_NUM_SDMA_ENGINES;
7982 /* which engine */
7983 unsigned int which = source % TXE_NUM_SDMA_ENGINES;
7984
7985#ifdef CONFIG_SDMA_VERBOSITY
7986 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", which,
7987 slashstrip(__FILE__), __LINE__, __func__);
7988 sdma_dumpstate(&dd->per_sdma[which]);
7989#endif
7990
7991 if (likely(what < 3 && which < dd->num_sdma)) {
7992 sdma_engine_interrupt(&dd->per_sdma[which], 1ull << source);
7993 } else {
7994 /* should not happen */
7995 dd_dev_err(dd, "Invalid SDMA interrupt 0x%x\n", source);
7996 }
7997}
7998
7999/*
8000 * RX block receive available interrupt. Source is < 160.
8001 */
8002static void is_rcv_avail_int(struct hfi1_devdata *dd, unsigned int source)
8003{
8004 struct hfi1_ctxtdata *rcd;
8005 char *err_detail;
8006
8007 if (likely(source < dd->num_rcv_contexts)) {
8008 rcd = dd->rcd[source];
8009 if (rcd) {
8010 if (source < dd->first_user_ctxt)
f4f30031 8011 rcd->do_interrupt(rcd, 0);
77241056
MM		 8012 else
8013 handle_user_interrupt(rcd);
8014 return; /* OK */
8015 }
8016 /* received an interrupt, but no rcd */
8017 err_detail = "dataless";
8018 } else {
8019 /* received an interrupt, but are not using that context */
8020 err_detail = "out of range";
8021 }
8022 dd_dev_err(dd, "unexpected %s receive available context interrupt %u\n",
17fb4f29 8023 err_detail, source);
77241056
MM		 8024}
8025
8026/*
8027 * RX block receive urgent interrupt. Source is < 160.
8028 */
8029static void is_rcv_urgent_int(struct hfi1_devdata *dd, unsigned int source)
8030{
8031 struct hfi1_ctxtdata *rcd;
8032 char *err_detail;
8033
8034 if (likely(source < dd->num_rcv_contexts)) {
8035 rcd = dd->rcd[source];
8036 if (rcd) {
8037 /* only pay attention to user urgent interrupts */
8038 if (source >= dd->first_user_ctxt)
8039 handle_user_interrupt(rcd);
8040 return; /* OK */
8041 }
8042 /* received an interrupt, but no rcd */
8043 err_detail = "dataless";
8044 } else {
8045 /* received an interrupt, but are not using that context */
8046 err_detail = "out of range";
8047 }
8048 dd_dev_err(dd, "unexpected %s receive urgent context interrupt %u\n",
17fb4f29 8049 err_detail, source);
77241056
MM		 8050}
8051
8052/*
8053 * Reserved range interrupt. Should not be called in normal operation.
8054 */
8055static void is_reserved_int(struct hfi1_devdata *dd, unsigned int source)
8056{
8057 char name[64];
8058
8059 dd_dev_err(dd, "unexpected %s interrupt\n",
17fb4f29 8060 is_reserved_name(name, sizeof(name), source));
77241056
MM		 8061}
8062
8063static const struct is_table is_table[] = {
4d114fdd
JJ		 8064/*
8065 * start end
8066 * name func interrupt func
8067 */
77241056
MM		 8068{ IS_GENERAL_ERR_START, IS_GENERAL_ERR_END,
8069 is_misc_err_name, is_misc_err_int },
8070{ IS_SDMAENG_ERR_START, IS_SDMAENG_ERR_END,
8071 is_sdma_eng_err_name, is_sdma_eng_err_int },
8072{ IS_SENDCTXT_ERR_START, IS_SENDCTXT_ERR_END,
8073 is_sendctxt_err_name, is_sendctxt_err_int },
8074{ IS_SDMA_START, IS_SDMA_END,
8075 is_sdma_eng_name, is_sdma_eng_int },
8076{ IS_VARIOUS_START, IS_VARIOUS_END,
8077 is_various_name, is_various_int },
8078{ IS_DC_START, IS_DC_END,
8079 is_dc_name, is_dc_int },
8080{ IS_RCVAVAIL_START, IS_RCVAVAIL_END,
8081 is_rcv_avail_name, is_rcv_avail_int },
8082{ IS_RCVURGENT_START, IS_RCVURGENT_END,
8083 is_rcv_urgent_name, is_rcv_urgent_int },
8084{ IS_SENDCREDIT_START, IS_SENDCREDIT_END,
8085 is_send_credit_name, is_send_credit_int},
8086{ IS_RESERVED_START, IS_RESERVED_END,
8087 is_reserved_name, is_reserved_int},
8088};
8089
8090/*
8091 * Interrupt source interrupt - called when the given source has an interrupt.
8092 * Source is a bit index into an array of 64-bit integers.
8093 */
8094static void is_interrupt(struct hfi1_devdata *dd, unsigned int source)
8095{
8096 const struct is_table *entry;
8097
8098 /* avoids a double compare by walking the table in-order */
8099 for (entry = &is_table[0]; entry->is_name; entry++) {
8100 if (source < entry->end) {
8101 trace_hfi1_interrupt(dd, entry, source);
8102 entry->is_int(dd, source - entry->start);
8103 return;
8104 }
8105 }
8106 /* fell off the end */
8107 dd_dev_err(dd, "invalid interrupt source %u\n", source);
8108}
8109
8110/*
8111 * General interrupt handler. This is able to correctly handle
8112 * all interrupts in case INTx is used.
8113 */
8114static irqreturn_t general_interrupt(int irq, void *data)
8115{
8116 struct hfi1_devdata *dd = data;
8117 u64 regs[CCE_NUM_INT_CSRS];
8118 u32 bit;
8119 int i;
8120
8121 this_cpu_inc(*dd->int_counter);
8122
8123 /* phase 1: scan and clear all handled interrupts */
8124 for (i = 0; i < CCE_NUM_INT_CSRS; i++) {
8125 if (dd->gi_mask[i] == 0) {
8126 regs[i] = 0; /* used later */
8127 continue;
8128 }
8129 regs[i] = read_csr(dd, CCE_INT_STATUS + (8 * i)) &
8130 dd->gi_mask[i];
8131 /* only clear if anything is set */
8132 if (regs[i])
8133 write_csr(dd, CCE_INT_CLEAR + (8 * i), regs[i]);
8134 }
8135
8136 /* phase 2: call the appropriate handler */
8137 for_each_set_bit(bit, (unsigned long *)&regs[0],
17fb4f29 8138 CCE_NUM_INT_CSRS * 64) {
77241056
MM		 8139 is_interrupt(dd, bit);
8140 }
8141
8142 return IRQ_HANDLED;
8143}
8144
8145static irqreturn_t sdma_interrupt(int irq, void *data)
8146{
8147 struct sdma_engine *sde = data;
8148 struct hfi1_devdata *dd = sde->dd;
8149 u64 status;
8150
8151#ifdef CONFIG_SDMA_VERBOSITY
8152 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
8153 slashstrip(__FILE__), __LINE__, __func__);
8154 sdma_dumpstate(sde);
8155#endif
8156
8157 this_cpu_inc(*dd->int_counter);
8158
8159 /* This read_csr is really bad in the hot path */
8160 status = read_csr(dd,
17fb4f29
JJ		 8161 CCE_INT_STATUS + (8 * (IS_SDMA_START / 64)))
8162 & sde->imask;
77241056
MM		 8163 if (likely(status)) {
8164 /* clear the interrupt(s) */
8165 write_csr(dd,
17fb4f29
JJ		 8166 CCE_INT_CLEAR + (8 * (IS_SDMA_START / 64)),
8167 status);
77241056
MM		 8168
8169 /* handle the interrupt(s) */
8170 sdma_engine_interrupt(sde, status);
8171 } else
8172 dd_dev_err(dd, "SDMA engine %u interrupt, but no status bits set\n",
17fb4f29 8173 sde->this_idx);
77241056
MM		 8174
8175 return IRQ_HANDLED;
8176}
8177
8178/*
ecd42f8d
DL		 8179 * Clear the receive interrupt. Use a read of the interrupt clear CSR
8180 * to insure that the write completed. This does NOT guarantee that
8181 * queued DMA writes to memory from the chip are pushed.
f4f30031
DL		 8182 */
8183static inline void clear_recv_intr(struct hfi1_ctxtdata *rcd)
8184{
8185 struct hfi1_devdata *dd = rcd->dd;
8186 u32 addr = CCE_INT_CLEAR + (8 * rcd->ireg);
8187
8188 mmiowb(); /* make sure everything before is written */
8189 write_csr(dd, addr, rcd->imask);
8190 /* force the above write on the chip and get a value back */
8191 (void)read_csr(dd, addr);
8192}
8193
8194/* force the receive interrupt */
fb9036dd 8195void force_recv_intr(struct hfi1_ctxtdata *rcd)
f4f30031
DL		 8196{
8197 write_csr(rcd->dd, CCE_INT_FORCE + (8 * rcd->ireg), rcd->imask);
8198}
8199
ecd42f8d
DL		 8200/*
8201 * Return non-zero if a packet is present.
8202 *
8203 * This routine is called when rechecking for packets after the RcvAvail
8204 * interrupt has been cleared down. First, do a quick check of memory for
8205 * a packet present. If not found, use an expensive CSR read of the context
8206 * tail to determine the actual tail. The CSR read is necessary because there
8207 * is no method to push pending DMAs to memory other than an interrupt and we
8208 * are trying to determine if we need to force an interrupt.
8209 */
f4f30031
DL		 8210static inline int check_packet_present(struct hfi1_ctxtdata *rcd)
8211{
ecd42f8d
DL		 8212 u32 tail;
8213 int present;
8214
f4f30031 8215 if (!HFI1_CAP_IS_KSET(DMA_RTAIL))
ecd42f8d 8216 present = (rcd->seq_cnt ==
f4f30031 8217 rhf_rcv_seq(rhf_to_cpu(get_rhf_addr(rcd))));
ecd42f8d
DL		 8218 else /* is RDMA rtail */
8219 present = (rcd->head != get_rcvhdrtail(rcd));
8220
8221 if (present)
8222 return 1;
f4f30031 8223
ecd42f8d
DL		 8224 /* fall back to a CSR read, correct indpendent of DMA_RTAIL */
8225 tail = (u32)read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
8226 return rcd->head != tail;
f4f30031
DL		 8227}
8228
8229/*
8230 * Receive packet IRQ handler. This routine expects to be on its own IRQ.
8231 * This routine will try to handle packets immediately (latency), but if
8232 * it finds too many, it will invoke the thread handler (bandwitdh). The
16733b88 8233 * chip receive interrupt is *not* cleared down until this or the thread (if
f4f30031
DL		 8234 * invoked) is finished. The intent is to avoid extra interrupts while we
8235 * are processing packets anyway.
77241056
MM		 8236 */
8237static irqreturn_t receive_context_interrupt(int irq, void *data)
8238{
8239 struct hfi1_ctxtdata *rcd = data;
8240 struct hfi1_devdata *dd = rcd->dd;
f4f30031
DL		 8241 int disposition;
8242 int present;
77241056
MM		 8243
8244 trace_hfi1_receive_interrupt(dd, rcd->ctxt);
8245 this_cpu_inc(*dd->int_counter);
affa48de 8246 aspm_ctx_disable(rcd);
77241056 8247
f4f30031
DL		 8248 /* receive interrupt remains blocked while processing packets */
8249 disposition = rcd->do_interrupt(rcd, 0);
77241056 8250
f4f30031
DL		 8251 /*
8252 * Too many packets were seen while processing packets in this
8253 * IRQ handler. Invoke the handler thread. The receive interrupt
8254 * remains blocked.
8255 */
8256 if (disposition == RCV_PKT_LIMIT)
8257 return IRQ_WAKE_THREAD;
8258
8259 /*
8260 * The packet processor detected no more packets. Clear the receive
8261 * interrupt and recheck for a packet packet that may have arrived
8262 * after the previous check and interrupt clear. If a packet arrived,
8263 * force another interrupt.
8264 */
8265 clear_recv_intr(rcd);
8266 present = check_packet_present(rcd);
8267 if (present)
8268 force_recv_intr(rcd);
8269
8270 return IRQ_HANDLED;
8271}
8272
8273/*
8274 * Receive packet thread handler. This expects to be invoked with the
8275 * receive interrupt still blocked.
8276 */
8277static irqreturn_t receive_context_thread(int irq, void *data)
8278{
8279 struct hfi1_ctxtdata *rcd = data;
8280 int present;
8281
8282 /* receive interrupt is still blocked from the IRQ handler */
8283 (void)rcd->do_interrupt(rcd, 1);
8284
8285 /*
8286 * The packet processor will only return if it detected no more
8287 * packets. Hold IRQs here so we can safely clear the interrupt and
8288 * recheck for a packet that may have arrived after the previous
8289 * check and the interrupt clear. If a packet arrived, force another
8290 * interrupt.
8291 */
8292 local_irq_disable();
8293 clear_recv_intr(rcd);
8294 present = check_packet_present(rcd);
8295 if (present)
8296 force_recv_intr(rcd);
8297 local_irq_enable();
77241056
MM		 8298
8299 return IRQ_HANDLED;
8300}
8301
8302/* ========================================================================= */
8303
8304u32 read_physical_state(struct hfi1_devdata *dd)
8305{
8306 u64 reg;
8307
8308 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE);
8309 return (reg >> DC_DC8051_STS_CUR_STATE_PORT_SHIFT)
8310 & DC_DC8051_STS_CUR_STATE_PORT_MASK;
8311}
8312
fb9036dd 8313u32 read_logical_state(struct hfi1_devdata *dd)
77241056
MM		 8314{
8315 u64 reg;
8316
8317 reg = read_csr(dd, DCC_CFG_PORT_CONFIG);
8318 return (reg >> DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT)
8319 & DCC_CFG_PORT_CONFIG_LINK_STATE_MASK;
8320}
8321
8322static void set_logical_state(struct hfi1_devdata *dd, u32 chip_lstate)
8323{
8324 u64 reg;
8325
8326 reg = read_csr(dd, DCC_CFG_PORT_CONFIG);
8327 /* clear current state, set new state */
8328 reg &= ~DCC_CFG_PORT_CONFIG_LINK_STATE_SMASK;
8329 reg |= (u64)chip_lstate << DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT;
8330 write_csr(dd, DCC_CFG_PORT_CONFIG, reg);
8331}
8332
8333/*
8334 * Use the 8051 to read a LCB CSR.
8335 */
8336static int read_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 *data)
8337{
8338 u32 regno;
8339 int ret;
8340
8341 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) {
8342 if (acquire_lcb_access(dd, 0) == 0) {
8343 *data = read_csr(dd, addr);
8344 release_lcb_access(dd, 0);
8345 return 0;
8346 }
8347 return -EBUSY;
8348 }
8349
8350 /* register is an index of LCB registers: (offset - base) / 8 */
8351 regno = (addr - DC_LCB_CFG_RUN) >> 3;
8352 ret = do_8051_command(dd, HCMD_READ_LCB_CSR, regno, data);
8353 if (ret != HCMD_SUCCESS)
8354 return -EBUSY;
8355 return 0;
8356}
8357
8358/*
8359 * Read an LCB CSR. Access may not be in host control, so check.
8360 * Return 0 on success, -EBUSY on failure.
8361 */
8362int read_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 *data)
8363{
8364 struct hfi1_pportdata *ppd = dd->pport;
8365
8366 /* if up, go through the 8051 for the value */
8367 if (ppd->host_link_state & HLS_UP)
8368 return read_lcb_via_8051(dd, addr, data);
8369 /* if going up or down, no access */
8370 if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE))
8371 return -EBUSY;
8372 /* otherwise, host has access */
8373 *data = read_csr(dd, addr);
8374 return 0;
8375}
8376
8377/*
8378 * Use the 8051 to write a LCB CSR.
8379 */
8380static int write_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 data)
8381{
3bf40d65
DL		 8382 u32 regno;
8383 int ret;
77241056 8384
3bf40d65
DL		 8385 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR ||
8386 (dd->dc8051_ver < dc8051_ver(0, 20))) {
8387 if (acquire_lcb_access(dd, 0) == 0) {
8388 write_csr(dd, addr, data);
8389 release_lcb_access(dd, 0);
8390 return 0;
8391 }
8392 return -EBUSY;
77241056 8393 }
3bf40d65
DL		 8394
8395 /* register is an index of LCB registers: (offset - base) / 8 */
8396 regno = (addr - DC_LCB_CFG_RUN) >> 3;
8397 ret = do_8051_command(dd, HCMD_WRITE_LCB_CSR, regno, &data);
8398 if (ret != HCMD_SUCCESS)
8399 return -EBUSY;
8400 return 0;
77241056
MM		 8401}
8402
8403/*
8404 * Write an LCB CSR. Access may not be in host control, so check.
8405 * Return 0 on success, -EBUSY on failure.
8406 */
8407int write_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 data)
8408{
8409 struct hfi1_pportdata *ppd = dd->pport;
8410
8411 /* if up, go through the 8051 for the value */
8412 if (ppd->host_link_state & HLS_UP)
8413 return write_lcb_via_8051(dd, addr, data);
8414 /* if going up or down, no access */
8415 if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE))
8416 return -EBUSY;
8417 /* otherwise, host has access */
8418 write_csr(dd, addr, data);
8419 return 0;
8420}
8421
8422/*
8423 * Returns:
8424 * < 0 = Linux error, not able to get access
8425 * > 0 = 8051 command RETURN_CODE
8426 */
8427static int do_8051_command(
8428 struct hfi1_devdata *dd,
8429 u32 type,
8430 u64 in_data,
8431 u64 *out_data)
8432{
8433 u64 reg, completed;
8434 int return_code;
8435 unsigned long flags;
8436 unsigned long timeout;
8437
8438 hfi1_cdbg(DC8051, "type %d, data 0x%012llx", type, in_data);
8439
8440 /*
8441 * Alternative to holding the lock for a long time:
8442 * - keep busy wait - have other users bounce off
8443 */
8444 spin_lock_irqsave(&dd->dc8051_lock, flags);
8445
8446 /* We can't send any commands to the 8051 if it's in reset */
8447 if (dd->dc_shutdown) {
8448 return_code = -ENODEV;
8449 goto fail;
8450 }
8451
8452 /*
8453 * If an 8051 host command timed out previously, then the 8051 is
8454 * stuck.
8455 *
8456 * On first timeout, attempt to reset and restart the entire DC
8457 * block (including 8051). (Is this too big of a hammer?)
8458 *
8459 * If the 8051 times out a second time, the reset did not bring it
8460 * back to healthy life. In that case, fail any subsequent commands.
8461 */
8462 if (dd->dc8051_timed_out) {
8463 if (dd->dc8051_timed_out > 1) {
8464 dd_dev_err(dd,
8465 "Previous 8051 host command timed out, skipping command %u\n",
8466 type);
8467 return_code = -ENXIO;
8468 goto fail;
8469 }
8470 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
8471 dc_shutdown(dd);
8472 dc_start(dd);
8473 spin_lock_irqsave(&dd->dc8051_lock, flags);
8474 }
8475
8476 /*
8477 * If there is no timeout, then the 8051 command interface is
8478 * waiting for a command.
8479 */
8480
3bf40d65
DL		 8481 /*
8482 * When writing a LCB CSR, out_data contains the full value to
8483 * to be written, while in_data contains the relative LCB
8484 * address in 7:0. Do the work here, rather than the caller,
8485 * of distrubting the write data to where it needs to go:
8486 *
8487 * Write data
8488 * 39:00 -> in_data[47:8]
8489 * 47:40 -> DC8051_CFG_EXT_DEV_0.RETURN_CODE
8490 * 63:48 -> DC8051_CFG_EXT_DEV_0.RSP_DATA
8491 */
8492 if (type == HCMD_WRITE_LCB_CSR) {
8493 in_data |= ((*out_data) & 0xffffffffffull) << 8;
8494 reg = ((((*out_data) >> 40) & 0xff) <<
8495 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT)
8496 | ((((*out_data) >> 48) & 0xffff) <<
8497 DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT);
8498 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, reg);
8499 }
8500
77241056
MM		 8501 /*
8502 * Do two writes: the first to stabilize the type and req_data, the
8503 * second to activate.
8504 */
8505 reg = ((u64)type & DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_MASK)
8506 << DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_SHIFT
8507 | (in_data & DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_MASK)
8508 << DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_SHIFT;
8509 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
8510 reg |= DC_DC8051_CFG_HOST_CMD_0_REQ_NEW_SMASK;
8511 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
8512
8513 /* wait for completion, alternate: interrupt */
8514 timeout = jiffies + msecs_to_jiffies(DC8051_COMMAND_TIMEOUT);
8515 while (1) {
8516 reg = read_csr(dd, DC_DC8051_CFG_HOST_CMD_1);
8517 completed = reg & DC_DC8051_CFG_HOST_CMD_1_COMPLETED_SMASK;
8518 if (completed)
8519 break;
8520 if (time_after(jiffies, timeout)) {
8521 dd->dc8051_timed_out++;
8522 dd_dev_err(dd, "8051 host command %u timeout\n", type);
8523 if (out_data)
8524 *out_data = 0;
8525 return_code = -ETIMEDOUT;
8526 goto fail;
8527 }
8528 udelay(2);
8529 }
8530
8531 if (out_data) {
8532 *out_data = (reg >> DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_SHIFT)
8533 & DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_MASK;
8534 if (type == HCMD_READ_LCB_CSR) {
8535 /* top 16 bits are in a different register */
8536 *out_data |= (read_csr(dd, DC_DC8051_CFG_EXT_DEV_1)
8537 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SMASK)
8538 << (48
8539 - DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT);
8540 }
8541 }
8542 return_code = (reg >> DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_SHIFT)
8543 & DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_MASK;
8544 dd->dc8051_timed_out = 0;
8545 /*
8546 * Clear command for next user.
8547 */
8548 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, 0);
8549
8550fail:
8551 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
8552
8553 return return_code;
8554}
8555
8556static int set_physical_link_state(struct hfi1_devdata *dd, u64 state)
8557{
8558 return do_8051_command(dd, HCMD_CHANGE_PHY_STATE, state, NULL);
8559}
8560
8ebd4cf1
EH		 8561int load_8051_config(struct hfi1_devdata *dd, u8 field_id,
8562 u8 lane_id, u32 config_data)
77241056
MM		 8563{
8564 u64 data;
8565 int ret;
8566
8567 data = (u64)field_id << LOAD_DATA_FIELD_ID_SHIFT
8568 | (u64)lane_id << LOAD_DATA_LANE_ID_SHIFT
8569 | (u64)config_data << LOAD_DATA_DATA_SHIFT;
8570 ret = do_8051_command(dd, HCMD_LOAD_CONFIG_DATA, data, NULL);
8571 if (ret != HCMD_SUCCESS) {
8572 dd_dev_err(dd,
17fb4f29
JJ		 8573 "load 8051 config: field id %d, lane %d, err %d\n",
8574 (int)field_id, (int)lane_id, ret);
77241056
MM		 8575 }
8576 return ret;
8577}
8578
8579/*
8580 * Read the 8051 firmware "registers". Use the RAM directly. Always
8581 * set the result, even on error.
8582 * Return 0 on success, -errno on failure
8583 */
8ebd4cf1
EH		 8584int read_8051_config(struct hfi1_devdata *dd, u8 field_id, u8 lane_id,
8585 u32 *result)
77241056
MM		 8586{
8587 u64 big_data;
8588 u32 addr;
8589 int ret;
8590
8591 /* address start depends on the lane_id */
8592 if (lane_id < 4)
8593 addr = (4 * NUM_GENERAL_FIELDS)
8594 + (lane_id * 4 * NUM_LANE_FIELDS);
8595 else
8596 addr = 0;
8597 addr += field_id * 4;
8598
8599 /* read is in 8-byte chunks, hardware will truncate the address down */
8600 ret = read_8051_data(dd, addr, 8, &big_data);
8601
8602 if (ret == 0) {
8603 /* extract the 4 bytes we want */
8604 if (addr & 0x4)
8605 *result = (u32)(big_data >> 32);
8606 else
8607 *result = (u32)big_data;
8608 } else {
8609 *result = 0;
8610 dd_dev_err(dd, "%s: direct read failed, lane %d, field %d!\n",
17fb4f29 8611 __func__, lane_id, field_id);
77241056
MM		 8612 }
8613
8614 return ret;
8615}
8616
8617static int write_vc_local_phy(struct hfi1_devdata *dd, u8 power_management,
8618 u8 continuous)
8619{
8620 u32 frame;
8621
8622 frame = continuous << CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT
8623 | power_management << POWER_MANAGEMENT_SHIFT;
8624 return load_8051_config(dd, VERIFY_CAP_LOCAL_PHY,
8625 GENERAL_CONFIG, frame);
8626}
8627
8628static int write_vc_local_fabric(struct hfi1_devdata *dd, u8 vau, u8 z, u8 vcu,
8629 u16 vl15buf, u8 crc_sizes)
8630{
8631 u32 frame;
8632
8633 frame = (u32)vau << VAU_SHIFT
8634 | (u32)z << Z_SHIFT
8635 | (u32)vcu << VCU_SHIFT
8636 | (u32)vl15buf << VL15BUF_SHIFT
8637 | (u32)crc_sizes << CRC_SIZES_SHIFT;
8638 return load_8051_config(dd, VERIFY_CAP_LOCAL_FABRIC,
8639 GENERAL_CONFIG, frame);
8640}
8641
8642static void read_vc_local_link_width(struct hfi1_devdata *dd, u8 *misc_bits,
8643 u8 *flag_bits, u16 *link_widths)
8644{
8645 u32 frame;
8646
8647 read_8051_config(dd, VERIFY_CAP_LOCAL_LINK_WIDTH, GENERAL_CONFIG,
17fb4f29 8648 &frame);
77241056
MM		 8649 *misc_bits = (frame >> MISC_CONFIG_BITS_SHIFT) & MISC_CONFIG_BITS_MASK;
8650 *flag_bits = (frame >> LOCAL_FLAG_BITS_SHIFT) & LOCAL_FLAG_BITS_MASK;
8651 *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK;
8652}
8653
8654static int write_vc_local_link_width(struct hfi1_devdata *dd,
8655 u8 misc_bits,
8656 u8 flag_bits,
8657 u16 link_widths)
8658{
8659 u32 frame;
8660
8661 frame = (u32)misc_bits << MISC_CONFIG_BITS_SHIFT
8662 | (u32)flag_bits << LOCAL_FLAG_BITS_SHIFT
8663 | (u32)link_widths << LINK_WIDTH_SHIFT;
8664 return load_8051_config(dd, VERIFY_CAP_LOCAL_LINK_WIDTH, GENERAL_CONFIG,
8665 frame);
8666}
8667
8668static int write_local_device_id(struct hfi1_devdata *dd, u16 device_id,
8669 u8 device_rev)
8670{
8671 u32 frame;
8672
8673 frame = ((u32)device_id << LOCAL_DEVICE_ID_SHIFT)
8674 | ((u32)device_rev << LOCAL_DEVICE_REV_SHIFT);
8675 return load_8051_config(dd, LOCAL_DEVICE_ID, GENERAL_CONFIG, frame);
8676}
8677
8678static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id,
8679 u8 *device_rev)
8680{
8681 u32 frame;
8682
8683 read_8051_config(dd, REMOTE_DEVICE_ID, GENERAL_CONFIG, &frame);
8684 *device_id = (frame >> REMOTE_DEVICE_ID_SHIFT) & REMOTE_DEVICE_ID_MASK;
8685 *device_rev = (frame >> REMOTE_DEVICE_REV_SHIFT)
8686 & REMOTE_DEVICE_REV_MASK;
8687}
8688
8689void read_misc_status(struct hfi1_devdata *dd, u8 *ver_a, u8 *ver_b)
8690{
8691 u32 frame;
8692
8693 read_8051_config(dd, MISC_STATUS, GENERAL_CONFIG, &frame);
8694 *ver_a = (frame >> STS_FM_VERSION_A_SHIFT) & STS_FM_VERSION_A_MASK;
8695 *ver_b = (frame >> STS_FM_VERSION_B_SHIFT) & STS_FM_VERSION_B_MASK;
8696}
8697
8698static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management,
8699 u8 *continuous)
8700{
8701 u32 frame;
8702
8703 read_8051_config(dd, VERIFY_CAP_REMOTE_PHY, GENERAL_CONFIG, &frame);
8704 *power_management = (frame >> POWER_MANAGEMENT_SHIFT)
8705 & POWER_MANAGEMENT_MASK;
8706 *continuous = (frame >> CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT)
8707 & CONTINIOUS_REMOTE_UPDATE_SUPPORT_MASK;
8708}
8709
8710static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z,
8711 u8 *vcu, u16 *vl15buf, u8 *crc_sizes)
8712{
8713 u32 frame;
8714
8715 read_8051_config(dd, VERIFY_CAP_REMOTE_FABRIC, GENERAL_CONFIG, &frame);
8716 *vau = (frame >> VAU_SHIFT) & VAU_MASK;
8717 *z = (frame >> Z_SHIFT) & Z_MASK;
8718 *vcu = (frame >> VCU_SHIFT) & VCU_MASK;
8719 *vl15buf = (frame >> VL15BUF_SHIFT) & VL15BUF_MASK;
8720 *crc_sizes = (frame >> CRC_SIZES_SHIFT) & CRC_SIZES_MASK;
8721}
8722
8723static void read_vc_remote_link_width(struct hfi1_devdata *dd,
8724 u8 *remote_tx_rate,
8725 u16 *link_widths)
8726{
8727 u32 frame;
8728
8729 read_8051_config(dd, VERIFY_CAP_REMOTE_LINK_WIDTH, GENERAL_CONFIG,
17fb4f29 8730 &frame);
77241056
MM		 8731 *remote_tx_rate = (frame >> REMOTE_TX_RATE_SHIFT)
8732 & REMOTE_TX_RATE_MASK;
8733 *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK;
8734}
8735
8736static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx)
8737{
8738 u32 frame;
8739
8740 read_8051_config(dd, LOCAL_LNI_INFO, GENERAL_CONFIG, &frame);
8741 *enable_lane_rx = (frame >> ENABLE_LANE_RX_SHIFT) & ENABLE_LANE_RX_MASK;
8742}
8743
8744static void read_mgmt_allowed(struct hfi1_devdata *dd, u8 *mgmt_allowed)
8745{
8746 u32 frame;
8747
8748 read_8051_config(dd, REMOTE_LNI_INFO, GENERAL_CONFIG, &frame);
8749 *mgmt_allowed = (frame >> MGMT_ALLOWED_SHIFT) & MGMT_ALLOWED_MASK;
8750}
8751
8752static void read_last_local_state(struct hfi1_devdata *dd, u32 *lls)
8753{
8754 read_8051_config(dd, LAST_LOCAL_STATE_COMPLETE, GENERAL_CONFIG, lls);
8755}
8756
8757static void read_last_remote_state(struct hfi1_devdata *dd, u32 *lrs)
8758{
8759 read_8051_config(dd, LAST_REMOTE_STATE_COMPLETE, GENERAL_CONFIG, lrs);
8760}
8761
8762void hfi1_read_link_quality(struct hfi1_devdata *dd, u8 *link_quality)
8763{
8764 u32 frame;
8765 int ret;
8766
8767 *link_quality = 0;
8768 if (dd->pport->host_link_state & HLS_UP) {
8769 ret = read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG,
17fb4f29 8770 &frame);
77241056
MM		 8771 if (ret == 0)
8772 *link_quality = (frame >> LINK_QUALITY_SHIFT)
8773 & LINK_QUALITY_MASK;
8774 }
8775}
8776
8777static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc)
8778{
8779 u32 frame;
8780
8781 read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG, &frame);
8782 *pdrrc = (frame >> DOWN_REMOTE_REASON_SHIFT) & DOWN_REMOTE_REASON_MASK;
8783}
8784
feb831dd
DL		 8785static void read_link_down_reason(struct hfi1_devdata *dd, u8 *ldr)
8786{
8787 u32 frame;
8788
8789 read_8051_config(dd, LINK_DOWN_REASON, GENERAL_CONFIG, &frame);
8790 *ldr = (frame & 0xff);
8791}
8792
77241056
MM		 8793static int read_tx_settings(struct hfi1_devdata *dd,
8794 u8 *enable_lane_tx,
8795 u8 *tx_polarity_inversion,
8796 u8 *rx_polarity_inversion,
8797 u8 *max_rate)
8798{
8799 u32 frame;
8800 int ret;
8801
8802 ret = read_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, &frame);
8803 *enable_lane_tx = (frame >> ENABLE_LANE_TX_SHIFT)
8804 & ENABLE_LANE_TX_MASK;
8805 *tx_polarity_inversion = (frame >> TX_POLARITY_INVERSION_SHIFT)
8806 & TX_POLARITY_INVERSION_MASK;
8807 *rx_polarity_inversion = (frame >> RX_POLARITY_INVERSION_SHIFT)
8808 & RX_POLARITY_INVERSION_MASK;
8809 *max_rate = (frame >> MAX_RATE_SHIFT) & MAX_RATE_MASK;
8810 return ret;
8811}
8812
8813static int write_tx_settings(struct hfi1_devdata *dd,
8814 u8 enable_lane_tx,
8815 u8 tx_polarity_inversion,
8816 u8 rx_polarity_inversion,
8817 u8 max_rate)
8818{
8819 u32 frame;
8820
8821 /* no need to mask, all variable sizes match field widths */
8822 frame = enable_lane_tx << ENABLE_LANE_TX_SHIFT
8823 | tx_polarity_inversion << TX_POLARITY_INVERSION_SHIFT
8824 | rx_polarity_inversion << RX_POLARITY_INVERSION_SHIFT
8825 | max_rate << MAX_RATE_SHIFT;
8826 return load_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, frame);
8827}
8828
77241056
MM		 8829/*
8830 * Read an idle LCB message.
8831 *
8832 * Returns 0 on success, -EINVAL on error
8833 */
8834static int read_idle_message(struct hfi1_devdata *dd, u64 type, u64 *data_out)
8835{
8836 int ret;
8837
17fb4f29 8838 ret = do_8051_command(dd, HCMD_READ_LCB_IDLE_MSG, type, data_out);
77241056
MM		 8839 if (ret != HCMD_SUCCESS) {
8840 dd_dev_err(dd, "read idle message: type %d, err %d\n",
17fb4f29 8841 (u32)type, ret);
77241056
MM		 8842 return -EINVAL;
8843 }
8844 dd_dev_info(dd, "%s: read idle message 0x%llx\n", __func__, *data_out);
8845 /* return only the payload as we already know the type */
8846 *data_out >>= IDLE_PAYLOAD_SHIFT;
8847 return 0;
8848}
8849
8850/*
8851 * Read an idle SMA message. To be done in response to a notification from
8852 * the 8051.
8853 *
8854 * Returns 0 on success, -EINVAL on error
8855 */
8856static int read_idle_sma(struct hfi1_devdata *dd, u64 *data)
8857{
17fb4f29
JJ		 8858 return read_idle_message(dd, (u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT,
8859 data);
77241056
MM		 8860}
8861
8862/*
8863 * Send an idle LCB message.
8864 *
8865 * Returns 0 on success, -EINVAL on error
8866 */
8867static int send_idle_message(struct hfi1_devdata *dd, u64 data)
8868{
8869 int ret;
8870
8871 dd_dev_info(dd, "%s: sending idle message 0x%llx\n", __func__, data);
8872 ret = do_8051_command(dd, HCMD_SEND_LCB_IDLE_MSG, data, NULL);
8873 if (ret != HCMD_SUCCESS) {
8874 dd_dev_err(dd, "send idle message: data 0x%llx, err %d\n",
17fb4f29 8875 data, ret);
77241056
MM		 8876 return -EINVAL;
8877 }
8878 return 0;
8879}
8880
8881/*
8882 * Send an idle SMA message.
8883 *
8884 * Returns 0 on success, -EINVAL on error
8885 */
8886int send_idle_sma(struct hfi1_devdata *dd, u64 message)
8887{
8888 u64 data;
8889
17fb4f29
JJ		 8890 data = ((message & IDLE_PAYLOAD_MASK) << IDLE_PAYLOAD_SHIFT) |
8891 ((u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT);
77241056
MM		 8892 return send_idle_message(dd, data);
8893}
8894
8895/*
8896 * Initialize the LCB then do a quick link up. This may or may not be
8897 * in loopback.
8898 *
8899 * return 0 on success, -errno on error
8900 */
8901static int do_quick_linkup(struct hfi1_devdata *dd)
8902{
8903 u64 reg;
8904 unsigned long timeout;
8905 int ret;
8906
8907 lcb_shutdown(dd, 0);
8908
8909 if (loopback) {
8910 /* LCB_CFG_LOOPBACK.VAL = 2 */
8911 /* LCB_CFG_LANE_WIDTH.VAL = 0 */
8912 write_csr(dd, DC_LCB_CFG_LOOPBACK,
17fb4f29 8913 IB_PACKET_TYPE << DC_LCB_CFG_LOOPBACK_VAL_SHIFT);
77241056
MM		 8914 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0);
8915 }
8916
8917 /* start the LCBs */
8918 /* LCB_CFG_TX_FIFOS_RESET.VAL = 0 */
8919 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
8920
8921 /* simulator only loopback steps */
8922 if (loopback && dd->icode == ICODE_FUNCTIONAL_SIMULATOR) {
8923 /* LCB_CFG_RUN.EN = 1 */
8924 write_csr(dd, DC_LCB_CFG_RUN,
17fb4f29 8925 1ull << DC_LCB_CFG_RUN_EN_SHIFT);
77241056
MM		 8926
8927 /* watch LCB_STS_LINK_TRANSFER_ACTIVE */
8928 timeout = jiffies + msecs_to_jiffies(10);
8929 while (1) {
17fb4f29 8930 reg = read_csr(dd, DC_LCB_STS_LINK_TRANSFER_ACTIVE);
77241056
MM		 8931 if (reg)
8932 break;
8933 if (time_after(jiffies, timeout)) {
8934 dd_dev_err(dd,
17fb4f29 8935 "timeout waiting for LINK_TRANSFER_ACTIVE\n");
77241056
MM		 8936 return -ETIMEDOUT;
8937 }
8938 udelay(2);
8939 }
8940
8941 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP,
17fb4f29 8942 1ull << DC_LCB_CFG_ALLOW_LINK_UP_VAL_SHIFT);
77241056
MM		 8943 }
8944
8945 if (!loopback) {
8946 /*
8947 * When doing quick linkup and not in loopback, both
8948 * sides must be done with LCB set-up before either
8949 * starts the quick linkup. Put a delay here so that
8950 * both sides can be started and have a chance to be
8951 * done with LCB set up before resuming.
8952 */
8953 dd_dev_err(dd,
17fb4f29 8954 "Pausing for peer to be finished with LCB set up\n");
77241056 8955 msleep(5000);
17fb4f29 8956 dd_dev_err(dd, "Continuing with quick linkup\n");
77241056
MM		 8957 }
8958
8959 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
8960 set_8051_lcb_access(dd);
8961
8962 /*
8963 * State "quick" LinkUp request sets the physical link state to
8964 * LinkUp without a verify capability sequence.
8965 * This state is in simulator v37 and later.
8966 */
8967 ret = set_physical_link_state(dd, PLS_QUICK_LINKUP);
8968 if (ret != HCMD_SUCCESS) {
8969 dd_dev_err(dd,
17fb4f29
JJ		 8970 "%s: set physical link state to quick LinkUp failed with return %d\n",
8971 __func__, ret);
77241056
MM		 8972
8973 set_host_lcb_access(dd);
8974 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
8975
8976 if (ret >= 0)
8977 ret = -EINVAL;
8978 return ret;
8979 }
8980
8981 return 0; /* success */
8982}
8983
8984/*
8985 * Set the SerDes to internal loopback mode.
8986 * Returns 0 on success, -errno on error.
8987 */
8988static int set_serdes_loopback_mode(struct hfi1_devdata *dd)
8989{
8990 int ret;
8991
8992 ret = set_physical_link_state(dd, PLS_INTERNAL_SERDES_LOOPBACK);
8993 if (ret == HCMD_SUCCESS)
8994 return 0;
8995 dd_dev_err(dd,
17fb4f29
JJ		 8996 "Set physical link state to SerDes Loopback failed with return %d\n",
8997 ret);
77241056
MM		 8998 if (ret >= 0)
8999 ret = -EINVAL;
9000 return ret;
9001}
9002
9003/*
9004 * Do all special steps to set up loopback.
9005 */
9006static int init_loopback(struct hfi1_devdata *dd)
9007{
9008 dd_dev_info(dd, "Entering loopback mode\n");
9009
9010 /* all loopbacks should disable self GUID check */
9011 write_csr(dd, DC_DC8051_CFG_MODE,
17fb4f29 9012 (read_csr(dd, DC_DC8051_CFG_MODE) | DISABLE_SELF_GUID_CHECK));
77241056
MM		 9013
9014 /*
9015 * The simulator has only one loopback option - LCB. Switch
9016 * to that option, which includes quick link up.
9017 *
9018 * Accept all valid loopback values.
9019 */
d0d236ea
JJ		 9020 if ((dd->icode == ICODE_FUNCTIONAL_SIMULATOR) &&
9021 (loopback == LOOPBACK_SERDES || loopback == LOOPBACK_LCB ||
9022 loopback == LOOPBACK_CABLE)) {
77241056
MM		 9023 loopback = LOOPBACK_LCB;
9024 quick_linkup = 1;
9025 return 0;
9026 }
9027
9028 /* handle serdes loopback */
9029 if (loopback == LOOPBACK_SERDES) {
9030 /* internal serdes loopack needs quick linkup on RTL */
9031 if (dd->icode == ICODE_RTL_SILICON)
9032 quick_linkup = 1;
9033 return set_serdes_loopback_mode(dd);
9034 }
9035
9036 /* LCB loopback - handled at poll time */
9037 if (loopback == LOOPBACK_LCB) {
9038 quick_linkup = 1; /* LCB is always quick linkup */
9039
9040 /* not supported in emulation due to emulation RTL changes */
9041 if (dd->icode == ICODE_FPGA_EMULATION) {
9042 dd_dev_err(dd,
17fb4f29 9043 "LCB loopback not supported in emulation\n");
77241056
MM		 9044 return -EINVAL;
9045 }
9046 return 0;
9047 }
9048
9049 /* external cable loopback requires no extra steps */
9050 if (loopback == LOOPBACK_CABLE)
9051 return 0;
9052
9053 dd_dev_err(dd, "Invalid loopback mode %d\n", loopback);
9054 return -EINVAL;
9055}
9056
9057/*
9058 * Translate from the OPA_LINK_WIDTH handed to us by the FM to bits
9059 * used in the Verify Capability link width attribute.
9060 */
9061static u16 opa_to_vc_link_widths(u16 opa_widths)
9062{
9063 int i;
9064 u16 result = 0;
9065
9066 static const struct link_bits {
9067 u16 from;
9068 u16 to;
9069 } opa_link_xlate[] = {
8638b77f
JJ		 9070 { OPA_LINK_WIDTH_1X, 1 << (1 - 1) },
9071 { OPA_LINK_WIDTH_2X, 1 << (2 - 1) },
9072 { OPA_LINK_WIDTH_3X, 1 << (3 - 1) },
9073 { OPA_LINK_WIDTH_4X, 1 << (4 - 1) },
77241056
MM		 9074 };
9075
9076 for (i = 0; i < ARRAY_SIZE(opa_link_xlate); i++) {
9077 if (opa_widths & opa_link_xlate[i].from)
9078 result |= opa_link_xlate[i].to;
9079 }
9080 return result;
9081}
9082
9083/*
9084 * Set link attributes before moving to polling.
9085 */
9086static int set_local_link_attributes(struct hfi1_pportdata *ppd)
9087{
9088 struct hfi1_devdata *dd = ppd->dd;
9089 u8 enable_lane_tx;
9090 u8 tx_polarity_inversion;
9091 u8 rx_polarity_inversion;
9092 int ret;
9093
9094 /* reset our fabric serdes to clear any lingering problems */
9095 fabric_serdes_reset(dd);
9096
9097 /* set the local tx rate - need to read-modify-write */
9098 ret = read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion,
17fb4f29 9099 &rx_polarity_inversion, &ppd->local_tx_rate);
77241056
MM		 9100 if (ret)
9101 goto set_local_link_attributes_fail;
9102
9103 if (dd->dc8051_ver < dc8051_ver(0, 20)) {
9104 /* set the tx rate to the fastest enabled */
9105 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G)
9106 ppd->local_tx_rate = 1;
9107 else
9108 ppd->local_tx_rate = 0;
9109 } else {
9110 /* set the tx rate to all enabled */
9111 ppd->local_tx_rate = 0;
9112 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G)
9113 ppd->local_tx_rate |= 2;
9114 if (ppd->link_speed_enabled & OPA_LINK_SPEED_12_5G)
9115 ppd->local_tx_rate |= 1;
9116 }
febffe2c
EH		 9117
9118 enable_lane_tx = 0xF; /* enable all four lanes */
77241056 9119 ret = write_tx_settings(dd, enable_lane_tx, tx_polarity_inversion,
17fb4f29 9120 rx_polarity_inversion, ppd->local_tx_rate);
77241056
MM		 9121 if (ret != HCMD_SUCCESS)
9122 goto set_local_link_attributes_fail;
9123
9124 /*
9125 * DC supports continuous updates.
9126 */
17fb4f29
JJ		 9127 ret = write_vc_local_phy(dd,
9128 0 /* no power management */,
9129 1 /* continuous updates */);
77241056
MM		 9130 if (ret != HCMD_SUCCESS)
9131 goto set_local_link_attributes_fail;
9132
9133 /* z=1 in the next call: AU of 0 is not supported by the hardware */
9134 ret = write_vc_local_fabric(dd, dd->vau, 1, dd->vcu, dd->vl15_init,
9135 ppd->port_crc_mode_enabled);
9136 if (ret != HCMD_SUCCESS)
9137 goto set_local_link_attributes_fail;
9138
9139 ret = write_vc_local_link_width(dd, 0, 0,
17fb4f29
JJ		 9140 opa_to_vc_link_widths(
9141 ppd->link_width_enabled));
77241056
MM		 9142 if (ret != HCMD_SUCCESS)
9143 goto set_local_link_attributes_fail;
9144
9145 /* let peer know who we are */
9146 ret = write_local_device_id(dd, dd->pcidev->device, dd->minrev);
9147 if (ret == HCMD_SUCCESS)
9148 return 0;
9149
9150set_local_link_attributes_fail:
9151 dd_dev_err(dd,
17fb4f29
JJ		 9152 "Failed to set local link attributes, return 0x%x\n",
9153 ret);
77241056
MM		 9154 return ret;
9155}
9156
9157/*
623bba2d
EH		 9158 * Call this to start the link.
9159 * Do not do anything if the link is disabled.
9160 * Returns 0 if link is disabled, moved to polling, or the driver is not ready.
77241056
MM		 9161 */
9162int start_link(struct hfi1_pportdata *ppd)
9163{
9164 if (!ppd->link_enabled) {
9165 dd_dev_info(ppd->dd,
17fb4f29
JJ		 9166 "%s: stopping link start because link is disabled\n",
9167 __func__);
77241056
MM		 9168 return 0;
9169 }
9170 if (!ppd->driver_link_ready) {
9171 dd_dev_info(ppd->dd,
17fb4f29
JJ		 9172 "%s: stopping link start because driver is not ready\n",
9173 __func__);
77241056
MM		 9174 return 0;
9175 }
9176
3ec5fa28
SS		 9177 /*
9178 * FULL_MGMT_P_KEY is cleared from the pkey table, so that the
9179 * pkey table can be configured properly if the HFI unit is connected
9180 * to switch port with MgmtAllowed=NO
9181 */
9182 clear_full_mgmt_pkey(ppd);
9183
623bba2d 9184 return set_link_state(ppd, HLS_DN_POLL);
77241056
MM		 9185}
9186
8ebd4cf1
EH		 9187static void wait_for_qsfp_init(struct hfi1_pportdata *ppd)
9188{
9189 struct hfi1_devdata *dd = ppd->dd;
9190 u64 mask;
9191 unsigned long timeout;
9192
9193 /*
9194 * Check for QSFP interrupt for t_init (SFF 8679)
9195 */
9196 timeout = jiffies + msecs_to_jiffies(2000);
9197 while (1) {
9198 mask = read_csr(dd, dd->hfi1_id ?
9199 ASIC_QSFP2_IN : ASIC_QSFP1_IN);
9200 if (!(mask & QSFP_HFI0_INT_N)) {
9201 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR :
9202 ASIC_QSFP1_CLEAR, QSFP_HFI0_INT_N);
9203 break;
9204 }
9205 if (time_after(jiffies, timeout)) {
9206 dd_dev_info(dd, "%s: No IntN detected, reset complete\n",
9207 __func__);
9208 break;
9209 }
9210 udelay(2);
9211 }
9212}
9213
9214static void set_qsfp_int_n(struct hfi1_pportdata *ppd, u8 enable)
9215{
9216 struct hfi1_devdata *dd = ppd->dd;
9217 u64 mask;
9218
9219 mask = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK);
9220 if (enable)
9221 mask |= (u64)QSFP_HFI0_INT_N;
9222 else
9223 mask &= ~(u64)QSFP_HFI0_INT_N;
9224 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, mask);
9225}
9226
9227void reset_qsfp(struct hfi1_pportdata *ppd)
77241056
MM		 9228{
9229 struct hfi1_devdata *dd = ppd->dd;
9230 u64 mask, qsfp_mask;
9231
8ebd4cf1
EH		 9232 /* Disable INT_N from triggering QSFP interrupts */
9233 set_qsfp_int_n(ppd, 0);
9234
9235 /* Reset the QSFP */
77241056 9236 mask = (u64)QSFP_HFI0_RESET_N;
77241056
MM		 9237
9238 qsfp_mask = read_csr(dd,
17fb4f29 9239 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT);
77241056
MM		 9240 qsfp_mask &= ~mask;
9241 write_csr(dd,
17fb4f29 9242 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask);
77241056
MM		 9243
9244 udelay(10);
9245
9246 qsfp_mask |= mask;
9247 write_csr(dd,
17fb4f29 9248 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask);
8ebd4cf1
EH		 9249
9250 wait_for_qsfp_init(ppd);
9251
9252 /*
9253 * Allow INT_N to trigger the QSFP interrupt to watch
9254 * for alarms and warnings
9255 */
9256 set_qsfp_int_n(ppd, 1);
77241056
MM		 9257}
9258
9259static int handle_qsfp_error_conditions(struct hfi1_pportdata *ppd,
9260 u8 *qsfp_interrupt_status)
9261{
9262 struct hfi1_devdata *dd = ppd->dd;
9263
9264 if ((qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_ALARM) ||
17fb4f29
JJ		 9265 (qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_WARNING))
9266 dd_dev_info(dd, "%s: QSFP cable on fire\n",
9267 __func__);
77241056
MM		 9268
9269 if ((qsfp_interrupt_status[0] & QSFP_LOW_TEMP_ALARM) ||
17fb4f29
JJ		 9270 (qsfp_interrupt_status[0] & QSFP_LOW_TEMP_WARNING))
9271 dd_dev_info(dd, "%s: QSFP cable temperature too low\n",
9272 __func__);
77241056 9273
0c7f77af
EH		 9274 /*
9275 * The remaining alarms/warnings don't matter if the link is down.
9276 */
9277 if (ppd->host_link_state & HLS_DOWN)
9278 return 0;
9279
77241056 9280 if ((qsfp_interrupt_status[1] & QSFP_HIGH_VCC_ALARM) ||
17fb4f29
JJ		 9281 (qsfp_interrupt_status[1] & QSFP_HIGH_VCC_WARNING))
9282 dd_dev_info(dd, "%s: QSFP supply voltage too high\n",
9283 __func__);
77241056
MM		 9284
9285 if ((qsfp_interrupt_status[1] & QSFP_LOW_VCC_ALARM) ||
17fb4f29
JJ		 9286 (qsfp_interrupt_status[1] & QSFP_LOW_VCC_WARNING))
9287 dd_dev_info(dd, "%s: QSFP supply voltage too low\n",
9288 __func__);
77241056
MM		 9289
9290 /* Byte 2 is vendor specific */
9291
9292 if ((qsfp_interrupt_status[3] & QSFP_HIGH_POWER_ALARM) ||
17fb4f29
JJ		 9293 (qsfp_interrupt_status[3] & QSFP_HIGH_POWER_WARNING))
9294 dd_dev_info(dd, "%s: Cable RX channel 1/2 power too high\n",
9295 __func__);
77241056
MM		 9296
9297 if ((qsfp_interrupt_status[3] & QSFP_LOW_POWER_ALARM) ||
17fb4f29
JJ		 9298 (qsfp_interrupt_status[3] & QSFP_LOW_POWER_WARNING))
9299 dd_dev_info(dd, "%s: Cable RX channel 1/2 power too low\n",
9300 __func__);
77241056
MM		 9301
9302 if ((qsfp_interrupt_status[4] & QSFP_HIGH_POWER_ALARM) ||
17fb4f29
JJ		 9303 (qsfp_interrupt_status[4] & QSFP_HIGH_POWER_WARNING))
9304 dd_dev_info(dd, "%s: Cable RX channel 3/4 power too high\n",
9305 __func__);
77241056
MM		 9306
9307 if ((qsfp_interrupt_status[4] & QSFP_LOW_POWER_ALARM) ||
17fb4f29
JJ		 9308 (qsfp_interrupt_status[4] & QSFP_LOW_POWER_WARNING))
9309 dd_dev_info(dd, "%s: Cable RX channel 3/4 power too low\n",
9310 __func__);
77241056
MM		 9311
9312 if ((qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_ALARM) ||
17fb4f29
JJ		 9313 (qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_WARNING))
9314 dd_dev_info(dd, "%s: Cable TX channel 1/2 bias too high\n",
9315 __func__);
77241056
MM		 9316
9317 if ((qsfp_interrupt_status[5] & QSFP_LOW_BIAS_ALARM) ||
17fb4f29
JJ		 9318 (qsfp_interrupt_status[5] & QSFP_LOW_BIAS_WARNING))
9319 dd_dev_info(dd, "%s: Cable TX channel 1/2 bias too low\n",
9320 __func__);
77241056
MM		 9321
9322 if ((qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_ALARM) ||
17fb4f29
JJ		 9323 (qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_WARNING))
9324 dd_dev_info(dd, "%s: Cable TX channel 3/4 bias too high\n",
9325 __func__);
77241056
MM		 9326
9327 if ((qsfp_interrupt_status[6] & QSFP_LOW_BIAS_ALARM) ||
17fb4f29
JJ		 9328 (qsfp_interrupt_status[6] & QSFP_LOW_BIAS_WARNING))
9329 dd_dev_info(dd, "%s: Cable TX channel 3/4 bias too low\n",
9330 __func__);
77241056
MM		 9331
9332 if ((qsfp_interrupt_status[7] & QSFP_HIGH_POWER_ALARM) ||
17fb4f29
JJ		 9333 (qsfp_interrupt_status[7] & QSFP_HIGH_POWER_WARNING))
9334 dd_dev_info(dd, "%s: Cable TX channel 1/2 power too high\n",
9335 __func__);
77241056
MM		 9336
9337 if ((qsfp_interrupt_status[7] & QSFP_LOW_POWER_ALARM) ||
17fb4f29
JJ		 9338 (qsfp_interrupt_status[7] & QSFP_LOW_POWER_WARNING))
9339 dd_dev_info(dd, "%s: Cable TX channel 1/2 power too low\n",
9340 __func__);
77241056
MM		 9341
9342 if ((qsfp_interrupt_status[8] & QSFP_HIGH_POWER_ALARM) ||
17fb4f29
JJ		 9343 (qsfp_interrupt_status[8] & QSFP_HIGH_POWER_WARNING))
9344 dd_dev_info(dd, "%s: Cable TX channel 3/4 power too high\n",
9345 __func__);
77241056
MM		 9346
9347 if ((qsfp_interrupt_status[8] & QSFP_LOW_POWER_ALARM) ||
17fb4f29
JJ		 9348 (qsfp_interrupt_status[8] & QSFP_LOW_POWER_WARNING))
9349 dd_dev_info(dd, "%s: Cable TX channel 3/4 power too low\n",
9350 __func__);
77241056
MM		 9351
9352 /* Bytes 9-10 and 11-12 are reserved */
9353 /* Bytes 13-15 are vendor specific */
9354
9355 return 0;
9356}
9357
623bba2d 9358/* This routine will only be scheduled if the QSFP module present is asserted */
8ebd4cf1 9359void qsfp_event(struct work_struct *work)
77241056
MM		 9360{
9361 struct qsfp_data *qd;
9362 struct hfi1_pportdata *ppd;
9363 struct hfi1_devdata *dd;
9364
9365 qd = container_of(work, struct qsfp_data, qsfp_work);
9366 ppd = qd->ppd;
9367 dd = ppd->dd;
9368
9369 /* Sanity check */
9370 if (!qsfp_mod_present(ppd))
9371 return;
9372
9373 /*
0c7f77af
EH		 9374 * Turn DC back on after cable has been re-inserted. Up until
9375 * now, the DC has been in reset to save power.
77241056
MM		 9376 */
9377 dc_start(dd);
9378
9379 if (qd->cache_refresh_required) {
8ebd4cf1 9380 set_qsfp_int_n(ppd, 0);
77241056 9381
8ebd4cf1
EH		 9382 wait_for_qsfp_init(ppd);
9383
9384 /*
9385 * Allow INT_N to trigger the QSFP interrupt to watch
9386 * for alarms and warnings
77241056 9387 */
8ebd4cf1
EH		 9388 set_qsfp_int_n(ppd, 1);
9389
9390 tune_serdes(ppd);
9391
9392 start_link(ppd);
77241056
MM		 9393 }
9394
9395 if (qd->check_interrupt_flags) {
9396 u8 qsfp_interrupt_status[16] = {0,};
9397
765a6fac
DL		 9398 if (one_qsfp_read(ppd, dd->hfi1_id, 6,
9399 &qsfp_interrupt_status[0], 16) != 16) {
77241056 9400 dd_dev_info(dd,
17fb4f29
JJ		 9401 "%s: Failed to read status of QSFP module\n",
9402 __func__);
77241056
MM		 9403 } else {
9404 unsigned long flags;
77241056 9405
8ebd4cf1
EH		 9406 handle_qsfp_error_conditions(
9407 ppd, qsfp_interrupt_status);
77241056
MM		 9408 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
9409 ppd->qsfp_info.check_interrupt_flags = 0;
9410 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
17fb4f29 9411 flags);
77241056
MM		 9412 }
9413 }
9414}
9415
8ebd4cf1 9416static void init_qsfp_int(struct hfi1_devdata *dd)
77241056 9417{
8ebd4cf1
EH		 9418 struct hfi1_pportdata *ppd = dd->pport;
9419 u64 qsfp_mask, cce_int_mask;
9420 const int qsfp1_int_smask = QSFP1_INT % 64;
9421 const int qsfp2_int_smask = QSFP2_INT % 64;
77241056 9422
8ebd4cf1
EH		 9423 /*
9424 * disable QSFP1 interrupts for HFI1, QSFP2 interrupts for HFI0
9425 * Qsfp1Int and Qsfp2Int are adjacent bits in the same CSR,
9426 * therefore just one of QSFP1_INT/QSFP2_INT can be used to find
9427 * the index of the appropriate CSR in the CCEIntMask CSR array
9428 */
9429 cce_int_mask = read_csr(dd, CCE_INT_MASK +
9430 (8 * (QSFP1_INT / 64)));
9431 if (dd->hfi1_id) {
9432 cce_int_mask &= ~((u64)1 << qsfp1_int_smask);
9433 write_csr(dd, CCE_INT_MASK + (8 * (QSFP1_INT / 64)),
9434 cce_int_mask);
9435 } else {
9436 cce_int_mask &= ~((u64)1 << qsfp2_int_smask);
9437 write_csr(dd, CCE_INT_MASK + (8 * (QSFP2_INT / 64)),
9438 cce_int_mask);
77241056
MM		 9439 }
9440
77241056
MM		 9441 qsfp_mask = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N);
9442 /* Clear current status to avoid spurious interrupts */
8ebd4cf1
EH		 9443 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR,
9444 qsfp_mask);
9445 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK,
9446 qsfp_mask);
9447
9448 set_qsfp_int_n(ppd, 0);
77241056
MM		 9449
9450 /* Handle active low nature of INT_N and MODPRST_N pins */
9451 if (qsfp_mod_present(ppd))
9452 qsfp_mask &= ~(u64)QSFP_HFI0_MODPRST_N;
9453 write_csr(dd,
9454 dd->hfi1_id ? ASIC_QSFP2_INVERT : ASIC_QSFP1_INVERT,
9455 qsfp_mask);
77241056
MM		 9456}
9457
bbdeb33d
DL		 9458/*
9459 * Do a one-time initialize of the LCB block.
9460 */
9461static void init_lcb(struct hfi1_devdata *dd)
9462{
a59329d5
DL		 9463 /* simulator does not correctly handle LCB cclk loopback, skip */
9464 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
9465 return;
9466
bbdeb33d
DL		 9467 /* the DC has been reset earlier in the driver load */
9468
9469 /* set LCB for cclk loopback on the port */
9470 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x01);
9471 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0x00);
9472 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0x00);
9473 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110);
9474 write_csr(dd, DC_LCB_CFG_CLK_CNTR, 0x08);
9475 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x02);
9476 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x00);
9477}
9478
77241056
MM		 9479int bringup_serdes(struct hfi1_pportdata *ppd)
9480{
9481 struct hfi1_devdata *dd = ppd->dd;
9482 u64 guid;
9483 int ret;
9484
9485 if (HFI1_CAP_IS_KSET(EXTENDED_PSN))
9486 add_rcvctrl(dd, RCV_CTRL_RCV_EXTENDED_PSN_ENABLE_SMASK);
9487
9488 guid = ppd->guid;
9489 if (!guid) {
9490 if (dd->base_guid)
9491 guid = dd->base_guid + ppd->port - 1;
9492 ppd->guid = guid;
9493 }
9494
77241056
MM		 9495 /* Set linkinit_reason on power up per OPA spec */
9496 ppd->linkinit_reason = OPA_LINKINIT_REASON_LINKUP;
9497
bbdeb33d
DL		 9498 /* one-time init of the LCB */
9499 init_lcb(dd);
9500
77241056
MM		 9501 if (loopback) {
9502 ret = init_loopback(dd);
9503 if (ret < 0)
9504 return ret;
9505 }
9506
9775a991
EH		 9507 get_port_type(ppd);
9508 if (ppd->port_type == PORT_TYPE_QSFP) {
9509 set_qsfp_int_n(ppd, 0);
9510 wait_for_qsfp_init(ppd);
9511 set_qsfp_int_n(ppd, 1);
9512 }
9513
9514 /*
9515 * Tune the SerDes to a ballpark setting for
8ebd4cf1
EH		 9516 * optimal signal and bit error rate
9517 * Needs to be done before starting the link
9518 */
9519 tune_serdes(ppd);
9520
77241056
MM		 9521 return start_link(ppd);
9522}
9523
9524void hfi1_quiet_serdes(struct hfi1_pportdata *ppd)
9525{
9526 struct hfi1_devdata *dd = ppd->dd;
9527
9528 /*
9529 * Shut down the link and keep it down. First turn off that the
9530 * driver wants to allow the link to be up (driver_link_ready).
9531 * Then make sure the link is not automatically restarted
9532 * (link_enabled). Cancel any pending restart. And finally
9533 * go offline.
9534 */
9535 ppd->driver_link_ready = 0;
9536 ppd->link_enabled = 0;
9537
8ebd4cf1
EH		 9538 ppd->offline_disabled_reason =
9539 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_SMA_DISABLED);
77241056 9540 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_SMA_DISABLED, 0,
17fb4f29 9541 OPA_LINKDOWN_REASON_SMA_DISABLED);
77241056
MM		 9542 set_link_state(ppd, HLS_DN_OFFLINE);
9543
9544 /* disable the port */
9545 clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
9546}
9547
9548static inline int init_cpu_counters(struct hfi1_devdata *dd)
9549{
9550 struct hfi1_pportdata *ppd;
9551 int i;
9552
9553 ppd = (struct hfi1_pportdata *)(dd + 1);
9554 for (i = 0; i < dd->num_pports; i++, ppd++) {
4eb06882
DD		 9555 ppd->ibport_data.rvp.rc_acks = NULL;
9556 ppd->ibport_data.rvp.rc_qacks = NULL;
9557 ppd->ibport_data.rvp.rc_acks = alloc_percpu(u64);
9558 ppd->ibport_data.rvp.rc_qacks = alloc_percpu(u64);
9559 ppd->ibport_data.rvp.rc_delayed_comp = alloc_percpu(u64);
9560 if (!ppd->ibport_data.rvp.rc_acks ||
9561 !ppd->ibport_data.rvp.rc_delayed_comp ||
9562 !ppd->ibport_data.rvp.rc_qacks)
77241056
MM		 9563 return -ENOMEM;
9564 }
9565
9566 return 0;
9567}
9568
9569static const char * const pt_names[] = {
9570 "expected",
9571 "eager",
9572 "invalid"
9573};
9574
9575static const char *pt_name(u32 type)
9576{
9577 return type >= ARRAY_SIZE(pt_names) ? "unknown" : pt_names[type];
9578}
9579
9580/*
9581 * index is the index into the receive array
9582 */
9583void hfi1_put_tid(struct hfi1_devdata *dd, u32 index,
9584 u32 type, unsigned long pa, u16 order)
9585{
9586 u64 reg;
9587 void __iomem *base = (dd->rcvarray_wc ? dd->rcvarray_wc :
9588 (dd->kregbase + RCV_ARRAY));
9589
9590 if (!(dd->flags & HFI1_PRESENT))
9591 goto done;
9592
9593 if (type == PT_INVALID) {
9594 pa = 0;
9595 } else if (type > PT_INVALID) {
9596 dd_dev_err(dd,
17fb4f29
JJ		 9597 "unexpected receive array type %u for index %u, not handled\n",
9598 type, index);
77241056
MM		 9599 goto done;
9600 }
9601
9602 hfi1_cdbg(TID, "type %s, index 0x%x, pa 0x%lx, bsize 0x%lx",
9603 pt_name(type), index, pa, (unsigned long)order);
9604
9605#define RT_ADDR_SHIFT 12 /* 4KB kernel address boundary */
9606 reg = RCV_ARRAY_RT_WRITE_ENABLE_SMASK
9607 | (u64)order << RCV_ARRAY_RT_BUF_SIZE_SHIFT
9608 | ((pa >> RT_ADDR_SHIFT) & RCV_ARRAY_RT_ADDR_MASK)
9609 << RCV_ARRAY_RT_ADDR_SHIFT;
9610 writeq(reg, base + (index * 8));
9611
9612 if (type == PT_EAGER)
9613 /*
9614 * Eager entries are written one-by-one so we have to push them
9615 * after we write the entry.
9616 */
9617 flush_wc();
9618done:
9619 return;
9620}
9621
9622void hfi1_clear_tids(struct hfi1_ctxtdata *rcd)
9623{
9624 struct hfi1_devdata *dd = rcd->dd;
9625 u32 i;
9626
9627 /* this could be optimized */
9628 for (i = rcd->eager_base; i < rcd->eager_base +
9629 rcd->egrbufs.alloced; i++)
9630 hfi1_put_tid(dd, i, PT_INVALID, 0, 0);
9631
9632 for (i = rcd->expected_base;
9633 i < rcd->expected_base + rcd->expected_count; i++)
9634 hfi1_put_tid(dd, i, PT_INVALID, 0, 0);
9635}
9636
9637int hfi1_get_base_kinfo(struct hfi1_ctxtdata *rcd,
9638 struct hfi1_ctxt_info *kinfo)
9639{
9640 kinfo->runtime_flags = (HFI1_MISC_GET() << HFI1_CAP_USER_SHIFT) |
9641 HFI1_CAP_UGET(MASK) | HFI1_CAP_KGET(K2U);
9642 return 0;
9643}
9644
9645struct hfi1_message_header *hfi1_get_msgheader(
9646 struct hfi1_devdata *dd, __le32 *rhf_addr)
9647{
9648 u32 offset = rhf_hdrq_offset(rhf_to_cpu(rhf_addr));
9649
9650 return (struct hfi1_message_header *)
9651 (rhf_addr - dd->rhf_offset + offset);
9652}
9653
9654static const char * const ib_cfg_name_strings[] = {
9655 "HFI1_IB_CFG_LIDLMC",
9656 "HFI1_IB_CFG_LWID_DG_ENB",
9657 "HFI1_IB_CFG_LWID_ENB",
9658 "HFI1_IB_CFG_LWID",
9659 "HFI1_IB_CFG_SPD_ENB",
9660 "HFI1_IB_CFG_SPD",
9661 "HFI1_IB_CFG_RXPOL_ENB",
9662 "HFI1_IB_CFG_LREV_ENB",
9663 "HFI1_IB_CFG_LINKLATENCY",
9664 "HFI1_IB_CFG_HRTBT",
9665 "HFI1_IB_CFG_OP_VLS",
9666 "HFI1_IB_CFG_VL_HIGH_CAP",
9667 "HFI1_IB_CFG_VL_LOW_CAP",
9668 "HFI1_IB_CFG_OVERRUN_THRESH",
9669 "HFI1_IB_CFG_PHYERR_THRESH",
9670 "HFI1_IB_CFG_LINKDEFAULT",
9671 "HFI1_IB_CFG_PKEYS",
9672 "HFI1_IB_CFG_MTU",
9673 "HFI1_IB_CFG_LSTATE",
9674 "HFI1_IB_CFG_VL_HIGH_LIMIT",
9675 "HFI1_IB_CFG_PMA_TICKS",
9676 "HFI1_IB_CFG_PORT"
9677};
9678
9679static const char *ib_cfg_name(int which)
9680{
9681 if (which < 0 || which >= ARRAY_SIZE(ib_cfg_name_strings))
9682 return "invalid";
9683 return ib_cfg_name_strings[which];
9684}
9685
9686int hfi1_get_ib_cfg(struct hfi1_pportdata *ppd, int which)
9687{
9688 struct hfi1_devdata *dd = ppd->dd;
9689 int val = 0;
9690
9691 switch (which) {
9692 case HFI1_IB_CFG_LWID_ENB: /* allowed Link-width */
9693 val = ppd->link_width_enabled;
9694 break;
9695 case HFI1_IB_CFG_LWID: /* currently active Link-width */
9696 val = ppd->link_width_active;
9697 break;
9698 case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */
9699 val = ppd->link_speed_enabled;
9700 break;
9701 case HFI1_IB_CFG_SPD: /* current Link speed */
9702 val = ppd->link_speed_active;
9703 break;
9704
9705 case HFI1_IB_CFG_RXPOL_ENB: /* Auto-RX-polarity enable */
9706 case HFI1_IB_CFG_LREV_ENB: /* Auto-Lane-reversal enable */
9707 case HFI1_IB_CFG_LINKLATENCY:
9708 goto unimplemented;
9709
9710 case HFI1_IB_CFG_OP_VLS:
9711 val = ppd->vls_operational;
9712 break;
9713 case HFI1_IB_CFG_VL_HIGH_CAP: /* VL arb high priority table size */
9714 val = VL_ARB_HIGH_PRIO_TABLE_SIZE;
9715 break;
9716 case HFI1_IB_CFG_VL_LOW_CAP: /* VL arb low priority table size */
9717 val = VL_ARB_LOW_PRIO_TABLE_SIZE;
9718 break;
9719 case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
9720 val = ppd->overrun_threshold;
9721 break;
9722 case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
9723 val = ppd->phy_error_threshold;
9724 break;
9725 case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
9726 val = dd->link_default;
9727 break;
9728
9729 case HFI1_IB_CFG_HRTBT: /* Heartbeat off/enable/auto */
9730 case HFI1_IB_CFG_PMA_TICKS:
9731 default:
9732unimplemented:
9733 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
9734 dd_dev_info(
9735 dd,
9736 "%s: which %s: not implemented\n",
9737 __func__,
9738 ib_cfg_name(which));
9739 break;
9740 }
9741
9742 return val;
9743}
9744
9745/*
9746 * The largest MAD packet size.
9747 */
9748#define MAX_MAD_PACKET 2048
9749
9750/*
9751 * Return the maximum header bytes that can go on the _wire_
9752 * for this device. This count includes the ICRC which is
9753 * not part of the packet held in memory but it is appended
9754 * by the HW.
9755 * This is dependent on the device's receive header entry size.
9756 * HFI allows this to be set per-receive context, but the
9757 * driver presently enforces a global value.
9758 */
9759u32 lrh_max_header_bytes(struct hfi1_devdata *dd)
9760{
9761 /*
9762 * The maximum non-payload (MTU) bytes in LRH.PktLen are
9763 * the Receive Header Entry Size minus the PBC (or RHF) size
9764 * plus one DW for the ICRC appended by HW.
9765 *
9766 * dd->rcd[0].rcvhdrqentsize is in DW.
9767 * We use rcd[0] as all context will have the same value. Also,
9768 * the first kernel context would have been allocated by now so
9769 * we are guaranteed a valid value.
9770 */
9771 return (dd->rcd[0]->rcvhdrqentsize - 2/*PBC/RHF*/ + 1/*ICRC*/) << 2;
9772}
9773
9774/*
9775 * Set Send Length
9776 * @ppd - per port data
9777 *
9778 * Set the MTU by limiting how many DWs may be sent. The SendLenCheck*
9779 * registers compare against LRH.PktLen, so use the max bytes included
9780 * in the LRH.
9781 *
9782 * This routine changes all VL values except VL15, which it maintains at
9783 * the same value.
9784 */
9785static void set_send_length(struct hfi1_pportdata *ppd)
9786{
9787 struct hfi1_devdata *dd = ppd->dd;
6cc6ad2e
HC		 9788 u32 max_hb = lrh_max_header_bytes(dd), dcmtu;
9789 u32 maxvlmtu = dd->vld[15].mtu;
77241056
MM		 9790 u64 len1 = 0, len2 = (((dd->vld[15].mtu + max_hb) >> 2)
9791 & SEND_LEN_CHECK1_LEN_VL15_MASK) <<
9792 SEND_LEN_CHECK1_LEN_VL15_SHIFT;
b4ba6633 9793 int i, j;
44306f15 9794 u32 thres;
77241056
MM		 9795
9796 for (i = 0; i < ppd->vls_supported; i++) {
9797 if (dd->vld[i].mtu > maxvlmtu)
9798 maxvlmtu = dd->vld[i].mtu;
9799 if (i <= 3)
9800 len1 |= (((dd->vld[i].mtu + max_hb) >> 2)
9801 & SEND_LEN_CHECK0_LEN_VL0_MASK) <<
9802 ((i % 4) * SEND_LEN_CHECK0_LEN_VL1_SHIFT);
9803 else
9804 len2 |= (((dd->vld[i].mtu + max_hb) >> 2)
9805 & SEND_LEN_CHECK1_LEN_VL4_MASK) <<
9806 ((i % 4) * SEND_LEN_CHECK1_LEN_VL5_SHIFT);
9807 }
9808 write_csr(dd, SEND_LEN_CHECK0, len1);
9809 write_csr(dd, SEND_LEN_CHECK1, len2);
9810 /* adjust kernel credit return thresholds based on new MTUs */
9811 /* all kernel receive contexts have the same hdrqentsize */
9812 for (i = 0; i < ppd->vls_supported; i++) {
44306f15
JX		 9813 thres = min(sc_percent_to_threshold(dd->vld[i].sc, 50),
9814 sc_mtu_to_threshold(dd->vld[i].sc,
9815 dd->vld[i].mtu,
17fb4f29 9816 dd->rcd[0]->rcvhdrqentsize));
b4ba6633
JJ		 9817 for (j = 0; j < INIT_SC_PER_VL; j++)
9818 sc_set_cr_threshold(
9819 pio_select_send_context_vl(dd, j, i),
9820 thres);
44306f15
JX		 9821 }
9822 thres = min(sc_percent_to_threshold(dd->vld[15].sc, 50),
9823 sc_mtu_to_threshold(dd->vld[15].sc,
9824 dd->vld[15].mtu,
9825 dd->rcd[0]->rcvhdrqentsize));
9826 sc_set_cr_threshold(dd->vld[15].sc, thres);
77241056
MM		 9827
9828 /* Adjust maximum MTU for the port in DC */
9829 dcmtu = maxvlmtu == 10240 ? DCC_CFG_PORT_MTU_CAP_10240 :
9830 (ilog2(maxvlmtu >> 8) + 1);
9831 len1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG);
9832 len1 &= ~DCC_CFG_PORT_CONFIG_MTU_CAP_SMASK;
9833 len1 |= ((u64)dcmtu & DCC_CFG_PORT_CONFIG_MTU_CAP_MASK) <<
9834 DCC_CFG_PORT_CONFIG_MTU_CAP_SHIFT;
9835 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG, len1);
9836}
9837
9838static void set_lidlmc(struct hfi1_pportdata *ppd)
9839{
9840 int i;
9841 u64 sreg = 0;
9842 struct hfi1_devdata *dd = ppd->dd;
9843 u32 mask = ~((1U << ppd->lmc) - 1);
9844 u64 c1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG1);
9845
9846 if (dd->hfi1_snoop.mode_flag)
9847 dd_dev_info(dd, "Set lid/lmc while snooping");
9848
9849 c1 &= ~(DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK
9850 | DCC_CFG_PORT_CONFIG1_DLID_MASK_SMASK);
9851 c1 |= ((ppd->lid & DCC_CFG_PORT_CONFIG1_TARGET_DLID_MASK)
8638b77f 9852 << DCC_CFG_PORT_CONFIG1_TARGET_DLID_SHIFT) |
77241056
MM		 9853 ((mask & DCC_CFG_PORT_CONFIG1_DLID_MASK_MASK)
9854 << DCC_CFG_PORT_CONFIG1_DLID_MASK_SHIFT);
9855 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG1, c1);
9856
9857 /*
9858 * Iterate over all the send contexts and set their SLID check
9859 */
9860 sreg = ((mask & SEND_CTXT_CHECK_SLID_MASK_MASK) <<
9861 SEND_CTXT_CHECK_SLID_MASK_SHIFT) |
9862 (((ppd->lid & mask) & SEND_CTXT_CHECK_SLID_VALUE_MASK) <<
9863 SEND_CTXT_CHECK_SLID_VALUE_SHIFT);
9864
9865 for (i = 0; i < dd->chip_send_contexts; i++) {
9866 hfi1_cdbg(LINKVERB, "SendContext[%d].SLID_CHECK = 0x%x",
9867 i, (u32)sreg);
9868 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, sreg);
9869 }
9870
9871 /* Now we have to do the same thing for the sdma engines */
9872 sdma_update_lmc(dd, mask, ppd->lid);
9873}
9874
9875static int wait_phy_linkstate(struct hfi1_devdata *dd, u32 state, u32 msecs)
9876{
9877 unsigned long timeout;
9878 u32 curr_state;
9879
9880 timeout = jiffies + msecs_to_jiffies(msecs);
9881 while (1) {
9882 curr_state = read_physical_state(dd);
9883 if (curr_state == state)
9884 break;
9885 if (time_after(jiffies, timeout)) {
9886 dd_dev_err(dd,
17fb4f29
JJ		 9887 "timeout waiting for phy link state 0x%x, current state is 0x%x\n",
9888 state, curr_state);
77241056
MM		 9889 return -ETIMEDOUT;
9890 }
9891 usleep_range(1950, 2050); /* sleep 2ms-ish */
9892 }
9893
9894 return 0;
9895}
9896
6854c692
DL		 9897static const char *state_completed_string(u32 completed)
9898{
9899 static const char * const state_completed[] = {
9900 "EstablishComm",
9901 "OptimizeEQ",
9902 "VerifyCap"
9903 };
9904
9905 if (completed < ARRAY_SIZE(state_completed))
9906 return state_completed[completed];
9907
9908 return "unknown";
9909}
9910
9911static const char all_lanes_dead_timeout_expired[] =
9912 "All lanes were inactive – was the interconnect media removed?";
9913static const char tx_out_of_policy[] =
9914 "Passing lanes on local port do not meet the local link width policy";
9915static const char no_state_complete[] =
9916 "State timeout occurred before link partner completed the state";
9917static const char * const state_complete_reasons[] = {
9918 [0x00] = "Reason unknown",
9919 [0x01] = "Link was halted by driver, refer to LinkDownReason",
9920 [0x02] = "Link partner reported failure",
9921 [0x10] = "Unable to achieve frame sync on any lane",
9922 [0x11] =
9923 "Unable to find a common bit rate with the link partner",
9924 [0x12] =
9925 "Unable to achieve frame sync on sufficient lanes to meet the local link width policy",
9926 [0x13] =
9927 "Unable to identify preset equalization on sufficient lanes to meet the local link width policy",
9928 [0x14] = no_state_complete,
9929 [0x15] =
9930 "State timeout occurred before link partner identified equalization presets",
9931 [0x16] =
9932 "Link partner completed the EstablishComm state, but the passing lanes do not meet the local link width policy",
9933 [0x17] = tx_out_of_policy,
9934 [0x20] = all_lanes_dead_timeout_expired,
9935 [0x21] =
9936 "Unable to achieve acceptable BER on sufficient lanes to meet the local link width policy",
9937 [0x22] = no_state_complete,
9938 [0x23] =
9939 "Link partner completed the OptimizeEq state, but the passing lanes do not meet the local link width policy",
9940 [0x24] = tx_out_of_policy,
9941 [0x30] = all_lanes_dead_timeout_expired,
9942 [0x31] =
9943 "State timeout occurred waiting for host to process received frames",
9944 [0x32] = no_state_complete,
9945 [0x33] =
9946 "Link partner completed the VerifyCap state, but the passing lanes do not meet the local link width policy",
9947 [0x34] = tx_out_of_policy,
9948};
9949
9950static const char *state_complete_reason_code_string(struct hfi1_pportdata *ppd,
9951 u32 code)
9952{
9953 const char *str = NULL;
9954
9955 if (code < ARRAY_SIZE(state_complete_reasons))
9956 str = state_complete_reasons[code];
9957
9958 if (str)
9959 return str;
9960 return "Reserved";
9961}
9962
9963/* describe the given last state complete frame */
9964static void decode_state_complete(struct hfi1_pportdata *ppd, u32 frame,
9965 const char *prefix)
9966{
9967 struct hfi1_devdata *dd = ppd->dd;
9968 u32 success;
9969 u32 state;
9970 u32 reason;
9971 u32 lanes;
9972
9973 /*
9974 * Decode frame:
9975 * [ 0: 0] - success
9976 * [ 3: 1] - state
9977 * [ 7: 4] - next state timeout
9978 * [15: 8] - reason code
9979 * [31:16] - lanes
9980 */
9981 success = frame & 0x1;
9982 state = (frame >> 1) & 0x7;
9983 reason = (frame >> 8) & 0xff;
9984 lanes = (frame >> 16) & 0xffff;
9985
9986 dd_dev_err(dd, "Last %s LNI state complete frame 0x%08x:\n",
9987 prefix, frame);
9988 dd_dev_err(dd, " last reported state state: %s (0x%x)\n",
9989 state_completed_string(state), state);
9990 dd_dev_err(dd, " state successfully completed: %s\n",
9991 success ? "yes" : "no");
9992 dd_dev_err(dd, " fail reason 0x%x: %s\n",
9993 reason, state_complete_reason_code_string(ppd, reason));
9994 dd_dev_err(dd, " passing lane mask: 0x%x", lanes);
9995}
9996
9997/*
9998 * Read the last state complete frames and explain them. This routine
9999 * expects to be called if the link went down during link negotiation
10000 * and initialization (LNI). That is, anywhere between polling and link up.
10001 */
10002static void check_lni_states(struct hfi1_pportdata *ppd)
10003{
10004 u32 last_local_state;
10005 u32 last_remote_state;
10006
10007 read_last_local_state(ppd->dd, &last_local_state);
10008 read_last_remote_state(ppd->dd, &last_remote_state);
10009
10010 /*
10011 * Don't report anything if there is nothing to report. A value of
10012 * 0 means the link was taken down while polling and there was no
10013 * training in-process.
10014 */
10015 if (last_local_state == 0 && last_remote_state == 0)
10016 return;
10017
10018 decode_state_complete(ppd, last_local_state, "transmitted");
10019 decode_state_complete(ppd, last_remote_state, "received");
10020}
10021
77241056
MM		 10022/*
10023 * Helper for set_link_state(). Do not call except from that routine.
10024 * Expects ppd->hls_mutex to be held.
10025 *
10026 * @rem_reason value to be sent to the neighbor
10027 *
10028 * LinkDownReasons only set if transition succeeds.
10029 */
10030static int goto_offline(struct hfi1_pportdata *ppd, u8 rem_reason)
10031{
10032 struct hfi1_devdata *dd = ppd->dd;
10033 u32 pstate, previous_state;
77241056
MM		 10034 int ret;
10035 int do_transition;
10036 int do_wait;
10037
10038 previous_state = ppd->host_link_state;
10039 ppd->host_link_state = HLS_GOING_OFFLINE;
10040 pstate = read_physical_state(dd);
10041 if (pstate == PLS_OFFLINE) {
10042 do_transition = 0; /* in right state */
10043 do_wait = 0; /* ...no need to wait */
10044 } else if ((pstate & 0xff) == PLS_OFFLINE) {
10045 do_transition = 0; /* in an offline transient state */
10046 do_wait = 1; /* ...wait for it to settle */
10047 } else {
10048 do_transition = 1; /* need to move to offline */
10049 do_wait = 1; /* ...will need to wait */
10050 }
10051
10052 if (do_transition) {
10053 ret = set_physical_link_state(dd,
bf640096 10054 (rem_reason << 8) | PLS_OFFLINE);
77241056
MM		 10055
10056 if (ret != HCMD_SUCCESS) {
10057 dd_dev_err(dd,
17fb4f29
JJ		 10058 "Failed to transition to Offline link state, return %d\n",
10059 ret);
77241056
MM		 10060 return -EINVAL;
10061 }
a9c05e35
BM		 10062 if (ppd->offline_disabled_reason ==
10063 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE))
77241056 10064 ppd->offline_disabled_reason =
a9c05e35 10065 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT);
77241056
MM		 10066 }
10067
10068 if (do_wait) {
10069 /* it can take a while for the link to go down */
dc060245 10070 ret = wait_phy_linkstate(dd, PLS_OFFLINE, 10000);
77241056
MM		 10071 if (ret < 0)
10072 return ret;
10073 }
10074
10075 /* make sure the logical state is also down */
10076 wait_logical_linkstate(ppd, IB_PORT_DOWN, 1000);
10077
10078 /*
10079 * Now in charge of LCB - must be after the physical state is
10080 * offline.quiet and before host_link_state is changed.
10081 */
10082 set_host_lcb_access(dd);
10083 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
10084 ppd->host_link_state = HLS_LINK_COOLDOWN; /* LCB access allowed */
10085
8ebd4cf1
EH		 10086 if (ppd->port_type == PORT_TYPE_QSFP &&
10087 ppd->qsfp_info.limiting_active &&
10088 qsfp_mod_present(ppd)) {
765a6fac
DL		 10089 int ret;
10090
10091 ret = acquire_chip_resource(dd, qsfp_resource(dd), QSFP_WAIT);
10092 if (ret == 0) {
10093 set_qsfp_tx(ppd, 0);
10094 release_chip_resource(dd, qsfp_resource(dd));
10095 } else {
10096 /* not fatal, but should warn */
10097 dd_dev_err(dd,
10098 "Unable to acquire lock to turn off QSFP TX\n");
10099 }
8ebd4cf1
EH		 10100 }
10101
77241056
MM		 10102 /*
10103 * The LNI has a mandatory wait time after the physical state
10104 * moves to Offline.Quiet. The wait time may be different
10105 * depending on how the link went down. The 8051 firmware
10106 * will observe the needed wait time and only move to ready
10107 * when that is completed. The largest of the quiet timeouts
05087f3b
DL		 10108 * is 6s, so wait that long and then at least 0.5s more for
10109 * other transitions, and another 0.5s for a buffer.
77241056 10110 */
05087f3b 10111 ret = wait_fm_ready(dd, 7000);
77241056
MM		 10112 if (ret) {
10113 dd_dev_err(dd,
17fb4f29 10114 "After going offline, timed out waiting for the 8051 to become ready to accept host requests\n");
77241056
MM		 10115 /* state is really offline, so make it so */
10116 ppd->host_link_state = HLS_DN_OFFLINE;
10117 return ret;
10118 }
10119
10120 /*
10121 * The state is now offline and the 8051 is ready to accept host
10122 * requests.
10123 * - change our state
10124 * - notify others if we were previously in a linkup state
10125 */
10126 ppd->host_link_state = HLS_DN_OFFLINE;
10127 if (previous_state & HLS_UP) {
10128 /* went down while link was up */
10129 handle_linkup_change(dd, 0);
10130 } else if (previous_state
10131 & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) {
10132 /* went down while attempting link up */
6854c692 10133 check_lni_states(ppd);
77241056
MM		 10134 }
10135
10136 /* the active link width (downgrade) is 0 on link down */
10137 ppd->link_width_active = 0;
10138 ppd->link_width_downgrade_tx_active = 0;
10139 ppd->link_width_downgrade_rx_active = 0;
10140 ppd->current_egress_rate = 0;
10141 return 0;
10142}
10143
10144/* return the link state name */
10145static const char *link_state_name(u32 state)
10146{
10147 const char *name;
10148 int n = ilog2(state);
10149 static const char * const names[] = {
10150 [__HLS_UP_INIT_BP] = "INIT",
10151 [__HLS_UP_ARMED_BP] = "ARMED",
10152 [__HLS_UP_ACTIVE_BP] = "ACTIVE",
10153 [__HLS_DN_DOWNDEF_BP] = "DOWNDEF",
10154 [__HLS_DN_POLL_BP] = "POLL",
10155 [__HLS_DN_DISABLE_BP] = "DISABLE",
10156 [__HLS_DN_OFFLINE_BP] = "OFFLINE",
10157 [__HLS_VERIFY_CAP_BP] = "VERIFY_CAP",
10158 [__HLS_GOING_UP_BP] = "GOING_UP",
10159 [__HLS_GOING_OFFLINE_BP] = "GOING_OFFLINE",
10160 [__HLS_LINK_COOLDOWN_BP] = "LINK_COOLDOWN"
10161 };
10162
10163 name = n < ARRAY_SIZE(names) ? names[n] : NULL;
10164 return name ? name : "unknown";
10165}
10166
10167/* return the link state reason name */
10168static const char *link_state_reason_name(struct hfi1_pportdata *ppd, u32 state)
10169{
10170 if (state == HLS_UP_INIT) {
10171 switch (ppd->linkinit_reason) {
10172 case OPA_LINKINIT_REASON_LINKUP:
10173 return "(LINKUP)";
10174 case OPA_LINKINIT_REASON_FLAPPING:
10175 return "(FLAPPING)";
10176 case OPA_LINKINIT_OUTSIDE_POLICY:
10177 return "(OUTSIDE_POLICY)";
10178 case OPA_LINKINIT_QUARANTINED:
10179 return "(QUARANTINED)";
10180 case OPA_LINKINIT_INSUFIC_CAPABILITY:
10181 return "(INSUFIC_CAPABILITY)";
10182 default:
10183 break;
10184 }
10185 }
10186 return "";
10187}
10188
10189/*
10190 * driver_physical_state - convert the driver's notion of a port's
10191 * state (an HLS_*) into a physical state (a {IB,OPA}_PORTPHYSSTATE_*).
10192 * Return -1 (converted to a u32) to indicate error.
10193 */
10194u32 driver_physical_state(struct hfi1_pportdata *ppd)
10195{
10196 switch (ppd->host_link_state) {
10197 case HLS_UP_INIT:
10198 case HLS_UP_ARMED:
10199 case HLS_UP_ACTIVE:
10200 return IB_PORTPHYSSTATE_LINKUP;
10201 case HLS_DN_POLL:
10202 return IB_PORTPHYSSTATE_POLLING;
10203 case HLS_DN_DISABLE:
10204 return IB_PORTPHYSSTATE_DISABLED;
10205 case HLS_DN_OFFLINE:
10206 return OPA_PORTPHYSSTATE_OFFLINE;
10207 case HLS_VERIFY_CAP:
10208 return IB_PORTPHYSSTATE_POLLING;
10209 case HLS_GOING_UP:
10210 return IB_PORTPHYSSTATE_POLLING;
10211 case HLS_GOING_OFFLINE:
10212 return OPA_PORTPHYSSTATE_OFFLINE;
10213 case HLS_LINK_COOLDOWN:
10214 return OPA_PORTPHYSSTATE_OFFLINE;
10215 case HLS_DN_DOWNDEF:
10216 default:
10217 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n",
10218 ppd->host_link_state);
10219 return -1;
10220 }
10221}
10222
10223/*
10224 * driver_logical_state - convert the driver's notion of a port's
10225 * state (an HLS_*) into a logical state (a IB_PORT_*). Return -1
10226 * (converted to a u32) to indicate error.
10227 */
10228u32 driver_logical_state(struct hfi1_pportdata *ppd)
10229{
0c7f77af 10230 if (ppd->host_link_state && (ppd->host_link_state & HLS_DOWN))
77241056
MM		 10231 return IB_PORT_DOWN;
10232
10233 switch (ppd->host_link_state & HLS_UP) {
10234 case HLS_UP_INIT:
10235 return IB_PORT_INIT;
10236 case HLS_UP_ARMED:
10237 return IB_PORT_ARMED;
10238 case HLS_UP_ACTIVE:
10239 return IB_PORT_ACTIVE;
10240 default:
10241 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n",
10242 ppd->host_link_state);
10243 return -1;
10244 }
10245}
10246
10247void set_link_down_reason(struct hfi1_pportdata *ppd, u8 lcl_reason,
10248 u8 neigh_reason, u8 rem_reason)
10249{
10250 if (ppd->local_link_down_reason.latest == 0 &&
10251 ppd->neigh_link_down_reason.latest == 0) {
10252 ppd->local_link_down_reason.latest = lcl_reason;
10253 ppd->neigh_link_down_reason.latest = neigh_reason;
10254 ppd->remote_link_down_reason = rem_reason;
10255 }
10256}
10257
10258/*
10259 * Change the physical and/or logical link state.
10260 *
10261 * Do not call this routine while inside an interrupt. It contains
10262 * calls to routines that can take multiple seconds to finish.
10263 *
10264 * Returns 0 on success, -errno on failure.
10265 */
10266int set_link_state(struct hfi1_pportdata *ppd, u32 state)
10267{
10268 struct hfi1_devdata *dd = ppd->dd;
10269 struct ib_event event = {.device = NULL};
10270 int ret1, ret = 0;
77241056
MM		 10271 int orig_new_state, poll_bounce;
10272
10273 mutex_lock(&ppd->hls_lock);
10274
10275 orig_new_state = state;
10276 if (state == HLS_DN_DOWNDEF)
10277 state = dd->link_default;
10278
10279 /* interpret poll -> poll as a link bounce */
d0d236ea
JJ		 10280 poll_bounce = ppd->host_link_state == HLS_DN_POLL &&
10281 state == HLS_DN_POLL;
77241056
MM		 10282
10283 dd_dev_info(dd, "%s: current %s, new %s %s%s\n", __func__,
17fb4f29
JJ		 10284 link_state_name(ppd->host_link_state),
10285 link_state_name(orig_new_state),
10286 poll_bounce ? "(bounce) " : "",
10287 link_state_reason_name(ppd, state));
77241056 10288
77241056
MM		 10289 /*
10290 * If we're going to a (HLS_*) link state that implies the logical
10291 * link state is neither of (IB_PORT_ARMED, IB_PORT_ACTIVE), then
10292 * reset is_sm_config_started to 0.
10293 */
10294 if (!(state & (HLS_UP_ARMED | HLS_UP_ACTIVE)))
10295 ppd->is_sm_config_started = 0;
10296
10297 /*
10298 * Do nothing if the states match. Let a poll to poll link bounce
10299 * go through.
10300 */
10301 if (ppd->host_link_state == state && !poll_bounce)
10302 goto done;
10303
10304 switch (state) {
10305 case HLS_UP_INIT:
d0d236ea
JJ		 10306 if (ppd->host_link_state == HLS_DN_POLL &&
10307 (quick_linkup || dd->icode == ICODE_FUNCTIONAL_SIMULATOR)) {
77241056
MM		 10308 /*
10309 * Quick link up jumps from polling to here.
10310 *
10311 * Whether in normal or loopback mode, the
10312 * simulator jumps from polling to link up.
10313 * Accept that here.
10314 */
17fb4f29 10315 /* OK */
77241056
MM		 10316 } else if (ppd->host_link_state != HLS_GOING_UP) {
10317 goto unexpected;
10318 }
10319
10320 ppd->host_link_state = HLS_UP_INIT;
10321 ret = wait_logical_linkstate(ppd, IB_PORT_INIT, 1000);
10322 if (ret) {
10323 /* logical state didn't change, stay at going_up */
10324 ppd->host_link_state = HLS_GOING_UP;
10325 dd_dev_err(dd,
17fb4f29
JJ		 10326 "%s: logical state did not change to INIT\n",
10327 __func__);
77241056
MM		 10328 } else {
10329 /* clear old transient LINKINIT_REASON code */
10330 if (ppd->linkinit_reason >= OPA_LINKINIT_REASON_CLEAR)
10331 ppd->linkinit_reason =
10332 OPA_LINKINIT_REASON_LINKUP;
10333
10334 /* enable the port */
10335 add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
10336
10337 handle_linkup_change(dd, 1);
10338 }
10339 break;
10340 case HLS_UP_ARMED:
10341 if (ppd->host_link_state != HLS_UP_INIT)
10342 goto unexpected;
10343
10344 ppd->host_link_state = HLS_UP_ARMED;
10345 set_logical_state(dd, LSTATE_ARMED);
10346 ret = wait_logical_linkstate(ppd, IB_PORT_ARMED, 1000);
10347 if (ret) {
10348 /* logical state didn't change, stay at init */
10349 ppd->host_link_state = HLS_UP_INIT;
10350 dd_dev_err(dd,
17fb4f29
JJ		 10351 "%s: logical state did not change to ARMED\n",
10352 __func__);
77241056
MM		 10353 }
10354 /*
10355 * The simulator does not currently implement SMA messages,
10356 * so neighbor_normal is not set. Set it here when we first
10357 * move to Armed.
10358 */
10359 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
10360 ppd->neighbor_normal = 1;
10361 break;
10362 case HLS_UP_ACTIVE:
10363 if (ppd->host_link_state != HLS_UP_ARMED)
10364 goto unexpected;
10365
10366 ppd->host_link_state = HLS_UP_ACTIVE;
10367 set_logical_state(dd, LSTATE_ACTIVE);
10368 ret = wait_logical_linkstate(ppd, IB_PORT_ACTIVE, 1000);
10369 if (ret) {
10370 /* logical state didn't change, stay at armed */
10371 ppd->host_link_state = HLS_UP_ARMED;
10372 dd_dev_err(dd,
17fb4f29
JJ		 10373 "%s: logical state did not change to ACTIVE\n",
10374 __func__);
77241056 10375 } else {
77241056
MM		 10376 /* tell all engines to go running */
10377 sdma_all_running(dd);
10378
10379 /* Signal the IB layer that the port has went active */
ec3f2c12 10380 event.device = &dd->verbs_dev.rdi.ibdev;
77241056
MM		 10381 event.element.port_num = ppd->port;
10382 event.event = IB_EVENT_PORT_ACTIVE;
10383 }
10384 break;
10385 case HLS_DN_POLL:
10386 if ((ppd->host_link_state == HLS_DN_DISABLE ||
10387 ppd->host_link_state == HLS_DN_OFFLINE) &&
10388 dd->dc_shutdown)
10389 dc_start(dd);
10390 /* Hand LED control to the DC */
10391 write_csr(dd, DCC_CFG_LED_CNTRL, 0);
10392
10393 if (ppd->host_link_state != HLS_DN_OFFLINE) {
10394 u8 tmp = ppd->link_enabled;
10395
10396 ret = goto_offline(ppd, ppd->remote_link_down_reason);
10397 if (ret) {
10398 ppd->link_enabled = tmp;
10399 break;
10400 }
10401 ppd->remote_link_down_reason = 0;
10402
10403 if (ppd->driver_link_ready)
10404 ppd->link_enabled = 1;
10405 }
10406
fb9036dd 10407 set_all_slowpath(ppd->dd);
77241056
MM		 10408 ret = set_local_link_attributes(ppd);
10409 if (ret)
10410 break;
10411
10412 ppd->port_error_action = 0;
10413 ppd->host_link_state = HLS_DN_POLL;
10414
10415 if (quick_linkup) {
10416 /* quick linkup does not go into polling */
10417 ret = do_quick_linkup(dd);
10418 } else {
10419 ret1 = set_physical_link_state(dd, PLS_POLLING);
10420 if (ret1 != HCMD_SUCCESS) {
10421 dd_dev_err(dd,
17fb4f29
JJ		 10422 "Failed to transition to Polling link state, return 0x%x\n",
10423 ret1);
77241056
MM		 10424 ret = -EINVAL;
10425 }
10426 }
a9c05e35
BM		 10427 ppd->offline_disabled_reason =
10428 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE);
77241056
MM		 10429 /*
10430 * If an error occurred above, go back to offline. The
10431 * caller may reschedule another attempt.
10432 */
10433 if (ret)
10434 goto_offline(ppd, 0);
10435 break;
10436 case HLS_DN_DISABLE:
10437 /* link is disabled */
10438 ppd->link_enabled = 0;
10439
10440 /* allow any state to transition to disabled */
10441
10442 /* must transition to offline first */
10443 if (ppd->host_link_state != HLS_DN_OFFLINE) {
10444 ret = goto_offline(ppd, ppd->remote_link_down_reason);
10445 if (ret)
10446 break;
10447 ppd->remote_link_down_reason = 0;
10448 }
10449
10450 ret1 = set_physical_link_state(dd, PLS_DISABLED);
10451 if (ret1 != HCMD_SUCCESS) {
10452 dd_dev_err(dd,
17fb4f29
JJ		 10453 "Failed to transition to Disabled link state, return 0x%x\n",
10454 ret1);
77241056
MM		 10455 ret = -EINVAL;
10456 break;
10457 }
10458 ppd->host_link_state = HLS_DN_DISABLE;
10459 dc_shutdown(dd);
10460 break;
10461 case HLS_DN_OFFLINE:
10462 if (ppd->host_link_state == HLS_DN_DISABLE)
10463 dc_start(dd);
10464
10465 /* allow any state to transition to offline */
10466 ret = goto_offline(ppd, ppd->remote_link_down_reason);
10467 if (!ret)
10468 ppd->remote_link_down_reason = 0;
10469 break;
10470 case HLS_VERIFY_CAP:
10471 if (ppd->host_link_state != HLS_DN_POLL)
10472 goto unexpected;
10473 ppd->host_link_state = HLS_VERIFY_CAP;
10474 break;
10475 case HLS_GOING_UP:
10476 if (ppd->host_link_state != HLS_VERIFY_CAP)
10477 goto unexpected;
10478
10479 ret1 = set_physical_link_state(dd, PLS_LINKUP);
10480 if (ret1 != HCMD_SUCCESS) {
10481 dd_dev_err(dd,
17fb4f29
JJ		 10482 "Failed to transition to link up state, return 0x%x\n",
10483 ret1);
77241056
MM		 10484 ret = -EINVAL;
10485 break;
10486 }
10487 ppd->host_link_state = HLS_GOING_UP;
10488 break;
10489
10490 case HLS_GOING_OFFLINE: /* transient within goto_offline() */
10491 case HLS_LINK_COOLDOWN: /* transient within goto_offline() */
10492 default:
10493 dd_dev_info(dd, "%s: state 0x%x: not supported\n",
17fb4f29 10494 __func__, state);
77241056
MM		 10495 ret = -EINVAL;
10496 break;
10497 }
10498
77241056
MM		 10499 goto done;
10500
10501unexpected:
10502 dd_dev_err(dd, "%s: unexpected state transition from %s to %s\n",
17fb4f29
JJ		 10503 __func__, link_state_name(ppd->host_link_state),
10504 link_state_name(state));
77241056
MM		 10505 ret = -EINVAL;
10506
10507done:
10508 mutex_unlock(&ppd->hls_lock);
10509
10510 if (event.device)
10511 ib_dispatch_event(&event);
10512
10513 return ret;
10514}
10515
10516int hfi1_set_ib_cfg(struct hfi1_pportdata *ppd, int which, u32 val)
10517{
10518 u64 reg;
10519 int ret = 0;
10520
10521 switch (which) {
10522 case HFI1_IB_CFG_LIDLMC:
10523 set_lidlmc(ppd);
10524 break;
10525 case HFI1_IB_CFG_VL_HIGH_LIMIT:
10526 /*
10527 * The VL Arbitrator high limit is sent in units of 4k
10528 * bytes, while HFI stores it in units of 64 bytes.
10529 */
8638b77f 10530 val *= 4096 / 64;
77241056
MM		 10531 reg = ((u64)val & SEND_HIGH_PRIORITY_LIMIT_LIMIT_MASK)
10532 << SEND_HIGH_PRIORITY_LIMIT_LIMIT_SHIFT;
10533 write_csr(ppd->dd, SEND_HIGH_PRIORITY_LIMIT, reg);
10534 break;
10535 case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
10536 /* HFI only supports POLL as the default link down state */
10537 if (val != HLS_DN_POLL)
10538 ret = -EINVAL;
10539 break;
10540 case HFI1_IB_CFG_OP_VLS:
10541 if (ppd->vls_operational != val) {
10542 ppd->vls_operational = val;
10543 if (!ppd->port)
10544 ret = -EINVAL;
77241056
MM		 10545 }
10546 break;
10547 /*
10548 * For link width, link width downgrade, and speed enable, always AND
10549 * the setting with what is actually supported. This has two benefits.
10550 * First, enabled can't have unsupported values, no matter what the
10551 * SM or FM might want. Second, the ALL_SUPPORTED wildcards that mean
10552 * "fill in with your supported value" have all the bits in the
10553 * field set, so simply ANDing with supported has the desired result.
10554 */
10555 case HFI1_IB_CFG_LWID_ENB: /* set allowed Link-width */
10556 ppd->link_width_enabled = val & ppd->link_width_supported;
10557 break;
10558 case HFI1_IB_CFG_LWID_DG_ENB: /* set allowed link width downgrade */
10559 ppd->link_width_downgrade_enabled =
10560 val & ppd->link_width_downgrade_supported;
10561 break;
10562 case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */
10563 ppd->link_speed_enabled = val & ppd->link_speed_supported;
10564 break;
10565 case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
10566 /*
10567 * HFI does not follow IB specs, save this value
10568 * so we can report it, if asked.
10569 */
10570 ppd->overrun_threshold = val;
10571 break;
10572 case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
10573 /*
10574 * HFI does not follow IB specs, save this value
10575 * so we can report it, if asked.
10576 */
10577 ppd->phy_error_threshold = val;
10578 break;
10579
10580 case HFI1_IB_CFG_MTU:
10581 set_send_length(ppd);
10582 break;
10583
10584 case HFI1_IB_CFG_PKEYS:
10585 if (HFI1_CAP_IS_KSET(PKEY_CHECK))
10586 set_partition_keys(ppd);
10587 break;
10588
10589 default:
10590 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
10591 dd_dev_info(ppd->dd,
17fb4f29
JJ		 10592 "%s: which %s, val 0x%x: not implemented\n",
10593 __func__, ib_cfg_name(which), val);
77241056
MM		 10594 break;
10595 }
10596 return ret;
10597}
10598
10599/* begin functions related to vl arbitration table caching */
10600static void init_vl_arb_caches(struct hfi1_pportdata *ppd)
10601{
10602 int i;
10603
10604 BUILD_BUG_ON(VL_ARB_TABLE_SIZE !=
10605 VL_ARB_LOW_PRIO_TABLE_SIZE);
10606 BUILD_BUG_ON(VL_ARB_TABLE_SIZE !=
10607 VL_ARB_HIGH_PRIO_TABLE_SIZE);
10608
10609 /*
10610 * Note that we always return values directly from the
10611 * 'vl_arb_cache' (and do no CSR reads) in response to a
10612 * 'Get(VLArbTable)'. This is obviously correct after a
10613 * 'Set(VLArbTable)', since the cache will then be up to
10614 * date. But it's also correct prior to any 'Set(VLArbTable)'
10615 * since then both the cache, and the relevant h/w registers
10616 * will be zeroed.
10617 */
10618
10619 for (i = 0; i < MAX_PRIO_TABLE; i++)
10620 spin_lock_init(&ppd->vl_arb_cache[i].lock);
10621}
10622
10623/*
10624 * vl_arb_lock_cache
10625 *
10626 * All other vl_arb_* functions should be called only after locking
10627 * the cache.
10628 */
10629static inline struct vl_arb_cache *
10630vl_arb_lock_cache(struct hfi1_pportdata *ppd, int idx)
10631{
10632 if (idx != LO_PRIO_TABLE && idx != HI_PRIO_TABLE)
10633 return NULL;
10634 spin_lock(&ppd->vl_arb_cache[idx].lock);
10635 return &ppd->vl_arb_cache[idx];
10636}
10637
10638static inline void vl_arb_unlock_cache(struct hfi1_pportdata *ppd, int idx)
10639{
10640 spin_unlock(&ppd->vl_arb_cache[idx].lock);
10641}
10642
10643static void vl_arb_get_cache(struct vl_arb_cache *cache,
10644 struct ib_vl_weight_elem *vl)
10645{
10646 memcpy(vl, cache->table, VL_ARB_TABLE_SIZE * sizeof(*vl));
10647}
10648
10649static void vl_arb_set_cache(struct vl_arb_cache *cache,
10650 struct ib_vl_weight_elem *vl)
10651{
10652 memcpy(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl));
10653}
10654
10655static int vl_arb_match_cache(struct vl_arb_cache *cache,
10656 struct ib_vl_weight_elem *vl)
10657{
10658 return !memcmp(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl));
10659}
f4d507cd 10660
77241056
MM		 10661/* end functions related to vl arbitration table caching */
10662
10663static int set_vl_weights(struct hfi1_pportdata *ppd, u32 target,
10664 u32 size, struct ib_vl_weight_elem *vl)
10665{
10666 struct hfi1_devdata *dd = ppd->dd;
10667 u64 reg;
10668 unsigned int i, is_up = 0;
10669 int drain, ret = 0;
10670
10671 mutex_lock(&ppd->hls_lock);
10672
10673 if (ppd->host_link_state & HLS_UP)
10674 is_up = 1;
10675
10676 drain = !is_ax(dd) && is_up;
10677
10678 if (drain)
10679 /*
10680 * Before adjusting VL arbitration weights, empty per-VL
10681 * FIFOs, otherwise a packet whose VL weight is being
10682 * set to 0 could get stuck in a FIFO with no chance to
10683 * egress.
10684 */
10685 ret = stop_drain_data_vls(dd);
10686
10687 if (ret) {
10688 dd_dev_err(
10689 dd,
10690 "%s: cannot stop/drain VLs - refusing to change VL arbitration weights\n",
10691 __func__);
10692 goto err;
10693 }
10694
10695 for (i = 0; i < size; i++, vl++) {
10696 /*
10697 * NOTE: The low priority shift and mask are used here, but
10698 * they are the same for both the low and high registers.
10699 */
10700 reg = (((u64)vl->vl & SEND_LOW_PRIORITY_LIST_VL_MASK)
10701 << SEND_LOW_PRIORITY_LIST_VL_SHIFT)
10702 | (((u64)vl->weight
10703 & SEND_LOW_PRIORITY_LIST_WEIGHT_MASK)
10704 << SEND_LOW_PRIORITY_LIST_WEIGHT_SHIFT);
10705 write_csr(dd, target + (i * 8), reg);
10706 }
10707 pio_send_control(dd, PSC_GLOBAL_VLARB_ENABLE);
10708
10709 if (drain)
10710 open_fill_data_vls(dd); /* reopen all VLs */
10711
10712err:
10713 mutex_unlock(&ppd->hls_lock);
10714
10715 return ret;
10716}
10717
10718/*
10719 * Read one credit merge VL register.
10720 */
10721static void read_one_cm_vl(struct hfi1_devdata *dd, u32 csr,
10722 struct vl_limit *vll)
10723{
10724 u64 reg = read_csr(dd, csr);
10725
10726 vll->dedicated = cpu_to_be16(
10727 (reg >> SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT)
10728 & SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_MASK);
10729 vll->shared = cpu_to_be16(
10730 (reg >> SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT)
10731 & SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_MASK);
10732}
10733
10734/*
10735 * Read the current credit merge limits.
10736 */
10737static int get_buffer_control(struct hfi1_devdata *dd,
10738 struct buffer_control *bc, u16 *overall_limit)
10739{
10740 u64 reg;
10741 int i;
10742
10743 /* not all entries are filled in */
10744 memset(bc, 0, sizeof(*bc));
10745
10746 /* OPA and HFI have a 1-1 mapping */
10747 for (i = 0; i < TXE_NUM_DATA_VL; i++)
8638b77f 10748 read_one_cm_vl(dd, SEND_CM_CREDIT_VL + (8 * i), &bc->vl[i]);
77241056
MM		 10749
10750 /* NOTE: assumes that VL* and VL15 CSRs are bit-wise identical */
10751 read_one_cm_vl(dd, SEND_CM_CREDIT_VL15, &bc->vl[15]);
10752
10753 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
10754 bc->overall_shared_limit = cpu_to_be16(
10755 (reg >> SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT)
10756 & SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_MASK);
10757 if (overall_limit)
10758 *overall_limit = (reg
10759 >> SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT)
10760 & SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_MASK;
10761 return sizeof(struct buffer_control);
10762}
10763
10764static int get_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp)
10765{
10766 u64 reg;
10767 int i;
10768
10769 /* each register contains 16 SC->VLnt mappings, 4 bits each */
10770 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_15_0);
10771 for (i = 0; i < sizeof(u64); i++) {
10772 u8 byte = *(((u8 *)&reg) + i);
10773
10774 dp->vlnt[2 * i] = byte & 0xf;
10775 dp->vlnt[(2 * i) + 1] = (byte & 0xf0) >> 4;
10776 }
10777
10778 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_31_16);
10779 for (i = 0; i < sizeof(u64); i++) {
10780 u8 byte = *(((u8 *)&reg) + i);
10781
10782 dp->vlnt[16 + (2 * i)] = byte & 0xf;
10783 dp->vlnt[16 + (2 * i) + 1] = (byte & 0xf0) >> 4;
10784 }
10785 return sizeof(struct sc2vlnt);
10786}
10787
10788static void get_vlarb_preempt(struct hfi1_devdata *dd, u32 nelems,
10789 struct ib_vl_weight_elem *vl)
10790{
10791 unsigned int i;
10792
10793 for (i = 0; i < nelems; i++, vl++) {
10794 vl->vl = 0xf;
10795 vl->weight = 0;
10796 }
10797}
10798
10799static void set_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp)
10800{
10801 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0,
17fb4f29
JJ		 10802 DC_SC_VL_VAL(15_0,
10803 0, dp->vlnt[0] & 0xf,
10804 1, dp->vlnt[1] & 0xf,
10805 2, dp->vlnt[2] & 0xf,
10806 3, dp->vlnt[3] & 0xf,
10807 4, dp->vlnt[4] & 0xf,
10808 5, dp->vlnt[5] & 0xf,
10809 6, dp->vlnt[6] & 0xf,
10810 7, dp->vlnt[7] & 0xf,
10811 8, dp->vlnt[8] & 0xf,
10812 9, dp->vlnt[9] & 0xf,
10813 10, dp->vlnt[10] & 0xf,
10814 11, dp->vlnt[11] & 0xf,
10815 12, dp->vlnt[12] & 0xf,
10816 13, dp->vlnt[13] & 0xf,
10817 14, dp->vlnt[14] & 0xf,
10818 15, dp->vlnt[15] & 0xf));
77241056 10819 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16,
17fb4f29
JJ		 10820 DC_SC_VL_VAL(31_16,
10821 16, dp->vlnt[16] & 0xf,
10822 17, dp->vlnt[17] & 0xf,
10823 18, dp->vlnt[18] & 0xf,
10824 19, dp->vlnt[19] & 0xf,
10825 20, dp->vlnt[20] & 0xf,
10826 21, dp->vlnt[21] & 0xf,
10827 22, dp->vlnt[22] & 0xf,
10828 23, dp->vlnt[23] & 0xf,
10829 24, dp->vlnt[24] & 0xf,
10830 25, dp->vlnt[25] & 0xf,
10831 26, dp->vlnt[26] & 0xf,
10832 27, dp->vlnt[27] & 0xf,
10833 28, dp->vlnt[28] & 0xf,
10834 29, dp->vlnt[29] & 0xf,
10835 30, dp->vlnt[30] & 0xf,
10836 31, dp->vlnt[31] & 0xf));
77241056
MM		 10837}
10838
10839static void nonzero_msg(struct hfi1_devdata *dd, int idx, const char *what,
10840 u16 limit)
10841{
10842 if (limit != 0)
10843 dd_dev_info(dd, "Invalid %s limit %d on VL %d, ignoring\n",
17fb4f29 10844 what, (int)limit, idx);
77241056
MM		 10845}
10846
10847/* change only the shared limit portion of SendCmGLobalCredit */
10848static void set_global_shared(struct hfi1_devdata *dd, u16 limit)
10849{
10850 u64 reg;
10851
10852 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
10853 reg &= ~SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK;
10854 reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT;
10855 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
10856}
10857
10858/* change only the total credit limit portion of SendCmGLobalCredit */
10859static void set_global_limit(struct hfi1_devdata *dd, u16 limit)
10860{
10861 u64 reg;
10862
10863 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
10864 reg &= ~SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK;
10865 reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT;
10866 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
10867}
10868
10869/* set the given per-VL shared limit */
10870static void set_vl_shared(struct hfi1_devdata *dd, int vl, u16 limit)
10871{
10872 u64 reg;
10873 u32 addr;
10874
10875 if (vl < TXE_NUM_DATA_VL)
10876 addr = SEND_CM_CREDIT_VL + (8 * vl);
10877 else
10878 addr = SEND_CM_CREDIT_VL15;
10879
10880 reg = read_csr(dd, addr);
10881 reg &= ~SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SMASK;
10882 reg |= (u64)limit << SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT;
10883 write_csr(dd, addr, reg);
10884}
10885
10886/* set the given per-VL dedicated limit */
10887static void set_vl_dedicated(struct hfi1_devdata *dd, int vl, u16 limit)
10888{
10889 u64 reg;
10890 u32 addr;
10891
10892 if (vl < TXE_NUM_DATA_VL)
10893 addr = SEND_CM_CREDIT_VL + (8 * vl);
10894 else
10895 addr = SEND_CM_CREDIT_VL15;
10896
10897 reg = read_csr(dd, addr);
10898 reg &= ~SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SMASK;
10899 reg |= (u64)limit << SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT;
10900 write_csr(dd, addr, reg);
10901}
10902
10903/* spin until the given per-VL status mask bits clear */
10904static void wait_for_vl_status_clear(struct hfi1_devdata *dd, u64 mask,
10905 const char *which)
10906{
10907 unsigned long timeout;
10908 u64 reg;
10909
10910 timeout = jiffies + msecs_to_jiffies(VL_STATUS_CLEAR_TIMEOUT);
10911 while (1) {
10912 reg = read_csr(dd, SEND_CM_CREDIT_USED_STATUS) & mask;
10913
10914 if (reg == 0)
10915 return; /* success */
10916 if (time_after(jiffies, timeout))
10917 break; /* timed out */
10918 udelay(1);
10919 }
10920
10921 dd_dev_err(dd,
17fb4f29
JJ		 10922 "%s credit change status not clearing after %dms, mask 0x%llx, not clear 0x%llx\n",
10923 which, VL_STATUS_CLEAR_TIMEOUT, mask, reg);
77241056
MM		 10924 /*
10925 * If this occurs, it is likely there was a credit loss on the link.
10926 * The only recovery from that is a link bounce.
10927 */
10928 dd_dev_err(dd,
17fb4f29 10929 "Continuing anyway. A credit loss may occur. Suggest a link bounce\n");
77241056
MM		 10930}
10931
10932/*
10933 * The number of credits on the VLs may be changed while everything
10934 * is "live", but the following algorithm must be followed due to
10935 * how the hardware is actually implemented. In particular,
10936 * Return_Credit_Status[] is the only correct status check.
10937 *
10938 * if (reducing Global_Shared_Credit_Limit or any shared limit changing)
10939 * set Global_Shared_Credit_Limit = 0
10940 * use_all_vl = 1
10941 * mask0 = all VLs that are changing either dedicated or shared limits
10942 * set Shared_Limit[mask0] = 0
10943 * spin until Return_Credit_Status[use_all_vl ? all VL : mask0] == 0
10944 * if (changing any dedicated limit)
10945 * mask1 = all VLs that are lowering dedicated limits
10946 * lower Dedicated_Limit[mask1]
10947 * spin until Return_Credit_Status[mask1] == 0
10948 * raise Dedicated_Limits
10949 * raise Shared_Limits
10950 * raise Global_Shared_Credit_Limit
10951 *
10952 * lower = if the new limit is lower, set the limit to the new value
10953 * raise = if the new limit is higher than the current value (may be changed
10954 * earlier in the algorithm), set the new limit to the new value
10955 */
8a4d3444
MM		 10956int set_buffer_control(struct hfi1_pportdata *ppd,
10957 struct buffer_control *new_bc)
77241056 10958{
8a4d3444 10959 struct hfi1_devdata *dd = ppd->dd;
77241056
MM		 10960 u64 changing_mask, ld_mask, stat_mask;
10961 int change_count;
10962 int i, use_all_mask;
10963 int this_shared_changing;
8a4d3444 10964 int vl_count = 0, ret;
77241056
MM		 10965 /*
10966 * A0: add the variable any_shared_limit_changing below and in the
10967 * algorithm above. If removing A0 support, it can be removed.
10968 */
10969 int any_shared_limit_changing;
10970 struct buffer_control cur_bc;
10971 u8 changing[OPA_MAX_VLS];
10972 u8 lowering_dedicated[OPA_MAX_VLS];
10973 u16 cur_total;
10974 u32 new_total = 0;
10975 const u64 all_mask =
10976 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK
10977 | SEND_CM_CREDIT_USED_STATUS_VL1_RETURN_CREDIT_STATUS_SMASK
10978 | SEND_CM_CREDIT_USED_STATUS_VL2_RETURN_CREDIT_STATUS_SMASK
10979 | SEND_CM_CREDIT_USED_STATUS_VL3_RETURN_CREDIT_STATUS_SMASK
10980 | SEND_CM_CREDIT_USED_STATUS_VL4_RETURN_CREDIT_STATUS_SMASK
10981 | SEND_CM_CREDIT_USED_STATUS_VL5_RETURN_CREDIT_STATUS_SMASK
10982 | SEND_CM_CREDIT_USED_STATUS_VL6_RETURN_CREDIT_STATUS_SMASK
10983 | SEND_CM_CREDIT_USED_STATUS_VL7_RETURN_CREDIT_STATUS_SMASK
10984 | SEND_CM_CREDIT_USED_STATUS_VL15_RETURN_CREDIT_STATUS_SMASK;
10985
10986#define valid_vl(idx) ((idx) < TXE_NUM_DATA_VL || (idx) == 15)
10987#define NUM_USABLE_VLS 16 /* look at VL15 and less */
10988
77241056
MM		 10989 /* find the new total credits, do sanity check on unused VLs */
10990 for (i = 0; i < OPA_MAX_VLS; i++) {
10991 if (valid_vl(i)) {
10992 new_total += be16_to_cpu(new_bc->vl[i].dedicated);
10993 continue;
10994 }
10995 nonzero_msg(dd, i, "dedicated",
17fb4f29 10996 be16_to_cpu(new_bc->vl[i].dedicated));
77241056 10997 nonzero_msg(dd, i, "shared",
17fb4f29 10998 be16_to_cpu(new_bc->vl[i].shared));
77241056
MM		 10999 new_bc->vl[i].dedicated = 0;
11000 new_bc->vl[i].shared = 0;
11001 }
11002 new_total += be16_to_cpu(new_bc->overall_shared_limit);
bff14bb6 11003
77241056
MM		 11004 /* fetch the current values */
11005 get_buffer_control(dd, &cur_bc, &cur_total);
11006
11007 /*
11008 * Create the masks we will use.
11009 */
11010 memset(changing, 0, sizeof(changing));
11011 memset(lowering_dedicated, 0, sizeof(lowering_dedicated));
4d114fdd
JJ		 11012 /*
11013 * NOTE: Assumes that the individual VL bits are adjacent and in
11014 * increasing order
11015 */
77241056
MM		 11016 stat_mask =
11017 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK;
11018 changing_mask = 0;
11019 ld_mask = 0;
11020 change_count = 0;
11021 any_shared_limit_changing = 0;
11022 for (i = 0; i < NUM_USABLE_VLS; i++, stat_mask <<= 1) {
11023 if (!valid_vl(i))
11024 continue;
11025 this_shared_changing = new_bc->vl[i].shared
11026 != cur_bc.vl[i].shared;
11027 if (this_shared_changing)
11028 any_shared_limit_changing = 1;
d0d236ea
JJ		 11029 if (new_bc->vl[i].dedicated != cur_bc.vl[i].dedicated ||
11030 this_shared_changing) {
77241056
MM		 11031 changing[i] = 1;
11032 changing_mask |= stat_mask;
11033 change_count++;
11034 }
11035 if (be16_to_cpu(new_bc->vl[i].dedicated) <
11036 be16_to_cpu(cur_bc.vl[i].dedicated)) {
11037 lowering_dedicated[i] = 1;
11038 ld_mask |= stat_mask;
11039 }
11040 }
11041
11042 /* bracket the credit change with a total adjustment */
11043 if (new_total > cur_total)
11044 set_global_limit(dd, new_total);
11045
11046 /*
11047 * Start the credit change algorithm.
11048 */
11049 use_all_mask = 0;
11050 if ((be16_to_cpu(new_bc->overall_shared_limit) <
995deafa
MM		 11051 be16_to_cpu(cur_bc.overall_shared_limit)) ||
11052 (is_ax(dd) && any_shared_limit_changing)) {
77241056
MM		 11053 set_global_shared(dd, 0);
11054 cur_bc.overall_shared_limit = 0;
11055 use_all_mask = 1;
11056 }
11057
11058 for (i = 0; i < NUM_USABLE_VLS; i++) {
11059 if (!valid_vl(i))
11060 continue;
11061
11062 if (changing[i]) {
11063 set_vl_shared(dd, i, 0);
11064 cur_bc.vl[i].shared = 0;
11065 }
11066 }
11067
11068 wait_for_vl_status_clear(dd, use_all_mask ? all_mask : changing_mask,
17fb4f29 11069 "shared");
77241056
MM		 11070
11071 if (change_count > 0) {
11072 for (i = 0; i < NUM_USABLE_VLS; i++) {
11073 if (!valid_vl(i))
11074 continue;
11075
11076 if (lowering_dedicated[i]) {
11077 set_vl_dedicated(dd, i,
17fb4f29
JJ		 11078 be16_to_cpu(new_bc->
11079 vl[i].dedicated));
77241056
MM		 11080 cur_bc.vl[i].dedicated =
11081 new_bc->vl[i].dedicated;
11082 }
11083 }
11084
11085 wait_for_vl_status_clear(dd, ld_mask, "dedicated");
11086
11087 /* now raise all dedicated that are going up */
11088 for (i = 0; i < NUM_USABLE_VLS; i++) {
11089 if (!valid_vl(i))
11090 continue;
11091
11092 if (be16_to_cpu(new_bc->vl[i].dedicated) >
11093 be16_to_cpu(cur_bc.vl[i].dedicated))
11094 set_vl_dedicated(dd, i,
17fb4f29
JJ		 11095 be16_to_cpu(new_bc->
11096 vl[i].dedicated));
77241056
MM		 11097 }
11098 }
11099
11100 /* next raise all shared that are going up */
11101 for (i = 0; i < NUM_USABLE_VLS; i++) {
11102 if (!valid_vl(i))
11103 continue;
11104
11105 if (be16_to_cpu(new_bc->vl[i].shared) >
11106 be16_to_cpu(cur_bc.vl[i].shared))
11107 set_vl_shared(dd, i, be16_to_cpu(new_bc->vl[i].shared));
11108 }
11109
11110 /* finally raise the global shared */
11111 if (be16_to_cpu(new_bc->overall_shared_limit) >
17fb4f29 11112 be16_to_cpu(cur_bc.overall_shared_limit))
77241056 11113 set_global_shared(dd,
17fb4f29 11114 be16_to_cpu(new_bc->overall_shared_limit));
77241056
MM		 11115
11116 /* bracket the credit change with a total adjustment */
11117 if (new_total < cur_total)
11118 set_global_limit(dd, new_total);
8a4d3444
MM		 11119
11120 /*
11121 * Determine the actual number of operational VLS using the number of
11122 * dedicated and shared credits for each VL.
11123 */
11124 if (change_count > 0) {
11125 for (i = 0; i < TXE_NUM_DATA_VL; i++)
11126 if (be16_to_cpu(new_bc->vl[i].dedicated) > 0 ||
11127 be16_to_cpu(new_bc->vl[i].shared) > 0)
11128 vl_count++;
11129 ppd->actual_vls_operational = vl_count;
11130 ret = sdma_map_init(dd, ppd->port - 1, vl_count ?
11131 ppd->actual_vls_operational :
11132 ppd->vls_operational,
11133 NULL);
11134 if (ret == 0)
11135 ret = pio_map_init(dd, ppd->port - 1, vl_count ?
11136 ppd->actual_vls_operational :
11137 ppd->vls_operational, NULL);
11138 if (ret)
11139 return ret;
11140 }
77241056
MM		 11141 return 0;
11142}
11143
11144/*
11145 * Read the given fabric manager table. Return the size of the
11146 * table (in bytes) on success, and a negative error code on
11147 * failure.
11148 */
11149int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t)
11150
11151{
11152 int size;
11153 struct vl_arb_cache *vlc;
11154
11155 switch (which) {
11156 case FM_TBL_VL_HIGH_ARB:
11157 size = 256;
11158 /*
11159 * OPA specifies 128 elements (of 2 bytes each), though
11160 * HFI supports only 16 elements in h/w.
11161 */
11162 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE);
11163 vl_arb_get_cache(vlc, t);
11164 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
11165 break;
11166 case FM_TBL_VL_LOW_ARB:
11167 size = 256;
11168 /*
11169 * OPA specifies 128 elements (of 2 bytes each), though
11170 * HFI supports only 16 elements in h/w.
11171 */
11172 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE);
11173 vl_arb_get_cache(vlc, t);
11174 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
11175 break;
11176 case FM_TBL_BUFFER_CONTROL:
11177 size = get_buffer_control(ppd->dd, t, NULL);
11178 break;
11179 case FM_TBL_SC2VLNT:
11180 size = get_sc2vlnt(ppd->dd, t);
11181 break;
11182 case FM_TBL_VL_PREEMPT_ELEMS:
11183 size = 256;
11184 /* OPA specifies 128 elements, of 2 bytes each */
11185 get_vlarb_preempt(ppd->dd, OPA_MAX_VLS, t);
11186 break;
11187 case FM_TBL_VL_PREEMPT_MATRIX:
11188 size = 256;
11189 /*
11190 * OPA specifies that this is the same size as the VL
11191 * arbitration tables (i.e., 256 bytes).
11192 */
11193 break;
11194 default:
11195 return -EINVAL;
11196 }
11197 return size;
11198}
11199
11200/*
11201 * Write the given fabric manager table.
11202 */
11203int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t)
11204{
11205 int ret = 0;
11206 struct vl_arb_cache *vlc;
11207
11208 switch (which) {
11209 case FM_TBL_VL_HIGH_ARB:
11210 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE);
11211 if (vl_arb_match_cache(vlc, t)) {
11212 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
11213 break;
11214 }
11215 vl_arb_set_cache(vlc, t);
11216 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
11217 ret = set_vl_weights(ppd, SEND_HIGH_PRIORITY_LIST,
11218 VL_ARB_HIGH_PRIO_TABLE_SIZE, t);
11219 break;
11220 case FM_TBL_VL_LOW_ARB:
11221 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE);
11222 if (vl_arb_match_cache(vlc, t)) {
11223 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
11224 break;
11225 }
11226 vl_arb_set_cache(vlc, t);
11227 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
11228 ret = set_vl_weights(ppd, SEND_LOW_PRIORITY_LIST,
11229 VL_ARB_LOW_PRIO_TABLE_SIZE, t);
11230 break;
11231 case FM_TBL_BUFFER_CONTROL:
8a4d3444 11232 ret = set_buffer_control(ppd, t);
77241056
MM		 11233 break;
11234 case FM_TBL_SC2VLNT:
11235 set_sc2vlnt(ppd->dd, t);
11236 break;
11237 default:
11238 ret = -EINVAL;
11239 }
11240 return ret;
11241}
11242
11243/*
11244 * Disable all data VLs.
11245 *
11246 * Return 0 if disabled, non-zero if the VLs cannot be disabled.
11247 */
11248static int disable_data_vls(struct hfi1_devdata *dd)
11249{
995deafa 11250 if (is_ax(dd))
77241056
MM		 11251 return 1;
11252
11253 pio_send_control(dd, PSC_DATA_VL_DISABLE);
11254
11255 return 0;
11256}
11257
11258/*
11259 * open_fill_data_vls() - the counterpart to stop_drain_data_vls().
11260 * Just re-enables all data VLs (the "fill" part happens
11261 * automatically - the name was chosen for symmetry with
11262 * stop_drain_data_vls()).
11263 *
11264 * Return 0 if successful, non-zero if the VLs cannot be enabled.
11265 */
11266int open_fill_data_vls(struct hfi1_devdata *dd)
11267{
995deafa 11268 if (is_ax(dd))
77241056
MM		 11269 return 1;
11270
11271 pio_send_control(dd, PSC_DATA_VL_ENABLE);
11272
11273 return 0;
11274}
11275
11276/*
11277 * drain_data_vls() - assumes that disable_data_vls() has been called,
11278 * wait for occupancy (of per-VL FIFOs) for all contexts, and SDMA
11279 * engines to drop to 0.
11280 */
11281static void drain_data_vls(struct hfi1_devdata *dd)
11282{
11283 sc_wait(dd);
11284 sdma_wait(dd);
11285 pause_for_credit_return(dd);
11286}
11287
11288/*
11289 * stop_drain_data_vls() - disable, then drain all per-VL fifos.
11290 *
11291 * Use open_fill_data_vls() to resume using data VLs. This pair is
11292 * meant to be used like this:
11293 *
11294 * stop_drain_data_vls(dd);
11295 * // do things with per-VL resources
11296 * open_fill_data_vls(dd);
11297 */
11298int stop_drain_data_vls(struct hfi1_devdata *dd)
11299{
11300 int ret;
11301
11302 ret = disable_data_vls(dd);
11303 if (ret == 0)
11304 drain_data_vls(dd);
11305
11306 return ret;
11307}
11308
11309/*
11310 * Convert a nanosecond time to a cclock count. No matter how slow
11311 * the cclock, a non-zero ns will always have a non-zero result.
11312 */
11313u32 ns_to_cclock(struct hfi1_devdata *dd, u32 ns)
11314{
11315 u32 cclocks;
11316
11317 if (dd->icode == ICODE_FPGA_EMULATION)
11318 cclocks = (ns * 1000) / FPGA_CCLOCK_PS;
11319 else /* simulation pretends to be ASIC */
11320 cclocks = (ns * 1000) / ASIC_CCLOCK_PS;
11321 if (ns && !cclocks) /* if ns nonzero, must be at least 1 */
11322 cclocks = 1;
11323 return cclocks;
11324}
11325
11326/*
11327 * Convert a cclock count to nanoseconds. Not matter how slow
11328 * the cclock, a non-zero cclocks will always have a non-zero result.
11329 */
11330u32 cclock_to_ns(struct hfi1_devdata *dd, u32 cclocks)
11331{
11332 u32 ns;
11333
11334 if (dd->icode == ICODE_FPGA_EMULATION)
11335 ns = (cclocks * FPGA_CCLOCK_PS) / 1000;
11336 else /* simulation pretends to be ASIC */
11337 ns = (cclocks * ASIC_CCLOCK_PS) / 1000;
11338 if (cclocks && !ns)
11339 ns = 1;
11340 return ns;
11341}
11342
11343/*
11344 * Dynamically adjust the receive interrupt timeout for a context based on
11345 * incoming packet rate.
11346 *
11347 * NOTE: Dynamic adjustment does not allow rcv_intr_count to be zero.
11348 */
11349static void adjust_rcv_timeout(struct hfi1_ctxtdata *rcd, u32 npkts)
11350{
11351 struct hfi1_devdata *dd = rcd->dd;
11352 u32 timeout = rcd->rcvavail_timeout;
11353
11354 /*
11355 * This algorithm doubles or halves the timeout depending on whether
11356 * the number of packets received in this interrupt were less than or
11357 * greater equal the interrupt count.
11358 *
11359 * The calculations below do not allow a steady state to be achieved.
11360 * Only at the endpoints it is possible to have an unchanging
11361 * timeout.
11362 */
11363 if (npkts < rcv_intr_count) {
11364 /*
11365 * Not enough packets arrived before the timeout, adjust
11366 * timeout downward.
11367 */
11368 if (timeout < 2) /* already at minimum? */
11369 return;
11370 timeout >>= 1;
11371 } else {
11372 /*
11373 * More than enough packets arrived before the timeout, adjust
11374 * timeout upward.
11375 */
11376 if (timeout >= dd->rcv_intr_timeout_csr) /* already at max? */
11377 return;
11378 timeout = min(timeout << 1, dd->rcv_intr_timeout_csr);
11379 }
11380
11381 rcd->rcvavail_timeout = timeout;
4d114fdd
JJ		 11382 /*
11383 * timeout cannot be larger than rcv_intr_timeout_csr which has already
11384 * been verified to be in range
11385 */
77241056 11386 write_kctxt_csr(dd, rcd->ctxt, RCV_AVAIL_TIME_OUT,
17fb4f29
JJ		 11387 (u64)timeout <<
11388 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
77241056
MM		 11389}
11390
11391void update_usrhead(struct hfi1_ctxtdata *rcd, u32 hd, u32 updegr, u32 egrhd,
11392 u32 intr_adjust, u32 npkts)
11393{
11394 struct hfi1_devdata *dd = rcd->dd;
11395 u64 reg;
11396 u32 ctxt = rcd->ctxt;
11397
11398 /*
11399 * Need to write timeout register before updating RcvHdrHead to ensure
11400 * that a new value is used when the HW decides to restart counting.
11401 */
11402 if (intr_adjust)
11403 adjust_rcv_timeout(rcd, npkts);
11404 if (updegr) {
11405 reg = (egrhd & RCV_EGR_INDEX_HEAD_HEAD_MASK)
11406 << RCV_EGR_INDEX_HEAD_HEAD_SHIFT;
11407 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, reg);
11408 }
11409 mmiowb();
11410 reg = ((u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT) |
11411 (((u64)hd & RCV_HDR_HEAD_HEAD_MASK)
11412 << RCV_HDR_HEAD_HEAD_SHIFT);
11413 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg);
11414 mmiowb();
11415}
11416
11417u32 hdrqempty(struct hfi1_ctxtdata *rcd)
11418{
11419 u32 head, tail;
11420
11421 head = (read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_HEAD)
11422 & RCV_HDR_HEAD_HEAD_SMASK) >> RCV_HDR_HEAD_HEAD_SHIFT;
11423
11424 if (rcd->rcvhdrtail_kvaddr)
11425 tail = get_rcvhdrtail(rcd);
11426 else
11427 tail = read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
11428
11429 return head == tail;
11430}
11431
11432/*
11433 * Context Control and Receive Array encoding for buffer size:
11434 * 0x0 invalid
11435 * 0x1 4 KB
11436 * 0x2 8 KB
11437 * 0x3 16 KB
11438 * 0x4 32 KB
11439 * 0x5 64 KB
11440 * 0x6 128 KB
11441 * 0x7 256 KB
11442 * 0x8 512 KB (Receive Array only)
11443 * 0x9 1 MB (Receive Array only)
11444 * 0xa 2 MB (Receive Array only)
11445 *
11446 * 0xB-0xF - reserved (Receive Array only)
11447 *
11448 *
11449 * This routine assumes that the value has already been sanity checked.
11450 */
11451static u32 encoded_size(u32 size)
11452{
11453 switch (size) {
8638b77f
JJ		 11454 case 4 * 1024: return 0x1;
11455 case 8 * 1024: return 0x2;
11456 case 16 * 1024: return 0x3;
11457 case 32 * 1024: return 0x4;
11458 case 64 * 1024: return 0x5;
11459 case 128 * 1024: return 0x6;
11460 case 256 * 1024: return 0x7;
11461 case 512 * 1024: return 0x8;
11462 case 1 * 1024 * 1024: return 0x9;
11463 case 2 * 1024 * 1024: return 0xa;
77241056
MM		 11464 }
11465 return 0x1; /* if invalid, go with the minimum size */
11466}
11467
11468void hfi1_rcvctrl(struct hfi1_devdata *dd, unsigned int op, int ctxt)
11469{
11470 struct hfi1_ctxtdata *rcd;
11471 u64 rcvctrl, reg;
11472 int did_enable = 0;
11473
11474 rcd = dd->rcd[ctxt];
11475 if (!rcd)
11476 return;
11477
11478 hfi1_cdbg(RCVCTRL, "ctxt %d op 0x%x", ctxt, op);
11479
11480 rcvctrl = read_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL);
11481 /* if the context already enabled, don't do the extra steps */
d0d236ea
JJ		 11482 if ((op & HFI1_RCVCTRL_CTXT_ENB) &&
11483 !(rcvctrl & RCV_CTXT_CTRL_ENABLE_SMASK)) {
77241056
MM		 11484 /* reset the tail and hdr addresses, and sequence count */
11485 write_kctxt_csr(dd, ctxt, RCV_HDR_ADDR,
11486 rcd->rcvhdrq_phys);
11487 if (HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL))
11488 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
11489 rcd->rcvhdrqtailaddr_phys);
11490 rcd->seq_cnt = 1;
11491
11492 /* reset the cached receive header queue head value */
11493 rcd->head = 0;
11494
11495 /*
11496 * Zero the receive header queue so we don't get false
11497 * positives when checking the sequence number. The
11498 * sequence numbers could land exactly on the same spot.
11499 * E.g. a rcd restart before the receive header wrapped.
11500 */
11501 memset(rcd->rcvhdrq, 0, rcd->rcvhdrq_size);
11502
11503 /* starting timeout */
11504 rcd->rcvavail_timeout = dd->rcv_intr_timeout_csr;
11505
11506 /* enable the context */
11507 rcvctrl |= RCV_CTXT_CTRL_ENABLE_SMASK;
11508
11509 /* clean the egr buffer size first */
11510 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK;
11511 rcvctrl |= ((u64)encoded_size(rcd->egrbufs.rcvtid_size)
11512 & RCV_CTXT_CTRL_EGR_BUF_SIZE_MASK)
11513 << RCV_CTXT_CTRL_EGR_BUF_SIZE_SHIFT;
11514
11515 /* zero RcvHdrHead - set RcvHdrHead.Counter after enable */
11516 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0);
11517 did_enable = 1;
11518
11519 /* zero RcvEgrIndexHead */
11520 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, 0);
11521
11522 /* set eager count and base index */
11523 reg = (((u64)(rcd->egrbufs.alloced >> RCV_SHIFT)
11524 & RCV_EGR_CTRL_EGR_CNT_MASK)
11525 << RCV_EGR_CTRL_EGR_CNT_SHIFT) |
11526 (((rcd->eager_base >> RCV_SHIFT)
11527 & RCV_EGR_CTRL_EGR_BASE_INDEX_MASK)
11528 << RCV_EGR_CTRL_EGR_BASE_INDEX_SHIFT);
11529 write_kctxt_csr(dd, ctxt, RCV_EGR_CTRL, reg);
11530
11531 /*
11532 * Set TID (expected) count and base index.
11533 * rcd->expected_count is set to individual RcvArray entries,
11534 * not pairs, and the CSR takes a pair-count in groups of
11535 * four, so divide by 8.
11536 */
11537 reg = (((rcd->expected_count >> RCV_SHIFT)
11538 & RCV_TID_CTRL_TID_PAIR_CNT_MASK)
11539 << RCV_TID_CTRL_TID_PAIR_CNT_SHIFT) |
11540 (((rcd->expected_base >> RCV_SHIFT)
11541 & RCV_TID_CTRL_TID_BASE_INDEX_MASK)
11542 << RCV_TID_CTRL_TID_BASE_INDEX_SHIFT);
11543 write_kctxt_csr(dd, ctxt, RCV_TID_CTRL, reg);
82c2611d
NV		 11544 if (ctxt == HFI1_CTRL_CTXT)
11545 write_csr(dd, RCV_VL15, HFI1_CTRL_CTXT);
77241056
MM		 11546 }
11547 if (op & HFI1_RCVCTRL_CTXT_DIS) {
11548 write_csr(dd, RCV_VL15, 0);
46b010d3
MB		 11549 /*
11550 * When receive context is being disabled turn on tail
11551 * update with a dummy tail address and then disable
11552 * receive context.
11553 */
11554 if (dd->rcvhdrtail_dummy_physaddr) {
11555 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
11556 dd->rcvhdrtail_dummy_physaddr);
566c157c 11557 /* Enabling RcvCtxtCtrl.TailUpd is intentional. */
46b010d3
MB		 11558 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11559 }
11560
77241056
MM		 11561 rcvctrl &= ~RCV_CTXT_CTRL_ENABLE_SMASK;
11562 }
11563 if (op & HFI1_RCVCTRL_INTRAVAIL_ENB)
11564 rcvctrl |= RCV_CTXT_CTRL_INTR_AVAIL_SMASK;
11565 if (op & HFI1_RCVCTRL_INTRAVAIL_DIS)
11566 rcvctrl &= ~RCV_CTXT_CTRL_INTR_AVAIL_SMASK;
11567 if (op & HFI1_RCVCTRL_TAILUPD_ENB && rcd->rcvhdrqtailaddr_phys)
11568 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK;
566c157c
MH		 11569 if (op & HFI1_RCVCTRL_TAILUPD_DIS) {
11570 /* See comment on RcvCtxtCtrl.TailUpd above */
11571 if (!(op & HFI1_RCVCTRL_CTXT_DIS))
11572 rcvctrl &= ~RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11573 }
77241056
MM		 11574 if (op & HFI1_RCVCTRL_TIDFLOW_ENB)
11575 rcvctrl |= RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK;
11576 if (op & HFI1_RCVCTRL_TIDFLOW_DIS)
11577 rcvctrl &= ~RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK;
11578 if (op & HFI1_RCVCTRL_ONE_PKT_EGR_ENB) {
4d114fdd
JJ		 11579 /*
11580 * In one-packet-per-eager mode, the size comes from
11581 * the RcvArray entry.
11582 */
77241056
MM		 11583 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK;
11584 rcvctrl |= RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK;
11585 }
11586 if (op & HFI1_RCVCTRL_ONE_PKT_EGR_DIS)
11587 rcvctrl &= ~RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK;
11588 if (op & HFI1_RCVCTRL_NO_RHQ_DROP_ENB)
11589 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK;
11590 if (op & HFI1_RCVCTRL_NO_RHQ_DROP_DIS)
11591 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK;
11592 if (op & HFI1_RCVCTRL_NO_EGR_DROP_ENB)
11593 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK;
11594 if (op & HFI1_RCVCTRL_NO_EGR_DROP_DIS)
11595 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK;
11596 rcd->rcvctrl = rcvctrl;
11597 hfi1_cdbg(RCVCTRL, "ctxt %d rcvctrl 0x%llx\n", ctxt, rcvctrl);
11598 write_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL, rcd->rcvctrl);
11599
11600 /* work around sticky RcvCtxtStatus.BlockedRHQFull */
d0d236ea
JJ		 11601 if (did_enable &&
11602 (rcvctrl & RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK)) {
77241056
MM		 11603 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS);
11604 if (reg != 0) {
11605 dd_dev_info(dd, "ctxt %d status %lld (blocked)\n",
17fb4f29 11606 ctxt, reg);
77241056
MM		 11607 read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD);
11608 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x10);
11609 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x00);
11610 read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD);
11611 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS);
11612 dd_dev_info(dd, "ctxt %d status %lld (%s blocked)\n",
17fb4f29 11613 ctxt, reg, reg == 0 ? "not" : "still");
77241056
MM		 11614 }
11615 }
11616
11617 if (did_enable) {
11618 /*
11619 * The interrupt timeout and count must be set after
11620 * the context is enabled to take effect.
11621 */
11622 /* set interrupt timeout */
11623 write_kctxt_csr(dd, ctxt, RCV_AVAIL_TIME_OUT,
17fb4f29 11624 (u64)rcd->rcvavail_timeout <<
77241056
MM		 11625 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
11626
11627 /* set RcvHdrHead.Counter, zero RcvHdrHead.Head (again) */
11628 reg = (u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT;
11629 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg);
11630 }
11631
11632 if (op & (HFI1_RCVCTRL_TAILUPD_DIS | HFI1_RCVCTRL_CTXT_DIS))
11633 /*
11634 * If the context has been disabled and the Tail Update has
46b010d3
MB		 11635 * been cleared, set the RCV_HDR_TAIL_ADDR CSR to dummy address
11636 * so it doesn't contain an address that is invalid.
77241056 11637 */
46b010d3
MB		 11638 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
11639 dd->rcvhdrtail_dummy_physaddr);
77241056
MM		 11640}
11641
582e05c3 11642u32 hfi1_read_cntrs(struct hfi1_devdata *dd, char **namep, u64 **cntrp)
77241056
MM		 11643{
11644 int ret;
11645 u64 val = 0;
11646
11647 if (namep) {
11648 ret = dd->cntrnameslen;
77241056
MM		 11649 *namep = dd->cntrnames;
11650 } else {
11651 const struct cntr_entry *entry;
11652 int i, j;
11653
11654 ret = (dd->ndevcntrs) * sizeof(u64);
77241056
MM		 11655
11656 /* Get the start of the block of counters */
11657 *cntrp = dd->cntrs;
11658
11659 /*
11660 * Now go and fill in each counter in the block.
11661 */
11662 for (i = 0; i < DEV_CNTR_LAST; i++) {
11663 entry = &dev_cntrs[i];
11664 hfi1_cdbg(CNTR, "reading %s", entry->name);
11665 if (entry->flags & CNTR_DISABLED) {
11666 /* Nothing */
11667 hfi1_cdbg(CNTR, "\tDisabled\n");
11668 } else {
11669 if (entry->flags & CNTR_VL) {
11670 hfi1_cdbg(CNTR, "\tPer VL\n");
11671 for (j = 0; j < C_VL_COUNT; j++) {
11672 val = entry->rw_cntr(entry,
11673 dd, j,
11674 CNTR_MODE_R,
11675 0);
11676 hfi1_cdbg(
11677 CNTR,
11678 "\t\tRead 0x%llx for %d\n",
11679 val, j);
11680 dd->cntrs[entry->offset + j] =
11681 val;
11682 }
a699c6c2
VM		 11683 } else if (entry->flags & CNTR_SDMA) {
11684 hfi1_cdbg(CNTR,
11685 "\t Per SDMA Engine\n");
11686 for (j = 0; j < dd->chip_sdma_engines;
11687 j++) {
11688 val =
11689 entry->rw_cntr(entry, dd, j,
11690 CNTR_MODE_R, 0);
11691 hfi1_cdbg(CNTR,
11692 "\t\tRead 0x%llx for %d\n",
11693 val, j);
11694 dd->cntrs[entry->offset + j] =
11695 val;
11696 }
77241056
MM		 11697 } else {
11698 val = entry->rw_cntr(entry, dd,
11699 CNTR_INVALID_VL,
11700 CNTR_MODE_R, 0);
11701 dd->cntrs[entry->offset] = val;
11702 hfi1_cdbg(CNTR, "\tRead 0x%llx", val);
11703 }
11704 }
11705 }
11706 }
11707 return ret;
11708}
11709
11710/*
11711 * Used by sysfs to create files for hfi stats to read
11712 */
582e05c3 11713u32 hfi1_read_portcntrs(struct hfi1_pportdata *ppd, char **namep, u64 **cntrp)
77241056
MM		 11714{
11715 int ret;
11716 u64 val = 0;
11717
11718 if (namep) {
582e05c3
DL		 11719 ret = ppd->dd->portcntrnameslen;
11720 *namep = ppd->dd->portcntrnames;
77241056
MM		 11721 } else {
11722 const struct cntr_entry *entry;
77241056
MM		 11723 int i, j;
11724
582e05c3 11725 ret = ppd->dd->nportcntrs * sizeof(u64);
77241056
MM		 11726 *cntrp = ppd->cntrs;
11727
11728 for (i = 0; i < PORT_CNTR_LAST; i++) {
11729 entry = &port_cntrs[i];
11730 hfi1_cdbg(CNTR, "reading %s", entry->name);
11731 if (entry->flags & CNTR_DISABLED) {
11732 /* Nothing */
11733 hfi1_cdbg(CNTR, "\tDisabled\n");
11734 continue;
11735 }
11736
11737 if (entry->flags & CNTR_VL) {
11738 hfi1_cdbg(CNTR, "\tPer VL");
11739 for (j = 0; j < C_VL_COUNT; j++) {
11740 val = entry->rw_cntr(entry, ppd, j,
11741 CNTR_MODE_R,
11742 0);
11743 hfi1_cdbg(
11744 CNTR,
11745 "\t\tRead 0x%llx for %d",
11746 val, j);
11747 ppd->cntrs[entry->offset + j] = val;
11748 }
11749 } else {
11750 val = entry->rw_cntr(entry, ppd,
11751 CNTR_INVALID_VL,
11752 CNTR_MODE_R,
11753 0);
11754 ppd->cntrs[entry->offset] = val;
11755 hfi1_cdbg(CNTR, "\tRead 0x%llx", val);
11756 }
11757 }
11758 }
11759 return ret;
11760}
11761
11762static void free_cntrs(struct hfi1_devdata *dd)
11763{
11764 struct hfi1_pportdata *ppd;
11765 int i;
11766
11767 if (dd->synth_stats_timer.data)
11768 del_timer_sync(&dd->synth_stats_timer);
11769 dd->synth_stats_timer.data = 0;
11770 ppd = (struct hfi1_pportdata *)(dd + 1);
11771 for (i = 0; i < dd->num_pports; i++, ppd++) {
11772 kfree(ppd->cntrs);
11773 kfree(ppd->scntrs);
4eb06882
DD		 11774 free_percpu(ppd->ibport_data.rvp.rc_acks);
11775 free_percpu(ppd->ibport_data.rvp.rc_qacks);
11776 free_percpu(ppd->ibport_data.rvp.rc_delayed_comp);
77241056
MM		 11777 ppd->cntrs = NULL;
11778 ppd->scntrs = NULL;
4eb06882
DD		 11779 ppd->ibport_data.rvp.rc_acks = NULL;
11780 ppd->ibport_data.rvp.rc_qacks = NULL;
11781 ppd->ibport_data.rvp.rc_delayed_comp = NULL;
77241056
MM		 11782 }
11783 kfree(dd->portcntrnames);
11784 dd->portcntrnames = NULL;
11785 kfree(dd->cntrs);
11786 dd->cntrs = NULL;
11787 kfree(dd->scntrs);
11788 dd->scntrs = NULL;
11789 kfree(dd->cntrnames);
11790 dd->cntrnames = NULL;
11791}
11792
77241056
MM		 11793static u64 read_dev_port_cntr(struct hfi1_devdata *dd, struct cntr_entry *entry,
11794 u64 *psval, void *context, int vl)
11795{
11796 u64 val;
11797 u64 sval = *psval;
11798
11799 if (entry->flags & CNTR_DISABLED) {
11800 dd_dev_err(dd, "Counter %s not enabled", entry->name);
11801 return 0;
11802 }
11803
11804 hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);
11805
11806 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_R, 0);
11807
11808 /* If its a synthetic counter there is more work we need to do */
11809 if (entry->flags & CNTR_SYNTH) {
11810 if (sval == CNTR_MAX) {
11811 /* No need to read already saturated */
11812 return CNTR_MAX;
11813 }
11814
11815 if (entry->flags & CNTR_32BIT) {
11816 /* 32bit counters can wrap multiple times */
11817 u64 upper = sval >> 32;
11818 u64 lower = (sval << 32) >> 32;
11819
11820 if (lower > val) { /* hw wrapped */
11821 if (upper == CNTR_32BIT_MAX)
11822 val = CNTR_MAX;
11823 else
11824 upper++;
11825 }
11826
11827 if (val != CNTR_MAX)
11828 val = (upper << 32) | val;
11829
11830 } else {
11831 /* If we rolled we are saturated */
11832 if ((val < sval) || (val > CNTR_MAX))
11833 val = CNTR_MAX;
11834 }
11835 }
11836
11837 *psval = val;
11838
11839 hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);
11840
11841 return val;
11842}
11843
11844static u64 write_dev_port_cntr(struct hfi1_devdata *dd,
11845 struct cntr_entry *entry,
11846 u64 *psval, void *context, int vl, u64 data)
11847{
11848 u64 val;
11849
11850 if (entry->flags & CNTR_DISABLED) {
11851 dd_dev_err(dd, "Counter %s not enabled", entry->name);
11852 return 0;
11853 }
11854
11855 hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);
11856
11857 if (entry->flags & CNTR_SYNTH) {
11858 *psval = data;
11859 if (entry->flags & CNTR_32BIT) {
11860 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W,
11861 (data << 32) >> 32);
11862 val = data; /* return the full 64bit value */
11863 } else {
11864 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W,
11865 data);
11866 }
11867 } else {
11868 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, data);
11869 }
11870
11871 *psval = val;
11872
11873 hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);
11874
11875 return val;
11876}
11877
11878u64 read_dev_cntr(struct hfi1_devdata *dd, int index, int vl)
11879{
11880 struct cntr_entry *entry;
11881 u64 *sval;
11882
11883 entry = &dev_cntrs[index];
11884 sval = dd->scntrs + entry->offset;
11885
11886 if (vl != CNTR_INVALID_VL)
11887 sval += vl;
11888
11889 return read_dev_port_cntr(dd, entry, sval, dd, vl);
11890}
11891
11892u64 write_dev_cntr(struct hfi1_devdata *dd, int index, int vl, u64 data)
11893{
11894 struct cntr_entry *entry;
11895 u64 *sval;
11896
11897 entry = &dev_cntrs[index];
11898 sval = dd->scntrs + entry->offset;
11899
11900 if (vl != CNTR_INVALID_VL)
11901 sval += vl;
11902
11903 return write_dev_port_cntr(dd, entry, sval, dd, vl, data);
11904}
11905
11906u64 read_port_cntr(struct hfi1_pportdata *ppd, int index, int vl)
11907{
11908 struct cntr_entry *entry;
11909 u64 *sval;
11910
11911 entry = &port_cntrs[index];
11912 sval = ppd->scntrs + entry->offset;
11913
11914 if (vl != CNTR_INVALID_VL)
11915 sval += vl;
11916
11917 if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) &&
11918 (index <= C_RCV_HDR_OVF_LAST)) {
11919 /* We do not want to bother for disabled contexts */
11920 return 0;
11921 }
11922
11923 return read_dev_port_cntr(ppd->dd, entry, sval, ppd, vl);
11924}
11925
11926u64 write_port_cntr(struct hfi1_pportdata *ppd, int index, int vl, u64 data)
11927{
11928 struct cntr_entry *entry;
11929 u64 *sval;
11930
11931 entry = &port_cntrs[index];
11932 sval = ppd->scntrs + entry->offset;
11933
11934 if (vl != CNTR_INVALID_VL)
11935 sval += vl;
11936
11937 if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) &&
11938 (index <= C_RCV_HDR_OVF_LAST)) {
11939 /* We do not want to bother for disabled contexts */
11940 return 0;
11941 }
11942
11943 return write_dev_port_cntr(ppd->dd, entry, sval, ppd, vl, data);
11944}
11945
11946static void update_synth_timer(unsigned long opaque)
11947{
11948 u64 cur_tx;
11949 u64 cur_rx;
11950 u64 total_flits;
11951 u8 update = 0;
11952 int i, j, vl;
11953 struct hfi1_pportdata *ppd;
11954 struct cntr_entry *entry;
11955
11956 struct hfi1_devdata *dd = (struct hfi1_devdata *)opaque;
11957
11958 /*
11959 * Rather than keep beating on the CSRs pick a minimal set that we can
11960 * check to watch for potential roll over. We can do this by looking at
11961 * the number of flits sent/recv. If the total flits exceeds 32bits then
11962 * we have to iterate all the counters and update.
11963 */
11964 entry = &dev_cntrs[C_DC_RCV_FLITS];
11965 cur_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0);
11966
11967 entry = &dev_cntrs[C_DC_XMIT_FLITS];
11968 cur_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0);
11969
11970 hfi1_cdbg(
11971 CNTR,
11972 "[%d] curr tx=0x%llx rx=0x%llx :: last tx=0x%llx rx=0x%llx\n",
11973 dd->unit, cur_tx, cur_rx, dd->last_tx, dd->last_rx);
11974
11975 if ((cur_tx < dd->last_tx) || (cur_rx < dd->last_rx)) {
11976 /*
11977 * May not be strictly necessary to update but it won't hurt and
11978 * simplifies the logic here.
11979 */
11980 update = 1;
11981 hfi1_cdbg(CNTR, "[%d] Tripwire counter rolled, updating",
11982 dd->unit);
11983 } else {
11984 total_flits = (cur_tx - dd->last_tx) + (cur_rx - dd->last_rx);
11985 hfi1_cdbg(CNTR,
11986 "[%d] total flits 0x%llx limit 0x%llx\n", dd->unit,
11987 total_flits, (u64)CNTR_32BIT_MAX);
11988 if (total_flits >= CNTR_32BIT_MAX) {
11989 hfi1_cdbg(CNTR, "[%d] 32bit limit hit, updating",
11990 dd->unit);
11991 update = 1;
11992 }
11993 }
11994
11995 if (update) {
11996 hfi1_cdbg(CNTR, "[%d] Updating dd and ppd counters", dd->unit);
11997 for (i = 0; i < DEV_CNTR_LAST; i++) {
11998 entry = &dev_cntrs[i];
11999 if (entry->flags & CNTR_VL) {
12000 for (vl = 0; vl < C_VL_COUNT; vl++)
12001 read_dev_cntr(dd, i, vl);
12002 } else {
12003 read_dev_cntr(dd, i, CNTR_INVALID_VL);
12004 }
12005 }
12006 ppd = (struct hfi1_pportdata *)(dd + 1);
12007 for (i = 0; i < dd->num_pports; i++, ppd++) {
12008 for (j = 0; j < PORT_CNTR_LAST; j++) {
12009 entry = &port_cntrs[j];
12010 if (entry->flags & CNTR_VL) {
12011 for (vl = 0; vl < C_VL_COUNT; vl++)
12012 read_port_cntr(ppd, j, vl);
12013 } else {
12014 read_port_cntr(ppd, j, CNTR_INVALID_VL);
12015 }
12016 }
12017 }
12018
12019 /*
12020 * We want the value in the register. The goal is to keep track
12021 * of the number of "ticks" not the counter value. In other
12022 * words if the register rolls we want to notice it and go ahead
12023 * and force an update.
12024 */
12025 entry = &dev_cntrs[C_DC_XMIT_FLITS];
12026 dd->last_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL,
12027 CNTR_MODE_R, 0);
12028
12029 entry = &dev_cntrs[C_DC_RCV_FLITS];
12030 dd->last_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL,
12031 CNTR_MODE_R, 0);
12032
12033 hfi1_cdbg(CNTR, "[%d] setting last tx/rx to 0x%llx 0x%llx",
12034 dd->unit, dd->last_tx, dd->last_rx);
12035
12036 } else {
12037 hfi1_cdbg(CNTR, "[%d] No update necessary", dd->unit);
12038 }
12039
48a0cc13 12040 mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME);
77241056
MM		 12041}
12042
12043#define C_MAX_NAME 13 /* 12 chars + one for /0 */
12044static int init_cntrs(struct hfi1_devdata *dd)
12045{
c024c554 12046 int i, rcv_ctxts, j;
77241056
MM		 12047 size_t sz;
12048 char *p;
12049 char name[C_MAX_NAME];
12050 struct hfi1_pportdata *ppd;
11d2b114
SS		 12051 const char *bit_type_32 = ",32";
12052 const int bit_type_32_sz = strlen(bit_type_32);
77241056
MM		 12053
12054 /* set up the stats timer; the add_timer is done at the end */
24523a94
MFW		 12055 setup_timer(&dd->synth_stats_timer, update_synth_timer,
12056 (unsigned long)dd);
77241056
MM		 12057
12058 /***********************/
12059 /* per device counters */
12060 /***********************/
12061
12062 /* size names and determine how many we have*/
12063 dd->ndevcntrs = 0;
12064 sz = 0;
77241056
MM		 12065
12066 for (i = 0; i < DEV_CNTR_LAST; i++) {
77241056
MM		 12067 if (dev_cntrs[i].flags & CNTR_DISABLED) {
12068 hfi1_dbg_early("\tSkipping %s\n", dev_cntrs[i].name);
12069 continue;
12070 }
12071
12072 if (dev_cntrs[i].flags & CNTR_VL) {
c024c554 12073 dev_cntrs[i].offset = dd->ndevcntrs;
77241056 12074 for (j = 0; j < C_VL_COUNT; j++) {
77241056 12075 snprintf(name, C_MAX_NAME, "%s%d",
17fb4f29 12076 dev_cntrs[i].name, vl_from_idx(j));
77241056 12077 sz += strlen(name);
11d2b114
SS		 12078 /* Add ",32" for 32-bit counters */
12079 if (dev_cntrs[i].flags & CNTR_32BIT)
12080 sz += bit_type_32_sz;
77241056 12081 sz++;
77241056 12082 dd->ndevcntrs++;
77241056 12083 }
a699c6c2 12084 } else if (dev_cntrs[i].flags & CNTR_SDMA) {
c024c554 12085 dev_cntrs[i].offset = dd->ndevcntrs;
a699c6c2 12086 for (j = 0; j < dd->chip_sdma_engines; j++) {
a699c6c2
VM		 12087 snprintf(name, C_MAX_NAME, "%s%d",
12088 dev_cntrs[i].name, j);
77241056 12089 sz += strlen(name);
11d2b114
SS		 12090 /* Add ",32" for 32-bit counters */
12091 if (dev_cntrs[i].flags & CNTR_32BIT)
12092 sz += bit_type_32_sz;
77241056 12093 sz++;
77241056 12094 dd->ndevcntrs++;
77241056
MM		 12095 }
12096 } else {
11d2b114 12097 /* +1 for newline. */
77241056 12098 sz += strlen(dev_cntrs[i].name) + 1;
11d2b114
SS		 12099 /* Add ",32" for 32-bit counters */
12100 if (dev_cntrs[i].flags & CNTR_32BIT)
12101 sz += bit_type_32_sz;
c024c554 12102 dev_cntrs[i].offset = dd->ndevcntrs;
77241056 12103 dd->ndevcntrs++;
77241056
MM		 12104 }
12105 }
12106
12107 /* allocate space for the counter values */
c024c554 12108 dd->cntrs = kcalloc(dd->ndevcntrs, sizeof(u64), GFP_KERNEL);
77241056
MM		 12109 if (!dd->cntrs)
12110 goto bail;
12111
c024c554 12112 dd->scntrs = kcalloc(dd->ndevcntrs, sizeof(u64), GFP_KERNEL);
77241056
MM		 12113 if (!dd->scntrs)
12114 goto bail;
12115
77241056
MM		 12116 /* allocate space for the counter names */
12117 dd->cntrnameslen = sz;
12118 dd->cntrnames = kmalloc(sz, GFP_KERNEL);
12119 if (!dd->cntrnames)
12120 goto bail;
12121
12122 /* fill in the names */
c024c554 12123 for (p = dd->cntrnames, i = 0; i < DEV_CNTR_LAST; i++) {
77241056
MM		 12124 if (dev_cntrs[i].flags & CNTR_DISABLED) {
12125 /* Nothing */
11d2b114
SS		 12126 } else if (dev_cntrs[i].flags & CNTR_VL) {
12127 for (j = 0; j < C_VL_COUNT; j++) {
11d2b114
SS		 12128 snprintf(name, C_MAX_NAME, "%s%d",
12129 dev_cntrs[i].name,
12130 vl_from_idx(j));
12131 memcpy(p, name, strlen(name));
12132 p += strlen(name);
12133
12134 /* Counter is 32 bits */
12135 if (dev_cntrs[i].flags & CNTR_32BIT) {
12136 memcpy(p, bit_type_32, bit_type_32_sz);
12137 p += bit_type_32_sz;
77241056 12138 }
11d2b114
SS		 12139
12140 *p++ = '\n';
12141 }
12142 } else if (dev_cntrs[i].flags & CNTR_SDMA) {
12143 for (j = 0; j < dd->chip_sdma_engines; j++) {
11d2b114
SS		 12144 snprintf(name, C_MAX_NAME, "%s%d",
12145 dev_cntrs[i].name, j);
12146 memcpy(p, name, strlen(name));
12147 p += strlen(name);
12148
12149 /* Counter is 32 bits */
12150 if (dev_cntrs[i].flags & CNTR_32BIT) {
12151 memcpy(p, bit_type_32, bit_type_32_sz);
12152 p += bit_type_32_sz;
a699c6c2 12153 }
11d2b114 12154
77241056
MM		 12155 *p++ = '\n';
12156 }
11d2b114
SS		 12157 } else {
12158 memcpy(p, dev_cntrs[i].name, strlen(dev_cntrs[i].name));
12159 p += strlen(dev_cntrs[i].name);
12160
12161 /* Counter is 32 bits */
12162 if (dev_cntrs[i].flags & CNTR_32BIT) {
12163 memcpy(p, bit_type_32, bit_type_32_sz);
12164 p += bit_type_32_sz;
12165 }
12166
12167 *p++ = '\n';
77241056
MM		 12168 }
12169 }
12170
12171 /*********************/
12172 /* per port counters */
12173 /*********************/
12174
12175 /*
12176 * Go through the counters for the overflows and disable the ones we
12177 * don't need. This varies based on platform so we need to do it
12178 * dynamically here.
12179 */
12180 rcv_ctxts = dd->num_rcv_contexts;
12181 for (i = C_RCV_HDR_OVF_FIRST + rcv_ctxts;
12182 i <= C_RCV_HDR_OVF_LAST; i++) {
12183 port_cntrs[i].flags |= CNTR_DISABLED;
12184 }
12185
12186 /* size port counter names and determine how many we have*/
12187 sz = 0;
12188 dd->nportcntrs = 0;
12189 for (i = 0; i < PORT_CNTR_LAST; i++) {
77241056
MM		 12190 if (port_cntrs[i].flags & CNTR_DISABLED) {
12191 hfi1_dbg_early("\tSkipping %s\n", port_cntrs[i].name);
12192 continue;
12193 }
12194
12195 if (port_cntrs[i].flags & CNTR_VL) {
77241056
MM		 12196 port_cntrs[i].offset = dd->nportcntrs;
12197 for (j = 0; j < C_VL_COUNT; j++) {
77241056 12198 snprintf(name, C_MAX_NAME, "%s%d",
17fb4f29 12199 port_cntrs[i].name, vl_from_idx(j));
77241056 12200 sz += strlen(name);
11d2b114
SS		 12201 /* Add ",32" for 32-bit counters */
12202 if (port_cntrs[i].flags & CNTR_32BIT)
12203 sz += bit_type_32_sz;
77241056 12204 sz++;
77241056
MM		 12205 dd->nportcntrs++;
12206 }
12207 } else {
11d2b114 12208 /* +1 for newline */
77241056 12209 sz += strlen(port_cntrs[i].name) + 1;
11d2b114
SS		 12210 /* Add ",32" for 32-bit counters */
12211 if (port_cntrs[i].flags & CNTR_32BIT)
12212 sz += bit_type_32_sz;
77241056
MM		 12213 port_cntrs[i].offset = dd->nportcntrs;
12214 dd->nportcntrs++;
77241056
MM		 12215 }
12216 }
12217
12218 /* allocate space for the counter names */
12219 dd->portcntrnameslen = sz;
12220 dd->portcntrnames = kmalloc(sz, GFP_KERNEL);
12221 if (!dd->portcntrnames)
12222 goto bail;
12223
12224 /* fill in port cntr names */
12225 for (p = dd->portcntrnames, i = 0; i < PORT_CNTR_LAST; i++) {
12226 if (port_cntrs[i].flags & CNTR_DISABLED)
12227 continue;
12228
12229 if (port_cntrs[i].flags & CNTR_VL) {
12230 for (j = 0; j < C_VL_COUNT; j++) {
77241056 12231 snprintf(name, C_MAX_NAME, "%s%d",
17fb4f29 12232 port_cntrs[i].name, vl_from_idx(j));
77241056
MM		 12233 memcpy(p, name, strlen(name));
12234 p += strlen(name);
11d2b114
SS		 12235
12236 /* Counter is 32 bits */
12237 if (port_cntrs[i].flags & CNTR_32BIT) {
12238 memcpy(p, bit_type_32, bit_type_32_sz);
12239 p += bit_type_32_sz;
12240 }
12241
77241056
MM		 12242 *p++ = '\n';
12243 }
12244 } else {
12245 memcpy(p, port_cntrs[i].name,
12246 strlen(port_cntrs[i].name));
12247 p += strlen(port_cntrs[i].name);
11d2b114
SS		 12248
12249 /* Counter is 32 bits */
12250 if (port_cntrs[i].flags & CNTR_32BIT) {
12251 memcpy(p, bit_type_32, bit_type_32_sz);
12252 p += bit_type_32_sz;
12253 }
12254
77241056
MM		 12255 *p++ = '\n';
12256 }
12257 }
12258
12259 /* allocate per port storage for counter values */
12260 ppd = (struct hfi1_pportdata *)(dd + 1);
12261 for (i = 0; i < dd->num_pports; i++, ppd++) {
12262 ppd->cntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL);
12263 if (!ppd->cntrs)
12264 goto bail;
12265
12266 ppd->scntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL);
12267 if (!ppd->scntrs)
12268 goto bail;
12269 }
12270
12271 /* CPU counters need to be allocated and zeroed */
12272 if (init_cpu_counters(dd))
12273 goto bail;
12274
12275 mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME);
12276 return 0;
12277bail:
12278 free_cntrs(dd);
12279 return -ENOMEM;
12280}
12281
77241056
MM		 12282static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate)
12283{
12284 switch (chip_lstate) {
12285 default:
12286 dd_dev_err(dd,
17fb4f29
JJ		 12287 "Unknown logical state 0x%x, reporting IB_PORT_DOWN\n",
12288 chip_lstate);
77241056
MM		 12289 /* fall through */
12290 case LSTATE_DOWN:
12291 return IB_PORT_DOWN;
12292 case LSTATE_INIT:
12293 return IB_PORT_INIT;
12294 case LSTATE_ARMED:
12295 return IB_PORT_ARMED;
12296 case LSTATE_ACTIVE:
12297 return IB_PORT_ACTIVE;
12298 }
12299}
12300
12301u32 chip_to_opa_pstate(struct hfi1_devdata *dd, u32 chip_pstate)
12302{
12303 /* look at the HFI meta-states only */
12304 switch (chip_pstate & 0xf0) {
12305 default:
12306 dd_dev_err(dd, "Unexpected chip physical state of 0x%x\n",
17fb4f29 12307 chip_pstate);
77241056
MM		 12308 /* fall through */
12309 case PLS_DISABLED:
12310 return IB_PORTPHYSSTATE_DISABLED;
12311 case PLS_OFFLINE:
12312 return OPA_PORTPHYSSTATE_OFFLINE;
12313 case PLS_POLLING:
12314 return IB_PORTPHYSSTATE_POLLING;
12315 case PLS_CONFIGPHY:
12316 return IB_PORTPHYSSTATE_TRAINING;
12317 case PLS_LINKUP:
12318 return IB_PORTPHYSSTATE_LINKUP;
12319 case PLS_PHYTEST:
12320 return IB_PORTPHYSSTATE_PHY_TEST;
12321 }
12322}
12323
12324/* return the OPA port logical state name */
12325const char *opa_lstate_name(u32 lstate)
12326{
12327 static const char * const port_logical_names[] = {
12328 "PORT_NOP",
12329 "PORT_DOWN",
12330 "PORT_INIT",
12331 "PORT_ARMED",
12332 "PORT_ACTIVE",
12333 "PORT_ACTIVE_DEFER",
12334 };
12335 if (lstate < ARRAY_SIZE(port_logical_names))
12336 return port_logical_names[lstate];
12337 return "unknown";
12338}
12339
12340/* return the OPA port physical state name */
12341const char *opa_pstate_name(u32 pstate)
12342{
12343 static const char * const port_physical_names[] = {
12344 "PHYS_NOP",
12345 "reserved1",
12346 "PHYS_POLL",
12347 "PHYS_DISABLED",
12348 "PHYS_TRAINING",
12349 "PHYS_LINKUP",
12350 "PHYS_LINK_ERR_RECOVER",
12351 "PHYS_PHY_TEST",
12352 "reserved8",
12353 "PHYS_OFFLINE",
12354 "PHYS_GANGED",
12355 "PHYS_TEST",
12356 };
12357 if (pstate < ARRAY_SIZE(port_physical_names))
12358 return port_physical_names[pstate];
12359 return "unknown";
12360}
12361
12362/*
12363 * Read the hardware link state and set the driver's cached value of it.
12364 * Return the (new) current value.
12365 */
12366u32 get_logical_state(struct hfi1_pportdata *ppd)
12367{
12368 u32 new_state;
12369
12370 new_state = chip_to_opa_lstate(ppd->dd, read_logical_state(ppd->dd));
12371 if (new_state != ppd->lstate) {
12372 dd_dev_info(ppd->dd, "logical state changed to %s (0x%x)\n",
17fb4f29 12373 opa_lstate_name(new_state), new_state);
77241056
MM		 12374 ppd->lstate = new_state;
12375 }
12376 /*
12377 * Set port status flags in the page mapped into userspace
12378 * memory. Do it here to ensure a reliable state - this is
12379 * the only function called by all state handling code.
12380 * Always set the flags due to the fact that the cache value
12381 * might have been changed explicitly outside of this
12382 * function.
12383 */
12384 if (ppd->statusp) {
12385 switch (ppd->lstate) {
12386 case IB_PORT_DOWN:
12387 case IB_PORT_INIT:
12388 *ppd->statusp &= ~(HFI1_STATUS_IB_CONF |
12389 HFI1_STATUS_IB_READY);
12390 break;
12391 case IB_PORT_ARMED:
12392 *ppd->statusp |= HFI1_STATUS_IB_CONF;
12393 break;
12394 case IB_PORT_ACTIVE:
12395 *ppd->statusp |= HFI1_STATUS_IB_READY;
12396 break;
12397 }
12398 }
12399 return ppd->lstate;
12400}
12401
12402/**
12403 * wait_logical_linkstate - wait for an IB link state change to occur
12404 * @ppd: port device
12405 * @state: the state to wait for
12406 * @msecs: the number of milliseconds to wait
12407 *
12408 * Wait up to msecs milliseconds for IB link state change to occur.
12409 * For now, take the easy polling route.
12410 * Returns 0 if state reached, otherwise -ETIMEDOUT.
12411 */
12412static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state,
12413 int msecs)
12414{
12415 unsigned long timeout;
12416
12417 timeout = jiffies + msecs_to_jiffies(msecs);
12418 while (1) {
12419 if (get_logical_state(ppd) == state)
12420 return 0;
12421 if (time_after(jiffies, timeout))
12422 break;
12423 msleep(20);
12424 }
12425 dd_dev_err(ppd->dd, "timeout waiting for link state 0x%x\n", state);
12426
12427 return -ETIMEDOUT;
12428}
12429
12430u8 hfi1_ibphys_portstate(struct hfi1_pportdata *ppd)
12431{
77241056
MM		 12432 u32 pstate;
12433 u32 ib_pstate;
12434
12435 pstate = read_physical_state(ppd->dd);
12436 ib_pstate = chip_to_opa_pstate(ppd->dd, pstate);
f45c8dc8 12437 if (ppd->last_pstate != ib_pstate) {
77241056 12438 dd_dev_info(ppd->dd,
17fb4f29
JJ		 12439 "%s: physical state changed to %s (0x%x), phy 0x%x\n",
12440 __func__, opa_pstate_name(ib_pstate), ib_pstate,
12441 pstate);
f45c8dc8 12442 ppd->last_pstate = ib_pstate;
77241056
MM		 12443 }
12444 return ib_pstate;
12445}
12446
77241056
MM		 12447#define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \
12448(r &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
12449
12450#define SET_STATIC_RATE_CONTROL_SMASK(r) \
12451(r |= SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
12452
12453int hfi1_init_ctxt(struct send_context *sc)
12454{
d125a6c6 12455 if (sc) {
77241056
MM		 12456 struct hfi1_devdata *dd = sc->dd;
12457 u64 reg;
12458 u8 set = (sc->type == SC_USER ?
12459 HFI1_CAP_IS_USET(STATIC_RATE_CTRL) :
12460 HFI1_CAP_IS_KSET(STATIC_RATE_CTRL));
12461 reg = read_kctxt_csr(dd, sc->hw_context,
12462 SEND_CTXT_CHECK_ENABLE);
12463 if (set)
12464 CLEAR_STATIC_RATE_CONTROL_SMASK(reg);
12465 else
12466 SET_STATIC_RATE_CONTROL_SMASK(reg);
12467 write_kctxt_csr(dd, sc->hw_context,
12468 SEND_CTXT_CHECK_ENABLE, reg);
12469 }
12470 return 0;
12471}
12472
12473int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp)
12474{
12475 int ret = 0;
12476 u64 reg;
12477
12478 if (dd->icode != ICODE_RTL_SILICON) {
12479 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
12480 dd_dev_info(dd, "%s: tempsense not supported by HW\n",
12481 __func__);
12482 return -EINVAL;
12483 }
12484 reg = read_csr(dd, ASIC_STS_THERM);
12485 temp->curr = ((reg >> ASIC_STS_THERM_CURR_TEMP_SHIFT) &
12486 ASIC_STS_THERM_CURR_TEMP_MASK);
12487 temp->lo_lim = ((reg >> ASIC_STS_THERM_LO_TEMP_SHIFT) &
12488 ASIC_STS_THERM_LO_TEMP_MASK);
12489 temp->hi_lim = ((reg >> ASIC_STS_THERM_HI_TEMP_SHIFT) &
12490 ASIC_STS_THERM_HI_TEMP_MASK);
12491 temp->crit_lim = ((reg >> ASIC_STS_THERM_CRIT_TEMP_SHIFT) &
12492 ASIC_STS_THERM_CRIT_TEMP_MASK);
12493 /* triggers is a 3-bit value - 1 bit per trigger. */
12494 temp->triggers = (u8)((reg >> ASIC_STS_THERM_LOW_SHIFT) & 0x7);
12495
12496 return ret;
12497}
12498
12499/* ========================================================================= */
12500
12501/*
12502 * Enable/disable chip from delivering interrupts.
12503 */
12504void set_intr_state(struct hfi1_devdata *dd, u32 enable)
12505{
12506 int i;
12507
12508 /*
12509 * In HFI, the mask needs to be 1 to allow interrupts.
12510 */
12511 if (enable) {
77241056
MM		 12512 /* enable all interrupts */
12513 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
8638b77f 12514 write_csr(dd, CCE_INT_MASK + (8 * i), ~(u64)0);
77241056 12515
8ebd4cf1 12516 init_qsfp_int(dd);
77241056
MM		 12517 } else {
12518 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
8638b77f 12519 write_csr(dd, CCE_INT_MASK + (8 * i), 0ull);
77241056
MM		 12520 }
12521}
12522
12523/*
12524 * Clear all interrupt sources on the chip.
12525 */
12526static void clear_all_interrupts(struct hfi1_devdata *dd)
12527{
12528 int i;
12529
12530 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
8638b77f 12531 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~(u64)0);
77241056
MM		 12532
12533 write_csr(dd, CCE_ERR_CLEAR, ~(u64)0);
12534 write_csr(dd, MISC_ERR_CLEAR, ~(u64)0);
12535 write_csr(dd, RCV_ERR_CLEAR, ~(u64)0);
12536 write_csr(dd, SEND_ERR_CLEAR, ~(u64)0);
12537 write_csr(dd, SEND_PIO_ERR_CLEAR, ~(u64)0);
12538 write_csr(dd, SEND_DMA_ERR_CLEAR, ~(u64)0);
12539 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~(u64)0);
12540 for (i = 0; i < dd->chip_send_contexts; i++)
12541 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~(u64)0);
12542 for (i = 0; i < dd->chip_sdma_engines; i++)
12543 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~(u64)0);
12544
12545 write_csr(dd, DCC_ERR_FLG_CLR, ~(u64)0);
12546 write_csr(dd, DC_LCB_ERR_CLR, ~(u64)0);
12547 write_csr(dd, DC_DC8051_ERR_CLR, ~(u64)0);
12548}
12549
12550/* Move to pcie.c? */
12551static void disable_intx(struct pci_dev *pdev)
12552{
12553 pci_intx(pdev, 0);
12554}
12555
12556static void clean_up_interrupts(struct hfi1_devdata *dd)
12557{
12558 int i;
12559
12560 /* remove irqs - must happen before disabling/turning off */
12561 if (dd->num_msix_entries) {
12562 /* MSI-X */
12563 struct hfi1_msix_entry *me = dd->msix_entries;
12564
12565 for (i = 0; i < dd->num_msix_entries; i++, me++) {
d125a6c6 12566 if (!me->arg) /* => no irq, no affinity */
957558c9
MH		 12567 continue;
12568 hfi1_put_irq_affinity(dd, &dd->msix_entries[i]);
77241056
MM		 12569 free_irq(me->msix.vector, me->arg);
12570 }
12571 } else {
12572 /* INTx */
12573 if (dd->requested_intx_irq) {
12574 free_irq(dd->pcidev->irq, dd);
12575 dd->requested_intx_irq = 0;
12576 }
12577 }
12578
12579 /* turn off interrupts */
12580 if (dd->num_msix_entries) {
12581 /* MSI-X */
6e5b6131 12582 pci_disable_msix(dd->pcidev);
77241056
MM		 12583 } else {
12584 /* INTx */
12585 disable_intx(dd->pcidev);
12586 }
12587
12588 /* clean structures */
77241056
MM		 12589 kfree(dd->msix_entries);
12590 dd->msix_entries = NULL;
12591 dd->num_msix_entries = 0;
12592}
12593
12594/*
12595 * Remap the interrupt source from the general handler to the given MSI-X
12596 * interrupt.
12597 */
12598static void remap_intr(struct hfi1_devdata *dd, int isrc, int msix_intr)
12599{
12600 u64 reg;
12601 int m, n;
12602
12603 /* clear from the handled mask of the general interrupt */
12604 m = isrc / 64;
12605 n = isrc % 64;
12606 dd->gi_mask[m] &= ~((u64)1 << n);
12607
12608 /* direct the chip source to the given MSI-X interrupt */
12609 m = isrc / 8;
12610 n = isrc % 8;
8638b77f
JJ		 12611 reg = read_csr(dd, CCE_INT_MAP + (8 * m));
12612 reg &= ~((u64)0xff << (8 * n));
12613 reg |= ((u64)msix_intr & 0xff) << (8 * n);
12614 write_csr(dd, CCE_INT_MAP + (8 * m), reg);
77241056
MM		 12615}
12616
12617static void remap_sdma_interrupts(struct hfi1_devdata *dd,
12618 int engine, int msix_intr)
12619{
12620 /*
12621 * SDMA engine interrupt sources grouped by type, rather than
12622 * engine. Per-engine interrupts are as follows:
12623 * SDMA
12624 * SDMAProgress
12625 * SDMAIdle
12626 */
8638b77f 12627 remap_intr(dd, IS_SDMA_START + 0 * TXE_NUM_SDMA_ENGINES + engine,
17fb4f29 12628 msix_intr);
8638b77f 12629 remap_intr(dd, IS_SDMA_START + 1 * TXE_NUM_SDMA_ENGINES + engine,
17fb4f29 12630 msix_intr);
8638b77f 12631 remap_intr(dd, IS_SDMA_START + 2 * TXE_NUM_SDMA_ENGINES + engine,
17fb4f29 12632 msix_intr);
77241056
MM		 12633}
12634
77241056
MM		 12635static int request_intx_irq(struct hfi1_devdata *dd)
12636{
12637 int ret;
12638
9805071e
JJ		 12639 snprintf(dd->intx_name, sizeof(dd->intx_name), DRIVER_NAME "_%d",
12640 dd->unit);
77241056 12641 ret = request_irq(dd->pcidev->irq, general_interrupt,
17fb4f29 12642 IRQF_SHARED, dd->intx_name, dd);
77241056
MM		 12643 if (ret)
12644 dd_dev_err(dd, "unable to request INTx interrupt, err %d\n",
17fb4f29 12645 ret);
77241056
MM		 12646 else
12647 dd->requested_intx_irq = 1;
12648 return ret;
12649}
12650
12651static int request_msix_irqs(struct hfi1_devdata *dd)
12652{
77241056
MM		 12653 int first_general, last_general;
12654 int first_sdma, last_sdma;
12655 int first_rx, last_rx;
957558c9 12656 int i, ret = 0;
77241056
MM		 12657
12658 /* calculate the ranges we are going to use */
12659 first_general = 0;
f3ff8189
JJ		 12660 last_general = first_general + 1;
12661 first_sdma = last_general;
12662 last_sdma = first_sdma + dd->num_sdma;
12663 first_rx = last_sdma;
77241056
MM		 12664 last_rx = first_rx + dd->n_krcv_queues;
12665
77241056
MM		 12666 /*
12667 * Sanity check - the code expects all SDMA chip source
12668 * interrupts to be in the same CSR, starting at bit 0. Verify
12669 * that this is true by checking the bit location of the start.
12670 */
12671 BUILD_BUG_ON(IS_SDMA_START % 64);
12672
12673 for (i = 0; i < dd->num_msix_entries; i++) {
12674 struct hfi1_msix_entry *me = &dd->msix_entries[i];
12675 const char *err_info;
12676 irq_handler_t handler;
f4f30031 12677 irq_handler_t thread = NULL;
77241056
MM		 12678 void *arg;
12679 int idx;
12680 struct hfi1_ctxtdata *rcd = NULL;
12681 struct sdma_engine *sde = NULL;
12682
12683 /* obtain the arguments to request_irq */
12684 if (first_general <= i && i < last_general) {
12685 idx = i - first_general;
12686 handler = general_interrupt;
12687 arg = dd;
12688 snprintf(me->name, sizeof(me->name),
9805071e 12689 DRIVER_NAME "_%d", dd->unit);
77241056 12690 err_info = "general";
957558c9 12691 me->type = IRQ_GENERAL;
77241056
MM		 12692 } else if (first_sdma <= i && i < last_sdma) {
12693 idx = i - first_sdma;
12694 sde = &dd->per_sdma[idx];
12695 handler = sdma_interrupt;
12696 arg = sde;
12697 snprintf(me->name, sizeof(me->name),
9805071e 12698 DRIVER_NAME "_%d sdma%d", dd->unit, idx);
77241056
MM		 12699 err_info = "sdma";
12700 remap_sdma_interrupts(dd, idx, i);
957558c9 12701 me->type = IRQ_SDMA;
77241056
MM		 12702 } else if (first_rx <= i && i < last_rx) {
12703 idx = i - first_rx;
12704 rcd = dd->rcd[idx];
12705 /* no interrupt if no rcd */
12706 if (!rcd)
12707 continue;
12708 /*
12709 * Set the interrupt register and mask for this
12710 * context's interrupt.
12711 */
8638b77f 12712 rcd->ireg = (IS_RCVAVAIL_START + idx) / 64;
77241056 12713 rcd->imask = ((u64)1) <<
8638b77f 12714 ((IS_RCVAVAIL_START + idx) % 64);
77241056 12715 handler = receive_context_interrupt;
f4f30031 12716 thread = receive_context_thread;
77241056
MM		 12717 arg = rcd;
12718 snprintf(me->name, sizeof(me->name),
9805071e 12719 DRIVER_NAME "_%d kctxt%d", dd->unit, idx);
77241056 12720 err_info = "receive context";
66c0933b 12721 remap_intr(dd, IS_RCVAVAIL_START + idx, i);
957558c9 12722 me->type = IRQ_RCVCTXT;
77241056
MM		 12723 } else {
12724 /* not in our expected range - complain, then
4d114fdd
JJ		 12725 * ignore it
12726 */
77241056 12727 dd_dev_err(dd,
17fb4f29 12728 "Unexpected extra MSI-X interrupt %d\n", i);
77241056
MM		 12729 continue;
12730 }
12731 /* no argument, no interrupt */
d125a6c6 12732 if (!arg)
77241056
MM		 12733 continue;
12734 /* make sure the name is terminated */
8638b77f 12735 me->name[sizeof(me->name) - 1] = 0;
77241056 12736
f4f30031 12737 ret = request_threaded_irq(me->msix.vector, handler, thread, 0,
17fb4f29 12738 me->name, arg);
77241056
MM		 12739 if (ret) {
12740 dd_dev_err(dd,
17fb4f29
JJ		 12741 "unable to allocate %s interrupt, vector %d, index %d, err %d\n",
12742 err_info, me->msix.vector, idx, ret);
77241056
MM		 12743 return ret;
12744 }
12745 /*
12746 * assign arg after request_irq call, so it will be
12747 * cleaned up
12748 */
12749 me->arg = arg;
12750
957558c9
MH		 12751 ret = hfi1_get_irq_affinity(dd, me);
12752 if (ret)
12753 dd_dev_err(dd,
12754 "unable to pin IRQ %d\n", ret);
77241056
MM		 12755 }
12756
77241056 12757 return ret;
77241056
MM		 12758}
12759
12760/*
12761 * Set the general handler to accept all interrupts, remap all
12762 * chip interrupts back to MSI-X 0.
12763 */
12764static void reset_interrupts(struct hfi1_devdata *dd)
12765{
12766 int i;
12767
12768 /* all interrupts handled by the general handler */
12769 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
12770 dd->gi_mask[i] = ~(u64)0;
12771
12772 /* all chip interrupts map to MSI-X 0 */
12773 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
8638b77f 12774 write_csr(dd, CCE_INT_MAP + (8 * i), 0);
77241056
MM		 12775}
12776
12777static int set_up_interrupts(struct hfi1_devdata *dd)
12778{
12779 struct hfi1_msix_entry *entries;
12780 u32 total, request;
12781 int i, ret;
12782 int single_interrupt = 0; /* we expect to have all the interrupts */
12783
12784 /*
12785 * Interrupt count:
12786 * 1 general, "slow path" interrupt (includes the SDMA engines
12787 * slow source, SDMACleanupDone)
12788 * N interrupts - one per used SDMA engine
12789 * M interrupt - one per kernel receive context
12790 */
12791 total = 1 + dd->num_sdma + dd->n_krcv_queues;
12792
12793 entries = kcalloc(total, sizeof(*entries), GFP_KERNEL);
12794 if (!entries) {
77241056
MM		 12795 ret = -ENOMEM;
12796 goto fail;
12797 }
12798 /* 1-1 MSI-X entry assignment */
12799 for (i = 0; i < total; i++)
12800 entries[i].msix.entry = i;
12801
12802 /* ask for MSI-X interrupts */
12803 request = total;
12804 request_msix(dd, &request, entries);
12805
12806 if (request == 0) {
12807 /* using INTx */
12808 /* dd->num_msix_entries already zero */
12809 kfree(entries);
12810 single_interrupt = 1;
12811 dd_dev_err(dd, "MSI-X failed, using INTx interrupts\n");
12812 } else {
12813 /* using MSI-X */
12814 dd->num_msix_entries = request;
12815 dd->msix_entries = entries;
12816
12817 if (request != total) {
12818 /* using MSI-X, with reduced interrupts */
12819 dd_dev_err(
12820 dd,
12821 "cannot handle reduced interrupt case, want %u, got %u\n",
12822 total, request);
12823 ret = -EINVAL;
12824 goto fail;
12825 }
12826 dd_dev_info(dd, "%u MSI-X interrupts allocated\n", total);
12827 }
12828
12829 /* mask all interrupts */
12830 set_intr_state(dd, 0);
12831 /* clear all pending interrupts */
12832 clear_all_interrupts(dd);
12833
12834 /* reset general handler mask, chip MSI-X mappings */
12835 reset_interrupts(dd);
12836
12837 if (single_interrupt)
12838 ret = request_intx_irq(dd);
12839 else
12840 ret = request_msix_irqs(dd);
12841 if (ret)
12842 goto fail;
12843
12844 return 0;
12845
12846fail:
12847 clean_up_interrupts(dd);
12848 return ret;
12849}
12850
12851/*
12852 * Set up context values in dd. Sets:
12853 *
12854 * num_rcv_contexts - number of contexts being used
12855 * n_krcv_queues - number of kernel contexts
12856 * first_user_ctxt - first non-kernel context in array of contexts
12857 * freectxts - number of free user contexts
12858 * num_send_contexts - number of PIO send contexts being used
12859 */
12860static int set_up_context_variables(struct hfi1_devdata *dd)
12861{
12862 int num_kernel_contexts;
77241056
MM		 12863 int total_contexts;
12864 int ret;
12865 unsigned ngroups;
8f000f7f
DL		 12866 int qos_rmt_count;
12867 int user_rmt_reduced;
77241056
MM		 12868
12869 /*
33a9eb52 12870 * Kernel receive contexts:
82c2611d 12871 * - Context 0 - control context (VL15/multicast/error)
33a9eb52
DL		 12872 * - Context 1 - first kernel context
12873 * - Context 2 - second kernel context
12874 * ...
77241056
MM		 12875 */
12876 if (n_krcvqs)
82c2611d 12877 /*
33a9eb52
DL		 12878 * n_krcvqs is the sum of module parameter kernel receive
12879 * contexts, krcvqs[]. It does not include the control
12880 * context, so add that.
82c2611d 12881 */
33a9eb52 12882 num_kernel_contexts = n_krcvqs + 1;
77241056 12883 else
8784ac02 12884 num_kernel_contexts = DEFAULT_KRCVQS + 1;
77241056
MM		 12885 /*
12886 * Every kernel receive context needs an ACK send context.
12887 * one send context is allocated for each VL{0-7} and VL15
12888 */
12889 if (num_kernel_contexts > (dd->chip_send_contexts - num_vls - 1)) {
12890 dd_dev_err(dd,
12891 "Reducing # kernel rcv contexts to: %d, from %d\n",
12892 (int)(dd->chip_send_contexts - num_vls - 1),
12893 (int)num_kernel_contexts);
12894 num_kernel_contexts = dd->chip_send_contexts - num_vls - 1;
12895 }
12896 /*
0852d241
JJ		 12897 * User contexts:
12898 * - default to 1 user context per real (non-HT) CPU core if
12899 * num_user_contexts is negative
77241056 12900 */
2ce6bf22 12901 if (num_user_contexts < 0)
0852d241 12902 num_user_contexts =
4197344b 12903 cpumask_weight(&node_affinity.real_cpu_mask);
77241056
MM		 12904
12905 total_contexts = num_kernel_contexts + num_user_contexts;
12906
12907 /*
12908 * Adjust the counts given a global max.
12909 */
12910 if (total_contexts > dd->chip_rcv_contexts) {
12911 dd_dev_err(dd,
12912 "Reducing # user receive contexts to: %d, from %d\n",
12913 (int)(dd->chip_rcv_contexts - num_kernel_contexts),
12914 (int)num_user_contexts);
12915 num_user_contexts = dd->chip_rcv_contexts - num_kernel_contexts;
12916 /* recalculate */
12917 total_contexts = num_kernel_contexts + num_user_contexts;
12918 }
12919
8f000f7f
DL		 12920 /* each user context requires an entry in the RMT */
12921 qos_rmt_count = qos_rmt_entries(dd, NULL, NULL);
12922 if (qos_rmt_count + num_user_contexts > NUM_MAP_ENTRIES) {
12923 user_rmt_reduced = NUM_MAP_ENTRIES - qos_rmt_count;
12924 dd_dev_err(dd,
12925 "RMT size is reducing the number of user receive contexts from %d to %d\n",
12926 (int)num_user_contexts,
12927 user_rmt_reduced);
12928 /* recalculate */
12929 num_user_contexts = user_rmt_reduced;
12930 total_contexts = num_kernel_contexts + num_user_contexts;
12931 }
12932
77241056
MM		 12933 /* the first N are kernel contexts, the rest are user contexts */
12934 dd->num_rcv_contexts = total_contexts;
12935 dd->n_krcv_queues = num_kernel_contexts;
12936 dd->first_user_ctxt = num_kernel_contexts;
affa48de 12937 dd->num_user_contexts = num_user_contexts;
77241056
MM		 12938 dd->freectxts = num_user_contexts;
12939 dd_dev_info(dd,
17fb4f29
JJ		 12940 "rcv contexts: chip %d, used %d (kernel %d, user %d)\n",
12941 (int)dd->chip_rcv_contexts,
12942 (int)dd->num_rcv_contexts,
12943 (int)dd->n_krcv_queues,
12944 (int)dd->num_rcv_contexts - dd->n_krcv_queues);
77241056
MM		 12945
12946 /*
12947 * Receive array allocation:
12948 * All RcvArray entries are divided into groups of 8. This
12949 * is required by the hardware and will speed up writes to
12950 * consecutive entries by using write-combining of the entire
12951 * cacheline.
12952 *
12953 * The number of groups are evenly divided among all contexts.
12954 * any left over groups will be given to the first N user
12955 * contexts.
12956 */
12957 dd->rcv_entries.group_size = RCV_INCREMENT;
12958 ngroups = dd->chip_rcv_array_count / dd->rcv_entries.group_size;
12959 dd->rcv_entries.ngroups = ngroups / dd->num_rcv_contexts;
12960 dd->rcv_entries.nctxt_extra = ngroups -
12961 (dd->num_rcv_contexts * dd->rcv_entries.ngroups);
12962 dd_dev_info(dd, "RcvArray groups %u, ctxts extra %u\n",
12963 dd->rcv_entries.ngroups,
12964 dd->rcv_entries.nctxt_extra);
12965 if (dd->rcv_entries.ngroups * dd->rcv_entries.group_size >
12966 MAX_EAGER_ENTRIES * 2) {
12967 dd->rcv_entries.ngroups = (MAX_EAGER_ENTRIES * 2) /
12968 dd->rcv_entries.group_size;
12969 dd_dev_info(dd,
17fb4f29
JJ		 12970 "RcvArray group count too high, change to %u\n",
12971 dd->rcv_entries.ngroups);
77241056
MM		 12972 dd->rcv_entries.nctxt_extra = 0;
12973 }
12974 /*
12975 * PIO send contexts
12976 */
12977 ret = init_sc_pools_and_sizes(dd);
12978 if (ret >= 0) { /* success */
12979 dd->num_send_contexts = ret;
12980 dd_dev_info(
12981 dd,
44306f15 12982 "send contexts: chip %d, used %d (kernel %d, ack %d, user %d, vl15 %d)\n",
77241056
MM		 12983 dd->chip_send_contexts,
12984 dd->num_send_contexts,
12985 dd->sc_sizes[SC_KERNEL].count,
12986 dd->sc_sizes[SC_ACK].count,
44306f15
JX		 12987 dd->sc_sizes[SC_USER].count,
12988 dd->sc_sizes[SC_VL15].count);
77241056
MM		 12989 ret = 0; /* success */
12990 }
12991
12992 return ret;
12993}
12994
12995/*
12996 * Set the device/port partition key table. The MAD code
12997 * will ensure that, at least, the partial management
12998 * partition key is present in the table.
12999 */
13000static void set_partition_keys(struct hfi1_pportdata *ppd)
13001{
13002 struct hfi1_devdata *dd = ppd->dd;
13003 u64 reg = 0;
13004 int i;
13005
13006 dd_dev_info(dd, "Setting partition keys\n");
13007 for (i = 0; i < hfi1_get_npkeys(dd); i++) {
13008 reg |= (ppd->pkeys[i] &
13009 RCV_PARTITION_KEY_PARTITION_KEY_A_MASK) <<
13010 ((i % 4) *
13011 RCV_PARTITION_KEY_PARTITION_KEY_B_SHIFT);
13012 /* Each register holds 4 PKey values. */
13013 if ((i % 4) == 3) {
13014 write_csr(dd, RCV_PARTITION_KEY +
13015 ((i - 3) * 2), reg);
13016 reg = 0;
13017 }
13018 }
13019
13020 /* Always enable HW pkeys check when pkeys table is set */
13021 add_rcvctrl(dd, RCV_CTRL_RCV_PARTITION_KEY_ENABLE_SMASK);
13022}
13023
13024/*
13025 * These CSRs and memories are uninitialized on reset and must be
13026 * written before reading to set the ECC/parity bits.
13027 *
13028 * NOTE: All user context CSRs that are not mmaped write-only
13029 * (e.g. the TID flows) must be initialized even if the driver never
13030 * reads them.
13031 */
13032static void write_uninitialized_csrs_and_memories(struct hfi1_devdata *dd)
13033{
13034 int i, j;
13035
13036 /* CceIntMap */
13037 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
8638b77f 13038 write_csr(dd, CCE_INT_MAP + (8 * i), 0);
77241056
MM		 13039
13040 /* SendCtxtCreditReturnAddr */
13041 for (i = 0; i < dd->chip_send_contexts; i++)
13042 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0);
13043
13044 /* PIO Send buffers */
13045 /* SDMA Send buffers */
4d114fdd
JJ		 13046 /*
13047 * These are not normally read, and (presently) have no method
13048 * to be read, so are not pre-initialized
13049 */
77241056
MM		 13050
13051 /* RcvHdrAddr */
13052 /* RcvHdrTailAddr */
13053 /* RcvTidFlowTable */
13054 for (i = 0; i < dd->chip_rcv_contexts; i++) {
13055 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0);
13056 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0);
13057 for (j = 0; j < RXE_NUM_TID_FLOWS; j++)
8638b77f 13058 write_uctxt_csr(dd, i, RCV_TID_FLOW_TABLE + (8 * j), 0);
77241056
MM		 13059 }
13060
13061 /* RcvArray */
13062 for (i = 0; i < dd->chip_rcv_array_count; i++)
8638b77f 13063 write_csr(dd, RCV_ARRAY + (8 * i),
17fb4f29 13064 RCV_ARRAY_RT_WRITE_ENABLE_SMASK);
77241056
MM		 13065
13066 /* RcvQPMapTable */
13067 for (i = 0; i < 32; i++)
13068 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
13069}
13070
13071/*
13072 * Use the ctrl_bits in CceCtrl to clear the status_bits in CceStatus.
13073 */
13074static void clear_cce_status(struct hfi1_devdata *dd, u64 status_bits,
13075 u64 ctrl_bits)
13076{
13077 unsigned long timeout;
13078 u64 reg;
13079
13080 /* is the condition present? */
13081 reg = read_csr(dd, CCE_STATUS);
13082 if ((reg & status_bits) == 0)
13083 return;
13084
13085 /* clear the condition */
13086 write_csr(dd, CCE_CTRL, ctrl_bits);
13087
13088 /* wait for the condition to clear */
13089 timeout = jiffies + msecs_to_jiffies(CCE_STATUS_TIMEOUT);
13090 while (1) {
13091 reg = read_csr(dd, CCE_STATUS);
13092 if ((reg & status_bits) == 0)
13093 return;
13094 if (time_after(jiffies, timeout)) {
13095 dd_dev_err(dd,
17fb4f29
JJ		 13096 "Timeout waiting for CceStatus to clear bits 0x%llx, remaining 0x%llx\n",
13097 status_bits, reg & status_bits);
77241056
MM		 13098 return;
13099 }
13100 udelay(1);
13101 }
13102}
13103
13104/* set CCE CSRs to chip reset defaults */
13105static void reset_cce_csrs(struct hfi1_devdata *dd)
13106{
13107 int i;
13108
13109 /* CCE_REVISION read-only */
13110 /* CCE_REVISION2 read-only */
13111 /* CCE_CTRL - bits clear automatically */
13112 /* CCE_STATUS read-only, use CceCtrl to clear */
13113 clear_cce_status(dd, ALL_FROZE, CCE_CTRL_SPC_UNFREEZE_SMASK);
13114 clear_cce_status(dd, ALL_TXE_PAUSE, CCE_CTRL_TXE_RESUME_SMASK);
13115 clear_cce_status(dd, ALL_RXE_PAUSE, CCE_CTRL_RXE_RESUME_SMASK);
13116 for (i = 0; i < CCE_NUM_SCRATCH; i++)
13117 write_csr(dd, CCE_SCRATCH + (8 * i), 0);
13118 /* CCE_ERR_STATUS read-only */
13119 write_csr(dd, CCE_ERR_MASK, 0);
13120 write_csr(dd, CCE_ERR_CLEAR, ~0ull);
13121 /* CCE_ERR_FORCE leave alone */
13122 for (i = 0; i < CCE_NUM_32_BIT_COUNTERS; i++)
13123 write_csr(dd, CCE_COUNTER_ARRAY32 + (8 * i), 0);
13124 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_RESETCSR);
13125 /* CCE_PCIE_CTRL leave alone */
13126 for (i = 0; i < CCE_NUM_MSIX_VECTORS; i++) {
13127 write_csr(dd, CCE_MSIX_TABLE_LOWER + (8 * i), 0);
13128 write_csr(dd, CCE_MSIX_TABLE_UPPER + (8 * i),
17fb4f29 13129 CCE_MSIX_TABLE_UPPER_RESETCSR);
77241056
MM		 13130 }
13131 for (i = 0; i < CCE_NUM_MSIX_PBAS; i++) {
13132 /* CCE_MSIX_PBA read-only */
13133 write_csr(dd, CCE_MSIX_INT_GRANTED, ~0ull);
13134 write_csr(dd, CCE_MSIX_VEC_CLR_WITHOUT_INT, ~0ull);
13135 }
13136 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
13137 write_csr(dd, CCE_INT_MAP, 0);
13138 for (i = 0; i < CCE_NUM_INT_CSRS; i++) {
13139 /* CCE_INT_STATUS read-only */
13140 write_csr(dd, CCE_INT_MASK + (8 * i), 0);
13141 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~0ull);
13142 /* CCE_INT_FORCE leave alone */
13143 /* CCE_INT_BLOCKED read-only */
13144 }
13145 for (i = 0; i < CCE_NUM_32_BIT_INT_COUNTERS; i++)
13146 write_csr(dd, CCE_INT_COUNTER_ARRAY32 + (8 * i), 0);
13147}
13148
77241056
MM		 13149/* set MISC CSRs to chip reset defaults */
13150static void reset_misc_csrs(struct hfi1_devdata *dd)
13151{
13152 int i;
13153
13154 for (i = 0; i < 32; i++) {
13155 write_csr(dd, MISC_CFG_RSA_R2 + (8 * i), 0);
13156 write_csr(dd, MISC_CFG_RSA_SIGNATURE + (8 * i), 0);
13157 write_csr(dd, MISC_CFG_RSA_MODULUS + (8 * i), 0);
13158 }
4d114fdd
JJ		 13159 /*
13160 * MISC_CFG_SHA_PRELOAD leave alone - always reads 0 and can
13161 * only be written 128-byte chunks
13162 */
77241056
MM		 13163 /* init RSA engine to clear lingering errors */
13164 write_csr(dd, MISC_CFG_RSA_CMD, 1);
13165 write_csr(dd, MISC_CFG_RSA_MU, 0);
13166 write_csr(dd, MISC_CFG_FW_CTRL, 0);
13167 /* MISC_STS_8051_DIGEST read-only */
13168 /* MISC_STS_SBM_DIGEST read-only */
13169 /* MISC_STS_PCIE_DIGEST read-only */
13170 /* MISC_STS_FAB_DIGEST read-only */
13171 /* MISC_ERR_STATUS read-only */
13172 write_csr(dd, MISC_ERR_MASK, 0);
13173 write_csr(dd, MISC_ERR_CLEAR, ~0ull);
13174 /* MISC_ERR_FORCE leave alone */
13175}
13176
13177/* set TXE CSRs to chip reset defaults */
13178static void reset_txe_csrs(struct hfi1_devdata *dd)
13179{
13180 int i;
13181
13182 /*
13183 * TXE Kernel CSRs
13184 */
13185 write_csr(dd, SEND_CTRL, 0);
13186 __cm_reset(dd, 0); /* reset CM internal state */
13187 /* SEND_CONTEXTS read-only */
13188 /* SEND_DMA_ENGINES read-only */
13189 /* SEND_PIO_MEM_SIZE read-only */
13190 /* SEND_DMA_MEM_SIZE read-only */
13191 write_csr(dd, SEND_HIGH_PRIORITY_LIMIT, 0);
13192 pio_reset_all(dd); /* SEND_PIO_INIT_CTXT */
13193 /* SEND_PIO_ERR_STATUS read-only */
13194 write_csr(dd, SEND_PIO_ERR_MASK, 0);
13195 write_csr(dd, SEND_PIO_ERR_CLEAR, ~0ull);
13196 /* SEND_PIO_ERR_FORCE leave alone */
13197 /* SEND_DMA_ERR_STATUS read-only */
13198 write_csr(dd, SEND_DMA_ERR_MASK, 0);
13199 write_csr(dd, SEND_DMA_ERR_CLEAR, ~0ull);
13200 /* SEND_DMA_ERR_FORCE leave alone */
13201 /* SEND_EGRESS_ERR_STATUS read-only */
13202 write_csr(dd, SEND_EGRESS_ERR_MASK, 0);
13203 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~0ull);
13204 /* SEND_EGRESS_ERR_FORCE leave alone */
13205 write_csr(dd, SEND_BTH_QP, 0);
13206 write_csr(dd, SEND_STATIC_RATE_CONTROL, 0);
13207 write_csr(dd, SEND_SC2VLT0, 0);
13208 write_csr(dd, SEND_SC2VLT1, 0);
13209 write_csr(dd, SEND_SC2VLT2, 0);
13210 write_csr(dd, SEND_SC2VLT3, 0);
13211 write_csr(dd, SEND_LEN_CHECK0, 0);
13212 write_csr(dd, SEND_LEN_CHECK1, 0);
13213 /* SEND_ERR_STATUS read-only */
13214 write_csr(dd, SEND_ERR_MASK, 0);
13215 write_csr(dd, SEND_ERR_CLEAR, ~0ull);
13216 /* SEND_ERR_FORCE read-only */
13217 for (i = 0; i < VL_ARB_LOW_PRIO_TABLE_SIZE; i++)
8638b77f 13218 write_csr(dd, SEND_LOW_PRIORITY_LIST + (8 * i), 0);
77241056 13219 for (i = 0; i < VL_ARB_HIGH_PRIO_TABLE_SIZE; i++)
8638b77f
JJ		 13220 write_csr(dd, SEND_HIGH_PRIORITY_LIST + (8 * i), 0);
13221 for (i = 0; i < dd->chip_send_contexts / NUM_CONTEXTS_PER_SET; i++)
13222 write_csr(dd, SEND_CONTEXT_SET_CTRL + (8 * i), 0);
77241056 13223 for (i = 0; i < TXE_NUM_32_BIT_COUNTER; i++)
8638b77f 13224 write_csr(dd, SEND_COUNTER_ARRAY32 + (8 * i), 0);
77241056 13225 for (i = 0; i < TXE_NUM_64_BIT_COUNTER; i++)
8638b77f 13226 write_csr(dd, SEND_COUNTER_ARRAY64 + (8 * i), 0);
77241056 13227 write_csr(dd, SEND_CM_CTRL, SEND_CM_CTRL_RESETCSR);
17fb4f29 13228 write_csr(dd, SEND_CM_GLOBAL_CREDIT, SEND_CM_GLOBAL_CREDIT_RESETCSR);
77241056
MM		 13229 /* SEND_CM_CREDIT_USED_STATUS read-only */
13230 write_csr(dd, SEND_CM_TIMER_CTRL, 0);
13231 write_csr(dd, SEND_CM_LOCAL_AU_TABLE0_TO3, 0);
13232 write_csr(dd, SEND_CM_LOCAL_AU_TABLE4_TO7, 0);
13233 write_csr(dd, SEND_CM_REMOTE_AU_TABLE0_TO3, 0);
13234 write_csr(dd, SEND_CM_REMOTE_AU_TABLE4_TO7, 0);
13235 for (i = 0; i < TXE_NUM_DATA_VL; i++)
8638b77f 13236 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
77241056
MM		 13237 write_csr(dd, SEND_CM_CREDIT_VL15, 0);
13238 /* SEND_CM_CREDIT_USED_VL read-only */
13239 /* SEND_CM_CREDIT_USED_VL15 read-only */
13240 /* SEND_EGRESS_CTXT_STATUS read-only */
13241 /* SEND_EGRESS_SEND_DMA_STATUS read-only */
13242 write_csr(dd, SEND_EGRESS_ERR_INFO, ~0ull);
13243 /* SEND_EGRESS_ERR_INFO read-only */
13244 /* SEND_EGRESS_ERR_SOURCE read-only */
13245
13246 /*
13247 * TXE Per-Context CSRs
13248 */
13249 for (i = 0; i < dd->chip_send_contexts; i++) {
13250 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0);
13251 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_CTRL, 0);
13252 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0);
13253 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_FORCE, 0);
13254 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, 0);
13255 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~0ull);
13256 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_ENABLE, 0);
13257 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_VL, 0);
13258 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_JOB_KEY, 0);
13259 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_PARTITION_KEY, 0);
13260 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, 0);
13261 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_OPCODE, 0);
13262 }
13263
13264 /*
13265 * TXE Per-SDMA CSRs
13266 */
13267 for (i = 0; i < dd->chip_sdma_engines; i++) {
13268 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0);
13269 /* SEND_DMA_STATUS read-only */
13270 write_kctxt_csr(dd, i, SEND_DMA_BASE_ADDR, 0);
13271 write_kctxt_csr(dd, i, SEND_DMA_LEN_GEN, 0);
13272 write_kctxt_csr(dd, i, SEND_DMA_TAIL, 0);
13273 /* SEND_DMA_HEAD read-only */
13274 write_kctxt_csr(dd, i, SEND_DMA_HEAD_ADDR, 0);
13275 write_kctxt_csr(dd, i, SEND_DMA_PRIORITY_THLD, 0);
13276 /* SEND_DMA_IDLE_CNT read-only */
13277 write_kctxt_csr(dd, i, SEND_DMA_RELOAD_CNT, 0);
13278 write_kctxt_csr(dd, i, SEND_DMA_DESC_CNT, 0);
13279 /* SEND_DMA_DESC_FETCHED_CNT read-only */
13280 /* SEND_DMA_ENG_ERR_STATUS read-only */
13281 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, 0);
13282 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~0ull);
13283 /* SEND_DMA_ENG_ERR_FORCE leave alone */
13284 write_kctxt_csr(dd, i, SEND_DMA_CHECK_ENABLE, 0);
13285 write_kctxt_csr(dd, i, SEND_DMA_CHECK_VL, 0);
13286 write_kctxt_csr(dd, i, SEND_DMA_CHECK_JOB_KEY, 0);
13287 write_kctxt_csr(dd, i, SEND_DMA_CHECK_PARTITION_KEY, 0);
13288 write_kctxt_csr(dd, i, SEND_DMA_CHECK_SLID, 0);
13289 write_kctxt_csr(dd, i, SEND_DMA_CHECK_OPCODE, 0);
13290 write_kctxt_csr(dd, i, SEND_DMA_MEMORY, 0);
13291 }
13292}
13293
13294/*
13295 * Expect on entry:
13296 * o Packet ingress is disabled, i.e. RcvCtrl.RcvPortEnable == 0
13297 */
13298static void init_rbufs(struct hfi1_devdata *dd)
13299{
13300 u64 reg;
13301 int count;
13302
13303 /*
13304 * Wait for DMA to stop: RxRbufPktPending and RxPktInProgress are
13305 * clear.
13306 */
13307 count = 0;
13308 while (1) {
13309 reg = read_csr(dd, RCV_STATUS);
13310 if ((reg & (RCV_STATUS_RX_RBUF_PKT_PENDING_SMASK
13311 | RCV_STATUS_RX_PKT_IN_PROGRESS_SMASK)) == 0)
13312 break;
13313 /*
13314 * Give up after 1ms - maximum wait time.
13315 *
13316 * RBuf size is 148KiB. Slowest possible is PCIe Gen1 x1 at
13317 * 250MB/s bandwidth. Lower rate to 66% for overhead to get:
13318 * 148 KB / (66% * 250MB/s) = 920us
13319 */
13320 if (count++ > 500) {
13321 dd_dev_err(dd,
17fb4f29
JJ		 13322 "%s: in-progress DMA not clearing: RcvStatus 0x%llx, continuing\n",
13323 __func__, reg);
77241056
MM		 13324 break;
13325 }
13326 udelay(2); /* do not busy-wait the CSR */
13327 }
13328
13329 /* start the init - expect RcvCtrl to be 0 */
13330 write_csr(dd, RCV_CTRL, RCV_CTRL_RX_RBUF_INIT_SMASK);
13331
13332 /*
13333 * Read to force the write of Rcvtrl.RxRbufInit. There is a brief
13334 * period after the write before RcvStatus.RxRbufInitDone is valid.
13335 * The delay in the first run through the loop below is sufficient and
13336 * required before the first read of RcvStatus.RxRbufInintDone.
13337 */
13338 read_csr(dd, RCV_CTRL);
13339
13340 /* wait for the init to finish */
13341 count = 0;
13342 while (1) {
13343 /* delay is required first time through - see above */
13344 udelay(2); /* do not busy-wait the CSR */
13345 reg = read_csr(dd, RCV_STATUS);
13346 if (reg & (RCV_STATUS_RX_RBUF_INIT_DONE_SMASK))
13347 break;
13348
13349 /* give up after 100us - slowest possible at 33MHz is 73us */
13350 if (count++ > 50) {
13351 dd_dev_err(dd,
17fb4f29
JJ		 13352 "%s: RcvStatus.RxRbufInit not set, continuing\n",
13353 __func__);
77241056
MM		 13354 break;
13355 }
13356 }
13357}
13358
13359/* set RXE CSRs to chip reset defaults */
13360static void reset_rxe_csrs(struct hfi1_devdata *dd)
13361{
13362 int i, j;
13363
13364 /*
13365 * RXE Kernel CSRs
13366 */
13367 write_csr(dd, RCV_CTRL, 0);
13368 init_rbufs(dd);
13369 /* RCV_STATUS read-only */
13370 /* RCV_CONTEXTS read-only */
13371 /* RCV_ARRAY_CNT read-only */
13372 /* RCV_BUF_SIZE read-only */
13373 write_csr(dd, RCV_BTH_QP, 0);
13374 write_csr(dd, RCV_MULTICAST, 0);
13375 write_csr(dd, RCV_BYPASS, 0);
13376 write_csr(dd, RCV_VL15, 0);
13377 /* this is a clear-down */
13378 write_csr(dd, RCV_ERR_INFO,
17fb4f29 13379 RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SMASK);
77241056
MM		 13380 /* RCV_ERR_STATUS read-only */
13381 write_csr(dd, RCV_ERR_MASK, 0);
13382 write_csr(dd, RCV_ERR_CLEAR, ~0ull);
13383 /* RCV_ERR_FORCE leave alone */
13384 for (i = 0; i < 32; i++)
13385 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
13386 for (i = 0; i < 4; i++)
13387 write_csr(dd, RCV_PARTITION_KEY + (8 * i), 0);
13388 for (i = 0; i < RXE_NUM_32_BIT_COUNTERS; i++)
13389 write_csr(dd, RCV_COUNTER_ARRAY32 + (8 * i), 0);
13390 for (i = 0; i < RXE_NUM_64_BIT_COUNTERS; i++)
13391 write_csr(dd, RCV_COUNTER_ARRAY64 + (8 * i), 0);
13392 for (i = 0; i < RXE_NUM_RSM_INSTANCES; i++) {
13393 write_csr(dd, RCV_RSM_CFG + (8 * i), 0);
13394 write_csr(dd, RCV_RSM_SELECT + (8 * i), 0);
13395 write_csr(dd, RCV_RSM_MATCH + (8 * i), 0);
13396 }
13397 for (i = 0; i < 32; i++)
13398 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), 0);
13399
13400 /*
13401 * RXE Kernel and User Per-Context CSRs
13402 */
13403 for (i = 0; i < dd->chip_rcv_contexts; i++) {
13404 /* kernel */
13405 write_kctxt_csr(dd, i, RCV_CTXT_CTRL, 0);
13406 /* RCV_CTXT_STATUS read-only */
13407 write_kctxt_csr(dd, i, RCV_EGR_CTRL, 0);
13408 write_kctxt_csr(dd, i, RCV_TID_CTRL, 0);
13409 write_kctxt_csr(dd, i, RCV_KEY_CTRL, 0);
13410 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0);
13411 write_kctxt_csr(dd, i, RCV_HDR_CNT, 0);
13412 write_kctxt_csr(dd, i, RCV_HDR_ENT_SIZE, 0);
13413 write_kctxt_csr(dd, i, RCV_HDR_SIZE, 0);
13414 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0);
13415 write_kctxt_csr(dd, i, RCV_AVAIL_TIME_OUT, 0);
13416 write_kctxt_csr(dd, i, RCV_HDR_OVFL_CNT, 0);
13417
13418 /* user */
13419 /* RCV_HDR_TAIL read-only */
13420 write_uctxt_csr(dd, i, RCV_HDR_HEAD, 0);
13421 /* RCV_EGR_INDEX_TAIL read-only */
13422 write_uctxt_csr(dd, i, RCV_EGR_INDEX_HEAD, 0);
13423 /* RCV_EGR_OFFSET_TAIL read-only */
13424 for (j = 0; j < RXE_NUM_TID_FLOWS; j++) {
17fb4f29
JJ		 13425 write_uctxt_csr(dd, i,
13426 RCV_TID_FLOW_TABLE + (8 * j), 0);
77241056
MM		 13427 }
13428 }
13429}
13430
13431/*
13432 * Set sc2vl tables.
13433 *
13434 * They power on to zeros, so to avoid send context errors
13435 * they need to be set:
13436 *
13437 * SC 0-7 -> VL 0-7 (respectively)
13438 * SC 15 -> VL 15
13439 * otherwise
13440 * -> VL 0
13441 */
13442static void init_sc2vl_tables(struct hfi1_devdata *dd)
13443{
13444 int i;
13445 /* init per architecture spec, constrained by hardware capability */
13446
13447 /* HFI maps sent packets */
13448 write_csr(dd, SEND_SC2VLT0, SC2VL_VAL(
13449 0,
13450 0, 0, 1, 1,
13451 2, 2, 3, 3,
13452 4, 4, 5, 5,
13453 6, 6, 7, 7));
13454 write_csr(dd, SEND_SC2VLT1, SC2VL_VAL(
13455 1,
13456 8, 0, 9, 0,
13457 10, 0, 11, 0,
13458 12, 0, 13, 0,
13459 14, 0, 15, 15));
13460 write_csr(dd, SEND_SC2VLT2, SC2VL_VAL(
13461 2,
13462 16, 0, 17, 0,
13463 18, 0, 19, 0,
13464 20, 0, 21, 0,
13465 22, 0, 23, 0));
13466 write_csr(dd, SEND_SC2VLT3, SC2VL_VAL(
13467 3,
13468 24, 0, 25, 0,
13469 26, 0, 27, 0,
13470 28, 0, 29, 0,
13471 30, 0, 31, 0));
13472
13473 /* DC maps received packets */
13474 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, DC_SC_VL_VAL(
13475 15_0,
13476 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
13477 8, 0, 9, 0, 10, 0, 11, 0, 12, 0, 13, 0, 14, 0, 15, 15));
13478 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, DC_SC_VL_VAL(
13479 31_16,
13480 16, 0, 17, 0, 18, 0, 19, 0, 20, 0, 21, 0, 22, 0, 23, 0,
13481 24, 0, 25, 0, 26, 0, 27, 0, 28, 0, 29, 0, 30, 0, 31, 0));
13482
13483 /* initialize the cached sc2vl values consistently with h/w */
13484 for (i = 0; i < 32; i++) {
13485 if (i < 8 || i == 15)
13486 *((u8 *)(dd->sc2vl) + i) = (u8)i;
13487 else
13488 *((u8 *)(dd->sc2vl) + i) = 0;
13489 }
13490}
13491
13492/*
13493 * Read chip sizes and then reset parts to sane, disabled, values. We cannot
13494 * depend on the chip going through a power-on reset - a driver may be loaded
13495 * and unloaded many times.
13496 *
13497 * Do not write any CSR values to the chip in this routine - there may be
13498 * a reset following the (possible) FLR in this routine.
13499 *
13500 */
13501static void init_chip(struct hfi1_devdata *dd)
13502{
13503 int i;
13504
13505 /*
13506 * Put the HFI CSRs in a known state.
13507 * Combine this with a DC reset.
13508 *
13509 * Stop the device from doing anything while we do a
13510 * reset. We know there are no other active users of
13511 * the device since we are now in charge. Turn off
13512 * off all outbound and inbound traffic and make sure
13513 * the device does not generate any interrupts.
13514 */
13515
13516 /* disable send contexts and SDMA engines */
13517 write_csr(dd, SEND_CTRL, 0);
13518 for (i = 0; i < dd->chip_send_contexts; i++)
13519 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0);
13520 for (i = 0; i < dd->chip_sdma_engines; i++)
13521 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0);
13522 /* disable port (turn off RXE inbound traffic) and contexts */
13523 write_csr(dd, RCV_CTRL, 0);
13524 for (i = 0; i < dd->chip_rcv_contexts; i++)
13525 write_csr(dd, RCV_CTXT_CTRL, 0);
13526 /* mask all interrupt sources */
13527 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
8638b77f 13528 write_csr(dd, CCE_INT_MASK + (8 * i), 0ull);
77241056
MM		 13529
13530 /*
13531 * DC Reset: do a full DC reset before the register clear.
13532 * A recommended length of time to hold is one CSR read,
13533 * so reread the CceDcCtrl. Then, hold the DC in reset
13534 * across the clear.
13535 */
13536 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK);
50e5dcbe 13537 (void)read_csr(dd, CCE_DC_CTRL);
77241056
MM		 13538
13539 if (use_flr) {
13540 /*
13541 * A FLR will reset the SPC core and part of the PCIe.
13542 * The parts that need to be restored have already been
13543 * saved.
13544 */
13545 dd_dev_info(dd, "Resetting CSRs with FLR\n");
13546
13547 /* do the FLR, the DC reset will remain */
13548 hfi1_pcie_flr(dd);
13549
13550 /* restore command and BARs */
13551 restore_pci_variables(dd);
13552
995deafa 13553 if (is_ax(dd)) {
77241056
MM		 13554 dd_dev_info(dd, "Resetting CSRs with FLR\n");
13555 hfi1_pcie_flr(dd);
13556 restore_pci_variables(dd);
13557 }
77241056
MM		 13558 } else {
13559 dd_dev_info(dd, "Resetting CSRs with writes\n");
13560 reset_cce_csrs(dd);
13561 reset_txe_csrs(dd);
13562 reset_rxe_csrs(dd);
77241056
MM		 13563 reset_misc_csrs(dd);
13564 }
13565 /* clear the DC reset */
13566 write_csr(dd, CCE_DC_CTRL, 0);
7c03ed85 13567
77241056 13568 /* Set the LED off */
773d0451
SS		 13569 setextled(dd, 0);
13570
77241056
MM		 13571 /*
13572 * Clear the QSFP reset.
72a67ba2 13573 * An FLR enforces a 0 on all out pins. The driver does not touch
77241056 13574 * ASIC_QSFPn_OUT otherwise. This leaves RESET_N low and
72a67ba2 13575 * anything plugged constantly in reset, if it pays attention
77241056 13576 * to RESET_N.
72a67ba2 13577 * Prime examples of this are optical cables. Set all pins high.
77241056
MM		 13578 * I2CCLK and I2CDAT will change per direction, and INT_N and
13579 * MODPRS_N are input only and their value is ignored.
13580 */
72a67ba2
EH		 13581 write_csr(dd, ASIC_QSFP1_OUT, 0x1f);
13582 write_csr(dd, ASIC_QSFP2_OUT, 0x1f);
a2ee27a4 13583 init_chip_resources(dd);
77241056
MM		 13584}
13585
13586static void init_early_variables(struct hfi1_devdata *dd)
13587{
13588 int i;
13589
13590 /* assign link credit variables */
13591 dd->vau = CM_VAU;
13592 dd->link_credits = CM_GLOBAL_CREDITS;
995deafa 13593 if (is_ax(dd))
77241056
MM		 13594 dd->link_credits--;
13595 dd->vcu = cu_to_vcu(hfi1_cu);
13596 /* enough room for 8 MAD packets plus header - 17K */
13597 dd->vl15_init = (8 * (2048 + 128)) / vau_to_au(dd->vau);
13598 if (dd->vl15_init > dd->link_credits)
13599 dd->vl15_init = dd->link_credits;
13600
13601 write_uninitialized_csrs_and_memories(dd);
13602
13603 if (HFI1_CAP_IS_KSET(PKEY_CHECK))
13604 for (i = 0; i < dd->num_pports; i++) {
13605 struct hfi1_pportdata *ppd = &dd->pport[i];
13606
13607 set_partition_keys(ppd);
13608 }
13609 init_sc2vl_tables(dd);
13610}
13611
13612static void init_kdeth_qp(struct hfi1_devdata *dd)
13613{
13614 /* user changed the KDETH_QP */
13615 if (kdeth_qp != 0 && kdeth_qp >= 0xff) {
13616 /* out of range or illegal value */
13617 dd_dev_err(dd, "Invalid KDETH queue pair prefix, ignoring");
13618 kdeth_qp = 0;
13619 }
13620 if (kdeth_qp == 0) /* not set, or failed range check */
13621 kdeth_qp = DEFAULT_KDETH_QP;
13622
13623 write_csr(dd, SEND_BTH_QP,
17fb4f29
JJ		 13624 (kdeth_qp & SEND_BTH_QP_KDETH_QP_MASK) <<
13625 SEND_BTH_QP_KDETH_QP_SHIFT);
77241056
MM		 13626
13627 write_csr(dd, RCV_BTH_QP,
17fb4f29
JJ		 13628 (kdeth_qp & RCV_BTH_QP_KDETH_QP_MASK) <<
13629 RCV_BTH_QP_KDETH_QP_SHIFT);
77241056
MM		 13630}
13631
13632/**
13633 * init_qpmap_table
13634 * @dd - device data
13635 * @first_ctxt - first context
13636 * @last_ctxt - first context
13637 *
13638 * This return sets the qpn mapping table that
13639 * is indexed by qpn[8:1].
13640 *
13641 * The routine will round robin the 256 settings
13642 * from first_ctxt to last_ctxt.
13643 *
13644 * The first/last looks ahead to having specialized
13645 * receive contexts for mgmt and bypass. Normal
13646 * verbs traffic will assumed to be on a range
13647 * of receive contexts.
13648 */
13649static void init_qpmap_table(struct hfi1_devdata *dd,
13650 u32 first_ctxt,
13651 u32 last_ctxt)
13652{
13653 u64 reg = 0;
13654 u64 regno = RCV_QP_MAP_TABLE;
13655 int i;
13656 u64 ctxt = first_ctxt;
13657
60d585ad 13658 for (i = 0; i < 256; i++) {
77241056 13659 reg |= ctxt << (8 * (i % 8));
77241056
MM		 13660 ctxt++;
13661 if (ctxt > last_ctxt)
13662 ctxt = first_ctxt;
60d585ad 13663 if (i % 8 == 7) {
77241056
MM		 13664 write_csr(dd, regno, reg);
13665 reg = 0;
13666 regno += 8;
13667 }
13668 }
77241056
MM		 13669
13670 add_rcvctrl(dd, RCV_CTRL_RCV_QP_MAP_ENABLE_SMASK
13671 | RCV_CTRL_RCV_BYPASS_ENABLE_SMASK);
13672}
13673
372cc85a
DL		 13674struct rsm_map_table {
13675 u64 map[NUM_MAP_REGS];
13676 unsigned int used;
13677};
13678
b12349ae
DL		 13679struct rsm_rule_data {
13680 u8 offset;
13681 u8 pkt_type;
13682 u32 field1_off;
13683 u32 field2_off;
13684 u32 index1_off;
13685 u32 index1_width;
13686 u32 index2_off;
13687 u32 index2_width;
13688 u32 mask1;
13689 u32 value1;
13690 u32 mask2;
13691 u32 value2;
13692};
13693
372cc85a
DL		 13694/*
13695 * Return an initialized RMT map table for users to fill in. OK if it
13696 * returns NULL, indicating no table.
13697 */
13698static struct rsm_map_table *alloc_rsm_map_table(struct hfi1_devdata *dd)
13699{
13700 struct rsm_map_table *rmt;
13701 u8 rxcontext = is_ax(dd) ? 0 : 0xff; /* 0 is default if a0 ver. */
13702
13703 rmt = kmalloc(sizeof(*rmt), GFP_KERNEL);
13704 if (rmt) {
13705 memset(rmt->map, rxcontext, sizeof(rmt->map));
13706 rmt->used = 0;
13707 }
13708
13709 return rmt;
13710}
13711
13712/*
13713 * Write the final RMT map table to the chip and free the table. OK if
13714 * table is NULL.
13715 */
13716static void complete_rsm_map_table(struct hfi1_devdata *dd,
13717 struct rsm_map_table *rmt)
13718{
13719 int i;
13720
13721 if (rmt) {
13722 /* write table to chip */
13723 for (i = 0; i < NUM_MAP_REGS; i++)
13724 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), rmt->map[i]);
13725
13726 /* enable RSM */
13727 add_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK);
13728 }
13729}
13730
b12349ae
DL		 13731/*
13732 * Add a receive side mapping rule.
13733 */
13734static void add_rsm_rule(struct hfi1_devdata *dd, u8 rule_index,
13735 struct rsm_rule_data *rrd)
13736{
13737 write_csr(dd, RCV_RSM_CFG + (8 * rule_index),
13738 (u64)rrd->offset << RCV_RSM_CFG_OFFSET_SHIFT |
13739 1ull << rule_index | /* enable bit */
13740 (u64)rrd->pkt_type << RCV_RSM_CFG_PACKET_TYPE_SHIFT);
13741 write_csr(dd, RCV_RSM_SELECT + (8 * rule_index),
13742 (u64)rrd->field1_off << RCV_RSM_SELECT_FIELD1_OFFSET_SHIFT |
13743 (u64)rrd->field2_off << RCV_RSM_SELECT_FIELD2_OFFSET_SHIFT |
13744 (u64)rrd->index1_off << RCV_RSM_SELECT_INDEX1_OFFSET_SHIFT |
13745 (u64)rrd->index1_width << RCV_RSM_SELECT_INDEX1_WIDTH_SHIFT |
13746 (u64)rrd->index2_off << RCV_RSM_SELECT_INDEX2_OFFSET_SHIFT |
13747 (u64)rrd->index2_width << RCV_RSM_SELECT_INDEX2_WIDTH_SHIFT);
13748 write_csr(dd, RCV_RSM_MATCH + (8 * rule_index),
13749 (u64)rrd->mask1 << RCV_RSM_MATCH_MASK1_SHIFT |
13750 (u64)rrd->value1 << RCV_RSM_MATCH_VALUE1_SHIFT |
13751 (u64)rrd->mask2 << RCV_RSM_MATCH_MASK2_SHIFT |
13752 (u64)rrd->value2 << RCV_RSM_MATCH_VALUE2_SHIFT);
13753}
13754
4a818bed
DL		 13755/* return the number of RSM map table entries that will be used for QOS */
13756static int qos_rmt_entries(struct hfi1_devdata *dd, unsigned int *mp,
13757 unsigned int *np)
13758{
13759 int i;
13760 unsigned int m, n;
13761 u8 max_by_vl = 0;
13762
13763 /* is QOS active at all? */
13764 if (dd->n_krcv_queues <= MIN_KERNEL_KCTXTS ||
13765 num_vls == 1 ||
13766 krcvqsset <= 1)
13767 goto no_qos;
13768
13769 /* determine bits for qpn */
13770 for (i = 0; i < min_t(unsigned int, num_vls, krcvqsset); i++)
13771 if (krcvqs[i] > max_by_vl)
13772 max_by_vl = krcvqs[i];
13773 if (max_by_vl > 32)
13774 goto no_qos;
13775 m = ilog2(__roundup_pow_of_two(max_by_vl));
13776
13777 /* determine bits for vl */
13778 n = ilog2(__roundup_pow_of_two(num_vls));
13779
13780 /* reject if too much is used */
13781 if ((m + n) > 7)
13782 goto no_qos;
13783
13784 if (mp)
13785 *mp = m;
13786 if (np)
13787 *np = n;
13788
13789 return 1 << (m + n);
13790
13791no_qos:
13792 if (mp)
13793 *mp = 0;
13794 if (np)
13795 *np = 0;
13796 return 0;
13797}
13798
77241056
MM		 13799/**
13800 * init_qos - init RX qos
13801 * @dd - device data
372cc85a 13802 * @rmt - RSM map table
77241056 13803 *
33a9eb52
DL		 13804 * This routine initializes Rule 0 and the RSM map table to implement
13805 * quality of service (qos).
77241056 13806 *
33a9eb52
DL		 13807 * If all of the limit tests succeed, qos is applied based on the array
13808 * interpretation of krcvqs where entry 0 is VL0.
77241056 13809 *
33a9eb52
DL		 13810 * The number of vl bits (n) and the number of qpn bits (m) are computed to
13811 * feed both the RSM map table and the single rule.
77241056 13812 */
372cc85a 13813static void init_qos(struct hfi1_devdata *dd, struct rsm_map_table *rmt)
77241056 13814{
b12349ae 13815 struct rsm_rule_data rrd;
77241056 13816 unsigned qpns_per_vl, ctxt, i, qpn, n = 1, m;
372cc85a 13817 unsigned int rmt_entries;
77241056 13818 u64 reg;
77241056 13819
4a818bed 13820 if (!rmt)
77241056 13821 goto bail;
4a818bed
DL		 13822 rmt_entries = qos_rmt_entries(dd, &m, &n);
13823 if (rmt_entries == 0)
77241056 13824 goto bail;
4a818bed
DL		 13825 qpns_per_vl = 1 << m;
13826
372cc85a
DL		 13827 /* enough room in the map table? */
13828 rmt_entries = 1 << (m + n);
13829 if (rmt->used + rmt_entries >= NUM_MAP_ENTRIES)
859bcad9 13830 goto bail;
4a818bed 13831
372cc85a 13832 /* add qos entries to the the RSM map table */
33a9eb52 13833 for (i = 0, ctxt = FIRST_KERNEL_KCTXT; i < num_vls; i++) {
77241056
MM		 13834 unsigned tctxt;
13835
13836 for (qpn = 0, tctxt = ctxt;
13837 krcvqs[i] && qpn < qpns_per_vl; qpn++) {
13838 unsigned idx, regoff, regidx;
13839
372cc85a
DL		 13840 /* generate the index the hardware will produce */
13841 idx = rmt->used + ((qpn << n) ^ i);
77241056
MM		 13842 regoff = (idx % 8) * 8;
13843 regidx = idx / 8;
372cc85a
DL		 13844 /* replace default with context number */
13845 reg = rmt->map[regidx];
77241056
MM		 13846 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK
13847 << regoff);
13848 reg |= (u64)(tctxt++) << regoff;
372cc85a 13849 rmt->map[regidx] = reg;
77241056
MM		 13850 if (tctxt == ctxt + krcvqs[i])
13851 tctxt = ctxt;
13852 }
13853 ctxt += krcvqs[i];
13854 }
b12349ae
DL		 13855
13856 rrd.offset = rmt->used;
13857 rrd.pkt_type = 2;
13858 rrd.field1_off = LRH_BTH_MATCH_OFFSET;
13859 rrd.field2_off = LRH_SC_MATCH_OFFSET;
13860 rrd.index1_off = LRH_SC_SELECT_OFFSET;
13861 rrd.index1_width = n;
13862 rrd.index2_off = QPN_SELECT_OFFSET;
13863 rrd.index2_width = m + n;
13864 rrd.mask1 = LRH_BTH_MASK;
13865 rrd.value1 = LRH_BTH_VALUE;
13866 rrd.mask2 = LRH_SC_MASK;
13867 rrd.value2 = LRH_SC_VALUE;
13868
13869 /* add rule 0 */
13870 add_rsm_rule(dd, 0, &rrd);
13871
372cc85a
DL		 13872 /* mark RSM map entries as used */
13873 rmt->used += rmt_entries;
33a9eb52
DL		 13874 /* map everything else to the mcast/err/vl15 context */
13875 init_qpmap_table(dd, HFI1_CTRL_CTXT, HFI1_CTRL_CTXT);
77241056
MM		 13876 dd->qos_shift = n + 1;
13877 return;
13878bail:
13879 dd->qos_shift = 1;
82c2611d 13880 init_qpmap_table(dd, FIRST_KERNEL_KCTXT, dd->n_krcv_queues - 1);
77241056
MM		 13881}
13882
8f000f7f
DL		 13883static void init_user_fecn_handling(struct hfi1_devdata *dd,
13884 struct rsm_map_table *rmt)
13885{
13886 struct rsm_rule_data rrd;
13887 u64 reg;
13888 int i, idx, regoff, regidx;
13889 u8 offset;
13890
13891 /* there needs to be enough room in the map table */
13892 if (rmt->used + dd->num_user_contexts >= NUM_MAP_ENTRIES) {
13893 dd_dev_err(dd, "User FECN handling disabled - too many user contexts allocated\n");
13894 return;
13895 }
13896
13897 /*
13898 * RSM will extract the destination context as an index into the
13899 * map table. The destination contexts are a sequential block
13900 * in the range first_user_ctxt...num_rcv_contexts-1 (inclusive).
13901 * Map entries are accessed as offset + extracted value. Adjust
13902 * the added offset so this sequence can be placed anywhere in
13903 * the table - as long as the entries themselves do not wrap.
13904 * There are only enough bits in offset for the table size, so
13905 * start with that to allow for a "negative" offset.
13906 */
13907 offset = (u8)(NUM_MAP_ENTRIES + (int)rmt->used -
13908 (int)dd->first_user_ctxt);
13909
13910 for (i = dd->first_user_ctxt, idx = rmt->used;
13911 i < dd->num_rcv_contexts; i++, idx++) {
13912 /* replace with identity mapping */
13913 regoff = (idx % 8) * 8;
13914 regidx = idx / 8;
13915 reg = rmt->map[regidx];
13916 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK << regoff);
13917 reg |= (u64)i << regoff;
13918 rmt->map[regidx] = reg;
13919 }
13920
13921 /*
13922 * For RSM intercept of Expected FECN packets:
13923 * o packet type 0 - expected
13924 * o match on F (bit 95), using select/match 1, and
13925 * o match on SH (bit 133), using select/match 2.
13926 *
13927 * Use index 1 to extract the 8-bit receive context from DestQP
13928 * (start at bit 64). Use that as the RSM map table index.
13929 */
13930 rrd.offset = offset;
13931 rrd.pkt_type = 0;
13932 rrd.field1_off = 95;
13933 rrd.field2_off = 133;
13934 rrd.index1_off = 64;
13935 rrd.index1_width = 8;
13936 rrd.index2_off = 0;
13937 rrd.index2_width = 0;
13938 rrd.mask1 = 1;
13939 rrd.value1 = 1;
13940 rrd.mask2 = 1;
13941 rrd.value2 = 1;
13942
13943 /* add rule 1 */
13944 add_rsm_rule(dd, 1, &rrd);
13945
13946 rmt->used += dd->num_user_contexts;
13947}
13948
77241056
MM		 13949static void init_rxe(struct hfi1_devdata *dd)
13950{
372cc85a
DL		 13951 struct rsm_map_table *rmt;
13952
77241056
MM		 13953 /* enable all receive errors */
13954 write_csr(dd, RCV_ERR_MASK, ~0ull);
372cc85a
DL		 13955
13956 rmt = alloc_rsm_map_table(dd);
13957 /* set up QOS, including the QPN map table */
13958 init_qos(dd, rmt);
8f000f7f 13959 init_user_fecn_handling(dd, rmt);
372cc85a
DL		 13960 complete_rsm_map_table(dd, rmt);
13961 kfree(rmt);
13962
77241056
MM		 13963 /*
13964 * make sure RcvCtrl.RcvWcb <= PCIe Device Control
13965 * Register Max_Payload_Size (PCI_EXP_DEVCTL in Linux PCIe config
13966 * space, PciCfgCap2.MaxPayloadSize in HFI). There is only one
13967 * invalid configuration: RcvCtrl.RcvWcb set to its max of 256 and
13968 * Max_PayLoad_Size set to its minimum of 128.
13969 *
13970 * Presently, RcvCtrl.RcvWcb is not modified from its default of 0
13971 * (64 bytes). Max_Payload_Size is possibly modified upward in
13972 * tune_pcie_caps() which is called after this routine.
13973 */
13974}
13975
13976static void init_other(struct hfi1_devdata *dd)
13977{
13978 /* enable all CCE errors */
13979 write_csr(dd, CCE_ERR_MASK, ~0ull);
13980 /* enable *some* Misc errors */
13981 write_csr(dd, MISC_ERR_MASK, DRIVER_MISC_MASK);
13982 /* enable all DC errors, except LCB */
13983 write_csr(dd, DCC_ERR_FLG_EN, ~0ull);
13984 write_csr(dd, DC_DC8051_ERR_EN, ~0ull);
13985}
13986
13987/*
13988 * Fill out the given AU table using the given CU. A CU is defined in terms
13989 * AUs. The table is a an encoding: given the index, how many AUs does that
13990 * represent?
13991 *
13992 * NOTE: Assumes that the register layout is the same for the
13993 * local and remote tables.
13994 */
13995static void assign_cm_au_table(struct hfi1_devdata *dd, u32 cu,
13996 u32 csr0to3, u32 csr4to7)
13997{
13998 write_csr(dd, csr0to3,
17fb4f29
JJ		 13999 0ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE0_SHIFT |
14000 1ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE1_SHIFT |
14001 2ull * cu <<
14002 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE2_SHIFT |
14003 4ull * cu <<
14004 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE3_SHIFT);
77241056 14005 write_csr(dd, csr4to7,
17fb4f29
JJ		 14006 8ull * cu <<
14007 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE4_SHIFT |
14008 16ull * cu <<
14009 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE5_SHIFT |
14010 32ull * cu <<
14011 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE6_SHIFT |
14012 64ull * cu <<
14013 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE7_SHIFT);
77241056
MM		 14014}
14015
14016static void assign_local_cm_au_table(struct hfi1_devdata *dd, u8 vcu)
14017{
14018 assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_LOCAL_AU_TABLE0_TO3,
17fb4f29 14019 SEND_CM_LOCAL_AU_TABLE4_TO7);
77241056
MM		 14020}
14021
14022void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu)
14023{
14024 assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_REMOTE_AU_TABLE0_TO3,
17fb4f29 14025 SEND_CM_REMOTE_AU_TABLE4_TO7);
77241056
MM		 14026}
14027
14028static void init_txe(struct hfi1_devdata *dd)
14029{
14030 int i;
14031
14032 /* enable all PIO, SDMA, general, and Egress errors */
14033 write_csr(dd, SEND_PIO_ERR_MASK, ~0ull);
14034 write_csr(dd, SEND_DMA_ERR_MASK, ~0ull);
14035 write_csr(dd, SEND_ERR_MASK, ~0ull);
14036 write_csr(dd, SEND_EGRESS_ERR_MASK, ~0ull);
14037
14038 /* enable all per-context and per-SDMA engine errors */
14039 for (i = 0; i < dd->chip_send_contexts; i++)
14040 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, ~0ull);
14041 for (i = 0; i < dd->chip_sdma_engines; i++)
14042 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, ~0ull);
14043
14044 /* set the local CU to AU mapping */
14045 assign_local_cm_au_table(dd, dd->vcu);
14046
14047 /*
14048 * Set reasonable default for Credit Return Timer
14049 * Don't set on Simulator - causes it to choke.
14050 */
14051 if (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)
14052 write_csr(dd, SEND_CM_TIMER_CTRL, HFI1_CREDIT_RETURN_RATE);
14053}
14054
14055int hfi1_set_ctxt_jkey(struct hfi1_devdata *dd, unsigned ctxt, u16 jkey)
14056{
14057 struct hfi1_ctxtdata *rcd = dd->rcd[ctxt];
14058 unsigned sctxt;
14059 int ret = 0;
14060 u64 reg;
14061
14062 if (!rcd || !rcd->sc) {
14063 ret = -EINVAL;
14064 goto done;
14065 }
14066 sctxt = rcd->sc->hw_context;
14067 reg = SEND_CTXT_CHECK_JOB_KEY_MASK_SMASK | /* mask is always 1's */
14068 ((jkey & SEND_CTXT_CHECK_JOB_KEY_VALUE_MASK) <<
14069 SEND_CTXT_CHECK_JOB_KEY_VALUE_SHIFT);
14070 /* JOB_KEY_ALLOW_PERMISSIVE is not allowed by default */
14071 if (HFI1_CAP_KGET_MASK(rcd->flags, ALLOW_PERM_JKEY))
14072 reg |= SEND_CTXT_CHECK_JOB_KEY_ALLOW_PERMISSIVE_SMASK;
14073 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_JOB_KEY, reg);
14074 /*
14075 * Enable send-side J_KEY integrity check, unless this is A0 h/w
77241056 14076 */
995deafa 14077 if (!is_ax(dd)) {
77241056
MM		 14078 reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
14079 reg |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
14080 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
14081 }
14082
14083 /* Enable J_KEY check on receive context. */
14084 reg = RCV_KEY_CTRL_JOB_KEY_ENABLE_SMASK |
14085 ((jkey & RCV_KEY_CTRL_JOB_KEY_VALUE_MASK) <<
14086 RCV_KEY_CTRL_JOB_KEY_VALUE_SHIFT);
14087 write_kctxt_csr(dd, ctxt, RCV_KEY_CTRL, reg);
14088done:
14089 return ret;
14090}
14091
14092int hfi1_clear_ctxt_jkey(struct hfi1_devdata *dd, unsigned ctxt)
14093{
14094 struct hfi1_ctxtdata *rcd = dd->rcd[ctxt];
14095 unsigned sctxt;
14096 int ret = 0;
14097 u64 reg;
14098
14099 if (!rcd || !rcd->sc) {
14100 ret = -EINVAL;
14101 goto done;
14102 }
14103 sctxt = rcd->sc->hw_context;
14104 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_JOB_KEY, 0);
14105 /*
14106 * Disable send-side J_KEY integrity check, unless this is A0 h/w.
14107 * This check would not have been enabled for A0 h/w, see
14108 * set_ctxt_jkey().
14109 */
995deafa 14110 if (!is_ax(dd)) {
77241056
MM		 14111 reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
14112 reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
14113 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
14114 }
14115 /* Turn off the J_KEY on the receive side */
14116 write_kctxt_csr(dd, ctxt, RCV_KEY_CTRL, 0);
14117done:
14118 return ret;
14119}
14120
14121int hfi1_set_ctxt_pkey(struct hfi1_devdata *dd, unsigned ctxt, u16 pkey)
14122{
14123 struct hfi1_ctxtdata *rcd;
14124 unsigned sctxt;
14125 int ret = 0;
14126 u64 reg;
14127
e490974e 14128 if (ctxt < dd->num_rcv_contexts) {
77241056 14129 rcd = dd->rcd[ctxt];
e490974e 14130 } else {
77241056
MM		 14131 ret = -EINVAL;
14132 goto done;
14133 }
14134 if (!rcd || !rcd->sc) {
14135 ret = -EINVAL;
14136 goto done;
14137 }
14138 sctxt = rcd->sc->hw_context;
14139 reg = ((u64)pkey & SEND_CTXT_CHECK_PARTITION_KEY_VALUE_MASK) <<
14140 SEND_CTXT_CHECK_PARTITION_KEY_VALUE_SHIFT;
14141 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_PARTITION_KEY, reg);
14142 reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
14143 reg |= SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK;
e38d1e4f 14144 reg &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK;
77241056
MM		 14145 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
14146done:
14147 return ret;
14148}
14149
14150int hfi1_clear_ctxt_pkey(struct hfi1_devdata *dd, unsigned ctxt)
14151{
14152 struct hfi1_ctxtdata *rcd;
14153 unsigned sctxt;
14154 int ret = 0;
14155 u64 reg;
14156
e490974e 14157 if (ctxt < dd->num_rcv_contexts) {
77241056 14158 rcd = dd->rcd[ctxt];
e490974e 14159 } else {
77241056
MM		 14160 ret = -EINVAL;
14161 goto done;
14162 }
14163 if (!rcd || !rcd->sc) {
14164 ret = -EINVAL;
14165 goto done;
14166 }
14167 sctxt = rcd->sc->hw_context;
14168 reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
14169 reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK;
14170 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
14171 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_PARTITION_KEY, 0);
14172done:
14173 return ret;
14174}
14175
14176/*
14177 * Start doing the clean up the the chip. Our clean up happens in multiple
14178 * stages and this is just the first.
14179 */
14180void hfi1_start_cleanup(struct hfi1_devdata *dd)
14181{
affa48de 14182 aspm_exit(dd);
77241056
MM		 14183 free_cntrs(dd);
14184 free_rcverr(dd);
14185 clean_up_interrupts(dd);
a2ee27a4 14186 finish_chip_resources(dd);
77241056
MM		 14187}
14188
14189#define HFI_BASE_GUID(dev) \
14190 ((dev)->base_guid & ~(1ULL << GUID_HFI_INDEX_SHIFT))
14191
14192/*
78eb129d
DL		 14193 * Information can be shared between the two HFIs on the same ASIC
14194 * in the same OS. This function finds the peer device and sets
14195 * up a shared structure.
77241056 14196 */
78eb129d 14197static int init_asic_data(struct hfi1_devdata *dd)
77241056
MM		 14198{
14199 unsigned long flags;
14200 struct hfi1_devdata *tmp, *peer = NULL;
98f179a5 14201 struct hfi1_asic_data *asic_data;
78eb129d 14202 int ret = 0;
77241056 14203
98f179a5
TS		 14204 /* pre-allocate the asic structure in case we are the first device */
14205 asic_data = kzalloc(sizeof(*dd->asic_data), GFP_KERNEL);
14206 if (!asic_data)
14207 return -ENOMEM;
14208
77241056
MM		 14209 spin_lock_irqsave(&hfi1_devs_lock, flags);
14210 /* Find our peer device */
14211 list_for_each_entry(tmp, &hfi1_dev_list, list) {
14212 if ((HFI_BASE_GUID(dd) == HFI_BASE_GUID(tmp)) &&
14213 dd->unit != tmp->unit) {
14214 peer = tmp;
14215 break;
14216 }
14217 }
14218
78eb129d 14219 if (peer) {
98f179a5 14220 /* use already allocated structure */
78eb129d 14221 dd->asic_data = peer->asic_data;
98f179a5 14222 kfree(asic_data);
78eb129d 14223 } else {
98f179a5 14224 dd->asic_data = asic_data;
78eb129d
DL		 14225 mutex_init(&dd->asic_data->asic_resource_mutex);
14226 }
14227 dd->asic_data->dds[dd->hfi1_id] = dd; /* self back-pointer */
77241056 14228 spin_unlock_irqrestore(&hfi1_devs_lock, flags);
dba715f0
DL		 14229
14230 /* first one through - set up i2c devices */
14231 if (!peer)
14232 ret = set_up_i2c(dd, dd->asic_data);
14233
78eb129d 14234 return ret;
77241056
MM		 14235}
14236
5d9157aa
DL		 14237/*
14238 * Set dd->boardname. Use a generic name if a name is not returned from
14239 * EFI variable space.
14240 *
14241 * Return 0 on success, -ENOMEM if space could not be allocated.
14242 */
14243static int obtain_boardname(struct hfi1_devdata *dd)
14244{
14245 /* generic board description */
14246 const char generic[] =
14247 "Intel Omni-Path Host Fabric Interface Adapter 100 Series";
14248 unsigned long size;
14249 int ret;
14250
14251 ret = read_hfi1_efi_var(dd, "description", &size,
14252 (void **)&dd->boardname);
14253 if (ret) {
845f876d 14254 dd_dev_info(dd, "Board description not found\n");
5d9157aa
DL		 14255 /* use generic description */
14256 dd->boardname = kstrdup(generic, GFP_KERNEL);
14257 if (!dd->boardname)
14258 return -ENOMEM;
14259 }
14260 return 0;
14261}
14262
24487dd3
KW		 14263/*
14264 * Check the interrupt registers to make sure that they are mapped correctly.
14265 * It is intended to help user identify any mismapping by VMM when the driver
14266 * is running in a VM. This function should only be called before interrupt
14267 * is set up properly.
14268 *
14269 * Return 0 on success, -EINVAL on failure.
14270 */
14271static int check_int_registers(struct hfi1_devdata *dd)
14272{
14273 u64 reg;
14274 u64 all_bits = ~(u64)0;
14275 u64 mask;
14276
14277 /* Clear CceIntMask[0] to avoid raising any interrupts */
14278 mask = read_csr(dd, CCE_INT_MASK);
14279 write_csr(dd, CCE_INT_MASK, 0ull);
14280 reg = read_csr(dd, CCE_INT_MASK);
14281 if (reg)
14282 goto err_exit;
14283
14284 /* Clear all interrupt status bits */
14285 write_csr(dd, CCE_INT_CLEAR, all_bits);
14286 reg = read_csr(dd, CCE_INT_STATUS);
14287 if (reg)
14288 goto err_exit;
14289
14290 /* Set all interrupt status bits */
14291 write_csr(dd, CCE_INT_FORCE, all_bits);
14292 reg = read_csr(dd, CCE_INT_STATUS);
14293 if (reg != all_bits)
14294 goto err_exit;
14295
14296 /* Restore the interrupt mask */
14297 write_csr(dd, CCE_INT_CLEAR, all_bits);
14298 write_csr(dd, CCE_INT_MASK, mask);
14299
14300 return 0;
14301err_exit:
14302 write_csr(dd, CCE_INT_MASK, mask);
14303 dd_dev_err(dd, "Interrupt registers not properly mapped by VMM\n");
14304 return -EINVAL;
14305}
14306
77241056 14307/**
7c03ed85 14308 * Allocate and initialize the device structure for the hfi.
77241056
MM		 14309 * @dev: the pci_dev for hfi1_ib device
14310 * @ent: pci_device_id struct for this dev
14311 *
14312 * Also allocates, initializes, and returns the devdata struct for this
14313 * device instance
14314 *
14315 * This is global, and is called directly at init to set up the
14316 * chip-specific function pointers for later use.
14317 */
14318struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev,
14319 const struct pci_device_id *ent)
14320{
14321 struct hfi1_devdata *dd;
14322 struct hfi1_pportdata *ppd;
14323 u64 reg;
14324 int i, ret;
14325 static const char * const inames[] = { /* implementation names */
14326 "RTL silicon",
14327 "RTL VCS simulation",
14328 "RTL FPGA emulation",
14329 "Functional simulator"
14330 };
24487dd3 14331 struct pci_dev *parent = pdev->bus->self;
77241056 14332
17fb4f29
JJ		 14333 dd = hfi1_alloc_devdata(pdev, NUM_IB_PORTS *
14334 sizeof(struct hfi1_pportdata));
77241056
MM		 14335 if (IS_ERR(dd))
14336 goto bail;
14337 ppd = dd->pport;
14338 for (i = 0; i < dd->num_pports; i++, ppd++) {
14339 int vl;
14340 /* init common fields */
14341 hfi1_init_pportdata(pdev, ppd, dd, 0, 1);
14342 /* DC supports 4 link widths */
14343 ppd->link_width_supported =
14344 OPA_LINK_WIDTH_1X | OPA_LINK_WIDTH_2X |
14345 OPA_LINK_WIDTH_3X | OPA_LINK_WIDTH_4X;
14346 ppd->link_width_downgrade_supported =
14347 ppd->link_width_supported;
14348 /* start out enabling only 4X */
14349 ppd->link_width_enabled = OPA_LINK_WIDTH_4X;
14350 ppd->link_width_downgrade_enabled =
14351 ppd->link_width_downgrade_supported;
14352 /* link width active is 0 when link is down */
14353 /* link width downgrade active is 0 when link is down */
14354
d0d236ea
JJ		 14355 if (num_vls < HFI1_MIN_VLS_SUPPORTED ||
14356 num_vls > HFI1_MAX_VLS_SUPPORTED) {
77241056
MM		 14357 hfi1_early_err(&pdev->dev,
14358 "Invalid num_vls %u, using %u VLs\n",
14359 num_vls, HFI1_MAX_VLS_SUPPORTED);
14360 num_vls = HFI1_MAX_VLS_SUPPORTED;
14361 }
14362 ppd->vls_supported = num_vls;
14363 ppd->vls_operational = ppd->vls_supported;
8a4d3444 14364 ppd->actual_vls_operational = ppd->vls_supported;
77241056
MM		 14365 /* Set the default MTU. */
14366 for (vl = 0; vl < num_vls; vl++)
14367 dd->vld[vl].mtu = hfi1_max_mtu;
14368 dd->vld[15].mtu = MAX_MAD_PACKET;
14369 /*
14370 * Set the initial values to reasonable default, will be set
14371 * for real when link is up.
14372 */
14373 ppd->lstate = IB_PORT_DOWN;
14374 ppd->overrun_threshold = 0x4;
14375 ppd->phy_error_threshold = 0xf;
14376 ppd->port_crc_mode_enabled = link_crc_mask;
14377 /* initialize supported LTP CRC mode */
14378 ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8;
14379 /* initialize enabled LTP CRC mode */
14380 ppd->port_ltp_crc_mode |= cap_to_port_ltp(link_crc_mask) << 4;
14381 /* start in offline */
14382 ppd->host_link_state = HLS_DN_OFFLINE;
14383 init_vl_arb_caches(ppd);
f45c8dc8 14384 ppd->last_pstate = 0xff; /* invalid value */
77241056
MM		 14385 }
14386
14387 dd->link_default = HLS_DN_POLL;
14388
14389 /*
14390 * Do remaining PCIe setup and save PCIe values in dd.
14391 * Any error printing is already done by the init code.
14392 * On return, we have the chip mapped.
14393 */
14394 ret = hfi1_pcie_ddinit(dd, pdev, ent);
14395 if (ret < 0)
14396 goto bail_free;
14397
14398 /* verify that reads actually work, save revision for reset check */
14399 dd->revision = read_csr(dd, CCE_REVISION);
14400 if (dd->revision == ~(u64)0) {
14401 dd_dev_err(dd, "cannot read chip CSRs\n");
14402 ret = -EINVAL;
14403 goto bail_cleanup;
14404 }
14405 dd->majrev = (dd->revision >> CCE_REVISION_CHIP_REV_MAJOR_SHIFT)
14406 & CCE_REVISION_CHIP_REV_MAJOR_MASK;
14407 dd->minrev = (dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT)
14408 & CCE_REVISION_CHIP_REV_MINOR_MASK;
14409
24487dd3
KW		 14410 /*
14411 * Check interrupt registers mapping if the driver has no access to
14412 * the upstream component. In this case, it is likely that the driver
14413 * is running in a VM.
14414 */
14415 if (!parent) {
14416 ret = check_int_registers(dd);
14417 if (ret)
14418 goto bail_cleanup;
14419 }
14420
4d114fdd
JJ		 14421 /*
14422 * obtain the hardware ID - NOT related to unit, which is a
14423 * software enumeration
14424 */
77241056
MM		 14425 reg = read_csr(dd, CCE_REVISION2);
14426 dd->hfi1_id = (reg >> CCE_REVISION2_HFI_ID_SHIFT)
14427 & CCE_REVISION2_HFI_ID_MASK;
14428 /* the variable size will remove unwanted bits */
14429 dd->icode = reg >> CCE_REVISION2_IMPL_CODE_SHIFT;
14430 dd->irev = reg >> CCE_REVISION2_IMPL_REVISION_SHIFT;
14431 dd_dev_info(dd, "Implementation: %s, revision 0x%x\n",
17fb4f29
JJ		 14432 dd->icode < ARRAY_SIZE(inames) ?
14433 inames[dd->icode] : "unknown", (int)dd->irev);
77241056
MM		 14434
14435 /* speeds the hardware can support */
14436 dd->pport->link_speed_supported = OPA_LINK_SPEED_25G;
14437 /* speeds allowed to run at */
14438 dd->pport->link_speed_enabled = dd->pport->link_speed_supported;
14439 /* give a reasonable active value, will be set on link up */
14440 dd->pport->link_speed_active = OPA_LINK_SPEED_25G;
14441
14442 dd->chip_rcv_contexts = read_csr(dd, RCV_CONTEXTS);
14443 dd->chip_send_contexts = read_csr(dd, SEND_CONTEXTS);
14444 dd->chip_sdma_engines = read_csr(dd, SEND_DMA_ENGINES);
14445 dd->chip_pio_mem_size = read_csr(dd, SEND_PIO_MEM_SIZE);
14446 dd->chip_sdma_mem_size = read_csr(dd, SEND_DMA_MEM_SIZE);
14447 /* fix up link widths for emulation _p */
14448 ppd = dd->pport;
14449 if (dd->icode == ICODE_FPGA_EMULATION && is_emulator_p(dd)) {
14450 ppd->link_width_supported =
14451 ppd->link_width_enabled =
14452 ppd->link_width_downgrade_supported =
14453 ppd->link_width_downgrade_enabled =
14454 OPA_LINK_WIDTH_1X;
14455 }
14456 /* insure num_vls isn't larger than number of sdma engines */
14457 if (HFI1_CAP_IS_KSET(SDMA) && num_vls > dd->chip_sdma_engines) {
14458 dd_dev_err(dd, "num_vls %u too large, using %u VLs\n",
11a5909b
DL		 14459 num_vls, dd->chip_sdma_engines);
14460 num_vls = dd->chip_sdma_engines;
14461 ppd->vls_supported = dd->chip_sdma_engines;
8a4d3444 14462 ppd->vls_operational = ppd->vls_supported;
77241056
MM		 14463 }
14464
14465 /*
14466 * Convert the ns parameter to the 64 * cclocks used in the CSR.
14467 * Limit the max if larger than the field holds. If timeout is
14468 * non-zero, then the calculated field will be at least 1.
14469 *
14470 * Must be after icode is set up - the cclock rate depends
14471 * on knowing the hardware being used.
14472 */
14473 dd->rcv_intr_timeout_csr = ns_to_cclock(dd, rcv_intr_timeout) / 64;
14474 if (dd->rcv_intr_timeout_csr >
14475 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK)
14476 dd->rcv_intr_timeout_csr =
14477 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK;
14478 else if (dd->rcv_intr_timeout_csr == 0 && rcv_intr_timeout)
14479 dd->rcv_intr_timeout_csr = 1;
14480
7c03ed85
EH		 14481 /* needs to be done before we look for the peer device */
14482 read_guid(dd);
14483
78eb129d
DL		 14484 /* set up shared ASIC data with peer device */
14485 ret = init_asic_data(dd);
14486 if (ret)
14487 goto bail_cleanup;
7c03ed85 14488
77241056
MM		 14489 /* obtain chip sizes, reset chip CSRs */
14490 init_chip(dd);
14491
14492 /* read in the PCIe link speed information */
14493 ret = pcie_speeds(dd);
14494 if (ret)
14495 goto bail_cleanup;
14496
c3838b39
EH		 14497 /* Needs to be called before hfi1_firmware_init */
14498 get_platform_config(dd);
14499
77241056
MM		 14500 /* read in firmware */
14501 ret = hfi1_firmware_init(dd);
14502 if (ret)
14503 goto bail_cleanup;
14504
14505 /*
14506 * In general, the PCIe Gen3 transition must occur after the
14507 * chip has been idled (so it won't initiate any PCIe transactions
14508 * e.g. an interrupt) and before the driver changes any registers
14509 * (the transition will reset the registers).
14510 *
14511 * In particular, place this call after:
14512 * - init_chip() - the chip will not initiate any PCIe transactions
14513 * - pcie_speeds() - reads the current link speed
14514 * - hfi1_firmware_init() - the needed firmware is ready to be
14515 * downloaded
14516 */
14517 ret = do_pcie_gen3_transition(dd);
14518 if (ret)
14519 goto bail_cleanup;
14520
14521 /* start setting dd values and adjusting CSRs */
14522 init_early_variables(dd);
14523
14524 parse_platform_config(dd);
14525
5d9157aa
DL		 14526 ret = obtain_boardname(dd);
14527 if (ret)
77241056 14528 goto bail_cleanup;
77241056
MM		 14529
14530 snprintf(dd->boardversion, BOARD_VERS_MAX,
5d9157aa 14531 "ChipABI %u.%u, ChipRev %u.%u, SW Compat %llu\n",
77241056 14532 HFI1_CHIP_VERS_MAJ, HFI1_CHIP_VERS_MIN,
77241056
MM		 14533 (u32)dd->majrev,
14534 (u32)dd->minrev,
14535 (dd->revision >> CCE_REVISION_SW_SHIFT)
14536 & CCE_REVISION_SW_MASK);
14537
14538 ret = set_up_context_variables(dd);
14539 if (ret)
14540 goto bail_cleanup;
14541
14542 /* set initial RXE CSRs */
14543 init_rxe(dd);
14544 /* set initial TXE CSRs */
14545 init_txe(dd);
14546 /* set initial non-RXE, non-TXE CSRs */
14547 init_other(dd);
14548 /* set up KDETH QP prefix in both RX and TX CSRs */
14549 init_kdeth_qp(dd);
14550
4197344b
DD		 14551 ret = hfi1_dev_affinity_init(dd);
14552 if (ret)
14553 goto bail_cleanup;
957558c9 14554
77241056
MM		 14555 /* send contexts must be set up before receive contexts */
14556 ret = init_send_contexts(dd);
14557 if (ret)
14558 goto bail_cleanup;
14559
14560 ret = hfi1_create_ctxts(dd);
14561 if (ret)
14562 goto bail_cleanup;
14563
14564 dd->rcvhdrsize = DEFAULT_RCVHDRSIZE;
14565 /*
14566 * rcd[0] is guaranteed to be valid by this point. Also, all
14567 * context are using the same value, as per the module parameter.
14568 */
14569 dd->rhf_offset = dd->rcd[0]->rcvhdrqentsize - sizeof(u64) / sizeof(u32);
14570
14571 ret = init_pervl_scs(dd);
14572 if (ret)
14573 goto bail_cleanup;
14574
14575 /* sdma init */
14576 for (i = 0; i < dd->num_pports; ++i) {
14577 ret = sdma_init(dd, i);
14578 if (ret)
14579 goto bail_cleanup;
14580 }
14581
14582 /* use contexts created by hfi1_create_ctxts */
14583 ret = set_up_interrupts(dd);
14584 if (ret)
14585 goto bail_cleanup;
14586
14587 /* set up LCB access - must be after set_up_interrupts() */
14588 init_lcb_access(dd);
14589
14590 snprintf(dd->serial, SERIAL_MAX, "0x%08llx\n",
14591 dd->base_guid & 0xFFFFFF);
14592
14593 dd->oui1 = dd->base_guid >> 56 & 0xFF;
14594 dd->oui2 = dd->base_guid >> 48 & 0xFF;
14595 dd->oui3 = dd->base_guid >> 40 & 0xFF;
14596
14597 ret = load_firmware(dd); /* asymmetric with dispose_firmware() */
14598 if (ret)
14599 goto bail_clear_intr;
77241056
MM		 14600
14601 thermal_init(dd);
14602
14603 ret = init_cntrs(dd);
14604 if (ret)
14605 goto bail_clear_intr;
14606
14607 ret = init_rcverr(dd);
14608 if (ret)
14609 goto bail_free_cntrs;
14610
14611 ret = eprom_init(dd);
14612 if (ret)
14613 goto bail_free_rcverr;
14614
14615 goto bail;
14616
14617bail_free_rcverr:
14618 free_rcverr(dd);
14619bail_free_cntrs:
14620 free_cntrs(dd);
14621bail_clear_intr:
14622 clean_up_interrupts(dd);
14623bail_cleanup:
14624 hfi1_pcie_ddcleanup(dd);
14625bail_free:
14626 hfi1_free_devdata(dd);
14627 dd = ERR_PTR(ret);
14628bail:
14629 return dd;
14630}
14631
14632static u16 delay_cycles(struct hfi1_pportdata *ppd, u32 desired_egress_rate,
14633 u32 dw_len)
14634{
14635 u32 delta_cycles;
14636 u32 current_egress_rate = ppd->current_egress_rate;
14637 /* rates here are in units of 10^6 bits/sec */
14638
14639 if (desired_egress_rate == -1)
14640 return 0; /* shouldn't happen */
14641
14642 if (desired_egress_rate >= current_egress_rate)
14643 return 0; /* we can't help go faster, only slower */
14644
14645 delta_cycles = egress_cycles(dw_len * 4, desired_egress_rate) -
14646 egress_cycles(dw_len * 4, current_egress_rate);
14647
14648 return (u16)delta_cycles;
14649}
14650
77241056
MM		 14651/**
14652 * create_pbc - build a pbc for transmission
14653 * @flags: special case flags or-ed in built pbc
14654 * @srate: static rate
14655 * @vl: vl
14656 * @dwlen: dword length (header words + data words + pbc words)
14657 *
14658 * Create a PBC with the given flags, rate, VL, and length.
14659 *
14660 * NOTE: The PBC created will not insert any HCRC - all callers but one are
14661 * for verbs, which does not use this PSM feature. The lone other caller
14662 * is for the diagnostic interface which calls this if the user does not
14663 * supply their own PBC.
14664 */
14665u64 create_pbc(struct hfi1_pportdata *ppd, u64 flags, int srate_mbs, u32 vl,
14666 u32 dw_len)
14667{
14668 u64 pbc, delay = 0;
14669
14670 if (unlikely(srate_mbs))
14671 delay = delay_cycles(ppd, srate_mbs, dw_len);
14672
14673 pbc = flags
14674 | (delay << PBC_STATIC_RATE_CONTROL_COUNT_SHIFT)
14675 | ((u64)PBC_IHCRC_NONE << PBC_INSERT_HCRC_SHIFT)
14676 | (vl & PBC_VL_MASK) << PBC_VL_SHIFT
14677 | (dw_len & PBC_LENGTH_DWS_MASK)
14678 << PBC_LENGTH_DWS_SHIFT;
14679
14680 return pbc;
14681}
14682
14683#define SBUS_THERMAL 0x4f
14684#define SBUS_THERM_MONITOR_MODE 0x1
14685
14686#define THERM_FAILURE(dev, ret, reason) \
14687 dd_dev_err((dd), \
14688 "Thermal sensor initialization failed: %s (%d)\n", \
14689 (reason), (ret))
14690
14691/*
cde10afa 14692 * Initialize the thermal sensor.
77241056
MM		 14693 *
14694 * After initialization, enable polling of thermal sensor through
14695 * SBus interface. In order for this to work, the SBus Master
14696 * firmware has to be loaded due to the fact that the HW polling
14697 * logic uses SBus interrupts, which are not supported with
14698 * default firmware. Otherwise, no data will be returned through
14699 * the ASIC_STS_THERM CSR.
14700 */
14701static int thermal_init(struct hfi1_devdata *dd)
14702{
14703 int ret = 0;
14704
14705 if (dd->icode != ICODE_RTL_SILICON ||
a453698b 14706 check_chip_resource(dd, CR_THERM_INIT, NULL))
77241056
MM		 14707 return ret;
14708
576531fd
DL		 14709 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT);
14710 if (ret) {
14711 THERM_FAILURE(dd, ret, "Acquire SBus");
14712 return ret;
14713 }
14714
77241056 14715 dd_dev_info(dd, "Initializing thermal sensor\n");
4ef98989
JAQ		 14716 /* Disable polling of thermal readings */
14717 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0);
14718 msleep(100);
77241056
MM		 14719 /* Thermal Sensor Initialization */
14720 /* Step 1: Reset the Thermal SBus Receiver */
14721 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
14722 RESET_SBUS_RECEIVER, 0);
14723 if (ret) {
14724 THERM_FAILURE(dd, ret, "Bus Reset");
14725 goto done;
14726 }
14727 /* Step 2: Set Reset bit in Thermal block */
14728 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
14729 WRITE_SBUS_RECEIVER, 0x1);
14730 if (ret) {
14731 THERM_FAILURE(dd, ret, "Therm Block Reset");
14732 goto done;
14733 }
14734 /* Step 3: Write clock divider value (100MHz -> 2MHz) */
14735 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x1,
14736 WRITE_SBUS_RECEIVER, 0x32);
14737 if (ret) {
14738 THERM_FAILURE(dd, ret, "Write Clock Div");
14739 goto done;
14740 }
14741 /* Step 4: Select temperature mode */
14742 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x3,
14743 WRITE_SBUS_RECEIVER,
14744 SBUS_THERM_MONITOR_MODE);
14745 if (ret) {
14746 THERM_FAILURE(dd, ret, "Write Mode Sel");
14747 goto done;
14748 }
14749 /* Step 5: De-assert block reset and start conversion */
14750 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
14751 WRITE_SBUS_RECEIVER, 0x2);
14752 if (ret) {
14753 THERM_FAILURE(dd, ret, "Write Reset Deassert");
14754 goto done;
14755 }
14756 /* Step 5.1: Wait for first conversion (21.5ms per spec) */
14757 msleep(22);
14758
14759 /* Enable polling of thermal readings */
14760 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1);
a453698b
DL		 14761
14762 /* Set initialized flag */
14763 ret = acquire_chip_resource(dd, CR_THERM_INIT, 0);
14764 if (ret)
14765 THERM_FAILURE(dd, ret, "Unable to set thermal init flag");
14766
77241056 14767done:
576531fd 14768 release_chip_resource(dd, CR_SBUS);
77241056
MM		 14769 return ret;
14770}
14771
14772static void handle_temp_err(struct hfi1_devdata *dd)
14773{
14774 struct hfi1_pportdata *ppd = &dd->pport[0];
14775 /*
14776 * Thermal Critical Interrupt
14777 * Put the device into forced freeze mode, take link down to
14778 * offline, and put DC into reset.
14779 */
14780 dd_dev_emerg(dd,
14781 "Critical temperature reached! Forcing device into freeze mode!\n");
14782 dd->flags |= HFI1_FORCED_FREEZE;
8638b77f 14783 start_freeze_handling(ppd, FREEZE_SELF | FREEZE_ABORT);
77241056
MM		 14784 /*
14785 * Shut DC down as much and as quickly as possible.
14786 *
14787 * Step 1: Take the link down to OFFLINE. This will cause the
14788 * 8051 to put the Serdes in reset. However, we don't want to
14789 * go through the entire link state machine since we want to
14790 * shutdown ASAP. Furthermore, this is not a graceful shutdown
14791 * but rather an attempt to save the chip.
14792 * Code below is almost the same as quiet_serdes() but avoids
14793 * all the extra work and the sleeps.
14794 */
14795 ppd->driver_link_ready = 0;
14796 ppd->link_enabled = 0;
bf640096
HC		 14797 set_physical_link_state(dd, (OPA_LINKDOWN_REASON_SMA_DISABLED << 8) |
14798 PLS_OFFLINE);
77241056
MM		 14799 /*
14800 * Step 2: Shutdown LCB and 8051
14801 * After shutdown, do not restore DC_CFG_RESET value.
14802 */
14803 dc_shutdown(dd);
14804}
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