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IB/hfi1: Protect the global dev_cntr_names and port_cntr_names
[mirror_ubuntu-artful-kernel.git] / drivers / infiniband / hw / hfi1 / chip.c
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77241056 1/*
05d6ac1d 2 * Copyright(c) 2015, 2016 Intel Corporation.
77241056
MM		 3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
77241056
MM		 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * BSD LICENSE
19 *
77241056
MM		 20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 *
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
29 * distribution.
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 */
47
48/*
49 * This file contains all of the code that is specific to the HFI chip
50 */
51
52#include <linux/pci.h>
53#include <linux/delay.h>
54#include <linux/interrupt.h>
55#include <linux/module.h>
56
57#include "hfi.h"
58#include "trace.h"
59#include "mad.h"
60#include "pio.h"
61#include "sdma.h"
62#include "eprom.h"
5d9157aa 63#include "efivar.h"
8ebd4cf1 64#include "platform.h"
affa48de 65#include "aspm.h"
4197344b 66#include "affinity.h"
77241056
MM		 67
68#define NUM_IB_PORTS 1
69
70uint kdeth_qp;
71module_param_named(kdeth_qp, kdeth_qp, uint, S_IRUGO);
72MODULE_PARM_DESC(kdeth_qp, "Set the KDETH queue pair prefix");
73
74uint num_vls = HFI1_MAX_VLS_SUPPORTED;
75module_param(num_vls, uint, S_IRUGO);
76MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
77
78/*
79 * Default time to aggregate two 10K packets from the idle state
80 * (timer not running). The timer starts at the end of the first packet,
81 * so only the time for one 10K packet and header plus a bit extra is needed.
82 * 10 * 1024 + 64 header byte = 10304 byte
83 * 10304 byte / 12.5 GB/s = 824.32ns
84 */
85uint rcv_intr_timeout = (824 + 16); /* 16 is for coalescing interrupt */
86module_param(rcv_intr_timeout, uint, S_IRUGO);
87MODULE_PARM_DESC(rcv_intr_timeout, "Receive interrupt mitigation timeout in ns");
88
89uint rcv_intr_count = 16; /* same as qib */
90module_param(rcv_intr_count, uint, S_IRUGO);
91MODULE_PARM_DESC(rcv_intr_count, "Receive interrupt mitigation count");
92
93ushort link_crc_mask = SUPPORTED_CRCS;
94module_param(link_crc_mask, ushort, S_IRUGO);
95MODULE_PARM_DESC(link_crc_mask, "CRCs to use on the link");
96
97uint loopback;
98module_param_named(loopback, loopback, uint, S_IRUGO);
99MODULE_PARM_DESC(loopback, "Put into loopback mode (1 = serdes, 3 = external cable");
100
101/* Other driver tunables */
102uint rcv_intr_dynamic = 1; /* enable dynamic mode for rcv int mitigation*/
103static ushort crc_14b_sideband = 1;
104static uint use_flr = 1;
105uint quick_linkup; /* skip LNI */
106
107struct flag_table {
108 u64 flag; /* the flag */
109 char *str; /* description string */
110 u16 extra; /* extra information */
111 u16 unused0;
112 u32 unused1;
113};
114
115/* str must be a string constant */
116#define FLAG_ENTRY(str, extra, flag) {flag, str, extra}
117#define FLAG_ENTRY0(str, flag) {flag, str, 0}
118
119/* Send Error Consequences */
120#define SEC_WRITE_DROPPED 0x1
121#define SEC_PACKET_DROPPED 0x2
122#define SEC_SC_HALTED 0x4 /* per-context only */
123#define SEC_SPC_FREEZE 0x8 /* per-HFI only */
124
8784ac02 125#define DEFAULT_KRCVQS 2
77241056 126#define MIN_KERNEL_KCTXTS 2
82c2611d 127#define FIRST_KERNEL_KCTXT 1
372cc85a
DL		 128/* sizes for both the QP and RSM map tables */
129#define NUM_MAP_ENTRIES 256
77241056
MM		 130#define NUM_MAP_REGS 32
131
132/* Bit offset into the GUID which carries HFI id information */
133#define GUID_HFI_INDEX_SHIFT 39
134
135/* extract the emulation revision */
136#define emulator_rev(dd) ((dd)->irev >> 8)
137/* parallel and serial emulation versions are 3 and 4 respectively */
138#define is_emulator_p(dd) ((((dd)->irev) & 0xf) == 3)
139#define is_emulator_s(dd) ((((dd)->irev) & 0xf) == 4)
140
141/* RSM fields */
142
143/* packet type */
144#define IB_PACKET_TYPE 2ull
145#define QW_SHIFT 6ull
146/* QPN[7..1] */
147#define QPN_WIDTH 7ull
148
149/* LRH.BTH: QW 0, OFFSET 48 - for match */
150#define LRH_BTH_QW 0ull
151#define LRH_BTH_BIT_OFFSET 48ull
152#define LRH_BTH_OFFSET(off) ((LRH_BTH_QW << QW_SHIFT) | (off))
153#define LRH_BTH_MATCH_OFFSET LRH_BTH_OFFSET(LRH_BTH_BIT_OFFSET)
154#define LRH_BTH_SELECT
155#define LRH_BTH_MASK 3ull
156#define LRH_BTH_VALUE 2ull
157
158/* LRH.SC[3..0] QW 0, OFFSET 56 - for match */
159#define LRH_SC_QW 0ull
160#define LRH_SC_BIT_OFFSET 56ull
161#define LRH_SC_OFFSET(off) ((LRH_SC_QW << QW_SHIFT) | (off))
162#define LRH_SC_MATCH_OFFSET LRH_SC_OFFSET(LRH_SC_BIT_OFFSET)
163#define LRH_SC_MASK 128ull
164#define LRH_SC_VALUE 0ull
165
166/* SC[n..0] QW 0, OFFSET 60 - for select */
167#define LRH_SC_SELECT_OFFSET ((LRH_SC_QW << QW_SHIFT) | (60ull))
168
169/* QPN[m+n:1] QW 1, OFFSET 1 */
170#define QPN_SELECT_OFFSET ((1ull << QW_SHIFT) | (1ull))
171
172/* defines to build power on SC2VL table */
173#define SC2VL_VAL( \
174 num, \
175 sc0, sc0val, \
176 sc1, sc1val, \
177 sc2, sc2val, \
178 sc3, sc3val, \
179 sc4, sc4val, \
180 sc5, sc5val, \
181 sc6, sc6val, \
182 sc7, sc7val) \
183( \
184 ((u64)(sc0val) << SEND_SC2VLT##num##_SC##sc0##_SHIFT) | \
185 ((u64)(sc1val) << SEND_SC2VLT##num##_SC##sc1##_SHIFT) | \
186 ((u64)(sc2val) << SEND_SC2VLT##num##_SC##sc2##_SHIFT) | \
187 ((u64)(sc3val) << SEND_SC2VLT##num##_SC##sc3##_SHIFT) | \
188 ((u64)(sc4val) << SEND_SC2VLT##num##_SC##sc4##_SHIFT) | \
189 ((u64)(sc5val) << SEND_SC2VLT##num##_SC##sc5##_SHIFT) | \
190 ((u64)(sc6val) << SEND_SC2VLT##num##_SC##sc6##_SHIFT) | \
191 ((u64)(sc7val) << SEND_SC2VLT##num##_SC##sc7##_SHIFT) \
192)
193
194#define DC_SC_VL_VAL( \
195 range, \
196 e0, e0val, \
197 e1, e1val, \
198 e2, e2val, \
199 e3, e3val, \
200 e4, e4val, \
201 e5, e5val, \
202 e6, e6val, \
203 e7, e7val, \
204 e8, e8val, \
205 e9, e9val, \
206 e10, e10val, \
207 e11, e11val, \
208 e12, e12val, \
209 e13, e13val, \
210 e14, e14val, \
211 e15, e15val) \
212( \
213 ((u64)(e0val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e0##_SHIFT) | \
214 ((u64)(e1val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e1##_SHIFT) | \
215 ((u64)(e2val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e2##_SHIFT) | \
216 ((u64)(e3val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e3##_SHIFT) | \
217 ((u64)(e4val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e4##_SHIFT) | \
218 ((u64)(e5val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e5##_SHIFT) | \
219 ((u64)(e6val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e6##_SHIFT) | \
220 ((u64)(e7val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e7##_SHIFT) | \
221 ((u64)(e8val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e8##_SHIFT) | \
222 ((u64)(e9val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e9##_SHIFT) | \
223 ((u64)(e10val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e10##_SHIFT) | \
224 ((u64)(e11val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e11##_SHIFT) | \
225 ((u64)(e12val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e12##_SHIFT) | \
226 ((u64)(e13val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e13##_SHIFT) | \
227 ((u64)(e14val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e14##_SHIFT) | \
228 ((u64)(e15val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e15##_SHIFT) \
229)
230
231/* all CceStatus sub-block freeze bits */
232#define ALL_FROZE (CCE_STATUS_SDMA_FROZE_SMASK \
233 | CCE_STATUS_RXE_FROZE_SMASK \
234 | CCE_STATUS_TXE_FROZE_SMASK \
235 | CCE_STATUS_TXE_PIO_FROZE_SMASK)
236/* all CceStatus sub-block TXE pause bits */
237#define ALL_TXE_PAUSE (CCE_STATUS_TXE_PIO_PAUSED_SMASK \
238 | CCE_STATUS_TXE_PAUSED_SMASK \
239 | CCE_STATUS_SDMA_PAUSED_SMASK)
240/* all CceStatus sub-block RXE pause bits */
241#define ALL_RXE_PAUSE CCE_STATUS_RXE_PAUSED_SMASK
242
2b719046
JP		 243#define CNTR_MAX 0xFFFFFFFFFFFFFFFFULL
244#define CNTR_32BIT_MAX 0x00000000FFFFFFFF
245
77241056
MM		 246/*
247 * CCE Error flags.
248 */
249static struct flag_table cce_err_status_flags[] = {
250/* 0*/ FLAG_ENTRY0("CceCsrParityErr",
251 CCE_ERR_STATUS_CCE_CSR_PARITY_ERR_SMASK),
252/* 1*/ FLAG_ENTRY0("CceCsrReadBadAddrErr",
253 CCE_ERR_STATUS_CCE_CSR_READ_BAD_ADDR_ERR_SMASK),
254/* 2*/ FLAG_ENTRY0("CceCsrWriteBadAddrErr",
255 CCE_ERR_STATUS_CCE_CSR_WRITE_BAD_ADDR_ERR_SMASK),
256/* 3*/ FLAG_ENTRY0("CceTrgtAsyncFifoParityErr",
257 CCE_ERR_STATUS_CCE_TRGT_ASYNC_FIFO_PARITY_ERR_SMASK),
258/* 4*/ FLAG_ENTRY0("CceTrgtAccessErr",
259 CCE_ERR_STATUS_CCE_TRGT_ACCESS_ERR_SMASK),
260/* 5*/ FLAG_ENTRY0("CceRspdDataParityErr",
261 CCE_ERR_STATUS_CCE_RSPD_DATA_PARITY_ERR_SMASK),
262/* 6*/ FLAG_ENTRY0("CceCli0AsyncFifoParityErr",
263 CCE_ERR_STATUS_CCE_CLI0_ASYNC_FIFO_PARITY_ERR_SMASK),
264/* 7*/ FLAG_ENTRY0("CceCsrCfgBusParityErr",
265 CCE_ERR_STATUS_CCE_CSR_CFG_BUS_PARITY_ERR_SMASK),
266/* 8*/ FLAG_ENTRY0("CceCli2AsyncFifoParityErr",
267 CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK),
268/* 9*/ FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr",
269 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR_SMASK),
270/*10*/ FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr",
271 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR_SMASK),
272/*11*/ FLAG_ENTRY0("CceCli1AsyncFifoRxdmaParityError",
273 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERROR_SMASK),
274/*12*/ FLAG_ENTRY0("CceCli1AsyncFifoDbgParityError",
275 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERROR_SMASK),
276/*13*/ FLAG_ENTRY0("PcicRetryMemCorErr",
277 CCE_ERR_STATUS_PCIC_RETRY_MEM_COR_ERR_SMASK),
278/*14*/ FLAG_ENTRY0("PcicRetryMemCorErr",
279 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_COR_ERR_SMASK),
280/*15*/ FLAG_ENTRY0("PcicPostHdQCorErr",
281 CCE_ERR_STATUS_PCIC_POST_HD_QCOR_ERR_SMASK),
282/*16*/ FLAG_ENTRY0("PcicPostHdQCorErr",
283 CCE_ERR_STATUS_PCIC_POST_DAT_QCOR_ERR_SMASK),
284/*17*/ FLAG_ENTRY0("PcicPostHdQCorErr",
285 CCE_ERR_STATUS_PCIC_CPL_HD_QCOR_ERR_SMASK),
286/*18*/ FLAG_ENTRY0("PcicCplDatQCorErr",
287 CCE_ERR_STATUS_PCIC_CPL_DAT_QCOR_ERR_SMASK),
288/*19*/ FLAG_ENTRY0("PcicNPostHQParityErr",
289 CCE_ERR_STATUS_PCIC_NPOST_HQ_PARITY_ERR_SMASK),
290/*20*/ FLAG_ENTRY0("PcicNPostDatQParityErr",
291 CCE_ERR_STATUS_PCIC_NPOST_DAT_QPARITY_ERR_SMASK),
292/*21*/ FLAG_ENTRY0("PcicRetryMemUncErr",
293 CCE_ERR_STATUS_PCIC_RETRY_MEM_UNC_ERR_SMASK),
294/*22*/ FLAG_ENTRY0("PcicRetrySotMemUncErr",
295 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_UNC_ERR_SMASK),
296/*23*/ FLAG_ENTRY0("PcicPostHdQUncErr",
297 CCE_ERR_STATUS_PCIC_POST_HD_QUNC_ERR_SMASK),
298/*24*/ FLAG_ENTRY0("PcicPostDatQUncErr",
299 CCE_ERR_STATUS_PCIC_POST_DAT_QUNC_ERR_SMASK),
300/*25*/ FLAG_ENTRY0("PcicCplHdQUncErr",
301 CCE_ERR_STATUS_PCIC_CPL_HD_QUNC_ERR_SMASK),
302/*26*/ FLAG_ENTRY0("PcicCplDatQUncErr",
303 CCE_ERR_STATUS_PCIC_CPL_DAT_QUNC_ERR_SMASK),
304/*27*/ FLAG_ENTRY0("PcicTransmitFrontParityErr",
305 CCE_ERR_STATUS_PCIC_TRANSMIT_FRONT_PARITY_ERR_SMASK),
306/*28*/ FLAG_ENTRY0("PcicTransmitBackParityErr",
307 CCE_ERR_STATUS_PCIC_TRANSMIT_BACK_PARITY_ERR_SMASK),
308/*29*/ FLAG_ENTRY0("PcicReceiveParityErr",
309 CCE_ERR_STATUS_PCIC_RECEIVE_PARITY_ERR_SMASK),
310/*30*/ FLAG_ENTRY0("CceTrgtCplTimeoutErr",
311 CCE_ERR_STATUS_CCE_TRGT_CPL_TIMEOUT_ERR_SMASK),
312/*31*/ FLAG_ENTRY0("LATriggered",
313 CCE_ERR_STATUS_LA_TRIGGERED_SMASK),
314/*32*/ FLAG_ENTRY0("CceSegReadBadAddrErr",
315 CCE_ERR_STATUS_CCE_SEG_READ_BAD_ADDR_ERR_SMASK),
316/*33*/ FLAG_ENTRY0("CceSegWriteBadAddrErr",
317 CCE_ERR_STATUS_CCE_SEG_WRITE_BAD_ADDR_ERR_SMASK),
318/*34*/ FLAG_ENTRY0("CceRcplAsyncFifoParityErr",
319 CCE_ERR_STATUS_CCE_RCPL_ASYNC_FIFO_PARITY_ERR_SMASK),
320/*35*/ FLAG_ENTRY0("CceRxdmaConvFifoParityErr",
321 CCE_ERR_STATUS_CCE_RXDMA_CONV_FIFO_PARITY_ERR_SMASK),
322/*36*/ FLAG_ENTRY0("CceMsixTableCorErr",
323 CCE_ERR_STATUS_CCE_MSIX_TABLE_COR_ERR_SMASK),
324/*37*/ FLAG_ENTRY0("CceMsixTableUncErr",
325 CCE_ERR_STATUS_CCE_MSIX_TABLE_UNC_ERR_SMASK),
326/*38*/ FLAG_ENTRY0("CceIntMapCorErr",
327 CCE_ERR_STATUS_CCE_INT_MAP_COR_ERR_SMASK),
328/*39*/ FLAG_ENTRY0("CceIntMapUncErr",
329 CCE_ERR_STATUS_CCE_INT_MAP_UNC_ERR_SMASK),
330/*40*/ FLAG_ENTRY0("CceMsixCsrParityErr",
331 CCE_ERR_STATUS_CCE_MSIX_CSR_PARITY_ERR_SMASK),
332/*41-63 reserved*/
333};
334
335/*
336 * Misc Error flags
337 */
338#define MES(text) MISC_ERR_STATUS_MISC_##text##_ERR_SMASK
339static struct flag_table misc_err_status_flags[] = {
340/* 0*/ FLAG_ENTRY0("CSR_PARITY", MES(CSR_PARITY)),
341/* 1*/ FLAG_ENTRY0("CSR_READ_BAD_ADDR", MES(CSR_READ_BAD_ADDR)),
342/* 2*/ FLAG_ENTRY0("CSR_WRITE_BAD_ADDR", MES(CSR_WRITE_BAD_ADDR)),
343/* 3*/ FLAG_ENTRY0("SBUS_WRITE_FAILED", MES(SBUS_WRITE_FAILED)),
344/* 4*/ FLAG_ENTRY0("KEY_MISMATCH", MES(KEY_MISMATCH)),
345/* 5*/ FLAG_ENTRY0("FW_AUTH_FAILED", MES(FW_AUTH_FAILED)),
346/* 6*/ FLAG_ENTRY0("EFUSE_CSR_PARITY", MES(EFUSE_CSR_PARITY)),
347/* 7*/ FLAG_ENTRY0("EFUSE_READ_BAD_ADDR", MES(EFUSE_READ_BAD_ADDR)),
348/* 8*/ FLAG_ENTRY0("EFUSE_WRITE", MES(EFUSE_WRITE)),
349/* 9*/ FLAG_ENTRY0("EFUSE_DONE_PARITY", MES(EFUSE_DONE_PARITY)),
350/*10*/ FLAG_ENTRY0("INVALID_EEP_CMD", MES(INVALID_EEP_CMD)),
351/*11*/ FLAG_ENTRY0("MBIST_FAIL", MES(MBIST_FAIL)),
352/*12*/ FLAG_ENTRY0("PLL_LOCK_FAIL", MES(PLL_LOCK_FAIL))
353};
354
355/*
356 * TXE PIO Error flags and consequences
357 */
358static struct flag_table pio_err_status_flags[] = {
359/* 0*/ FLAG_ENTRY("PioWriteBadCtxt",
360 SEC_WRITE_DROPPED,
361 SEND_PIO_ERR_STATUS_PIO_WRITE_BAD_CTXT_ERR_SMASK),
362/* 1*/ FLAG_ENTRY("PioWriteAddrParity",
363 SEC_SPC_FREEZE,
364 SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK),
365/* 2*/ FLAG_ENTRY("PioCsrParity",
366 SEC_SPC_FREEZE,
367 SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK),
368/* 3*/ FLAG_ENTRY("PioSbMemFifo0",
369 SEC_SPC_FREEZE,
370 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK),
371/* 4*/ FLAG_ENTRY("PioSbMemFifo1",
372 SEC_SPC_FREEZE,
373 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK),
374/* 5*/ FLAG_ENTRY("PioPccFifoParity",
375 SEC_SPC_FREEZE,
376 SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK),
377/* 6*/ FLAG_ENTRY("PioPecFifoParity",
378 SEC_SPC_FREEZE,
379 SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK),
380/* 7*/ FLAG_ENTRY("PioSbrdctlCrrelParity",
381 SEC_SPC_FREEZE,
382 SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK),
383/* 8*/ FLAG_ENTRY("PioSbrdctrlCrrelFifoParity",
384 SEC_SPC_FREEZE,
385 SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK),
386/* 9*/ FLAG_ENTRY("PioPktEvictFifoParityErr",
387 SEC_SPC_FREEZE,
388 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK),
389/*10*/ FLAG_ENTRY("PioSmPktResetParity",
390 SEC_SPC_FREEZE,
391 SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK),
392/*11*/ FLAG_ENTRY("PioVlLenMemBank0Unc",
393 SEC_SPC_FREEZE,
394 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK),
395/*12*/ FLAG_ENTRY("PioVlLenMemBank1Unc",
396 SEC_SPC_FREEZE,
397 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK),
398/*13*/ FLAG_ENTRY("PioVlLenMemBank0Cor",
399 0,
400 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_COR_ERR_SMASK),
401/*14*/ FLAG_ENTRY("PioVlLenMemBank1Cor",
402 0,
403 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_COR_ERR_SMASK),
404/*15*/ FLAG_ENTRY("PioCreditRetFifoParity",
405 SEC_SPC_FREEZE,
406 SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK),
407/*16*/ FLAG_ENTRY("PioPpmcPblFifo",
408 SEC_SPC_FREEZE,
409 SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK),
410/*17*/ FLAG_ENTRY("PioInitSmIn",
411 0,
412 SEND_PIO_ERR_STATUS_PIO_INIT_SM_IN_ERR_SMASK),
413/*18*/ FLAG_ENTRY("PioPktEvictSmOrArbSm",
414 SEC_SPC_FREEZE,
415 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK),
416/*19*/ FLAG_ENTRY("PioHostAddrMemUnc",
417 SEC_SPC_FREEZE,
418 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK),
419/*20*/ FLAG_ENTRY("PioHostAddrMemCor",
420 0,
421 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_COR_ERR_SMASK),
422/*21*/ FLAG_ENTRY("PioWriteDataParity",
423 SEC_SPC_FREEZE,
424 SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK),
425/*22*/ FLAG_ENTRY("PioStateMachine",
426 SEC_SPC_FREEZE,
427 SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK),
428/*23*/ FLAG_ENTRY("PioWriteQwValidParity",
8638b77f 429 SEC_WRITE_DROPPED | SEC_SPC_FREEZE,
77241056
MM		 430 SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK),
431/*24*/ FLAG_ENTRY("PioBlockQwCountParity",
8638b77f 432 SEC_WRITE_DROPPED | SEC_SPC_FREEZE,
77241056
MM		 433 SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK),
434/*25*/ FLAG_ENTRY("PioVlfVlLenParity",
435 SEC_SPC_FREEZE,
436 SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK),
437/*26*/ FLAG_ENTRY("PioVlfSopParity",
438 SEC_SPC_FREEZE,
439 SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK),
440/*27*/ FLAG_ENTRY("PioVlFifoParity",
441 SEC_SPC_FREEZE,
442 SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK),
443/*28*/ FLAG_ENTRY("PioPpmcBqcMemParity",
444 SEC_SPC_FREEZE,
445 SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK),
446/*29*/ FLAG_ENTRY("PioPpmcSopLen",
447 SEC_SPC_FREEZE,
448 SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK),
449/*30-31 reserved*/
450/*32*/ FLAG_ENTRY("PioCurrentFreeCntParity",
451 SEC_SPC_FREEZE,
452 SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK),
453/*33*/ FLAG_ENTRY("PioLastReturnedCntParity",
454 SEC_SPC_FREEZE,
455 SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK),
456/*34*/ FLAG_ENTRY("PioPccSopHeadParity",
457 SEC_SPC_FREEZE,
458 SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK),
459/*35*/ FLAG_ENTRY("PioPecSopHeadParityErr",
460 SEC_SPC_FREEZE,
461 SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK),
462/*36-63 reserved*/
463};
464
465/* TXE PIO errors that cause an SPC freeze */
466#define ALL_PIO_FREEZE_ERR \
467 (SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK \
468 | SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK \
469 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK \
470 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK \
471 | SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK \
472 | SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK \
473 | SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK \
474 | SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK \
475 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK \
476 | SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK \
477 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK \
478 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK \
479 | SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK \
480 | SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK \
481 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK \
482 | SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK \
483 | SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK \
484 | SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK \
485 | SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK \
486 | SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK \
487 | SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK \
488 | SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK \
489 | SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK \
490 | SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK \
491 | SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK \
492 | SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK \
493 | SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK \
494 | SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK \
495 | SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK)
496
497/*
498 * TXE SDMA Error flags
499 */
500static struct flag_table sdma_err_status_flags[] = {
501/* 0*/ FLAG_ENTRY0("SDmaRpyTagErr",
502 SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK),
503/* 1*/ FLAG_ENTRY0("SDmaCsrParityErr",
504 SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK),
505/* 2*/ FLAG_ENTRY0("SDmaPcieReqTrackingUncErr",
506 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK),
507/* 3*/ FLAG_ENTRY0("SDmaPcieReqTrackingCorErr",
508 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_COR_ERR_SMASK),
509/*04-63 reserved*/
510};
511
512/* TXE SDMA errors that cause an SPC freeze */
513#define ALL_SDMA_FREEZE_ERR \
514 (SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK \
515 | SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK \
516 | SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK)
517
69a00b8e
MM		 518/* SendEgressErrInfo bits that correspond to a PortXmitDiscard counter */
519#define PORT_DISCARD_EGRESS_ERRS \
520 (SEND_EGRESS_ERR_INFO_TOO_LONG_IB_PACKET_ERR_SMASK \
521 | SEND_EGRESS_ERR_INFO_VL_MAPPING_ERR_SMASK \
522 | SEND_EGRESS_ERR_INFO_VL_ERR_SMASK)
523
77241056
MM		 524/*
525 * TXE Egress Error flags
526 */
527#define SEES(text) SEND_EGRESS_ERR_STATUS_##text##_ERR_SMASK
528static struct flag_table egress_err_status_flags[] = {
529/* 0*/ FLAG_ENTRY0("TxPktIntegrityMemCorErr", SEES(TX_PKT_INTEGRITY_MEM_COR)),
530/* 1*/ FLAG_ENTRY0("TxPktIntegrityMemUncErr", SEES(TX_PKT_INTEGRITY_MEM_UNC)),
531/* 2 reserved */
532/* 3*/ FLAG_ENTRY0("TxEgressFifoUnderrunOrParityErr",
533 SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY)),
534/* 4*/ FLAG_ENTRY0("TxLinkdownErr", SEES(TX_LINKDOWN)),
535/* 5*/ FLAG_ENTRY0("TxIncorrectLinkStateErr", SEES(TX_INCORRECT_LINK_STATE)),
536/* 6 reserved */
537/* 7*/ FLAG_ENTRY0("TxPioLaunchIntfParityErr",
538 SEES(TX_PIO_LAUNCH_INTF_PARITY)),
539/* 8*/ FLAG_ENTRY0("TxSdmaLaunchIntfParityErr",
540 SEES(TX_SDMA_LAUNCH_INTF_PARITY)),
541/* 9-10 reserved */
542/*11*/ FLAG_ENTRY0("TxSbrdCtlStateMachineParityErr",
543 SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY)),
544/*12*/ FLAG_ENTRY0("TxIllegalVLErr", SEES(TX_ILLEGAL_VL)),
545/*13*/ FLAG_ENTRY0("TxLaunchCsrParityErr", SEES(TX_LAUNCH_CSR_PARITY)),
546/*14*/ FLAG_ENTRY0("TxSbrdCtlCsrParityErr", SEES(TX_SBRD_CTL_CSR_PARITY)),
547/*15*/ FLAG_ENTRY0("TxConfigParityErr", SEES(TX_CONFIG_PARITY)),
548/*16*/ FLAG_ENTRY0("TxSdma0DisallowedPacketErr",
549 SEES(TX_SDMA0_DISALLOWED_PACKET)),
550/*17*/ FLAG_ENTRY0("TxSdma1DisallowedPacketErr",
551 SEES(TX_SDMA1_DISALLOWED_PACKET)),
552/*18*/ FLAG_ENTRY0("TxSdma2DisallowedPacketErr",
553 SEES(TX_SDMA2_DISALLOWED_PACKET)),
554/*19*/ FLAG_ENTRY0("TxSdma3DisallowedPacketErr",
555 SEES(TX_SDMA3_DISALLOWED_PACKET)),
556/*20*/ FLAG_ENTRY0("TxSdma4DisallowedPacketErr",
557 SEES(TX_SDMA4_DISALLOWED_PACKET)),
558/*21*/ FLAG_ENTRY0("TxSdma5DisallowedPacketErr",
559 SEES(TX_SDMA5_DISALLOWED_PACKET)),
560/*22*/ FLAG_ENTRY0("TxSdma6DisallowedPacketErr",
561 SEES(TX_SDMA6_DISALLOWED_PACKET)),
562/*23*/ FLAG_ENTRY0("TxSdma7DisallowedPacketErr",
563 SEES(TX_SDMA7_DISALLOWED_PACKET)),
564/*24*/ FLAG_ENTRY0("TxSdma8DisallowedPacketErr",
565 SEES(TX_SDMA8_DISALLOWED_PACKET)),
566/*25*/ FLAG_ENTRY0("TxSdma9DisallowedPacketErr",
567 SEES(TX_SDMA9_DISALLOWED_PACKET)),
568/*26*/ FLAG_ENTRY0("TxSdma10DisallowedPacketErr",
569 SEES(TX_SDMA10_DISALLOWED_PACKET)),
570/*27*/ FLAG_ENTRY0("TxSdma11DisallowedPacketErr",
571 SEES(TX_SDMA11_DISALLOWED_PACKET)),
572/*28*/ FLAG_ENTRY0("TxSdma12DisallowedPacketErr",
573 SEES(TX_SDMA12_DISALLOWED_PACKET)),
574/*29*/ FLAG_ENTRY0("TxSdma13DisallowedPacketErr",
575 SEES(TX_SDMA13_DISALLOWED_PACKET)),
576/*30*/ FLAG_ENTRY0("TxSdma14DisallowedPacketErr",
577 SEES(TX_SDMA14_DISALLOWED_PACKET)),
578/*31*/ FLAG_ENTRY0("TxSdma15DisallowedPacketErr",
579 SEES(TX_SDMA15_DISALLOWED_PACKET)),
580/*32*/ FLAG_ENTRY0("TxLaunchFifo0UncOrParityErr",
581 SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY)),
582/*33*/ FLAG_ENTRY0("TxLaunchFifo1UncOrParityErr",
583 SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY)),
584/*34*/ FLAG_ENTRY0("TxLaunchFifo2UncOrParityErr",
585 SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY)),
586/*35*/ FLAG_ENTRY0("TxLaunchFifo3UncOrParityErr",
587 SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY)),
588/*36*/ FLAG_ENTRY0("TxLaunchFifo4UncOrParityErr",
589 SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY)),
590/*37*/ FLAG_ENTRY0("TxLaunchFifo5UncOrParityErr",
591 SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY)),
592/*38*/ FLAG_ENTRY0("TxLaunchFifo6UncOrParityErr",
593 SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY)),
594/*39*/ FLAG_ENTRY0("TxLaunchFifo7UncOrParityErr",
595 SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY)),
596/*40*/ FLAG_ENTRY0("TxLaunchFifo8UncOrParityErr",
597 SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY)),
598/*41*/ FLAG_ENTRY0("TxCreditReturnParityErr", SEES(TX_CREDIT_RETURN_PARITY)),
599/*42*/ FLAG_ENTRY0("TxSbHdrUncErr", SEES(TX_SB_HDR_UNC)),
600/*43*/ FLAG_ENTRY0("TxReadSdmaMemoryUncErr", SEES(TX_READ_SDMA_MEMORY_UNC)),
601/*44*/ FLAG_ENTRY0("TxReadPioMemoryUncErr", SEES(TX_READ_PIO_MEMORY_UNC)),
602/*45*/ FLAG_ENTRY0("TxEgressFifoUncErr", SEES(TX_EGRESS_FIFO_UNC)),
603/*46*/ FLAG_ENTRY0("TxHcrcInsertionErr", SEES(TX_HCRC_INSERTION)),
604/*47*/ FLAG_ENTRY0("TxCreditReturnVLErr", SEES(TX_CREDIT_RETURN_VL)),
605/*48*/ FLAG_ENTRY0("TxLaunchFifo0CorErr", SEES(TX_LAUNCH_FIFO0_COR)),
606/*49*/ FLAG_ENTRY0("TxLaunchFifo1CorErr", SEES(TX_LAUNCH_FIFO1_COR)),
607/*50*/ FLAG_ENTRY0("TxLaunchFifo2CorErr", SEES(TX_LAUNCH_FIFO2_COR)),
608/*51*/ FLAG_ENTRY0("TxLaunchFifo3CorErr", SEES(TX_LAUNCH_FIFO3_COR)),
609/*52*/ FLAG_ENTRY0("TxLaunchFifo4CorErr", SEES(TX_LAUNCH_FIFO4_COR)),
610/*53*/ FLAG_ENTRY0("TxLaunchFifo5CorErr", SEES(TX_LAUNCH_FIFO5_COR)),
611/*54*/ FLAG_ENTRY0("TxLaunchFifo6CorErr", SEES(TX_LAUNCH_FIFO6_COR)),
612/*55*/ FLAG_ENTRY0("TxLaunchFifo7CorErr", SEES(TX_LAUNCH_FIFO7_COR)),
613/*56*/ FLAG_ENTRY0("TxLaunchFifo8CorErr", SEES(TX_LAUNCH_FIFO8_COR)),
614/*57*/ FLAG_ENTRY0("TxCreditOverrunErr", SEES(TX_CREDIT_OVERRUN)),
615/*58*/ FLAG_ENTRY0("TxSbHdrCorErr", SEES(TX_SB_HDR_COR)),
616/*59*/ FLAG_ENTRY0("TxReadSdmaMemoryCorErr", SEES(TX_READ_SDMA_MEMORY_COR)),
617/*60*/ FLAG_ENTRY0("TxReadPioMemoryCorErr", SEES(TX_READ_PIO_MEMORY_COR)),
618/*61*/ FLAG_ENTRY0("TxEgressFifoCorErr", SEES(TX_EGRESS_FIFO_COR)),
619/*62*/ FLAG_ENTRY0("TxReadSdmaMemoryCsrUncErr",
620 SEES(TX_READ_SDMA_MEMORY_CSR_UNC)),
621/*63*/ FLAG_ENTRY0("TxReadPioMemoryCsrUncErr",
622 SEES(TX_READ_PIO_MEMORY_CSR_UNC)),
623};
624
625/*
626 * TXE Egress Error Info flags
627 */
628#define SEEI(text) SEND_EGRESS_ERR_INFO_##text##_ERR_SMASK
629static struct flag_table egress_err_info_flags[] = {
630/* 0*/ FLAG_ENTRY0("Reserved", 0ull),
631/* 1*/ FLAG_ENTRY0("VLErr", SEEI(VL)),
632/* 2*/ FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)),
633/* 3*/ FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)),
634/* 4*/ FLAG_ENTRY0("PartitionKeyErr", SEEI(PARTITION_KEY)),
635/* 5*/ FLAG_ENTRY0("SLIDErr", SEEI(SLID)),
636/* 6*/ FLAG_ENTRY0("OpcodeErr", SEEI(OPCODE)),
637/* 7*/ FLAG_ENTRY0("VLMappingErr", SEEI(VL_MAPPING)),
638/* 8*/ FLAG_ENTRY0("RawErr", SEEI(RAW)),
639/* 9*/ FLAG_ENTRY0("RawIPv6Err", SEEI(RAW_IPV6)),
640/*10*/ FLAG_ENTRY0("GRHErr", SEEI(GRH)),
641/*11*/ FLAG_ENTRY0("BypassErr", SEEI(BYPASS)),
642/*12*/ FLAG_ENTRY0("KDETHPacketsErr", SEEI(KDETH_PACKETS)),
643/*13*/ FLAG_ENTRY0("NonKDETHPacketsErr", SEEI(NON_KDETH_PACKETS)),
644/*14*/ FLAG_ENTRY0("TooSmallIBPacketsErr", SEEI(TOO_SMALL_IB_PACKETS)),
645/*15*/ FLAG_ENTRY0("TooSmallBypassPacketsErr", SEEI(TOO_SMALL_BYPASS_PACKETS)),
646/*16*/ FLAG_ENTRY0("PbcTestErr", SEEI(PBC_TEST)),
647/*17*/ FLAG_ENTRY0("BadPktLenErr", SEEI(BAD_PKT_LEN)),
648/*18*/ FLAG_ENTRY0("TooLongIBPacketErr", SEEI(TOO_LONG_IB_PACKET)),
649/*19*/ FLAG_ENTRY0("TooLongBypassPacketsErr", SEEI(TOO_LONG_BYPASS_PACKETS)),
650/*20*/ FLAG_ENTRY0("PbcStaticRateControlErr", SEEI(PBC_STATIC_RATE_CONTROL)),
651/*21*/ FLAG_ENTRY0("BypassBadPktLenErr", SEEI(BAD_PKT_LEN)),
652};
653
654/* TXE Egress errors that cause an SPC freeze */
655#define ALL_TXE_EGRESS_FREEZE_ERR \
656 (SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY) \
657 | SEES(TX_PIO_LAUNCH_INTF_PARITY) \
658 | SEES(TX_SDMA_LAUNCH_INTF_PARITY) \
659 | SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY) \
660 | SEES(TX_LAUNCH_CSR_PARITY) \
661 | SEES(TX_SBRD_CTL_CSR_PARITY) \
662 | SEES(TX_CONFIG_PARITY) \
663 | SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY) \
664 | SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY) \
665 | SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY) \
666 | SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY) \
667 | SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY) \
668 | SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY) \
669 | SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY) \
670 | SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY) \
671 | SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY) \
672 | SEES(TX_CREDIT_RETURN_PARITY))
673
674/*
675 * TXE Send error flags
676 */
677#define SES(name) SEND_ERR_STATUS_SEND_##name##_ERR_SMASK
678static struct flag_table send_err_status_flags[] = {
2c5b521a 679/* 0*/ FLAG_ENTRY0("SendCsrParityErr", SES(CSR_PARITY)),
77241056
MM		 680/* 1*/ FLAG_ENTRY0("SendCsrReadBadAddrErr", SES(CSR_READ_BAD_ADDR)),
681/* 2*/ FLAG_ENTRY0("SendCsrWriteBadAddrErr", SES(CSR_WRITE_BAD_ADDR))
682};
683
684/*
685 * TXE Send Context Error flags and consequences
686 */
687static struct flag_table sc_err_status_flags[] = {
688/* 0*/ FLAG_ENTRY("InconsistentSop",
689 SEC_PACKET_DROPPED | SEC_SC_HALTED,
690 SEND_CTXT_ERR_STATUS_PIO_INCONSISTENT_SOP_ERR_SMASK),
691/* 1*/ FLAG_ENTRY("DisallowedPacket",
692 SEC_PACKET_DROPPED | SEC_SC_HALTED,
693 SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK),
694/* 2*/ FLAG_ENTRY("WriteCrossesBoundary",
695 SEC_WRITE_DROPPED | SEC_SC_HALTED,
696 SEND_CTXT_ERR_STATUS_PIO_WRITE_CROSSES_BOUNDARY_ERR_SMASK),
697/* 3*/ FLAG_ENTRY("WriteOverflow",
698 SEC_WRITE_DROPPED | SEC_SC_HALTED,
699 SEND_CTXT_ERR_STATUS_PIO_WRITE_OVERFLOW_ERR_SMASK),
700/* 4*/ FLAG_ENTRY("WriteOutOfBounds",
701 SEC_WRITE_DROPPED | SEC_SC_HALTED,
702 SEND_CTXT_ERR_STATUS_PIO_WRITE_OUT_OF_BOUNDS_ERR_SMASK),
703/* 5-63 reserved*/
704};
705
706/*
707 * RXE Receive Error flags
708 */
709#define RXES(name) RCV_ERR_STATUS_RX_##name##_ERR_SMASK
710static struct flag_table rxe_err_status_flags[] = {
711/* 0*/ FLAG_ENTRY0("RxDmaCsrCorErr", RXES(DMA_CSR_COR)),
712/* 1*/ FLAG_ENTRY0("RxDcIntfParityErr", RXES(DC_INTF_PARITY)),
713/* 2*/ FLAG_ENTRY0("RxRcvHdrUncErr", RXES(RCV_HDR_UNC)),
714/* 3*/ FLAG_ENTRY0("RxRcvHdrCorErr", RXES(RCV_HDR_COR)),
715/* 4*/ FLAG_ENTRY0("RxRcvDataUncErr", RXES(RCV_DATA_UNC)),
716/* 5*/ FLAG_ENTRY0("RxRcvDataCorErr", RXES(RCV_DATA_COR)),
717/* 6*/ FLAG_ENTRY0("RxRcvQpMapTableUncErr", RXES(RCV_QP_MAP_TABLE_UNC)),
718/* 7*/ FLAG_ENTRY0("RxRcvQpMapTableCorErr", RXES(RCV_QP_MAP_TABLE_COR)),
719/* 8*/ FLAG_ENTRY0("RxRcvCsrParityErr", RXES(RCV_CSR_PARITY)),
720/* 9*/ FLAG_ENTRY0("RxDcSopEopParityErr", RXES(DC_SOP_EOP_PARITY)),
721/*10*/ FLAG_ENTRY0("RxDmaFlagUncErr", RXES(DMA_FLAG_UNC)),
722/*11*/ FLAG_ENTRY0("RxDmaFlagCorErr", RXES(DMA_FLAG_COR)),
723/*12*/ FLAG_ENTRY0("RxRcvFsmEncodingErr", RXES(RCV_FSM_ENCODING)),
724/*13*/ FLAG_ENTRY0("RxRbufFreeListUncErr", RXES(RBUF_FREE_LIST_UNC)),
725/*14*/ FLAG_ENTRY0("RxRbufFreeListCorErr", RXES(RBUF_FREE_LIST_COR)),
726/*15*/ FLAG_ENTRY0("RxRbufLookupDesRegUncErr", RXES(RBUF_LOOKUP_DES_REG_UNC)),
727/*16*/ FLAG_ENTRY0("RxRbufLookupDesRegUncCorErr",
728 RXES(RBUF_LOOKUP_DES_REG_UNC_COR)),
729/*17*/ FLAG_ENTRY0("RxRbufLookupDesUncErr", RXES(RBUF_LOOKUP_DES_UNC)),
730/*18*/ FLAG_ENTRY0("RxRbufLookupDesCorErr", RXES(RBUF_LOOKUP_DES_COR)),
731/*19*/ FLAG_ENTRY0("RxRbufBlockListReadUncErr",
732 RXES(RBUF_BLOCK_LIST_READ_UNC)),
733/*20*/ FLAG_ENTRY0("RxRbufBlockListReadCorErr",
734 RXES(RBUF_BLOCK_LIST_READ_COR)),
735/*21*/ FLAG_ENTRY0("RxRbufCsrQHeadBufNumParityErr",
736 RXES(RBUF_CSR_QHEAD_BUF_NUM_PARITY)),
737/*22*/ FLAG_ENTRY0("RxRbufCsrQEntCntParityErr",
738 RXES(RBUF_CSR_QENT_CNT_PARITY)),
739/*23*/ FLAG_ENTRY0("RxRbufCsrQNextBufParityErr",
740 RXES(RBUF_CSR_QNEXT_BUF_PARITY)),
741/*24*/ FLAG_ENTRY0("RxRbufCsrQVldBitParityErr",
742 RXES(RBUF_CSR_QVLD_BIT_PARITY)),
743/*25*/ FLAG_ENTRY0("RxRbufCsrQHdPtrParityErr", RXES(RBUF_CSR_QHD_PTR_PARITY)),
744/*26*/ FLAG_ENTRY0("RxRbufCsrQTlPtrParityErr", RXES(RBUF_CSR_QTL_PTR_PARITY)),
745/*27*/ FLAG_ENTRY0("RxRbufCsrQNumOfPktParityErr",
746 RXES(RBUF_CSR_QNUM_OF_PKT_PARITY)),
747/*28*/ FLAG_ENTRY0("RxRbufCsrQEOPDWParityErr", RXES(RBUF_CSR_QEOPDW_PARITY)),
748/*29*/ FLAG_ENTRY0("RxRbufCtxIdParityErr", RXES(RBUF_CTX_ID_PARITY)),
749/*30*/ FLAG_ENTRY0("RxRBufBadLookupErr", RXES(RBUF_BAD_LOOKUP)),
750/*31*/ FLAG_ENTRY0("RxRbufFullErr", RXES(RBUF_FULL)),
751/*32*/ FLAG_ENTRY0("RxRbufEmptyErr", RXES(RBUF_EMPTY)),
752/*33*/ FLAG_ENTRY0("RxRbufFlRdAddrParityErr", RXES(RBUF_FL_RD_ADDR_PARITY)),
753/*34*/ FLAG_ENTRY0("RxRbufFlWrAddrParityErr", RXES(RBUF_FL_WR_ADDR_PARITY)),
754/*35*/ FLAG_ENTRY0("RxRbufFlInitdoneParityErr",
755 RXES(RBUF_FL_INITDONE_PARITY)),
756/*36*/ FLAG_ENTRY0("RxRbufFlInitWrAddrParityErr",
757 RXES(RBUF_FL_INIT_WR_ADDR_PARITY)),
758/*37*/ FLAG_ENTRY0("RxRbufNextFreeBufUncErr", RXES(RBUF_NEXT_FREE_BUF_UNC)),
759/*38*/ FLAG_ENTRY0("RxRbufNextFreeBufCorErr", RXES(RBUF_NEXT_FREE_BUF_COR)),
760/*39*/ FLAG_ENTRY0("RxLookupDesPart1UncErr", RXES(LOOKUP_DES_PART1_UNC)),
761/*40*/ FLAG_ENTRY0("RxLookupDesPart1UncCorErr",
762 RXES(LOOKUP_DES_PART1_UNC_COR)),
763/*41*/ FLAG_ENTRY0("RxLookupDesPart2ParityErr",
764 RXES(LOOKUP_DES_PART2_PARITY)),
765/*42*/ FLAG_ENTRY0("RxLookupRcvArrayUncErr", RXES(LOOKUP_RCV_ARRAY_UNC)),
766/*43*/ FLAG_ENTRY0("RxLookupRcvArrayCorErr", RXES(LOOKUP_RCV_ARRAY_COR)),
767/*44*/ FLAG_ENTRY0("RxLookupCsrParityErr", RXES(LOOKUP_CSR_PARITY)),
768/*45*/ FLAG_ENTRY0("RxHqIntrCsrParityErr", RXES(HQ_INTR_CSR_PARITY)),
769/*46*/ FLAG_ENTRY0("RxHqIntrFsmErr", RXES(HQ_INTR_FSM)),
770/*47*/ FLAG_ENTRY0("RxRbufDescPart1UncErr", RXES(RBUF_DESC_PART1_UNC)),
771/*48*/ FLAG_ENTRY0("RxRbufDescPart1CorErr", RXES(RBUF_DESC_PART1_COR)),
772/*49*/ FLAG_ENTRY0("RxRbufDescPart2UncErr", RXES(RBUF_DESC_PART2_UNC)),
773/*50*/ FLAG_ENTRY0("RxRbufDescPart2CorErr", RXES(RBUF_DESC_PART2_COR)),
774/*51*/ FLAG_ENTRY0("RxDmaHdrFifoRdUncErr", RXES(DMA_HDR_FIFO_RD_UNC)),
775/*52*/ FLAG_ENTRY0("RxDmaHdrFifoRdCorErr", RXES(DMA_HDR_FIFO_RD_COR)),
776/*53*/ FLAG_ENTRY0("RxDmaDataFifoRdUncErr", RXES(DMA_DATA_FIFO_RD_UNC)),
777/*54*/ FLAG_ENTRY0("RxDmaDataFifoRdCorErr", RXES(DMA_DATA_FIFO_RD_COR)),
778/*55*/ FLAG_ENTRY0("RxRbufDataUncErr", RXES(RBUF_DATA_UNC)),
779/*56*/ FLAG_ENTRY0("RxRbufDataCorErr", RXES(RBUF_DATA_COR)),
780/*57*/ FLAG_ENTRY0("RxDmaCsrParityErr", RXES(DMA_CSR_PARITY)),
781/*58*/ FLAG_ENTRY0("RxDmaEqFsmEncodingErr", RXES(DMA_EQ_FSM_ENCODING)),
782/*59*/ FLAG_ENTRY0("RxDmaDqFsmEncodingErr", RXES(DMA_DQ_FSM_ENCODING)),
783/*60*/ FLAG_ENTRY0("RxDmaCsrUncErr", RXES(DMA_CSR_UNC)),
784/*61*/ FLAG_ENTRY0("RxCsrReadBadAddrErr", RXES(CSR_READ_BAD_ADDR)),
785/*62*/ FLAG_ENTRY0("RxCsrWriteBadAddrErr", RXES(CSR_WRITE_BAD_ADDR)),
786/*63*/ FLAG_ENTRY0("RxCsrParityErr", RXES(CSR_PARITY))
787};
788
789/* RXE errors that will trigger an SPC freeze */
790#define ALL_RXE_FREEZE_ERR \
791 (RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_UNC_ERR_SMASK \
792 | RCV_ERR_STATUS_RX_RCV_CSR_PARITY_ERR_SMASK \
793 | RCV_ERR_STATUS_RX_DMA_FLAG_UNC_ERR_SMASK \
794 | RCV_ERR_STATUS_RX_RCV_FSM_ENCODING_ERR_SMASK \
795 | RCV_ERR_STATUS_RX_RBUF_FREE_LIST_UNC_ERR_SMASK \
796 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_ERR_SMASK \
797 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR_SMASK \
798 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_UNC_ERR_SMASK \
799 | RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_UNC_ERR_SMASK \
800 | RCV_ERR_STATUS_RX_RBUF_CSR_QHEAD_BUF_NUM_PARITY_ERR_SMASK \
801 | RCV_ERR_STATUS_RX_RBUF_CSR_QENT_CNT_PARITY_ERR_SMASK \
802 | RCV_ERR_STATUS_RX_RBUF_CSR_QNEXT_BUF_PARITY_ERR_SMASK \
803 | RCV_ERR_STATUS_RX_RBUF_CSR_QVLD_BIT_PARITY_ERR_SMASK \
804 | RCV_ERR_STATUS_RX_RBUF_CSR_QHD_PTR_PARITY_ERR_SMASK \
805 | RCV_ERR_STATUS_RX_RBUF_CSR_QTL_PTR_PARITY_ERR_SMASK \
806 | RCV_ERR_STATUS_RX_RBUF_CSR_QNUM_OF_PKT_PARITY_ERR_SMASK \
807 | RCV_ERR_STATUS_RX_RBUF_CSR_QEOPDW_PARITY_ERR_SMASK \
808 | RCV_ERR_STATUS_RX_RBUF_CTX_ID_PARITY_ERR_SMASK \
809 | RCV_ERR_STATUS_RX_RBUF_BAD_LOOKUP_ERR_SMASK \
810 | RCV_ERR_STATUS_RX_RBUF_FULL_ERR_SMASK \
811 | RCV_ERR_STATUS_RX_RBUF_EMPTY_ERR_SMASK \
812 | RCV_ERR_STATUS_RX_RBUF_FL_RD_ADDR_PARITY_ERR_SMASK \
813 | RCV_ERR_STATUS_RX_RBUF_FL_WR_ADDR_PARITY_ERR_SMASK \
814 | RCV_ERR_STATUS_RX_RBUF_FL_INITDONE_PARITY_ERR_SMASK \
815 | RCV_ERR_STATUS_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR_SMASK \
816 | RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_UNC_ERR_SMASK \
817 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_ERR_SMASK \
818 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_COR_ERR_SMASK \
819 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART2_PARITY_ERR_SMASK \
820 | RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_UNC_ERR_SMASK \
821 | RCV_ERR_STATUS_RX_LOOKUP_CSR_PARITY_ERR_SMASK \
822 | RCV_ERR_STATUS_RX_HQ_INTR_CSR_PARITY_ERR_SMASK \
823 | RCV_ERR_STATUS_RX_HQ_INTR_FSM_ERR_SMASK \
824 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_UNC_ERR_SMASK \
825 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_COR_ERR_SMASK \
826 | RCV_ERR_STATUS_RX_RBUF_DESC_PART2_UNC_ERR_SMASK \
827 | RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK \
828 | RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK \
829 | RCV_ERR_STATUS_RX_RBUF_DATA_UNC_ERR_SMASK \
830 | RCV_ERR_STATUS_RX_DMA_CSR_PARITY_ERR_SMASK \
831 | RCV_ERR_STATUS_RX_DMA_EQ_FSM_ENCODING_ERR_SMASK \
832 | RCV_ERR_STATUS_RX_DMA_DQ_FSM_ENCODING_ERR_SMASK \
833 | RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK \
834 | RCV_ERR_STATUS_RX_CSR_PARITY_ERR_SMASK)
835
836#define RXE_FREEZE_ABORT_MASK \
837 (RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK | \
838 RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK | \
839 RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK)
840
841/*
842 * DCC Error Flags
843 */
844#define DCCE(name) DCC_ERR_FLG_##name##_SMASK
845static struct flag_table dcc_err_flags[] = {
846 FLAG_ENTRY0("bad_l2_err", DCCE(BAD_L2_ERR)),
847 FLAG_ENTRY0("bad_sc_err", DCCE(BAD_SC_ERR)),
848 FLAG_ENTRY0("bad_mid_tail_err", DCCE(BAD_MID_TAIL_ERR)),
849 FLAG_ENTRY0("bad_preemption_err", DCCE(BAD_PREEMPTION_ERR)),
850 FLAG_ENTRY0("preemption_err", DCCE(PREEMPTION_ERR)),
851 FLAG_ENTRY0("preemptionvl15_err", DCCE(PREEMPTIONVL15_ERR)),
852 FLAG_ENTRY0("bad_vl_marker_err", DCCE(BAD_VL_MARKER_ERR)),
853 FLAG_ENTRY0("bad_dlid_target_err", DCCE(BAD_DLID_TARGET_ERR)),
854 FLAG_ENTRY0("bad_lver_err", DCCE(BAD_LVER_ERR)),
855 FLAG_ENTRY0("uncorrectable_err", DCCE(UNCORRECTABLE_ERR)),
856 FLAG_ENTRY0("bad_crdt_ack_err", DCCE(BAD_CRDT_ACK_ERR)),
857 FLAG_ENTRY0("unsup_pkt_type", DCCE(UNSUP_PKT_TYPE)),
858 FLAG_ENTRY0("bad_ctrl_flit_err", DCCE(BAD_CTRL_FLIT_ERR)),
859 FLAG_ENTRY0("event_cntr_parity_err", DCCE(EVENT_CNTR_PARITY_ERR)),
860 FLAG_ENTRY0("event_cntr_rollover_err", DCCE(EVENT_CNTR_ROLLOVER_ERR)),
861 FLAG_ENTRY0("link_err", DCCE(LINK_ERR)),
862 FLAG_ENTRY0("misc_cntr_rollover_err", DCCE(MISC_CNTR_ROLLOVER_ERR)),
863 FLAG_ENTRY0("bad_ctrl_dist_err", DCCE(BAD_CTRL_DIST_ERR)),
864 FLAG_ENTRY0("bad_tail_dist_err", DCCE(BAD_TAIL_DIST_ERR)),
865 FLAG_ENTRY0("bad_head_dist_err", DCCE(BAD_HEAD_DIST_ERR)),
866 FLAG_ENTRY0("nonvl15_state_err", DCCE(NONVL15_STATE_ERR)),
867 FLAG_ENTRY0("vl15_multi_err", DCCE(VL15_MULTI_ERR)),
868 FLAG_ENTRY0("bad_pkt_length_err", DCCE(BAD_PKT_LENGTH_ERR)),
869 FLAG_ENTRY0("unsup_vl_err", DCCE(UNSUP_VL_ERR)),
870 FLAG_ENTRY0("perm_nvl15_err", DCCE(PERM_NVL15_ERR)),
871 FLAG_ENTRY0("slid_zero_err", DCCE(SLID_ZERO_ERR)),
872 FLAG_ENTRY0("dlid_zero_err", DCCE(DLID_ZERO_ERR)),
873 FLAG_ENTRY0("length_mtu_err", DCCE(LENGTH_MTU_ERR)),
874 FLAG_ENTRY0("rx_early_drop_err", DCCE(RX_EARLY_DROP_ERR)),
875 FLAG_ENTRY0("late_short_err", DCCE(LATE_SHORT_ERR)),
876 FLAG_ENTRY0("late_long_err", DCCE(LATE_LONG_ERR)),
877 FLAG_ENTRY0("late_ebp_err", DCCE(LATE_EBP_ERR)),
878 FLAG_ENTRY0("fpe_tx_fifo_ovflw_err", DCCE(FPE_TX_FIFO_OVFLW_ERR)),
879 FLAG_ENTRY0("fpe_tx_fifo_unflw_err", DCCE(FPE_TX_FIFO_UNFLW_ERR)),
880 FLAG_ENTRY0("csr_access_blocked_host", DCCE(CSR_ACCESS_BLOCKED_HOST)),
881 FLAG_ENTRY0("csr_access_blocked_uc", DCCE(CSR_ACCESS_BLOCKED_UC)),
882 FLAG_ENTRY0("tx_ctrl_parity_err", DCCE(TX_CTRL_PARITY_ERR)),
883 FLAG_ENTRY0("tx_ctrl_parity_mbe_err", DCCE(TX_CTRL_PARITY_MBE_ERR)),
884 FLAG_ENTRY0("tx_sc_parity_err", DCCE(TX_SC_PARITY_ERR)),
885 FLAG_ENTRY0("rx_ctrl_parity_mbe_err", DCCE(RX_CTRL_PARITY_MBE_ERR)),
886 FLAG_ENTRY0("csr_parity_err", DCCE(CSR_PARITY_ERR)),
887 FLAG_ENTRY0("csr_inval_addr", DCCE(CSR_INVAL_ADDR)),
888 FLAG_ENTRY0("tx_byte_shft_parity_err", DCCE(TX_BYTE_SHFT_PARITY_ERR)),
889 FLAG_ENTRY0("rx_byte_shft_parity_err", DCCE(RX_BYTE_SHFT_PARITY_ERR)),
890 FLAG_ENTRY0("fmconfig_err", DCCE(FMCONFIG_ERR)),
891 FLAG_ENTRY0("rcvport_err", DCCE(RCVPORT_ERR)),
892};
893
894/*
895 * LCB error flags
896 */
897#define LCBE(name) DC_LCB_ERR_FLG_##name##_SMASK
898static struct flag_table lcb_err_flags[] = {
899/* 0*/ FLAG_ENTRY0("CSR_PARITY_ERR", LCBE(CSR_PARITY_ERR)),
900/* 1*/ FLAG_ENTRY0("INVALID_CSR_ADDR", LCBE(INVALID_CSR_ADDR)),
901/* 2*/ FLAG_ENTRY0("RST_FOR_FAILED_DESKEW", LCBE(RST_FOR_FAILED_DESKEW)),
902/* 3*/ FLAG_ENTRY0("ALL_LNS_FAILED_REINIT_TEST",
903 LCBE(ALL_LNS_FAILED_REINIT_TEST)),
904/* 4*/ FLAG_ENTRY0("LOST_REINIT_STALL_OR_TOS", LCBE(LOST_REINIT_STALL_OR_TOS)),
905/* 5*/ FLAG_ENTRY0("TX_LESS_THAN_FOUR_LNS", LCBE(TX_LESS_THAN_FOUR_LNS)),
906/* 6*/ FLAG_ENTRY0("RX_LESS_THAN_FOUR_LNS", LCBE(RX_LESS_THAN_FOUR_LNS)),
907/* 7*/ FLAG_ENTRY0("SEQ_CRC_ERR", LCBE(SEQ_CRC_ERR)),
908/* 8*/ FLAG_ENTRY0("REINIT_FROM_PEER", LCBE(REINIT_FROM_PEER)),
909/* 9*/ FLAG_ENTRY0("REINIT_FOR_LN_DEGRADE", LCBE(REINIT_FOR_LN_DEGRADE)),
910/*10*/ FLAG_ENTRY0("CRC_ERR_CNT_HIT_LIMIT", LCBE(CRC_ERR_CNT_HIT_LIMIT)),
911/*11*/ FLAG_ENTRY0("RCLK_STOPPED", LCBE(RCLK_STOPPED)),
912/*12*/ FLAG_ENTRY0("UNEXPECTED_REPLAY_MARKER", LCBE(UNEXPECTED_REPLAY_MARKER)),
913/*13*/ FLAG_ENTRY0("UNEXPECTED_ROUND_TRIP_MARKER",
914 LCBE(UNEXPECTED_ROUND_TRIP_MARKER)),
915/*14*/ FLAG_ENTRY0("ILLEGAL_NULL_LTP", LCBE(ILLEGAL_NULL_LTP)),
916/*15*/ FLAG_ENTRY0("ILLEGAL_FLIT_ENCODING", LCBE(ILLEGAL_FLIT_ENCODING)),
917/*16*/ FLAG_ENTRY0("FLIT_INPUT_BUF_OFLW", LCBE(FLIT_INPUT_BUF_OFLW)),
918/*17*/ FLAG_ENTRY0("VL_ACK_INPUT_BUF_OFLW", LCBE(VL_ACK_INPUT_BUF_OFLW)),
919/*18*/ FLAG_ENTRY0("VL_ACK_INPUT_PARITY_ERR", LCBE(VL_ACK_INPUT_PARITY_ERR)),
920/*19*/ FLAG_ENTRY0("VL_ACK_INPUT_WRONG_CRC_MODE",
921 LCBE(VL_ACK_INPUT_WRONG_CRC_MODE)),
922/*20*/ FLAG_ENTRY0("FLIT_INPUT_BUF_MBE", LCBE(FLIT_INPUT_BUF_MBE)),
923/*21*/ FLAG_ENTRY0("FLIT_INPUT_BUF_SBE", LCBE(FLIT_INPUT_BUF_SBE)),
924/*22*/ FLAG_ENTRY0("REPLAY_BUF_MBE", LCBE(REPLAY_BUF_MBE)),
925/*23*/ FLAG_ENTRY0("REPLAY_BUF_SBE", LCBE(REPLAY_BUF_SBE)),
926/*24*/ FLAG_ENTRY0("CREDIT_RETURN_FLIT_MBE", LCBE(CREDIT_RETURN_FLIT_MBE)),
927/*25*/ FLAG_ENTRY0("RST_FOR_LINK_TIMEOUT", LCBE(RST_FOR_LINK_TIMEOUT)),
928/*26*/ FLAG_ENTRY0("RST_FOR_INCOMPLT_RND_TRIP",
929 LCBE(RST_FOR_INCOMPLT_RND_TRIP)),
930/*27*/ FLAG_ENTRY0("HOLD_REINIT", LCBE(HOLD_REINIT)),
931/*28*/ FLAG_ENTRY0("NEG_EDGE_LINK_TRANSFER_ACTIVE",
932 LCBE(NEG_EDGE_LINK_TRANSFER_ACTIVE)),
933/*29*/ FLAG_ENTRY0("REDUNDANT_FLIT_PARITY_ERR",
934 LCBE(REDUNDANT_FLIT_PARITY_ERR))
935};
936
937/*
938 * DC8051 Error Flags
939 */
940#define D8E(name) DC_DC8051_ERR_FLG_##name##_SMASK
941static struct flag_table dc8051_err_flags[] = {
942 FLAG_ENTRY0("SET_BY_8051", D8E(SET_BY_8051)),
943 FLAG_ENTRY0("LOST_8051_HEART_BEAT", D8E(LOST_8051_HEART_BEAT)),
944 FLAG_ENTRY0("CRAM_MBE", D8E(CRAM_MBE)),
945 FLAG_ENTRY0("CRAM_SBE", D8E(CRAM_SBE)),
946 FLAG_ENTRY0("DRAM_MBE", D8E(DRAM_MBE)),
947 FLAG_ENTRY0("DRAM_SBE", D8E(DRAM_SBE)),
948 FLAG_ENTRY0("IRAM_MBE", D8E(IRAM_MBE)),
949 FLAG_ENTRY0("IRAM_SBE", D8E(IRAM_SBE)),
950 FLAG_ENTRY0("UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES",
17fb4f29 951 D8E(UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES)),
77241056
MM		 952 FLAG_ENTRY0("INVALID_CSR_ADDR", D8E(INVALID_CSR_ADDR)),
953};
954
955/*
956 * DC8051 Information Error flags
957 *
958 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.ERROR field.
959 */
960static struct flag_table dc8051_info_err_flags[] = {
961 FLAG_ENTRY0("Spico ROM check failed", SPICO_ROM_FAILED),
962 FLAG_ENTRY0("Unknown frame received", UNKNOWN_FRAME),
963 FLAG_ENTRY0("Target BER not met", TARGET_BER_NOT_MET),
964 FLAG_ENTRY0("Serdes internal loopback failure",
17fb4f29 965 FAILED_SERDES_INTERNAL_LOOPBACK),
77241056
MM		 966 FLAG_ENTRY0("Failed SerDes init", FAILED_SERDES_INIT),
967 FLAG_ENTRY0("Failed LNI(Polling)", FAILED_LNI_POLLING),
968 FLAG_ENTRY0("Failed LNI(Debounce)", FAILED_LNI_DEBOUNCE),
969 FLAG_ENTRY0("Failed LNI(EstbComm)", FAILED_LNI_ESTBCOMM),
970 FLAG_ENTRY0("Failed LNI(OptEq)", FAILED_LNI_OPTEQ),
971 FLAG_ENTRY0("Failed LNI(VerifyCap_1)", FAILED_LNI_VERIFY_CAP1),
972 FLAG_ENTRY0("Failed LNI(VerifyCap_2)", FAILED_LNI_VERIFY_CAP2),
8fefef12 973 FLAG_ENTRY0("Failed LNI(ConfigLT)", FAILED_LNI_CONFIGLT),
50921be0
DL		 974 FLAG_ENTRY0("Host Handshake Timeout", HOST_HANDSHAKE_TIMEOUT),
975 FLAG_ENTRY0("External Device Request Timeout",
976 EXTERNAL_DEVICE_REQ_TIMEOUT),
77241056
MM		 977};
978
979/*
980 * DC8051 Information Host Information flags
981 *
982 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.HOST_MSG field.
983 */
984static struct flag_table dc8051_info_host_msg_flags[] = {
985 FLAG_ENTRY0("Host request done", 0x0001),
986 FLAG_ENTRY0("BC SMA message", 0x0002),
987 FLAG_ENTRY0("BC PWR_MGM message", 0x0004),
988 FLAG_ENTRY0("BC Unknown message (BCC)", 0x0008),
989 FLAG_ENTRY0("BC Unknown message (LCB)", 0x0010),
990 FLAG_ENTRY0("External device config request", 0x0020),
991 FLAG_ENTRY0("VerifyCap all frames received", 0x0040),
992 FLAG_ENTRY0("LinkUp achieved", 0x0080),
993 FLAG_ENTRY0("Link going down", 0x0100),
994};
995
77241056
MM		 996static u32 encoded_size(u32 size);
997static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate);
998static int set_physical_link_state(struct hfi1_devdata *dd, u64 state);
999static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management,
1000 u8 *continuous);
1001static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z,
1002 u8 *vcu, u16 *vl15buf, u8 *crc_sizes);
1003static void read_vc_remote_link_width(struct hfi1_devdata *dd,
1004 u8 *remote_tx_rate, u16 *link_widths);
1005static void read_vc_local_link_width(struct hfi1_devdata *dd, u8 *misc_bits,
1006 u8 *flag_bits, u16 *link_widths);
1007static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id,
1008 u8 *device_rev);
1009static void read_mgmt_allowed(struct hfi1_devdata *dd, u8 *mgmt_allowed);
1010static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx);
1011static int read_tx_settings(struct hfi1_devdata *dd, u8 *enable_lane_tx,
1012 u8 *tx_polarity_inversion,
1013 u8 *rx_polarity_inversion, u8 *max_rate);
1014static void handle_sdma_eng_err(struct hfi1_devdata *dd,
1015 unsigned int context, u64 err_status);
1016static void handle_qsfp_int(struct hfi1_devdata *dd, u32 source, u64 reg);
1017static void handle_dcc_err(struct hfi1_devdata *dd,
1018 unsigned int context, u64 err_status);
1019static void handle_lcb_err(struct hfi1_devdata *dd,
1020 unsigned int context, u64 err_status);
1021static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg);
1022static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1023static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1024static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1025static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1026static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1027static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1028static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1029static void set_partition_keys(struct hfi1_pportdata *);
1030static const char *link_state_name(u32 state);
1031static const char *link_state_reason_name(struct hfi1_pportdata *ppd,
1032 u32 state);
1033static int do_8051_command(struct hfi1_devdata *dd, u32 type, u64 in_data,
1034 u64 *out_data);
1035static int read_idle_sma(struct hfi1_devdata *dd, u64 *data);
1036static int thermal_init(struct hfi1_devdata *dd);
1037
1038static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state,
1039 int msecs);
1040static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc);
feb831dd 1041static void read_link_down_reason(struct hfi1_devdata *dd, u8 *ldr);
77241056
MM		 1042static void handle_temp_err(struct hfi1_devdata *);
1043static void dc_shutdown(struct hfi1_devdata *);
1044static void dc_start(struct hfi1_devdata *);
8f000f7f
DL		 1045static int qos_rmt_entries(struct hfi1_devdata *dd, unsigned int *mp,
1046 unsigned int *np);
3ec5fa28 1047static void clear_full_mgmt_pkey(struct hfi1_pportdata *ppd);
ec8a1423 1048static int wait_link_transfer_active(struct hfi1_devdata *dd, int wait_ms);
77241056
MM		 1049
1050/*
1051 * Error interrupt table entry. This is used as input to the interrupt
1052 * "clear down" routine used for all second tier error interrupt register.
1053 * Second tier interrupt registers have a single bit representing them
1054 * in the top-level CceIntStatus.
1055 */
1056struct err_reg_info {
1057 u32 status; /* status CSR offset */
1058 u32 clear; /* clear CSR offset */
1059 u32 mask; /* mask CSR offset */
1060 void (*handler)(struct hfi1_devdata *dd, u32 source, u64 reg);
1061 const char *desc;
1062};
1063
1064#define NUM_MISC_ERRS (IS_GENERAL_ERR_END - IS_GENERAL_ERR_START)
1065#define NUM_DC_ERRS (IS_DC_END - IS_DC_START)
1066#define NUM_VARIOUS (IS_VARIOUS_END - IS_VARIOUS_START)
1067
1068/*
1069 * Helpers for building HFI and DC error interrupt table entries. Different
1070 * helpers are needed because of inconsistent register names.
1071 */
1072#define EE(reg, handler, desc) \
1073 { reg##_STATUS, reg##_CLEAR, reg##_MASK, \
1074 handler, desc }
1075#define DC_EE1(reg, handler, desc) \
1076 { reg##_FLG, reg##_FLG_CLR, reg##_FLG_EN, handler, desc }
1077#define DC_EE2(reg, handler, desc) \
1078 { reg##_FLG, reg##_CLR, reg##_EN, handler, desc }
1079
1080/*
1081 * Table of the "misc" grouping of error interrupts. Each entry refers to
1082 * another register containing more information.
1083 */
1084static const struct err_reg_info misc_errs[NUM_MISC_ERRS] = {
1085/* 0*/ EE(CCE_ERR, handle_cce_err, "CceErr"),
1086/* 1*/ EE(RCV_ERR, handle_rxe_err, "RxeErr"),
1087/* 2*/ EE(MISC_ERR, handle_misc_err, "MiscErr"),
1088/* 3*/ { 0, 0, 0, NULL }, /* reserved */
1089/* 4*/ EE(SEND_PIO_ERR, handle_pio_err, "PioErr"),
1090/* 5*/ EE(SEND_DMA_ERR, handle_sdma_err, "SDmaErr"),
1091/* 6*/ EE(SEND_EGRESS_ERR, handle_egress_err, "EgressErr"),
1092/* 7*/ EE(SEND_ERR, handle_txe_err, "TxeErr")
1093 /* the rest are reserved */
1094};
1095
1096/*
1097 * Index into the Various section of the interrupt sources
1098 * corresponding to the Critical Temperature interrupt.
1099 */
1100#define TCRIT_INT_SOURCE 4
1101
1102/*
1103 * SDMA error interrupt entry - refers to another register containing more
1104 * information.
1105 */
1106static const struct err_reg_info sdma_eng_err =
1107 EE(SEND_DMA_ENG_ERR, handle_sdma_eng_err, "SDmaEngErr");
1108
1109static const struct err_reg_info various_err[NUM_VARIOUS] = {
1110/* 0*/ { 0, 0, 0, NULL }, /* PbcInt */
1111/* 1*/ { 0, 0, 0, NULL }, /* GpioAssertInt */
1112/* 2*/ EE(ASIC_QSFP1, handle_qsfp_int, "QSFP1"),
1113/* 3*/ EE(ASIC_QSFP2, handle_qsfp_int, "QSFP2"),
1114/* 4*/ { 0, 0, 0, NULL }, /* TCritInt */
1115 /* rest are reserved */
1116};
1117
1118/*
1119 * The DC encoding of mtu_cap for 10K MTU in the DCC_CFG_PORT_CONFIG
1120 * register can not be derived from the MTU value because 10K is not
1121 * a power of 2. Therefore, we need a constant. Everything else can
1122 * be calculated.
1123 */
1124#define DCC_CFG_PORT_MTU_CAP_10240 7
1125
1126/*
1127 * Table of the DC grouping of error interrupts. Each entry refers to
1128 * another register containing more information.
1129 */
1130static const struct err_reg_info dc_errs[NUM_DC_ERRS] = {
1131/* 0*/ DC_EE1(DCC_ERR, handle_dcc_err, "DCC Err"),
1132/* 1*/ DC_EE2(DC_LCB_ERR, handle_lcb_err, "LCB Err"),
1133/* 2*/ DC_EE2(DC_DC8051_ERR, handle_8051_interrupt, "DC8051 Interrupt"),
1134/* 3*/ /* dc_lbm_int - special, see is_dc_int() */
1135 /* the rest are reserved */
1136};
1137
1138struct cntr_entry {
1139 /*
1140 * counter name
1141 */
1142 char *name;
1143
1144 /*
1145 * csr to read for name (if applicable)
1146 */
1147 u64 csr;
1148
1149 /*
1150 * offset into dd or ppd to store the counter's value
1151 */
1152 int offset;
1153
1154 /*
1155 * flags
1156 */
1157 u8 flags;
1158
1159 /*
1160 * accessor for stat element, context either dd or ppd
1161 */
17fb4f29
JJ		 1162 u64 (*rw_cntr)(const struct cntr_entry *, void *context, int vl,
1163 int mode, u64 data);
77241056
MM		 1164};
1165
1166#define C_RCV_HDR_OVF_FIRST C_RCV_HDR_OVF_0
1167#define C_RCV_HDR_OVF_LAST C_RCV_HDR_OVF_159
1168
1169#define CNTR_ELEM(name, csr, offset, flags, accessor) \
1170{ \
1171 name, \
1172 csr, \
1173 offset, \
1174 flags, \
1175 accessor \
1176}
1177
1178/* 32bit RXE */
1179#define RXE32_PORT_CNTR_ELEM(name, counter, flags) \
1180CNTR_ELEM(#name, \
1181 (counter * 8 + RCV_COUNTER_ARRAY32), \
1182 0, flags | CNTR_32BIT, \
1183 port_access_u32_csr)
1184
1185#define RXE32_DEV_CNTR_ELEM(name, counter, flags) \
1186CNTR_ELEM(#name, \
1187 (counter * 8 + RCV_COUNTER_ARRAY32), \
1188 0, flags | CNTR_32BIT, \
1189 dev_access_u32_csr)
1190
1191/* 64bit RXE */
1192#define RXE64_PORT_CNTR_ELEM(name, counter, flags) \
1193CNTR_ELEM(#name, \
1194 (counter * 8 + RCV_COUNTER_ARRAY64), \
1195 0, flags, \
1196 port_access_u64_csr)
1197
1198#define RXE64_DEV_CNTR_ELEM(name, counter, flags) \
1199CNTR_ELEM(#name, \
1200 (counter * 8 + RCV_COUNTER_ARRAY64), \
1201 0, flags, \
1202 dev_access_u64_csr)
1203
1204#define OVR_LBL(ctx) C_RCV_HDR_OVF_ ## ctx
1205#define OVR_ELM(ctx) \
1206CNTR_ELEM("RcvHdrOvr" #ctx, \
8638b77f 1207 (RCV_HDR_OVFL_CNT + ctx * 0x100), \
77241056
MM		 1208 0, CNTR_NORMAL, port_access_u64_csr)
1209
1210/* 32bit TXE */
1211#define TXE32_PORT_CNTR_ELEM(name, counter, flags) \
1212CNTR_ELEM(#name, \
1213 (counter * 8 + SEND_COUNTER_ARRAY32), \
1214 0, flags | CNTR_32BIT, \
1215 port_access_u32_csr)
1216
1217/* 64bit TXE */
1218#define TXE64_PORT_CNTR_ELEM(name, counter, flags) \
1219CNTR_ELEM(#name, \
1220 (counter * 8 + SEND_COUNTER_ARRAY64), \
1221 0, flags, \
1222 port_access_u64_csr)
1223
1224# define TX64_DEV_CNTR_ELEM(name, counter, flags) \
1225CNTR_ELEM(#name,\
1226 counter * 8 + SEND_COUNTER_ARRAY64, \
1227 0, \
1228 flags, \
1229 dev_access_u64_csr)
1230
1231/* CCE */
1232#define CCE_PERF_DEV_CNTR_ELEM(name, counter, flags) \
1233CNTR_ELEM(#name, \
1234 (counter * 8 + CCE_COUNTER_ARRAY32), \
1235 0, flags | CNTR_32BIT, \
1236 dev_access_u32_csr)
1237
1238#define CCE_INT_DEV_CNTR_ELEM(name, counter, flags) \
1239CNTR_ELEM(#name, \
1240 (counter * 8 + CCE_INT_COUNTER_ARRAY32), \
1241 0, flags | CNTR_32BIT, \
1242 dev_access_u32_csr)
1243
1244/* DC */
1245#define DC_PERF_CNTR(name, counter, flags) \
1246CNTR_ELEM(#name, \
1247 counter, \
1248 0, \
1249 flags, \
1250 dev_access_u64_csr)
1251
1252#define DC_PERF_CNTR_LCB(name, counter, flags) \
1253CNTR_ELEM(#name, \
1254 counter, \
1255 0, \
1256 flags, \
1257 dc_access_lcb_cntr)
1258
1259/* ibp counters */
1260#define SW_IBP_CNTR(name, cntr) \
1261CNTR_ELEM(#name, \
1262 0, \
1263 0, \
1264 CNTR_SYNTH, \
1265 access_ibp_##cntr)
1266
1267u64 read_csr(const struct hfi1_devdata *dd, u32 offset)
1268{
77241056 1269 if (dd->flags & HFI1_PRESENT) {
6d210eef 1270 return readq((void __iomem *)dd->kregbase + offset);
77241056
MM		 1271 }
1272 return -1;
1273}
1274
1275void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value)
1276{
1277 if (dd->flags & HFI1_PRESENT)
1278 writeq(value, (void __iomem *)dd->kregbase + offset);
1279}
1280
1281void __iomem *get_csr_addr(
1282 struct hfi1_devdata *dd,
1283 u32 offset)
1284{
1285 return (void __iomem *)dd->kregbase + offset;
1286}
1287
1288static inline u64 read_write_csr(const struct hfi1_devdata *dd, u32 csr,
1289 int mode, u64 value)
1290{
1291 u64 ret;
1292
77241056
MM		 1293 if (mode == CNTR_MODE_R) {
1294 ret = read_csr(dd, csr);
1295 } else if (mode == CNTR_MODE_W) {
1296 write_csr(dd, csr, value);
1297 ret = value;
1298 } else {
1299 dd_dev_err(dd, "Invalid cntr register access mode");
1300 return 0;
1301 }
1302
1303 hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, ret, mode);
1304 return ret;
1305}
1306
1307/* Dev Access */
1308static u64 dev_access_u32_csr(const struct cntr_entry *entry,
17fb4f29 1309 void *context, int vl, int mode, u64 data)
77241056 1310{
a787bde8 1311 struct hfi1_devdata *dd = context;
a699c6c2 1312 u64 csr = entry->csr;
77241056 1313
a699c6c2
VM		 1314 if (entry->flags & CNTR_SDMA) {
1315 if (vl == CNTR_INVALID_VL)
1316 return 0;
1317 csr += 0x100 * vl;
1318 } else {
1319 if (vl != CNTR_INVALID_VL)
1320 return 0;
1321 }
1322 return read_write_csr(dd, csr, mode, data);
1323}
1324
1325static u64 access_sde_err_cnt(const struct cntr_entry *entry,
1326 void *context, int idx, int mode, u64 data)
1327{
1328 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1329
1330 if (dd->per_sdma && idx < dd->num_sdma)
1331 return dd->per_sdma[idx].err_cnt;
1332 return 0;
1333}
1334
1335static u64 access_sde_int_cnt(const struct cntr_entry *entry,
1336 void *context, int idx, int mode, u64 data)
1337{
1338 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1339
1340 if (dd->per_sdma && idx < dd->num_sdma)
1341 return dd->per_sdma[idx].sdma_int_cnt;
1342 return 0;
1343}
1344
1345static u64 access_sde_idle_int_cnt(const struct cntr_entry *entry,
1346 void *context, int idx, int mode, u64 data)
1347{
1348 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1349
1350 if (dd->per_sdma && idx < dd->num_sdma)
1351 return dd->per_sdma[idx].idle_int_cnt;
1352 return 0;
1353}
1354
1355static u64 access_sde_progress_int_cnt(const struct cntr_entry *entry,
1356 void *context, int idx, int mode,
1357 u64 data)
1358{
1359 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1360
1361 if (dd->per_sdma && idx < dd->num_sdma)
1362 return dd->per_sdma[idx].progress_int_cnt;
1363 return 0;
77241056
MM		 1364}
1365
1366static u64 dev_access_u64_csr(const struct cntr_entry *entry, void *context,
17fb4f29 1367 int vl, int mode, u64 data)
77241056 1368{
a787bde8 1369 struct hfi1_devdata *dd = context;
77241056
MM		 1370
1371 u64 val = 0;
1372 u64 csr = entry->csr;
1373
1374 if (entry->flags & CNTR_VL) {
1375 if (vl == CNTR_INVALID_VL)
1376 return 0;
1377 csr += 8 * vl;
1378 } else {
1379 if (vl != CNTR_INVALID_VL)
1380 return 0;
1381 }
1382
1383 val = read_write_csr(dd, csr, mode, data);
1384 return val;
1385}
1386
1387static u64 dc_access_lcb_cntr(const struct cntr_entry *entry, void *context,
17fb4f29 1388 int vl, int mode, u64 data)
77241056 1389{
a787bde8 1390 struct hfi1_devdata *dd = context;
77241056
MM		 1391 u32 csr = entry->csr;
1392 int ret = 0;
1393
1394 if (vl != CNTR_INVALID_VL)
1395 return 0;
1396 if (mode == CNTR_MODE_R)
1397 ret = read_lcb_csr(dd, csr, &data);
1398 else if (mode == CNTR_MODE_W)
1399 ret = write_lcb_csr(dd, csr, data);
1400
1401 if (ret) {
1402 dd_dev_err(dd, "Could not acquire LCB for counter 0x%x", csr);
1403 return 0;
1404 }
1405
1406 hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, data, mode);
1407 return data;
1408}
1409
1410/* Port Access */
1411static u64 port_access_u32_csr(const struct cntr_entry *entry, void *context,
17fb4f29 1412 int vl, int mode, u64 data)
77241056 1413{
a787bde8 1414 struct hfi1_pportdata *ppd = context;
77241056
MM		 1415
1416 if (vl != CNTR_INVALID_VL)
1417 return 0;
1418 return read_write_csr(ppd->dd, entry->csr, mode, data);
1419}
1420
1421static u64 port_access_u64_csr(const struct cntr_entry *entry,
17fb4f29 1422 void *context, int vl, int mode, u64 data)
77241056 1423{
a787bde8 1424 struct hfi1_pportdata *ppd = context;
77241056
MM		 1425 u64 val;
1426 u64 csr = entry->csr;
1427
1428 if (entry->flags & CNTR_VL) {
1429 if (vl == CNTR_INVALID_VL)
1430 return 0;
1431 csr += 8 * vl;
1432 } else {
1433 if (vl != CNTR_INVALID_VL)
1434 return 0;
1435 }
1436 val = read_write_csr(ppd->dd, csr, mode, data);
1437 return val;
1438}
1439
1440/* Software defined */
1441static inline u64 read_write_sw(struct hfi1_devdata *dd, u64 *cntr, int mode,
1442 u64 data)
1443{
1444 u64 ret;
1445
1446 if (mode == CNTR_MODE_R) {
1447 ret = *cntr;
1448 } else if (mode == CNTR_MODE_W) {
1449 *cntr = data;
1450 ret = data;
1451 } else {
1452 dd_dev_err(dd, "Invalid cntr sw access mode");
1453 return 0;
1454 }
1455
1456 hfi1_cdbg(CNTR, "val 0x%llx mode %d", ret, mode);
1457
1458 return ret;
1459}
1460
1461static u64 access_sw_link_dn_cnt(const struct cntr_entry *entry, void *context,
17fb4f29 1462 int vl, int mode, u64 data)
77241056 1463{
a787bde8 1464 struct hfi1_pportdata *ppd = context;
77241056
MM		 1465
1466 if (vl != CNTR_INVALID_VL)
1467 return 0;
1468 return read_write_sw(ppd->dd, &ppd->link_downed, mode, data);
1469}
1470
1471static u64 access_sw_link_up_cnt(const struct cntr_entry *entry, void *context,
17fb4f29 1472 int vl, int mode, u64 data)
77241056 1473{
a787bde8 1474 struct hfi1_pportdata *ppd = context;
77241056
MM		 1475
1476 if (vl != CNTR_INVALID_VL)
1477 return 0;
1478 return read_write_sw(ppd->dd, &ppd->link_up, mode, data);
1479}
1480
6d014530
DL		 1481static u64 access_sw_unknown_frame_cnt(const struct cntr_entry *entry,
1482 void *context, int vl, int mode,
1483 u64 data)
1484{
1485 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;
1486
1487 if (vl != CNTR_INVALID_VL)
1488 return 0;
1489 return read_write_sw(ppd->dd, &ppd->unknown_frame_count, mode, data);
1490}
1491
77241056 1492static u64 access_sw_xmit_discards(const struct cntr_entry *entry,
17fb4f29 1493 void *context, int vl, int mode, u64 data)
77241056 1494{
69a00b8e
MM		 1495 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;
1496 u64 zero = 0;
1497 u64 *counter;
77241056 1498
69a00b8e
MM		 1499 if (vl == CNTR_INVALID_VL)
1500 counter = &ppd->port_xmit_discards;
1501 else if (vl >= 0 && vl < C_VL_COUNT)
1502 counter = &ppd->port_xmit_discards_vl[vl];
1503 else
1504 counter = &zero;
77241056 1505
69a00b8e 1506 return read_write_sw(ppd->dd, counter, mode, data);
77241056
MM		 1507}
1508
1509static u64 access_xmit_constraint_errs(const struct cntr_entry *entry,
17fb4f29
JJ		 1510 void *context, int vl, int mode,
1511 u64 data)
77241056 1512{
a787bde8 1513 struct hfi1_pportdata *ppd = context;
77241056
MM		 1514
1515 if (vl != CNTR_INVALID_VL)
1516 return 0;
1517
1518 return read_write_sw(ppd->dd, &ppd->port_xmit_constraint_errors,
1519 mode, data);
1520}
1521
1522static u64 access_rcv_constraint_errs(const struct cntr_entry *entry,
17fb4f29 1523 void *context, int vl, int mode, u64 data)
77241056 1524{
a787bde8 1525 struct hfi1_pportdata *ppd = context;
77241056
MM		 1526
1527 if (vl != CNTR_INVALID_VL)
1528 return 0;
1529
1530 return read_write_sw(ppd->dd, &ppd->port_rcv_constraint_errors,
1531 mode, data);
1532}
1533
1534u64 get_all_cpu_total(u64 __percpu *cntr)
1535{
1536 int cpu;
1537 u64 counter = 0;
1538
1539 for_each_possible_cpu(cpu)
1540 counter += *per_cpu_ptr(cntr, cpu);
1541 return counter;
1542}
1543
1544static u64 read_write_cpu(struct hfi1_devdata *dd, u64 *z_val,
1545 u64 __percpu *cntr,
1546 int vl, int mode, u64 data)
1547{
77241056
MM		 1548 u64 ret = 0;
1549
1550 if (vl != CNTR_INVALID_VL)
1551 return 0;
1552
1553 if (mode == CNTR_MODE_R) {
1554 ret = get_all_cpu_total(cntr) - *z_val;
1555 } else if (mode == CNTR_MODE_W) {
1556 /* A write can only zero the counter */
1557 if (data == 0)
1558 *z_val = get_all_cpu_total(cntr);
1559 else
1560 dd_dev_err(dd, "Per CPU cntrs can only be zeroed");
1561 } else {
1562 dd_dev_err(dd, "Invalid cntr sw cpu access mode");
1563 return 0;
1564 }
1565
1566 return ret;
1567}
1568
1569static u64 access_sw_cpu_intr(const struct cntr_entry *entry,
1570 void *context, int vl, int mode, u64 data)
1571{
a787bde8 1572 struct hfi1_devdata *dd = context;
77241056
MM		 1573
1574 return read_write_cpu(dd, &dd->z_int_counter, dd->int_counter, vl,
1575 mode, data);
1576}
1577
1578static u64 access_sw_cpu_rcv_limit(const struct cntr_entry *entry,
17fb4f29 1579 void *context, int vl, int mode, u64 data)
77241056 1580{
a787bde8 1581 struct hfi1_devdata *dd = context;
77241056
MM		 1582
1583 return read_write_cpu(dd, &dd->z_rcv_limit, dd->rcv_limit, vl,
1584 mode, data);
1585}
1586
1587static u64 access_sw_pio_wait(const struct cntr_entry *entry,
1588 void *context, int vl, int mode, u64 data)
1589{
a787bde8 1590 struct hfi1_devdata *dd = context;
77241056
MM		 1591
1592 return dd->verbs_dev.n_piowait;
1593}
1594
14553ca1
MM		 1595static u64 access_sw_pio_drain(const struct cntr_entry *entry,
1596 void *context, int vl, int mode, u64 data)
1597{
1598 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1599
1600 return dd->verbs_dev.n_piodrain;
1601}
1602
77241056
MM		 1603static u64 access_sw_vtx_wait(const struct cntr_entry *entry,
1604 void *context, int vl, int mode, u64 data)
1605{
a787bde8 1606 struct hfi1_devdata *dd = context;
77241056
MM		 1607
1608 return dd->verbs_dev.n_txwait;
1609}
1610
1611static u64 access_sw_kmem_wait(const struct cntr_entry *entry,
1612 void *context, int vl, int mode, u64 data)
1613{
a787bde8 1614 struct hfi1_devdata *dd = context;
77241056
MM		 1615
1616 return dd->verbs_dev.n_kmem_wait;
1617}
1618
b421922e 1619static u64 access_sw_send_schedule(const struct cntr_entry *entry,
17fb4f29 1620 void *context, int vl, int mode, u64 data)
b421922e
DL		 1621{
1622 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1623
89abfc8d
VM		 1624 return read_write_cpu(dd, &dd->z_send_schedule, dd->send_schedule, vl,
1625 mode, data);
b421922e
DL		 1626}
1627
2c5b521a
JR		 1628/* Software counters for the error status bits within MISC_ERR_STATUS */
1629static u64 access_misc_pll_lock_fail_err_cnt(const struct cntr_entry *entry,
1630 void *context, int vl, int mode,
1631 u64 data)
1632{
1633 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1634
1635 return dd->misc_err_status_cnt[12];
1636}
1637
1638static u64 access_misc_mbist_fail_err_cnt(const struct cntr_entry *entry,
1639 void *context, int vl, int mode,
1640 u64 data)
1641{
1642 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1643
1644 return dd->misc_err_status_cnt[11];
1645}
1646
1647static u64 access_misc_invalid_eep_cmd_err_cnt(const struct cntr_entry *entry,
1648 void *context, int vl, int mode,
1649 u64 data)
1650{
1651 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1652
1653 return dd->misc_err_status_cnt[10];
1654}
1655
1656static u64 access_misc_efuse_done_parity_err_cnt(const struct cntr_entry *entry,
1657 void *context, int vl,
1658 int mode, u64 data)
1659{
1660 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1661
1662 return dd->misc_err_status_cnt[9];
1663}
1664
1665static u64 access_misc_efuse_write_err_cnt(const struct cntr_entry *entry,
1666 void *context, int vl, int mode,
1667 u64 data)
1668{
1669 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1670
1671 return dd->misc_err_status_cnt[8];
1672}
1673
1674static u64 access_misc_efuse_read_bad_addr_err_cnt(
1675 const struct cntr_entry *entry,
1676 void *context, int vl, int mode, u64 data)
1677{
1678 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1679
1680 return dd->misc_err_status_cnt[7];
1681}
1682
1683static u64 access_misc_efuse_csr_parity_err_cnt(const struct cntr_entry *entry,
1684 void *context, int vl,
1685 int mode, u64 data)
1686{
1687 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1688
1689 return dd->misc_err_status_cnt[6];
1690}
1691
1692static u64 access_misc_fw_auth_failed_err_cnt(const struct cntr_entry *entry,
1693 void *context, int vl, int mode,
1694 u64 data)
1695{
1696 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1697
1698 return dd->misc_err_status_cnt[5];
1699}
1700
1701static u64 access_misc_key_mismatch_err_cnt(const struct cntr_entry *entry,
1702 void *context, int vl, int mode,
1703 u64 data)
1704{
1705 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1706
1707 return dd->misc_err_status_cnt[4];
1708}
1709
1710static u64 access_misc_sbus_write_failed_err_cnt(const struct cntr_entry *entry,
1711 void *context, int vl,
1712 int mode, u64 data)
1713{
1714 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1715
1716 return dd->misc_err_status_cnt[3];
1717}
1718
1719static u64 access_misc_csr_write_bad_addr_err_cnt(
1720 const struct cntr_entry *entry,
1721 void *context, int vl, int mode, u64 data)
1722{
1723 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1724
1725 return dd->misc_err_status_cnt[2];
1726}
1727
1728static u64 access_misc_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
1729 void *context, int vl,
1730 int mode, u64 data)
1731{
1732 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1733
1734 return dd->misc_err_status_cnt[1];
1735}
1736
1737static u64 access_misc_csr_parity_err_cnt(const struct cntr_entry *entry,
1738 void *context, int vl, int mode,
1739 u64 data)
1740{
1741 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1742
1743 return dd->misc_err_status_cnt[0];
1744}
1745
1746/*
1747 * Software counter for the aggregate of
1748 * individual CceErrStatus counters
1749 */
1750static u64 access_sw_cce_err_status_aggregated_cnt(
1751 const struct cntr_entry *entry,
1752 void *context, int vl, int mode, u64 data)
1753{
1754 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1755
1756 return dd->sw_cce_err_status_aggregate;
1757}
1758
1759/*
1760 * Software counters corresponding to each of the
1761 * error status bits within CceErrStatus
1762 */
1763static u64 access_cce_msix_csr_parity_err_cnt(const struct cntr_entry *entry,
1764 void *context, int vl, int mode,
1765 u64 data)
1766{
1767 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1768
1769 return dd->cce_err_status_cnt[40];
1770}
1771
1772static u64 access_cce_int_map_unc_err_cnt(const struct cntr_entry *entry,
1773 void *context, int vl, int mode,
1774 u64 data)
1775{
1776 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1777
1778 return dd->cce_err_status_cnt[39];
1779}
1780
1781static u64 access_cce_int_map_cor_err_cnt(const struct cntr_entry *entry,
1782 void *context, int vl, int mode,
1783 u64 data)
1784{
1785 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1786
1787 return dd->cce_err_status_cnt[38];
1788}
1789
1790static u64 access_cce_msix_table_unc_err_cnt(const struct cntr_entry *entry,
1791 void *context, int vl, int mode,
1792 u64 data)
1793{
1794 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1795
1796 return dd->cce_err_status_cnt[37];
1797}
1798
1799static u64 access_cce_msix_table_cor_err_cnt(const struct cntr_entry *entry,
1800 void *context, int vl, int mode,
1801 u64 data)
1802{
1803 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1804
1805 return dd->cce_err_status_cnt[36];
1806}
1807
1808static u64 access_cce_rxdma_conv_fifo_parity_err_cnt(
1809 const struct cntr_entry *entry,
1810 void *context, int vl, int mode, u64 data)
1811{
1812 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1813
1814 return dd->cce_err_status_cnt[35];
1815}
1816
1817static u64 access_cce_rcpl_async_fifo_parity_err_cnt(
1818 const struct cntr_entry *entry,
1819 void *context, int vl, int mode, u64 data)
1820{
1821 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1822
1823 return dd->cce_err_status_cnt[34];
1824}
1825
1826static u64 access_cce_seg_write_bad_addr_err_cnt(const struct cntr_entry *entry,
1827 void *context, int vl,
1828 int mode, u64 data)
1829{
1830 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1831
1832 return dd->cce_err_status_cnt[33];
1833}
1834
1835static u64 access_cce_seg_read_bad_addr_err_cnt(const struct cntr_entry *entry,
1836 void *context, int vl, int mode,
1837 u64 data)
1838{
1839 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1840
1841 return dd->cce_err_status_cnt[32];
1842}
1843
1844static u64 access_la_triggered_cnt(const struct cntr_entry *entry,
1845 void *context, int vl, int mode, u64 data)
1846{
1847 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1848
1849 return dd->cce_err_status_cnt[31];
1850}
1851
1852static u64 access_cce_trgt_cpl_timeout_err_cnt(const struct cntr_entry *entry,
1853 void *context, int vl, int mode,
1854 u64 data)
1855{
1856 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1857
1858 return dd->cce_err_status_cnt[30];
1859}
1860
1861static u64 access_pcic_receive_parity_err_cnt(const struct cntr_entry *entry,
1862 void *context, int vl, int mode,
1863 u64 data)
1864{
1865 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1866
1867 return dd->cce_err_status_cnt[29];
1868}
1869
1870static u64 access_pcic_transmit_back_parity_err_cnt(
1871 const struct cntr_entry *entry,
1872 void *context, int vl, int mode, u64 data)
1873{
1874 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1875
1876 return dd->cce_err_status_cnt[28];
1877}
1878
1879static u64 access_pcic_transmit_front_parity_err_cnt(
1880 const struct cntr_entry *entry,
1881 void *context, int vl, int mode, u64 data)
1882{
1883 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1884
1885 return dd->cce_err_status_cnt[27];
1886}
1887
1888static u64 access_pcic_cpl_dat_q_unc_err_cnt(const struct cntr_entry *entry,
1889 void *context, int vl, int mode,
1890 u64 data)
1891{
1892 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1893
1894 return dd->cce_err_status_cnt[26];
1895}
1896
1897static u64 access_pcic_cpl_hd_q_unc_err_cnt(const struct cntr_entry *entry,
1898 void *context, int vl, int mode,
1899 u64 data)
1900{
1901 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1902
1903 return dd->cce_err_status_cnt[25];
1904}
1905
1906static u64 access_pcic_post_dat_q_unc_err_cnt(const struct cntr_entry *entry,
1907 void *context, int vl, int mode,
1908 u64 data)
1909{
1910 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1911
1912 return dd->cce_err_status_cnt[24];
1913}
1914
1915static u64 access_pcic_post_hd_q_unc_err_cnt(const struct cntr_entry *entry,
1916 void *context, int vl, int mode,
1917 u64 data)
1918{
1919 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1920
1921 return dd->cce_err_status_cnt[23];
1922}
1923
1924static u64 access_pcic_retry_sot_mem_unc_err_cnt(const struct cntr_entry *entry,
1925 void *context, int vl,
1926 int mode, u64 data)
1927{
1928 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1929
1930 return dd->cce_err_status_cnt[22];
1931}
1932
1933static u64 access_pcic_retry_mem_unc_err(const struct cntr_entry *entry,
1934 void *context, int vl, int mode,
1935 u64 data)
1936{
1937 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1938
1939 return dd->cce_err_status_cnt[21];
1940}
1941
1942static u64 access_pcic_n_post_dat_q_parity_err_cnt(
1943 const struct cntr_entry *entry,
1944 void *context, int vl, int mode, u64 data)
1945{
1946 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1947
1948 return dd->cce_err_status_cnt[20];
1949}
1950
1951static u64 access_pcic_n_post_h_q_parity_err_cnt(const struct cntr_entry *entry,
1952 void *context, int vl,
1953 int mode, u64 data)
1954{
1955 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1956
1957 return dd->cce_err_status_cnt[19];
1958}
1959
1960static u64 access_pcic_cpl_dat_q_cor_err_cnt(const struct cntr_entry *entry,
1961 void *context, int vl, int mode,
1962 u64 data)
1963{
1964 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1965
1966 return dd->cce_err_status_cnt[18];
1967}
1968
1969static u64 access_pcic_cpl_hd_q_cor_err_cnt(const struct cntr_entry *entry,
1970 void *context, int vl, int mode,
1971 u64 data)
1972{
1973 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1974
1975 return dd->cce_err_status_cnt[17];
1976}
1977
1978static u64 access_pcic_post_dat_q_cor_err_cnt(const struct cntr_entry *entry,
1979 void *context, int vl, int mode,
1980 u64 data)
1981{
1982 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1983
1984 return dd->cce_err_status_cnt[16];
1985}
1986
1987static u64 access_pcic_post_hd_q_cor_err_cnt(const struct cntr_entry *entry,
1988 void *context, int vl, int mode,
1989 u64 data)
1990{
1991 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1992
1993 return dd->cce_err_status_cnt[15];
1994}
1995
1996static u64 access_pcic_retry_sot_mem_cor_err_cnt(const struct cntr_entry *entry,
1997 void *context, int vl,
1998 int mode, u64 data)
1999{
2000 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2001
2002 return dd->cce_err_status_cnt[14];
2003}
2004
2005static u64 access_pcic_retry_mem_cor_err_cnt(const struct cntr_entry *entry,
2006 void *context, int vl, int mode,
2007 u64 data)
2008{
2009 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2010
2011 return dd->cce_err_status_cnt[13];
2012}
2013
2014static u64 access_cce_cli1_async_fifo_dbg_parity_err_cnt(
2015 const struct cntr_entry *entry,
2016 void *context, int vl, int mode, u64 data)
2017{
2018 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2019
2020 return dd->cce_err_status_cnt[12];
2021}
2022
2023static u64 access_cce_cli1_async_fifo_rxdma_parity_err_cnt(
2024 const struct cntr_entry *entry,
2025 void *context, int vl, int mode, u64 data)
2026{
2027 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2028
2029 return dd->cce_err_status_cnt[11];
2030}
2031
2032static u64 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt(
2033 const struct cntr_entry *entry,
2034 void *context, int vl, int mode, u64 data)
2035{
2036 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2037
2038 return dd->cce_err_status_cnt[10];
2039}
2040
2041static u64 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt(
2042 const struct cntr_entry *entry,
2043 void *context, int vl, int mode, u64 data)
2044{
2045 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2046
2047 return dd->cce_err_status_cnt[9];
2048}
2049
2050static u64 access_cce_cli2_async_fifo_parity_err_cnt(
2051 const struct cntr_entry *entry,
2052 void *context, int vl, int mode, u64 data)
2053{
2054 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2055
2056 return dd->cce_err_status_cnt[8];
2057}
2058
2059static u64 access_cce_csr_cfg_bus_parity_err_cnt(const struct cntr_entry *entry,
2060 void *context, int vl,
2061 int mode, u64 data)
2062{
2063 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2064
2065 return dd->cce_err_status_cnt[7];
2066}
2067
2068static u64 access_cce_cli0_async_fifo_parity_err_cnt(
2069 const struct cntr_entry *entry,
2070 void *context, int vl, int mode, u64 data)
2071{
2072 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2073
2074 return dd->cce_err_status_cnt[6];
2075}
2076
2077static u64 access_cce_rspd_data_parity_err_cnt(const struct cntr_entry *entry,
2078 void *context, int vl, int mode,
2079 u64 data)
2080{
2081 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2082
2083 return dd->cce_err_status_cnt[5];
2084}
2085
2086static u64 access_cce_trgt_access_err_cnt(const struct cntr_entry *entry,
2087 void *context, int vl, int mode,
2088 u64 data)
2089{
2090 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2091
2092 return dd->cce_err_status_cnt[4];
2093}
2094
2095static u64 access_cce_trgt_async_fifo_parity_err_cnt(
2096 const struct cntr_entry *entry,
2097 void *context, int vl, int mode, u64 data)
2098{
2099 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2100
2101 return dd->cce_err_status_cnt[3];
2102}
2103
2104static u64 access_cce_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry,
2105 void *context, int vl,
2106 int mode, u64 data)
2107{
2108 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2109
2110 return dd->cce_err_status_cnt[2];
2111}
2112
2113static u64 access_cce_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
2114 void *context, int vl,
2115 int mode, u64 data)
2116{
2117 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2118
2119 return dd->cce_err_status_cnt[1];
2120}
2121
2122static u64 access_ccs_csr_parity_err_cnt(const struct cntr_entry *entry,
2123 void *context, int vl, int mode,
2124 u64 data)
2125{
2126 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2127
2128 return dd->cce_err_status_cnt[0];
2129}
2130
2131/*
2132 * Software counters corresponding to each of the
2133 * error status bits within RcvErrStatus
2134 */
2135static u64 access_rx_csr_parity_err_cnt(const struct cntr_entry *entry,
2136 void *context, int vl, int mode,
2137 u64 data)
2138{
2139 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2140
2141 return dd->rcv_err_status_cnt[63];
2142}
2143
2144static u64 access_rx_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry,
2145 void *context, int vl,
2146 int mode, u64 data)
2147{
2148 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2149
2150 return dd->rcv_err_status_cnt[62];
2151}
2152
2153static u64 access_rx_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
2154 void *context, int vl, int mode,
2155 u64 data)
2156{
2157 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2158
2159 return dd->rcv_err_status_cnt[61];
2160}
2161
2162static u64 access_rx_dma_csr_unc_err_cnt(const struct cntr_entry *entry,
2163 void *context, int vl, int mode,
2164 u64 data)
2165{
2166 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2167
2168 return dd->rcv_err_status_cnt[60];
2169}
2170
2171static u64 access_rx_dma_dq_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2172 void *context, int vl,
2173 int mode, u64 data)
2174{
2175 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2176
2177 return dd->rcv_err_status_cnt[59];
2178}
2179
2180static u64 access_rx_dma_eq_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2181 void *context, int vl,
2182 int mode, u64 data)
2183{
2184 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2185
2186 return dd->rcv_err_status_cnt[58];
2187}
2188
2189static u64 access_rx_dma_csr_parity_err_cnt(const struct cntr_entry *entry,
2190 void *context, int vl, int mode,
2191 u64 data)
2192{
2193 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2194
2195 return dd->rcv_err_status_cnt[57];
2196}
2197
2198static u64 access_rx_rbuf_data_cor_err_cnt(const struct cntr_entry *entry,
2199 void *context, int vl, int mode,
2200 u64 data)
2201{
2202 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2203
2204 return dd->rcv_err_status_cnt[56];
2205}
2206
2207static u64 access_rx_rbuf_data_unc_err_cnt(const struct cntr_entry *entry,
2208 void *context, int vl, int mode,
2209 u64 data)
2210{
2211 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2212
2213 return dd->rcv_err_status_cnt[55];
2214}
2215
2216static u64 access_rx_dma_data_fifo_rd_cor_err_cnt(
2217 const struct cntr_entry *entry,
2218 void *context, int vl, int mode, u64 data)
2219{
2220 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2221
2222 return dd->rcv_err_status_cnt[54];
2223}
2224
2225static u64 access_rx_dma_data_fifo_rd_unc_err_cnt(
2226 const struct cntr_entry *entry,
2227 void *context, int vl, int mode, u64 data)
2228{
2229 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2230
2231 return dd->rcv_err_status_cnt[53];
2232}
2233
2234static u64 access_rx_dma_hdr_fifo_rd_cor_err_cnt(const struct cntr_entry *entry,
2235 void *context, int vl,
2236 int mode, u64 data)
2237{
2238 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2239
2240 return dd->rcv_err_status_cnt[52];
2241}
2242
2243static u64 access_rx_dma_hdr_fifo_rd_unc_err_cnt(const struct cntr_entry *entry,
2244 void *context, int vl,
2245 int mode, u64 data)
2246{
2247 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2248
2249 return dd->rcv_err_status_cnt[51];
2250}
2251
2252static u64 access_rx_rbuf_desc_part2_cor_err_cnt(const struct cntr_entry *entry,
2253 void *context, int vl,
2254 int mode, u64 data)
2255{
2256 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2257
2258 return dd->rcv_err_status_cnt[50];
2259}
2260
2261static u64 access_rx_rbuf_desc_part2_unc_err_cnt(const struct cntr_entry *entry,
2262 void *context, int vl,
2263 int mode, u64 data)
2264{
2265 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2266
2267 return dd->rcv_err_status_cnt[49];
2268}
2269
2270static u64 access_rx_rbuf_desc_part1_cor_err_cnt(const struct cntr_entry *entry,
2271 void *context, int vl,
2272 int mode, u64 data)
2273{
2274 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2275
2276 return dd->rcv_err_status_cnt[48];
2277}
2278
2279static u64 access_rx_rbuf_desc_part1_unc_err_cnt(const struct cntr_entry *entry,
2280 void *context, int vl,
2281 int mode, u64 data)
2282{
2283 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2284
2285 return dd->rcv_err_status_cnt[47];
2286}
2287
2288static u64 access_rx_hq_intr_fsm_err_cnt(const struct cntr_entry *entry,
2289 void *context, int vl, int mode,
2290 u64 data)
2291{
2292 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2293
2294 return dd->rcv_err_status_cnt[46];
2295}
2296
2297static u64 access_rx_hq_intr_csr_parity_err_cnt(
2298 const struct cntr_entry *entry,
2299 void *context, int vl, int mode, u64 data)
2300{
2301 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2302
2303 return dd->rcv_err_status_cnt[45];
2304}
2305
2306static u64 access_rx_lookup_csr_parity_err_cnt(
2307 const struct cntr_entry *entry,
2308 void *context, int vl, int mode, u64 data)
2309{
2310 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2311
2312 return dd->rcv_err_status_cnt[44];
2313}
2314
2315static u64 access_rx_lookup_rcv_array_cor_err_cnt(
2316 const struct cntr_entry *entry,
2317 void *context, int vl, int mode, u64 data)
2318{
2319 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2320
2321 return dd->rcv_err_status_cnt[43];
2322}
2323
2324static u64 access_rx_lookup_rcv_array_unc_err_cnt(
2325 const struct cntr_entry *entry,
2326 void *context, int vl, int mode, u64 data)
2327{
2328 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2329
2330 return dd->rcv_err_status_cnt[42];
2331}
2332
2333static u64 access_rx_lookup_des_part2_parity_err_cnt(
2334 const struct cntr_entry *entry,
2335 void *context, int vl, int mode, u64 data)
2336{
2337 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2338
2339 return dd->rcv_err_status_cnt[41];
2340}
2341
2342static u64 access_rx_lookup_des_part1_unc_cor_err_cnt(
2343 const struct cntr_entry *entry,
2344 void *context, int vl, int mode, u64 data)
2345{
2346 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2347
2348 return dd->rcv_err_status_cnt[40];
2349}
2350
2351static u64 access_rx_lookup_des_part1_unc_err_cnt(
2352 const struct cntr_entry *entry,
2353 void *context, int vl, int mode, u64 data)
2354{
2355 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2356
2357 return dd->rcv_err_status_cnt[39];
2358}
2359
2360static u64 access_rx_rbuf_next_free_buf_cor_err_cnt(
2361 const struct cntr_entry *entry,
2362 void *context, int vl, int mode, u64 data)
2363{
2364 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2365
2366 return dd->rcv_err_status_cnt[38];
2367}
2368
2369static u64 access_rx_rbuf_next_free_buf_unc_err_cnt(
2370 const struct cntr_entry *entry,
2371 void *context, int vl, int mode, u64 data)
2372{
2373 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2374
2375 return dd->rcv_err_status_cnt[37];
2376}
2377
2378static u64 access_rbuf_fl_init_wr_addr_parity_err_cnt(
2379 const struct cntr_entry *entry,
2380 void *context, int vl, int mode, u64 data)
2381{
2382 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2383
2384 return dd->rcv_err_status_cnt[36];
2385}
2386
2387static u64 access_rx_rbuf_fl_initdone_parity_err_cnt(
2388 const struct cntr_entry *entry,
2389 void *context, int vl, int mode, u64 data)
2390{
2391 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2392
2393 return dd->rcv_err_status_cnt[35];
2394}
2395
2396static u64 access_rx_rbuf_fl_write_addr_parity_err_cnt(
2397 const struct cntr_entry *entry,
2398 void *context, int vl, int mode, u64 data)
2399{
2400 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2401
2402 return dd->rcv_err_status_cnt[34];
2403}
2404
2405static u64 access_rx_rbuf_fl_rd_addr_parity_err_cnt(
2406 const struct cntr_entry *entry,
2407 void *context, int vl, int mode, u64 data)
2408{
2409 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2410
2411 return dd->rcv_err_status_cnt[33];
2412}
2413
2414static u64 access_rx_rbuf_empty_err_cnt(const struct cntr_entry *entry,
2415 void *context, int vl, int mode,
2416 u64 data)
2417{
2418 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2419
2420 return dd->rcv_err_status_cnt[32];
2421}
2422
2423static u64 access_rx_rbuf_full_err_cnt(const struct cntr_entry *entry,
2424 void *context, int vl, int mode,
2425 u64 data)
2426{
2427 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2428
2429 return dd->rcv_err_status_cnt[31];
2430}
2431
2432static u64 access_rbuf_bad_lookup_err_cnt(const struct cntr_entry *entry,
2433 void *context, int vl, int mode,
2434 u64 data)
2435{
2436 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2437
2438 return dd->rcv_err_status_cnt[30];
2439}
2440
2441static u64 access_rbuf_ctx_id_parity_err_cnt(const struct cntr_entry *entry,
2442 void *context, int vl, int mode,
2443 u64 data)
2444{
2445 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2446
2447 return dd->rcv_err_status_cnt[29];
2448}
2449
2450static u64 access_rbuf_csr_qeopdw_parity_err_cnt(const struct cntr_entry *entry,
2451 void *context, int vl,
2452 int mode, u64 data)
2453{
2454 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2455
2456 return dd->rcv_err_status_cnt[28];
2457}
2458
2459static u64 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt(
2460 const struct cntr_entry *entry,
2461 void *context, int vl, int mode, u64 data)
2462{
2463 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2464
2465 return dd->rcv_err_status_cnt[27];
2466}
2467
2468static u64 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt(
2469 const struct cntr_entry *entry,
2470 void *context, int vl, int mode, u64 data)
2471{
2472 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2473
2474 return dd->rcv_err_status_cnt[26];
2475}
2476
2477static u64 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt(
2478 const struct cntr_entry *entry,
2479 void *context, int vl, int mode, u64 data)
2480{
2481 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2482
2483 return dd->rcv_err_status_cnt[25];
2484}
2485
2486static u64 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt(
2487 const struct cntr_entry *entry,
2488 void *context, int vl, int mode, u64 data)
2489{
2490 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2491
2492 return dd->rcv_err_status_cnt[24];
2493}
2494
2495static u64 access_rx_rbuf_csr_q_next_buf_parity_err_cnt(
2496 const struct cntr_entry *entry,
2497 void *context, int vl, int mode, u64 data)
2498{
2499 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2500
2501 return dd->rcv_err_status_cnt[23];
2502}
2503
2504static u64 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt(
2505 const struct cntr_entry *entry,
2506 void *context, int vl, int mode, u64 data)
2507{
2508 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2509
2510 return dd->rcv_err_status_cnt[22];
2511}
2512
2513static u64 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt(
2514 const struct cntr_entry *entry,
2515 void *context, int vl, int mode, u64 data)
2516{
2517 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2518
2519 return dd->rcv_err_status_cnt[21];
2520}
2521
2522static u64 access_rx_rbuf_block_list_read_cor_err_cnt(
2523 const struct cntr_entry *entry,
2524 void *context, int vl, int mode, u64 data)
2525{
2526 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2527
2528 return dd->rcv_err_status_cnt[20];
2529}
2530
2531static u64 access_rx_rbuf_block_list_read_unc_err_cnt(
2532 const struct cntr_entry *entry,
2533 void *context, int vl, int mode, u64 data)
2534{
2535 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2536
2537 return dd->rcv_err_status_cnt[19];
2538}
2539
2540static u64 access_rx_rbuf_lookup_des_cor_err_cnt(const struct cntr_entry *entry,
2541 void *context, int vl,
2542 int mode, u64 data)
2543{
2544 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2545
2546 return dd->rcv_err_status_cnt[18];
2547}
2548
2549static u64 access_rx_rbuf_lookup_des_unc_err_cnt(const struct cntr_entry *entry,
2550 void *context, int vl,
2551 int mode, u64 data)
2552{
2553 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2554
2555 return dd->rcv_err_status_cnt[17];
2556}
2557
2558static u64 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt(
2559 const struct cntr_entry *entry,
2560 void *context, int vl, int mode, u64 data)
2561{
2562 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2563
2564 return dd->rcv_err_status_cnt[16];
2565}
2566
2567static u64 access_rx_rbuf_lookup_des_reg_unc_err_cnt(
2568 const struct cntr_entry *entry,
2569 void *context, int vl, int mode, u64 data)
2570{
2571 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2572
2573 return dd->rcv_err_status_cnt[15];
2574}
2575
2576static u64 access_rx_rbuf_free_list_cor_err_cnt(const struct cntr_entry *entry,
2577 void *context, int vl,
2578 int mode, u64 data)
2579{
2580 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2581
2582 return dd->rcv_err_status_cnt[14];
2583}
2584
2585static u64 access_rx_rbuf_free_list_unc_err_cnt(const struct cntr_entry *entry,
2586 void *context, int vl,
2587 int mode, u64 data)
2588{
2589 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2590
2591 return dd->rcv_err_status_cnt[13];
2592}
2593
2594static u64 access_rx_rcv_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2595 void *context, int vl, int mode,
2596 u64 data)
2597{
2598 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2599
2600 return dd->rcv_err_status_cnt[12];
2601}
2602
2603static u64 access_rx_dma_flag_cor_err_cnt(const struct cntr_entry *entry,
2604 void *context, int vl, int mode,
2605 u64 data)
2606{
2607 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2608
2609 return dd->rcv_err_status_cnt[11];
2610}
2611
2612static u64 access_rx_dma_flag_unc_err_cnt(const struct cntr_entry *entry,
2613 void *context, int vl, int mode,
2614 u64 data)
2615{
2616 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2617
2618 return dd->rcv_err_status_cnt[10];
2619}
2620
2621static u64 access_rx_dc_sop_eop_parity_err_cnt(const struct cntr_entry *entry,
2622 void *context, int vl, int mode,
2623 u64 data)
2624{
2625 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2626
2627 return dd->rcv_err_status_cnt[9];
2628}
2629
2630static u64 access_rx_rcv_csr_parity_err_cnt(const struct cntr_entry *entry,
2631 void *context, int vl, int mode,
2632 u64 data)
2633{
2634 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2635
2636 return dd->rcv_err_status_cnt[8];
2637}
2638
2639static u64 access_rx_rcv_qp_map_table_cor_err_cnt(
2640 const struct cntr_entry *entry,
2641 void *context, int vl, int mode, u64 data)
2642{
2643 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2644
2645 return dd->rcv_err_status_cnt[7];
2646}
2647
2648static u64 access_rx_rcv_qp_map_table_unc_err_cnt(
2649 const struct cntr_entry *entry,
2650 void *context, int vl, int mode, u64 data)
2651{
2652 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2653
2654 return dd->rcv_err_status_cnt[6];
2655}
2656
2657static u64 access_rx_rcv_data_cor_err_cnt(const struct cntr_entry *entry,
2658 void *context, int vl, int mode,
2659 u64 data)
2660{
2661 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2662
2663 return dd->rcv_err_status_cnt[5];
2664}
2665
2666static u64 access_rx_rcv_data_unc_err_cnt(const struct cntr_entry *entry,
2667 void *context, int vl, int mode,
2668 u64 data)
2669{
2670 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2671
2672 return dd->rcv_err_status_cnt[4];
2673}
2674
2675static u64 access_rx_rcv_hdr_cor_err_cnt(const struct cntr_entry *entry,
2676 void *context, int vl, int mode,
2677 u64 data)
2678{
2679 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2680
2681 return dd->rcv_err_status_cnt[3];
2682}
2683
2684static u64 access_rx_rcv_hdr_unc_err_cnt(const struct cntr_entry *entry,
2685 void *context, int vl, int mode,
2686 u64 data)
2687{
2688 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2689
2690 return dd->rcv_err_status_cnt[2];
2691}
2692
2693static u64 access_rx_dc_intf_parity_err_cnt(const struct cntr_entry *entry,
2694 void *context, int vl, int mode,
2695 u64 data)
2696{
2697 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2698
2699 return dd->rcv_err_status_cnt[1];
2700}
2701
2702static u64 access_rx_dma_csr_cor_err_cnt(const struct cntr_entry *entry,
2703 void *context, int vl, int mode,
2704 u64 data)
2705{
2706 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2707
2708 return dd->rcv_err_status_cnt[0];
2709}
2710
2711/*
2712 * Software counters corresponding to each of the
2713 * error status bits within SendPioErrStatus
2714 */
2715static u64 access_pio_pec_sop_head_parity_err_cnt(
2716 const struct cntr_entry *entry,
2717 void *context, int vl, int mode, u64 data)
2718{
2719 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2720
2721 return dd->send_pio_err_status_cnt[35];
2722}
2723
2724static u64 access_pio_pcc_sop_head_parity_err_cnt(
2725 const struct cntr_entry *entry,
2726 void *context, int vl, int mode, u64 data)
2727{
2728 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2729
2730 return dd->send_pio_err_status_cnt[34];
2731}
2732
2733static u64 access_pio_last_returned_cnt_parity_err_cnt(
2734 const struct cntr_entry *entry,
2735 void *context, int vl, int mode, u64 data)
2736{
2737 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2738
2739 return dd->send_pio_err_status_cnt[33];
2740}
2741
2742static u64 access_pio_current_free_cnt_parity_err_cnt(
2743 const struct cntr_entry *entry,
2744 void *context, int vl, int mode, u64 data)
2745{
2746 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2747
2748 return dd->send_pio_err_status_cnt[32];
2749}
2750
2751static u64 access_pio_reserved_31_err_cnt(const struct cntr_entry *entry,
2752 void *context, int vl, int mode,
2753 u64 data)
2754{
2755 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2756
2757 return dd->send_pio_err_status_cnt[31];
2758}
2759
2760static u64 access_pio_reserved_30_err_cnt(const struct cntr_entry *entry,
2761 void *context, int vl, int mode,
2762 u64 data)
2763{
2764 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2765
2766 return dd->send_pio_err_status_cnt[30];
2767}
2768
2769static u64 access_pio_ppmc_sop_len_err_cnt(const struct cntr_entry *entry,
2770 void *context, int vl, int mode,
2771 u64 data)
2772{
2773 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2774
2775 return dd->send_pio_err_status_cnt[29];
2776}
2777
2778static u64 access_pio_ppmc_bqc_mem_parity_err_cnt(
2779 const struct cntr_entry *entry,
2780 void *context, int vl, int mode, u64 data)
2781{
2782 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2783
2784 return dd->send_pio_err_status_cnt[28];
2785}
2786
2787static u64 access_pio_vl_fifo_parity_err_cnt(const struct cntr_entry *entry,
2788 void *context, int vl, int mode,
2789 u64 data)
2790{
2791 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2792
2793 return dd->send_pio_err_status_cnt[27];
2794}
2795
2796static u64 access_pio_vlf_sop_parity_err_cnt(const struct cntr_entry *entry,
2797 void *context, int vl, int mode,
2798 u64 data)
2799{
2800 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2801
2802 return dd->send_pio_err_status_cnt[26];
2803}
2804
2805static u64 access_pio_vlf_v1_len_parity_err_cnt(const struct cntr_entry *entry,
2806 void *context, int vl,
2807 int mode, u64 data)
2808{
2809 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2810
2811 return dd->send_pio_err_status_cnt[25];
2812}
2813
2814static u64 access_pio_block_qw_count_parity_err_cnt(
2815 const struct cntr_entry *entry,
2816 void *context, int vl, int mode, u64 data)
2817{
2818 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2819
2820 return dd->send_pio_err_status_cnt[24];
2821}
2822
2823static u64 access_pio_write_qw_valid_parity_err_cnt(
2824 const struct cntr_entry *entry,
2825 void *context, int vl, int mode, u64 data)
2826{
2827 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2828
2829 return dd->send_pio_err_status_cnt[23];
2830}
2831
2832static u64 access_pio_state_machine_err_cnt(const struct cntr_entry *entry,
2833 void *context, int vl, int mode,
2834 u64 data)
2835{
2836 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2837
2838 return dd->send_pio_err_status_cnt[22];
2839}
2840
2841static u64 access_pio_write_data_parity_err_cnt(const struct cntr_entry *entry,
2842 void *context, int vl,
2843 int mode, u64 data)
2844{
2845 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2846
2847 return dd->send_pio_err_status_cnt[21];
2848}
2849
2850static u64 access_pio_host_addr_mem_cor_err_cnt(const struct cntr_entry *entry,
2851 void *context, int vl,
2852 int mode, u64 data)
2853{
2854 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2855
2856 return dd->send_pio_err_status_cnt[20];
2857}
2858
2859static u64 access_pio_host_addr_mem_unc_err_cnt(const struct cntr_entry *entry,
2860 void *context, int vl,
2861 int mode, u64 data)
2862{
2863 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2864
2865 return dd->send_pio_err_status_cnt[19];
2866}
2867
2868static u64 access_pio_pkt_evict_sm_or_arb_sm_err_cnt(
2869 const struct cntr_entry *entry,
2870 void *context, int vl, int mode, u64 data)
2871{
2872 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2873
2874 return dd->send_pio_err_status_cnt[18];
2875}
2876
2877static u64 access_pio_init_sm_in_err_cnt(const struct cntr_entry *entry,
2878 void *context, int vl, int mode,
2879 u64 data)
2880{
2881 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2882
2883 return dd->send_pio_err_status_cnt[17];
2884}
2885
2886static u64 access_pio_ppmc_pbl_fifo_err_cnt(const struct cntr_entry *entry,
2887 void *context, int vl, int mode,
2888 u64 data)
2889{
2890 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2891
2892 return dd->send_pio_err_status_cnt[16];
2893}
2894
2895static u64 access_pio_credit_ret_fifo_parity_err_cnt(
2896 const struct cntr_entry *entry,
2897 void *context, int vl, int mode, u64 data)
2898{
2899 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2900
2901 return dd->send_pio_err_status_cnt[15];
2902}
2903
2904static u64 access_pio_v1_len_mem_bank1_cor_err_cnt(
2905 const struct cntr_entry *entry,
2906 void *context, int vl, int mode, u64 data)
2907{
2908 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2909
2910 return dd->send_pio_err_status_cnt[14];
2911}
2912
2913static u64 access_pio_v1_len_mem_bank0_cor_err_cnt(
2914 const struct cntr_entry *entry,
2915 void *context, int vl, int mode, u64 data)
2916{
2917 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2918
2919 return dd->send_pio_err_status_cnt[13];
2920}
2921
2922static u64 access_pio_v1_len_mem_bank1_unc_err_cnt(
2923 const struct cntr_entry *entry,
2924 void *context, int vl, int mode, u64 data)
2925{
2926 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2927
2928 return dd->send_pio_err_status_cnt[12];
2929}
2930
2931static u64 access_pio_v1_len_mem_bank0_unc_err_cnt(
2932 const struct cntr_entry *entry,
2933 void *context, int vl, int mode, u64 data)
2934{
2935 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2936
2937 return dd->send_pio_err_status_cnt[11];
2938}
2939
2940static u64 access_pio_sm_pkt_reset_parity_err_cnt(
2941 const struct cntr_entry *entry,
2942 void *context, int vl, int mode, u64 data)
2943{
2944 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2945
2946 return dd->send_pio_err_status_cnt[10];
2947}
2948
2949static u64 access_pio_pkt_evict_fifo_parity_err_cnt(
2950 const struct cntr_entry *entry,
2951 void *context, int vl, int mode, u64 data)
2952{
2953 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2954
2955 return dd->send_pio_err_status_cnt[9];
2956}
2957
2958static u64 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt(
2959 const struct cntr_entry *entry,
2960 void *context, int vl, int mode, u64 data)
2961{
2962 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2963
2964 return dd->send_pio_err_status_cnt[8];
2965}
2966
2967static u64 access_pio_sbrdctl_crrel_parity_err_cnt(
2968 const struct cntr_entry *entry,
2969 void *context, int vl, int mode, u64 data)
2970{
2971 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2972
2973 return dd->send_pio_err_status_cnt[7];
2974}
2975
2976static u64 access_pio_pec_fifo_parity_err_cnt(const struct cntr_entry *entry,
2977 void *context, int vl, int mode,
2978 u64 data)
2979{
2980 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2981
2982 return dd->send_pio_err_status_cnt[6];
2983}
2984
2985static u64 access_pio_pcc_fifo_parity_err_cnt(const struct cntr_entry *entry,
2986 void *context, int vl, int mode,
2987 u64 data)
2988{
2989 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2990
2991 return dd->send_pio_err_status_cnt[5];
2992}
2993
2994static u64 access_pio_sb_mem_fifo1_err_cnt(const struct cntr_entry *entry,
2995 void *context, int vl, int mode,
2996 u64 data)
2997{
2998 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2999
3000 return dd->send_pio_err_status_cnt[4];
3001}
3002
3003static u64 access_pio_sb_mem_fifo0_err_cnt(const struct cntr_entry *entry,
3004 void *context, int vl, int mode,
3005 u64 data)
3006{
3007 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3008
3009 return dd->send_pio_err_status_cnt[3];
3010}
3011
3012static u64 access_pio_csr_parity_err_cnt(const struct cntr_entry *entry,
3013 void *context, int vl, int mode,
3014 u64 data)
3015{
3016 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3017
3018 return dd->send_pio_err_status_cnt[2];
3019}
3020
3021static u64 access_pio_write_addr_parity_err_cnt(const struct cntr_entry *entry,
3022 void *context, int vl,
3023 int mode, u64 data)
3024{
3025 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3026
3027 return dd->send_pio_err_status_cnt[1];
3028}
3029
3030static u64 access_pio_write_bad_ctxt_err_cnt(const struct cntr_entry *entry,
3031 void *context, int vl, int mode,
3032 u64 data)
3033{
3034 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3035
3036 return dd->send_pio_err_status_cnt[0];
3037}
3038
3039/*
3040 * Software counters corresponding to each of the
3041 * error status bits within SendDmaErrStatus
3042 */
3043static u64 access_sdma_pcie_req_tracking_cor_err_cnt(
3044 const struct cntr_entry *entry,
3045 void *context, int vl, int mode, u64 data)
3046{
3047 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3048
3049 return dd->send_dma_err_status_cnt[3];
3050}
3051
3052static u64 access_sdma_pcie_req_tracking_unc_err_cnt(
3053 const struct cntr_entry *entry,
3054 void *context, int vl, int mode, u64 data)
3055{
3056 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3057
3058 return dd->send_dma_err_status_cnt[2];
3059}
3060
3061static u64 access_sdma_csr_parity_err_cnt(const struct cntr_entry *entry,
3062 void *context, int vl, int mode,
3063 u64 data)
3064{
3065 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3066
3067 return dd->send_dma_err_status_cnt[1];
3068}
3069
3070static u64 access_sdma_rpy_tag_err_cnt(const struct cntr_entry *entry,
3071 void *context, int vl, int mode,
3072 u64 data)
3073{
3074 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3075
3076 return dd->send_dma_err_status_cnt[0];
3077}
3078
3079/*
3080 * Software counters corresponding to each of the
3081 * error status bits within SendEgressErrStatus
3082 */
3083static u64 access_tx_read_pio_memory_csr_unc_err_cnt(
3084 const struct cntr_entry *entry,
3085 void *context, int vl, int mode, u64 data)
3086{
3087 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3088
3089 return dd->send_egress_err_status_cnt[63];
3090}
3091
3092static u64 access_tx_read_sdma_memory_csr_err_cnt(
3093 const struct cntr_entry *entry,
3094 void *context, int vl, int mode, u64 data)
3095{
3096 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3097
3098 return dd->send_egress_err_status_cnt[62];
3099}
3100
3101static u64 access_tx_egress_fifo_cor_err_cnt(const struct cntr_entry *entry,
3102 void *context, int vl, int mode,
3103 u64 data)
3104{
3105 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3106
3107 return dd->send_egress_err_status_cnt[61];
3108}
3109
3110static u64 access_tx_read_pio_memory_cor_err_cnt(const struct cntr_entry *entry,
3111 void *context, int vl,
3112 int mode, u64 data)
3113{
3114 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3115
3116 return dd->send_egress_err_status_cnt[60];
3117}
3118
3119static u64 access_tx_read_sdma_memory_cor_err_cnt(
3120 const struct cntr_entry *entry,
3121 void *context, int vl, int mode, u64 data)
3122{
3123 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3124
3125 return dd->send_egress_err_status_cnt[59];
3126}
3127
3128static u64 access_tx_sb_hdr_cor_err_cnt(const struct cntr_entry *entry,
3129 void *context, int vl, int mode,
3130 u64 data)
3131{
3132 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3133
3134 return dd->send_egress_err_status_cnt[58];
3135}
3136
3137static u64 access_tx_credit_overrun_err_cnt(const struct cntr_entry *entry,
3138 void *context, int vl, int mode,
3139 u64 data)
3140{
3141 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3142
3143 return dd->send_egress_err_status_cnt[57];
3144}
3145
3146static u64 access_tx_launch_fifo8_cor_err_cnt(const struct cntr_entry *entry,
3147 void *context, int vl, int mode,
3148 u64 data)
3149{
3150 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3151
3152 return dd->send_egress_err_status_cnt[56];
3153}
3154
3155static u64 access_tx_launch_fifo7_cor_err_cnt(const struct cntr_entry *entry,
3156 void *context, int vl, int mode,
3157 u64 data)
3158{
3159 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3160
3161 return dd->send_egress_err_status_cnt[55];
3162}
3163
3164static u64 access_tx_launch_fifo6_cor_err_cnt(const struct cntr_entry *entry,
3165 void *context, int vl, int mode,
3166 u64 data)
3167{
3168 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3169
3170 return dd->send_egress_err_status_cnt[54];
3171}
3172
3173static u64 access_tx_launch_fifo5_cor_err_cnt(const struct cntr_entry *entry,
3174 void *context, int vl, int mode,
3175 u64 data)
3176{
3177 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3178
3179 return dd->send_egress_err_status_cnt[53];
3180}
3181
3182static u64 access_tx_launch_fifo4_cor_err_cnt(const struct cntr_entry *entry,
3183 void *context, int vl, int mode,
3184 u64 data)
3185{
3186 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3187
3188 return dd->send_egress_err_status_cnt[52];
3189}
3190
3191static u64 access_tx_launch_fifo3_cor_err_cnt(const struct cntr_entry *entry,
3192 void *context, int vl, int mode,
3193 u64 data)
3194{
3195 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3196
3197 return dd->send_egress_err_status_cnt[51];
3198}
3199
3200static u64 access_tx_launch_fifo2_cor_err_cnt(const struct cntr_entry *entry,
3201 void *context, int vl, int mode,
3202 u64 data)
3203{
3204 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3205
3206 return dd->send_egress_err_status_cnt[50];
3207}
3208
3209static u64 access_tx_launch_fifo1_cor_err_cnt(const struct cntr_entry *entry,
3210 void *context, int vl, int mode,
3211 u64 data)
3212{
3213 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3214
3215 return dd->send_egress_err_status_cnt[49];
3216}
3217
3218static u64 access_tx_launch_fifo0_cor_err_cnt(const struct cntr_entry *entry,
3219 void *context, int vl, int mode,
3220 u64 data)
3221{
3222 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3223
3224 return dd->send_egress_err_status_cnt[48];
3225}
3226
3227static u64 access_tx_credit_return_vl_err_cnt(const struct cntr_entry *entry,
3228 void *context, int vl, int mode,
3229 u64 data)
3230{
3231 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3232
3233 return dd->send_egress_err_status_cnt[47];
3234}
3235
3236static u64 access_tx_hcrc_insertion_err_cnt(const struct cntr_entry *entry,
3237 void *context, int vl, int mode,
3238 u64 data)
3239{
3240 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3241
3242 return dd->send_egress_err_status_cnt[46];
3243}
3244
3245static u64 access_tx_egress_fifo_unc_err_cnt(const struct cntr_entry *entry,
3246 void *context, int vl, int mode,
3247 u64 data)
3248{
3249 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3250
3251 return dd->send_egress_err_status_cnt[45];
3252}
3253
3254static u64 access_tx_read_pio_memory_unc_err_cnt(const struct cntr_entry *entry,
3255 void *context, int vl,
3256 int mode, u64 data)
3257{
3258 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3259
3260 return dd->send_egress_err_status_cnt[44];
3261}
3262
3263static u64 access_tx_read_sdma_memory_unc_err_cnt(
3264 const struct cntr_entry *entry,
3265 void *context, int vl, int mode, u64 data)
3266{
3267 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3268
3269 return dd->send_egress_err_status_cnt[43];
3270}
3271
3272static u64 access_tx_sb_hdr_unc_err_cnt(const struct cntr_entry *entry,
3273 void *context, int vl, int mode,
3274 u64 data)
3275{
3276 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3277
3278 return dd->send_egress_err_status_cnt[42];
3279}
3280
3281static u64 access_tx_credit_return_partiy_err_cnt(
3282 const struct cntr_entry *entry,
3283 void *context, int vl, int mode, u64 data)
3284{
3285 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3286
3287 return dd->send_egress_err_status_cnt[41];
3288}
3289
3290static u64 access_tx_launch_fifo8_unc_or_parity_err_cnt(
3291 const struct cntr_entry *entry,
3292 void *context, int vl, int mode, u64 data)
3293{
3294 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3295
3296 return dd->send_egress_err_status_cnt[40];
3297}
3298
3299static u64 access_tx_launch_fifo7_unc_or_parity_err_cnt(
3300 const struct cntr_entry *entry,
3301 void *context, int vl, int mode, u64 data)
3302{
3303 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3304
3305 return dd->send_egress_err_status_cnt[39];
3306}
3307
3308static u64 access_tx_launch_fifo6_unc_or_parity_err_cnt(
3309 const struct cntr_entry *entry,
3310 void *context, int vl, int mode, u64 data)
3311{
3312 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3313
3314 return dd->send_egress_err_status_cnt[38];
3315}
3316
3317static u64 access_tx_launch_fifo5_unc_or_parity_err_cnt(
3318 const struct cntr_entry *entry,
3319 void *context, int vl, int mode, u64 data)
3320{
3321 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3322
3323 return dd->send_egress_err_status_cnt[37];
3324}
3325
3326static u64 access_tx_launch_fifo4_unc_or_parity_err_cnt(
3327 const struct cntr_entry *entry,
3328 void *context, int vl, int mode, u64 data)
3329{
3330 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3331
3332 return dd->send_egress_err_status_cnt[36];
3333}
3334
3335static u64 access_tx_launch_fifo3_unc_or_parity_err_cnt(
3336 const struct cntr_entry *entry,
3337 void *context, int vl, int mode, u64 data)
3338{
3339 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3340
3341 return dd->send_egress_err_status_cnt[35];
3342}
3343
3344static u64 access_tx_launch_fifo2_unc_or_parity_err_cnt(
3345 const struct cntr_entry *entry,
3346 void *context, int vl, int mode, u64 data)
3347{
3348 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3349
3350 return dd->send_egress_err_status_cnt[34];
3351}
3352
3353static u64 access_tx_launch_fifo1_unc_or_parity_err_cnt(
3354 const struct cntr_entry *entry,
3355 void *context, int vl, int mode, u64 data)
3356{
3357 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3358
3359 return dd->send_egress_err_status_cnt[33];
3360}
3361
3362static u64 access_tx_launch_fifo0_unc_or_parity_err_cnt(
3363 const struct cntr_entry *entry,
3364 void *context, int vl, int mode, u64 data)
3365{
3366 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3367
3368 return dd->send_egress_err_status_cnt[32];
3369}
3370
3371static u64 access_tx_sdma15_disallowed_packet_err_cnt(
3372 const struct cntr_entry *entry,
3373 void *context, int vl, int mode, u64 data)
3374{
3375 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3376
3377 return dd->send_egress_err_status_cnt[31];
3378}
3379
3380static u64 access_tx_sdma14_disallowed_packet_err_cnt(
3381 const struct cntr_entry *entry,
3382 void *context, int vl, int mode, u64 data)
3383{
3384 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3385
3386 return dd->send_egress_err_status_cnt[30];
3387}
3388
3389static u64 access_tx_sdma13_disallowed_packet_err_cnt(
3390 const struct cntr_entry *entry,
3391 void *context, int vl, int mode, u64 data)
3392{
3393 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3394
3395 return dd->send_egress_err_status_cnt[29];
3396}
3397
3398static u64 access_tx_sdma12_disallowed_packet_err_cnt(
3399 const struct cntr_entry *entry,
3400 void *context, int vl, int mode, u64 data)
3401{
3402 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3403
3404 return dd->send_egress_err_status_cnt[28];
3405}
3406
3407static u64 access_tx_sdma11_disallowed_packet_err_cnt(
3408 const struct cntr_entry *entry,
3409 void *context, int vl, int mode, u64 data)
3410{
3411 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3412
3413 return dd->send_egress_err_status_cnt[27];
3414}
3415
3416static u64 access_tx_sdma10_disallowed_packet_err_cnt(
3417 const struct cntr_entry *entry,
3418 void *context, int vl, int mode, u64 data)
3419{
3420 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3421
3422 return dd->send_egress_err_status_cnt[26];
3423}
3424
3425static u64 access_tx_sdma9_disallowed_packet_err_cnt(
3426 const struct cntr_entry *entry,
3427 void *context, int vl, int mode, u64 data)
3428{
3429 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3430
3431 return dd->send_egress_err_status_cnt[25];
3432}
3433
3434static u64 access_tx_sdma8_disallowed_packet_err_cnt(
3435 const struct cntr_entry *entry,
3436 void *context, int vl, int mode, u64 data)
3437{
3438 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3439
3440 return dd->send_egress_err_status_cnt[24];
3441}
3442
3443static u64 access_tx_sdma7_disallowed_packet_err_cnt(
3444 const struct cntr_entry *entry,
3445 void *context, int vl, int mode, u64 data)
3446{
3447 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3448
3449 return dd->send_egress_err_status_cnt[23];
3450}
3451
3452static u64 access_tx_sdma6_disallowed_packet_err_cnt(
3453 const struct cntr_entry *entry,
3454 void *context, int vl, int mode, u64 data)
3455{
3456 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3457
3458 return dd->send_egress_err_status_cnt[22];
3459}
3460
3461static u64 access_tx_sdma5_disallowed_packet_err_cnt(
3462 const struct cntr_entry *entry,
3463 void *context, int vl, int mode, u64 data)
3464{
3465 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3466
3467 return dd->send_egress_err_status_cnt[21];
3468}
3469
3470static u64 access_tx_sdma4_disallowed_packet_err_cnt(
3471 const struct cntr_entry *entry,
3472 void *context, int vl, int mode, u64 data)
3473{
3474 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3475
3476 return dd->send_egress_err_status_cnt[20];
3477}
3478
3479static u64 access_tx_sdma3_disallowed_packet_err_cnt(
3480 const struct cntr_entry *entry,
3481 void *context, int vl, int mode, u64 data)
3482{
3483 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3484
3485 return dd->send_egress_err_status_cnt[19];
3486}
3487
3488static u64 access_tx_sdma2_disallowed_packet_err_cnt(
3489 const struct cntr_entry *entry,
3490 void *context, int vl, int mode, u64 data)
3491{
3492 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3493
3494 return dd->send_egress_err_status_cnt[18];
3495}
3496
3497static u64 access_tx_sdma1_disallowed_packet_err_cnt(
3498 const struct cntr_entry *entry,
3499 void *context, int vl, int mode, u64 data)
3500{
3501 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3502
3503 return dd->send_egress_err_status_cnt[17];
3504}
3505
3506static u64 access_tx_sdma0_disallowed_packet_err_cnt(
3507 const struct cntr_entry *entry,
3508 void *context, int vl, int mode, u64 data)
3509{
3510 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3511
3512 return dd->send_egress_err_status_cnt[16];
3513}
3514
3515static u64 access_tx_config_parity_err_cnt(const struct cntr_entry *entry,
3516 void *context, int vl, int mode,
3517 u64 data)
3518{
3519 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3520
3521 return dd->send_egress_err_status_cnt[15];
3522}
3523
3524static u64 access_tx_sbrd_ctl_csr_parity_err_cnt(const struct cntr_entry *entry,
3525 void *context, int vl,
3526 int mode, u64 data)
3527{
3528 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3529
3530 return dd->send_egress_err_status_cnt[14];
3531}
3532
3533static u64 access_tx_launch_csr_parity_err_cnt(const struct cntr_entry *entry,
3534 void *context, int vl, int mode,
3535 u64 data)
3536{
3537 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3538
3539 return dd->send_egress_err_status_cnt[13];
3540}
3541
3542static u64 access_tx_illegal_vl_err_cnt(const struct cntr_entry *entry,
3543 void *context, int vl, int mode,
3544 u64 data)
3545{
3546 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3547
3548 return dd->send_egress_err_status_cnt[12];
3549}
3550
3551static u64 access_tx_sbrd_ctl_state_machine_parity_err_cnt(
3552 const struct cntr_entry *entry,
3553 void *context, int vl, int mode, u64 data)
3554{
3555 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3556
3557 return dd->send_egress_err_status_cnt[11];
3558}
3559
3560static u64 access_egress_reserved_10_err_cnt(const struct cntr_entry *entry,
3561 void *context, int vl, int mode,
3562 u64 data)
3563{
3564 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3565
3566 return dd->send_egress_err_status_cnt[10];
3567}
3568
3569static u64 access_egress_reserved_9_err_cnt(const struct cntr_entry *entry,
3570 void *context, int vl, int mode,
3571 u64 data)
3572{
3573 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3574
3575 return dd->send_egress_err_status_cnt[9];
3576}
3577
3578static u64 access_tx_sdma_launch_intf_parity_err_cnt(
3579 const struct cntr_entry *entry,
3580 void *context, int vl, int mode, u64 data)
3581{
3582 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3583
3584 return dd->send_egress_err_status_cnt[8];
3585}
3586
3587static u64 access_tx_pio_launch_intf_parity_err_cnt(
3588 const struct cntr_entry *entry,
3589 void *context, int vl, int mode, u64 data)
3590{
3591 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3592
3593 return dd->send_egress_err_status_cnt[7];
3594}
3595
3596static u64 access_egress_reserved_6_err_cnt(const struct cntr_entry *entry,
3597 void *context, int vl, int mode,
3598 u64 data)
3599{
3600 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3601
3602 return dd->send_egress_err_status_cnt[6];
3603}
3604
3605static u64 access_tx_incorrect_link_state_err_cnt(
3606 const struct cntr_entry *entry,
3607 void *context, int vl, int mode, u64 data)
3608{
3609 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3610
3611 return dd->send_egress_err_status_cnt[5];
3612}
3613
3614static u64 access_tx_linkdown_err_cnt(const struct cntr_entry *entry,
3615 void *context, int vl, int mode,
3616 u64 data)
3617{
3618 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3619
3620 return dd->send_egress_err_status_cnt[4];
3621}
3622
3623static u64 access_tx_egress_fifi_underrun_or_parity_err_cnt(
3624 const struct cntr_entry *entry,
3625 void *context, int vl, int mode, u64 data)
3626{
3627 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3628
3629 return dd->send_egress_err_status_cnt[3];
3630}
3631
3632static u64 access_egress_reserved_2_err_cnt(const struct cntr_entry *entry,
3633 void *context, int vl, int mode,
3634 u64 data)
3635{
3636 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3637
3638 return dd->send_egress_err_status_cnt[2];
3639}
3640
3641static u64 access_tx_pkt_integrity_mem_unc_err_cnt(
3642 const struct cntr_entry *entry,
3643 void *context, int vl, int mode, u64 data)
3644{
3645 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3646
3647 return dd->send_egress_err_status_cnt[1];
3648}
3649
3650static u64 access_tx_pkt_integrity_mem_cor_err_cnt(
3651 const struct cntr_entry *entry,
3652 void *context, int vl, int mode, u64 data)
3653{
3654 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3655
3656 return dd->send_egress_err_status_cnt[0];
3657}
3658
3659/*
3660 * Software counters corresponding to each of the
3661 * error status bits within SendErrStatus
3662 */
3663static u64 access_send_csr_write_bad_addr_err_cnt(
3664 const struct cntr_entry *entry,
3665 void *context, int vl, int mode, u64 data)
3666{
3667 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3668
3669 return dd->send_err_status_cnt[2];
3670}
3671
3672static u64 access_send_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
3673 void *context, int vl,
3674 int mode, u64 data)
3675{
3676 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3677
3678 return dd->send_err_status_cnt[1];
3679}
3680
3681static u64 access_send_csr_parity_cnt(const struct cntr_entry *entry,
3682 void *context, int vl, int mode,
3683 u64 data)
3684{
3685 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3686
3687 return dd->send_err_status_cnt[0];
3688}
3689
3690/*
3691 * Software counters corresponding to each of the
3692 * error status bits within SendCtxtErrStatus
3693 */
3694static u64 access_pio_write_out_of_bounds_err_cnt(
3695 const struct cntr_entry *entry,
3696 void *context, int vl, int mode, u64 data)
3697{
3698 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3699
3700 return dd->sw_ctxt_err_status_cnt[4];
3701}
3702
3703static u64 access_pio_write_overflow_err_cnt(const struct cntr_entry *entry,
3704 void *context, int vl, int mode,
3705 u64 data)
3706{
3707 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3708
3709 return dd->sw_ctxt_err_status_cnt[3];
3710}
3711
3712static u64 access_pio_write_crosses_boundary_err_cnt(
3713 const struct cntr_entry *entry,
3714 void *context, int vl, int mode, u64 data)
3715{
3716 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3717
3718 return dd->sw_ctxt_err_status_cnt[2];
3719}
3720
3721static u64 access_pio_disallowed_packet_err_cnt(const struct cntr_entry *entry,
3722 void *context, int vl,
3723 int mode, u64 data)
3724{
3725 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3726
3727 return dd->sw_ctxt_err_status_cnt[1];
3728}
3729
3730static u64 access_pio_inconsistent_sop_err_cnt(const struct cntr_entry *entry,
3731 void *context, int vl, int mode,
3732 u64 data)
3733{
3734 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3735
3736 return dd->sw_ctxt_err_status_cnt[0];
3737}
3738
3739/*
3740 * Software counters corresponding to each of the
3741 * error status bits within SendDmaEngErrStatus
3742 */
3743static u64 access_sdma_header_request_fifo_cor_err_cnt(
3744 const struct cntr_entry *entry,
3745 void *context, int vl, int mode, u64 data)
3746{
3747 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3748
3749 return dd->sw_send_dma_eng_err_status_cnt[23];
3750}
3751
3752static u64 access_sdma_header_storage_cor_err_cnt(
3753 const struct cntr_entry *entry,
3754 void *context, int vl, int mode, u64 data)
3755{
3756 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3757
3758 return dd->sw_send_dma_eng_err_status_cnt[22];
3759}
3760
3761static u64 access_sdma_packet_tracking_cor_err_cnt(
3762 const struct cntr_entry *entry,
3763 void *context, int vl, int mode, u64 data)
3764{
3765 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3766
3767 return dd->sw_send_dma_eng_err_status_cnt[21];
3768}
3769
3770static u64 access_sdma_assembly_cor_err_cnt(const struct cntr_entry *entry,
3771 void *context, int vl, int mode,
3772 u64 data)
3773{
3774 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3775
3776 return dd->sw_send_dma_eng_err_status_cnt[20];
3777}
3778
3779static u64 access_sdma_desc_table_cor_err_cnt(const struct cntr_entry *entry,
3780 void *context, int vl, int mode,
3781 u64 data)
3782{
3783 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3784
3785 return dd->sw_send_dma_eng_err_status_cnt[19];
3786}
3787
3788static u64 access_sdma_header_request_fifo_unc_err_cnt(
3789 const struct cntr_entry *entry,
3790 void *context, int vl, int mode, u64 data)
3791{
3792 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3793
3794 return dd->sw_send_dma_eng_err_status_cnt[18];
3795}
3796
3797static u64 access_sdma_header_storage_unc_err_cnt(
3798 const struct cntr_entry *entry,
3799 void *context, int vl, int mode, u64 data)
3800{
3801 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3802
3803 return dd->sw_send_dma_eng_err_status_cnt[17];
3804}
3805
3806static u64 access_sdma_packet_tracking_unc_err_cnt(
3807 const struct cntr_entry *entry,
3808 void *context, int vl, int mode, u64 data)
3809{
3810 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3811
3812 return dd->sw_send_dma_eng_err_status_cnt[16];
3813}
3814
3815static u64 access_sdma_assembly_unc_err_cnt(const struct cntr_entry *entry,
3816 void *context, int vl, int mode,
3817 u64 data)
3818{
3819 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3820
3821 return dd->sw_send_dma_eng_err_status_cnt[15];
3822}
3823
3824static u64 access_sdma_desc_table_unc_err_cnt(const struct cntr_entry *entry,
3825 void *context, int vl, int mode,
3826 u64 data)
3827{
3828 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3829
3830 return dd->sw_send_dma_eng_err_status_cnt[14];
3831}
3832
3833static u64 access_sdma_timeout_err_cnt(const struct cntr_entry *entry,
3834 void *context, int vl, int mode,
3835 u64 data)
3836{
3837 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3838
3839 return dd->sw_send_dma_eng_err_status_cnt[13];
3840}
3841
3842static u64 access_sdma_header_length_err_cnt(const struct cntr_entry *entry,
3843 void *context, int vl, int mode,
3844 u64 data)
3845{
3846 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3847
3848 return dd->sw_send_dma_eng_err_status_cnt[12];
3849}
3850
3851static u64 access_sdma_header_address_err_cnt(const struct cntr_entry *entry,
3852 void *context, int vl, int mode,
3853 u64 data)
3854{
3855 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3856
3857 return dd->sw_send_dma_eng_err_status_cnt[11];
3858}
3859
3860static u64 access_sdma_header_select_err_cnt(const struct cntr_entry *entry,
3861 void *context, int vl, int mode,
3862 u64 data)
3863{
3864 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3865
3866 return dd->sw_send_dma_eng_err_status_cnt[10];
3867}
3868
3869static u64 access_sdma_reserved_9_err_cnt(const struct cntr_entry *entry,
3870 void *context, int vl, int mode,
3871 u64 data)
3872{
3873 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3874
3875 return dd->sw_send_dma_eng_err_status_cnt[9];
3876}
3877
3878static u64 access_sdma_packet_desc_overflow_err_cnt(
3879 const struct cntr_entry *entry,
3880 void *context, int vl, int mode, u64 data)
3881{
3882 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3883
3884 return dd->sw_send_dma_eng_err_status_cnt[8];
3885}
3886
3887static u64 access_sdma_length_mismatch_err_cnt(const struct cntr_entry *entry,
3888 void *context, int vl,
3889 int mode, u64 data)
3890{
3891 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3892
3893 return dd->sw_send_dma_eng_err_status_cnt[7];
3894}
3895
3896static u64 access_sdma_halt_err_cnt(const struct cntr_entry *entry,
3897 void *context, int vl, int mode, u64 data)
3898{
3899 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3900
3901 return dd->sw_send_dma_eng_err_status_cnt[6];
3902}
3903
3904static u64 access_sdma_mem_read_err_cnt(const struct cntr_entry *entry,
3905 void *context, int vl, int mode,
3906 u64 data)
3907{
3908 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3909
3910 return dd->sw_send_dma_eng_err_status_cnt[5];
3911}
3912
3913static u64 access_sdma_first_desc_err_cnt(const struct cntr_entry *entry,
3914 void *context, int vl, int mode,
3915 u64 data)
3916{
3917 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3918
3919 return dd->sw_send_dma_eng_err_status_cnt[4];
3920}
3921
3922static u64 access_sdma_tail_out_of_bounds_err_cnt(
3923 const struct cntr_entry *entry,
3924 void *context, int vl, int mode, u64 data)
3925{
3926 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3927
3928 return dd->sw_send_dma_eng_err_status_cnt[3];
3929}
3930
3931static u64 access_sdma_too_long_err_cnt(const struct cntr_entry *entry,
3932 void *context, int vl, int mode,
3933 u64 data)
3934{
3935 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3936
3937 return dd->sw_send_dma_eng_err_status_cnt[2];
3938}
3939
3940static u64 access_sdma_gen_mismatch_err_cnt(const struct cntr_entry *entry,
3941 void *context, int vl, int mode,
3942 u64 data)
3943{
3944 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3945
3946 return dd->sw_send_dma_eng_err_status_cnt[1];
3947}
3948
3949static u64 access_sdma_wrong_dw_err_cnt(const struct cntr_entry *entry,
3950 void *context, int vl, int mode,
3951 u64 data)
3952{
3953 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3954
3955 return dd->sw_send_dma_eng_err_status_cnt[0];
3956}
3957
2b719046
JP		 3958static u64 access_dc_rcv_err_cnt(const struct cntr_entry *entry,
3959 void *context, int vl, int mode,
3960 u64 data)
3961{
3962 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3963
3964 u64 val = 0;
3965 u64 csr = entry->csr;
3966
3967 val = read_write_csr(dd, csr, mode, data);
3968 if (mode == CNTR_MODE_R) {
3969 val = val > CNTR_MAX - dd->sw_rcv_bypass_packet_errors ?
3970 CNTR_MAX : val + dd->sw_rcv_bypass_packet_errors;
3971 } else if (mode == CNTR_MODE_W) {
3972 dd->sw_rcv_bypass_packet_errors = 0;
3973 } else {
3974 dd_dev_err(dd, "Invalid cntr register access mode");
3975 return 0;
3976 }
3977 return val;
3978}
3979
77241056
MM		 3980#define def_access_sw_cpu(cntr) \
3981static u64 access_sw_cpu_##cntr(const struct cntr_entry *entry, \
3982 void *context, int vl, int mode, u64 data) \
3983{ \
3984 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \
4eb06882
DD		 3985 return read_write_cpu(ppd->dd, &ppd->ibport_data.rvp.z_ ##cntr, \
3986 ppd->ibport_data.rvp.cntr, vl, \
77241056
MM		 3987 mode, data); \
3988}
3989
3990def_access_sw_cpu(rc_acks);
3991def_access_sw_cpu(rc_qacks);
3992def_access_sw_cpu(rc_delayed_comp);
3993
3994#define def_access_ibp_counter(cntr) \
3995static u64 access_ibp_##cntr(const struct cntr_entry *entry, \
3996 void *context, int vl, int mode, u64 data) \
3997{ \
3998 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \
3999 \
4000 if (vl != CNTR_INVALID_VL) \
4001 return 0; \
4002 \
4eb06882 4003 return read_write_sw(ppd->dd, &ppd->ibport_data.rvp.n_ ##cntr, \
77241056
MM		 4004 mode, data); \
4005}
4006
4007def_access_ibp_counter(loop_pkts);
4008def_access_ibp_counter(rc_resends);
4009def_access_ibp_counter(rnr_naks);
4010def_access_ibp_counter(other_naks);
4011def_access_ibp_counter(rc_timeouts);
4012def_access_ibp_counter(pkt_drops);
4013def_access_ibp_counter(dmawait);
4014def_access_ibp_counter(rc_seqnak);
4015def_access_ibp_counter(rc_dupreq);
4016def_access_ibp_counter(rdma_seq);
4017def_access_ibp_counter(unaligned);
4018def_access_ibp_counter(seq_naks);
4019
4020static struct cntr_entry dev_cntrs[DEV_CNTR_LAST] = {
4021[C_RCV_OVF] = RXE32_DEV_CNTR_ELEM(RcvOverflow, RCV_BUF_OVFL_CNT, CNTR_SYNTH),
4022[C_RX_TID_FULL] = RXE32_DEV_CNTR_ELEM(RxTIDFullEr, RCV_TID_FULL_ERR_CNT,
4023 CNTR_NORMAL),
4024[C_RX_TID_INVALID] = RXE32_DEV_CNTR_ELEM(RxTIDInvalid, RCV_TID_VALID_ERR_CNT,
4025 CNTR_NORMAL),
4026[C_RX_TID_FLGMS] = RXE32_DEV_CNTR_ELEM(RxTidFLGMs,
4027 RCV_TID_FLOW_GEN_MISMATCH_CNT,
4028 CNTR_NORMAL),
77241056
MM		 4029[C_RX_CTX_EGRS] = RXE32_DEV_CNTR_ELEM(RxCtxEgrS, RCV_CONTEXT_EGR_STALL,
4030 CNTR_NORMAL),
4031[C_RCV_TID_FLSMS] = RXE32_DEV_CNTR_ELEM(RxTidFLSMs,
4032 RCV_TID_FLOW_SEQ_MISMATCH_CNT, CNTR_NORMAL),
4033[C_CCE_PCI_CR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciCrSt,
4034 CCE_PCIE_POSTED_CRDT_STALL_CNT, CNTR_NORMAL),
4035[C_CCE_PCI_TR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciTrSt, CCE_PCIE_TRGT_STALL_CNT,
4036 CNTR_NORMAL),
4037[C_CCE_PIO_WR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePioWrSt, CCE_PIO_WR_STALL_CNT,
4038 CNTR_NORMAL),
4039[C_CCE_ERR_INT] = CCE_INT_DEV_CNTR_ELEM(CceErrInt, CCE_ERR_INT_CNT,
4040 CNTR_NORMAL),
4041[C_CCE_SDMA_INT] = CCE_INT_DEV_CNTR_ELEM(CceSdmaInt, CCE_SDMA_INT_CNT,
4042 CNTR_NORMAL),
4043[C_CCE_MISC_INT] = CCE_INT_DEV_CNTR_ELEM(CceMiscInt, CCE_MISC_INT_CNT,
4044 CNTR_NORMAL),
4045[C_CCE_RCV_AV_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvAvInt, CCE_RCV_AVAIL_INT_CNT,
4046 CNTR_NORMAL),
4047[C_CCE_RCV_URG_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvUrgInt,
4048 CCE_RCV_URGENT_INT_CNT, CNTR_NORMAL),
4049[C_CCE_SEND_CR_INT] = CCE_INT_DEV_CNTR_ELEM(CceSndCrInt,
4050 CCE_SEND_CREDIT_INT_CNT, CNTR_NORMAL),
4051[C_DC_UNC_ERR] = DC_PERF_CNTR(DcUnctblErr, DCC_ERR_UNCORRECTABLE_CNT,
4052 CNTR_SYNTH),
2b719046
JP		 4053[C_DC_RCV_ERR] = CNTR_ELEM("DcRecvErr", DCC_ERR_PORTRCV_ERR_CNT, 0, CNTR_SYNTH,
4054 access_dc_rcv_err_cnt),
77241056
MM		 4055[C_DC_FM_CFG_ERR] = DC_PERF_CNTR(DcFmCfgErr, DCC_ERR_FMCONFIG_ERR_CNT,
4056 CNTR_SYNTH),
4057[C_DC_RMT_PHY_ERR] = DC_PERF_CNTR(DcRmtPhyErr, DCC_ERR_RCVREMOTE_PHY_ERR_CNT,
4058 CNTR_SYNTH),
4059[C_DC_DROPPED_PKT] = DC_PERF_CNTR(DcDroppedPkt, DCC_ERR_DROPPED_PKT_CNT,
4060 CNTR_SYNTH),
4061[C_DC_MC_XMIT_PKTS] = DC_PERF_CNTR(DcMcXmitPkts,
4062 DCC_PRF_PORT_XMIT_MULTICAST_CNT, CNTR_SYNTH),
4063[C_DC_MC_RCV_PKTS] = DC_PERF_CNTR(DcMcRcvPkts,
4064 DCC_PRF_PORT_RCV_MULTICAST_PKT_CNT,
4065 CNTR_SYNTH),
4066[C_DC_XMIT_CERR] = DC_PERF_CNTR(DcXmitCorr,
4067 DCC_PRF_PORT_XMIT_CORRECTABLE_CNT, CNTR_SYNTH),
4068[C_DC_RCV_CERR] = DC_PERF_CNTR(DcRcvCorrCnt, DCC_PRF_PORT_RCV_CORRECTABLE_CNT,
4069 CNTR_SYNTH),
4070[C_DC_RCV_FCC] = DC_PERF_CNTR(DcRxFCntl, DCC_PRF_RX_FLOW_CRTL_CNT,
4071 CNTR_SYNTH),
4072[C_DC_XMIT_FCC] = DC_PERF_CNTR(DcXmitFCntl, DCC_PRF_TX_FLOW_CRTL_CNT,
4073 CNTR_SYNTH),
4074[C_DC_XMIT_FLITS] = DC_PERF_CNTR(DcXmitFlits, DCC_PRF_PORT_XMIT_DATA_CNT,
4075 CNTR_SYNTH),
4076[C_DC_RCV_FLITS] = DC_PERF_CNTR(DcRcvFlits, DCC_PRF_PORT_RCV_DATA_CNT,
4077 CNTR_SYNTH),
4078[C_DC_XMIT_PKTS] = DC_PERF_CNTR(DcXmitPkts, DCC_PRF_PORT_XMIT_PKTS_CNT,
4079 CNTR_SYNTH),
4080[C_DC_RCV_PKTS] = DC_PERF_CNTR(DcRcvPkts, DCC_PRF_PORT_RCV_PKTS_CNT,
4081 CNTR_SYNTH),
4082[C_DC_RX_FLIT_VL] = DC_PERF_CNTR(DcRxFlitVl, DCC_PRF_PORT_VL_RCV_DATA_CNT,
4083 CNTR_SYNTH | CNTR_VL),
4084[C_DC_RX_PKT_VL] = DC_PERF_CNTR(DcRxPktVl, DCC_PRF_PORT_VL_RCV_PKTS_CNT,
4085 CNTR_SYNTH | CNTR_VL),
4086[C_DC_RCV_FCN] = DC_PERF_CNTR(DcRcvFcn, DCC_PRF_PORT_RCV_FECN_CNT, CNTR_SYNTH),
4087[C_DC_RCV_FCN_VL] = DC_PERF_CNTR(DcRcvFcnVl, DCC_PRF_PORT_VL_RCV_FECN_CNT,
4088 CNTR_SYNTH | CNTR_VL),
4089[C_DC_RCV_BCN] = DC_PERF_CNTR(DcRcvBcn, DCC_PRF_PORT_RCV_BECN_CNT, CNTR_SYNTH),
4090[C_DC_RCV_BCN_VL] = DC_PERF_CNTR(DcRcvBcnVl, DCC_PRF_PORT_VL_RCV_BECN_CNT,
4091 CNTR_SYNTH | CNTR_VL),
4092[C_DC_RCV_BBL] = DC_PERF_CNTR(DcRcvBbl, DCC_PRF_PORT_RCV_BUBBLE_CNT,
4093 CNTR_SYNTH),
4094[C_DC_RCV_BBL_VL] = DC_PERF_CNTR(DcRcvBblVl, DCC_PRF_PORT_VL_RCV_BUBBLE_CNT,
4095 CNTR_SYNTH | CNTR_VL),
4096[C_DC_MARK_FECN] = DC_PERF_CNTR(DcMarkFcn, DCC_PRF_PORT_MARK_FECN_CNT,
4097 CNTR_SYNTH),
4098[C_DC_MARK_FECN_VL] = DC_PERF_CNTR(DcMarkFcnVl, DCC_PRF_PORT_VL_MARK_FECN_CNT,
4099 CNTR_SYNTH | CNTR_VL),
4100[C_DC_TOTAL_CRC] =
4101 DC_PERF_CNTR_LCB(DcTotCrc, DC_LCB_ERR_INFO_TOTAL_CRC_ERR,
4102 CNTR_SYNTH),
4103[C_DC_CRC_LN0] = DC_PERF_CNTR_LCB(DcCrcLn0, DC_LCB_ERR_INFO_CRC_ERR_LN0,
4104 CNTR_SYNTH),
4105[C_DC_CRC_LN1] = DC_PERF_CNTR_LCB(DcCrcLn1, DC_LCB_ERR_INFO_CRC_ERR_LN1,
4106 CNTR_SYNTH),
4107[C_DC_CRC_LN2] = DC_PERF_CNTR_LCB(DcCrcLn2, DC_LCB_ERR_INFO_CRC_ERR_LN2,
4108 CNTR_SYNTH),
4109[C_DC_CRC_LN3] = DC_PERF_CNTR_LCB(DcCrcLn3, DC_LCB_ERR_INFO_CRC_ERR_LN3,
4110 CNTR_SYNTH),
4111[C_DC_CRC_MULT_LN] =
4112 DC_PERF_CNTR_LCB(DcMultLn, DC_LCB_ERR_INFO_CRC_ERR_MULTI_LN,
4113 CNTR_SYNTH),
4114[C_DC_TX_REPLAY] = DC_PERF_CNTR_LCB(DcTxReplay, DC_LCB_ERR_INFO_TX_REPLAY_CNT,
4115 CNTR_SYNTH),
4116[C_DC_RX_REPLAY] = DC_PERF_CNTR_LCB(DcRxReplay, DC_LCB_ERR_INFO_RX_REPLAY_CNT,
4117 CNTR_SYNTH),
4118[C_DC_SEQ_CRC_CNT] =
4119 DC_PERF_CNTR_LCB(DcLinkSeqCrc, DC_LCB_ERR_INFO_SEQ_CRC_CNT,
4120 CNTR_SYNTH),
4121[C_DC_ESC0_ONLY_CNT] =
4122 DC_PERF_CNTR_LCB(DcEsc0, DC_LCB_ERR_INFO_ESCAPE_0_ONLY_CNT,
4123 CNTR_SYNTH),
4124[C_DC_ESC0_PLUS1_CNT] =
4125 DC_PERF_CNTR_LCB(DcEsc1, DC_LCB_ERR_INFO_ESCAPE_0_PLUS1_CNT,
4126 CNTR_SYNTH),
4127[C_DC_ESC0_PLUS2_CNT] =
4128 DC_PERF_CNTR_LCB(DcEsc0Plus2, DC_LCB_ERR_INFO_ESCAPE_0_PLUS2_CNT,
4129 CNTR_SYNTH),
4130[C_DC_REINIT_FROM_PEER_CNT] =
4131 DC_PERF_CNTR_LCB(DcReinitPeer, DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT,
4132 CNTR_SYNTH),
4133[C_DC_SBE_CNT] = DC_PERF_CNTR_LCB(DcSbe, DC_LCB_ERR_INFO_SBE_CNT,
4134 CNTR_SYNTH),
4135[C_DC_MISC_FLG_CNT] =
4136 DC_PERF_CNTR_LCB(DcMiscFlg, DC_LCB_ERR_INFO_MISC_FLG_CNT,
4137 CNTR_SYNTH),
4138[C_DC_PRF_GOOD_LTP_CNT] =
4139 DC_PERF_CNTR_LCB(DcGoodLTP, DC_LCB_PRF_GOOD_LTP_CNT, CNTR_SYNTH),
4140[C_DC_PRF_ACCEPTED_LTP_CNT] =
4141 DC_PERF_CNTR_LCB(DcAccLTP, DC_LCB_PRF_ACCEPTED_LTP_CNT,
4142 CNTR_SYNTH),
4143[C_DC_PRF_RX_FLIT_CNT] =
4144 DC_PERF_CNTR_LCB(DcPrfRxFlit, DC_LCB_PRF_RX_FLIT_CNT, CNTR_SYNTH),
4145[C_DC_PRF_TX_FLIT_CNT] =
4146 DC_PERF_CNTR_LCB(DcPrfTxFlit, DC_LCB_PRF_TX_FLIT_CNT, CNTR_SYNTH),
4147[C_DC_PRF_CLK_CNTR] =
4148 DC_PERF_CNTR_LCB(DcPrfClk, DC_LCB_PRF_CLK_CNTR, CNTR_SYNTH),
4149[C_DC_PG_DBG_FLIT_CRDTS_CNT] =
4150 DC_PERF_CNTR_LCB(DcFltCrdts, DC_LCB_PG_DBG_FLIT_CRDTS_CNT, CNTR_SYNTH),
4151[C_DC_PG_STS_PAUSE_COMPLETE_CNT] =
4152 DC_PERF_CNTR_LCB(DcPauseComp, DC_LCB_PG_STS_PAUSE_COMPLETE_CNT,
4153 CNTR_SYNTH),
4154[C_DC_PG_STS_TX_SBE_CNT] =
4155 DC_PERF_CNTR_LCB(DcStsTxSbe, DC_LCB_PG_STS_TX_SBE_CNT, CNTR_SYNTH),
4156[C_DC_PG_STS_TX_MBE_CNT] =
4157 DC_PERF_CNTR_LCB(DcStsTxMbe, DC_LCB_PG_STS_TX_MBE_CNT,
4158 CNTR_SYNTH),
4159[C_SW_CPU_INTR] = CNTR_ELEM("Intr", 0, 0, CNTR_NORMAL,
4160 access_sw_cpu_intr),
4161[C_SW_CPU_RCV_LIM] = CNTR_ELEM("RcvLimit", 0, 0, CNTR_NORMAL,
4162 access_sw_cpu_rcv_limit),
4163[C_SW_VTX_WAIT] = CNTR_ELEM("vTxWait", 0, 0, CNTR_NORMAL,
4164 access_sw_vtx_wait),
4165[C_SW_PIO_WAIT] = CNTR_ELEM("PioWait", 0, 0, CNTR_NORMAL,
4166 access_sw_pio_wait),
14553ca1
MM		 4167[C_SW_PIO_DRAIN] = CNTR_ELEM("PioDrain", 0, 0, CNTR_NORMAL,
4168 access_sw_pio_drain),
77241056
MM		 4169[C_SW_KMEM_WAIT] = CNTR_ELEM("KmemWait", 0, 0, CNTR_NORMAL,
4170 access_sw_kmem_wait),
b421922e
DL		 4171[C_SW_SEND_SCHED] = CNTR_ELEM("SendSched", 0, 0, CNTR_NORMAL,
4172 access_sw_send_schedule),
a699c6c2
VM		 4173[C_SDMA_DESC_FETCHED_CNT] = CNTR_ELEM("SDEDscFdCn",
4174 SEND_DMA_DESC_FETCHED_CNT, 0,
4175 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4176 dev_access_u32_csr),
4177[C_SDMA_INT_CNT] = CNTR_ELEM("SDMAInt", 0, 0,
4178 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4179 access_sde_int_cnt),
4180[C_SDMA_ERR_CNT] = CNTR_ELEM("SDMAErrCt", 0, 0,
4181 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4182 access_sde_err_cnt),
4183[C_SDMA_IDLE_INT_CNT] = CNTR_ELEM("SDMAIdInt", 0, 0,
4184 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4185 access_sde_idle_int_cnt),
4186[C_SDMA_PROGRESS_INT_CNT] = CNTR_ELEM("SDMAPrIntCn", 0, 0,
4187 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4188 access_sde_progress_int_cnt),
2c5b521a
JR		 4189/* MISC_ERR_STATUS */
4190[C_MISC_PLL_LOCK_FAIL_ERR] = CNTR_ELEM("MISC_PLL_LOCK_FAIL_ERR", 0, 0,
4191 CNTR_NORMAL,
4192 access_misc_pll_lock_fail_err_cnt),
4193[C_MISC_MBIST_FAIL_ERR] = CNTR_ELEM("MISC_MBIST_FAIL_ERR", 0, 0,
4194 CNTR_NORMAL,
4195 access_misc_mbist_fail_err_cnt),
4196[C_MISC_INVALID_EEP_CMD_ERR] = CNTR_ELEM("MISC_INVALID_EEP_CMD_ERR", 0, 0,
4197 CNTR_NORMAL,
4198 access_misc_invalid_eep_cmd_err_cnt),
4199[C_MISC_EFUSE_DONE_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_DONE_PARITY_ERR", 0, 0,
4200 CNTR_NORMAL,
4201 access_misc_efuse_done_parity_err_cnt),
4202[C_MISC_EFUSE_WRITE_ERR] = CNTR_ELEM("MISC_EFUSE_WRITE_ERR", 0, 0,
4203 CNTR_NORMAL,
4204 access_misc_efuse_write_err_cnt),
4205[C_MISC_EFUSE_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_EFUSE_READ_BAD_ADDR_ERR", 0,
4206 0, CNTR_NORMAL,
4207 access_misc_efuse_read_bad_addr_err_cnt),
4208[C_MISC_EFUSE_CSR_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_CSR_PARITY_ERR", 0, 0,
4209 CNTR_NORMAL,
4210 access_misc_efuse_csr_parity_err_cnt),
4211[C_MISC_FW_AUTH_FAILED_ERR] = CNTR_ELEM("MISC_FW_AUTH_FAILED_ERR", 0, 0,
4212 CNTR_NORMAL,
4213 access_misc_fw_auth_failed_err_cnt),
4214[C_MISC_KEY_MISMATCH_ERR] = CNTR_ELEM("MISC_KEY_MISMATCH_ERR", 0, 0,
4215 CNTR_NORMAL,
4216 access_misc_key_mismatch_err_cnt),
4217[C_MISC_SBUS_WRITE_FAILED_ERR] = CNTR_ELEM("MISC_SBUS_WRITE_FAILED_ERR", 0, 0,
4218 CNTR_NORMAL,
4219 access_misc_sbus_write_failed_err_cnt),
4220[C_MISC_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_WRITE_BAD_ADDR_ERR", 0, 0,
4221 CNTR_NORMAL,
4222 access_misc_csr_write_bad_addr_err_cnt),
4223[C_MISC_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_READ_BAD_ADDR_ERR", 0, 0,
4224 CNTR_NORMAL,
4225 access_misc_csr_read_bad_addr_err_cnt),
4226[C_MISC_CSR_PARITY_ERR] = CNTR_ELEM("MISC_CSR_PARITY_ERR", 0, 0,
4227 CNTR_NORMAL,
4228 access_misc_csr_parity_err_cnt),
4229/* CceErrStatus */
4230[C_CCE_ERR_STATUS_AGGREGATED_CNT] = CNTR_ELEM("CceErrStatusAggregatedCnt", 0, 0,
4231 CNTR_NORMAL,
4232 access_sw_cce_err_status_aggregated_cnt),
4233[C_CCE_MSIX_CSR_PARITY_ERR] = CNTR_ELEM("CceMsixCsrParityErr", 0, 0,
4234 CNTR_NORMAL,
4235 access_cce_msix_csr_parity_err_cnt),
4236[C_CCE_INT_MAP_UNC_ERR] = CNTR_ELEM("CceIntMapUncErr", 0, 0,
4237 CNTR_NORMAL,
4238 access_cce_int_map_unc_err_cnt),
4239[C_CCE_INT_MAP_COR_ERR] = CNTR_ELEM("CceIntMapCorErr", 0, 0,
4240 CNTR_NORMAL,
4241 access_cce_int_map_cor_err_cnt),
4242[C_CCE_MSIX_TABLE_UNC_ERR] = CNTR_ELEM("CceMsixTableUncErr", 0, 0,
4243 CNTR_NORMAL,
4244 access_cce_msix_table_unc_err_cnt),
4245[C_CCE_MSIX_TABLE_COR_ERR] = CNTR_ELEM("CceMsixTableCorErr", 0, 0,
4246 CNTR_NORMAL,
4247 access_cce_msix_table_cor_err_cnt),
4248[C_CCE_RXDMA_CONV_FIFO_PARITY_ERR] = CNTR_ELEM("CceRxdmaConvFifoParityErr", 0,
4249 0, CNTR_NORMAL,
4250 access_cce_rxdma_conv_fifo_parity_err_cnt),
4251[C_CCE_RCPL_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceRcplAsyncFifoParityErr", 0,
4252 0, CNTR_NORMAL,
4253 access_cce_rcpl_async_fifo_parity_err_cnt),
4254[C_CCE_SEG_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceSegWriteBadAddrErr", 0, 0,
4255 CNTR_NORMAL,
4256 access_cce_seg_write_bad_addr_err_cnt),
4257[C_CCE_SEG_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceSegReadBadAddrErr", 0, 0,
4258 CNTR_NORMAL,
4259 access_cce_seg_read_bad_addr_err_cnt),
4260[C_LA_TRIGGERED] = CNTR_ELEM("Cce LATriggered", 0, 0,
4261 CNTR_NORMAL,
4262 access_la_triggered_cnt),
4263[C_CCE_TRGT_CPL_TIMEOUT_ERR] = CNTR_ELEM("CceTrgtCplTimeoutErr", 0, 0,
4264 CNTR_NORMAL,
4265 access_cce_trgt_cpl_timeout_err_cnt),
4266[C_PCIC_RECEIVE_PARITY_ERR] = CNTR_ELEM("PcicReceiveParityErr", 0, 0,
4267 CNTR_NORMAL,
4268 access_pcic_receive_parity_err_cnt),
4269[C_PCIC_TRANSMIT_BACK_PARITY_ERR] = CNTR_ELEM("PcicTransmitBackParityErr", 0, 0,
4270 CNTR_NORMAL,
4271 access_pcic_transmit_back_parity_err_cnt),
4272[C_PCIC_TRANSMIT_FRONT_PARITY_ERR] = CNTR_ELEM("PcicTransmitFrontParityErr", 0,
4273 0, CNTR_NORMAL,
4274 access_pcic_transmit_front_parity_err_cnt),
4275[C_PCIC_CPL_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicCplDatQUncErr", 0, 0,
4276 CNTR_NORMAL,
4277 access_pcic_cpl_dat_q_unc_err_cnt),
4278[C_PCIC_CPL_HD_Q_UNC_ERR] = CNTR_ELEM("PcicCplHdQUncErr", 0, 0,
4279 CNTR_NORMAL,
4280 access_pcic_cpl_hd_q_unc_err_cnt),
4281[C_PCIC_POST_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicPostDatQUncErr", 0, 0,
4282 CNTR_NORMAL,
4283 access_pcic_post_dat_q_unc_err_cnt),
4284[C_PCIC_POST_HD_Q_UNC_ERR] = CNTR_ELEM("PcicPostHdQUncErr", 0, 0,
4285 CNTR_NORMAL,
4286 access_pcic_post_hd_q_unc_err_cnt),
4287[C_PCIC_RETRY_SOT_MEM_UNC_ERR] = CNTR_ELEM("PcicRetrySotMemUncErr", 0, 0,
4288 CNTR_NORMAL,
4289 access_pcic_retry_sot_mem_unc_err_cnt),
4290[C_PCIC_RETRY_MEM_UNC_ERR] = CNTR_ELEM("PcicRetryMemUncErr", 0, 0,
4291 CNTR_NORMAL,
4292 access_pcic_retry_mem_unc_err),
4293[C_PCIC_N_POST_DAT_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostDatQParityErr", 0, 0,
4294 CNTR_NORMAL,
4295 access_pcic_n_post_dat_q_parity_err_cnt),
4296[C_PCIC_N_POST_H_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostHQParityErr", 0, 0,
4297 CNTR_NORMAL,
4298 access_pcic_n_post_h_q_parity_err_cnt),
4299[C_PCIC_CPL_DAT_Q_COR_ERR] = CNTR_ELEM("PcicCplDatQCorErr", 0, 0,
4300 CNTR_NORMAL,
4301 access_pcic_cpl_dat_q_cor_err_cnt),
4302[C_PCIC_CPL_HD_Q_COR_ERR] = CNTR_ELEM("PcicCplHdQCorErr", 0, 0,
4303 CNTR_NORMAL,
4304 access_pcic_cpl_hd_q_cor_err_cnt),
4305[C_PCIC_POST_DAT_Q_COR_ERR] = CNTR_ELEM("PcicPostDatQCorErr", 0, 0,
4306 CNTR_NORMAL,
4307 access_pcic_post_dat_q_cor_err_cnt),
4308[C_PCIC_POST_HD_Q_COR_ERR] = CNTR_ELEM("PcicPostHdQCorErr", 0, 0,
4309 CNTR_NORMAL,
4310 access_pcic_post_hd_q_cor_err_cnt),
4311[C_PCIC_RETRY_SOT_MEM_COR_ERR] = CNTR_ELEM("PcicRetrySotMemCorErr", 0, 0,
4312 CNTR_NORMAL,
4313 access_pcic_retry_sot_mem_cor_err_cnt),
4314[C_PCIC_RETRY_MEM_COR_ERR] = CNTR_ELEM("PcicRetryMemCorErr", 0, 0,
4315 CNTR_NORMAL,
4316 access_pcic_retry_mem_cor_err_cnt),
4317[C_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERR] = CNTR_ELEM(
4318 "CceCli1AsyncFifoDbgParityError", 0, 0,
4319 CNTR_NORMAL,
4320 access_cce_cli1_async_fifo_dbg_parity_err_cnt),
4321[C_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERR] = CNTR_ELEM(
4322 "CceCli1AsyncFifoRxdmaParityError", 0, 0,
4323 CNTR_NORMAL,
4324 access_cce_cli1_async_fifo_rxdma_parity_err_cnt
4325 ),
4326[C_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR] = CNTR_ELEM(
4327 "CceCli1AsyncFifoSdmaHdParityErr", 0, 0,
4328 CNTR_NORMAL,
4329 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt),
4330[C_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR] = CNTR_ELEM(
4331 "CceCli1AsyncFifoPioCrdtParityErr", 0, 0,
4332 CNTR_NORMAL,
4333 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt),
4334[C_CCE_CLI2_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceCli2AsyncFifoParityErr", 0,
4335 0, CNTR_NORMAL,
4336 access_cce_cli2_async_fifo_parity_err_cnt),
4337[C_CCE_CSR_CFG_BUS_PARITY_ERR] = CNTR_ELEM("CceCsrCfgBusParityErr", 0, 0,
4338 CNTR_NORMAL,
4339 access_cce_csr_cfg_bus_parity_err_cnt),
4340[C_CCE_CLI0_ASYNC_FIFO_PARTIY_ERR] = CNTR_ELEM("CceCli0AsyncFifoParityErr", 0,
4341 0, CNTR_NORMAL,
4342 access_cce_cli0_async_fifo_parity_err_cnt),
4343[C_CCE_RSPD_DATA_PARITY_ERR] = CNTR_ELEM("CceRspdDataParityErr", 0, 0,
4344 CNTR_NORMAL,
4345 access_cce_rspd_data_parity_err_cnt),
4346[C_CCE_TRGT_ACCESS_ERR] = CNTR_ELEM("CceTrgtAccessErr", 0, 0,
4347 CNTR_NORMAL,
4348 access_cce_trgt_access_err_cnt),
4349[C_CCE_TRGT_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceTrgtAsyncFifoParityErr", 0,
4350 0, CNTR_NORMAL,
4351 access_cce_trgt_async_fifo_parity_err_cnt),
4352[C_CCE_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrWriteBadAddrErr", 0, 0,
4353 CNTR_NORMAL,
4354 access_cce_csr_write_bad_addr_err_cnt),
4355[C_CCE_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrReadBadAddrErr", 0, 0,
4356 CNTR_NORMAL,
4357 access_cce_csr_read_bad_addr_err_cnt),
4358[C_CCE_CSR_PARITY_ERR] = CNTR_ELEM("CceCsrParityErr", 0, 0,
4359 CNTR_NORMAL,
4360 access_ccs_csr_parity_err_cnt),
4361
4362/* RcvErrStatus */
4363[C_RX_CSR_PARITY_ERR] = CNTR_ELEM("RxCsrParityErr", 0, 0,
4364 CNTR_NORMAL,
4365 access_rx_csr_parity_err_cnt),
4366[C_RX_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrWriteBadAddrErr", 0, 0,
4367 CNTR_NORMAL,
4368 access_rx_csr_write_bad_addr_err_cnt),
4369[C_RX_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrReadBadAddrErr", 0, 0,
4370 CNTR_NORMAL,
4371 access_rx_csr_read_bad_addr_err_cnt),
4372[C_RX_DMA_CSR_UNC_ERR] = CNTR_ELEM("RxDmaCsrUncErr", 0, 0,
4373 CNTR_NORMAL,
4374 access_rx_dma_csr_unc_err_cnt),
4375[C_RX_DMA_DQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaDqFsmEncodingErr", 0, 0,
4376 CNTR_NORMAL,
4377 access_rx_dma_dq_fsm_encoding_err_cnt),
4378[C_RX_DMA_EQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaEqFsmEncodingErr", 0, 0,
4379 CNTR_NORMAL,
4380 access_rx_dma_eq_fsm_encoding_err_cnt),
4381[C_RX_DMA_CSR_PARITY_ERR] = CNTR_ELEM("RxDmaCsrParityErr", 0, 0,
4382 CNTR_NORMAL,
4383 access_rx_dma_csr_parity_err_cnt),
4384[C_RX_RBUF_DATA_COR_ERR] = CNTR_ELEM("RxRbufDataCorErr", 0, 0,
4385 CNTR_NORMAL,
4386 access_rx_rbuf_data_cor_err_cnt),
4387[C_RX_RBUF_DATA_UNC_ERR] = CNTR_ELEM("RxRbufDataUncErr", 0, 0,
4388 CNTR_NORMAL,
4389 access_rx_rbuf_data_unc_err_cnt),
4390[C_RX_DMA_DATA_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaDataFifoRdCorErr", 0, 0,
4391 CNTR_NORMAL,
4392 access_rx_dma_data_fifo_rd_cor_err_cnt),
4393[C_RX_DMA_DATA_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaDataFifoRdUncErr", 0, 0,
4394 CNTR_NORMAL,
4395 access_rx_dma_data_fifo_rd_unc_err_cnt),
4396[C_RX_DMA_HDR_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaHdrFifoRdCorErr", 0, 0,
4397 CNTR_NORMAL,
4398 access_rx_dma_hdr_fifo_rd_cor_err_cnt),
4399[C_RX_DMA_HDR_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaHdrFifoRdUncErr", 0, 0,
4400 CNTR_NORMAL,
4401 access_rx_dma_hdr_fifo_rd_unc_err_cnt),
4402[C_RX_RBUF_DESC_PART2_COR_ERR] = CNTR_ELEM("RxRbufDescPart2CorErr", 0, 0,
4403 CNTR_NORMAL,
4404 access_rx_rbuf_desc_part2_cor_err_cnt),
4405[C_RX_RBUF_DESC_PART2_UNC_ERR] = CNTR_ELEM("RxRbufDescPart2UncErr", 0, 0,
4406 CNTR_NORMAL,
4407 access_rx_rbuf_desc_part2_unc_err_cnt),
4408[C_RX_RBUF_DESC_PART1_COR_ERR] = CNTR_ELEM("RxRbufDescPart1CorErr", 0, 0,
4409 CNTR_NORMAL,
4410 access_rx_rbuf_desc_part1_cor_err_cnt),
4411[C_RX_RBUF_DESC_PART1_UNC_ERR] = CNTR_ELEM("RxRbufDescPart1UncErr", 0, 0,
4412 CNTR_NORMAL,
4413 access_rx_rbuf_desc_part1_unc_err_cnt),
4414[C_RX_HQ_INTR_FSM_ERR] = CNTR_ELEM("RxHqIntrFsmErr", 0, 0,
4415 CNTR_NORMAL,
4416 access_rx_hq_intr_fsm_err_cnt),
4417[C_RX_HQ_INTR_CSR_PARITY_ERR] = CNTR_ELEM("RxHqIntrCsrParityErr", 0, 0,
4418 CNTR_NORMAL,
4419 access_rx_hq_intr_csr_parity_err_cnt),
4420[C_RX_LOOKUP_CSR_PARITY_ERR] = CNTR_ELEM("RxLookupCsrParityErr", 0, 0,
4421 CNTR_NORMAL,
4422 access_rx_lookup_csr_parity_err_cnt),
4423[C_RX_LOOKUP_RCV_ARRAY_COR_ERR] = CNTR_ELEM("RxLookupRcvArrayCorErr", 0, 0,
4424 CNTR_NORMAL,
4425 access_rx_lookup_rcv_array_cor_err_cnt),
4426[C_RX_LOOKUP_RCV_ARRAY_UNC_ERR] = CNTR_ELEM("RxLookupRcvArrayUncErr", 0, 0,
4427 CNTR_NORMAL,
4428 access_rx_lookup_rcv_array_unc_err_cnt),
4429[C_RX_LOOKUP_DES_PART2_PARITY_ERR] = CNTR_ELEM("RxLookupDesPart2ParityErr", 0,
4430 0, CNTR_NORMAL,
4431 access_rx_lookup_des_part2_parity_err_cnt),
4432[C_RX_LOOKUP_DES_PART1_UNC_COR_ERR] = CNTR_ELEM("RxLookupDesPart1UncCorErr", 0,
4433 0, CNTR_NORMAL,
4434 access_rx_lookup_des_part1_unc_cor_err_cnt),
4435[C_RX_LOOKUP_DES_PART1_UNC_ERR] = CNTR_ELEM("RxLookupDesPart1UncErr", 0, 0,
4436 CNTR_NORMAL,
4437 access_rx_lookup_des_part1_unc_err_cnt),
4438[C_RX_RBUF_NEXT_FREE_BUF_COR_ERR] = CNTR_ELEM("RxRbufNextFreeBufCorErr", 0, 0,
4439 CNTR_NORMAL,
4440 access_rx_rbuf_next_free_buf_cor_err_cnt),
4441[C_RX_RBUF_NEXT_FREE_BUF_UNC_ERR] = CNTR_ELEM("RxRbufNextFreeBufUncErr", 0, 0,
4442 CNTR_NORMAL,
4443 access_rx_rbuf_next_free_buf_unc_err_cnt),
4444[C_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR] = CNTR_ELEM(
4445 "RxRbufFlInitWrAddrParityErr", 0, 0,
4446 CNTR_NORMAL,
4447 access_rbuf_fl_init_wr_addr_parity_err_cnt),
4448[C_RX_RBUF_FL_INITDONE_PARITY_ERR] = CNTR_ELEM("RxRbufFlInitdoneParityErr", 0,
4449 0, CNTR_NORMAL,
4450 access_rx_rbuf_fl_initdone_parity_err_cnt),
4451[C_RX_RBUF_FL_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlWrAddrParityErr", 0,
4452 0, CNTR_NORMAL,
4453 access_rx_rbuf_fl_write_addr_parity_err_cnt),
4454[C_RX_RBUF_FL_RD_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlRdAddrParityErr", 0, 0,
4455 CNTR_NORMAL,
4456 access_rx_rbuf_fl_rd_addr_parity_err_cnt),
4457[C_RX_RBUF_EMPTY_ERR] = CNTR_ELEM("RxRbufEmptyErr", 0, 0,
4458 CNTR_NORMAL,
4459 access_rx_rbuf_empty_err_cnt),
4460[C_RX_RBUF_FULL_ERR] = CNTR_ELEM("RxRbufFullErr", 0, 0,
4461 CNTR_NORMAL,
4462 access_rx_rbuf_full_err_cnt),
4463[C_RX_RBUF_BAD_LOOKUP_ERR] = CNTR_ELEM("RxRBufBadLookupErr", 0, 0,
4464 CNTR_NORMAL,
4465 access_rbuf_bad_lookup_err_cnt),
4466[C_RX_RBUF_CTX_ID_PARITY_ERR] = CNTR_ELEM("RxRbufCtxIdParityErr", 0, 0,
4467 CNTR_NORMAL,
4468 access_rbuf_ctx_id_parity_err_cnt),
4469[C_RX_RBUF_CSR_QEOPDW_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEOPDWParityErr", 0, 0,
4470 CNTR_NORMAL,
4471 access_rbuf_csr_qeopdw_parity_err_cnt),
4472[C_RX_RBUF_CSR_Q_NUM_OF_PKT_PARITY_ERR] = CNTR_ELEM(
4473 "RxRbufCsrQNumOfPktParityErr", 0, 0,
4474 CNTR_NORMAL,
4475 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt),
4476[C_RX_RBUF_CSR_Q_T1_PTR_PARITY_ERR] = CNTR_ELEM(
4477 "RxRbufCsrQTlPtrParityErr", 0, 0,
4478 CNTR_NORMAL,
4479 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt),
4480[C_RX_RBUF_CSR_Q_HD_PTR_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQHdPtrParityErr", 0,
4481 0, CNTR_NORMAL,
4482 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt),
4483[C_RX_RBUF_CSR_Q_VLD_BIT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQVldBitParityErr", 0,
4484 0, CNTR_NORMAL,
4485 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt),
4486[C_RX_RBUF_CSR_Q_NEXT_BUF_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQNextBufParityErr",
4487 0, 0, CNTR_NORMAL,
4488 access_rx_rbuf_csr_q_next_buf_parity_err_cnt),
4489[C_RX_RBUF_CSR_Q_ENT_CNT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEntCntParityErr", 0,
4490 0, CNTR_NORMAL,
4491 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt),
4492[C_RX_RBUF_CSR_Q_HEAD_BUF_NUM_PARITY_ERR] = CNTR_ELEM(
4493 "RxRbufCsrQHeadBufNumParityErr", 0, 0,
4494 CNTR_NORMAL,
4495 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt),
4496[C_RX_RBUF_BLOCK_LIST_READ_COR_ERR] = CNTR_ELEM("RxRbufBlockListReadCorErr", 0,
4497 0, CNTR_NORMAL,
4498 access_rx_rbuf_block_list_read_cor_err_cnt),
4499[C_RX_RBUF_BLOCK_LIST_READ_UNC_ERR] = CNTR_ELEM("RxRbufBlockListReadUncErr", 0,
4500 0, CNTR_NORMAL,
4501 access_rx_rbuf_block_list_read_unc_err_cnt),
4502[C_RX_RBUF_LOOKUP_DES_COR_ERR] = CNTR_ELEM("RxRbufLookupDesCorErr", 0, 0,
4503 CNTR_NORMAL,
4504 access_rx_rbuf_lookup_des_cor_err_cnt),
4505[C_RX_RBUF_LOOKUP_DES_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesUncErr", 0, 0,
4506 CNTR_NORMAL,
4507 access_rx_rbuf_lookup_des_unc_err_cnt),
4508[C_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR] = CNTR_ELEM(
4509 "RxRbufLookupDesRegUncCorErr", 0, 0,
4510 CNTR_NORMAL,
4511 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt),
4512[C_RX_RBUF_LOOKUP_DES_REG_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesRegUncErr", 0, 0,
4513 CNTR_NORMAL,
4514 access_rx_rbuf_lookup_des_reg_unc_err_cnt),
4515[C_RX_RBUF_FREE_LIST_COR_ERR] = CNTR_ELEM("RxRbufFreeListCorErr", 0, 0,
4516 CNTR_NORMAL,
4517 access_rx_rbuf_free_list_cor_err_cnt),
4518[C_RX_RBUF_FREE_LIST_UNC_ERR] = CNTR_ELEM("RxRbufFreeListUncErr", 0, 0,
4519 CNTR_NORMAL,
4520 access_rx_rbuf_free_list_unc_err_cnt),
4521[C_RX_RCV_FSM_ENCODING_ERR] = CNTR_ELEM("RxRcvFsmEncodingErr", 0, 0,
4522 CNTR_NORMAL,
4523 access_rx_rcv_fsm_encoding_err_cnt),
4524[C_RX_DMA_FLAG_COR_ERR] = CNTR_ELEM("RxDmaFlagCorErr", 0, 0,
4525 CNTR_NORMAL,
4526 access_rx_dma_flag_cor_err_cnt),
4527[C_RX_DMA_FLAG_UNC_ERR] = CNTR_ELEM("RxDmaFlagUncErr", 0, 0,
4528 CNTR_NORMAL,
4529 access_rx_dma_flag_unc_err_cnt),
4530[C_RX_DC_SOP_EOP_PARITY_ERR] = CNTR_ELEM("RxDcSopEopParityErr", 0, 0,
4531 CNTR_NORMAL,
4532 access_rx_dc_sop_eop_parity_err_cnt),
4533[C_RX_RCV_CSR_PARITY_ERR] = CNTR_ELEM("RxRcvCsrParityErr", 0, 0,
4534 CNTR_NORMAL,
4535 access_rx_rcv_csr_parity_err_cnt),
4536[C_RX_RCV_QP_MAP_TABLE_COR_ERR] = CNTR_ELEM("RxRcvQpMapTableCorErr", 0, 0,
4537 CNTR_NORMAL,
4538 access_rx_rcv_qp_map_table_cor_err_cnt),
4539[C_RX_RCV_QP_MAP_TABLE_UNC_ERR] = CNTR_ELEM("RxRcvQpMapTableUncErr", 0, 0,
4540 CNTR_NORMAL,
4541 access_rx_rcv_qp_map_table_unc_err_cnt),
4542[C_RX_RCV_DATA_COR_ERR] = CNTR_ELEM("RxRcvDataCorErr", 0, 0,
4543 CNTR_NORMAL,
4544 access_rx_rcv_data_cor_err_cnt),
4545[C_RX_RCV_DATA_UNC_ERR] = CNTR_ELEM("RxRcvDataUncErr", 0, 0,
4546 CNTR_NORMAL,
4547 access_rx_rcv_data_unc_err_cnt),
4548[C_RX_RCV_HDR_COR_ERR] = CNTR_ELEM("RxRcvHdrCorErr", 0, 0,
4549 CNTR_NORMAL,
4550 access_rx_rcv_hdr_cor_err_cnt),
4551[C_RX_RCV_HDR_UNC_ERR] = CNTR_ELEM("RxRcvHdrUncErr", 0, 0,
4552 CNTR_NORMAL,
4553 access_rx_rcv_hdr_unc_err_cnt),
4554[C_RX_DC_INTF_PARITY_ERR] = CNTR_ELEM("RxDcIntfParityErr", 0, 0,
4555 CNTR_NORMAL,
4556 access_rx_dc_intf_parity_err_cnt),
4557[C_RX_DMA_CSR_COR_ERR] = CNTR_ELEM("RxDmaCsrCorErr", 0, 0,
4558 CNTR_NORMAL,
4559 access_rx_dma_csr_cor_err_cnt),
4560/* SendPioErrStatus */
4561[C_PIO_PEC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPecSopHeadParityErr", 0, 0,
4562 CNTR_NORMAL,
4563 access_pio_pec_sop_head_parity_err_cnt),
4564[C_PIO_PCC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPccSopHeadParityErr", 0, 0,
4565 CNTR_NORMAL,
4566 access_pio_pcc_sop_head_parity_err_cnt),
4567[C_PIO_LAST_RETURNED_CNT_PARITY_ERR] = CNTR_ELEM("PioLastReturnedCntParityErr",
4568 0, 0, CNTR_NORMAL,
4569 access_pio_last_returned_cnt_parity_err_cnt),
4570[C_PIO_CURRENT_FREE_CNT_PARITY_ERR] = CNTR_ELEM("PioCurrentFreeCntParityErr", 0,
4571 0, CNTR_NORMAL,
4572 access_pio_current_free_cnt_parity_err_cnt),
4573[C_PIO_RSVD_31_ERR] = CNTR_ELEM("Pio Reserved 31", 0, 0,
4574 CNTR_NORMAL,
4575 access_pio_reserved_31_err_cnt),
4576[C_PIO_RSVD_30_ERR] = CNTR_ELEM("Pio Reserved 30", 0, 0,
4577 CNTR_NORMAL,
4578 access_pio_reserved_30_err_cnt),
4579[C_PIO_PPMC_SOP_LEN_ERR] = CNTR_ELEM("PioPpmcSopLenErr", 0, 0,
4580 CNTR_NORMAL,
4581 access_pio_ppmc_sop_len_err_cnt),
4582[C_PIO_PPMC_BQC_MEM_PARITY_ERR] = CNTR_ELEM("PioPpmcBqcMemParityErr", 0, 0,
4583 CNTR_NORMAL,
4584 access_pio_ppmc_bqc_mem_parity_err_cnt),
4585[C_PIO_VL_FIFO_PARITY_ERR] = CNTR_ELEM("PioVlFifoParityErr", 0, 0,
4586 CNTR_NORMAL,
4587 access_pio_vl_fifo_parity_err_cnt),
4588[C_PIO_VLF_SOP_PARITY_ERR] = CNTR_ELEM("PioVlfSopParityErr", 0, 0,
4589 CNTR_NORMAL,
4590 access_pio_vlf_sop_parity_err_cnt),
4591[C_PIO_VLF_V1_LEN_PARITY_ERR] = CNTR_ELEM("PioVlfVlLenParityErr", 0, 0,
4592 CNTR_NORMAL,
4593 access_pio_vlf_v1_len_parity_err_cnt),
4594[C_PIO_BLOCK_QW_COUNT_PARITY_ERR] = CNTR_ELEM("PioBlockQwCountParityErr", 0, 0,
4595 CNTR_NORMAL,
4596 access_pio_block_qw_count_parity_err_cnt),
4597[C_PIO_WRITE_QW_VALID_PARITY_ERR] = CNTR_ELEM("PioWriteQwValidParityErr", 0, 0,
4598 CNTR_NORMAL,
4599 access_pio_write_qw_valid_parity_err_cnt),
4600[C_PIO_STATE_MACHINE_ERR] = CNTR_ELEM("PioStateMachineErr", 0, 0,
4601 CNTR_NORMAL,
4602 access_pio_state_machine_err_cnt),
4603[C_PIO_WRITE_DATA_PARITY_ERR] = CNTR_ELEM("PioWriteDataParityErr", 0, 0,
4604 CNTR_NORMAL,
4605 access_pio_write_data_parity_err_cnt),
4606[C_PIO_HOST_ADDR_MEM_COR_ERR] = CNTR_ELEM("PioHostAddrMemCorErr", 0, 0,
4607 CNTR_NORMAL,
4608 access_pio_host_addr_mem_cor_err_cnt),
4609[C_PIO_HOST_ADDR_MEM_UNC_ERR] = CNTR_ELEM("PioHostAddrMemUncErr", 0, 0,
4610 CNTR_NORMAL,
4611 access_pio_host_addr_mem_unc_err_cnt),
4612[C_PIO_PKT_EVICT_SM_OR_ARM_SM_ERR] = CNTR_ELEM("PioPktEvictSmOrArbSmErr", 0, 0,
4613 CNTR_NORMAL,
4614 access_pio_pkt_evict_sm_or_arb_sm_err_cnt),
4615[C_PIO_INIT_SM_IN_ERR] = CNTR_ELEM("PioInitSmInErr", 0, 0,
4616 CNTR_NORMAL,
4617 access_pio_init_sm_in_err_cnt),
4618[C_PIO_PPMC_PBL_FIFO_ERR] = CNTR_ELEM("PioPpmcPblFifoErr", 0, 0,
4619 CNTR_NORMAL,
4620 access_pio_ppmc_pbl_fifo_err_cnt),
4621[C_PIO_CREDIT_RET_FIFO_PARITY_ERR] = CNTR_ELEM("PioCreditRetFifoParityErr", 0,
4622 0, CNTR_NORMAL,
4623 access_pio_credit_ret_fifo_parity_err_cnt),
4624[C_PIO_V1_LEN_MEM_BANK1_COR_ERR] = CNTR_ELEM("PioVlLenMemBank1CorErr", 0, 0,
4625 CNTR_NORMAL,
4626 access_pio_v1_len_mem_bank1_cor_err_cnt),
4627[C_PIO_V1_LEN_MEM_BANK0_COR_ERR] = CNTR_ELEM("PioVlLenMemBank0CorErr", 0, 0,
4628 CNTR_NORMAL,
4629 access_pio_v1_len_mem_bank0_cor_err_cnt),
4630[C_PIO_V1_LEN_MEM_BANK1_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank1UncErr", 0, 0,
4631 CNTR_NORMAL,
4632 access_pio_v1_len_mem_bank1_unc_err_cnt),
4633[C_PIO_V1_LEN_MEM_BANK0_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank0UncErr", 0, 0,
4634 CNTR_NORMAL,
4635 access_pio_v1_len_mem_bank0_unc_err_cnt),
4636[C_PIO_SM_PKT_RESET_PARITY_ERR] = CNTR_ELEM("PioSmPktResetParityErr", 0, 0,
4637 CNTR_NORMAL,
4638 access_pio_sm_pkt_reset_parity_err_cnt),
4639[C_PIO_PKT_EVICT_FIFO_PARITY_ERR] = CNTR_ELEM("PioPktEvictFifoParityErr", 0, 0,
4640 CNTR_NORMAL,
4641 access_pio_pkt_evict_fifo_parity_err_cnt),
4642[C_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR] = CNTR_ELEM(
4643 "PioSbrdctrlCrrelFifoParityErr", 0, 0,
4644 CNTR_NORMAL,
4645 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt),
4646[C_PIO_SBRDCTL_CRREL_PARITY_ERR] = CNTR_ELEM("PioSbrdctlCrrelParityErr", 0, 0,
4647 CNTR_NORMAL,
4648 access_pio_sbrdctl_crrel_parity_err_cnt),
4649[C_PIO_PEC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPecFifoParityErr", 0, 0,
4650 CNTR_NORMAL,
4651 access_pio_pec_fifo_parity_err_cnt),
4652[C_PIO_PCC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPccFifoParityErr", 0, 0,
4653 CNTR_NORMAL,
4654 access_pio_pcc_fifo_parity_err_cnt),
4655[C_PIO_SB_MEM_FIFO1_ERR] = CNTR_ELEM("PioSbMemFifo1Err", 0, 0,
4656 CNTR_NORMAL,
4657 access_pio_sb_mem_fifo1_err_cnt),
4658[C_PIO_SB_MEM_FIFO0_ERR] = CNTR_ELEM("PioSbMemFifo0Err", 0, 0,
4659 CNTR_NORMAL,
4660 access_pio_sb_mem_fifo0_err_cnt),
4661[C_PIO_CSR_PARITY_ERR] = CNTR_ELEM("PioCsrParityErr", 0, 0,
4662 CNTR_NORMAL,
4663 access_pio_csr_parity_err_cnt),
4664[C_PIO_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("PioWriteAddrParityErr", 0, 0,
4665 CNTR_NORMAL,
4666 access_pio_write_addr_parity_err_cnt),
4667[C_PIO_WRITE_BAD_CTXT_ERR] = CNTR_ELEM("PioWriteBadCtxtErr", 0, 0,
4668 CNTR_NORMAL,
4669 access_pio_write_bad_ctxt_err_cnt),
4670/* SendDmaErrStatus */
4671[C_SDMA_PCIE_REQ_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPcieReqTrackingCorErr", 0,
4672 0, CNTR_NORMAL,
4673 access_sdma_pcie_req_tracking_cor_err_cnt),
4674[C_SDMA_PCIE_REQ_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPcieReqTrackingUncErr", 0,
4675 0, CNTR_NORMAL,
4676 access_sdma_pcie_req_tracking_unc_err_cnt),
4677[C_SDMA_CSR_PARITY_ERR] = CNTR_ELEM("SDmaCsrParityErr", 0, 0,
4678 CNTR_NORMAL,
4679 access_sdma_csr_parity_err_cnt),
4680[C_SDMA_RPY_TAG_ERR] = CNTR_ELEM("SDmaRpyTagErr", 0, 0,
4681 CNTR_NORMAL,
4682 access_sdma_rpy_tag_err_cnt),
4683/* SendEgressErrStatus */
4684[C_TX_READ_PIO_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryCsrUncErr", 0, 0,
4685 CNTR_NORMAL,
4686 access_tx_read_pio_memory_csr_unc_err_cnt),
4687[C_TX_READ_SDMA_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryCsrUncErr", 0,
4688 0, CNTR_NORMAL,
4689 access_tx_read_sdma_memory_csr_err_cnt),
4690[C_TX_EGRESS_FIFO_COR_ERR] = CNTR_ELEM("TxEgressFifoCorErr", 0, 0,
4691 CNTR_NORMAL,
4692 access_tx_egress_fifo_cor_err_cnt),
4693[C_TX_READ_PIO_MEMORY_COR_ERR] = CNTR_ELEM("TxReadPioMemoryCorErr", 0, 0,
4694 CNTR_NORMAL,
4695 access_tx_read_pio_memory_cor_err_cnt),
4696[C_TX_READ_SDMA_MEMORY_COR_ERR] = CNTR_ELEM("TxReadSdmaMemoryCorErr", 0, 0,
4697 CNTR_NORMAL,
4698 access_tx_read_sdma_memory_cor_err_cnt),
4699[C_TX_SB_HDR_COR_ERR] = CNTR_ELEM("TxSbHdrCorErr", 0, 0,
4700 CNTR_NORMAL,
4701 access_tx_sb_hdr_cor_err_cnt),
4702[C_TX_CREDIT_OVERRUN_ERR] = CNTR_ELEM("TxCreditOverrunErr", 0, 0,
4703 CNTR_NORMAL,
4704 access_tx_credit_overrun_err_cnt),
4705[C_TX_LAUNCH_FIFO8_COR_ERR] = CNTR_ELEM("TxLaunchFifo8CorErr", 0, 0,
4706 CNTR_NORMAL,
4707 access_tx_launch_fifo8_cor_err_cnt),
4708[C_TX_LAUNCH_FIFO7_COR_ERR] = CNTR_ELEM("TxLaunchFifo7CorErr", 0, 0,
4709 CNTR_NORMAL,
4710 access_tx_launch_fifo7_cor_err_cnt),
4711[C_TX_LAUNCH_FIFO6_COR_ERR] = CNTR_ELEM("TxLaunchFifo6CorErr", 0, 0,
4712 CNTR_NORMAL,
4713 access_tx_launch_fifo6_cor_err_cnt),
4714[C_TX_LAUNCH_FIFO5_COR_ERR] = CNTR_ELEM("TxLaunchFifo5CorErr", 0, 0,
4715 CNTR_NORMAL,
4716 access_tx_launch_fifo5_cor_err_cnt),
4717[C_TX_LAUNCH_FIFO4_COR_ERR] = CNTR_ELEM("TxLaunchFifo4CorErr", 0, 0,
4718 CNTR_NORMAL,
4719 access_tx_launch_fifo4_cor_err_cnt),
4720[C_TX_LAUNCH_FIFO3_COR_ERR] = CNTR_ELEM("TxLaunchFifo3CorErr", 0, 0,
4721 CNTR_NORMAL,
4722 access_tx_launch_fifo3_cor_err_cnt),
4723[C_TX_LAUNCH_FIFO2_COR_ERR] = CNTR_ELEM("TxLaunchFifo2CorErr", 0, 0,
4724 CNTR_NORMAL,
4725 access_tx_launch_fifo2_cor_err_cnt),
4726[C_TX_LAUNCH_FIFO1_COR_ERR] = CNTR_ELEM("TxLaunchFifo1CorErr", 0, 0,
4727 CNTR_NORMAL,
4728 access_tx_launch_fifo1_cor_err_cnt),
4729[C_TX_LAUNCH_FIFO0_COR_ERR] = CNTR_ELEM("TxLaunchFifo0CorErr", 0, 0,
4730 CNTR_NORMAL,
4731 access_tx_launch_fifo0_cor_err_cnt),
4732[C_TX_CREDIT_RETURN_VL_ERR] = CNTR_ELEM("TxCreditReturnVLErr", 0, 0,
4733 CNTR_NORMAL,
4734 access_tx_credit_return_vl_err_cnt),
4735[C_TX_HCRC_INSERTION_ERR] = CNTR_ELEM("TxHcrcInsertionErr", 0, 0,
4736 CNTR_NORMAL,
4737 access_tx_hcrc_insertion_err_cnt),
4738[C_TX_EGRESS_FIFI_UNC_ERR] = CNTR_ELEM("TxEgressFifoUncErr", 0, 0,
4739 CNTR_NORMAL,
4740 access_tx_egress_fifo_unc_err_cnt),
4741[C_TX_READ_PIO_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryUncErr", 0, 0,
4742 CNTR_NORMAL,
4743 access_tx_read_pio_memory_unc_err_cnt),
4744[C_TX_READ_SDMA_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryUncErr", 0, 0,
4745 CNTR_NORMAL,
4746 access_tx_read_sdma_memory_unc_err_cnt),
4747[C_TX_SB_HDR_UNC_ERR] = CNTR_ELEM("TxSbHdrUncErr", 0, 0,
4748 CNTR_NORMAL,
4749 access_tx_sb_hdr_unc_err_cnt),
4750[C_TX_CREDIT_RETURN_PARITY_ERR] = CNTR_ELEM("TxCreditReturnParityErr", 0, 0,
4751 CNTR_NORMAL,
4752 access_tx_credit_return_partiy_err_cnt),
4753[C_TX_LAUNCH_FIFO8_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo8UncOrParityErr",
4754 0, 0, CNTR_NORMAL,
4755 access_tx_launch_fifo8_unc_or_parity_err_cnt),
4756[C_TX_LAUNCH_FIFO7_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo7UncOrParityErr",
4757 0, 0, CNTR_NORMAL,
4758 access_tx_launch_fifo7_unc_or_parity_err_cnt),
4759[C_TX_LAUNCH_FIFO6_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo6UncOrParityErr",
4760 0, 0, CNTR_NORMAL,
4761 access_tx_launch_fifo6_unc_or_parity_err_cnt),
4762[C_TX_LAUNCH_FIFO5_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo5UncOrParityErr",
4763 0, 0, CNTR_NORMAL,
4764 access_tx_launch_fifo5_unc_or_parity_err_cnt),
4765[C_TX_LAUNCH_FIFO4_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo4UncOrParityErr",
4766 0, 0, CNTR_NORMAL,
4767 access_tx_launch_fifo4_unc_or_parity_err_cnt),
4768[C_TX_LAUNCH_FIFO3_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo3UncOrParityErr",
4769 0, 0, CNTR_NORMAL,
4770 access_tx_launch_fifo3_unc_or_parity_err_cnt),
4771[C_TX_LAUNCH_FIFO2_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo2UncOrParityErr",
4772 0, 0, CNTR_NORMAL,
4773 access_tx_launch_fifo2_unc_or_parity_err_cnt),
4774[C_TX_LAUNCH_FIFO1_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo1UncOrParityErr",
4775 0, 0, CNTR_NORMAL,
4776 access_tx_launch_fifo1_unc_or_parity_err_cnt),
4777[C_TX_LAUNCH_FIFO0_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo0UncOrParityErr",
4778 0, 0, CNTR_NORMAL,
4779 access_tx_launch_fifo0_unc_or_parity_err_cnt),
4780[C_TX_SDMA15_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma15DisallowedPacketErr",
4781 0, 0, CNTR_NORMAL,
4782 access_tx_sdma15_disallowed_packet_err_cnt),
4783[C_TX_SDMA14_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma14DisallowedPacketErr",
4784 0, 0, CNTR_NORMAL,
4785 access_tx_sdma14_disallowed_packet_err_cnt),
4786[C_TX_SDMA13_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma13DisallowedPacketErr",
4787 0, 0, CNTR_NORMAL,
4788 access_tx_sdma13_disallowed_packet_err_cnt),
4789[C_TX_SDMA12_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma12DisallowedPacketErr",
4790 0, 0, CNTR_NORMAL,
4791 access_tx_sdma12_disallowed_packet_err_cnt),
4792[C_TX_SDMA11_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma11DisallowedPacketErr",
4793 0, 0, CNTR_NORMAL,
4794 access_tx_sdma11_disallowed_packet_err_cnt),
4795[C_TX_SDMA10_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma10DisallowedPacketErr",
4796 0, 0, CNTR_NORMAL,
4797 access_tx_sdma10_disallowed_packet_err_cnt),
4798[C_TX_SDMA9_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma9DisallowedPacketErr",
4799 0, 0, CNTR_NORMAL,
4800 access_tx_sdma9_disallowed_packet_err_cnt),
4801[C_TX_SDMA8_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma8DisallowedPacketErr",
4802 0, 0, CNTR_NORMAL,
4803 access_tx_sdma8_disallowed_packet_err_cnt),
4804[C_TX_SDMA7_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma7DisallowedPacketErr",
4805 0, 0, CNTR_NORMAL,
4806 access_tx_sdma7_disallowed_packet_err_cnt),
4807[C_TX_SDMA6_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma6DisallowedPacketErr",
4808 0, 0, CNTR_NORMAL,
4809 access_tx_sdma6_disallowed_packet_err_cnt),
4810[C_TX_SDMA5_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma5DisallowedPacketErr",
4811 0, 0, CNTR_NORMAL,
4812 access_tx_sdma5_disallowed_packet_err_cnt),
4813[C_TX_SDMA4_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma4DisallowedPacketErr",
4814 0, 0, CNTR_NORMAL,
4815 access_tx_sdma4_disallowed_packet_err_cnt),
4816[C_TX_SDMA3_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma3DisallowedPacketErr",
4817 0, 0, CNTR_NORMAL,
4818 access_tx_sdma3_disallowed_packet_err_cnt),
4819[C_TX_SDMA2_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma2DisallowedPacketErr",
4820 0, 0, CNTR_NORMAL,
4821 access_tx_sdma2_disallowed_packet_err_cnt),
4822[C_TX_SDMA1_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma1DisallowedPacketErr",
4823 0, 0, CNTR_NORMAL,
4824 access_tx_sdma1_disallowed_packet_err_cnt),
4825[C_TX_SDMA0_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma0DisallowedPacketErr",
4826 0, 0, CNTR_NORMAL,
4827 access_tx_sdma0_disallowed_packet_err_cnt),
4828[C_TX_CONFIG_PARITY_ERR] = CNTR_ELEM("TxConfigParityErr", 0, 0,
4829 CNTR_NORMAL,
4830 access_tx_config_parity_err_cnt),
4831[C_TX_SBRD_CTL_CSR_PARITY_ERR] = CNTR_ELEM("TxSbrdCtlCsrParityErr", 0, 0,
4832 CNTR_NORMAL,
4833 access_tx_sbrd_ctl_csr_parity_err_cnt),
4834[C_TX_LAUNCH_CSR_PARITY_ERR] = CNTR_ELEM("TxLaunchCsrParityErr", 0, 0,
4835 CNTR_NORMAL,
4836 access_tx_launch_csr_parity_err_cnt),
4837[C_TX_ILLEGAL_CL_ERR] = CNTR_ELEM("TxIllegalVLErr", 0, 0,
4838 CNTR_NORMAL,
4839 access_tx_illegal_vl_err_cnt),
4840[C_TX_SBRD_CTL_STATE_MACHINE_PARITY_ERR] = CNTR_ELEM(
4841 "TxSbrdCtlStateMachineParityErr", 0, 0,
4842 CNTR_NORMAL,
4843 access_tx_sbrd_ctl_state_machine_parity_err_cnt),
4844[C_TX_RESERVED_10] = CNTR_ELEM("Tx Egress Reserved 10", 0, 0,
4845 CNTR_NORMAL,
4846 access_egress_reserved_10_err_cnt),
4847[C_TX_RESERVED_9] = CNTR_ELEM("Tx Egress Reserved 9", 0, 0,
4848 CNTR_NORMAL,
4849 access_egress_reserved_9_err_cnt),
4850[C_TX_SDMA_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxSdmaLaunchIntfParityErr",
4851 0, 0, CNTR_NORMAL,
4852 access_tx_sdma_launch_intf_parity_err_cnt),
4853[C_TX_PIO_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxPioLaunchIntfParityErr", 0, 0,
4854 CNTR_NORMAL,
4855 access_tx_pio_launch_intf_parity_err_cnt),
4856[C_TX_RESERVED_6] = CNTR_ELEM("Tx Egress Reserved 6", 0, 0,
4857 CNTR_NORMAL,
4858 access_egress_reserved_6_err_cnt),
4859[C_TX_INCORRECT_LINK_STATE_ERR] = CNTR_ELEM("TxIncorrectLinkStateErr", 0, 0,
4860 CNTR_NORMAL,
4861 access_tx_incorrect_link_state_err_cnt),
4862[C_TX_LINK_DOWN_ERR] = CNTR_ELEM("TxLinkdownErr", 0, 0,
4863 CNTR_NORMAL,
4864 access_tx_linkdown_err_cnt),
4865[C_TX_EGRESS_FIFO_UNDERRUN_OR_PARITY_ERR] = CNTR_ELEM(
4866 "EgressFifoUnderrunOrParityErr", 0, 0,
4867 CNTR_NORMAL,
4868 access_tx_egress_fifi_underrun_or_parity_err_cnt),
4869[C_TX_RESERVED_2] = CNTR_ELEM("Tx Egress Reserved 2", 0, 0,
4870 CNTR_NORMAL,
4871 access_egress_reserved_2_err_cnt),
4872[C_TX_PKT_INTEGRITY_MEM_UNC_ERR] = CNTR_ELEM("TxPktIntegrityMemUncErr", 0, 0,
4873 CNTR_NORMAL,
4874 access_tx_pkt_integrity_mem_unc_err_cnt),
4875[C_TX_PKT_INTEGRITY_MEM_COR_ERR] = CNTR_ELEM("TxPktIntegrityMemCorErr", 0, 0,
4876 CNTR_NORMAL,
4877 access_tx_pkt_integrity_mem_cor_err_cnt),
4878/* SendErrStatus */
4879[C_SEND_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("SendCsrWriteBadAddrErr", 0, 0,
4880 CNTR_NORMAL,
4881 access_send_csr_write_bad_addr_err_cnt),
4882[C_SEND_CSR_READ_BAD_ADD_ERR] = CNTR_ELEM("SendCsrReadBadAddrErr", 0, 0,
4883 CNTR_NORMAL,
4884 access_send_csr_read_bad_addr_err_cnt),
4885[C_SEND_CSR_PARITY_ERR] = CNTR_ELEM("SendCsrParityErr", 0, 0,
4886 CNTR_NORMAL,
4887 access_send_csr_parity_cnt),
4888/* SendCtxtErrStatus */
4889[C_PIO_WRITE_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("PioWriteOutOfBoundsErr", 0, 0,
4890 CNTR_NORMAL,
4891 access_pio_write_out_of_bounds_err_cnt),
4892[C_PIO_WRITE_OVERFLOW_ERR] = CNTR_ELEM("PioWriteOverflowErr", 0, 0,
4893 CNTR_NORMAL,
4894 access_pio_write_overflow_err_cnt),
4895[C_PIO_WRITE_CROSSES_BOUNDARY_ERR] = CNTR_ELEM("PioWriteCrossesBoundaryErr",
4896 0, 0, CNTR_NORMAL,
4897 access_pio_write_crosses_boundary_err_cnt),
4898[C_PIO_DISALLOWED_PACKET_ERR] = CNTR_ELEM("PioDisallowedPacketErr", 0, 0,
4899 CNTR_NORMAL,
4900 access_pio_disallowed_packet_err_cnt),
4901[C_PIO_INCONSISTENT_SOP_ERR] = CNTR_ELEM("PioInconsistentSopErr", 0, 0,
4902 CNTR_NORMAL,
4903 access_pio_inconsistent_sop_err_cnt),
4904/* SendDmaEngErrStatus */
4905[C_SDMA_HEADER_REQUEST_FIFO_COR_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoCorErr",
4906 0, 0, CNTR_NORMAL,
4907 access_sdma_header_request_fifo_cor_err_cnt),
4908[C_SDMA_HEADER_STORAGE_COR_ERR] = CNTR_ELEM("SDmaHeaderStorageCorErr", 0, 0,
4909 CNTR_NORMAL,
4910 access_sdma_header_storage_cor_err_cnt),
4911[C_SDMA_PACKET_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPacketTrackingCorErr", 0, 0,
4912 CNTR_NORMAL,
4913 access_sdma_packet_tracking_cor_err_cnt),
4914[C_SDMA_ASSEMBLY_COR_ERR] = CNTR_ELEM("SDmaAssemblyCorErr", 0, 0,
4915 CNTR_NORMAL,
4916 access_sdma_assembly_cor_err_cnt),
4917[C_SDMA_DESC_TABLE_COR_ERR] = CNTR_ELEM("SDmaDescTableCorErr", 0, 0,
4918 CNTR_NORMAL,
4919 access_sdma_desc_table_cor_err_cnt),
4920[C_SDMA_HEADER_REQUEST_FIFO_UNC_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoUncErr",
4921 0, 0, CNTR_NORMAL,
4922 access_sdma_header_request_fifo_unc_err_cnt),
4923[C_SDMA_HEADER_STORAGE_UNC_ERR] = CNTR_ELEM("SDmaHeaderStorageUncErr", 0, 0,
4924 CNTR_NORMAL,
4925 access_sdma_header_storage_unc_err_cnt),
4926[C_SDMA_PACKET_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPacketTrackingUncErr", 0, 0,
4927 CNTR_NORMAL,
4928 access_sdma_packet_tracking_unc_err_cnt),
4929[C_SDMA_ASSEMBLY_UNC_ERR] = CNTR_ELEM("SDmaAssemblyUncErr", 0, 0,
4930 CNTR_NORMAL,
4931 access_sdma_assembly_unc_err_cnt),
4932[C_SDMA_DESC_TABLE_UNC_ERR] = CNTR_ELEM("SDmaDescTableUncErr", 0, 0,
4933 CNTR_NORMAL,
4934 access_sdma_desc_table_unc_err_cnt),
4935[C_SDMA_TIMEOUT_ERR] = CNTR_ELEM("SDmaTimeoutErr", 0, 0,
4936 CNTR_NORMAL,
4937 access_sdma_timeout_err_cnt),
4938[C_SDMA_HEADER_LENGTH_ERR] = CNTR_ELEM("SDmaHeaderLengthErr", 0, 0,
4939 CNTR_NORMAL,
4940 access_sdma_header_length_err_cnt),
4941[C_SDMA_HEADER_ADDRESS_ERR] = CNTR_ELEM("SDmaHeaderAddressErr", 0, 0,
4942 CNTR_NORMAL,
4943 access_sdma_header_address_err_cnt),
4944[C_SDMA_HEADER_SELECT_ERR] = CNTR_ELEM("SDmaHeaderSelectErr", 0, 0,
4945 CNTR_NORMAL,
4946 access_sdma_header_select_err_cnt),
4947[C_SMDA_RESERVED_9] = CNTR_ELEM("SDma Reserved 9", 0, 0,
4948 CNTR_NORMAL,
4949 access_sdma_reserved_9_err_cnt),
4950[C_SDMA_PACKET_DESC_OVERFLOW_ERR] = CNTR_ELEM("SDmaPacketDescOverflowErr", 0, 0,
4951 CNTR_NORMAL,
4952 access_sdma_packet_desc_overflow_err_cnt),
4953[C_SDMA_LENGTH_MISMATCH_ERR] = CNTR_ELEM("SDmaLengthMismatchErr", 0, 0,
4954 CNTR_NORMAL,
4955 access_sdma_length_mismatch_err_cnt),
4956[C_SDMA_HALT_ERR] = CNTR_ELEM("SDmaHaltErr", 0, 0,
4957 CNTR_NORMAL,
4958 access_sdma_halt_err_cnt),
4959[C_SDMA_MEM_READ_ERR] = CNTR_ELEM("SDmaMemReadErr", 0, 0,
4960 CNTR_NORMAL,
4961 access_sdma_mem_read_err_cnt),
4962[C_SDMA_FIRST_DESC_ERR] = CNTR_ELEM("SDmaFirstDescErr", 0, 0,
4963 CNTR_NORMAL,
4964 access_sdma_first_desc_err_cnt),
4965[C_SDMA_TAIL_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("SDmaTailOutOfBoundsErr", 0, 0,
4966 CNTR_NORMAL,
4967 access_sdma_tail_out_of_bounds_err_cnt),
4968[C_SDMA_TOO_LONG_ERR] = CNTR_ELEM("SDmaTooLongErr", 0, 0,
4969 CNTR_NORMAL,
4970 access_sdma_too_long_err_cnt),
4971[C_SDMA_GEN_MISMATCH_ERR] = CNTR_ELEM("SDmaGenMismatchErr", 0, 0,
4972 CNTR_NORMAL,
4973 access_sdma_gen_mismatch_err_cnt),
4974[C_SDMA_WRONG_DW_ERR] = CNTR_ELEM("SDmaWrongDwErr", 0, 0,
4975 CNTR_NORMAL,
4976 access_sdma_wrong_dw_err_cnt),
77241056
MM		 4977};
4978
4979static struct cntr_entry port_cntrs[PORT_CNTR_LAST] = {
4980[C_TX_UNSUP_VL] = TXE32_PORT_CNTR_ELEM(TxUnVLErr, SEND_UNSUP_VL_ERR_CNT,
4981 CNTR_NORMAL),
4982[C_TX_INVAL_LEN] = TXE32_PORT_CNTR_ELEM(TxInvalLen, SEND_LEN_ERR_CNT,
4983 CNTR_NORMAL),
4984[C_TX_MM_LEN_ERR] = TXE32_PORT_CNTR_ELEM(TxMMLenErr, SEND_MAX_MIN_LEN_ERR_CNT,
4985 CNTR_NORMAL),
4986[C_TX_UNDERRUN] = TXE32_PORT_CNTR_ELEM(TxUnderrun, SEND_UNDERRUN_CNT,
4987 CNTR_NORMAL),
4988[C_TX_FLOW_STALL] = TXE32_PORT_CNTR_ELEM(TxFlowStall, SEND_FLOW_STALL_CNT,
4989 CNTR_NORMAL),
4990[C_TX_DROPPED] = TXE32_PORT_CNTR_ELEM(TxDropped, SEND_DROPPED_PKT_CNT,
4991 CNTR_NORMAL),
4992[C_TX_HDR_ERR] = TXE32_PORT_CNTR_ELEM(TxHdrErr, SEND_HEADERS_ERR_CNT,
4993 CNTR_NORMAL),
4994[C_TX_PKT] = TXE64_PORT_CNTR_ELEM(TxPkt, SEND_DATA_PKT_CNT, CNTR_NORMAL),
4995[C_TX_WORDS] = TXE64_PORT_CNTR_ELEM(TxWords, SEND_DWORD_CNT, CNTR_NORMAL),
4996[C_TX_WAIT] = TXE64_PORT_CNTR_ELEM(TxWait, SEND_WAIT_CNT, CNTR_SYNTH),
4997[C_TX_FLIT_VL] = TXE64_PORT_CNTR_ELEM(TxFlitVL, SEND_DATA_VL0_CNT,
17fb4f29 4998 CNTR_SYNTH | CNTR_VL),
77241056 4999[C_TX_PKT_VL] = TXE64_PORT_CNTR_ELEM(TxPktVL, SEND_DATA_PKT_VL0_CNT,
17fb4f29 5000 CNTR_SYNTH | CNTR_VL),
77241056 5001[C_TX_WAIT_VL] = TXE64_PORT_CNTR_ELEM(TxWaitVL, SEND_WAIT_VL0_CNT,
17fb4f29 5002 CNTR_SYNTH | CNTR_VL),
77241056
MM		 5003[C_RX_PKT] = RXE64_PORT_CNTR_ELEM(RxPkt, RCV_DATA_PKT_CNT, CNTR_NORMAL),
5004[C_RX_WORDS] = RXE64_PORT_CNTR_ELEM(RxWords, RCV_DWORD_CNT, CNTR_NORMAL),
5005[C_SW_LINK_DOWN] = CNTR_ELEM("SwLinkDown", 0, 0, CNTR_SYNTH | CNTR_32BIT,
17fb4f29 5006 access_sw_link_dn_cnt),
77241056 5007[C_SW_LINK_UP] = CNTR_ELEM("SwLinkUp", 0, 0, CNTR_SYNTH | CNTR_32BIT,
17fb4f29 5008 access_sw_link_up_cnt),
6d014530
DL		 5009[C_SW_UNKNOWN_FRAME] = CNTR_ELEM("UnknownFrame", 0, 0, CNTR_NORMAL,
5010 access_sw_unknown_frame_cnt),
77241056 5011[C_SW_XMIT_DSCD] = CNTR_ELEM("XmitDscd", 0, 0, CNTR_SYNTH | CNTR_32BIT,
17fb4f29 5012 access_sw_xmit_discards),
77241056 5013[C_SW_XMIT_DSCD_VL] = CNTR_ELEM("XmitDscdVl", 0, 0,
17fb4f29
JJ		 5014 CNTR_SYNTH | CNTR_32BIT | CNTR_VL,
5015 access_sw_xmit_discards),
77241056 5016[C_SW_XMIT_CSTR_ERR] = CNTR_ELEM("XmitCstrErr", 0, 0, CNTR_SYNTH,
17fb4f29 5017 access_xmit_constraint_errs),
77241056 5018[C_SW_RCV_CSTR_ERR] = CNTR_ELEM("RcvCstrErr", 0, 0, CNTR_SYNTH,
17fb4f29 5019 access_rcv_constraint_errs),
77241056
MM		 5020[C_SW_IBP_LOOP_PKTS] = SW_IBP_CNTR(LoopPkts, loop_pkts),
5021[C_SW_IBP_RC_RESENDS] = SW_IBP_CNTR(RcResend, rc_resends),
5022[C_SW_IBP_RNR_NAKS] = SW_IBP_CNTR(RnrNak, rnr_naks),
5023[C_SW_IBP_OTHER_NAKS] = SW_IBP_CNTR(OtherNak, other_naks),
5024[C_SW_IBP_RC_TIMEOUTS] = SW_IBP_CNTR(RcTimeOut, rc_timeouts),
5025[C_SW_IBP_PKT_DROPS] = SW_IBP_CNTR(PktDrop, pkt_drops),
5026[C_SW_IBP_DMA_WAIT] = SW_IBP_CNTR(DmaWait, dmawait),
5027[C_SW_IBP_RC_SEQNAK] = SW_IBP_CNTR(RcSeqNak, rc_seqnak),
5028[C_SW_IBP_RC_DUPREQ] = SW_IBP_CNTR(RcDupRew, rc_dupreq),
5029[C_SW_IBP_RDMA_SEQ] = SW_IBP_CNTR(RdmaSeq, rdma_seq),
5030[C_SW_IBP_UNALIGNED] = SW_IBP_CNTR(Unaligned, unaligned),
5031[C_SW_IBP_SEQ_NAK] = SW_IBP_CNTR(SeqNak, seq_naks),
5032[C_SW_CPU_RC_ACKS] = CNTR_ELEM("RcAcks", 0, 0, CNTR_NORMAL,
5033 access_sw_cpu_rc_acks),
5034[C_SW_CPU_RC_QACKS] = CNTR_ELEM("RcQacks", 0, 0, CNTR_NORMAL,
17fb4f29 5035 access_sw_cpu_rc_qacks),
77241056 5036[C_SW_CPU_RC_DELAYED_COMP] = CNTR_ELEM("RcDelayComp", 0, 0, CNTR_NORMAL,
17fb4f29 5037 access_sw_cpu_rc_delayed_comp),
77241056
MM		 5038[OVR_LBL(0)] = OVR_ELM(0), [OVR_LBL(1)] = OVR_ELM(1),
5039[OVR_LBL(2)] = OVR_ELM(2), [OVR_LBL(3)] = OVR_ELM(3),
5040[OVR_LBL(4)] = OVR_ELM(4), [OVR_LBL(5)] = OVR_ELM(5),
5041[OVR_LBL(6)] = OVR_ELM(6), [OVR_LBL(7)] = OVR_ELM(7),
5042[OVR_LBL(8)] = OVR_ELM(8), [OVR_LBL(9)] = OVR_ELM(9),
5043[OVR_LBL(10)] = OVR_ELM(10), [OVR_LBL(11)] = OVR_ELM(11),
5044[OVR_LBL(12)] = OVR_ELM(12), [OVR_LBL(13)] = OVR_ELM(13),
5045[OVR_LBL(14)] = OVR_ELM(14), [OVR_LBL(15)] = OVR_ELM(15),
5046[OVR_LBL(16)] = OVR_ELM(16), [OVR_LBL(17)] = OVR_ELM(17),
5047[OVR_LBL(18)] = OVR_ELM(18), [OVR_LBL(19)] = OVR_ELM(19),
5048[OVR_LBL(20)] = OVR_ELM(20), [OVR_LBL(21)] = OVR_ELM(21),
5049[OVR_LBL(22)] = OVR_ELM(22), [OVR_LBL(23)] = OVR_ELM(23),
5050[OVR_LBL(24)] = OVR_ELM(24), [OVR_LBL(25)] = OVR_ELM(25),
5051[OVR_LBL(26)] = OVR_ELM(26), [OVR_LBL(27)] = OVR_ELM(27),
5052[OVR_LBL(28)] = OVR_ELM(28), [OVR_LBL(29)] = OVR_ELM(29),
5053[OVR_LBL(30)] = OVR_ELM(30), [OVR_LBL(31)] = OVR_ELM(31),
5054[OVR_LBL(32)] = OVR_ELM(32), [OVR_LBL(33)] = OVR_ELM(33),
5055[OVR_LBL(34)] = OVR_ELM(34), [OVR_LBL(35)] = OVR_ELM(35),
5056[OVR_LBL(36)] = OVR_ELM(36), [OVR_LBL(37)] = OVR_ELM(37),
5057[OVR_LBL(38)] = OVR_ELM(38), [OVR_LBL(39)] = OVR_ELM(39),
5058[OVR_LBL(40)] = OVR_ELM(40), [OVR_LBL(41)] = OVR_ELM(41),
5059[OVR_LBL(42)] = OVR_ELM(42), [OVR_LBL(43)] = OVR_ELM(43),
5060[OVR_LBL(44)] = OVR_ELM(44), [OVR_LBL(45)] = OVR_ELM(45),
5061[OVR_LBL(46)] = OVR_ELM(46), [OVR_LBL(47)] = OVR_ELM(47),
5062[OVR_LBL(48)] = OVR_ELM(48), [OVR_LBL(49)] = OVR_ELM(49),
5063[OVR_LBL(50)] = OVR_ELM(50), [OVR_LBL(51)] = OVR_ELM(51),
5064[OVR_LBL(52)] = OVR_ELM(52), [OVR_LBL(53)] = OVR_ELM(53),
5065[OVR_LBL(54)] = OVR_ELM(54), [OVR_LBL(55)] = OVR_ELM(55),
5066[OVR_LBL(56)] = OVR_ELM(56), [OVR_LBL(57)] = OVR_ELM(57),
5067[OVR_LBL(58)] = OVR_ELM(58), [OVR_LBL(59)] = OVR_ELM(59),
5068[OVR_LBL(60)] = OVR_ELM(60), [OVR_LBL(61)] = OVR_ELM(61),
5069[OVR_LBL(62)] = OVR_ELM(62), [OVR_LBL(63)] = OVR_ELM(63),
5070[OVR_LBL(64)] = OVR_ELM(64), [OVR_LBL(65)] = OVR_ELM(65),
5071[OVR_LBL(66)] = OVR_ELM(66), [OVR_LBL(67)] = OVR_ELM(67),
5072[OVR_LBL(68)] = OVR_ELM(68), [OVR_LBL(69)] = OVR_ELM(69),
5073[OVR_LBL(70)] = OVR_ELM(70), [OVR_LBL(71)] = OVR_ELM(71),
5074[OVR_LBL(72)] = OVR_ELM(72), [OVR_LBL(73)] = OVR_ELM(73),
5075[OVR_LBL(74)] = OVR_ELM(74), [OVR_LBL(75)] = OVR_ELM(75),
5076[OVR_LBL(76)] = OVR_ELM(76), [OVR_LBL(77)] = OVR_ELM(77),
5077[OVR_LBL(78)] = OVR_ELM(78), [OVR_LBL(79)] = OVR_ELM(79),
5078[OVR_LBL(80)] = OVR_ELM(80), [OVR_LBL(81)] = OVR_ELM(81),
5079[OVR_LBL(82)] = OVR_ELM(82), [OVR_LBL(83)] = OVR_ELM(83),
5080[OVR_LBL(84)] = OVR_ELM(84), [OVR_LBL(85)] = OVR_ELM(85),
5081[OVR_LBL(86)] = OVR_ELM(86), [OVR_LBL(87)] = OVR_ELM(87),
5082[OVR_LBL(88)] = OVR_ELM(88), [OVR_LBL(89)] = OVR_ELM(89),
5083[OVR_LBL(90)] = OVR_ELM(90), [OVR_LBL(91)] = OVR_ELM(91),
5084[OVR_LBL(92)] = OVR_ELM(92), [OVR_LBL(93)] = OVR_ELM(93),
5085[OVR_LBL(94)] = OVR_ELM(94), [OVR_LBL(95)] = OVR_ELM(95),
5086[OVR_LBL(96)] = OVR_ELM(96), [OVR_LBL(97)] = OVR_ELM(97),
5087[OVR_LBL(98)] = OVR_ELM(98), [OVR_LBL(99)] = OVR_ELM(99),
5088[OVR_LBL(100)] = OVR_ELM(100), [OVR_LBL(101)] = OVR_ELM(101),
5089[OVR_LBL(102)] = OVR_ELM(102), [OVR_LBL(103)] = OVR_ELM(103),
5090[OVR_LBL(104)] = OVR_ELM(104), [OVR_LBL(105)] = OVR_ELM(105),
5091[OVR_LBL(106)] = OVR_ELM(106), [OVR_LBL(107)] = OVR_ELM(107),
5092[OVR_LBL(108)] = OVR_ELM(108), [OVR_LBL(109)] = OVR_ELM(109),
5093[OVR_LBL(110)] = OVR_ELM(110), [OVR_LBL(111)] = OVR_ELM(111),
5094[OVR_LBL(112)] = OVR_ELM(112), [OVR_LBL(113)] = OVR_ELM(113),
5095[OVR_LBL(114)] = OVR_ELM(114), [OVR_LBL(115)] = OVR_ELM(115),
5096[OVR_LBL(116)] = OVR_ELM(116), [OVR_LBL(117)] = OVR_ELM(117),
5097[OVR_LBL(118)] = OVR_ELM(118), [OVR_LBL(119)] = OVR_ELM(119),
5098[OVR_LBL(120)] = OVR_ELM(120), [OVR_LBL(121)] = OVR_ELM(121),
5099[OVR_LBL(122)] = OVR_ELM(122), [OVR_LBL(123)] = OVR_ELM(123),
5100[OVR_LBL(124)] = OVR_ELM(124), [OVR_LBL(125)] = OVR_ELM(125),
5101[OVR_LBL(126)] = OVR_ELM(126), [OVR_LBL(127)] = OVR_ELM(127),
5102[OVR_LBL(128)] = OVR_ELM(128), [OVR_LBL(129)] = OVR_ELM(129),
5103[OVR_LBL(130)] = OVR_ELM(130), [OVR_LBL(131)] = OVR_ELM(131),
5104[OVR_LBL(132)] = OVR_ELM(132), [OVR_LBL(133)] = OVR_ELM(133),
5105[OVR_LBL(134)] = OVR_ELM(134), [OVR_LBL(135)] = OVR_ELM(135),
5106[OVR_LBL(136)] = OVR_ELM(136), [OVR_LBL(137)] = OVR_ELM(137),
5107[OVR_LBL(138)] = OVR_ELM(138), [OVR_LBL(139)] = OVR_ELM(139),
5108[OVR_LBL(140)] = OVR_ELM(140), [OVR_LBL(141)] = OVR_ELM(141),
5109[OVR_LBL(142)] = OVR_ELM(142), [OVR_LBL(143)] = OVR_ELM(143),
5110[OVR_LBL(144)] = OVR_ELM(144), [OVR_LBL(145)] = OVR_ELM(145),
5111[OVR_LBL(146)] = OVR_ELM(146), [OVR_LBL(147)] = OVR_ELM(147),
5112[OVR_LBL(148)] = OVR_ELM(148), [OVR_LBL(149)] = OVR_ELM(149),
5113[OVR_LBL(150)] = OVR_ELM(150), [OVR_LBL(151)] = OVR_ELM(151),
5114[OVR_LBL(152)] = OVR_ELM(152), [OVR_LBL(153)] = OVR_ELM(153),
5115[OVR_LBL(154)] = OVR_ELM(154), [OVR_LBL(155)] = OVR_ELM(155),
5116[OVR_LBL(156)] = OVR_ELM(156), [OVR_LBL(157)] = OVR_ELM(157),
5117[OVR_LBL(158)] = OVR_ELM(158), [OVR_LBL(159)] = OVR_ELM(159),
5118};
5119
5120/* ======================================================================== */
5121
77241056
MM		 5122/* return true if this is chip revision revision a */
5123int is_ax(struct hfi1_devdata *dd)
5124{
5125 u8 chip_rev_minor =
5126 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT
5127 & CCE_REVISION_CHIP_REV_MINOR_MASK;
5128 return (chip_rev_minor & 0xf0) == 0;
5129}
5130
5131/* return true if this is chip revision revision b */
5132int is_bx(struct hfi1_devdata *dd)
5133{
5134 u8 chip_rev_minor =
5135 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT
5136 & CCE_REVISION_CHIP_REV_MINOR_MASK;
995deafa 5137 return (chip_rev_minor & 0xF0) == 0x10;
77241056
MM		 5138}
5139
5140/*
5141 * Append string s to buffer buf. Arguments curp and len are the current
5142 * position and remaining length, respectively.
5143 *
5144 * return 0 on success, 1 on out of room
5145 */
5146static int append_str(char *buf, char **curp, int *lenp, const char *s)
5147{
5148 char *p = *curp;
5149 int len = *lenp;
5150 int result = 0; /* success */
5151 char c;
5152
5153 /* add a comma, if first in the buffer */
5154 if (p != buf) {
5155 if (len == 0) {
5156 result = 1; /* out of room */
5157 goto done;
5158 }
5159 *p++ = ',';
5160 len--;
5161 }
5162
5163 /* copy the string */
5164 while ((c = *s++) != 0) {
5165 if (len == 0) {
5166 result = 1; /* out of room */
5167 goto done;
5168 }
5169 *p++ = c;
5170 len--;
5171 }
5172
5173done:
5174 /* write return values */
5175 *curp = p;
5176 *lenp = len;
5177
5178 return result;
5179}
5180
5181/*
5182 * Using the given flag table, print a comma separated string into
5183 * the buffer. End in '*' if the buffer is too short.
5184 */
5185static char *flag_string(char *buf, int buf_len, u64 flags,
17fb4f29 5186 struct flag_table *table, int table_size)
77241056
MM		 5187{
5188 char extra[32];
5189 char *p = buf;
5190 int len = buf_len;
5191 int no_room = 0;
5192 int i;
5193
5194 /* make sure there is at least 2 so we can form "*" */
5195 if (len < 2)
5196 return "";
5197
5198 len--; /* leave room for a nul */
5199 for (i = 0; i < table_size; i++) {
5200 if (flags & table[i].flag) {
5201 no_room = append_str(buf, &p, &len, table[i].str);
5202 if (no_room)
5203 break;
5204 flags &= ~table[i].flag;
5205 }
5206 }
5207
5208 /* any undocumented bits left? */
5209 if (!no_room && flags) {
5210 snprintf(extra, sizeof(extra), "bits 0x%llx", flags);
5211 no_room = append_str(buf, &p, &len, extra);
5212 }
5213
5214 /* add * if ran out of room */
5215 if (no_room) {
5216 /* may need to back up to add space for a '*' */
5217 if (len == 0)
5218 --p;
5219 *p++ = '*';
5220 }
5221
5222 /* add final nul - space already allocated above */
5223 *p = 0;
5224 return buf;
5225}
5226
5227/* first 8 CCE error interrupt source names */
5228static const char * const cce_misc_names[] = {
5229 "CceErrInt", /* 0 */
5230 "RxeErrInt", /* 1 */
5231 "MiscErrInt", /* 2 */
5232 "Reserved3", /* 3 */
5233 "PioErrInt", /* 4 */
5234 "SDmaErrInt", /* 5 */
5235 "EgressErrInt", /* 6 */
5236 "TxeErrInt" /* 7 */
5237};
5238
5239/*
5240 * Return the miscellaneous error interrupt name.
5241 */
5242static char *is_misc_err_name(char *buf, size_t bsize, unsigned int source)
5243{
5244 if (source < ARRAY_SIZE(cce_misc_names))
5245 strncpy(buf, cce_misc_names[source], bsize);
5246 else
17fb4f29
JJ		 5247 snprintf(buf, bsize, "Reserved%u",
5248 source + IS_GENERAL_ERR_START);
77241056
MM		 5249
5250 return buf;
5251}
5252
5253/*
5254 * Return the SDMA engine error interrupt name.
5255 */
5256static char *is_sdma_eng_err_name(char *buf, size_t bsize, unsigned int source)
5257{
5258 snprintf(buf, bsize, "SDmaEngErrInt%u", source);
5259 return buf;
5260}
5261
5262/*
5263 * Return the send context error interrupt name.
5264 */
5265static char *is_sendctxt_err_name(char *buf, size_t bsize, unsigned int source)
5266{
5267 snprintf(buf, bsize, "SendCtxtErrInt%u", source);
5268 return buf;
5269}
5270
5271static const char * const various_names[] = {
5272 "PbcInt",
5273 "GpioAssertInt",
5274 "Qsfp1Int",
5275 "Qsfp2Int",
5276 "TCritInt"
5277};
5278
5279/*
5280 * Return the various interrupt name.
5281 */
5282static char *is_various_name(char *buf, size_t bsize, unsigned int source)
5283{
5284 if (source < ARRAY_SIZE(various_names))
5285 strncpy(buf, various_names[source], bsize);
5286 else
8638b77f 5287 snprintf(buf, bsize, "Reserved%u", source + IS_VARIOUS_START);
77241056
MM		 5288 return buf;
5289}
5290
5291/*
5292 * Return the DC interrupt name.
5293 */
5294static char *is_dc_name(char *buf, size_t bsize, unsigned int source)
5295{
5296 static const char * const dc_int_names[] = {
5297 "common",
5298 "lcb",
5299 "8051",
5300 "lbm" /* local block merge */
5301 };
5302
5303 if (source < ARRAY_SIZE(dc_int_names))
5304 snprintf(buf, bsize, "dc_%s_int", dc_int_names[source]);
5305 else
5306 snprintf(buf, bsize, "DCInt%u", source);
5307 return buf;
5308}
5309
5310static const char * const sdma_int_names[] = {
5311 "SDmaInt",
5312 "SdmaIdleInt",
5313 "SdmaProgressInt",
5314};
5315
5316/*
5317 * Return the SDMA engine interrupt name.
5318 */
5319static char *is_sdma_eng_name(char *buf, size_t bsize, unsigned int source)
5320{
5321 /* what interrupt */
5322 unsigned int what = source / TXE_NUM_SDMA_ENGINES;
5323 /* which engine */
5324 unsigned int which = source % TXE_NUM_SDMA_ENGINES;
5325
5326 if (likely(what < 3))
5327 snprintf(buf, bsize, "%s%u", sdma_int_names[what], which);
5328 else
5329 snprintf(buf, bsize, "Invalid SDMA interrupt %u", source);
5330 return buf;
5331}
5332
5333/*
5334 * Return the receive available interrupt name.
5335 */
5336static char *is_rcv_avail_name(char *buf, size_t bsize, unsigned int source)
5337{
5338 snprintf(buf, bsize, "RcvAvailInt%u", source);
5339 return buf;
5340}
5341
5342/*
5343 * Return the receive urgent interrupt name.
5344 */
5345static char *is_rcv_urgent_name(char *buf, size_t bsize, unsigned int source)
5346{
5347 snprintf(buf, bsize, "RcvUrgentInt%u", source);
5348 return buf;
5349}
5350
5351/*
5352 * Return the send credit interrupt name.
5353 */
5354static char *is_send_credit_name(char *buf, size_t bsize, unsigned int source)
5355{
5356 snprintf(buf, bsize, "SendCreditInt%u", source);
5357 return buf;
5358}
5359
5360/*
5361 * Return the reserved interrupt name.
5362 */
5363static char *is_reserved_name(char *buf, size_t bsize, unsigned int source)
5364{
5365 snprintf(buf, bsize, "Reserved%u", source + IS_RESERVED_START);
5366 return buf;
5367}
5368
5369static char *cce_err_status_string(char *buf, int buf_len, u64 flags)
5370{
5371 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5372 cce_err_status_flags,
5373 ARRAY_SIZE(cce_err_status_flags));
77241056
MM		 5374}
5375
5376static char *rxe_err_status_string(char *buf, int buf_len, u64 flags)
5377{
5378 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5379 rxe_err_status_flags,
5380 ARRAY_SIZE(rxe_err_status_flags));
77241056
MM		 5381}
5382
5383static char *misc_err_status_string(char *buf, int buf_len, u64 flags)
5384{
5385 return flag_string(buf, buf_len, flags, misc_err_status_flags,
17fb4f29 5386 ARRAY_SIZE(misc_err_status_flags));
77241056
MM		 5387}
5388
5389static char *pio_err_status_string(char *buf, int buf_len, u64 flags)
5390{
5391 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5392 pio_err_status_flags,
5393 ARRAY_SIZE(pio_err_status_flags));
77241056
MM		 5394}
5395
5396static char *sdma_err_status_string(char *buf, int buf_len, u64 flags)
5397{
5398 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5399 sdma_err_status_flags,
5400 ARRAY_SIZE(sdma_err_status_flags));
77241056
MM		 5401}
5402
5403static char *egress_err_status_string(char *buf, int buf_len, u64 flags)
5404{
5405 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5406 egress_err_status_flags,
5407 ARRAY_SIZE(egress_err_status_flags));
77241056
MM		 5408}
5409
5410static char *egress_err_info_string(char *buf, int buf_len, u64 flags)
5411{
5412 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5413 egress_err_info_flags,
5414 ARRAY_SIZE(egress_err_info_flags));
77241056
MM		 5415}
5416
5417static char *send_err_status_string(char *buf, int buf_len, u64 flags)
5418{
5419 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5420 send_err_status_flags,
5421 ARRAY_SIZE(send_err_status_flags));
77241056
MM		 5422}
5423
5424static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5425{
5426 char buf[96];
2c5b521a 5427 int i = 0;
77241056
MM		 5428
5429 /*
5430 * For most these errors, there is nothing that can be done except
5431 * report or record it.
5432 */
5433 dd_dev_info(dd, "CCE Error: %s\n",
17fb4f29 5434 cce_err_status_string(buf, sizeof(buf), reg));
77241056 5435
995deafa
MM		 5436 if ((reg & CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK) &&
5437 is_ax(dd) && (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)) {
77241056
MM		 5438 /* this error requires a manual drop into SPC freeze mode */
5439 /* then a fix up */
5440 start_freeze_handling(dd->pport, FREEZE_SELF);
5441 }
2c5b521a
JR		 5442
5443 for (i = 0; i < NUM_CCE_ERR_STATUS_COUNTERS; i++) {
5444 if (reg & (1ull << i)) {
5445 incr_cntr64(&dd->cce_err_status_cnt[i]);
5446 /* maintain a counter over all cce_err_status errors */
5447 incr_cntr64(&dd->sw_cce_err_status_aggregate);
5448 }
5449 }
77241056
MM		 5450}
5451
5452/*
5453 * Check counters for receive errors that do not have an interrupt
5454 * associated with them.
5455 */
5456#define RCVERR_CHECK_TIME 10
5457static void update_rcverr_timer(unsigned long opaque)
5458{
5459 struct hfi1_devdata *dd = (struct hfi1_devdata *)opaque;
5460 struct hfi1_pportdata *ppd = dd->pport;
5461 u32 cur_ovfl_cnt = read_dev_cntr(dd, C_RCV_OVF, CNTR_INVALID_VL);
5462
5463 if (dd->rcv_ovfl_cnt < cur_ovfl_cnt &&
17fb4f29 5464 ppd->port_error_action & OPA_PI_MASK_EX_BUFFER_OVERRUN) {
77241056 5465 dd_dev_info(dd, "%s: PortErrorAction bounce\n", __func__);
17fb4f29
JJ		 5466 set_link_down_reason(
5467 ppd, OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN, 0,
5468 OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN);
77241056
MM		 5469 queue_work(ppd->hfi1_wq, &ppd->link_bounce_work);
5470 }
50e5dcbe 5471 dd->rcv_ovfl_cnt = (u32)cur_ovfl_cnt;
77241056
MM		 5472
5473 mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME);
5474}
5475
5476static int init_rcverr(struct hfi1_devdata *dd)
5477{
24523a94 5478 setup_timer(&dd->rcverr_timer, update_rcverr_timer, (unsigned long)dd);
77241056
MM		 5479 /* Assume the hardware counter has been reset */
5480 dd->rcv_ovfl_cnt = 0;
5481 return mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME);
5482}
5483
5484static void free_rcverr(struct hfi1_devdata *dd)
5485{
5486 if (dd->rcverr_timer.data)
5487 del_timer_sync(&dd->rcverr_timer);
5488 dd->rcverr_timer.data = 0;
5489}
5490
5491static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5492{
5493 char buf[96];
2c5b521a 5494 int i = 0;
77241056
MM		 5495
5496 dd_dev_info(dd, "Receive Error: %s\n",
17fb4f29 5497 rxe_err_status_string(buf, sizeof(buf), reg));
77241056
MM		 5498
5499 if (reg & ALL_RXE_FREEZE_ERR) {
5500 int flags = 0;
5501
5502 /*
5503 * Freeze mode recovery is disabled for the errors
5504 * in RXE_FREEZE_ABORT_MASK
5505 */
995deafa 5506 if (is_ax(dd) && (reg & RXE_FREEZE_ABORT_MASK))
77241056
MM		 5507 flags = FREEZE_ABORT;
5508
5509 start_freeze_handling(dd->pport, flags);
5510 }
2c5b521a
JR		 5511
5512 for (i = 0; i < NUM_RCV_ERR_STATUS_COUNTERS; i++) {
5513 if (reg & (1ull << i))
5514 incr_cntr64(&dd->rcv_err_status_cnt[i]);
5515 }
77241056
MM		 5516}
5517
5518static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5519{
5520 char buf[96];
2c5b521a 5521 int i = 0;
77241056
MM		 5522
5523 dd_dev_info(dd, "Misc Error: %s",
17fb4f29 5524 misc_err_status_string(buf, sizeof(buf), reg));
2c5b521a
JR		 5525 for (i = 0; i < NUM_MISC_ERR_STATUS_COUNTERS; i++) {
5526 if (reg & (1ull << i))
5527 incr_cntr64(&dd->misc_err_status_cnt[i]);
5528 }
77241056
MM		 5529}
5530
5531static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5532{
5533 char buf[96];
2c5b521a 5534 int i = 0;
77241056
MM		 5535
5536 dd_dev_info(dd, "PIO Error: %s\n",
17fb4f29 5537 pio_err_status_string(buf, sizeof(buf), reg));
77241056
MM		 5538
5539 if (reg & ALL_PIO_FREEZE_ERR)
5540 start_freeze_handling(dd->pport, 0);
2c5b521a
JR		 5541
5542 for (i = 0; i < NUM_SEND_PIO_ERR_STATUS_COUNTERS; i++) {
5543 if (reg & (1ull << i))
5544 incr_cntr64(&dd->send_pio_err_status_cnt[i]);
5545 }
77241056
MM		 5546}
5547
5548static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5549{
5550 char buf[96];
2c5b521a 5551 int i = 0;
77241056
MM		 5552
5553 dd_dev_info(dd, "SDMA Error: %s\n",
17fb4f29 5554 sdma_err_status_string(buf, sizeof(buf), reg));
77241056
MM		 5555
5556 if (reg & ALL_SDMA_FREEZE_ERR)
5557 start_freeze_handling(dd->pport, 0);
2c5b521a
JR		 5558
5559 for (i = 0; i < NUM_SEND_DMA_ERR_STATUS_COUNTERS; i++) {
5560 if (reg & (1ull << i))
5561 incr_cntr64(&dd->send_dma_err_status_cnt[i]);
5562 }
77241056
MM		 5563}
5564
69a00b8e 5565static inline void __count_port_discards(struct hfi1_pportdata *ppd)
77241056 5566{
69a00b8e
MM		 5567 incr_cntr64(&ppd->port_xmit_discards);
5568}
77241056 5569
69a00b8e
MM		 5570static void count_port_inactive(struct hfi1_devdata *dd)
5571{
5572 __count_port_discards(dd->pport);
77241056
MM		 5573}
5574
5575/*
5576 * We have had a "disallowed packet" error during egress. Determine the
5577 * integrity check which failed, and update relevant error counter, etc.
5578 *
5579 * Note that the SEND_EGRESS_ERR_INFO register has only a single
5580 * bit of state per integrity check, and so we can miss the reason for an
5581 * egress error if more than one packet fails the same integrity check
5582 * since we cleared the corresponding bit in SEND_EGRESS_ERR_INFO.
5583 */
69a00b8e
MM		 5584static void handle_send_egress_err_info(struct hfi1_devdata *dd,
5585 int vl)
77241056
MM		 5586{
5587 struct hfi1_pportdata *ppd = dd->pport;
5588 u64 src = read_csr(dd, SEND_EGRESS_ERR_SOURCE); /* read first */
5589 u64 info = read_csr(dd, SEND_EGRESS_ERR_INFO);
5590 char buf[96];
5591
5592 /* clear down all observed info as quickly as possible after read */
5593 write_csr(dd, SEND_EGRESS_ERR_INFO, info);
5594
5595 dd_dev_info(dd,
17fb4f29
JJ		 5596 "Egress Error Info: 0x%llx, %s Egress Error Src 0x%llx\n",
5597 info, egress_err_info_string(buf, sizeof(buf), info), src);
77241056
MM		 5598
5599 /* Eventually add other counters for each bit */
69a00b8e
MM		 5600 if (info & PORT_DISCARD_EGRESS_ERRS) {
5601 int weight, i;
77241056 5602
69a00b8e 5603 /*
4c9e7aac
DL		 5604 * Count all applicable bits as individual errors and
5605 * attribute them to the packet that triggered this handler.
5606 * This may not be completely accurate due to limitations
5607 * on the available hardware error information. There is
5608 * a single information register and any number of error
5609 * packets may have occurred and contributed to it before
5610 * this routine is called. This means that:
5611 * a) If multiple packets with the same error occur before
5612 * this routine is called, earlier packets are missed.
5613 * There is only a single bit for each error type.
5614 * b) Errors may not be attributed to the correct VL.
5615 * The driver is attributing all bits in the info register
5616 * to the packet that triggered this call, but bits
5617 * could be an accumulation of different packets with
5618 * different VLs.
5619 * c) A single error packet may have multiple counts attached
5620 * to it. There is no way for the driver to know if
5621 * multiple bits set in the info register are due to a
5622 * single packet or multiple packets. The driver assumes
5623 * multiple packets.
69a00b8e 5624 */
4c9e7aac 5625 weight = hweight64(info & PORT_DISCARD_EGRESS_ERRS);
69a00b8e
MM		 5626 for (i = 0; i < weight; i++) {
5627 __count_port_discards(ppd);
5628 if (vl >= 0 && vl < TXE_NUM_DATA_VL)
5629 incr_cntr64(&ppd->port_xmit_discards_vl[vl]);
5630 else if (vl == 15)
5631 incr_cntr64(&ppd->port_xmit_discards_vl
5632 [C_VL_15]);
5633 }
77241056
MM		 5634 }
5635}
5636
5637/*
5638 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5639 * register. Does it represent a 'port inactive' error?
5640 */
5641static inline int port_inactive_err(u64 posn)
5642{
5643 return (posn >= SEES(TX_LINKDOWN) &&
5644 posn <= SEES(TX_INCORRECT_LINK_STATE));
5645}
5646
5647/*
5648 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5649 * register. Does it represent a 'disallowed packet' error?
5650 */
69a00b8e 5651static inline int disallowed_pkt_err(int posn)
77241056
MM		 5652{
5653 return (posn >= SEES(TX_SDMA0_DISALLOWED_PACKET) &&
5654 posn <= SEES(TX_SDMA15_DISALLOWED_PACKET));
5655}
5656
69a00b8e
MM		 5657/*
5658 * Input value is a bit position of one of the SDMA engine disallowed
5659 * packet errors. Return which engine. Use of this must be guarded by
5660 * disallowed_pkt_err().
5661 */
5662static inline int disallowed_pkt_engine(int posn)
5663{
5664 return posn - SEES(TX_SDMA0_DISALLOWED_PACKET);
5665}
5666
5667/*
5668 * Translate an SDMA engine to a VL. Return -1 if the tranlation cannot
5669 * be done.
5670 */
5671static int engine_to_vl(struct hfi1_devdata *dd, int engine)
5672{
5673 struct sdma_vl_map *m;
5674 int vl;
5675
5676 /* range check */
5677 if (engine < 0 || engine >= TXE_NUM_SDMA_ENGINES)
5678 return -1;
5679
5680 rcu_read_lock();
5681 m = rcu_dereference(dd->sdma_map);
5682 vl = m->engine_to_vl[engine];
5683 rcu_read_unlock();
5684
5685 return vl;
5686}
5687
5688/*
5689 * Translate the send context (sofware index) into a VL. Return -1 if the
5690 * translation cannot be done.
5691 */
5692static int sc_to_vl(struct hfi1_devdata *dd, int sw_index)
5693{
5694 struct send_context_info *sci;
5695 struct send_context *sc;
5696 int i;
5697
5698 sci = &dd->send_contexts[sw_index];
5699
5700 /* there is no information for user (PSM) and ack contexts */
44306f15 5701 if ((sci->type != SC_KERNEL) && (sci->type != SC_VL15))
69a00b8e
MM		 5702 return -1;
5703
5704 sc = sci->sc;
5705 if (!sc)
5706 return -1;
5707 if (dd->vld[15].sc == sc)
5708 return 15;
5709 for (i = 0; i < num_vls; i++)
5710 if (dd->vld[i].sc == sc)
5711 return i;
5712
5713 return -1;
5714}
5715
77241056
MM		 5716static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5717{
5718 u64 reg_copy = reg, handled = 0;
5719 char buf[96];
2c5b521a 5720 int i = 0;
77241056
MM		 5721
5722 if (reg & ALL_TXE_EGRESS_FREEZE_ERR)
5723 start_freeze_handling(dd->pport, 0);
69a00b8e
MM		 5724 else if (is_ax(dd) &&
5725 (reg & SEND_EGRESS_ERR_STATUS_TX_CREDIT_RETURN_VL_ERR_SMASK) &&
5726 (dd->icode != ICODE_FUNCTIONAL_SIMULATOR))
77241056
MM		 5727 start_freeze_handling(dd->pport, 0);
5728
5729 while (reg_copy) {
5730 int posn = fls64(reg_copy);
69a00b8e 5731 /* fls64() returns a 1-based offset, we want it zero based */
77241056 5732 int shift = posn - 1;
69a00b8e 5733 u64 mask = 1ULL << shift;
77241056
MM		 5734
5735 if (port_inactive_err(shift)) {
5736 count_port_inactive(dd);
69a00b8e 5737 handled |= mask;
77241056 5738 } else if (disallowed_pkt_err(shift)) {
69a00b8e
MM		 5739 int vl = engine_to_vl(dd, disallowed_pkt_engine(shift));
5740
5741 handle_send_egress_err_info(dd, vl);
5742 handled |= mask;
77241056 5743 }
69a00b8e 5744 reg_copy &= ~mask;
77241056
MM		 5745 }
5746
5747 reg &= ~handled;
5748
5749 if (reg)
5750 dd_dev_info(dd, "Egress Error: %s\n",
17fb4f29 5751 egress_err_status_string(buf, sizeof(buf), reg));
2c5b521a
JR		 5752
5753 for (i = 0; i < NUM_SEND_EGRESS_ERR_STATUS_COUNTERS; i++) {
5754 if (reg & (1ull << i))
5755 incr_cntr64(&dd->send_egress_err_status_cnt[i]);
5756 }
77241056
MM		 5757}
5758
5759static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5760{
5761 char buf[96];
2c5b521a 5762 int i = 0;
77241056
MM		 5763
5764 dd_dev_info(dd, "Send Error: %s\n",
17fb4f29 5765 send_err_status_string(buf, sizeof(buf), reg));
77241056 5766
2c5b521a
JR		 5767 for (i = 0; i < NUM_SEND_ERR_STATUS_COUNTERS; i++) {
5768 if (reg & (1ull << i))
5769 incr_cntr64(&dd->send_err_status_cnt[i]);
5770 }
77241056
MM		 5771}
5772
5773/*
5774 * The maximum number of times the error clear down will loop before
5775 * blocking a repeating error. This value is arbitrary.
5776 */
5777#define MAX_CLEAR_COUNT 20
5778
5779/*
5780 * Clear and handle an error register. All error interrupts are funneled
5781 * through here to have a central location to correctly handle single-
5782 * or multi-shot errors.
5783 *
5784 * For non per-context registers, call this routine with a context value
5785 * of 0 so the per-context offset is zero.
5786 *
5787 * If the handler loops too many times, assume that something is wrong
5788 * and can't be fixed, so mask the error bits.
5789 */
5790static void interrupt_clear_down(struct hfi1_devdata *dd,
5791 u32 context,
5792 const struct err_reg_info *eri)
5793{
5794 u64 reg;
5795 u32 count;
5796
5797 /* read in a loop until no more errors are seen */
5798 count = 0;
5799 while (1) {
5800 reg = read_kctxt_csr(dd, context, eri->status);
5801 if (reg == 0)
5802 break;
5803 write_kctxt_csr(dd, context, eri->clear, reg);
5804 if (likely(eri->handler))
5805 eri->handler(dd, context, reg);
5806 count++;
5807 if (count > MAX_CLEAR_COUNT) {
5808 u64 mask;
5809
5810 dd_dev_err(dd, "Repeating %s bits 0x%llx - masking\n",
17fb4f29 5811 eri->desc, reg);
77241056
MM		 5812 /*
5813 * Read-modify-write so any other masked bits
5814 * remain masked.
5815 */
5816 mask = read_kctxt_csr(dd, context, eri->mask);
5817 mask &= ~reg;
5818 write_kctxt_csr(dd, context, eri->mask, mask);
5819 break;
5820 }
5821 }
5822}
5823
5824/*
5825 * CCE block "misc" interrupt. Source is < 16.
5826 */
5827static void is_misc_err_int(struct hfi1_devdata *dd, unsigned int source)
5828{
5829 const struct err_reg_info *eri = &misc_errs[source];
5830
5831 if (eri->handler) {
5832 interrupt_clear_down(dd, 0, eri);
5833 } else {
5834 dd_dev_err(dd, "Unexpected misc interrupt (%u) - reserved\n",
17fb4f29 5835 source);
77241056
MM		 5836 }
5837}
5838
5839static char *send_context_err_status_string(char *buf, int buf_len, u64 flags)
5840{
5841 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5842 sc_err_status_flags,
5843 ARRAY_SIZE(sc_err_status_flags));
77241056
MM		 5844}
5845
5846/*
5847 * Send context error interrupt. Source (hw_context) is < 160.
5848 *
5849 * All send context errors cause the send context to halt. The normal
5850 * clear-down mechanism cannot be used because we cannot clear the
5851 * error bits until several other long-running items are done first.
5852 * This is OK because with the context halted, nothing else is going
5853 * to happen on it anyway.
5854 */
5855static void is_sendctxt_err_int(struct hfi1_devdata *dd,
5856 unsigned int hw_context)
5857{
5858 struct send_context_info *sci;
5859 struct send_context *sc;
5860 char flags[96];
5861 u64 status;
5862 u32 sw_index;
2c5b521a 5863 int i = 0;
77241056
MM		 5864
5865 sw_index = dd->hw_to_sw[hw_context];
5866 if (sw_index >= dd->num_send_contexts) {
5867 dd_dev_err(dd,
17fb4f29
JJ		 5868 "out of range sw index %u for send context %u\n",
5869 sw_index, hw_context);
77241056
MM		 5870 return;
5871 }
5872 sci = &dd->send_contexts[sw_index];
5873 sc = sci->sc;
5874 if (!sc) {
5875 dd_dev_err(dd, "%s: context %u(%u): no sc?\n", __func__,
17fb4f29 5876 sw_index, hw_context);
77241056
MM		 5877 return;
5878 }
5879
5880 /* tell the software that a halt has begun */
5881 sc_stop(sc, SCF_HALTED);
5882
5883 status = read_kctxt_csr(dd, hw_context, SEND_CTXT_ERR_STATUS);
5884
5885 dd_dev_info(dd, "Send Context %u(%u) Error: %s\n", sw_index, hw_context,
17fb4f29
JJ		 5886 send_context_err_status_string(flags, sizeof(flags),
5887 status));
77241056
MM		 5888
5889 if (status & SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK)
69a00b8e 5890 handle_send_egress_err_info(dd, sc_to_vl(dd, sw_index));
77241056
MM		 5891
5892 /*
5893 * Automatically restart halted kernel contexts out of interrupt
5894 * context. User contexts must ask the driver to restart the context.
5895 */
5896 if (sc->type != SC_USER)
5897 queue_work(dd->pport->hfi1_wq, &sc->halt_work);
2c5b521a
JR		 5898
5899 /*
5900 * Update the counters for the corresponding status bits.
5901 * Note that these particular counters are aggregated over all
5902 * 160 contexts.
5903 */
5904 for (i = 0; i < NUM_SEND_CTXT_ERR_STATUS_COUNTERS; i++) {
5905 if (status & (1ull << i))
5906 incr_cntr64(&dd->sw_ctxt_err_status_cnt[i]);
5907 }
77241056
MM		 5908}
5909
5910static void handle_sdma_eng_err(struct hfi1_devdata *dd,
5911 unsigned int source, u64 status)
5912{
5913 struct sdma_engine *sde;
2c5b521a 5914 int i = 0;
77241056
MM		 5915
5916 sde = &dd->per_sdma[source];
5917#ifdef CONFIG_SDMA_VERBOSITY
5918 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
5919 slashstrip(__FILE__), __LINE__, __func__);
5920 dd_dev_err(sde->dd, "CONFIG SDMA(%u) source: %u status 0x%llx\n",
5921 sde->this_idx, source, (unsigned long long)status);
5922#endif
a699c6c2 5923 sde->err_cnt++;
77241056 5924 sdma_engine_error(sde, status);
2c5b521a
JR		 5925
5926 /*
5927 * Update the counters for the corresponding status bits.
5928 * Note that these particular counters are aggregated over
5929 * all 16 DMA engines.
5930 */
5931 for (i = 0; i < NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS; i++) {
5932 if (status & (1ull << i))
5933 incr_cntr64(&dd->sw_send_dma_eng_err_status_cnt[i]);
5934 }
77241056
MM		 5935}
5936
5937/*
5938 * CCE block SDMA error interrupt. Source is < 16.
5939 */
5940static void is_sdma_eng_err_int(struct hfi1_devdata *dd, unsigned int source)
5941{
5942#ifdef CONFIG_SDMA_VERBOSITY
5943 struct sdma_engine *sde = &dd->per_sdma[source];
5944
5945 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
5946 slashstrip(__FILE__), __LINE__, __func__);
5947 dd_dev_err(dd, "CONFIG SDMA(%u) source: %u\n", sde->this_idx,
5948 source);
5949 sdma_dumpstate(sde);
5950#endif
5951 interrupt_clear_down(dd, source, &sdma_eng_err);
5952}
5953
5954/*
5955 * CCE block "various" interrupt. Source is < 8.
5956 */
5957static void is_various_int(struct hfi1_devdata *dd, unsigned int source)
5958{
5959 const struct err_reg_info *eri = &various_err[source];
5960
5961 /*
5962 * TCritInt cannot go through interrupt_clear_down()
5963 * because it is not a second tier interrupt. The handler
5964 * should be called directly.
5965 */
5966 if (source == TCRIT_INT_SOURCE)
5967 handle_temp_err(dd);
5968 else if (eri->handler)
5969 interrupt_clear_down(dd, 0, eri);
5970 else
5971 dd_dev_info(dd,
17fb4f29
JJ		 5972 "%s: Unimplemented/reserved interrupt %d\n",
5973 __func__, source);
77241056
MM		 5974}
5975
5976static void handle_qsfp_int(struct hfi1_devdata *dd, u32 src_ctx, u64 reg)
5977{
8ebd4cf1 5978 /* src_ctx is always zero */
77241056
MM		 5979 struct hfi1_pportdata *ppd = dd->pport;
5980 unsigned long flags;
5981 u64 qsfp_int_mgmt = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N);
5982
5983 if (reg & QSFP_HFI0_MODPRST_N) {
77241056 5984 if (!qsfp_mod_present(ppd)) {
e8aa284b
EH		 5985 dd_dev_info(dd, "%s: QSFP module removed\n",
5986 __func__);
5987
77241056
MM		 5988 ppd->driver_link_ready = 0;
5989 /*
5990 * Cable removed, reset all our information about the
5991 * cache and cable capabilities
5992 */
5993
5994 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
5995 /*
5996 * We don't set cache_refresh_required here as we expect
5997 * an interrupt when a cable is inserted
5998 */
5999 ppd->qsfp_info.cache_valid = 0;
8ebd4cf1
EH		 6000 ppd->qsfp_info.reset_needed = 0;
6001 ppd->qsfp_info.limiting_active = 0;
77241056 6002 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
17fb4f29 6003 flags);
8ebd4cf1
EH		 6004 /* Invert the ModPresent pin now to detect plug-in */
6005 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
6006 ASIC_QSFP1_INVERT, qsfp_int_mgmt);
a9c05e35
BM		 6007
6008 if ((ppd->offline_disabled_reason >
6009 HFI1_ODR_MASK(
e1bf0d5e 6010 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED)) ||
a9c05e35
BM		 6011 (ppd->offline_disabled_reason ==
6012 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE)))
6013 ppd->offline_disabled_reason =
6014 HFI1_ODR_MASK(
e1bf0d5e 6015 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED);
a9c05e35 6016
77241056
MM		 6017 if (ppd->host_link_state == HLS_DN_POLL) {
6018 /*
6019 * The link is still in POLL. This means
6020 * that the normal link down processing
6021 * will not happen. We have to do it here
6022 * before turning the DC off.
6023 */
6024 queue_work(ppd->hfi1_wq, &ppd->link_down_work);
6025 }
6026 } else {
e8aa284b
EH		 6027 dd_dev_info(dd, "%s: QSFP module inserted\n",
6028 __func__);
6029
77241056
MM		 6030 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
6031 ppd->qsfp_info.cache_valid = 0;
6032 ppd->qsfp_info.cache_refresh_required = 1;
6033 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
17fb4f29 6034 flags);
77241056 6035
8ebd4cf1
EH		 6036 /*
6037 * Stop inversion of ModPresent pin to detect
6038 * removal of the cable
6039 */
77241056 6040 qsfp_int_mgmt &= ~(u64)QSFP_HFI0_MODPRST_N;
8ebd4cf1
EH		 6041 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
6042 ASIC_QSFP1_INVERT, qsfp_int_mgmt);
6043
6044 ppd->offline_disabled_reason =
6045 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT);
77241056
MM		 6046 }
6047 }
6048
6049 if (reg & QSFP_HFI0_INT_N) {
e8aa284b 6050 dd_dev_info(dd, "%s: Interrupt received from QSFP module\n",
17fb4f29 6051 __func__);
77241056
MM		 6052 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
6053 ppd->qsfp_info.check_interrupt_flags = 1;
77241056
MM		 6054 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, flags);
6055 }
6056
6057 /* Schedule the QSFP work only if there is a cable attached. */
6058 if (qsfp_mod_present(ppd))
6059 queue_work(ppd->hfi1_wq, &ppd->qsfp_info.qsfp_work);
6060}
6061
6062static int request_host_lcb_access(struct hfi1_devdata *dd)
6063{
6064 int ret;
6065
6066 ret = do_8051_command(dd, HCMD_MISC,
17fb4f29
JJ		 6067 (u64)HCMD_MISC_REQUEST_LCB_ACCESS <<
6068 LOAD_DATA_FIELD_ID_SHIFT, NULL);
77241056
MM		 6069 if (ret != HCMD_SUCCESS) {
6070 dd_dev_err(dd, "%s: command failed with error %d\n",
17fb4f29 6071 __func__, ret);
77241056
MM		 6072 }
6073 return ret == HCMD_SUCCESS ? 0 : -EBUSY;
6074}
6075
6076static int request_8051_lcb_access(struct hfi1_devdata *dd)
6077{
6078 int ret;
6079
6080 ret = do_8051_command(dd, HCMD_MISC,
17fb4f29
JJ		 6081 (u64)HCMD_MISC_GRANT_LCB_ACCESS <<
6082 LOAD_DATA_FIELD_ID_SHIFT, NULL);
77241056
MM		 6083 if (ret != HCMD_SUCCESS) {
6084 dd_dev_err(dd, "%s: command failed with error %d\n",
17fb4f29 6085 __func__, ret);
77241056
MM		 6086 }
6087 return ret == HCMD_SUCCESS ? 0 : -EBUSY;
6088}
6089
6090/*
6091 * Set the LCB selector - allow host access. The DCC selector always
6092 * points to the host.
6093 */
6094static inline void set_host_lcb_access(struct hfi1_devdata *dd)
6095{
6096 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
17fb4f29
JJ		 6097 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK |
6098 DC_DC8051_CFG_CSR_ACCESS_SEL_LCB_SMASK);
77241056
MM		 6099}
6100
6101/*
6102 * Clear the LCB selector - allow 8051 access. The DCC selector always
6103 * points to the host.
6104 */
6105static inline void set_8051_lcb_access(struct hfi1_devdata *dd)
6106{
6107 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
17fb4f29 6108 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK);
77241056
MM		 6109}
6110
6111/*
6112 * Acquire LCB access from the 8051. If the host already has access,
6113 * just increment a counter. Otherwise, inform the 8051 that the
6114 * host is taking access.
6115 *
6116 * Returns:
6117 * 0 on success
6118 * -EBUSY if the 8051 has control and cannot be disturbed
6119 * -errno if unable to acquire access from the 8051
6120 */
6121int acquire_lcb_access(struct hfi1_devdata *dd, int sleep_ok)
6122{
6123 struct hfi1_pportdata *ppd = dd->pport;
6124 int ret = 0;
6125
6126 /*
6127 * Use the host link state lock so the operation of this routine
6128 * { link state check, selector change, count increment } can occur
6129 * as a unit against a link state change. Otherwise there is a
6130 * race between the state change and the count increment.
6131 */
6132 if (sleep_ok) {
6133 mutex_lock(&ppd->hls_lock);
6134 } else {
951842b0 6135 while (!mutex_trylock(&ppd->hls_lock))
77241056
MM		 6136 udelay(1);
6137 }
6138
6139 /* this access is valid only when the link is up */
0c7f77af 6140 if (ppd->host_link_state & HLS_DOWN) {
77241056 6141 dd_dev_info(dd, "%s: link state %s not up\n",
17fb4f29 6142 __func__, link_state_name(ppd->host_link_state));
77241056
MM		 6143 ret = -EBUSY;
6144 goto done;
6145 }
6146
6147 if (dd->lcb_access_count == 0) {
6148 ret = request_host_lcb_access(dd);
6149 if (ret) {
6150 dd_dev_err(dd,
17fb4f29
JJ		 6151 "%s: unable to acquire LCB access, err %d\n",
6152 __func__, ret);
77241056
MM		 6153 goto done;
6154 }
6155 set_host_lcb_access(dd);
6156 }
6157 dd->lcb_access_count++;
6158done:
6159 mutex_unlock(&ppd->hls_lock);
6160 return ret;
6161}
6162
6163/*
6164 * Release LCB access by decrementing the use count. If the count is moving
6165 * from 1 to 0, inform 8051 that it has control back.
6166 *
6167 * Returns:
6168 * 0 on success
6169 * -errno if unable to release access to the 8051
6170 */
6171int release_lcb_access(struct hfi1_devdata *dd, int sleep_ok)
6172{
6173 int ret = 0;
6174
6175 /*
6176 * Use the host link state lock because the acquire needed it.
6177 * Here, we only need to keep { selector change, count decrement }
6178 * as a unit.
6179 */
6180 if (sleep_ok) {
6181 mutex_lock(&dd->pport->hls_lock);
6182 } else {
951842b0 6183 while (!mutex_trylock(&dd->pport->hls_lock))
77241056
MM		 6184 udelay(1);
6185 }
6186
6187 if (dd->lcb_access_count == 0) {
6188 dd_dev_err(dd, "%s: LCB access count is zero. Skipping.\n",
17fb4f29 6189 __func__);
77241056
MM		 6190 goto done;
6191 }
6192
6193 if (dd->lcb_access_count == 1) {
6194 set_8051_lcb_access(dd);
6195 ret = request_8051_lcb_access(dd);
6196 if (ret) {
6197 dd_dev_err(dd,
17fb4f29
JJ		 6198 "%s: unable to release LCB access, err %d\n",
6199 __func__, ret);
77241056
MM		 6200 /* restore host access if the grant didn't work */
6201 set_host_lcb_access(dd);
6202 goto done;
6203 }
6204 }
6205 dd->lcb_access_count--;
6206done:
6207 mutex_unlock(&dd->pport->hls_lock);
6208 return ret;
6209}
6210
6211/*
6212 * Initialize LCB access variables and state. Called during driver load,
6213 * after most of the initialization is finished.
6214 *
6215 * The DC default is LCB access on for the host. The driver defaults to
6216 * leaving access to the 8051. Assign access now - this constrains the call
6217 * to this routine to be after all LCB set-up is done. In particular, after
6218 * hf1_init_dd() -> set_up_interrupts() -> clear_all_interrupts()
6219 */
6220static void init_lcb_access(struct hfi1_devdata *dd)
6221{
6222 dd->lcb_access_count = 0;
6223}
6224
6225/*
6226 * Write a response back to a 8051 request.
6227 */
6228static void hreq_response(struct hfi1_devdata *dd, u8 return_code, u16 rsp_data)
6229{
6230 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0,
17fb4f29
JJ		 6231 DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK |
6232 (u64)return_code <<
6233 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT |
6234 (u64)rsp_data << DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT);
77241056
MM		 6235}
6236
6237/*
cbac386a 6238 * Handle host requests from the 8051.
77241056 6239 */
145dd2b3 6240static void handle_8051_request(struct hfi1_pportdata *ppd)
77241056 6241{
cbac386a 6242 struct hfi1_devdata *dd = ppd->dd;
77241056 6243 u64 reg;
cbac386a 6244 u16 data = 0;
145dd2b3 6245 u8 type;
77241056
MM		 6246
6247 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_1);
6248 if ((reg & DC_DC8051_CFG_EXT_DEV_1_REQ_NEW_SMASK) == 0)
6249 return; /* no request */
6250
6251 /* zero out COMPLETED so the response is seen */
6252 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 0);
6253
6254 /* extract request details */
6255 type = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_SHIFT)
6256 & DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_MASK;
6257 data = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT)
6258 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_MASK;
6259
6260 switch (type) {
6261 case HREQ_LOAD_CONFIG:
6262 case HREQ_SAVE_CONFIG:
6263 case HREQ_READ_CONFIG:
6264 case HREQ_SET_TX_EQ_ABS:
6265 case HREQ_SET_TX_EQ_REL:
145dd2b3 6266 case HREQ_ENABLE:
77241056 6267 dd_dev_info(dd, "8051 request: request 0x%x not supported\n",
17fb4f29 6268 type);
77241056
MM		 6269 hreq_response(dd, HREQ_NOT_SUPPORTED, 0);
6270 break;
77241056
MM		 6271 case HREQ_CONFIG_DONE:
6272 hreq_response(dd, HREQ_SUCCESS, 0);
6273 break;
6274
6275 case HREQ_INTERFACE_TEST:
6276 hreq_response(dd, HREQ_SUCCESS, data);
6277 break;
77241056
MM		 6278 default:
6279 dd_dev_err(dd, "8051 request: unknown request 0x%x\n", type);
6280 hreq_response(dd, HREQ_NOT_SUPPORTED, 0);
6281 break;
6282 }
6283}
6284
6285static void write_global_credit(struct hfi1_devdata *dd,
6286 u8 vau, u16 total, u16 shared)
6287{
6288 write_csr(dd, SEND_CM_GLOBAL_CREDIT,
17fb4f29
JJ		 6289 ((u64)total <<
6290 SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT) |
6291 ((u64)shared <<
6292 SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT) |
6293 ((u64)vau << SEND_CM_GLOBAL_CREDIT_AU_SHIFT));
77241056
MM		 6294}
6295
6296/*
6297 * Set up initial VL15 credits of the remote. Assumes the rest of
6298 * the CM credit registers are zero from a previous global or credit reset .
6299 */
6300void set_up_vl15(struct hfi1_devdata *dd, u8 vau, u16 vl15buf)
6301{
6302 /* leave shared count at zero for both global and VL15 */
6303 write_global_credit(dd, vau, vl15buf, 0);
6304
eacc830f
DD		 6305 write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf
6306 << SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT);
77241056
MM		 6307}
6308
6309/*
6310 * Zero all credit details from the previous connection and
6311 * reset the CM manager's internal counters.
6312 */
6313void reset_link_credits(struct hfi1_devdata *dd)
6314{
6315 int i;
6316
6317 /* remove all previous VL credit limits */
6318 for (i = 0; i < TXE_NUM_DATA_VL; i++)
8638b77f 6319 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
77241056
MM		 6320 write_csr(dd, SEND_CM_CREDIT_VL15, 0);
6321 write_global_credit(dd, 0, 0, 0);
6322 /* reset the CM block */
6323 pio_send_control(dd, PSC_CM_RESET);
6324}
6325
6326/* convert a vCU to a CU */
6327static u32 vcu_to_cu(u8 vcu)
6328{
6329 return 1 << vcu;
6330}
6331
6332/* convert a CU to a vCU */
6333static u8 cu_to_vcu(u32 cu)
6334{
6335 return ilog2(cu);
6336}
6337
6338/* convert a vAU to an AU */
6339static u32 vau_to_au(u8 vau)
6340{
6341 return 8 * (1 << vau);
6342}
6343
6344static void set_linkup_defaults(struct hfi1_pportdata *ppd)
6345{
6346 ppd->sm_trap_qp = 0x0;
6347 ppd->sa_qp = 0x1;
6348}
6349
6350/*
6351 * Graceful LCB shutdown. This leaves the LCB FIFOs in reset.
6352 */
6353static void lcb_shutdown(struct hfi1_devdata *dd, int abort)
6354{
6355 u64 reg;
6356
6357 /* clear lcb run: LCB_CFG_RUN.EN = 0 */
6358 write_csr(dd, DC_LCB_CFG_RUN, 0);
6359 /* set tx fifo reset: LCB_CFG_TX_FIFOS_RESET.VAL = 1 */
6360 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET,
17fb4f29 6361 1ull << DC_LCB_CFG_TX_FIFOS_RESET_VAL_SHIFT);
77241056
MM		 6362 /* set dcc reset csr: DCC_CFG_RESET.{reset_lcb,reset_rx_fpe} = 1 */
6363 dd->lcb_err_en = read_csr(dd, DC_LCB_ERR_EN);
6364 reg = read_csr(dd, DCC_CFG_RESET);
17fb4f29
JJ		 6365 write_csr(dd, DCC_CFG_RESET, reg |
6366 (1ull << DCC_CFG_RESET_RESET_LCB_SHIFT) |
6367 (1ull << DCC_CFG_RESET_RESET_RX_FPE_SHIFT));
50e5dcbe 6368 (void)read_csr(dd, DCC_CFG_RESET); /* make sure the write completed */
77241056
MM		 6369 if (!abort) {
6370 udelay(1); /* must hold for the longer of 16cclks or 20ns */
6371 write_csr(dd, DCC_CFG_RESET, reg);
6372 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
6373 }
6374}
6375
6376/*
6377 * This routine should be called after the link has been transitioned to
6378 * OFFLINE (OFFLINE state has the side effect of putting the SerDes into
6379 * reset).
6380 *
6381 * The expectation is that the caller of this routine would have taken
6382 * care of properly transitioning the link into the correct state.
6383 */
6384static void dc_shutdown(struct hfi1_devdata *dd)
6385{
6386 unsigned long flags;
6387
6388 spin_lock_irqsave(&dd->dc8051_lock, flags);
6389 if (dd->dc_shutdown) {
6390 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
6391 return;
6392 }
6393 dd->dc_shutdown = 1;
6394 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
6395 /* Shutdown the LCB */
6396 lcb_shutdown(dd, 1);
4d114fdd
JJ		 6397 /*
6398 * Going to OFFLINE would have causes the 8051 to put the
77241056 6399 * SerDes into reset already. Just need to shut down the 8051,
4d114fdd
JJ		 6400 * itself.
6401 */
77241056
MM		 6402 write_csr(dd, DC_DC8051_CFG_RST, 0x1);
6403}
6404
4d114fdd
JJ		 6405/*
6406 * Calling this after the DC has been brought out of reset should not
6407 * do any damage.
6408 */
77241056
MM		 6409static void dc_start(struct hfi1_devdata *dd)
6410{
6411 unsigned long flags;
6412 int ret;
6413
6414 spin_lock_irqsave(&dd->dc8051_lock, flags);
6415 if (!dd->dc_shutdown)
6416 goto done;
6417 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
6418 /* Take the 8051 out of reset */
6419 write_csr(dd, DC_DC8051_CFG_RST, 0ull);
6420 /* Wait until 8051 is ready */
6421 ret = wait_fm_ready(dd, TIMEOUT_8051_START);
6422 if (ret) {
6423 dd_dev_err(dd, "%s: timeout starting 8051 firmware\n",
17fb4f29 6424 __func__);
77241056
MM		 6425 }
6426 /* Take away reset for LCB and RX FPE (set in lcb_shutdown). */
6427 write_csr(dd, DCC_CFG_RESET, 0x10);
6428 /* lcb_shutdown() with abort=1 does not restore these */
6429 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
6430 spin_lock_irqsave(&dd->dc8051_lock, flags);
6431 dd->dc_shutdown = 0;
6432done:
6433 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
6434}
6435
6436/*
6437 * These LCB adjustments are for the Aurora SerDes core in the FPGA.
6438 */
6439static void adjust_lcb_for_fpga_serdes(struct hfi1_devdata *dd)
6440{
6441 u64 rx_radr, tx_radr;
6442 u32 version;
6443
6444 if (dd->icode != ICODE_FPGA_EMULATION)
6445 return;
6446
6447 /*
6448 * These LCB defaults on emulator _s are good, nothing to do here:
6449 * LCB_CFG_TX_FIFOS_RADR
6450 * LCB_CFG_RX_FIFOS_RADR
6451 * LCB_CFG_LN_DCLK
6452 * LCB_CFG_IGNORE_LOST_RCLK
6453 */
6454 if (is_emulator_s(dd))
6455 return;
6456 /* else this is _p */
6457
6458 version = emulator_rev(dd);
995deafa 6459 if (!is_ax(dd))
77241056
MM		 6460 version = 0x2d; /* all B0 use 0x2d or higher settings */
6461
6462 if (version <= 0x12) {
6463 /* release 0x12 and below */
6464
6465 /*
6466 * LCB_CFG_RX_FIFOS_RADR.RST_VAL = 0x9
6467 * LCB_CFG_RX_FIFOS_RADR.OK_TO_JUMP_VAL = 0x9
6468 * LCB_CFG_RX_FIFOS_RADR.DO_NOT_JUMP_VAL = 0xa
6469 */
6470 rx_radr =
6471 0xaull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6472 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6473 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6474 /*
6475 * LCB_CFG_TX_FIFOS_RADR.ON_REINIT = 0 (default)
6476 * LCB_CFG_TX_FIFOS_RADR.RST_VAL = 6
6477 */
6478 tx_radr = 6ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6479 } else if (version <= 0x18) {
6480 /* release 0x13 up to 0x18 */
6481 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6482 rx_radr =
6483 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6484 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6485 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6486 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6487 } else if (version == 0x19) {
6488 /* release 0x19 */
6489 /* LCB_CFG_RX_FIFOS_RADR = 0xa99 */
6490 rx_radr =
6491 0xAull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6492 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6493 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6494 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6495 } else if (version == 0x1a) {
6496 /* release 0x1a */
6497 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6498 rx_radr =
6499 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6500 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6501 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6502 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6503 write_csr(dd, DC_LCB_CFG_LN_DCLK, 1ull);
6504 } else {
6505 /* release 0x1b and higher */
6506 /* LCB_CFG_RX_FIFOS_RADR = 0x877 */
6507 rx_radr =
6508 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6509 | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6510 | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6511 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6512 }
6513
6514 write_csr(dd, DC_LCB_CFG_RX_FIFOS_RADR, rx_radr);
6515 /* LCB_CFG_IGNORE_LOST_RCLK.EN = 1 */
6516 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK,
17fb4f29 6517 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK);
77241056
MM		 6518 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RADR, tx_radr);
6519}
6520
6521/*
6522 * Handle a SMA idle message
6523 *
6524 * This is a work-queue function outside of the interrupt.
6525 */
6526void handle_sma_message(struct work_struct *work)
6527{
6528 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6529 sma_message_work);
6530 struct hfi1_devdata *dd = ppd->dd;
6531 u64 msg;
6532 int ret;
6533
4d114fdd
JJ		 6534 /*
6535 * msg is bytes 1-4 of the 40-bit idle message - the command code
6536 * is stripped off
6537 */
77241056
MM		 6538 ret = read_idle_sma(dd, &msg);
6539 if (ret)
6540 return;
6541 dd_dev_info(dd, "%s: SMA message 0x%llx\n", __func__, msg);
6542 /*
6543 * React to the SMA message. Byte[1] (0 for us) is the command.
6544 */
6545 switch (msg & 0xff) {
6546 case SMA_IDLE_ARM:
6547 /*
6548 * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6549 * State Transitions
6550 *
6551 * Only expected in INIT or ARMED, discard otherwise.
6552 */
6553 if (ppd->host_link_state & (HLS_UP_INIT | HLS_UP_ARMED))
6554 ppd->neighbor_normal = 1;
6555 break;
6556 case SMA_IDLE_ACTIVE:
6557 /*
6558 * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6559 * State Transitions
6560 *
6561 * Can activate the node. Discard otherwise.
6562 */
d0d236ea
JJ		 6563 if (ppd->host_link_state == HLS_UP_ARMED &&
6564 ppd->is_active_optimize_enabled) {
77241056
MM		 6565 ppd->neighbor_normal = 1;
6566 ret = set_link_state(ppd, HLS_UP_ACTIVE);
6567 if (ret)
6568 dd_dev_err(
6569 dd,
6570 "%s: received Active SMA idle message, couldn't set link to Active\n",
6571 __func__);
6572 }
6573 break;
6574 default:
6575 dd_dev_err(dd,
17fb4f29
JJ		 6576 "%s: received unexpected SMA idle message 0x%llx\n",
6577 __func__, msg);
77241056
MM		 6578 break;
6579 }
6580}
6581
6582static void adjust_rcvctrl(struct hfi1_devdata *dd, u64 add, u64 clear)
6583{
6584 u64 rcvctrl;
6585 unsigned long flags;
6586
6587 spin_lock_irqsave(&dd->rcvctrl_lock, flags);
6588 rcvctrl = read_csr(dd, RCV_CTRL);
6589 rcvctrl |= add;
6590 rcvctrl &= ~clear;
6591 write_csr(dd, RCV_CTRL, rcvctrl);
6592 spin_unlock_irqrestore(&dd->rcvctrl_lock, flags);
6593}
6594
6595static inline void add_rcvctrl(struct hfi1_devdata *dd, u64 add)
6596{
6597 adjust_rcvctrl(dd, add, 0);
6598}
6599
6600static inline void clear_rcvctrl(struct hfi1_devdata *dd, u64 clear)
6601{
6602 adjust_rcvctrl(dd, 0, clear);
6603}
6604
6605/*
6606 * Called from all interrupt handlers to start handling an SPC freeze.
6607 */
6608void start_freeze_handling(struct hfi1_pportdata *ppd, int flags)
6609{
6610 struct hfi1_devdata *dd = ppd->dd;
6611 struct send_context *sc;
6612 int i;
6613
6614 if (flags & FREEZE_SELF)
6615 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
6616
6617 /* enter frozen mode */
6618 dd->flags |= HFI1_FROZEN;
6619
6620 /* notify all SDMA engines that they are going into a freeze */
6621 sdma_freeze_notify(dd, !!(flags & FREEZE_LINK_DOWN));
6622
6623 /* do halt pre-handling on all enabled send contexts */
6624 for (i = 0; i < dd->num_send_contexts; i++) {
6625 sc = dd->send_contexts[i].sc;
6626 if (sc && (sc->flags & SCF_ENABLED))
6627 sc_stop(sc, SCF_FROZEN | SCF_HALTED);
6628 }
6629
6630 /* Send context are frozen. Notify user space */
6631 hfi1_set_uevent_bits(ppd, _HFI1_EVENT_FROZEN_BIT);
6632
6633 if (flags & FREEZE_ABORT) {
6634 dd_dev_err(dd,
6635 "Aborted freeze recovery. Please REBOOT system\n");
6636 return;
6637 }
6638 /* queue non-interrupt handler */
6639 queue_work(ppd->hfi1_wq, &ppd->freeze_work);
6640}
6641
6642/*
6643 * Wait until all 4 sub-blocks indicate that they have frozen or unfrozen,
6644 * depending on the "freeze" parameter.
6645 *
6646 * No need to return an error if it times out, our only option
6647 * is to proceed anyway.
6648 */
6649static void wait_for_freeze_status(struct hfi1_devdata *dd, int freeze)
6650{
6651 unsigned long timeout;
6652 u64 reg;
6653
6654 timeout = jiffies + msecs_to_jiffies(FREEZE_STATUS_TIMEOUT);
6655 while (1) {
6656 reg = read_csr(dd, CCE_STATUS);
6657 if (freeze) {
6658 /* waiting until all indicators are set */
6659 if ((reg & ALL_FROZE) == ALL_FROZE)
6660 return; /* all done */
6661 } else {
6662 /* waiting until all indicators are clear */
6663 if ((reg & ALL_FROZE) == 0)
6664 return; /* all done */
6665 }
6666
6667 if (time_after(jiffies, timeout)) {
6668 dd_dev_err(dd,
17fb4f29
JJ		 6669 "Time out waiting for SPC %sfreeze, bits 0x%llx, expecting 0x%llx, continuing",
6670 freeze ? "" : "un", reg & ALL_FROZE,
6671 freeze ? ALL_FROZE : 0ull);
77241056
MM		 6672 return;
6673 }
6674 usleep_range(80, 120);
6675 }
6676}
6677
6678/*
6679 * Do all freeze handling for the RXE block.
6680 */
6681static void rxe_freeze(struct hfi1_devdata *dd)
6682{
6683 int i;
6684
6685 /* disable port */
6686 clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
6687
6688 /* disable all receive contexts */
6689 for (i = 0; i < dd->num_rcv_contexts; i++)
6690 hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS, i);
6691}
6692
6693/*
6694 * Unfreeze handling for the RXE block - kernel contexts only.
6695 * This will also enable the port. User contexts will do unfreeze
6696 * handling on a per-context basis as they call into the driver.
6697 *
6698 */
6699static void rxe_kernel_unfreeze(struct hfi1_devdata *dd)
6700{
566c157c 6701 u32 rcvmask;
77241056
MM		 6702 int i;
6703
6704 /* enable all kernel contexts */
566c157c
MH		 6705 for (i = 0; i < dd->n_krcv_queues; i++) {
6706 rcvmask = HFI1_RCVCTRL_CTXT_ENB;
6707 /* HFI1_RCVCTRL_TAILUPD_[ENB|DIS] needs to be set explicitly */
6708 rcvmask |= HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, DMA_RTAIL) ?
6709 HFI1_RCVCTRL_TAILUPD_ENB : HFI1_RCVCTRL_TAILUPD_DIS;
6710 hfi1_rcvctrl(dd, rcvmask, i);
6711 }
77241056
MM		 6712
6713 /* enable port */
6714 add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
6715}
6716
6717/*
6718 * Non-interrupt SPC freeze handling.
6719 *
6720 * This is a work-queue function outside of the triggering interrupt.
6721 */
6722void handle_freeze(struct work_struct *work)
6723{
6724 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6725 freeze_work);
6726 struct hfi1_devdata *dd = ppd->dd;
6727
6728 /* wait for freeze indicators on all affected blocks */
77241056
MM		 6729 wait_for_freeze_status(dd, 1);
6730
6731 /* SPC is now frozen */
6732
6733 /* do send PIO freeze steps */
6734 pio_freeze(dd);
6735
6736 /* do send DMA freeze steps */
6737 sdma_freeze(dd);
6738
6739 /* do send egress freeze steps - nothing to do */
6740
6741 /* do receive freeze steps */
6742 rxe_freeze(dd);
6743
6744 /*
6745 * Unfreeze the hardware - clear the freeze, wait for each
6746 * block's frozen bit to clear, then clear the frozen flag.
6747 */
6748 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
6749 wait_for_freeze_status(dd, 0);
6750
995deafa 6751 if (is_ax(dd)) {
77241056
MM		 6752 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
6753 wait_for_freeze_status(dd, 1);
6754 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
6755 wait_for_freeze_status(dd, 0);
6756 }
6757
6758 /* do send PIO unfreeze steps for kernel contexts */
6759 pio_kernel_unfreeze(dd);
6760
6761 /* do send DMA unfreeze steps */
6762 sdma_unfreeze(dd);
6763
6764 /* do send egress unfreeze steps - nothing to do */
6765
6766 /* do receive unfreeze steps for kernel contexts */
6767 rxe_kernel_unfreeze(dd);
6768
6769 /*
6770 * The unfreeze procedure touches global device registers when
6771 * it disables and re-enables RXE. Mark the device unfrozen
6772 * after all that is done so other parts of the driver waiting
6773 * for the device to unfreeze don't do things out of order.
6774 *
6775 * The above implies that the meaning of HFI1_FROZEN flag is
6776 * "Device has gone into freeze mode and freeze mode handling
6777 * is still in progress."
6778 *
6779 * The flag will be removed when freeze mode processing has
6780 * completed.
6781 */
6782 dd->flags &= ~HFI1_FROZEN;
6783 wake_up(&dd->event_queue);
6784
6785 /* no longer frozen */
77241056
MM		 6786}
6787
6788/*
6789 * Handle a link up interrupt from the 8051.
6790 *
6791 * This is a work-queue function outside of the interrupt.
6792 */
6793void handle_link_up(struct work_struct *work)
6794{
6795 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
17fb4f29 6796 link_up_work);
77241056
MM		 6797 set_link_state(ppd, HLS_UP_INIT);
6798
6799 /* cache the read of DC_LCB_STS_ROUND_TRIP_LTP_CNT */
6800 read_ltp_rtt(ppd->dd);
6801 /*
6802 * OPA specifies that certain counters are cleared on a transition
6803 * to link up, so do that.
6804 */
6805 clear_linkup_counters(ppd->dd);
6806 /*
6807 * And (re)set link up default values.
6808 */
6809 set_linkup_defaults(ppd);
6810
6811 /* enforce link speed enabled */
6812 if ((ppd->link_speed_active & ppd->link_speed_enabled) == 0) {
6813 /* oops - current speed is not enabled, bounce */
6814 dd_dev_err(ppd->dd,
17fb4f29
JJ		 6815 "Link speed active 0x%x is outside enabled 0x%x, downing link\n",
6816 ppd->link_speed_active, ppd->link_speed_enabled);
77241056 6817 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_SPEED_POLICY, 0,
17fb4f29 6818 OPA_LINKDOWN_REASON_SPEED_POLICY);
77241056
MM		 6819 set_link_state(ppd, HLS_DN_OFFLINE);
6820 start_link(ppd);
6821 }
6822}
6823
4d114fdd
JJ		 6824/*
6825 * Several pieces of LNI information were cached for SMA in ppd.
6826 * Reset these on link down
6827 */
77241056
MM		 6828static void reset_neighbor_info(struct hfi1_pportdata *ppd)
6829{
6830 ppd->neighbor_guid = 0;
6831 ppd->neighbor_port_number = 0;
6832 ppd->neighbor_type = 0;
6833 ppd->neighbor_fm_security = 0;
6834}
6835
feb831dd
DL		 6836static const char * const link_down_reason_strs[] = {
6837 [OPA_LINKDOWN_REASON_NONE] = "None",
6838 [OPA_LINKDOWN_REASON_RCV_ERROR_0] = "Recive error 0",
6839 [OPA_LINKDOWN_REASON_BAD_PKT_LEN] = "Bad packet length",
6840 [OPA_LINKDOWN_REASON_PKT_TOO_LONG] = "Packet too long",
6841 [OPA_LINKDOWN_REASON_PKT_TOO_SHORT] = "Packet too short",
6842 [OPA_LINKDOWN_REASON_BAD_SLID] = "Bad SLID",
6843 [OPA_LINKDOWN_REASON_BAD_DLID] = "Bad DLID",
6844 [OPA_LINKDOWN_REASON_BAD_L2] = "Bad L2",
6845 [OPA_LINKDOWN_REASON_BAD_SC] = "Bad SC",
6846 [OPA_LINKDOWN_REASON_RCV_ERROR_8] = "Receive error 8",
6847 [OPA_LINKDOWN_REASON_BAD_MID_TAIL] = "Bad mid tail",
6848 [OPA_LINKDOWN_REASON_RCV_ERROR_10] = "Receive error 10",
6849 [OPA_LINKDOWN_REASON_PREEMPT_ERROR] = "Preempt error",
6850 [OPA_LINKDOWN_REASON_PREEMPT_VL15] = "Preempt vl15",
6851 [OPA_LINKDOWN_REASON_BAD_VL_MARKER] = "Bad VL marker",
6852 [OPA_LINKDOWN_REASON_RCV_ERROR_14] = "Receive error 14",
6853 [OPA_LINKDOWN_REASON_RCV_ERROR_15] = "Receive error 15",
6854 [OPA_LINKDOWN_REASON_BAD_HEAD_DIST] = "Bad head distance",
6855 [OPA_LINKDOWN_REASON_BAD_TAIL_DIST] = "Bad tail distance",
6856 [OPA_LINKDOWN_REASON_BAD_CTRL_DIST] = "Bad control distance",
6857 [OPA_LINKDOWN_REASON_BAD_CREDIT_ACK] = "Bad credit ack",
6858 [OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER] = "Unsupported VL marker",
6859 [OPA_LINKDOWN_REASON_BAD_PREEMPT] = "Bad preempt",
6860 [OPA_LINKDOWN_REASON_BAD_CONTROL_FLIT] = "Bad control flit",
6861 [OPA_LINKDOWN_REASON_EXCEED_MULTICAST_LIMIT] = "Exceed multicast limit",
6862 [OPA_LINKDOWN_REASON_RCV_ERROR_24] = "Receive error 24",
6863 [OPA_LINKDOWN_REASON_RCV_ERROR_25] = "Receive error 25",
6864 [OPA_LINKDOWN_REASON_RCV_ERROR_26] = "Receive error 26",
6865 [OPA_LINKDOWN_REASON_RCV_ERROR_27] = "Receive error 27",
6866 [OPA_LINKDOWN_REASON_RCV_ERROR_28] = "Receive error 28",
6867 [OPA_LINKDOWN_REASON_RCV_ERROR_29] = "Receive error 29",
6868 [OPA_LINKDOWN_REASON_RCV_ERROR_30] = "Receive error 30",
6869 [OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN] =
6870 "Excessive buffer overrun",
6871 [OPA_LINKDOWN_REASON_UNKNOWN] = "Unknown",
6872 [OPA_LINKDOWN_REASON_REBOOT] = "Reboot",
6873 [OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN] = "Neighbor unknown",
6874 [OPA_LINKDOWN_REASON_FM_BOUNCE] = "FM bounce",
6875 [OPA_LINKDOWN_REASON_SPEED_POLICY] = "Speed policy",
6876 [OPA_LINKDOWN_REASON_WIDTH_POLICY] = "Width policy",
6877 [OPA_LINKDOWN_REASON_DISCONNECTED] = "Disconnected",
6878 [OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED] =
6879 "Local media not installed",
6880 [OPA_LINKDOWN_REASON_NOT_INSTALLED] = "Not installed",
6881 [OPA_LINKDOWN_REASON_CHASSIS_CONFIG] = "Chassis config",
6882 [OPA_LINKDOWN_REASON_END_TO_END_NOT_INSTALLED] =
6883 "End to end not installed",
6884 [OPA_LINKDOWN_REASON_POWER_POLICY] = "Power policy",
6885 [OPA_LINKDOWN_REASON_LINKSPEED_POLICY] = "Link speed policy",
6886 [OPA_LINKDOWN_REASON_LINKWIDTH_POLICY] = "Link width policy",
6887 [OPA_LINKDOWN_REASON_SWITCH_MGMT] = "Switch management",
6888 [OPA_LINKDOWN_REASON_SMA_DISABLED] = "SMA disabled",
6889 [OPA_LINKDOWN_REASON_TRANSIENT] = "Transient"
6890};
6891
6892/* return the neighbor link down reason string */
6893static const char *link_down_reason_str(u8 reason)
6894{
6895 const char *str = NULL;
6896
6897 if (reason < ARRAY_SIZE(link_down_reason_strs))
6898 str = link_down_reason_strs[reason];
6899 if (!str)
6900 str = "(invalid)";
6901
6902 return str;
6903}
6904
77241056
MM		 6905/*
6906 * Handle a link down interrupt from the 8051.
6907 *
6908 * This is a work-queue function outside of the interrupt.
6909 */
6910void handle_link_down(struct work_struct *work)
6911{
6912 u8 lcl_reason, neigh_reason = 0;
feb831dd 6913 u8 link_down_reason;
77241056 6914 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
feb831dd
DL		 6915 link_down_work);
6916 int was_up;
6917 static const char ldr_str[] = "Link down reason: ";
77241056 6918
8ebd4cf1
EH		 6919 if ((ppd->host_link_state &
6920 (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) &&
6921 ppd->port_type == PORT_TYPE_FIXED)
6922 ppd->offline_disabled_reason =
6923 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NOT_INSTALLED);
6924
6925 /* Go offline first, then deal with reading/writing through 8051 */
feb831dd 6926 was_up = !!(ppd->host_link_state & HLS_UP);
77241056
MM		 6927 set_link_state(ppd, HLS_DN_OFFLINE);
6928
feb831dd
DL		 6929 if (was_up) {
6930 lcl_reason = 0;
6931 /* link down reason is only valid if the link was up */
6932 read_link_down_reason(ppd->dd, &link_down_reason);
6933 switch (link_down_reason) {
6934 case LDR_LINK_TRANSFER_ACTIVE_LOW:
6935 /* the link went down, no idle message reason */
6936 dd_dev_info(ppd->dd, "%sUnexpected link down\n",
6937 ldr_str);
6938 break;
6939 case LDR_RECEIVED_LINKDOWN_IDLE_MSG:
6940 /*
6941 * The neighbor reason is only valid if an idle message
6942 * was received for it.
6943 */
6944 read_planned_down_reason_code(ppd->dd, &neigh_reason);
6945 dd_dev_info(ppd->dd,
6946 "%sNeighbor link down message %d, %s\n",
6947 ldr_str, neigh_reason,
6948 link_down_reason_str(neigh_reason));
6949 break;
6950 case LDR_RECEIVED_HOST_OFFLINE_REQ:
6951 dd_dev_info(ppd->dd,
6952 "%sHost requested link to go offline\n",
6953 ldr_str);
6954 break;
6955 default:
6956 dd_dev_info(ppd->dd, "%sUnknown reason 0x%x\n",
6957 ldr_str, link_down_reason);
6958 break;
6959 }
77241056 6960
feb831dd
DL		 6961 /*
6962 * If no reason, assume peer-initiated but missed
6963 * LinkGoingDown idle flits.
6964 */
6965 if (neigh_reason == 0)
6966 lcl_reason = OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN;
6967 } else {
6968 /* went down while polling or going up */
6969 lcl_reason = OPA_LINKDOWN_REASON_TRANSIENT;
6970 }
77241056
MM		 6971
6972 set_link_down_reason(ppd, lcl_reason, neigh_reason, 0);
6973
015e91fb
DL		 6974 /* inform the SMA when the link transitions from up to down */
6975 if (was_up && ppd->local_link_down_reason.sma == 0 &&
6976 ppd->neigh_link_down_reason.sma == 0) {
6977 ppd->local_link_down_reason.sma =
6978 ppd->local_link_down_reason.latest;
6979 ppd->neigh_link_down_reason.sma =
6980 ppd->neigh_link_down_reason.latest;
6981 }
6982
77241056
MM		 6983 reset_neighbor_info(ppd);
6984
6985 /* disable the port */
6986 clear_rcvctrl(ppd->dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
6987
4d114fdd
JJ		 6988 /*
6989 * If there is no cable attached, turn the DC off. Otherwise,
6990 * start the link bring up.
6991 */
0db9dec2 6992 if (ppd->port_type == PORT_TYPE_QSFP && !qsfp_mod_present(ppd))
77241056 6993 dc_shutdown(ppd->dd);
0db9dec2 6994 else
77241056
MM		 6995 start_link(ppd);
6996}
6997
6998void handle_link_bounce(struct work_struct *work)
6999{
7000 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7001 link_bounce_work);
7002
7003 /*
7004 * Only do something if the link is currently up.
7005 */
7006 if (ppd->host_link_state & HLS_UP) {
7007 set_link_state(ppd, HLS_DN_OFFLINE);
7008 start_link(ppd);
7009 } else {
7010 dd_dev_info(ppd->dd, "%s: link not up (%s), nothing to do\n",
17fb4f29 7011 __func__, link_state_name(ppd->host_link_state));
77241056
MM		 7012 }
7013}
7014
7015/*
7016 * Mask conversion: Capability exchange to Port LTP. The capability
7017 * exchange has an implicit 16b CRC that is mandatory.
7018 */
7019static int cap_to_port_ltp(int cap)
7020{
7021 int port_ltp = PORT_LTP_CRC_MODE_16; /* this mode is mandatory */
7022
7023 if (cap & CAP_CRC_14B)
7024 port_ltp |= PORT_LTP_CRC_MODE_14;
7025 if (cap & CAP_CRC_48B)
7026 port_ltp |= PORT_LTP_CRC_MODE_48;
7027 if (cap & CAP_CRC_12B_16B_PER_LANE)
7028 port_ltp |= PORT_LTP_CRC_MODE_PER_LANE;
7029
7030 return port_ltp;
7031}
7032
7033/*
7034 * Convert an OPA Port LTP mask to capability mask
7035 */
7036int port_ltp_to_cap(int port_ltp)
7037{
7038 int cap_mask = 0;
7039
7040 if (port_ltp & PORT_LTP_CRC_MODE_14)
7041 cap_mask |= CAP_CRC_14B;
7042 if (port_ltp & PORT_LTP_CRC_MODE_48)
7043 cap_mask |= CAP_CRC_48B;
7044 if (port_ltp & PORT_LTP_CRC_MODE_PER_LANE)
7045 cap_mask |= CAP_CRC_12B_16B_PER_LANE;
7046
7047 return cap_mask;
7048}
7049
7050/*
7051 * Convert a single DC LCB CRC mode to an OPA Port LTP mask.
7052 */
7053static int lcb_to_port_ltp(int lcb_crc)
7054{
7055 int port_ltp = 0;
7056
7057 if (lcb_crc == LCB_CRC_12B_16B_PER_LANE)
7058 port_ltp = PORT_LTP_CRC_MODE_PER_LANE;
7059 else if (lcb_crc == LCB_CRC_48B)
7060 port_ltp = PORT_LTP_CRC_MODE_48;
7061 else if (lcb_crc == LCB_CRC_14B)
7062 port_ltp = PORT_LTP_CRC_MODE_14;
7063 else
7064 port_ltp = PORT_LTP_CRC_MODE_16;
7065
7066 return port_ltp;
7067}
7068
7069/*
7070 * Our neighbor has indicated that we are allowed to act as a fabric
7071 * manager, so place the full management partition key in the second
7072 * (0-based) pkey array position (see OPAv1, section 20.2.2.6.8). Note
7073 * that we should already have the limited management partition key in
7074 * array element 1, and also that the port is not yet up when
7075 * add_full_mgmt_pkey() is invoked.
7076 */
7077static void add_full_mgmt_pkey(struct hfi1_pportdata *ppd)
7078{
7079 struct hfi1_devdata *dd = ppd->dd;
7080
8764522e
DL		 7081 /* Sanity check - ppd->pkeys[2] should be 0, or already initalized */
7082 if (!((ppd->pkeys[2] == 0) || (ppd->pkeys[2] == FULL_MGMT_P_KEY)))
7083 dd_dev_warn(dd, "%s pkey[2] already set to 0x%x, resetting it to 0x%x\n",
7084 __func__, ppd->pkeys[2], FULL_MGMT_P_KEY);
77241056
MM		 7085 ppd->pkeys[2] = FULL_MGMT_P_KEY;
7086 (void)hfi1_set_ib_cfg(ppd, HFI1_IB_CFG_PKEYS, 0);
34d351f8 7087 hfi1_event_pkey_change(ppd->dd, ppd->port);
77241056
MM		 7088}
7089
3ec5fa28 7090static void clear_full_mgmt_pkey(struct hfi1_pportdata *ppd)
ce8b2fd0 7091{
3ec5fa28
SS		 7092 if (ppd->pkeys[2] != 0) {
7093 ppd->pkeys[2] = 0;
7094 (void)hfi1_set_ib_cfg(ppd, HFI1_IB_CFG_PKEYS, 0);
34d351f8 7095 hfi1_event_pkey_change(ppd->dd, ppd->port);
3ec5fa28 7096 }
ce8b2fd0
SS		 7097}
7098
77241056
MM		 7099/*
7100 * Convert the given link width to the OPA link width bitmask.
7101 */
7102static u16 link_width_to_bits(struct hfi1_devdata *dd, u16 width)
7103{
7104 switch (width) {
7105 case 0:
7106 /*
7107 * Simulator and quick linkup do not set the width.
7108 * Just set it to 4x without complaint.
7109 */
7110 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR || quick_linkup)
7111 return OPA_LINK_WIDTH_4X;
7112 return 0; /* no lanes up */
7113 case 1: return OPA_LINK_WIDTH_1X;
7114 case 2: return OPA_LINK_WIDTH_2X;
7115 case 3: return OPA_LINK_WIDTH_3X;
7116 default:
7117 dd_dev_info(dd, "%s: invalid width %d, using 4\n",
17fb4f29 7118 __func__, width);
77241056
MM		 7119 /* fall through */
7120 case 4: return OPA_LINK_WIDTH_4X;
7121 }
7122}
7123
7124/*
7125 * Do a population count on the bottom nibble.
7126 */
7127static const u8 bit_counts[16] = {
7128 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4
7129};
f4d507cd 7130
77241056
MM		 7131static inline u8 nibble_to_count(u8 nibble)
7132{
7133 return bit_counts[nibble & 0xf];
7134}
7135
7136/*
7137 * Read the active lane information from the 8051 registers and return
7138 * their widths.
7139 *
7140 * Active lane information is found in these 8051 registers:
7141 * enable_lane_tx
7142 * enable_lane_rx
7143 */
7144static void get_link_widths(struct hfi1_devdata *dd, u16 *tx_width,
7145 u16 *rx_width)
7146{
7147 u16 tx, rx;
7148 u8 enable_lane_rx;
7149 u8 enable_lane_tx;
7150 u8 tx_polarity_inversion;
7151 u8 rx_polarity_inversion;
7152 u8 max_rate;
7153
7154 /* read the active lanes */
7155 read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion,
17fb4f29 7156 &rx_polarity_inversion, &max_rate);
77241056
MM		 7157 read_local_lni(dd, &enable_lane_rx);
7158
7159 /* convert to counts */
7160 tx = nibble_to_count(enable_lane_tx);
7161 rx = nibble_to_count(enable_lane_rx);
7162
7163 /*
7164 * Set link_speed_active here, overriding what was set in
7165 * handle_verify_cap(). The ASIC 8051 firmware does not correctly
7166 * set the max_rate field in handle_verify_cap until v0.19.
7167 */
d0d236ea
JJ		 7168 if ((dd->icode == ICODE_RTL_SILICON) &&
7169 (dd->dc8051_ver < dc8051_ver(0, 19))) {
77241056
MM		 7170 /* max_rate: 0 = 12.5G, 1 = 25G */
7171 switch (max_rate) {
7172 case 0:
7173 dd->pport[0].link_speed_active = OPA_LINK_SPEED_12_5G;
7174 break;
7175 default:
7176 dd_dev_err(dd,
17fb4f29
JJ		 7177 "%s: unexpected max rate %d, using 25Gb\n",
7178 __func__, (int)max_rate);
77241056
MM		 7179 /* fall through */
7180 case 1:
7181 dd->pport[0].link_speed_active = OPA_LINK_SPEED_25G;
7182 break;
7183 }
7184 }
7185
7186 dd_dev_info(dd,
17fb4f29
JJ		 7187 "Fabric active lanes (width): tx 0x%x (%d), rx 0x%x (%d)\n",
7188 enable_lane_tx, tx, enable_lane_rx, rx);
77241056
MM		 7189 *tx_width = link_width_to_bits(dd, tx);
7190 *rx_width = link_width_to_bits(dd, rx);
7191}
7192
7193/*
7194 * Read verify_cap_local_fm_link_width[1] to obtain the link widths.
7195 * Valid after the end of VerifyCap and during LinkUp. Does not change
7196 * after link up. I.e. look elsewhere for downgrade information.
7197 *
7198 * Bits are:
7199 * + bits [7:4] contain the number of active transmitters
7200 * + bits [3:0] contain the number of active receivers
7201 * These are numbers 1 through 4 and can be different values if the
7202 * link is asymmetric.
7203 *
7204 * verify_cap_local_fm_link_width[0] retains its original value.
7205 */
7206static void get_linkup_widths(struct hfi1_devdata *dd, u16 *tx_width,
7207 u16 *rx_width)
7208{
7209 u16 widths, tx, rx;
7210 u8 misc_bits, local_flags;
7211 u16 active_tx, active_rx;
7212
7213 read_vc_local_link_width(dd, &misc_bits, &local_flags, &widths);
7214 tx = widths >> 12;
7215 rx = (widths >> 8) & 0xf;
7216
7217 *tx_width = link_width_to_bits(dd, tx);
7218 *rx_width = link_width_to_bits(dd, rx);
7219
7220 /* print the active widths */
7221 get_link_widths(dd, &active_tx, &active_rx);
7222}
7223
7224/*
7225 * Set ppd->link_width_active and ppd->link_width_downgrade_active using
7226 * hardware information when the link first comes up.
7227 *
7228 * The link width is not available until after VerifyCap.AllFramesReceived
7229 * (the trigger for handle_verify_cap), so this is outside that routine
7230 * and should be called when the 8051 signals linkup.
7231 */
7232void get_linkup_link_widths(struct hfi1_pportdata *ppd)
7233{
7234 u16 tx_width, rx_width;
7235
7236 /* get end-of-LNI link widths */
7237 get_linkup_widths(ppd->dd, &tx_width, &rx_width);
7238
7239 /* use tx_width as the link is supposed to be symmetric on link up */
7240 ppd->link_width_active = tx_width;
7241 /* link width downgrade active (LWD.A) starts out matching LW.A */
7242 ppd->link_width_downgrade_tx_active = ppd->link_width_active;
7243 ppd->link_width_downgrade_rx_active = ppd->link_width_active;
7244 /* per OPA spec, on link up LWD.E resets to LWD.S */
7245 ppd->link_width_downgrade_enabled = ppd->link_width_downgrade_supported;
7246 /* cache the active egress rate (units {10^6 bits/sec]) */
7247 ppd->current_egress_rate = active_egress_rate(ppd);
7248}
7249
7250/*
7251 * Handle a verify capabilities interrupt from the 8051.
7252 *
7253 * This is a work-queue function outside of the interrupt.
7254 */
7255void handle_verify_cap(struct work_struct *work)
7256{
7257 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7258 link_vc_work);
7259 struct hfi1_devdata *dd = ppd->dd;
7260 u64 reg;
7261 u8 power_management;
7262 u8 continious;
7263 u8 vcu;
7264 u8 vau;
7265 u8 z;
7266 u16 vl15buf;
7267 u16 link_widths;
7268 u16 crc_mask;
7269 u16 crc_val;
7270 u16 device_id;
7271 u16 active_tx, active_rx;
7272 u8 partner_supported_crc;
7273 u8 remote_tx_rate;
7274 u8 device_rev;
7275
7276 set_link_state(ppd, HLS_VERIFY_CAP);
7277
7278 lcb_shutdown(dd, 0);
7279 adjust_lcb_for_fpga_serdes(dd);
7280
7281 /*
7282 * These are now valid:
7283 * remote VerifyCap fields in the general LNI config
7284 * CSR DC8051_STS_REMOTE_GUID
7285 * CSR DC8051_STS_REMOTE_NODE_TYPE
7286 * CSR DC8051_STS_REMOTE_FM_SECURITY
7287 * CSR DC8051_STS_REMOTE_PORT_NO
7288 */
7289
7290 read_vc_remote_phy(dd, &power_management, &continious);
17fb4f29
JJ		 7291 read_vc_remote_fabric(dd, &vau, &z, &vcu, &vl15buf,
7292 &partner_supported_crc);
77241056
MM		 7293 read_vc_remote_link_width(dd, &remote_tx_rate, &link_widths);
7294 read_remote_device_id(dd, &device_id, &device_rev);
7295 /*
7296 * And the 'MgmtAllowed' information, which is exchanged during
7297 * LNI, is also be available at this point.
7298 */
7299 read_mgmt_allowed(dd, &ppd->mgmt_allowed);
7300 /* print the active widths */
7301 get_link_widths(dd, &active_tx, &active_rx);
7302 dd_dev_info(dd,
17fb4f29
JJ		 7303 "Peer PHY: power management 0x%x, continuous updates 0x%x\n",
7304 (int)power_management, (int)continious);
77241056 7305 dd_dev_info(dd,
17fb4f29
JJ		 7306 "Peer Fabric: vAU %d, Z %d, vCU %d, vl15 credits 0x%x, CRC sizes 0x%x\n",
7307 (int)vau, (int)z, (int)vcu, (int)vl15buf,
7308 (int)partner_supported_crc);
77241056 7309 dd_dev_info(dd, "Peer Link Width: tx rate 0x%x, widths 0x%x\n",
17fb4f29 7310 (u32)remote_tx_rate, (u32)link_widths);
77241056 7311 dd_dev_info(dd, "Peer Device ID: 0x%04x, Revision 0x%02x\n",
17fb4f29 7312 (u32)device_id, (u32)device_rev);
77241056
MM		 7313 /*
7314 * The peer vAU value just read is the peer receiver value. HFI does
7315 * not support a transmit vAU of 0 (AU == 8). We advertised that
7316 * with Z=1 in the fabric capabilities sent to the peer. The peer
7317 * will see our Z=1, and, if it advertised a vAU of 0, will move its
7318 * receive to vAU of 1 (AU == 16). Do the same here. We do not care
7319 * about the peer Z value - our sent vAU is 3 (hardwired) and is not
7320 * subject to the Z value exception.
7321 */
7322 if (vau == 0)
7323 vau = 1;
7324 set_up_vl15(dd, vau, vl15buf);
7325
7326 /* set up the LCB CRC mode */
7327 crc_mask = ppd->port_crc_mode_enabled & partner_supported_crc;
7328
7329 /* order is important: use the lowest bit in common */
7330 if (crc_mask & CAP_CRC_14B)
7331 crc_val = LCB_CRC_14B;
7332 else if (crc_mask & CAP_CRC_48B)
7333 crc_val = LCB_CRC_48B;
7334 else if (crc_mask & CAP_CRC_12B_16B_PER_LANE)
7335 crc_val = LCB_CRC_12B_16B_PER_LANE;
7336 else
7337 crc_val = LCB_CRC_16B;
7338
7339 dd_dev_info(dd, "Final LCB CRC mode: %d\n", (int)crc_val);
7340 write_csr(dd, DC_LCB_CFG_CRC_MODE,
7341 (u64)crc_val << DC_LCB_CFG_CRC_MODE_TX_VAL_SHIFT);
7342
7343 /* set (14b only) or clear sideband credit */
7344 reg = read_csr(dd, SEND_CM_CTRL);
7345 if (crc_val == LCB_CRC_14B && crc_14b_sideband) {
7346 write_csr(dd, SEND_CM_CTRL,
17fb4f29 7347 reg | SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK);
77241056
MM		 7348 } else {
7349 write_csr(dd, SEND_CM_CTRL,
17fb4f29 7350 reg & ~SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK);
77241056
MM		 7351 }
7352
7353 ppd->link_speed_active = 0; /* invalid value */
7354 if (dd->dc8051_ver < dc8051_ver(0, 20)) {
7355 /* remote_tx_rate: 0 = 12.5G, 1 = 25G */
7356 switch (remote_tx_rate) {
7357 case 0:
7358 ppd->link_speed_active = OPA_LINK_SPEED_12_5G;
7359 break;
7360 case 1:
7361 ppd->link_speed_active = OPA_LINK_SPEED_25G;
7362 break;
7363 }
7364 } else {
7365 /* actual rate is highest bit of the ANDed rates */
7366 u8 rate = remote_tx_rate & ppd->local_tx_rate;
7367
7368 if (rate & 2)
7369 ppd->link_speed_active = OPA_LINK_SPEED_25G;
7370 else if (rate & 1)
7371 ppd->link_speed_active = OPA_LINK_SPEED_12_5G;
7372 }
7373 if (ppd->link_speed_active == 0) {
7374 dd_dev_err(dd, "%s: unexpected remote tx rate %d, using 25Gb\n",
17fb4f29 7375 __func__, (int)remote_tx_rate);
77241056
MM		 7376 ppd->link_speed_active = OPA_LINK_SPEED_25G;
7377 }
7378
7379 /*
7380 * Cache the values of the supported, enabled, and active
7381 * LTP CRC modes to return in 'portinfo' queries. But the bit
7382 * flags that are returned in the portinfo query differ from
7383 * what's in the link_crc_mask, crc_sizes, and crc_val
7384 * variables. Convert these here.
7385 */
7386 ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8;
7387 /* supported crc modes */
7388 ppd->port_ltp_crc_mode |=
7389 cap_to_port_ltp(ppd->port_crc_mode_enabled) << 4;
7390 /* enabled crc modes */
7391 ppd->port_ltp_crc_mode |= lcb_to_port_ltp(crc_val);
7392 /* active crc mode */
7393
7394 /* set up the remote credit return table */
7395 assign_remote_cm_au_table(dd, vcu);
7396
7397 /*
7398 * The LCB is reset on entry to handle_verify_cap(), so this must
7399 * be applied on every link up.
7400 *
7401 * Adjust LCB error kill enable to kill the link if
7402 * these RBUF errors are seen:
7403 * REPLAY_BUF_MBE_SMASK
7404 * FLIT_INPUT_BUF_MBE_SMASK
7405 */
995deafa 7406 if (is_ax(dd)) { /* fixed in B0 */
77241056
MM		 7407 reg = read_csr(dd, DC_LCB_CFG_LINK_KILL_EN);
7408 reg |= DC_LCB_CFG_LINK_KILL_EN_REPLAY_BUF_MBE_SMASK
7409 | DC_LCB_CFG_LINK_KILL_EN_FLIT_INPUT_BUF_MBE_SMASK;
7410 write_csr(dd, DC_LCB_CFG_LINK_KILL_EN, reg);
7411 }
7412
7413 /* pull LCB fifos out of reset - all fifo clocks must be stable */
7414 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
7415
7416 /* give 8051 access to the LCB CSRs */
7417 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
7418 set_8051_lcb_access(dd);
7419
7420 ppd->neighbor_guid =
7421 read_csr(dd, DC_DC8051_STS_REMOTE_GUID);
7422 ppd->neighbor_port_number = read_csr(dd, DC_DC8051_STS_REMOTE_PORT_NO) &
7423 DC_DC8051_STS_REMOTE_PORT_NO_VAL_SMASK;
7424 ppd->neighbor_type =
7425 read_csr(dd, DC_DC8051_STS_REMOTE_NODE_TYPE) &
7426 DC_DC8051_STS_REMOTE_NODE_TYPE_VAL_MASK;
7427 ppd->neighbor_fm_security =
7428 read_csr(dd, DC_DC8051_STS_REMOTE_FM_SECURITY) &
7429 DC_DC8051_STS_LOCAL_FM_SECURITY_DISABLED_MASK;
7430 dd_dev_info(dd,
17fb4f29
JJ		 7431 "Neighbor Guid: %llx Neighbor type %d MgmtAllowed %d FM security bypass %d\n",
7432 ppd->neighbor_guid, ppd->neighbor_type,
7433 ppd->mgmt_allowed, ppd->neighbor_fm_security);
77241056
MM		 7434 if (ppd->mgmt_allowed)
7435 add_full_mgmt_pkey(ppd);
7436
7437 /* tell the 8051 to go to LinkUp */
7438 set_link_state(ppd, HLS_GOING_UP);
7439}
7440
7441/*
7442 * Apply the link width downgrade enabled policy against the current active
7443 * link widths.
7444 *
7445 * Called when the enabled policy changes or the active link widths change.
7446 */
7447void apply_link_downgrade_policy(struct hfi1_pportdata *ppd, int refresh_widths)
7448{
77241056 7449 int do_bounce = 0;
323fd785
DL		 7450 int tries;
7451 u16 lwde;
77241056
MM		 7452 u16 tx, rx;
7453
323fd785
DL		 7454 /* use the hls lock to avoid a race with actual link up */
7455 tries = 0;
7456retry:
77241056
MM		 7457 mutex_lock(&ppd->hls_lock);
7458 /* only apply if the link is up */
0c7f77af 7459 if (ppd->host_link_state & HLS_DOWN) {
323fd785
DL		 7460 /* still going up..wait and retry */
7461 if (ppd->host_link_state & HLS_GOING_UP) {
7462 if (++tries < 1000) {
7463 mutex_unlock(&ppd->hls_lock);
7464 usleep_range(100, 120); /* arbitrary */
7465 goto retry;
7466 }
7467 dd_dev_err(ppd->dd,
7468 "%s: giving up waiting for link state change\n",
7469 __func__);
7470 }
7471 goto done;
7472 }
7473
7474 lwde = ppd->link_width_downgrade_enabled;
77241056
MM		 7475
7476 if (refresh_widths) {
7477 get_link_widths(ppd->dd, &tx, &rx);
7478 ppd->link_width_downgrade_tx_active = tx;
7479 ppd->link_width_downgrade_rx_active = rx;
7480 }
7481
f9b5635c
DL		 7482 if (ppd->link_width_downgrade_tx_active == 0 ||
7483 ppd->link_width_downgrade_rx_active == 0) {
7484 /* the 8051 reported a dead link as a downgrade */
7485 dd_dev_err(ppd->dd, "Link downgrade is really a link down, ignoring\n");
7486 } else if (lwde == 0) {
77241056
MM		 7487 /* downgrade is disabled */
7488
7489 /* bounce if not at starting active width */
7490 if ((ppd->link_width_active !=
17fb4f29
JJ		 7491 ppd->link_width_downgrade_tx_active) ||
7492 (ppd->link_width_active !=
7493 ppd->link_width_downgrade_rx_active)) {
77241056 7494 dd_dev_err(ppd->dd,
17fb4f29 7495 "Link downgrade is disabled and link has downgraded, downing link\n");
77241056 7496 dd_dev_err(ppd->dd,
17fb4f29
JJ		 7497 " original 0x%x, tx active 0x%x, rx active 0x%x\n",
7498 ppd->link_width_active,
7499 ppd->link_width_downgrade_tx_active,
7500 ppd->link_width_downgrade_rx_active);
77241056
MM		 7501 do_bounce = 1;
7502 }
d0d236ea
JJ		 7503 } else if ((lwde & ppd->link_width_downgrade_tx_active) == 0 ||
7504 (lwde & ppd->link_width_downgrade_rx_active) == 0) {
77241056
MM		 7505 /* Tx or Rx is outside the enabled policy */
7506 dd_dev_err(ppd->dd,
17fb4f29 7507 "Link is outside of downgrade allowed, downing link\n");
77241056 7508 dd_dev_err(ppd->dd,
17fb4f29
JJ		 7509 " enabled 0x%x, tx active 0x%x, rx active 0x%x\n",
7510 lwde, ppd->link_width_downgrade_tx_active,
7511 ppd->link_width_downgrade_rx_active);
77241056
MM		 7512 do_bounce = 1;
7513 }
7514
323fd785
DL		 7515done:
7516 mutex_unlock(&ppd->hls_lock);
7517
77241056
MM		 7518 if (do_bounce) {
7519 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_WIDTH_POLICY, 0,
17fb4f29 7520 OPA_LINKDOWN_REASON_WIDTH_POLICY);
77241056
MM		 7521 set_link_state(ppd, HLS_DN_OFFLINE);
7522 start_link(ppd);
7523 }
7524}
7525
7526/*
7527 * Handle a link downgrade interrupt from the 8051.
7528 *
7529 * This is a work-queue function outside of the interrupt.
7530 */
7531void handle_link_downgrade(struct work_struct *work)
7532{
7533 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7534 link_downgrade_work);
7535
7536 dd_dev_info(ppd->dd, "8051: Link width downgrade\n");
7537 apply_link_downgrade_policy(ppd, 1);
7538}
7539
7540static char *dcc_err_string(char *buf, int buf_len, u64 flags)
7541{
7542 return flag_string(buf, buf_len, flags, dcc_err_flags,
7543 ARRAY_SIZE(dcc_err_flags));
7544}
7545
7546static char *lcb_err_string(char *buf, int buf_len, u64 flags)
7547{
7548 return flag_string(buf, buf_len, flags, lcb_err_flags,
7549 ARRAY_SIZE(lcb_err_flags));
7550}
7551
7552static char *dc8051_err_string(char *buf, int buf_len, u64 flags)
7553{
7554 return flag_string(buf, buf_len, flags, dc8051_err_flags,
7555 ARRAY_SIZE(dc8051_err_flags));
7556}
7557
7558static char *dc8051_info_err_string(char *buf, int buf_len, u64 flags)
7559{
7560 return flag_string(buf, buf_len, flags, dc8051_info_err_flags,
7561 ARRAY_SIZE(dc8051_info_err_flags));
7562}
7563
7564static char *dc8051_info_host_msg_string(char *buf, int buf_len, u64 flags)
7565{
7566 return flag_string(buf, buf_len, flags, dc8051_info_host_msg_flags,
7567 ARRAY_SIZE(dc8051_info_host_msg_flags));
7568}
7569
7570static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg)
7571{
7572 struct hfi1_pportdata *ppd = dd->pport;
7573 u64 info, err, host_msg;
7574 int queue_link_down = 0;
7575 char buf[96];
7576
7577 /* look at the flags */
7578 if (reg & DC_DC8051_ERR_FLG_SET_BY_8051_SMASK) {
7579 /* 8051 information set by firmware */
7580 /* read DC8051_DBG_ERR_INFO_SET_BY_8051 for details */
7581 info = read_csr(dd, DC_DC8051_DBG_ERR_INFO_SET_BY_8051);
7582 err = (info >> DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_SHIFT)
7583 & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_MASK;
7584 host_msg = (info >>
7585 DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_SHIFT)
7586 & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_MASK;
7587
7588 /*
7589 * Handle error flags.
7590 */
7591 if (err & FAILED_LNI) {
7592 /*
7593 * LNI error indications are cleared by the 8051
7594 * only when starting polling. Only pay attention
7595 * to them when in the states that occur during
7596 * LNI.
7597 */
7598 if (ppd->host_link_state
7599 & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) {
7600 queue_link_down = 1;
7601 dd_dev_info(dd, "Link error: %s\n",
17fb4f29
JJ		 7602 dc8051_info_err_string(buf,
7603 sizeof(buf),
7604 err &
7605 FAILED_LNI));
77241056
MM		 7606 }
7607 err &= ~(u64)FAILED_LNI;
7608 }
6d014530
DL		 7609 /* unknown frames can happen durning LNI, just count */
7610 if (err & UNKNOWN_FRAME) {
7611 ppd->unknown_frame_count++;
7612 err &= ~(u64)UNKNOWN_FRAME;
7613 }
77241056
MM		 7614 if (err) {
7615 /* report remaining errors, but do not do anything */
7616 dd_dev_err(dd, "8051 info error: %s\n",
17fb4f29
JJ		 7617 dc8051_info_err_string(buf, sizeof(buf),
7618 err));
77241056
MM		 7619 }
7620
7621 /*
7622 * Handle host message flags.
7623 */
7624 if (host_msg & HOST_REQ_DONE) {
7625 /*
7626 * Presently, the driver does a busy wait for
7627 * host requests to complete. This is only an
7628 * informational message.
7629 * NOTE: The 8051 clears the host message
7630 * information *on the next 8051 command*.
7631 * Therefore, when linkup is achieved,
7632 * this flag will still be set.
7633 */
7634 host_msg &= ~(u64)HOST_REQ_DONE;
7635 }
7636 if (host_msg & BC_SMA_MSG) {
7637 queue_work(ppd->hfi1_wq, &ppd->sma_message_work);
7638 host_msg &= ~(u64)BC_SMA_MSG;
7639 }
7640 if (host_msg & LINKUP_ACHIEVED) {
7641 dd_dev_info(dd, "8051: Link up\n");
7642 queue_work(ppd->hfi1_wq, &ppd->link_up_work);
7643 host_msg &= ~(u64)LINKUP_ACHIEVED;
7644 }
7645 if (host_msg & EXT_DEVICE_CFG_REQ) {
145dd2b3 7646 handle_8051_request(ppd);
77241056
MM		 7647 host_msg &= ~(u64)EXT_DEVICE_CFG_REQ;
7648 }
7649 if (host_msg & VERIFY_CAP_FRAME) {
7650 queue_work(ppd->hfi1_wq, &ppd->link_vc_work);
7651 host_msg &= ~(u64)VERIFY_CAP_FRAME;
7652 }
7653 if (host_msg & LINK_GOING_DOWN) {
7654 const char *extra = "";
7655 /* no downgrade action needed if going down */
7656 if (host_msg & LINK_WIDTH_DOWNGRADED) {
7657 host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED;
7658 extra = " (ignoring downgrade)";
7659 }
7660 dd_dev_info(dd, "8051: Link down%s\n", extra);
7661 queue_link_down = 1;
7662 host_msg &= ~(u64)LINK_GOING_DOWN;
7663 }
7664 if (host_msg & LINK_WIDTH_DOWNGRADED) {
7665 queue_work(ppd->hfi1_wq, &ppd->link_downgrade_work);
7666 host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED;
7667 }
7668 if (host_msg) {
7669 /* report remaining messages, but do not do anything */
7670 dd_dev_info(dd, "8051 info host message: %s\n",
17fb4f29
JJ		 7671 dc8051_info_host_msg_string(buf,
7672 sizeof(buf),
7673 host_msg));
77241056
MM		 7674 }
7675
7676 reg &= ~DC_DC8051_ERR_FLG_SET_BY_8051_SMASK;
7677 }
7678 if (reg & DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK) {
7679 /*
7680 * Lost the 8051 heartbeat. If this happens, we
7681 * receive constant interrupts about it. Disable
7682 * the interrupt after the first.
7683 */
7684 dd_dev_err(dd, "Lost 8051 heartbeat\n");
7685 write_csr(dd, DC_DC8051_ERR_EN,
17fb4f29
JJ		 7686 read_csr(dd, DC_DC8051_ERR_EN) &
7687 ~DC_DC8051_ERR_EN_LOST_8051_HEART_BEAT_SMASK);
77241056
MM		 7688
7689 reg &= ~DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK;
7690 }
7691 if (reg) {
7692 /* report the error, but do not do anything */
7693 dd_dev_err(dd, "8051 error: %s\n",
17fb4f29 7694 dc8051_err_string(buf, sizeof(buf), reg));
77241056
MM		 7695 }
7696
7697 if (queue_link_down) {
4d114fdd
JJ		 7698 /*
7699 * if the link is already going down or disabled, do not
7700 * queue another
7701 */
d0d236ea
JJ		 7702 if ((ppd->host_link_state &
7703 (HLS_GOING_OFFLINE | HLS_LINK_COOLDOWN)) ||
7704 ppd->link_enabled == 0) {
77241056 7705 dd_dev_info(dd, "%s: not queuing link down\n",
17fb4f29 7706 __func__);
77241056
MM		 7707 } else {
7708 queue_work(ppd->hfi1_wq, &ppd->link_down_work);
7709 }
7710 }
7711}
7712
7713static const char * const fm_config_txt[] = {
7714[0] =
7715 "BadHeadDist: Distance violation between two head flits",
7716[1] =
7717 "BadTailDist: Distance violation between two tail flits",
7718[2] =
7719 "BadCtrlDist: Distance violation between two credit control flits",
7720[3] =
7721 "BadCrdAck: Credits return for unsupported VL",
7722[4] =
7723 "UnsupportedVLMarker: Received VL Marker",
7724[5] =
7725 "BadPreempt: Exceeded the preemption nesting level",
7726[6] =
7727 "BadControlFlit: Received unsupported control flit",
7728/* no 7 */
7729[8] =
7730 "UnsupportedVLMarker: Received VL Marker for unconfigured or disabled VL",
7731};
7732
7733static const char * const port_rcv_txt[] = {
7734[1] =
7735 "BadPktLen: Illegal PktLen",
7736[2] =
7737 "PktLenTooLong: Packet longer than PktLen",
7738[3] =
7739 "PktLenTooShort: Packet shorter than PktLen",
7740[4] =
7741 "BadSLID: Illegal SLID (0, using multicast as SLID, does not include security validation of SLID)",
7742[5] =
7743 "BadDLID: Illegal DLID (0, doesn't match HFI)",
7744[6] =
7745 "BadL2: Illegal L2 opcode",
7746[7] =
7747 "BadSC: Unsupported SC",
7748[9] =
7749 "BadRC: Illegal RC",
7750[11] =
7751 "PreemptError: Preempting with same VL",
7752[12] =
7753 "PreemptVL15: Preempting a VL15 packet",
7754};
7755
7756#define OPA_LDR_FMCONFIG_OFFSET 16
7757#define OPA_LDR_PORTRCV_OFFSET 0
7758static void handle_dcc_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
7759{
7760 u64 info, hdr0, hdr1;
7761 const char *extra;
7762 char buf[96];
7763 struct hfi1_pportdata *ppd = dd->pport;
7764 u8 lcl_reason = 0;
7765 int do_bounce = 0;
7766
7767 if (reg & DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK) {
7768 if (!(dd->err_info_uncorrectable & OPA_EI_STATUS_SMASK)) {
7769 info = read_csr(dd, DCC_ERR_INFO_UNCORRECTABLE);
7770 dd->err_info_uncorrectable = info & OPA_EI_CODE_SMASK;
7771 /* set status bit */
7772 dd->err_info_uncorrectable |= OPA_EI_STATUS_SMASK;
7773 }
7774 reg &= ~DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK;
7775 }
7776
7777 if (reg & DCC_ERR_FLG_LINK_ERR_SMASK) {
7778 struct hfi1_pportdata *ppd = dd->pport;
7779 /* this counter saturates at (2^32) - 1 */
7780 if (ppd->link_downed < (u32)UINT_MAX)
7781 ppd->link_downed++;
7782 reg &= ~DCC_ERR_FLG_LINK_ERR_SMASK;
7783 }
7784
7785 if (reg & DCC_ERR_FLG_FMCONFIG_ERR_SMASK) {
7786 u8 reason_valid = 1;
7787
7788 info = read_csr(dd, DCC_ERR_INFO_FMCONFIG);
7789 if (!(dd->err_info_fmconfig & OPA_EI_STATUS_SMASK)) {
7790 dd->err_info_fmconfig = info & OPA_EI_CODE_SMASK;
7791 /* set status bit */
7792 dd->err_info_fmconfig |= OPA_EI_STATUS_SMASK;
7793 }
7794 switch (info) {
7795 case 0:
7796 case 1:
7797 case 2:
7798 case 3:
7799 case 4:
7800 case 5:
7801 case 6:
7802 extra = fm_config_txt[info];
7803 break;
7804 case 8:
7805 extra = fm_config_txt[info];
7806 if (ppd->port_error_action &
7807 OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER) {
7808 do_bounce = 1;
7809 /*
7810 * lcl_reason cannot be derived from info
7811 * for this error
7812 */
7813 lcl_reason =
7814 OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER;
7815 }
7816 break;
7817 default:
7818 reason_valid = 0;
7819 snprintf(buf, sizeof(buf), "reserved%lld", info);
7820 extra = buf;
7821 break;
7822 }
7823
7824 if (reason_valid && !do_bounce) {
7825 do_bounce = ppd->port_error_action &
7826 (1 << (OPA_LDR_FMCONFIG_OFFSET + info));
7827 lcl_reason = info + OPA_LINKDOWN_REASON_BAD_HEAD_DIST;
7828 }
7829
7830 /* just report this */
c27aad00
JB		 7831 dd_dev_info_ratelimited(dd, "DCC Error: fmconfig error: %s\n",
7832 extra);
77241056
MM		 7833 reg &= ~DCC_ERR_FLG_FMCONFIG_ERR_SMASK;
7834 }
7835
7836 if (reg & DCC_ERR_FLG_RCVPORT_ERR_SMASK) {
7837 u8 reason_valid = 1;
7838
7839 info = read_csr(dd, DCC_ERR_INFO_PORTRCV);
7840 hdr0 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR0);
7841 hdr1 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR1);
7842 if (!(dd->err_info_rcvport.status_and_code &
7843 OPA_EI_STATUS_SMASK)) {
7844 dd->err_info_rcvport.status_and_code =
7845 info & OPA_EI_CODE_SMASK;
7846 /* set status bit */
7847 dd->err_info_rcvport.status_and_code |=
7848 OPA_EI_STATUS_SMASK;
4d114fdd
JJ		 7849 /*
7850 * save first 2 flits in the packet that caused
7851 * the error
7852 */
48a0cc13
BVA		 7853 dd->err_info_rcvport.packet_flit1 = hdr0;
7854 dd->err_info_rcvport.packet_flit2 = hdr1;
77241056
MM		 7855 }
7856 switch (info) {
7857 case 1:
7858 case 2:
7859 case 3:
7860 case 4:
7861 case 5:
7862 case 6:
7863 case 7:
7864 case 9:
7865 case 11:
7866 case 12:
7867 extra = port_rcv_txt[info];
7868 break;
7869 default:
7870 reason_valid = 0;
7871 snprintf(buf, sizeof(buf), "reserved%lld", info);
7872 extra = buf;
7873 break;
7874 }
7875
7876 if (reason_valid && !do_bounce) {
7877 do_bounce = ppd->port_error_action &
7878 (1 << (OPA_LDR_PORTRCV_OFFSET + info));
7879 lcl_reason = info + OPA_LINKDOWN_REASON_RCV_ERROR_0;
7880 }
7881
7882 /* just report this */
c27aad00
JB		 7883 dd_dev_info_ratelimited(dd, "DCC Error: PortRcv error: %s\n"
7884 " hdr0 0x%llx, hdr1 0x%llx\n",
7885 extra, hdr0, hdr1);
77241056
MM		 7886
7887 reg &= ~DCC_ERR_FLG_RCVPORT_ERR_SMASK;
7888 }
7889
7890 if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK) {
7891 /* informative only */
c27aad00 7892 dd_dev_info_ratelimited(dd, "8051 access to LCB blocked\n");
77241056
MM		 7893 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK;
7894 }
7895 if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK) {
7896 /* informative only */
c27aad00 7897 dd_dev_info_ratelimited(dd, "host access to LCB blocked\n");
77241056
MM		 7898 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK;
7899 }
7900
7901 /* report any remaining errors */
7902 if (reg)
c27aad00
JB		 7903 dd_dev_info_ratelimited(dd, "DCC Error: %s\n",
7904 dcc_err_string(buf, sizeof(buf), reg));
77241056
MM		 7905
7906 if (lcl_reason == 0)
7907 lcl_reason = OPA_LINKDOWN_REASON_UNKNOWN;
7908
7909 if (do_bounce) {
c27aad00
JB		 7910 dd_dev_info_ratelimited(dd, "%s: PortErrorAction bounce\n",
7911 __func__);
77241056
MM		 7912 set_link_down_reason(ppd, lcl_reason, 0, lcl_reason);
7913 queue_work(ppd->hfi1_wq, &ppd->link_bounce_work);
7914 }
7915}
7916
7917static void handle_lcb_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
7918{
7919 char buf[96];
7920
7921 dd_dev_info(dd, "LCB Error: %s\n",
17fb4f29 7922 lcb_err_string(buf, sizeof(buf), reg));
77241056
MM		 7923}
7924
7925/*
7926 * CCE block DC interrupt. Source is < 8.
7927 */
7928static void is_dc_int(struct hfi1_devdata *dd, unsigned int source)
7929{
7930 const struct err_reg_info *eri = &dc_errs[source];
7931
7932 if (eri->handler) {
7933 interrupt_clear_down(dd, 0, eri);
7934 } else if (source == 3 /* dc_lbm_int */) {
7935 /*
7936 * This indicates that a parity error has occurred on the
7937 * address/control lines presented to the LBM. The error
7938 * is a single pulse, there is no associated error flag,
7939 * and it is non-maskable. This is because if a parity
7940 * error occurs on the request the request is dropped.
7941 * This should never occur, but it is nice to know if it
7942 * ever does.
7943 */
7944 dd_dev_err(dd, "Parity error in DC LBM block\n");
7945 } else {
7946 dd_dev_err(dd, "Invalid DC interrupt %u\n", source);
7947 }
7948}
7949
7950/*
7951 * TX block send credit interrupt. Source is < 160.
7952 */
7953static void is_send_credit_int(struct hfi1_devdata *dd, unsigned int source)
7954{
7955 sc_group_release_update(dd, source);
7956}
7957
7958/*
7959 * TX block SDMA interrupt. Source is < 48.
7960 *
7961 * SDMA interrupts are grouped by type:
7962 *
7963 * 0 - N-1 = SDma
7964 * N - 2N-1 = SDmaProgress
7965 * 2N - 3N-1 = SDmaIdle
7966 */
7967static void is_sdma_eng_int(struct hfi1_devdata *dd, unsigned int source)
7968{
7969 /* what interrupt */
7970 unsigned int what = source / TXE_NUM_SDMA_ENGINES;
7971 /* which engine */
7972 unsigned int which = source % TXE_NUM_SDMA_ENGINES;
7973
7974#ifdef CONFIG_SDMA_VERBOSITY
7975 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", which,
7976 slashstrip(__FILE__), __LINE__, __func__);
7977 sdma_dumpstate(&dd->per_sdma[which]);
7978#endif
7979
7980 if (likely(what < 3 && which < dd->num_sdma)) {
7981 sdma_engine_interrupt(&dd->per_sdma[which], 1ull << source);
7982 } else {
7983 /* should not happen */
7984 dd_dev_err(dd, "Invalid SDMA interrupt 0x%x\n", source);
7985 }
7986}
7987
7988/*
7989 * RX block receive available interrupt. Source is < 160.
7990 */
7991static void is_rcv_avail_int(struct hfi1_devdata *dd, unsigned int source)
7992{
7993 struct hfi1_ctxtdata *rcd;
7994 char *err_detail;
7995
7996 if (likely(source < dd->num_rcv_contexts)) {
7997 rcd = dd->rcd[source];
7998 if (rcd) {
7999 if (source < dd->first_user_ctxt)
f4f30031 8000 rcd->do_interrupt(rcd, 0);
77241056
MM		 8001 else
8002 handle_user_interrupt(rcd);
8003 return; /* OK */
8004 }
8005 /* received an interrupt, but no rcd */
8006 err_detail = "dataless";
8007 } else {
8008 /* received an interrupt, but are not using that context */
8009 err_detail = "out of range";
8010 }
8011 dd_dev_err(dd, "unexpected %s receive available context interrupt %u\n",
17fb4f29 8012 err_detail, source);
77241056
MM		 8013}
8014
8015/*
8016 * RX block receive urgent interrupt. Source is < 160.
8017 */
8018static void is_rcv_urgent_int(struct hfi1_devdata *dd, unsigned int source)
8019{
8020 struct hfi1_ctxtdata *rcd;
8021 char *err_detail;
8022
8023 if (likely(source < dd->num_rcv_contexts)) {
8024 rcd = dd->rcd[source];
8025 if (rcd) {
8026 /* only pay attention to user urgent interrupts */
8027 if (source >= dd->first_user_ctxt)
8028 handle_user_interrupt(rcd);
8029 return; /* OK */
8030 }
8031 /* received an interrupt, but no rcd */
8032 err_detail = "dataless";
8033 } else {
8034 /* received an interrupt, but are not using that context */
8035 err_detail = "out of range";
8036 }
8037 dd_dev_err(dd, "unexpected %s receive urgent context interrupt %u\n",
17fb4f29 8038 err_detail, source);
77241056
MM		 8039}
8040
8041/*
8042 * Reserved range interrupt. Should not be called in normal operation.
8043 */
8044static void is_reserved_int(struct hfi1_devdata *dd, unsigned int source)
8045{
8046 char name[64];
8047
8048 dd_dev_err(dd, "unexpected %s interrupt\n",
17fb4f29 8049 is_reserved_name(name, sizeof(name), source));
77241056
MM		 8050}
8051
8052static const struct is_table is_table[] = {
4d114fdd
JJ		 8053/*
8054 * start end
8055 * name func interrupt func
8056 */
77241056
MM		 8057{ IS_GENERAL_ERR_START, IS_GENERAL_ERR_END,
8058 is_misc_err_name, is_misc_err_int },
8059{ IS_SDMAENG_ERR_START, IS_SDMAENG_ERR_END,
8060 is_sdma_eng_err_name, is_sdma_eng_err_int },
8061{ IS_SENDCTXT_ERR_START, IS_SENDCTXT_ERR_END,
8062 is_sendctxt_err_name, is_sendctxt_err_int },
8063{ IS_SDMA_START, IS_SDMA_END,
8064 is_sdma_eng_name, is_sdma_eng_int },
8065{ IS_VARIOUS_START, IS_VARIOUS_END,
8066 is_various_name, is_various_int },
8067{ IS_DC_START, IS_DC_END,
8068 is_dc_name, is_dc_int },
8069{ IS_RCVAVAIL_START, IS_RCVAVAIL_END,
8070 is_rcv_avail_name, is_rcv_avail_int },
8071{ IS_RCVURGENT_START, IS_RCVURGENT_END,
8072 is_rcv_urgent_name, is_rcv_urgent_int },
8073{ IS_SENDCREDIT_START, IS_SENDCREDIT_END,
8074 is_send_credit_name, is_send_credit_int},
8075{ IS_RESERVED_START, IS_RESERVED_END,
8076 is_reserved_name, is_reserved_int},
8077};
8078
8079/*
8080 * Interrupt source interrupt - called when the given source has an interrupt.
8081 * Source is a bit index into an array of 64-bit integers.
8082 */
8083static void is_interrupt(struct hfi1_devdata *dd, unsigned int source)
8084{
8085 const struct is_table *entry;
8086
8087 /* avoids a double compare by walking the table in-order */
8088 for (entry = &is_table[0]; entry->is_name; entry++) {
8089 if (source < entry->end) {
8090 trace_hfi1_interrupt(dd, entry, source);
8091 entry->is_int(dd, source - entry->start);
8092 return;
8093 }
8094 }
8095 /* fell off the end */
8096 dd_dev_err(dd, "invalid interrupt source %u\n", source);
8097}
8098
8099/*
8100 * General interrupt handler. This is able to correctly handle
8101 * all interrupts in case INTx is used.
8102 */
8103static irqreturn_t general_interrupt(int irq, void *data)
8104{
8105 struct hfi1_devdata *dd = data;
8106 u64 regs[CCE_NUM_INT_CSRS];
8107 u32 bit;
8108 int i;
8109
8110 this_cpu_inc(*dd->int_counter);
8111
8112 /* phase 1: scan and clear all handled interrupts */
8113 for (i = 0; i < CCE_NUM_INT_CSRS; i++) {
8114 if (dd->gi_mask[i] == 0) {
8115 regs[i] = 0; /* used later */
8116 continue;
8117 }
8118 regs[i] = read_csr(dd, CCE_INT_STATUS + (8 * i)) &
8119 dd->gi_mask[i];
8120 /* only clear if anything is set */
8121 if (regs[i])
8122 write_csr(dd, CCE_INT_CLEAR + (8 * i), regs[i]);
8123 }
8124
8125 /* phase 2: call the appropriate handler */
8126 for_each_set_bit(bit, (unsigned long *)&regs[0],
17fb4f29 8127 CCE_NUM_INT_CSRS * 64) {
77241056
MM		 8128 is_interrupt(dd, bit);
8129 }
8130
8131 return IRQ_HANDLED;
8132}
8133
8134static irqreturn_t sdma_interrupt(int irq, void *data)
8135{
8136 struct sdma_engine *sde = data;
8137 struct hfi1_devdata *dd = sde->dd;
8138 u64 status;
8139
8140#ifdef CONFIG_SDMA_VERBOSITY
8141 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
8142 slashstrip(__FILE__), __LINE__, __func__);
8143 sdma_dumpstate(sde);
8144#endif
8145
8146 this_cpu_inc(*dd->int_counter);
8147
8148 /* This read_csr is really bad in the hot path */
8149 status = read_csr(dd,
17fb4f29
JJ		 8150 CCE_INT_STATUS + (8 * (IS_SDMA_START / 64)))
8151 & sde->imask;
77241056
MM		 8152 if (likely(status)) {
8153 /* clear the interrupt(s) */
8154 write_csr(dd,
17fb4f29
JJ		 8155 CCE_INT_CLEAR + (8 * (IS_SDMA_START / 64)),
8156 status);
77241056
MM		 8157
8158 /* handle the interrupt(s) */
8159 sdma_engine_interrupt(sde, status);
8160 } else
8161 dd_dev_err(dd, "SDMA engine %u interrupt, but no status bits set\n",
17fb4f29 8162 sde->this_idx);
77241056
MM		 8163
8164 return IRQ_HANDLED;
8165}
8166
8167/*
ecd42f8d
DL		 8168 * Clear the receive interrupt. Use a read of the interrupt clear CSR
8169 * to insure that the write completed. This does NOT guarantee that
8170 * queued DMA writes to memory from the chip are pushed.
f4f30031
DL		 8171 */
8172static inline void clear_recv_intr(struct hfi1_ctxtdata *rcd)
8173{
8174 struct hfi1_devdata *dd = rcd->dd;
8175 u32 addr = CCE_INT_CLEAR + (8 * rcd->ireg);
8176
8177 mmiowb(); /* make sure everything before is written */
8178 write_csr(dd, addr, rcd->imask);
8179 /* force the above write on the chip and get a value back */
8180 (void)read_csr(dd, addr);
8181}
8182
8183/* force the receive interrupt */
fb9036dd 8184void force_recv_intr(struct hfi1_ctxtdata *rcd)
f4f30031
DL		 8185{
8186 write_csr(rcd->dd, CCE_INT_FORCE + (8 * rcd->ireg), rcd->imask);
8187}
8188
ecd42f8d
DL		 8189/*
8190 * Return non-zero if a packet is present.
8191 *
8192 * This routine is called when rechecking for packets after the RcvAvail
8193 * interrupt has been cleared down. First, do a quick check of memory for
8194 * a packet present. If not found, use an expensive CSR read of the context
8195 * tail to determine the actual tail. The CSR read is necessary because there
8196 * is no method to push pending DMAs to memory other than an interrupt and we
8197 * are trying to determine if we need to force an interrupt.
8198 */
f4f30031
DL		 8199static inline int check_packet_present(struct hfi1_ctxtdata *rcd)
8200{
ecd42f8d
DL		 8201 u32 tail;
8202 int present;
8203
f4f30031 8204 if (!HFI1_CAP_IS_KSET(DMA_RTAIL))
ecd42f8d 8205 present = (rcd->seq_cnt ==
f4f30031 8206 rhf_rcv_seq(rhf_to_cpu(get_rhf_addr(rcd))));
ecd42f8d
DL		 8207 else /* is RDMA rtail */
8208 present = (rcd->head != get_rcvhdrtail(rcd));
8209
8210 if (present)
8211 return 1;
f4f30031 8212
ecd42f8d
DL		 8213 /* fall back to a CSR read, correct indpendent of DMA_RTAIL */
8214 tail = (u32)read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
8215 return rcd->head != tail;
f4f30031
DL		 8216}
8217
8218/*
8219 * Receive packet IRQ handler. This routine expects to be on its own IRQ.
8220 * This routine will try to handle packets immediately (latency), but if
8221 * it finds too many, it will invoke the thread handler (bandwitdh). The
16733b88 8222 * chip receive interrupt is *not* cleared down until this or the thread (if
f4f30031
DL		 8223 * invoked) is finished. The intent is to avoid extra interrupts while we
8224 * are processing packets anyway.
77241056
MM		 8225 */
8226static irqreturn_t receive_context_interrupt(int irq, void *data)
8227{
8228 struct hfi1_ctxtdata *rcd = data;
8229 struct hfi1_devdata *dd = rcd->dd;
f4f30031
DL		 8230 int disposition;
8231 int present;
77241056
MM		 8232
8233 trace_hfi1_receive_interrupt(dd, rcd->ctxt);
8234 this_cpu_inc(*dd->int_counter);
affa48de 8235 aspm_ctx_disable(rcd);
77241056 8236
f4f30031
DL		 8237 /* receive interrupt remains blocked while processing packets */
8238 disposition = rcd->do_interrupt(rcd, 0);
77241056 8239
f4f30031
DL		 8240 /*
8241 * Too many packets were seen while processing packets in this
8242 * IRQ handler. Invoke the handler thread. The receive interrupt
8243 * remains blocked.
8244 */
8245 if (disposition == RCV_PKT_LIMIT)
8246 return IRQ_WAKE_THREAD;
8247
8248 /*
8249 * The packet processor detected no more packets. Clear the receive
8250 * interrupt and recheck for a packet packet that may have arrived
8251 * after the previous check and interrupt clear. If a packet arrived,
8252 * force another interrupt.
8253 */
8254 clear_recv_intr(rcd);
8255 present = check_packet_present(rcd);
8256 if (present)
8257 force_recv_intr(rcd);
8258
8259 return IRQ_HANDLED;
8260}
8261
8262/*
8263 * Receive packet thread handler. This expects to be invoked with the
8264 * receive interrupt still blocked.
8265 */
8266static irqreturn_t receive_context_thread(int irq, void *data)
8267{
8268 struct hfi1_ctxtdata *rcd = data;
8269 int present;
8270
8271 /* receive interrupt is still blocked from the IRQ handler */
8272 (void)rcd->do_interrupt(rcd, 1);
8273
8274 /*
8275 * The packet processor will only return if it detected no more
8276 * packets. Hold IRQs here so we can safely clear the interrupt and
8277 * recheck for a packet that may have arrived after the previous
8278 * check and the interrupt clear. If a packet arrived, force another
8279 * interrupt.
8280 */
8281 local_irq_disable();
8282 clear_recv_intr(rcd);
8283 present = check_packet_present(rcd);
8284 if (present)
8285 force_recv_intr(rcd);
8286 local_irq_enable();
77241056
MM		 8287
8288 return IRQ_HANDLED;
8289}
8290
8291/* ========================================================================= */
8292
8293u32 read_physical_state(struct hfi1_devdata *dd)
8294{
8295 u64 reg;
8296
8297 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE);
8298 return (reg >> DC_DC8051_STS_CUR_STATE_PORT_SHIFT)
8299 & DC_DC8051_STS_CUR_STATE_PORT_MASK;
8300}
8301
fb9036dd 8302u32 read_logical_state(struct hfi1_devdata *dd)
77241056
MM		 8303{
8304 u64 reg;
8305
8306 reg = read_csr(dd, DCC_CFG_PORT_CONFIG);
8307 return (reg >> DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT)
8308 & DCC_CFG_PORT_CONFIG_LINK_STATE_MASK;
8309}
8310
8311static void set_logical_state(struct hfi1_devdata *dd, u32 chip_lstate)
8312{
8313 u64 reg;
8314
8315 reg = read_csr(dd, DCC_CFG_PORT_CONFIG);
8316 /* clear current state, set new state */
8317 reg &= ~DCC_CFG_PORT_CONFIG_LINK_STATE_SMASK;
8318 reg |= (u64)chip_lstate << DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT;
8319 write_csr(dd, DCC_CFG_PORT_CONFIG, reg);
8320}
8321
8322/*
8323 * Use the 8051 to read a LCB CSR.
8324 */
8325static int read_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 *data)
8326{
8327 u32 regno;
8328 int ret;
8329
8330 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) {
8331 if (acquire_lcb_access(dd, 0) == 0) {
8332 *data = read_csr(dd, addr);
8333 release_lcb_access(dd, 0);
8334 return 0;
8335 }
8336 return -EBUSY;
8337 }
8338
8339 /* register is an index of LCB registers: (offset - base) / 8 */
8340 regno = (addr - DC_LCB_CFG_RUN) >> 3;
8341 ret = do_8051_command(dd, HCMD_READ_LCB_CSR, regno, data);
8342 if (ret != HCMD_SUCCESS)
8343 return -EBUSY;
8344 return 0;
8345}
8346
8688426b
MR		 8347/*
8348 * Provide a cache for some of the LCB registers in case the LCB is
8349 * unavailable.
8350 * (The LCB is unavailable in certain link states, for example.)
8351 */
8352struct lcb_datum {
8353 u32 off;
8354 u64 val;
8355};
8356
8357static struct lcb_datum lcb_cache[] = {
8358 { DC_LCB_ERR_INFO_RX_REPLAY_CNT, 0},
8359 { DC_LCB_ERR_INFO_SEQ_CRC_CNT, 0 },
8360 { DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT, 0 },
8361};
8362
8363static void update_lcb_cache(struct hfi1_devdata *dd)
8364{
8365 int i;
8366 int ret;
8367 u64 val;
8368
8369 for (i = 0; i < ARRAY_SIZE(lcb_cache); i++) {
8370 ret = read_lcb_csr(dd, lcb_cache[i].off, &val);
8371
8372 /* Update if we get good data */
8373 if (likely(ret != -EBUSY))
8374 lcb_cache[i].val = val;
8375 }
8376}
8377
8378static int read_lcb_cache(u32 off, u64 *val)
8379{
8380 int i;
8381
8382 for (i = 0; i < ARRAY_SIZE(lcb_cache); i++) {
8383 if (lcb_cache[i].off == off) {
8384 *val = lcb_cache[i].val;
8385 return 0;
8386 }
8387 }
8388
8389 pr_warn("%s bad offset 0x%x\n", __func__, off);
8390 return -1;
8391}
8392
77241056
MM		 8393/*
8394 * Read an LCB CSR. Access may not be in host control, so check.
8395 * Return 0 on success, -EBUSY on failure.
8396 */
8397int read_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 *data)
8398{
8399 struct hfi1_pportdata *ppd = dd->pport;
8400
8401 /* if up, go through the 8051 for the value */
8402 if (ppd->host_link_state & HLS_UP)
8403 return read_lcb_via_8051(dd, addr, data);
8688426b
MR		 8404 /* if going up or down, check the cache, otherwise, no access */
8405 if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE)) {
8406 if (read_lcb_cache(addr, data))
8407 return -EBUSY;
8408 return 0;
8409 }
8410
77241056
MM		 8411 /* otherwise, host has access */
8412 *data = read_csr(dd, addr);
8413 return 0;
8414}
8415
8416/*
8417 * Use the 8051 to write a LCB CSR.
8418 */
8419static int write_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 data)
8420{
3bf40d65
DL		 8421 u32 regno;
8422 int ret;
77241056 8423
3bf40d65
DL		 8424 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR ||
8425 (dd->dc8051_ver < dc8051_ver(0, 20))) {
8426 if (acquire_lcb_access(dd, 0) == 0) {
8427 write_csr(dd, addr, data);
8428 release_lcb_access(dd, 0);
8429 return 0;
8430 }
8431 return -EBUSY;
77241056 8432 }
3bf40d65
DL		 8433
8434 /* register is an index of LCB registers: (offset - base) / 8 */
8435 regno = (addr - DC_LCB_CFG_RUN) >> 3;
8436 ret = do_8051_command(dd, HCMD_WRITE_LCB_CSR, regno, &data);
8437 if (ret != HCMD_SUCCESS)
8438 return -EBUSY;
8439 return 0;
77241056
MM		 8440}
8441
8442/*
8443 * Write an LCB CSR. Access may not be in host control, so check.
8444 * Return 0 on success, -EBUSY on failure.
8445 */
8446int write_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 data)
8447{
8448 struct hfi1_pportdata *ppd = dd->pport;
8449
8450 /* if up, go through the 8051 for the value */
8451 if (ppd->host_link_state & HLS_UP)
8452 return write_lcb_via_8051(dd, addr, data);
8453 /* if going up or down, no access */
8454 if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE))
8455 return -EBUSY;
8456 /* otherwise, host has access */
8457 write_csr(dd, addr, data);
8458 return 0;
8459}
8460
8461/*
8462 * Returns:
8463 * < 0 = Linux error, not able to get access
8464 * > 0 = 8051 command RETURN_CODE
8465 */
8466static int do_8051_command(
8467 struct hfi1_devdata *dd,
8468 u32 type,
8469 u64 in_data,
8470 u64 *out_data)
8471{
8472 u64 reg, completed;
8473 int return_code;
8474 unsigned long flags;
8475 unsigned long timeout;
8476
8477 hfi1_cdbg(DC8051, "type %d, data 0x%012llx", type, in_data);
8478
8479 /*
8480 * Alternative to holding the lock for a long time:
8481 * - keep busy wait - have other users bounce off
8482 */
8483 spin_lock_irqsave(&dd->dc8051_lock, flags);
8484
8485 /* We can't send any commands to the 8051 if it's in reset */
8486 if (dd->dc_shutdown) {
8487 return_code = -ENODEV;
8488 goto fail;
8489 }
8490
8491 /*
8492 * If an 8051 host command timed out previously, then the 8051 is
8493 * stuck.
8494 *
8495 * On first timeout, attempt to reset and restart the entire DC
8496 * block (including 8051). (Is this too big of a hammer?)
8497 *
8498 * If the 8051 times out a second time, the reset did not bring it
8499 * back to healthy life. In that case, fail any subsequent commands.
8500 */
8501 if (dd->dc8051_timed_out) {
8502 if (dd->dc8051_timed_out > 1) {
8503 dd_dev_err(dd,
8504 "Previous 8051 host command timed out, skipping command %u\n",
8505 type);
8506 return_code = -ENXIO;
8507 goto fail;
8508 }
8509 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
8510 dc_shutdown(dd);
8511 dc_start(dd);
8512 spin_lock_irqsave(&dd->dc8051_lock, flags);
8513 }
8514
8515 /*
8516 * If there is no timeout, then the 8051 command interface is
8517 * waiting for a command.
8518 */
8519
3bf40d65
DL		 8520 /*
8521 * When writing a LCB CSR, out_data contains the full value to
8522 * to be written, while in_data contains the relative LCB
8523 * address in 7:0. Do the work here, rather than the caller,
8524 * of distrubting the write data to where it needs to go:
8525 *
8526 * Write data
8527 * 39:00 -> in_data[47:8]
8528 * 47:40 -> DC8051_CFG_EXT_DEV_0.RETURN_CODE
8529 * 63:48 -> DC8051_CFG_EXT_DEV_0.RSP_DATA
8530 */
8531 if (type == HCMD_WRITE_LCB_CSR) {
8532 in_data |= ((*out_data) & 0xffffffffffull) << 8;
00801674
DL		 8533 /* must preserve COMPLETED - it is tied to hardware */
8534 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_0);
8535 reg &= DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK;
8536 reg |= ((((*out_data) >> 40) & 0xff) <<
3bf40d65
DL		 8537 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT)
8538 | ((((*out_data) >> 48) & 0xffff) <<
8539 DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT);
8540 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, reg);
8541 }
8542
77241056
MM		 8543 /*
8544 * Do two writes: the first to stabilize the type and req_data, the
8545 * second to activate.
8546 */
8547 reg = ((u64)type & DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_MASK)
8548 << DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_SHIFT
8549 | (in_data & DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_MASK)
8550 << DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_SHIFT;
8551 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
8552 reg |= DC_DC8051_CFG_HOST_CMD_0_REQ_NEW_SMASK;
8553 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
8554
8555 /* wait for completion, alternate: interrupt */
8556 timeout = jiffies + msecs_to_jiffies(DC8051_COMMAND_TIMEOUT);
8557 while (1) {
8558 reg = read_csr(dd, DC_DC8051_CFG_HOST_CMD_1);
8559 completed = reg & DC_DC8051_CFG_HOST_CMD_1_COMPLETED_SMASK;
8560 if (completed)
8561 break;
8562 if (time_after(jiffies, timeout)) {
8563 dd->dc8051_timed_out++;
8564 dd_dev_err(dd, "8051 host command %u timeout\n", type);
8565 if (out_data)
8566 *out_data = 0;
8567 return_code = -ETIMEDOUT;
8568 goto fail;
8569 }
8570 udelay(2);
8571 }
8572
8573 if (out_data) {
8574 *out_data = (reg >> DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_SHIFT)
8575 & DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_MASK;
8576 if (type == HCMD_READ_LCB_CSR) {
8577 /* top 16 bits are in a different register */
8578 *out_data |= (read_csr(dd, DC_DC8051_CFG_EXT_DEV_1)
8579 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SMASK)
8580 << (48
8581 - DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT);
8582 }
8583 }
8584 return_code = (reg >> DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_SHIFT)
8585 & DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_MASK;
8586 dd->dc8051_timed_out = 0;
8587 /*
8588 * Clear command for next user.
8589 */
8590 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, 0);
8591
8592fail:
8593 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
8594
8595 return return_code;
8596}
8597
8598static int set_physical_link_state(struct hfi1_devdata *dd, u64 state)
8599{
8600 return do_8051_command(dd, HCMD_CHANGE_PHY_STATE, state, NULL);
8601}
8602
8ebd4cf1
EH		 8603int load_8051_config(struct hfi1_devdata *dd, u8 field_id,
8604 u8 lane_id, u32 config_data)
77241056
MM		 8605{
8606 u64 data;
8607 int ret;
8608
8609 data = (u64)field_id << LOAD_DATA_FIELD_ID_SHIFT
8610 | (u64)lane_id << LOAD_DATA_LANE_ID_SHIFT
8611 | (u64)config_data << LOAD_DATA_DATA_SHIFT;
8612 ret = do_8051_command(dd, HCMD_LOAD_CONFIG_DATA, data, NULL);
8613 if (ret != HCMD_SUCCESS) {
8614 dd_dev_err(dd,
17fb4f29
JJ		 8615 "load 8051 config: field id %d, lane %d, err %d\n",
8616 (int)field_id, (int)lane_id, ret);
77241056
MM		 8617 }
8618 return ret;
8619}
8620
8621/*
8622 * Read the 8051 firmware "registers". Use the RAM directly. Always
8623 * set the result, even on error.
8624 * Return 0 on success, -errno on failure
8625 */
8ebd4cf1
EH		 8626int read_8051_config(struct hfi1_devdata *dd, u8 field_id, u8 lane_id,
8627 u32 *result)
77241056
MM		 8628{
8629 u64 big_data;
8630 u32 addr;
8631 int ret;
8632
8633 /* address start depends on the lane_id */
8634 if (lane_id < 4)
8635 addr = (4 * NUM_GENERAL_FIELDS)
8636 + (lane_id * 4 * NUM_LANE_FIELDS);
8637 else
8638 addr = 0;
8639 addr += field_id * 4;
8640
8641 /* read is in 8-byte chunks, hardware will truncate the address down */
8642 ret = read_8051_data(dd, addr, 8, &big_data);
8643
8644 if (ret == 0) {
8645 /* extract the 4 bytes we want */
8646 if (addr & 0x4)
8647 *result = (u32)(big_data >> 32);
8648 else
8649 *result = (u32)big_data;
8650 } else {
8651 *result = 0;
8652 dd_dev_err(dd, "%s: direct read failed, lane %d, field %d!\n",
17fb4f29 8653 __func__, lane_id, field_id);
77241056
MM		 8654 }
8655
8656 return ret;
8657}
8658
8659static int write_vc_local_phy(struct hfi1_devdata *dd, u8 power_management,
8660 u8 continuous)
8661{
8662 u32 frame;
8663
8664 frame = continuous << CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT
8665 | power_management << POWER_MANAGEMENT_SHIFT;
8666 return load_8051_config(dd, VERIFY_CAP_LOCAL_PHY,
8667 GENERAL_CONFIG, frame);
8668}
8669
8670static int write_vc_local_fabric(struct hfi1_devdata *dd, u8 vau, u8 z, u8 vcu,
8671 u16 vl15buf, u8 crc_sizes)
8672{
8673 u32 frame;
8674
8675 frame = (u32)vau << VAU_SHIFT
8676 | (u32)z << Z_SHIFT
8677 | (u32)vcu << VCU_SHIFT
8678 | (u32)vl15buf << VL15BUF_SHIFT
8679 | (u32)crc_sizes << CRC_SIZES_SHIFT;
8680 return load_8051_config(dd, VERIFY_CAP_LOCAL_FABRIC,
8681 GENERAL_CONFIG, frame);
8682}
8683
8684static void read_vc_local_link_width(struct hfi1_devdata *dd, u8 *misc_bits,
8685 u8 *flag_bits, u16 *link_widths)
8686{
8687 u32 frame;
8688
8689 read_8051_config(dd, VERIFY_CAP_LOCAL_LINK_WIDTH, GENERAL_CONFIG,
17fb4f29 8690 &frame);
77241056
MM		 8691 *misc_bits = (frame >> MISC_CONFIG_BITS_SHIFT) & MISC_CONFIG_BITS_MASK;
8692 *flag_bits = (frame >> LOCAL_FLAG_BITS_SHIFT) & LOCAL_FLAG_BITS_MASK;
8693 *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK;
8694}
8695
8696static int write_vc_local_link_width(struct hfi1_devdata *dd,
8697 u8 misc_bits,
8698 u8 flag_bits,
8699 u16 link_widths)
8700{
8701 u32 frame;
8702
8703 frame = (u32)misc_bits << MISC_CONFIG_BITS_SHIFT
8704 | (u32)flag_bits << LOCAL_FLAG_BITS_SHIFT
8705 | (u32)link_widths << LINK_WIDTH_SHIFT;
8706 return load_8051_config(dd, VERIFY_CAP_LOCAL_LINK_WIDTH, GENERAL_CONFIG,
8707 frame);
8708}
8709
8710static int write_local_device_id(struct hfi1_devdata *dd, u16 device_id,
8711 u8 device_rev)
8712{
8713 u32 frame;
8714
8715 frame = ((u32)device_id << LOCAL_DEVICE_ID_SHIFT)
8716 | ((u32)device_rev << LOCAL_DEVICE_REV_SHIFT);
8717 return load_8051_config(dd, LOCAL_DEVICE_ID, GENERAL_CONFIG, frame);
8718}
8719
8720static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id,
8721 u8 *device_rev)
8722{
8723 u32 frame;
8724
8725 read_8051_config(dd, REMOTE_DEVICE_ID, GENERAL_CONFIG, &frame);
8726 *device_id = (frame >> REMOTE_DEVICE_ID_SHIFT) & REMOTE_DEVICE_ID_MASK;
8727 *device_rev = (frame >> REMOTE_DEVICE_REV_SHIFT)
8728 & REMOTE_DEVICE_REV_MASK;
8729}
8730
8731void read_misc_status(struct hfi1_devdata *dd, u8 *ver_a, u8 *ver_b)
8732{
8733 u32 frame;
8734
8735 read_8051_config(dd, MISC_STATUS, GENERAL_CONFIG, &frame);
8736 *ver_a = (frame >> STS_FM_VERSION_A_SHIFT) & STS_FM_VERSION_A_MASK;
8737 *ver_b = (frame >> STS_FM_VERSION_B_SHIFT) & STS_FM_VERSION_B_MASK;
8738}
8739
8740static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management,
8741 u8 *continuous)
8742{
8743 u32 frame;
8744
8745 read_8051_config(dd, VERIFY_CAP_REMOTE_PHY, GENERAL_CONFIG, &frame);
8746 *power_management = (frame >> POWER_MANAGEMENT_SHIFT)
8747 & POWER_MANAGEMENT_MASK;
8748 *continuous = (frame >> CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT)
8749 & CONTINIOUS_REMOTE_UPDATE_SUPPORT_MASK;
8750}
8751
8752static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z,
8753 u8 *vcu, u16 *vl15buf, u8 *crc_sizes)
8754{
8755 u32 frame;
8756
8757 read_8051_config(dd, VERIFY_CAP_REMOTE_FABRIC, GENERAL_CONFIG, &frame);
8758 *vau = (frame >> VAU_SHIFT) & VAU_MASK;
8759 *z = (frame >> Z_SHIFT) & Z_MASK;
8760 *vcu = (frame >> VCU_SHIFT) & VCU_MASK;
8761 *vl15buf = (frame >> VL15BUF_SHIFT) & VL15BUF_MASK;
8762 *crc_sizes = (frame >> CRC_SIZES_SHIFT) & CRC_SIZES_MASK;
8763}
8764
8765static void read_vc_remote_link_width(struct hfi1_devdata *dd,
8766 u8 *remote_tx_rate,
8767 u16 *link_widths)
8768{
8769 u32 frame;
8770
8771 read_8051_config(dd, VERIFY_CAP_REMOTE_LINK_WIDTH, GENERAL_CONFIG,
17fb4f29 8772 &frame);
77241056
MM		 8773 *remote_tx_rate = (frame >> REMOTE_TX_RATE_SHIFT)
8774 & REMOTE_TX_RATE_MASK;
8775 *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK;
8776}
8777
8778static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx)
8779{
8780 u32 frame;
8781
8782 read_8051_config(dd, LOCAL_LNI_INFO, GENERAL_CONFIG, &frame);
8783 *enable_lane_rx = (frame >> ENABLE_LANE_RX_SHIFT) & ENABLE_LANE_RX_MASK;
8784}
8785
8786static void read_mgmt_allowed(struct hfi1_devdata *dd, u8 *mgmt_allowed)
8787{
8788 u32 frame;
8789
8790 read_8051_config(dd, REMOTE_LNI_INFO, GENERAL_CONFIG, &frame);
8791 *mgmt_allowed = (frame >> MGMT_ALLOWED_SHIFT) & MGMT_ALLOWED_MASK;
8792}
8793
8794static void read_last_local_state(struct hfi1_devdata *dd, u32 *lls)
8795{
8796 read_8051_config(dd, LAST_LOCAL_STATE_COMPLETE, GENERAL_CONFIG, lls);
8797}
8798
8799static void read_last_remote_state(struct hfi1_devdata *dd, u32 *lrs)
8800{
8801 read_8051_config(dd, LAST_REMOTE_STATE_COMPLETE, GENERAL_CONFIG, lrs);
8802}
8803
8804void hfi1_read_link_quality(struct hfi1_devdata *dd, u8 *link_quality)
8805{
8806 u32 frame;
8807 int ret;
8808
8809 *link_quality = 0;
8810 if (dd->pport->host_link_state & HLS_UP) {
8811 ret = read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG,
17fb4f29 8812 &frame);
77241056
MM		 8813 if (ret == 0)
8814 *link_quality = (frame >> LINK_QUALITY_SHIFT)
8815 & LINK_QUALITY_MASK;
8816 }
8817}
8818
8819static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc)
8820{
8821 u32 frame;
8822
8823 read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG, &frame);
8824 *pdrrc = (frame >> DOWN_REMOTE_REASON_SHIFT) & DOWN_REMOTE_REASON_MASK;
8825}
8826
feb831dd
DL		 8827static void read_link_down_reason(struct hfi1_devdata *dd, u8 *ldr)
8828{
8829 u32 frame;
8830
8831 read_8051_config(dd, LINK_DOWN_REASON, GENERAL_CONFIG, &frame);
8832 *ldr = (frame & 0xff);
8833}
8834
77241056
MM		 8835static int read_tx_settings(struct hfi1_devdata *dd,
8836 u8 *enable_lane_tx,
8837 u8 *tx_polarity_inversion,
8838 u8 *rx_polarity_inversion,
8839 u8 *max_rate)
8840{
8841 u32 frame;
8842 int ret;
8843
8844 ret = read_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, &frame);
8845 *enable_lane_tx = (frame >> ENABLE_LANE_TX_SHIFT)
8846 & ENABLE_LANE_TX_MASK;
8847 *tx_polarity_inversion = (frame >> TX_POLARITY_INVERSION_SHIFT)
8848 & TX_POLARITY_INVERSION_MASK;
8849 *rx_polarity_inversion = (frame >> RX_POLARITY_INVERSION_SHIFT)
8850 & RX_POLARITY_INVERSION_MASK;
8851 *max_rate = (frame >> MAX_RATE_SHIFT) & MAX_RATE_MASK;
8852 return ret;
8853}
8854
8855static int write_tx_settings(struct hfi1_devdata *dd,
8856 u8 enable_lane_tx,
8857 u8 tx_polarity_inversion,
8858 u8 rx_polarity_inversion,
8859 u8 max_rate)
8860{
8861 u32 frame;
8862
8863 /* no need to mask, all variable sizes match field widths */
8864 frame = enable_lane_tx << ENABLE_LANE_TX_SHIFT
8865 | tx_polarity_inversion << TX_POLARITY_INVERSION_SHIFT
8866 | rx_polarity_inversion << RX_POLARITY_INVERSION_SHIFT
8867 | max_rate << MAX_RATE_SHIFT;
8868 return load_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, frame);
8869}
8870
77241056
MM		 8871/*
8872 * Read an idle LCB message.
8873 *
8874 * Returns 0 on success, -EINVAL on error
8875 */
8876static int read_idle_message(struct hfi1_devdata *dd, u64 type, u64 *data_out)
8877{
8878 int ret;
8879
17fb4f29 8880 ret = do_8051_command(dd, HCMD_READ_LCB_IDLE_MSG, type, data_out);
77241056
MM		 8881 if (ret != HCMD_SUCCESS) {
8882 dd_dev_err(dd, "read idle message: type %d, err %d\n",
17fb4f29 8883 (u32)type, ret);
77241056
MM		 8884 return -EINVAL;
8885 }
8886 dd_dev_info(dd, "%s: read idle message 0x%llx\n", __func__, *data_out);
8887 /* return only the payload as we already know the type */
8888 *data_out >>= IDLE_PAYLOAD_SHIFT;
8889 return 0;
8890}
8891
8892/*
8893 * Read an idle SMA message. To be done in response to a notification from
8894 * the 8051.
8895 *
8896 * Returns 0 on success, -EINVAL on error
8897 */
8898static int read_idle_sma(struct hfi1_devdata *dd, u64 *data)
8899{
17fb4f29
JJ		 8900 return read_idle_message(dd, (u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT,
8901 data);
77241056
MM		 8902}
8903
8904/*
8905 * Send an idle LCB message.
8906 *
8907 * Returns 0 on success, -EINVAL on error
8908 */
8909static int send_idle_message(struct hfi1_devdata *dd, u64 data)
8910{
8911 int ret;
8912
8913 dd_dev_info(dd, "%s: sending idle message 0x%llx\n", __func__, data);
8914 ret = do_8051_command(dd, HCMD_SEND_LCB_IDLE_MSG, data, NULL);
8915 if (ret != HCMD_SUCCESS) {
8916 dd_dev_err(dd, "send idle message: data 0x%llx, err %d\n",
17fb4f29 8917 data, ret);
77241056
MM		 8918 return -EINVAL;
8919 }
8920 return 0;
8921}
8922
8923/*
8924 * Send an idle SMA message.
8925 *
8926 * Returns 0 on success, -EINVAL on error
8927 */
8928int send_idle_sma(struct hfi1_devdata *dd, u64 message)
8929{
8930 u64 data;
8931
17fb4f29
JJ		 8932 data = ((message & IDLE_PAYLOAD_MASK) << IDLE_PAYLOAD_SHIFT) |
8933 ((u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT);
77241056
MM		 8934 return send_idle_message(dd, data);
8935}
8936
8937/*
8938 * Initialize the LCB then do a quick link up. This may or may not be
8939 * in loopback.
8940 *
8941 * return 0 on success, -errno on error
8942 */
8943static int do_quick_linkup(struct hfi1_devdata *dd)
8944{
77241056
MM		 8945 int ret;
8946
8947 lcb_shutdown(dd, 0);
8948
8949 if (loopback) {
8950 /* LCB_CFG_LOOPBACK.VAL = 2 */
8951 /* LCB_CFG_LANE_WIDTH.VAL = 0 */
8952 write_csr(dd, DC_LCB_CFG_LOOPBACK,
17fb4f29 8953 IB_PACKET_TYPE << DC_LCB_CFG_LOOPBACK_VAL_SHIFT);
77241056
MM		 8954 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0);
8955 }
8956
8957 /* start the LCBs */
8958 /* LCB_CFG_TX_FIFOS_RESET.VAL = 0 */
8959 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
8960
8961 /* simulator only loopback steps */
8962 if (loopback && dd->icode == ICODE_FUNCTIONAL_SIMULATOR) {
8963 /* LCB_CFG_RUN.EN = 1 */
8964 write_csr(dd, DC_LCB_CFG_RUN,
17fb4f29 8965 1ull << DC_LCB_CFG_RUN_EN_SHIFT);
77241056 8966
ec8a1423
DL		 8967 ret = wait_link_transfer_active(dd, 10);
8968 if (ret)
8969 return ret;
77241056
MM		 8970
8971 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP,
17fb4f29 8972 1ull << DC_LCB_CFG_ALLOW_LINK_UP_VAL_SHIFT);
77241056
MM		 8973 }
8974
8975 if (!loopback) {
8976 /*
8977 * When doing quick linkup and not in loopback, both
8978 * sides must be done with LCB set-up before either
8979 * starts the quick linkup. Put a delay here so that
8980 * both sides can be started and have a chance to be
8981 * done with LCB set up before resuming.
8982 */
8983 dd_dev_err(dd,
17fb4f29 8984 "Pausing for peer to be finished with LCB set up\n");
77241056 8985 msleep(5000);
17fb4f29 8986 dd_dev_err(dd, "Continuing with quick linkup\n");
77241056
MM		 8987 }
8988
8989 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
8990 set_8051_lcb_access(dd);
8991
8992 /*
8993 * State "quick" LinkUp request sets the physical link state to
8994 * LinkUp without a verify capability sequence.
8995 * This state is in simulator v37 and later.
8996 */
8997 ret = set_physical_link_state(dd, PLS_QUICK_LINKUP);
8998 if (ret != HCMD_SUCCESS) {
8999 dd_dev_err(dd,
17fb4f29
JJ		 9000 "%s: set physical link state to quick LinkUp failed with return %d\n",
9001 __func__, ret);
77241056
MM		 9002
9003 set_host_lcb_access(dd);
9004 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
9005
9006 if (ret >= 0)
9007 ret = -EINVAL;
9008 return ret;
9009 }
9010
9011 return 0; /* success */
9012}
9013
9014/*
9015 * Set the SerDes to internal loopback mode.
9016 * Returns 0 on success, -errno on error.
9017 */
9018static int set_serdes_loopback_mode(struct hfi1_devdata *dd)
9019{
9020 int ret;
9021
9022 ret = set_physical_link_state(dd, PLS_INTERNAL_SERDES_LOOPBACK);
9023 if (ret == HCMD_SUCCESS)
9024 return 0;
9025 dd_dev_err(dd,
17fb4f29
JJ		 9026 "Set physical link state to SerDes Loopback failed with return %d\n",
9027 ret);
77241056
MM		 9028 if (ret >= 0)
9029 ret = -EINVAL;
9030 return ret;
9031}
9032
9033/*
9034 * Do all special steps to set up loopback.
9035 */
9036static int init_loopback(struct hfi1_devdata *dd)
9037{
9038 dd_dev_info(dd, "Entering loopback mode\n");
9039
9040 /* all loopbacks should disable self GUID check */
9041 write_csr(dd, DC_DC8051_CFG_MODE,
17fb4f29 9042 (read_csr(dd, DC_DC8051_CFG_MODE) | DISABLE_SELF_GUID_CHECK));
77241056
MM		 9043
9044 /*
9045 * The simulator has only one loopback option - LCB. Switch
9046 * to that option, which includes quick link up.
9047 *
9048 * Accept all valid loopback values.
9049 */
d0d236ea
JJ		 9050 if ((dd->icode == ICODE_FUNCTIONAL_SIMULATOR) &&
9051 (loopback == LOOPBACK_SERDES || loopback == LOOPBACK_LCB ||
9052 loopback == LOOPBACK_CABLE)) {
77241056
MM		 9053 loopback = LOOPBACK_LCB;
9054 quick_linkup = 1;
9055 return 0;
9056 }
9057
9058 /* handle serdes loopback */
9059 if (loopback == LOOPBACK_SERDES) {
9060 /* internal serdes loopack needs quick linkup on RTL */
9061 if (dd->icode == ICODE_RTL_SILICON)
9062 quick_linkup = 1;
9063 return set_serdes_loopback_mode(dd);
9064 }
9065
9066 /* LCB loopback - handled at poll time */
9067 if (loopback == LOOPBACK_LCB) {
9068 quick_linkup = 1; /* LCB is always quick linkup */
9069
9070 /* not supported in emulation due to emulation RTL changes */
9071 if (dd->icode == ICODE_FPGA_EMULATION) {
9072 dd_dev_err(dd,
17fb4f29 9073 "LCB loopback not supported in emulation\n");
77241056
MM		 9074 return -EINVAL;
9075 }
9076 return 0;
9077 }
9078
9079 /* external cable loopback requires no extra steps */
9080 if (loopback == LOOPBACK_CABLE)
9081 return 0;
9082
9083 dd_dev_err(dd, "Invalid loopback mode %d\n", loopback);
9084 return -EINVAL;
9085}
9086
9087/*
9088 * Translate from the OPA_LINK_WIDTH handed to us by the FM to bits
9089 * used in the Verify Capability link width attribute.
9090 */
9091static u16 opa_to_vc_link_widths(u16 opa_widths)
9092{
9093 int i;
9094 u16 result = 0;
9095
9096 static const struct link_bits {
9097 u16 from;
9098 u16 to;
9099 } opa_link_xlate[] = {
8638b77f
JJ		 9100 { OPA_LINK_WIDTH_1X, 1 << (1 - 1) },
9101 { OPA_LINK_WIDTH_2X, 1 << (2 - 1) },
9102 { OPA_LINK_WIDTH_3X, 1 << (3 - 1) },
9103 { OPA_LINK_WIDTH_4X, 1 << (4 - 1) },
77241056
MM		 9104 };
9105
9106 for (i = 0; i < ARRAY_SIZE(opa_link_xlate); i++) {
9107 if (opa_widths & opa_link_xlate[i].from)
9108 result |= opa_link_xlate[i].to;
9109 }
9110 return result;
9111}
9112
9113/*
9114 * Set link attributes before moving to polling.
9115 */
9116static int set_local_link_attributes(struct hfi1_pportdata *ppd)
9117{
9118 struct hfi1_devdata *dd = ppd->dd;
9119 u8 enable_lane_tx;
9120 u8 tx_polarity_inversion;
9121 u8 rx_polarity_inversion;
9122 int ret;
9123
9124 /* reset our fabric serdes to clear any lingering problems */
9125 fabric_serdes_reset(dd);
9126
9127 /* set the local tx rate - need to read-modify-write */
9128 ret = read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion,
17fb4f29 9129 &rx_polarity_inversion, &ppd->local_tx_rate);
77241056
MM		 9130 if (ret)
9131 goto set_local_link_attributes_fail;
9132
9133 if (dd->dc8051_ver < dc8051_ver(0, 20)) {
9134 /* set the tx rate to the fastest enabled */
9135 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G)
9136 ppd->local_tx_rate = 1;
9137 else
9138 ppd->local_tx_rate = 0;
9139 } else {
9140 /* set the tx rate to all enabled */
9141 ppd->local_tx_rate = 0;
9142 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G)
9143 ppd->local_tx_rate |= 2;
9144 if (ppd->link_speed_enabled & OPA_LINK_SPEED_12_5G)
9145 ppd->local_tx_rate |= 1;
9146 }
febffe2c
EH		 9147
9148 enable_lane_tx = 0xF; /* enable all four lanes */
77241056 9149 ret = write_tx_settings(dd, enable_lane_tx, tx_polarity_inversion,
17fb4f29 9150 rx_polarity_inversion, ppd->local_tx_rate);
77241056
MM		 9151 if (ret != HCMD_SUCCESS)
9152 goto set_local_link_attributes_fail;
9153
9154 /*
9155 * DC supports continuous updates.
9156 */
17fb4f29
JJ		 9157 ret = write_vc_local_phy(dd,
9158 0 /* no power management */,
9159 1 /* continuous updates */);
77241056
MM		 9160 if (ret != HCMD_SUCCESS)
9161 goto set_local_link_attributes_fail;
9162
9163 /* z=1 in the next call: AU of 0 is not supported by the hardware */
9164 ret = write_vc_local_fabric(dd, dd->vau, 1, dd->vcu, dd->vl15_init,
9165 ppd->port_crc_mode_enabled);
9166 if (ret != HCMD_SUCCESS)
9167 goto set_local_link_attributes_fail;
9168
9169 ret = write_vc_local_link_width(dd, 0, 0,
17fb4f29
JJ		 9170 opa_to_vc_link_widths(
9171 ppd->link_width_enabled));
77241056
MM		 9172 if (ret != HCMD_SUCCESS)
9173 goto set_local_link_attributes_fail;
9174
9175 /* let peer know who we are */
9176 ret = write_local_device_id(dd, dd->pcidev->device, dd->minrev);
9177 if (ret == HCMD_SUCCESS)
9178 return 0;
9179
9180set_local_link_attributes_fail:
9181 dd_dev_err(dd,
17fb4f29
JJ		 9182 "Failed to set local link attributes, return 0x%x\n",
9183 ret);
77241056
MM		 9184 return ret;
9185}
9186
9187/*
623bba2d
EH		 9188 * Call this to start the link.
9189 * Do not do anything if the link is disabled.
9190 * Returns 0 if link is disabled, moved to polling, or the driver is not ready.
77241056
MM		 9191 */
9192int start_link(struct hfi1_pportdata *ppd)
9193{
0db9dec2
DL		 9194 /*
9195 * Tune the SerDes to a ballpark setting for optimal signal and bit
9196 * error rate. Needs to be done before starting the link.
9197 */
9198 tune_serdes(ppd);
9199
77241056
MM		 9200 if (!ppd->link_enabled) {
9201 dd_dev_info(ppd->dd,
17fb4f29
JJ		 9202 "%s: stopping link start because link is disabled\n",
9203 __func__);
77241056
MM		 9204 return 0;
9205 }
9206 if (!ppd->driver_link_ready) {
9207 dd_dev_info(ppd->dd,
17fb4f29
JJ		 9208 "%s: stopping link start because driver is not ready\n",
9209 __func__);
77241056
MM		 9210 return 0;
9211 }
9212
3ec5fa28
SS		 9213 /*
9214 * FULL_MGMT_P_KEY is cleared from the pkey table, so that the
9215 * pkey table can be configured properly if the HFI unit is connected
9216 * to switch port with MgmtAllowed=NO
9217 */
9218 clear_full_mgmt_pkey(ppd);
9219
623bba2d 9220 return set_link_state(ppd, HLS_DN_POLL);
77241056
MM		 9221}
9222
8ebd4cf1
EH		 9223static void wait_for_qsfp_init(struct hfi1_pportdata *ppd)
9224{
9225 struct hfi1_devdata *dd = ppd->dd;
9226 u64 mask;
9227 unsigned long timeout;
9228
9229 /*
5fbd98dd
EH		 9230 * Some QSFP cables have a quirk that asserts the IntN line as a side
9231 * effect of power up on plug-in. We ignore this false positive
9232 * interrupt until the module has finished powering up by waiting for
9233 * a minimum timeout of the module inrush initialization time of
9234 * 500 ms (SFF 8679 Table 5-6) to ensure the voltage rails in the
9235 * module have stabilized.
9236 */
9237 msleep(500);
9238
9239 /*
9240 * Check for QSFP interrupt for t_init (SFF 8679 Table 8-1)
8ebd4cf1
EH		 9241 */
9242 timeout = jiffies + msecs_to_jiffies(2000);
9243 while (1) {
9244 mask = read_csr(dd, dd->hfi1_id ?
9245 ASIC_QSFP2_IN : ASIC_QSFP1_IN);
5fbd98dd 9246 if (!(mask & QSFP_HFI0_INT_N))
8ebd4cf1 9247 break;
8ebd4cf1
EH		 9248 if (time_after(jiffies, timeout)) {
9249 dd_dev_info(dd, "%s: No IntN detected, reset complete\n",
9250 __func__);
9251 break;
9252 }
9253 udelay(2);
9254 }
9255}
9256
9257static void set_qsfp_int_n(struct hfi1_pportdata *ppd, u8 enable)
9258{
9259 struct hfi1_devdata *dd = ppd->dd;
9260 u64 mask;
9261
9262 mask = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK);
5fbd98dd
EH		 9263 if (enable) {
9264 /*
9265 * Clear the status register to avoid an immediate interrupt
9266 * when we re-enable the IntN pin
9267 */
9268 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR,
9269 QSFP_HFI0_INT_N);
8ebd4cf1 9270 mask |= (u64)QSFP_HFI0_INT_N;
5fbd98dd 9271 } else {
8ebd4cf1 9272 mask &= ~(u64)QSFP_HFI0_INT_N;
5fbd98dd 9273 }
8ebd4cf1
EH		 9274 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, mask);
9275}
9276
9277void reset_qsfp(struct hfi1_pportdata *ppd)
77241056
MM		 9278{
9279 struct hfi1_devdata *dd = ppd->dd;
9280 u64 mask, qsfp_mask;
9281
8ebd4cf1
EH		 9282 /* Disable INT_N from triggering QSFP interrupts */
9283 set_qsfp_int_n(ppd, 0);
9284
9285 /* Reset the QSFP */
77241056 9286 mask = (u64)QSFP_HFI0_RESET_N;
77241056
MM		 9287
9288 qsfp_mask = read_csr(dd,
17fb4f29 9289 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT);
77241056
MM		 9290 qsfp_mask &= ~mask;
9291 write_csr(dd,
17fb4f29 9292 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask);
77241056
MM		 9293
9294 udelay(10);
9295
9296 qsfp_mask |= mask;
9297 write_csr(dd,
17fb4f29 9298 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask);
8ebd4cf1
EH		 9299
9300 wait_for_qsfp_init(ppd);
9301
9302 /*
9303 * Allow INT_N to trigger the QSFP interrupt to watch
9304 * for alarms and warnings
9305 */
9306 set_qsfp_int_n(ppd, 1);
77241056
MM		 9307}
9308
9309static int handle_qsfp_error_conditions(struct hfi1_pportdata *ppd,
9310 u8 *qsfp_interrupt_status)
9311{
9312 struct hfi1_devdata *dd = ppd->dd;
9313
9314 if ((qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_ALARM) ||
17fb4f29
JJ		 9315 (qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_WARNING))
9316 dd_dev_info(dd, "%s: QSFP cable on fire\n",
9317 __func__);
77241056
MM		 9318
9319 if ((qsfp_interrupt_status[0] & QSFP_LOW_TEMP_ALARM) ||
17fb4f29
JJ		 9320 (qsfp_interrupt_status[0] & QSFP_LOW_TEMP_WARNING))
9321 dd_dev_info(dd, "%s: QSFP cable temperature too low\n",
9322 __func__);
77241056 9323
0c7f77af
EH		 9324 /*
9325 * The remaining alarms/warnings don't matter if the link is down.
9326 */
9327 if (ppd->host_link_state & HLS_DOWN)
9328 return 0;
9329
77241056 9330 if ((qsfp_interrupt_status[1] & QSFP_HIGH_VCC_ALARM) ||
17fb4f29
JJ		 9331 (qsfp_interrupt_status[1] & QSFP_HIGH_VCC_WARNING))
9332 dd_dev_info(dd, "%s: QSFP supply voltage too high\n",
9333 __func__);
77241056
MM		 9334
9335 if ((qsfp_interrupt_status[1] & QSFP_LOW_VCC_ALARM) ||
17fb4f29
JJ		 9336 (qsfp_interrupt_status[1] & QSFP_LOW_VCC_WARNING))
9337 dd_dev_info(dd, "%s: QSFP supply voltage too low\n",
9338 __func__);
77241056
MM		 9339
9340 /* Byte 2 is vendor specific */
9341
9342 if ((qsfp_interrupt_status[3] & QSFP_HIGH_POWER_ALARM) ||
17fb4f29
JJ		 9343 (qsfp_interrupt_status[3] & QSFP_HIGH_POWER_WARNING))
9344 dd_dev_info(dd, "%s: Cable RX channel 1/2 power too high\n",
9345 __func__);
77241056
MM		 9346
9347 if ((qsfp_interrupt_status[3] & QSFP_LOW_POWER_ALARM) ||
17fb4f29
JJ		 9348 (qsfp_interrupt_status[3] & QSFP_LOW_POWER_WARNING))
9349 dd_dev_info(dd, "%s: Cable RX channel 1/2 power too low\n",
9350 __func__);
77241056
MM		 9351
9352 if ((qsfp_interrupt_status[4] & QSFP_HIGH_POWER_ALARM) ||
17fb4f29
JJ		 9353 (qsfp_interrupt_status[4] & QSFP_HIGH_POWER_WARNING))
9354 dd_dev_info(dd, "%s: Cable RX channel 3/4 power too high\n",
9355 __func__);
77241056
MM		 9356
9357 if ((qsfp_interrupt_status[4] & QSFP_LOW_POWER_ALARM) ||
17fb4f29
JJ		 9358 (qsfp_interrupt_status[4] & QSFP_LOW_POWER_WARNING))
9359 dd_dev_info(dd, "%s: Cable RX channel 3/4 power too low\n",
9360 __func__);
77241056
MM		 9361
9362 if ((qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_ALARM) ||
17fb4f29
JJ		 9363 (qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_WARNING))
9364 dd_dev_info(dd, "%s: Cable TX channel 1/2 bias too high\n",
9365 __func__);
77241056
MM		 9366
9367 if ((qsfp_interrupt_status[5] & QSFP_LOW_BIAS_ALARM) ||
17fb4f29
JJ		 9368 (qsfp_interrupt_status[5] & QSFP_LOW_BIAS_WARNING))
9369 dd_dev_info(dd, "%s: Cable TX channel 1/2 bias too low\n",
9370 __func__);
77241056
MM		 9371
9372 if ((qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_ALARM) ||
17fb4f29
JJ		 9373 (qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_WARNING))
9374 dd_dev_info(dd, "%s: Cable TX channel 3/4 bias too high\n",
9375 __func__);
77241056
MM		 9376
9377 if ((qsfp_interrupt_status[6] & QSFP_LOW_BIAS_ALARM) ||
17fb4f29
JJ		 9378 (qsfp_interrupt_status[6] & QSFP_LOW_BIAS_WARNING))
9379 dd_dev_info(dd, "%s: Cable TX channel 3/4 bias too low\n",
9380 __func__);
77241056
MM		 9381
9382 if ((qsfp_interrupt_status[7] & QSFP_HIGH_POWER_ALARM) ||
17fb4f29
JJ		 9383 (qsfp_interrupt_status[7] & QSFP_HIGH_POWER_WARNING))
9384 dd_dev_info(dd, "%s: Cable TX channel 1/2 power too high\n",
9385 __func__);
77241056
MM		 9386
9387 if ((qsfp_interrupt_status[7] & QSFP_LOW_POWER_ALARM) ||
17fb4f29
JJ		 9388 (qsfp_interrupt_status[7] & QSFP_LOW_POWER_WARNING))
9389 dd_dev_info(dd, "%s: Cable TX channel 1/2 power too low\n",
9390 __func__);
77241056
MM		 9391
9392 if ((qsfp_interrupt_status[8] & QSFP_HIGH_POWER_ALARM) ||
17fb4f29
JJ		 9393 (qsfp_interrupt_status[8] & QSFP_HIGH_POWER_WARNING))
9394 dd_dev_info(dd, "%s: Cable TX channel 3/4 power too high\n",
9395 __func__);
77241056
MM		 9396
9397 if ((qsfp_interrupt_status[8] & QSFP_LOW_POWER_ALARM) ||
17fb4f29
JJ		 9398 (qsfp_interrupt_status[8] & QSFP_LOW_POWER_WARNING))
9399 dd_dev_info(dd, "%s: Cable TX channel 3/4 power too low\n",
9400 __func__);
77241056
MM		 9401
9402 /* Bytes 9-10 and 11-12 are reserved */
9403 /* Bytes 13-15 are vendor specific */
9404
9405 return 0;
9406}
9407
623bba2d 9408/* This routine will only be scheduled if the QSFP module present is asserted */
8ebd4cf1 9409void qsfp_event(struct work_struct *work)
77241056
MM		 9410{
9411 struct qsfp_data *qd;
9412 struct hfi1_pportdata *ppd;
9413 struct hfi1_devdata *dd;
9414
9415 qd = container_of(work, struct qsfp_data, qsfp_work);
9416 ppd = qd->ppd;
9417 dd = ppd->dd;
9418
9419 /* Sanity check */
9420 if (!qsfp_mod_present(ppd))
9421 return;
9422
9423 /*
0c7f77af
EH		 9424 * Turn DC back on after cable has been re-inserted. Up until
9425 * now, the DC has been in reset to save power.
77241056
MM		 9426 */
9427 dc_start(dd);
9428
9429 if (qd->cache_refresh_required) {
8ebd4cf1 9430 set_qsfp_int_n(ppd, 0);
77241056 9431
8ebd4cf1
EH		 9432 wait_for_qsfp_init(ppd);
9433
9434 /*
9435 * Allow INT_N to trigger the QSFP interrupt to watch
9436 * for alarms and warnings
77241056 9437 */
8ebd4cf1
EH		 9438 set_qsfp_int_n(ppd, 1);
9439
8ebd4cf1 9440 start_link(ppd);
77241056
MM		 9441 }
9442
9443 if (qd->check_interrupt_flags) {
9444 u8 qsfp_interrupt_status[16] = {0,};
9445
765a6fac
DL		 9446 if (one_qsfp_read(ppd, dd->hfi1_id, 6,
9447 &qsfp_interrupt_status[0], 16) != 16) {
77241056 9448 dd_dev_info(dd,
17fb4f29
JJ		 9449 "%s: Failed to read status of QSFP module\n",
9450 __func__);
77241056
MM		 9451 } else {
9452 unsigned long flags;
77241056 9453
8ebd4cf1
EH		 9454 handle_qsfp_error_conditions(
9455 ppd, qsfp_interrupt_status);
77241056
MM		 9456 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
9457 ppd->qsfp_info.check_interrupt_flags = 0;
9458 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
17fb4f29 9459 flags);
77241056
MM		 9460 }
9461 }
9462}
9463
8ebd4cf1 9464static void init_qsfp_int(struct hfi1_devdata *dd)
77241056 9465{
8ebd4cf1
EH		 9466 struct hfi1_pportdata *ppd = dd->pport;
9467 u64 qsfp_mask, cce_int_mask;
9468 const int qsfp1_int_smask = QSFP1_INT % 64;
9469 const int qsfp2_int_smask = QSFP2_INT % 64;
77241056 9470
8ebd4cf1
EH		 9471 /*
9472 * disable QSFP1 interrupts for HFI1, QSFP2 interrupts for HFI0
9473 * Qsfp1Int and Qsfp2Int are adjacent bits in the same CSR,
9474 * therefore just one of QSFP1_INT/QSFP2_INT can be used to find
9475 * the index of the appropriate CSR in the CCEIntMask CSR array
9476 */
9477 cce_int_mask = read_csr(dd, CCE_INT_MASK +
9478 (8 * (QSFP1_INT / 64)));
9479 if (dd->hfi1_id) {
9480 cce_int_mask &= ~((u64)1 << qsfp1_int_smask);
9481 write_csr(dd, CCE_INT_MASK + (8 * (QSFP1_INT / 64)),
9482 cce_int_mask);
9483 } else {
9484 cce_int_mask &= ~((u64)1 << qsfp2_int_smask);
9485 write_csr(dd, CCE_INT_MASK + (8 * (QSFP2_INT / 64)),
9486 cce_int_mask);
77241056
MM		 9487 }
9488
77241056
MM		 9489 qsfp_mask = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N);
9490 /* Clear current status to avoid spurious interrupts */
8ebd4cf1
EH		 9491 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR,
9492 qsfp_mask);
9493 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK,
9494 qsfp_mask);
9495
9496 set_qsfp_int_n(ppd, 0);
77241056
MM		 9497
9498 /* Handle active low nature of INT_N and MODPRST_N pins */
9499 if (qsfp_mod_present(ppd))
9500 qsfp_mask &= ~(u64)QSFP_HFI0_MODPRST_N;
9501 write_csr(dd,
9502 dd->hfi1_id ? ASIC_QSFP2_INVERT : ASIC_QSFP1_INVERT,
9503 qsfp_mask);
77241056
MM		 9504}
9505
bbdeb33d
DL		 9506/*
9507 * Do a one-time initialize of the LCB block.
9508 */
9509static void init_lcb(struct hfi1_devdata *dd)
9510{
a59329d5
DL		 9511 /* simulator does not correctly handle LCB cclk loopback, skip */
9512 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
9513 return;
9514
bbdeb33d
DL		 9515 /* the DC has been reset earlier in the driver load */
9516
9517 /* set LCB for cclk loopback on the port */
9518 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x01);
9519 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0x00);
9520 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0x00);
9521 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110);
9522 write_csr(dd, DC_LCB_CFG_CLK_CNTR, 0x08);
9523 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x02);
9524 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x00);
9525}
9526
673b975f
DL		 9527/*
9528 * Perform a test read on the QSFP. Return 0 on success, -ERRNO
9529 * on error.
9530 */
9531static int test_qsfp_read(struct hfi1_pportdata *ppd)
9532{
9533 int ret;
9534 u8 status;
9535
9536 /* report success if not a QSFP */
9537 if (ppd->port_type != PORT_TYPE_QSFP)
9538 return 0;
9539
9540 /* read byte 2, the status byte */
9541 ret = one_qsfp_read(ppd, ppd->dd->hfi1_id, 2, &status, 1);
9542 if (ret < 0)
9543 return ret;
9544 if (ret != 1)
9545 return -EIO;
9546
9547 return 0; /* success */
9548}
9549
9550/*
9551 * Values for QSFP retry.
9552 *
9553 * Give up after 10s (20 x 500ms). The overall timeout was empirically
9554 * arrived at from experience on a large cluster.
9555 */
9556#define MAX_QSFP_RETRIES 20
9557#define QSFP_RETRY_WAIT 500 /* msec */
9558
9559/*
9560 * Try a QSFP read. If it fails, schedule a retry for later.
9561 * Called on first link activation after driver load.
9562 */
9563static void try_start_link(struct hfi1_pportdata *ppd)
9564{
9565 if (test_qsfp_read(ppd)) {
9566 /* read failed */
9567 if (ppd->qsfp_retry_count >= MAX_QSFP_RETRIES) {
9568 dd_dev_err(ppd->dd, "QSFP not responding, giving up\n");
9569 return;
9570 }
9571 dd_dev_info(ppd->dd,
9572 "QSFP not responding, waiting and retrying %d\n",
9573 (int)ppd->qsfp_retry_count);
9574 ppd->qsfp_retry_count++;
9575 queue_delayed_work(ppd->hfi1_wq, &ppd->start_link_work,
9576 msecs_to_jiffies(QSFP_RETRY_WAIT));
9577 return;
9578 }
9579 ppd->qsfp_retry_count = 0;
9580
673b975f
DL		 9581 start_link(ppd);
9582}
9583
9584/*
9585 * Workqueue function to start the link after a delay.
9586 */
9587void handle_start_link(struct work_struct *work)
9588{
9589 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
9590 start_link_work.work);
9591 try_start_link(ppd);
9592}
9593
77241056
MM		 9594int bringup_serdes(struct hfi1_pportdata *ppd)
9595{
9596 struct hfi1_devdata *dd = ppd->dd;
9597 u64 guid;
9598 int ret;
9599
9600 if (HFI1_CAP_IS_KSET(EXTENDED_PSN))
9601 add_rcvctrl(dd, RCV_CTRL_RCV_EXTENDED_PSN_ENABLE_SMASK);
9602
a6cd5f08 9603 guid = ppd->guids[HFI1_PORT_GUID_INDEX];
77241056
MM		 9604 if (!guid) {
9605 if (dd->base_guid)
9606 guid = dd->base_guid + ppd->port - 1;
a6cd5f08 9607 ppd->guids[HFI1_PORT_GUID_INDEX] = guid;
77241056
MM		 9608 }
9609
77241056
MM		 9610 /* Set linkinit_reason on power up per OPA spec */
9611 ppd->linkinit_reason = OPA_LINKINIT_REASON_LINKUP;
9612
bbdeb33d
DL		 9613 /* one-time init of the LCB */
9614 init_lcb(dd);
9615
77241056
MM		 9616 if (loopback) {
9617 ret = init_loopback(dd);
9618 if (ret < 0)
9619 return ret;
9620 }
9621
9775a991
EH		 9622 get_port_type(ppd);
9623 if (ppd->port_type == PORT_TYPE_QSFP) {
9624 set_qsfp_int_n(ppd, 0);
9625 wait_for_qsfp_init(ppd);
9626 set_qsfp_int_n(ppd, 1);
9627 }
9628
673b975f
DL		 9629 try_start_link(ppd);
9630 return 0;
77241056
MM		 9631}
9632
9633void hfi1_quiet_serdes(struct hfi1_pportdata *ppd)
9634{
9635 struct hfi1_devdata *dd = ppd->dd;
9636
9637 /*
9638 * Shut down the link and keep it down. First turn off that the
9639 * driver wants to allow the link to be up (driver_link_ready).
9640 * Then make sure the link is not automatically restarted
9641 * (link_enabled). Cancel any pending restart. And finally
9642 * go offline.
9643 */
9644 ppd->driver_link_ready = 0;
9645 ppd->link_enabled = 0;
9646
673b975f
DL		 9647 ppd->qsfp_retry_count = MAX_QSFP_RETRIES; /* prevent more retries */
9648 flush_delayed_work(&ppd->start_link_work);
9649 cancel_delayed_work_sync(&ppd->start_link_work);
9650
8ebd4cf1
EH		 9651 ppd->offline_disabled_reason =
9652 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_SMA_DISABLED);
77241056 9653 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_SMA_DISABLED, 0,
17fb4f29 9654 OPA_LINKDOWN_REASON_SMA_DISABLED);
77241056
MM		 9655 set_link_state(ppd, HLS_DN_OFFLINE);
9656
9657 /* disable the port */
9658 clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
9659}
9660
9661static inline int init_cpu_counters(struct hfi1_devdata *dd)
9662{
9663 struct hfi1_pportdata *ppd;
9664 int i;
9665
9666 ppd = (struct hfi1_pportdata *)(dd + 1);
9667 for (i = 0; i < dd->num_pports; i++, ppd++) {
4eb06882
DD		 9668 ppd->ibport_data.rvp.rc_acks = NULL;
9669 ppd->ibport_data.rvp.rc_qacks = NULL;
9670 ppd->ibport_data.rvp.rc_acks = alloc_percpu(u64);
9671 ppd->ibport_data.rvp.rc_qacks = alloc_percpu(u64);
9672 ppd->ibport_data.rvp.rc_delayed_comp = alloc_percpu(u64);
9673 if (!ppd->ibport_data.rvp.rc_acks ||
9674 !ppd->ibport_data.rvp.rc_delayed_comp ||
9675 !ppd->ibport_data.rvp.rc_qacks)
77241056
MM		 9676 return -ENOMEM;
9677 }
9678
9679 return 0;
9680}
9681
9682static const char * const pt_names[] = {
9683 "expected",
9684 "eager",
9685 "invalid"
9686};
9687
9688static const char *pt_name(u32 type)
9689{
9690 return type >= ARRAY_SIZE(pt_names) ? "unknown" : pt_names[type];
9691}
9692
9693/*
9694 * index is the index into the receive array
9695 */
9696void hfi1_put_tid(struct hfi1_devdata *dd, u32 index,
9697 u32 type, unsigned long pa, u16 order)
9698{
9699 u64 reg;
9700 void __iomem *base = (dd->rcvarray_wc ? dd->rcvarray_wc :
9701 (dd->kregbase + RCV_ARRAY));
9702
9703 if (!(dd->flags & HFI1_PRESENT))
9704 goto done;
9705
9706 if (type == PT_INVALID) {
9707 pa = 0;
9708 } else if (type > PT_INVALID) {
9709 dd_dev_err(dd,
17fb4f29
JJ		 9710 "unexpected receive array type %u for index %u, not handled\n",
9711 type, index);
77241056
MM		 9712 goto done;
9713 }
9714
9715 hfi1_cdbg(TID, "type %s, index 0x%x, pa 0x%lx, bsize 0x%lx",
9716 pt_name(type), index, pa, (unsigned long)order);
9717
9718#define RT_ADDR_SHIFT 12 /* 4KB kernel address boundary */
9719 reg = RCV_ARRAY_RT_WRITE_ENABLE_SMASK
9720 | (u64)order << RCV_ARRAY_RT_BUF_SIZE_SHIFT
9721 | ((pa >> RT_ADDR_SHIFT) & RCV_ARRAY_RT_ADDR_MASK)
9722 << RCV_ARRAY_RT_ADDR_SHIFT;
9723 writeq(reg, base + (index * 8));
9724
9725 if (type == PT_EAGER)
9726 /*
9727 * Eager entries are written one-by-one so we have to push them
9728 * after we write the entry.
9729 */
9730 flush_wc();
9731done:
9732 return;
9733}
9734
9735void hfi1_clear_tids(struct hfi1_ctxtdata *rcd)
9736{
9737 struct hfi1_devdata *dd = rcd->dd;
9738 u32 i;
9739
9740 /* this could be optimized */
9741 for (i = rcd->eager_base; i < rcd->eager_base +
9742 rcd->egrbufs.alloced; i++)
9743 hfi1_put_tid(dd, i, PT_INVALID, 0, 0);
9744
9745 for (i = rcd->expected_base;
9746 i < rcd->expected_base + rcd->expected_count; i++)
9747 hfi1_put_tid(dd, i, PT_INVALID, 0, 0);
9748}
9749
261a4351
MM		 9750struct ib_header *hfi1_get_msgheader(
9751 struct hfi1_devdata *dd, __le32 *rhf_addr)
77241056
MM		 9752{
9753 u32 offset = rhf_hdrq_offset(rhf_to_cpu(rhf_addr));
9754
261a4351 9755 return (struct ib_header *)
77241056
MM		 9756 (rhf_addr - dd->rhf_offset + offset);
9757}
9758
9759static const char * const ib_cfg_name_strings[] = {
9760 "HFI1_IB_CFG_LIDLMC",
9761 "HFI1_IB_CFG_LWID_DG_ENB",
9762 "HFI1_IB_CFG_LWID_ENB",
9763 "HFI1_IB_CFG_LWID",
9764 "HFI1_IB_CFG_SPD_ENB",
9765 "HFI1_IB_CFG_SPD",
9766 "HFI1_IB_CFG_RXPOL_ENB",
9767 "HFI1_IB_CFG_LREV_ENB",
9768 "HFI1_IB_CFG_LINKLATENCY",
9769 "HFI1_IB_CFG_HRTBT",
9770 "HFI1_IB_CFG_OP_VLS",
9771 "HFI1_IB_CFG_VL_HIGH_CAP",
9772 "HFI1_IB_CFG_VL_LOW_CAP",
9773 "HFI1_IB_CFG_OVERRUN_THRESH",
9774 "HFI1_IB_CFG_PHYERR_THRESH",
9775 "HFI1_IB_CFG_LINKDEFAULT",
9776 "HFI1_IB_CFG_PKEYS",
9777 "HFI1_IB_CFG_MTU",
9778 "HFI1_IB_CFG_LSTATE",
9779 "HFI1_IB_CFG_VL_HIGH_LIMIT",
9780 "HFI1_IB_CFG_PMA_TICKS",
9781 "HFI1_IB_CFG_PORT"
9782};
9783
9784static const char *ib_cfg_name(int which)
9785{
9786 if (which < 0 || which >= ARRAY_SIZE(ib_cfg_name_strings))
9787 return "invalid";
9788 return ib_cfg_name_strings[which];
9789}
9790
9791int hfi1_get_ib_cfg(struct hfi1_pportdata *ppd, int which)
9792{
9793 struct hfi1_devdata *dd = ppd->dd;
9794 int val = 0;
9795
9796 switch (which) {
9797 case HFI1_IB_CFG_LWID_ENB: /* allowed Link-width */
9798 val = ppd->link_width_enabled;
9799 break;
9800 case HFI1_IB_CFG_LWID: /* currently active Link-width */
9801 val = ppd->link_width_active;
9802 break;
9803 case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */
9804 val = ppd->link_speed_enabled;
9805 break;
9806 case HFI1_IB_CFG_SPD: /* current Link speed */
9807 val = ppd->link_speed_active;
9808 break;
9809
9810 case HFI1_IB_CFG_RXPOL_ENB: /* Auto-RX-polarity enable */
9811 case HFI1_IB_CFG_LREV_ENB: /* Auto-Lane-reversal enable */
9812 case HFI1_IB_CFG_LINKLATENCY:
9813 goto unimplemented;
9814
9815 case HFI1_IB_CFG_OP_VLS:
9816 val = ppd->vls_operational;
9817 break;
9818 case HFI1_IB_CFG_VL_HIGH_CAP: /* VL arb high priority table size */
9819 val = VL_ARB_HIGH_PRIO_TABLE_SIZE;
9820 break;
9821 case HFI1_IB_CFG_VL_LOW_CAP: /* VL arb low priority table size */
9822 val = VL_ARB_LOW_PRIO_TABLE_SIZE;
9823 break;
9824 case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
9825 val = ppd->overrun_threshold;
9826 break;
9827 case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
9828 val = ppd->phy_error_threshold;
9829 break;
9830 case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
9831 val = dd->link_default;
9832 break;
9833
9834 case HFI1_IB_CFG_HRTBT: /* Heartbeat off/enable/auto */
9835 case HFI1_IB_CFG_PMA_TICKS:
9836 default:
9837unimplemented:
9838 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
9839 dd_dev_info(
9840 dd,
9841 "%s: which %s: not implemented\n",
9842 __func__,
9843 ib_cfg_name(which));
9844 break;
9845 }
9846
9847 return val;
9848}
9849
9850/*
9851 * The largest MAD packet size.
9852 */
9853#define MAX_MAD_PACKET 2048
9854
9855/*
9856 * Return the maximum header bytes that can go on the _wire_
9857 * for this device. This count includes the ICRC which is
9858 * not part of the packet held in memory but it is appended
9859 * by the HW.
9860 * This is dependent on the device's receive header entry size.
9861 * HFI allows this to be set per-receive context, but the
9862 * driver presently enforces a global value.
9863 */
9864u32 lrh_max_header_bytes(struct hfi1_devdata *dd)
9865{
9866 /*
9867 * The maximum non-payload (MTU) bytes in LRH.PktLen are
9868 * the Receive Header Entry Size minus the PBC (or RHF) size
9869 * plus one DW for the ICRC appended by HW.
9870 *
9871 * dd->rcd[0].rcvhdrqentsize is in DW.
9872 * We use rcd[0] as all context will have the same value. Also,
9873 * the first kernel context would have been allocated by now so
9874 * we are guaranteed a valid value.
9875 */
9876 return (dd->rcd[0]->rcvhdrqentsize - 2/*PBC/RHF*/ + 1/*ICRC*/) << 2;
9877}
9878
9879/*
9880 * Set Send Length
9881 * @ppd - per port data
9882 *
9883 * Set the MTU by limiting how many DWs may be sent. The SendLenCheck*
9884 * registers compare against LRH.PktLen, so use the max bytes included
9885 * in the LRH.
9886 *
9887 * This routine changes all VL values except VL15, which it maintains at
9888 * the same value.
9889 */
9890static void set_send_length(struct hfi1_pportdata *ppd)
9891{
9892 struct hfi1_devdata *dd = ppd->dd;
6cc6ad2e
HC		 9893 u32 max_hb = lrh_max_header_bytes(dd), dcmtu;
9894 u32 maxvlmtu = dd->vld[15].mtu;
77241056
MM		 9895 u64 len1 = 0, len2 = (((dd->vld[15].mtu + max_hb) >> 2)
9896 & SEND_LEN_CHECK1_LEN_VL15_MASK) <<
9897 SEND_LEN_CHECK1_LEN_VL15_SHIFT;
b4ba6633 9898 int i, j;
44306f15 9899 u32 thres;
77241056
MM		 9900
9901 for (i = 0; i < ppd->vls_supported; i++) {
9902 if (dd->vld[i].mtu > maxvlmtu)
9903 maxvlmtu = dd->vld[i].mtu;
9904 if (i <= 3)
9905 len1 |= (((dd->vld[i].mtu + max_hb) >> 2)
9906 & SEND_LEN_CHECK0_LEN_VL0_MASK) <<
9907 ((i % 4) * SEND_LEN_CHECK0_LEN_VL1_SHIFT);
9908 else
9909 len2 |= (((dd->vld[i].mtu + max_hb) >> 2)
9910 & SEND_LEN_CHECK1_LEN_VL4_MASK) <<
9911 ((i % 4) * SEND_LEN_CHECK1_LEN_VL5_SHIFT);
9912 }
9913 write_csr(dd, SEND_LEN_CHECK0, len1);
9914 write_csr(dd, SEND_LEN_CHECK1, len2);
9915 /* adjust kernel credit return thresholds based on new MTUs */
9916 /* all kernel receive contexts have the same hdrqentsize */
9917 for (i = 0; i < ppd->vls_supported; i++) {
44306f15
JX		 9918 thres = min(sc_percent_to_threshold(dd->vld[i].sc, 50),
9919 sc_mtu_to_threshold(dd->vld[i].sc,
9920 dd->vld[i].mtu,
17fb4f29 9921 dd->rcd[0]->rcvhdrqentsize));
b4ba6633
JJ		 9922 for (j = 0; j < INIT_SC_PER_VL; j++)
9923 sc_set_cr_threshold(
9924 pio_select_send_context_vl(dd, j, i),
9925 thres);
44306f15
JX		 9926 }
9927 thres = min(sc_percent_to_threshold(dd->vld[15].sc, 50),
9928 sc_mtu_to_threshold(dd->vld[15].sc,
9929 dd->vld[15].mtu,
9930 dd->rcd[0]->rcvhdrqentsize));
9931 sc_set_cr_threshold(dd->vld[15].sc, thres);
77241056
MM		 9932
9933 /* Adjust maximum MTU for the port in DC */
9934 dcmtu = maxvlmtu == 10240 ? DCC_CFG_PORT_MTU_CAP_10240 :
9935 (ilog2(maxvlmtu >> 8) + 1);
9936 len1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG);
9937 len1 &= ~DCC_CFG_PORT_CONFIG_MTU_CAP_SMASK;
9938 len1 |= ((u64)dcmtu & DCC_CFG_PORT_CONFIG_MTU_CAP_MASK) <<
9939 DCC_CFG_PORT_CONFIG_MTU_CAP_SHIFT;
9940 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG, len1);
9941}
9942
9943static void set_lidlmc(struct hfi1_pportdata *ppd)
9944{
9945 int i;
9946 u64 sreg = 0;
9947 struct hfi1_devdata *dd = ppd->dd;
9948 u32 mask = ~((1U << ppd->lmc) - 1);
9949 u64 c1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG1);
9950
77241056
MM		 9951 c1 &= ~(DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK
9952 | DCC_CFG_PORT_CONFIG1_DLID_MASK_SMASK);
9953 c1 |= ((ppd->lid & DCC_CFG_PORT_CONFIG1_TARGET_DLID_MASK)
8638b77f 9954 << DCC_CFG_PORT_CONFIG1_TARGET_DLID_SHIFT) |
77241056
MM		 9955 ((mask & DCC_CFG_PORT_CONFIG1_DLID_MASK_MASK)
9956 << DCC_CFG_PORT_CONFIG1_DLID_MASK_SHIFT);
9957 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG1, c1);
9958
9959 /*
9960 * Iterate over all the send contexts and set their SLID check
9961 */
9962 sreg = ((mask & SEND_CTXT_CHECK_SLID_MASK_MASK) <<
9963 SEND_CTXT_CHECK_SLID_MASK_SHIFT) |
9964 (((ppd->lid & mask) & SEND_CTXT_CHECK_SLID_VALUE_MASK) <<
9965 SEND_CTXT_CHECK_SLID_VALUE_SHIFT);
9966
9967 for (i = 0; i < dd->chip_send_contexts; i++) {
9968 hfi1_cdbg(LINKVERB, "SendContext[%d].SLID_CHECK = 0x%x",
9969 i, (u32)sreg);
9970 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, sreg);
9971 }
9972
9973 /* Now we have to do the same thing for the sdma engines */
9974 sdma_update_lmc(dd, mask, ppd->lid);
9975}
9976
9977static int wait_phy_linkstate(struct hfi1_devdata *dd, u32 state, u32 msecs)
9978{
9979 unsigned long timeout;
9980 u32 curr_state;
9981
9982 timeout = jiffies + msecs_to_jiffies(msecs);
9983 while (1) {
9984 curr_state = read_physical_state(dd);
9985 if (curr_state == state)
9986 break;
9987 if (time_after(jiffies, timeout)) {
9988 dd_dev_err(dd,
17fb4f29
JJ		 9989 "timeout waiting for phy link state 0x%x, current state is 0x%x\n",
9990 state, curr_state);
77241056
MM		 9991 return -ETIMEDOUT;
9992 }
9993 usleep_range(1950, 2050); /* sleep 2ms-ish */
9994 }
9995
9996 return 0;
9997}
9998
6854c692
DL		 9999static const char *state_completed_string(u32 completed)
10000{
10001 static const char * const state_completed[] = {
10002 "EstablishComm",
10003 "OptimizeEQ",
10004 "VerifyCap"
10005 };
10006
10007 if (completed < ARRAY_SIZE(state_completed))
10008 return state_completed[completed];
10009
10010 return "unknown";
10011}
10012
10013static const char all_lanes_dead_timeout_expired[] =
10014 "All lanes were inactive – was the interconnect media removed?";
10015static const char tx_out_of_policy[] =
10016 "Passing lanes on local port do not meet the local link width policy";
10017static const char no_state_complete[] =
10018 "State timeout occurred before link partner completed the state";
10019static const char * const state_complete_reasons[] = {
10020 [0x00] = "Reason unknown",
10021 [0x01] = "Link was halted by driver, refer to LinkDownReason",
10022 [0x02] = "Link partner reported failure",
10023 [0x10] = "Unable to achieve frame sync on any lane",
10024 [0x11] =
10025 "Unable to find a common bit rate with the link partner",
10026 [0x12] =
10027 "Unable to achieve frame sync on sufficient lanes to meet the local link width policy",
10028 [0x13] =
10029 "Unable to identify preset equalization on sufficient lanes to meet the local link width policy",
10030 [0x14] = no_state_complete,
10031 [0x15] =
10032 "State timeout occurred before link partner identified equalization presets",
10033 [0x16] =
10034 "Link partner completed the EstablishComm state, but the passing lanes do not meet the local link width policy",
10035 [0x17] = tx_out_of_policy,
10036 [0x20] = all_lanes_dead_timeout_expired,
10037 [0x21] =
10038 "Unable to achieve acceptable BER on sufficient lanes to meet the local link width policy",
10039 [0x22] = no_state_complete,
10040 [0x23] =
10041 "Link partner completed the OptimizeEq state, but the passing lanes do not meet the local link width policy",
10042 [0x24] = tx_out_of_policy,
10043 [0x30] = all_lanes_dead_timeout_expired,
10044 [0x31] =
10045 "State timeout occurred waiting for host to process received frames",
10046 [0x32] = no_state_complete,
10047 [0x33] =
10048 "Link partner completed the VerifyCap state, but the passing lanes do not meet the local link width policy",
10049 [0x34] = tx_out_of_policy,
10050};
10051
10052static const char *state_complete_reason_code_string(struct hfi1_pportdata *ppd,
10053 u32 code)
10054{
10055 const char *str = NULL;
10056
10057 if (code < ARRAY_SIZE(state_complete_reasons))
10058 str = state_complete_reasons[code];
10059
10060 if (str)
10061 return str;
10062 return "Reserved";
10063}
10064
10065/* describe the given last state complete frame */
10066static void decode_state_complete(struct hfi1_pportdata *ppd, u32 frame,
10067 const char *prefix)
10068{
10069 struct hfi1_devdata *dd = ppd->dd;
10070 u32 success;
10071 u32 state;
10072 u32 reason;
10073 u32 lanes;
10074
10075 /*
10076 * Decode frame:
10077 * [ 0: 0] - success
10078 * [ 3: 1] - state
10079 * [ 7: 4] - next state timeout
10080 * [15: 8] - reason code
10081 * [31:16] - lanes
10082 */
10083 success = frame & 0x1;
10084 state = (frame >> 1) & 0x7;
10085 reason = (frame >> 8) & 0xff;
10086 lanes = (frame >> 16) & 0xffff;
10087
10088 dd_dev_err(dd, "Last %s LNI state complete frame 0x%08x:\n",
10089 prefix, frame);
10090 dd_dev_err(dd, " last reported state state: %s (0x%x)\n",
10091 state_completed_string(state), state);
10092 dd_dev_err(dd, " state successfully completed: %s\n",
10093 success ? "yes" : "no");
10094 dd_dev_err(dd, " fail reason 0x%x: %s\n",
10095 reason, state_complete_reason_code_string(ppd, reason));
10096 dd_dev_err(dd, " passing lane mask: 0x%x", lanes);
10097}
10098
10099/*
10100 * Read the last state complete frames and explain them. This routine
10101 * expects to be called if the link went down during link negotiation
10102 * and initialization (LNI). That is, anywhere between polling and link up.
10103 */
10104static void check_lni_states(struct hfi1_pportdata *ppd)
10105{
10106 u32 last_local_state;
10107 u32 last_remote_state;
10108
10109 read_last_local_state(ppd->dd, &last_local_state);
10110 read_last_remote_state(ppd->dd, &last_remote_state);
10111
10112 /*
10113 * Don't report anything if there is nothing to report. A value of
10114 * 0 means the link was taken down while polling and there was no
10115 * training in-process.
10116 */
10117 if (last_local_state == 0 && last_remote_state == 0)
10118 return;
10119
10120 decode_state_complete(ppd, last_local_state, "transmitted");
10121 decode_state_complete(ppd, last_remote_state, "received");
10122}
10123
ec8a1423
DL		 10124/* wait for wait_ms for LINK_TRANSFER_ACTIVE to go to 1 */
10125static int wait_link_transfer_active(struct hfi1_devdata *dd, int wait_ms)
10126{
10127 u64 reg;
10128 unsigned long timeout;
10129
10130 /* watch LCB_STS_LINK_TRANSFER_ACTIVE */
10131 timeout = jiffies + msecs_to_jiffies(wait_ms);
10132 while (1) {
10133 reg = read_csr(dd, DC_LCB_STS_LINK_TRANSFER_ACTIVE);
10134 if (reg)
10135 break;
10136 if (time_after(jiffies, timeout)) {
10137 dd_dev_err(dd,
10138 "timeout waiting for LINK_TRANSFER_ACTIVE\n");
10139 return -ETIMEDOUT;
10140 }
10141 udelay(2);
10142 }
10143 return 0;
10144}
10145
10146/* called when the logical link state is not down as it should be */
10147static void force_logical_link_state_down(struct hfi1_pportdata *ppd)
10148{
10149 struct hfi1_devdata *dd = ppd->dd;
10150
10151 /*
10152 * Bring link up in LCB loopback
10153 */
10154 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1);
10155 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK,
10156 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK);
10157
10158 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0);
10159 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0);
10160 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110);
10161 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x2);
10162
10163 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
10164 (void)read_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET);
10165 udelay(3);
10166 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 1);
10167 write_csr(dd, DC_LCB_CFG_RUN, 1ull << DC_LCB_CFG_RUN_EN_SHIFT);
10168
10169 wait_link_transfer_active(dd, 100);
10170
10171 /*
10172 * Bring the link down again.
10173 */
10174 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1);
10175 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 0);
10176 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 0);
10177
10178 /* call again to adjust ppd->statusp, if needed */
10179 get_logical_state(ppd);
10180}
10181
77241056
MM		 10182/*
10183 * Helper for set_link_state(). Do not call except from that routine.
10184 * Expects ppd->hls_mutex to be held.
10185 *
10186 * @rem_reason value to be sent to the neighbor
10187 *
10188 * LinkDownReasons only set if transition succeeds.
10189 */
10190static int goto_offline(struct hfi1_pportdata *ppd, u8 rem_reason)
10191{
10192 struct hfi1_devdata *dd = ppd->dd;
10193 u32 pstate, previous_state;
77241056
MM		 10194 int ret;
10195 int do_transition;
10196 int do_wait;
10197
8688426b
MR		 10198 update_lcb_cache(dd);
10199
77241056
MM		 10200 previous_state = ppd->host_link_state;
10201 ppd->host_link_state = HLS_GOING_OFFLINE;
10202 pstate = read_physical_state(dd);
10203 if (pstate == PLS_OFFLINE) {
10204 do_transition = 0; /* in right state */
10205 do_wait = 0; /* ...no need to wait */
10206 } else if ((pstate & 0xff) == PLS_OFFLINE) {
10207 do_transition = 0; /* in an offline transient state */
10208 do_wait = 1; /* ...wait for it to settle */
10209 } else {
10210 do_transition = 1; /* need to move to offline */
10211 do_wait = 1; /* ...will need to wait */
10212 }
10213
10214 if (do_transition) {
10215 ret = set_physical_link_state(dd,
bf640096 10216 (rem_reason << 8) | PLS_OFFLINE);
77241056
MM		 10217
10218 if (ret != HCMD_SUCCESS) {
10219 dd_dev_err(dd,
17fb4f29
JJ		 10220 "Failed to transition to Offline link state, return %d\n",
10221 ret);
77241056
MM		 10222 return -EINVAL;
10223 }
a9c05e35
BM		 10224 if (ppd->offline_disabled_reason ==
10225 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE))
77241056 10226 ppd->offline_disabled_reason =
a9c05e35 10227 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT);
77241056
MM		 10228 }
10229
10230 if (do_wait) {
10231 /* it can take a while for the link to go down */
dc060245 10232 ret = wait_phy_linkstate(dd, PLS_OFFLINE, 10000);
77241056
MM		 10233 if (ret < 0)
10234 return ret;
10235 }
10236
77241056
MM		 10237 /*
10238 * Now in charge of LCB - must be after the physical state is
10239 * offline.quiet and before host_link_state is changed.
10240 */
10241 set_host_lcb_access(dd);
10242 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
ec8a1423
DL		 10243
10244 /* make sure the logical state is also down */
10245 ret = wait_logical_linkstate(ppd, IB_PORT_DOWN, 1000);
10246 if (ret)
10247 force_logical_link_state_down(ppd);
10248
77241056
MM		 10249 ppd->host_link_state = HLS_LINK_COOLDOWN; /* LCB access allowed */
10250
8ebd4cf1
EH		 10251 if (ppd->port_type == PORT_TYPE_QSFP &&
10252 ppd->qsfp_info.limiting_active &&
10253 qsfp_mod_present(ppd)) {
765a6fac
DL		 10254 int ret;
10255
10256 ret = acquire_chip_resource(dd, qsfp_resource(dd), QSFP_WAIT);
10257 if (ret == 0) {
10258 set_qsfp_tx(ppd, 0);
10259 release_chip_resource(dd, qsfp_resource(dd));
10260 } else {
10261 /* not fatal, but should warn */
10262 dd_dev_err(dd,
10263 "Unable to acquire lock to turn off QSFP TX\n");
10264 }
8ebd4cf1
EH		 10265 }
10266
77241056
MM		 10267 /*
10268 * The LNI has a mandatory wait time after the physical state
10269 * moves to Offline.Quiet. The wait time may be different
10270 * depending on how the link went down. The 8051 firmware
10271 * will observe the needed wait time and only move to ready
10272 * when that is completed. The largest of the quiet timeouts
05087f3b
DL		 10273 * is 6s, so wait that long and then at least 0.5s more for
10274 * other transitions, and another 0.5s for a buffer.
77241056 10275 */
05087f3b 10276 ret = wait_fm_ready(dd, 7000);
77241056
MM		 10277 if (ret) {
10278 dd_dev_err(dd,
17fb4f29 10279 "After going offline, timed out waiting for the 8051 to become ready to accept host requests\n");
77241056
MM		 10280 /* state is really offline, so make it so */
10281 ppd->host_link_state = HLS_DN_OFFLINE;
10282 return ret;
10283 }
10284
10285 /*
10286 * The state is now offline and the 8051 is ready to accept host
10287 * requests.
10288 * - change our state
10289 * - notify others if we were previously in a linkup state
10290 */
10291 ppd->host_link_state = HLS_DN_OFFLINE;
10292 if (previous_state & HLS_UP) {
10293 /* went down while link was up */
10294 handle_linkup_change(dd, 0);
10295 } else if (previous_state
10296 & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) {
10297 /* went down while attempting link up */
6854c692 10298 check_lni_states(ppd);
77241056
MM		 10299 }
10300
10301 /* the active link width (downgrade) is 0 on link down */
10302 ppd->link_width_active = 0;
10303 ppd->link_width_downgrade_tx_active = 0;
10304 ppd->link_width_downgrade_rx_active = 0;
10305 ppd->current_egress_rate = 0;
10306 return 0;
10307}
10308
10309/* return the link state name */
10310static const char *link_state_name(u32 state)
10311{
10312 const char *name;
10313 int n = ilog2(state);
10314 static const char * const names[] = {
10315 [__HLS_UP_INIT_BP] = "INIT",
10316 [__HLS_UP_ARMED_BP] = "ARMED",
10317 [__HLS_UP_ACTIVE_BP] = "ACTIVE",
10318 [__HLS_DN_DOWNDEF_BP] = "DOWNDEF",
10319 [__HLS_DN_POLL_BP] = "POLL",
10320 [__HLS_DN_DISABLE_BP] = "DISABLE",
10321 [__HLS_DN_OFFLINE_BP] = "OFFLINE",
10322 [__HLS_VERIFY_CAP_BP] = "VERIFY_CAP",
10323 [__HLS_GOING_UP_BP] = "GOING_UP",
10324 [__HLS_GOING_OFFLINE_BP] = "GOING_OFFLINE",
10325 [__HLS_LINK_COOLDOWN_BP] = "LINK_COOLDOWN"
10326 };
10327
10328 name = n < ARRAY_SIZE(names) ? names[n] : NULL;
10329 return name ? name : "unknown";
10330}
10331
10332/* return the link state reason name */
10333static const char *link_state_reason_name(struct hfi1_pportdata *ppd, u32 state)
10334{
10335 if (state == HLS_UP_INIT) {
10336 switch (ppd->linkinit_reason) {
10337 case OPA_LINKINIT_REASON_LINKUP:
10338 return "(LINKUP)";
10339 case OPA_LINKINIT_REASON_FLAPPING:
10340 return "(FLAPPING)";
10341 case OPA_LINKINIT_OUTSIDE_POLICY:
10342 return "(OUTSIDE_POLICY)";
10343 case OPA_LINKINIT_QUARANTINED:
10344 return "(QUARANTINED)";
10345 case OPA_LINKINIT_INSUFIC_CAPABILITY:
10346 return "(INSUFIC_CAPABILITY)";
10347 default:
10348 break;
10349 }
10350 }
10351 return "";
10352}
10353
10354/*
10355 * driver_physical_state - convert the driver's notion of a port's
10356 * state (an HLS_*) into a physical state (a {IB,OPA}_PORTPHYSSTATE_*).
10357 * Return -1 (converted to a u32) to indicate error.
10358 */
10359u32 driver_physical_state(struct hfi1_pportdata *ppd)
10360{
10361 switch (ppd->host_link_state) {
10362 case HLS_UP_INIT:
10363 case HLS_UP_ARMED:
10364 case HLS_UP_ACTIVE:
10365 return IB_PORTPHYSSTATE_LINKUP;
10366 case HLS_DN_POLL:
10367 return IB_PORTPHYSSTATE_POLLING;
10368 case HLS_DN_DISABLE:
10369 return IB_PORTPHYSSTATE_DISABLED;
10370 case HLS_DN_OFFLINE:
10371 return OPA_PORTPHYSSTATE_OFFLINE;
10372 case HLS_VERIFY_CAP:
10373 return IB_PORTPHYSSTATE_POLLING;
10374 case HLS_GOING_UP:
10375 return IB_PORTPHYSSTATE_POLLING;
10376 case HLS_GOING_OFFLINE:
10377 return OPA_PORTPHYSSTATE_OFFLINE;
10378 case HLS_LINK_COOLDOWN:
10379 return OPA_PORTPHYSSTATE_OFFLINE;
10380 case HLS_DN_DOWNDEF:
10381 default:
10382 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n",
10383 ppd->host_link_state);
10384 return -1;
10385 }
10386}
10387
10388/*
10389 * driver_logical_state - convert the driver's notion of a port's
10390 * state (an HLS_*) into a logical state (a IB_PORT_*). Return -1
10391 * (converted to a u32) to indicate error.
10392 */
10393u32 driver_logical_state(struct hfi1_pportdata *ppd)
10394{
0c7f77af 10395 if (ppd->host_link_state && (ppd->host_link_state & HLS_DOWN))
77241056
MM		 10396 return IB_PORT_DOWN;
10397
10398 switch (ppd->host_link_state & HLS_UP) {
10399 case HLS_UP_INIT:
10400 return IB_PORT_INIT;
10401 case HLS_UP_ARMED:
10402 return IB_PORT_ARMED;
10403 case HLS_UP_ACTIVE:
10404 return IB_PORT_ACTIVE;
10405 default:
10406 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n",
10407 ppd->host_link_state);
10408 return -1;
10409 }
10410}
10411
10412void set_link_down_reason(struct hfi1_pportdata *ppd, u8 lcl_reason,
10413 u8 neigh_reason, u8 rem_reason)
10414{
10415 if (ppd->local_link_down_reason.latest == 0 &&
10416 ppd->neigh_link_down_reason.latest == 0) {
10417 ppd->local_link_down_reason.latest = lcl_reason;
10418 ppd->neigh_link_down_reason.latest = neigh_reason;
10419 ppd->remote_link_down_reason = rem_reason;
10420 }
10421}
10422
10423/*
10424 * Change the physical and/or logical link state.
10425 *
10426 * Do not call this routine while inside an interrupt. It contains
10427 * calls to routines that can take multiple seconds to finish.
10428 *
10429 * Returns 0 on success, -errno on failure.
10430 */
10431int set_link_state(struct hfi1_pportdata *ppd, u32 state)
10432{
10433 struct hfi1_devdata *dd = ppd->dd;
10434 struct ib_event event = {.device = NULL};
10435 int ret1, ret = 0;
77241056
MM		 10436 int orig_new_state, poll_bounce;
10437
10438 mutex_lock(&ppd->hls_lock);
10439
10440 orig_new_state = state;
10441 if (state == HLS_DN_DOWNDEF)
10442 state = dd->link_default;
10443
10444 /* interpret poll -> poll as a link bounce */
d0d236ea
JJ		 10445 poll_bounce = ppd->host_link_state == HLS_DN_POLL &&
10446 state == HLS_DN_POLL;
77241056
MM		 10447
10448 dd_dev_info(dd, "%s: current %s, new %s %s%s\n", __func__,
17fb4f29
JJ		 10449 link_state_name(ppd->host_link_state),
10450 link_state_name(orig_new_state),
10451 poll_bounce ? "(bounce) " : "",
10452 link_state_reason_name(ppd, state));
77241056 10453
77241056
MM		 10454 /*
10455 * If we're going to a (HLS_*) link state that implies the logical
10456 * link state is neither of (IB_PORT_ARMED, IB_PORT_ACTIVE), then
10457 * reset is_sm_config_started to 0.
10458 */
10459 if (!(state & (HLS_UP_ARMED | HLS_UP_ACTIVE)))
10460 ppd->is_sm_config_started = 0;
10461
10462 /*
10463 * Do nothing if the states match. Let a poll to poll link bounce
10464 * go through.
10465 */
10466 if (ppd->host_link_state == state && !poll_bounce)
10467 goto done;
10468
10469 switch (state) {
10470 case HLS_UP_INIT:
d0d236ea
JJ		 10471 if (ppd->host_link_state == HLS_DN_POLL &&
10472 (quick_linkup || dd->icode == ICODE_FUNCTIONAL_SIMULATOR)) {
77241056
MM		 10473 /*
10474 * Quick link up jumps from polling to here.
10475 *
10476 * Whether in normal or loopback mode, the
10477 * simulator jumps from polling to link up.
10478 * Accept that here.
10479 */
17fb4f29 10480 /* OK */
77241056
MM		 10481 } else if (ppd->host_link_state != HLS_GOING_UP) {
10482 goto unexpected;
10483 }
10484
10485 ppd->host_link_state = HLS_UP_INIT;
10486 ret = wait_logical_linkstate(ppd, IB_PORT_INIT, 1000);
10487 if (ret) {
10488 /* logical state didn't change, stay at going_up */
10489 ppd->host_link_state = HLS_GOING_UP;
10490 dd_dev_err(dd,
17fb4f29
JJ		 10491 "%s: logical state did not change to INIT\n",
10492 __func__);
77241056
MM		 10493 } else {
10494 /* clear old transient LINKINIT_REASON code */
10495 if (ppd->linkinit_reason >= OPA_LINKINIT_REASON_CLEAR)
10496 ppd->linkinit_reason =
10497 OPA_LINKINIT_REASON_LINKUP;
10498
10499 /* enable the port */
10500 add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
10501
10502 handle_linkup_change(dd, 1);
10503 }
10504 break;
10505 case HLS_UP_ARMED:
10506 if (ppd->host_link_state != HLS_UP_INIT)
10507 goto unexpected;
10508
10509 ppd->host_link_state = HLS_UP_ARMED;
10510 set_logical_state(dd, LSTATE_ARMED);
10511 ret = wait_logical_linkstate(ppd, IB_PORT_ARMED, 1000);
10512 if (ret) {
10513 /* logical state didn't change, stay at init */
10514 ppd->host_link_state = HLS_UP_INIT;
10515 dd_dev_err(dd,
17fb4f29
JJ		 10516 "%s: logical state did not change to ARMED\n",
10517 __func__);
77241056
MM		 10518 }
10519 /*
10520 * The simulator does not currently implement SMA messages,
10521 * so neighbor_normal is not set. Set it here when we first
10522 * move to Armed.
10523 */
10524 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
10525 ppd->neighbor_normal = 1;
10526 break;
10527 case HLS_UP_ACTIVE:
10528 if (ppd->host_link_state != HLS_UP_ARMED)
10529 goto unexpected;
10530
10531 ppd->host_link_state = HLS_UP_ACTIVE;
10532 set_logical_state(dd, LSTATE_ACTIVE);
10533 ret = wait_logical_linkstate(ppd, IB_PORT_ACTIVE, 1000);
10534 if (ret) {
10535 /* logical state didn't change, stay at armed */
10536 ppd->host_link_state = HLS_UP_ARMED;
10537 dd_dev_err(dd,
17fb4f29
JJ		 10538 "%s: logical state did not change to ACTIVE\n",
10539 __func__);
77241056 10540 } else {
77241056
MM		 10541 /* tell all engines to go running */
10542 sdma_all_running(dd);
10543
10544 /* Signal the IB layer that the port has went active */
ec3f2c12 10545 event.device = &dd->verbs_dev.rdi.ibdev;
77241056
MM		 10546 event.element.port_num = ppd->port;
10547 event.event = IB_EVENT_PORT_ACTIVE;
10548 }
10549 break;
10550 case HLS_DN_POLL:
10551 if ((ppd->host_link_state == HLS_DN_DISABLE ||
10552 ppd->host_link_state == HLS_DN_OFFLINE) &&
10553 dd->dc_shutdown)
10554 dc_start(dd);
10555 /* Hand LED control to the DC */
10556 write_csr(dd, DCC_CFG_LED_CNTRL, 0);
10557
10558 if (ppd->host_link_state != HLS_DN_OFFLINE) {
10559 u8 tmp = ppd->link_enabled;
10560
10561 ret = goto_offline(ppd, ppd->remote_link_down_reason);
10562 if (ret) {
10563 ppd->link_enabled = tmp;
10564 break;
10565 }
10566 ppd->remote_link_down_reason = 0;
10567
10568 if (ppd->driver_link_ready)
10569 ppd->link_enabled = 1;
10570 }
10571
fb9036dd 10572 set_all_slowpath(ppd->dd);
77241056
MM		 10573 ret = set_local_link_attributes(ppd);
10574 if (ret)
10575 break;
10576
10577 ppd->port_error_action = 0;
10578 ppd->host_link_state = HLS_DN_POLL;
10579
10580 if (quick_linkup) {
10581 /* quick linkup does not go into polling */
10582 ret = do_quick_linkup(dd);
10583 } else {
10584 ret1 = set_physical_link_state(dd, PLS_POLLING);
10585 if (ret1 != HCMD_SUCCESS) {
10586 dd_dev_err(dd,
17fb4f29
JJ		 10587 "Failed to transition to Polling link state, return 0x%x\n",
10588 ret1);
77241056
MM		 10589 ret = -EINVAL;
10590 }
10591 }
a9c05e35
BM		 10592 ppd->offline_disabled_reason =
10593 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE);
77241056
MM		 10594 /*
10595 * If an error occurred above, go back to offline. The
10596 * caller may reschedule another attempt.
10597 */
10598 if (ret)
10599 goto_offline(ppd, 0);
10600 break;
10601 case HLS_DN_DISABLE:
10602 /* link is disabled */
10603 ppd->link_enabled = 0;
10604
10605 /* allow any state to transition to disabled */
10606
10607 /* must transition to offline first */
10608 if (ppd->host_link_state != HLS_DN_OFFLINE) {
10609 ret = goto_offline(ppd, ppd->remote_link_down_reason);
10610 if (ret)
10611 break;
10612 ppd->remote_link_down_reason = 0;
10613 }
10614
db069ecb
MR		 10615 if (!dd->dc_shutdown) {
10616 ret1 = set_physical_link_state(dd, PLS_DISABLED);
10617 if (ret1 != HCMD_SUCCESS) {
10618 dd_dev_err(dd,
10619 "Failed to transition to Disabled link state, return 0x%x\n",
10620 ret1);
10621 ret = -EINVAL;
10622 break;
10623 }
10624 dc_shutdown(dd);
77241056
MM		 10625 }
10626 ppd->host_link_state = HLS_DN_DISABLE;
77241056
MM		 10627 break;
10628 case HLS_DN_OFFLINE:
10629 if (ppd->host_link_state == HLS_DN_DISABLE)
10630 dc_start(dd);
10631
10632 /* allow any state to transition to offline */
10633 ret = goto_offline(ppd, ppd->remote_link_down_reason);
10634 if (!ret)
10635 ppd->remote_link_down_reason = 0;
10636 break;
10637 case HLS_VERIFY_CAP:
10638 if (ppd->host_link_state != HLS_DN_POLL)
10639 goto unexpected;
10640 ppd->host_link_state = HLS_VERIFY_CAP;
10641 break;
10642 case HLS_GOING_UP:
10643 if (ppd->host_link_state != HLS_VERIFY_CAP)
10644 goto unexpected;
10645
10646 ret1 = set_physical_link_state(dd, PLS_LINKUP);
10647 if (ret1 != HCMD_SUCCESS) {
10648 dd_dev_err(dd,
17fb4f29
JJ		 10649 "Failed to transition to link up state, return 0x%x\n",
10650 ret1);
77241056
MM		 10651 ret = -EINVAL;
10652 break;
10653 }
10654 ppd->host_link_state = HLS_GOING_UP;
10655 break;
10656
10657 case HLS_GOING_OFFLINE: /* transient within goto_offline() */
10658 case HLS_LINK_COOLDOWN: /* transient within goto_offline() */
10659 default:
10660 dd_dev_info(dd, "%s: state 0x%x: not supported\n",
17fb4f29 10661 __func__, state);
77241056
MM		 10662 ret = -EINVAL;
10663 break;
10664 }
10665
77241056
MM		 10666 goto done;
10667
10668unexpected:
10669 dd_dev_err(dd, "%s: unexpected state transition from %s to %s\n",
17fb4f29
JJ		 10670 __func__, link_state_name(ppd->host_link_state),
10671 link_state_name(state));
77241056
MM		 10672 ret = -EINVAL;
10673
10674done:
10675 mutex_unlock(&ppd->hls_lock);
10676
10677 if (event.device)
10678 ib_dispatch_event(&event);
10679
10680 return ret;
10681}
10682
10683int hfi1_set_ib_cfg(struct hfi1_pportdata *ppd, int which, u32 val)
10684{
10685 u64 reg;
10686 int ret = 0;
10687
10688 switch (which) {
10689 case HFI1_IB_CFG_LIDLMC:
10690 set_lidlmc(ppd);
10691 break;
10692 case HFI1_IB_CFG_VL_HIGH_LIMIT:
10693 /*
10694 * The VL Arbitrator high limit is sent in units of 4k
10695 * bytes, while HFI stores it in units of 64 bytes.
10696 */
8638b77f 10697 val *= 4096 / 64;
77241056
MM		 10698 reg = ((u64)val & SEND_HIGH_PRIORITY_LIMIT_LIMIT_MASK)
10699 << SEND_HIGH_PRIORITY_LIMIT_LIMIT_SHIFT;
10700 write_csr(ppd->dd, SEND_HIGH_PRIORITY_LIMIT, reg);
10701 break;
10702 case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
10703 /* HFI only supports POLL as the default link down state */
10704 if (val != HLS_DN_POLL)
10705 ret = -EINVAL;
10706 break;
10707 case HFI1_IB_CFG_OP_VLS:
10708 if (ppd->vls_operational != val) {
10709 ppd->vls_operational = val;
10710 if (!ppd->port)
10711 ret = -EINVAL;
77241056
MM		 10712 }
10713 break;
10714 /*
10715 * For link width, link width downgrade, and speed enable, always AND
10716 * the setting with what is actually supported. This has two benefits.
10717 * First, enabled can't have unsupported values, no matter what the
10718 * SM or FM might want. Second, the ALL_SUPPORTED wildcards that mean
10719 * "fill in with your supported value" have all the bits in the
10720 * field set, so simply ANDing with supported has the desired result.
10721 */
10722 case HFI1_IB_CFG_LWID_ENB: /* set allowed Link-width */
10723 ppd->link_width_enabled = val & ppd->link_width_supported;
10724 break;
10725 case HFI1_IB_CFG_LWID_DG_ENB: /* set allowed link width downgrade */
10726 ppd->link_width_downgrade_enabled =
10727 val & ppd->link_width_downgrade_supported;
10728 break;
10729 case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */
10730 ppd->link_speed_enabled = val & ppd->link_speed_supported;
10731 break;
10732 case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
10733 /*
10734 * HFI does not follow IB specs, save this value
10735 * so we can report it, if asked.
10736 */
10737 ppd->overrun_threshold = val;
10738 break;
10739 case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
10740 /*
10741 * HFI does not follow IB specs, save this value
10742 * so we can report it, if asked.
10743 */
10744 ppd->phy_error_threshold = val;
10745 break;
10746
10747 case HFI1_IB_CFG_MTU:
10748 set_send_length(ppd);
10749 break;
10750
10751 case HFI1_IB_CFG_PKEYS:
10752 if (HFI1_CAP_IS_KSET(PKEY_CHECK))
10753 set_partition_keys(ppd);
10754 break;
10755
10756 default:
10757 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
10758 dd_dev_info(ppd->dd,
17fb4f29
JJ		 10759 "%s: which %s, val 0x%x: not implemented\n",
10760 __func__, ib_cfg_name(which), val);
77241056
MM		 10761 break;
10762 }
10763 return ret;
10764}
10765
10766/* begin functions related to vl arbitration table caching */
10767static void init_vl_arb_caches(struct hfi1_pportdata *ppd)
10768{
10769 int i;
10770
10771 BUILD_BUG_ON(VL_ARB_TABLE_SIZE !=
10772 VL_ARB_LOW_PRIO_TABLE_SIZE);
10773 BUILD_BUG_ON(VL_ARB_TABLE_SIZE !=
10774 VL_ARB_HIGH_PRIO_TABLE_SIZE);
10775
10776 /*
10777 * Note that we always return values directly from the
10778 * 'vl_arb_cache' (and do no CSR reads) in response to a
10779 * 'Get(VLArbTable)'. This is obviously correct after a
10780 * 'Set(VLArbTable)', since the cache will then be up to
10781 * date. But it's also correct prior to any 'Set(VLArbTable)'
10782 * since then both the cache, and the relevant h/w registers
10783 * will be zeroed.
10784 */
10785
10786 for (i = 0; i < MAX_PRIO_TABLE; i++)
10787 spin_lock_init(&ppd->vl_arb_cache[i].lock);
10788}
10789
10790/*
10791 * vl_arb_lock_cache
10792 *
10793 * All other vl_arb_* functions should be called only after locking
10794 * the cache.
10795 */
10796static inline struct vl_arb_cache *
10797vl_arb_lock_cache(struct hfi1_pportdata *ppd, int idx)
10798{
10799 if (idx != LO_PRIO_TABLE && idx != HI_PRIO_TABLE)
10800 return NULL;
10801 spin_lock(&ppd->vl_arb_cache[idx].lock);
10802 return &ppd->vl_arb_cache[idx];
10803}
10804
10805static inline void vl_arb_unlock_cache(struct hfi1_pportdata *ppd, int idx)
10806{
10807 spin_unlock(&ppd->vl_arb_cache[idx].lock);
10808}
10809
10810static void vl_arb_get_cache(struct vl_arb_cache *cache,
10811 struct ib_vl_weight_elem *vl)
10812{
10813 memcpy(vl, cache->table, VL_ARB_TABLE_SIZE * sizeof(*vl));
10814}
10815
10816static void vl_arb_set_cache(struct vl_arb_cache *cache,
10817 struct ib_vl_weight_elem *vl)
10818{
10819 memcpy(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl));
10820}
10821
10822static int vl_arb_match_cache(struct vl_arb_cache *cache,
10823 struct ib_vl_weight_elem *vl)
10824{
10825 return !memcmp(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl));
10826}
f4d507cd 10827
77241056
MM		 10828/* end functions related to vl arbitration table caching */
10829
10830static int set_vl_weights(struct hfi1_pportdata *ppd, u32 target,
10831 u32 size, struct ib_vl_weight_elem *vl)
10832{
10833 struct hfi1_devdata *dd = ppd->dd;
10834 u64 reg;
10835 unsigned int i, is_up = 0;
10836 int drain, ret = 0;
10837
10838 mutex_lock(&ppd->hls_lock);
10839
10840 if (ppd->host_link_state & HLS_UP)
10841 is_up = 1;
10842
10843 drain = !is_ax(dd) && is_up;
10844
10845 if (drain)
10846 /*
10847 * Before adjusting VL arbitration weights, empty per-VL
10848 * FIFOs, otherwise a packet whose VL weight is being
10849 * set to 0 could get stuck in a FIFO with no chance to
10850 * egress.
10851 */
10852 ret = stop_drain_data_vls(dd);
10853
10854 if (ret) {
10855 dd_dev_err(
10856 dd,
10857 "%s: cannot stop/drain VLs - refusing to change VL arbitration weights\n",
10858 __func__);
10859 goto err;
10860 }
10861
10862 for (i = 0; i < size; i++, vl++) {
10863 /*
10864 * NOTE: The low priority shift and mask are used here, but
10865 * they are the same for both the low and high registers.
10866 */
10867 reg = (((u64)vl->vl & SEND_LOW_PRIORITY_LIST_VL_MASK)
10868 << SEND_LOW_PRIORITY_LIST_VL_SHIFT)
10869 | (((u64)vl->weight
10870 & SEND_LOW_PRIORITY_LIST_WEIGHT_MASK)
10871 << SEND_LOW_PRIORITY_LIST_WEIGHT_SHIFT);
10872 write_csr(dd, target + (i * 8), reg);
10873 }
10874 pio_send_control(dd, PSC_GLOBAL_VLARB_ENABLE);
10875
10876 if (drain)
10877 open_fill_data_vls(dd); /* reopen all VLs */
10878
10879err:
10880 mutex_unlock(&ppd->hls_lock);
10881
10882 return ret;
10883}
10884
10885/*
10886 * Read one credit merge VL register.
10887 */
10888static void read_one_cm_vl(struct hfi1_devdata *dd, u32 csr,
10889 struct vl_limit *vll)
10890{
10891 u64 reg = read_csr(dd, csr);
10892
10893 vll->dedicated = cpu_to_be16(
10894 (reg >> SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT)
10895 & SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_MASK);
10896 vll->shared = cpu_to_be16(
10897 (reg >> SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT)
10898 & SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_MASK);
10899}
10900
10901/*
10902 * Read the current credit merge limits.
10903 */
10904static int get_buffer_control(struct hfi1_devdata *dd,
10905 struct buffer_control *bc, u16 *overall_limit)
10906{
10907 u64 reg;
10908 int i;
10909
10910 /* not all entries are filled in */
10911 memset(bc, 0, sizeof(*bc));
10912
10913 /* OPA and HFI have a 1-1 mapping */
10914 for (i = 0; i < TXE_NUM_DATA_VL; i++)
8638b77f 10915 read_one_cm_vl(dd, SEND_CM_CREDIT_VL + (8 * i), &bc->vl[i]);
77241056
MM		 10916
10917 /* NOTE: assumes that VL* and VL15 CSRs are bit-wise identical */
10918 read_one_cm_vl(dd, SEND_CM_CREDIT_VL15, &bc->vl[15]);
10919
10920 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
10921 bc->overall_shared_limit = cpu_to_be16(
10922 (reg >> SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT)
10923 & SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_MASK);
10924 if (overall_limit)
10925 *overall_limit = (reg
10926 >> SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT)
10927 & SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_MASK;
10928 return sizeof(struct buffer_control);
10929}
10930
10931static int get_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp)
10932{
10933 u64 reg;
10934 int i;
10935
10936 /* each register contains 16 SC->VLnt mappings, 4 bits each */
10937 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_15_0);
10938 for (i = 0; i < sizeof(u64); i++) {
10939 u8 byte = *(((u8 *)&reg) + i);
10940
10941 dp->vlnt[2 * i] = byte & 0xf;
10942 dp->vlnt[(2 * i) + 1] = (byte & 0xf0) >> 4;
10943 }
10944
10945 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_31_16);
10946 for (i = 0; i < sizeof(u64); i++) {
10947 u8 byte = *(((u8 *)&reg) + i);
10948
10949 dp->vlnt[16 + (2 * i)] = byte & 0xf;
10950 dp->vlnt[16 + (2 * i) + 1] = (byte & 0xf0) >> 4;
10951 }
10952 return sizeof(struct sc2vlnt);
10953}
10954
10955static void get_vlarb_preempt(struct hfi1_devdata *dd, u32 nelems,
10956 struct ib_vl_weight_elem *vl)
10957{
10958 unsigned int i;
10959
10960 for (i = 0; i < nelems; i++, vl++) {
10961 vl->vl = 0xf;
10962 vl->weight = 0;
10963 }
10964}
10965
10966static void set_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp)
10967{
10968 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0,
17fb4f29
JJ		 10969 DC_SC_VL_VAL(15_0,
10970 0, dp->vlnt[0] & 0xf,
10971 1, dp->vlnt[1] & 0xf,
10972 2, dp->vlnt[2] & 0xf,
10973 3, dp->vlnt[3] & 0xf,
10974 4, dp->vlnt[4] & 0xf,
10975 5, dp->vlnt[5] & 0xf,
10976 6, dp->vlnt[6] & 0xf,
10977 7, dp->vlnt[7] & 0xf,
10978 8, dp->vlnt[8] & 0xf,
10979 9, dp->vlnt[9] & 0xf,
10980 10, dp->vlnt[10] & 0xf,
10981 11, dp->vlnt[11] & 0xf,
10982 12, dp->vlnt[12] & 0xf,
10983 13, dp->vlnt[13] & 0xf,
10984 14, dp->vlnt[14] & 0xf,
10985 15, dp->vlnt[15] & 0xf));
77241056 10986 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16,
17fb4f29
JJ		 10987 DC_SC_VL_VAL(31_16,
10988 16, dp->vlnt[16] & 0xf,
10989 17, dp->vlnt[17] & 0xf,
10990 18, dp->vlnt[18] & 0xf,
10991 19, dp->vlnt[19] & 0xf,
10992 20, dp->vlnt[20] & 0xf,
10993 21, dp->vlnt[21] & 0xf,
10994 22, dp->vlnt[22] & 0xf,
10995 23, dp->vlnt[23] & 0xf,
10996 24, dp->vlnt[24] & 0xf,
10997 25, dp->vlnt[25] & 0xf,
10998 26, dp->vlnt[26] & 0xf,
10999 27, dp->vlnt[27] & 0xf,
11000 28, dp->vlnt[28] & 0xf,
11001 29, dp->vlnt[29] & 0xf,
11002 30, dp->vlnt[30] & 0xf,
11003 31, dp->vlnt[31] & 0xf));
77241056
MM		 11004}
11005
11006static void nonzero_msg(struct hfi1_devdata *dd, int idx, const char *what,
11007 u16 limit)
11008{
11009 if (limit != 0)
11010 dd_dev_info(dd, "Invalid %s limit %d on VL %d, ignoring\n",
17fb4f29 11011 what, (int)limit, idx);
77241056
MM		 11012}
11013
11014/* change only the shared limit portion of SendCmGLobalCredit */
11015static void set_global_shared(struct hfi1_devdata *dd, u16 limit)
11016{
11017 u64 reg;
11018
11019 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
11020 reg &= ~SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK;
11021 reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT;
11022 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
11023}
11024
11025/* change only the total credit limit portion of SendCmGLobalCredit */
11026static void set_global_limit(struct hfi1_devdata *dd, u16 limit)
11027{
11028 u64 reg;
11029
11030 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
11031 reg &= ~SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK;
11032 reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT;
11033 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
11034}
11035
11036/* set the given per-VL shared limit */
11037static void set_vl_shared(struct hfi1_devdata *dd, int vl, u16 limit)
11038{
11039 u64 reg;
11040 u32 addr;
11041
11042 if (vl < TXE_NUM_DATA_VL)
11043 addr = SEND_CM_CREDIT_VL + (8 * vl);
11044 else
11045 addr = SEND_CM_CREDIT_VL15;
11046
11047 reg = read_csr(dd, addr);
11048 reg &= ~SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SMASK;
11049 reg |= (u64)limit << SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT;
11050 write_csr(dd, addr, reg);
11051}
11052
11053/* set the given per-VL dedicated limit */
11054static void set_vl_dedicated(struct hfi1_devdata *dd, int vl, u16 limit)
11055{
11056 u64 reg;
11057 u32 addr;
11058
11059 if (vl < TXE_NUM_DATA_VL)
11060 addr = SEND_CM_CREDIT_VL + (8 * vl);
11061 else
11062 addr = SEND_CM_CREDIT_VL15;
11063
11064 reg = read_csr(dd, addr);
11065 reg &= ~SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SMASK;
11066 reg |= (u64)limit << SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT;
11067 write_csr(dd, addr, reg);
11068}
11069
11070/* spin until the given per-VL status mask bits clear */
11071static void wait_for_vl_status_clear(struct hfi1_devdata *dd, u64 mask,
11072 const char *which)
11073{
11074 unsigned long timeout;
11075 u64 reg;
11076
11077 timeout = jiffies + msecs_to_jiffies(VL_STATUS_CLEAR_TIMEOUT);
11078 while (1) {
11079 reg = read_csr(dd, SEND_CM_CREDIT_USED_STATUS) & mask;
11080
11081 if (reg == 0)
11082 return; /* success */
11083 if (time_after(jiffies, timeout))
11084 break; /* timed out */
11085 udelay(1);
11086 }
11087
11088 dd_dev_err(dd,
17fb4f29
JJ		 11089 "%s credit change status not clearing after %dms, mask 0x%llx, not clear 0x%llx\n",
11090 which, VL_STATUS_CLEAR_TIMEOUT, mask, reg);
77241056
MM		 11091 /*
11092 * If this occurs, it is likely there was a credit loss on the link.
11093 * The only recovery from that is a link bounce.
11094 */
11095 dd_dev_err(dd,
17fb4f29 11096 "Continuing anyway. A credit loss may occur. Suggest a link bounce\n");
77241056
MM		 11097}
11098
11099/*
11100 * The number of credits on the VLs may be changed while everything
11101 * is "live", but the following algorithm must be followed due to
11102 * how the hardware is actually implemented. In particular,
11103 * Return_Credit_Status[] is the only correct status check.
11104 *
11105 * if (reducing Global_Shared_Credit_Limit or any shared limit changing)
11106 * set Global_Shared_Credit_Limit = 0
11107 * use_all_vl = 1
11108 * mask0 = all VLs that are changing either dedicated or shared limits
11109 * set Shared_Limit[mask0] = 0
11110 * spin until Return_Credit_Status[use_all_vl ? all VL : mask0] == 0
11111 * if (changing any dedicated limit)
11112 * mask1 = all VLs that are lowering dedicated limits
11113 * lower Dedicated_Limit[mask1]
11114 * spin until Return_Credit_Status[mask1] == 0
11115 * raise Dedicated_Limits
11116 * raise Shared_Limits
11117 * raise Global_Shared_Credit_Limit
11118 *
11119 * lower = if the new limit is lower, set the limit to the new value
11120 * raise = if the new limit is higher than the current value (may be changed
11121 * earlier in the algorithm), set the new limit to the new value
11122 */
8a4d3444
MM		 11123int set_buffer_control(struct hfi1_pportdata *ppd,
11124 struct buffer_control *new_bc)
77241056 11125{
8a4d3444 11126 struct hfi1_devdata *dd = ppd->dd;
77241056
MM		 11127 u64 changing_mask, ld_mask, stat_mask;
11128 int change_count;
11129 int i, use_all_mask;
11130 int this_shared_changing;
8a4d3444 11131 int vl_count = 0, ret;
77241056
MM		 11132 /*
11133 * A0: add the variable any_shared_limit_changing below and in the
11134 * algorithm above. If removing A0 support, it can be removed.
11135 */
11136 int any_shared_limit_changing;
11137 struct buffer_control cur_bc;
11138 u8 changing[OPA_MAX_VLS];
11139 u8 lowering_dedicated[OPA_MAX_VLS];
11140 u16 cur_total;
11141 u32 new_total = 0;
11142 const u64 all_mask =
11143 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK
11144 | SEND_CM_CREDIT_USED_STATUS_VL1_RETURN_CREDIT_STATUS_SMASK
11145 | SEND_CM_CREDIT_USED_STATUS_VL2_RETURN_CREDIT_STATUS_SMASK
11146 | SEND_CM_CREDIT_USED_STATUS_VL3_RETURN_CREDIT_STATUS_SMASK
11147 | SEND_CM_CREDIT_USED_STATUS_VL4_RETURN_CREDIT_STATUS_SMASK
11148 | SEND_CM_CREDIT_USED_STATUS_VL5_RETURN_CREDIT_STATUS_SMASK
11149 | SEND_CM_CREDIT_USED_STATUS_VL6_RETURN_CREDIT_STATUS_SMASK
11150 | SEND_CM_CREDIT_USED_STATUS_VL7_RETURN_CREDIT_STATUS_SMASK
11151 | SEND_CM_CREDIT_USED_STATUS_VL15_RETURN_CREDIT_STATUS_SMASK;
11152
11153#define valid_vl(idx) ((idx) < TXE_NUM_DATA_VL || (idx) == 15)
11154#define NUM_USABLE_VLS 16 /* look at VL15 and less */
11155
77241056
MM		 11156 /* find the new total credits, do sanity check on unused VLs */
11157 for (i = 0; i < OPA_MAX_VLS; i++) {
11158 if (valid_vl(i)) {
11159 new_total += be16_to_cpu(new_bc->vl[i].dedicated);
11160 continue;
11161 }
11162 nonzero_msg(dd, i, "dedicated",
17fb4f29 11163 be16_to_cpu(new_bc->vl[i].dedicated));
77241056 11164 nonzero_msg(dd, i, "shared",
17fb4f29 11165 be16_to_cpu(new_bc->vl[i].shared));
77241056
MM		 11166 new_bc->vl[i].dedicated = 0;
11167 new_bc->vl[i].shared = 0;
11168 }
11169 new_total += be16_to_cpu(new_bc->overall_shared_limit);
bff14bb6 11170
77241056
MM		 11171 /* fetch the current values */
11172 get_buffer_control(dd, &cur_bc, &cur_total);
11173
11174 /*
11175 * Create the masks we will use.
11176 */
11177 memset(changing, 0, sizeof(changing));
11178 memset(lowering_dedicated, 0, sizeof(lowering_dedicated));
4d114fdd
JJ		 11179 /*
11180 * NOTE: Assumes that the individual VL bits are adjacent and in
11181 * increasing order
11182 */
77241056
MM		 11183 stat_mask =
11184 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK;
11185 changing_mask = 0;
11186 ld_mask = 0;
11187 change_count = 0;
11188 any_shared_limit_changing = 0;
11189 for (i = 0; i < NUM_USABLE_VLS; i++, stat_mask <<= 1) {
11190 if (!valid_vl(i))
11191 continue;
11192 this_shared_changing = new_bc->vl[i].shared
11193 != cur_bc.vl[i].shared;
11194 if (this_shared_changing)
11195 any_shared_limit_changing = 1;
d0d236ea
JJ		 11196 if (new_bc->vl[i].dedicated != cur_bc.vl[i].dedicated ||
11197 this_shared_changing) {
77241056
MM		 11198 changing[i] = 1;
11199 changing_mask |= stat_mask;
11200 change_count++;
11201 }
11202 if (be16_to_cpu(new_bc->vl[i].dedicated) <
11203 be16_to_cpu(cur_bc.vl[i].dedicated)) {
11204 lowering_dedicated[i] = 1;
11205 ld_mask |= stat_mask;
11206 }
11207 }
11208
11209 /* bracket the credit change with a total adjustment */
11210 if (new_total > cur_total)
11211 set_global_limit(dd, new_total);
11212
11213 /*
11214 * Start the credit change algorithm.
11215 */
11216 use_all_mask = 0;
11217 if ((be16_to_cpu(new_bc->overall_shared_limit) <
995deafa
MM		 11218 be16_to_cpu(cur_bc.overall_shared_limit)) ||
11219 (is_ax(dd) && any_shared_limit_changing)) {
77241056
MM		 11220 set_global_shared(dd, 0);
11221 cur_bc.overall_shared_limit = 0;
11222 use_all_mask = 1;
11223 }
11224
11225 for (i = 0; i < NUM_USABLE_VLS; i++) {
11226 if (!valid_vl(i))
11227 continue;
11228
11229 if (changing[i]) {
11230 set_vl_shared(dd, i, 0);
11231 cur_bc.vl[i].shared = 0;
11232 }
11233 }
11234
11235 wait_for_vl_status_clear(dd, use_all_mask ? all_mask : changing_mask,
17fb4f29 11236 "shared");
77241056
MM		 11237
11238 if (change_count > 0) {
11239 for (i = 0; i < NUM_USABLE_VLS; i++) {
11240 if (!valid_vl(i))
11241 continue;
11242
11243 if (lowering_dedicated[i]) {
11244 set_vl_dedicated(dd, i,
17fb4f29
JJ		 11245 be16_to_cpu(new_bc->
11246 vl[i].dedicated));
77241056
MM		 11247 cur_bc.vl[i].dedicated =
11248 new_bc->vl[i].dedicated;
11249 }
11250 }
11251
11252 wait_for_vl_status_clear(dd, ld_mask, "dedicated");
11253
11254 /* now raise all dedicated that are going up */
11255 for (i = 0; i < NUM_USABLE_VLS; i++) {
11256 if (!valid_vl(i))
11257 continue;
11258
11259 if (be16_to_cpu(new_bc->vl[i].dedicated) >
11260 be16_to_cpu(cur_bc.vl[i].dedicated))
11261 set_vl_dedicated(dd, i,
17fb4f29
JJ		 11262 be16_to_cpu(new_bc->
11263 vl[i].dedicated));
77241056
MM		 11264 }
11265 }
11266
11267 /* next raise all shared that are going up */
11268 for (i = 0; i < NUM_USABLE_VLS; i++) {
11269 if (!valid_vl(i))
11270 continue;
11271
11272 if (be16_to_cpu(new_bc->vl[i].shared) >
11273 be16_to_cpu(cur_bc.vl[i].shared))
11274 set_vl_shared(dd, i, be16_to_cpu(new_bc->vl[i].shared));
11275 }
11276
11277 /* finally raise the global shared */
11278 if (be16_to_cpu(new_bc->overall_shared_limit) >
17fb4f29 11279 be16_to_cpu(cur_bc.overall_shared_limit))
77241056 11280 set_global_shared(dd,
17fb4f29 11281 be16_to_cpu(new_bc->overall_shared_limit));
77241056
MM		 11282
11283 /* bracket the credit change with a total adjustment */
11284 if (new_total < cur_total)
11285 set_global_limit(dd, new_total);
8a4d3444
MM		 11286
11287 /*
11288 * Determine the actual number of operational VLS using the number of
11289 * dedicated and shared credits for each VL.
11290 */
11291 if (change_count > 0) {
11292 for (i = 0; i < TXE_NUM_DATA_VL; i++)
11293 if (be16_to_cpu(new_bc->vl[i].dedicated) > 0 ||
11294 be16_to_cpu(new_bc->vl[i].shared) > 0)
11295 vl_count++;
11296 ppd->actual_vls_operational = vl_count;
11297 ret = sdma_map_init(dd, ppd->port - 1, vl_count ?
11298 ppd->actual_vls_operational :
11299 ppd->vls_operational,
11300 NULL);
11301 if (ret == 0)
11302 ret = pio_map_init(dd, ppd->port - 1, vl_count ?
11303 ppd->actual_vls_operational :
11304 ppd->vls_operational, NULL);
11305 if (ret)
11306 return ret;
11307 }
77241056
MM		 11308 return 0;
11309}
11310
11311/*
11312 * Read the given fabric manager table. Return the size of the
11313 * table (in bytes) on success, and a negative error code on
11314 * failure.
11315 */
11316int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t)
11317
11318{
11319 int size;
11320 struct vl_arb_cache *vlc;
11321
11322 switch (which) {
11323 case FM_TBL_VL_HIGH_ARB:
11324 size = 256;
11325 /*
11326 * OPA specifies 128 elements (of 2 bytes each), though
11327 * HFI supports only 16 elements in h/w.
11328 */
11329 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE);
11330 vl_arb_get_cache(vlc, t);
11331 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
11332 break;
11333 case FM_TBL_VL_LOW_ARB:
11334 size = 256;
11335 /*
11336 * OPA specifies 128 elements (of 2 bytes each), though
11337 * HFI supports only 16 elements in h/w.
11338 */
11339 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE);
11340 vl_arb_get_cache(vlc, t);
11341 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
11342 break;
11343 case FM_TBL_BUFFER_CONTROL:
11344 size = get_buffer_control(ppd->dd, t, NULL);
11345 break;
11346 case FM_TBL_SC2VLNT:
11347 size = get_sc2vlnt(ppd->dd, t);
11348 break;
11349 case FM_TBL_VL_PREEMPT_ELEMS:
11350 size = 256;
11351 /* OPA specifies 128 elements, of 2 bytes each */
11352 get_vlarb_preempt(ppd->dd, OPA_MAX_VLS, t);
11353 break;
11354 case FM_TBL_VL_PREEMPT_MATRIX:
11355 size = 256;
11356 /*
11357 * OPA specifies that this is the same size as the VL
11358 * arbitration tables (i.e., 256 bytes).
11359 */
11360 break;
11361 default:
11362 return -EINVAL;
11363 }
11364 return size;
11365}
11366
11367/*
11368 * Write the given fabric manager table.
11369 */
11370int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t)
11371{
11372 int ret = 0;
11373 struct vl_arb_cache *vlc;
11374
11375 switch (which) {
11376 case FM_TBL_VL_HIGH_ARB:
11377 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE);
11378 if (vl_arb_match_cache(vlc, t)) {
11379 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
11380 break;
11381 }
11382 vl_arb_set_cache(vlc, t);
11383 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
11384 ret = set_vl_weights(ppd, SEND_HIGH_PRIORITY_LIST,
11385 VL_ARB_HIGH_PRIO_TABLE_SIZE, t);
11386 break;
11387 case FM_TBL_VL_LOW_ARB:
11388 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE);
11389 if (vl_arb_match_cache(vlc, t)) {
11390 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
11391 break;
11392 }
11393 vl_arb_set_cache(vlc, t);
11394 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
11395 ret = set_vl_weights(ppd, SEND_LOW_PRIORITY_LIST,
11396 VL_ARB_LOW_PRIO_TABLE_SIZE, t);
11397 break;
11398 case FM_TBL_BUFFER_CONTROL:
8a4d3444 11399 ret = set_buffer_control(ppd, t);
77241056
MM		 11400 break;
11401 case FM_TBL_SC2VLNT:
11402 set_sc2vlnt(ppd->dd, t);
11403 break;
11404 default:
11405 ret = -EINVAL;
11406 }
11407 return ret;
11408}
11409
11410/*
11411 * Disable all data VLs.
11412 *
11413 * Return 0 if disabled, non-zero if the VLs cannot be disabled.
11414 */
11415static int disable_data_vls(struct hfi1_devdata *dd)
11416{
995deafa 11417 if (is_ax(dd))
77241056
MM		 11418 return 1;
11419
11420 pio_send_control(dd, PSC_DATA_VL_DISABLE);
11421
11422 return 0;
11423}
11424
11425/*
11426 * open_fill_data_vls() - the counterpart to stop_drain_data_vls().
11427 * Just re-enables all data VLs (the "fill" part happens
11428 * automatically - the name was chosen for symmetry with
11429 * stop_drain_data_vls()).
11430 *
11431 * Return 0 if successful, non-zero if the VLs cannot be enabled.
11432 */
11433int open_fill_data_vls(struct hfi1_devdata *dd)
11434{
995deafa 11435 if (is_ax(dd))
77241056
MM		 11436 return 1;
11437
11438 pio_send_control(dd, PSC_DATA_VL_ENABLE);
11439
11440 return 0;
11441}
11442
11443/*
11444 * drain_data_vls() - assumes that disable_data_vls() has been called,
11445 * wait for occupancy (of per-VL FIFOs) for all contexts, and SDMA
11446 * engines to drop to 0.
11447 */
11448static void drain_data_vls(struct hfi1_devdata *dd)
11449{
11450 sc_wait(dd);
11451 sdma_wait(dd);
11452 pause_for_credit_return(dd);
11453}
11454
11455/*
11456 * stop_drain_data_vls() - disable, then drain all per-VL fifos.
11457 *
11458 * Use open_fill_data_vls() to resume using data VLs. This pair is
11459 * meant to be used like this:
11460 *
11461 * stop_drain_data_vls(dd);
11462 * // do things with per-VL resources
11463 * open_fill_data_vls(dd);
11464 */
11465int stop_drain_data_vls(struct hfi1_devdata *dd)
11466{
11467 int ret;
11468
11469 ret = disable_data_vls(dd);
11470 if (ret == 0)
11471 drain_data_vls(dd);
11472
11473 return ret;
11474}
11475
11476/*
11477 * Convert a nanosecond time to a cclock count. No matter how slow
11478 * the cclock, a non-zero ns will always have a non-zero result.
11479 */
11480u32 ns_to_cclock(struct hfi1_devdata *dd, u32 ns)
11481{
11482 u32 cclocks;
11483
11484 if (dd->icode == ICODE_FPGA_EMULATION)
11485 cclocks = (ns * 1000) / FPGA_CCLOCK_PS;
11486 else /* simulation pretends to be ASIC */
11487 cclocks = (ns * 1000) / ASIC_CCLOCK_PS;
11488 if (ns && !cclocks) /* if ns nonzero, must be at least 1 */
11489 cclocks = 1;
11490 return cclocks;
11491}
11492
11493/*
11494 * Convert a cclock count to nanoseconds. Not matter how slow
11495 * the cclock, a non-zero cclocks will always have a non-zero result.
11496 */
11497u32 cclock_to_ns(struct hfi1_devdata *dd, u32 cclocks)
11498{
11499 u32 ns;
11500
11501 if (dd->icode == ICODE_FPGA_EMULATION)
11502 ns = (cclocks * FPGA_CCLOCK_PS) / 1000;
11503 else /* simulation pretends to be ASIC */
11504 ns = (cclocks * ASIC_CCLOCK_PS) / 1000;
11505 if (cclocks && !ns)
11506 ns = 1;
11507 return ns;
11508}
11509
11510/*
11511 * Dynamically adjust the receive interrupt timeout for a context based on
11512 * incoming packet rate.
11513 *
11514 * NOTE: Dynamic adjustment does not allow rcv_intr_count to be zero.
11515 */
11516static void adjust_rcv_timeout(struct hfi1_ctxtdata *rcd, u32 npkts)
11517{
11518 struct hfi1_devdata *dd = rcd->dd;
11519 u32 timeout = rcd->rcvavail_timeout;
11520
11521 /*
11522 * This algorithm doubles or halves the timeout depending on whether
11523 * the number of packets received in this interrupt were less than or
11524 * greater equal the interrupt count.
11525 *
11526 * The calculations below do not allow a steady state to be achieved.
11527 * Only at the endpoints it is possible to have an unchanging
11528 * timeout.
11529 */
11530 if (npkts < rcv_intr_count) {
11531 /*
11532 * Not enough packets arrived before the timeout, adjust
11533 * timeout downward.
11534 */
11535 if (timeout < 2) /* already at minimum? */
11536 return;
11537 timeout >>= 1;
11538 } else {
11539 /*
11540 * More than enough packets arrived before the timeout, adjust
11541 * timeout upward.
11542 */
11543 if (timeout >= dd->rcv_intr_timeout_csr) /* already at max? */
11544 return;
11545 timeout = min(timeout << 1, dd->rcv_intr_timeout_csr);
11546 }
11547
11548 rcd->rcvavail_timeout = timeout;
4d114fdd
JJ		 11549 /*
11550 * timeout cannot be larger than rcv_intr_timeout_csr which has already
11551 * been verified to be in range
11552 */
77241056 11553 write_kctxt_csr(dd, rcd->ctxt, RCV_AVAIL_TIME_OUT,
17fb4f29
JJ		 11554 (u64)timeout <<
11555 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
77241056
MM		 11556}
11557
11558void update_usrhead(struct hfi1_ctxtdata *rcd, u32 hd, u32 updegr, u32 egrhd,
11559 u32 intr_adjust, u32 npkts)
11560{
11561 struct hfi1_devdata *dd = rcd->dd;
11562 u64 reg;
11563 u32 ctxt = rcd->ctxt;
11564
11565 /*
11566 * Need to write timeout register before updating RcvHdrHead to ensure
11567 * that a new value is used when the HW decides to restart counting.
11568 */
11569 if (intr_adjust)
11570 adjust_rcv_timeout(rcd, npkts);
11571 if (updegr) {
11572 reg = (egrhd & RCV_EGR_INDEX_HEAD_HEAD_MASK)
11573 << RCV_EGR_INDEX_HEAD_HEAD_SHIFT;
11574 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, reg);
11575 }
11576 mmiowb();
11577 reg = ((u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT) |
11578 (((u64)hd & RCV_HDR_HEAD_HEAD_MASK)
11579 << RCV_HDR_HEAD_HEAD_SHIFT);
11580 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg);
11581 mmiowb();
11582}
11583
11584u32 hdrqempty(struct hfi1_ctxtdata *rcd)
11585{
11586 u32 head, tail;
11587
11588 head = (read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_HEAD)
11589 & RCV_HDR_HEAD_HEAD_SMASK) >> RCV_HDR_HEAD_HEAD_SHIFT;
11590
11591 if (rcd->rcvhdrtail_kvaddr)
11592 tail = get_rcvhdrtail(rcd);
11593 else
11594 tail = read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
11595
11596 return head == tail;
11597}
11598
11599/*
11600 * Context Control and Receive Array encoding for buffer size:
11601 * 0x0 invalid
11602 * 0x1 4 KB
11603 * 0x2 8 KB
11604 * 0x3 16 KB
11605 * 0x4 32 KB
11606 * 0x5 64 KB
11607 * 0x6 128 KB
11608 * 0x7 256 KB
11609 * 0x8 512 KB (Receive Array only)
11610 * 0x9 1 MB (Receive Array only)
11611 * 0xa 2 MB (Receive Array only)
11612 *
11613 * 0xB-0xF - reserved (Receive Array only)
11614 *
11615 *
11616 * This routine assumes that the value has already been sanity checked.
11617 */
11618static u32 encoded_size(u32 size)
11619{
11620 switch (size) {
8638b77f
JJ		 11621 case 4 * 1024: return 0x1;
11622 case 8 * 1024: return 0x2;
11623 case 16 * 1024: return 0x3;
11624 case 32 * 1024: return 0x4;
11625 case 64 * 1024: return 0x5;
11626 case 128 * 1024: return 0x6;
11627 case 256 * 1024: return 0x7;
11628 case 512 * 1024: return 0x8;
11629 case 1 * 1024 * 1024: return 0x9;
11630 case 2 * 1024 * 1024: return 0xa;
77241056
MM		 11631 }
11632 return 0x1; /* if invalid, go with the minimum size */
11633}
11634
11635void hfi1_rcvctrl(struct hfi1_devdata *dd, unsigned int op, int ctxt)
11636{
11637 struct hfi1_ctxtdata *rcd;
11638 u64 rcvctrl, reg;
11639 int did_enable = 0;
11640
11641 rcd = dd->rcd[ctxt];
11642 if (!rcd)
11643 return;
11644
11645 hfi1_cdbg(RCVCTRL, "ctxt %d op 0x%x", ctxt, op);
11646
11647 rcvctrl = read_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL);
11648 /* if the context already enabled, don't do the extra steps */
d0d236ea
JJ		 11649 if ((op & HFI1_RCVCTRL_CTXT_ENB) &&
11650 !(rcvctrl & RCV_CTXT_CTRL_ENABLE_SMASK)) {
77241056
MM		 11651 /* reset the tail and hdr addresses, and sequence count */
11652 write_kctxt_csr(dd, ctxt, RCV_HDR_ADDR,
60368186 11653 rcd->rcvhdrq_dma);
77241056
MM		 11654 if (HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL))
11655 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
60368186 11656 rcd->rcvhdrqtailaddr_dma);
77241056
MM		 11657 rcd->seq_cnt = 1;
11658
11659 /* reset the cached receive header queue head value */
11660 rcd->head = 0;
11661
11662 /*
11663 * Zero the receive header queue so we don't get false
11664 * positives when checking the sequence number. The
11665 * sequence numbers could land exactly on the same spot.
11666 * E.g. a rcd restart before the receive header wrapped.
11667 */
11668 memset(rcd->rcvhdrq, 0, rcd->rcvhdrq_size);
11669
11670 /* starting timeout */
11671 rcd->rcvavail_timeout = dd->rcv_intr_timeout_csr;
11672
11673 /* enable the context */
11674 rcvctrl |= RCV_CTXT_CTRL_ENABLE_SMASK;
11675
11676 /* clean the egr buffer size first */
11677 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK;
11678 rcvctrl |= ((u64)encoded_size(rcd->egrbufs.rcvtid_size)
11679 & RCV_CTXT_CTRL_EGR_BUF_SIZE_MASK)
11680 << RCV_CTXT_CTRL_EGR_BUF_SIZE_SHIFT;
11681
11682 /* zero RcvHdrHead - set RcvHdrHead.Counter after enable */
11683 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0);
11684 did_enable = 1;
11685
11686 /* zero RcvEgrIndexHead */
11687 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, 0);
11688
11689 /* set eager count and base index */
11690 reg = (((u64)(rcd->egrbufs.alloced >> RCV_SHIFT)
11691 & RCV_EGR_CTRL_EGR_CNT_MASK)
11692 << RCV_EGR_CTRL_EGR_CNT_SHIFT) |
11693 (((rcd->eager_base >> RCV_SHIFT)
11694 & RCV_EGR_CTRL_EGR_BASE_INDEX_MASK)
11695 << RCV_EGR_CTRL_EGR_BASE_INDEX_SHIFT);
11696 write_kctxt_csr(dd, ctxt, RCV_EGR_CTRL, reg);
11697
11698 /*
11699 * Set TID (expected) count and base index.
11700 * rcd->expected_count is set to individual RcvArray entries,
11701 * not pairs, and the CSR takes a pair-count in groups of
11702 * four, so divide by 8.
11703 */
11704 reg = (((rcd->expected_count >> RCV_SHIFT)
11705 & RCV_TID_CTRL_TID_PAIR_CNT_MASK)
11706 << RCV_TID_CTRL_TID_PAIR_CNT_SHIFT) |
11707 (((rcd->expected_base >> RCV_SHIFT)
11708 & RCV_TID_CTRL_TID_BASE_INDEX_MASK)
11709 << RCV_TID_CTRL_TID_BASE_INDEX_SHIFT);
11710 write_kctxt_csr(dd, ctxt, RCV_TID_CTRL, reg);
82c2611d
NV		 11711 if (ctxt == HFI1_CTRL_CTXT)
11712 write_csr(dd, RCV_VL15, HFI1_CTRL_CTXT);
77241056
MM		 11713 }
11714 if (op & HFI1_RCVCTRL_CTXT_DIS) {
11715 write_csr(dd, RCV_VL15, 0);
46b010d3
MB		 11716 /*
11717 * When receive context is being disabled turn on tail
11718 * update with a dummy tail address and then disable
11719 * receive context.
11720 */
60368186 11721 if (dd->rcvhdrtail_dummy_dma) {
46b010d3 11722 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
60368186 11723 dd->rcvhdrtail_dummy_dma);
566c157c 11724 /* Enabling RcvCtxtCtrl.TailUpd is intentional. */
46b010d3
MB		 11725 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11726 }
11727
77241056
MM		 11728 rcvctrl &= ~RCV_CTXT_CTRL_ENABLE_SMASK;
11729 }
11730 if (op & HFI1_RCVCTRL_INTRAVAIL_ENB)
11731 rcvctrl |= RCV_CTXT_CTRL_INTR_AVAIL_SMASK;
11732 if (op & HFI1_RCVCTRL_INTRAVAIL_DIS)
11733 rcvctrl &= ~RCV_CTXT_CTRL_INTR_AVAIL_SMASK;
60368186 11734 if (op & HFI1_RCVCTRL_TAILUPD_ENB && rcd->rcvhdrqtailaddr_dma)
77241056 11735 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK;
566c157c
MH		 11736 if (op & HFI1_RCVCTRL_TAILUPD_DIS) {
11737 /* See comment on RcvCtxtCtrl.TailUpd above */
11738 if (!(op & HFI1_RCVCTRL_CTXT_DIS))
11739 rcvctrl &= ~RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11740 }
77241056
MM		 11741 if (op & HFI1_RCVCTRL_TIDFLOW_ENB)
11742 rcvctrl |= RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK;
11743 if (op & HFI1_RCVCTRL_TIDFLOW_DIS)
11744 rcvctrl &= ~RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK;
11745 if (op & HFI1_RCVCTRL_ONE_PKT_EGR_ENB) {
4d114fdd
JJ		 11746 /*
11747 * In one-packet-per-eager mode, the size comes from
11748 * the RcvArray entry.
11749 */
77241056
MM		 11750 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK;
11751 rcvctrl |= RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK;
11752 }
11753 if (op & HFI1_RCVCTRL_ONE_PKT_EGR_DIS)
11754 rcvctrl &= ~RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK;
11755 if (op & HFI1_RCVCTRL_NO_RHQ_DROP_ENB)
11756 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK;
11757 if (op & HFI1_RCVCTRL_NO_RHQ_DROP_DIS)
11758 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK;
11759 if (op & HFI1_RCVCTRL_NO_EGR_DROP_ENB)
11760 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK;
11761 if (op & HFI1_RCVCTRL_NO_EGR_DROP_DIS)
11762 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK;
11763 rcd->rcvctrl = rcvctrl;
11764 hfi1_cdbg(RCVCTRL, "ctxt %d rcvctrl 0x%llx\n", ctxt, rcvctrl);
11765 write_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL, rcd->rcvctrl);
11766
11767 /* work around sticky RcvCtxtStatus.BlockedRHQFull */
d0d236ea
JJ		 11768 if (did_enable &&
11769 (rcvctrl & RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK)) {
77241056
MM		 11770 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS);
11771 if (reg != 0) {
11772 dd_dev_info(dd, "ctxt %d status %lld (blocked)\n",
17fb4f29 11773 ctxt, reg);
77241056
MM		 11774 read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD);
11775 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x10);
11776 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x00);
11777 read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD);
11778 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS);
11779 dd_dev_info(dd, "ctxt %d status %lld (%s blocked)\n",
17fb4f29 11780 ctxt, reg, reg == 0 ? "not" : "still");
77241056
MM		 11781 }
11782 }
11783
11784 if (did_enable) {
11785 /*
11786 * The interrupt timeout and count must be set after
11787 * the context is enabled to take effect.
11788 */
11789 /* set interrupt timeout */
11790 write_kctxt_csr(dd, ctxt, RCV_AVAIL_TIME_OUT,
17fb4f29 11791 (u64)rcd->rcvavail_timeout <<
77241056
MM		 11792 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
11793
11794 /* set RcvHdrHead.Counter, zero RcvHdrHead.Head (again) */
11795 reg = (u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT;
11796 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg);
11797 }
11798
11799 if (op & (HFI1_RCVCTRL_TAILUPD_DIS | HFI1_RCVCTRL_CTXT_DIS))
11800 /*
11801 * If the context has been disabled and the Tail Update has
46b010d3
MB		 11802 * been cleared, set the RCV_HDR_TAIL_ADDR CSR to dummy address
11803 * so it doesn't contain an address that is invalid.
77241056 11804 */
46b010d3 11805 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
60368186 11806 dd->rcvhdrtail_dummy_dma);
77241056
MM		 11807}
11808
582e05c3 11809u32 hfi1_read_cntrs(struct hfi1_devdata *dd, char **namep, u64 **cntrp)
77241056
MM		 11810{
11811 int ret;
11812 u64 val = 0;
11813
11814 if (namep) {
11815 ret = dd->cntrnameslen;
77241056
MM		 11816 *namep = dd->cntrnames;
11817 } else {
11818 const struct cntr_entry *entry;
11819 int i, j;
11820
11821 ret = (dd->ndevcntrs) * sizeof(u64);
77241056
MM		 11822
11823 /* Get the start of the block of counters */
11824 *cntrp = dd->cntrs;
11825
11826 /*
11827 * Now go and fill in each counter in the block.
11828 */
11829 for (i = 0; i < DEV_CNTR_LAST; i++) {
11830 entry = &dev_cntrs[i];
11831 hfi1_cdbg(CNTR, "reading %s", entry->name);
11832 if (entry->flags & CNTR_DISABLED) {
11833 /* Nothing */
11834 hfi1_cdbg(CNTR, "\tDisabled\n");
11835 } else {
11836 if (entry->flags & CNTR_VL) {
11837 hfi1_cdbg(CNTR, "\tPer VL\n");
11838 for (j = 0; j < C_VL_COUNT; j++) {
11839 val = entry->rw_cntr(entry,
11840 dd, j,
11841 CNTR_MODE_R,
11842 0);
11843 hfi1_cdbg(
11844 CNTR,
11845 "\t\tRead 0x%llx for %d\n",
11846 val, j);
11847 dd->cntrs[entry->offset + j] =
11848 val;
11849 }
a699c6c2
VM		 11850 } else if (entry->flags & CNTR_SDMA) {
11851 hfi1_cdbg(CNTR,
11852 "\t Per SDMA Engine\n");
11853 for (j = 0; j < dd->chip_sdma_engines;
11854 j++) {
11855 val =
11856 entry->rw_cntr(entry, dd, j,
11857 CNTR_MODE_R, 0);
11858 hfi1_cdbg(CNTR,
11859 "\t\tRead 0x%llx for %d\n",
11860 val, j);
11861 dd->cntrs[entry->offset + j] =
11862 val;
11863 }
77241056
MM		 11864 } else {
11865 val = entry->rw_cntr(entry, dd,
11866 CNTR_INVALID_VL,
11867 CNTR_MODE_R, 0);
11868 dd->cntrs[entry->offset] = val;
11869 hfi1_cdbg(CNTR, "\tRead 0x%llx", val);
11870 }
11871 }
11872 }
11873 }
11874 return ret;
11875}
11876
11877/*
11878 * Used by sysfs to create files for hfi stats to read
11879 */
582e05c3 11880u32 hfi1_read_portcntrs(struct hfi1_pportdata *ppd, char **namep, u64 **cntrp)
77241056
MM		 11881{
11882 int ret;
11883 u64 val = 0;
11884
11885 if (namep) {
582e05c3
DL		 11886 ret = ppd->dd->portcntrnameslen;
11887 *namep = ppd->dd->portcntrnames;
77241056
MM		 11888 } else {
11889 const struct cntr_entry *entry;
77241056
MM		 11890 int i, j;
11891
582e05c3 11892 ret = ppd->dd->nportcntrs * sizeof(u64);
77241056
MM		 11893 *cntrp = ppd->cntrs;
11894
11895 for (i = 0; i < PORT_CNTR_LAST; i++) {
11896 entry = &port_cntrs[i];
11897 hfi1_cdbg(CNTR, "reading %s", entry->name);
11898 if (entry->flags & CNTR_DISABLED) {
11899 /* Nothing */
11900 hfi1_cdbg(CNTR, "\tDisabled\n");
11901 continue;
11902 }
11903
11904 if (entry->flags & CNTR_VL) {
11905 hfi1_cdbg(CNTR, "\tPer VL");
11906 for (j = 0; j < C_VL_COUNT; j++) {
11907 val = entry->rw_cntr(entry, ppd, j,
11908 CNTR_MODE_R,
11909 0);
11910 hfi1_cdbg(
11911 CNTR,
11912 "\t\tRead 0x%llx for %d",
11913 val, j);
11914 ppd->cntrs[entry->offset + j] = val;
11915 }
11916 } else {
11917 val = entry->rw_cntr(entry, ppd,
11918 CNTR_INVALID_VL,
11919 CNTR_MODE_R,
11920 0);
11921 ppd->cntrs[entry->offset] = val;
11922 hfi1_cdbg(CNTR, "\tRead 0x%llx", val);
11923 }
11924 }
11925 }
11926 return ret;
11927}
11928
11929static void free_cntrs(struct hfi1_devdata *dd)
11930{
11931 struct hfi1_pportdata *ppd;
11932 int i;
11933
11934 if (dd->synth_stats_timer.data)
11935 del_timer_sync(&dd->synth_stats_timer);
11936 dd->synth_stats_timer.data = 0;
11937 ppd = (struct hfi1_pportdata *)(dd + 1);
11938 for (i = 0; i < dd->num_pports; i++, ppd++) {
11939 kfree(ppd->cntrs);
11940 kfree(ppd->scntrs);
4eb06882
DD		 11941 free_percpu(ppd->ibport_data.rvp.rc_acks);
11942 free_percpu(ppd->ibport_data.rvp.rc_qacks);
11943 free_percpu(ppd->ibport_data.rvp.rc_delayed_comp);
77241056
MM		 11944 ppd->cntrs = NULL;
11945 ppd->scntrs = NULL;
4eb06882
DD		 11946 ppd->ibport_data.rvp.rc_acks = NULL;
11947 ppd->ibport_data.rvp.rc_qacks = NULL;
11948 ppd->ibport_data.rvp.rc_delayed_comp = NULL;
77241056
MM		 11949 }
11950 kfree(dd->portcntrnames);
11951 dd->portcntrnames = NULL;
11952 kfree(dd->cntrs);
11953 dd->cntrs = NULL;
11954 kfree(dd->scntrs);
11955 dd->scntrs = NULL;
11956 kfree(dd->cntrnames);
11957 dd->cntrnames = NULL;
11958}
11959
77241056
MM		 11960static u64 read_dev_port_cntr(struct hfi1_devdata *dd, struct cntr_entry *entry,
11961 u64 *psval, void *context, int vl)
11962{
11963 u64 val;
11964 u64 sval = *psval;
11965
11966 if (entry->flags & CNTR_DISABLED) {
11967 dd_dev_err(dd, "Counter %s not enabled", entry->name);
11968 return 0;
11969 }
11970
11971 hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);
11972
11973 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_R, 0);
11974
11975 /* If its a synthetic counter there is more work we need to do */
11976 if (entry->flags & CNTR_SYNTH) {
11977 if (sval == CNTR_MAX) {
11978 /* No need to read already saturated */
11979 return CNTR_MAX;
11980 }
11981
11982 if (entry->flags & CNTR_32BIT) {
11983 /* 32bit counters can wrap multiple times */
11984 u64 upper = sval >> 32;
11985 u64 lower = (sval << 32) >> 32;
11986
11987 if (lower > val) { /* hw wrapped */
11988 if (upper == CNTR_32BIT_MAX)
11989 val = CNTR_MAX;
11990 else
11991 upper++;
11992 }
11993
11994 if (val != CNTR_MAX)
11995 val = (upper << 32) | val;
11996
11997 } else {
11998 /* If we rolled we are saturated */
11999 if ((val < sval) || (val > CNTR_MAX))
12000 val = CNTR_MAX;
12001 }
12002 }
12003
12004 *psval = val;
12005
12006 hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);
12007
12008 return val;
12009}
12010
12011static u64 write_dev_port_cntr(struct hfi1_devdata *dd,
12012 struct cntr_entry *entry,
12013 u64 *psval, void *context, int vl, u64 data)
12014{
12015 u64 val;
12016
12017 if (entry->flags & CNTR_DISABLED) {
12018 dd_dev_err(dd, "Counter %s not enabled", entry->name);
12019 return 0;
12020 }
12021
12022 hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);
12023
12024 if (entry->flags & CNTR_SYNTH) {
12025 *psval = data;
12026 if (entry->flags & CNTR_32BIT) {
12027 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W,
12028 (data << 32) >> 32);
12029 val = data; /* return the full 64bit value */
12030 } else {
12031 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W,
12032 data);
12033 }
12034 } else {
12035 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, data);
12036 }
12037
12038 *psval = val;
12039
12040 hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);
12041
12042 return val;
12043}
12044
12045u64 read_dev_cntr(struct hfi1_devdata *dd, int index, int vl)
12046{
12047 struct cntr_entry *entry;
12048 u64 *sval;
12049
12050 entry = &dev_cntrs[index];
12051 sval = dd->scntrs + entry->offset;
12052
12053 if (vl != CNTR_INVALID_VL)
12054 sval += vl;
12055
12056 return read_dev_port_cntr(dd, entry, sval, dd, vl);
12057}
12058
12059u64 write_dev_cntr(struct hfi1_devdata *dd, int index, int vl, u64 data)
12060{
12061 struct cntr_entry *entry;
12062 u64 *sval;
12063
12064 entry = &dev_cntrs[index];
12065 sval = dd->scntrs + entry->offset;
12066
12067 if (vl != CNTR_INVALID_VL)
12068 sval += vl;
12069
12070 return write_dev_port_cntr(dd, entry, sval, dd, vl, data);
12071}
12072
12073u64 read_port_cntr(struct hfi1_pportdata *ppd, int index, int vl)
12074{
12075 struct cntr_entry *entry;
12076 u64 *sval;
12077
12078 entry = &port_cntrs[index];
12079 sval = ppd->scntrs + entry->offset;
12080
12081 if (vl != CNTR_INVALID_VL)
12082 sval += vl;
12083
12084 if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) &&
12085 (index <= C_RCV_HDR_OVF_LAST)) {
12086 /* We do not want to bother for disabled contexts */
12087 return 0;
12088 }
12089
12090 return read_dev_port_cntr(ppd->dd, entry, sval, ppd, vl);
12091}
12092
12093u64 write_port_cntr(struct hfi1_pportdata *ppd, int index, int vl, u64 data)
12094{
12095 struct cntr_entry *entry;
12096 u64 *sval;
12097
12098 entry = &port_cntrs[index];
12099 sval = ppd->scntrs + entry->offset;
12100
12101 if (vl != CNTR_INVALID_VL)
12102 sval += vl;
12103
12104 if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) &&
12105 (index <= C_RCV_HDR_OVF_LAST)) {
12106 /* We do not want to bother for disabled contexts */
12107 return 0;
12108 }
12109
12110 return write_dev_port_cntr(ppd->dd, entry, sval, ppd, vl, data);
12111}
12112
12113static void update_synth_timer(unsigned long opaque)
12114{
12115 u64 cur_tx;
12116 u64 cur_rx;
12117 u64 total_flits;
12118 u8 update = 0;
12119 int i, j, vl;
12120 struct hfi1_pportdata *ppd;
12121 struct cntr_entry *entry;
12122
12123 struct hfi1_devdata *dd = (struct hfi1_devdata *)opaque;
12124
12125 /*
12126 * Rather than keep beating on the CSRs pick a minimal set that we can
12127 * check to watch for potential roll over. We can do this by looking at
12128 * the number of flits sent/recv. If the total flits exceeds 32bits then
12129 * we have to iterate all the counters and update.
12130 */
12131 entry = &dev_cntrs[C_DC_RCV_FLITS];
12132 cur_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0);
12133
12134 entry = &dev_cntrs[C_DC_XMIT_FLITS];
12135 cur_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0);
12136
12137 hfi1_cdbg(
12138 CNTR,
12139 "[%d] curr tx=0x%llx rx=0x%llx :: last tx=0x%llx rx=0x%llx\n",
12140 dd->unit, cur_tx, cur_rx, dd->last_tx, dd->last_rx);
12141
12142 if ((cur_tx < dd->last_tx) || (cur_rx < dd->last_rx)) {
12143 /*
12144 * May not be strictly necessary to update but it won't hurt and
12145 * simplifies the logic here.
12146 */
12147 update = 1;
12148 hfi1_cdbg(CNTR, "[%d] Tripwire counter rolled, updating",
12149 dd->unit);
12150 } else {
12151 total_flits = (cur_tx - dd->last_tx) + (cur_rx - dd->last_rx);
12152 hfi1_cdbg(CNTR,
12153 "[%d] total flits 0x%llx limit 0x%llx\n", dd->unit,
12154 total_flits, (u64)CNTR_32BIT_MAX);
12155 if (total_flits >= CNTR_32BIT_MAX) {
12156 hfi1_cdbg(CNTR, "[%d] 32bit limit hit, updating",
12157 dd->unit);
12158 update = 1;
12159 }
12160 }
12161
12162 if (update) {
12163 hfi1_cdbg(CNTR, "[%d] Updating dd and ppd counters", dd->unit);
12164 for (i = 0; i < DEV_CNTR_LAST; i++) {
12165 entry = &dev_cntrs[i];
12166 if (entry->flags & CNTR_VL) {
12167 for (vl = 0; vl < C_VL_COUNT; vl++)
12168 read_dev_cntr(dd, i, vl);
12169 } else {
12170 read_dev_cntr(dd, i, CNTR_INVALID_VL);
12171 }
12172 }
12173 ppd = (struct hfi1_pportdata *)(dd + 1);
12174 for (i = 0; i < dd->num_pports; i++, ppd++) {
12175 for (j = 0; j < PORT_CNTR_LAST; j++) {
12176 entry = &port_cntrs[j];
12177 if (entry->flags & CNTR_VL) {
12178 for (vl = 0; vl < C_VL_COUNT; vl++)
12179 read_port_cntr(ppd, j, vl);
12180 } else {
12181 read_port_cntr(ppd, j, CNTR_INVALID_VL);
12182 }
12183 }
12184 }
12185
12186 /*
12187 * We want the value in the register. The goal is to keep track
12188 * of the number of "ticks" not the counter value. In other
12189 * words if the register rolls we want to notice it and go ahead
12190 * and force an update.
12191 */
12192 entry = &dev_cntrs[C_DC_XMIT_FLITS];
12193 dd->last_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL,
12194 CNTR_MODE_R, 0);
12195
12196 entry = &dev_cntrs[C_DC_RCV_FLITS];
12197 dd->last_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL,
12198 CNTR_MODE_R, 0);
12199
12200 hfi1_cdbg(CNTR, "[%d] setting last tx/rx to 0x%llx 0x%llx",
12201 dd->unit, dd->last_tx, dd->last_rx);
12202
12203 } else {
12204 hfi1_cdbg(CNTR, "[%d] No update necessary", dd->unit);
12205 }
12206
48a0cc13 12207 mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME);
77241056
MM		 12208}
12209
09a7908b 12210#define C_MAX_NAME 16 /* 15 chars + one for /0 */
77241056
MM		 12211static int init_cntrs(struct hfi1_devdata *dd)
12212{
c024c554 12213 int i, rcv_ctxts, j;
77241056
MM		 12214 size_t sz;
12215 char *p;
12216 char name[C_MAX_NAME];
12217 struct hfi1_pportdata *ppd;
11d2b114
SS		 12218 const char *bit_type_32 = ",32";
12219 const int bit_type_32_sz = strlen(bit_type_32);
77241056
MM		 12220
12221 /* set up the stats timer; the add_timer is done at the end */
24523a94
MFW		 12222 setup_timer(&dd->synth_stats_timer, update_synth_timer,
12223 (unsigned long)dd);
77241056
MM		 12224
12225 /***********************/
12226 /* per device counters */
12227 /***********************/
12228
12229 /* size names and determine how many we have*/
12230 dd->ndevcntrs = 0;
12231 sz = 0;
77241056
MM		 12232
12233 for (i = 0; i < DEV_CNTR_LAST; i++) {
77241056
MM		 12234 if (dev_cntrs[i].flags & CNTR_DISABLED) {
12235 hfi1_dbg_early("\tSkipping %s\n", dev_cntrs[i].name);
12236 continue;
12237 }
12238
12239 if (dev_cntrs[i].flags & CNTR_VL) {
c024c554 12240 dev_cntrs[i].offset = dd->ndevcntrs;
77241056 12241 for (j = 0; j < C_VL_COUNT; j++) {
77241056 12242 snprintf(name, C_MAX_NAME, "%s%d",
17fb4f29 12243 dev_cntrs[i].name, vl_from_idx(j));
77241056 12244 sz += strlen(name);
11d2b114
SS		 12245 /* Add ",32" for 32-bit counters */
12246 if (dev_cntrs[i].flags & CNTR_32BIT)
12247 sz += bit_type_32_sz;
77241056 12248 sz++;
77241056 12249 dd->ndevcntrs++;
77241056 12250 }
a699c6c2 12251 } else if (dev_cntrs[i].flags & CNTR_SDMA) {
c024c554 12252 dev_cntrs[i].offset = dd->ndevcntrs;
a699c6c2 12253 for (j = 0; j < dd->chip_sdma_engines; j++) {
a699c6c2
VM		 12254 snprintf(name, C_MAX_NAME, "%s%d",
12255 dev_cntrs[i].name, j);
77241056 12256 sz += strlen(name);
11d2b114
SS		 12257 /* Add ",32" for 32-bit counters */
12258 if (dev_cntrs[i].flags & CNTR_32BIT)
12259 sz += bit_type_32_sz;
77241056 12260 sz++;
77241056 12261 dd->ndevcntrs++;
77241056
MM		 12262 }
12263 } else {
11d2b114 12264 /* +1 for newline. */
77241056 12265 sz += strlen(dev_cntrs[i].name) + 1;
11d2b114
SS		 12266 /* Add ",32" for 32-bit counters */
12267 if (dev_cntrs[i].flags & CNTR_32BIT)
12268 sz += bit_type_32_sz;
c024c554 12269 dev_cntrs[i].offset = dd->ndevcntrs;
77241056 12270 dd->ndevcntrs++;
77241056
MM		 12271 }
12272 }
12273
12274 /* allocate space for the counter values */
c024c554 12275 dd->cntrs = kcalloc(dd->ndevcntrs, sizeof(u64), GFP_KERNEL);
77241056
MM		 12276 if (!dd->cntrs)
12277 goto bail;
12278
c024c554 12279 dd->scntrs = kcalloc(dd->ndevcntrs, sizeof(u64), GFP_KERNEL);
77241056
MM		 12280 if (!dd->scntrs)
12281 goto bail;
12282
77241056
MM		 12283 /* allocate space for the counter names */
12284 dd->cntrnameslen = sz;
12285 dd->cntrnames = kmalloc(sz, GFP_KERNEL);
12286 if (!dd->cntrnames)
12287 goto bail;
12288
12289 /* fill in the names */
c024c554 12290 for (p = dd->cntrnames, i = 0; i < DEV_CNTR_LAST; i++) {
77241056
MM		 12291 if (dev_cntrs[i].flags & CNTR_DISABLED) {
12292 /* Nothing */
11d2b114
SS		 12293 } else if (dev_cntrs[i].flags & CNTR_VL) {
12294 for (j = 0; j < C_VL_COUNT; j++) {
11d2b114
SS		 12295 snprintf(name, C_MAX_NAME, "%s%d",
12296 dev_cntrs[i].name,
12297 vl_from_idx(j));
12298 memcpy(p, name, strlen(name));
12299 p += strlen(name);
12300
12301 /* Counter is 32 bits */
12302 if (dev_cntrs[i].flags & CNTR_32BIT) {
12303 memcpy(p, bit_type_32, bit_type_32_sz);
12304 p += bit_type_32_sz;
77241056 12305 }
11d2b114
SS		 12306
12307 *p++ = '\n';
12308 }
12309 } else if (dev_cntrs[i].flags & CNTR_SDMA) {
12310 for (j = 0; j < dd->chip_sdma_engines; j++) {
11d2b114
SS		 12311 snprintf(name, C_MAX_NAME, "%s%d",
12312 dev_cntrs[i].name, j);
12313 memcpy(p, name, strlen(name));
12314 p += strlen(name);
12315
12316 /* Counter is 32 bits */
12317 if (dev_cntrs[i].flags & CNTR_32BIT) {
12318 memcpy(p, bit_type_32, bit_type_32_sz);
12319 p += bit_type_32_sz;
a699c6c2 12320 }
11d2b114 12321
77241056
MM		 12322 *p++ = '\n';
12323 }
11d2b114
SS		 12324 } else {
12325 memcpy(p, dev_cntrs[i].name, strlen(dev_cntrs[i].name));
12326 p += strlen(dev_cntrs[i].name);
12327
12328 /* Counter is 32 bits */
12329 if (dev_cntrs[i].flags & CNTR_32BIT) {
12330 memcpy(p, bit_type_32, bit_type_32_sz);
12331 p += bit_type_32_sz;
12332 }
12333
12334 *p++ = '\n';
77241056
MM		 12335 }
12336 }
12337
12338 /*********************/
12339 /* per port counters */
12340 /*********************/
12341
12342 /*
12343 * Go through the counters for the overflows and disable the ones we
12344 * don't need. This varies based on platform so we need to do it
12345 * dynamically here.
12346 */
12347 rcv_ctxts = dd->num_rcv_contexts;
12348 for (i = C_RCV_HDR_OVF_FIRST + rcv_ctxts;
12349 i <= C_RCV_HDR_OVF_LAST; i++) {
12350 port_cntrs[i].flags |= CNTR_DISABLED;
12351 }
12352
12353 /* size port counter names and determine how many we have*/
12354 sz = 0;
12355 dd->nportcntrs = 0;
12356 for (i = 0; i < PORT_CNTR_LAST; i++) {
77241056
MM		 12357 if (port_cntrs[i].flags & CNTR_DISABLED) {
12358 hfi1_dbg_early("\tSkipping %s\n", port_cntrs[i].name);
12359 continue;
12360 }
12361
12362 if (port_cntrs[i].flags & CNTR_VL) {
77241056
MM		 12363 port_cntrs[i].offset = dd->nportcntrs;
12364 for (j = 0; j < C_VL_COUNT; j++) {
77241056 12365 snprintf(name, C_MAX_NAME, "%s%d",
17fb4f29 12366 port_cntrs[i].name, vl_from_idx(j));
77241056 12367 sz += strlen(name);
11d2b114
SS		 12368 /* Add ",32" for 32-bit counters */
12369 if (port_cntrs[i].flags & CNTR_32BIT)
12370 sz += bit_type_32_sz;
77241056 12371 sz++;
77241056
MM		 12372 dd->nportcntrs++;
12373 }
12374 } else {
11d2b114 12375 /* +1 for newline */
77241056 12376 sz += strlen(port_cntrs[i].name) + 1;
11d2b114
SS		 12377 /* Add ",32" for 32-bit counters */
12378 if (port_cntrs[i].flags & CNTR_32BIT)
12379 sz += bit_type_32_sz;
77241056
MM		 12380 port_cntrs[i].offset = dd->nportcntrs;
12381 dd->nportcntrs++;
77241056
MM		 12382 }
12383 }
12384
12385 /* allocate space for the counter names */
12386 dd->portcntrnameslen = sz;
12387 dd->portcntrnames = kmalloc(sz, GFP_KERNEL);
12388 if (!dd->portcntrnames)
12389 goto bail;
12390
12391 /* fill in port cntr names */
12392 for (p = dd->portcntrnames, i = 0; i < PORT_CNTR_LAST; i++) {
12393 if (port_cntrs[i].flags & CNTR_DISABLED)
12394 continue;
12395
12396 if (port_cntrs[i].flags & CNTR_VL) {
12397 for (j = 0; j < C_VL_COUNT; j++) {
77241056 12398 snprintf(name, C_MAX_NAME, "%s%d",
17fb4f29 12399 port_cntrs[i].name, vl_from_idx(j));
77241056
MM		 12400 memcpy(p, name, strlen(name));
12401 p += strlen(name);
11d2b114
SS		 12402
12403 /* Counter is 32 bits */
12404 if (port_cntrs[i].flags & CNTR_32BIT) {
12405 memcpy(p, bit_type_32, bit_type_32_sz);
12406 p += bit_type_32_sz;
12407 }
12408
77241056
MM		 12409 *p++ = '\n';
12410 }
12411 } else {
12412 memcpy(p, port_cntrs[i].name,
12413 strlen(port_cntrs[i].name));
12414 p += strlen(port_cntrs[i].name);
11d2b114
SS		 12415
12416 /* Counter is 32 bits */
12417 if (port_cntrs[i].flags & CNTR_32BIT) {
12418 memcpy(p, bit_type_32, bit_type_32_sz);
12419 p += bit_type_32_sz;
12420 }
12421
77241056
MM		 12422 *p++ = '\n';
12423 }
12424 }
12425
12426 /* allocate per port storage for counter values */
12427 ppd = (struct hfi1_pportdata *)(dd + 1);
12428 for (i = 0; i < dd->num_pports; i++, ppd++) {
12429 ppd->cntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL);
12430 if (!ppd->cntrs)
12431 goto bail;
12432
12433 ppd->scntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL);
12434 if (!ppd->scntrs)
12435 goto bail;
12436 }
12437
12438 /* CPU counters need to be allocated and zeroed */
12439 if (init_cpu_counters(dd))
12440 goto bail;
12441
12442 mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME);
12443 return 0;
12444bail:
12445 free_cntrs(dd);
12446 return -ENOMEM;
12447}
12448
77241056
MM		 12449static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate)
12450{
12451 switch (chip_lstate) {
12452 default:
12453 dd_dev_err(dd,
17fb4f29
JJ		 12454 "Unknown logical state 0x%x, reporting IB_PORT_DOWN\n",
12455 chip_lstate);
77241056
MM		 12456 /* fall through */
12457 case LSTATE_DOWN:
12458 return IB_PORT_DOWN;
12459 case LSTATE_INIT:
12460 return IB_PORT_INIT;
12461 case LSTATE_ARMED:
12462 return IB_PORT_ARMED;
12463 case LSTATE_ACTIVE:
12464 return IB_PORT_ACTIVE;
12465 }
12466}
12467
12468u32 chip_to_opa_pstate(struct hfi1_devdata *dd, u32 chip_pstate)
12469{
12470 /* look at the HFI meta-states only */
12471 switch (chip_pstate & 0xf0) {
12472 default:
12473 dd_dev_err(dd, "Unexpected chip physical state of 0x%x\n",
17fb4f29 12474 chip_pstate);
77241056
MM		 12475 /* fall through */
12476 case PLS_DISABLED:
12477 return IB_PORTPHYSSTATE_DISABLED;
12478 case PLS_OFFLINE:
12479 return OPA_PORTPHYSSTATE_OFFLINE;
12480 case PLS_POLLING:
12481 return IB_PORTPHYSSTATE_POLLING;
12482 case PLS_CONFIGPHY:
12483 return IB_PORTPHYSSTATE_TRAINING;
12484 case PLS_LINKUP:
12485 return IB_PORTPHYSSTATE_LINKUP;
12486 case PLS_PHYTEST:
12487 return IB_PORTPHYSSTATE_PHY_TEST;
12488 }
12489}
12490
12491/* return the OPA port logical state name */
12492const char *opa_lstate_name(u32 lstate)
12493{
12494 static const char * const port_logical_names[] = {
12495 "PORT_NOP",
12496 "PORT_DOWN",
12497 "PORT_INIT",
12498 "PORT_ARMED",
12499 "PORT_ACTIVE",
12500 "PORT_ACTIVE_DEFER",
12501 };
12502 if (lstate < ARRAY_SIZE(port_logical_names))
12503 return port_logical_names[lstate];
12504 return "unknown";
12505}
12506
12507/* return the OPA port physical state name */
12508const char *opa_pstate_name(u32 pstate)
12509{
12510 static const char * const port_physical_names[] = {
12511 "PHYS_NOP",
12512 "reserved1",
12513 "PHYS_POLL",
12514 "PHYS_DISABLED",
12515 "PHYS_TRAINING",
12516 "PHYS_LINKUP",
12517 "PHYS_LINK_ERR_RECOVER",
12518 "PHYS_PHY_TEST",
12519 "reserved8",
12520 "PHYS_OFFLINE",
12521 "PHYS_GANGED",
12522 "PHYS_TEST",
12523 };
12524 if (pstate < ARRAY_SIZE(port_physical_names))
12525 return port_physical_names[pstate];
12526 return "unknown";
12527}
12528
12529/*
12530 * Read the hardware link state and set the driver's cached value of it.
12531 * Return the (new) current value.
12532 */
12533u32 get_logical_state(struct hfi1_pportdata *ppd)
12534{
12535 u32 new_state;
12536
12537 new_state = chip_to_opa_lstate(ppd->dd, read_logical_state(ppd->dd));
12538 if (new_state != ppd->lstate) {
12539 dd_dev_info(ppd->dd, "logical state changed to %s (0x%x)\n",
17fb4f29 12540 opa_lstate_name(new_state), new_state);
77241056
MM		 12541 ppd->lstate = new_state;
12542 }
12543 /*
12544 * Set port status flags in the page mapped into userspace
12545 * memory. Do it here to ensure a reliable state - this is
12546 * the only function called by all state handling code.
12547 * Always set the flags due to the fact that the cache value
12548 * might have been changed explicitly outside of this
12549 * function.
12550 */
12551 if (ppd->statusp) {
12552 switch (ppd->lstate) {
12553 case IB_PORT_DOWN:
12554 case IB_PORT_INIT:
12555 *ppd->statusp &= ~(HFI1_STATUS_IB_CONF |
12556 HFI1_STATUS_IB_READY);
12557 break;
12558 case IB_PORT_ARMED:
12559 *ppd->statusp |= HFI1_STATUS_IB_CONF;
12560 break;
12561 case IB_PORT_ACTIVE:
12562 *ppd->statusp |= HFI1_STATUS_IB_READY;
12563 break;
12564 }
12565 }
12566 return ppd->lstate;
12567}
12568
12569/**
12570 * wait_logical_linkstate - wait for an IB link state change to occur
12571 * @ppd: port device
12572 * @state: the state to wait for
12573 * @msecs: the number of milliseconds to wait
12574 *
12575 * Wait up to msecs milliseconds for IB link state change to occur.
12576 * For now, take the easy polling route.
12577 * Returns 0 if state reached, otherwise -ETIMEDOUT.
12578 */
12579static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state,
12580 int msecs)
12581{
12582 unsigned long timeout;
12583
12584 timeout = jiffies + msecs_to_jiffies(msecs);
12585 while (1) {
12586 if (get_logical_state(ppd) == state)
12587 return 0;
12588 if (time_after(jiffies, timeout))
12589 break;
12590 msleep(20);
12591 }
12592 dd_dev_err(ppd->dd, "timeout waiting for link state 0x%x\n", state);
12593
12594 return -ETIMEDOUT;
12595}
12596
12597u8 hfi1_ibphys_portstate(struct hfi1_pportdata *ppd)
12598{
77241056
MM		 12599 u32 pstate;
12600 u32 ib_pstate;
12601
12602 pstate = read_physical_state(ppd->dd);
12603 ib_pstate = chip_to_opa_pstate(ppd->dd, pstate);
f45c8dc8 12604 if (ppd->last_pstate != ib_pstate) {
77241056 12605 dd_dev_info(ppd->dd,
17fb4f29
JJ		 12606 "%s: physical state changed to %s (0x%x), phy 0x%x\n",
12607 __func__, opa_pstate_name(ib_pstate), ib_pstate,
12608 pstate);
f45c8dc8 12609 ppd->last_pstate = ib_pstate;
77241056
MM		 12610 }
12611 return ib_pstate;
12612}
12613
77241056
MM		 12614#define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \
12615(r &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
12616
12617#define SET_STATIC_RATE_CONTROL_SMASK(r) \
12618(r |= SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
12619
12620int hfi1_init_ctxt(struct send_context *sc)
12621{
d125a6c6 12622 if (sc) {
77241056
MM		 12623 struct hfi1_devdata *dd = sc->dd;
12624 u64 reg;
12625 u8 set = (sc->type == SC_USER ?
12626 HFI1_CAP_IS_USET(STATIC_RATE_CTRL) :
12627 HFI1_CAP_IS_KSET(STATIC_RATE_CTRL));
12628 reg = read_kctxt_csr(dd, sc->hw_context,
12629 SEND_CTXT_CHECK_ENABLE);
12630 if (set)
12631 CLEAR_STATIC_RATE_CONTROL_SMASK(reg);
12632 else
12633 SET_STATIC_RATE_CONTROL_SMASK(reg);
12634 write_kctxt_csr(dd, sc->hw_context,
12635 SEND_CTXT_CHECK_ENABLE, reg);
12636 }
12637 return 0;
12638}
12639
12640int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp)
12641{
12642 int ret = 0;
12643 u64 reg;
12644
12645 if (dd->icode != ICODE_RTL_SILICON) {
12646 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
12647 dd_dev_info(dd, "%s: tempsense not supported by HW\n",
12648 __func__);
12649 return -EINVAL;
12650 }
12651 reg = read_csr(dd, ASIC_STS_THERM);
12652 temp->curr = ((reg >> ASIC_STS_THERM_CURR_TEMP_SHIFT) &
12653 ASIC_STS_THERM_CURR_TEMP_MASK);
12654 temp->lo_lim = ((reg >> ASIC_STS_THERM_LO_TEMP_SHIFT) &
12655 ASIC_STS_THERM_LO_TEMP_MASK);
12656 temp->hi_lim = ((reg >> ASIC_STS_THERM_HI_TEMP_SHIFT) &
12657 ASIC_STS_THERM_HI_TEMP_MASK);
12658 temp->crit_lim = ((reg >> ASIC_STS_THERM_CRIT_TEMP_SHIFT) &
12659 ASIC_STS_THERM_CRIT_TEMP_MASK);
12660 /* triggers is a 3-bit value - 1 bit per trigger. */
12661 temp->triggers = (u8)((reg >> ASIC_STS_THERM_LOW_SHIFT) & 0x7);
12662
12663 return ret;
12664}
12665
12666/* ========================================================================= */
12667
12668/*
12669 * Enable/disable chip from delivering interrupts.
12670 */
12671void set_intr_state(struct hfi1_devdata *dd, u32 enable)
12672{
12673 int i;
12674
12675 /*
12676 * In HFI, the mask needs to be 1 to allow interrupts.
12677 */
12678 if (enable) {
77241056
MM		 12679 /* enable all interrupts */
12680 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
8638b77f 12681 write_csr(dd, CCE_INT_MASK + (8 * i), ~(u64)0);
77241056 12682
8ebd4cf1 12683 init_qsfp_int(dd);
77241056
MM		 12684 } else {
12685 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
8638b77f 12686 write_csr(dd, CCE_INT_MASK + (8 * i), 0ull);
77241056
MM		 12687 }
12688}
12689
12690/*
12691 * Clear all interrupt sources on the chip.
12692 */
12693static void clear_all_interrupts(struct hfi1_devdata *dd)
12694{
12695 int i;
12696
12697 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
8638b77f 12698 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~(u64)0);
77241056
MM		 12699
12700 write_csr(dd, CCE_ERR_CLEAR, ~(u64)0);
12701 write_csr(dd, MISC_ERR_CLEAR, ~(u64)0);
12702 write_csr(dd, RCV_ERR_CLEAR, ~(u64)0);
12703 write_csr(dd, SEND_ERR_CLEAR, ~(u64)0);
12704 write_csr(dd, SEND_PIO_ERR_CLEAR, ~(u64)0);
12705 write_csr(dd, SEND_DMA_ERR_CLEAR, ~(u64)0);
12706 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~(u64)0);
12707 for (i = 0; i < dd->chip_send_contexts; i++)
12708 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~(u64)0);
12709 for (i = 0; i < dd->chip_sdma_engines; i++)
12710 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~(u64)0);
12711
12712 write_csr(dd, DCC_ERR_FLG_CLR, ~(u64)0);
12713 write_csr(dd, DC_LCB_ERR_CLR, ~(u64)0);
12714 write_csr(dd, DC_DC8051_ERR_CLR, ~(u64)0);
12715}
12716
12717/* Move to pcie.c? */
12718static void disable_intx(struct pci_dev *pdev)
12719{
12720 pci_intx(pdev, 0);
12721}
12722
12723static void clean_up_interrupts(struct hfi1_devdata *dd)
12724{
12725 int i;
12726
12727 /* remove irqs - must happen before disabling/turning off */
12728 if (dd->num_msix_entries) {
12729 /* MSI-X */
12730 struct hfi1_msix_entry *me = dd->msix_entries;
12731
12732 for (i = 0; i < dd->num_msix_entries; i++, me++) {
d125a6c6 12733 if (!me->arg) /* => no irq, no affinity */
957558c9
MH		 12734 continue;
12735 hfi1_put_irq_affinity(dd, &dd->msix_entries[i]);
77241056
MM		 12736 free_irq(me->msix.vector, me->arg);
12737 }
12738 } else {
12739 /* INTx */
12740 if (dd->requested_intx_irq) {
12741 free_irq(dd->pcidev->irq, dd);
12742 dd->requested_intx_irq = 0;
12743 }
12744 }
12745
12746 /* turn off interrupts */
12747 if (dd->num_msix_entries) {
12748 /* MSI-X */
6e5b6131 12749 pci_disable_msix(dd->pcidev);
77241056
MM		 12750 } else {
12751 /* INTx */
12752 disable_intx(dd->pcidev);
12753 }
12754
12755 /* clean structures */
77241056
MM		 12756 kfree(dd->msix_entries);
12757 dd->msix_entries = NULL;
12758 dd->num_msix_entries = 0;
12759}
12760
12761/*
12762 * Remap the interrupt source from the general handler to the given MSI-X
12763 * interrupt.
12764 */
12765static void remap_intr(struct hfi1_devdata *dd, int isrc, int msix_intr)
12766{
12767 u64 reg;
12768 int m, n;
12769
12770 /* clear from the handled mask of the general interrupt */
12771 m = isrc / 64;
12772 n = isrc % 64;
12773 dd->gi_mask[m] &= ~((u64)1 << n);
12774
12775 /* direct the chip source to the given MSI-X interrupt */
12776 m = isrc / 8;
12777 n = isrc % 8;
8638b77f
JJ		 12778 reg = read_csr(dd, CCE_INT_MAP + (8 * m));
12779 reg &= ~((u64)0xff << (8 * n));
12780 reg |= ((u64)msix_intr & 0xff) << (8 * n);
12781 write_csr(dd, CCE_INT_MAP + (8 * m), reg);
77241056
MM		 12782}
12783
12784static void remap_sdma_interrupts(struct hfi1_devdata *dd,
12785 int engine, int msix_intr)
12786{
12787 /*
12788 * SDMA engine interrupt sources grouped by type, rather than
12789 * engine. Per-engine interrupts are as follows:
12790 * SDMA
12791 * SDMAProgress
12792 * SDMAIdle
12793 */
8638b77f 12794 remap_intr(dd, IS_SDMA_START + 0 * TXE_NUM_SDMA_ENGINES + engine,
17fb4f29 12795 msix_intr);
8638b77f 12796 remap_intr(dd, IS_SDMA_START + 1 * TXE_NUM_SDMA_ENGINES + engine,
17fb4f29 12797 msix_intr);
8638b77f 12798 remap_intr(dd, IS_SDMA_START + 2 * TXE_NUM_SDMA_ENGINES + engine,
17fb4f29 12799 msix_intr);
77241056
MM		 12800}
12801
77241056
MM		 12802static int request_intx_irq(struct hfi1_devdata *dd)
12803{
12804 int ret;
12805
9805071e
JJ		 12806 snprintf(dd->intx_name, sizeof(dd->intx_name), DRIVER_NAME "_%d",
12807 dd->unit);
77241056 12808 ret = request_irq(dd->pcidev->irq, general_interrupt,
17fb4f29 12809 IRQF_SHARED, dd->intx_name, dd);
77241056
MM		 12810 if (ret)
12811 dd_dev_err(dd, "unable to request INTx interrupt, err %d\n",
17fb4f29 12812 ret);
77241056
MM		 12813 else
12814 dd->requested_intx_irq = 1;
12815 return ret;
12816}
12817
12818static int request_msix_irqs(struct hfi1_devdata *dd)
12819{
77241056
MM		 12820 int first_general, last_general;
12821 int first_sdma, last_sdma;
12822 int first_rx, last_rx;
957558c9 12823 int i, ret = 0;
77241056
MM		 12824
12825 /* calculate the ranges we are going to use */
12826 first_general = 0;
f3ff8189
JJ		 12827 last_general = first_general + 1;
12828 first_sdma = last_general;
12829 last_sdma = first_sdma + dd->num_sdma;
12830 first_rx = last_sdma;
77241056
MM		 12831 last_rx = first_rx + dd->n_krcv_queues;
12832
77241056
MM		 12833 /*
12834 * Sanity check - the code expects all SDMA chip source
12835 * interrupts to be in the same CSR, starting at bit 0. Verify
12836 * that this is true by checking the bit location of the start.
12837 */
12838 BUILD_BUG_ON(IS_SDMA_START % 64);
12839
12840 for (i = 0; i < dd->num_msix_entries; i++) {
12841 struct hfi1_msix_entry *me = &dd->msix_entries[i];
12842 const char *err_info;
12843 irq_handler_t handler;
f4f30031 12844 irq_handler_t thread = NULL;
77241056
MM		 12845 void *arg;
12846 int idx;
12847 struct hfi1_ctxtdata *rcd = NULL;
12848 struct sdma_engine *sde = NULL;
12849
12850 /* obtain the arguments to request_irq */
12851 if (first_general <= i && i < last_general) {
12852 idx = i - first_general;
12853 handler = general_interrupt;
12854 arg = dd;
12855 snprintf(me->name, sizeof(me->name),
9805071e 12856 DRIVER_NAME "_%d", dd->unit);
77241056 12857 err_info = "general";
957558c9 12858 me->type = IRQ_GENERAL;
77241056
MM		 12859 } else if (first_sdma <= i && i < last_sdma) {
12860 idx = i - first_sdma;
12861 sde = &dd->per_sdma[idx];
12862 handler = sdma_interrupt;
12863 arg = sde;
12864 snprintf(me->name, sizeof(me->name),
9805071e 12865 DRIVER_NAME "_%d sdma%d", dd->unit, idx);
77241056
MM		 12866 err_info = "sdma";
12867 remap_sdma_interrupts(dd, idx, i);
957558c9 12868 me->type = IRQ_SDMA;
77241056
MM		 12869 } else if (first_rx <= i && i < last_rx) {
12870 idx = i - first_rx;
12871 rcd = dd->rcd[idx];
12872 /* no interrupt if no rcd */
12873 if (!rcd)
12874 continue;
12875 /*
12876 * Set the interrupt register and mask for this
12877 * context's interrupt.
12878 */
8638b77f 12879 rcd->ireg = (IS_RCVAVAIL_START + idx) / 64;
77241056 12880 rcd->imask = ((u64)1) <<
8638b77f 12881 ((IS_RCVAVAIL_START + idx) % 64);
77241056 12882 handler = receive_context_interrupt;
f4f30031 12883 thread = receive_context_thread;
77241056
MM		 12884 arg = rcd;
12885 snprintf(me->name, sizeof(me->name),
9805071e 12886 DRIVER_NAME "_%d kctxt%d", dd->unit, idx);
77241056 12887 err_info = "receive context";
66c0933b 12888 remap_intr(dd, IS_RCVAVAIL_START + idx, i);
957558c9 12889 me->type = IRQ_RCVCTXT;
77241056
MM		 12890 } else {
12891 /* not in our expected range - complain, then
4d114fdd
JJ		 12892 * ignore it
12893 */
77241056 12894 dd_dev_err(dd,
17fb4f29 12895 "Unexpected extra MSI-X interrupt %d\n", i);
77241056
MM		 12896 continue;
12897 }
12898 /* no argument, no interrupt */
d125a6c6 12899 if (!arg)
77241056
MM		 12900 continue;
12901 /* make sure the name is terminated */
8638b77f 12902 me->name[sizeof(me->name) - 1] = 0;
77241056 12903
f4f30031 12904 ret = request_threaded_irq(me->msix.vector, handler, thread, 0,
17fb4f29 12905 me->name, arg);
77241056
MM		 12906 if (ret) {
12907 dd_dev_err(dd,
17fb4f29
JJ		 12908 "unable to allocate %s interrupt, vector %d, index %d, err %d\n",
12909 err_info, me->msix.vector, idx, ret);
77241056
MM		 12910 return ret;
12911 }
12912 /*
12913 * assign arg after request_irq call, so it will be
12914 * cleaned up
12915 */
12916 me->arg = arg;
12917
957558c9
MH		 12918 ret = hfi1_get_irq_affinity(dd, me);
12919 if (ret)
12920 dd_dev_err(dd,
12921 "unable to pin IRQ %d\n", ret);
77241056
MM		 12922 }
12923
77241056 12924 return ret;
77241056
MM		 12925}
12926
12927/*
12928 * Set the general handler to accept all interrupts, remap all
12929 * chip interrupts back to MSI-X 0.
12930 */
12931static void reset_interrupts(struct hfi1_devdata *dd)
12932{
12933 int i;
12934
12935 /* all interrupts handled by the general handler */
12936 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
12937 dd->gi_mask[i] = ~(u64)0;
12938
12939 /* all chip interrupts map to MSI-X 0 */
12940 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
8638b77f 12941 write_csr(dd, CCE_INT_MAP + (8 * i), 0);
77241056
MM		 12942}
12943
12944static int set_up_interrupts(struct hfi1_devdata *dd)
12945{
12946 struct hfi1_msix_entry *entries;
12947 u32 total, request;
12948 int i, ret;
12949 int single_interrupt = 0; /* we expect to have all the interrupts */
12950
12951 /*
12952 * Interrupt count:
12953 * 1 general, "slow path" interrupt (includes the SDMA engines
12954 * slow source, SDMACleanupDone)
12955 * N interrupts - one per used SDMA engine
12956 * M interrupt - one per kernel receive context
12957 */
12958 total = 1 + dd->num_sdma + dd->n_krcv_queues;
12959
12960 entries = kcalloc(total, sizeof(*entries), GFP_KERNEL);
12961 if (!entries) {
77241056
MM		 12962 ret = -ENOMEM;
12963 goto fail;
12964 }
12965 /* 1-1 MSI-X entry assignment */
12966 for (i = 0; i < total; i++)
12967 entries[i].msix.entry = i;
12968
12969 /* ask for MSI-X interrupts */
12970 request = total;
12971 request_msix(dd, &request, entries);
12972
12973 if (request == 0) {
12974 /* using INTx */
12975 /* dd->num_msix_entries already zero */
12976 kfree(entries);
12977 single_interrupt = 1;
12978 dd_dev_err(dd, "MSI-X failed, using INTx interrupts\n");
12979 } else {
12980 /* using MSI-X */
12981 dd->num_msix_entries = request;
12982 dd->msix_entries = entries;
12983
12984 if (request != total) {
12985 /* using MSI-X, with reduced interrupts */
12986 dd_dev_err(
12987 dd,
12988 "cannot handle reduced interrupt case, want %u, got %u\n",
12989 total, request);
12990 ret = -EINVAL;
12991 goto fail;
12992 }
12993 dd_dev_info(dd, "%u MSI-X interrupts allocated\n", total);
12994 }
12995
12996 /* mask all interrupts */
12997 set_intr_state(dd, 0);
12998 /* clear all pending interrupts */
12999 clear_all_interrupts(dd);
13000
13001 /* reset general handler mask, chip MSI-X mappings */
13002 reset_interrupts(dd);
13003
13004 if (single_interrupt)
13005 ret = request_intx_irq(dd);
13006 else
13007 ret = request_msix_irqs(dd);
13008 if (ret)
13009 goto fail;
13010
13011 return 0;
13012
13013fail:
13014 clean_up_interrupts(dd);
13015 return ret;
13016}
13017
13018/*
13019 * Set up context values in dd. Sets:
13020 *
13021 * num_rcv_contexts - number of contexts being used
13022 * n_krcv_queues - number of kernel contexts
13023 * first_user_ctxt - first non-kernel context in array of contexts
13024 * freectxts - number of free user contexts
13025 * num_send_contexts - number of PIO send contexts being used
13026 */
13027static int set_up_context_variables(struct hfi1_devdata *dd)
13028{
429b6a72 13029 unsigned long num_kernel_contexts;
77241056
MM		 13030 int total_contexts;
13031 int ret;
13032 unsigned ngroups;
8f000f7f
DL		 13033 int qos_rmt_count;
13034 int user_rmt_reduced;
77241056
MM		 13035
13036 /*
33a9eb52 13037 * Kernel receive contexts:
82c2611d 13038 * - Context 0 - control context (VL15/multicast/error)
33a9eb52
DL		 13039 * - Context 1 - first kernel context
13040 * - Context 2 - second kernel context
13041 * ...
77241056
MM		 13042 */
13043 if (n_krcvqs)
82c2611d 13044 /*
33a9eb52
DL		 13045 * n_krcvqs is the sum of module parameter kernel receive
13046 * contexts, krcvqs[]. It does not include the control
13047 * context, so add that.
82c2611d 13048 */
33a9eb52 13049 num_kernel_contexts = n_krcvqs + 1;
77241056 13050 else
8784ac02 13051 num_kernel_contexts = DEFAULT_KRCVQS + 1;
77241056
MM		 13052 /*
13053 * Every kernel receive context needs an ACK send context.
13054 * one send context is allocated for each VL{0-7} and VL15
13055 */
13056 if (num_kernel_contexts > (dd->chip_send_contexts - num_vls - 1)) {
13057 dd_dev_err(dd,
429b6a72 13058 "Reducing # kernel rcv contexts to: %d, from %lu\n",
77241056 13059 (int)(dd->chip_send_contexts - num_vls - 1),
429b6a72 13060 num_kernel_contexts);
77241056
MM		 13061 num_kernel_contexts = dd->chip_send_contexts - num_vls - 1;
13062 }
13063 /*
0852d241
JJ		 13064 * User contexts:
13065 * - default to 1 user context per real (non-HT) CPU core if
13066 * num_user_contexts is negative
77241056 13067 */
2ce6bf22 13068 if (num_user_contexts < 0)
0852d241 13069 num_user_contexts =
4197344b 13070 cpumask_weight(&node_affinity.real_cpu_mask);
77241056
MM		 13071
13072 total_contexts = num_kernel_contexts + num_user_contexts;
13073
13074 /*
13075 * Adjust the counts given a global max.
13076 */
13077 if (total_contexts > dd->chip_rcv_contexts) {
13078 dd_dev_err(dd,
13079 "Reducing # user receive contexts to: %d, from %d\n",
13080 (int)(dd->chip_rcv_contexts - num_kernel_contexts),
13081 (int)num_user_contexts);
13082 num_user_contexts = dd->chip_rcv_contexts - num_kernel_contexts;
13083 /* recalculate */
13084 total_contexts = num_kernel_contexts + num_user_contexts;
13085 }
13086
8f000f7f
DL		 13087 /* each user context requires an entry in the RMT */
13088 qos_rmt_count = qos_rmt_entries(dd, NULL, NULL);
13089 if (qos_rmt_count + num_user_contexts > NUM_MAP_ENTRIES) {
13090 user_rmt_reduced = NUM_MAP_ENTRIES - qos_rmt_count;
13091 dd_dev_err(dd,
13092 "RMT size is reducing the number of user receive contexts from %d to %d\n",
13093 (int)num_user_contexts,
13094 user_rmt_reduced);
13095 /* recalculate */
13096 num_user_contexts = user_rmt_reduced;
13097 total_contexts = num_kernel_contexts + num_user_contexts;
13098 }
13099
77241056
MM		 13100 /* the first N are kernel contexts, the rest are user contexts */
13101 dd->num_rcv_contexts = total_contexts;
13102 dd->n_krcv_queues = num_kernel_contexts;
13103 dd->first_user_ctxt = num_kernel_contexts;
affa48de 13104 dd->num_user_contexts = num_user_contexts;
77241056
MM		 13105 dd->freectxts = num_user_contexts;
13106 dd_dev_info(dd,
17fb4f29
JJ		 13107 "rcv contexts: chip %d, used %d (kernel %d, user %d)\n",
13108 (int)dd->chip_rcv_contexts,
13109 (int)dd->num_rcv_contexts,
13110 (int)dd->n_krcv_queues,
13111 (int)dd->num_rcv_contexts - dd->n_krcv_queues);
77241056
MM		 13112
13113 /*
13114 * Receive array allocation:
13115 * All RcvArray entries are divided into groups of 8. This
13116 * is required by the hardware and will speed up writes to
13117 * consecutive entries by using write-combining of the entire
13118 * cacheline.
13119 *
13120 * The number of groups are evenly divided among all contexts.
13121 * any left over groups will be given to the first N user
13122 * contexts.
13123 */
13124 dd->rcv_entries.group_size = RCV_INCREMENT;
13125 ngroups = dd->chip_rcv_array_count / dd->rcv_entries.group_size;
13126 dd->rcv_entries.ngroups = ngroups / dd->num_rcv_contexts;
13127 dd->rcv_entries.nctxt_extra = ngroups -
13128 (dd->num_rcv_contexts * dd->rcv_entries.ngroups);
13129 dd_dev_info(dd, "RcvArray groups %u, ctxts extra %u\n",
13130 dd->rcv_entries.ngroups,
13131 dd->rcv_entries.nctxt_extra);
13132 if (dd->rcv_entries.ngroups * dd->rcv_entries.group_size >
13133 MAX_EAGER_ENTRIES * 2) {
13134 dd->rcv_entries.ngroups = (MAX_EAGER_ENTRIES * 2) /
13135 dd->rcv_entries.group_size;
13136 dd_dev_info(dd,
17fb4f29
JJ		 13137 "RcvArray group count too high, change to %u\n",
13138 dd->rcv_entries.ngroups);
77241056
MM		 13139 dd->rcv_entries.nctxt_extra = 0;
13140 }
13141 /*
13142 * PIO send contexts
13143 */
13144 ret = init_sc_pools_and_sizes(dd);
13145 if (ret >= 0) { /* success */
13146 dd->num_send_contexts = ret;
13147 dd_dev_info(
13148 dd,
44306f15 13149 "send contexts: chip %d, used %d (kernel %d, ack %d, user %d, vl15 %d)\n",
77241056
MM		 13150 dd->chip_send_contexts,
13151 dd->num_send_contexts,
13152 dd->sc_sizes[SC_KERNEL].count,
13153 dd->sc_sizes[SC_ACK].count,
44306f15
JX		 13154 dd->sc_sizes[SC_USER].count,
13155 dd->sc_sizes[SC_VL15].count);
77241056
MM		 13156 ret = 0; /* success */
13157 }
13158
13159 return ret;
13160}
13161
13162/*
13163 * Set the device/port partition key table. The MAD code
13164 * will ensure that, at least, the partial management
13165 * partition key is present in the table.
13166 */
13167static void set_partition_keys(struct hfi1_pportdata *ppd)
13168{
13169 struct hfi1_devdata *dd = ppd->dd;
13170 u64 reg = 0;
13171 int i;
13172
13173 dd_dev_info(dd, "Setting partition keys\n");
13174 for (i = 0; i < hfi1_get_npkeys(dd); i++) {
13175 reg |= (ppd->pkeys[i] &
13176 RCV_PARTITION_KEY_PARTITION_KEY_A_MASK) <<
13177 ((i % 4) *
13178 RCV_PARTITION_KEY_PARTITION_KEY_B_SHIFT);
13179 /* Each register holds 4 PKey values. */
13180 if ((i % 4) == 3) {
13181 write_csr(dd, RCV_PARTITION_KEY +
13182 ((i - 3) * 2), reg);
13183 reg = 0;
13184 }
13185 }
13186
13187 /* Always enable HW pkeys check when pkeys table is set */
13188 add_rcvctrl(dd, RCV_CTRL_RCV_PARTITION_KEY_ENABLE_SMASK);
13189}
13190
13191/*
13192 * These CSRs and memories are uninitialized on reset and must be
13193 * written before reading to set the ECC/parity bits.
13194 *
13195 * NOTE: All user context CSRs that are not mmaped write-only
13196 * (e.g. the TID flows) must be initialized even if the driver never
13197 * reads them.
13198 */
13199static void write_uninitialized_csrs_and_memories(struct hfi1_devdata *dd)
13200{
13201 int i, j;
13202
13203 /* CceIntMap */
13204 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
8638b77f 13205 write_csr(dd, CCE_INT_MAP + (8 * i), 0);
77241056
MM		 13206
13207 /* SendCtxtCreditReturnAddr */
13208 for (i = 0; i < dd->chip_send_contexts; i++)
13209 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0);
13210
13211 /* PIO Send buffers */
13212 /* SDMA Send buffers */
4d114fdd
JJ		 13213 /*
13214 * These are not normally read, and (presently) have no method
13215 * to be read, so are not pre-initialized
13216 */
77241056
MM		 13217
13218 /* RcvHdrAddr */
13219 /* RcvHdrTailAddr */
13220 /* RcvTidFlowTable */
13221 for (i = 0; i < dd->chip_rcv_contexts; i++) {
13222 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0);
13223 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0);
13224 for (j = 0; j < RXE_NUM_TID_FLOWS; j++)
8638b77f 13225 write_uctxt_csr(dd, i, RCV_TID_FLOW_TABLE + (8 * j), 0);
77241056
MM		 13226 }
13227
13228 /* RcvArray */
13229 for (i = 0; i < dd->chip_rcv_array_count; i++)
8638b77f 13230 write_csr(dd, RCV_ARRAY + (8 * i),
17fb4f29 13231 RCV_ARRAY_RT_WRITE_ENABLE_SMASK);
77241056
MM		 13232
13233 /* RcvQPMapTable */
13234 for (i = 0; i < 32; i++)
13235 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
13236}
13237
13238/*
13239 * Use the ctrl_bits in CceCtrl to clear the status_bits in CceStatus.
13240 */
13241static void clear_cce_status(struct hfi1_devdata *dd, u64 status_bits,
13242 u64 ctrl_bits)
13243{
13244 unsigned long timeout;
13245 u64 reg;
13246
13247 /* is the condition present? */
13248 reg = read_csr(dd, CCE_STATUS);
13249 if ((reg & status_bits) == 0)
13250 return;
13251
13252 /* clear the condition */
13253 write_csr(dd, CCE_CTRL, ctrl_bits);
13254
13255 /* wait for the condition to clear */
13256 timeout = jiffies + msecs_to_jiffies(CCE_STATUS_TIMEOUT);
13257 while (1) {
13258 reg = read_csr(dd, CCE_STATUS);
13259 if ((reg & status_bits) == 0)
13260 return;
13261 if (time_after(jiffies, timeout)) {
13262 dd_dev_err(dd,
17fb4f29
JJ		 13263 "Timeout waiting for CceStatus to clear bits 0x%llx, remaining 0x%llx\n",
13264 status_bits, reg & status_bits);
77241056
MM		 13265 return;
13266 }
13267 udelay(1);
13268 }
13269}
13270
13271/* set CCE CSRs to chip reset defaults */
13272static void reset_cce_csrs(struct hfi1_devdata *dd)
13273{
13274 int i;
13275
13276 /* CCE_REVISION read-only */
13277 /* CCE_REVISION2 read-only */
13278 /* CCE_CTRL - bits clear automatically */
13279 /* CCE_STATUS read-only, use CceCtrl to clear */
13280 clear_cce_status(dd, ALL_FROZE, CCE_CTRL_SPC_UNFREEZE_SMASK);
13281 clear_cce_status(dd, ALL_TXE_PAUSE, CCE_CTRL_TXE_RESUME_SMASK);
13282 clear_cce_status(dd, ALL_RXE_PAUSE, CCE_CTRL_RXE_RESUME_SMASK);
13283 for (i = 0; i < CCE_NUM_SCRATCH; i++)
13284 write_csr(dd, CCE_SCRATCH + (8 * i), 0);
13285 /* CCE_ERR_STATUS read-only */
13286 write_csr(dd, CCE_ERR_MASK, 0);
13287 write_csr(dd, CCE_ERR_CLEAR, ~0ull);
13288 /* CCE_ERR_FORCE leave alone */
13289 for (i = 0; i < CCE_NUM_32_BIT_COUNTERS; i++)
13290 write_csr(dd, CCE_COUNTER_ARRAY32 + (8 * i), 0);
13291 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_RESETCSR);
13292 /* CCE_PCIE_CTRL leave alone */
13293 for (i = 0; i < CCE_NUM_MSIX_VECTORS; i++) {
13294 write_csr(dd, CCE_MSIX_TABLE_LOWER + (8 * i), 0);
13295 write_csr(dd, CCE_MSIX_TABLE_UPPER + (8 * i),
17fb4f29 13296 CCE_MSIX_TABLE_UPPER_RESETCSR);
77241056
MM		 13297 }
13298 for (i = 0; i < CCE_NUM_MSIX_PBAS; i++) {
13299 /* CCE_MSIX_PBA read-only */
13300 write_csr(dd, CCE_MSIX_INT_GRANTED, ~0ull);
13301 write_csr(dd, CCE_MSIX_VEC_CLR_WITHOUT_INT, ~0ull);
13302 }
13303 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
13304 write_csr(dd, CCE_INT_MAP, 0);
13305 for (i = 0; i < CCE_NUM_INT_CSRS; i++) {
13306 /* CCE_INT_STATUS read-only */
13307 write_csr(dd, CCE_INT_MASK + (8 * i), 0);
13308 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~0ull);
13309 /* CCE_INT_FORCE leave alone */
13310 /* CCE_INT_BLOCKED read-only */
13311 }
13312 for (i = 0; i < CCE_NUM_32_BIT_INT_COUNTERS; i++)
13313 write_csr(dd, CCE_INT_COUNTER_ARRAY32 + (8 * i), 0);
13314}
13315
77241056
MM		 13316/* set MISC CSRs to chip reset defaults */
13317static void reset_misc_csrs(struct hfi1_devdata *dd)
13318{
13319 int i;
13320
13321 for (i = 0; i < 32; i++) {
13322 write_csr(dd, MISC_CFG_RSA_R2 + (8 * i), 0);
13323 write_csr(dd, MISC_CFG_RSA_SIGNATURE + (8 * i), 0);
13324 write_csr(dd, MISC_CFG_RSA_MODULUS + (8 * i), 0);
13325 }
4d114fdd
JJ		 13326 /*
13327 * MISC_CFG_SHA_PRELOAD leave alone - always reads 0 and can
13328 * only be written 128-byte chunks
13329 */
77241056
MM		 13330 /* init RSA engine to clear lingering errors */
13331 write_csr(dd, MISC_CFG_RSA_CMD, 1);
13332 write_csr(dd, MISC_CFG_RSA_MU, 0);
13333 write_csr(dd, MISC_CFG_FW_CTRL, 0);
13334 /* MISC_STS_8051_DIGEST read-only */
13335 /* MISC_STS_SBM_DIGEST read-only */
13336 /* MISC_STS_PCIE_DIGEST read-only */
13337 /* MISC_STS_FAB_DIGEST read-only */
13338 /* MISC_ERR_STATUS read-only */
13339 write_csr(dd, MISC_ERR_MASK, 0);
13340 write_csr(dd, MISC_ERR_CLEAR, ~0ull);
13341 /* MISC_ERR_FORCE leave alone */
13342}
13343
13344/* set TXE CSRs to chip reset defaults */
13345static void reset_txe_csrs(struct hfi1_devdata *dd)
13346{
13347 int i;
13348
13349 /*
13350 * TXE Kernel CSRs
13351 */
13352 write_csr(dd, SEND_CTRL, 0);
13353 __cm_reset(dd, 0); /* reset CM internal state */
13354 /* SEND_CONTEXTS read-only */
13355 /* SEND_DMA_ENGINES read-only */
13356 /* SEND_PIO_MEM_SIZE read-only */
13357 /* SEND_DMA_MEM_SIZE read-only */
13358 write_csr(dd, SEND_HIGH_PRIORITY_LIMIT, 0);
13359 pio_reset_all(dd); /* SEND_PIO_INIT_CTXT */
13360 /* SEND_PIO_ERR_STATUS read-only */
13361 write_csr(dd, SEND_PIO_ERR_MASK, 0);
13362 write_csr(dd, SEND_PIO_ERR_CLEAR, ~0ull);
13363 /* SEND_PIO_ERR_FORCE leave alone */
13364 /* SEND_DMA_ERR_STATUS read-only */
13365 write_csr(dd, SEND_DMA_ERR_MASK, 0);
13366 write_csr(dd, SEND_DMA_ERR_CLEAR, ~0ull);
13367 /* SEND_DMA_ERR_FORCE leave alone */
13368 /* SEND_EGRESS_ERR_STATUS read-only */
13369 write_csr(dd, SEND_EGRESS_ERR_MASK, 0);
13370 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~0ull);
13371 /* SEND_EGRESS_ERR_FORCE leave alone */
13372 write_csr(dd, SEND_BTH_QP, 0);
13373 write_csr(dd, SEND_STATIC_RATE_CONTROL, 0);
13374 write_csr(dd, SEND_SC2VLT0, 0);
13375 write_csr(dd, SEND_SC2VLT1, 0);
13376 write_csr(dd, SEND_SC2VLT2, 0);
13377 write_csr(dd, SEND_SC2VLT3, 0);
13378 write_csr(dd, SEND_LEN_CHECK0, 0);
13379 write_csr(dd, SEND_LEN_CHECK1, 0);
13380 /* SEND_ERR_STATUS read-only */
13381 write_csr(dd, SEND_ERR_MASK, 0);
13382 write_csr(dd, SEND_ERR_CLEAR, ~0ull);
13383 /* SEND_ERR_FORCE read-only */
13384 for (i = 0; i < VL_ARB_LOW_PRIO_TABLE_SIZE; i++)
8638b77f 13385 write_csr(dd, SEND_LOW_PRIORITY_LIST + (8 * i), 0);
77241056 13386 for (i = 0; i < VL_ARB_HIGH_PRIO_TABLE_SIZE; i++)
8638b77f
JJ		 13387 write_csr(dd, SEND_HIGH_PRIORITY_LIST + (8 * i), 0);
13388 for (i = 0; i < dd->chip_send_contexts / NUM_CONTEXTS_PER_SET; i++)
13389 write_csr(dd, SEND_CONTEXT_SET_CTRL + (8 * i), 0);
77241056 13390 for (i = 0; i < TXE_NUM_32_BIT_COUNTER; i++)
8638b77f 13391 write_csr(dd, SEND_COUNTER_ARRAY32 + (8 * i), 0);
77241056 13392 for (i = 0; i < TXE_NUM_64_BIT_COUNTER; i++)
8638b77f 13393 write_csr(dd, SEND_COUNTER_ARRAY64 + (8 * i), 0);
77241056 13394 write_csr(dd, SEND_CM_CTRL, SEND_CM_CTRL_RESETCSR);
17fb4f29 13395 write_csr(dd, SEND_CM_GLOBAL_CREDIT, SEND_CM_GLOBAL_CREDIT_RESETCSR);
77241056
MM		 13396 /* SEND_CM_CREDIT_USED_STATUS read-only */
13397 write_csr(dd, SEND_CM_TIMER_CTRL, 0);
13398 write_csr(dd, SEND_CM_LOCAL_AU_TABLE0_TO3, 0);
13399 write_csr(dd, SEND_CM_LOCAL_AU_TABLE4_TO7, 0);
13400 write_csr(dd, SEND_CM_REMOTE_AU_TABLE0_TO3, 0);
13401 write_csr(dd, SEND_CM_REMOTE_AU_TABLE4_TO7, 0);
13402 for (i = 0; i < TXE_NUM_DATA_VL; i++)
8638b77f 13403 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
77241056
MM		 13404 write_csr(dd, SEND_CM_CREDIT_VL15, 0);
13405 /* SEND_CM_CREDIT_USED_VL read-only */
13406 /* SEND_CM_CREDIT_USED_VL15 read-only */
13407 /* SEND_EGRESS_CTXT_STATUS read-only */
13408 /* SEND_EGRESS_SEND_DMA_STATUS read-only */
13409 write_csr(dd, SEND_EGRESS_ERR_INFO, ~0ull);
13410 /* SEND_EGRESS_ERR_INFO read-only */
13411 /* SEND_EGRESS_ERR_SOURCE read-only */
13412
13413 /*
13414 * TXE Per-Context CSRs
13415 */
13416 for (i = 0; i < dd->chip_send_contexts; i++) {
13417 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0);
13418 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_CTRL, 0);
13419 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0);
13420 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_FORCE, 0);
13421 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, 0);
13422 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~0ull);
13423 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_ENABLE, 0);
13424 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_VL, 0);
13425 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_JOB_KEY, 0);
13426 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_PARTITION_KEY, 0);
13427 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, 0);
13428 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_OPCODE, 0);
13429 }
13430
13431 /*
13432 * TXE Per-SDMA CSRs
13433 */
13434 for (i = 0; i < dd->chip_sdma_engines; i++) {
13435 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0);
13436 /* SEND_DMA_STATUS read-only */
13437 write_kctxt_csr(dd, i, SEND_DMA_BASE_ADDR, 0);
13438 write_kctxt_csr(dd, i, SEND_DMA_LEN_GEN, 0);
13439 write_kctxt_csr(dd, i, SEND_DMA_TAIL, 0);
13440 /* SEND_DMA_HEAD read-only */
13441 write_kctxt_csr(dd, i, SEND_DMA_HEAD_ADDR, 0);
13442 write_kctxt_csr(dd, i, SEND_DMA_PRIORITY_THLD, 0);
13443 /* SEND_DMA_IDLE_CNT read-only */
13444 write_kctxt_csr(dd, i, SEND_DMA_RELOAD_CNT, 0);
13445 write_kctxt_csr(dd, i, SEND_DMA_DESC_CNT, 0);
13446 /* SEND_DMA_DESC_FETCHED_CNT read-only */
13447 /* SEND_DMA_ENG_ERR_STATUS read-only */
13448 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, 0);
13449 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~0ull);
13450 /* SEND_DMA_ENG_ERR_FORCE leave alone */
13451 write_kctxt_csr(dd, i, SEND_DMA_CHECK_ENABLE, 0);
13452 write_kctxt_csr(dd, i, SEND_DMA_CHECK_VL, 0);
13453 write_kctxt_csr(dd, i, SEND_DMA_CHECK_JOB_KEY, 0);
13454 write_kctxt_csr(dd, i, SEND_DMA_CHECK_PARTITION_KEY, 0);
13455 write_kctxt_csr(dd, i, SEND_DMA_CHECK_SLID, 0);
13456 write_kctxt_csr(dd, i, SEND_DMA_CHECK_OPCODE, 0);
13457 write_kctxt_csr(dd, i, SEND_DMA_MEMORY, 0);
13458 }
13459}
13460
13461/*
13462 * Expect on entry:
13463 * o Packet ingress is disabled, i.e. RcvCtrl.RcvPortEnable == 0
13464 */
13465static void init_rbufs(struct hfi1_devdata *dd)
13466{
13467 u64 reg;
13468 int count;
13469
13470 /*
13471 * Wait for DMA to stop: RxRbufPktPending and RxPktInProgress are
13472 * clear.
13473 */
13474 count = 0;
13475 while (1) {
13476 reg = read_csr(dd, RCV_STATUS);
13477 if ((reg & (RCV_STATUS_RX_RBUF_PKT_PENDING_SMASK
13478 | RCV_STATUS_RX_PKT_IN_PROGRESS_SMASK)) == 0)
13479 break;
13480 /*
13481 * Give up after 1ms - maximum wait time.
13482 *
e8a70af2 13483 * RBuf size is 136KiB. Slowest possible is PCIe Gen1 x1 at
77241056 13484 * 250MB/s bandwidth. Lower rate to 66% for overhead to get:
e8a70af2 13485 * 136 KB / (66% * 250MB/s) = 844us
77241056
MM		 13486 */
13487 if (count++ > 500) {
13488 dd_dev_err(dd,
17fb4f29
JJ		 13489 "%s: in-progress DMA not clearing: RcvStatus 0x%llx, continuing\n",
13490 __func__, reg);
77241056
MM		 13491 break;
13492 }
13493 udelay(2); /* do not busy-wait the CSR */
13494 }
13495
13496 /* start the init - expect RcvCtrl to be 0 */
13497 write_csr(dd, RCV_CTRL, RCV_CTRL_RX_RBUF_INIT_SMASK);
13498
13499 /*
13500 * Read to force the write of Rcvtrl.RxRbufInit. There is a brief
13501 * period after the write before RcvStatus.RxRbufInitDone is valid.
13502 * The delay in the first run through the loop below is sufficient and
13503 * required before the first read of RcvStatus.RxRbufInintDone.
13504 */
13505 read_csr(dd, RCV_CTRL);
13506
13507 /* wait for the init to finish */
13508 count = 0;
13509 while (1) {
13510 /* delay is required first time through - see above */
13511 udelay(2); /* do not busy-wait the CSR */
13512 reg = read_csr(dd, RCV_STATUS);
13513 if (reg & (RCV_STATUS_RX_RBUF_INIT_DONE_SMASK))
13514 break;
13515
13516 /* give up after 100us - slowest possible at 33MHz is 73us */
13517 if (count++ > 50) {
13518 dd_dev_err(dd,
17fb4f29
JJ		 13519 "%s: RcvStatus.RxRbufInit not set, continuing\n",
13520 __func__);
77241056
MM		 13521 break;
13522 }
13523 }
13524}
13525
13526/* set RXE CSRs to chip reset defaults */
13527static void reset_rxe_csrs(struct hfi1_devdata *dd)
13528{
13529 int i, j;
13530
13531 /*
13532 * RXE Kernel CSRs
13533 */
13534 write_csr(dd, RCV_CTRL, 0);
13535 init_rbufs(dd);
13536 /* RCV_STATUS read-only */
13537 /* RCV_CONTEXTS read-only */
13538 /* RCV_ARRAY_CNT read-only */
13539 /* RCV_BUF_SIZE read-only */
13540 write_csr(dd, RCV_BTH_QP, 0);
13541 write_csr(dd, RCV_MULTICAST, 0);
13542 write_csr(dd, RCV_BYPASS, 0);
13543 write_csr(dd, RCV_VL15, 0);
13544 /* this is a clear-down */
13545 write_csr(dd, RCV_ERR_INFO,
17fb4f29 13546 RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SMASK);
77241056
MM		 13547 /* RCV_ERR_STATUS read-only */
13548 write_csr(dd, RCV_ERR_MASK, 0);
13549 write_csr(dd, RCV_ERR_CLEAR, ~0ull);
13550 /* RCV_ERR_FORCE leave alone */
13551 for (i = 0; i < 32; i++)
13552 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
13553 for (i = 0; i < 4; i++)
13554 write_csr(dd, RCV_PARTITION_KEY + (8 * i), 0);
13555 for (i = 0; i < RXE_NUM_32_BIT_COUNTERS; i++)
13556 write_csr(dd, RCV_COUNTER_ARRAY32 + (8 * i), 0);
13557 for (i = 0; i < RXE_NUM_64_BIT_COUNTERS; i++)
13558 write_csr(dd, RCV_COUNTER_ARRAY64 + (8 * i), 0);
13559 for (i = 0; i < RXE_NUM_RSM_INSTANCES; i++) {
13560 write_csr(dd, RCV_RSM_CFG + (8 * i), 0);
13561 write_csr(dd, RCV_RSM_SELECT + (8 * i), 0);
13562 write_csr(dd, RCV_RSM_MATCH + (8 * i), 0);
13563 }
13564 for (i = 0; i < 32; i++)
13565 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), 0);
13566
13567 /*
13568 * RXE Kernel and User Per-Context CSRs
13569 */
13570 for (i = 0; i < dd->chip_rcv_contexts; i++) {
13571 /* kernel */
13572 write_kctxt_csr(dd, i, RCV_CTXT_CTRL, 0);
13573 /* RCV_CTXT_STATUS read-only */
13574 write_kctxt_csr(dd, i, RCV_EGR_CTRL, 0);
13575 write_kctxt_csr(dd, i, RCV_TID_CTRL, 0);
13576 write_kctxt_csr(dd, i, RCV_KEY_CTRL, 0);
13577 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0);
13578 write_kctxt_csr(dd, i, RCV_HDR_CNT, 0);
13579 write_kctxt_csr(dd, i, RCV_HDR_ENT_SIZE, 0);
13580 write_kctxt_csr(dd, i, RCV_HDR_SIZE, 0);
13581 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0);
13582 write_kctxt_csr(dd, i, RCV_AVAIL_TIME_OUT, 0);
13583 write_kctxt_csr(dd, i, RCV_HDR_OVFL_CNT, 0);
13584
13585 /* user */
13586 /* RCV_HDR_TAIL read-only */
13587 write_uctxt_csr(dd, i, RCV_HDR_HEAD, 0);
13588 /* RCV_EGR_INDEX_TAIL read-only */
13589 write_uctxt_csr(dd, i, RCV_EGR_INDEX_HEAD, 0);
13590 /* RCV_EGR_OFFSET_TAIL read-only */
13591 for (j = 0; j < RXE_NUM_TID_FLOWS; j++) {
17fb4f29
JJ		 13592 write_uctxt_csr(dd, i,
13593 RCV_TID_FLOW_TABLE + (8 * j), 0);
77241056
MM		 13594 }
13595 }
13596}
13597
13598/*
13599 * Set sc2vl tables.
13600 *
13601 * They power on to zeros, so to avoid send context errors
13602 * they need to be set:
13603 *
13604 * SC 0-7 -> VL 0-7 (respectively)
13605 * SC 15 -> VL 15
13606 * otherwise
13607 * -> VL 0
13608 */
13609static void init_sc2vl_tables(struct hfi1_devdata *dd)
13610{
13611 int i;
13612 /* init per architecture spec, constrained by hardware capability */
13613
13614 /* HFI maps sent packets */
13615 write_csr(dd, SEND_SC2VLT0, SC2VL_VAL(
13616 0,
13617 0, 0, 1, 1,
13618 2, 2, 3, 3,
13619 4, 4, 5, 5,
13620 6, 6, 7, 7));
13621 write_csr(dd, SEND_SC2VLT1, SC2VL_VAL(
13622 1,
13623 8, 0, 9, 0,
13624 10, 0, 11, 0,
13625 12, 0, 13, 0,
13626 14, 0, 15, 15));
13627 write_csr(dd, SEND_SC2VLT2, SC2VL_VAL(
13628 2,
13629 16, 0, 17, 0,
13630 18, 0, 19, 0,
13631 20, 0, 21, 0,
13632 22, 0, 23, 0));
13633 write_csr(dd, SEND_SC2VLT3, SC2VL_VAL(
13634 3,
13635 24, 0, 25, 0,
13636 26, 0, 27, 0,
13637 28, 0, 29, 0,
13638 30, 0, 31, 0));
13639
13640 /* DC maps received packets */
13641 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, DC_SC_VL_VAL(
13642 15_0,
13643 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
13644 8, 0, 9, 0, 10, 0, 11, 0, 12, 0, 13, 0, 14, 0, 15, 15));
13645 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, DC_SC_VL_VAL(
13646 31_16,
13647 16, 0, 17, 0, 18, 0, 19, 0, 20, 0, 21, 0, 22, 0, 23, 0,
13648 24, 0, 25, 0, 26, 0, 27, 0, 28, 0, 29, 0, 30, 0, 31, 0));
13649
13650 /* initialize the cached sc2vl values consistently with h/w */
13651 for (i = 0; i < 32; i++) {
13652 if (i < 8 || i == 15)
13653 *((u8 *)(dd->sc2vl) + i) = (u8)i;
13654 else
13655 *((u8 *)(dd->sc2vl) + i) = 0;
13656 }
13657}
13658
13659/*
13660 * Read chip sizes and then reset parts to sane, disabled, values. We cannot
13661 * depend on the chip going through a power-on reset - a driver may be loaded
13662 * and unloaded many times.
13663 *
13664 * Do not write any CSR values to the chip in this routine - there may be
13665 * a reset following the (possible) FLR in this routine.
13666 *
13667 */
13668static void init_chip(struct hfi1_devdata *dd)
13669{
13670 int i;
13671
13672 /*
13673 * Put the HFI CSRs in a known state.
13674 * Combine this with a DC reset.
13675 *
13676 * Stop the device from doing anything while we do a
13677 * reset. We know there are no other active users of
13678 * the device since we are now in charge. Turn off
13679 * off all outbound and inbound traffic and make sure
13680 * the device does not generate any interrupts.
13681 */
13682
13683 /* disable send contexts and SDMA engines */
13684 write_csr(dd, SEND_CTRL, 0);
13685 for (i = 0; i < dd->chip_send_contexts; i++)
13686 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0);
13687 for (i = 0; i < dd->chip_sdma_engines; i++)
13688 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0);
13689 /* disable port (turn off RXE inbound traffic) and contexts */
13690 write_csr(dd, RCV_CTRL, 0);
13691 for (i = 0; i < dd->chip_rcv_contexts; i++)
13692 write_csr(dd, RCV_CTXT_CTRL, 0);
13693 /* mask all interrupt sources */
13694 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
8638b77f 13695 write_csr(dd, CCE_INT_MASK + (8 * i), 0ull);
77241056
MM		 13696
13697 /*
13698 * DC Reset: do a full DC reset before the register clear.
13699 * A recommended length of time to hold is one CSR read,
13700 * so reread the CceDcCtrl. Then, hold the DC in reset
13701 * across the clear.
13702 */
13703 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK);
50e5dcbe 13704 (void)read_csr(dd, CCE_DC_CTRL);
77241056
MM		 13705
13706 if (use_flr) {
13707 /*
13708 * A FLR will reset the SPC core and part of the PCIe.
13709 * The parts that need to be restored have already been
13710 * saved.
13711 */
13712 dd_dev_info(dd, "Resetting CSRs with FLR\n");
13713
13714 /* do the FLR, the DC reset will remain */
13715 hfi1_pcie_flr(dd);
13716
13717 /* restore command and BARs */
13718 restore_pci_variables(dd);
13719
995deafa 13720 if (is_ax(dd)) {
77241056
MM		 13721 dd_dev_info(dd, "Resetting CSRs with FLR\n");
13722 hfi1_pcie_flr(dd);
13723 restore_pci_variables(dd);
13724 }
77241056
MM		 13725 } else {
13726 dd_dev_info(dd, "Resetting CSRs with writes\n");
13727 reset_cce_csrs(dd);
13728 reset_txe_csrs(dd);
13729 reset_rxe_csrs(dd);
77241056
MM		 13730 reset_misc_csrs(dd);
13731 }
13732 /* clear the DC reset */
13733 write_csr(dd, CCE_DC_CTRL, 0);
7c03ed85 13734
77241056 13735 /* Set the LED off */
773d0451
SS		 13736 setextled(dd, 0);
13737
77241056
MM		 13738 /*
13739 * Clear the QSFP reset.
72a67ba2 13740 * An FLR enforces a 0 on all out pins. The driver does not touch
77241056 13741 * ASIC_QSFPn_OUT otherwise. This leaves RESET_N low and
72a67ba2 13742 * anything plugged constantly in reset, if it pays attention
77241056 13743 * to RESET_N.
72a67ba2 13744 * Prime examples of this are optical cables. Set all pins high.
77241056
MM		 13745 * I2CCLK and I2CDAT will change per direction, and INT_N and
13746 * MODPRS_N are input only and their value is ignored.
13747 */
72a67ba2
EH		 13748 write_csr(dd, ASIC_QSFP1_OUT, 0x1f);
13749 write_csr(dd, ASIC_QSFP2_OUT, 0x1f);
a2ee27a4 13750 init_chip_resources(dd);
77241056
MM		 13751}
13752
13753static void init_early_variables(struct hfi1_devdata *dd)
13754{
13755 int i;
13756
13757 /* assign link credit variables */
13758 dd->vau = CM_VAU;
13759 dd->link_credits = CM_GLOBAL_CREDITS;
995deafa 13760 if (is_ax(dd))
77241056
MM		 13761 dd->link_credits--;
13762 dd->vcu = cu_to_vcu(hfi1_cu);
13763 /* enough room for 8 MAD packets plus header - 17K */
13764 dd->vl15_init = (8 * (2048 + 128)) / vau_to_au(dd->vau);
13765 if (dd->vl15_init > dd->link_credits)
13766 dd->vl15_init = dd->link_credits;
13767
13768 write_uninitialized_csrs_and_memories(dd);
13769
13770 if (HFI1_CAP_IS_KSET(PKEY_CHECK))
13771 for (i = 0; i < dd->num_pports; i++) {
13772 struct hfi1_pportdata *ppd = &dd->pport[i];
13773
13774 set_partition_keys(ppd);
13775 }
13776 init_sc2vl_tables(dd);
13777}
13778
13779static void init_kdeth_qp(struct hfi1_devdata *dd)
13780{
13781 /* user changed the KDETH_QP */
13782 if (kdeth_qp != 0 && kdeth_qp >= 0xff) {
13783 /* out of range or illegal value */
13784 dd_dev_err(dd, "Invalid KDETH queue pair prefix, ignoring");
13785 kdeth_qp = 0;
13786 }
13787 if (kdeth_qp == 0) /* not set, or failed range check */
13788 kdeth_qp = DEFAULT_KDETH_QP;
13789
13790 write_csr(dd, SEND_BTH_QP,
17fb4f29
JJ		 13791 (kdeth_qp & SEND_BTH_QP_KDETH_QP_MASK) <<
13792 SEND_BTH_QP_KDETH_QP_SHIFT);
77241056
MM		 13793
13794 write_csr(dd, RCV_BTH_QP,
17fb4f29
JJ		 13795 (kdeth_qp & RCV_BTH_QP_KDETH_QP_MASK) <<
13796 RCV_BTH_QP_KDETH_QP_SHIFT);
77241056
MM		 13797}
13798
13799/**
13800 * init_qpmap_table
13801 * @dd - device data
13802 * @first_ctxt - first context
13803 * @last_ctxt - first context
13804 *
13805 * This return sets the qpn mapping table that
13806 * is indexed by qpn[8:1].
13807 *
13808 * The routine will round robin the 256 settings
13809 * from first_ctxt to last_ctxt.
13810 *
13811 * The first/last looks ahead to having specialized
13812 * receive contexts for mgmt and bypass. Normal
13813 * verbs traffic will assumed to be on a range
13814 * of receive contexts.
13815 */
13816static void init_qpmap_table(struct hfi1_devdata *dd,
13817 u32 first_ctxt,
13818 u32 last_ctxt)
13819{
13820 u64 reg = 0;
13821 u64 regno = RCV_QP_MAP_TABLE;
13822 int i;
13823 u64 ctxt = first_ctxt;
13824
60d585ad 13825 for (i = 0; i < 256; i++) {
77241056 13826 reg |= ctxt << (8 * (i % 8));
77241056
MM		 13827 ctxt++;
13828 if (ctxt > last_ctxt)
13829 ctxt = first_ctxt;
60d585ad 13830 if (i % 8 == 7) {
77241056
MM		 13831 write_csr(dd, regno, reg);
13832 reg = 0;
13833 regno += 8;
13834 }
13835 }
77241056
MM		 13836
13837 add_rcvctrl(dd, RCV_CTRL_RCV_QP_MAP_ENABLE_SMASK
13838 | RCV_CTRL_RCV_BYPASS_ENABLE_SMASK);
13839}
13840
372cc85a
DL		 13841struct rsm_map_table {
13842 u64 map[NUM_MAP_REGS];
13843 unsigned int used;
13844};
13845
b12349ae
DL		 13846struct rsm_rule_data {
13847 u8 offset;
13848 u8 pkt_type;
13849 u32 field1_off;
13850 u32 field2_off;
13851 u32 index1_off;
13852 u32 index1_width;
13853 u32 index2_off;
13854 u32 index2_width;
13855 u32 mask1;
13856 u32 value1;
13857 u32 mask2;
13858 u32 value2;
13859};
13860
372cc85a
DL		 13861/*
13862 * Return an initialized RMT map table for users to fill in. OK if it
13863 * returns NULL, indicating no table.
13864 */
13865static struct rsm_map_table *alloc_rsm_map_table(struct hfi1_devdata *dd)
13866{
13867 struct rsm_map_table *rmt;
13868 u8 rxcontext = is_ax(dd) ? 0 : 0xff; /* 0 is default if a0 ver. */
13869
13870 rmt = kmalloc(sizeof(*rmt), GFP_KERNEL);
13871 if (rmt) {
13872 memset(rmt->map, rxcontext, sizeof(rmt->map));
13873 rmt->used = 0;
13874 }
13875
13876 return rmt;
13877}
13878
13879/*
13880 * Write the final RMT map table to the chip and free the table. OK if
13881 * table is NULL.
13882 */
13883static void complete_rsm_map_table(struct hfi1_devdata *dd,
13884 struct rsm_map_table *rmt)
13885{
13886 int i;
13887
13888 if (rmt) {
13889 /* write table to chip */
13890 for (i = 0; i < NUM_MAP_REGS; i++)
13891 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), rmt->map[i]);
13892
13893 /* enable RSM */
13894 add_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK);
13895 }
13896}
13897
b12349ae
DL		 13898/*
13899 * Add a receive side mapping rule.
13900 */
13901static void add_rsm_rule(struct hfi1_devdata *dd, u8 rule_index,
13902 struct rsm_rule_data *rrd)
13903{
13904 write_csr(dd, RCV_RSM_CFG + (8 * rule_index),
13905 (u64)rrd->offset << RCV_RSM_CFG_OFFSET_SHIFT |
13906 1ull << rule_index | /* enable bit */
13907 (u64)rrd->pkt_type << RCV_RSM_CFG_PACKET_TYPE_SHIFT);
13908 write_csr(dd, RCV_RSM_SELECT + (8 * rule_index),
13909 (u64)rrd->field1_off << RCV_RSM_SELECT_FIELD1_OFFSET_SHIFT |
13910 (u64)rrd->field2_off << RCV_RSM_SELECT_FIELD2_OFFSET_SHIFT |
13911 (u64)rrd->index1_off << RCV_RSM_SELECT_INDEX1_OFFSET_SHIFT |
13912 (u64)rrd->index1_width << RCV_RSM_SELECT_INDEX1_WIDTH_SHIFT |
13913 (u64)rrd->index2_off << RCV_RSM_SELECT_INDEX2_OFFSET_SHIFT |
13914 (u64)rrd->index2_width << RCV_RSM_SELECT_INDEX2_WIDTH_SHIFT);
13915 write_csr(dd, RCV_RSM_MATCH + (8 * rule_index),
13916 (u64)rrd->mask1 << RCV_RSM_MATCH_MASK1_SHIFT |
13917 (u64)rrd->value1 << RCV_RSM_MATCH_VALUE1_SHIFT |
13918 (u64)rrd->mask2 << RCV_RSM_MATCH_MASK2_SHIFT |
13919 (u64)rrd->value2 << RCV_RSM_MATCH_VALUE2_SHIFT);
13920}
13921
4a818bed
DL		 13922/* return the number of RSM map table entries that will be used for QOS */
13923static int qos_rmt_entries(struct hfi1_devdata *dd, unsigned int *mp,
13924 unsigned int *np)
13925{
13926 int i;
13927 unsigned int m, n;
13928 u8 max_by_vl = 0;
13929
13930 /* is QOS active at all? */
13931 if (dd->n_krcv_queues <= MIN_KERNEL_KCTXTS ||
13932 num_vls == 1 ||
13933 krcvqsset <= 1)
13934 goto no_qos;
13935
13936 /* determine bits for qpn */
13937 for (i = 0; i < min_t(unsigned int, num_vls, krcvqsset); i++)
13938 if (krcvqs[i] > max_by_vl)
13939 max_by_vl = krcvqs[i];
13940 if (max_by_vl > 32)
13941 goto no_qos;
13942 m = ilog2(__roundup_pow_of_two(max_by_vl));
13943
13944 /* determine bits for vl */
13945 n = ilog2(__roundup_pow_of_two(num_vls));
13946
13947 /* reject if too much is used */
13948 if ((m + n) > 7)
13949 goto no_qos;
13950
13951 if (mp)
13952 *mp = m;
13953 if (np)
13954 *np = n;
13955
13956 return 1 << (m + n);
13957
13958no_qos:
13959 if (mp)
13960 *mp = 0;
13961 if (np)
13962 *np = 0;
13963 return 0;
13964}
13965
77241056
MM		 13966/**
13967 * init_qos - init RX qos
13968 * @dd - device data
372cc85a 13969 * @rmt - RSM map table
77241056 13970 *
33a9eb52
DL		 13971 * This routine initializes Rule 0 and the RSM map table to implement
13972 * quality of service (qos).
77241056 13973 *
33a9eb52
DL		 13974 * If all of the limit tests succeed, qos is applied based on the array
13975 * interpretation of krcvqs where entry 0 is VL0.
77241056 13976 *
33a9eb52
DL		 13977 * The number of vl bits (n) and the number of qpn bits (m) are computed to
13978 * feed both the RSM map table and the single rule.
77241056 13979 */
372cc85a 13980static void init_qos(struct hfi1_devdata *dd, struct rsm_map_table *rmt)
77241056 13981{
b12349ae 13982 struct rsm_rule_data rrd;
77241056 13983 unsigned qpns_per_vl, ctxt, i, qpn, n = 1, m;
372cc85a 13984 unsigned int rmt_entries;
77241056 13985 u64 reg;
77241056 13986
4a818bed 13987 if (!rmt)
77241056 13988 goto bail;
4a818bed
DL		 13989 rmt_entries = qos_rmt_entries(dd, &m, &n);
13990 if (rmt_entries == 0)
77241056 13991 goto bail;
4a818bed
DL		 13992 qpns_per_vl = 1 << m;
13993
372cc85a
DL		 13994 /* enough room in the map table? */
13995 rmt_entries = 1 << (m + n);
13996 if (rmt->used + rmt_entries >= NUM_MAP_ENTRIES)
859bcad9 13997 goto bail;
4a818bed 13998
372cc85a 13999 /* add qos entries to the the RSM map table */
33a9eb52 14000 for (i = 0, ctxt = FIRST_KERNEL_KCTXT; i < num_vls; i++) {
77241056
MM		 14001 unsigned tctxt;
14002
14003 for (qpn = 0, tctxt = ctxt;
14004 krcvqs[i] && qpn < qpns_per_vl; qpn++) {
14005 unsigned idx, regoff, regidx;
14006
372cc85a
DL		 14007 /* generate the index the hardware will produce */
14008 idx = rmt->used + ((qpn << n) ^ i);
77241056
MM		 14009 regoff = (idx % 8) * 8;
14010 regidx = idx / 8;
372cc85a
DL		 14011 /* replace default with context number */
14012 reg = rmt->map[regidx];
77241056
MM		 14013 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK
14014 << regoff);
14015 reg |= (u64)(tctxt++) << regoff;
372cc85a 14016 rmt->map[regidx] = reg;
77241056
MM		 14017 if (tctxt == ctxt + krcvqs[i])
14018 tctxt = ctxt;
14019 }
14020 ctxt += krcvqs[i];
14021 }
b12349ae
DL		 14022
14023 rrd.offset = rmt->used;
14024 rrd.pkt_type = 2;
14025 rrd.field1_off = LRH_BTH_MATCH_OFFSET;
14026 rrd.field2_off = LRH_SC_MATCH_OFFSET;
14027 rrd.index1_off = LRH_SC_SELECT_OFFSET;
14028 rrd.index1_width = n;
14029 rrd.index2_off = QPN_SELECT_OFFSET;
14030 rrd.index2_width = m + n;
14031 rrd.mask1 = LRH_BTH_MASK;
14032 rrd.value1 = LRH_BTH_VALUE;
14033 rrd.mask2 = LRH_SC_MASK;
14034 rrd.value2 = LRH_SC_VALUE;
14035
14036 /* add rule 0 */
14037 add_rsm_rule(dd, 0, &rrd);
14038
372cc85a
DL		 14039 /* mark RSM map entries as used */
14040 rmt->used += rmt_entries;
33a9eb52
DL		 14041 /* map everything else to the mcast/err/vl15 context */
14042 init_qpmap_table(dd, HFI1_CTRL_CTXT, HFI1_CTRL_CTXT);
77241056
MM		 14043 dd->qos_shift = n + 1;
14044 return;
14045bail:
14046 dd->qos_shift = 1;
82c2611d 14047 init_qpmap_table(dd, FIRST_KERNEL_KCTXT, dd->n_krcv_queues - 1);
77241056
MM		 14048}
14049
8f000f7f
DL		 14050static void init_user_fecn_handling(struct hfi1_devdata *dd,
14051 struct rsm_map_table *rmt)
14052{
14053 struct rsm_rule_data rrd;
14054 u64 reg;
14055 int i, idx, regoff, regidx;
14056 u8 offset;
14057
14058 /* there needs to be enough room in the map table */
14059 if (rmt->used + dd->num_user_contexts >= NUM_MAP_ENTRIES) {
14060 dd_dev_err(dd, "User FECN handling disabled - too many user contexts allocated\n");
14061 return;
14062 }
14063
14064 /*
14065 * RSM will extract the destination context as an index into the
14066 * map table. The destination contexts are a sequential block
14067 * in the range first_user_ctxt...num_rcv_contexts-1 (inclusive).
14068 * Map entries are accessed as offset + extracted value. Adjust
14069 * the added offset so this sequence can be placed anywhere in
14070 * the table - as long as the entries themselves do not wrap.
14071 * There are only enough bits in offset for the table size, so
14072 * start with that to allow for a "negative" offset.
14073 */
14074 offset = (u8)(NUM_MAP_ENTRIES + (int)rmt->used -
14075 (int)dd->first_user_ctxt);
14076
14077 for (i = dd->first_user_ctxt, idx = rmt->used;
14078 i < dd->num_rcv_contexts; i++, idx++) {
14079 /* replace with identity mapping */
14080 regoff = (idx % 8) * 8;
14081 regidx = idx / 8;
14082 reg = rmt->map[regidx];
14083 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK << regoff);
14084 reg |= (u64)i << regoff;
14085 rmt->map[regidx] = reg;
14086 }
14087
14088 /*
14089 * For RSM intercept of Expected FECN packets:
14090 * o packet type 0 - expected
14091 * o match on F (bit 95), using select/match 1, and
14092 * o match on SH (bit 133), using select/match 2.
14093 *
14094 * Use index 1 to extract the 8-bit receive context from DestQP
14095 * (start at bit 64). Use that as the RSM map table index.
14096 */
14097 rrd.offset = offset;
14098 rrd.pkt_type = 0;
14099 rrd.field1_off = 95;
14100 rrd.field2_off = 133;
14101 rrd.index1_off = 64;
14102 rrd.index1_width = 8;
14103 rrd.index2_off = 0;
14104 rrd.index2_width = 0;
14105 rrd.mask1 = 1;
14106 rrd.value1 = 1;
14107 rrd.mask2 = 1;
14108 rrd.value2 = 1;
14109
14110 /* add rule 1 */
14111 add_rsm_rule(dd, 1, &rrd);
14112
14113 rmt->used += dd->num_user_contexts;
14114}
14115
77241056
MM		 14116static void init_rxe(struct hfi1_devdata *dd)
14117{
372cc85a
DL		 14118 struct rsm_map_table *rmt;
14119
77241056
MM		 14120 /* enable all receive errors */
14121 write_csr(dd, RCV_ERR_MASK, ~0ull);
372cc85a
DL		 14122
14123 rmt = alloc_rsm_map_table(dd);
14124 /* set up QOS, including the QPN map table */
14125 init_qos(dd, rmt);
8f000f7f 14126 init_user_fecn_handling(dd, rmt);
372cc85a
DL		 14127 complete_rsm_map_table(dd, rmt);
14128 kfree(rmt);
14129
77241056
MM		 14130 /*
14131 * make sure RcvCtrl.RcvWcb <= PCIe Device Control
14132 * Register Max_Payload_Size (PCI_EXP_DEVCTL in Linux PCIe config
14133 * space, PciCfgCap2.MaxPayloadSize in HFI). There is only one
14134 * invalid configuration: RcvCtrl.RcvWcb set to its max of 256 and
14135 * Max_PayLoad_Size set to its minimum of 128.
14136 *
14137 * Presently, RcvCtrl.RcvWcb is not modified from its default of 0
14138 * (64 bytes). Max_Payload_Size is possibly modified upward in
14139 * tune_pcie_caps() which is called after this routine.
14140 */
14141}
14142
14143static void init_other(struct hfi1_devdata *dd)
14144{
14145 /* enable all CCE errors */
14146 write_csr(dd, CCE_ERR_MASK, ~0ull);
14147 /* enable *some* Misc errors */
14148 write_csr(dd, MISC_ERR_MASK, DRIVER_MISC_MASK);
14149 /* enable all DC errors, except LCB */
14150 write_csr(dd, DCC_ERR_FLG_EN, ~0ull);
14151 write_csr(dd, DC_DC8051_ERR_EN, ~0ull);
14152}
14153
14154/*
14155 * Fill out the given AU table using the given CU. A CU is defined in terms
14156 * AUs. The table is a an encoding: given the index, how many AUs does that
14157 * represent?
14158 *
14159 * NOTE: Assumes that the register layout is the same for the
14160 * local and remote tables.
14161 */
14162static void assign_cm_au_table(struct hfi1_devdata *dd, u32 cu,
14163 u32 csr0to3, u32 csr4to7)
14164{
14165 write_csr(dd, csr0to3,
17fb4f29
JJ		 14166 0ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE0_SHIFT |
14167 1ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE1_SHIFT |
14168 2ull * cu <<
14169 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE2_SHIFT |
14170 4ull * cu <<
14171 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE3_SHIFT);
77241056 14172 write_csr(dd, csr4to7,
17fb4f29
JJ		 14173 8ull * cu <<
14174 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE4_SHIFT |
14175 16ull * cu <<
14176 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE5_SHIFT |
14177 32ull * cu <<
14178 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE6_SHIFT |
14179 64ull * cu <<
14180 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE7_SHIFT);
77241056
MM		 14181}
14182
14183static void assign_local_cm_au_table(struct hfi1_devdata *dd, u8 vcu)
14184{
14185 assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_LOCAL_AU_TABLE0_TO3,
17fb4f29 14186 SEND_CM_LOCAL_AU_TABLE4_TO7);
77241056
MM		 14187}
14188
14189void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu)
14190{
14191 assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_REMOTE_AU_TABLE0_TO3,
17fb4f29 14192 SEND_CM_REMOTE_AU_TABLE4_TO7);
77241056
MM		 14193}
14194
14195static void init_txe(struct hfi1_devdata *dd)
14196{
14197 int i;
14198
14199 /* enable all PIO, SDMA, general, and Egress errors */
14200 write_csr(dd, SEND_PIO_ERR_MASK, ~0ull);
14201 write_csr(dd, SEND_DMA_ERR_MASK, ~0ull);
14202 write_csr(dd, SEND_ERR_MASK, ~0ull);
14203 write_csr(dd, SEND_EGRESS_ERR_MASK, ~0ull);
14204
14205 /* enable all per-context and per-SDMA engine errors */
14206 for (i = 0; i < dd->chip_send_contexts; i++)
14207 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, ~0ull);
14208 for (i = 0; i < dd->chip_sdma_engines; i++)
14209 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, ~0ull);
14210
14211 /* set the local CU to AU mapping */
14212 assign_local_cm_au_table(dd, dd->vcu);
14213
14214 /*
14215 * Set reasonable default for Credit Return Timer
14216 * Don't set on Simulator - causes it to choke.
14217 */
14218 if (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)
14219 write_csr(dd, SEND_CM_TIMER_CTRL, HFI1_CREDIT_RETURN_RATE);
14220}
14221
14222int hfi1_set_ctxt_jkey(struct hfi1_devdata *dd, unsigned ctxt, u16 jkey)
14223{
14224 struct hfi1_ctxtdata *rcd = dd->rcd[ctxt];
14225 unsigned sctxt;
14226 int ret = 0;
14227 u64 reg;
14228
14229 if (!rcd || !rcd->sc) {
14230 ret = -EINVAL;
14231 goto done;
14232 }
14233 sctxt = rcd->sc->hw_context;
14234 reg = SEND_CTXT_CHECK_JOB_KEY_MASK_SMASK | /* mask is always 1's */
14235 ((jkey & SEND_CTXT_CHECK_JOB_KEY_VALUE_MASK) <<
14236 SEND_CTXT_CHECK_JOB_KEY_VALUE_SHIFT);
14237 /* JOB_KEY_ALLOW_PERMISSIVE is not allowed by default */
14238 if (HFI1_CAP_KGET_MASK(rcd->flags, ALLOW_PERM_JKEY))
14239 reg |= SEND_CTXT_CHECK_JOB_KEY_ALLOW_PERMISSIVE_SMASK;
14240 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_JOB_KEY, reg);
14241 /*
14242 * Enable send-side J_KEY integrity check, unless this is A0 h/w
77241056 14243 */
995deafa 14244 if (!is_ax(dd)) {
77241056
MM		 14245 reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
14246 reg |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
14247 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
14248 }
14249
14250 /* Enable J_KEY check on receive context. */
14251 reg = RCV_KEY_CTRL_JOB_KEY_ENABLE_SMASK |
14252 ((jkey & RCV_KEY_CTRL_JOB_KEY_VALUE_MASK) <<
14253 RCV_KEY_CTRL_JOB_KEY_VALUE_SHIFT);
14254 write_kctxt_csr(dd, ctxt, RCV_KEY_CTRL, reg);
14255done:
14256 return ret;
14257}
14258
14259int hfi1_clear_ctxt_jkey(struct hfi1_devdata *dd, unsigned ctxt)
14260{
14261 struct hfi1_ctxtdata *rcd = dd->rcd[ctxt];
14262 unsigned sctxt;
14263 int ret = 0;
14264 u64 reg;
14265
14266 if (!rcd || !rcd->sc) {
14267 ret = -EINVAL;
14268 goto done;
14269 }
14270 sctxt = rcd->sc->hw_context;
14271 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_JOB_KEY, 0);
14272 /*
14273 * Disable send-side J_KEY integrity check, unless this is A0 h/w.
14274 * This check would not have been enabled for A0 h/w, see
14275 * set_ctxt_jkey().
14276 */
995deafa 14277 if (!is_ax(dd)) {
77241056
MM		 14278 reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
14279 reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
14280 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
14281 }
14282 /* Turn off the J_KEY on the receive side */
14283 write_kctxt_csr(dd, ctxt, RCV_KEY_CTRL, 0);
14284done:
14285 return ret;
14286}
14287
14288int hfi1_set_ctxt_pkey(struct hfi1_devdata *dd, unsigned ctxt, u16 pkey)
14289{
14290 struct hfi1_ctxtdata *rcd;
14291 unsigned sctxt;
14292 int ret = 0;
14293 u64 reg;
14294
e490974e 14295 if (ctxt < dd->num_rcv_contexts) {
77241056 14296 rcd = dd->rcd[ctxt];
e490974e 14297 } else {
77241056
MM		 14298 ret = -EINVAL;
14299 goto done;
14300 }
14301 if (!rcd || !rcd->sc) {
14302 ret = -EINVAL;
14303 goto done;
14304 }
14305 sctxt = rcd->sc->hw_context;
14306 reg = ((u64)pkey & SEND_CTXT_CHECK_PARTITION_KEY_VALUE_MASK) <<
14307 SEND_CTXT_CHECK_PARTITION_KEY_VALUE_SHIFT;
14308 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_PARTITION_KEY, reg);
14309 reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
14310 reg |= SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK;
e38d1e4f 14311 reg &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK;
77241056
MM		 14312 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
14313done:
14314 return ret;
14315}
14316
14317int hfi1_clear_ctxt_pkey(struct hfi1_devdata *dd, unsigned ctxt)
14318{
14319 struct hfi1_ctxtdata *rcd;
14320 unsigned sctxt;
14321 int ret = 0;
14322 u64 reg;
14323
e490974e 14324 if (ctxt < dd->num_rcv_contexts) {
77241056 14325 rcd = dd->rcd[ctxt];
e490974e 14326 } else {
77241056
MM		 14327 ret = -EINVAL;
14328 goto done;
14329 }
14330 if (!rcd || !rcd->sc) {
14331 ret = -EINVAL;
14332 goto done;
14333 }
14334 sctxt = rcd->sc->hw_context;
14335 reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
14336 reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK;
14337 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
14338 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_PARTITION_KEY, 0);
14339done:
14340 return ret;
14341}
14342
14343/*
14344 * Start doing the clean up the the chip. Our clean up happens in multiple
14345 * stages and this is just the first.
14346 */
14347void hfi1_start_cleanup(struct hfi1_devdata *dd)
14348{
affa48de 14349 aspm_exit(dd);
77241056
MM		 14350 free_cntrs(dd);
14351 free_rcverr(dd);
14352 clean_up_interrupts(dd);
a2ee27a4 14353 finish_chip_resources(dd);
77241056
MM		 14354}
14355
14356#define HFI_BASE_GUID(dev) \
14357 ((dev)->base_guid & ~(1ULL << GUID_HFI_INDEX_SHIFT))
14358
14359/*
78eb129d
DL		 14360 * Information can be shared between the two HFIs on the same ASIC
14361 * in the same OS. This function finds the peer device and sets
14362 * up a shared structure.
77241056 14363 */
78eb129d 14364static int init_asic_data(struct hfi1_devdata *dd)
77241056
MM		 14365{
14366 unsigned long flags;
14367 struct hfi1_devdata *tmp, *peer = NULL;
98f179a5 14368 struct hfi1_asic_data *asic_data;
78eb129d 14369 int ret = 0;
77241056 14370
98f179a5
TS		 14371 /* pre-allocate the asic structure in case we are the first device */
14372 asic_data = kzalloc(sizeof(*dd->asic_data), GFP_KERNEL);
14373 if (!asic_data)
14374 return -ENOMEM;
14375
77241056
MM		 14376 spin_lock_irqsave(&hfi1_devs_lock, flags);
14377 /* Find our peer device */
14378 list_for_each_entry(tmp, &hfi1_dev_list, list) {
14379 if ((HFI_BASE_GUID(dd) == HFI_BASE_GUID(tmp)) &&
14380 dd->unit != tmp->unit) {
14381 peer = tmp;
14382 break;
14383 }
14384 }
14385
78eb129d 14386 if (peer) {
98f179a5 14387 /* use already allocated structure */
78eb129d 14388 dd->asic_data = peer->asic_data;
98f179a5 14389 kfree(asic_data);
78eb129d 14390 } else {
98f179a5 14391 dd->asic_data = asic_data;
78eb129d
DL		 14392 mutex_init(&dd->asic_data->asic_resource_mutex);
14393 }
14394 dd->asic_data->dds[dd->hfi1_id] = dd; /* self back-pointer */
77241056 14395 spin_unlock_irqrestore(&hfi1_devs_lock, flags);
dba715f0
DL		 14396
14397 /* first one through - set up i2c devices */
14398 if (!peer)
14399 ret = set_up_i2c(dd, dd->asic_data);
14400
78eb129d 14401 return ret;
77241056
MM		 14402}
14403
5d9157aa
DL		 14404/*
14405 * Set dd->boardname. Use a generic name if a name is not returned from
14406 * EFI variable space.
14407 *
14408 * Return 0 on success, -ENOMEM if space could not be allocated.
14409 */
14410static int obtain_boardname(struct hfi1_devdata *dd)
14411{
14412 /* generic board description */
14413 const char generic[] =
14414 "Intel Omni-Path Host Fabric Interface Adapter 100 Series";
14415 unsigned long size;
14416 int ret;
14417
14418 ret = read_hfi1_efi_var(dd, "description", &size,
14419 (void **)&dd->boardname);
14420 if (ret) {
845f876d 14421 dd_dev_info(dd, "Board description not found\n");
5d9157aa
DL		 14422 /* use generic description */
14423 dd->boardname = kstrdup(generic, GFP_KERNEL);
14424 if (!dd->boardname)
14425 return -ENOMEM;
14426 }
14427 return 0;
14428}
14429
24487dd3
KW		 14430/*
14431 * Check the interrupt registers to make sure that they are mapped correctly.
14432 * It is intended to help user identify any mismapping by VMM when the driver
14433 * is running in a VM. This function should only be called before interrupt
14434 * is set up properly.
14435 *
14436 * Return 0 on success, -EINVAL on failure.
14437 */
14438static int check_int_registers(struct hfi1_devdata *dd)
14439{
14440 u64 reg;
14441 u64 all_bits = ~(u64)0;
14442 u64 mask;
14443
14444 /* Clear CceIntMask[0] to avoid raising any interrupts */
14445 mask = read_csr(dd, CCE_INT_MASK);
14446 write_csr(dd, CCE_INT_MASK, 0ull);
14447 reg = read_csr(dd, CCE_INT_MASK);
14448 if (reg)
14449 goto err_exit;
14450
14451 /* Clear all interrupt status bits */
14452 write_csr(dd, CCE_INT_CLEAR, all_bits);
14453 reg = read_csr(dd, CCE_INT_STATUS);
14454 if (reg)
14455 goto err_exit;
14456
14457 /* Set all interrupt status bits */
14458 write_csr(dd, CCE_INT_FORCE, all_bits);
14459 reg = read_csr(dd, CCE_INT_STATUS);
14460 if (reg != all_bits)
14461 goto err_exit;
14462
14463 /* Restore the interrupt mask */
14464 write_csr(dd, CCE_INT_CLEAR, all_bits);
14465 write_csr(dd, CCE_INT_MASK, mask);
14466
14467 return 0;
14468err_exit:
14469 write_csr(dd, CCE_INT_MASK, mask);
14470 dd_dev_err(dd, "Interrupt registers not properly mapped by VMM\n");
14471 return -EINVAL;
14472}
14473
77241056 14474/**
7c03ed85 14475 * Allocate and initialize the device structure for the hfi.
77241056
MM		 14476 * @dev: the pci_dev for hfi1_ib device
14477 * @ent: pci_device_id struct for this dev
14478 *
14479 * Also allocates, initializes, and returns the devdata struct for this
14480 * device instance
14481 *
14482 * This is global, and is called directly at init to set up the
14483 * chip-specific function pointers for later use.
14484 */
14485struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev,
14486 const struct pci_device_id *ent)
14487{
14488 struct hfi1_devdata *dd;
14489 struct hfi1_pportdata *ppd;
14490 u64 reg;
14491 int i, ret;
14492 static const char * const inames[] = { /* implementation names */
14493 "RTL silicon",
14494 "RTL VCS simulation",
14495 "RTL FPGA emulation",
14496 "Functional simulator"
14497 };
24487dd3 14498 struct pci_dev *parent = pdev->bus->self;
77241056 14499
17fb4f29
JJ		 14500 dd = hfi1_alloc_devdata(pdev, NUM_IB_PORTS *
14501 sizeof(struct hfi1_pportdata));
77241056
MM		 14502 if (IS_ERR(dd))
14503 goto bail;
14504 ppd = dd->pport;
14505 for (i = 0; i < dd->num_pports; i++, ppd++) {
14506 int vl;
14507 /* init common fields */
14508 hfi1_init_pportdata(pdev, ppd, dd, 0, 1);
14509 /* DC supports 4 link widths */
14510 ppd->link_width_supported =
14511 OPA_LINK_WIDTH_1X | OPA_LINK_WIDTH_2X |
14512 OPA_LINK_WIDTH_3X | OPA_LINK_WIDTH_4X;
14513 ppd->link_width_downgrade_supported =
14514 ppd->link_width_supported;
14515 /* start out enabling only 4X */
14516 ppd->link_width_enabled = OPA_LINK_WIDTH_4X;
14517 ppd->link_width_downgrade_enabled =
14518 ppd->link_width_downgrade_supported;
14519 /* link width active is 0 when link is down */
14520 /* link width downgrade active is 0 when link is down */
14521
d0d236ea
JJ		 14522 if (num_vls < HFI1_MIN_VLS_SUPPORTED ||
14523 num_vls > HFI1_MAX_VLS_SUPPORTED) {
77241056
MM		 14524 hfi1_early_err(&pdev->dev,
14525 "Invalid num_vls %u, using %u VLs\n",
14526 num_vls, HFI1_MAX_VLS_SUPPORTED);
14527 num_vls = HFI1_MAX_VLS_SUPPORTED;
14528 }
14529 ppd->vls_supported = num_vls;
14530 ppd->vls_operational = ppd->vls_supported;
8a4d3444 14531 ppd->actual_vls_operational = ppd->vls_supported;
77241056
MM		 14532 /* Set the default MTU. */
14533 for (vl = 0; vl < num_vls; vl++)
14534 dd->vld[vl].mtu = hfi1_max_mtu;
14535 dd->vld[15].mtu = MAX_MAD_PACKET;
14536 /*
14537 * Set the initial values to reasonable default, will be set
14538 * for real when link is up.
14539 */
14540 ppd->lstate = IB_PORT_DOWN;
14541 ppd->overrun_threshold = 0x4;
14542 ppd->phy_error_threshold = 0xf;
14543 ppd->port_crc_mode_enabled = link_crc_mask;
14544 /* initialize supported LTP CRC mode */
14545 ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8;
14546 /* initialize enabled LTP CRC mode */
14547 ppd->port_ltp_crc_mode |= cap_to_port_ltp(link_crc_mask) << 4;
14548 /* start in offline */
14549 ppd->host_link_state = HLS_DN_OFFLINE;
14550 init_vl_arb_caches(ppd);
f45c8dc8 14551 ppd->last_pstate = 0xff; /* invalid value */
77241056
MM		 14552 }
14553
14554 dd->link_default = HLS_DN_POLL;
14555
14556 /*
14557 * Do remaining PCIe setup and save PCIe values in dd.
14558 * Any error printing is already done by the init code.
14559 * On return, we have the chip mapped.
14560 */
26ea2544 14561 ret = hfi1_pcie_ddinit(dd, pdev);
77241056
MM		 14562 if (ret < 0)
14563 goto bail_free;
14564
14565 /* verify that reads actually work, save revision for reset check */
14566 dd->revision = read_csr(dd, CCE_REVISION);
14567 if (dd->revision == ~(u64)0) {
14568 dd_dev_err(dd, "cannot read chip CSRs\n");
14569 ret = -EINVAL;
14570 goto bail_cleanup;
14571 }
14572 dd->majrev = (dd->revision >> CCE_REVISION_CHIP_REV_MAJOR_SHIFT)
14573 & CCE_REVISION_CHIP_REV_MAJOR_MASK;
14574 dd->minrev = (dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT)
14575 & CCE_REVISION_CHIP_REV_MINOR_MASK;
14576
24487dd3
KW		 14577 /*
14578 * Check interrupt registers mapping if the driver has no access to
14579 * the upstream component. In this case, it is likely that the driver
14580 * is running in a VM.
14581 */
14582 if (!parent) {
14583 ret = check_int_registers(dd);
14584 if (ret)
14585 goto bail_cleanup;
14586 }
14587
4d114fdd
JJ		 14588 /*
14589 * obtain the hardware ID - NOT related to unit, which is a
14590 * software enumeration
14591 */
77241056
MM		 14592 reg = read_csr(dd, CCE_REVISION2);
14593 dd->hfi1_id = (reg >> CCE_REVISION2_HFI_ID_SHIFT)
14594 & CCE_REVISION2_HFI_ID_MASK;
14595 /* the variable size will remove unwanted bits */
14596 dd->icode = reg >> CCE_REVISION2_IMPL_CODE_SHIFT;
14597 dd->irev = reg >> CCE_REVISION2_IMPL_REVISION_SHIFT;
14598 dd_dev_info(dd, "Implementation: %s, revision 0x%x\n",
17fb4f29
JJ		 14599 dd->icode < ARRAY_SIZE(inames) ?
14600 inames[dd->icode] : "unknown", (int)dd->irev);
77241056
MM		 14601
14602 /* speeds the hardware can support */
14603 dd->pport->link_speed_supported = OPA_LINK_SPEED_25G;
14604 /* speeds allowed to run at */
14605 dd->pport->link_speed_enabled = dd->pport->link_speed_supported;
14606 /* give a reasonable active value, will be set on link up */
14607 dd->pport->link_speed_active = OPA_LINK_SPEED_25G;
14608
14609 dd->chip_rcv_contexts = read_csr(dd, RCV_CONTEXTS);
14610 dd->chip_send_contexts = read_csr(dd, SEND_CONTEXTS);
14611 dd->chip_sdma_engines = read_csr(dd, SEND_DMA_ENGINES);
14612 dd->chip_pio_mem_size = read_csr(dd, SEND_PIO_MEM_SIZE);
14613 dd->chip_sdma_mem_size = read_csr(dd, SEND_DMA_MEM_SIZE);
14614 /* fix up link widths for emulation _p */
14615 ppd = dd->pport;
14616 if (dd->icode == ICODE_FPGA_EMULATION && is_emulator_p(dd)) {
14617 ppd->link_width_supported =
14618 ppd->link_width_enabled =
14619 ppd->link_width_downgrade_supported =
14620 ppd->link_width_downgrade_enabled =
14621 OPA_LINK_WIDTH_1X;
14622 }
14623 /* insure num_vls isn't larger than number of sdma engines */
14624 if (HFI1_CAP_IS_KSET(SDMA) && num_vls > dd->chip_sdma_engines) {
14625 dd_dev_err(dd, "num_vls %u too large, using %u VLs\n",
11a5909b
DL		 14626 num_vls, dd->chip_sdma_engines);
14627 num_vls = dd->chip_sdma_engines;
14628 ppd->vls_supported = dd->chip_sdma_engines;
8a4d3444 14629 ppd->vls_operational = ppd->vls_supported;
77241056
MM		 14630 }
14631
14632 /*
14633 * Convert the ns parameter to the 64 * cclocks used in the CSR.
14634 * Limit the max if larger than the field holds. If timeout is
14635 * non-zero, then the calculated field will be at least 1.
14636 *
14637 * Must be after icode is set up - the cclock rate depends
14638 * on knowing the hardware being used.
14639 */
14640 dd->rcv_intr_timeout_csr = ns_to_cclock(dd, rcv_intr_timeout) / 64;
14641 if (dd->rcv_intr_timeout_csr >
14642 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK)
14643 dd->rcv_intr_timeout_csr =
14644 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK;
14645 else if (dd->rcv_intr_timeout_csr == 0 && rcv_intr_timeout)
14646 dd->rcv_intr_timeout_csr = 1;
14647
7c03ed85
EH		 14648 /* needs to be done before we look for the peer device */
14649 read_guid(dd);
14650
78eb129d
DL		 14651 /* set up shared ASIC data with peer device */
14652 ret = init_asic_data(dd);
14653 if (ret)
14654 goto bail_cleanup;
7c03ed85 14655
77241056
MM		 14656 /* obtain chip sizes, reset chip CSRs */
14657 init_chip(dd);
14658
14659 /* read in the PCIe link speed information */
14660 ret = pcie_speeds(dd);
14661 if (ret)
14662 goto bail_cleanup;
14663
e83eba21
DL		 14664 /* call before get_platform_config(), after init_chip_resources() */
14665 ret = eprom_init(dd);
14666 if (ret)
14667 goto bail_free_rcverr;
14668
c3838b39
EH		 14669 /* Needs to be called before hfi1_firmware_init */
14670 get_platform_config(dd);
14671
77241056
MM		 14672 /* read in firmware */
14673 ret = hfi1_firmware_init(dd);
14674 if (ret)
14675 goto bail_cleanup;
14676
14677 /*
14678 * In general, the PCIe Gen3 transition must occur after the
14679 * chip has been idled (so it won't initiate any PCIe transactions
14680 * e.g. an interrupt) and before the driver changes any registers
14681 * (the transition will reset the registers).
14682 *
14683 * In particular, place this call after:
14684 * - init_chip() - the chip will not initiate any PCIe transactions
14685 * - pcie_speeds() - reads the current link speed
14686 * - hfi1_firmware_init() - the needed firmware is ready to be
14687 * downloaded
14688 */
14689 ret = do_pcie_gen3_transition(dd);
14690 if (ret)
14691 goto bail_cleanup;
14692
14693 /* start setting dd values and adjusting CSRs */
14694 init_early_variables(dd);
14695
14696 parse_platform_config(dd);
14697
5d9157aa
DL		 14698 ret = obtain_boardname(dd);
14699 if (ret)
77241056 14700 goto bail_cleanup;
77241056
MM		 14701
14702 snprintf(dd->boardversion, BOARD_VERS_MAX,
5d9157aa 14703 "ChipABI %u.%u, ChipRev %u.%u, SW Compat %llu\n",
77241056 14704 HFI1_CHIP_VERS_MAJ, HFI1_CHIP_VERS_MIN,
77241056
MM		 14705 (u32)dd->majrev,
14706 (u32)dd->minrev,
14707 (dd->revision >> CCE_REVISION_SW_SHIFT)
14708 & CCE_REVISION_SW_MASK);
14709
14710 ret = set_up_context_variables(dd);
14711 if (ret)
14712 goto bail_cleanup;
14713
14714 /* set initial RXE CSRs */
14715 init_rxe(dd);
14716 /* set initial TXE CSRs */
14717 init_txe(dd);
14718 /* set initial non-RXE, non-TXE CSRs */
14719 init_other(dd);
14720 /* set up KDETH QP prefix in both RX and TX CSRs */
14721 init_kdeth_qp(dd);
14722
4197344b
DD		 14723 ret = hfi1_dev_affinity_init(dd);
14724 if (ret)
14725 goto bail_cleanup;
957558c9 14726
77241056
MM		 14727 /* send contexts must be set up before receive contexts */
14728 ret = init_send_contexts(dd);
14729 if (ret)
14730 goto bail_cleanup;
14731
14732 ret = hfi1_create_ctxts(dd);
14733 if (ret)
14734 goto bail_cleanup;
14735
14736 dd->rcvhdrsize = DEFAULT_RCVHDRSIZE;
14737 /*
14738 * rcd[0] is guaranteed to be valid by this point. Also, all
14739 * context are using the same value, as per the module parameter.
14740 */
14741 dd->rhf_offset = dd->rcd[0]->rcvhdrqentsize - sizeof(u64) / sizeof(u32);
14742
14743 ret = init_pervl_scs(dd);
14744 if (ret)
14745 goto bail_cleanup;
14746
14747 /* sdma init */
14748 for (i = 0; i < dd->num_pports; ++i) {
14749 ret = sdma_init(dd, i);
14750 if (ret)
14751 goto bail_cleanup;
14752 }
14753
14754 /* use contexts created by hfi1_create_ctxts */
14755 ret = set_up_interrupts(dd);
14756 if (ret)
14757 goto bail_cleanup;
14758
14759 /* set up LCB access - must be after set_up_interrupts() */
14760 init_lcb_access(dd);
14761
fc0b76c0
IW		 14762 /*
14763 * Serial number is created from the base guid:
14764 * [27:24] = base guid [38:35]
14765 * [23: 0] = base guid [23: 0]
14766 */
77241056 14767 snprintf(dd->serial, SERIAL_MAX, "0x%08llx\n",
fc0b76c0
IW		 14768 (dd->base_guid & 0xFFFFFF) |
14769 ((dd->base_guid >> 11) & 0xF000000));
77241056
MM		 14770
14771 dd->oui1 = dd->base_guid >> 56 & 0xFF;
14772 dd->oui2 = dd->base_guid >> 48 & 0xFF;
14773 dd->oui3 = dd->base_guid >> 40 & 0xFF;
14774
14775 ret = load_firmware(dd); /* asymmetric with dispose_firmware() */
14776 if (ret)
14777 goto bail_clear_intr;
77241056
MM		 14778
14779 thermal_init(dd);
14780
14781 ret = init_cntrs(dd);
14782 if (ret)
14783 goto bail_clear_intr;
14784
14785 ret = init_rcverr(dd);
14786 if (ret)
14787 goto bail_free_cntrs;
14788
acd7c8fe
TS		 14789 init_completion(&dd->user_comp);
14790
14791 /* The user refcount starts with one to inidicate an active device */
14792 atomic_set(&dd->user_refcount, 1);
14793
77241056
MM		 14794 goto bail;
14795
14796bail_free_rcverr:
14797 free_rcverr(dd);
14798bail_free_cntrs:
14799 free_cntrs(dd);
14800bail_clear_intr:
14801 clean_up_interrupts(dd);
14802bail_cleanup:
14803 hfi1_pcie_ddcleanup(dd);
14804bail_free:
14805 hfi1_free_devdata(dd);
14806 dd = ERR_PTR(ret);
14807bail:
14808 return dd;
14809}
14810
14811static u16 delay_cycles(struct hfi1_pportdata *ppd, u32 desired_egress_rate,
14812 u32 dw_len)
14813{
14814 u32 delta_cycles;
14815 u32 current_egress_rate = ppd->current_egress_rate;
14816 /* rates here are in units of 10^6 bits/sec */
14817
14818 if (desired_egress_rate == -1)
14819 return 0; /* shouldn't happen */
14820
14821 if (desired_egress_rate >= current_egress_rate)
14822 return 0; /* we can't help go faster, only slower */
14823
14824 delta_cycles = egress_cycles(dw_len * 4, desired_egress_rate) -
14825 egress_cycles(dw_len * 4, current_egress_rate);
14826
14827 return (u16)delta_cycles;
14828}
14829
77241056
MM		 14830/**
14831 * create_pbc - build a pbc for transmission
14832 * @flags: special case flags or-ed in built pbc
14833 * @srate: static rate
14834 * @vl: vl
14835 * @dwlen: dword length (header words + data words + pbc words)
14836 *
14837 * Create a PBC with the given flags, rate, VL, and length.
14838 *
14839 * NOTE: The PBC created will not insert any HCRC - all callers but one are
14840 * for verbs, which does not use this PSM feature. The lone other caller
14841 * is for the diagnostic interface which calls this if the user does not
14842 * supply their own PBC.
14843 */
14844u64 create_pbc(struct hfi1_pportdata *ppd, u64 flags, int srate_mbs, u32 vl,
14845 u32 dw_len)
14846{
14847 u64 pbc, delay = 0;
14848
14849 if (unlikely(srate_mbs))
14850 delay = delay_cycles(ppd, srate_mbs, dw_len);
14851
14852 pbc = flags
14853 | (delay << PBC_STATIC_RATE_CONTROL_COUNT_SHIFT)
14854 | ((u64)PBC_IHCRC_NONE << PBC_INSERT_HCRC_SHIFT)
14855 | (vl & PBC_VL_MASK) << PBC_VL_SHIFT
14856 | (dw_len & PBC_LENGTH_DWS_MASK)
14857 << PBC_LENGTH_DWS_SHIFT;
14858
14859 return pbc;
14860}
14861
14862#define SBUS_THERMAL 0x4f
14863#define SBUS_THERM_MONITOR_MODE 0x1
14864
14865#define THERM_FAILURE(dev, ret, reason) \
14866 dd_dev_err((dd), \
14867 "Thermal sensor initialization failed: %s (%d)\n", \
14868 (reason), (ret))
14869
14870/*
cde10afa 14871 * Initialize the thermal sensor.
77241056
MM		 14872 *
14873 * After initialization, enable polling of thermal sensor through
14874 * SBus interface. In order for this to work, the SBus Master
14875 * firmware has to be loaded due to the fact that the HW polling
14876 * logic uses SBus interrupts, which are not supported with
14877 * default firmware. Otherwise, no data will be returned through
14878 * the ASIC_STS_THERM CSR.
14879 */
14880static int thermal_init(struct hfi1_devdata *dd)
14881{
14882 int ret = 0;
14883
14884 if (dd->icode != ICODE_RTL_SILICON ||
a453698b 14885 check_chip_resource(dd, CR_THERM_INIT, NULL))
77241056
MM		 14886 return ret;
14887
576531fd
DL		 14888 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT);
14889 if (ret) {
14890 THERM_FAILURE(dd, ret, "Acquire SBus");
14891 return ret;
14892 }
14893
77241056 14894 dd_dev_info(dd, "Initializing thermal sensor\n");
4ef98989
JAQ		 14895 /* Disable polling of thermal readings */
14896 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0);
14897 msleep(100);
77241056
MM		 14898 /* Thermal Sensor Initialization */
14899 /* Step 1: Reset the Thermal SBus Receiver */
14900 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
14901 RESET_SBUS_RECEIVER, 0);
14902 if (ret) {
14903 THERM_FAILURE(dd, ret, "Bus Reset");
14904 goto done;
14905 }
14906 /* Step 2: Set Reset bit in Thermal block */
14907 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
14908 WRITE_SBUS_RECEIVER, 0x1);
14909 if (ret) {
14910 THERM_FAILURE(dd, ret, "Therm Block Reset");
14911 goto done;
14912 }
14913 /* Step 3: Write clock divider value (100MHz -> 2MHz) */
14914 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x1,
14915 WRITE_SBUS_RECEIVER, 0x32);
14916 if (ret) {
14917 THERM_FAILURE(dd, ret, "Write Clock Div");
14918 goto done;
14919 }
14920 /* Step 4: Select temperature mode */
14921 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x3,
14922 WRITE_SBUS_RECEIVER,
14923 SBUS_THERM_MONITOR_MODE);
14924 if (ret) {
14925 THERM_FAILURE(dd, ret, "Write Mode Sel");
14926 goto done;
14927 }
14928 /* Step 5: De-assert block reset and start conversion */
14929 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
14930 WRITE_SBUS_RECEIVER, 0x2);
14931 if (ret) {
14932 THERM_FAILURE(dd, ret, "Write Reset Deassert");
14933 goto done;
14934 }
14935 /* Step 5.1: Wait for first conversion (21.5ms per spec) */
14936 msleep(22);
14937
14938 /* Enable polling of thermal readings */
14939 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1);
a453698b
DL		 14940
14941 /* Set initialized flag */
14942 ret = acquire_chip_resource(dd, CR_THERM_INIT, 0);
14943 if (ret)
14944 THERM_FAILURE(dd, ret, "Unable to set thermal init flag");
14945
77241056 14946done:
576531fd 14947 release_chip_resource(dd, CR_SBUS);
77241056
MM		 14948 return ret;
14949}
14950
14951static void handle_temp_err(struct hfi1_devdata *dd)
14952{
14953 struct hfi1_pportdata *ppd = &dd->pport[0];
14954 /*
14955 * Thermal Critical Interrupt
14956 * Put the device into forced freeze mode, take link down to
14957 * offline, and put DC into reset.
14958 */
14959 dd_dev_emerg(dd,
14960 "Critical temperature reached! Forcing device into freeze mode!\n");
14961 dd->flags |= HFI1_FORCED_FREEZE;
8638b77f 14962 start_freeze_handling(ppd, FREEZE_SELF | FREEZE_ABORT);
77241056
MM		 14963 /*
14964 * Shut DC down as much and as quickly as possible.
14965 *
14966 * Step 1: Take the link down to OFFLINE. This will cause the
14967 * 8051 to put the Serdes in reset. However, we don't want to
14968 * go through the entire link state machine since we want to
14969 * shutdown ASAP. Furthermore, this is not a graceful shutdown
14970 * but rather an attempt to save the chip.
14971 * Code below is almost the same as quiet_serdes() but avoids
14972 * all the extra work and the sleeps.
14973 */
14974 ppd->driver_link_ready = 0;
14975 ppd->link_enabled = 0;
bf640096
HC		 14976 set_physical_link_state(dd, (OPA_LINKDOWN_REASON_SMA_DISABLED << 8) |
14977 PLS_OFFLINE);
77241056
MM		 14978 /*
14979 * Step 2: Shutdown LCB and 8051
14980 * After shutdown, do not restore DC_CFG_RESET value.
14981 */
14982 dc_shutdown(dd);
14983}
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