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Merge tag 'for-linus-20170825' of git://git.infradead.org/linux-mtd
[mirror_ubuntu-artful-kernel.git] / drivers / infiniband / hw / hfi1 / chip.c
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77241056 1/*
5e6e9424 2 * Copyright(c) 2015 - 2017 Intel Corporation.
77241056
MM		 3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
77241056
MM		 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * BSD LICENSE
19 *
77241056
MM		 20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 *
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
29 * distribution.
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 */
47
48/*
49 * This file contains all of the code that is specific to the HFI chip
50 */
51
52#include <linux/pci.h>
53#include <linux/delay.h>
54#include <linux/interrupt.h>
55#include <linux/module.h>
56
57#include "hfi.h"
58#include "trace.h"
59#include "mad.h"
60#include "pio.h"
61#include "sdma.h"
62#include "eprom.h"
5d9157aa 63#include "efivar.h"
8ebd4cf1 64#include "platform.h"
affa48de 65#include "aspm.h"
4197344b 66#include "affinity.h"
243d9f43 67#include "debugfs.h"
77241056
MM		 68
69#define NUM_IB_PORTS 1
70
71uint kdeth_qp;
72module_param_named(kdeth_qp, kdeth_qp, uint, S_IRUGO);
73MODULE_PARM_DESC(kdeth_qp, "Set the KDETH queue pair prefix");
74
75uint num_vls = HFI1_MAX_VLS_SUPPORTED;
76module_param(num_vls, uint, S_IRUGO);
77MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
78
79/*
80 * Default time to aggregate two 10K packets from the idle state
81 * (timer not running). The timer starts at the end of the first packet,
82 * so only the time for one 10K packet and header plus a bit extra is needed.
83 * 10 * 1024 + 64 header byte = 10304 byte
84 * 10304 byte / 12.5 GB/s = 824.32ns
85 */
86uint rcv_intr_timeout = (824 + 16); /* 16 is for coalescing interrupt */
87module_param(rcv_intr_timeout, uint, S_IRUGO);
88MODULE_PARM_DESC(rcv_intr_timeout, "Receive interrupt mitigation timeout in ns");
89
90uint rcv_intr_count = 16; /* same as qib */
91module_param(rcv_intr_count, uint, S_IRUGO);
92MODULE_PARM_DESC(rcv_intr_count, "Receive interrupt mitigation count");
93
94ushort link_crc_mask = SUPPORTED_CRCS;
95module_param(link_crc_mask, ushort, S_IRUGO);
96MODULE_PARM_DESC(link_crc_mask, "CRCs to use on the link");
97
98uint loopback;
99module_param_named(loopback, loopback, uint, S_IRUGO);
100MODULE_PARM_DESC(loopback, "Put into loopback mode (1 = serdes, 3 = external cable");
101
102/* Other driver tunables */
103uint rcv_intr_dynamic = 1; /* enable dynamic mode for rcv int mitigation*/
104static ushort crc_14b_sideband = 1;
105static uint use_flr = 1;
106uint quick_linkup; /* skip LNI */
107
108struct flag_table {
109 u64 flag; /* the flag */
110 char *str; /* description string */
111 u16 extra; /* extra information */
112 u16 unused0;
113 u32 unused1;
114};
115
116/* str must be a string constant */
117#define FLAG_ENTRY(str, extra, flag) {flag, str, extra}
118#define FLAG_ENTRY0(str, flag) {flag, str, 0}
119
120/* Send Error Consequences */
121#define SEC_WRITE_DROPPED 0x1
122#define SEC_PACKET_DROPPED 0x2
123#define SEC_SC_HALTED 0x4 /* per-context only */
124#define SEC_SPC_FREEZE 0x8 /* per-HFI only */
125
8784ac02 126#define DEFAULT_KRCVQS 2
77241056 127#define MIN_KERNEL_KCTXTS 2
82c2611d 128#define FIRST_KERNEL_KCTXT 1
2280740f
VN		 129
130/*
131 * RSM instance allocation
132 * 0 - Verbs
133 * 1 - User Fecn Handling
134 * 2 - Vnic
135 */
136#define RSM_INS_VERBS 0
137#define RSM_INS_FECN 1
138#define RSM_INS_VNIC 2
77241056
MM		 139
140/* Bit offset into the GUID which carries HFI id information */
141#define GUID_HFI_INDEX_SHIFT 39
142
143/* extract the emulation revision */
144#define emulator_rev(dd) ((dd)->irev >> 8)
145/* parallel and serial emulation versions are 3 and 4 respectively */
146#define is_emulator_p(dd) ((((dd)->irev) & 0xf) == 3)
147#define is_emulator_s(dd) ((((dd)->irev) & 0xf) == 4)
148
2280740f 149/* RSM fields for Verbs */
77241056
MM		 150/* packet type */
151#define IB_PACKET_TYPE 2ull
152#define QW_SHIFT 6ull
153/* QPN[7..1] */
154#define QPN_WIDTH 7ull
155
156/* LRH.BTH: QW 0, OFFSET 48 - for match */
157#define LRH_BTH_QW 0ull
158#define LRH_BTH_BIT_OFFSET 48ull
159#define LRH_BTH_OFFSET(off) ((LRH_BTH_QW << QW_SHIFT) | (off))
160#define LRH_BTH_MATCH_OFFSET LRH_BTH_OFFSET(LRH_BTH_BIT_OFFSET)
161#define LRH_BTH_SELECT
162#define LRH_BTH_MASK 3ull
163#define LRH_BTH_VALUE 2ull
164
165/* LRH.SC[3..0] QW 0, OFFSET 56 - for match */
166#define LRH_SC_QW 0ull
167#define LRH_SC_BIT_OFFSET 56ull
168#define LRH_SC_OFFSET(off) ((LRH_SC_QW << QW_SHIFT) | (off))
169#define LRH_SC_MATCH_OFFSET LRH_SC_OFFSET(LRH_SC_BIT_OFFSET)
170#define LRH_SC_MASK 128ull
171#define LRH_SC_VALUE 0ull
172
173/* SC[n..0] QW 0, OFFSET 60 - for select */
174#define LRH_SC_SELECT_OFFSET ((LRH_SC_QW << QW_SHIFT) | (60ull))
175
176/* QPN[m+n:1] QW 1, OFFSET 1 */
177#define QPN_SELECT_OFFSET ((1ull << QW_SHIFT) | (1ull))
178
2280740f
VN		 179/* RSM fields for Vnic */
180/* L2_TYPE: QW 0, OFFSET 61 - for match */
181#define L2_TYPE_QW 0ull
182#define L2_TYPE_BIT_OFFSET 61ull
183#define L2_TYPE_OFFSET(off) ((L2_TYPE_QW << QW_SHIFT) | (off))
184#define L2_TYPE_MATCH_OFFSET L2_TYPE_OFFSET(L2_TYPE_BIT_OFFSET)
185#define L2_TYPE_MASK 3ull
186#define L2_16B_VALUE 2ull
187
188/* L4_TYPE QW 1, OFFSET 0 - for match */
189#define L4_TYPE_QW 1ull
190#define L4_TYPE_BIT_OFFSET 0ull
191#define L4_TYPE_OFFSET(off) ((L4_TYPE_QW << QW_SHIFT) | (off))
192#define L4_TYPE_MATCH_OFFSET L4_TYPE_OFFSET(L4_TYPE_BIT_OFFSET)
193#define L4_16B_TYPE_MASK 0xFFull
194#define L4_16B_ETH_VALUE 0x78ull
195
196/* 16B VESWID - for select */
197#define L4_16B_HDR_VESWID_OFFSET ((2 << QW_SHIFT) | (16ull))
198/* 16B ENTROPY - for select */
199#define L2_16B_ENTROPY_OFFSET ((1 << QW_SHIFT) | (32ull))
200
77241056
MM		 201/* defines to build power on SC2VL table */
202#define SC2VL_VAL( \
203 num, \
204 sc0, sc0val, \
205 sc1, sc1val, \
206 sc2, sc2val, \
207 sc3, sc3val, \
208 sc4, sc4val, \
209 sc5, sc5val, \
210 sc6, sc6val, \
211 sc7, sc7val) \
212( \
213 ((u64)(sc0val) << SEND_SC2VLT##num##_SC##sc0##_SHIFT) | \
214 ((u64)(sc1val) << SEND_SC2VLT##num##_SC##sc1##_SHIFT) | \
215 ((u64)(sc2val) << SEND_SC2VLT##num##_SC##sc2##_SHIFT) | \
216 ((u64)(sc3val) << SEND_SC2VLT##num##_SC##sc3##_SHIFT) | \
217 ((u64)(sc4val) << SEND_SC2VLT##num##_SC##sc4##_SHIFT) | \
218 ((u64)(sc5val) << SEND_SC2VLT##num##_SC##sc5##_SHIFT) | \
219 ((u64)(sc6val) << SEND_SC2VLT##num##_SC##sc6##_SHIFT) | \
220 ((u64)(sc7val) << SEND_SC2VLT##num##_SC##sc7##_SHIFT) \
221)
222
223#define DC_SC_VL_VAL( \
224 range, \
225 e0, e0val, \
226 e1, e1val, \
227 e2, e2val, \
228 e3, e3val, \
229 e4, e4val, \
230 e5, e5val, \
231 e6, e6val, \
232 e7, e7val, \
233 e8, e8val, \
234 e9, e9val, \
235 e10, e10val, \
236 e11, e11val, \
237 e12, e12val, \
238 e13, e13val, \
239 e14, e14val, \
240 e15, e15val) \
241( \
242 ((u64)(e0val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e0##_SHIFT) | \
243 ((u64)(e1val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e1##_SHIFT) | \
244 ((u64)(e2val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e2##_SHIFT) | \
245 ((u64)(e3val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e3##_SHIFT) | \
246 ((u64)(e4val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e4##_SHIFT) | \
247 ((u64)(e5val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e5##_SHIFT) | \
248 ((u64)(e6val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e6##_SHIFT) | \
249 ((u64)(e7val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e7##_SHIFT) | \
250 ((u64)(e8val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e8##_SHIFT) | \
251 ((u64)(e9val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e9##_SHIFT) | \
252 ((u64)(e10val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e10##_SHIFT) | \
253 ((u64)(e11val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e11##_SHIFT) | \
254 ((u64)(e12val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e12##_SHIFT) | \
255 ((u64)(e13val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e13##_SHIFT) | \
256 ((u64)(e14val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e14##_SHIFT) | \
257 ((u64)(e15val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e15##_SHIFT) \
258)
259
260/* all CceStatus sub-block freeze bits */
261#define ALL_FROZE (CCE_STATUS_SDMA_FROZE_SMASK \
262 | CCE_STATUS_RXE_FROZE_SMASK \
263 | CCE_STATUS_TXE_FROZE_SMASK \
264 | CCE_STATUS_TXE_PIO_FROZE_SMASK)
265/* all CceStatus sub-block TXE pause bits */
266#define ALL_TXE_PAUSE (CCE_STATUS_TXE_PIO_PAUSED_SMASK \
267 | CCE_STATUS_TXE_PAUSED_SMASK \
268 | CCE_STATUS_SDMA_PAUSED_SMASK)
269/* all CceStatus sub-block RXE pause bits */
270#define ALL_RXE_PAUSE CCE_STATUS_RXE_PAUSED_SMASK
271
2b719046
JP		 272#define CNTR_MAX 0xFFFFFFFFFFFFFFFFULL
273#define CNTR_32BIT_MAX 0x00000000FFFFFFFF
274
77241056
MM		 275/*
276 * CCE Error flags.
277 */
278static struct flag_table cce_err_status_flags[] = {
279/* 0*/ FLAG_ENTRY0("CceCsrParityErr",
280 CCE_ERR_STATUS_CCE_CSR_PARITY_ERR_SMASK),
281/* 1*/ FLAG_ENTRY0("CceCsrReadBadAddrErr",
282 CCE_ERR_STATUS_CCE_CSR_READ_BAD_ADDR_ERR_SMASK),
283/* 2*/ FLAG_ENTRY0("CceCsrWriteBadAddrErr",
284 CCE_ERR_STATUS_CCE_CSR_WRITE_BAD_ADDR_ERR_SMASK),
285/* 3*/ FLAG_ENTRY0("CceTrgtAsyncFifoParityErr",
286 CCE_ERR_STATUS_CCE_TRGT_ASYNC_FIFO_PARITY_ERR_SMASK),
287/* 4*/ FLAG_ENTRY0("CceTrgtAccessErr",
288 CCE_ERR_STATUS_CCE_TRGT_ACCESS_ERR_SMASK),
289/* 5*/ FLAG_ENTRY0("CceRspdDataParityErr",
290 CCE_ERR_STATUS_CCE_RSPD_DATA_PARITY_ERR_SMASK),
291/* 6*/ FLAG_ENTRY0("CceCli0AsyncFifoParityErr",
292 CCE_ERR_STATUS_CCE_CLI0_ASYNC_FIFO_PARITY_ERR_SMASK),
293/* 7*/ FLAG_ENTRY0("CceCsrCfgBusParityErr",
294 CCE_ERR_STATUS_CCE_CSR_CFG_BUS_PARITY_ERR_SMASK),
295/* 8*/ FLAG_ENTRY0("CceCli2AsyncFifoParityErr",
296 CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK),
297/* 9*/ FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr",
298 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR_SMASK),
299/*10*/ FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr",
300 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR_SMASK),
301/*11*/ FLAG_ENTRY0("CceCli1AsyncFifoRxdmaParityError",
302 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERROR_SMASK),
303/*12*/ FLAG_ENTRY0("CceCli1AsyncFifoDbgParityError",
304 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERROR_SMASK),
305/*13*/ FLAG_ENTRY0("PcicRetryMemCorErr",
306 CCE_ERR_STATUS_PCIC_RETRY_MEM_COR_ERR_SMASK),
307/*14*/ FLAG_ENTRY0("PcicRetryMemCorErr",
308 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_COR_ERR_SMASK),
309/*15*/ FLAG_ENTRY0("PcicPostHdQCorErr",
310 CCE_ERR_STATUS_PCIC_POST_HD_QCOR_ERR_SMASK),
311/*16*/ FLAG_ENTRY0("PcicPostHdQCorErr",
312 CCE_ERR_STATUS_PCIC_POST_DAT_QCOR_ERR_SMASK),
313/*17*/ FLAG_ENTRY0("PcicPostHdQCorErr",
314 CCE_ERR_STATUS_PCIC_CPL_HD_QCOR_ERR_SMASK),
315/*18*/ FLAG_ENTRY0("PcicCplDatQCorErr",
316 CCE_ERR_STATUS_PCIC_CPL_DAT_QCOR_ERR_SMASK),
317/*19*/ FLAG_ENTRY0("PcicNPostHQParityErr",
318 CCE_ERR_STATUS_PCIC_NPOST_HQ_PARITY_ERR_SMASK),
319/*20*/ FLAG_ENTRY0("PcicNPostDatQParityErr",
320 CCE_ERR_STATUS_PCIC_NPOST_DAT_QPARITY_ERR_SMASK),
321/*21*/ FLAG_ENTRY0("PcicRetryMemUncErr",
322 CCE_ERR_STATUS_PCIC_RETRY_MEM_UNC_ERR_SMASK),
323/*22*/ FLAG_ENTRY0("PcicRetrySotMemUncErr",
324 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_UNC_ERR_SMASK),
325/*23*/ FLAG_ENTRY0("PcicPostHdQUncErr",
326 CCE_ERR_STATUS_PCIC_POST_HD_QUNC_ERR_SMASK),
327/*24*/ FLAG_ENTRY0("PcicPostDatQUncErr",
328 CCE_ERR_STATUS_PCIC_POST_DAT_QUNC_ERR_SMASK),
329/*25*/ FLAG_ENTRY0("PcicCplHdQUncErr",
330 CCE_ERR_STATUS_PCIC_CPL_HD_QUNC_ERR_SMASK),
331/*26*/ FLAG_ENTRY0("PcicCplDatQUncErr",
332 CCE_ERR_STATUS_PCIC_CPL_DAT_QUNC_ERR_SMASK),
333/*27*/ FLAG_ENTRY0("PcicTransmitFrontParityErr",
334 CCE_ERR_STATUS_PCIC_TRANSMIT_FRONT_PARITY_ERR_SMASK),
335/*28*/ FLAG_ENTRY0("PcicTransmitBackParityErr",
336 CCE_ERR_STATUS_PCIC_TRANSMIT_BACK_PARITY_ERR_SMASK),
337/*29*/ FLAG_ENTRY0("PcicReceiveParityErr",
338 CCE_ERR_STATUS_PCIC_RECEIVE_PARITY_ERR_SMASK),
339/*30*/ FLAG_ENTRY0("CceTrgtCplTimeoutErr",
340 CCE_ERR_STATUS_CCE_TRGT_CPL_TIMEOUT_ERR_SMASK),
341/*31*/ FLAG_ENTRY0("LATriggered",
342 CCE_ERR_STATUS_LA_TRIGGERED_SMASK),
343/*32*/ FLAG_ENTRY0("CceSegReadBadAddrErr",
344 CCE_ERR_STATUS_CCE_SEG_READ_BAD_ADDR_ERR_SMASK),
345/*33*/ FLAG_ENTRY0("CceSegWriteBadAddrErr",
346 CCE_ERR_STATUS_CCE_SEG_WRITE_BAD_ADDR_ERR_SMASK),
347/*34*/ FLAG_ENTRY0("CceRcplAsyncFifoParityErr",
348 CCE_ERR_STATUS_CCE_RCPL_ASYNC_FIFO_PARITY_ERR_SMASK),
349/*35*/ FLAG_ENTRY0("CceRxdmaConvFifoParityErr",
350 CCE_ERR_STATUS_CCE_RXDMA_CONV_FIFO_PARITY_ERR_SMASK),
351/*36*/ FLAG_ENTRY0("CceMsixTableCorErr",
352 CCE_ERR_STATUS_CCE_MSIX_TABLE_COR_ERR_SMASK),
353/*37*/ FLAG_ENTRY0("CceMsixTableUncErr",
354 CCE_ERR_STATUS_CCE_MSIX_TABLE_UNC_ERR_SMASK),
355/*38*/ FLAG_ENTRY0("CceIntMapCorErr",
356 CCE_ERR_STATUS_CCE_INT_MAP_COR_ERR_SMASK),
357/*39*/ FLAG_ENTRY0("CceIntMapUncErr",
358 CCE_ERR_STATUS_CCE_INT_MAP_UNC_ERR_SMASK),
359/*40*/ FLAG_ENTRY0("CceMsixCsrParityErr",
360 CCE_ERR_STATUS_CCE_MSIX_CSR_PARITY_ERR_SMASK),
361/*41-63 reserved*/
362};
363
364/*
365 * Misc Error flags
366 */
367#define MES(text) MISC_ERR_STATUS_MISC_##text##_ERR_SMASK
368static struct flag_table misc_err_status_flags[] = {
369/* 0*/ FLAG_ENTRY0("CSR_PARITY", MES(CSR_PARITY)),
370/* 1*/ FLAG_ENTRY0("CSR_READ_BAD_ADDR", MES(CSR_READ_BAD_ADDR)),
371/* 2*/ FLAG_ENTRY0("CSR_WRITE_BAD_ADDR", MES(CSR_WRITE_BAD_ADDR)),
372/* 3*/ FLAG_ENTRY0("SBUS_WRITE_FAILED", MES(SBUS_WRITE_FAILED)),
373/* 4*/ FLAG_ENTRY0("KEY_MISMATCH", MES(KEY_MISMATCH)),
374/* 5*/ FLAG_ENTRY0("FW_AUTH_FAILED", MES(FW_AUTH_FAILED)),
375/* 6*/ FLAG_ENTRY0("EFUSE_CSR_PARITY", MES(EFUSE_CSR_PARITY)),
376/* 7*/ FLAG_ENTRY0("EFUSE_READ_BAD_ADDR", MES(EFUSE_READ_BAD_ADDR)),
377/* 8*/ FLAG_ENTRY0("EFUSE_WRITE", MES(EFUSE_WRITE)),
378/* 9*/ FLAG_ENTRY0("EFUSE_DONE_PARITY", MES(EFUSE_DONE_PARITY)),
379/*10*/ FLAG_ENTRY0("INVALID_EEP_CMD", MES(INVALID_EEP_CMD)),
380/*11*/ FLAG_ENTRY0("MBIST_FAIL", MES(MBIST_FAIL)),
381/*12*/ FLAG_ENTRY0("PLL_LOCK_FAIL", MES(PLL_LOCK_FAIL))
382};
383
384/*
385 * TXE PIO Error flags and consequences
386 */
387static struct flag_table pio_err_status_flags[] = {
388/* 0*/ FLAG_ENTRY("PioWriteBadCtxt",
389 SEC_WRITE_DROPPED,
390 SEND_PIO_ERR_STATUS_PIO_WRITE_BAD_CTXT_ERR_SMASK),
391/* 1*/ FLAG_ENTRY("PioWriteAddrParity",
392 SEC_SPC_FREEZE,
393 SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK),
394/* 2*/ FLAG_ENTRY("PioCsrParity",
395 SEC_SPC_FREEZE,
396 SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK),
397/* 3*/ FLAG_ENTRY("PioSbMemFifo0",
398 SEC_SPC_FREEZE,
399 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK),
400/* 4*/ FLAG_ENTRY("PioSbMemFifo1",
401 SEC_SPC_FREEZE,
402 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK),
403/* 5*/ FLAG_ENTRY("PioPccFifoParity",
404 SEC_SPC_FREEZE,
405 SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK),
406/* 6*/ FLAG_ENTRY("PioPecFifoParity",
407 SEC_SPC_FREEZE,
408 SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK),
409/* 7*/ FLAG_ENTRY("PioSbrdctlCrrelParity",
410 SEC_SPC_FREEZE,
411 SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK),
412/* 8*/ FLAG_ENTRY("PioSbrdctrlCrrelFifoParity",
413 SEC_SPC_FREEZE,
414 SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK),
415/* 9*/ FLAG_ENTRY("PioPktEvictFifoParityErr",
416 SEC_SPC_FREEZE,
417 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK),
418/*10*/ FLAG_ENTRY("PioSmPktResetParity",
419 SEC_SPC_FREEZE,
420 SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK),
421/*11*/ FLAG_ENTRY("PioVlLenMemBank0Unc",
422 SEC_SPC_FREEZE,
423 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK),
424/*12*/ FLAG_ENTRY("PioVlLenMemBank1Unc",
425 SEC_SPC_FREEZE,
426 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK),
427/*13*/ FLAG_ENTRY("PioVlLenMemBank0Cor",
428 0,
429 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_COR_ERR_SMASK),
430/*14*/ FLAG_ENTRY("PioVlLenMemBank1Cor",
431 0,
432 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_COR_ERR_SMASK),
433/*15*/ FLAG_ENTRY("PioCreditRetFifoParity",
434 SEC_SPC_FREEZE,
435 SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK),
436/*16*/ FLAG_ENTRY("PioPpmcPblFifo",
437 SEC_SPC_FREEZE,
438 SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK),
439/*17*/ FLAG_ENTRY("PioInitSmIn",
440 0,
441 SEND_PIO_ERR_STATUS_PIO_INIT_SM_IN_ERR_SMASK),
442/*18*/ FLAG_ENTRY("PioPktEvictSmOrArbSm",
443 SEC_SPC_FREEZE,
444 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK),
445/*19*/ FLAG_ENTRY("PioHostAddrMemUnc",
446 SEC_SPC_FREEZE,
447 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK),
448/*20*/ FLAG_ENTRY("PioHostAddrMemCor",
449 0,
450 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_COR_ERR_SMASK),
451/*21*/ FLAG_ENTRY("PioWriteDataParity",
452 SEC_SPC_FREEZE,
453 SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK),
454/*22*/ FLAG_ENTRY("PioStateMachine",
455 SEC_SPC_FREEZE,
456 SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK),
457/*23*/ FLAG_ENTRY("PioWriteQwValidParity",
8638b77f 458 SEC_WRITE_DROPPED | SEC_SPC_FREEZE,
77241056
MM		 459 SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK),
460/*24*/ FLAG_ENTRY("PioBlockQwCountParity",
8638b77f 461 SEC_WRITE_DROPPED | SEC_SPC_FREEZE,
77241056
MM		 462 SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK),
463/*25*/ FLAG_ENTRY("PioVlfVlLenParity",
464 SEC_SPC_FREEZE,
465 SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK),
466/*26*/ FLAG_ENTRY("PioVlfSopParity",
467 SEC_SPC_FREEZE,
468 SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK),
469/*27*/ FLAG_ENTRY("PioVlFifoParity",
470 SEC_SPC_FREEZE,
471 SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK),
472/*28*/ FLAG_ENTRY("PioPpmcBqcMemParity",
473 SEC_SPC_FREEZE,
474 SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK),
475/*29*/ FLAG_ENTRY("PioPpmcSopLen",
476 SEC_SPC_FREEZE,
477 SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK),
478/*30-31 reserved*/
479/*32*/ FLAG_ENTRY("PioCurrentFreeCntParity",
480 SEC_SPC_FREEZE,
481 SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK),
482/*33*/ FLAG_ENTRY("PioLastReturnedCntParity",
483 SEC_SPC_FREEZE,
484 SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK),
485/*34*/ FLAG_ENTRY("PioPccSopHeadParity",
486 SEC_SPC_FREEZE,
487 SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK),
488/*35*/ FLAG_ENTRY("PioPecSopHeadParityErr",
489 SEC_SPC_FREEZE,
490 SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK),
491/*36-63 reserved*/
492};
493
494/* TXE PIO errors that cause an SPC freeze */
495#define ALL_PIO_FREEZE_ERR \
496 (SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK \
497 | SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK \
498 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK \
499 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK \
500 | SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK \
501 | SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK \
502 | SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK \
503 | SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK \
504 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK \
505 | SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK \
506 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK \
507 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK \
508 | SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK \
509 | SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK \
510 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK \
511 | SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK \
512 | SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK \
513 | SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK \
514 | SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK \
515 | SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK \
516 | SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK \
517 | SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK \
518 | SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK \
519 | SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK \
520 | SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK \
521 | SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK \
522 | SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK \
523 | SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK \
524 | SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK)
525
526/*
527 * TXE SDMA Error flags
528 */
529static struct flag_table sdma_err_status_flags[] = {
530/* 0*/ FLAG_ENTRY0("SDmaRpyTagErr",
531 SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK),
532/* 1*/ FLAG_ENTRY0("SDmaCsrParityErr",
533 SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK),
534/* 2*/ FLAG_ENTRY0("SDmaPcieReqTrackingUncErr",
535 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK),
536/* 3*/ FLAG_ENTRY0("SDmaPcieReqTrackingCorErr",
537 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_COR_ERR_SMASK),
538/*04-63 reserved*/
539};
540
541/* TXE SDMA errors that cause an SPC freeze */
542#define ALL_SDMA_FREEZE_ERR \
543 (SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK \
544 | SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK \
545 | SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK)
546
69a00b8e
MM		 547/* SendEgressErrInfo bits that correspond to a PortXmitDiscard counter */
548#define PORT_DISCARD_EGRESS_ERRS \
549 (SEND_EGRESS_ERR_INFO_TOO_LONG_IB_PACKET_ERR_SMASK \
550 | SEND_EGRESS_ERR_INFO_VL_MAPPING_ERR_SMASK \
551 | SEND_EGRESS_ERR_INFO_VL_ERR_SMASK)
552
77241056
MM		 553/*
554 * TXE Egress Error flags
555 */
556#define SEES(text) SEND_EGRESS_ERR_STATUS_##text##_ERR_SMASK
557static struct flag_table egress_err_status_flags[] = {
558/* 0*/ FLAG_ENTRY0("TxPktIntegrityMemCorErr", SEES(TX_PKT_INTEGRITY_MEM_COR)),
559/* 1*/ FLAG_ENTRY0("TxPktIntegrityMemUncErr", SEES(TX_PKT_INTEGRITY_MEM_UNC)),
560/* 2 reserved */
561/* 3*/ FLAG_ENTRY0("TxEgressFifoUnderrunOrParityErr",
562 SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY)),
563/* 4*/ FLAG_ENTRY0("TxLinkdownErr", SEES(TX_LINKDOWN)),
564/* 5*/ FLAG_ENTRY0("TxIncorrectLinkStateErr", SEES(TX_INCORRECT_LINK_STATE)),
565/* 6 reserved */
566/* 7*/ FLAG_ENTRY0("TxPioLaunchIntfParityErr",
567 SEES(TX_PIO_LAUNCH_INTF_PARITY)),
568/* 8*/ FLAG_ENTRY0("TxSdmaLaunchIntfParityErr",
569 SEES(TX_SDMA_LAUNCH_INTF_PARITY)),
570/* 9-10 reserved */
571/*11*/ FLAG_ENTRY0("TxSbrdCtlStateMachineParityErr",
572 SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY)),
573/*12*/ FLAG_ENTRY0("TxIllegalVLErr", SEES(TX_ILLEGAL_VL)),
574/*13*/ FLAG_ENTRY0("TxLaunchCsrParityErr", SEES(TX_LAUNCH_CSR_PARITY)),
575/*14*/ FLAG_ENTRY0("TxSbrdCtlCsrParityErr", SEES(TX_SBRD_CTL_CSR_PARITY)),
576/*15*/ FLAG_ENTRY0("TxConfigParityErr", SEES(TX_CONFIG_PARITY)),
577/*16*/ FLAG_ENTRY0("TxSdma0DisallowedPacketErr",
578 SEES(TX_SDMA0_DISALLOWED_PACKET)),
579/*17*/ FLAG_ENTRY0("TxSdma1DisallowedPacketErr",
580 SEES(TX_SDMA1_DISALLOWED_PACKET)),
581/*18*/ FLAG_ENTRY0("TxSdma2DisallowedPacketErr",
582 SEES(TX_SDMA2_DISALLOWED_PACKET)),
583/*19*/ FLAG_ENTRY0("TxSdma3DisallowedPacketErr",
584 SEES(TX_SDMA3_DISALLOWED_PACKET)),
585/*20*/ FLAG_ENTRY0("TxSdma4DisallowedPacketErr",
586 SEES(TX_SDMA4_DISALLOWED_PACKET)),
587/*21*/ FLAG_ENTRY0("TxSdma5DisallowedPacketErr",
588 SEES(TX_SDMA5_DISALLOWED_PACKET)),
589/*22*/ FLAG_ENTRY0("TxSdma6DisallowedPacketErr",
590 SEES(TX_SDMA6_DISALLOWED_PACKET)),
591/*23*/ FLAG_ENTRY0("TxSdma7DisallowedPacketErr",
592 SEES(TX_SDMA7_DISALLOWED_PACKET)),
593/*24*/ FLAG_ENTRY0("TxSdma8DisallowedPacketErr",
594 SEES(TX_SDMA8_DISALLOWED_PACKET)),
595/*25*/ FLAG_ENTRY0("TxSdma9DisallowedPacketErr",
596 SEES(TX_SDMA9_DISALLOWED_PACKET)),
597/*26*/ FLAG_ENTRY0("TxSdma10DisallowedPacketErr",
598 SEES(TX_SDMA10_DISALLOWED_PACKET)),
599/*27*/ FLAG_ENTRY0("TxSdma11DisallowedPacketErr",
600 SEES(TX_SDMA11_DISALLOWED_PACKET)),
601/*28*/ FLAG_ENTRY0("TxSdma12DisallowedPacketErr",
602 SEES(TX_SDMA12_DISALLOWED_PACKET)),
603/*29*/ FLAG_ENTRY0("TxSdma13DisallowedPacketErr",
604 SEES(TX_SDMA13_DISALLOWED_PACKET)),
605/*30*/ FLAG_ENTRY0("TxSdma14DisallowedPacketErr",
606 SEES(TX_SDMA14_DISALLOWED_PACKET)),
607/*31*/ FLAG_ENTRY0("TxSdma15DisallowedPacketErr",
608 SEES(TX_SDMA15_DISALLOWED_PACKET)),
609/*32*/ FLAG_ENTRY0("TxLaunchFifo0UncOrParityErr",
610 SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY)),
611/*33*/ FLAG_ENTRY0("TxLaunchFifo1UncOrParityErr",
612 SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY)),
613/*34*/ FLAG_ENTRY0("TxLaunchFifo2UncOrParityErr",
614 SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY)),
615/*35*/ FLAG_ENTRY0("TxLaunchFifo3UncOrParityErr",
616 SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY)),
617/*36*/ FLAG_ENTRY0("TxLaunchFifo4UncOrParityErr",
618 SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY)),
619/*37*/ FLAG_ENTRY0("TxLaunchFifo5UncOrParityErr",
620 SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY)),
621/*38*/ FLAG_ENTRY0("TxLaunchFifo6UncOrParityErr",
622 SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY)),
623/*39*/ FLAG_ENTRY0("TxLaunchFifo7UncOrParityErr",
624 SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY)),
625/*40*/ FLAG_ENTRY0("TxLaunchFifo8UncOrParityErr",
626 SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY)),
627/*41*/ FLAG_ENTRY0("TxCreditReturnParityErr", SEES(TX_CREDIT_RETURN_PARITY)),
628/*42*/ FLAG_ENTRY0("TxSbHdrUncErr", SEES(TX_SB_HDR_UNC)),
629/*43*/ FLAG_ENTRY0("TxReadSdmaMemoryUncErr", SEES(TX_READ_SDMA_MEMORY_UNC)),
630/*44*/ FLAG_ENTRY0("TxReadPioMemoryUncErr", SEES(TX_READ_PIO_MEMORY_UNC)),
631/*45*/ FLAG_ENTRY0("TxEgressFifoUncErr", SEES(TX_EGRESS_FIFO_UNC)),
632/*46*/ FLAG_ENTRY0("TxHcrcInsertionErr", SEES(TX_HCRC_INSERTION)),
633/*47*/ FLAG_ENTRY0("TxCreditReturnVLErr", SEES(TX_CREDIT_RETURN_VL)),
634/*48*/ FLAG_ENTRY0("TxLaunchFifo0CorErr", SEES(TX_LAUNCH_FIFO0_COR)),
635/*49*/ FLAG_ENTRY0("TxLaunchFifo1CorErr", SEES(TX_LAUNCH_FIFO1_COR)),
636/*50*/ FLAG_ENTRY0("TxLaunchFifo2CorErr", SEES(TX_LAUNCH_FIFO2_COR)),
637/*51*/ FLAG_ENTRY0("TxLaunchFifo3CorErr", SEES(TX_LAUNCH_FIFO3_COR)),
638/*52*/ FLAG_ENTRY0("TxLaunchFifo4CorErr", SEES(TX_LAUNCH_FIFO4_COR)),
639/*53*/ FLAG_ENTRY0("TxLaunchFifo5CorErr", SEES(TX_LAUNCH_FIFO5_COR)),
640/*54*/ FLAG_ENTRY0("TxLaunchFifo6CorErr", SEES(TX_LAUNCH_FIFO6_COR)),
641/*55*/ FLAG_ENTRY0("TxLaunchFifo7CorErr", SEES(TX_LAUNCH_FIFO7_COR)),
642/*56*/ FLAG_ENTRY0("TxLaunchFifo8CorErr", SEES(TX_LAUNCH_FIFO8_COR)),
643/*57*/ FLAG_ENTRY0("TxCreditOverrunErr", SEES(TX_CREDIT_OVERRUN)),
644/*58*/ FLAG_ENTRY0("TxSbHdrCorErr", SEES(TX_SB_HDR_COR)),
645/*59*/ FLAG_ENTRY0("TxReadSdmaMemoryCorErr", SEES(TX_READ_SDMA_MEMORY_COR)),
646/*60*/ FLAG_ENTRY0("TxReadPioMemoryCorErr", SEES(TX_READ_PIO_MEMORY_COR)),
647/*61*/ FLAG_ENTRY0("TxEgressFifoCorErr", SEES(TX_EGRESS_FIFO_COR)),
648/*62*/ FLAG_ENTRY0("TxReadSdmaMemoryCsrUncErr",
649 SEES(TX_READ_SDMA_MEMORY_CSR_UNC)),
650/*63*/ FLAG_ENTRY0("TxReadPioMemoryCsrUncErr",
651 SEES(TX_READ_PIO_MEMORY_CSR_UNC)),
652};
653
654/*
655 * TXE Egress Error Info flags
656 */
657#define SEEI(text) SEND_EGRESS_ERR_INFO_##text##_ERR_SMASK
658static struct flag_table egress_err_info_flags[] = {
659/* 0*/ FLAG_ENTRY0("Reserved", 0ull),
660/* 1*/ FLAG_ENTRY0("VLErr", SEEI(VL)),
661/* 2*/ FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)),
662/* 3*/ FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)),
663/* 4*/ FLAG_ENTRY0("PartitionKeyErr", SEEI(PARTITION_KEY)),
664/* 5*/ FLAG_ENTRY0("SLIDErr", SEEI(SLID)),
665/* 6*/ FLAG_ENTRY0("OpcodeErr", SEEI(OPCODE)),
666/* 7*/ FLAG_ENTRY0("VLMappingErr", SEEI(VL_MAPPING)),
667/* 8*/ FLAG_ENTRY0("RawErr", SEEI(RAW)),
668/* 9*/ FLAG_ENTRY0("RawIPv6Err", SEEI(RAW_IPV6)),
669/*10*/ FLAG_ENTRY0("GRHErr", SEEI(GRH)),
670/*11*/ FLAG_ENTRY0("BypassErr", SEEI(BYPASS)),
671/*12*/ FLAG_ENTRY0("KDETHPacketsErr", SEEI(KDETH_PACKETS)),
672/*13*/ FLAG_ENTRY0("NonKDETHPacketsErr", SEEI(NON_KDETH_PACKETS)),
673/*14*/ FLAG_ENTRY0("TooSmallIBPacketsErr", SEEI(TOO_SMALL_IB_PACKETS)),
674/*15*/ FLAG_ENTRY0("TooSmallBypassPacketsErr", SEEI(TOO_SMALL_BYPASS_PACKETS)),
675/*16*/ FLAG_ENTRY0("PbcTestErr", SEEI(PBC_TEST)),
676/*17*/ FLAG_ENTRY0("BadPktLenErr", SEEI(BAD_PKT_LEN)),
677/*18*/ FLAG_ENTRY0("TooLongIBPacketErr", SEEI(TOO_LONG_IB_PACKET)),
678/*19*/ FLAG_ENTRY0("TooLongBypassPacketsErr", SEEI(TOO_LONG_BYPASS_PACKETS)),
679/*20*/ FLAG_ENTRY0("PbcStaticRateControlErr", SEEI(PBC_STATIC_RATE_CONTROL)),
680/*21*/ FLAG_ENTRY0("BypassBadPktLenErr", SEEI(BAD_PKT_LEN)),
681};
682
683/* TXE Egress errors that cause an SPC freeze */
684#define ALL_TXE_EGRESS_FREEZE_ERR \
685 (SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY) \
686 | SEES(TX_PIO_LAUNCH_INTF_PARITY) \
687 | SEES(TX_SDMA_LAUNCH_INTF_PARITY) \
688 | SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY) \
689 | SEES(TX_LAUNCH_CSR_PARITY) \
690 | SEES(TX_SBRD_CTL_CSR_PARITY) \
691 | SEES(TX_CONFIG_PARITY) \
692 | SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY) \
693 | SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY) \
694 | SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY) \
695 | SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY) \
696 | SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY) \
697 | SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY) \
698 | SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY) \
699 | SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY) \
700 | SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY) \
701 | SEES(TX_CREDIT_RETURN_PARITY))
702
703/*
704 * TXE Send error flags
705 */
706#define SES(name) SEND_ERR_STATUS_SEND_##name##_ERR_SMASK
707static struct flag_table send_err_status_flags[] = {
2c5b521a 708/* 0*/ FLAG_ENTRY0("SendCsrParityErr", SES(CSR_PARITY)),
77241056
MM		 709/* 1*/ FLAG_ENTRY0("SendCsrReadBadAddrErr", SES(CSR_READ_BAD_ADDR)),
710/* 2*/ FLAG_ENTRY0("SendCsrWriteBadAddrErr", SES(CSR_WRITE_BAD_ADDR))
711};
712
713/*
714 * TXE Send Context Error flags and consequences
715 */
716static struct flag_table sc_err_status_flags[] = {
717/* 0*/ FLAG_ENTRY("InconsistentSop",
718 SEC_PACKET_DROPPED | SEC_SC_HALTED,
719 SEND_CTXT_ERR_STATUS_PIO_INCONSISTENT_SOP_ERR_SMASK),
720/* 1*/ FLAG_ENTRY("DisallowedPacket",
721 SEC_PACKET_DROPPED | SEC_SC_HALTED,
722 SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK),
723/* 2*/ FLAG_ENTRY("WriteCrossesBoundary",
724 SEC_WRITE_DROPPED | SEC_SC_HALTED,
725 SEND_CTXT_ERR_STATUS_PIO_WRITE_CROSSES_BOUNDARY_ERR_SMASK),
726/* 3*/ FLAG_ENTRY("WriteOverflow",
727 SEC_WRITE_DROPPED | SEC_SC_HALTED,
728 SEND_CTXT_ERR_STATUS_PIO_WRITE_OVERFLOW_ERR_SMASK),
729/* 4*/ FLAG_ENTRY("WriteOutOfBounds",
730 SEC_WRITE_DROPPED | SEC_SC_HALTED,
731 SEND_CTXT_ERR_STATUS_PIO_WRITE_OUT_OF_BOUNDS_ERR_SMASK),
732/* 5-63 reserved*/
733};
734
735/*
736 * RXE Receive Error flags
737 */
738#define RXES(name) RCV_ERR_STATUS_RX_##name##_ERR_SMASK
739static struct flag_table rxe_err_status_flags[] = {
740/* 0*/ FLAG_ENTRY0("RxDmaCsrCorErr", RXES(DMA_CSR_COR)),
741/* 1*/ FLAG_ENTRY0("RxDcIntfParityErr", RXES(DC_INTF_PARITY)),
742/* 2*/ FLAG_ENTRY0("RxRcvHdrUncErr", RXES(RCV_HDR_UNC)),
743/* 3*/ FLAG_ENTRY0("RxRcvHdrCorErr", RXES(RCV_HDR_COR)),
744/* 4*/ FLAG_ENTRY0("RxRcvDataUncErr", RXES(RCV_DATA_UNC)),
745/* 5*/ FLAG_ENTRY0("RxRcvDataCorErr", RXES(RCV_DATA_COR)),
746/* 6*/ FLAG_ENTRY0("RxRcvQpMapTableUncErr", RXES(RCV_QP_MAP_TABLE_UNC)),
747/* 7*/ FLAG_ENTRY0("RxRcvQpMapTableCorErr", RXES(RCV_QP_MAP_TABLE_COR)),
748/* 8*/ FLAG_ENTRY0("RxRcvCsrParityErr", RXES(RCV_CSR_PARITY)),
749/* 9*/ FLAG_ENTRY0("RxDcSopEopParityErr", RXES(DC_SOP_EOP_PARITY)),
750/*10*/ FLAG_ENTRY0("RxDmaFlagUncErr", RXES(DMA_FLAG_UNC)),
751/*11*/ FLAG_ENTRY0("RxDmaFlagCorErr", RXES(DMA_FLAG_COR)),
752/*12*/ FLAG_ENTRY0("RxRcvFsmEncodingErr", RXES(RCV_FSM_ENCODING)),
753/*13*/ FLAG_ENTRY0("RxRbufFreeListUncErr", RXES(RBUF_FREE_LIST_UNC)),
754/*14*/ FLAG_ENTRY0("RxRbufFreeListCorErr", RXES(RBUF_FREE_LIST_COR)),
755/*15*/ FLAG_ENTRY0("RxRbufLookupDesRegUncErr", RXES(RBUF_LOOKUP_DES_REG_UNC)),
756/*16*/ FLAG_ENTRY0("RxRbufLookupDesRegUncCorErr",
757 RXES(RBUF_LOOKUP_DES_REG_UNC_COR)),
758/*17*/ FLAG_ENTRY0("RxRbufLookupDesUncErr", RXES(RBUF_LOOKUP_DES_UNC)),
759/*18*/ FLAG_ENTRY0("RxRbufLookupDesCorErr", RXES(RBUF_LOOKUP_DES_COR)),
760/*19*/ FLAG_ENTRY0("RxRbufBlockListReadUncErr",
761 RXES(RBUF_BLOCK_LIST_READ_UNC)),
762/*20*/ FLAG_ENTRY0("RxRbufBlockListReadCorErr",
763 RXES(RBUF_BLOCK_LIST_READ_COR)),
764/*21*/ FLAG_ENTRY0("RxRbufCsrQHeadBufNumParityErr",
765 RXES(RBUF_CSR_QHEAD_BUF_NUM_PARITY)),
766/*22*/ FLAG_ENTRY0("RxRbufCsrQEntCntParityErr",
767 RXES(RBUF_CSR_QENT_CNT_PARITY)),
768/*23*/ FLAG_ENTRY0("RxRbufCsrQNextBufParityErr",
769 RXES(RBUF_CSR_QNEXT_BUF_PARITY)),
770/*24*/ FLAG_ENTRY0("RxRbufCsrQVldBitParityErr",
771 RXES(RBUF_CSR_QVLD_BIT_PARITY)),
772/*25*/ FLAG_ENTRY0("RxRbufCsrQHdPtrParityErr", RXES(RBUF_CSR_QHD_PTR_PARITY)),
773/*26*/ FLAG_ENTRY0("RxRbufCsrQTlPtrParityErr", RXES(RBUF_CSR_QTL_PTR_PARITY)),
774/*27*/ FLAG_ENTRY0("RxRbufCsrQNumOfPktParityErr",
775 RXES(RBUF_CSR_QNUM_OF_PKT_PARITY)),
776/*28*/ FLAG_ENTRY0("RxRbufCsrQEOPDWParityErr", RXES(RBUF_CSR_QEOPDW_PARITY)),
777/*29*/ FLAG_ENTRY0("RxRbufCtxIdParityErr", RXES(RBUF_CTX_ID_PARITY)),
778/*30*/ FLAG_ENTRY0("RxRBufBadLookupErr", RXES(RBUF_BAD_LOOKUP)),
779/*31*/ FLAG_ENTRY0("RxRbufFullErr", RXES(RBUF_FULL)),
780/*32*/ FLAG_ENTRY0("RxRbufEmptyErr", RXES(RBUF_EMPTY)),
781/*33*/ FLAG_ENTRY0("RxRbufFlRdAddrParityErr", RXES(RBUF_FL_RD_ADDR_PARITY)),
782/*34*/ FLAG_ENTRY0("RxRbufFlWrAddrParityErr", RXES(RBUF_FL_WR_ADDR_PARITY)),
783/*35*/ FLAG_ENTRY0("RxRbufFlInitdoneParityErr",
784 RXES(RBUF_FL_INITDONE_PARITY)),
785/*36*/ FLAG_ENTRY0("RxRbufFlInitWrAddrParityErr",
786 RXES(RBUF_FL_INIT_WR_ADDR_PARITY)),
787/*37*/ FLAG_ENTRY0("RxRbufNextFreeBufUncErr", RXES(RBUF_NEXT_FREE_BUF_UNC)),
788/*38*/ FLAG_ENTRY0("RxRbufNextFreeBufCorErr", RXES(RBUF_NEXT_FREE_BUF_COR)),
789/*39*/ FLAG_ENTRY0("RxLookupDesPart1UncErr", RXES(LOOKUP_DES_PART1_UNC)),
790/*40*/ FLAG_ENTRY0("RxLookupDesPart1UncCorErr",
791 RXES(LOOKUP_DES_PART1_UNC_COR)),
792/*41*/ FLAG_ENTRY0("RxLookupDesPart2ParityErr",
793 RXES(LOOKUP_DES_PART2_PARITY)),
794/*42*/ FLAG_ENTRY0("RxLookupRcvArrayUncErr", RXES(LOOKUP_RCV_ARRAY_UNC)),
795/*43*/ FLAG_ENTRY0("RxLookupRcvArrayCorErr", RXES(LOOKUP_RCV_ARRAY_COR)),
796/*44*/ FLAG_ENTRY0("RxLookupCsrParityErr", RXES(LOOKUP_CSR_PARITY)),
797/*45*/ FLAG_ENTRY0("RxHqIntrCsrParityErr", RXES(HQ_INTR_CSR_PARITY)),
798/*46*/ FLAG_ENTRY0("RxHqIntrFsmErr", RXES(HQ_INTR_FSM)),
799/*47*/ FLAG_ENTRY0("RxRbufDescPart1UncErr", RXES(RBUF_DESC_PART1_UNC)),
800/*48*/ FLAG_ENTRY0("RxRbufDescPart1CorErr", RXES(RBUF_DESC_PART1_COR)),
801/*49*/ FLAG_ENTRY0("RxRbufDescPart2UncErr", RXES(RBUF_DESC_PART2_UNC)),
802/*50*/ FLAG_ENTRY0("RxRbufDescPart2CorErr", RXES(RBUF_DESC_PART2_COR)),
803/*51*/ FLAG_ENTRY0("RxDmaHdrFifoRdUncErr", RXES(DMA_HDR_FIFO_RD_UNC)),
804/*52*/ FLAG_ENTRY0("RxDmaHdrFifoRdCorErr", RXES(DMA_HDR_FIFO_RD_COR)),
805/*53*/ FLAG_ENTRY0("RxDmaDataFifoRdUncErr", RXES(DMA_DATA_FIFO_RD_UNC)),
806/*54*/ FLAG_ENTRY0("RxDmaDataFifoRdCorErr", RXES(DMA_DATA_FIFO_RD_COR)),
807/*55*/ FLAG_ENTRY0("RxRbufDataUncErr", RXES(RBUF_DATA_UNC)),
808/*56*/ FLAG_ENTRY0("RxRbufDataCorErr", RXES(RBUF_DATA_COR)),
809/*57*/ FLAG_ENTRY0("RxDmaCsrParityErr", RXES(DMA_CSR_PARITY)),
810/*58*/ FLAG_ENTRY0("RxDmaEqFsmEncodingErr", RXES(DMA_EQ_FSM_ENCODING)),
811/*59*/ FLAG_ENTRY0("RxDmaDqFsmEncodingErr", RXES(DMA_DQ_FSM_ENCODING)),
812/*60*/ FLAG_ENTRY0("RxDmaCsrUncErr", RXES(DMA_CSR_UNC)),
813/*61*/ FLAG_ENTRY0("RxCsrReadBadAddrErr", RXES(CSR_READ_BAD_ADDR)),
814/*62*/ FLAG_ENTRY0("RxCsrWriteBadAddrErr", RXES(CSR_WRITE_BAD_ADDR)),
815/*63*/ FLAG_ENTRY0("RxCsrParityErr", RXES(CSR_PARITY))
816};
817
818/* RXE errors that will trigger an SPC freeze */
819#define ALL_RXE_FREEZE_ERR \
820 (RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_UNC_ERR_SMASK \
821 | RCV_ERR_STATUS_RX_RCV_CSR_PARITY_ERR_SMASK \
822 | RCV_ERR_STATUS_RX_DMA_FLAG_UNC_ERR_SMASK \
823 | RCV_ERR_STATUS_RX_RCV_FSM_ENCODING_ERR_SMASK \
824 | RCV_ERR_STATUS_RX_RBUF_FREE_LIST_UNC_ERR_SMASK \
825 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_ERR_SMASK \
826 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR_SMASK \
827 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_UNC_ERR_SMASK \
828 | RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_UNC_ERR_SMASK \
829 | RCV_ERR_STATUS_RX_RBUF_CSR_QHEAD_BUF_NUM_PARITY_ERR_SMASK \
830 | RCV_ERR_STATUS_RX_RBUF_CSR_QENT_CNT_PARITY_ERR_SMASK \
831 | RCV_ERR_STATUS_RX_RBUF_CSR_QNEXT_BUF_PARITY_ERR_SMASK \
832 | RCV_ERR_STATUS_RX_RBUF_CSR_QVLD_BIT_PARITY_ERR_SMASK \
833 | RCV_ERR_STATUS_RX_RBUF_CSR_QHD_PTR_PARITY_ERR_SMASK \
834 | RCV_ERR_STATUS_RX_RBUF_CSR_QTL_PTR_PARITY_ERR_SMASK \
835 | RCV_ERR_STATUS_RX_RBUF_CSR_QNUM_OF_PKT_PARITY_ERR_SMASK \
836 | RCV_ERR_STATUS_RX_RBUF_CSR_QEOPDW_PARITY_ERR_SMASK \
837 | RCV_ERR_STATUS_RX_RBUF_CTX_ID_PARITY_ERR_SMASK \
838 | RCV_ERR_STATUS_RX_RBUF_BAD_LOOKUP_ERR_SMASK \
839 | RCV_ERR_STATUS_RX_RBUF_FULL_ERR_SMASK \
840 | RCV_ERR_STATUS_RX_RBUF_EMPTY_ERR_SMASK \
841 | RCV_ERR_STATUS_RX_RBUF_FL_RD_ADDR_PARITY_ERR_SMASK \
842 | RCV_ERR_STATUS_RX_RBUF_FL_WR_ADDR_PARITY_ERR_SMASK \
843 | RCV_ERR_STATUS_RX_RBUF_FL_INITDONE_PARITY_ERR_SMASK \
844 | RCV_ERR_STATUS_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR_SMASK \
845 | RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_UNC_ERR_SMASK \
846 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_ERR_SMASK \
847 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_COR_ERR_SMASK \
848 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART2_PARITY_ERR_SMASK \
849 | RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_UNC_ERR_SMASK \
850 | RCV_ERR_STATUS_RX_LOOKUP_CSR_PARITY_ERR_SMASK \
851 | RCV_ERR_STATUS_RX_HQ_INTR_CSR_PARITY_ERR_SMASK \
852 | RCV_ERR_STATUS_RX_HQ_INTR_FSM_ERR_SMASK \
853 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_UNC_ERR_SMASK \
854 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_COR_ERR_SMASK \
855 | RCV_ERR_STATUS_RX_RBUF_DESC_PART2_UNC_ERR_SMASK \
856 | RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK \
857 | RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK \
858 | RCV_ERR_STATUS_RX_RBUF_DATA_UNC_ERR_SMASK \
859 | RCV_ERR_STATUS_RX_DMA_CSR_PARITY_ERR_SMASK \
860 | RCV_ERR_STATUS_RX_DMA_EQ_FSM_ENCODING_ERR_SMASK \
861 | RCV_ERR_STATUS_RX_DMA_DQ_FSM_ENCODING_ERR_SMASK \
862 | RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK \
863 | RCV_ERR_STATUS_RX_CSR_PARITY_ERR_SMASK)
864
865#define RXE_FREEZE_ABORT_MASK \
866 (RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK | \
867 RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK | \
868 RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK)
869
870/*
871 * DCC Error Flags
872 */
873#define DCCE(name) DCC_ERR_FLG_##name##_SMASK
874static struct flag_table dcc_err_flags[] = {
875 FLAG_ENTRY0("bad_l2_err", DCCE(BAD_L2_ERR)),
876 FLAG_ENTRY0("bad_sc_err", DCCE(BAD_SC_ERR)),
877 FLAG_ENTRY0("bad_mid_tail_err", DCCE(BAD_MID_TAIL_ERR)),
878 FLAG_ENTRY0("bad_preemption_err", DCCE(BAD_PREEMPTION_ERR)),
879 FLAG_ENTRY0("preemption_err", DCCE(PREEMPTION_ERR)),
880 FLAG_ENTRY0("preemptionvl15_err", DCCE(PREEMPTIONVL15_ERR)),
881 FLAG_ENTRY0("bad_vl_marker_err", DCCE(BAD_VL_MARKER_ERR)),
882 FLAG_ENTRY0("bad_dlid_target_err", DCCE(BAD_DLID_TARGET_ERR)),
883 FLAG_ENTRY0("bad_lver_err", DCCE(BAD_LVER_ERR)),
884 FLAG_ENTRY0("uncorrectable_err", DCCE(UNCORRECTABLE_ERR)),
885 FLAG_ENTRY0("bad_crdt_ack_err", DCCE(BAD_CRDT_ACK_ERR)),
886 FLAG_ENTRY0("unsup_pkt_type", DCCE(UNSUP_PKT_TYPE)),
887 FLAG_ENTRY0("bad_ctrl_flit_err", DCCE(BAD_CTRL_FLIT_ERR)),
888 FLAG_ENTRY0("event_cntr_parity_err", DCCE(EVENT_CNTR_PARITY_ERR)),
889 FLAG_ENTRY0("event_cntr_rollover_err", DCCE(EVENT_CNTR_ROLLOVER_ERR)),
890 FLAG_ENTRY0("link_err", DCCE(LINK_ERR)),
891 FLAG_ENTRY0("misc_cntr_rollover_err", DCCE(MISC_CNTR_ROLLOVER_ERR)),
892 FLAG_ENTRY0("bad_ctrl_dist_err", DCCE(BAD_CTRL_DIST_ERR)),
893 FLAG_ENTRY0("bad_tail_dist_err", DCCE(BAD_TAIL_DIST_ERR)),
894 FLAG_ENTRY0("bad_head_dist_err", DCCE(BAD_HEAD_DIST_ERR)),
895 FLAG_ENTRY0("nonvl15_state_err", DCCE(NONVL15_STATE_ERR)),
896 FLAG_ENTRY0("vl15_multi_err", DCCE(VL15_MULTI_ERR)),
897 FLAG_ENTRY0("bad_pkt_length_err", DCCE(BAD_PKT_LENGTH_ERR)),
898 FLAG_ENTRY0("unsup_vl_err", DCCE(UNSUP_VL_ERR)),
899 FLAG_ENTRY0("perm_nvl15_err", DCCE(PERM_NVL15_ERR)),
900 FLAG_ENTRY0("slid_zero_err", DCCE(SLID_ZERO_ERR)),
901 FLAG_ENTRY0("dlid_zero_err", DCCE(DLID_ZERO_ERR)),
902 FLAG_ENTRY0("length_mtu_err", DCCE(LENGTH_MTU_ERR)),
903 FLAG_ENTRY0("rx_early_drop_err", DCCE(RX_EARLY_DROP_ERR)),
904 FLAG_ENTRY0("late_short_err", DCCE(LATE_SHORT_ERR)),
905 FLAG_ENTRY0("late_long_err", DCCE(LATE_LONG_ERR)),
906 FLAG_ENTRY0("late_ebp_err", DCCE(LATE_EBP_ERR)),
907 FLAG_ENTRY0("fpe_tx_fifo_ovflw_err", DCCE(FPE_TX_FIFO_OVFLW_ERR)),
908 FLAG_ENTRY0("fpe_tx_fifo_unflw_err", DCCE(FPE_TX_FIFO_UNFLW_ERR)),
909 FLAG_ENTRY0("csr_access_blocked_host", DCCE(CSR_ACCESS_BLOCKED_HOST)),
910 FLAG_ENTRY0("csr_access_blocked_uc", DCCE(CSR_ACCESS_BLOCKED_UC)),
911 FLAG_ENTRY0("tx_ctrl_parity_err", DCCE(TX_CTRL_PARITY_ERR)),
912 FLAG_ENTRY0("tx_ctrl_parity_mbe_err", DCCE(TX_CTRL_PARITY_MBE_ERR)),
913 FLAG_ENTRY0("tx_sc_parity_err", DCCE(TX_SC_PARITY_ERR)),
914 FLAG_ENTRY0("rx_ctrl_parity_mbe_err", DCCE(RX_CTRL_PARITY_MBE_ERR)),
915 FLAG_ENTRY0("csr_parity_err", DCCE(CSR_PARITY_ERR)),
916 FLAG_ENTRY0("csr_inval_addr", DCCE(CSR_INVAL_ADDR)),
917 FLAG_ENTRY0("tx_byte_shft_parity_err", DCCE(TX_BYTE_SHFT_PARITY_ERR)),
918 FLAG_ENTRY0("rx_byte_shft_parity_err", DCCE(RX_BYTE_SHFT_PARITY_ERR)),
919 FLAG_ENTRY0("fmconfig_err", DCCE(FMCONFIG_ERR)),
920 FLAG_ENTRY0("rcvport_err", DCCE(RCVPORT_ERR)),
921};
922
923/*
924 * LCB error flags
925 */
926#define LCBE(name) DC_LCB_ERR_FLG_##name##_SMASK
927static struct flag_table lcb_err_flags[] = {
928/* 0*/ FLAG_ENTRY0("CSR_PARITY_ERR", LCBE(CSR_PARITY_ERR)),
929/* 1*/ FLAG_ENTRY0("INVALID_CSR_ADDR", LCBE(INVALID_CSR_ADDR)),
930/* 2*/ FLAG_ENTRY0("RST_FOR_FAILED_DESKEW", LCBE(RST_FOR_FAILED_DESKEW)),
931/* 3*/ FLAG_ENTRY0("ALL_LNS_FAILED_REINIT_TEST",
932 LCBE(ALL_LNS_FAILED_REINIT_TEST)),
933/* 4*/ FLAG_ENTRY0("LOST_REINIT_STALL_OR_TOS", LCBE(LOST_REINIT_STALL_OR_TOS)),
934/* 5*/ FLAG_ENTRY0("TX_LESS_THAN_FOUR_LNS", LCBE(TX_LESS_THAN_FOUR_LNS)),
935/* 6*/ FLAG_ENTRY0("RX_LESS_THAN_FOUR_LNS", LCBE(RX_LESS_THAN_FOUR_LNS)),
936/* 7*/ FLAG_ENTRY0("SEQ_CRC_ERR", LCBE(SEQ_CRC_ERR)),
937/* 8*/ FLAG_ENTRY0("REINIT_FROM_PEER", LCBE(REINIT_FROM_PEER)),
938/* 9*/ FLAG_ENTRY0("REINIT_FOR_LN_DEGRADE", LCBE(REINIT_FOR_LN_DEGRADE)),
939/*10*/ FLAG_ENTRY0("CRC_ERR_CNT_HIT_LIMIT", LCBE(CRC_ERR_CNT_HIT_LIMIT)),
940/*11*/ FLAG_ENTRY0("RCLK_STOPPED", LCBE(RCLK_STOPPED)),
941/*12*/ FLAG_ENTRY0("UNEXPECTED_REPLAY_MARKER", LCBE(UNEXPECTED_REPLAY_MARKER)),
942/*13*/ FLAG_ENTRY0("UNEXPECTED_ROUND_TRIP_MARKER",
943 LCBE(UNEXPECTED_ROUND_TRIP_MARKER)),
944/*14*/ FLAG_ENTRY0("ILLEGAL_NULL_LTP", LCBE(ILLEGAL_NULL_LTP)),
945/*15*/ FLAG_ENTRY0("ILLEGAL_FLIT_ENCODING", LCBE(ILLEGAL_FLIT_ENCODING)),
946/*16*/ FLAG_ENTRY0("FLIT_INPUT_BUF_OFLW", LCBE(FLIT_INPUT_BUF_OFLW)),
947/*17*/ FLAG_ENTRY0("VL_ACK_INPUT_BUF_OFLW", LCBE(VL_ACK_INPUT_BUF_OFLW)),
948/*18*/ FLAG_ENTRY0("VL_ACK_INPUT_PARITY_ERR", LCBE(VL_ACK_INPUT_PARITY_ERR)),
949/*19*/ FLAG_ENTRY0("VL_ACK_INPUT_WRONG_CRC_MODE",
950 LCBE(VL_ACK_INPUT_WRONG_CRC_MODE)),
951/*20*/ FLAG_ENTRY0("FLIT_INPUT_BUF_MBE", LCBE(FLIT_INPUT_BUF_MBE)),
952/*21*/ FLAG_ENTRY0("FLIT_INPUT_BUF_SBE", LCBE(FLIT_INPUT_BUF_SBE)),
953/*22*/ FLAG_ENTRY0("REPLAY_BUF_MBE", LCBE(REPLAY_BUF_MBE)),
954/*23*/ FLAG_ENTRY0("REPLAY_BUF_SBE", LCBE(REPLAY_BUF_SBE)),
955/*24*/ FLAG_ENTRY0("CREDIT_RETURN_FLIT_MBE", LCBE(CREDIT_RETURN_FLIT_MBE)),
956/*25*/ FLAG_ENTRY0("RST_FOR_LINK_TIMEOUT", LCBE(RST_FOR_LINK_TIMEOUT)),
957/*26*/ FLAG_ENTRY0("RST_FOR_INCOMPLT_RND_TRIP",
958 LCBE(RST_FOR_INCOMPLT_RND_TRIP)),
959/*27*/ FLAG_ENTRY0("HOLD_REINIT", LCBE(HOLD_REINIT)),
960/*28*/ FLAG_ENTRY0("NEG_EDGE_LINK_TRANSFER_ACTIVE",
961 LCBE(NEG_EDGE_LINK_TRANSFER_ACTIVE)),
962/*29*/ FLAG_ENTRY0("REDUNDANT_FLIT_PARITY_ERR",
963 LCBE(REDUNDANT_FLIT_PARITY_ERR))
964};
965
966/*
967 * DC8051 Error Flags
968 */
969#define D8E(name) DC_DC8051_ERR_FLG_##name##_SMASK
970static struct flag_table dc8051_err_flags[] = {
971 FLAG_ENTRY0("SET_BY_8051", D8E(SET_BY_8051)),
972 FLAG_ENTRY0("LOST_8051_HEART_BEAT", D8E(LOST_8051_HEART_BEAT)),
973 FLAG_ENTRY0("CRAM_MBE", D8E(CRAM_MBE)),
974 FLAG_ENTRY0("CRAM_SBE", D8E(CRAM_SBE)),
975 FLAG_ENTRY0("DRAM_MBE", D8E(DRAM_MBE)),
976 FLAG_ENTRY0("DRAM_SBE", D8E(DRAM_SBE)),
977 FLAG_ENTRY0("IRAM_MBE", D8E(IRAM_MBE)),
978 FLAG_ENTRY0("IRAM_SBE", D8E(IRAM_SBE)),
979 FLAG_ENTRY0("UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES",
17fb4f29 980 D8E(UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES)),
77241056
MM		 981 FLAG_ENTRY0("INVALID_CSR_ADDR", D8E(INVALID_CSR_ADDR)),
982};
983
984/*
985 * DC8051 Information Error flags
986 *
987 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.ERROR field.
988 */
989static struct flag_table dc8051_info_err_flags[] = {
990 FLAG_ENTRY0("Spico ROM check failed", SPICO_ROM_FAILED),
991 FLAG_ENTRY0("Unknown frame received", UNKNOWN_FRAME),
992 FLAG_ENTRY0("Target BER not met", TARGET_BER_NOT_MET),
993 FLAG_ENTRY0("Serdes internal loopback failure",
17fb4f29 994 FAILED_SERDES_INTERNAL_LOOPBACK),
77241056
MM		 995 FLAG_ENTRY0("Failed SerDes init", FAILED_SERDES_INIT),
996 FLAG_ENTRY0("Failed LNI(Polling)", FAILED_LNI_POLLING),
997 FLAG_ENTRY0("Failed LNI(Debounce)", FAILED_LNI_DEBOUNCE),
998 FLAG_ENTRY0("Failed LNI(EstbComm)", FAILED_LNI_ESTBCOMM),
999 FLAG_ENTRY0("Failed LNI(OptEq)", FAILED_LNI_OPTEQ),
1000 FLAG_ENTRY0("Failed LNI(VerifyCap_1)", FAILED_LNI_VERIFY_CAP1),
1001 FLAG_ENTRY0("Failed LNI(VerifyCap_2)", FAILED_LNI_VERIFY_CAP2),
8fefef12 1002 FLAG_ENTRY0("Failed LNI(ConfigLT)", FAILED_LNI_CONFIGLT),
50921be0
DL		 1003 FLAG_ENTRY0("Host Handshake Timeout", HOST_HANDSHAKE_TIMEOUT),
1004 FLAG_ENTRY0("External Device Request Timeout",
1005 EXTERNAL_DEVICE_REQ_TIMEOUT),
77241056
MM		 1006};
1007
1008/*
1009 * DC8051 Information Host Information flags
1010 *
1011 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.HOST_MSG field.
1012 */
1013static struct flag_table dc8051_info_host_msg_flags[] = {
1014 FLAG_ENTRY0("Host request done", 0x0001),
1015 FLAG_ENTRY0("BC SMA message", 0x0002),
1016 FLAG_ENTRY0("BC PWR_MGM message", 0x0004),
1017 FLAG_ENTRY0("BC Unknown message (BCC)", 0x0008),
1018 FLAG_ENTRY0("BC Unknown message (LCB)", 0x0010),
1019 FLAG_ENTRY0("External device config request", 0x0020),
1020 FLAG_ENTRY0("VerifyCap all frames received", 0x0040),
1021 FLAG_ENTRY0("LinkUp achieved", 0x0080),
1022 FLAG_ENTRY0("Link going down", 0x0100),
1023};
1024
77241056
MM		 1025static u32 encoded_size(u32 size);
1026static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate);
1027static int set_physical_link_state(struct hfi1_devdata *dd, u64 state);
1028static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management,
1029 u8 *continuous);
1030static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z,
1031 u8 *vcu, u16 *vl15buf, u8 *crc_sizes);
1032static void read_vc_remote_link_width(struct hfi1_devdata *dd,
1033 u8 *remote_tx_rate, u16 *link_widths);
1034static void read_vc_local_link_width(struct hfi1_devdata *dd, u8 *misc_bits,
1035 u8 *flag_bits, u16 *link_widths);
1036static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id,
1037 u8 *device_rev);
1038static void read_mgmt_allowed(struct hfi1_devdata *dd, u8 *mgmt_allowed);
1039static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx);
1040static int read_tx_settings(struct hfi1_devdata *dd, u8 *enable_lane_tx,
1041 u8 *tx_polarity_inversion,
1042 u8 *rx_polarity_inversion, u8 *max_rate);
1043static void handle_sdma_eng_err(struct hfi1_devdata *dd,
1044 unsigned int context, u64 err_status);
1045static void handle_qsfp_int(struct hfi1_devdata *dd, u32 source, u64 reg);
1046static void handle_dcc_err(struct hfi1_devdata *dd,
1047 unsigned int context, u64 err_status);
1048static void handle_lcb_err(struct hfi1_devdata *dd,
1049 unsigned int context, u64 err_status);
1050static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg);
1051static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1052static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1053static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1054static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1055static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1056static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1057static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
f4cd8765 1058static void set_partition_keys(struct hfi1_pportdata *ppd);
77241056
MM		 1059static const char *link_state_name(u32 state);
1060static const char *link_state_reason_name(struct hfi1_pportdata *ppd,
1061 u32 state);
1062static int do_8051_command(struct hfi1_devdata *dd, u32 type, u64 in_data,
1063 u64 *out_data);
1064static int read_idle_sma(struct hfi1_devdata *dd, u64 *data);
1065static int thermal_init(struct hfi1_devdata *dd);
1066
1067static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state,
1068 int msecs);
1069static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc);
feb831dd 1070static void read_link_down_reason(struct hfi1_devdata *dd, u8 *ldr);
f4cd8765
MR		 1071static void handle_temp_err(struct hfi1_devdata *dd);
1072static void dc_shutdown(struct hfi1_devdata *dd);
1073static void dc_start(struct hfi1_devdata *dd);
8f000f7f
DL		 1074static int qos_rmt_entries(struct hfi1_devdata *dd, unsigned int *mp,
1075 unsigned int *np);
3ec5fa28 1076static void clear_full_mgmt_pkey(struct hfi1_pportdata *ppd);
ec8a1423 1077static int wait_link_transfer_active(struct hfi1_devdata *dd, int wait_ms);
2280740f 1078static void clear_rsm_rule(struct hfi1_devdata *dd, u8 rule_index);
77241056
MM		 1079
1080/*
1081 * Error interrupt table entry. This is used as input to the interrupt
1082 * "clear down" routine used for all second tier error interrupt register.
1083 * Second tier interrupt registers have a single bit representing them
1084 * in the top-level CceIntStatus.
1085 */
1086struct err_reg_info {
1087 u32 status; /* status CSR offset */
1088 u32 clear; /* clear CSR offset */
1089 u32 mask; /* mask CSR offset */
1090 void (*handler)(struct hfi1_devdata *dd, u32 source, u64 reg);
1091 const char *desc;
1092};
1093
1094#define NUM_MISC_ERRS (IS_GENERAL_ERR_END - IS_GENERAL_ERR_START)
1095#define NUM_DC_ERRS (IS_DC_END - IS_DC_START)
1096#define NUM_VARIOUS (IS_VARIOUS_END - IS_VARIOUS_START)
1097
1098/*
1099 * Helpers for building HFI and DC error interrupt table entries. Different
1100 * helpers are needed because of inconsistent register names.
1101 */
1102#define EE(reg, handler, desc) \
1103 { reg##_STATUS, reg##_CLEAR, reg##_MASK, \
1104 handler, desc }
1105#define DC_EE1(reg, handler, desc) \
1106 { reg##_FLG, reg##_FLG_CLR, reg##_FLG_EN, handler, desc }
1107#define DC_EE2(reg, handler, desc) \
1108 { reg##_FLG, reg##_CLR, reg##_EN, handler, desc }
1109
1110/*
1111 * Table of the "misc" grouping of error interrupts. Each entry refers to
1112 * another register containing more information.
1113 */
1114static const struct err_reg_info misc_errs[NUM_MISC_ERRS] = {
1115/* 0*/ EE(CCE_ERR, handle_cce_err, "CceErr"),
1116/* 1*/ EE(RCV_ERR, handle_rxe_err, "RxeErr"),
1117/* 2*/ EE(MISC_ERR, handle_misc_err, "MiscErr"),
1118/* 3*/ { 0, 0, 0, NULL }, /* reserved */
1119/* 4*/ EE(SEND_PIO_ERR, handle_pio_err, "PioErr"),
1120/* 5*/ EE(SEND_DMA_ERR, handle_sdma_err, "SDmaErr"),
1121/* 6*/ EE(SEND_EGRESS_ERR, handle_egress_err, "EgressErr"),
1122/* 7*/ EE(SEND_ERR, handle_txe_err, "TxeErr")
1123 /* the rest are reserved */
1124};
1125
1126/*
1127 * Index into the Various section of the interrupt sources
1128 * corresponding to the Critical Temperature interrupt.
1129 */
1130#define TCRIT_INT_SOURCE 4
1131
1132/*
1133 * SDMA error interrupt entry - refers to another register containing more
1134 * information.
1135 */
1136static const struct err_reg_info sdma_eng_err =
1137 EE(SEND_DMA_ENG_ERR, handle_sdma_eng_err, "SDmaEngErr");
1138
1139static const struct err_reg_info various_err[NUM_VARIOUS] = {
1140/* 0*/ { 0, 0, 0, NULL }, /* PbcInt */
1141/* 1*/ { 0, 0, 0, NULL }, /* GpioAssertInt */
1142/* 2*/ EE(ASIC_QSFP1, handle_qsfp_int, "QSFP1"),
1143/* 3*/ EE(ASIC_QSFP2, handle_qsfp_int, "QSFP2"),
1144/* 4*/ { 0, 0, 0, NULL }, /* TCritInt */
1145 /* rest are reserved */
1146};
1147
1148/*
1149 * The DC encoding of mtu_cap for 10K MTU in the DCC_CFG_PORT_CONFIG
1150 * register can not be derived from the MTU value because 10K is not
1151 * a power of 2. Therefore, we need a constant. Everything else can
1152 * be calculated.
1153 */
1154#define DCC_CFG_PORT_MTU_CAP_10240 7
1155
1156/*
1157 * Table of the DC grouping of error interrupts. Each entry refers to
1158 * another register containing more information.
1159 */
1160static const struct err_reg_info dc_errs[NUM_DC_ERRS] = {
1161/* 0*/ DC_EE1(DCC_ERR, handle_dcc_err, "DCC Err"),
1162/* 1*/ DC_EE2(DC_LCB_ERR, handle_lcb_err, "LCB Err"),
1163/* 2*/ DC_EE2(DC_DC8051_ERR, handle_8051_interrupt, "DC8051 Interrupt"),
1164/* 3*/ /* dc_lbm_int - special, see is_dc_int() */
1165 /* the rest are reserved */
1166};
1167
1168struct cntr_entry {
1169 /*
1170 * counter name
1171 */
1172 char *name;
1173
1174 /*
1175 * csr to read for name (if applicable)
1176 */
1177 u64 csr;
1178
1179 /*
1180 * offset into dd or ppd to store the counter's value
1181 */
1182 int offset;
1183
1184 /*
1185 * flags
1186 */
1187 u8 flags;
1188
1189 /*
1190 * accessor for stat element, context either dd or ppd
1191 */
17fb4f29
JJ		 1192 u64 (*rw_cntr)(const struct cntr_entry *, void *context, int vl,
1193 int mode, u64 data);
77241056
MM		 1194};
1195
1196#define C_RCV_HDR_OVF_FIRST C_RCV_HDR_OVF_0
1197#define C_RCV_HDR_OVF_LAST C_RCV_HDR_OVF_159
1198
1199#define CNTR_ELEM(name, csr, offset, flags, accessor) \
1200{ \
1201 name, \
1202 csr, \
1203 offset, \
1204 flags, \
1205 accessor \
1206}
1207
1208/* 32bit RXE */
1209#define RXE32_PORT_CNTR_ELEM(name, counter, flags) \
1210CNTR_ELEM(#name, \
1211 (counter * 8 + RCV_COUNTER_ARRAY32), \
1212 0, flags | CNTR_32BIT, \
1213 port_access_u32_csr)
1214
1215#define RXE32_DEV_CNTR_ELEM(name, counter, flags) \
1216CNTR_ELEM(#name, \
1217 (counter * 8 + RCV_COUNTER_ARRAY32), \
1218 0, flags | CNTR_32BIT, \
1219 dev_access_u32_csr)
1220
1221/* 64bit RXE */
1222#define RXE64_PORT_CNTR_ELEM(name, counter, flags) \
1223CNTR_ELEM(#name, \
1224 (counter * 8 + RCV_COUNTER_ARRAY64), \
1225 0, flags, \
1226 port_access_u64_csr)
1227
1228#define RXE64_DEV_CNTR_ELEM(name, counter, flags) \
1229CNTR_ELEM(#name, \
1230 (counter * 8 + RCV_COUNTER_ARRAY64), \
1231 0, flags, \
1232 dev_access_u64_csr)
1233
1234#define OVR_LBL(ctx) C_RCV_HDR_OVF_ ## ctx
1235#define OVR_ELM(ctx) \
1236CNTR_ELEM("RcvHdrOvr" #ctx, \
8638b77f 1237 (RCV_HDR_OVFL_CNT + ctx * 0x100), \
77241056
MM		 1238 0, CNTR_NORMAL, port_access_u64_csr)
1239
1240/* 32bit TXE */
1241#define TXE32_PORT_CNTR_ELEM(name, counter, flags) \
1242CNTR_ELEM(#name, \
1243 (counter * 8 + SEND_COUNTER_ARRAY32), \
1244 0, flags | CNTR_32BIT, \
1245 port_access_u32_csr)
1246
1247/* 64bit TXE */
1248#define TXE64_PORT_CNTR_ELEM(name, counter, flags) \
1249CNTR_ELEM(#name, \
1250 (counter * 8 + SEND_COUNTER_ARRAY64), \
1251 0, flags, \
1252 port_access_u64_csr)
1253
1254# define TX64_DEV_CNTR_ELEM(name, counter, flags) \
1255CNTR_ELEM(#name,\
1256 counter * 8 + SEND_COUNTER_ARRAY64, \
1257 0, \
1258 flags, \
1259 dev_access_u64_csr)
1260
1261/* CCE */
1262#define CCE_PERF_DEV_CNTR_ELEM(name, counter, flags) \
1263CNTR_ELEM(#name, \
1264 (counter * 8 + CCE_COUNTER_ARRAY32), \
1265 0, flags | CNTR_32BIT, \
1266 dev_access_u32_csr)
1267
1268#define CCE_INT_DEV_CNTR_ELEM(name, counter, flags) \
1269CNTR_ELEM(#name, \
1270 (counter * 8 + CCE_INT_COUNTER_ARRAY32), \
1271 0, flags | CNTR_32BIT, \
1272 dev_access_u32_csr)
1273
1274/* DC */
1275#define DC_PERF_CNTR(name, counter, flags) \
1276CNTR_ELEM(#name, \
1277 counter, \
1278 0, \
1279 flags, \
1280 dev_access_u64_csr)
1281
1282#define DC_PERF_CNTR_LCB(name, counter, flags) \
1283CNTR_ELEM(#name, \
1284 counter, \
1285 0, \
1286 flags, \
1287 dc_access_lcb_cntr)
1288
1289/* ibp counters */
1290#define SW_IBP_CNTR(name, cntr) \
1291CNTR_ELEM(#name, \
1292 0, \
1293 0, \
1294 CNTR_SYNTH, \
1295 access_ibp_##cntr)
1296
1297u64 read_csr(const struct hfi1_devdata *dd, u32 offset)
1298{
77241056 1299 if (dd->flags & HFI1_PRESENT) {
6d210eef 1300 return readq((void __iomem *)dd->kregbase + offset);
77241056
MM		 1301 }
1302 return -1;
1303}
1304
1305void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value)
1306{
1307 if (dd->flags & HFI1_PRESENT)
1308 writeq(value, (void __iomem *)dd->kregbase + offset);
1309}
1310
1311void __iomem *get_csr_addr(
1312 struct hfi1_devdata *dd,
1313 u32 offset)
1314{
1315 return (void __iomem *)dd->kregbase + offset;
1316}
1317
1318static inline u64 read_write_csr(const struct hfi1_devdata *dd, u32 csr,
1319 int mode, u64 value)
1320{
1321 u64 ret;
1322
77241056
MM		 1323 if (mode == CNTR_MODE_R) {
1324 ret = read_csr(dd, csr);
1325 } else if (mode == CNTR_MODE_W) {
1326 write_csr(dd, csr, value);
1327 ret = value;
1328 } else {
1329 dd_dev_err(dd, "Invalid cntr register access mode");
1330 return 0;
1331 }
1332
1333 hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, ret, mode);
1334 return ret;
1335}
1336
1337/* Dev Access */
1338static u64 dev_access_u32_csr(const struct cntr_entry *entry,
17fb4f29 1339 void *context, int vl, int mode, u64 data)
77241056 1340{
a787bde8 1341 struct hfi1_devdata *dd = context;
a699c6c2 1342 u64 csr = entry->csr;
77241056 1343
a699c6c2
VM		 1344 if (entry->flags & CNTR_SDMA) {
1345 if (vl == CNTR_INVALID_VL)
1346 return 0;
1347 csr += 0x100 * vl;
1348 } else {
1349 if (vl != CNTR_INVALID_VL)
1350 return 0;
1351 }
1352 return read_write_csr(dd, csr, mode, data);
1353}
1354
1355static u64 access_sde_err_cnt(const struct cntr_entry *entry,
1356 void *context, int idx, int mode, u64 data)
1357{
1358 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1359
1360 if (dd->per_sdma && idx < dd->num_sdma)
1361 return dd->per_sdma[idx].err_cnt;
1362 return 0;
1363}
1364
1365static u64 access_sde_int_cnt(const struct cntr_entry *entry,
1366 void *context, int idx, int mode, u64 data)
1367{
1368 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1369
1370 if (dd->per_sdma && idx < dd->num_sdma)
1371 return dd->per_sdma[idx].sdma_int_cnt;
1372 return 0;
1373}
1374
1375static u64 access_sde_idle_int_cnt(const struct cntr_entry *entry,
1376 void *context, int idx, int mode, u64 data)
1377{
1378 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1379
1380 if (dd->per_sdma && idx < dd->num_sdma)
1381 return dd->per_sdma[idx].idle_int_cnt;
1382 return 0;
1383}
1384
1385static u64 access_sde_progress_int_cnt(const struct cntr_entry *entry,
1386 void *context, int idx, int mode,
1387 u64 data)
1388{
1389 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1390
1391 if (dd->per_sdma && idx < dd->num_sdma)
1392 return dd->per_sdma[idx].progress_int_cnt;
1393 return 0;
77241056
MM		 1394}
1395
1396static u64 dev_access_u64_csr(const struct cntr_entry *entry, void *context,
17fb4f29 1397 int vl, int mode, u64 data)
77241056 1398{
a787bde8 1399 struct hfi1_devdata *dd = context;
77241056
MM		 1400
1401 u64 val = 0;
1402 u64 csr = entry->csr;
1403
1404 if (entry->flags & CNTR_VL) {
1405 if (vl == CNTR_INVALID_VL)
1406 return 0;
1407 csr += 8 * vl;
1408 } else {
1409 if (vl != CNTR_INVALID_VL)
1410 return 0;
1411 }
1412
1413 val = read_write_csr(dd, csr, mode, data);
1414 return val;
1415}
1416
1417static u64 dc_access_lcb_cntr(const struct cntr_entry *entry, void *context,
17fb4f29 1418 int vl, int mode, u64 data)
77241056 1419{
a787bde8 1420 struct hfi1_devdata *dd = context;
77241056
MM		 1421 u32 csr = entry->csr;
1422 int ret = 0;
1423
1424 if (vl != CNTR_INVALID_VL)
1425 return 0;
1426 if (mode == CNTR_MODE_R)
1427 ret = read_lcb_csr(dd, csr, &data);
1428 else if (mode == CNTR_MODE_W)
1429 ret = write_lcb_csr(dd, csr, data);
1430
1431 if (ret) {
1432 dd_dev_err(dd, "Could not acquire LCB for counter 0x%x", csr);
1433 return 0;
1434 }
1435
1436 hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, data, mode);
1437 return data;
1438}
1439
1440/* Port Access */
1441static u64 port_access_u32_csr(const struct cntr_entry *entry, void *context,
17fb4f29 1442 int vl, int mode, u64 data)
77241056 1443{
a787bde8 1444 struct hfi1_pportdata *ppd = context;
77241056
MM		 1445
1446 if (vl != CNTR_INVALID_VL)
1447 return 0;
1448 return read_write_csr(ppd->dd, entry->csr, mode, data);
1449}
1450
1451static u64 port_access_u64_csr(const struct cntr_entry *entry,
17fb4f29 1452 void *context, int vl, int mode, u64 data)
77241056 1453{
a787bde8 1454 struct hfi1_pportdata *ppd = context;
77241056
MM		 1455 u64 val;
1456 u64 csr = entry->csr;
1457
1458 if (entry->flags & CNTR_VL) {
1459 if (vl == CNTR_INVALID_VL)
1460 return 0;
1461 csr += 8 * vl;
1462 } else {
1463 if (vl != CNTR_INVALID_VL)
1464 return 0;
1465 }
1466 val = read_write_csr(ppd->dd, csr, mode, data);
1467 return val;
1468}
1469
1470/* Software defined */
1471static inline u64 read_write_sw(struct hfi1_devdata *dd, u64 *cntr, int mode,
1472 u64 data)
1473{
1474 u64 ret;
1475
1476 if (mode == CNTR_MODE_R) {
1477 ret = *cntr;
1478 } else if (mode == CNTR_MODE_W) {
1479 *cntr = data;
1480 ret = data;
1481 } else {
1482 dd_dev_err(dd, "Invalid cntr sw access mode");
1483 return 0;
1484 }
1485
1486 hfi1_cdbg(CNTR, "val 0x%llx mode %d", ret, mode);
1487
1488 return ret;
1489}
1490
1491static u64 access_sw_link_dn_cnt(const struct cntr_entry *entry, void *context,
17fb4f29 1492 int vl, int mode, u64 data)
77241056 1493{
a787bde8 1494 struct hfi1_pportdata *ppd = context;
77241056
MM		 1495
1496 if (vl != CNTR_INVALID_VL)
1497 return 0;
1498 return read_write_sw(ppd->dd, &ppd->link_downed, mode, data);
1499}
1500
1501static u64 access_sw_link_up_cnt(const struct cntr_entry *entry, void *context,
17fb4f29 1502 int vl, int mode, u64 data)
77241056 1503{
a787bde8 1504 struct hfi1_pportdata *ppd = context;
77241056
MM		 1505
1506 if (vl != CNTR_INVALID_VL)
1507 return 0;
1508 return read_write_sw(ppd->dd, &ppd->link_up, mode, data);
1509}
1510
6d014530
DL		 1511static u64 access_sw_unknown_frame_cnt(const struct cntr_entry *entry,
1512 void *context, int vl, int mode,
1513 u64 data)
1514{
1515 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;
1516
1517 if (vl != CNTR_INVALID_VL)
1518 return 0;
1519 return read_write_sw(ppd->dd, &ppd->unknown_frame_count, mode, data);
1520}
1521
77241056 1522static u64 access_sw_xmit_discards(const struct cntr_entry *entry,
17fb4f29 1523 void *context, int vl, int mode, u64 data)
77241056 1524{
69a00b8e
MM		 1525 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;
1526 u64 zero = 0;
1527 u64 *counter;
77241056 1528
69a00b8e
MM		 1529 if (vl == CNTR_INVALID_VL)
1530 counter = &ppd->port_xmit_discards;
1531 else if (vl >= 0 && vl < C_VL_COUNT)
1532 counter = &ppd->port_xmit_discards_vl[vl];
1533 else
1534 counter = &zero;
77241056 1535
69a00b8e 1536 return read_write_sw(ppd->dd, counter, mode, data);
77241056
MM		 1537}
1538
1539static u64 access_xmit_constraint_errs(const struct cntr_entry *entry,
17fb4f29
JJ		 1540 void *context, int vl, int mode,
1541 u64 data)
77241056 1542{
a787bde8 1543 struct hfi1_pportdata *ppd = context;
77241056
MM		 1544
1545 if (vl != CNTR_INVALID_VL)
1546 return 0;
1547
1548 return read_write_sw(ppd->dd, &ppd->port_xmit_constraint_errors,
1549 mode, data);
1550}
1551
1552static u64 access_rcv_constraint_errs(const struct cntr_entry *entry,
17fb4f29 1553 void *context, int vl, int mode, u64 data)
77241056 1554{
a787bde8 1555 struct hfi1_pportdata *ppd = context;
77241056
MM		 1556
1557 if (vl != CNTR_INVALID_VL)
1558 return 0;
1559
1560 return read_write_sw(ppd->dd, &ppd->port_rcv_constraint_errors,
1561 mode, data);
1562}
1563
1564u64 get_all_cpu_total(u64 __percpu *cntr)
1565{
1566 int cpu;
1567 u64 counter = 0;
1568
1569 for_each_possible_cpu(cpu)
1570 counter += *per_cpu_ptr(cntr, cpu);
1571 return counter;
1572}
1573
1574static u64 read_write_cpu(struct hfi1_devdata *dd, u64 *z_val,
1575 u64 __percpu *cntr,
1576 int vl, int mode, u64 data)
1577{
77241056
MM		 1578 u64 ret = 0;
1579
1580 if (vl != CNTR_INVALID_VL)
1581 return 0;
1582
1583 if (mode == CNTR_MODE_R) {
1584 ret = get_all_cpu_total(cntr) - *z_val;
1585 } else if (mode == CNTR_MODE_W) {
1586 /* A write can only zero the counter */
1587 if (data == 0)
1588 *z_val = get_all_cpu_total(cntr);
1589 else
1590 dd_dev_err(dd, "Per CPU cntrs can only be zeroed");
1591 } else {
1592 dd_dev_err(dd, "Invalid cntr sw cpu access mode");
1593 return 0;
1594 }
1595
1596 return ret;
1597}
1598
1599static u64 access_sw_cpu_intr(const struct cntr_entry *entry,
1600 void *context, int vl, int mode, u64 data)
1601{
a787bde8 1602 struct hfi1_devdata *dd = context;
77241056
MM		 1603
1604 return read_write_cpu(dd, &dd->z_int_counter, dd->int_counter, vl,
1605 mode, data);
1606}
1607
1608static u64 access_sw_cpu_rcv_limit(const struct cntr_entry *entry,
17fb4f29 1609 void *context, int vl, int mode, u64 data)
77241056 1610{
a787bde8 1611 struct hfi1_devdata *dd = context;
77241056
MM		 1612
1613 return read_write_cpu(dd, &dd->z_rcv_limit, dd->rcv_limit, vl,
1614 mode, data);
1615}
1616
1617static u64 access_sw_pio_wait(const struct cntr_entry *entry,
1618 void *context, int vl, int mode, u64 data)
1619{
a787bde8 1620 struct hfi1_devdata *dd = context;
77241056
MM		 1621
1622 return dd->verbs_dev.n_piowait;
1623}
1624
14553ca1
MM		 1625static u64 access_sw_pio_drain(const struct cntr_entry *entry,
1626 void *context, int vl, int mode, u64 data)
1627{
1628 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1629
1630 return dd->verbs_dev.n_piodrain;
1631}
1632
77241056
MM		 1633static u64 access_sw_vtx_wait(const struct cntr_entry *entry,
1634 void *context, int vl, int mode, u64 data)
1635{
a787bde8 1636 struct hfi1_devdata *dd = context;
77241056
MM		 1637
1638 return dd->verbs_dev.n_txwait;
1639}
1640
1641static u64 access_sw_kmem_wait(const struct cntr_entry *entry,
1642 void *context, int vl, int mode, u64 data)
1643{
a787bde8 1644 struct hfi1_devdata *dd = context;
77241056
MM		 1645
1646 return dd->verbs_dev.n_kmem_wait;
1647}
1648
b421922e 1649static u64 access_sw_send_schedule(const struct cntr_entry *entry,
17fb4f29 1650 void *context, int vl, int mode, u64 data)
b421922e
DL		 1651{
1652 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1653
89abfc8d
VM		 1654 return read_write_cpu(dd, &dd->z_send_schedule, dd->send_schedule, vl,
1655 mode, data);
b421922e
DL		 1656}
1657
2c5b521a
JR		 1658/* Software counters for the error status bits within MISC_ERR_STATUS */
1659static u64 access_misc_pll_lock_fail_err_cnt(const struct cntr_entry *entry,
1660 void *context, int vl, int mode,
1661 u64 data)
1662{
1663 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1664
1665 return dd->misc_err_status_cnt[12];
1666}
1667
1668static u64 access_misc_mbist_fail_err_cnt(const struct cntr_entry *entry,
1669 void *context, int vl, int mode,
1670 u64 data)
1671{
1672 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1673
1674 return dd->misc_err_status_cnt[11];
1675}
1676
1677static u64 access_misc_invalid_eep_cmd_err_cnt(const struct cntr_entry *entry,
1678 void *context, int vl, int mode,
1679 u64 data)
1680{
1681 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1682
1683 return dd->misc_err_status_cnt[10];
1684}
1685
1686static u64 access_misc_efuse_done_parity_err_cnt(const struct cntr_entry *entry,
1687 void *context, int vl,
1688 int mode, u64 data)
1689{
1690 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1691
1692 return dd->misc_err_status_cnt[9];
1693}
1694
1695static u64 access_misc_efuse_write_err_cnt(const struct cntr_entry *entry,
1696 void *context, int vl, int mode,
1697 u64 data)
1698{
1699 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1700
1701 return dd->misc_err_status_cnt[8];
1702}
1703
1704static u64 access_misc_efuse_read_bad_addr_err_cnt(
1705 const struct cntr_entry *entry,
1706 void *context, int vl, int mode, u64 data)
1707{
1708 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1709
1710 return dd->misc_err_status_cnt[7];
1711}
1712
1713static u64 access_misc_efuse_csr_parity_err_cnt(const struct cntr_entry *entry,
1714 void *context, int vl,
1715 int mode, u64 data)
1716{
1717 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1718
1719 return dd->misc_err_status_cnt[6];
1720}
1721
1722static u64 access_misc_fw_auth_failed_err_cnt(const struct cntr_entry *entry,
1723 void *context, int vl, int mode,
1724 u64 data)
1725{
1726 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1727
1728 return dd->misc_err_status_cnt[5];
1729}
1730
1731static u64 access_misc_key_mismatch_err_cnt(const struct cntr_entry *entry,
1732 void *context, int vl, int mode,
1733 u64 data)
1734{
1735 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1736
1737 return dd->misc_err_status_cnt[4];
1738}
1739
1740static u64 access_misc_sbus_write_failed_err_cnt(const struct cntr_entry *entry,
1741 void *context, int vl,
1742 int mode, u64 data)
1743{
1744 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1745
1746 return dd->misc_err_status_cnt[3];
1747}
1748
1749static u64 access_misc_csr_write_bad_addr_err_cnt(
1750 const struct cntr_entry *entry,
1751 void *context, int vl, int mode, u64 data)
1752{
1753 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1754
1755 return dd->misc_err_status_cnt[2];
1756}
1757
1758static u64 access_misc_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
1759 void *context, int vl,
1760 int mode, u64 data)
1761{
1762 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1763
1764 return dd->misc_err_status_cnt[1];
1765}
1766
1767static u64 access_misc_csr_parity_err_cnt(const struct cntr_entry *entry,
1768 void *context, int vl, int mode,
1769 u64 data)
1770{
1771 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1772
1773 return dd->misc_err_status_cnt[0];
1774}
1775
1776/*
1777 * Software counter for the aggregate of
1778 * individual CceErrStatus counters
1779 */
1780static u64 access_sw_cce_err_status_aggregated_cnt(
1781 const struct cntr_entry *entry,
1782 void *context, int vl, int mode, u64 data)
1783{
1784 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1785
1786 return dd->sw_cce_err_status_aggregate;
1787}
1788
1789/*
1790 * Software counters corresponding to each of the
1791 * error status bits within CceErrStatus
1792 */
1793static u64 access_cce_msix_csr_parity_err_cnt(const struct cntr_entry *entry,
1794 void *context, int vl, int mode,
1795 u64 data)
1796{
1797 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1798
1799 return dd->cce_err_status_cnt[40];
1800}
1801
1802static u64 access_cce_int_map_unc_err_cnt(const struct cntr_entry *entry,
1803 void *context, int vl, int mode,
1804 u64 data)
1805{
1806 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1807
1808 return dd->cce_err_status_cnt[39];
1809}
1810
1811static u64 access_cce_int_map_cor_err_cnt(const struct cntr_entry *entry,
1812 void *context, int vl, int mode,
1813 u64 data)
1814{
1815 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1816
1817 return dd->cce_err_status_cnt[38];
1818}
1819
1820static u64 access_cce_msix_table_unc_err_cnt(const struct cntr_entry *entry,
1821 void *context, int vl, int mode,
1822 u64 data)
1823{
1824 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1825
1826 return dd->cce_err_status_cnt[37];
1827}
1828
1829static u64 access_cce_msix_table_cor_err_cnt(const struct cntr_entry *entry,
1830 void *context, int vl, int mode,
1831 u64 data)
1832{
1833 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1834
1835 return dd->cce_err_status_cnt[36];
1836}
1837
1838static u64 access_cce_rxdma_conv_fifo_parity_err_cnt(
1839 const struct cntr_entry *entry,
1840 void *context, int vl, int mode, u64 data)
1841{
1842 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1843
1844 return dd->cce_err_status_cnt[35];
1845}
1846
1847static u64 access_cce_rcpl_async_fifo_parity_err_cnt(
1848 const struct cntr_entry *entry,
1849 void *context, int vl, int mode, u64 data)
1850{
1851 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1852
1853 return dd->cce_err_status_cnt[34];
1854}
1855
1856static u64 access_cce_seg_write_bad_addr_err_cnt(const struct cntr_entry *entry,
1857 void *context, int vl,
1858 int mode, u64 data)
1859{
1860 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1861
1862 return dd->cce_err_status_cnt[33];
1863}
1864
1865static u64 access_cce_seg_read_bad_addr_err_cnt(const struct cntr_entry *entry,
1866 void *context, int vl, int mode,
1867 u64 data)
1868{
1869 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1870
1871 return dd->cce_err_status_cnt[32];
1872}
1873
1874static u64 access_la_triggered_cnt(const struct cntr_entry *entry,
1875 void *context, int vl, int mode, u64 data)
1876{
1877 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1878
1879 return dd->cce_err_status_cnt[31];
1880}
1881
1882static u64 access_cce_trgt_cpl_timeout_err_cnt(const struct cntr_entry *entry,
1883 void *context, int vl, int mode,
1884 u64 data)
1885{
1886 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1887
1888 return dd->cce_err_status_cnt[30];
1889}
1890
1891static u64 access_pcic_receive_parity_err_cnt(const struct cntr_entry *entry,
1892 void *context, int vl, int mode,
1893 u64 data)
1894{
1895 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1896
1897 return dd->cce_err_status_cnt[29];
1898}
1899
1900static u64 access_pcic_transmit_back_parity_err_cnt(
1901 const struct cntr_entry *entry,
1902 void *context, int vl, int mode, u64 data)
1903{
1904 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1905
1906 return dd->cce_err_status_cnt[28];
1907}
1908
1909static u64 access_pcic_transmit_front_parity_err_cnt(
1910 const struct cntr_entry *entry,
1911 void *context, int vl, int mode, u64 data)
1912{
1913 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1914
1915 return dd->cce_err_status_cnt[27];
1916}
1917
1918static u64 access_pcic_cpl_dat_q_unc_err_cnt(const struct cntr_entry *entry,
1919 void *context, int vl, int mode,
1920 u64 data)
1921{
1922 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1923
1924 return dd->cce_err_status_cnt[26];
1925}
1926
1927static u64 access_pcic_cpl_hd_q_unc_err_cnt(const struct cntr_entry *entry,
1928 void *context, int vl, int mode,
1929 u64 data)
1930{
1931 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1932
1933 return dd->cce_err_status_cnt[25];
1934}
1935
1936static u64 access_pcic_post_dat_q_unc_err_cnt(const struct cntr_entry *entry,
1937 void *context, int vl, int mode,
1938 u64 data)
1939{
1940 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1941
1942 return dd->cce_err_status_cnt[24];
1943}
1944
1945static u64 access_pcic_post_hd_q_unc_err_cnt(const struct cntr_entry *entry,
1946 void *context, int vl, int mode,
1947 u64 data)
1948{
1949 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1950
1951 return dd->cce_err_status_cnt[23];
1952}
1953
1954static u64 access_pcic_retry_sot_mem_unc_err_cnt(const struct cntr_entry *entry,
1955 void *context, int vl,
1956 int mode, u64 data)
1957{
1958 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1959
1960 return dd->cce_err_status_cnt[22];
1961}
1962
1963static u64 access_pcic_retry_mem_unc_err(const struct cntr_entry *entry,
1964 void *context, int vl, int mode,
1965 u64 data)
1966{
1967 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1968
1969 return dd->cce_err_status_cnt[21];
1970}
1971
1972static u64 access_pcic_n_post_dat_q_parity_err_cnt(
1973 const struct cntr_entry *entry,
1974 void *context, int vl, int mode, u64 data)
1975{
1976 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1977
1978 return dd->cce_err_status_cnt[20];
1979}
1980
1981static u64 access_pcic_n_post_h_q_parity_err_cnt(const struct cntr_entry *entry,
1982 void *context, int vl,
1983 int mode, u64 data)
1984{
1985 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1986
1987 return dd->cce_err_status_cnt[19];
1988}
1989
1990static u64 access_pcic_cpl_dat_q_cor_err_cnt(const struct cntr_entry *entry,
1991 void *context, int vl, int mode,
1992 u64 data)
1993{
1994 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1995
1996 return dd->cce_err_status_cnt[18];
1997}
1998
1999static u64 access_pcic_cpl_hd_q_cor_err_cnt(const struct cntr_entry *entry,
2000 void *context, int vl, int mode,
2001 u64 data)
2002{
2003 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2004
2005 return dd->cce_err_status_cnt[17];
2006}
2007
2008static u64 access_pcic_post_dat_q_cor_err_cnt(const struct cntr_entry *entry,
2009 void *context, int vl, int mode,
2010 u64 data)
2011{
2012 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2013
2014 return dd->cce_err_status_cnt[16];
2015}
2016
2017static u64 access_pcic_post_hd_q_cor_err_cnt(const struct cntr_entry *entry,
2018 void *context, int vl, int mode,
2019 u64 data)
2020{
2021 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2022
2023 return dd->cce_err_status_cnt[15];
2024}
2025
2026static u64 access_pcic_retry_sot_mem_cor_err_cnt(const struct cntr_entry *entry,
2027 void *context, int vl,
2028 int mode, u64 data)
2029{
2030 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2031
2032 return dd->cce_err_status_cnt[14];
2033}
2034
2035static u64 access_pcic_retry_mem_cor_err_cnt(const struct cntr_entry *entry,
2036 void *context, int vl, int mode,
2037 u64 data)
2038{
2039 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2040
2041 return dd->cce_err_status_cnt[13];
2042}
2043
2044static u64 access_cce_cli1_async_fifo_dbg_parity_err_cnt(
2045 const struct cntr_entry *entry,
2046 void *context, int vl, int mode, u64 data)
2047{
2048 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2049
2050 return dd->cce_err_status_cnt[12];
2051}
2052
2053static u64 access_cce_cli1_async_fifo_rxdma_parity_err_cnt(
2054 const struct cntr_entry *entry,
2055 void *context, int vl, int mode, u64 data)
2056{
2057 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2058
2059 return dd->cce_err_status_cnt[11];
2060}
2061
2062static u64 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt(
2063 const struct cntr_entry *entry,
2064 void *context, int vl, int mode, u64 data)
2065{
2066 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2067
2068 return dd->cce_err_status_cnt[10];
2069}
2070
2071static u64 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt(
2072 const struct cntr_entry *entry,
2073 void *context, int vl, int mode, u64 data)
2074{
2075 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2076
2077 return dd->cce_err_status_cnt[9];
2078}
2079
2080static u64 access_cce_cli2_async_fifo_parity_err_cnt(
2081 const struct cntr_entry *entry,
2082 void *context, int vl, int mode, u64 data)
2083{
2084 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2085
2086 return dd->cce_err_status_cnt[8];
2087}
2088
2089static u64 access_cce_csr_cfg_bus_parity_err_cnt(const struct cntr_entry *entry,
2090 void *context, int vl,
2091 int mode, u64 data)
2092{
2093 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2094
2095 return dd->cce_err_status_cnt[7];
2096}
2097
2098static u64 access_cce_cli0_async_fifo_parity_err_cnt(
2099 const struct cntr_entry *entry,
2100 void *context, int vl, int mode, u64 data)
2101{
2102 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2103
2104 return dd->cce_err_status_cnt[6];
2105}
2106
2107static u64 access_cce_rspd_data_parity_err_cnt(const struct cntr_entry *entry,
2108 void *context, int vl, int mode,
2109 u64 data)
2110{
2111 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2112
2113 return dd->cce_err_status_cnt[5];
2114}
2115
2116static u64 access_cce_trgt_access_err_cnt(const struct cntr_entry *entry,
2117 void *context, int vl, int mode,
2118 u64 data)
2119{
2120 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2121
2122 return dd->cce_err_status_cnt[4];
2123}
2124
2125static u64 access_cce_trgt_async_fifo_parity_err_cnt(
2126 const struct cntr_entry *entry,
2127 void *context, int vl, int mode, u64 data)
2128{
2129 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2130
2131 return dd->cce_err_status_cnt[3];
2132}
2133
2134static u64 access_cce_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry,
2135 void *context, int vl,
2136 int mode, u64 data)
2137{
2138 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2139
2140 return dd->cce_err_status_cnt[2];
2141}
2142
2143static u64 access_cce_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
2144 void *context, int vl,
2145 int mode, u64 data)
2146{
2147 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2148
2149 return dd->cce_err_status_cnt[1];
2150}
2151
2152static u64 access_ccs_csr_parity_err_cnt(const struct cntr_entry *entry,
2153 void *context, int vl, int mode,
2154 u64 data)
2155{
2156 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2157
2158 return dd->cce_err_status_cnt[0];
2159}
2160
2161/*
2162 * Software counters corresponding to each of the
2163 * error status bits within RcvErrStatus
2164 */
2165static u64 access_rx_csr_parity_err_cnt(const struct cntr_entry *entry,
2166 void *context, int vl, int mode,
2167 u64 data)
2168{
2169 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2170
2171 return dd->rcv_err_status_cnt[63];
2172}
2173
2174static u64 access_rx_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry,
2175 void *context, int vl,
2176 int mode, u64 data)
2177{
2178 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2179
2180 return dd->rcv_err_status_cnt[62];
2181}
2182
2183static u64 access_rx_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
2184 void *context, int vl, int mode,
2185 u64 data)
2186{
2187 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2188
2189 return dd->rcv_err_status_cnt[61];
2190}
2191
2192static u64 access_rx_dma_csr_unc_err_cnt(const struct cntr_entry *entry,
2193 void *context, int vl, int mode,
2194 u64 data)
2195{
2196 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2197
2198 return dd->rcv_err_status_cnt[60];
2199}
2200
2201static u64 access_rx_dma_dq_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2202 void *context, int vl,
2203 int mode, u64 data)
2204{
2205 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2206
2207 return dd->rcv_err_status_cnt[59];
2208}
2209
2210static u64 access_rx_dma_eq_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2211 void *context, int vl,
2212 int mode, u64 data)
2213{
2214 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2215
2216 return dd->rcv_err_status_cnt[58];
2217}
2218
2219static u64 access_rx_dma_csr_parity_err_cnt(const struct cntr_entry *entry,
2220 void *context, int vl, int mode,
2221 u64 data)
2222{
2223 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2224
2225 return dd->rcv_err_status_cnt[57];
2226}
2227
2228static u64 access_rx_rbuf_data_cor_err_cnt(const struct cntr_entry *entry,
2229 void *context, int vl, int mode,
2230 u64 data)
2231{
2232 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2233
2234 return dd->rcv_err_status_cnt[56];
2235}
2236
2237static u64 access_rx_rbuf_data_unc_err_cnt(const struct cntr_entry *entry,
2238 void *context, int vl, int mode,
2239 u64 data)
2240{
2241 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2242
2243 return dd->rcv_err_status_cnt[55];
2244}
2245
2246static u64 access_rx_dma_data_fifo_rd_cor_err_cnt(
2247 const struct cntr_entry *entry,
2248 void *context, int vl, int mode, u64 data)
2249{
2250 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2251
2252 return dd->rcv_err_status_cnt[54];
2253}
2254
2255static u64 access_rx_dma_data_fifo_rd_unc_err_cnt(
2256 const struct cntr_entry *entry,
2257 void *context, int vl, int mode, u64 data)
2258{
2259 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2260
2261 return dd->rcv_err_status_cnt[53];
2262}
2263
2264static u64 access_rx_dma_hdr_fifo_rd_cor_err_cnt(const struct cntr_entry *entry,
2265 void *context, int vl,
2266 int mode, u64 data)
2267{
2268 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2269
2270 return dd->rcv_err_status_cnt[52];
2271}
2272
2273static u64 access_rx_dma_hdr_fifo_rd_unc_err_cnt(const struct cntr_entry *entry,
2274 void *context, int vl,
2275 int mode, u64 data)
2276{
2277 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2278
2279 return dd->rcv_err_status_cnt[51];
2280}
2281
2282static u64 access_rx_rbuf_desc_part2_cor_err_cnt(const struct cntr_entry *entry,
2283 void *context, int vl,
2284 int mode, u64 data)
2285{
2286 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2287
2288 return dd->rcv_err_status_cnt[50];
2289}
2290
2291static u64 access_rx_rbuf_desc_part2_unc_err_cnt(const struct cntr_entry *entry,
2292 void *context, int vl,
2293 int mode, u64 data)
2294{
2295 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2296
2297 return dd->rcv_err_status_cnt[49];
2298}
2299
2300static u64 access_rx_rbuf_desc_part1_cor_err_cnt(const struct cntr_entry *entry,
2301 void *context, int vl,
2302 int mode, u64 data)
2303{
2304 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2305
2306 return dd->rcv_err_status_cnt[48];
2307}
2308
2309static u64 access_rx_rbuf_desc_part1_unc_err_cnt(const struct cntr_entry *entry,
2310 void *context, int vl,
2311 int mode, u64 data)
2312{
2313 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2314
2315 return dd->rcv_err_status_cnt[47];
2316}
2317
2318static u64 access_rx_hq_intr_fsm_err_cnt(const struct cntr_entry *entry,
2319 void *context, int vl, int mode,
2320 u64 data)
2321{
2322 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2323
2324 return dd->rcv_err_status_cnt[46];
2325}
2326
2327static u64 access_rx_hq_intr_csr_parity_err_cnt(
2328 const struct cntr_entry *entry,
2329 void *context, int vl, int mode, u64 data)
2330{
2331 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2332
2333 return dd->rcv_err_status_cnt[45];
2334}
2335
2336static u64 access_rx_lookup_csr_parity_err_cnt(
2337 const struct cntr_entry *entry,
2338 void *context, int vl, int mode, u64 data)
2339{
2340 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2341
2342 return dd->rcv_err_status_cnt[44];
2343}
2344
2345static u64 access_rx_lookup_rcv_array_cor_err_cnt(
2346 const struct cntr_entry *entry,
2347 void *context, int vl, int mode, u64 data)
2348{
2349 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2350
2351 return dd->rcv_err_status_cnt[43];
2352}
2353
2354static u64 access_rx_lookup_rcv_array_unc_err_cnt(
2355 const struct cntr_entry *entry,
2356 void *context, int vl, int mode, u64 data)
2357{
2358 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2359
2360 return dd->rcv_err_status_cnt[42];
2361}
2362
2363static u64 access_rx_lookup_des_part2_parity_err_cnt(
2364 const struct cntr_entry *entry,
2365 void *context, int vl, int mode, u64 data)
2366{
2367 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2368
2369 return dd->rcv_err_status_cnt[41];
2370}
2371
2372static u64 access_rx_lookup_des_part1_unc_cor_err_cnt(
2373 const struct cntr_entry *entry,
2374 void *context, int vl, int mode, u64 data)
2375{
2376 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2377
2378 return dd->rcv_err_status_cnt[40];
2379}
2380
2381static u64 access_rx_lookup_des_part1_unc_err_cnt(
2382 const struct cntr_entry *entry,
2383 void *context, int vl, int mode, u64 data)
2384{
2385 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2386
2387 return dd->rcv_err_status_cnt[39];
2388}
2389
2390static u64 access_rx_rbuf_next_free_buf_cor_err_cnt(
2391 const struct cntr_entry *entry,
2392 void *context, int vl, int mode, u64 data)
2393{
2394 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2395
2396 return dd->rcv_err_status_cnt[38];
2397}
2398
2399static u64 access_rx_rbuf_next_free_buf_unc_err_cnt(
2400 const struct cntr_entry *entry,
2401 void *context, int vl, int mode, u64 data)
2402{
2403 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2404
2405 return dd->rcv_err_status_cnt[37];
2406}
2407
2408static u64 access_rbuf_fl_init_wr_addr_parity_err_cnt(
2409 const struct cntr_entry *entry,
2410 void *context, int vl, int mode, u64 data)
2411{
2412 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2413
2414 return dd->rcv_err_status_cnt[36];
2415}
2416
2417static u64 access_rx_rbuf_fl_initdone_parity_err_cnt(
2418 const struct cntr_entry *entry,
2419 void *context, int vl, int mode, u64 data)
2420{
2421 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2422
2423 return dd->rcv_err_status_cnt[35];
2424}
2425
2426static u64 access_rx_rbuf_fl_write_addr_parity_err_cnt(
2427 const struct cntr_entry *entry,
2428 void *context, int vl, int mode, u64 data)
2429{
2430 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2431
2432 return dd->rcv_err_status_cnt[34];
2433}
2434
2435static u64 access_rx_rbuf_fl_rd_addr_parity_err_cnt(
2436 const struct cntr_entry *entry,
2437 void *context, int vl, int mode, u64 data)
2438{
2439 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2440
2441 return dd->rcv_err_status_cnt[33];
2442}
2443
2444static u64 access_rx_rbuf_empty_err_cnt(const struct cntr_entry *entry,
2445 void *context, int vl, int mode,
2446 u64 data)
2447{
2448 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2449
2450 return dd->rcv_err_status_cnt[32];
2451}
2452
2453static u64 access_rx_rbuf_full_err_cnt(const struct cntr_entry *entry,
2454 void *context, int vl, int mode,
2455 u64 data)
2456{
2457 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2458
2459 return dd->rcv_err_status_cnt[31];
2460}
2461
2462static u64 access_rbuf_bad_lookup_err_cnt(const struct cntr_entry *entry,
2463 void *context, int vl, int mode,
2464 u64 data)
2465{
2466 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2467
2468 return dd->rcv_err_status_cnt[30];
2469}
2470
2471static u64 access_rbuf_ctx_id_parity_err_cnt(const struct cntr_entry *entry,
2472 void *context, int vl, int mode,
2473 u64 data)
2474{
2475 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2476
2477 return dd->rcv_err_status_cnt[29];
2478}
2479
2480static u64 access_rbuf_csr_qeopdw_parity_err_cnt(const struct cntr_entry *entry,
2481 void *context, int vl,
2482 int mode, u64 data)
2483{
2484 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2485
2486 return dd->rcv_err_status_cnt[28];
2487}
2488
2489static u64 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt(
2490 const struct cntr_entry *entry,
2491 void *context, int vl, int mode, u64 data)
2492{
2493 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2494
2495 return dd->rcv_err_status_cnt[27];
2496}
2497
2498static u64 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt(
2499 const struct cntr_entry *entry,
2500 void *context, int vl, int mode, u64 data)
2501{
2502 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2503
2504 return dd->rcv_err_status_cnt[26];
2505}
2506
2507static u64 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt(
2508 const struct cntr_entry *entry,
2509 void *context, int vl, int mode, u64 data)
2510{
2511 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2512
2513 return dd->rcv_err_status_cnt[25];
2514}
2515
2516static u64 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt(
2517 const struct cntr_entry *entry,
2518 void *context, int vl, int mode, u64 data)
2519{
2520 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2521
2522 return dd->rcv_err_status_cnt[24];
2523}
2524
2525static u64 access_rx_rbuf_csr_q_next_buf_parity_err_cnt(
2526 const struct cntr_entry *entry,
2527 void *context, int vl, int mode, u64 data)
2528{
2529 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2530
2531 return dd->rcv_err_status_cnt[23];
2532}
2533
2534static u64 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt(
2535 const struct cntr_entry *entry,
2536 void *context, int vl, int mode, u64 data)
2537{
2538 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2539
2540 return dd->rcv_err_status_cnt[22];
2541}
2542
2543static u64 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt(
2544 const struct cntr_entry *entry,
2545 void *context, int vl, int mode, u64 data)
2546{
2547 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2548
2549 return dd->rcv_err_status_cnt[21];
2550}
2551
2552static u64 access_rx_rbuf_block_list_read_cor_err_cnt(
2553 const struct cntr_entry *entry,
2554 void *context, int vl, int mode, u64 data)
2555{
2556 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2557
2558 return dd->rcv_err_status_cnt[20];
2559}
2560
2561static u64 access_rx_rbuf_block_list_read_unc_err_cnt(
2562 const struct cntr_entry *entry,
2563 void *context, int vl, int mode, u64 data)
2564{
2565 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2566
2567 return dd->rcv_err_status_cnt[19];
2568}
2569
2570static u64 access_rx_rbuf_lookup_des_cor_err_cnt(const struct cntr_entry *entry,
2571 void *context, int vl,
2572 int mode, u64 data)
2573{
2574 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2575
2576 return dd->rcv_err_status_cnt[18];
2577}
2578
2579static u64 access_rx_rbuf_lookup_des_unc_err_cnt(const struct cntr_entry *entry,
2580 void *context, int vl,
2581 int mode, u64 data)
2582{
2583 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2584
2585 return dd->rcv_err_status_cnt[17];
2586}
2587
2588static u64 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt(
2589 const struct cntr_entry *entry,
2590 void *context, int vl, int mode, u64 data)
2591{
2592 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2593
2594 return dd->rcv_err_status_cnt[16];
2595}
2596
2597static u64 access_rx_rbuf_lookup_des_reg_unc_err_cnt(
2598 const struct cntr_entry *entry,
2599 void *context, int vl, int mode, u64 data)
2600{
2601 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2602
2603 return dd->rcv_err_status_cnt[15];
2604}
2605
2606static u64 access_rx_rbuf_free_list_cor_err_cnt(const struct cntr_entry *entry,
2607 void *context, int vl,
2608 int mode, u64 data)
2609{
2610 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2611
2612 return dd->rcv_err_status_cnt[14];
2613}
2614
2615static u64 access_rx_rbuf_free_list_unc_err_cnt(const struct cntr_entry *entry,
2616 void *context, int vl,
2617 int mode, u64 data)
2618{
2619 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2620
2621 return dd->rcv_err_status_cnt[13];
2622}
2623
2624static u64 access_rx_rcv_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2625 void *context, int vl, int mode,
2626 u64 data)
2627{
2628 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2629
2630 return dd->rcv_err_status_cnt[12];
2631}
2632
2633static u64 access_rx_dma_flag_cor_err_cnt(const struct cntr_entry *entry,
2634 void *context, int vl, int mode,
2635 u64 data)
2636{
2637 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2638
2639 return dd->rcv_err_status_cnt[11];
2640}
2641
2642static u64 access_rx_dma_flag_unc_err_cnt(const struct cntr_entry *entry,
2643 void *context, int vl, int mode,
2644 u64 data)
2645{
2646 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2647
2648 return dd->rcv_err_status_cnt[10];
2649}
2650
2651static u64 access_rx_dc_sop_eop_parity_err_cnt(const struct cntr_entry *entry,
2652 void *context, int vl, int mode,
2653 u64 data)
2654{
2655 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2656
2657 return dd->rcv_err_status_cnt[9];
2658}
2659
2660static u64 access_rx_rcv_csr_parity_err_cnt(const struct cntr_entry *entry,
2661 void *context, int vl, int mode,
2662 u64 data)
2663{
2664 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2665
2666 return dd->rcv_err_status_cnt[8];
2667}
2668
2669static u64 access_rx_rcv_qp_map_table_cor_err_cnt(
2670 const struct cntr_entry *entry,
2671 void *context, int vl, int mode, u64 data)
2672{
2673 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2674
2675 return dd->rcv_err_status_cnt[7];
2676}
2677
2678static u64 access_rx_rcv_qp_map_table_unc_err_cnt(
2679 const struct cntr_entry *entry,
2680 void *context, int vl, int mode, u64 data)
2681{
2682 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2683
2684 return dd->rcv_err_status_cnt[6];
2685}
2686
2687static u64 access_rx_rcv_data_cor_err_cnt(const struct cntr_entry *entry,
2688 void *context, int vl, int mode,
2689 u64 data)
2690{
2691 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2692
2693 return dd->rcv_err_status_cnt[5];
2694}
2695
2696static u64 access_rx_rcv_data_unc_err_cnt(const struct cntr_entry *entry,
2697 void *context, int vl, int mode,
2698 u64 data)
2699{
2700 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2701
2702 return dd->rcv_err_status_cnt[4];
2703}
2704
2705static u64 access_rx_rcv_hdr_cor_err_cnt(const struct cntr_entry *entry,
2706 void *context, int vl, int mode,
2707 u64 data)
2708{
2709 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2710
2711 return dd->rcv_err_status_cnt[3];
2712}
2713
2714static u64 access_rx_rcv_hdr_unc_err_cnt(const struct cntr_entry *entry,
2715 void *context, int vl, int mode,
2716 u64 data)
2717{
2718 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2719
2720 return dd->rcv_err_status_cnt[2];
2721}
2722
2723static u64 access_rx_dc_intf_parity_err_cnt(const struct cntr_entry *entry,
2724 void *context, int vl, int mode,
2725 u64 data)
2726{
2727 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2728
2729 return dd->rcv_err_status_cnt[1];
2730}
2731
2732static u64 access_rx_dma_csr_cor_err_cnt(const struct cntr_entry *entry,
2733 void *context, int vl, int mode,
2734 u64 data)
2735{
2736 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2737
2738 return dd->rcv_err_status_cnt[0];
2739}
2740
2741/*
2742 * Software counters corresponding to each of the
2743 * error status bits within SendPioErrStatus
2744 */
2745static u64 access_pio_pec_sop_head_parity_err_cnt(
2746 const struct cntr_entry *entry,
2747 void *context, int vl, int mode, u64 data)
2748{
2749 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2750
2751 return dd->send_pio_err_status_cnt[35];
2752}
2753
2754static u64 access_pio_pcc_sop_head_parity_err_cnt(
2755 const struct cntr_entry *entry,
2756 void *context, int vl, int mode, u64 data)
2757{
2758 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2759
2760 return dd->send_pio_err_status_cnt[34];
2761}
2762
2763static u64 access_pio_last_returned_cnt_parity_err_cnt(
2764 const struct cntr_entry *entry,
2765 void *context, int vl, int mode, u64 data)
2766{
2767 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2768
2769 return dd->send_pio_err_status_cnt[33];
2770}
2771
2772static u64 access_pio_current_free_cnt_parity_err_cnt(
2773 const struct cntr_entry *entry,
2774 void *context, int vl, int mode, u64 data)
2775{
2776 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2777
2778 return dd->send_pio_err_status_cnt[32];
2779}
2780
2781static u64 access_pio_reserved_31_err_cnt(const struct cntr_entry *entry,
2782 void *context, int vl, int mode,
2783 u64 data)
2784{
2785 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2786
2787 return dd->send_pio_err_status_cnt[31];
2788}
2789
2790static u64 access_pio_reserved_30_err_cnt(const struct cntr_entry *entry,
2791 void *context, int vl, int mode,
2792 u64 data)
2793{
2794 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2795
2796 return dd->send_pio_err_status_cnt[30];
2797}
2798
2799static u64 access_pio_ppmc_sop_len_err_cnt(const struct cntr_entry *entry,
2800 void *context, int vl, int mode,
2801 u64 data)
2802{
2803 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2804
2805 return dd->send_pio_err_status_cnt[29];
2806}
2807
2808static u64 access_pio_ppmc_bqc_mem_parity_err_cnt(
2809 const struct cntr_entry *entry,
2810 void *context, int vl, int mode, u64 data)
2811{
2812 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2813
2814 return dd->send_pio_err_status_cnt[28];
2815}
2816
2817static u64 access_pio_vl_fifo_parity_err_cnt(const struct cntr_entry *entry,
2818 void *context, int vl, int mode,
2819 u64 data)
2820{
2821 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2822
2823 return dd->send_pio_err_status_cnt[27];
2824}
2825
2826static u64 access_pio_vlf_sop_parity_err_cnt(const struct cntr_entry *entry,
2827 void *context, int vl, int mode,
2828 u64 data)
2829{
2830 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2831
2832 return dd->send_pio_err_status_cnt[26];
2833}
2834
2835static u64 access_pio_vlf_v1_len_parity_err_cnt(const struct cntr_entry *entry,
2836 void *context, int vl,
2837 int mode, u64 data)
2838{
2839 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2840
2841 return dd->send_pio_err_status_cnt[25];
2842}
2843
2844static u64 access_pio_block_qw_count_parity_err_cnt(
2845 const struct cntr_entry *entry,
2846 void *context, int vl, int mode, u64 data)
2847{
2848 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2849
2850 return dd->send_pio_err_status_cnt[24];
2851}
2852
2853static u64 access_pio_write_qw_valid_parity_err_cnt(
2854 const struct cntr_entry *entry,
2855 void *context, int vl, int mode, u64 data)
2856{
2857 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2858
2859 return dd->send_pio_err_status_cnt[23];
2860}
2861
2862static u64 access_pio_state_machine_err_cnt(const struct cntr_entry *entry,
2863 void *context, int vl, int mode,
2864 u64 data)
2865{
2866 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2867
2868 return dd->send_pio_err_status_cnt[22];
2869}
2870
2871static u64 access_pio_write_data_parity_err_cnt(const struct cntr_entry *entry,
2872 void *context, int vl,
2873 int mode, u64 data)
2874{
2875 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2876
2877 return dd->send_pio_err_status_cnt[21];
2878}
2879
2880static u64 access_pio_host_addr_mem_cor_err_cnt(const struct cntr_entry *entry,
2881 void *context, int vl,
2882 int mode, u64 data)
2883{
2884 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2885
2886 return dd->send_pio_err_status_cnt[20];
2887}
2888
2889static u64 access_pio_host_addr_mem_unc_err_cnt(const struct cntr_entry *entry,
2890 void *context, int vl,
2891 int mode, u64 data)
2892{
2893 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2894
2895 return dd->send_pio_err_status_cnt[19];
2896}
2897
2898static u64 access_pio_pkt_evict_sm_or_arb_sm_err_cnt(
2899 const struct cntr_entry *entry,
2900 void *context, int vl, int mode, u64 data)
2901{
2902 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2903
2904 return dd->send_pio_err_status_cnt[18];
2905}
2906
2907static u64 access_pio_init_sm_in_err_cnt(const struct cntr_entry *entry,
2908 void *context, int vl, int mode,
2909 u64 data)
2910{
2911 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2912
2913 return dd->send_pio_err_status_cnt[17];
2914}
2915
2916static u64 access_pio_ppmc_pbl_fifo_err_cnt(const struct cntr_entry *entry,
2917 void *context, int vl, int mode,
2918 u64 data)
2919{
2920 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2921
2922 return dd->send_pio_err_status_cnt[16];
2923}
2924
2925static u64 access_pio_credit_ret_fifo_parity_err_cnt(
2926 const struct cntr_entry *entry,
2927 void *context, int vl, int mode, u64 data)
2928{
2929 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2930
2931 return dd->send_pio_err_status_cnt[15];
2932}
2933
2934static u64 access_pio_v1_len_mem_bank1_cor_err_cnt(
2935 const struct cntr_entry *entry,
2936 void *context, int vl, int mode, u64 data)
2937{
2938 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2939
2940 return dd->send_pio_err_status_cnt[14];
2941}
2942
2943static u64 access_pio_v1_len_mem_bank0_cor_err_cnt(
2944 const struct cntr_entry *entry,
2945 void *context, int vl, int mode, u64 data)
2946{
2947 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2948
2949 return dd->send_pio_err_status_cnt[13];
2950}
2951
2952static u64 access_pio_v1_len_mem_bank1_unc_err_cnt(
2953 const struct cntr_entry *entry,
2954 void *context, int vl, int mode, u64 data)
2955{
2956 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2957
2958 return dd->send_pio_err_status_cnt[12];
2959}
2960
2961static u64 access_pio_v1_len_mem_bank0_unc_err_cnt(
2962 const struct cntr_entry *entry,
2963 void *context, int vl, int mode, u64 data)
2964{
2965 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2966
2967 return dd->send_pio_err_status_cnt[11];
2968}
2969
2970static u64 access_pio_sm_pkt_reset_parity_err_cnt(
2971 const struct cntr_entry *entry,
2972 void *context, int vl, int mode, u64 data)
2973{
2974 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2975
2976 return dd->send_pio_err_status_cnt[10];
2977}
2978
2979static u64 access_pio_pkt_evict_fifo_parity_err_cnt(
2980 const struct cntr_entry *entry,
2981 void *context, int vl, int mode, u64 data)
2982{
2983 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2984
2985 return dd->send_pio_err_status_cnt[9];
2986}
2987
2988static u64 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt(
2989 const struct cntr_entry *entry,
2990 void *context, int vl, int mode, u64 data)
2991{
2992 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2993
2994 return dd->send_pio_err_status_cnt[8];
2995}
2996
2997static u64 access_pio_sbrdctl_crrel_parity_err_cnt(
2998 const struct cntr_entry *entry,
2999 void *context, int vl, int mode, u64 data)
3000{
3001 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3002
3003 return dd->send_pio_err_status_cnt[7];
3004}
3005
3006static u64 access_pio_pec_fifo_parity_err_cnt(const struct cntr_entry *entry,
3007 void *context, int vl, int mode,
3008 u64 data)
3009{
3010 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3011
3012 return dd->send_pio_err_status_cnt[6];
3013}
3014
3015static u64 access_pio_pcc_fifo_parity_err_cnt(const struct cntr_entry *entry,
3016 void *context, int vl, int mode,
3017 u64 data)
3018{
3019 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3020
3021 return dd->send_pio_err_status_cnt[5];
3022}
3023
3024static u64 access_pio_sb_mem_fifo1_err_cnt(const struct cntr_entry *entry,
3025 void *context, int vl, int mode,
3026 u64 data)
3027{
3028 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3029
3030 return dd->send_pio_err_status_cnt[4];
3031}
3032
3033static u64 access_pio_sb_mem_fifo0_err_cnt(const struct cntr_entry *entry,
3034 void *context, int vl, int mode,
3035 u64 data)
3036{
3037 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3038
3039 return dd->send_pio_err_status_cnt[3];
3040}
3041
3042static u64 access_pio_csr_parity_err_cnt(const struct cntr_entry *entry,
3043 void *context, int vl, int mode,
3044 u64 data)
3045{
3046 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3047
3048 return dd->send_pio_err_status_cnt[2];
3049}
3050
3051static u64 access_pio_write_addr_parity_err_cnt(const struct cntr_entry *entry,
3052 void *context, int vl,
3053 int mode, u64 data)
3054{
3055 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3056
3057 return dd->send_pio_err_status_cnt[1];
3058}
3059
3060static u64 access_pio_write_bad_ctxt_err_cnt(const struct cntr_entry *entry,
3061 void *context, int vl, int mode,
3062 u64 data)
3063{
3064 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3065
3066 return dd->send_pio_err_status_cnt[0];
3067}
3068
3069/*
3070 * Software counters corresponding to each of the
3071 * error status bits within SendDmaErrStatus
3072 */
3073static u64 access_sdma_pcie_req_tracking_cor_err_cnt(
3074 const struct cntr_entry *entry,
3075 void *context, int vl, int mode, u64 data)
3076{
3077 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3078
3079 return dd->send_dma_err_status_cnt[3];
3080}
3081
3082static u64 access_sdma_pcie_req_tracking_unc_err_cnt(
3083 const struct cntr_entry *entry,
3084 void *context, int vl, int mode, u64 data)
3085{
3086 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3087
3088 return dd->send_dma_err_status_cnt[2];
3089}
3090
3091static u64 access_sdma_csr_parity_err_cnt(const struct cntr_entry *entry,
3092 void *context, int vl, int mode,
3093 u64 data)
3094{
3095 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3096
3097 return dd->send_dma_err_status_cnt[1];
3098}
3099
3100static u64 access_sdma_rpy_tag_err_cnt(const struct cntr_entry *entry,
3101 void *context, int vl, int mode,
3102 u64 data)
3103{
3104 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3105
3106 return dd->send_dma_err_status_cnt[0];
3107}
3108
3109/*
3110 * Software counters corresponding to each of the
3111 * error status bits within SendEgressErrStatus
3112 */
3113static u64 access_tx_read_pio_memory_csr_unc_err_cnt(
3114 const struct cntr_entry *entry,
3115 void *context, int vl, int mode, u64 data)
3116{
3117 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3118
3119 return dd->send_egress_err_status_cnt[63];
3120}
3121
3122static u64 access_tx_read_sdma_memory_csr_err_cnt(
3123 const struct cntr_entry *entry,
3124 void *context, int vl, int mode, u64 data)
3125{
3126 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3127
3128 return dd->send_egress_err_status_cnt[62];
3129}
3130
3131static u64 access_tx_egress_fifo_cor_err_cnt(const struct cntr_entry *entry,
3132 void *context, int vl, int mode,
3133 u64 data)
3134{
3135 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3136
3137 return dd->send_egress_err_status_cnt[61];
3138}
3139
3140static u64 access_tx_read_pio_memory_cor_err_cnt(const struct cntr_entry *entry,
3141 void *context, int vl,
3142 int mode, u64 data)
3143{
3144 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3145
3146 return dd->send_egress_err_status_cnt[60];
3147}
3148
3149static u64 access_tx_read_sdma_memory_cor_err_cnt(
3150 const struct cntr_entry *entry,
3151 void *context, int vl, int mode, u64 data)
3152{
3153 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3154
3155 return dd->send_egress_err_status_cnt[59];
3156}
3157
3158static u64 access_tx_sb_hdr_cor_err_cnt(const struct cntr_entry *entry,
3159 void *context, int vl, int mode,
3160 u64 data)
3161{
3162 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3163
3164 return dd->send_egress_err_status_cnt[58];
3165}
3166
3167static u64 access_tx_credit_overrun_err_cnt(const struct cntr_entry *entry,
3168 void *context, int vl, int mode,
3169 u64 data)
3170{
3171 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3172
3173 return dd->send_egress_err_status_cnt[57];
3174}
3175
3176static u64 access_tx_launch_fifo8_cor_err_cnt(const struct cntr_entry *entry,
3177 void *context, int vl, int mode,
3178 u64 data)
3179{
3180 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3181
3182 return dd->send_egress_err_status_cnt[56];
3183}
3184
3185static u64 access_tx_launch_fifo7_cor_err_cnt(const struct cntr_entry *entry,
3186 void *context, int vl, int mode,
3187 u64 data)
3188{
3189 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3190
3191 return dd->send_egress_err_status_cnt[55];
3192}
3193
3194static u64 access_tx_launch_fifo6_cor_err_cnt(const struct cntr_entry *entry,
3195 void *context, int vl, int mode,
3196 u64 data)
3197{
3198 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3199
3200 return dd->send_egress_err_status_cnt[54];
3201}
3202
3203static u64 access_tx_launch_fifo5_cor_err_cnt(const struct cntr_entry *entry,
3204 void *context, int vl, int mode,
3205 u64 data)
3206{
3207 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3208
3209 return dd->send_egress_err_status_cnt[53];
3210}
3211
3212static u64 access_tx_launch_fifo4_cor_err_cnt(const struct cntr_entry *entry,
3213 void *context, int vl, int mode,
3214 u64 data)
3215{
3216 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3217
3218 return dd->send_egress_err_status_cnt[52];
3219}
3220
3221static u64 access_tx_launch_fifo3_cor_err_cnt(const struct cntr_entry *entry,
3222 void *context, int vl, int mode,
3223 u64 data)
3224{
3225 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3226
3227 return dd->send_egress_err_status_cnt[51];
3228}
3229
3230static u64 access_tx_launch_fifo2_cor_err_cnt(const struct cntr_entry *entry,
3231 void *context, int vl, int mode,
3232 u64 data)
3233{
3234 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3235
3236 return dd->send_egress_err_status_cnt[50];
3237}
3238
3239static u64 access_tx_launch_fifo1_cor_err_cnt(const struct cntr_entry *entry,
3240 void *context, int vl, int mode,
3241 u64 data)
3242{
3243 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3244
3245 return dd->send_egress_err_status_cnt[49];
3246}
3247
3248static u64 access_tx_launch_fifo0_cor_err_cnt(const struct cntr_entry *entry,
3249 void *context, int vl, int mode,
3250 u64 data)
3251{
3252 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3253
3254 return dd->send_egress_err_status_cnt[48];
3255}
3256
3257static u64 access_tx_credit_return_vl_err_cnt(const struct cntr_entry *entry,
3258 void *context, int vl, int mode,
3259 u64 data)
3260{
3261 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3262
3263 return dd->send_egress_err_status_cnt[47];
3264}
3265
3266static u64 access_tx_hcrc_insertion_err_cnt(const struct cntr_entry *entry,
3267 void *context, int vl, int mode,
3268 u64 data)
3269{
3270 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3271
3272 return dd->send_egress_err_status_cnt[46];
3273}
3274
3275static u64 access_tx_egress_fifo_unc_err_cnt(const struct cntr_entry *entry,
3276 void *context, int vl, int mode,
3277 u64 data)
3278{
3279 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3280
3281 return dd->send_egress_err_status_cnt[45];
3282}
3283
3284static u64 access_tx_read_pio_memory_unc_err_cnt(const struct cntr_entry *entry,
3285 void *context, int vl,
3286 int mode, u64 data)
3287{
3288 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3289
3290 return dd->send_egress_err_status_cnt[44];
3291}
3292
3293static u64 access_tx_read_sdma_memory_unc_err_cnt(
3294 const struct cntr_entry *entry,
3295 void *context, int vl, int mode, u64 data)
3296{
3297 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3298
3299 return dd->send_egress_err_status_cnt[43];
3300}
3301
3302static u64 access_tx_sb_hdr_unc_err_cnt(const struct cntr_entry *entry,
3303 void *context, int vl, int mode,
3304 u64 data)
3305{
3306 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3307
3308 return dd->send_egress_err_status_cnt[42];
3309}
3310
3311static u64 access_tx_credit_return_partiy_err_cnt(
3312 const struct cntr_entry *entry,
3313 void *context, int vl, int mode, u64 data)
3314{
3315 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3316
3317 return dd->send_egress_err_status_cnt[41];
3318}
3319
3320static u64 access_tx_launch_fifo8_unc_or_parity_err_cnt(
3321 const struct cntr_entry *entry,
3322 void *context, int vl, int mode, u64 data)
3323{
3324 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3325
3326 return dd->send_egress_err_status_cnt[40];
3327}
3328
3329static u64 access_tx_launch_fifo7_unc_or_parity_err_cnt(
3330 const struct cntr_entry *entry,
3331 void *context, int vl, int mode, u64 data)
3332{
3333 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3334
3335 return dd->send_egress_err_status_cnt[39];
3336}
3337
3338static u64 access_tx_launch_fifo6_unc_or_parity_err_cnt(
3339 const struct cntr_entry *entry,
3340 void *context, int vl, int mode, u64 data)
3341{
3342 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3343
3344 return dd->send_egress_err_status_cnt[38];
3345}
3346
3347static u64 access_tx_launch_fifo5_unc_or_parity_err_cnt(
3348 const struct cntr_entry *entry,
3349 void *context, int vl, int mode, u64 data)
3350{
3351 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3352
3353 return dd->send_egress_err_status_cnt[37];
3354}
3355
3356static u64 access_tx_launch_fifo4_unc_or_parity_err_cnt(
3357 const struct cntr_entry *entry,
3358 void *context, int vl, int mode, u64 data)
3359{
3360 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3361
3362 return dd->send_egress_err_status_cnt[36];
3363}
3364
3365static u64 access_tx_launch_fifo3_unc_or_parity_err_cnt(
3366 const struct cntr_entry *entry,
3367 void *context, int vl, int mode, u64 data)
3368{
3369 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3370
3371 return dd->send_egress_err_status_cnt[35];
3372}
3373
3374static u64 access_tx_launch_fifo2_unc_or_parity_err_cnt(
3375 const struct cntr_entry *entry,
3376 void *context, int vl, int mode, u64 data)
3377{
3378 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3379
3380 return dd->send_egress_err_status_cnt[34];
3381}
3382
3383static u64 access_tx_launch_fifo1_unc_or_parity_err_cnt(
3384 const struct cntr_entry *entry,
3385 void *context, int vl, int mode, u64 data)
3386{
3387 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3388
3389 return dd->send_egress_err_status_cnt[33];
3390}
3391
3392static u64 access_tx_launch_fifo0_unc_or_parity_err_cnt(
3393 const struct cntr_entry *entry,
3394 void *context, int vl, int mode, u64 data)
3395{
3396 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3397
3398 return dd->send_egress_err_status_cnt[32];
3399}
3400
3401static u64 access_tx_sdma15_disallowed_packet_err_cnt(
3402 const struct cntr_entry *entry,
3403 void *context, int vl, int mode, u64 data)
3404{
3405 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3406
3407 return dd->send_egress_err_status_cnt[31];
3408}
3409
3410static u64 access_tx_sdma14_disallowed_packet_err_cnt(
3411 const struct cntr_entry *entry,
3412 void *context, int vl, int mode, u64 data)
3413{
3414 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3415
3416 return dd->send_egress_err_status_cnt[30];
3417}
3418
3419static u64 access_tx_sdma13_disallowed_packet_err_cnt(
3420 const struct cntr_entry *entry,
3421 void *context, int vl, int mode, u64 data)
3422{
3423 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3424
3425 return dd->send_egress_err_status_cnt[29];
3426}
3427
3428static u64 access_tx_sdma12_disallowed_packet_err_cnt(
3429 const struct cntr_entry *entry,
3430 void *context, int vl, int mode, u64 data)
3431{
3432 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3433
3434 return dd->send_egress_err_status_cnt[28];
3435}
3436
3437static u64 access_tx_sdma11_disallowed_packet_err_cnt(
3438 const struct cntr_entry *entry,
3439 void *context, int vl, int mode, u64 data)
3440{
3441 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3442
3443 return dd->send_egress_err_status_cnt[27];
3444}
3445
3446static u64 access_tx_sdma10_disallowed_packet_err_cnt(
3447 const struct cntr_entry *entry,
3448 void *context, int vl, int mode, u64 data)
3449{
3450 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3451
3452 return dd->send_egress_err_status_cnt[26];
3453}
3454
3455static u64 access_tx_sdma9_disallowed_packet_err_cnt(
3456 const struct cntr_entry *entry,
3457 void *context, int vl, int mode, u64 data)
3458{
3459 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3460
3461 return dd->send_egress_err_status_cnt[25];
3462}
3463
3464static u64 access_tx_sdma8_disallowed_packet_err_cnt(
3465 const struct cntr_entry *entry,
3466 void *context, int vl, int mode, u64 data)
3467{
3468 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3469
3470 return dd->send_egress_err_status_cnt[24];
3471}
3472
3473static u64 access_tx_sdma7_disallowed_packet_err_cnt(
3474 const struct cntr_entry *entry,
3475 void *context, int vl, int mode, u64 data)
3476{
3477 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3478
3479 return dd->send_egress_err_status_cnt[23];
3480}
3481
3482static u64 access_tx_sdma6_disallowed_packet_err_cnt(
3483 const struct cntr_entry *entry,
3484 void *context, int vl, int mode, u64 data)
3485{
3486 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3487
3488 return dd->send_egress_err_status_cnt[22];
3489}
3490
3491static u64 access_tx_sdma5_disallowed_packet_err_cnt(
3492 const struct cntr_entry *entry,
3493 void *context, int vl, int mode, u64 data)
3494{
3495 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3496
3497 return dd->send_egress_err_status_cnt[21];
3498}
3499
3500static u64 access_tx_sdma4_disallowed_packet_err_cnt(
3501 const struct cntr_entry *entry,
3502 void *context, int vl, int mode, u64 data)
3503{
3504 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3505
3506 return dd->send_egress_err_status_cnt[20];
3507}
3508
3509static u64 access_tx_sdma3_disallowed_packet_err_cnt(
3510 const struct cntr_entry *entry,
3511 void *context, int vl, int mode, u64 data)
3512{
3513 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3514
3515 return dd->send_egress_err_status_cnt[19];
3516}
3517
3518static u64 access_tx_sdma2_disallowed_packet_err_cnt(
3519 const struct cntr_entry *entry,
3520 void *context, int vl, int mode, u64 data)
3521{
3522 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3523
3524 return dd->send_egress_err_status_cnt[18];
3525}
3526
3527static u64 access_tx_sdma1_disallowed_packet_err_cnt(
3528 const struct cntr_entry *entry,
3529 void *context, int vl, int mode, u64 data)
3530{
3531 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3532
3533 return dd->send_egress_err_status_cnt[17];
3534}
3535
3536static u64 access_tx_sdma0_disallowed_packet_err_cnt(
3537 const struct cntr_entry *entry,
3538 void *context, int vl, int mode, u64 data)
3539{
3540 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3541
3542 return dd->send_egress_err_status_cnt[16];
3543}
3544
3545static u64 access_tx_config_parity_err_cnt(const struct cntr_entry *entry,
3546 void *context, int vl, int mode,
3547 u64 data)
3548{
3549 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3550
3551 return dd->send_egress_err_status_cnt[15];
3552}
3553
3554static u64 access_tx_sbrd_ctl_csr_parity_err_cnt(const struct cntr_entry *entry,
3555 void *context, int vl,
3556 int mode, u64 data)
3557{
3558 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3559
3560 return dd->send_egress_err_status_cnt[14];
3561}
3562
3563static u64 access_tx_launch_csr_parity_err_cnt(const struct cntr_entry *entry,
3564 void *context, int vl, int mode,
3565 u64 data)
3566{
3567 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3568
3569 return dd->send_egress_err_status_cnt[13];
3570}
3571
3572static u64 access_tx_illegal_vl_err_cnt(const struct cntr_entry *entry,
3573 void *context, int vl, int mode,
3574 u64 data)
3575{
3576 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3577
3578 return dd->send_egress_err_status_cnt[12];
3579}
3580
3581static u64 access_tx_sbrd_ctl_state_machine_parity_err_cnt(
3582 const struct cntr_entry *entry,
3583 void *context, int vl, int mode, u64 data)
3584{
3585 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3586
3587 return dd->send_egress_err_status_cnt[11];
3588}
3589
3590static u64 access_egress_reserved_10_err_cnt(const struct cntr_entry *entry,
3591 void *context, int vl, int mode,
3592 u64 data)
3593{
3594 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3595
3596 return dd->send_egress_err_status_cnt[10];
3597}
3598
3599static u64 access_egress_reserved_9_err_cnt(const struct cntr_entry *entry,
3600 void *context, int vl, int mode,
3601 u64 data)
3602{
3603 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3604
3605 return dd->send_egress_err_status_cnt[9];
3606}
3607
3608static u64 access_tx_sdma_launch_intf_parity_err_cnt(
3609 const struct cntr_entry *entry,
3610 void *context, int vl, int mode, u64 data)
3611{
3612 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3613
3614 return dd->send_egress_err_status_cnt[8];
3615}
3616
3617static u64 access_tx_pio_launch_intf_parity_err_cnt(
3618 const struct cntr_entry *entry,
3619 void *context, int vl, int mode, u64 data)
3620{
3621 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3622
3623 return dd->send_egress_err_status_cnt[7];
3624}
3625
3626static u64 access_egress_reserved_6_err_cnt(const struct cntr_entry *entry,
3627 void *context, int vl, int mode,
3628 u64 data)
3629{
3630 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3631
3632 return dd->send_egress_err_status_cnt[6];
3633}
3634
3635static u64 access_tx_incorrect_link_state_err_cnt(
3636 const struct cntr_entry *entry,
3637 void *context, int vl, int mode, u64 data)
3638{
3639 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3640
3641 return dd->send_egress_err_status_cnt[5];
3642}
3643
3644static u64 access_tx_linkdown_err_cnt(const struct cntr_entry *entry,
3645 void *context, int vl, int mode,
3646 u64 data)
3647{
3648 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3649
3650 return dd->send_egress_err_status_cnt[4];
3651}
3652
3653static u64 access_tx_egress_fifi_underrun_or_parity_err_cnt(
3654 const struct cntr_entry *entry,
3655 void *context, int vl, int mode, u64 data)
3656{
3657 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3658
3659 return dd->send_egress_err_status_cnt[3];
3660}
3661
3662static u64 access_egress_reserved_2_err_cnt(const struct cntr_entry *entry,
3663 void *context, int vl, int mode,
3664 u64 data)
3665{
3666 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3667
3668 return dd->send_egress_err_status_cnt[2];
3669}
3670
3671static u64 access_tx_pkt_integrity_mem_unc_err_cnt(
3672 const struct cntr_entry *entry,
3673 void *context, int vl, int mode, u64 data)
3674{
3675 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3676
3677 return dd->send_egress_err_status_cnt[1];
3678}
3679
3680static u64 access_tx_pkt_integrity_mem_cor_err_cnt(
3681 const struct cntr_entry *entry,
3682 void *context, int vl, int mode, u64 data)
3683{
3684 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3685
3686 return dd->send_egress_err_status_cnt[0];
3687}
3688
3689/*
3690 * Software counters corresponding to each of the
3691 * error status bits within SendErrStatus
3692 */
3693static u64 access_send_csr_write_bad_addr_err_cnt(
3694 const struct cntr_entry *entry,
3695 void *context, int vl, int mode, u64 data)
3696{
3697 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3698
3699 return dd->send_err_status_cnt[2];
3700}
3701
3702static u64 access_send_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
3703 void *context, int vl,
3704 int mode, u64 data)
3705{
3706 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3707
3708 return dd->send_err_status_cnt[1];
3709}
3710
3711static u64 access_send_csr_parity_cnt(const struct cntr_entry *entry,
3712 void *context, int vl, int mode,
3713 u64 data)
3714{
3715 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3716
3717 return dd->send_err_status_cnt[0];
3718}
3719
3720/*
3721 * Software counters corresponding to each of the
3722 * error status bits within SendCtxtErrStatus
3723 */
3724static u64 access_pio_write_out_of_bounds_err_cnt(
3725 const struct cntr_entry *entry,
3726 void *context, int vl, int mode, u64 data)
3727{
3728 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3729
3730 return dd->sw_ctxt_err_status_cnt[4];
3731}
3732
3733static u64 access_pio_write_overflow_err_cnt(const struct cntr_entry *entry,
3734 void *context, int vl, int mode,
3735 u64 data)
3736{
3737 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3738
3739 return dd->sw_ctxt_err_status_cnt[3];
3740}
3741
3742static u64 access_pio_write_crosses_boundary_err_cnt(
3743 const struct cntr_entry *entry,
3744 void *context, int vl, int mode, u64 data)
3745{
3746 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3747
3748 return dd->sw_ctxt_err_status_cnt[2];
3749}
3750
3751static u64 access_pio_disallowed_packet_err_cnt(const struct cntr_entry *entry,
3752 void *context, int vl,
3753 int mode, u64 data)
3754{
3755 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3756
3757 return dd->sw_ctxt_err_status_cnt[1];
3758}
3759
3760static u64 access_pio_inconsistent_sop_err_cnt(const struct cntr_entry *entry,
3761 void *context, int vl, int mode,
3762 u64 data)
3763{
3764 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3765
3766 return dd->sw_ctxt_err_status_cnt[0];
3767}
3768
3769/*
3770 * Software counters corresponding to each of the
3771 * error status bits within SendDmaEngErrStatus
3772 */
3773static u64 access_sdma_header_request_fifo_cor_err_cnt(
3774 const struct cntr_entry *entry,
3775 void *context, int vl, int mode, u64 data)
3776{
3777 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3778
3779 return dd->sw_send_dma_eng_err_status_cnt[23];
3780}
3781
3782static u64 access_sdma_header_storage_cor_err_cnt(
3783 const struct cntr_entry *entry,
3784 void *context, int vl, int mode, u64 data)
3785{
3786 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3787
3788 return dd->sw_send_dma_eng_err_status_cnt[22];
3789}
3790
3791static u64 access_sdma_packet_tracking_cor_err_cnt(
3792 const struct cntr_entry *entry,
3793 void *context, int vl, int mode, u64 data)
3794{
3795 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3796
3797 return dd->sw_send_dma_eng_err_status_cnt[21];
3798}
3799
3800static u64 access_sdma_assembly_cor_err_cnt(const struct cntr_entry *entry,
3801 void *context, int vl, int mode,
3802 u64 data)
3803{
3804 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3805
3806 return dd->sw_send_dma_eng_err_status_cnt[20];
3807}
3808
3809static u64 access_sdma_desc_table_cor_err_cnt(const struct cntr_entry *entry,
3810 void *context, int vl, int mode,
3811 u64 data)
3812{
3813 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3814
3815 return dd->sw_send_dma_eng_err_status_cnt[19];
3816}
3817
3818static u64 access_sdma_header_request_fifo_unc_err_cnt(
3819 const struct cntr_entry *entry,
3820 void *context, int vl, int mode, u64 data)
3821{
3822 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3823
3824 return dd->sw_send_dma_eng_err_status_cnt[18];
3825}
3826
3827static u64 access_sdma_header_storage_unc_err_cnt(
3828 const struct cntr_entry *entry,
3829 void *context, int vl, int mode, u64 data)
3830{
3831 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3832
3833 return dd->sw_send_dma_eng_err_status_cnt[17];
3834}
3835
3836static u64 access_sdma_packet_tracking_unc_err_cnt(
3837 const struct cntr_entry *entry,
3838 void *context, int vl, int mode, u64 data)
3839{
3840 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3841
3842 return dd->sw_send_dma_eng_err_status_cnt[16];
3843}
3844
3845static u64 access_sdma_assembly_unc_err_cnt(const struct cntr_entry *entry,
3846 void *context, int vl, int mode,
3847 u64 data)
3848{
3849 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3850
3851 return dd->sw_send_dma_eng_err_status_cnt[15];
3852}
3853
3854static u64 access_sdma_desc_table_unc_err_cnt(const struct cntr_entry *entry,
3855 void *context, int vl, int mode,
3856 u64 data)
3857{
3858 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3859
3860 return dd->sw_send_dma_eng_err_status_cnt[14];
3861}
3862
3863static u64 access_sdma_timeout_err_cnt(const struct cntr_entry *entry,
3864 void *context, int vl, int mode,
3865 u64 data)
3866{
3867 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3868
3869 return dd->sw_send_dma_eng_err_status_cnt[13];
3870}
3871
3872static u64 access_sdma_header_length_err_cnt(const struct cntr_entry *entry,
3873 void *context, int vl, int mode,
3874 u64 data)
3875{
3876 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3877
3878 return dd->sw_send_dma_eng_err_status_cnt[12];
3879}
3880
3881static u64 access_sdma_header_address_err_cnt(const struct cntr_entry *entry,
3882 void *context, int vl, int mode,
3883 u64 data)
3884{
3885 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3886
3887 return dd->sw_send_dma_eng_err_status_cnt[11];
3888}
3889
3890static u64 access_sdma_header_select_err_cnt(const struct cntr_entry *entry,
3891 void *context, int vl, int mode,
3892 u64 data)
3893{
3894 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3895
3896 return dd->sw_send_dma_eng_err_status_cnt[10];
3897}
3898
3899static u64 access_sdma_reserved_9_err_cnt(const struct cntr_entry *entry,
3900 void *context, int vl, int mode,
3901 u64 data)
3902{
3903 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3904
3905 return dd->sw_send_dma_eng_err_status_cnt[9];
3906}
3907
3908static u64 access_sdma_packet_desc_overflow_err_cnt(
3909 const struct cntr_entry *entry,
3910 void *context, int vl, int mode, u64 data)
3911{
3912 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3913
3914 return dd->sw_send_dma_eng_err_status_cnt[8];
3915}
3916
3917static u64 access_sdma_length_mismatch_err_cnt(const struct cntr_entry *entry,
3918 void *context, int vl,
3919 int mode, u64 data)
3920{
3921 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3922
3923 return dd->sw_send_dma_eng_err_status_cnt[7];
3924}
3925
3926static u64 access_sdma_halt_err_cnt(const struct cntr_entry *entry,
3927 void *context, int vl, int mode, u64 data)
3928{
3929 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3930
3931 return dd->sw_send_dma_eng_err_status_cnt[6];
3932}
3933
3934static u64 access_sdma_mem_read_err_cnt(const struct cntr_entry *entry,
3935 void *context, int vl, int mode,
3936 u64 data)
3937{
3938 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3939
3940 return dd->sw_send_dma_eng_err_status_cnt[5];
3941}
3942
3943static u64 access_sdma_first_desc_err_cnt(const struct cntr_entry *entry,
3944 void *context, int vl, int mode,
3945 u64 data)
3946{
3947 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3948
3949 return dd->sw_send_dma_eng_err_status_cnt[4];
3950}
3951
3952static u64 access_sdma_tail_out_of_bounds_err_cnt(
3953 const struct cntr_entry *entry,
3954 void *context, int vl, int mode, u64 data)
3955{
3956 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3957
3958 return dd->sw_send_dma_eng_err_status_cnt[3];
3959}
3960
3961static u64 access_sdma_too_long_err_cnt(const struct cntr_entry *entry,
3962 void *context, int vl, int mode,
3963 u64 data)
3964{
3965 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3966
3967 return dd->sw_send_dma_eng_err_status_cnt[2];
3968}
3969
3970static u64 access_sdma_gen_mismatch_err_cnt(const struct cntr_entry *entry,
3971 void *context, int vl, int mode,
3972 u64 data)
3973{
3974 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3975
3976 return dd->sw_send_dma_eng_err_status_cnt[1];
3977}
3978
3979static u64 access_sdma_wrong_dw_err_cnt(const struct cntr_entry *entry,
3980 void *context, int vl, int mode,
3981 u64 data)
3982{
3983 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3984
3985 return dd->sw_send_dma_eng_err_status_cnt[0];
3986}
3987
2b719046
JP		 3988static u64 access_dc_rcv_err_cnt(const struct cntr_entry *entry,
3989 void *context, int vl, int mode,
3990 u64 data)
3991{
3992 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3993
3994 u64 val = 0;
3995 u64 csr = entry->csr;
3996
3997 val = read_write_csr(dd, csr, mode, data);
3998 if (mode == CNTR_MODE_R) {
3999 val = val > CNTR_MAX - dd->sw_rcv_bypass_packet_errors ?
4000 CNTR_MAX : val + dd->sw_rcv_bypass_packet_errors;
4001 } else if (mode == CNTR_MODE_W) {
4002 dd->sw_rcv_bypass_packet_errors = 0;
4003 } else {
4004 dd_dev_err(dd, "Invalid cntr register access mode");
4005 return 0;
4006 }
4007 return val;
4008}
4009
77241056
MM		 4010#define def_access_sw_cpu(cntr) \
4011static u64 access_sw_cpu_##cntr(const struct cntr_entry *entry, \
4012 void *context, int vl, int mode, u64 data) \
4013{ \
4014 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \
4eb06882
DD		 4015 return read_write_cpu(ppd->dd, &ppd->ibport_data.rvp.z_ ##cntr, \
4016 ppd->ibport_data.rvp.cntr, vl, \
77241056
MM		 4017 mode, data); \
4018}
4019
4020def_access_sw_cpu(rc_acks);
4021def_access_sw_cpu(rc_qacks);
4022def_access_sw_cpu(rc_delayed_comp);
4023
4024#define def_access_ibp_counter(cntr) \
4025static u64 access_ibp_##cntr(const struct cntr_entry *entry, \
4026 void *context, int vl, int mode, u64 data) \
4027{ \
4028 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \
4029 \
4030 if (vl != CNTR_INVALID_VL) \
4031 return 0; \
4032 \
4eb06882 4033 return read_write_sw(ppd->dd, &ppd->ibport_data.rvp.n_ ##cntr, \
77241056
MM		 4034 mode, data); \
4035}
4036
4037def_access_ibp_counter(loop_pkts);
4038def_access_ibp_counter(rc_resends);
4039def_access_ibp_counter(rnr_naks);
4040def_access_ibp_counter(other_naks);
4041def_access_ibp_counter(rc_timeouts);
4042def_access_ibp_counter(pkt_drops);
4043def_access_ibp_counter(dmawait);
4044def_access_ibp_counter(rc_seqnak);
4045def_access_ibp_counter(rc_dupreq);
4046def_access_ibp_counter(rdma_seq);
4047def_access_ibp_counter(unaligned);
4048def_access_ibp_counter(seq_naks);
4049
4050static struct cntr_entry dev_cntrs[DEV_CNTR_LAST] = {
4051[C_RCV_OVF] = RXE32_DEV_CNTR_ELEM(RcvOverflow, RCV_BUF_OVFL_CNT, CNTR_SYNTH),
4052[C_RX_TID_FULL] = RXE32_DEV_CNTR_ELEM(RxTIDFullEr, RCV_TID_FULL_ERR_CNT,
4053 CNTR_NORMAL),
4054[C_RX_TID_INVALID] = RXE32_DEV_CNTR_ELEM(RxTIDInvalid, RCV_TID_VALID_ERR_CNT,
4055 CNTR_NORMAL),
4056[C_RX_TID_FLGMS] = RXE32_DEV_CNTR_ELEM(RxTidFLGMs,
4057 RCV_TID_FLOW_GEN_MISMATCH_CNT,
4058 CNTR_NORMAL),
77241056
MM		 4059[C_RX_CTX_EGRS] = RXE32_DEV_CNTR_ELEM(RxCtxEgrS, RCV_CONTEXT_EGR_STALL,
4060 CNTR_NORMAL),
4061[C_RCV_TID_FLSMS] = RXE32_DEV_CNTR_ELEM(RxTidFLSMs,
4062 RCV_TID_FLOW_SEQ_MISMATCH_CNT, CNTR_NORMAL),
4063[C_CCE_PCI_CR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciCrSt,
4064 CCE_PCIE_POSTED_CRDT_STALL_CNT, CNTR_NORMAL),
4065[C_CCE_PCI_TR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciTrSt, CCE_PCIE_TRGT_STALL_CNT,
4066 CNTR_NORMAL),
4067[C_CCE_PIO_WR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePioWrSt, CCE_PIO_WR_STALL_CNT,
4068 CNTR_NORMAL),
4069[C_CCE_ERR_INT] = CCE_INT_DEV_CNTR_ELEM(CceErrInt, CCE_ERR_INT_CNT,
4070 CNTR_NORMAL),
4071[C_CCE_SDMA_INT] = CCE_INT_DEV_CNTR_ELEM(CceSdmaInt, CCE_SDMA_INT_CNT,
4072 CNTR_NORMAL),
4073[C_CCE_MISC_INT] = CCE_INT_DEV_CNTR_ELEM(CceMiscInt, CCE_MISC_INT_CNT,
4074 CNTR_NORMAL),
4075[C_CCE_RCV_AV_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvAvInt, CCE_RCV_AVAIL_INT_CNT,
4076 CNTR_NORMAL),
4077[C_CCE_RCV_URG_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvUrgInt,
4078 CCE_RCV_URGENT_INT_CNT, CNTR_NORMAL),
4079[C_CCE_SEND_CR_INT] = CCE_INT_DEV_CNTR_ELEM(CceSndCrInt,
4080 CCE_SEND_CREDIT_INT_CNT, CNTR_NORMAL),
4081[C_DC_UNC_ERR] = DC_PERF_CNTR(DcUnctblErr, DCC_ERR_UNCORRECTABLE_CNT,
4082 CNTR_SYNTH),
2b719046
JP		 4083[C_DC_RCV_ERR] = CNTR_ELEM("DcRecvErr", DCC_ERR_PORTRCV_ERR_CNT, 0, CNTR_SYNTH,
4084 access_dc_rcv_err_cnt),
77241056
MM		 4085[C_DC_FM_CFG_ERR] = DC_PERF_CNTR(DcFmCfgErr, DCC_ERR_FMCONFIG_ERR_CNT,
4086 CNTR_SYNTH),
4087[C_DC_RMT_PHY_ERR] = DC_PERF_CNTR(DcRmtPhyErr, DCC_ERR_RCVREMOTE_PHY_ERR_CNT,
4088 CNTR_SYNTH),
4089[C_DC_DROPPED_PKT] = DC_PERF_CNTR(DcDroppedPkt, DCC_ERR_DROPPED_PKT_CNT,
4090 CNTR_SYNTH),
4091[C_DC_MC_XMIT_PKTS] = DC_PERF_CNTR(DcMcXmitPkts,
4092 DCC_PRF_PORT_XMIT_MULTICAST_CNT, CNTR_SYNTH),
4093[C_DC_MC_RCV_PKTS] = DC_PERF_CNTR(DcMcRcvPkts,
4094 DCC_PRF_PORT_RCV_MULTICAST_PKT_CNT,
4095 CNTR_SYNTH),
4096[C_DC_XMIT_CERR] = DC_PERF_CNTR(DcXmitCorr,
4097 DCC_PRF_PORT_XMIT_CORRECTABLE_CNT, CNTR_SYNTH),
4098[C_DC_RCV_CERR] = DC_PERF_CNTR(DcRcvCorrCnt, DCC_PRF_PORT_RCV_CORRECTABLE_CNT,
4099 CNTR_SYNTH),
4100[C_DC_RCV_FCC] = DC_PERF_CNTR(DcRxFCntl, DCC_PRF_RX_FLOW_CRTL_CNT,
4101 CNTR_SYNTH),
4102[C_DC_XMIT_FCC] = DC_PERF_CNTR(DcXmitFCntl, DCC_PRF_TX_FLOW_CRTL_CNT,
4103 CNTR_SYNTH),
4104[C_DC_XMIT_FLITS] = DC_PERF_CNTR(DcXmitFlits, DCC_PRF_PORT_XMIT_DATA_CNT,
4105 CNTR_SYNTH),
4106[C_DC_RCV_FLITS] = DC_PERF_CNTR(DcRcvFlits, DCC_PRF_PORT_RCV_DATA_CNT,
4107 CNTR_SYNTH),
4108[C_DC_XMIT_PKTS] = DC_PERF_CNTR(DcXmitPkts, DCC_PRF_PORT_XMIT_PKTS_CNT,
4109 CNTR_SYNTH),
4110[C_DC_RCV_PKTS] = DC_PERF_CNTR(DcRcvPkts, DCC_PRF_PORT_RCV_PKTS_CNT,
4111 CNTR_SYNTH),
4112[C_DC_RX_FLIT_VL] = DC_PERF_CNTR(DcRxFlitVl, DCC_PRF_PORT_VL_RCV_DATA_CNT,
4113 CNTR_SYNTH | CNTR_VL),
4114[C_DC_RX_PKT_VL] = DC_PERF_CNTR(DcRxPktVl, DCC_PRF_PORT_VL_RCV_PKTS_CNT,
4115 CNTR_SYNTH | CNTR_VL),
4116[C_DC_RCV_FCN] = DC_PERF_CNTR(DcRcvFcn, DCC_PRF_PORT_RCV_FECN_CNT, CNTR_SYNTH),
4117[C_DC_RCV_FCN_VL] = DC_PERF_CNTR(DcRcvFcnVl, DCC_PRF_PORT_VL_RCV_FECN_CNT,
4118 CNTR_SYNTH | CNTR_VL),
4119[C_DC_RCV_BCN] = DC_PERF_CNTR(DcRcvBcn, DCC_PRF_PORT_RCV_BECN_CNT, CNTR_SYNTH),
4120[C_DC_RCV_BCN_VL] = DC_PERF_CNTR(DcRcvBcnVl, DCC_PRF_PORT_VL_RCV_BECN_CNT,
4121 CNTR_SYNTH | CNTR_VL),
4122[C_DC_RCV_BBL] = DC_PERF_CNTR(DcRcvBbl, DCC_PRF_PORT_RCV_BUBBLE_CNT,
4123 CNTR_SYNTH),
4124[C_DC_RCV_BBL_VL] = DC_PERF_CNTR(DcRcvBblVl, DCC_PRF_PORT_VL_RCV_BUBBLE_CNT,
4125 CNTR_SYNTH | CNTR_VL),
4126[C_DC_MARK_FECN] = DC_PERF_CNTR(DcMarkFcn, DCC_PRF_PORT_MARK_FECN_CNT,
4127 CNTR_SYNTH),
4128[C_DC_MARK_FECN_VL] = DC_PERF_CNTR(DcMarkFcnVl, DCC_PRF_PORT_VL_MARK_FECN_CNT,
4129 CNTR_SYNTH | CNTR_VL),
4130[C_DC_TOTAL_CRC] =
4131 DC_PERF_CNTR_LCB(DcTotCrc, DC_LCB_ERR_INFO_TOTAL_CRC_ERR,
4132 CNTR_SYNTH),
4133[C_DC_CRC_LN0] = DC_PERF_CNTR_LCB(DcCrcLn0, DC_LCB_ERR_INFO_CRC_ERR_LN0,
4134 CNTR_SYNTH),
4135[C_DC_CRC_LN1] = DC_PERF_CNTR_LCB(DcCrcLn1, DC_LCB_ERR_INFO_CRC_ERR_LN1,
4136 CNTR_SYNTH),
4137[C_DC_CRC_LN2] = DC_PERF_CNTR_LCB(DcCrcLn2, DC_LCB_ERR_INFO_CRC_ERR_LN2,
4138 CNTR_SYNTH),
4139[C_DC_CRC_LN3] = DC_PERF_CNTR_LCB(DcCrcLn3, DC_LCB_ERR_INFO_CRC_ERR_LN3,
4140 CNTR_SYNTH),
4141[C_DC_CRC_MULT_LN] =
4142 DC_PERF_CNTR_LCB(DcMultLn, DC_LCB_ERR_INFO_CRC_ERR_MULTI_LN,
4143 CNTR_SYNTH),
4144[C_DC_TX_REPLAY] = DC_PERF_CNTR_LCB(DcTxReplay, DC_LCB_ERR_INFO_TX_REPLAY_CNT,
4145 CNTR_SYNTH),
4146[C_DC_RX_REPLAY] = DC_PERF_CNTR_LCB(DcRxReplay, DC_LCB_ERR_INFO_RX_REPLAY_CNT,
4147 CNTR_SYNTH),
4148[C_DC_SEQ_CRC_CNT] =
4149 DC_PERF_CNTR_LCB(DcLinkSeqCrc, DC_LCB_ERR_INFO_SEQ_CRC_CNT,
4150 CNTR_SYNTH),
4151[C_DC_ESC0_ONLY_CNT] =
4152 DC_PERF_CNTR_LCB(DcEsc0, DC_LCB_ERR_INFO_ESCAPE_0_ONLY_CNT,
4153 CNTR_SYNTH),
4154[C_DC_ESC0_PLUS1_CNT] =
4155 DC_PERF_CNTR_LCB(DcEsc1, DC_LCB_ERR_INFO_ESCAPE_0_PLUS1_CNT,
4156 CNTR_SYNTH),
4157[C_DC_ESC0_PLUS2_CNT] =
4158 DC_PERF_CNTR_LCB(DcEsc0Plus2, DC_LCB_ERR_INFO_ESCAPE_0_PLUS2_CNT,
4159 CNTR_SYNTH),
4160[C_DC_REINIT_FROM_PEER_CNT] =
4161 DC_PERF_CNTR_LCB(DcReinitPeer, DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT,
4162 CNTR_SYNTH),
4163[C_DC_SBE_CNT] = DC_PERF_CNTR_LCB(DcSbe, DC_LCB_ERR_INFO_SBE_CNT,
4164 CNTR_SYNTH),
4165[C_DC_MISC_FLG_CNT] =
4166 DC_PERF_CNTR_LCB(DcMiscFlg, DC_LCB_ERR_INFO_MISC_FLG_CNT,
4167 CNTR_SYNTH),
4168[C_DC_PRF_GOOD_LTP_CNT] =
4169 DC_PERF_CNTR_LCB(DcGoodLTP, DC_LCB_PRF_GOOD_LTP_CNT, CNTR_SYNTH),
4170[C_DC_PRF_ACCEPTED_LTP_CNT] =
4171 DC_PERF_CNTR_LCB(DcAccLTP, DC_LCB_PRF_ACCEPTED_LTP_CNT,
4172 CNTR_SYNTH),
4173[C_DC_PRF_RX_FLIT_CNT] =
4174 DC_PERF_CNTR_LCB(DcPrfRxFlit, DC_LCB_PRF_RX_FLIT_CNT, CNTR_SYNTH),
4175[C_DC_PRF_TX_FLIT_CNT] =
4176 DC_PERF_CNTR_LCB(DcPrfTxFlit, DC_LCB_PRF_TX_FLIT_CNT, CNTR_SYNTH),
4177[C_DC_PRF_CLK_CNTR] =
4178 DC_PERF_CNTR_LCB(DcPrfClk, DC_LCB_PRF_CLK_CNTR, CNTR_SYNTH),
4179[C_DC_PG_DBG_FLIT_CRDTS_CNT] =
4180 DC_PERF_CNTR_LCB(DcFltCrdts, DC_LCB_PG_DBG_FLIT_CRDTS_CNT, CNTR_SYNTH),
4181[C_DC_PG_STS_PAUSE_COMPLETE_CNT] =
4182 DC_PERF_CNTR_LCB(DcPauseComp, DC_LCB_PG_STS_PAUSE_COMPLETE_CNT,
4183 CNTR_SYNTH),
4184[C_DC_PG_STS_TX_SBE_CNT] =
4185 DC_PERF_CNTR_LCB(DcStsTxSbe, DC_LCB_PG_STS_TX_SBE_CNT, CNTR_SYNTH),
4186[C_DC_PG_STS_TX_MBE_CNT] =
4187 DC_PERF_CNTR_LCB(DcStsTxMbe, DC_LCB_PG_STS_TX_MBE_CNT,
4188 CNTR_SYNTH),
4189[C_SW_CPU_INTR] = CNTR_ELEM("Intr", 0, 0, CNTR_NORMAL,
4190 access_sw_cpu_intr),
4191[C_SW_CPU_RCV_LIM] = CNTR_ELEM("RcvLimit", 0, 0, CNTR_NORMAL,
4192 access_sw_cpu_rcv_limit),
4193[C_SW_VTX_WAIT] = CNTR_ELEM("vTxWait", 0, 0, CNTR_NORMAL,
4194 access_sw_vtx_wait),
4195[C_SW_PIO_WAIT] = CNTR_ELEM("PioWait", 0, 0, CNTR_NORMAL,
4196 access_sw_pio_wait),
14553ca1
MM		 4197[C_SW_PIO_DRAIN] = CNTR_ELEM("PioDrain", 0, 0, CNTR_NORMAL,
4198 access_sw_pio_drain),
77241056
MM		 4199[C_SW_KMEM_WAIT] = CNTR_ELEM("KmemWait", 0, 0, CNTR_NORMAL,
4200 access_sw_kmem_wait),
b421922e
DL		 4201[C_SW_SEND_SCHED] = CNTR_ELEM("SendSched", 0, 0, CNTR_NORMAL,
4202 access_sw_send_schedule),
a699c6c2
VM		 4203[C_SDMA_DESC_FETCHED_CNT] = CNTR_ELEM("SDEDscFdCn",
4204 SEND_DMA_DESC_FETCHED_CNT, 0,
4205 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4206 dev_access_u32_csr),
4207[C_SDMA_INT_CNT] = CNTR_ELEM("SDMAInt", 0, 0,
4208 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4209 access_sde_int_cnt),
4210[C_SDMA_ERR_CNT] = CNTR_ELEM("SDMAErrCt", 0, 0,
4211 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4212 access_sde_err_cnt),
4213[C_SDMA_IDLE_INT_CNT] = CNTR_ELEM("SDMAIdInt", 0, 0,
4214 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4215 access_sde_idle_int_cnt),
4216[C_SDMA_PROGRESS_INT_CNT] = CNTR_ELEM("SDMAPrIntCn", 0, 0,
4217 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4218 access_sde_progress_int_cnt),
2c5b521a
JR		 4219/* MISC_ERR_STATUS */
4220[C_MISC_PLL_LOCK_FAIL_ERR] = CNTR_ELEM("MISC_PLL_LOCK_FAIL_ERR", 0, 0,
4221 CNTR_NORMAL,
4222 access_misc_pll_lock_fail_err_cnt),
4223[C_MISC_MBIST_FAIL_ERR] = CNTR_ELEM("MISC_MBIST_FAIL_ERR", 0, 0,
4224 CNTR_NORMAL,
4225 access_misc_mbist_fail_err_cnt),
4226[C_MISC_INVALID_EEP_CMD_ERR] = CNTR_ELEM("MISC_INVALID_EEP_CMD_ERR", 0, 0,
4227 CNTR_NORMAL,
4228 access_misc_invalid_eep_cmd_err_cnt),
4229[C_MISC_EFUSE_DONE_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_DONE_PARITY_ERR", 0, 0,
4230 CNTR_NORMAL,
4231 access_misc_efuse_done_parity_err_cnt),
4232[C_MISC_EFUSE_WRITE_ERR] = CNTR_ELEM("MISC_EFUSE_WRITE_ERR", 0, 0,
4233 CNTR_NORMAL,
4234 access_misc_efuse_write_err_cnt),
4235[C_MISC_EFUSE_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_EFUSE_READ_BAD_ADDR_ERR", 0,
4236 0, CNTR_NORMAL,
4237 access_misc_efuse_read_bad_addr_err_cnt),
4238[C_MISC_EFUSE_CSR_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_CSR_PARITY_ERR", 0, 0,
4239 CNTR_NORMAL,
4240 access_misc_efuse_csr_parity_err_cnt),
4241[C_MISC_FW_AUTH_FAILED_ERR] = CNTR_ELEM("MISC_FW_AUTH_FAILED_ERR", 0, 0,
4242 CNTR_NORMAL,
4243 access_misc_fw_auth_failed_err_cnt),
4244[C_MISC_KEY_MISMATCH_ERR] = CNTR_ELEM("MISC_KEY_MISMATCH_ERR", 0, 0,
4245 CNTR_NORMAL,
4246 access_misc_key_mismatch_err_cnt),
4247[C_MISC_SBUS_WRITE_FAILED_ERR] = CNTR_ELEM("MISC_SBUS_WRITE_FAILED_ERR", 0, 0,
4248 CNTR_NORMAL,
4249 access_misc_sbus_write_failed_err_cnt),
4250[C_MISC_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_WRITE_BAD_ADDR_ERR", 0, 0,
4251 CNTR_NORMAL,
4252 access_misc_csr_write_bad_addr_err_cnt),
4253[C_MISC_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_READ_BAD_ADDR_ERR", 0, 0,
4254 CNTR_NORMAL,
4255 access_misc_csr_read_bad_addr_err_cnt),
4256[C_MISC_CSR_PARITY_ERR] = CNTR_ELEM("MISC_CSR_PARITY_ERR", 0, 0,
4257 CNTR_NORMAL,
4258 access_misc_csr_parity_err_cnt),
4259/* CceErrStatus */
4260[C_CCE_ERR_STATUS_AGGREGATED_CNT] = CNTR_ELEM("CceErrStatusAggregatedCnt", 0, 0,
4261 CNTR_NORMAL,
4262 access_sw_cce_err_status_aggregated_cnt),
4263[C_CCE_MSIX_CSR_PARITY_ERR] = CNTR_ELEM("CceMsixCsrParityErr", 0, 0,
4264 CNTR_NORMAL,
4265 access_cce_msix_csr_parity_err_cnt),
4266[C_CCE_INT_MAP_UNC_ERR] = CNTR_ELEM("CceIntMapUncErr", 0, 0,
4267 CNTR_NORMAL,
4268 access_cce_int_map_unc_err_cnt),
4269[C_CCE_INT_MAP_COR_ERR] = CNTR_ELEM("CceIntMapCorErr", 0, 0,
4270 CNTR_NORMAL,
4271 access_cce_int_map_cor_err_cnt),
4272[C_CCE_MSIX_TABLE_UNC_ERR] = CNTR_ELEM("CceMsixTableUncErr", 0, 0,
4273 CNTR_NORMAL,
4274 access_cce_msix_table_unc_err_cnt),
4275[C_CCE_MSIX_TABLE_COR_ERR] = CNTR_ELEM("CceMsixTableCorErr", 0, 0,
4276 CNTR_NORMAL,
4277 access_cce_msix_table_cor_err_cnt),
4278[C_CCE_RXDMA_CONV_FIFO_PARITY_ERR] = CNTR_ELEM("CceRxdmaConvFifoParityErr", 0,
4279 0, CNTR_NORMAL,
4280 access_cce_rxdma_conv_fifo_parity_err_cnt),
4281[C_CCE_RCPL_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceRcplAsyncFifoParityErr", 0,
4282 0, CNTR_NORMAL,
4283 access_cce_rcpl_async_fifo_parity_err_cnt),
4284[C_CCE_SEG_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceSegWriteBadAddrErr", 0, 0,
4285 CNTR_NORMAL,
4286 access_cce_seg_write_bad_addr_err_cnt),
4287[C_CCE_SEG_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceSegReadBadAddrErr", 0, 0,
4288 CNTR_NORMAL,
4289 access_cce_seg_read_bad_addr_err_cnt),
4290[C_LA_TRIGGERED] = CNTR_ELEM("Cce LATriggered", 0, 0,
4291 CNTR_NORMAL,
4292 access_la_triggered_cnt),
4293[C_CCE_TRGT_CPL_TIMEOUT_ERR] = CNTR_ELEM("CceTrgtCplTimeoutErr", 0, 0,
4294 CNTR_NORMAL,
4295 access_cce_trgt_cpl_timeout_err_cnt),
4296[C_PCIC_RECEIVE_PARITY_ERR] = CNTR_ELEM("PcicReceiveParityErr", 0, 0,
4297 CNTR_NORMAL,
4298 access_pcic_receive_parity_err_cnt),
4299[C_PCIC_TRANSMIT_BACK_PARITY_ERR] = CNTR_ELEM("PcicTransmitBackParityErr", 0, 0,
4300 CNTR_NORMAL,
4301 access_pcic_transmit_back_parity_err_cnt),
4302[C_PCIC_TRANSMIT_FRONT_PARITY_ERR] = CNTR_ELEM("PcicTransmitFrontParityErr", 0,
4303 0, CNTR_NORMAL,
4304 access_pcic_transmit_front_parity_err_cnt),
4305[C_PCIC_CPL_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicCplDatQUncErr", 0, 0,
4306 CNTR_NORMAL,
4307 access_pcic_cpl_dat_q_unc_err_cnt),
4308[C_PCIC_CPL_HD_Q_UNC_ERR] = CNTR_ELEM("PcicCplHdQUncErr", 0, 0,
4309 CNTR_NORMAL,
4310 access_pcic_cpl_hd_q_unc_err_cnt),
4311[C_PCIC_POST_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicPostDatQUncErr", 0, 0,
4312 CNTR_NORMAL,
4313 access_pcic_post_dat_q_unc_err_cnt),
4314[C_PCIC_POST_HD_Q_UNC_ERR] = CNTR_ELEM("PcicPostHdQUncErr", 0, 0,
4315 CNTR_NORMAL,
4316 access_pcic_post_hd_q_unc_err_cnt),
4317[C_PCIC_RETRY_SOT_MEM_UNC_ERR] = CNTR_ELEM("PcicRetrySotMemUncErr", 0, 0,
4318 CNTR_NORMAL,
4319 access_pcic_retry_sot_mem_unc_err_cnt),
4320[C_PCIC_RETRY_MEM_UNC_ERR] = CNTR_ELEM("PcicRetryMemUncErr", 0, 0,
4321 CNTR_NORMAL,
4322 access_pcic_retry_mem_unc_err),
4323[C_PCIC_N_POST_DAT_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostDatQParityErr", 0, 0,
4324 CNTR_NORMAL,
4325 access_pcic_n_post_dat_q_parity_err_cnt),
4326[C_PCIC_N_POST_H_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostHQParityErr", 0, 0,
4327 CNTR_NORMAL,
4328 access_pcic_n_post_h_q_parity_err_cnt),
4329[C_PCIC_CPL_DAT_Q_COR_ERR] = CNTR_ELEM("PcicCplDatQCorErr", 0, 0,
4330 CNTR_NORMAL,
4331 access_pcic_cpl_dat_q_cor_err_cnt),
4332[C_PCIC_CPL_HD_Q_COR_ERR] = CNTR_ELEM("PcicCplHdQCorErr", 0, 0,
4333 CNTR_NORMAL,
4334 access_pcic_cpl_hd_q_cor_err_cnt),
4335[C_PCIC_POST_DAT_Q_COR_ERR] = CNTR_ELEM("PcicPostDatQCorErr", 0, 0,
4336 CNTR_NORMAL,
4337 access_pcic_post_dat_q_cor_err_cnt),
4338[C_PCIC_POST_HD_Q_COR_ERR] = CNTR_ELEM("PcicPostHdQCorErr", 0, 0,
4339 CNTR_NORMAL,
4340 access_pcic_post_hd_q_cor_err_cnt),
4341[C_PCIC_RETRY_SOT_MEM_COR_ERR] = CNTR_ELEM("PcicRetrySotMemCorErr", 0, 0,
4342 CNTR_NORMAL,
4343 access_pcic_retry_sot_mem_cor_err_cnt),
4344[C_PCIC_RETRY_MEM_COR_ERR] = CNTR_ELEM("PcicRetryMemCorErr", 0, 0,
4345 CNTR_NORMAL,
4346 access_pcic_retry_mem_cor_err_cnt),
4347[C_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERR] = CNTR_ELEM(
4348 "CceCli1AsyncFifoDbgParityError", 0, 0,
4349 CNTR_NORMAL,
4350 access_cce_cli1_async_fifo_dbg_parity_err_cnt),
4351[C_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERR] = CNTR_ELEM(
4352 "CceCli1AsyncFifoRxdmaParityError", 0, 0,
4353 CNTR_NORMAL,
4354 access_cce_cli1_async_fifo_rxdma_parity_err_cnt
4355 ),
4356[C_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR] = CNTR_ELEM(
4357 "CceCli1AsyncFifoSdmaHdParityErr", 0, 0,
4358 CNTR_NORMAL,
4359 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt),
4360[C_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR] = CNTR_ELEM(
4361 "CceCli1AsyncFifoPioCrdtParityErr", 0, 0,
4362 CNTR_NORMAL,
4363 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt),
4364[C_CCE_CLI2_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceCli2AsyncFifoParityErr", 0,
4365 0, CNTR_NORMAL,
4366 access_cce_cli2_async_fifo_parity_err_cnt),
4367[C_CCE_CSR_CFG_BUS_PARITY_ERR] = CNTR_ELEM("CceCsrCfgBusParityErr", 0, 0,
4368 CNTR_NORMAL,
4369 access_cce_csr_cfg_bus_parity_err_cnt),
4370[C_CCE_CLI0_ASYNC_FIFO_PARTIY_ERR] = CNTR_ELEM("CceCli0AsyncFifoParityErr", 0,
4371 0, CNTR_NORMAL,
4372 access_cce_cli0_async_fifo_parity_err_cnt),
4373[C_CCE_RSPD_DATA_PARITY_ERR] = CNTR_ELEM("CceRspdDataParityErr", 0, 0,
4374 CNTR_NORMAL,
4375 access_cce_rspd_data_parity_err_cnt),
4376[C_CCE_TRGT_ACCESS_ERR] = CNTR_ELEM("CceTrgtAccessErr", 0, 0,
4377 CNTR_NORMAL,
4378 access_cce_trgt_access_err_cnt),
4379[C_CCE_TRGT_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceTrgtAsyncFifoParityErr", 0,
4380 0, CNTR_NORMAL,
4381 access_cce_trgt_async_fifo_parity_err_cnt),
4382[C_CCE_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrWriteBadAddrErr", 0, 0,
4383 CNTR_NORMAL,
4384 access_cce_csr_write_bad_addr_err_cnt),
4385[C_CCE_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrReadBadAddrErr", 0, 0,
4386 CNTR_NORMAL,
4387 access_cce_csr_read_bad_addr_err_cnt),
4388[C_CCE_CSR_PARITY_ERR] = CNTR_ELEM("CceCsrParityErr", 0, 0,
4389 CNTR_NORMAL,
4390 access_ccs_csr_parity_err_cnt),
4391
4392/* RcvErrStatus */
4393[C_RX_CSR_PARITY_ERR] = CNTR_ELEM("RxCsrParityErr", 0, 0,
4394 CNTR_NORMAL,
4395 access_rx_csr_parity_err_cnt),
4396[C_RX_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrWriteBadAddrErr", 0, 0,
4397 CNTR_NORMAL,
4398 access_rx_csr_write_bad_addr_err_cnt),
4399[C_RX_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrReadBadAddrErr", 0, 0,
4400 CNTR_NORMAL,
4401 access_rx_csr_read_bad_addr_err_cnt),
4402[C_RX_DMA_CSR_UNC_ERR] = CNTR_ELEM("RxDmaCsrUncErr", 0, 0,
4403 CNTR_NORMAL,
4404 access_rx_dma_csr_unc_err_cnt),
4405[C_RX_DMA_DQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaDqFsmEncodingErr", 0, 0,
4406 CNTR_NORMAL,
4407 access_rx_dma_dq_fsm_encoding_err_cnt),
4408[C_RX_DMA_EQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaEqFsmEncodingErr", 0, 0,
4409 CNTR_NORMAL,
4410 access_rx_dma_eq_fsm_encoding_err_cnt),
4411[C_RX_DMA_CSR_PARITY_ERR] = CNTR_ELEM("RxDmaCsrParityErr", 0, 0,
4412 CNTR_NORMAL,
4413 access_rx_dma_csr_parity_err_cnt),
4414[C_RX_RBUF_DATA_COR_ERR] = CNTR_ELEM("RxRbufDataCorErr", 0, 0,
4415 CNTR_NORMAL,
4416 access_rx_rbuf_data_cor_err_cnt),
4417[C_RX_RBUF_DATA_UNC_ERR] = CNTR_ELEM("RxRbufDataUncErr", 0, 0,
4418 CNTR_NORMAL,
4419 access_rx_rbuf_data_unc_err_cnt),
4420[C_RX_DMA_DATA_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaDataFifoRdCorErr", 0, 0,
4421 CNTR_NORMAL,
4422 access_rx_dma_data_fifo_rd_cor_err_cnt),
4423[C_RX_DMA_DATA_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaDataFifoRdUncErr", 0, 0,
4424 CNTR_NORMAL,
4425 access_rx_dma_data_fifo_rd_unc_err_cnt),
4426[C_RX_DMA_HDR_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaHdrFifoRdCorErr", 0, 0,
4427 CNTR_NORMAL,
4428 access_rx_dma_hdr_fifo_rd_cor_err_cnt),
4429[C_RX_DMA_HDR_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaHdrFifoRdUncErr", 0, 0,
4430 CNTR_NORMAL,
4431 access_rx_dma_hdr_fifo_rd_unc_err_cnt),
4432[C_RX_RBUF_DESC_PART2_COR_ERR] = CNTR_ELEM("RxRbufDescPart2CorErr", 0, 0,
4433 CNTR_NORMAL,
4434 access_rx_rbuf_desc_part2_cor_err_cnt),
4435[C_RX_RBUF_DESC_PART2_UNC_ERR] = CNTR_ELEM("RxRbufDescPart2UncErr", 0, 0,
4436 CNTR_NORMAL,
4437 access_rx_rbuf_desc_part2_unc_err_cnt),
4438[C_RX_RBUF_DESC_PART1_COR_ERR] = CNTR_ELEM("RxRbufDescPart1CorErr", 0, 0,
4439 CNTR_NORMAL,
4440 access_rx_rbuf_desc_part1_cor_err_cnt),
4441[C_RX_RBUF_DESC_PART1_UNC_ERR] = CNTR_ELEM("RxRbufDescPart1UncErr", 0, 0,
4442 CNTR_NORMAL,
4443 access_rx_rbuf_desc_part1_unc_err_cnt),
4444[C_RX_HQ_INTR_FSM_ERR] = CNTR_ELEM("RxHqIntrFsmErr", 0, 0,
4445 CNTR_NORMAL,
4446 access_rx_hq_intr_fsm_err_cnt),
4447[C_RX_HQ_INTR_CSR_PARITY_ERR] = CNTR_ELEM("RxHqIntrCsrParityErr", 0, 0,
4448 CNTR_NORMAL,
4449 access_rx_hq_intr_csr_parity_err_cnt),
4450[C_RX_LOOKUP_CSR_PARITY_ERR] = CNTR_ELEM("RxLookupCsrParityErr", 0, 0,
4451 CNTR_NORMAL,
4452 access_rx_lookup_csr_parity_err_cnt),
4453[C_RX_LOOKUP_RCV_ARRAY_COR_ERR] = CNTR_ELEM("RxLookupRcvArrayCorErr", 0, 0,
4454 CNTR_NORMAL,
4455 access_rx_lookup_rcv_array_cor_err_cnt),
4456[C_RX_LOOKUP_RCV_ARRAY_UNC_ERR] = CNTR_ELEM("RxLookupRcvArrayUncErr", 0, 0,
4457 CNTR_NORMAL,
4458 access_rx_lookup_rcv_array_unc_err_cnt),
4459[C_RX_LOOKUP_DES_PART2_PARITY_ERR] = CNTR_ELEM("RxLookupDesPart2ParityErr", 0,
4460 0, CNTR_NORMAL,
4461 access_rx_lookup_des_part2_parity_err_cnt),
4462[C_RX_LOOKUP_DES_PART1_UNC_COR_ERR] = CNTR_ELEM("RxLookupDesPart1UncCorErr", 0,
4463 0, CNTR_NORMAL,
4464 access_rx_lookup_des_part1_unc_cor_err_cnt),
4465[C_RX_LOOKUP_DES_PART1_UNC_ERR] = CNTR_ELEM("RxLookupDesPart1UncErr", 0, 0,
4466 CNTR_NORMAL,
4467 access_rx_lookup_des_part1_unc_err_cnt),
4468[C_RX_RBUF_NEXT_FREE_BUF_COR_ERR] = CNTR_ELEM("RxRbufNextFreeBufCorErr", 0, 0,
4469 CNTR_NORMAL,
4470 access_rx_rbuf_next_free_buf_cor_err_cnt),
4471[C_RX_RBUF_NEXT_FREE_BUF_UNC_ERR] = CNTR_ELEM("RxRbufNextFreeBufUncErr", 0, 0,
4472 CNTR_NORMAL,
4473 access_rx_rbuf_next_free_buf_unc_err_cnt),
4474[C_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR] = CNTR_ELEM(
4475 "RxRbufFlInitWrAddrParityErr", 0, 0,
4476 CNTR_NORMAL,
4477 access_rbuf_fl_init_wr_addr_parity_err_cnt),
4478[C_RX_RBUF_FL_INITDONE_PARITY_ERR] = CNTR_ELEM("RxRbufFlInitdoneParityErr", 0,
4479 0, CNTR_NORMAL,
4480 access_rx_rbuf_fl_initdone_parity_err_cnt),
4481[C_RX_RBUF_FL_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlWrAddrParityErr", 0,
4482 0, CNTR_NORMAL,
4483 access_rx_rbuf_fl_write_addr_parity_err_cnt),
4484[C_RX_RBUF_FL_RD_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlRdAddrParityErr", 0, 0,
4485 CNTR_NORMAL,
4486 access_rx_rbuf_fl_rd_addr_parity_err_cnt),
4487[C_RX_RBUF_EMPTY_ERR] = CNTR_ELEM("RxRbufEmptyErr", 0, 0,
4488 CNTR_NORMAL,
4489 access_rx_rbuf_empty_err_cnt),
4490[C_RX_RBUF_FULL_ERR] = CNTR_ELEM("RxRbufFullErr", 0, 0,
4491 CNTR_NORMAL,
4492 access_rx_rbuf_full_err_cnt),
4493[C_RX_RBUF_BAD_LOOKUP_ERR] = CNTR_ELEM("RxRBufBadLookupErr", 0, 0,
4494 CNTR_NORMAL,
4495 access_rbuf_bad_lookup_err_cnt),
4496[C_RX_RBUF_CTX_ID_PARITY_ERR] = CNTR_ELEM("RxRbufCtxIdParityErr", 0, 0,
4497 CNTR_NORMAL,
4498 access_rbuf_ctx_id_parity_err_cnt),
4499[C_RX_RBUF_CSR_QEOPDW_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEOPDWParityErr", 0, 0,
4500 CNTR_NORMAL,
4501 access_rbuf_csr_qeopdw_parity_err_cnt),
4502[C_RX_RBUF_CSR_Q_NUM_OF_PKT_PARITY_ERR] = CNTR_ELEM(
4503 "RxRbufCsrQNumOfPktParityErr", 0, 0,
4504 CNTR_NORMAL,
4505 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt),
4506[C_RX_RBUF_CSR_Q_T1_PTR_PARITY_ERR] = CNTR_ELEM(
4507 "RxRbufCsrQTlPtrParityErr", 0, 0,
4508 CNTR_NORMAL,
4509 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt),
4510[C_RX_RBUF_CSR_Q_HD_PTR_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQHdPtrParityErr", 0,
4511 0, CNTR_NORMAL,
4512 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt),
4513[C_RX_RBUF_CSR_Q_VLD_BIT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQVldBitParityErr", 0,
4514 0, CNTR_NORMAL,
4515 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt),
4516[C_RX_RBUF_CSR_Q_NEXT_BUF_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQNextBufParityErr",
4517 0, 0, CNTR_NORMAL,
4518 access_rx_rbuf_csr_q_next_buf_parity_err_cnt),
4519[C_RX_RBUF_CSR_Q_ENT_CNT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEntCntParityErr", 0,
4520 0, CNTR_NORMAL,
4521 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt),
4522[C_RX_RBUF_CSR_Q_HEAD_BUF_NUM_PARITY_ERR] = CNTR_ELEM(
4523 "RxRbufCsrQHeadBufNumParityErr", 0, 0,
4524 CNTR_NORMAL,
4525 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt),
4526[C_RX_RBUF_BLOCK_LIST_READ_COR_ERR] = CNTR_ELEM("RxRbufBlockListReadCorErr", 0,
4527 0, CNTR_NORMAL,
4528 access_rx_rbuf_block_list_read_cor_err_cnt),
4529[C_RX_RBUF_BLOCK_LIST_READ_UNC_ERR] = CNTR_ELEM("RxRbufBlockListReadUncErr", 0,
4530 0, CNTR_NORMAL,
4531 access_rx_rbuf_block_list_read_unc_err_cnt),
4532[C_RX_RBUF_LOOKUP_DES_COR_ERR] = CNTR_ELEM("RxRbufLookupDesCorErr", 0, 0,
4533 CNTR_NORMAL,
4534 access_rx_rbuf_lookup_des_cor_err_cnt),
4535[C_RX_RBUF_LOOKUP_DES_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesUncErr", 0, 0,
4536 CNTR_NORMAL,
4537 access_rx_rbuf_lookup_des_unc_err_cnt),
4538[C_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR] = CNTR_ELEM(
4539 "RxRbufLookupDesRegUncCorErr", 0, 0,
4540 CNTR_NORMAL,
4541 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt),
4542[C_RX_RBUF_LOOKUP_DES_REG_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesRegUncErr", 0, 0,
4543 CNTR_NORMAL,
4544 access_rx_rbuf_lookup_des_reg_unc_err_cnt),
4545[C_RX_RBUF_FREE_LIST_COR_ERR] = CNTR_ELEM("RxRbufFreeListCorErr", 0, 0,
4546 CNTR_NORMAL,
4547 access_rx_rbuf_free_list_cor_err_cnt),
4548[C_RX_RBUF_FREE_LIST_UNC_ERR] = CNTR_ELEM("RxRbufFreeListUncErr", 0, 0,
4549 CNTR_NORMAL,
4550 access_rx_rbuf_free_list_unc_err_cnt),
4551[C_RX_RCV_FSM_ENCODING_ERR] = CNTR_ELEM("RxRcvFsmEncodingErr", 0, 0,
4552 CNTR_NORMAL,
4553 access_rx_rcv_fsm_encoding_err_cnt),
4554[C_RX_DMA_FLAG_COR_ERR] = CNTR_ELEM("RxDmaFlagCorErr", 0, 0,
4555 CNTR_NORMAL,
4556 access_rx_dma_flag_cor_err_cnt),
4557[C_RX_DMA_FLAG_UNC_ERR] = CNTR_ELEM("RxDmaFlagUncErr", 0, 0,
4558 CNTR_NORMAL,
4559 access_rx_dma_flag_unc_err_cnt),
4560[C_RX_DC_SOP_EOP_PARITY_ERR] = CNTR_ELEM("RxDcSopEopParityErr", 0, 0,
4561 CNTR_NORMAL,
4562 access_rx_dc_sop_eop_parity_err_cnt),
4563[C_RX_RCV_CSR_PARITY_ERR] = CNTR_ELEM("RxRcvCsrParityErr", 0, 0,
4564 CNTR_NORMAL,
4565 access_rx_rcv_csr_parity_err_cnt),
4566[C_RX_RCV_QP_MAP_TABLE_COR_ERR] = CNTR_ELEM("RxRcvQpMapTableCorErr", 0, 0,
4567 CNTR_NORMAL,
4568 access_rx_rcv_qp_map_table_cor_err_cnt),
4569[C_RX_RCV_QP_MAP_TABLE_UNC_ERR] = CNTR_ELEM("RxRcvQpMapTableUncErr", 0, 0,
4570 CNTR_NORMAL,
4571 access_rx_rcv_qp_map_table_unc_err_cnt),
4572[C_RX_RCV_DATA_COR_ERR] = CNTR_ELEM("RxRcvDataCorErr", 0, 0,
4573 CNTR_NORMAL,
4574 access_rx_rcv_data_cor_err_cnt),
4575[C_RX_RCV_DATA_UNC_ERR] = CNTR_ELEM("RxRcvDataUncErr", 0, 0,
4576 CNTR_NORMAL,
4577 access_rx_rcv_data_unc_err_cnt),
4578[C_RX_RCV_HDR_COR_ERR] = CNTR_ELEM("RxRcvHdrCorErr", 0, 0,
4579 CNTR_NORMAL,
4580 access_rx_rcv_hdr_cor_err_cnt),
4581[C_RX_RCV_HDR_UNC_ERR] = CNTR_ELEM("RxRcvHdrUncErr", 0, 0,
4582 CNTR_NORMAL,
4583 access_rx_rcv_hdr_unc_err_cnt),
4584[C_RX_DC_INTF_PARITY_ERR] = CNTR_ELEM("RxDcIntfParityErr", 0, 0,
4585 CNTR_NORMAL,
4586 access_rx_dc_intf_parity_err_cnt),
4587[C_RX_DMA_CSR_COR_ERR] = CNTR_ELEM("RxDmaCsrCorErr", 0, 0,
4588 CNTR_NORMAL,
4589 access_rx_dma_csr_cor_err_cnt),
4590/* SendPioErrStatus */
4591[C_PIO_PEC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPecSopHeadParityErr", 0, 0,
4592 CNTR_NORMAL,
4593 access_pio_pec_sop_head_parity_err_cnt),
4594[C_PIO_PCC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPccSopHeadParityErr", 0, 0,
4595 CNTR_NORMAL,
4596 access_pio_pcc_sop_head_parity_err_cnt),
4597[C_PIO_LAST_RETURNED_CNT_PARITY_ERR] = CNTR_ELEM("PioLastReturnedCntParityErr",
4598 0, 0, CNTR_NORMAL,
4599 access_pio_last_returned_cnt_parity_err_cnt),
4600[C_PIO_CURRENT_FREE_CNT_PARITY_ERR] = CNTR_ELEM("PioCurrentFreeCntParityErr", 0,
4601 0, CNTR_NORMAL,
4602 access_pio_current_free_cnt_parity_err_cnt),
4603[C_PIO_RSVD_31_ERR] = CNTR_ELEM("Pio Reserved 31", 0, 0,
4604 CNTR_NORMAL,
4605 access_pio_reserved_31_err_cnt),
4606[C_PIO_RSVD_30_ERR] = CNTR_ELEM("Pio Reserved 30", 0, 0,
4607 CNTR_NORMAL,
4608 access_pio_reserved_30_err_cnt),
4609[C_PIO_PPMC_SOP_LEN_ERR] = CNTR_ELEM("PioPpmcSopLenErr", 0, 0,
4610 CNTR_NORMAL,
4611 access_pio_ppmc_sop_len_err_cnt),
4612[C_PIO_PPMC_BQC_MEM_PARITY_ERR] = CNTR_ELEM("PioPpmcBqcMemParityErr", 0, 0,
4613 CNTR_NORMAL,
4614 access_pio_ppmc_bqc_mem_parity_err_cnt),
4615[C_PIO_VL_FIFO_PARITY_ERR] = CNTR_ELEM("PioVlFifoParityErr", 0, 0,
4616 CNTR_NORMAL,
4617 access_pio_vl_fifo_parity_err_cnt),
4618[C_PIO_VLF_SOP_PARITY_ERR] = CNTR_ELEM("PioVlfSopParityErr", 0, 0,
4619 CNTR_NORMAL,
4620 access_pio_vlf_sop_parity_err_cnt),
4621[C_PIO_VLF_V1_LEN_PARITY_ERR] = CNTR_ELEM("PioVlfVlLenParityErr", 0, 0,
4622 CNTR_NORMAL,
4623 access_pio_vlf_v1_len_parity_err_cnt),
4624[C_PIO_BLOCK_QW_COUNT_PARITY_ERR] = CNTR_ELEM("PioBlockQwCountParityErr", 0, 0,
4625 CNTR_NORMAL,
4626 access_pio_block_qw_count_parity_err_cnt),
4627[C_PIO_WRITE_QW_VALID_PARITY_ERR] = CNTR_ELEM("PioWriteQwValidParityErr", 0, 0,
4628 CNTR_NORMAL,
4629 access_pio_write_qw_valid_parity_err_cnt),
4630[C_PIO_STATE_MACHINE_ERR] = CNTR_ELEM("PioStateMachineErr", 0, 0,
4631 CNTR_NORMAL,
4632 access_pio_state_machine_err_cnt),
4633[C_PIO_WRITE_DATA_PARITY_ERR] = CNTR_ELEM("PioWriteDataParityErr", 0, 0,
4634 CNTR_NORMAL,
4635 access_pio_write_data_parity_err_cnt),
4636[C_PIO_HOST_ADDR_MEM_COR_ERR] = CNTR_ELEM("PioHostAddrMemCorErr", 0, 0,
4637 CNTR_NORMAL,
4638 access_pio_host_addr_mem_cor_err_cnt),
4639[C_PIO_HOST_ADDR_MEM_UNC_ERR] = CNTR_ELEM("PioHostAddrMemUncErr", 0, 0,
4640 CNTR_NORMAL,
4641 access_pio_host_addr_mem_unc_err_cnt),
4642[C_PIO_PKT_EVICT_SM_OR_ARM_SM_ERR] = CNTR_ELEM("PioPktEvictSmOrArbSmErr", 0, 0,
4643 CNTR_NORMAL,
4644 access_pio_pkt_evict_sm_or_arb_sm_err_cnt),
4645[C_PIO_INIT_SM_IN_ERR] = CNTR_ELEM("PioInitSmInErr", 0, 0,
4646 CNTR_NORMAL,
4647 access_pio_init_sm_in_err_cnt),
4648[C_PIO_PPMC_PBL_FIFO_ERR] = CNTR_ELEM("PioPpmcPblFifoErr", 0, 0,
4649 CNTR_NORMAL,
4650 access_pio_ppmc_pbl_fifo_err_cnt),
4651[C_PIO_CREDIT_RET_FIFO_PARITY_ERR] = CNTR_ELEM("PioCreditRetFifoParityErr", 0,
4652 0, CNTR_NORMAL,
4653 access_pio_credit_ret_fifo_parity_err_cnt),
4654[C_PIO_V1_LEN_MEM_BANK1_COR_ERR] = CNTR_ELEM("PioVlLenMemBank1CorErr", 0, 0,
4655 CNTR_NORMAL,
4656 access_pio_v1_len_mem_bank1_cor_err_cnt),
4657[C_PIO_V1_LEN_MEM_BANK0_COR_ERR] = CNTR_ELEM("PioVlLenMemBank0CorErr", 0, 0,
4658 CNTR_NORMAL,
4659 access_pio_v1_len_mem_bank0_cor_err_cnt),
4660[C_PIO_V1_LEN_MEM_BANK1_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank1UncErr", 0, 0,
4661 CNTR_NORMAL,
4662 access_pio_v1_len_mem_bank1_unc_err_cnt),
4663[C_PIO_V1_LEN_MEM_BANK0_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank0UncErr", 0, 0,
4664 CNTR_NORMAL,
4665 access_pio_v1_len_mem_bank0_unc_err_cnt),
4666[C_PIO_SM_PKT_RESET_PARITY_ERR] = CNTR_ELEM("PioSmPktResetParityErr", 0, 0,
4667 CNTR_NORMAL,
4668 access_pio_sm_pkt_reset_parity_err_cnt),
4669[C_PIO_PKT_EVICT_FIFO_PARITY_ERR] = CNTR_ELEM("PioPktEvictFifoParityErr", 0, 0,
4670 CNTR_NORMAL,
4671 access_pio_pkt_evict_fifo_parity_err_cnt),
4672[C_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR] = CNTR_ELEM(
4673 "PioSbrdctrlCrrelFifoParityErr", 0, 0,
4674 CNTR_NORMAL,
4675 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt),
4676[C_PIO_SBRDCTL_CRREL_PARITY_ERR] = CNTR_ELEM("PioSbrdctlCrrelParityErr", 0, 0,
4677 CNTR_NORMAL,
4678 access_pio_sbrdctl_crrel_parity_err_cnt),
4679[C_PIO_PEC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPecFifoParityErr", 0, 0,
4680 CNTR_NORMAL,
4681 access_pio_pec_fifo_parity_err_cnt),
4682[C_PIO_PCC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPccFifoParityErr", 0, 0,
4683 CNTR_NORMAL,
4684 access_pio_pcc_fifo_parity_err_cnt),
4685[C_PIO_SB_MEM_FIFO1_ERR] = CNTR_ELEM("PioSbMemFifo1Err", 0, 0,
4686 CNTR_NORMAL,
4687 access_pio_sb_mem_fifo1_err_cnt),
4688[C_PIO_SB_MEM_FIFO0_ERR] = CNTR_ELEM("PioSbMemFifo0Err", 0, 0,
4689 CNTR_NORMAL,
4690 access_pio_sb_mem_fifo0_err_cnt),
4691[C_PIO_CSR_PARITY_ERR] = CNTR_ELEM("PioCsrParityErr", 0, 0,
4692 CNTR_NORMAL,
4693 access_pio_csr_parity_err_cnt),
4694[C_PIO_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("PioWriteAddrParityErr", 0, 0,
4695 CNTR_NORMAL,
4696 access_pio_write_addr_parity_err_cnt),
4697[C_PIO_WRITE_BAD_CTXT_ERR] = CNTR_ELEM("PioWriteBadCtxtErr", 0, 0,
4698 CNTR_NORMAL,
4699 access_pio_write_bad_ctxt_err_cnt),
4700/* SendDmaErrStatus */
4701[C_SDMA_PCIE_REQ_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPcieReqTrackingCorErr", 0,
4702 0, CNTR_NORMAL,
4703 access_sdma_pcie_req_tracking_cor_err_cnt),
4704[C_SDMA_PCIE_REQ_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPcieReqTrackingUncErr", 0,
4705 0, CNTR_NORMAL,
4706 access_sdma_pcie_req_tracking_unc_err_cnt),
4707[C_SDMA_CSR_PARITY_ERR] = CNTR_ELEM("SDmaCsrParityErr", 0, 0,
4708 CNTR_NORMAL,
4709 access_sdma_csr_parity_err_cnt),
4710[C_SDMA_RPY_TAG_ERR] = CNTR_ELEM("SDmaRpyTagErr", 0, 0,
4711 CNTR_NORMAL,
4712 access_sdma_rpy_tag_err_cnt),
4713/* SendEgressErrStatus */
4714[C_TX_READ_PIO_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryCsrUncErr", 0, 0,
4715 CNTR_NORMAL,
4716 access_tx_read_pio_memory_csr_unc_err_cnt),
4717[C_TX_READ_SDMA_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryCsrUncErr", 0,
4718 0, CNTR_NORMAL,
4719 access_tx_read_sdma_memory_csr_err_cnt),
4720[C_TX_EGRESS_FIFO_COR_ERR] = CNTR_ELEM("TxEgressFifoCorErr", 0, 0,
4721 CNTR_NORMAL,
4722 access_tx_egress_fifo_cor_err_cnt),
4723[C_TX_READ_PIO_MEMORY_COR_ERR] = CNTR_ELEM("TxReadPioMemoryCorErr", 0, 0,
4724 CNTR_NORMAL,
4725 access_tx_read_pio_memory_cor_err_cnt),
4726[C_TX_READ_SDMA_MEMORY_COR_ERR] = CNTR_ELEM("TxReadSdmaMemoryCorErr", 0, 0,
4727 CNTR_NORMAL,
4728 access_tx_read_sdma_memory_cor_err_cnt),
4729[C_TX_SB_HDR_COR_ERR] = CNTR_ELEM("TxSbHdrCorErr", 0, 0,
4730 CNTR_NORMAL,
4731 access_tx_sb_hdr_cor_err_cnt),
4732[C_TX_CREDIT_OVERRUN_ERR] = CNTR_ELEM("TxCreditOverrunErr", 0, 0,
4733 CNTR_NORMAL,
4734 access_tx_credit_overrun_err_cnt),
4735[C_TX_LAUNCH_FIFO8_COR_ERR] = CNTR_ELEM("TxLaunchFifo8CorErr", 0, 0,
4736 CNTR_NORMAL,
4737 access_tx_launch_fifo8_cor_err_cnt),
4738[C_TX_LAUNCH_FIFO7_COR_ERR] = CNTR_ELEM("TxLaunchFifo7CorErr", 0, 0,
4739 CNTR_NORMAL,
4740 access_tx_launch_fifo7_cor_err_cnt),
4741[C_TX_LAUNCH_FIFO6_COR_ERR] = CNTR_ELEM("TxLaunchFifo6CorErr", 0, 0,
4742 CNTR_NORMAL,
4743 access_tx_launch_fifo6_cor_err_cnt),
4744[C_TX_LAUNCH_FIFO5_COR_ERR] = CNTR_ELEM("TxLaunchFifo5CorErr", 0, 0,
4745 CNTR_NORMAL,
4746 access_tx_launch_fifo5_cor_err_cnt),
4747[C_TX_LAUNCH_FIFO4_COR_ERR] = CNTR_ELEM("TxLaunchFifo4CorErr", 0, 0,
4748 CNTR_NORMAL,
4749 access_tx_launch_fifo4_cor_err_cnt),
4750[C_TX_LAUNCH_FIFO3_COR_ERR] = CNTR_ELEM("TxLaunchFifo3CorErr", 0, 0,
4751 CNTR_NORMAL,
4752 access_tx_launch_fifo3_cor_err_cnt),
4753[C_TX_LAUNCH_FIFO2_COR_ERR] = CNTR_ELEM("TxLaunchFifo2CorErr", 0, 0,
4754 CNTR_NORMAL,
4755 access_tx_launch_fifo2_cor_err_cnt),
4756[C_TX_LAUNCH_FIFO1_COR_ERR] = CNTR_ELEM("TxLaunchFifo1CorErr", 0, 0,
4757 CNTR_NORMAL,
4758 access_tx_launch_fifo1_cor_err_cnt),
4759[C_TX_LAUNCH_FIFO0_COR_ERR] = CNTR_ELEM("TxLaunchFifo0CorErr", 0, 0,
4760 CNTR_NORMAL,
4761 access_tx_launch_fifo0_cor_err_cnt),
4762[C_TX_CREDIT_RETURN_VL_ERR] = CNTR_ELEM("TxCreditReturnVLErr", 0, 0,
4763 CNTR_NORMAL,
4764 access_tx_credit_return_vl_err_cnt),
4765[C_TX_HCRC_INSERTION_ERR] = CNTR_ELEM("TxHcrcInsertionErr", 0, 0,
4766 CNTR_NORMAL,
4767 access_tx_hcrc_insertion_err_cnt),
4768[C_TX_EGRESS_FIFI_UNC_ERR] = CNTR_ELEM("TxEgressFifoUncErr", 0, 0,
4769 CNTR_NORMAL,
4770 access_tx_egress_fifo_unc_err_cnt),
4771[C_TX_READ_PIO_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryUncErr", 0, 0,
4772 CNTR_NORMAL,
4773 access_tx_read_pio_memory_unc_err_cnt),
4774[C_TX_READ_SDMA_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryUncErr", 0, 0,
4775 CNTR_NORMAL,
4776 access_tx_read_sdma_memory_unc_err_cnt),
4777[C_TX_SB_HDR_UNC_ERR] = CNTR_ELEM("TxSbHdrUncErr", 0, 0,
4778 CNTR_NORMAL,
4779 access_tx_sb_hdr_unc_err_cnt),
4780[C_TX_CREDIT_RETURN_PARITY_ERR] = CNTR_ELEM("TxCreditReturnParityErr", 0, 0,
4781 CNTR_NORMAL,
4782 access_tx_credit_return_partiy_err_cnt),
4783[C_TX_LAUNCH_FIFO8_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo8UncOrParityErr",
4784 0, 0, CNTR_NORMAL,
4785 access_tx_launch_fifo8_unc_or_parity_err_cnt),
4786[C_TX_LAUNCH_FIFO7_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo7UncOrParityErr",
4787 0, 0, CNTR_NORMAL,
4788 access_tx_launch_fifo7_unc_or_parity_err_cnt),
4789[C_TX_LAUNCH_FIFO6_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo6UncOrParityErr",
4790 0, 0, CNTR_NORMAL,
4791 access_tx_launch_fifo6_unc_or_parity_err_cnt),
4792[C_TX_LAUNCH_FIFO5_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo5UncOrParityErr",
4793 0, 0, CNTR_NORMAL,
4794 access_tx_launch_fifo5_unc_or_parity_err_cnt),
4795[C_TX_LAUNCH_FIFO4_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo4UncOrParityErr",
4796 0, 0, CNTR_NORMAL,
4797 access_tx_launch_fifo4_unc_or_parity_err_cnt),
4798[C_TX_LAUNCH_FIFO3_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo3UncOrParityErr",
4799 0, 0, CNTR_NORMAL,
4800 access_tx_launch_fifo3_unc_or_parity_err_cnt),
4801[C_TX_LAUNCH_FIFO2_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo2UncOrParityErr",
4802 0, 0, CNTR_NORMAL,
4803 access_tx_launch_fifo2_unc_or_parity_err_cnt),
4804[C_TX_LAUNCH_FIFO1_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo1UncOrParityErr",
4805 0, 0, CNTR_NORMAL,
4806 access_tx_launch_fifo1_unc_or_parity_err_cnt),
4807[C_TX_LAUNCH_FIFO0_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo0UncOrParityErr",
4808 0, 0, CNTR_NORMAL,
4809 access_tx_launch_fifo0_unc_or_parity_err_cnt),
4810[C_TX_SDMA15_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma15DisallowedPacketErr",
4811 0, 0, CNTR_NORMAL,
4812 access_tx_sdma15_disallowed_packet_err_cnt),
4813[C_TX_SDMA14_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma14DisallowedPacketErr",
4814 0, 0, CNTR_NORMAL,
4815 access_tx_sdma14_disallowed_packet_err_cnt),
4816[C_TX_SDMA13_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma13DisallowedPacketErr",
4817 0, 0, CNTR_NORMAL,
4818 access_tx_sdma13_disallowed_packet_err_cnt),
4819[C_TX_SDMA12_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma12DisallowedPacketErr",
4820 0, 0, CNTR_NORMAL,
4821 access_tx_sdma12_disallowed_packet_err_cnt),
4822[C_TX_SDMA11_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma11DisallowedPacketErr",
4823 0, 0, CNTR_NORMAL,
4824 access_tx_sdma11_disallowed_packet_err_cnt),
4825[C_TX_SDMA10_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma10DisallowedPacketErr",
4826 0, 0, CNTR_NORMAL,
4827 access_tx_sdma10_disallowed_packet_err_cnt),
4828[C_TX_SDMA9_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma9DisallowedPacketErr",
4829 0, 0, CNTR_NORMAL,
4830 access_tx_sdma9_disallowed_packet_err_cnt),
4831[C_TX_SDMA8_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma8DisallowedPacketErr",
4832 0, 0, CNTR_NORMAL,
4833 access_tx_sdma8_disallowed_packet_err_cnt),
4834[C_TX_SDMA7_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma7DisallowedPacketErr",
4835 0, 0, CNTR_NORMAL,
4836 access_tx_sdma7_disallowed_packet_err_cnt),
4837[C_TX_SDMA6_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma6DisallowedPacketErr",
4838 0, 0, CNTR_NORMAL,
4839 access_tx_sdma6_disallowed_packet_err_cnt),
4840[C_TX_SDMA5_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma5DisallowedPacketErr",
4841 0, 0, CNTR_NORMAL,
4842 access_tx_sdma5_disallowed_packet_err_cnt),
4843[C_TX_SDMA4_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma4DisallowedPacketErr",
4844 0, 0, CNTR_NORMAL,
4845 access_tx_sdma4_disallowed_packet_err_cnt),
4846[C_TX_SDMA3_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma3DisallowedPacketErr",
4847 0, 0, CNTR_NORMAL,
4848 access_tx_sdma3_disallowed_packet_err_cnt),
4849[C_TX_SDMA2_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma2DisallowedPacketErr",
4850 0, 0, CNTR_NORMAL,
4851 access_tx_sdma2_disallowed_packet_err_cnt),
4852[C_TX_SDMA1_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma1DisallowedPacketErr",
4853 0, 0, CNTR_NORMAL,
4854 access_tx_sdma1_disallowed_packet_err_cnt),
4855[C_TX_SDMA0_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma0DisallowedPacketErr",
4856 0, 0, CNTR_NORMAL,
4857 access_tx_sdma0_disallowed_packet_err_cnt),
4858[C_TX_CONFIG_PARITY_ERR] = CNTR_ELEM("TxConfigParityErr", 0, 0,
4859 CNTR_NORMAL,
4860 access_tx_config_parity_err_cnt),
4861[C_TX_SBRD_CTL_CSR_PARITY_ERR] = CNTR_ELEM("TxSbrdCtlCsrParityErr", 0, 0,
4862 CNTR_NORMAL,
4863 access_tx_sbrd_ctl_csr_parity_err_cnt),
4864[C_TX_LAUNCH_CSR_PARITY_ERR] = CNTR_ELEM("TxLaunchCsrParityErr", 0, 0,
4865 CNTR_NORMAL,
4866 access_tx_launch_csr_parity_err_cnt),
4867[C_TX_ILLEGAL_CL_ERR] = CNTR_ELEM("TxIllegalVLErr", 0, 0,
4868 CNTR_NORMAL,
4869 access_tx_illegal_vl_err_cnt),
4870[C_TX_SBRD_CTL_STATE_MACHINE_PARITY_ERR] = CNTR_ELEM(
4871 "TxSbrdCtlStateMachineParityErr", 0, 0,
4872 CNTR_NORMAL,
4873 access_tx_sbrd_ctl_state_machine_parity_err_cnt),
4874[C_TX_RESERVED_10] = CNTR_ELEM("Tx Egress Reserved 10", 0, 0,
4875 CNTR_NORMAL,
4876 access_egress_reserved_10_err_cnt),
4877[C_TX_RESERVED_9] = CNTR_ELEM("Tx Egress Reserved 9", 0, 0,
4878 CNTR_NORMAL,
4879 access_egress_reserved_9_err_cnt),
4880[C_TX_SDMA_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxSdmaLaunchIntfParityErr",
4881 0, 0, CNTR_NORMAL,
4882 access_tx_sdma_launch_intf_parity_err_cnt),
4883[C_TX_PIO_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxPioLaunchIntfParityErr", 0, 0,
4884 CNTR_NORMAL,
4885 access_tx_pio_launch_intf_parity_err_cnt),
4886[C_TX_RESERVED_6] = CNTR_ELEM("Tx Egress Reserved 6", 0, 0,
4887 CNTR_NORMAL,
4888 access_egress_reserved_6_err_cnt),
4889[C_TX_INCORRECT_LINK_STATE_ERR] = CNTR_ELEM("TxIncorrectLinkStateErr", 0, 0,
4890 CNTR_NORMAL,
4891 access_tx_incorrect_link_state_err_cnt),
4892[C_TX_LINK_DOWN_ERR] = CNTR_ELEM("TxLinkdownErr", 0, 0,
4893 CNTR_NORMAL,
4894 access_tx_linkdown_err_cnt),
4895[C_TX_EGRESS_FIFO_UNDERRUN_OR_PARITY_ERR] = CNTR_ELEM(
4896 "EgressFifoUnderrunOrParityErr", 0, 0,
4897 CNTR_NORMAL,
4898 access_tx_egress_fifi_underrun_or_parity_err_cnt),
4899[C_TX_RESERVED_2] = CNTR_ELEM("Tx Egress Reserved 2", 0, 0,
4900 CNTR_NORMAL,
4901 access_egress_reserved_2_err_cnt),
4902[C_TX_PKT_INTEGRITY_MEM_UNC_ERR] = CNTR_ELEM("TxPktIntegrityMemUncErr", 0, 0,
4903 CNTR_NORMAL,
4904 access_tx_pkt_integrity_mem_unc_err_cnt),
4905[C_TX_PKT_INTEGRITY_MEM_COR_ERR] = CNTR_ELEM("TxPktIntegrityMemCorErr", 0, 0,
4906 CNTR_NORMAL,
4907 access_tx_pkt_integrity_mem_cor_err_cnt),
4908/* SendErrStatus */
4909[C_SEND_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("SendCsrWriteBadAddrErr", 0, 0,
4910 CNTR_NORMAL,
4911 access_send_csr_write_bad_addr_err_cnt),
4912[C_SEND_CSR_READ_BAD_ADD_ERR] = CNTR_ELEM("SendCsrReadBadAddrErr", 0, 0,
4913 CNTR_NORMAL,
4914 access_send_csr_read_bad_addr_err_cnt),
4915[C_SEND_CSR_PARITY_ERR] = CNTR_ELEM("SendCsrParityErr", 0, 0,
4916 CNTR_NORMAL,
4917 access_send_csr_parity_cnt),
4918/* SendCtxtErrStatus */
4919[C_PIO_WRITE_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("PioWriteOutOfBoundsErr", 0, 0,
4920 CNTR_NORMAL,
4921 access_pio_write_out_of_bounds_err_cnt),
4922[C_PIO_WRITE_OVERFLOW_ERR] = CNTR_ELEM("PioWriteOverflowErr", 0, 0,
4923 CNTR_NORMAL,
4924 access_pio_write_overflow_err_cnt),
4925[C_PIO_WRITE_CROSSES_BOUNDARY_ERR] = CNTR_ELEM("PioWriteCrossesBoundaryErr",
4926 0, 0, CNTR_NORMAL,
4927 access_pio_write_crosses_boundary_err_cnt),
4928[C_PIO_DISALLOWED_PACKET_ERR] = CNTR_ELEM("PioDisallowedPacketErr", 0, 0,
4929 CNTR_NORMAL,
4930 access_pio_disallowed_packet_err_cnt),
4931[C_PIO_INCONSISTENT_SOP_ERR] = CNTR_ELEM("PioInconsistentSopErr", 0, 0,
4932 CNTR_NORMAL,
4933 access_pio_inconsistent_sop_err_cnt),
4934/* SendDmaEngErrStatus */
4935[C_SDMA_HEADER_REQUEST_FIFO_COR_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoCorErr",
4936 0, 0, CNTR_NORMAL,
4937 access_sdma_header_request_fifo_cor_err_cnt),
4938[C_SDMA_HEADER_STORAGE_COR_ERR] = CNTR_ELEM("SDmaHeaderStorageCorErr", 0, 0,
4939 CNTR_NORMAL,
4940 access_sdma_header_storage_cor_err_cnt),
4941[C_SDMA_PACKET_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPacketTrackingCorErr", 0, 0,
4942 CNTR_NORMAL,
4943 access_sdma_packet_tracking_cor_err_cnt),
4944[C_SDMA_ASSEMBLY_COR_ERR] = CNTR_ELEM("SDmaAssemblyCorErr", 0, 0,
4945 CNTR_NORMAL,
4946 access_sdma_assembly_cor_err_cnt),
4947[C_SDMA_DESC_TABLE_COR_ERR] = CNTR_ELEM("SDmaDescTableCorErr", 0, 0,
4948 CNTR_NORMAL,
4949 access_sdma_desc_table_cor_err_cnt),
4950[C_SDMA_HEADER_REQUEST_FIFO_UNC_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoUncErr",
4951 0, 0, CNTR_NORMAL,
4952 access_sdma_header_request_fifo_unc_err_cnt),
4953[C_SDMA_HEADER_STORAGE_UNC_ERR] = CNTR_ELEM("SDmaHeaderStorageUncErr", 0, 0,
4954 CNTR_NORMAL,
4955 access_sdma_header_storage_unc_err_cnt),
4956[C_SDMA_PACKET_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPacketTrackingUncErr", 0, 0,
4957 CNTR_NORMAL,
4958 access_sdma_packet_tracking_unc_err_cnt),
4959[C_SDMA_ASSEMBLY_UNC_ERR] = CNTR_ELEM("SDmaAssemblyUncErr", 0, 0,
4960 CNTR_NORMAL,
4961 access_sdma_assembly_unc_err_cnt),
4962[C_SDMA_DESC_TABLE_UNC_ERR] = CNTR_ELEM("SDmaDescTableUncErr", 0, 0,
4963 CNTR_NORMAL,
4964 access_sdma_desc_table_unc_err_cnt),
4965[C_SDMA_TIMEOUT_ERR] = CNTR_ELEM("SDmaTimeoutErr", 0, 0,
4966 CNTR_NORMAL,
4967 access_sdma_timeout_err_cnt),
4968[C_SDMA_HEADER_LENGTH_ERR] = CNTR_ELEM("SDmaHeaderLengthErr", 0, 0,
4969 CNTR_NORMAL,
4970 access_sdma_header_length_err_cnt),
4971[C_SDMA_HEADER_ADDRESS_ERR] = CNTR_ELEM("SDmaHeaderAddressErr", 0, 0,
4972 CNTR_NORMAL,
4973 access_sdma_header_address_err_cnt),
4974[C_SDMA_HEADER_SELECT_ERR] = CNTR_ELEM("SDmaHeaderSelectErr", 0, 0,
4975 CNTR_NORMAL,
4976 access_sdma_header_select_err_cnt),
4977[C_SMDA_RESERVED_9] = CNTR_ELEM("SDma Reserved 9", 0, 0,
4978 CNTR_NORMAL,
4979 access_sdma_reserved_9_err_cnt),
4980[C_SDMA_PACKET_DESC_OVERFLOW_ERR] = CNTR_ELEM("SDmaPacketDescOverflowErr", 0, 0,
4981 CNTR_NORMAL,
4982 access_sdma_packet_desc_overflow_err_cnt),
4983[C_SDMA_LENGTH_MISMATCH_ERR] = CNTR_ELEM("SDmaLengthMismatchErr", 0, 0,
4984 CNTR_NORMAL,
4985 access_sdma_length_mismatch_err_cnt),
4986[C_SDMA_HALT_ERR] = CNTR_ELEM("SDmaHaltErr", 0, 0,
4987 CNTR_NORMAL,
4988 access_sdma_halt_err_cnt),
4989[C_SDMA_MEM_READ_ERR] = CNTR_ELEM("SDmaMemReadErr", 0, 0,
4990 CNTR_NORMAL,
4991 access_sdma_mem_read_err_cnt),
4992[C_SDMA_FIRST_DESC_ERR] = CNTR_ELEM("SDmaFirstDescErr", 0, 0,
4993 CNTR_NORMAL,
4994 access_sdma_first_desc_err_cnt),
4995[C_SDMA_TAIL_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("SDmaTailOutOfBoundsErr", 0, 0,
4996 CNTR_NORMAL,
4997 access_sdma_tail_out_of_bounds_err_cnt),
4998[C_SDMA_TOO_LONG_ERR] = CNTR_ELEM("SDmaTooLongErr", 0, 0,
4999 CNTR_NORMAL,
5000 access_sdma_too_long_err_cnt),
5001[C_SDMA_GEN_MISMATCH_ERR] = CNTR_ELEM("SDmaGenMismatchErr", 0, 0,
5002 CNTR_NORMAL,
5003 access_sdma_gen_mismatch_err_cnt),
5004[C_SDMA_WRONG_DW_ERR] = CNTR_ELEM("SDmaWrongDwErr", 0, 0,
5005 CNTR_NORMAL,
5006 access_sdma_wrong_dw_err_cnt),
77241056
MM		 5007};
5008
5009static struct cntr_entry port_cntrs[PORT_CNTR_LAST] = {
5010[C_TX_UNSUP_VL] = TXE32_PORT_CNTR_ELEM(TxUnVLErr, SEND_UNSUP_VL_ERR_CNT,
5011 CNTR_NORMAL),
5012[C_TX_INVAL_LEN] = TXE32_PORT_CNTR_ELEM(TxInvalLen, SEND_LEN_ERR_CNT,
5013 CNTR_NORMAL),
5014[C_TX_MM_LEN_ERR] = TXE32_PORT_CNTR_ELEM(TxMMLenErr, SEND_MAX_MIN_LEN_ERR_CNT,
5015 CNTR_NORMAL),
5016[C_TX_UNDERRUN] = TXE32_PORT_CNTR_ELEM(TxUnderrun, SEND_UNDERRUN_CNT,
5017 CNTR_NORMAL),
5018[C_TX_FLOW_STALL] = TXE32_PORT_CNTR_ELEM(TxFlowStall, SEND_FLOW_STALL_CNT,
5019 CNTR_NORMAL),
5020[C_TX_DROPPED] = TXE32_PORT_CNTR_ELEM(TxDropped, SEND_DROPPED_PKT_CNT,
5021 CNTR_NORMAL),
5022[C_TX_HDR_ERR] = TXE32_PORT_CNTR_ELEM(TxHdrErr, SEND_HEADERS_ERR_CNT,
5023 CNTR_NORMAL),
5024[C_TX_PKT] = TXE64_PORT_CNTR_ELEM(TxPkt, SEND_DATA_PKT_CNT, CNTR_NORMAL),
5025[C_TX_WORDS] = TXE64_PORT_CNTR_ELEM(TxWords, SEND_DWORD_CNT, CNTR_NORMAL),
5026[C_TX_WAIT] = TXE64_PORT_CNTR_ELEM(TxWait, SEND_WAIT_CNT, CNTR_SYNTH),
5027[C_TX_FLIT_VL] = TXE64_PORT_CNTR_ELEM(TxFlitVL, SEND_DATA_VL0_CNT,
17fb4f29 5028 CNTR_SYNTH | CNTR_VL),
77241056 5029[C_TX_PKT_VL] = TXE64_PORT_CNTR_ELEM(TxPktVL, SEND_DATA_PKT_VL0_CNT,
17fb4f29 5030 CNTR_SYNTH | CNTR_VL),
77241056 5031[C_TX_WAIT_VL] = TXE64_PORT_CNTR_ELEM(TxWaitVL, SEND_WAIT_VL0_CNT,
17fb4f29 5032 CNTR_SYNTH | CNTR_VL),
77241056
MM		 5033[C_RX_PKT] = RXE64_PORT_CNTR_ELEM(RxPkt, RCV_DATA_PKT_CNT, CNTR_NORMAL),
5034[C_RX_WORDS] = RXE64_PORT_CNTR_ELEM(RxWords, RCV_DWORD_CNT, CNTR_NORMAL),
5035[C_SW_LINK_DOWN] = CNTR_ELEM("SwLinkDown", 0, 0, CNTR_SYNTH | CNTR_32BIT,
17fb4f29 5036 access_sw_link_dn_cnt),
77241056 5037[C_SW_LINK_UP] = CNTR_ELEM("SwLinkUp", 0, 0, CNTR_SYNTH | CNTR_32BIT,
17fb4f29 5038 access_sw_link_up_cnt),
6d014530
DL		 5039[C_SW_UNKNOWN_FRAME] = CNTR_ELEM("UnknownFrame", 0, 0, CNTR_NORMAL,
5040 access_sw_unknown_frame_cnt),
77241056 5041[C_SW_XMIT_DSCD] = CNTR_ELEM("XmitDscd", 0, 0, CNTR_SYNTH | CNTR_32BIT,
17fb4f29 5042 access_sw_xmit_discards),
77241056 5043[C_SW_XMIT_DSCD_VL] = CNTR_ELEM("XmitDscdVl", 0, 0,
17fb4f29
JJ		 5044 CNTR_SYNTH | CNTR_32BIT | CNTR_VL,
5045 access_sw_xmit_discards),
77241056 5046[C_SW_XMIT_CSTR_ERR] = CNTR_ELEM("XmitCstrErr", 0, 0, CNTR_SYNTH,
17fb4f29 5047 access_xmit_constraint_errs),
77241056 5048[C_SW_RCV_CSTR_ERR] = CNTR_ELEM("RcvCstrErr", 0, 0, CNTR_SYNTH,
17fb4f29 5049 access_rcv_constraint_errs),
77241056
MM		 5050[C_SW_IBP_LOOP_PKTS] = SW_IBP_CNTR(LoopPkts, loop_pkts),
5051[C_SW_IBP_RC_RESENDS] = SW_IBP_CNTR(RcResend, rc_resends),
5052[C_SW_IBP_RNR_NAKS] = SW_IBP_CNTR(RnrNak, rnr_naks),
5053[C_SW_IBP_OTHER_NAKS] = SW_IBP_CNTR(OtherNak, other_naks),
5054[C_SW_IBP_RC_TIMEOUTS] = SW_IBP_CNTR(RcTimeOut, rc_timeouts),
5055[C_SW_IBP_PKT_DROPS] = SW_IBP_CNTR(PktDrop, pkt_drops),
5056[C_SW_IBP_DMA_WAIT] = SW_IBP_CNTR(DmaWait, dmawait),
5057[C_SW_IBP_RC_SEQNAK] = SW_IBP_CNTR(RcSeqNak, rc_seqnak),
5058[C_SW_IBP_RC_DUPREQ] = SW_IBP_CNTR(RcDupRew, rc_dupreq),
5059[C_SW_IBP_RDMA_SEQ] = SW_IBP_CNTR(RdmaSeq, rdma_seq),
5060[C_SW_IBP_UNALIGNED] = SW_IBP_CNTR(Unaligned, unaligned),
5061[C_SW_IBP_SEQ_NAK] = SW_IBP_CNTR(SeqNak, seq_naks),
5062[C_SW_CPU_RC_ACKS] = CNTR_ELEM("RcAcks", 0, 0, CNTR_NORMAL,
5063 access_sw_cpu_rc_acks),
5064[C_SW_CPU_RC_QACKS] = CNTR_ELEM("RcQacks", 0, 0, CNTR_NORMAL,
17fb4f29 5065 access_sw_cpu_rc_qacks),
77241056 5066[C_SW_CPU_RC_DELAYED_COMP] = CNTR_ELEM("RcDelayComp", 0, 0, CNTR_NORMAL,
17fb4f29 5067 access_sw_cpu_rc_delayed_comp),
77241056
MM		 5068[OVR_LBL(0)] = OVR_ELM(0), [OVR_LBL(1)] = OVR_ELM(1),
5069[OVR_LBL(2)] = OVR_ELM(2), [OVR_LBL(3)] = OVR_ELM(3),
5070[OVR_LBL(4)] = OVR_ELM(4), [OVR_LBL(5)] = OVR_ELM(5),
5071[OVR_LBL(6)] = OVR_ELM(6), [OVR_LBL(7)] = OVR_ELM(7),
5072[OVR_LBL(8)] = OVR_ELM(8), [OVR_LBL(9)] = OVR_ELM(9),
5073[OVR_LBL(10)] = OVR_ELM(10), [OVR_LBL(11)] = OVR_ELM(11),
5074[OVR_LBL(12)] = OVR_ELM(12), [OVR_LBL(13)] = OVR_ELM(13),
5075[OVR_LBL(14)] = OVR_ELM(14), [OVR_LBL(15)] = OVR_ELM(15),
5076[OVR_LBL(16)] = OVR_ELM(16), [OVR_LBL(17)] = OVR_ELM(17),
5077[OVR_LBL(18)] = OVR_ELM(18), [OVR_LBL(19)] = OVR_ELM(19),
5078[OVR_LBL(20)] = OVR_ELM(20), [OVR_LBL(21)] = OVR_ELM(21),
5079[OVR_LBL(22)] = OVR_ELM(22), [OVR_LBL(23)] = OVR_ELM(23),
5080[OVR_LBL(24)] = OVR_ELM(24), [OVR_LBL(25)] = OVR_ELM(25),
5081[OVR_LBL(26)] = OVR_ELM(26), [OVR_LBL(27)] = OVR_ELM(27),
5082[OVR_LBL(28)] = OVR_ELM(28), [OVR_LBL(29)] = OVR_ELM(29),
5083[OVR_LBL(30)] = OVR_ELM(30), [OVR_LBL(31)] = OVR_ELM(31),
5084[OVR_LBL(32)] = OVR_ELM(32), [OVR_LBL(33)] = OVR_ELM(33),
5085[OVR_LBL(34)] = OVR_ELM(34), [OVR_LBL(35)] = OVR_ELM(35),
5086[OVR_LBL(36)] = OVR_ELM(36), [OVR_LBL(37)] = OVR_ELM(37),
5087[OVR_LBL(38)] = OVR_ELM(38), [OVR_LBL(39)] = OVR_ELM(39),
5088[OVR_LBL(40)] = OVR_ELM(40), [OVR_LBL(41)] = OVR_ELM(41),
5089[OVR_LBL(42)] = OVR_ELM(42), [OVR_LBL(43)] = OVR_ELM(43),
5090[OVR_LBL(44)] = OVR_ELM(44), [OVR_LBL(45)] = OVR_ELM(45),
5091[OVR_LBL(46)] = OVR_ELM(46), [OVR_LBL(47)] = OVR_ELM(47),
5092[OVR_LBL(48)] = OVR_ELM(48), [OVR_LBL(49)] = OVR_ELM(49),
5093[OVR_LBL(50)] = OVR_ELM(50), [OVR_LBL(51)] = OVR_ELM(51),
5094[OVR_LBL(52)] = OVR_ELM(52), [OVR_LBL(53)] = OVR_ELM(53),
5095[OVR_LBL(54)] = OVR_ELM(54), [OVR_LBL(55)] = OVR_ELM(55),
5096[OVR_LBL(56)] = OVR_ELM(56), [OVR_LBL(57)] = OVR_ELM(57),
5097[OVR_LBL(58)] = OVR_ELM(58), [OVR_LBL(59)] = OVR_ELM(59),
5098[OVR_LBL(60)] = OVR_ELM(60), [OVR_LBL(61)] = OVR_ELM(61),
5099[OVR_LBL(62)] = OVR_ELM(62), [OVR_LBL(63)] = OVR_ELM(63),
5100[OVR_LBL(64)] = OVR_ELM(64), [OVR_LBL(65)] = OVR_ELM(65),
5101[OVR_LBL(66)] = OVR_ELM(66), [OVR_LBL(67)] = OVR_ELM(67),
5102[OVR_LBL(68)] = OVR_ELM(68), [OVR_LBL(69)] = OVR_ELM(69),
5103[OVR_LBL(70)] = OVR_ELM(70), [OVR_LBL(71)] = OVR_ELM(71),
5104[OVR_LBL(72)] = OVR_ELM(72), [OVR_LBL(73)] = OVR_ELM(73),
5105[OVR_LBL(74)] = OVR_ELM(74), [OVR_LBL(75)] = OVR_ELM(75),
5106[OVR_LBL(76)] = OVR_ELM(76), [OVR_LBL(77)] = OVR_ELM(77),
5107[OVR_LBL(78)] = OVR_ELM(78), [OVR_LBL(79)] = OVR_ELM(79),
5108[OVR_LBL(80)] = OVR_ELM(80), [OVR_LBL(81)] = OVR_ELM(81),
5109[OVR_LBL(82)] = OVR_ELM(82), [OVR_LBL(83)] = OVR_ELM(83),
5110[OVR_LBL(84)] = OVR_ELM(84), [OVR_LBL(85)] = OVR_ELM(85),
5111[OVR_LBL(86)] = OVR_ELM(86), [OVR_LBL(87)] = OVR_ELM(87),
5112[OVR_LBL(88)] = OVR_ELM(88), [OVR_LBL(89)] = OVR_ELM(89),
5113[OVR_LBL(90)] = OVR_ELM(90), [OVR_LBL(91)] = OVR_ELM(91),
5114[OVR_LBL(92)] = OVR_ELM(92), [OVR_LBL(93)] = OVR_ELM(93),
5115[OVR_LBL(94)] = OVR_ELM(94), [OVR_LBL(95)] = OVR_ELM(95),
5116[OVR_LBL(96)] = OVR_ELM(96), [OVR_LBL(97)] = OVR_ELM(97),
5117[OVR_LBL(98)] = OVR_ELM(98), [OVR_LBL(99)] = OVR_ELM(99),
5118[OVR_LBL(100)] = OVR_ELM(100), [OVR_LBL(101)] = OVR_ELM(101),
5119[OVR_LBL(102)] = OVR_ELM(102), [OVR_LBL(103)] = OVR_ELM(103),
5120[OVR_LBL(104)] = OVR_ELM(104), [OVR_LBL(105)] = OVR_ELM(105),
5121[OVR_LBL(106)] = OVR_ELM(106), [OVR_LBL(107)] = OVR_ELM(107),
5122[OVR_LBL(108)] = OVR_ELM(108), [OVR_LBL(109)] = OVR_ELM(109),
5123[OVR_LBL(110)] = OVR_ELM(110), [OVR_LBL(111)] = OVR_ELM(111),
5124[OVR_LBL(112)] = OVR_ELM(112), [OVR_LBL(113)] = OVR_ELM(113),
5125[OVR_LBL(114)] = OVR_ELM(114), [OVR_LBL(115)] = OVR_ELM(115),
5126[OVR_LBL(116)] = OVR_ELM(116), [OVR_LBL(117)] = OVR_ELM(117),
5127[OVR_LBL(118)] = OVR_ELM(118), [OVR_LBL(119)] = OVR_ELM(119),
5128[OVR_LBL(120)] = OVR_ELM(120), [OVR_LBL(121)] = OVR_ELM(121),
5129[OVR_LBL(122)] = OVR_ELM(122), [OVR_LBL(123)] = OVR_ELM(123),
5130[OVR_LBL(124)] = OVR_ELM(124), [OVR_LBL(125)] = OVR_ELM(125),
5131[OVR_LBL(126)] = OVR_ELM(126), [OVR_LBL(127)] = OVR_ELM(127),
5132[OVR_LBL(128)] = OVR_ELM(128), [OVR_LBL(129)] = OVR_ELM(129),
5133[OVR_LBL(130)] = OVR_ELM(130), [OVR_LBL(131)] = OVR_ELM(131),
5134[OVR_LBL(132)] = OVR_ELM(132), [OVR_LBL(133)] = OVR_ELM(133),
5135[OVR_LBL(134)] = OVR_ELM(134), [OVR_LBL(135)] = OVR_ELM(135),
5136[OVR_LBL(136)] = OVR_ELM(136), [OVR_LBL(137)] = OVR_ELM(137),
5137[OVR_LBL(138)] = OVR_ELM(138), [OVR_LBL(139)] = OVR_ELM(139),
5138[OVR_LBL(140)] = OVR_ELM(140), [OVR_LBL(141)] = OVR_ELM(141),
5139[OVR_LBL(142)] = OVR_ELM(142), [OVR_LBL(143)] = OVR_ELM(143),
5140[OVR_LBL(144)] = OVR_ELM(144), [OVR_LBL(145)] = OVR_ELM(145),
5141[OVR_LBL(146)] = OVR_ELM(146), [OVR_LBL(147)] = OVR_ELM(147),
5142[OVR_LBL(148)] = OVR_ELM(148), [OVR_LBL(149)] = OVR_ELM(149),
5143[OVR_LBL(150)] = OVR_ELM(150), [OVR_LBL(151)] = OVR_ELM(151),
5144[OVR_LBL(152)] = OVR_ELM(152), [OVR_LBL(153)] = OVR_ELM(153),
5145[OVR_LBL(154)] = OVR_ELM(154), [OVR_LBL(155)] = OVR_ELM(155),
5146[OVR_LBL(156)] = OVR_ELM(156), [OVR_LBL(157)] = OVR_ELM(157),
5147[OVR_LBL(158)] = OVR_ELM(158), [OVR_LBL(159)] = OVR_ELM(159),
5148};
5149
5150/* ======================================================================== */
5151
77241056
MM		 5152/* return true if this is chip revision revision a */
5153int is_ax(struct hfi1_devdata *dd)
5154{
5155 u8 chip_rev_minor =
5156 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT
5157 & CCE_REVISION_CHIP_REV_MINOR_MASK;
5158 return (chip_rev_minor & 0xf0) == 0;
5159}
5160
5161/* return true if this is chip revision revision b */
5162int is_bx(struct hfi1_devdata *dd)
5163{
5164 u8 chip_rev_minor =
5165 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT
5166 & CCE_REVISION_CHIP_REV_MINOR_MASK;
995deafa 5167 return (chip_rev_minor & 0xF0) == 0x10;
77241056
MM		 5168}
5169
5170/*
5171 * Append string s to buffer buf. Arguments curp and len are the current
5172 * position and remaining length, respectively.
5173 *
5174 * return 0 on success, 1 on out of room
5175 */
5176static int append_str(char *buf, char **curp, int *lenp, const char *s)
5177{
5178 char *p = *curp;
5179 int len = *lenp;
5180 int result = 0; /* success */
5181 char c;
5182
5183 /* add a comma, if first in the buffer */
5184 if (p != buf) {
5185 if (len == 0) {
5186 result = 1; /* out of room */
5187 goto done;
5188 }
5189 *p++ = ',';
5190 len--;
5191 }
5192
5193 /* copy the string */
5194 while ((c = *s++) != 0) {
5195 if (len == 0) {
5196 result = 1; /* out of room */
5197 goto done;
5198 }
5199 *p++ = c;
5200 len--;
5201 }
5202
5203done:
5204 /* write return values */
5205 *curp = p;
5206 *lenp = len;
5207
5208 return result;
5209}
5210
5211/*
5212 * Using the given flag table, print a comma separated string into
5213 * the buffer. End in '*' if the buffer is too short.
5214 */
5215static char *flag_string(char *buf, int buf_len, u64 flags,
17fb4f29 5216 struct flag_table *table, int table_size)
77241056
MM		 5217{
5218 char extra[32];
5219 char *p = buf;
5220 int len = buf_len;
5221 int no_room = 0;
5222 int i;
5223
5224 /* make sure there is at least 2 so we can form "*" */
5225 if (len < 2)
5226 return "";
5227
5228 len--; /* leave room for a nul */
5229 for (i = 0; i < table_size; i++) {
5230 if (flags & table[i].flag) {
5231 no_room = append_str(buf, &p, &len, table[i].str);
5232 if (no_room)
5233 break;
5234 flags &= ~table[i].flag;
5235 }
5236 }
5237
5238 /* any undocumented bits left? */
5239 if (!no_room && flags) {
5240 snprintf(extra, sizeof(extra), "bits 0x%llx", flags);
5241 no_room = append_str(buf, &p, &len, extra);
5242 }
5243
5244 /* add * if ran out of room */
5245 if (no_room) {
5246 /* may need to back up to add space for a '*' */
5247 if (len == 0)
5248 --p;
5249 *p++ = '*';
5250 }
5251
5252 /* add final nul - space already allocated above */
5253 *p = 0;
5254 return buf;
5255}
5256
5257/* first 8 CCE error interrupt source names */
5258static const char * const cce_misc_names[] = {
5259 "CceErrInt", /* 0 */
5260 "RxeErrInt", /* 1 */
5261 "MiscErrInt", /* 2 */
5262 "Reserved3", /* 3 */
5263 "PioErrInt", /* 4 */
5264 "SDmaErrInt", /* 5 */
5265 "EgressErrInt", /* 6 */
5266 "TxeErrInt" /* 7 */
5267};
5268
5269/*
5270 * Return the miscellaneous error interrupt name.
5271 */
5272static char *is_misc_err_name(char *buf, size_t bsize, unsigned int source)
5273{
5274 if (source < ARRAY_SIZE(cce_misc_names))
5275 strncpy(buf, cce_misc_names[source], bsize);
5276 else
17fb4f29
JJ		 5277 snprintf(buf, bsize, "Reserved%u",
5278 source + IS_GENERAL_ERR_START);
77241056
MM		 5279
5280 return buf;
5281}
5282
5283/*
5284 * Return the SDMA engine error interrupt name.
5285 */
5286static char *is_sdma_eng_err_name(char *buf, size_t bsize, unsigned int source)
5287{
5288 snprintf(buf, bsize, "SDmaEngErrInt%u", source);
5289 return buf;
5290}
5291
5292/*
5293 * Return the send context error interrupt name.
5294 */
5295static char *is_sendctxt_err_name(char *buf, size_t bsize, unsigned int source)
5296{
5297 snprintf(buf, bsize, "SendCtxtErrInt%u", source);
5298 return buf;
5299}
5300
5301static const char * const various_names[] = {
5302 "PbcInt",
5303 "GpioAssertInt",
5304 "Qsfp1Int",
5305 "Qsfp2Int",
5306 "TCritInt"
5307};
5308
5309/*
5310 * Return the various interrupt name.
5311 */
5312static char *is_various_name(char *buf, size_t bsize, unsigned int source)
5313{
5314 if (source < ARRAY_SIZE(various_names))
5315 strncpy(buf, various_names[source], bsize);
5316 else
8638b77f 5317 snprintf(buf, bsize, "Reserved%u", source + IS_VARIOUS_START);
77241056
MM		 5318 return buf;
5319}
5320
5321/*
5322 * Return the DC interrupt name.
5323 */
5324static char *is_dc_name(char *buf, size_t bsize, unsigned int source)
5325{
5326 static const char * const dc_int_names[] = {
5327 "common",
5328 "lcb",
5329 "8051",
5330 "lbm" /* local block merge */
5331 };
5332
5333 if (source < ARRAY_SIZE(dc_int_names))
5334 snprintf(buf, bsize, "dc_%s_int", dc_int_names[source]);
5335 else
5336 snprintf(buf, bsize, "DCInt%u", source);
5337 return buf;
5338}
5339
5340static const char * const sdma_int_names[] = {
5341 "SDmaInt",
5342 "SdmaIdleInt",
5343 "SdmaProgressInt",
5344};
5345
5346/*
5347 * Return the SDMA engine interrupt name.
5348 */
5349static char *is_sdma_eng_name(char *buf, size_t bsize, unsigned int source)
5350{
5351 /* what interrupt */
5352 unsigned int what = source / TXE_NUM_SDMA_ENGINES;
5353 /* which engine */
5354 unsigned int which = source % TXE_NUM_SDMA_ENGINES;
5355
5356 if (likely(what < 3))
5357 snprintf(buf, bsize, "%s%u", sdma_int_names[what], which);
5358 else
5359 snprintf(buf, bsize, "Invalid SDMA interrupt %u", source);
5360 return buf;
5361}
5362
5363/*
5364 * Return the receive available interrupt name.
5365 */
5366static char *is_rcv_avail_name(char *buf, size_t bsize, unsigned int source)
5367{
5368 snprintf(buf, bsize, "RcvAvailInt%u", source);
5369 return buf;
5370}
5371
5372/*
5373 * Return the receive urgent interrupt name.
5374 */
5375static char *is_rcv_urgent_name(char *buf, size_t bsize, unsigned int source)
5376{
5377 snprintf(buf, bsize, "RcvUrgentInt%u", source);
5378 return buf;
5379}
5380
5381/*
5382 * Return the send credit interrupt name.
5383 */
5384static char *is_send_credit_name(char *buf, size_t bsize, unsigned int source)
5385{
5386 snprintf(buf, bsize, "SendCreditInt%u", source);
5387 return buf;
5388}
5389
5390/*
5391 * Return the reserved interrupt name.
5392 */
5393static char *is_reserved_name(char *buf, size_t bsize, unsigned int source)
5394{
5395 snprintf(buf, bsize, "Reserved%u", source + IS_RESERVED_START);
5396 return buf;
5397}
5398
5399static char *cce_err_status_string(char *buf, int buf_len, u64 flags)
5400{
5401 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5402 cce_err_status_flags,
5403 ARRAY_SIZE(cce_err_status_flags));
77241056
MM		 5404}
5405
5406static char *rxe_err_status_string(char *buf, int buf_len, u64 flags)
5407{
5408 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5409 rxe_err_status_flags,
5410 ARRAY_SIZE(rxe_err_status_flags));
77241056
MM		 5411}
5412
5413static char *misc_err_status_string(char *buf, int buf_len, u64 flags)
5414{
5415 return flag_string(buf, buf_len, flags, misc_err_status_flags,
17fb4f29 5416 ARRAY_SIZE(misc_err_status_flags));
77241056
MM		 5417}
5418
5419static char *pio_err_status_string(char *buf, int buf_len, u64 flags)
5420{
5421 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5422 pio_err_status_flags,
5423 ARRAY_SIZE(pio_err_status_flags));
77241056
MM		 5424}
5425
5426static char *sdma_err_status_string(char *buf, int buf_len, u64 flags)
5427{
5428 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5429 sdma_err_status_flags,
5430 ARRAY_SIZE(sdma_err_status_flags));
77241056
MM		 5431}
5432
5433static char *egress_err_status_string(char *buf, int buf_len, u64 flags)
5434{
5435 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5436 egress_err_status_flags,
5437 ARRAY_SIZE(egress_err_status_flags));
77241056
MM		 5438}
5439
5440static char *egress_err_info_string(char *buf, int buf_len, u64 flags)
5441{
5442 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5443 egress_err_info_flags,
5444 ARRAY_SIZE(egress_err_info_flags));
77241056
MM		 5445}
5446
5447static char *send_err_status_string(char *buf, int buf_len, u64 flags)
5448{
5449 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5450 send_err_status_flags,
5451 ARRAY_SIZE(send_err_status_flags));
77241056
MM		 5452}
5453
5454static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5455{
5456 char buf[96];
2c5b521a 5457 int i = 0;
77241056
MM		 5458
5459 /*
5460 * For most these errors, there is nothing that can be done except
5461 * report or record it.
5462 */
5463 dd_dev_info(dd, "CCE Error: %s\n",
17fb4f29 5464 cce_err_status_string(buf, sizeof(buf), reg));
77241056 5465
995deafa
MM		 5466 if ((reg & CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK) &&
5467 is_ax(dd) && (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)) {
77241056
MM		 5468 /* this error requires a manual drop into SPC freeze mode */
5469 /* then a fix up */
5470 start_freeze_handling(dd->pport, FREEZE_SELF);
5471 }
2c5b521a
JR		 5472
5473 for (i = 0; i < NUM_CCE_ERR_STATUS_COUNTERS; i++) {
5474 if (reg & (1ull << i)) {
5475 incr_cntr64(&dd->cce_err_status_cnt[i]);
5476 /* maintain a counter over all cce_err_status errors */
5477 incr_cntr64(&dd->sw_cce_err_status_aggregate);
5478 }
5479 }
77241056
MM		 5480}
5481
5482/*
5483 * Check counters for receive errors that do not have an interrupt
5484 * associated with them.
5485 */
5486#define RCVERR_CHECK_TIME 10
5487static void update_rcverr_timer(unsigned long opaque)
5488{
5489 struct hfi1_devdata *dd = (struct hfi1_devdata *)opaque;
5490 struct hfi1_pportdata *ppd = dd->pport;
5491 u32 cur_ovfl_cnt = read_dev_cntr(dd, C_RCV_OVF, CNTR_INVALID_VL);
5492
5493 if (dd->rcv_ovfl_cnt < cur_ovfl_cnt &&
17fb4f29 5494 ppd->port_error_action & OPA_PI_MASK_EX_BUFFER_OVERRUN) {
77241056 5495 dd_dev_info(dd, "%s: PortErrorAction bounce\n", __func__);
17fb4f29
JJ		 5496 set_link_down_reason(
5497 ppd, OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN, 0,
5498 OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN);
77241056
MM		 5499 queue_work(ppd->hfi1_wq, &ppd->link_bounce_work);
5500 }
50e5dcbe 5501 dd->rcv_ovfl_cnt = (u32)cur_ovfl_cnt;
77241056
MM		 5502
5503 mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME);
5504}
5505
5506static int init_rcverr(struct hfi1_devdata *dd)
5507{
24523a94 5508 setup_timer(&dd->rcverr_timer, update_rcverr_timer, (unsigned long)dd);
77241056
MM		 5509 /* Assume the hardware counter has been reset */
5510 dd->rcv_ovfl_cnt = 0;
5511 return mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME);
5512}
5513
5514static void free_rcverr(struct hfi1_devdata *dd)
5515{
5516 if (dd->rcverr_timer.data)
5517 del_timer_sync(&dd->rcverr_timer);
5518 dd->rcverr_timer.data = 0;
5519}
5520
5521static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5522{
5523 char buf[96];
2c5b521a 5524 int i = 0;
77241056
MM		 5525
5526 dd_dev_info(dd, "Receive Error: %s\n",
17fb4f29 5527 rxe_err_status_string(buf, sizeof(buf), reg));
77241056
MM		 5528
5529 if (reg & ALL_RXE_FREEZE_ERR) {
5530 int flags = 0;
5531
5532 /*
5533 * Freeze mode recovery is disabled for the errors
5534 * in RXE_FREEZE_ABORT_MASK
5535 */
995deafa 5536 if (is_ax(dd) && (reg & RXE_FREEZE_ABORT_MASK))
77241056
MM		 5537 flags = FREEZE_ABORT;
5538
5539 start_freeze_handling(dd->pport, flags);
5540 }
2c5b521a
JR		 5541
5542 for (i = 0; i < NUM_RCV_ERR_STATUS_COUNTERS; i++) {
5543 if (reg & (1ull << i))
5544 incr_cntr64(&dd->rcv_err_status_cnt[i]);
5545 }
77241056
MM		 5546}
5547
5548static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5549{
5550 char buf[96];
2c5b521a 5551 int i = 0;
77241056
MM		 5552
5553 dd_dev_info(dd, "Misc Error: %s",
17fb4f29 5554 misc_err_status_string(buf, sizeof(buf), reg));
2c5b521a
JR		 5555 for (i = 0; i < NUM_MISC_ERR_STATUS_COUNTERS; i++) {
5556 if (reg & (1ull << i))
5557 incr_cntr64(&dd->misc_err_status_cnt[i]);
5558 }
77241056
MM		 5559}
5560
5561static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5562{
5563 char buf[96];
2c5b521a 5564 int i = 0;
77241056
MM		 5565
5566 dd_dev_info(dd, "PIO Error: %s\n",
17fb4f29 5567 pio_err_status_string(buf, sizeof(buf), reg));
77241056
MM		 5568
5569 if (reg & ALL_PIO_FREEZE_ERR)
5570 start_freeze_handling(dd->pport, 0);
2c5b521a
JR		 5571
5572 for (i = 0; i < NUM_SEND_PIO_ERR_STATUS_COUNTERS; i++) {
5573 if (reg & (1ull << i))
5574 incr_cntr64(&dd->send_pio_err_status_cnt[i]);
5575 }
77241056
MM		 5576}
5577
5578static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5579{
5580 char buf[96];
2c5b521a 5581 int i = 0;
77241056
MM		 5582
5583 dd_dev_info(dd, "SDMA Error: %s\n",
17fb4f29 5584 sdma_err_status_string(buf, sizeof(buf), reg));
77241056
MM		 5585
5586 if (reg & ALL_SDMA_FREEZE_ERR)
5587 start_freeze_handling(dd->pport, 0);
2c5b521a
JR		 5588
5589 for (i = 0; i < NUM_SEND_DMA_ERR_STATUS_COUNTERS; i++) {
5590 if (reg & (1ull << i))
5591 incr_cntr64(&dd->send_dma_err_status_cnt[i]);
5592 }
77241056
MM		 5593}
5594
69a00b8e 5595static inline void __count_port_discards(struct hfi1_pportdata *ppd)
77241056 5596{
69a00b8e
MM		 5597 incr_cntr64(&ppd->port_xmit_discards);
5598}
77241056 5599
69a00b8e
MM		 5600static void count_port_inactive(struct hfi1_devdata *dd)
5601{
5602 __count_port_discards(dd->pport);
77241056
MM		 5603}
5604
5605/*
5606 * We have had a "disallowed packet" error during egress. Determine the
5607 * integrity check which failed, and update relevant error counter, etc.
5608 *
5609 * Note that the SEND_EGRESS_ERR_INFO register has only a single
5610 * bit of state per integrity check, and so we can miss the reason for an
5611 * egress error if more than one packet fails the same integrity check
5612 * since we cleared the corresponding bit in SEND_EGRESS_ERR_INFO.
5613 */
69a00b8e
MM		 5614static void handle_send_egress_err_info(struct hfi1_devdata *dd,
5615 int vl)
77241056
MM		 5616{
5617 struct hfi1_pportdata *ppd = dd->pport;
5618 u64 src = read_csr(dd, SEND_EGRESS_ERR_SOURCE); /* read first */
5619 u64 info = read_csr(dd, SEND_EGRESS_ERR_INFO);
5620 char buf[96];
5621
5622 /* clear down all observed info as quickly as possible after read */
5623 write_csr(dd, SEND_EGRESS_ERR_INFO, info);
5624
5625 dd_dev_info(dd,
17fb4f29
JJ		 5626 "Egress Error Info: 0x%llx, %s Egress Error Src 0x%llx\n",
5627 info, egress_err_info_string(buf, sizeof(buf), info), src);
77241056
MM		 5628
5629 /* Eventually add other counters for each bit */
69a00b8e
MM		 5630 if (info & PORT_DISCARD_EGRESS_ERRS) {
5631 int weight, i;
77241056 5632
69a00b8e 5633 /*
4c9e7aac
DL		 5634 * Count all applicable bits as individual errors and
5635 * attribute them to the packet that triggered this handler.
5636 * This may not be completely accurate due to limitations
5637 * on the available hardware error information. There is
5638 * a single information register and any number of error
5639 * packets may have occurred and contributed to it before
5640 * this routine is called. This means that:
5641 * a) If multiple packets with the same error occur before
5642 * this routine is called, earlier packets are missed.
5643 * There is only a single bit for each error type.
5644 * b) Errors may not be attributed to the correct VL.
5645 * The driver is attributing all bits in the info register
5646 * to the packet that triggered this call, but bits
5647 * could be an accumulation of different packets with
5648 * different VLs.
5649 * c) A single error packet may have multiple counts attached
5650 * to it. There is no way for the driver to know if
5651 * multiple bits set in the info register are due to a
5652 * single packet or multiple packets. The driver assumes
5653 * multiple packets.
69a00b8e 5654 */
4c9e7aac 5655 weight = hweight64(info & PORT_DISCARD_EGRESS_ERRS);
69a00b8e
MM		 5656 for (i = 0; i < weight; i++) {
5657 __count_port_discards(ppd);
5658 if (vl >= 0 && vl < TXE_NUM_DATA_VL)
5659 incr_cntr64(&ppd->port_xmit_discards_vl[vl]);
5660 else if (vl == 15)
5661 incr_cntr64(&ppd->port_xmit_discards_vl
5662 [C_VL_15]);
5663 }
77241056
MM		 5664 }
5665}
5666
5667/*
5668 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5669 * register. Does it represent a 'port inactive' error?
5670 */
5671static inline int port_inactive_err(u64 posn)
5672{
5673 return (posn >= SEES(TX_LINKDOWN) &&
5674 posn <= SEES(TX_INCORRECT_LINK_STATE));
5675}
5676
5677/*
5678 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5679 * register. Does it represent a 'disallowed packet' error?
5680 */
69a00b8e 5681static inline int disallowed_pkt_err(int posn)
77241056
MM		 5682{
5683 return (posn >= SEES(TX_SDMA0_DISALLOWED_PACKET) &&
5684 posn <= SEES(TX_SDMA15_DISALLOWED_PACKET));
5685}
5686
69a00b8e
MM		 5687/*
5688 * Input value is a bit position of one of the SDMA engine disallowed
5689 * packet errors. Return which engine. Use of this must be guarded by
5690 * disallowed_pkt_err().
5691 */
5692static inline int disallowed_pkt_engine(int posn)
5693{
5694 return posn - SEES(TX_SDMA0_DISALLOWED_PACKET);
5695}
5696
5697/*
5698 * Translate an SDMA engine to a VL. Return -1 if the tranlation cannot
5699 * be done.
5700 */
5701static int engine_to_vl(struct hfi1_devdata *dd, int engine)
5702{
5703 struct sdma_vl_map *m;
5704 int vl;
5705
5706 /* range check */
5707 if (engine < 0 || engine >= TXE_NUM_SDMA_ENGINES)
5708 return -1;
5709
5710 rcu_read_lock();
5711 m = rcu_dereference(dd->sdma_map);
5712 vl = m->engine_to_vl[engine];
5713 rcu_read_unlock();
5714
5715 return vl;
5716}
5717
5718/*
5719 * Translate the send context (sofware index) into a VL. Return -1 if the
5720 * translation cannot be done.
5721 */
5722static int sc_to_vl(struct hfi1_devdata *dd, int sw_index)
5723{
5724 struct send_context_info *sci;
5725 struct send_context *sc;
5726 int i;
5727
5728 sci = &dd->send_contexts[sw_index];
5729
5730 /* there is no information for user (PSM) and ack contexts */
44306f15 5731 if ((sci->type != SC_KERNEL) && (sci->type != SC_VL15))
69a00b8e
MM		 5732 return -1;
5733
5734 sc = sci->sc;
5735 if (!sc)
5736 return -1;
5737 if (dd->vld[15].sc == sc)
5738 return 15;
5739 for (i = 0; i < num_vls; i++)
5740 if (dd->vld[i].sc == sc)
5741 return i;
5742
5743 return -1;
5744}
5745
77241056
MM		 5746static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5747{
5748 u64 reg_copy = reg, handled = 0;
5749 char buf[96];
2c5b521a 5750 int i = 0;
77241056
MM		 5751
5752 if (reg & ALL_TXE_EGRESS_FREEZE_ERR)
5753 start_freeze_handling(dd->pport, 0);
69a00b8e
MM		 5754 else if (is_ax(dd) &&
5755 (reg & SEND_EGRESS_ERR_STATUS_TX_CREDIT_RETURN_VL_ERR_SMASK) &&
5756 (dd->icode != ICODE_FUNCTIONAL_SIMULATOR))
77241056
MM		 5757 start_freeze_handling(dd->pport, 0);
5758
5759 while (reg_copy) {
5760 int posn = fls64(reg_copy);
69a00b8e 5761 /* fls64() returns a 1-based offset, we want it zero based */
77241056 5762 int shift = posn - 1;
69a00b8e 5763 u64 mask = 1ULL << shift;
77241056
MM		 5764
5765 if (port_inactive_err(shift)) {
5766 count_port_inactive(dd);
69a00b8e 5767 handled |= mask;
77241056 5768 } else if (disallowed_pkt_err(shift)) {
69a00b8e
MM		 5769 int vl = engine_to_vl(dd, disallowed_pkt_engine(shift));
5770
5771 handle_send_egress_err_info(dd, vl);
5772 handled |= mask;
77241056 5773 }
69a00b8e 5774 reg_copy &= ~mask;
77241056
MM		 5775 }
5776
5777 reg &= ~handled;
5778
5779 if (reg)
5780 dd_dev_info(dd, "Egress Error: %s\n",
17fb4f29 5781 egress_err_status_string(buf, sizeof(buf), reg));
2c5b521a
JR		 5782
5783 for (i = 0; i < NUM_SEND_EGRESS_ERR_STATUS_COUNTERS; i++) {
5784 if (reg & (1ull << i))
5785 incr_cntr64(&dd->send_egress_err_status_cnt[i]);
5786 }
77241056
MM		 5787}
5788
5789static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5790{
5791 char buf[96];
2c5b521a 5792 int i = 0;
77241056
MM		 5793
5794 dd_dev_info(dd, "Send Error: %s\n",
17fb4f29 5795 send_err_status_string(buf, sizeof(buf), reg));
77241056 5796
2c5b521a
JR		 5797 for (i = 0; i < NUM_SEND_ERR_STATUS_COUNTERS; i++) {
5798 if (reg & (1ull << i))
5799 incr_cntr64(&dd->send_err_status_cnt[i]);
5800 }
77241056
MM		 5801}
5802
5803/*
5804 * The maximum number of times the error clear down will loop before
5805 * blocking a repeating error. This value is arbitrary.
5806 */
5807#define MAX_CLEAR_COUNT 20
5808
5809/*
5810 * Clear and handle an error register. All error interrupts are funneled
5811 * through here to have a central location to correctly handle single-
5812 * or multi-shot errors.
5813 *
5814 * For non per-context registers, call this routine with a context value
5815 * of 0 so the per-context offset is zero.
5816 *
5817 * If the handler loops too many times, assume that something is wrong
5818 * and can't be fixed, so mask the error bits.
5819 */
5820static void interrupt_clear_down(struct hfi1_devdata *dd,
5821 u32 context,
5822 const struct err_reg_info *eri)
5823{
5824 u64 reg;
5825 u32 count;
5826
5827 /* read in a loop until no more errors are seen */
5828 count = 0;
5829 while (1) {
5830 reg = read_kctxt_csr(dd, context, eri->status);
5831 if (reg == 0)
5832 break;
5833 write_kctxt_csr(dd, context, eri->clear, reg);
5834 if (likely(eri->handler))
5835 eri->handler(dd, context, reg);
5836 count++;
5837 if (count > MAX_CLEAR_COUNT) {
5838 u64 mask;
5839
5840 dd_dev_err(dd, "Repeating %s bits 0x%llx - masking\n",
17fb4f29 5841 eri->desc, reg);
77241056
MM		 5842 /*
5843 * Read-modify-write so any other masked bits
5844 * remain masked.
5845 */
5846 mask = read_kctxt_csr(dd, context, eri->mask);
5847 mask &= ~reg;
5848 write_kctxt_csr(dd, context, eri->mask, mask);
5849 break;
5850 }
5851 }
5852}
5853
5854/*
5855 * CCE block "misc" interrupt. Source is < 16.
5856 */
5857static void is_misc_err_int(struct hfi1_devdata *dd, unsigned int source)
5858{
5859 const struct err_reg_info *eri = &misc_errs[source];
5860
5861 if (eri->handler) {
5862 interrupt_clear_down(dd, 0, eri);
5863 } else {
5864 dd_dev_err(dd, "Unexpected misc interrupt (%u) - reserved\n",
17fb4f29 5865 source);
77241056
MM		 5866 }
5867}
5868
5869static char *send_context_err_status_string(char *buf, int buf_len, u64 flags)
5870{
5871 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5872 sc_err_status_flags,
5873 ARRAY_SIZE(sc_err_status_flags));
77241056
MM		 5874}
5875
5876/*
5877 * Send context error interrupt. Source (hw_context) is < 160.
5878 *
5879 * All send context errors cause the send context to halt. The normal
5880 * clear-down mechanism cannot be used because we cannot clear the
5881 * error bits until several other long-running items are done first.
5882 * This is OK because with the context halted, nothing else is going
5883 * to happen on it anyway.
5884 */
5885static void is_sendctxt_err_int(struct hfi1_devdata *dd,
5886 unsigned int hw_context)
5887{
5888 struct send_context_info *sci;
5889 struct send_context *sc;
5890 char flags[96];
5891 u64 status;
5892 u32 sw_index;
2c5b521a 5893 int i = 0;
77241056
MM		 5894
5895 sw_index = dd->hw_to_sw[hw_context];
5896 if (sw_index >= dd->num_send_contexts) {
5897 dd_dev_err(dd,
17fb4f29
JJ		 5898 "out of range sw index %u for send context %u\n",
5899 sw_index, hw_context);
77241056
MM		 5900 return;
5901 }
5902 sci = &dd->send_contexts[sw_index];
5903 sc = sci->sc;
5904 if (!sc) {
5905 dd_dev_err(dd, "%s: context %u(%u): no sc?\n", __func__,
17fb4f29 5906 sw_index, hw_context);
77241056
MM		 5907 return;
5908 }
5909
5910 /* tell the software that a halt has begun */
5911 sc_stop(sc, SCF_HALTED);
5912
5913 status = read_kctxt_csr(dd, hw_context, SEND_CTXT_ERR_STATUS);
5914
5915 dd_dev_info(dd, "Send Context %u(%u) Error: %s\n", sw_index, hw_context,
17fb4f29
JJ		 5916 send_context_err_status_string(flags, sizeof(flags),
5917 status));
77241056
MM		 5918
5919 if (status & SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK)
69a00b8e 5920 handle_send_egress_err_info(dd, sc_to_vl(dd, sw_index));
77241056
MM		 5921
5922 /*
5923 * Automatically restart halted kernel contexts out of interrupt
5924 * context. User contexts must ask the driver to restart the context.
5925 */
5926 if (sc->type != SC_USER)
5927 queue_work(dd->pport->hfi1_wq, &sc->halt_work);
2c5b521a
JR		 5928
5929 /*
5930 * Update the counters for the corresponding status bits.
5931 * Note that these particular counters are aggregated over all
5932 * 160 contexts.
5933 */
5934 for (i = 0; i < NUM_SEND_CTXT_ERR_STATUS_COUNTERS; i++) {
5935 if (status & (1ull << i))
5936 incr_cntr64(&dd->sw_ctxt_err_status_cnt[i]);
5937 }
77241056
MM		 5938}
5939
5940static void handle_sdma_eng_err(struct hfi1_devdata *dd,
5941 unsigned int source, u64 status)
5942{
5943 struct sdma_engine *sde;
2c5b521a 5944 int i = 0;
77241056
MM		 5945
5946 sde = &dd->per_sdma[source];
5947#ifdef CONFIG_SDMA_VERBOSITY
5948 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
5949 slashstrip(__FILE__), __LINE__, __func__);
5950 dd_dev_err(sde->dd, "CONFIG SDMA(%u) source: %u status 0x%llx\n",
5951 sde->this_idx, source, (unsigned long long)status);
5952#endif
a699c6c2 5953 sde->err_cnt++;
77241056 5954 sdma_engine_error(sde, status);
2c5b521a
JR		 5955
5956 /*
5957 * Update the counters for the corresponding status bits.
5958 * Note that these particular counters are aggregated over
5959 * all 16 DMA engines.
5960 */
5961 for (i = 0; i < NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS; i++) {
5962 if (status & (1ull << i))
5963 incr_cntr64(&dd->sw_send_dma_eng_err_status_cnt[i]);
5964 }
77241056
MM		 5965}
5966
5967/*
5968 * CCE block SDMA error interrupt. Source is < 16.
5969 */
5970static void is_sdma_eng_err_int(struct hfi1_devdata *dd, unsigned int source)
5971{
5972#ifdef CONFIG_SDMA_VERBOSITY
5973 struct sdma_engine *sde = &dd->per_sdma[source];
5974
5975 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
5976 slashstrip(__FILE__), __LINE__, __func__);
5977 dd_dev_err(dd, "CONFIG SDMA(%u) source: %u\n", sde->this_idx,
5978 source);
5979 sdma_dumpstate(sde);
5980#endif
5981 interrupt_clear_down(dd, source, &sdma_eng_err);
5982}
5983
5984/*
5985 * CCE block "various" interrupt. Source is < 8.
5986 */
5987static void is_various_int(struct hfi1_devdata *dd, unsigned int source)
5988{
5989 const struct err_reg_info *eri = &various_err[source];
5990
5991 /*
5992 * TCritInt cannot go through interrupt_clear_down()
5993 * because it is not a second tier interrupt. The handler
5994 * should be called directly.
5995 */
5996 if (source == TCRIT_INT_SOURCE)
5997 handle_temp_err(dd);
5998 else if (eri->handler)
5999 interrupt_clear_down(dd, 0, eri);
6000 else
6001 dd_dev_info(dd,
17fb4f29
JJ		 6002 "%s: Unimplemented/reserved interrupt %d\n",
6003 __func__, source);
77241056
MM		 6004}
6005
6006static void handle_qsfp_int(struct hfi1_devdata *dd, u32 src_ctx, u64 reg)
6007{
8ebd4cf1 6008 /* src_ctx is always zero */
77241056
MM		 6009 struct hfi1_pportdata *ppd = dd->pport;
6010 unsigned long flags;
6011 u64 qsfp_int_mgmt = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N);
6012
6013 if (reg & QSFP_HFI0_MODPRST_N) {
77241056 6014 if (!qsfp_mod_present(ppd)) {
e8aa284b
EH		 6015 dd_dev_info(dd, "%s: QSFP module removed\n",
6016 __func__);
6017
77241056
MM		 6018 ppd->driver_link_ready = 0;
6019 /*
6020 * Cable removed, reset all our information about the
6021 * cache and cable capabilities
6022 */
6023
6024 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
6025 /*
6026 * We don't set cache_refresh_required here as we expect
6027 * an interrupt when a cable is inserted
6028 */
6029 ppd->qsfp_info.cache_valid = 0;
8ebd4cf1
EH		 6030 ppd->qsfp_info.reset_needed = 0;
6031 ppd->qsfp_info.limiting_active = 0;
77241056 6032 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
17fb4f29 6033 flags);
8ebd4cf1
EH		 6034 /* Invert the ModPresent pin now to detect plug-in */
6035 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
6036 ASIC_QSFP1_INVERT, qsfp_int_mgmt);
a9c05e35
BM		 6037
6038 if ((ppd->offline_disabled_reason >
6039 HFI1_ODR_MASK(
e1bf0d5e 6040 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED)) ||
a9c05e35
BM		 6041 (ppd->offline_disabled_reason ==
6042 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE)))
6043 ppd->offline_disabled_reason =
6044 HFI1_ODR_MASK(
e1bf0d5e 6045 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED);
a9c05e35 6046
77241056
MM		 6047 if (ppd->host_link_state == HLS_DN_POLL) {
6048 /*
6049 * The link is still in POLL. This means
6050 * that the normal link down processing
6051 * will not happen. We have to do it here
6052 * before turning the DC off.
6053 */
6054 queue_work(ppd->hfi1_wq, &ppd->link_down_work);
6055 }
6056 } else {
e8aa284b
EH		 6057 dd_dev_info(dd, "%s: QSFP module inserted\n",
6058 __func__);
6059
77241056
MM		 6060 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
6061 ppd->qsfp_info.cache_valid = 0;
6062 ppd->qsfp_info.cache_refresh_required = 1;
6063 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
17fb4f29 6064 flags);
77241056 6065
8ebd4cf1
EH		 6066 /*
6067 * Stop inversion of ModPresent pin to detect
6068 * removal of the cable
6069 */
77241056 6070 qsfp_int_mgmt &= ~(u64)QSFP_HFI0_MODPRST_N;
8ebd4cf1
EH		 6071 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
6072 ASIC_QSFP1_INVERT, qsfp_int_mgmt);
6073
6074 ppd->offline_disabled_reason =
6075 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT);
77241056
MM		 6076 }
6077 }
6078
6079 if (reg & QSFP_HFI0_INT_N) {
e8aa284b 6080 dd_dev_info(dd, "%s: Interrupt received from QSFP module\n",
17fb4f29 6081 __func__);
77241056
MM		 6082 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
6083 ppd->qsfp_info.check_interrupt_flags = 1;
77241056
MM		 6084 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, flags);
6085 }
6086
6087 /* Schedule the QSFP work only if there is a cable attached. */
6088 if (qsfp_mod_present(ppd))
6089 queue_work(ppd->hfi1_wq, &ppd->qsfp_info.qsfp_work);
6090}
6091
6092static int request_host_lcb_access(struct hfi1_devdata *dd)
6093{
6094 int ret;
6095
6096 ret = do_8051_command(dd, HCMD_MISC,
17fb4f29
JJ		 6097 (u64)HCMD_MISC_REQUEST_LCB_ACCESS <<
6098 LOAD_DATA_FIELD_ID_SHIFT, NULL);
77241056
MM		 6099 if (ret != HCMD_SUCCESS) {
6100 dd_dev_err(dd, "%s: command failed with error %d\n",
17fb4f29 6101 __func__, ret);
77241056
MM		 6102 }
6103 return ret == HCMD_SUCCESS ? 0 : -EBUSY;
6104}
6105
6106static int request_8051_lcb_access(struct hfi1_devdata *dd)
6107{
6108 int ret;
6109
6110 ret = do_8051_command(dd, HCMD_MISC,
17fb4f29
JJ		 6111 (u64)HCMD_MISC_GRANT_LCB_ACCESS <<
6112 LOAD_DATA_FIELD_ID_SHIFT, NULL);
77241056
MM		 6113 if (ret != HCMD_SUCCESS) {
6114 dd_dev_err(dd, "%s: command failed with error %d\n",
17fb4f29 6115 __func__, ret);
77241056
MM		 6116 }
6117 return ret == HCMD_SUCCESS ? 0 : -EBUSY;
6118}
6119
6120/*
6121 * Set the LCB selector - allow host access. The DCC selector always
6122 * points to the host.
6123 */
6124static inline void set_host_lcb_access(struct hfi1_devdata *dd)
6125{
6126 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
17fb4f29
JJ		 6127 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK |
6128 DC_DC8051_CFG_CSR_ACCESS_SEL_LCB_SMASK);
77241056
MM		 6129}
6130
6131/*
6132 * Clear the LCB selector - allow 8051 access. The DCC selector always
6133 * points to the host.
6134 */
6135static inline void set_8051_lcb_access(struct hfi1_devdata *dd)
6136{
6137 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
17fb4f29 6138 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK);
77241056
MM		 6139}
6140
6141/*
6142 * Acquire LCB access from the 8051. If the host already has access,
6143 * just increment a counter. Otherwise, inform the 8051 that the
6144 * host is taking access.
6145 *
6146 * Returns:
6147 * 0 on success
6148 * -EBUSY if the 8051 has control and cannot be disturbed
6149 * -errno if unable to acquire access from the 8051
6150 */
6151int acquire_lcb_access(struct hfi1_devdata *dd, int sleep_ok)
6152{
6153 struct hfi1_pportdata *ppd = dd->pport;
6154 int ret = 0;
6155
6156 /*
6157 * Use the host link state lock so the operation of this routine
6158 * { link state check, selector change, count increment } can occur
6159 * as a unit against a link state change. Otherwise there is a
6160 * race between the state change and the count increment.
6161 */
6162 if (sleep_ok) {
6163 mutex_lock(&ppd->hls_lock);
6164 } else {
951842b0 6165 while (!mutex_trylock(&ppd->hls_lock))
77241056
MM		 6166 udelay(1);
6167 }
6168
6169 /* this access is valid only when the link is up */
0c7f77af 6170 if (ppd->host_link_state & HLS_DOWN) {
77241056 6171 dd_dev_info(dd, "%s: link state %s not up\n",
17fb4f29 6172 __func__, link_state_name(ppd->host_link_state));
77241056
MM		 6173 ret = -EBUSY;
6174 goto done;
6175 }
6176
6177 if (dd->lcb_access_count == 0) {
6178 ret = request_host_lcb_access(dd);
6179 if (ret) {
6180 dd_dev_err(dd,
17fb4f29
JJ		 6181 "%s: unable to acquire LCB access, err %d\n",
6182 __func__, ret);
77241056
MM		 6183 goto done;
6184 }
6185 set_host_lcb_access(dd);
6186 }
6187 dd->lcb_access_count++;
6188done:
6189 mutex_unlock(&ppd->hls_lock);
6190 return ret;
6191}
6192
6193/*
6194 * Release LCB access by decrementing the use count. If the count is moving
6195 * from 1 to 0, inform 8051 that it has control back.
6196 *
6197 * Returns:
6198 * 0 on success
6199 * -errno if unable to release access to the 8051
6200 */
6201int release_lcb_access(struct hfi1_devdata *dd, int sleep_ok)
6202{
6203 int ret = 0;
6204
6205 /*
6206 * Use the host link state lock because the acquire needed it.
6207 * Here, we only need to keep { selector change, count decrement }
6208 * as a unit.
6209 */
6210 if (sleep_ok) {
6211 mutex_lock(&dd->pport->hls_lock);
6212 } else {
951842b0 6213 while (!mutex_trylock(&dd->pport->hls_lock))
77241056
MM		 6214 udelay(1);
6215 }
6216
6217 if (dd->lcb_access_count == 0) {
6218 dd_dev_err(dd, "%s: LCB access count is zero. Skipping.\n",
17fb4f29 6219 __func__);
77241056
MM		 6220 goto done;
6221 }
6222
6223 if (dd->lcb_access_count == 1) {
6224 set_8051_lcb_access(dd);
6225 ret = request_8051_lcb_access(dd);
6226 if (ret) {
6227 dd_dev_err(dd,
17fb4f29
JJ		 6228 "%s: unable to release LCB access, err %d\n",
6229 __func__, ret);
77241056
MM		 6230 /* restore host access if the grant didn't work */
6231 set_host_lcb_access(dd);
6232 goto done;
6233 }
6234 }
6235 dd->lcb_access_count--;
6236done:
6237 mutex_unlock(&dd->pport->hls_lock);
6238 return ret;
6239}
6240
6241/*
6242 * Initialize LCB access variables and state. Called during driver load,
6243 * after most of the initialization is finished.
6244 *
6245 * The DC default is LCB access on for the host. The driver defaults to
6246 * leaving access to the 8051. Assign access now - this constrains the call
6247 * to this routine to be after all LCB set-up is done. In particular, after
6248 * hf1_init_dd() -> set_up_interrupts() -> clear_all_interrupts()
6249 */
6250static void init_lcb_access(struct hfi1_devdata *dd)
6251{
6252 dd->lcb_access_count = 0;
6253}
6254
6255/*
6256 * Write a response back to a 8051 request.
6257 */
6258static void hreq_response(struct hfi1_devdata *dd, u8 return_code, u16 rsp_data)
6259{
6260 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0,
17fb4f29
JJ		 6261 DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK |
6262 (u64)return_code <<
6263 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT |
6264 (u64)rsp_data << DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT);
77241056
MM		 6265}
6266
6267/*
cbac386a 6268 * Handle host requests from the 8051.
77241056 6269 */
145dd2b3 6270static void handle_8051_request(struct hfi1_pportdata *ppd)
77241056 6271{
cbac386a 6272 struct hfi1_devdata *dd = ppd->dd;
77241056 6273 u64 reg;
cbac386a 6274 u16 data = 0;
145dd2b3 6275 u8 type;
77241056
MM		 6276
6277 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_1);
6278 if ((reg & DC_DC8051_CFG_EXT_DEV_1_REQ_NEW_SMASK) == 0)
6279 return; /* no request */
6280
6281 /* zero out COMPLETED so the response is seen */
6282 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 0);
6283
6284 /* extract request details */
6285 type = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_SHIFT)
6286 & DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_MASK;
6287 data = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT)
6288 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_MASK;
6289
6290 switch (type) {
6291 case HREQ_LOAD_CONFIG:
6292 case HREQ_SAVE_CONFIG:
6293 case HREQ_READ_CONFIG:
6294 case HREQ_SET_TX_EQ_ABS:
6295 case HREQ_SET_TX_EQ_REL:
145dd2b3 6296 case HREQ_ENABLE:
77241056 6297 dd_dev_info(dd, "8051 request: request 0x%x not supported\n",
17fb4f29 6298 type);
77241056
MM		 6299 hreq_response(dd, HREQ_NOT_SUPPORTED, 0);
6300 break;
77241056
MM		 6301 case HREQ_CONFIG_DONE:
6302 hreq_response(dd, HREQ_SUCCESS, 0);
6303 break;
6304
6305 case HREQ_INTERFACE_TEST:
6306 hreq_response(dd, HREQ_SUCCESS, data);
6307 break;
77241056
MM		 6308 default:
6309 dd_dev_err(dd, "8051 request: unknown request 0x%x\n", type);
6310 hreq_response(dd, HREQ_NOT_SUPPORTED, 0);
6311 break;
6312 }
6313}
6314
b3e6b4bd
BJ		 6315/*
6316 * Set up allocation unit vaulue.
6317 */
6318void set_up_vau(struct hfi1_devdata *dd, u8 vau)
77241056 6319{
b3e6b4bd
BJ		 6320 u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
6321
6322 /* do not modify other values in the register */
6323 reg &= ~SEND_CM_GLOBAL_CREDIT_AU_SMASK;
6324 reg |= (u64)vau << SEND_CM_GLOBAL_CREDIT_AU_SHIFT;
6325 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
77241056
MM		 6326}
6327
6328/*
6329 * Set up initial VL15 credits of the remote. Assumes the rest of
b3e6b4bd
BJ		 6330 * the CM credit registers are zero from a previous global or credit reset.
6331 * Shared limit for VL15 will always be 0.
77241056 6332 */
b3e6b4bd 6333void set_up_vl15(struct hfi1_devdata *dd, u16 vl15buf)
77241056 6334{
b3e6b4bd
BJ		 6335 u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
6336
6337 /* set initial values for total and shared credit limit */
6338 reg &= ~(SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK |
6339 SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK);
6340
6341 /*
6342 * Set total limit to be equal to VL15 credits.
6343 * Leave shared limit at 0.
6344 */
6345 reg |= (u64)vl15buf << SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT;
6346 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
77241056 6347
eacc830f
DD		 6348 write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf
6349 << SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT);
77241056
MM		 6350}
6351
6352/*
6353 * Zero all credit details from the previous connection and
6354 * reset the CM manager's internal counters.
6355 */
6356void reset_link_credits(struct hfi1_devdata *dd)
6357{
6358 int i;
6359
6360 /* remove all previous VL credit limits */
6361 for (i = 0; i < TXE_NUM_DATA_VL; i++)
8638b77f 6362 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
77241056 6363 write_csr(dd, SEND_CM_CREDIT_VL15, 0);
b3e6b4bd 6364 write_csr(dd, SEND_CM_GLOBAL_CREDIT, 0);
77241056
MM		 6365 /* reset the CM block */
6366 pio_send_control(dd, PSC_CM_RESET);
b3e6b4bd
BJ		 6367 /* reset cached value */
6368 dd->vl15buf_cached = 0;
77241056
MM		 6369}
6370
6371/* convert a vCU to a CU */
6372static u32 vcu_to_cu(u8 vcu)
6373{
6374 return 1 << vcu;
6375}
6376
6377/* convert a CU to a vCU */
6378static u8 cu_to_vcu(u32 cu)
6379{
6380 return ilog2(cu);
6381}
6382
6383/* convert a vAU to an AU */
6384static u32 vau_to_au(u8 vau)
6385{
6386 return 8 * (1 << vau);
6387}
6388
6389static void set_linkup_defaults(struct hfi1_pportdata *ppd)
6390{
6391 ppd->sm_trap_qp = 0x0;
6392 ppd->sa_qp = 0x1;
6393}
6394
6395/*
6396 * Graceful LCB shutdown. This leaves the LCB FIFOs in reset.
6397 */
6398static void lcb_shutdown(struct hfi1_devdata *dd, int abort)
6399{
6400 u64 reg;
6401
6402 /* clear lcb run: LCB_CFG_RUN.EN = 0 */
6403 write_csr(dd, DC_LCB_CFG_RUN, 0);
6404 /* set tx fifo reset: LCB_CFG_TX_FIFOS_RESET.VAL = 1 */
6405 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET,
17fb4f29 6406 1ull << DC_LCB_CFG_TX_FIFOS_RESET_VAL_SHIFT);
77241056
MM		 6407 /* set dcc reset csr: DCC_CFG_RESET.{reset_lcb,reset_rx_fpe} = 1 */
6408 dd->lcb_err_en = read_csr(dd, DC_LCB_ERR_EN);
6409 reg = read_csr(dd, DCC_CFG_RESET);
17fb4f29
JJ		 6410 write_csr(dd, DCC_CFG_RESET, reg |
6411 (1ull << DCC_CFG_RESET_RESET_LCB_SHIFT) |
6412 (1ull << DCC_CFG_RESET_RESET_RX_FPE_SHIFT));
50e5dcbe 6413 (void)read_csr(dd, DCC_CFG_RESET); /* make sure the write completed */
77241056
MM		 6414 if (!abort) {
6415 udelay(1); /* must hold for the longer of 16cclks or 20ns */
6416 write_csr(dd, DCC_CFG_RESET, reg);
6417 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
6418 }
6419}
6420
6421/*
6422 * This routine should be called after the link has been transitioned to
6423 * OFFLINE (OFFLINE state has the side effect of putting the SerDes into
6424 * reset).
6425 *
6426 * The expectation is that the caller of this routine would have taken
6427 * care of properly transitioning the link into the correct state.
22546b74
TS		 6428 * NOTE: the caller needs to acquire the dd->dc8051_lock lock
6429 * before calling this function.
77241056 6430 */
22546b74 6431static void _dc_shutdown(struct hfi1_devdata *dd)
77241056 6432{
22546b74 6433 lockdep_assert_held(&dd->dc8051_lock);
77241056 6434
22546b74 6435 if (dd->dc_shutdown)
77241056 6436 return;
22546b74 6437
77241056 6438 dd->dc_shutdown = 1;
77241056
MM		 6439 /* Shutdown the LCB */
6440 lcb_shutdown(dd, 1);
4d114fdd
JJ		 6441 /*
6442 * Going to OFFLINE would have causes the 8051 to put the
77241056 6443 * SerDes into reset already. Just need to shut down the 8051,
4d114fdd
JJ		 6444 * itself.
6445 */
77241056
MM		 6446 write_csr(dd, DC_DC8051_CFG_RST, 0x1);
6447}
6448
22546b74
TS		 6449static void dc_shutdown(struct hfi1_devdata *dd)
6450{
6451 mutex_lock(&dd->dc8051_lock);
6452 _dc_shutdown(dd);
6453 mutex_unlock(&dd->dc8051_lock);
6454}
6455
4d114fdd
JJ		 6456/*
6457 * Calling this after the DC has been brought out of reset should not
6458 * do any damage.
22546b74
TS		 6459 * NOTE: the caller needs to acquire the dd->dc8051_lock lock
6460 * before calling this function.
4d114fdd 6461 */
22546b74 6462static void _dc_start(struct hfi1_devdata *dd)
77241056 6463{
22546b74 6464 lockdep_assert_held(&dd->dc8051_lock);
77241056 6465
77241056 6466 if (!dd->dc_shutdown)
22546b74
TS		 6467 return;
6468
77241056
MM		 6469 /* Take the 8051 out of reset */
6470 write_csr(dd, DC_DC8051_CFG_RST, 0ull);
6471 /* Wait until 8051 is ready */
22546b74 6472 if (wait_fm_ready(dd, TIMEOUT_8051_START))
77241056 6473 dd_dev_err(dd, "%s: timeout starting 8051 firmware\n",
17fb4f29 6474 __func__);
22546b74 6475
77241056
MM		 6476 /* Take away reset for LCB and RX FPE (set in lcb_shutdown). */
6477 write_csr(dd, DCC_CFG_RESET, 0x10);
6478 /* lcb_shutdown() with abort=1 does not restore these */
6479 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
77241056 6480 dd->dc_shutdown = 0;
22546b74
TS		 6481}
6482
6483static void dc_start(struct hfi1_devdata *dd)
6484{
6485 mutex_lock(&dd->dc8051_lock);
6486 _dc_start(dd);
6487 mutex_unlock(&dd->dc8051_lock);
77241056
MM		 6488}
6489
6490/*
6491 * These LCB adjustments are for the Aurora SerDes core in the FPGA.
6492 */
6493static void adjust_lcb_for_fpga_serdes(struct hfi1_devdata *dd)
6494{
6495 u64 rx_radr, tx_radr;
6496 u32 version;
6497
6498 if (dd->icode != ICODE_FPGA_EMULATION)
6499 return;
6500
6501 /*
6502 * These LCB defaults on emulator _s are good, nothing to do here:
6503 * LCB_CFG_TX_FIFOS_RADR
6504 * LCB_CFG_RX_FIFOS_RADR
6505 * LCB_CFG_LN_DCLK
6506 * LCB_CFG_IGNORE_LOST_RCLK
6507 */
6508 if (is_emulator_s(dd))
6509 return;
6510 /* else this is _p */
6511
6512 version = emulator_rev(dd);
995deafa 6513 if (!is_ax(dd))
77241056
MM		 6514 version = 0x2d; /* all B0 use 0x2d or higher settings */
6515
6516 if (version <= 0x12) {
6517 /* release 0x12 and below */
6518
6519 /*
6520 * LCB_CFG_RX_FIFOS_RADR.RST_VAL = 0x9
6521 * LCB_CFG_RX_FIFOS_RADR.OK_TO_JUMP_VAL = 0x9
6522 * LCB_CFG_RX_FIFOS_RADR.DO_NOT_JUMP_VAL = 0xa
6523 */
6524 rx_radr =
6525 0xaull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6526 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6527 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6528 /*
6529 * LCB_CFG_TX_FIFOS_RADR.ON_REINIT = 0 (default)
6530 * LCB_CFG_TX_FIFOS_RADR.RST_VAL = 6
6531 */
6532 tx_radr = 6ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6533 } else if (version <= 0x18) {
6534 /* release 0x13 up to 0x18 */
6535 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6536 rx_radr =
6537 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6538 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6539 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6540 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6541 } else if (version == 0x19) {
6542 /* release 0x19 */
6543 /* LCB_CFG_RX_FIFOS_RADR = 0xa99 */
6544 rx_radr =
6545 0xAull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6546 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6547 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6548 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6549 } else if (version == 0x1a) {
6550 /* release 0x1a */
6551 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6552 rx_radr =
6553 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6554 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6555 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6556 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6557 write_csr(dd, DC_LCB_CFG_LN_DCLK, 1ull);
6558 } else {
6559 /* release 0x1b and higher */
6560 /* LCB_CFG_RX_FIFOS_RADR = 0x877 */
6561 rx_radr =
6562 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6563 | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6564 | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6565 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6566 }
6567
6568 write_csr(dd, DC_LCB_CFG_RX_FIFOS_RADR, rx_radr);
6569 /* LCB_CFG_IGNORE_LOST_RCLK.EN = 1 */
6570 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK,
17fb4f29 6571 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK);
77241056
MM		 6572 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RADR, tx_radr);
6573}
6574
6575/*
6576 * Handle a SMA idle message
6577 *
6578 * This is a work-queue function outside of the interrupt.
6579 */
6580void handle_sma_message(struct work_struct *work)
6581{
6582 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6583 sma_message_work);
6584 struct hfi1_devdata *dd = ppd->dd;
6585 u64 msg;
6586 int ret;
6587
4d114fdd
JJ		 6588 /*
6589 * msg is bytes 1-4 of the 40-bit idle message - the command code
6590 * is stripped off
6591 */
77241056
MM		 6592 ret = read_idle_sma(dd, &msg);
6593 if (ret)
6594 return;
6595 dd_dev_info(dd, "%s: SMA message 0x%llx\n", __func__, msg);
6596 /*
6597 * React to the SMA message. Byte[1] (0 for us) is the command.
6598 */
6599 switch (msg & 0xff) {
6600 case SMA_IDLE_ARM:
6601 /*
6602 * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6603 * State Transitions
6604 *
6605 * Only expected in INIT or ARMED, discard otherwise.
6606 */
6607 if (ppd->host_link_state & (HLS_UP_INIT | HLS_UP_ARMED))
6608 ppd->neighbor_normal = 1;
6609 break;
6610 case SMA_IDLE_ACTIVE:
6611 /*
6612 * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6613 * State Transitions
6614 *
6615 * Can activate the node. Discard otherwise.
6616 */
d0d236ea
JJ		 6617 if (ppd->host_link_state == HLS_UP_ARMED &&
6618 ppd->is_active_optimize_enabled) {
77241056
MM		 6619 ppd->neighbor_normal = 1;
6620 ret = set_link_state(ppd, HLS_UP_ACTIVE);
6621 if (ret)
6622 dd_dev_err(
6623 dd,
6624 "%s: received Active SMA idle message, couldn't set link to Active\n",
6625 __func__);
6626 }
6627 break;
6628 default:
6629 dd_dev_err(dd,
17fb4f29
JJ		 6630 "%s: received unexpected SMA idle message 0x%llx\n",
6631 __func__, msg);
77241056
MM		 6632 break;
6633 }
6634}
6635
6636static void adjust_rcvctrl(struct hfi1_devdata *dd, u64 add, u64 clear)
6637{
6638 u64 rcvctrl;
6639 unsigned long flags;
6640
6641 spin_lock_irqsave(&dd->rcvctrl_lock, flags);
6642 rcvctrl = read_csr(dd, RCV_CTRL);
6643 rcvctrl |= add;
6644 rcvctrl &= ~clear;
6645 write_csr(dd, RCV_CTRL, rcvctrl);
6646 spin_unlock_irqrestore(&dd->rcvctrl_lock, flags);
6647}
6648
6649static inline void add_rcvctrl(struct hfi1_devdata *dd, u64 add)
6650{
6651 adjust_rcvctrl(dd, add, 0);
6652}
6653
6654static inline void clear_rcvctrl(struct hfi1_devdata *dd, u64 clear)
6655{
6656 adjust_rcvctrl(dd, 0, clear);
6657}
6658
6659/*
6660 * Called from all interrupt handlers to start handling an SPC freeze.
6661 */
6662void start_freeze_handling(struct hfi1_pportdata *ppd, int flags)
6663{
6664 struct hfi1_devdata *dd = ppd->dd;
6665 struct send_context *sc;
6666 int i;
6667
6668 if (flags & FREEZE_SELF)
6669 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
6670
6671 /* enter frozen mode */
6672 dd->flags |= HFI1_FROZEN;
6673
6674 /* notify all SDMA engines that they are going into a freeze */
6675 sdma_freeze_notify(dd, !!(flags & FREEZE_LINK_DOWN));
6676
6677 /* do halt pre-handling on all enabled send contexts */
6678 for (i = 0; i < dd->num_send_contexts; i++) {
6679 sc = dd->send_contexts[i].sc;
6680 if (sc && (sc->flags & SCF_ENABLED))
6681 sc_stop(sc, SCF_FROZEN | SCF_HALTED);
6682 }
6683
6684 /* Send context are frozen. Notify user space */
6685 hfi1_set_uevent_bits(ppd, _HFI1_EVENT_FROZEN_BIT);
6686
6687 if (flags & FREEZE_ABORT) {
6688 dd_dev_err(dd,
6689 "Aborted freeze recovery. Please REBOOT system\n");
6690 return;
6691 }
6692 /* queue non-interrupt handler */
6693 queue_work(ppd->hfi1_wq, &ppd->freeze_work);
6694}
6695
6696/*
6697 * Wait until all 4 sub-blocks indicate that they have frozen or unfrozen,
6698 * depending on the "freeze" parameter.
6699 *
6700 * No need to return an error if it times out, our only option
6701 * is to proceed anyway.
6702 */
6703static void wait_for_freeze_status(struct hfi1_devdata *dd, int freeze)
6704{
6705 unsigned long timeout;
6706 u64 reg;
6707
6708 timeout = jiffies + msecs_to_jiffies(FREEZE_STATUS_TIMEOUT);
6709 while (1) {
6710 reg = read_csr(dd, CCE_STATUS);
6711 if (freeze) {
6712 /* waiting until all indicators are set */
6713 if ((reg & ALL_FROZE) == ALL_FROZE)
6714 return; /* all done */
6715 } else {
6716 /* waiting until all indicators are clear */
6717 if ((reg & ALL_FROZE) == 0)
6718 return; /* all done */
6719 }
6720
6721 if (time_after(jiffies, timeout)) {
6722 dd_dev_err(dd,
17fb4f29
JJ		 6723 "Time out waiting for SPC %sfreeze, bits 0x%llx, expecting 0x%llx, continuing",
6724 freeze ? "" : "un", reg & ALL_FROZE,
6725 freeze ? ALL_FROZE : 0ull);
77241056
MM		 6726 return;
6727 }
6728 usleep_range(80, 120);
6729 }
6730}
6731
6732/*
6733 * Do all freeze handling for the RXE block.
6734 */
6735static void rxe_freeze(struct hfi1_devdata *dd)
6736{
6737 int i;
6738
6739 /* disable port */
6740 clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
6741
6742 /* disable all receive contexts */
6743 for (i = 0; i < dd->num_rcv_contexts; i++)
6744 hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS, i);
6745}
6746
6747/*
6748 * Unfreeze handling for the RXE block - kernel contexts only.
6749 * This will also enable the port. User contexts will do unfreeze
6750 * handling on a per-context basis as they call into the driver.
6751 *
6752 */
6753static void rxe_kernel_unfreeze(struct hfi1_devdata *dd)
6754{
566c157c 6755 u32 rcvmask;
77241056
MM		 6756 int i;
6757
6758 /* enable all kernel contexts */
2280740f
VN		 6759 for (i = 0; i < dd->num_rcv_contexts; i++) {
6760 struct hfi1_ctxtdata *rcd = dd->rcd[i];
6761
6762 /* Ensure all non-user contexts(including vnic) are enabled */
6763 if (!rcd || !rcd->sc || (rcd->sc->type == SC_USER))
6764 continue;
6765
566c157c
MH		 6766 rcvmask = HFI1_RCVCTRL_CTXT_ENB;
6767 /* HFI1_RCVCTRL_TAILUPD_[ENB|DIS] needs to be set explicitly */
6768 rcvmask |= HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, DMA_RTAIL) ?
6769 HFI1_RCVCTRL_TAILUPD_ENB : HFI1_RCVCTRL_TAILUPD_DIS;
6770 hfi1_rcvctrl(dd, rcvmask, i);
6771 }
77241056
MM		 6772
6773 /* enable port */
6774 add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
6775}
6776
6777/*
6778 * Non-interrupt SPC freeze handling.
6779 *
6780 * This is a work-queue function outside of the triggering interrupt.
6781 */
6782void handle_freeze(struct work_struct *work)
6783{
6784 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6785 freeze_work);
6786 struct hfi1_devdata *dd = ppd->dd;
6787
6788 /* wait for freeze indicators on all affected blocks */
77241056
MM		 6789 wait_for_freeze_status(dd, 1);
6790
6791 /* SPC is now frozen */
6792
6793 /* do send PIO freeze steps */
6794 pio_freeze(dd);
6795
6796 /* do send DMA freeze steps */
6797 sdma_freeze(dd);
6798
6799 /* do send egress freeze steps - nothing to do */
6800
6801 /* do receive freeze steps */
6802 rxe_freeze(dd);
6803
6804 /*
6805 * Unfreeze the hardware - clear the freeze, wait for each
6806 * block's frozen bit to clear, then clear the frozen flag.
6807 */
6808 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
6809 wait_for_freeze_status(dd, 0);
6810
995deafa 6811 if (is_ax(dd)) {
77241056
MM		 6812 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
6813 wait_for_freeze_status(dd, 1);
6814 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
6815 wait_for_freeze_status(dd, 0);
6816 }
6817
6818 /* do send PIO unfreeze steps for kernel contexts */
6819 pio_kernel_unfreeze(dd);
6820
6821 /* do send DMA unfreeze steps */
6822 sdma_unfreeze(dd);
6823
6824 /* do send egress unfreeze steps - nothing to do */
6825
6826 /* do receive unfreeze steps for kernel contexts */
6827 rxe_kernel_unfreeze(dd);
6828
6829 /*
6830 * The unfreeze procedure touches global device registers when
6831 * it disables and re-enables RXE. Mark the device unfrozen
6832 * after all that is done so other parts of the driver waiting
6833 * for the device to unfreeze don't do things out of order.
6834 *
6835 * The above implies that the meaning of HFI1_FROZEN flag is
6836 * "Device has gone into freeze mode and freeze mode handling
6837 * is still in progress."
6838 *
6839 * The flag will be removed when freeze mode processing has
6840 * completed.
6841 */
6842 dd->flags &= ~HFI1_FROZEN;
6843 wake_up(&dd->event_queue);
6844
6845 /* no longer frozen */
77241056
MM		 6846}
6847
6848/*
6849 * Handle a link up interrupt from the 8051.
6850 *
6851 * This is a work-queue function outside of the interrupt.
6852 */
6853void handle_link_up(struct work_struct *work)
6854{
6855 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
17fb4f29 6856 link_up_work);
b3e6b4bd
BJ		 6857 struct hfi1_devdata *dd = ppd->dd;
6858
77241056
MM		 6859 set_link_state(ppd, HLS_UP_INIT);
6860
6861 /* cache the read of DC_LCB_STS_ROUND_TRIP_LTP_CNT */
b3e6b4bd 6862 read_ltp_rtt(dd);
77241056
MM		 6863 /*
6864 * OPA specifies that certain counters are cleared on a transition
6865 * to link up, so do that.
6866 */
b3e6b4bd 6867 clear_linkup_counters(dd);
77241056
MM		 6868 /*
6869 * And (re)set link up default values.
6870 */
6871 set_linkup_defaults(ppd);
6872
b3e6b4bd
BJ		 6873 /*
6874 * Set VL15 credits. Use cached value from verify cap interrupt.
6875 * In case of quick linkup or simulator, vl15 value will be set by
6876 * handle_linkup_change. VerifyCap interrupt handler will not be
6877 * called in those scenarios.
6878 */
6879 if (!(quick_linkup || dd->icode == ICODE_FUNCTIONAL_SIMULATOR))
6880 set_up_vl15(dd, dd->vl15buf_cached);
6881
77241056
MM		 6882 /* enforce link speed enabled */
6883 if ((ppd->link_speed_active & ppd->link_speed_enabled) == 0) {
6884 /* oops - current speed is not enabled, bounce */
b3e6b4bd 6885 dd_dev_err(dd,
17fb4f29
JJ		 6886 "Link speed active 0x%x is outside enabled 0x%x, downing link\n",
6887 ppd->link_speed_active, ppd->link_speed_enabled);
77241056 6888 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_SPEED_POLICY, 0,
17fb4f29 6889 OPA_LINKDOWN_REASON_SPEED_POLICY);
77241056
MM		 6890 set_link_state(ppd, HLS_DN_OFFLINE);
6891 start_link(ppd);
6892 }
6893}
6894
4d114fdd
JJ		 6895/*
6896 * Several pieces of LNI information were cached for SMA in ppd.
6897 * Reset these on link down
6898 */
77241056
MM		 6899static void reset_neighbor_info(struct hfi1_pportdata *ppd)
6900{
6901 ppd->neighbor_guid = 0;
6902 ppd->neighbor_port_number = 0;
6903 ppd->neighbor_type = 0;
6904 ppd->neighbor_fm_security = 0;
6905}
6906
feb831dd
DL		 6907static const char * const link_down_reason_strs[] = {
6908 [OPA_LINKDOWN_REASON_NONE] = "None",
6909 [OPA_LINKDOWN_REASON_RCV_ERROR_0] = "Recive error 0",
6910 [OPA_LINKDOWN_REASON_BAD_PKT_LEN] = "Bad packet length",
6911 [OPA_LINKDOWN_REASON_PKT_TOO_LONG] = "Packet too long",
6912 [OPA_LINKDOWN_REASON_PKT_TOO_SHORT] = "Packet too short",
6913 [OPA_LINKDOWN_REASON_BAD_SLID] = "Bad SLID",
6914 [OPA_LINKDOWN_REASON_BAD_DLID] = "Bad DLID",
6915 [OPA_LINKDOWN_REASON_BAD_L2] = "Bad L2",
6916 [OPA_LINKDOWN_REASON_BAD_SC] = "Bad SC",
6917 [OPA_LINKDOWN_REASON_RCV_ERROR_8] = "Receive error 8",
6918 [OPA_LINKDOWN_REASON_BAD_MID_TAIL] = "Bad mid tail",
6919 [OPA_LINKDOWN_REASON_RCV_ERROR_10] = "Receive error 10",
6920 [OPA_LINKDOWN_REASON_PREEMPT_ERROR] = "Preempt error",
6921 [OPA_LINKDOWN_REASON_PREEMPT_VL15] = "Preempt vl15",
6922 [OPA_LINKDOWN_REASON_BAD_VL_MARKER] = "Bad VL marker",
6923 [OPA_LINKDOWN_REASON_RCV_ERROR_14] = "Receive error 14",
6924 [OPA_LINKDOWN_REASON_RCV_ERROR_15] = "Receive error 15",
6925 [OPA_LINKDOWN_REASON_BAD_HEAD_DIST] = "Bad head distance",
6926 [OPA_LINKDOWN_REASON_BAD_TAIL_DIST] = "Bad tail distance",
6927 [OPA_LINKDOWN_REASON_BAD_CTRL_DIST] = "Bad control distance",
6928 [OPA_LINKDOWN_REASON_BAD_CREDIT_ACK] = "Bad credit ack",
6929 [OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER] = "Unsupported VL marker",
6930 [OPA_LINKDOWN_REASON_BAD_PREEMPT] = "Bad preempt",
6931 [OPA_LINKDOWN_REASON_BAD_CONTROL_FLIT] = "Bad control flit",
6932 [OPA_LINKDOWN_REASON_EXCEED_MULTICAST_LIMIT] = "Exceed multicast limit",
6933 [OPA_LINKDOWN_REASON_RCV_ERROR_24] = "Receive error 24",
6934 [OPA_LINKDOWN_REASON_RCV_ERROR_25] = "Receive error 25",
6935 [OPA_LINKDOWN_REASON_RCV_ERROR_26] = "Receive error 26",
6936 [OPA_LINKDOWN_REASON_RCV_ERROR_27] = "Receive error 27",
6937 [OPA_LINKDOWN_REASON_RCV_ERROR_28] = "Receive error 28",
6938 [OPA_LINKDOWN_REASON_RCV_ERROR_29] = "Receive error 29",
6939 [OPA_LINKDOWN_REASON_RCV_ERROR_30] = "Receive error 30",
6940 [OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN] =
6941 "Excessive buffer overrun",
6942 [OPA_LINKDOWN_REASON_UNKNOWN] = "Unknown",
6943 [OPA_LINKDOWN_REASON_REBOOT] = "Reboot",
6944 [OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN] = "Neighbor unknown",
6945 [OPA_LINKDOWN_REASON_FM_BOUNCE] = "FM bounce",
6946 [OPA_LINKDOWN_REASON_SPEED_POLICY] = "Speed policy",
6947 [OPA_LINKDOWN_REASON_WIDTH_POLICY] = "Width policy",
6948 [OPA_LINKDOWN_REASON_DISCONNECTED] = "Disconnected",
6949 [OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED] =
6950 "Local media not installed",
6951 [OPA_LINKDOWN_REASON_NOT_INSTALLED] = "Not installed",
6952 [OPA_LINKDOWN_REASON_CHASSIS_CONFIG] = "Chassis config",
6953 [OPA_LINKDOWN_REASON_END_TO_END_NOT_INSTALLED] =
6954 "End to end not installed",
6955 [OPA_LINKDOWN_REASON_POWER_POLICY] = "Power policy",
6956 [OPA_LINKDOWN_REASON_LINKSPEED_POLICY] = "Link speed policy",
6957 [OPA_LINKDOWN_REASON_LINKWIDTH_POLICY] = "Link width policy",
6958 [OPA_LINKDOWN_REASON_SWITCH_MGMT] = "Switch management",
6959 [OPA_LINKDOWN_REASON_SMA_DISABLED] = "SMA disabled",
6960 [OPA_LINKDOWN_REASON_TRANSIENT] = "Transient"
6961};
6962
6963/* return the neighbor link down reason string */
6964static const char *link_down_reason_str(u8 reason)
6965{
6966 const char *str = NULL;
6967
6968 if (reason < ARRAY_SIZE(link_down_reason_strs))
6969 str = link_down_reason_strs[reason];
6970 if (!str)
6971 str = "(invalid)";
6972
6973 return str;
6974}
6975
77241056
MM		 6976/*
6977 * Handle a link down interrupt from the 8051.
6978 *
6979 * This is a work-queue function outside of the interrupt.
6980 */
6981void handle_link_down(struct work_struct *work)
6982{
6983 u8 lcl_reason, neigh_reason = 0;
feb831dd 6984 u8 link_down_reason;
77241056 6985 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
feb831dd
DL		 6986 link_down_work);
6987 int was_up;
6988 static const char ldr_str[] = "Link down reason: ";
77241056 6989
8ebd4cf1
EH		 6990 if ((ppd->host_link_state &
6991 (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) &&
6992 ppd->port_type == PORT_TYPE_FIXED)
6993 ppd->offline_disabled_reason =
6994 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NOT_INSTALLED);
6995
6996 /* Go offline first, then deal with reading/writing through 8051 */
feb831dd 6997 was_up = !!(ppd->host_link_state & HLS_UP);
77241056
MM		 6998 set_link_state(ppd, HLS_DN_OFFLINE);
6999
feb831dd
DL		 7000 if (was_up) {
7001 lcl_reason = 0;
7002 /* link down reason is only valid if the link was up */
7003 read_link_down_reason(ppd->dd, &link_down_reason);
7004 switch (link_down_reason) {
7005 case LDR_LINK_TRANSFER_ACTIVE_LOW:
7006 /* the link went down, no idle message reason */
7007 dd_dev_info(ppd->dd, "%sUnexpected link down\n",
7008 ldr_str);
7009 break;
7010 case LDR_RECEIVED_LINKDOWN_IDLE_MSG:
7011 /*
7012 * The neighbor reason is only valid if an idle message
7013 * was received for it.
7014 */
7015 read_planned_down_reason_code(ppd->dd, &neigh_reason);
7016 dd_dev_info(ppd->dd,
7017 "%sNeighbor link down message %d, %s\n",
7018 ldr_str, neigh_reason,
7019 link_down_reason_str(neigh_reason));
7020 break;
7021 case LDR_RECEIVED_HOST_OFFLINE_REQ:
7022 dd_dev_info(ppd->dd,
7023 "%sHost requested link to go offline\n",
7024 ldr_str);
7025 break;
7026 default:
7027 dd_dev_info(ppd->dd, "%sUnknown reason 0x%x\n",
7028 ldr_str, link_down_reason);
7029 break;
7030 }
77241056 7031
feb831dd
DL		 7032 /*
7033 * If no reason, assume peer-initiated but missed
7034 * LinkGoingDown idle flits.
7035 */
7036 if (neigh_reason == 0)
7037 lcl_reason = OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN;
7038 } else {
7039 /* went down while polling or going up */
7040 lcl_reason = OPA_LINKDOWN_REASON_TRANSIENT;
7041 }
77241056
MM		 7042
7043 set_link_down_reason(ppd, lcl_reason, neigh_reason, 0);
7044
015e91fb
DL		 7045 /* inform the SMA when the link transitions from up to down */
7046 if (was_up && ppd->local_link_down_reason.sma == 0 &&
7047 ppd->neigh_link_down_reason.sma == 0) {
7048 ppd->local_link_down_reason.sma =
7049 ppd->local_link_down_reason.latest;
7050 ppd->neigh_link_down_reason.sma =
7051 ppd->neigh_link_down_reason.latest;
7052 }
7053
77241056
MM		 7054 reset_neighbor_info(ppd);
7055
7056 /* disable the port */
7057 clear_rcvctrl(ppd->dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
7058
4d114fdd
JJ		 7059 /*
7060 * If there is no cable attached, turn the DC off. Otherwise,
7061 * start the link bring up.
7062 */
0db9dec2 7063 if (ppd->port_type == PORT_TYPE_QSFP && !qsfp_mod_present(ppd))
77241056 7064 dc_shutdown(ppd->dd);
0db9dec2 7065 else
77241056
MM		 7066 start_link(ppd);
7067}
7068
7069void handle_link_bounce(struct work_struct *work)
7070{
7071 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7072 link_bounce_work);
7073
7074 /*
7075 * Only do something if the link is currently up.
7076 */
7077 if (ppd->host_link_state & HLS_UP) {
7078 set_link_state(ppd, HLS_DN_OFFLINE);
7079 start_link(ppd);
7080 } else {
7081 dd_dev_info(ppd->dd, "%s: link not up (%s), nothing to do\n",
17fb4f29 7082 __func__, link_state_name(ppd->host_link_state));
77241056
MM		 7083 }
7084}
7085
7086/*
7087 * Mask conversion: Capability exchange to Port LTP. The capability
7088 * exchange has an implicit 16b CRC that is mandatory.
7089 */
7090static int cap_to_port_ltp(int cap)
7091{
7092 int port_ltp = PORT_LTP_CRC_MODE_16; /* this mode is mandatory */
7093
7094 if (cap & CAP_CRC_14B)
7095 port_ltp |= PORT_LTP_CRC_MODE_14;
7096 if (cap & CAP_CRC_48B)
7097 port_ltp |= PORT_LTP_CRC_MODE_48;
7098 if (cap & CAP_CRC_12B_16B_PER_LANE)
7099 port_ltp |= PORT_LTP_CRC_MODE_PER_LANE;
7100
7101 return port_ltp;
7102}
7103
7104/*
7105 * Convert an OPA Port LTP mask to capability mask
7106 */
7107int port_ltp_to_cap(int port_ltp)
7108{
7109 int cap_mask = 0;
7110
7111 if (port_ltp & PORT_LTP_CRC_MODE_14)
7112 cap_mask |= CAP_CRC_14B;
7113 if (port_ltp & PORT_LTP_CRC_MODE_48)
7114 cap_mask |= CAP_CRC_48B;
7115 if (port_ltp & PORT_LTP_CRC_MODE_PER_LANE)
7116 cap_mask |= CAP_CRC_12B_16B_PER_LANE;
7117
7118 return cap_mask;
7119}
7120
7121/*
7122 * Convert a single DC LCB CRC mode to an OPA Port LTP mask.
7123 */
7124static int lcb_to_port_ltp(int lcb_crc)
7125{
7126 int port_ltp = 0;
7127
7128 if (lcb_crc == LCB_CRC_12B_16B_PER_LANE)
7129 port_ltp = PORT_LTP_CRC_MODE_PER_LANE;
7130 else if (lcb_crc == LCB_CRC_48B)
7131 port_ltp = PORT_LTP_CRC_MODE_48;
7132 else if (lcb_crc == LCB_CRC_14B)
7133 port_ltp = PORT_LTP_CRC_MODE_14;
7134 else
7135 port_ltp = PORT_LTP_CRC_MODE_16;
7136
7137 return port_ltp;
7138}
7139
7140/*
7141 * Our neighbor has indicated that we are allowed to act as a fabric
7142 * manager, so place the full management partition key in the second
7143 * (0-based) pkey array position (see OPAv1, section 20.2.2.6.8). Note
7144 * that we should already have the limited management partition key in
7145 * array element 1, and also that the port is not yet up when
7146 * add_full_mgmt_pkey() is invoked.
7147 */
7148static void add_full_mgmt_pkey(struct hfi1_pportdata *ppd)
7149{
7150 struct hfi1_devdata *dd = ppd->dd;
7151
a498fbcd 7152 /* Sanity check - ppd->pkeys[2] should be 0, or already initialized */
8764522e
DL		 7153 if (!((ppd->pkeys[2] == 0) || (ppd->pkeys[2] == FULL_MGMT_P_KEY)))
7154 dd_dev_warn(dd, "%s pkey[2] already set to 0x%x, resetting it to 0x%x\n",
7155 __func__, ppd->pkeys[2], FULL_MGMT_P_KEY);
77241056
MM		 7156 ppd->pkeys[2] = FULL_MGMT_P_KEY;
7157 (void)hfi1_set_ib_cfg(ppd, HFI1_IB_CFG_PKEYS, 0);
34d351f8 7158 hfi1_event_pkey_change(ppd->dd, ppd->port);
77241056
MM		 7159}
7160
3ec5fa28 7161static void clear_full_mgmt_pkey(struct hfi1_pportdata *ppd)
ce8b2fd0 7162{
3ec5fa28
SS		 7163 if (ppd->pkeys[2] != 0) {
7164 ppd->pkeys[2] = 0;
7165 (void)hfi1_set_ib_cfg(ppd, HFI1_IB_CFG_PKEYS, 0);
34d351f8 7166 hfi1_event_pkey_change(ppd->dd, ppd->port);
3ec5fa28 7167 }
ce8b2fd0
SS		 7168}
7169
77241056
MM		 7170/*
7171 * Convert the given link width to the OPA link width bitmask.
7172 */
7173static u16 link_width_to_bits(struct hfi1_devdata *dd, u16 width)
7174{
7175 switch (width) {
7176 case 0:
7177 /*
7178 * Simulator and quick linkup do not set the width.
7179 * Just set it to 4x without complaint.
7180 */
7181 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR || quick_linkup)
7182 return OPA_LINK_WIDTH_4X;
7183 return 0; /* no lanes up */
7184 case 1: return OPA_LINK_WIDTH_1X;
7185 case 2: return OPA_LINK_WIDTH_2X;
7186 case 3: return OPA_LINK_WIDTH_3X;
7187 default:
7188 dd_dev_info(dd, "%s: invalid width %d, using 4\n",
17fb4f29 7189 __func__, width);
77241056
MM		 7190 /* fall through */
7191 case 4: return OPA_LINK_WIDTH_4X;
7192 }
7193}
7194
7195/*
7196 * Do a population count on the bottom nibble.
7197 */
7198static const u8 bit_counts[16] = {
7199 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4
7200};
f4d507cd 7201
77241056
MM		 7202static inline u8 nibble_to_count(u8 nibble)
7203{
7204 return bit_counts[nibble & 0xf];
7205}
7206
7207/*
7208 * Read the active lane information from the 8051 registers and return
7209 * their widths.
7210 *
7211 * Active lane information is found in these 8051 registers:
7212 * enable_lane_tx
7213 * enable_lane_rx
7214 */
7215static void get_link_widths(struct hfi1_devdata *dd, u16 *tx_width,
7216 u16 *rx_width)
7217{
7218 u16 tx, rx;
7219 u8 enable_lane_rx;
7220 u8 enable_lane_tx;
7221 u8 tx_polarity_inversion;
7222 u8 rx_polarity_inversion;
7223 u8 max_rate;
7224
7225 /* read the active lanes */
7226 read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion,
17fb4f29 7227 &rx_polarity_inversion, &max_rate);
77241056
MM		 7228 read_local_lni(dd, &enable_lane_rx);
7229
7230 /* convert to counts */
7231 tx = nibble_to_count(enable_lane_tx);
7232 rx = nibble_to_count(enable_lane_rx);
7233
7234 /*
7235 * Set link_speed_active here, overriding what was set in
7236 * handle_verify_cap(). The ASIC 8051 firmware does not correctly
7237 * set the max_rate field in handle_verify_cap until v0.19.
7238 */
d0d236ea 7239 if ((dd->icode == ICODE_RTL_SILICON) &&
5e6e9424 7240 (dd->dc8051_ver < dc8051_ver(0, 19, 0))) {
77241056
MM		 7241 /* max_rate: 0 = 12.5G, 1 = 25G */
7242 switch (max_rate) {
7243 case 0:
7244 dd->pport[0].link_speed_active = OPA_LINK_SPEED_12_5G;
7245 break;
7246 default:
7247 dd_dev_err(dd,
17fb4f29
JJ		 7248 "%s: unexpected max rate %d, using 25Gb\n",
7249 __func__, (int)max_rate);
77241056
MM		 7250 /* fall through */
7251 case 1:
7252 dd->pport[0].link_speed_active = OPA_LINK_SPEED_25G;
7253 break;
7254 }
7255 }
7256
7257 dd_dev_info(dd,
17fb4f29
JJ		 7258 "Fabric active lanes (width): tx 0x%x (%d), rx 0x%x (%d)\n",
7259 enable_lane_tx, tx, enable_lane_rx, rx);
77241056
MM		 7260 *tx_width = link_width_to_bits(dd, tx);
7261 *rx_width = link_width_to_bits(dd, rx);
7262}
7263
7264/*
7265 * Read verify_cap_local_fm_link_width[1] to obtain the link widths.
7266 * Valid after the end of VerifyCap and during LinkUp. Does not change
7267 * after link up. I.e. look elsewhere for downgrade information.
7268 *
7269 * Bits are:
7270 * + bits [7:4] contain the number of active transmitters
7271 * + bits [3:0] contain the number of active receivers
7272 * These are numbers 1 through 4 and can be different values if the
7273 * link is asymmetric.
7274 *
7275 * verify_cap_local_fm_link_width[0] retains its original value.
7276 */
7277static void get_linkup_widths(struct hfi1_devdata *dd, u16 *tx_width,
7278 u16 *rx_width)
7279{
7280 u16 widths, tx, rx;
7281 u8 misc_bits, local_flags;
7282 u16 active_tx, active_rx;
7283
7284 read_vc_local_link_width(dd, &misc_bits, &local_flags, &widths);
7285 tx = widths >> 12;
7286 rx = (widths >> 8) & 0xf;
7287
7288 *tx_width = link_width_to_bits(dd, tx);
7289 *rx_width = link_width_to_bits(dd, rx);
7290
7291 /* print the active widths */
7292 get_link_widths(dd, &active_tx, &active_rx);
7293}
7294
7295/*
7296 * Set ppd->link_width_active and ppd->link_width_downgrade_active using
7297 * hardware information when the link first comes up.
7298 *
7299 * The link width is not available until after VerifyCap.AllFramesReceived
7300 * (the trigger for handle_verify_cap), so this is outside that routine
7301 * and should be called when the 8051 signals linkup.
7302 */
7303void get_linkup_link_widths(struct hfi1_pportdata *ppd)
7304{
7305 u16 tx_width, rx_width;
7306
7307 /* get end-of-LNI link widths */
7308 get_linkup_widths(ppd->dd, &tx_width, &rx_width);
7309
7310 /* use tx_width as the link is supposed to be symmetric on link up */
7311 ppd->link_width_active = tx_width;
7312 /* link width downgrade active (LWD.A) starts out matching LW.A */
7313 ppd->link_width_downgrade_tx_active = ppd->link_width_active;
7314 ppd->link_width_downgrade_rx_active = ppd->link_width_active;
7315 /* per OPA spec, on link up LWD.E resets to LWD.S */
7316 ppd->link_width_downgrade_enabled = ppd->link_width_downgrade_supported;
7317 /* cache the active egress rate (units {10^6 bits/sec]) */
7318 ppd->current_egress_rate = active_egress_rate(ppd);
7319}
7320
7321/*
7322 * Handle a verify capabilities interrupt from the 8051.
7323 *
7324 * This is a work-queue function outside of the interrupt.
7325 */
7326void handle_verify_cap(struct work_struct *work)
7327{
7328 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7329 link_vc_work);
7330 struct hfi1_devdata *dd = ppd->dd;
7331 u64 reg;
7332 u8 power_management;
7333 u8 continious;
7334 u8 vcu;
7335 u8 vau;
7336 u8 z;
7337 u16 vl15buf;
7338 u16 link_widths;
7339 u16 crc_mask;
7340 u16 crc_val;
7341 u16 device_id;
7342 u16 active_tx, active_rx;
7343 u8 partner_supported_crc;
7344 u8 remote_tx_rate;
7345 u8 device_rev;
7346
7347 set_link_state(ppd, HLS_VERIFY_CAP);
7348
7349 lcb_shutdown(dd, 0);
7350 adjust_lcb_for_fpga_serdes(dd);
7351
77241056 7352 read_vc_remote_phy(dd, &power_management, &continious);
17fb4f29
JJ		 7353 read_vc_remote_fabric(dd, &vau, &z, &vcu, &vl15buf,
7354 &partner_supported_crc);
77241056
MM		 7355 read_vc_remote_link_width(dd, &remote_tx_rate, &link_widths);
7356 read_remote_device_id(dd, &device_id, &device_rev);
7357 /*
7358 * And the 'MgmtAllowed' information, which is exchanged during
7359 * LNI, is also be available at this point.
7360 */
7361 read_mgmt_allowed(dd, &ppd->mgmt_allowed);
7362 /* print the active widths */
7363 get_link_widths(dd, &active_tx, &active_rx);
7364 dd_dev_info(dd,
17fb4f29
JJ		 7365 "Peer PHY: power management 0x%x, continuous updates 0x%x\n",
7366 (int)power_management, (int)continious);
77241056 7367 dd_dev_info(dd,
17fb4f29
JJ		 7368 "Peer Fabric: vAU %d, Z %d, vCU %d, vl15 credits 0x%x, CRC sizes 0x%x\n",
7369 (int)vau, (int)z, (int)vcu, (int)vl15buf,
7370 (int)partner_supported_crc);
77241056 7371 dd_dev_info(dd, "Peer Link Width: tx rate 0x%x, widths 0x%x\n",
17fb4f29 7372 (u32)remote_tx_rate, (u32)link_widths);
77241056 7373 dd_dev_info(dd, "Peer Device ID: 0x%04x, Revision 0x%02x\n",
17fb4f29 7374 (u32)device_id, (u32)device_rev);
77241056
MM		 7375 /*
7376 * The peer vAU value just read is the peer receiver value. HFI does
7377 * not support a transmit vAU of 0 (AU == 8). We advertised that
7378 * with Z=1 in the fabric capabilities sent to the peer. The peer
7379 * will see our Z=1, and, if it advertised a vAU of 0, will move its
7380 * receive to vAU of 1 (AU == 16). Do the same here. We do not care
7381 * about the peer Z value - our sent vAU is 3 (hardwired) and is not
7382 * subject to the Z value exception.
7383 */
7384 if (vau == 0)
7385 vau = 1;
b3e6b4bd
BJ		 7386 set_up_vau(dd, vau);
7387
7388 /*
7389 * Set VL15 credits to 0 in global credit register. Cache remote VL15
7390 * credits value and wait for link-up interrupt ot set it.
7391 */
7392 set_up_vl15(dd, 0);
7393 dd->vl15buf_cached = vl15buf;
77241056
MM		 7394
7395 /* set up the LCB CRC mode */
7396 crc_mask = ppd->port_crc_mode_enabled & partner_supported_crc;
7397
7398 /* order is important: use the lowest bit in common */
7399 if (crc_mask & CAP_CRC_14B)
7400 crc_val = LCB_CRC_14B;
7401 else if (crc_mask & CAP_CRC_48B)
7402 crc_val = LCB_CRC_48B;
7403 else if (crc_mask & CAP_CRC_12B_16B_PER_LANE)
7404 crc_val = LCB_CRC_12B_16B_PER_LANE;
7405 else
7406 crc_val = LCB_CRC_16B;
7407
7408 dd_dev_info(dd, "Final LCB CRC mode: %d\n", (int)crc_val);
7409 write_csr(dd, DC_LCB_CFG_CRC_MODE,
7410 (u64)crc_val << DC_LCB_CFG_CRC_MODE_TX_VAL_SHIFT);
7411
7412 /* set (14b only) or clear sideband credit */
7413 reg = read_csr(dd, SEND_CM_CTRL);
7414 if (crc_val == LCB_CRC_14B && crc_14b_sideband) {
7415 write_csr(dd, SEND_CM_CTRL,
17fb4f29 7416 reg | SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK);
77241056
MM		 7417 } else {
7418 write_csr(dd, SEND_CM_CTRL,
17fb4f29 7419 reg & ~SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK);
77241056
MM		 7420 }
7421
7422 ppd->link_speed_active = 0; /* invalid value */
5e6e9424 7423 if (dd->dc8051_ver < dc8051_ver(0, 20, 0)) {
77241056
MM		 7424 /* remote_tx_rate: 0 = 12.5G, 1 = 25G */
7425 switch (remote_tx_rate) {
7426 case 0:
7427 ppd->link_speed_active = OPA_LINK_SPEED_12_5G;
7428 break;
7429 case 1:
7430 ppd->link_speed_active = OPA_LINK_SPEED_25G;
7431 break;
7432 }
7433 } else {
7434 /* actual rate is highest bit of the ANDed rates */
7435 u8 rate = remote_tx_rate & ppd->local_tx_rate;
7436
7437 if (rate & 2)
7438 ppd->link_speed_active = OPA_LINK_SPEED_25G;
7439 else if (rate & 1)
7440 ppd->link_speed_active = OPA_LINK_SPEED_12_5G;
7441 }
7442 if (ppd->link_speed_active == 0) {
7443 dd_dev_err(dd, "%s: unexpected remote tx rate %d, using 25Gb\n",
17fb4f29 7444 __func__, (int)remote_tx_rate);
77241056
MM		 7445 ppd->link_speed_active = OPA_LINK_SPEED_25G;
7446 }
7447
7448 /*
7449 * Cache the values of the supported, enabled, and active
7450 * LTP CRC modes to return in 'portinfo' queries. But the bit
7451 * flags that are returned in the portinfo query differ from
7452 * what's in the link_crc_mask, crc_sizes, and crc_val
7453 * variables. Convert these here.
7454 */
7455 ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8;
7456 /* supported crc modes */
7457 ppd->port_ltp_crc_mode |=
7458 cap_to_port_ltp(ppd->port_crc_mode_enabled) << 4;
7459 /* enabled crc modes */
7460 ppd->port_ltp_crc_mode |= lcb_to_port_ltp(crc_val);
7461 /* active crc mode */
7462
7463 /* set up the remote credit return table */
7464 assign_remote_cm_au_table(dd, vcu);
7465
7466 /*
7467 * The LCB is reset on entry to handle_verify_cap(), so this must
7468 * be applied on every link up.
7469 *
7470 * Adjust LCB error kill enable to kill the link if
7471 * these RBUF errors are seen:
7472 * REPLAY_BUF_MBE_SMASK
7473 * FLIT_INPUT_BUF_MBE_SMASK
7474 */
995deafa 7475 if (is_ax(dd)) { /* fixed in B0 */
77241056
MM		 7476 reg = read_csr(dd, DC_LCB_CFG_LINK_KILL_EN);
7477 reg |= DC_LCB_CFG_LINK_KILL_EN_REPLAY_BUF_MBE_SMASK
7478 | DC_LCB_CFG_LINK_KILL_EN_FLIT_INPUT_BUF_MBE_SMASK;
7479 write_csr(dd, DC_LCB_CFG_LINK_KILL_EN, reg);
7480 }
7481
7482 /* pull LCB fifos out of reset - all fifo clocks must be stable */
7483 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
7484
7485 /* give 8051 access to the LCB CSRs */
7486 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
7487 set_8051_lcb_access(dd);
7488
77241056
MM		 7489 if (ppd->mgmt_allowed)
7490 add_full_mgmt_pkey(ppd);
7491
7492 /* tell the 8051 to go to LinkUp */
7493 set_link_state(ppd, HLS_GOING_UP);
7494}
7495
7496/*
7497 * Apply the link width downgrade enabled policy against the current active
7498 * link widths.
7499 *
7500 * Called when the enabled policy changes or the active link widths change.
7501 */
7502void apply_link_downgrade_policy(struct hfi1_pportdata *ppd, int refresh_widths)
7503{
77241056 7504 int do_bounce = 0;
323fd785
DL		 7505 int tries;
7506 u16 lwde;
77241056
MM		 7507 u16 tx, rx;
7508
323fd785
DL		 7509 /* use the hls lock to avoid a race with actual link up */
7510 tries = 0;
7511retry:
77241056
MM		 7512 mutex_lock(&ppd->hls_lock);
7513 /* only apply if the link is up */
0c7f77af 7514 if (ppd->host_link_state & HLS_DOWN) {
323fd785
DL		 7515 /* still going up..wait and retry */
7516 if (ppd->host_link_state & HLS_GOING_UP) {
7517 if (++tries < 1000) {
7518 mutex_unlock(&ppd->hls_lock);
7519 usleep_range(100, 120); /* arbitrary */
7520 goto retry;
7521 }
7522 dd_dev_err(ppd->dd,
7523 "%s: giving up waiting for link state change\n",
7524 __func__);
7525 }
7526 goto done;
7527 }
7528
7529 lwde = ppd->link_width_downgrade_enabled;
77241056
MM		 7530
7531 if (refresh_widths) {
7532 get_link_widths(ppd->dd, &tx, &rx);
7533 ppd->link_width_downgrade_tx_active = tx;
7534 ppd->link_width_downgrade_rx_active = rx;
7535 }
7536
f9b5635c
DL		 7537 if (ppd->link_width_downgrade_tx_active == 0 ||
7538 ppd->link_width_downgrade_rx_active == 0) {
7539 /* the 8051 reported a dead link as a downgrade */
7540 dd_dev_err(ppd->dd, "Link downgrade is really a link down, ignoring\n");
7541 } else if (lwde == 0) {
77241056
MM		 7542 /* downgrade is disabled */
7543
7544 /* bounce if not at starting active width */
7545 if ((ppd->link_width_active !=
17fb4f29
JJ		 7546 ppd->link_width_downgrade_tx_active) ||
7547 (ppd->link_width_active !=
7548 ppd->link_width_downgrade_rx_active)) {
77241056 7549 dd_dev_err(ppd->dd,
17fb4f29 7550 "Link downgrade is disabled and link has downgraded, downing link\n");
77241056 7551 dd_dev_err(ppd->dd,
17fb4f29
JJ		 7552 " original 0x%x, tx active 0x%x, rx active 0x%x\n",
7553 ppd->link_width_active,
7554 ppd->link_width_downgrade_tx_active,
7555 ppd->link_width_downgrade_rx_active);
77241056
MM		 7556 do_bounce = 1;
7557 }
d0d236ea
JJ		 7558 } else if ((lwde & ppd->link_width_downgrade_tx_active) == 0 ||
7559 (lwde & ppd->link_width_downgrade_rx_active) == 0) {
77241056
MM		 7560 /* Tx or Rx is outside the enabled policy */
7561 dd_dev_err(ppd->dd,
17fb4f29 7562 "Link is outside of downgrade allowed, downing link\n");
77241056 7563 dd_dev_err(ppd->dd,
17fb4f29
JJ		 7564 " enabled 0x%x, tx active 0x%x, rx active 0x%x\n",
7565 lwde, ppd->link_width_downgrade_tx_active,
7566 ppd->link_width_downgrade_rx_active);
77241056
MM		 7567 do_bounce = 1;
7568 }
7569
323fd785
DL		 7570done:
7571 mutex_unlock(&ppd->hls_lock);
7572
77241056
MM		 7573 if (do_bounce) {
7574 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_WIDTH_POLICY, 0,
17fb4f29 7575 OPA_LINKDOWN_REASON_WIDTH_POLICY);
77241056
MM		 7576 set_link_state(ppd, HLS_DN_OFFLINE);
7577 start_link(ppd);
7578 }
7579}
7580
7581/*
7582 * Handle a link downgrade interrupt from the 8051.
7583 *
7584 * This is a work-queue function outside of the interrupt.
7585 */
7586void handle_link_downgrade(struct work_struct *work)
7587{
7588 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7589 link_downgrade_work);
7590
7591 dd_dev_info(ppd->dd, "8051: Link width downgrade\n");
7592 apply_link_downgrade_policy(ppd, 1);
7593}
7594
7595static char *dcc_err_string(char *buf, int buf_len, u64 flags)
7596{
7597 return flag_string(buf, buf_len, flags, dcc_err_flags,
7598 ARRAY_SIZE(dcc_err_flags));
7599}
7600
7601static char *lcb_err_string(char *buf, int buf_len, u64 flags)
7602{
7603 return flag_string(buf, buf_len, flags, lcb_err_flags,
7604 ARRAY_SIZE(lcb_err_flags));
7605}
7606
7607static char *dc8051_err_string(char *buf, int buf_len, u64 flags)
7608{
7609 return flag_string(buf, buf_len, flags, dc8051_err_flags,
7610 ARRAY_SIZE(dc8051_err_flags));
7611}
7612
7613static char *dc8051_info_err_string(char *buf, int buf_len, u64 flags)
7614{
7615 return flag_string(buf, buf_len, flags, dc8051_info_err_flags,
7616 ARRAY_SIZE(dc8051_info_err_flags));
7617}
7618
7619static char *dc8051_info_host_msg_string(char *buf, int buf_len, u64 flags)
7620{
7621 return flag_string(buf, buf_len, flags, dc8051_info_host_msg_flags,
7622 ARRAY_SIZE(dc8051_info_host_msg_flags));
7623}
7624
7625static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg)
7626{
7627 struct hfi1_pportdata *ppd = dd->pport;
7628 u64 info, err, host_msg;
7629 int queue_link_down = 0;
7630 char buf[96];
7631
7632 /* look at the flags */
7633 if (reg & DC_DC8051_ERR_FLG_SET_BY_8051_SMASK) {
7634 /* 8051 information set by firmware */
7635 /* read DC8051_DBG_ERR_INFO_SET_BY_8051 for details */
7636 info = read_csr(dd, DC_DC8051_DBG_ERR_INFO_SET_BY_8051);
7637 err = (info >> DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_SHIFT)
7638 & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_MASK;
7639 host_msg = (info >>
7640 DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_SHIFT)
7641 & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_MASK;
7642
7643 /*
7644 * Handle error flags.
7645 */
7646 if (err & FAILED_LNI) {
7647 /*
7648 * LNI error indications are cleared by the 8051
7649 * only when starting polling. Only pay attention
7650 * to them when in the states that occur during
7651 * LNI.
7652 */
7653 if (ppd->host_link_state
7654 & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) {
7655 queue_link_down = 1;
7656 dd_dev_info(dd, "Link error: %s\n",
17fb4f29
JJ		 7657 dc8051_info_err_string(buf,
7658 sizeof(buf),
7659 err &
7660 FAILED_LNI));
77241056
MM		 7661 }
7662 err &= ~(u64)FAILED_LNI;
7663 }
6d014530
DL		 7664 /* unknown frames can happen durning LNI, just count */
7665 if (err & UNKNOWN_FRAME) {
7666 ppd->unknown_frame_count++;
7667 err &= ~(u64)UNKNOWN_FRAME;
7668 }
77241056
MM		 7669 if (err) {
7670 /* report remaining errors, but do not do anything */
7671 dd_dev_err(dd, "8051 info error: %s\n",
17fb4f29
JJ		 7672 dc8051_info_err_string(buf, sizeof(buf),
7673 err));
77241056
MM		 7674 }
7675
7676 /*
7677 * Handle host message flags.
7678 */
7679 if (host_msg & HOST_REQ_DONE) {
7680 /*
7681 * Presently, the driver does a busy wait for
7682 * host requests to complete. This is only an
7683 * informational message.
7684 * NOTE: The 8051 clears the host message
7685 * information *on the next 8051 command*.
7686 * Therefore, when linkup is achieved,
7687 * this flag will still be set.
7688 */
7689 host_msg &= ~(u64)HOST_REQ_DONE;
7690 }
7691 if (host_msg & BC_SMA_MSG) {
7692 queue_work(ppd->hfi1_wq, &ppd->sma_message_work);
7693 host_msg &= ~(u64)BC_SMA_MSG;
7694 }
7695 if (host_msg & LINKUP_ACHIEVED) {
7696 dd_dev_info(dd, "8051: Link up\n");
7697 queue_work(ppd->hfi1_wq, &ppd->link_up_work);
7698 host_msg &= ~(u64)LINKUP_ACHIEVED;
7699 }
7700 if (host_msg & EXT_DEVICE_CFG_REQ) {
145dd2b3 7701 handle_8051_request(ppd);
77241056
MM		 7702 host_msg &= ~(u64)EXT_DEVICE_CFG_REQ;
7703 }
7704 if (host_msg & VERIFY_CAP_FRAME) {
7705 queue_work(ppd->hfi1_wq, &ppd->link_vc_work);
7706 host_msg &= ~(u64)VERIFY_CAP_FRAME;
7707 }
7708 if (host_msg & LINK_GOING_DOWN) {
7709 const char *extra = "";
7710 /* no downgrade action needed if going down */
7711 if (host_msg & LINK_WIDTH_DOWNGRADED) {
7712 host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED;
7713 extra = " (ignoring downgrade)";
7714 }
7715 dd_dev_info(dd, "8051: Link down%s\n", extra);
7716 queue_link_down = 1;
7717 host_msg &= ~(u64)LINK_GOING_DOWN;
7718 }
7719 if (host_msg & LINK_WIDTH_DOWNGRADED) {
7720 queue_work(ppd->hfi1_wq, &ppd->link_downgrade_work);
7721 host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED;
7722 }
7723 if (host_msg) {
7724 /* report remaining messages, but do not do anything */
7725 dd_dev_info(dd, "8051 info host message: %s\n",
17fb4f29
JJ		 7726 dc8051_info_host_msg_string(buf,
7727 sizeof(buf),
7728 host_msg));
77241056
MM		 7729 }
7730
7731 reg &= ~DC_DC8051_ERR_FLG_SET_BY_8051_SMASK;
7732 }
7733 if (reg & DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK) {
7734 /*
7735 * Lost the 8051 heartbeat. If this happens, we
7736 * receive constant interrupts about it. Disable
7737 * the interrupt after the first.
7738 */
7739 dd_dev_err(dd, "Lost 8051 heartbeat\n");
7740 write_csr(dd, DC_DC8051_ERR_EN,
17fb4f29
JJ		 7741 read_csr(dd, DC_DC8051_ERR_EN) &
7742 ~DC_DC8051_ERR_EN_LOST_8051_HEART_BEAT_SMASK);
77241056
MM		 7743
7744 reg &= ~DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK;
7745 }
7746 if (reg) {
7747 /* report the error, but do not do anything */
7748 dd_dev_err(dd, "8051 error: %s\n",
17fb4f29 7749 dc8051_err_string(buf, sizeof(buf), reg));
77241056
MM		 7750 }
7751
7752 if (queue_link_down) {
4d114fdd
JJ		 7753 /*
7754 * if the link is already going down or disabled, do not
7755 * queue another
7756 */
d0d236ea
JJ		 7757 if ((ppd->host_link_state &
7758 (HLS_GOING_OFFLINE | HLS_LINK_COOLDOWN)) ||
7759 ppd->link_enabled == 0) {
77241056 7760 dd_dev_info(dd, "%s: not queuing link down\n",
17fb4f29 7761 __func__);
77241056
MM		 7762 } else {
7763 queue_work(ppd->hfi1_wq, &ppd->link_down_work);
7764 }
7765 }
7766}
7767
7768static const char * const fm_config_txt[] = {
7769[0] =
7770 "BadHeadDist: Distance violation between two head flits",
7771[1] =
7772 "BadTailDist: Distance violation between two tail flits",
7773[2] =
7774 "BadCtrlDist: Distance violation between two credit control flits",
7775[3] =
7776 "BadCrdAck: Credits return for unsupported VL",
7777[4] =
7778 "UnsupportedVLMarker: Received VL Marker",
7779[5] =
7780 "BadPreempt: Exceeded the preemption nesting level",
7781[6] =
7782 "BadControlFlit: Received unsupported control flit",
7783/* no 7 */
7784[8] =
7785 "UnsupportedVLMarker: Received VL Marker for unconfigured or disabled VL",
7786};
7787
7788static const char * const port_rcv_txt[] = {
7789[1] =
7790 "BadPktLen: Illegal PktLen",
7791[2] =
7792 "PktLenTooLong: Packet longer than PktLen",
7793[3] =
7794 "PktLenTooShort: Packet shorter than PktLen",
7795[4] =
7796 "BadSLID: Illegal SLID (0, using multicast as SLID, does not include security validation of SLID)",
7797[5] =
7798 "BadDLID: Illegal DLID (0, doesn't match HFI)",
7799[6] =
7800 "BadL2: Illegal L2 opcode",
7801[7] =
7802 "BadSC: Unsupported SC",
7803[9] =
7804 "BadRC: Illegal RC",
7805[11] =
7806 "PreemptError: Preempting with same VL",
7807[12] =
7808 "PreemptVL15: Preempting a VL15 packet",
7809};
7810
7811#define OPA_LDR_FMCONFIG_OFFSET 16
7812#define OPA_LDR_PORTRCV_OFFSET 0
7813static void handle_dcc_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
7814{
7815 u64 info, hdr0, hdr1;
7816 const char *extra;
7817 char buf[96];
7818 struct hfi1_pportdata *ppd = dd->pport;
7819 u8 lcl_reason = 0;
7820 int do_bounce = 0;
7821
7822 if (reg & DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK) {
7823 if (!(dd->err_info_uncorrectable & OPA_EI_STATUS_SMASK)) {
7824 info = read_csr(dd, DCC_ERR_INFO_UNCORRECTABLE);
7825 dd->err_info_uncorrectable = info & OPA_EI_CODE_SMASK;
7826 /* set status bit */
7827 dd->err_info_uncorrectable |= OPA_EI_STATUS_SMASK;
7828 }
7829 reg &= ~DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK;
7830 }
7831
7832 if (reg & DCC_ERR_FLG_LINK_ERR_SMASK) {
7833 struct hfi1_pportdata *ppd = dd->pport;
7834 /* this counter saturates at (2^32) - 1 */
7835 if (ppd->link_downed < (u32)UINT_MAX)
7836 ppd->link_downed++;
7837 reg &= ~DCC_ERR_FLG_LINK_ERR_SMASK;
7838 }
7839
7840 if (reg & DCC_ERR_FLG_FMCONFIG_ERR_SMASK) {
7841 u8 reason_valid = 1;
7842
7843 info = read_csr(dd, DCC_ERR_INFO_FMCONFIG);
7844 if (!(dd->err_info_fmconfig & OPA_EI_STATUS_SMASK)) {
7845 dd->err_info_fmconfig = info & OPA_EI_CODE_SMASK;
7846 /* set status bit */
7847 dd->err_info_fmconfig |= OPA_EI_STATUS_SMASK;
7848 }
7849 switch (info) {
7850 case 0:
7851 case 1:
7852 case 2:
7853 case 3:
7854 case 4:
7855 case 5:
7856 case 6:
7857 extra = fm_config_txt[info];
7858 break;
7859 case 8:
7860 extra = fm_config_txt[info];
7861 if (ppd->port_error_action &
7862 OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER) {
7863 do_bounce = 1;
7864 /*
7865 * lcl_reason cannot be derived from info
7866 * for this error
7867 */
7868 lcl_reason =
7869 OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER;
7870 }
7871 break;
7872 default:
7873 reason_valid = 0;
7874 snprintf(buf, sizeof(buf), "reserved%lld", info);
7875 extra = buf;
7876 break;
7877 }
7878
7879 if (reason_valid && !do_bounce) {
7880 do_bounce = ppd->port_error_action &
7881 (1 << (OPA_LDR_FMCONFIG_OFFSET + info));
7882 lcl_reason = info + OPA_LINKDOWN_REASON_BAD_HEAD_DIST;
7883 }
7884
7885 /* just report this */
c27aad00
JB		 7886 dd_dev_info_ratelimited(dd, "DCC Error: fmconfig error: %s\n",
7887 extra);
77241056
MM		 7888 reg &= ~DCC_ERR_FLG_FMCONFIG_ERR_SMASK;
7889 }
7890
7891 if (reg & DCC_ERR_FLG_RCVPORT_ERR_SMASK) {
7892 u8 reason_valid = 1;
7893
7894 info = read_csr(dd, DCC_ERR_INFO_PORTRCV);
7895 hdr0 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR0);
7896 hdr1 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR1);
7897 if (!(dd->err_info_rcvport.status_and_code &
7898 OPA_EI_STATUS_SMASK)) {
7899 dd->err_info_rcvport.status_and_code =
7900 info & OPA_EI_CODE_SMASK;
7901 /* set status bit */
7902 dd->err_info_rcvport.status_and_code |=
7903 OPA_EI_STATUS_SMASK;
4d114fdd
JJ		 7904 /*
7905 * save first 2 flits in the packet that caused
7906 * the error
7907 */
48a0cc13
BVA		 7908 dd->err_info_rcvport.packet_flit1 = hdr0;
7909 dd->err_info_rcvport.packet_flit2 = hdr1;
77241056
MM		 7910 }
7911 switch (info) {
7912 case 1:
7913 case 2:
7914 case 3:
7915 case 4:
7916 case 5:
7917 case 6:
7918 case 7:
7919 case 9:
7920 case 11:
7921 case 12:
7922 extra = port_rcv_txt[info];
7923 break;
7924 default:
7925 reason_valid = 0;
7926 snprintf(buf, sizeof(buf), "reserved%lld", info);
7927 extra = buf;
7928 break;
7929 }
7930
7931 if (reason_valid && !do_bounce) {
7932 do_bounce = ppd->port_error_action &
7933 (1 << (OPA_LDR_PORTRCV_OFFSET + info));
7934 lcl_reason = info + OPA_LINKDOWN_REASON_RCV_ERROR_0;
7935 }
7936
7937 /* just report this */
c27aad00
JB		 7938 dd_dev_info_ratelimited(dd, "DCC Error: PortRcv error: %s\n"
7939 " hdr0 0x%llx, hdr1 0x%llx\n",
7940 extra, hdr0, hdr1);
77241056
MM		 7941
7942 reg &= ~DCC_ERR_FLG_RCVPORT_ERR_SMASK;
7943 }
7944
7945 if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK) {
7946 /* informative only */
c27aad00 7947 dd_dev_info_ratelimited(dd, "8051 access to LCB blocked\n");
77241056
MM		 7948 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK;
7949 }
7950 if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK) {
7951 /* informative only */
c27aad00 7952 dd_dev_info_ratelimited(dd, "host access to LCB blocked\n");
77241056
MM		 7953 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK;
7954 }
7955
243d9f43
DH		 7956 if (unlikely(hfi1_dbg_fault_suppress_err(&dd->verbs_dev)))
7957 reg &= ~DCC_ERR_FLG_LATE_EBP_ERR_SMASK;
7958
77241056
MM		 7959 /* report any remaining errors */
7960 if (reg)
c27aad00
JB		 7961 dd_dev_info_ratelimited(dd, "DCC Error: %s\n",
7962 dcc_err_string(buf, sizeof(buf), reg));
77241056
MM		 7963
7964 if (lcl_reason == 0)
7965 lcl_reason = OPA_LINKDOWN_REASON_UNKNOWN;
7966
7967 if (do_bounce) {
c27aad00
JB		 7968 dd_dev_info_ratelimited(dd, "%s: PortErrorAction bounce\n",
7969 __func__);
77241056
MM		 7970 set_link_down_reason(ppd, lcl_reason, 0, lcl_reason);
7971 queue_work(ppd->hfi1_wq, &ppd->link_bounce_work);
7972 }
7973}
7974
7975static void handle_lcb_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
7976{
7977 char buf[96];
7978
7979 dd_dev_info(dd, "LCB Error: %s\n",
17fb4f29 7980 lcb_err_string(buf, sizeof(buf), reg));
77241056
MM		 7981}
7982
7983/*
7984 * CCE block DC interrupt. Source is < 8.
7985 */
7986static void is_dc_int(struct hfi1_devdata *dd, unsigned int source)
7987{
7988 const struct err_reg_info *eri = &dc_errs[source];
7989
7990 if (eri->handler) {
7991 interrupt_clear_down(dd, 0, eri);
7992 } else if (source == 3 /* dc_lbm_int */) {
7993 /*
7994 * This indicates that a parity error has occurred on the
7995 * address/control lines presented to the LBM. The error
7996 * is a single pulse, there is no associated error flag,
7997 * and it is non-maskable. This is because if a parity
7998 * error occurs on the request the request is dropped.
7999 * This should never occur, but it is nice to know if it
8000 * ever does.
8001 */
8002 dd_dev_err(dd, "Parity error in DC LBM block\n");
8003 } else {
8004 dd_dev_err(dd, "Invalid DC interrupt %u\n", source);
8005 }
8006}
8007
8008/*
8009 * TX block send credit interrupt. Source is < 160.
8010 */
8011static void is_send_credit_int(struct hfi1_devdata *dd, unsigned int source)
8012{
8013 sc_group_release_update(dd, source);
8014}
8015
8016/*
8017 * TX block SDMA interrupt. Source is < 48.
8018 *
8019 * SDMA interrupts are grouped by type:
8020 *
8021 * 0 - N-1 = SDma
8022 * N - 2N-1 = SDmaProgress
8023 * 2N - 3N-1 = SDmaIdle
8024 */
8025static void is_sdma_eng_int(struct hfi1_devdata *dd, unsigned int source)
8026{
8027 /* what interrupt */
8028 unsigned int what = source / TXE_NUM_SDMA_ENGINES;
8029 /* which engine */
8030 unsigned int which = source % TXE_NUM_SDMA_ENGINES;
8031
8032#ifdef CONFIG_SDMA_VERBOSITY
8033 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", which,
8034 slashstrip(__FILE__), __LINE__, __func__);
8035 sdma_dumpstate(&dd->per_sdma[which]);
8036#endif
8037
8038 if (likely(what < 3 && which < dd->num_sdma)) {
8039 sdma_engine_interrupt(&dd->per_sdma[which], 1ull << source);
8040 } else {
8041 /* should not happen */
8042 dd_dev_err(dd, "Invalid SDMA interrupt 0x%x\n", source);
8043 }
8044}
8045
8046/*
8047 * RX block receive available interrupt. Source is < 160.
8048 */
8049static void is_rcv_avail_int(struct hfi1_devdata *dd, unsigned int source)
8050{
8051 struct hfi1_ctxtdata *rcd;
8052 char *err_detail;
8053
8054 if (likely(source < dd->num_rcv_contexts)) {
8055 rcd = dd->rcd[source];
8056 if (rcd) {
2280740f
VN		 8057 /* Check for non-user contexts, including vnic */
8058 if ((source < dd->first_dyn_alloc_ctxt) ||
8059 (rcd->sc && (rcd->sc->type == SC_KERNEL)))
f4f30031 8060 rcd->do_interrupt(rcd, 0);
77241056
MM		 8061 else
8062 handle_user_interrupt(rcd);
8063 return; /* OK */
8064 }
8065 /* received an interrupt, but no rcd */
8066 err_detail = "dataless";
8067 } else {
8068 /* received an interrupt, but are not using that context */
8069 err_detail = "out of range";
8070 }
8071 dd_dev_err(dd, "unexpected %s receive available context interrupt %u\n",
17fb4f29 8072 err_detail, source);
77241056
MM		 8073}
8074
8075/*
8076 * RX block receive urgent interrupt. Source is < 160.
8077 */
8078static void is_rcv_urgent_int(struct hfi1_devdata *dd, unsigned int source)
8079{
8080 struct hfi1_ctxtdata *rcd;
8081 char *err_detail;
8082
8083 if (likely(source < dd->num_rcv_contexts)) {
8084 rcd = dd->rcd[source];
8085 if (rcd) {
8086 /* only pay attention to user urgent interrupts */
2280740f
VN		 8087 if ((source >= dd->first_dyn_alloc_ctxt) &&
8088 (!rcd->sc || (rcd->sc->type == SC_USER)))
77241056
MM		 8089 handle_user_interrupt(rcd);
8090 return; /* OK */
8091 }
8092 /* received an interrupt, but no rcd */
8093 err_detail = "dataless";
8094 } else {
8095 /* received an interrupt, but are not using that context */
8096 err_detail = "out of range";
8097 }
8098 dd_dev_err(dd, "unexpected %s receive urgent context interrupt %u\n",
17fb4f29 8099 err_detail, source);
77241056
MM		 8100}
8101
8102/*
8103 * Reserved range interrupt. Should not be called in normal operation.
8104 */
8105static void is_reserved_int(struct hfi1_devdata *dd, unsigned int source)
8106{
8107 char name[64];
8108
8109 dd_dev_err(dd, "unexpected %s interrupt\n",
17fb4f29 8110 is_reserved_name(name, sizeof(name), source));
77241056
MM		 8111}
8112
8113static const struct is_table is_table[] = {
4d114fdd
JJ		 8114/*
8115 * start end
8116 * name func interrupt func
8117 */
77241056
MM		 8118{ IS_GENERAL_ERR_START, IS_GENERAL_ERR_END,
8119 is_misc_err_name, is_misc_err_int },
8120{ IS_SDMAENG_ERR_START, IS_SDMAENG_ERR_END,
8121 is_sdma_eng_err_name, is_sdma_eng_err_int },
8122{ IS_SENDCTXT_ERR_START, IS_SENDCTXT_ERR_END,
8123 is_sendctxt_err_name, is_sendctxt_err_int },
8124{ IS_SDMA_START, IS_SDMA_END,
8125 is_sdma_eng_name, is_sdma_eng_int },
8126{ IS_VARIOUS_START, IS_VARIOUS_END,
8127 is_various_name, is_various_int },
8128{ IS_DC_START, IS_DC_END,
8129 is_dc_name, is_dc_int },
8130{ IS_RCVAVAIL_START, IS_RCVAVAIL_END,
8131 is_rcv_avail_name, is_rcv_avail_int },
8132{ IS_RCVURGENT_START, IS_RCVURGENT_END,
8133 is_rcv_urgent_name, is_rcv_urgent_int },
8134{ IS_SENDCREDIT_START, IS_SENDCREDIT_END,
8135 is_send_credit_name, is_send_credit_int},
8136{ IS_RESERVED_START, IS_RESERVED_END,
8137 is_reserved_name, is_reserved_int},
8138};
8139
8140/*
8141 * Interrupt source interrupt - called when the given source has an interrupt.
8142 * Source is a bit index into an array of 64-bit integers.
8143 */
8144static void is_interrupt(struct hfi1_devdata *dd, unsigned int source)
8145{
8146 const struct is_table *entry;
8147
8148 /* avoids a double compare by walking the table in-order */
8149 for (entry = &is_table[0]; entry->is_name; entry++) {
8150 if (source < entry->end) {
8151 trace_hfi1_interrupt(dd, entry, source);
8152 entry->is_int(dd, source - entry->start);
8153 return;
8154 }
8155 }
8156 /* fell off the end */
8157 dd_dev_err(dd, "invalid interrupt source %u\n", source);
8158}
8159
8160/*
8161 * General interrupt handler. This is able to correctly handle
8162 * all interrupts in case INTx is used.
8163 */
8164static irqreturn_t general_interrupt(int irq, void *data)
8165{
8166 struct hfi1_devdata *dd = data;
8167 u64 regs[CCE_NUM_INT_CSRS];
8168 u32 bit;
8169 int i;
8170
8171 this_cpu_inc(*dd->int_counter);
8172
8173 /* phase 1: scan and clear all handled interrupts */
8174 for (i = 0; i < CCE_NUM_INT_CSRS; i++) {
8175 if (dd->gi_mask[i] == 0) {
8176 regs[i] = 0; /* used later */
8177 continue;
8178 }
8179 regs[i] = read_csr(dd, CCE_INT_STATUS + (8 * i)) &
8180 dd->gi_mask[i];
8181 /* only clear if anything is set */
8182 if (regs[i])
8183 write_csr(dd, CCE_INT_CLEAR + (8 * i), regs[i]);
8184 }
8185
8186 /* phase 2: call the appropriate handler */
8187 for_each_set_bit(bit, (unsigned long *)&regs[0],
17fb4f29 8188 CCE_NUM_INT_CSRS * 64) {
77241056
MM		 8189 is_interrupt(dd, bit);
8190 }
8191
8192 return IRQ_HANDLED;
8193}
8194
8195static irqreturn_t sdma_interrupt(int irq, void *data)
8196{
8197 struct sdma_engine *sde = data;
8198 struct hfi1_devdata *dd = sde->dd;
8199 u64 status;
8200
8201#ifdef CONFIG_SDMA_VERBOSITY
8202 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
8203 slashstrip(__FILE__), __LINE__, __func__);
8204 sdma_dumpstate(sde);
8205#endif
8206
8207 this_cpu_inc(*dd->int_counter);
8208
8209 /* This read_csr is really bad in the hot path */
8210 status = read_csr(dd,
17fb4f29
JJ		 8211 CCE_INT_STATUS + (8 * (IS_SDMA_START / 64)))
8212 & sde->imask;
77241056
MM		 8213 if (likely(status)) {
8214 /* clear the interrupt(s) */
8215 write_csr(dd,
17fb4f29
JJ		 8216 CCE_INT_CLEAR + (8 * (IS_SDMA_START / 64)),
8217 status);
77241056
MM		 8218
8219 /* handle the interrupt(s) */
8220 sdma_engine_interrupt(sde, status);
ee495ada 8221 } else {
77241056 8222 dd_dev_err(dd, "SDMA engine %u interrupt, but no status bits set\n",
17fb4f29 8223 sde->this_idx);
ee495ada 8224 }
77241056
MM		 8225 return IRQ_HANDLED;
8226}
8227
8228/*
ecd42f8d
DL		 8229 * Clear the receive interrupt. Use a read of the interrupt clear CSR
8230 * to insure that the write completed. This does NOT guarantee that
8231 * queued DMA writes to memory from the chip are pushed.
f4f30031
DL		 8232 */
8233static inline void clear_recv_intr(struct hfi1_ctxtdata *rcd)
8234{
8235 struct hfi1_devdata *dd = rcd->dd;
8236 u32 addr = CCE_INT_CLEAR + (8 * rcd->ireg);
8237
8238 mmiowb(); /* make sure everything before is written */
8239 write_csr(dd, addr, rcd->imask);
8240 /* force the above write on the chip and get a value back */
8241 (void)read_csr(dd, addr);
8242}
8243
8244/* force the receive interrupt */
fb9036dd 8245void force_recv_intr(struct hfi1_ctxtdata *rcd)
f4f30031
DL		 8246{
8247 write_csr(rcd->dd, CCE_INT_FORCE + (8 * rcd->ireg), rcd->imask);
8248}
8249
ecd42f8d
DL		 8250/*
8251 * Return non-zero if a packet is present.
8252 *
8253 * This routine is called when rechecking for packets after the RcvAvail
8254 * interrupt has been cleared down. First, do a quick check of memory for
8255 * a packet present. If not found, use an expensive CSR read of the context
8256 * tail to determine the actual tail. The CSR read is necessary because there
8257 * is no method to push pending DMAs to memory other than an interrupt and we
8258 * are trying to determine if we need to force an interrupt.
8259 */
f4f30031
DL		 8260static inline int check_packet_present(struct hfi1_ctxtdata *rcd)
8261{
ecd42f8d
DL		 8262 u32 tail;
8263 int present;
8264
f4f30031 8265 if (!HFI1_CAP_IS_KSET(DMA_RTAIL))
ecd42f8d 8266 present = (rcd->seq_cnt ==
f4f30031 8267 rhf_rcv_seq(rhf_to_cpu(get_rhf_addr(rcd))));
ecd42f8d
DL		 8268 else /* is RDMA rtail */
8269 present = (rcd->head != get_rcvhdrtail(rcd));
8270
8271 if (present)
8272 return 1;
f4f30031 8273
ecd42f8d
DL		 8274 /* fall back to a CSR read, correct indpendent of DMA_RTAIL */
8275 tail = (u32)read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
8276 return rcd->head != tail;
f4f30031
DL		 8277}
8278
8279/*
8280 * Receive packet IRQ handler. This routine expects to be on its own IRQ.
8281 * This routine will try to handle packets immediately (latency), but if
8282 * it finds too many, it will invoke the thread handler (bandwitdh). The
16733b88 8283 * chip receive interrupt is *not* cleared down until this or the thread (if
f4f30031
DL		 8284 * invoked) is finished. The intent is to avoid extra interrupts while we
8285 * are processing packets anyway.
77241056
MM		 8286 */
8287static irqreturn_t receive_context_interrupt(int irq, void *data)
8288{
8289 struct hfi1_ctxtdata *rcd = data;
8290 struct hfi1_devdata *dd = rcd->dd;
f4f30031
DL		 8291 int disposition;
8292 int present;
77241056
MM		 8293
8294 trace_hfi1_receive_interrupt(dd, rcd->ctxt);
8295 this_cpu_inc(*dd->int_counter);
affa48de 8296 aspm_ctx_disable(rcd);
77241056 8297
f4f30031
DL		 8298 /* receive interrupt remains blocked while processing packets */
8299 disposition = rcd->do_interrupt(rcd, 0);
77241056 8300
f4f30031
DL		 8301 /*
8302 * Too many packets were seen while processing packets in this
8303 * IRQ handler. Invoke the handler thread. The receive interrupt
8304 * remains blocked.
8305 */
8306 if (disposition == RCV_PKT_LIMIT)
8307 return IRQ_WAKE_THREAD;
8308
8309 /*
8310 * The packet processor detected no more packets. Clear the receive
8311 * interrupt and recheck for a packet packet that may have arrived
8312 * after the previous check and interrupt clear. If a packet arrived,
8313 * force another interrupt.
8314 */
8315 clear_recv_intr(rcd);
8316 present = check_packet_present(rcd);
8317 if (present)
8318 force_recv_intr(rcd);
8319
8320 return IRQ_HANDLED;
8321}
8322
8323/*
8324 * Receive packet thread handler. This expects to be invoked with the
8325 * receive interrupt still blocked.
8326 */
8327static irqreturn_t receive_context_thread(int irq, void *data)
8328{
8329 struct hfi1_ctxtdata *rcd = data;
8330 int present;
8331
8332 /* receive interrupt is still blocked from the IRQ handler */
8333 (void)rcd->do_interrupt(rcd, 1);
8334
8335 /*
8336 * The packet processor will only return if it detected no more
8337 * packets. Hold IRQs here so we can safely clear the interrupt and
8338 * recheck for a packet that may have arrived after the previous
8339 * check and the interrupt clear. If a packet arrived, force another
8340 * interrupt.
8341 */
8342 local_irq_disable();
8343 clear_recv_intr(rcd);
8344 present = check_packet_present(rcd);
8345 if (present)
8346 force_recv_intr(rcd);
8347 local_irq_enable();
77241056
MM		 8348
8349 return IRQ_HANDLED;
8350}
8351
8352/* ========================================================================= */
8353
8354u32 read_physical_state(struct hfi1_devdata *dd)
8355{
8356 u64 reg;
8357
8358 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE);
8359 return (reg >> DC_DC8051_STS_CUR_STATE_PORT_SHIFT)
8360 & DC_DC8051_STS_CUR_STATE_PORT_MASK;
8361}
8362
fb9036dd 8363u32 read_logical_state(struct hfi1_devdata *dd)
77241056
MM		 8364{
8365 u64 reg;
8366
8367 reg = read_csr(dd, DCC_CFG_PORT_CONFIG);
8368 return (reg >> DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT)
8369 & DCC_CFG_PORT_CONFIG_LINK_STATE_MASK;
8370}
8371
8372static void set_logical_state(struct hfi1_devdata *dd, u32 chip_lstate)
8373{
8374 u64 reg;
8375
8376 reg = read_csr(dd, DCC_CFG_PORT_CONFIG);
8377 /* clear current state, set new state */
8378 reg &= ~DCC_CFG_PORT_CONFIG_LINK_STATE_SMASK;
8379 reg |= (u64)chip_lstate << DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT;
8380 write_csr(dd, DCC_CFG_PORT_CONFIG, reg);
8381}
8382
8383/*
8384 * Use the 8051 to read a LCB CSR.
8385 */
8386static int read_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 *data)
8387{
8388 u32 regno;
8389 int ret;
8390
8391 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) {
8392 if (acquire_lcb_access(dd, 0) == 0) {
8393 *data = read_csr(dd, addr);
8394 release_lcb_access(dd, 0);
8395 return 0;
8396 }
8397 return -EBUSY;
8398 }
8399
8400 /* register is an index of LCB registers: (offset - base) / 8 */
8401 regno = (addr - DC_LCB_CFG_RUN) >> 3;
8402 ret = do_8051_command(dd, HCMD_READ_LCB_CSR, regno, data);
8403 if (ret != HCMD_SUCCESS)
8404 return -EBUSY;
8405 return 0;
8406}
8407
8688426b
MR		 8408/*
8409 * Provide a cache for some of the LCB registers in case the LCB is
8410 * unavailable.
8411 * (The LCB is unavailable in certain link states, for example.)
8412 */
8413struct lcb_datum {
8414 u32 off;
8415 u64 val;
8416};
8417
8418static struct lcb_datum lcb_cache[] = {
8419 { DC_LCB_ERR_INFO_RX_REPLAY_CNT, 0},
8420 { DC_LCB_ERR_INFO_SEQ_CRC_CNT, 0 },
8421 { DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT, 0 },
8422};
8423
8424static void update_lcb_cache(struct hfi1_devdata *dd)
8425{
8426 int i;
8427 int ret;
8428 u64 val;
8429
8430 for (i = 0; i < ARRAY_SIZE(lcb_cache); i++) {
8431 ret = read_lcb_csr(dd, lcb_cache[i].off, &val);
8432
8433 /* Update if we get good data */
8434 if (likely(ret != -EBUSY))
8435 lcb_cache[i].val = val;
8436 }
8437}
8438
8439static int read_lcb_cache(u32 off, u64 *val)
8440{
8441 int i;
8442
8443 for (i = 0; i < ARRAY_SIZE(lcb_cache); i++) {
8444 if (lcb_cache[i].off == off) {
8445 *val = lcb_cache[i].val;
8446 return 0;
8447 }
8448 }
8449
8450 pr_warn("%s bad offset 0x%x\n", __func__, off);
8451 return -1;
8452}
8453
77241056
MM		 8454/*
8455 * Read an LCB CSR. Access may not be in host control, so check.
8456 * Return 0 on success, -EBUSY on failure.
8457 */
8458int read_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 *data)
8459{
8460 struct hfi1_pportdata *ppd = dd->pport;
8461
8462 /* if up, go through the 8051 for the value */
8463 if (ppd->host_link_state & HLS_UP)
8464 return read_lcb_via_8051(dd, addr, data);
8688426b
MR		 8465 /* if going up or down, check the cache, otherwise, no access */
8466 if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE)) {
8467 if (read_lcb_cache(addr, data))
8468 return -EBUSY;
8469 return 0;
8470 }
8471
77241056
MM		 8472 /* otherwise, host has access */
8473 *data = read_csr(dd, addr);
8474 return 0;
8475}
8476
8477/*
8478 * Use the 8051 to write a LCB CSR.
8479 */
8480static int write_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 data)
8481{
3bf40d65
DL		 8482 u32 regno;
8483 int ret;
77241056 8484
3bf40d65 8485 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR ||
5e6e9424 8486 (dd->dc8051_ver < dc8051_ver(0, 20, 0))) {
3bf40d65
DL		 8487 if (acquire_lcb_access(dd, 0) == 0) {
8488 write_csr(dd, addr, data);
8489 release_lcb_access(dd, 0);
8490 return 0;
8491 }
8492 return -EBUSY;
77241056 8493 }
3bf40d65
DL		 8494
8495 /* register is an index of LCB registers: (offset - base) / 8 */
8496 regno = (addr - DC_LCB_CFG_RUN) >> 3;
8497 ret = do_8051_command(dd, HCMD_WRITE_LCB_CSR, regno, &data);
8498 if (ret != HCMD_SUCCESS)
8499 return -EBUSY;
8500 return 0;
77241056
MM		 8501}
8502
8503/*
8504 * Write an LCB CSR. Access may not be in host control, so check.
8505 * Return 0 on success, -EBUSY on failure.
8506 */
8507int write_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 data)
8508{
8509 struct hfi1_pportdata *ppd = dd->pport;
8510
8511 /* if up, go through the 8051 for the value */
8512 if (ppd->host_link_state & HLS_UP)
8513 return write_lcb_via_8051(dd, addr, data);
8514 /* if going up or down, no access */
8515 if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE))
8516 return -EBUSY;
8517 /* otherwise, host has access */
8518 write_csr(dd, addr, data);
8519 return 0;
8520}
8521
8522/*
8523 * Returns:
8524 * < 0 = Linux error, not able to get access
8525 * > 0 = 8051 command RETURN_CODE
8526 */
8527static int do_8051_command(
8528 struct hfi1_devdata *dd,
8529 u32 type,
8530 u64 in_data,
8531 u64 *out_data)
8532{
8533 u64 reg, completed;
8534 int return_code;
77241056
MM		 8535 unsigned long timeout;
8536
8537 hfi1_cdbg(DC8051, "type %d, data 0x%012llx", type, in_data);
8538
22546b74 8539 mutex_lock(&dd->dc8051_lock);
77241056
MM		 8540
8541 /* We can't send any commands to the 8051 if it's in reset */
8542 if (dd->dc_shutdown) {
8543 return_code = -ENODEV;
8544 goto fail;
8545 }
8546
8547 /*
8548 * If an 8051 host command timed out previously, then the 8051 is
8549 * stuck.
8550 *
8551 * On first timeout, attempt to reset and restart the entire DC
8552 * block (including 8051). (Is this too big of a hammer?)
8553 *
8554 * If the 8051 times out a second time, the reset did not bring it
8555 * back to healthy life. In that case, fail any subsequent commands.
8556 */
8557 if (dd->dc8051_timed_out) {
8558 if (dd->dc8051_timed_out > 1) {
8559 dd_dev_err(dd,
8560 "Previous 8051 host command timed out, skipping command %u\n",
8561 type);
8562 return_code = -ENXIO;
8563 goto fail;
8564 }
22546b74
TS		 8565 _dc_shutdown(dd);
8566 _dc_start(dd);
77241056
MM		 8567 }
8568
8569 /*
8570 * If there is no timeout, then the 8051 command interface is
8571 * waiting for a command.
8572 */
8573
3bf40d65
DL		 8574 /*
8575 * When writing a LCB CSR, out_data contains the full value to
8576 * to be written, while in_data contains the relative LCB
8577 * address in 7:0. Do the work here, rather than the caller,
8578 * of distrubting the write data to where it needs to go:
8579 *
8580 * Write data
8581 * 39:00 -> in_data[47:8]
8582 * 47:40 -> DC8051_CFG_EXT_DEV_0.RETURN_CODE
8583 * 63:48 -> DC8051_CFG_EXT_DEV_0.RSP_DATA
8584 */
8585 if (type == HCMD_WRITE_LCB_CSR) {
8586 in_data |= ((*out_data) & 0xffffffffffull) << 8;
00801674
DL		 8587 /* must preserve COMPLETED - it is tied to hardware */
8588 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_0);
8589 reg &= DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK;
8590 reg |= ((((*out_data) >> 40) & 0xff) <<
3bf40d65
DL		 8591 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT)
8592 | ((((*out_data) >> 48) & 0xffff) <<
8593 DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT);
8594 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, reg);
8595 }
8596
77241056
MM		 8597 /*
8598 * Do two writes: the first to stabilize the type and req_data, the
8599 * second to activate.
8600 */
8601 reg = ((u64)type & DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_MASK)
8602 << DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_SHIFT
8603 | (in_data & DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_MASK)
8604 << DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_SHIFT;
8605 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
8606 reg |= DC_DC8051_CFG_HOST_CMD_0_REQ_NEW_SMASK;
8607 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
8608
8609 /* wait for completion, alternate: interrupt */
8610 timeout = jiffies + msecs_to_jiffies(DC8051_COMMAND_TIMEOUT);
8611 while (1) {
8612 reg = read_csr(dd, DC_DC8051_CFG_HOST_CMD_1);
8613 completed = reg & DC_DC8051_CFG_HOST_CMD_1_COMPLETED_SMASK;
8614 if (completed)
8615 break;
8616 if (time_after(jiffies, timeout)) {
8617 dd->dc8051_timed_out++;
8618 dd_dev_err(dd, "8051 host command %u timeout\n", type);
8619 if (out_data)
8620 *out_data = 0;
8621 return_code = -ETIMEDOUT;
8622 goto fail;
8623 }
8624 udelay(2);
8625 }
8626
8627 if (out_data) {
8628 *out_data = (reg >> DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_SHIFT)
8629 & DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_MASK;
8630 if (type == HCMD_READ_LCB_CSR) {
8631 /* top 16 bits are in a different register */
8632 *out_data |= (read_csr(dd, DC_DC8051_CFG_EXT_DEV_1)
8633 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SMASK)
8634 << (48
8635 - DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT);
8636 }
8637 }
8638 return_code = (reg >> DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_SHIFT)
8639 & DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_MASK;
8640 dd->dc8051_timed_out = 0;
8641 /*
8642 * Clear command for next user.
8643 */
8644 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, 0);
8645
8646fail:
22546b74 8647 mutex_unlock(&dd->dc8051_lock);
77241056
MM		 8648 return return_code;
8649}
8650
8651static int set_physical_link_state(struct hfi1_devdata *dd, u64 state)
8652{
8653 return do_8051_command(dd, HCMD_CHANGE_PHY_STATE, state, NULL);
8654}
8655
8ebd4cf1
EH		 8656int load_8051_config(struct hfi1_devdata *dd, u8 field_id,
8657 u8 lane_id, u32 config_data)
77241056
MM		 8658{
8659 u64 data;
8660 int ret;
8661
8662 data = (u64)field_id << LOAD_DATA_FIELD_ID_SHIFT
8663 | (u64)lane_id << LOAD_DATA_LANE_ID_SHIFT
8664 | (u64)config_data << LOAD_DATA_DATA_SHIFT;
8665 ret = do_8051_command(dd, HCMD_LOAD_CONFIG_DATA, data, NULL);
8666 if (ret != HCMD_SUCCESS) {
8667 dd_dev_err(dd,
17fb4f29
JJ		 8668 "load 8051 config: field id %d, lane %d, err %d\n",
8669 (int)field_id, (int)lane_id, ret);
77241056
MM		 8670 }
8671 return ret;
8672}
8673
8674/*
8675 * Read the 8051 firmware "registers". Use the RAM directly. Always
8676 * set the result, even on error.
8677 * Return 0 on success, -errno on failure
8678 */
8ebd4cf1
EH		 8679int read_8051_config(struct hfi1_devdata *dd, u8 field_id, u8 lane_id,
8680 u32 *result)
77241056
MM		 8681{
8682 u64 big_data;
8683 u32 addr;
8684 int ret;
8685
8686 /* address start depends on the lane_id */
8687 if (lane_id < 4)
8688 addr = (4 * NUM_GENERAL_FIELDS)
8689 + (lane_id * 4 * NUM_LANE_FIELDS);
8690 else
8691 addr = 0;
8692 addr += field_id * 4;
8693
8694 /* read is in 8-byte chunks, hardware will truncate the address down */
8695 ret = read_8051_data(dd, addr, 8, &big_data);
8696
8697 if (ret == 0) {
8698 /* extract the 4 bytes we want */
8699 if (addr & 0x4)
8700 *result = (u32)(big_data >> 32);
8701 else
8702 *result = (u32)big_data;
8703 } else {
8704 *result = 0;
8705 dd_dev_err(dd, "%s: direct read failed, lane %d, field %d!\n",
17fb4f29 8706 __func__, lane_id, field_id);
77241056
MM		 8707 }
8708
8709 return ret;
8710}
8711
8712static int write_vc_local_phy(struct hfi1_devdata *dd, u8 power_management,
8713 u8 continuous)
8714{
8715 u32 frame;
8716
8717 frame = continuous << CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT
8718 | power_management << POWER_MANAGEMENT_SHIFT;
8719 return load_8051_config(dd, VERIFY_CAP_LOCAL_PHY,
8720 GENERAL_CONFIG, frame);
8721}
8722
8723static int write_vc_local_fabric(struct hfi1_devdata *dd, u8 vau, u8 z, u8 vcu,
8724 u16 vl15buf, u8 crc_sizes)
8725{
8726 u32 frame;
8727
8728 frame = (u32)vau << VAU_SHIFT
8729 | (u32)z << Z_SHIFT
8730 | (u32)vcu << VCU_SHIFT
8731 | (u32)vl15buf << VL15BUF_SHIFT
8732 | (u32)crc_sizes << CRC_SIZES_SHIFT;
8733 return load_8051_config(dd, VERIFY_CAP_LOCAL_FABRIC,
8734 GENERAL_CONFIG, frame);
8735}
8736
8737static void read_vc_local_link_width(struct hfi1_devdata *dd, u8 *misc_bits,
8738 u8 *flag_bits, u16 *link_widths)
8739{
8740 u32 frame;
8741
8742 read_8051_config(dd, VERIFY_CAP_LOCAL_LINK_WIDTH, GENERAL_CONFIG,
17fb4f29 8743 &frame);
77241056
MM		 8744 *misc_bits = (frame >> MISC_CONFIG_BITS_SHIFT) & MISC_CONFIG_BITS_MASK;
8745 *flag_bits = (frame >> LOCAL_FLAG_BITS_SHIFT) & LOCAL_FLAG_BITS_MASK;
8746 *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK;
8747}
8748
8749static int write_vc_local_link_width(struct hfi1_devdata *dd,
8750 u8 misc_bits,
8751 u8 flag_bits,
8752 u16 link_widths)
8753{
8754 u32 frame;
8755
8756 frame = (u32)misc_bits << MISC_CONFIG_BITS_SHIFT
8757 | (u32)flag_bits << LOCAL_FLAG_BITS_SHIFT
8758 | (u32)link_widths << LINK_WIDTH_SHIFT;
8759 return load_8051_config(dd, VERIFY_CAP_LOCAL_LINK_WIDTH, GENERAL_CONFIG,
8760 frame);
8761}
8762
8763static int write_local_device_id(struct hfi1_devdata *dd, u16 device_id,
8764 u8 device_rev)
8765{
8766 u32 frame;
8767
8768 frame = ((u32)device_id << LOCAL_DEVICE_ID_SHIFT)
8769 | ((u32)device_rev << LOCAL_DEVICE_REV_SHIFT);
8770 return load_8051_config(dd, LOCAL_DEVICE_ID, GENERAL_CONFIG, frame);
8771}
8772
8773static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id,
8774 u8 *device_rev)
8775{
8776 u32 frame;
8777
8778 read_8051_config(dd, REMOTE_DEVICE_ID, GENERAL_CONFIG, &frame);
8779 *device_id = (frame >> REMOTE_DEVICE_ID_SHIFT) & REMOTE_DEVICE_ID_MASK;
8780 *device_rev = (frame >> REMOTE_DEVICE_REV_SHIFT)
8781 & REMOTE_DEVICE_REV_MASK;
8782}
8783
5e6e9424
MR		 8784void read_misc_status(struct hfi1_devdata *dd, u8 *ver_major, u8 *ver_minor,
8785 u8 *ver_patch)
77241056
MM		 8786{
8787 u32 frame;
8788
8789 read_8051_config(dd, MISC_STATUS, GENERAL_CONFIG, &frame);
5e6e9424
MR		 8790 *ver_major = (frame >> STS_FM_VERSION_MAJOR_SHIFT) &
8791 STS_FM_VERSION_MAJOR_MASK;
8792 *ver_minor = (frame >> STS_FM_VERSION_MINOR_SHIFT) &
8793 STS_FM_VERSION_MINOR_MASK;
8794
8795 read_8051_config(dd, VERSION_PATCH, GENERAL_CONFIG, &frame);
8796 *ver_patch = (frame >> STS_FM_VERSION_PATCH_SHIFT) &
8797 STS_FM_VERSION_PATCH_MASK;
77241056
MM		 8798}
8799
8800static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management,
8801 u8 *continuous)
8802{
8803 u32 frame;
8804
8805 read_8051_config(dd, VERIFY_CAP_REMOTE_PHY, GENERAL_CONFIG, &frame);
8806 *power_management = (frame >> POWER_MANAGEMENT_SHIFT)
8807 & POWER_MANAGEMENT_MASK;
8808 *continuous = (frame >> CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT)
8809 & CONTINIOUS_REMOTE_UPDATE_SUPPORT_MASK;
8810}
8811
8812static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z,
8813 u8 *vcu, u16 *vl15buf, u8 *crc_sizes)
8814{
8815 u32 frame;
8816
8817 read_8051_config(dd, VERIFY_CAP_REMOTE_FABRIC, GENERAL_CONFIG, &frame);
8818 *vau = (frame >> VAU_SHIFT) & VAU_MASK;
8819 *z = (frame >> Z_SHIFT) & Z_MASK;
8820 *vcu = (frame >> VCU_SHIFT) & VCU_MASK;
8821 *vl15buf = (frame >> VL15BUF_SHIFT) & VL15BUF_MASK;
8822 *crc_sizes = (frame >> CRC_SIZES_SHIFT) & CRC_SIZES_MASK;
8823}
8824
8825static void read_vc_remote_link_width(struct hfi1_devdata *dd,
8826 u8 *remote_tx_rate,
8827 u16 *link_widths)
8828{
8829 u32 frame;
8830
8831 read_8051_config(dd, VERIFY_CAP_REMOTE_LINK_WIDTH, GENERAL_CONFIG,
17fb4f29 8832 &frame);
77241056
MM		 8833 *remote_tx_rate = (frame >> REMOTE_TX_RATE_SHIFT)
8834 & REMOTE_TX_RATE_MASK;
8835 *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK;
8836}
8837
8838static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx)
8839{
8840 u32 frame;
8841
8842 read_8051_config(dd, LOCAL_LNI_INFO, GENERAL_CONFIG, &frame);
8843 *enable_lane_rx = (frame >> ENABLE_LANE_RX_SHIFT) & ENABLE_LANE_RX_MASK;
8844}
8845
8846static void read_mgmt_allowed(struct hfi1_devdata *dd, u8 *mgmt_allowed)
8847{
8848 u32 frame;
8849
8850 read_8051_config(dd, REMOTE_LNI_INFO, GENERAL_CONFIG, &frame);
8851 *mgmt_allowed = (frame >> MGMT_ALLOWED_SHIFT) & MGMT_ALLOWED_MASK;
8852}
8853
8854static void read_last_local_state(struct hfi1_devdata *dd, u32 *lls)
8855{
8856 read_8051_config(dd, LAST_LOCAL_STATE_COMPLETE, GENERAL_CONFIG, lls);
8857}
8858
8859static void read_last_remote_state(struct hfi1_devdata *dd, u32 *lrs)
8860{
8861 read_8051_config(dd, LAST_REMOTE_STATE_COMPLETE, GENERAL_CONFIG, lrs);
8862}
8863
8864void hfi1_read_link_quality(struct hfi1_devdata *dd, u8 *link_quality)
8865{
8866 u32 frame;
8867 int ret;
8868
8869 *link_quality = 0;
8870 if (dd->pport->host_link_state & HLS_UP) {
8871 ret = read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG,
17fb4f29 8872 &frame);
77241056
MM		 8873 if (ret == 0)
8874 *link_quality = (frame >> LINK_QUALITY_SHIFT)
8875 & LINK_QUALITY_MASK;
8876 }
8877}
8878
8879static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc)
8880{
8881 u32 frame;
8882
8883 read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG, &frame);
8884 *pdrrc = (frame >> DOWN_REMOTE_REASON_SHIFT) & DOWN_REMOTE_REASON_MASK;
8885}
8886
feb831dd
DL		 8887static void read_link_down_reason(struct hfi1_devdata *dd, u8 *ldr)
8888{
8889 u32 frame;
8890
8891 read_8051_config(dd, LINK_DOWN_REASON, GENERAL_CONFIG, &frame);
8892 *ldr = (frame & 0xff);
8893}
8894
77241056
MM		 8895static int read_tx_settings(struct hfi1_devdata *dd,
8896 u8 *enable_lane_tx,
8897 u8 *tx_polarity_inversion,
8898 u8 *rx_polarity_inversion,
8899 u8 *max_rate)
8900{
8901 u32 frame;
8902 int ret;
8903
8904 ret = read_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, &frame);
8905 *enable_lane_tx = (frame >> ENABLE_LANE_TX_SHIFT)
8906 & ENABLE_LANE_TX_MASK;
8907 *tx_polarity_inversion = (frame >> TX_POLARITY_INVERSION_SHIFT)
8908 & TX_POLARITY_INVERSION_MASK;
8909 *rx_polarity_inversion = (frame >> RX_POLARITY_INVERSION_SHIFT)
8910 & RX_POLARITY_INVERSION_MASK;
8911 *max_rate = (frame >> MAX_RATE_SHIFT) & MAX_RATE_MASK;
8912 return ret;
8913}
8914
8915static int write_tx_settings(struct hfi1_devdata *dd,
8916 u8 enable_lane_tx,
8917 u8 tx_polarity_inversion,
8918 u8 rx_polarity_inversion,
8919 u8 max_rate)
8920{
8921 u32 frame;
8922
8923 /* no need to mask, all variable sizes match field widths */
8924 frame = enable_lane_tx << ENABLE_LANE_TX_SHIFT
8925 | tx_polarity_inversion << TX_POLARITY_INVERSION_SHIFT
8926 | rx_polarity_inversion << RX_POLARITY_INVERSION_SHIFT
8927 | max_rate << MAX_RATE_SHIFT;
8928 return load_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, frame);
8929}
8930
77241056
MM		 8931/*
8932 * Read an idle LCB message.
8933 *
8934 * Returns 0 on success, -EINVAL on error
8935 */
8936static int read_idle_message(struct hfi1_devdata *dd, u64 type, u64 *data_out)
8937{
8938 int ret;
8939
17fb4f29 8940 ret = do_8051_command(dd, HCMD_READ_LCB_IDLE_MSG, type, data_out);
77241056
MM		 8941 if (ret != HCMD_SUCCESS) {
8942 dd_dev_err(dd, "read idle message: type %d, err %d\n",
17fb4f29 8943 (u32)type, ret);
77241056
MM		 8944 return -EINVAL;
8945 }
8946 dd_dev_info(dd, "%s: read idle message 0x%llx\n", __func__, *data_out);
8947 /* return only the payload as we already know the type */
8948 *data_out >>= IDLE_PAYLOAD_SHIFT;
8949 return 0;
8950}
8951
8952/*
8953 * Read an idle SMA message. To be done in response to a notification from
8954 * the 8051.
8955 *
8956 * Returns 0 on success, -EINVAL on error
8957 */
8958static int read_idle_sma(struct hfi1_devdata *dd, u64 *data)
8959{
17fb4f29
JJ		 8960 return read_idle_message(dd, (u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT,
8961 data);
77241056
MM		 8962}
8963
8964/*
8965 * Send an idle LCB message.
8966 *
8967 * Returns 0 on success, -EINVAL on error
8968 */
8969static int send_idle_message(struct hfi1_devdata *dd, u64 data)
8970{
8971 int ret;
8972
8973 dd_dev_info(dd, "%s: sending idle message 0x%llx\n", __func__, data);
8974 ret = do_8051_command(dd, HCMD_SEND_LCB_IDLE_MSG, data, NULL);
8975 if (ret != HCMD_SUCCESS) {
8976 dd_dev_err(dd, "send idle message: data 0x%llx, err %d\n",
17fb4f29 8977 data, ret);
77241056
MM		 8978 return -EINVAL;
8979 }
8980 return 0;
8981}
8982
8983/*
8984 * Send an idle SMA message.
8985 *
8986 * Returns 0 on success, -EINVAL on error
8987 */
8988int send_idle_sma(struct hfi1_devdata *dd, u64 message)
8989{
8990 u64 data;
8991
17fb4f29
JJ		 8992 data = ((message & IDLE_PAYLOAD_MASK) << IDLE_PAYLOAD_SHIFT) |
8993 ((u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT);
77241056
MM		 8994 return send_idle_message(dd, data);
8995}
8996
8997/*
8998 * Initialize the LCB then do a quick link up. This may or may not be
8999 * in loopback.
9000 *
9001 * return 0 on success, -errno on error
9002 */
9003static int do_quick_linkup(struct hfi1_devdata *dd)
9004{
77241056
MM		 9005 int ret;
9006
9007 lcb_shutdown(dd, 0);
9008
9009 if (loopback) {
9010 /* LCB_CFG_LOOPBACK.VAL = 2 */
9011 /* LCB_CFG_LANE_WIDTH.VAL = 0 */
9012 write_csr(dd, DC_LCB_CFG_LOOPBACK,
17fb4f29 9013 IB_PACKET_TYPE << DC_LCB_CFG_LOOPBACK_VAL_SHIFT);
77241056
MM		 9014 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0);
9015 }
9016
9017 /* start the LCBs */
9018 /* LCB_CFG_TX_FIFOS_RESET.VAL = 0 */
9019 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
9020
9021 /* simulator only loopback steps */
9022 if (loopback && dd->icode == ICODE_FUNCTIONAL_SIMULATOR) {
9023 /* LCB_CFG_RUN.EN = 1 */
9024 write_csr(dd, DC_LCB_CFG_RUN,
17fb4f29 9025 1ull << DC_LCB_CFG_RUN_EN_SHIFT);
77241056 9026
ec8a1423
DL		 9027 ret = wait_link_transfer_active(dd, 10);
9028 if (ret)
9029 return ret;
77241056
MM		 9030
9031 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP,
17fb4f29 9032 1ull << DC_LCB_CFG_ALLOW_LINK_UP_VAL_SHIFT);
77241056
MM		 9033 }
9034
9035 if (!loopback) {
9036 /*
9037 * When doing quick linkup and not in loopback, both
9038 * sides must be done with LCB set-up before either
9039 * starts the quick linkup. Put a delay here so that
9040 * both sides can be started and have a chance to be
9041 * done with LCB set up before resuming.
9042 */
9043 dd_dev_err(dd,
17fb4f29 9044 "Pausing for peer to be finished with LCB set up\n");
77241056 9045 msleep(5000);
17fb4f29 9046 dd_dev_err(dd, "Continuing with quick linkup\n");
77241056
MM		 9047 }
9048
9049 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
9050 set_8051_lcb_access(dd);
9051
9052 /*
9053 * State "quick" LinkUp request sets the physical link state to
9054 * LinkUp without a verify capability sequence.
9055 * This state is in simulator v37 and later.
9056 */
9057 ret = set_physical_link_state(dd, PLS_QUICK_LINKUP);
9058 if (ret != HCMD_SUCCESS) {
9059 dd_dev_err(dd,
17fb4f29
JJ		 9060 "%s: set physical link state to quick LinkUp failed with return %d\n",
9061 __func__, ret);
77241056
MM		 9062
9063 set_host_lcb_access(dd);
9064 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
9065
9066 if (ret >= 0)
9067 ret = -EINVAL;
9068 return ret;
9069 }
9070
9071 return 0; /* success */
9072}
9073
9074/*
9075 * Set the SerDes to internal loopback mode.
9076 * Returns 0 on success, -errno on error.
9077 */
9078static int set_serdes_loopback_mode(struct hfi1_devdata *dd)
9079{
9080 int ret;
9081
9082 ret = set_physical_link_state(dd, PLS_INTERNAL_SERDES_LOOPBACK);
9083 if (ret == HCMD_SUCCESS)
9084 return 0;
9085 dd_dev_err(dd,
17fb4f29
JJ		 9086 "Set physical link state to SerDes Loopback failed with return %d\n",
9087 ret);
77241056
MM		 9088 if (ret >= 0)
9089 ret = -EINVAL;
9090 return ret;
9091}
9092
9093/*
9094 * Do all special steps to set up loopback.
9095 */
9096static int init_loopback(struct hfi1_devdata *dd)
9097{
9098 dd_dev_info(dd, "Entering loopback mode\n");
9099
9100 /* all loopbacks should disable self GUID check */
9101 write_csr(dd, DC_DC8051_CFG_MODE,
17fb4f29 9102 (read_csr(dd, DC_DC8051_CFG_MODE) | DISABLE_SELF_GUID_CHECK));
77241056
MM		 9103
9104 /*
9105 * The simulator has only one loopback option - LCB. Switch
9106 * to that option, which includes quick link up.
9107 *
9108 * Accept all valid loopback values.
9109 */
d0d236ea
JJ		 9110 if ((dd->icode == ICODE_FUNCTIONAL_SIMULATOR) &&
9111 (loopback == LOOPBACK_SERDES || loopback == LOOPBACK_LCB ||
9112 loopback == LOOPBACK_CABLE)) {
77241056
MM		 9113 loopback = LOOPBACK_LCB;
9114 quick_linkup = 1;
9115 return 0;
9116 }
9117
9118 /* handle serdes loopback */
9119 if (loopback == LOOPBACK_SERDES) {
9120 /* internal serdes loopack needs quick linkup on RTL */
9121 if (dd->icode == ICODE_RTL_SILICON)
9122 quick_linkup = 1;
9123 return set_serdes_loopback_mode(dd);
9124 }
9125
9126 /* LCB loopback - handled at poll time */
9127 if (loopback == LOOPBACK_LCB) {
9128 quick_linkup = 1; /* LCB is always quick linkup */
9129
9130 /* not supported in emulation due to emulation RTL changes */
9131 if (dd->icode == ICODE_FPGA_EMULATION) {
9132 dd_dev_err(dd,
17fb4f29 9133 "LCB loopback not supported in emulation\n");
77241056
MM		 9134 return -EINVAL;
9135 }
9136 return 0;
9137 }
9138
9139 /* external cable loopback requires no extra steps */
9140 if (loopback == LOOPBACK_CABLE)
9141 return 0;
9142
9143 dd_dev_err(dd, "Invalid loopback mode %d\n", loopback);
9144 return -EINVAL;
9145}
9146
9147/*
9148 * Translate from the OPA_LINK_WIDTH handed to us by the FM to bits
9149 * used in the Verify Capability link width attribute.
9150 */
9151static u16 opa_to_vc_link_widths(u16 opa_widths)
9152{
9153 int i;
9154 u16 result = 0;
9155
9156 static const struct link_bits {
9157 u16 from;
9158 u16 to;
9159 } opa_link_xlate[] = {
8638b77f
JJ		 9160 { OPA_LINK_WIDTH_1X, 1 << (1 - 1) },
9161 { OPA_LINK_WIDTH_2X, 1 << (2 - 1) },
9162 { OPA_LINK_WIDTH_3X, 1 << (3 - 1) },
9163 { OPA_LINK_WIDTH_4X, 1 << (4 - 1) },
77241056
MM		 9164 };
9165
9166 for (i = 0; i < ARRAY_SIZE(opa_link_xlate); i++) {
9167 if (opa_widths & opa_link_xlate[i].from)
9168 result |= opa_link_xlate[i].to;
9169 }
9170 return result;
9171}
9172
9173/*
9174 * Set link attributes before moving to polling.
9175 */
9176static int set_local_link_attributes(struct hfi1_pportdata *ppd)
9177{
9178 struct hfi1_devdata *dd = ppd->dd;
9179 u8 enable_lane_tx;
9180 u8 tx_polarity_inversion;
9181 u8 rx_polarity_inversion;
9182 int ret;
9183
9184 /* reset our fabric serdes to clear any lingering problems */
9185 fabric_serdes_reset(dd);
9186
9187 /* set the local tx rate - need to read-modify-write */
9188 ret = read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion,
17fb4f29 9189 &rx_polarity_inversion, &ppd->local_tx_rate);
77241056
MM		 9190 if (ret)
9191 goto set_local_link_attributes_fail;
9192
5e6e9424 9193 if (dd->dc8051_ver < dc8051_ver(0, 20, 0)) {
77241056
MM		 9194 /* set the tx rate to the fastest enabled */
9195 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G)
9196 ppd->local_tx_rate = 1;
9197 else
9198 ppd->local_tx_rate = 0;
9199 } else {
9200 /* set the tx rate to all enabled */
9201 ppd->local_tx_rate = 0;
9202 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G)
9203 ppd->local_tx_rate |= 2;
9204 if (ppd->link_speed_enabled & OPA_LINK_SPEED_12_5G)
9205 ppd->local_tx_rate |= 1;
9206 }
febffe2c
EH		 9207
9208 enable_lane_tx = 0xF; /* enable all four lanes */
77241056 9209 ret = write_tx_settings(dd, enable_lane_tx, tx_polarity_inversion,
17fb4f29 9210 rx_polarity_inversion, ppd->local_tx_rate);
77241056
MM		 9211 if (ret != HCMD_SUCCESS)
9212 goto set_local_link_attributes_fail;
9213
9214 /*
9215 * DC supports continuous updates.
9216 */
17fb4f29
JJ		 9217 ret = write_vc_local_phy(dd,
9218 0 /* no power management */,
9219 1 /* continuous updates */);
77241056
MM		 9220 if (ret != HCMD_SUCCESS)
9221 goto set_local_link_attributes_fail;
9222
9223 /* z=1 in the next call: AU of 0 is not supported by the hardware */
9224 ret = write_vc_local_fabric(dd, dd->vau, 1, dd->vcu, dd->vl15_init,
9225 ppd->port_crc_mode_enabled);
9226 if (ret != HCMD_SUCCESS)
9227 goto set_local_link_attributes_fail;
9228
9229 ret = write_vc_local_link_width(dd, 0, 0,
17fb4f29
JJ		 9230 opa_to_vc_link_widths(
9231 ppd->link_width_enabled));
77241056
MM		 9232 if (ret != HCMD_SUCCESS)
9233 goto set_local_link_attributes_fail;
9234
9235 /* let peer know who we are */
9236 ret = write_local_device_id(dd, dd->pcidev->device, dd->minrev);
9237 if (ret == HCMD_SUCCESS)
9238 return 0;
9239
9240set_local_link_attributes_fail:
9241 dd_dev_err(dd,
17fb4f29
JJ		 9242 "Failed to set local link attributes, return 0x%x\n",
9243 ret);
77241056
MM		 9244 return ret;
9245}
9246
9247/*
623bba2d
EH		 9248 * Call this to start the link.
9249 * Do not do anything if the link is disabled.
9250 * Returns 0 if link is disabled, moved to polling, or the driver is not ready.
77241056
MM		 9251 */
9252int start_link(struct hfi1_pportdata *ppd)
9253{
0db9dec2
DL		 9254 /*
9255 * Tune the SerDes to a ballpark setting for optimal signal and bit
9256 * error rate. Needs to be done before starting the link.
9257 */
9258 tune_serdes(ppd);
9259
77241056
MM		 9260 if (!ppd->link_enabled) {
9261 dd_dev_info(ppd->dd,
17fb4f29
JJ		 9262 "%s: stopping link start because link is disabled\n",
9263 __func__);
77241056
MM		 9264 return 0;
9265 }
9266 if (!ppd->driver_link_ready) {
9267 dd_dev_info(ppd->dd,
17fb4f29
JJ		 9268 "%s: stopping link start because driver is not ready\n",
9269 __func__);
77241056
MM		 9270 return 0;
9271 }
9272
3ec5fa28
SS		 9273 /*
9274 * FULL_MGMT_P_KEY is cleared from the pkey table, so that the
9275 * pkey table can be configured properly if the HFI unit is connected
9276 * to switch port with MgmtAllowed=NO
9277 */
9278 clear_full_mgmt_pkey(ppd);
9279
623bba2d 9280 return set_link_state(ppd, HLS_DN_POLL);
77241056
MM		 9281}
9282
8ebd4cf1
EH		 9283static void wait_for_qsfp_init(struct hfi1_pportdata *ppd)
9284{
9285 struct hfi1_devdata *dd = ppd->dd;
9286 u64 mask;
9287 unsigned long timeout;
9288
9289 /*
5fbd98dd
EH		 9290 * Some QSFP cables have a quirk that asserts the IntN line as a side
9291 * effect of power up on plug-in. We ignore this false positive
9292 * interrupt until the module has finished powering up by waiting for
9293 * a minimum timeout of the module inrush initialization time of
9294 * 500 ms (SFF 8679 Table 5-6) to ensure the voltage rails in the
9295 * module have stabilized.
9296 */
9297 msleep(500);
9298
9299 /*
9300 * Check for QSFP interrupt for t_init (SFF 8679 Table 8-1)
8ebd4cf1
EH		 9301 */
9302 timeout = jiffies + msecs_to_jiffies(2000);
9303 while (1) {
9304 mask = read_csr(dd, dd->hfi1_id ?
9305 ASIC_QSFP2_IN : ASIC_QSFP1_IN);
5fbd98dd 9306 if (!(mask & QSFP_HFI0_INT_N))
8ebd4cf1 9307 break;
8ebd4cf1
EH		 9308 if (time_after(jiffies, timeout)) {
9309 dd_dev_info(dd, "%s: No IntN detected, reset complete\n",
9310 __func__);
9311 break;
9312 }
9313 udelay(2);
9314 }
9315}
9316
9317static void set_qsfp_int_n(struct hfi1_pportdata *ppd, u8 enable)
9318{
9319 struct hfi1_devdata *dd = ppd->dd;
9320 u64 mask;
9321
9322 mask = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK);
5fbd98dd
EH		 9323 if (enable) {
9324 /*
9325 * Clear the status register to avoid an immediate interrupt
9326 * when we re-enable the IntN pin
9327 */
9328 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR,
9329 QSFP_HFI0_INT_N);
8ebd4cf1 9330 mask |= (u64)QSFP_HFI0_INT_N;
5fbd98dd 9331 } else {
8ebd4cf1 9332 mask &= ~(u64)QSFP_HFI0_INT_N;
5fbd98dd 9333 }
8ebd4cf1
EH		 9334 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, mask);
9335}
9336
9337void reset_qsfp(struct hfi1_pportdata *ppd)
77241056
MM		 9338{
9339 struct hfi1_devdata *dd = ppd->dd;
9340 u64 mask, qsfp_mask;
9341
8ebd4cf1
EH		 9342 /* Disable INT_N from triggering QSFP interrupts */
9343 set_qsfp_int_n(ppd, 0);
9344
9345 /* Reset the QSFP */
77241056 9346 mask = (u64)QSFP_HFI0_RESET_N;
77241056
MM		 9347
9348 qsfp_mask = read_csr(dd,
17fb4f29 9349 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT);
77241056
MM		 9350 qsfp_mask &= ~mask;
9351 write_csr(dd,
17fb4f29 9352 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask);
77241056
MM		 9353
9354 udelay(10);
9355
9356 qsfp_mask |= mask;
9357 write_csr(dd,
17fb4f29 9358 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask);
8ebd4cf1
EH		 9359
9360 wait_for_qsfp_init(ppd);
9361
9362 /*
9363 * Allow INT_N to trigger the QSFP interrupt to watch
9364 * for alarms and warnings
9365 */
9366 set_qsfp_int_n(ppd, 1);
77241056
MM		 9367}
9368
9369static int handle_qsfp_error_conditions(struct hfi1_pportdata *ppd,
9370 u8 *qsfp_interrupt_status)
9371{
9372 struct hfi1_devdata *dd = ppd->dd;
9373
9374 if ((qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_ALARM) ||
17fb4f29 9375 (qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_WARNING))
03e80e9a 9376 dd_dev_info(dd, "%s: QSFP cable temperature too high\n",
17fb4f29 9377 __func__);
77241056
MM		 9378
9379 if ((qsfp_interrupt_status[0] & QSFP_LOW_TEMP_ALARM) ||
17fb4f29
JJ		 9380 (qsfp_interrupt_status[0] & QSFP_LOW_TEMP_WARNING))
9381 dd_dev_info(dd, "%s: QSFP cable temperature too low\n",
9382 __func__);
77241056 9383
0c7f77af
EH		 9384 /*
9385 * The remaining alarms/warnings don't matter if the link is down.
9386 */
9387 if (ppd->host_link_state & HLS_DOWN)
9388 return 0;
9389
77241056 9390 if ((qsfp_interrupt_status[1] & QSFP_HIGH_VCC_ALARM) ||
17fb4f29
JJ		 9391 (qsfp_interrupt_status[1] & QSFP_HIGH_VCC_WARNING))
9392 dd_dev_info(dd, "%s: QSFP supply voltage too high\n",
9393 __func__);
77241056
MM		 9394
9395 if ((qsfp_interrupt_status[1] & QSFP_LOW_VCC_ALARM) ||
17fb4f29
JJ		 9396 (qsfp_interrupt_status[1] & QSFP_LOW_VCC_WARNING))
9397 dd_dev_info(dd, "%s: QSFP supply voltage too low\n",
9398 __func__);
77241056
MM		 9399
9400 /* Byte 2 is vendor specific */
9401
9402 if ((qsfp_interrupt_status[3] & QSFP_HIGH_POWER_ALARM) ||
17fb4f29
JJ		 9403 (qsfp_interrupt_status[3] & QSFP_HIGH_POWER_WARNING))
9404 dd_dev_info(dd, "%s: Cable RX channel 1/2 power too high\n",
9405 __func__);
77241056
MM		 9406
9407 if ((qsfp_interrupt_status[3] & QSFP_LOW_POWER_ALARM) ||
17fb4f29
JJ		 9408 (qsfp_interrupt_status[3] & QSFP_LOW_POWER_WARNING))
9409 dd_dev_info(dd, "%s: Cable RX channel 1/2 power too low\n",
9410 __func__);
77241056
MM		 9411
9412 if ((qsfp_interrupt_status[4] & QSFP_HIGH_POWER_ALARM) ||
17fb4f29
JJ		 9413 (qsfp_interrupt_status[4] & QSFP_HIGH_POWER_WARNING))
9414 dd_dev_info(dd, "%s: Cable RX channel 3/4 power too high\n",
9415 __func__);
77241056
MM		 9416
9417 if ((qsfp_interrupt_status[4] & QSFP_LOW_POWER_ALARM) ||
17fb4f29
JJ		 9418 (qsfp_interrupt_status[4] & QSFP_LOW_POWER_WARNING))
9419 dd_dev_info(dd, "%s: Cable RX channel 3/4 power too low\n",
9420 __func__);
77241056
MM		 9421
9422 if ((qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_ALARM) ||
17fb4f29
JJ		 9423 (qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_WARNING))
9424 dd_dev_info(dd, "%s: Cable TX channel 1/2 bias too high\n",
9425 __func__);
77241056
MM		 9426
9427 if ((qsfp_interrupt_status[5] & QSFP_LOW_BIAS_ALARM) ||
17fb4f29
JJ		 9428 (qsfp_interrupt_status[5] & QSFP_LOW_BIAS_WARNING))
9429 dd_dev_info(dd, "%s: Cable TX channel 1/2 bias too low\n",
9430 __func__);
77241056
MM		 9431
9432 if ((qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_ALARM) ||
17fb4f29
JJ		 9433 (qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_WARNING))
9434 dd_dev_info(dd, "%s: Cable TX channel 3/4 bias too high\n",
9435 __func__);
77241056
MM		 9436
9437 if ((qsfp_interrupt_status[6] & QSFP_LOW_BIAS_ALARM) ||
17fb4f29
JJ		 9438 (qsfp_interrupt_status[6] & QSFP_LOW_BIAS_WARNING))
9439 dd_dev_info(dd, "%s: Cable TX channel 3/4 bias too low\n",
9440 __func__);
77241056
MM		 9441
9442 if ((qsfp_interrupt_status[7] & QSFP_HIGH_POWER_ALARM) ||
17fb4f29
JJ		 9443 (qsfp_interrupt_status[7] & QSFP_HIGH_POWER_WARNING))
9444 dd_dev_info(dd, "%s: Cable TX channel 1/2 power too high\n",
9445 __func__);
77241056
MM		 9446
9447 if ((qsfp_interrupt_status[7] & QSFP_LOW_POWER_ALARM) ||
17fb4f29
JJ		 9448 (qsfp_interrupt_status[7] & QSFP_LOW_POWER_WARNING))
9449 dd_dev_info(dd, "%s: Cable TX channel 1/2 power too low\n",
9450 __func__);
77241056
MM		 9451
9452 if ((qsfp_interrupt_status[8] & QSFP_HIGH_POWER_ALARM) ||
17fb4f29
JJ		 9453 (qsfp_interrupt_status[8] & QSFP_HIGH_POWER_WARNING))
9454 dd_dev_info(dd, "%s: Cable TX channel 3/4 power too high\n",
9455 __func__);
77241056
MM		 9456
9457 if ((qsfp_interrupt_status[8] & QSFP_LOW_POWER_ALARM) ||
17fb4f29
JJ		 9458 (qsfp_interrupt_status[8] & QSFP_LOW_POWER_WARNING))
9459 dd_dev_info(dd, "%s: Cable TX channel 3/4 power too low\n",
9460 __func__);
77241056
MM		 9461
9462 /* Bytes 9-10 and 11-12 are reserved */
9463 /* Bytes 13-15 are vendor specific */
9464
9465 return 0;
9466}
9467
623bba2d 9468/* This routine will only be scheduled if the QSFP module present is asserted */
8ebd4cf1 9469void qsfp_event(struct work_struct *work)
77241056
MM		 9470{
9471 struct qsfp_data *qd;
9472 struct hfi1_pportdata *ppd;
9473 struct hfi1_devdata *dd;
9474
9475 qd = container_of(work, struct qsfp_data, qsfp_work);
9476 ppd = qd->ppd;
9477 dd = ppd->dd;
9478
9479 /* Sanity check */
9480 if (!qsfp_mod_present(ppd))
9481 return;
9482
9483 /*
0c7f77af
EH		 9484 * Turn DC back on after cable has been re-inserted. Up until
9485 * now, the DC has been in reset to save power.
77241056
MM		 9486 */
9487 dc_start(dd);
9488
9489 if (qd->cache_refresh_required) {
8ebd4cf1 9490 set_qsfp_int_n(ppd, 0);
77241056 9491
8ebd4cf1
EH		 9492 wait_for_qsfp_init(ppd);
9493
9494 /*
9495 * Allow INT_N to trigger the QSFP interrupt to watch
9496 * for alarms and warnings
77241056 9497 */
8ebd4cf1
EH		 9498 set_qsfp_int_n(ppd, 1);
9499
8ebd4cf1 9500 start_link(ppd);
77241056
MM		 9501 }
9502
9503 if (qd->check_interrupt_flags) {
9504 u8 qsfp_interrupt_status[16] = {0,};
9505
765a6fac
DL		 9506 if (one_qsfp_read(ppd, dd->hfi1_id, 6,
9507 &qsfp_interrupt_status[0], 16) != 16) {
77241056 9508 dd_dev_info(dd,
17fb4f29
JJ		 9509 "%s: Failed to read status of QSFP module\n",
9510 __func__);
77241056
MM		 9511 } else {
9512 unsigned long flags;
77241056 9513
8ebd4cf1
EH		 9514 handle_qsfp_error_conditions(
9515 ppd, qsfp_interrupt_status);
77241056
MM		 9516 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
9517 ppd->qsfp_info.check_interrupt_flags = 0;
9518 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
17fb4f29 9519 flags);
77241056
MM		 9520 }
9521 }
9522}
9523
8ebd4cf1 9524static void init_qsfp_int(struct hfi1_devdata *dd)
77241056 9525{
8ebd4cf1
EH		 9526 struct hfi1_pportdata *ppd = dd->pport;
9527 u64 qsfp_mask, cce_int_mask;
9528 const int qsfp1_int_smask = QSFP1_INT % 64;
9529 const int qsfp2_int_smask = QSFP2_INT % 64;
77241056 9530
8ebd4cf1
EH		 9531 /*
9532 * disable QSFP1 interrupts for HFI1, QSFP2 interrupts for HFI0
9533 * Qsfp1Int and Qsfp2Int are adjacent bits in the same CSR,
9534 * therefore just one of QSFP1_INT/QSFP2_INT can be used to find
9535 * the index of the appropriate CSR in the CCEIntMask CSR array
9536 */
9537 cce_int_mask = read_csr(dd, CCE_INT_MASK +
9538 (8 * (QSFP1_INT / 64)));
9539 if (dd->hfi1_id) {
9540 cce_int_mask &= ~((u64)1 << qsfp1_int_smask);
9541 write_csr(dd, CCE_INT_MASK + (8 * (QSFP1_INT / 64)),
9542 cce_int_mask);
9543 } else {
9544 cce_int_mask &= ~((u64)1 << qsfp2_int_smask);
9545 write_csr(dd, CCE_INT_MASK + (8 * (QSFP2_INT / 64)),
9546 cce_int_mask);
77241056
MM		 9547 }
9548
77241056
MM		 9549 qsfp_mask = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N);
9550 /* Clear current status to avoid spurious interrupts */
8ebd4cf1
EH		 9551 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR,
9552 qsfp_mask);
9553 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK,
9554 qsfp_mask);
9555
9556 set_qsfp_int_n(ppd, 0);
77241056
MM		 9557
9558 /* Handle active low nature of INT_N and MODPRST_N pins */
9559 if (qsfp_mod_present(ppd))
9560 qsfp_mask &= ~(u64)QSFP_HFI0_MODPRST_N;
9561 write_csr(dd,
9562 dd->hfi1_id ? ASIC_QSFP2_INVERT : ASIC_QSFP1_INVERT,
9563 qsfp_mask);
77241056
MM		 9564}
9565
bbdeb33d
DL		 9566/*
9567 * Do a one-time initialize of the LCB block.
9568 */
9569static void init_lcb(struct hfi1_devdata *dd)
9570{
a59329d5
DL		 9571 /* simulator does not correctly handle LCB cclk loopback, skip */
9572 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
9573 return;
9574
bbdeb33d
DL		 9575 /* the DC has been reset earlier in the driver load */
9576
9577 /* set LCB for cclk loopback on the port */
9578 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x01);
9579 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0x00);
9580 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0x00);
9581 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110);
9582 write_csr(dd, DC_LCB_CFG_CLK_CNTR, 0x08);
9583 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x02);
9584 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x00);
9585}
9586
673b975f
DL		 9587/*
9588 * Perform a test read on the QSFP. Return 0 on success, -ERRNO
9589 * on error.
9590 */
9591static int test_qsfp_read(struct hfi1_pportdata *ppd)
9592{
9593 int ret;
9594 u8 status;
9595
fb897ad3
EH		 9596 /*
9597 * Report success if not a QSFP or, if it is a QSFP, but the cable is
9598 * not present
9599 */
9600 if (ppd->port_type != PORT_TYPE_QSFP || !qsfp_mod_present(ppd))
673b975f
DL		 9601 return 0;
9602
9603 /* read byte 2, the status byte */
9604 ret = one_qsfp_read(ppd, ppd->dd->hfi1_id, 2, &status, 1);
9605 if (ret < 0)
9606 return ret;
9607 if (ret != 1)
9608 return -EIO;
9609
9610 return 0; /* success */
9611}
9612
9613/*
9614 * Values for QSFP retry.
9615 *
9616 * Give up after 10s (20 x 500ms). The overall timeout was empirically
9617 * arrived at from experience on a large cluster.
9618 */
9619#define MAX_QSFP_RETRIES 20
9620#define QSFP_RETRY_WAIT 500 /* msec */
9621
9622/*
9623 * Try a QSFP read. If it fails, schedule a retry for later.
9624 * Called on first link activation after driver load.
9625 */
9626static void try_start_link(struct hfi1_pportdata *ppd)
9627{
9628 if (test_qsfp_read(ppd)) {
9629 /* read failed */
9630 if (ppd->qsfp_retry_count >= MAX_QSFP_RETRIES) {
9631 dd_dev_err(ppd->dd, "QSFP not responding, giving up\n");
9632 return;
9633 }
9634 dd_dev_info(ppd->dd,
9635 "QSFP not responding, waiting and retrying %d\n",
9636 (int)ppd->qsfp_retry_count);
9637 ppd->qsfp_retry_count++;
9638 queue_delayed_work(ppd->hfi1_wq, &ppd->start_link_work,
9639 msecs_to_jiffies(QSFP_RETRY_WAIT));
9640 return;
9641 }
9642 ppd->qsfp_retry_count = 0;
9643
673b975f
DL		 9644 start_link(ppd);
9645}
9646
9647/*
9648 * Workqueue function to start the link after a delay.
9649 */
9650void handle_start_link(struct work_struct *work)
9651{
9652 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
9653 start_link_work.work);
9654 try_start_link(ppd);
9655}
9656
77241056
MM		 9657int bringup_serdes(struct hfi1_pportdata *ppd)
9658{
9659 struct hfi1_devdata *dd = ppd->dd;
9660 u64 guid;
9661 int ret;
9662
9663 if (HFI1_CAP_IS_KSET(EXTENDED_PSN))
9664 add_rcvctrl(dd, RCV_CTRL_RCV_EXTENDED_PSN_ENABLE_SMASK);
9665
a6cd5f08 9666 guid = ppd->guids[HFI1_PORT_GUID_INDEX];
77241056
MM		 9667 if (!guid) {
9668 if (dd->base_guid)
9669 guid = dd->base_guid + ppd->port - 1;
a6cd5f08 9670 ppd->guids[HFI1_PORT_GUID_INDEX] = guid;
77241056
MM		 9671 }
9672
77241056
MM		 9673 /* Set linkinit_reason on power up per OPA spec */
9674 ppd->linkinit_reason = OPA_LINKINIT_REASON_LINKUP;
9675
bbdeb33d
DL		 9676 /* one-time init of the LCB */
9677 init_lcb(dd);
9678
77241056
MM		 9679 if (loopback) {
9680 ret = init_loopback(dd);
9681 if (ret < 0)
9682 return ret;
9683 }
9684
9775a991
EH		 9685 get_port_type(ppd);
9686 if (ppd->port_type == PORT_TYPE_QSFP) {
9687 set_qsfp_int_n(ppd, 0);
9688 wait_for_qsfp_init(ppd);
9689 set_qsfp_int_n(ppd, 1);
9690 }
9691
673b975f
DL		 9692 try_start_link(ppd);
9693 return 0;
77241056
MM		 9694}
9695
9696void hfi1_quiet_serdes(struct hfi1_pportdata *ppd)
9697{
9698 struct hfi1_devdata *dd = ppd->dd;
9699
9700 /*
9701 * Shut down the link and keep it down. First turn off that the
9702 * driver wants to allow the link to be up (driver_link_ready).
9703 * Then make sure the link is not automatically restarted
9704 * (link_enabled). Cancel any pending restart. And finally
9705 * go offline.
9706 */
9707 ppd->driver_link_ready = 0;
9708 ppd->link_enabled = 0;
9709
673b975f
DL		 9710 ppd->qsfp_retry_count = MAX_QSFP_RETRIES; /* prevent more retries */
9711 flush_delayed_work(&ppd->start_link_work);
9712 cancel_delayed_work_sync(&ppd->start_link_work);
9713
8ebd4cf1
EH		 9714 ppd->offline_disabled_reason =
9715 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_SMA_DISABLED);
77241056 9716 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_SMA_DISABLED, 0,
17fb4f29 9717 OPA_LINKDOWN_REASON_SMA_DISABLED);
77241056
MM		 9718 set_link_state(ppd, HLS_DN_OFFLINE);
9719
9720 /* disable the port */
9721 clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
9722}
9723
9724static inline int init_cpu_counters(struct hfi1_devdata *dd)
9725{
9726 struct hfi1_pportdata *ppd;
9727 int i;
9728
9729 ppd = (struct hfi1_pportdata *)(dd + 1);
9730 for (i = 0; i < dd->num_pports; i++, ppd++) {
4eb06882
DD		 9731 ppd->ibport_data.rvp.rc_acks = NULL;
9732 ppd->ibport_data.rvp.rc_qacks = NULL;
9733 ppd->ibport_data.rvp.rc_acks = alloc_percpu(u64);
9734 ppd->ibport_data.rvp.rc_qacks = alloc_percpu(u64);
9735 ppd->ibport_data.rvp.rc_delayed_comp = alloc_percpu(u64);
9736 if (!ppd->ibport_data.rvp.rc_acks ||
9737 !ppd->ibport_data.rvp.rc_delayed_comp ||
9738 !ppd->ibport_data.rvp.rc_qacks)
77241056
MM		 9739 return -ENOMEM;
9740 }
9741
9742 return 0;
9743}
9744
9745static const char * const pt_names[] = {
9746 "expected",
9747 "eager",
9748 "invalid"
9749};
9750
9751static const char *pt_name(u32 type)
9752{
9753 return type >= ARRAY_SIZE(pt_names) ? "unknown" : pt_names[type];
9754}
9755
9756/*
9757 * index is the index into the receive array
9758 */
9759void hfi1_put_tid(struct hfi1_devdata *dd, u32 index,
9760 u32 type, unsigned long pa, u16 order)
9761{
9762 u64 reg;
9763 void __iomem *base = (dd->rcvarray_wc ? dd->rcvarray_wc :
9764 (dd->kregbase + RCV_ARRAY));
9765
9766 if (!(dd->flags & HFI1_PRESENT))
9767 goto done;
9768
9769 if (type == PT_INVALID) {
9770 pa = 0;
9771 } else if (type > PT_INVALID) {
9772 dd_dev_err(dd,
17fb4f29
JJ		 9773 "unexpected receive array type %u for index %u, not handled\n",
9774 type, index);
77241056
MM		 9775 goto done;
9776 }
9777
9778 hfi1_cdbg(TID, "type %s, index 0x%x, pa 0x%lx, bsize 0x%lx",
9779 pt_name(type), index, pa, (unsigned long)order);
9780
9781#define RT_ADDR_SHIFT 12 /* 4KB kernel address boundary */
9782 reg = RCV_ARRAY_RT_WRITE_ENABLE_SMASK
9783 | (u64)order << RCV_ARRAY_RT_BUF_SIZE_SHIFT
9784 | ((pa >> RT_ADDR_SHIFT) & RCV_ARRAY_RT_ADDR_MASK)
9785 << RCV_ARRAY_RT_ADDR_SHIFT;
9786 writeq(reg, base + (index * 8));
9787
9788 if (type == PT_EAGER)
9789 /*
9790 * Eager entries are written one-by-one so we have to push them
9791 * after we write the entry.
9792 */
9793 flush_wc();
9794done:
9795 return;
9796}
9797
9798void hfi1_clear_tids(struct hfi1_ctxtdata *rcd)
9799{
9800 struct hfi1_devdata *dd = rcd->dd;
9801 u32 i;
9802
9803 /* this could be optimized */
9804 for (i = rcd->eager_base; i < rcd->eager_base +
9805 rcd->egrbufs.alloced; i++)
9806 hfi1_put_tid(dd, i, PT_INVALID, 0, 0);
9807
9808 for (i = rcd->expected_base;
9809 i < rcd->expected_base + rcd->expected_count; i++)
9810 hfi1_put_tid(dd, i, PT_INVALID, 0, 0);
9811}
9812
261a4351
MM		 9813struct ib_header *hfi1_get_msgheader(
9814 struct hfi1_devdata *dd, __le32 *rhf_addr)
77241056
MM		 9815{
9816 u32 offset = rhf_hdrq_offset(rhf_to_cpu(rhf_addr));
9817
261a4351 9818 return (struct ib_header *)
77241056
MM		 9819 (rhf_addr - dd->rhf_offset + offset);
9820}
9821
9822static const char * const ib_cfg_name_strings[] = {
9823 "HFI1_IB_CFG_LIDLMC",
9824 "HFI1_IB_CFG_LWID_DG_ENB",
9825 "HFI1_IB_CFG_LWID_ENB",
9826 "HFI1_IB_CFG_LWID",
9827 "HFI1_IB_CFG_SPD_ENB",
9828 "HFI1_IB_CFG_SPD",
9829 "HFI1_IB_CFG_RXPOL_ENB",
9830 "HFI1_IB_CFG_LREV_ENB",
9831 "HFI1_IB_CFG_LINKLATENCY",
9832 "HFI1_IB_CFG_HRTBT",
9833 "HFI1_IB_CFG_OP_VLS",
9834 "HFI1_IB_CFG_VL_HIGH_CAP",
9835 "HFI1_IB_CFG_VL_LOW_CAP",
9836 "HFI1_IB_CFG_OVERRUN_THRESH",
9837 "HFI1_IB_CFG_PHYERR_THRESH",
9838 "HFI1_IB_CFG_LINKDEFAULT",
9839 "HFI1_IB_CFG_PKEYS",
9840 "HFI1_IB_CFG_MTU",
9841 "HFI1_IB_CFG_LSTATE",
9842 "HFI1_IB_CFG_VL_HIGH_LIMIT",
9843 "HFI1_IB_CFG_PMA_TICKS",
9844 "HFI1_IB_CFG_PORT"
9845};
9846
9847static const char *ib_cfg_name(int which)
9848{
9849 if (which < 0 || which >= ARRAY_SIZE(ib_cfg_name_strings))
9850 return "invalid";
9851 return ib_cfg_name_strings[which];
9852}
9853
9854int hfi1_get_ib_cfg(struct hfi1_pportdata *ppd, int which)
9855{
9856 struct hfi1_devdata *dd = ppd->dd;
9857 int val = 0;
9858
9859 switch (which) {
9860 case HFI1_IB_CFG_LWID_ENB: /* allowed Link-width */
9861 val = ppd->link_width_enabled;
9862 break;
9863 case HFI1_IB_CFG_LWID: /* currently active Link-width */
9864 val = ppd->link_width_active;
9865 break;
9866 case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */
9867 val = ppd->link_speed_enabled;
9868 break;
9869 case HFI1_IB_CFG_SPD: /* current Link speed */
9870 val = ppd->link_speed_active;
9871 break;
9872
9873 case HFI1_IB_CFG_RXPOL_ENB: /* Auto-RX-polarity enable */
9874 case HFI1_IB_CFG_LREV_ENB: /* Auto-Lane-reversal enable */
9875 case HFI1_IB_CFG_LINKLATENCY:
9876 goto unimplemented;
9877
9878 case HFI1_IB_CFG_OP_VLS:
9879 val = ppd->vls_operational;
9880 break;
9881 case HFI1_IB_CFG_VL_HIGH_CAP: /* VL arb high priority table size */
9882 val = VL_ARB_HIGH_PRIO_TABLE_SIZE;
9883 break;
9884 case HFI1_IB_CFG_VL_LOW_CAP: /* VL arb low priority table size */
9885 val = VL_ARB_LOW_PRIO_TABLE_SIZE;
9886 break;
9887 case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
9888 val = ppd->overrun_threshold;
9889 break;
9890 case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
9891 val = ppd->phy_error_threshold;
9892 break;
9893 case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
9894 val = dd->link_default;
9895 break;
9896
9897 case HFI1_IB_CFG_HRTBT: /* Heartbeat off/enable/auto */
9898 case HFI1_IB_CFG_PMA_TICKS:
9899 default:
9900unimplemented:
9901 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
9902 dd_dev_info(
9903 dd,
9904 "%s: which %s: not implemented\n",
9905 __func__,
9906 ib_cfg_name(which));
9907 break;
9908 }
9909
9910 return val;
9911}
9912
9913/*
9914 * The largest MAD packet size.
9915 */
9916#define MAX_MAD_PACKET 2048
9917
9918/*
9919 * Return the maximum header bytes that can go on the _wire_
9920 * for this device. This count includes the ICRC which is
9921 * not part of the packet held in memory but it is appended
9922 * by the HW.
9923 * This is dependent on the device's receive header entry size.
9924 * HFI allows this to be set per-receive context, but the
9925 * driver presently enforces a global value.
9926 */
9927u32 lrh_max_header_bytes(struct hfi1_devdata *dd)
9928{
9929 /*
9930 * The maximum non-payload (MTU) bytes in LRH.PktLen are
9931 * the Receive Header Entry Size minus the PBC (or RHF) size
9932 * plus one DW for the ICRC appended by HW.
9933 *
9934 * dd->rcd[0].rcvhdrqentsize is in DW.
9935 * We use rcd[0] as all context will have the same value. Also,
9936 * the first kernel context would have been allocated by now so
9937 * we are guaranteed a valid value.
9938 */
9939 return (dd->rcd[0]->rcvhdrqentsize - 2/*PBC/RHF*/ + 1/*ICRC*/) << 2;
9940}
9941
9942/*
9943 * Set Send Length
9944 * @ppd - per port data
9945 *
9946 * Set the MTU by limiting how many DWs may be sent. The SendLenCheck*
9947 * registers compare against LRH.PktLen, so use the max bytes included
9948 * in the LRH.
9949 *
9950 * This routine changes all VL values except VL15, which it maintains at
9951 * the same value.
9952 */
9953static void set_send_length(struct hfi1_pportdata *ppd)
9954{
9955 struct hfi1_devdata *dd = ppd->dd;
6cc6ad2e
HC		 9956 u32 max_hb = lrh_max_header_bytes(dd), dcmtu;
9957 u32 maxvlmtu = dd->vld[15].mtu;
77241056
MM		 9958 u64 len1 = 0, len2 = (((dd->vld[15].mtu + max_hb) >> 2)
9959 & SEND_LEN_CHECK1_LEN_VL15_MASK) <<
9960 SEND_LEN_CHECK1_LEN_VL15_SHIFT;
b4ba6633 9961 int i, j;
44306f15 9962 u32 thres;
77241056
MM		 9963
9964 for (i = 0; i < ppd->vls_supported; i++) {
9965 if (dd->vld[i].mtu > maxvlmtu)
9966 maxvlmtu = dd->vld[i].mtu;
9967 if (i <= 3)
9968 len1 |= (((dd->vld[i].mtu + max_hb) >> 2)
9969 & SEND_LEN_CHECK0_LEN_VL0_MASK) <<
9970 ((i % 4) * SEND_LEN_CHECK0_LEN_VL1_SHIFT);
9971 else
9972 len2 |= (((dd->vld[i].mtu + max_hb) >> 2)
9973 & SEND_LEN_CHECK1_LEN_VL4_MASK) <<
9974 ((i % 4) * SEND_LEN_CHECK1_LEN_VL5_SHIFT);
9975 }
9976 write_csr(dd, SEND_LEN_CHECK0, len1);
9977 write_csr(dd, SEND_LEN_CHECK1, len2);
9978 /* adjust kernel credit return thresholds based on new MTUs */
9979 /* all kernel receive contexts have the same hdrqentsize */
9980 for (i = 0; i < ppd->vls_supported; i++) {
44306f15
JX		 9981 thres = min(sc_percent_to_threshold(dd->vld[i].sc, 50),
9982 sc_mtu_to_threshold(dd->vld[i].sc,
9983 dd->vld[i].mtu,
17fb4f29 9984 dd->rcd[0]->rcvhdrqentsize));
b4ba6633
JJ		 9985 for (j = 0; j < INIT_SC_PER_VL; j++)
9986 sc_set_cr_threshold(
9987 pio_select_send_context_vl(dd, j, i),
9988 thres);
44306f15
JX		 9989 }
9990 thres = min(sc_percent_to_threshold(dd->vld[15].sc, 50),
9991 sc_mtu_to_threshold(dd->vld[15].sc,
9992 dd->vld[15].mtu,
9993 dd->rcd[0]->rcvhdrqentsize));
9994 sc_set_cr_threshold(dd->vld[15].sc, thres);
77241056
MM		 9995
9996 /* Adjust maximum MTU for the port in DC */
9997 dcmtu = maxvlmtu == 10240 ? DCC_CFG_PORT_MTU_CAP_10240 :
9998 (ilog2(maxvlmtu >> 8) + 1);
9999 len1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG);
10000 len1 &= ~DCC_CFG_PORT_CONFIG_MTU_CAP_SMASK;
10001 len1 |= ((u64)dcmtu & DCC_CFG_PORT_CONFIG_MTU_CAP_MASK) <<
10002 DCC_CFG_PORT_CONFIG_MTU_CAP_SHIFT;
10003 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG, len1);
10004}
10005
10006static void set_lidlmc(struct hfi1_pportdata *ppd)
10007{
10008 int i;
10009 u64 sreg = 0;
10010 struct hfi1_devdata *dd = ppd->dd;
10011 u32 mask = ~((1U << ppd->lmc) - 1);
10012 u64 c1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG1);
10013
77241056
MM		 10014 c1 &= ~(DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK
10015 | DCC_CFG_PORT_CONFIG1_DLID_MASK_SMASK);
10016 c1 |= ((ppd->lid & DCC_CFG_PORT_CONFIG1_TARGET_DLID_MASK)
8638b77f 10017 << DCC_CFG_PORT_CONFIG1_TARGET_DLID_SHIFT) |
77241056
MM		 10018 ((mask & DCC_CFG_PORT_CONFIG1_DLID_MASK_MASK)
10019 << DCC_CFG_PORT_CONFIG1_DLID_MASK_SHIFT);
10020 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG1, c1);
10021
10022 /*
10023 * Iterate over all the send contexts and set their SLID check
10024 */
10025 sreg = ((mask & SEND_CTXT_CHECK_SLID_MASK_MASK) <<
10026 SEND_CTXT_CHECK_SLID_MASK_SHIFT) |
10027 (((ppd->lid & mask) & SEND_CTXT_CHECK_SLID_VALUE_MASK) <<
10028 SEND_CTXT_CHECK_SLID_VALUE_SHIFT);
10029
10030 for (i = 0; i < dd->chip_send_contexts; i++) {
10031 hfi1_cdbg(LINKVERB, "SendContext[%d].SLID_CHECK = 0x%x",
10032 i, (u32)sreg);
10033 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, sreg);
10034 }
10035
10036 /* Now we have to do the same thing for the sdma engines */
10037 sdma_update_lmc(dd, mask, ppd->lid);
10038}
10039
10040static int wait_phy_linkstate(struct hfi1_devdata *dd, u32 state, u32 msecs)
10041{
10042 unsigned long timeout;
10043 u32 curr_state;
10044
10045 timeout = jiffies + msecs_to_jiffies(msecs);
10046 while (1) {
10047 curr_state = read_physical_state(dd);
10048 if (curr_state == state)
10049 break;
10050 if (time_after(jiffies, timeout)) {
10051 dd_dev_err(dd,
17fb4f29
JJ		 10052 "timeout waiting for phy link state 0x%x, current state is 0x%x\n",
10053 state, curr_state);
77241056
MM		 10054 return -ETIMEDOUT;
10055 }
10056 usleep_range(1950, 2050); /* sleep 2ms-ish */
10057 }
10058
10059 return 0;
10060}
10061
6854c692
DL		 10062static const char *state_completed_string(u32 completed)
10063{
10064 static const char * const state_completed[] = {
10065 "EstablishComm",
10066 "OptimizeEQ",
10067 "VerifyCap"
10068 };
10069
10070 if (completed < ARRAY_SIZE(state_completed))
10071 return state_completed[completed];
10072
10073 return "unknown";
10074}
10075
10076static const char all_lanes_dead_timeout_expired[] =
10077 "All lanes were inactive – was the interconnect media removed?";
10078static const char tx_out_of_policy[] =
10079 "Passing lanes on local port do not meet the local link width policy";
10080static const char no_state_complete[] =
10081 "State timeout occurred before link partner completed the state";
10082static const char * const state_complete_reasons[] = {
10083 [0x00] = "Reason unknown",
10084 [0x01] = "Link was halted by driver, refer to LinkDownReason",
10085 [0x02] = "Link partner reported failure",
10086 [0x10] = "Unable to achieve frame sync on any lane",
10087 [0x11] =
10088 "Unable to find a common bit rate with the link partner",
10089 [0x12] =
10090 "Unable to achieve frame sync on sufficient lanes to meet the local link width policy",
10091 [0x13] =
10092 "Unable to identify preset equalization on sufficient lanes to meet the local link width policy",
10093 [0x14] = no_state_complete,
10094 [0x15] =
10095 "State timeout occurred before link partner identified equalization presets",
10096 [0x16] =
10097 "Link partner completed the EstablishComm state, but the passing lanes do not meet the local link width policy",
10098 [0x17] = tx_out_of_policy,
10099 [0x20] = all_lanes_dead_timeout_expired,
10100 [0x21] =
10101 "Unable to achieve acceptable BER on sufficient lanes to meet the local link width policy",
10102 [0x22] = no_state_complete,
10103 [0x23] =
10104 "Link partner completed the OptimizeEq state, but the passing lanes do not meet the local link width policy",
10105 [0x24] = tx_out_of_policy,
10106 [0x30] = all_lanes_dead_timeout_expired,
10107 [0x31] =
10108 "State timeout occurred waiting for host to process received frames",
10109 [0x32] = no_state_complete,
10110 [0x33] =
10111 "Link partner completed the VerifyCap state, but the passing lanes do not meet the local link width policy",
10112 [0x34] = tx_out_of_policy,
10113};
10114
10115static const char *state_complete_reason_code_string(struct hfi1_pportdata *ppd,
10116 u32 code)
10117{
10118 const char *str = NULL;
10119
10120 if (code < ARRAY_SIZE(state_complete_reasons))
10121 str = state_complete_reasons[code];
10122
10123 if (str)
10124 return str;
10125 return "Reserved";
10126}
10127
10128/* describe the given last state complete frame */
10129static void decode_state_complete(struct hfi1_pportdata *ppd, u32 frame,
10130 const char *prefix)
10131{
10132 struct hfi1_devdata *dd = ppd->dd;
10133 u32 success;
10134 u32 state;
10135 u32 reason;
10136 u32 lanes;
10137
10138 /*
10139 * Decode frame:
10140 * [ 0: 0] - success
10141 * [ 3: 1] - state
10142 * [ 7: 4] - next state timeout
10143 * [15: 8] - reason code
10144 * [31:16] - lanes
10145 */
10146 success = frame & 0x1;
10147 state = (frame >> 1) & 0x7;
10148 reason = (frame >> 8) & 0xff;
10149 lanes = (frame >> 16) & 0xffff;
10150
10151 dd_dev_err(dd, "Last %s LNI state complete frame 0x%08x:\n",
10152 prefix, frame);
10153 dd_dev_err(dd, " last reported state state: %s (0x%x)\n",
10154 state_completed_string(state), state);
10155 dd_dev_err(dd, " state successfully completed: %s\n",
10156 success ? "yes" : "no");
10157 dd_dev_err(dd, " fail reason 0x%x: %s\n",
10158 reason, state_complete_reason_code_string(ppd, reason));
10159 dd_dev_err(dd, " passing lane mask: 0x%x", lanes);
10160}
10161
10162/*
10163 * Read the last state complete frames and explain them. This routine
10164 * expects to be called if the link went down during link negotiation
10165 * and initialization (LNI). That is, anywhere between polling and link up.
10166 */
10167static void check_lni_states(struct hfi1_pportdata *ppd)
10168{
10169 u32 last_local_state;
10170 u32 last_remote_state;
10171
10172 read_last_local_state(ppd->dd, &last_local_state);
10173 read_last_remote_state(ppd->dd, &last_remote_state);
10174
10175 /*
10176 * Don't report anything if there is nothing to report. A value of
10177 * 0 means the link was taken down while polling and there was no
10178 * training in-process.
10179 */
10180 if (last_local_state == 0 && last_remote_state == 0)
10181 return;
10182
10183 decode_state_complete(ppd, last_local_state, "transmitted");
10184 decode_state_complete(ppd, last_remote_state, "received");
10185}
10186
ec8a1423
DL		 10187/* wait for wait_ms for LINK_TRANSFER_ACTIVE to go to 1 */
10188static int wait_link_transfer_active(struct hfi1_devdata *dd, int wait_ms)
10189{
10190 u64 reg;
10191 unsigned long timeout;
10192
10193 /* watch LCB_STS_LINK_TRANSFER_ACTIVE */
10194 timeout = jiffies + msecs_to_jiffies(wait_ms);
10195 while (1) {
10196 reg = read_csr(dd, DC_LCB_STS_LINK_TRANSFER_ACTIVE);
10197 if (reg)
10198 break;
10199 if (time_after(jiffies, timeout)) {
10200 dd_dev_err(dd,
10201 "timeout waiting for LINK_TRANSFER_ACTIVE\n");
10202 return -ETIMEDOUT;
10203 }
10204 udelay(2);
10205 }
10206 return 0;
10207}
10208
10209/* called when the logical link state is not down as it should be */
10210static void force_logical_link_state_down(struct hfi1_pportdata *ppd)
10211{
10212 struct hfi1_devdata *dd = ppd->dd;
10213
10214 /*
10215 * Bring link up in LCB loopback
10216 */
10217 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1);
10218 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK,
10219 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK);
10220
10221 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0);
10222 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0);
10223 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110);
10224 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x2);
10225
10226 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
10227 (void)read_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET);
10228 udelay(3);
10229 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 1);
10230 write_csr(dd, DC_LCB_CFG_RUN, 1ull << DC_LCB_CFG_RUN_EN_SHIFT);
10231
10232 wait_link_transfer_active(dd, 100);
10233
10234 /*
10235 * Bring the link down again.
10236 */
10237 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1);
10238 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 0);
10239 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 0);
10240
10241 /* call again to adjust ppd->statusp, if needed */
10242 get_logical_state(ppd);
10243}
10244
77241056
MM		 10245/*
10246 * Helper for set_link_state(). Do not call except from that routine.
10247 * Expects ppd->hls_mutex to be held.
10248 *
10249 * @rem_reason value to be sent to the neighbor
10250 *
10251 * LinkDownReasons only set if transition succeeds.
10252 */
10253static int goto_offline(struct hfi1_pportdata *ppd, u8 rem_reason)
10254{
10255 struct hfi1_devdata *dd = ppd->dd;
10256 u32 pstate, previous_state;
77241056
MM		 10257 int ret;
10258 int do_transition;
10259 int do_wait;
10260
8688426b
MR		 10261 update_lcb_cache(dd);
10262
77241056
MM		 10263 previous_state = ppd->host_link_state;
10264 ppd->host_link_state = HLS_GOING_OFFLINE;
10265 pstate = read_physical_state(dd);
10266 if (pstate == PLS_OFFLINE) {
10267 do_transition = 0; /* in right state */
10268 do_wait = 0; /* ...no need to wait */
02d1008b 10269 } else if ((pstate & 0xf0) == PLS_OFFLINE) {
77241056
MM		 10270 do_transition = 0; /* in an offline transient state */
10271 do_wait = 1; /* ...wait for it to settle */
10272 } else {
10273 do_transition = 1; /* need to move to offline */
10274 do_wait = 1; /* ...will need to wait */
10275 }
10276
10277 if (do_transition) {
10278 ret = set_physical_link_state(dd,
bf640096 10279 (rem_reason << 8) | PLS_OFFLINE);
77241056
MM		 10280
10281 if (ret != HCMD_SUCCESS) {
10282 dd_dev_err(dd,
17fb4f29
JJ		 10283 "Failed to transition to Offline link state, return %d\n",
10284 ret);
77241056
MM		 10285 return -EINVAL;
10286 }
a9c05e35
BM		 10287 if (ppd->offline_disabled_reason ==
10288 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE))
77241056 10289 ppd->offline_disabled_reason =
a9c05e35 10290 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT);
77241056
MM		 10291 }
10292
10293 if (do_wait) {
10294 /* it can take a while for the link to go down */
dc060245 10295 ret = wait_phy_linkstate(dd, PLS_OFFLINE, 10000);
77241056
MM		 10296 if (ret < 0)
10297 return ret;
10298 }
10299
77241056
MM		 10300 /*
10301 * Now in charge of LCB - must be after the physical state is
10302 * offline.quiet and before host_link_state is changed.
10303 */
10304 set_host_lcb_access(dd);
10305 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
ec8a1423
DL		 10306
10307 /* make sure the logical state is also down */
10308 ret = wait_logical_linkstate(ppd, IB_PORT_DOWN, 1000);
10309 if (ret)
10310 force_logical_link_state_down(ppd);
10311
77241056
MM		 10312 ppd->host_link_state = HLS_LINK_COOLDOWN; /* LCB access allowed */
10313
8ebd4cf1
EH		 10314 if (ppd->port_type == PORT_TYPE_QSFP &&
10315 ppd->qsfp_info.limiting_active &&
10316 qsfp_mod_present(ppd)) {
765a6fac
DL		 10317 int ret;
10318
10319 ret = acquire_chip_resource(dd, qsfp_resource(dd), QSFP_WAIT);
10320 if (ret == 0) {
10321 set_qsfp_tx(ppd, 0);
10322 release_chip_resource(dd, qsfp_resource(dd));
10323 } else {
10324 /* not fatal, but should warn */
10325 dd_dev_err(dd,
10326 "Unable to acquire lock to turn off QSFP TX\n");
10327 }
8ebd4cf1
EH		 10328 }
10329
77241056
MM		 10330 /*
10331 * The LNI has a mandatory wait time after the physical state
10332 * moves to Offline.Quiet. The wait time may be different
10333 * depending on how the link went down. The 8051 firmware
10334 * will observe the needed wait time and only move to ready
10335 * when that is completed. The largest of the quiet timeouts
05087f3b
DL		 10336 * is 6s, so wait that long and then at least 0.5s more for
10337 * other transitions, and another 0.5s for a buffer.
77241056 10338 */
05087f3b 10339 ret = wait_fm_ready(dd, 7000);
77241056
MM		 10340 if (ret) {
10341 dd_dev_err(dd,
17fb4f29 10342 "After going offline, timed out waiting for the 8051 to become ready to accept host requests\n");
77241056
MM		 10343 /* state is really offline, so make it so */
10344 ppd->host_link_state = HLS_DN_OFFLINE;
10345 return ret;
10346 }
10347
10348 /*
10349 * The state is now offline and the 8051 is ready to accept host
10350 * requests.
10351 * - change our state
10352 * - notify others if we were previously in a linkup state
10353 */
10354 ppd->host_link_state = HLS_DN_OFFLINE;
10355 if (previous_state & HLS_UP) {
10356 /* went down while link was up */
10357 handle_linkup_change(dd, 0);
10358 } else if (previous_state
10359 & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) {
10360 /* went down while attempting link up */
6854c692 10361 check_lni_states(ppd);
77241056
MM		 10362 }
10363
10364 /* the active link width (downgrade) is 0 on link down */
10365 ppd->link_width_active = 0;
10366 ppd->link_width_downgrade_tx_active = 0;
10367 ppd->link_width_downgrade_rx_active = 0;
10368 ppd->current_egress_rate = 0;
10369 return 0;
10370}
10371
10372/* return the link state name */
10373static const char *link_state_name(u32 state)
10374{
10375 const char *name;
10376 int n = ilog2(state);
10377 static const char * const names[] = {
10378 [__HLS_UP_INIT_BP] = "INIT",
10379 [__HLS_UP_ARMED_BP] = "ARMED",
10380 [__HLS_UP_ACTIVE_BP] = "ACTIVE",
10381 [__HLS_DN_DOWNDEF_BP] = "DOWNDEF",
10382 [__HLS_DN_POLL_BP] = "POLL",
10383 [__HLS_DN_DISABLE_BP] = "DISABLE",
10384 [__HLS_DN_OFFLINE_BP] = "OFFLINE",
10385 [__HLS_VERIFY_CAP_BP] = "VERIFY_CAP",
10386 [__HLS_GOING_UP_BP] = "GOING_UP",
10387 [__HLS_GOING_OFFLINE_BP] = "GOING_OFFLINE",
10388 [__HLS_LINK_COOLDOWN_BP] = "LINK_COOLDOWN"
10389 };
10390
10391 name = n < ARRAY_SIZE(names) ? names[n] : NULL;
10392 return name ? name : "unknown";
10393}
10394
10395/* return the link state reason name */
10396static const char *link_state_reason_name(struct hfi1_pportdata *ppd, u32 state)
10397{
10398 if (state == HLS_UP_INIT) {
10399 switch (ppd->linkinit_reason) {
10400 case OPA_LINKINIT_REASON_LINKUP:
10401 return "(LINKUP)";
10402 case OPA_LINKINIT_REASON_FLAPPING:
10403 return "(FLAPPING)";
10404 case OPA_LINKINIT_OUTSIDE_POLICY:
10405 return "(OUTSIDE_POLICY)";
10406 case OPA_LINKINIT_QUARANTINED:
10407 return "(QUARANTINED)";
10408 case OPA_LINKINIT_INSUFIC_CAPABILITY:
10409 return "(INSUFIC_CAPABILITY)";
10410 default:
10411 break;
10412 }
10413 }
10414 return "";
10415}
10416
10417/*
10418 * driver_physical_state - convert the driver's notion of a port's
10419 * state (an HLS_*) into a physical state (a {IB,OPA}_PORTPHYSSTATE_*).
10420 * Return -1 (converted to a u32) to indicate error.
10421 */
10422u32 driver_physical_state(struct hfi1_pportdata *ppd)
10423{
10424 switch (ppd->host_link_state) {
10425 case HLS_UP_INIT:
10426 case HLS_UP_ARMED:
10427 case HLS_UP_ACTIVE:
10428 return IB_PORTPHYSSTATE_LINKUP;
10429 case HLS_DN_POLL:
10430 return IB_PORTPHYSSTATE_POLLING;
10431 case HLS_DN_DISABLE:
10432 return IB_PORTPHYSSTATE_DISABLED;
10433 case HLS_DN_OFFLINE:
10434 return OPA_PORTPHYSSTATE_OFFLINE;
10435 case HLS_VERIFY_CAP:
10436 return IB_PORTPHYSSTATE_POLLING;
10437 case HLS_GOING_UP:
10438 return IB_PORTPHYSSTATE_POLLING;
10439 case HLS_GOING_OFFLINE:
10440 return OPA_PORTPHYSSTATE_OFFLINE;
10441 case HLS_LINK_COOLDOWN:
10442 return OPA_PORTPHYSSTATE_OFFLINE;
10443 case HLS_DN_DOWNDEF:
10444 default:
10445 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n",
10446 ppd->host_link_state);
10447 return -1;
10448 }
10449}
10450
10451/*
10452 * driver_logical_state - convert the driver's notion of a port's
10453 * state (an HLS_*) into a logical state (a IB_PORT_*). Return -1
10454 * (converted to a u32) to indicate error.
10455 */
10456u32 driver_logical_state(struct hfi1_pportdata *ppd)
10457{
0c7f77af 10458 if (ppd->host_link_state && (ppd->host_link_state & HLS_DOWN))
77241056
MM		 10459 return IB_PORT_DOWN;
10460
10461 switch (ppd->host_link_state & HLS_UP) {
10462 case HLS_UP_INIT:
10463 return IB_PORT_INIT;
10464 case HLS_UP_ARMED:
10465 return IB_PORT_ARMED;
10466 case HLS_UP_ACTIVE:
10467 return IB_PORT_ACTIVE;
10468 default:
10469 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n",
10470 ppd->host_link_state);
10471 return -1;
10472 }
10473}
10474
10475void set_link_down_reason(struct hfi1_pportdata *ppd, u8 lcl_reason,
10476 u8 neigh_reason, u8 rem_reason)
10477{
10478 if (ppd->local_link_down_reason.latest == 0 &&
10479 ppd->neigh_link_down_reason.latest == 0) {
10480 ppd->local_link_down_reason.latest = lcl_reason;
10481 ppd->neigh_link_down_reason.latest = neigh_reason;
10482 ppd->remote_link_down_reason = rem_reason;
10483 }
10484}
10485
10486/*
10487 * Change the physical and/or logical link state.
10488 *
10489 * Do not call this routine while inside an interrupt. It contains
10490 * calls to routines that can take multiple seconds to finish.
10491 *
10492 * Returns 0 on success, -errno on failure.
10493 */
10494int set_link_state(struct hfi1_pportdata *ppd, u32 state)
10495{
10496 struct hfi1_devdata *dd = ppd->dd;
10497 struct ib_event event = {.device = NULL};
10498 int ret1, ret = 0;
77241056
MM		 10499 int orig_new_state, poll_bounce;
10500
10501 mutex_lock(&ppd->hls_lock);
10502
10503 orig_new_state = state;
10504 if (state == HLS_DN_DOWNDEF)
10505 state = dd->link_default;
10506
10507 /* interpret poll -> poll as a link bounce */
d0d236ea
JJ		 10508 poll_bounce = ppd->host_link_state == HLS_DN_POLL &&
10509 state == HLS_DN_POLL;
77241056
MM		 10510
10511 dd_dev_info(dd, "%s: current %s, new %s %s%s\n", __func__,
17fb4f29
JJ		 10512 link_state_name(ppd->host_link_state),
10513 link_state_name(orig_new_state),
10514 poll_bounce ? "(bounce) " : "",
10515 link_state_reason_name(ppd, state));
77241056 10516
77241056
MM		 10517 /*
10518 * If we're going to a (HLS_*) link state that implies the logical
10519 * link state is neither of (IB_PORT_ARMED, IB_PORT_ACTIVE), then
10520 * reset is_sm_config_started to 0.
10521 */
10522 if (!(state & (HLS_UP_ARMED | HLS_UP_ACTIVE)))
10523 ppd->is_sm_config_started = 0;
10524
10525 /*
10526 * Do nothing if the states match. Let a poll to poll link bounce
10527 * go through.
10528 */
10529 if (ppd->host_link_state == state && !poll_bounce)
10530 goto done;
10531
10532 switch (state) {
10533 case HLS_UP_INIT:
d0d236ea
JJ		 10534 if (ppd->host_link_state == HLS_DN_POLL &&
10535 (quick_linkup || dd->icode == ICODE_FUNCTIONAL_SIMULATOR)) {
77241056
MM		 10536 /*
10537 * Quick link up jumps from polling to here.
10538 *
10539 * Whether in normal or loopback mode, the
10540 * simulator jumps from polling to link up.
10541 * Accept that here.
10542 */
17fb4f29 10543 /* OK */
77241056
MM		 10544 } else if (ppd->host_link_state != HLS_GOING_UP) {
10545 goto unexpected;
10546 }
10547
77241056
MM		 10548 ret = wait_logical_linkstate(ppd, IB_PORT_INIT, 1000);
10549 if (ret) {
77241056 10550 dd_dev_err(dd,
17fb4f29
JJ		 10551 "%s: logical state did not change to INIT\n",
10552 __func__);
77241056
MM		 10553 } else {
10554 /* clear old transient LINKINIT_REASON code */
10555 if (ppd->linkinit_reason >= OPA_LINKINIT_REASON_CLEAR)
10556 ppd->linkinit_reason =
10557 OPA_LINKINIT_REASON_LINKUP;
10558
10559 /* enable the port */
10560 add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
10561
10562 handle_linkup_change(dd, 1);
98b9ee20 10563 ppd->host_link_state = HLS_UP_INIT;
77241056
MM		 10564 }
10565 break;
10566 case HLS_UP_ARMED:
10567 if (ppd->host_link_state != HLS_UP_INIT)
10568 goto unexpected;
10569
10570 ppd->host_link_state = HLS_UP_ARMED;
10571 set_logical_state(dd, LSTATE_ARMED);
10572 ret = wait_logical_linkstate(ppd, IB_PORT_ARMED, 1000);
10573 if (ret) {
10574 /* logical state didn't change, stay at init */
10575 ppd->host_link_state = HLS_UP_INIT;
10576 dd_dev_err(dd,
17fb4f29
JJ		 10577 "%s: logical state did not change to ARMED\n",
10578 __func__);
77241056
MM		 10579 }
10580 /*
10581 * The simulator does not currently implement SMA messages,
10582 * so neighbor_normal is not set. Set it here when we first
10583 * move to Armed.
10584 */
10585 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
10586 ppd->neighbor_normal = 1;
10587 break;
10588 case HLS_UP_ACTIVE:
10589 if (ppd->host_link_state != HLS_UP_ARMED)
10590 goto unexpected;
10591
10592 ppd->host_link_state = HLS_UP_ACTIVE;
10593 set_logical_state(dd, LSTATE_ACTIVE);
10594 ret = wait_logical_linkstate(ppd, IB_PORT_ACTIVE, 1000);
10595 if (ret) {
10596 /* logical state didn't change, stay at armed */
10597 ppd->host_link_state = HLS_UP_ARMED;
10598 dd_dev_err(dd,
17fb4f29
JJ		 10599 "%s: logical state did not change to ACTIVE\n",
10600 __func__);
77241056 10601 } else {
77241056
MM		 10602 /* tell all engines to go running */
10603 sdma_all_running(dd);
10604
10605 /* Signal the IB layer that the port has went active */
ec3f2c12 10606 event.device = &dd->verbs_dev.rdi.ibdev;
77241056
MM		 10607 event.element.port_num = ppd->port;
10608 event.event = IB_EVENT_PORT_ACTIVE;
10609 }
10610 break;
10611 case HLS_DN_POLL:
10612 if ((ppd->host_link_state == HLS_DN_DISABLE ||
10613 ppd->host_link_state == HLS_DN_OFFLINE) &&
10614 dd->dc_shutdown)
10615 dc_start(dd);
10616 /* Hand LED control to the DC */
10617 write_csr(dd, DCC_CFG_LED_CNTRL, 0);
10618
10619 if (ppd->host_link_state != HLS_DN_OFFLINE) {
10620 u8 tmp = ppd->link_enabled;
10621
10622 ret = goto_offline(ppd, ppd->remote_link_down_reason);
10623 if (ret) {
10624 ppd->link_enabled = tmp;
10625 break;
10626 }
10627 ppd->remote_link_down_reason = 0;
10628
10629 if (ppd->driver_link_ready)
10630 ppd->link_enabled = 1;
10631 }
10632
fb9036dd 10633 set_all_slowpath(ppd->dd);
77241056
MM		 10634 ret = set_local_link_attributes(ppd);
10635 if (ret)
10636 break;
10637
10638 ppd->port_error_action = 0;
10639 ppd->host_link_state = HLS_DN_POLL;
10640
10641 if (quick_linkup) {
10642 /* quick linkup does not go into polling */
10643 ret = do_quick_linkup(dd);
10644 } else {
10645 ret1 = set_physical_link_state(dd, PLS_POLLING);
10646 if (ret1 != HCMD_SUCCESS) {
10647 dd_dev_err(dd,
17fb4f29
JJ		 10648 "Failed to transition to Polling link state, return 0x%x\n",
10649 ret1);
77241056
MM		 10650 ret = -EINVAL;
10651 }
10652 }
a9c05e35
BM		 10653 ppd->offline_disabled_reason =
10654 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE);
77241056
MM		 10655 /*
10656 * If an error occurred above, go back to offline. The
10657 * caller may reschedule another attempt.
10658 */
10659 if (ret)
10660 goto_offline(ppd, 0);
10661 break;
10662 case HLS_DN_DISABLE:
10663 /* link is disabled */
10664 ppd->link_enabled = 0;
10665
10666 /* allow any state to transition to disabled */
10667
10668 /* must transition to offline first */
10669 if (ppd->host_link_state != HLS_DN_OFFLINE) {
10670 ret = goto_offline(ppd, ppd->remote_link_down_reason);
10671 if (ret)
10672 break;
10673 ppd->remote_link_down_reason = 0;
10674 }
10675
db069ecb
MR		 10676 if (!dd->dc_shutdown) {
10677 ret1 = set_physical_link_state(dd, PLS_DISABLED);
10678 if (ret1 != HCMD_SUCCESS) {
10679 dd_dev_err(dd,
10680 "Failed to transition to Disabled link state, return 0x%x\n",
10681 ret1);
10682 ret = -EINVAL;
10683 break;
10684 }
10685 dc_shutdown(dd);
77241056
MM		 10686 }
10687 ppd->host_link_state = HLS_DN_DISABLE;
77241056
MM		 10688 break;
10689 case HLS_DN_OFFLINE:
10690 if (ppd->host_link_state == HLS_DN_DISABLE)
10691 dc_start(dd);
10692
10693 /* allow any state to transition to offline */
10694 ret = goto_offline(ppd, ppd->remote_link_down_reason);
10695 if (!ret)
10696 ppd->remote_link_down_reason = 0;
10697 break;
10698 case HLS_VERIFY_CAP:
10699 if (ppd->host_link_state != HLS_DN_POLL)
10700 goto unexpected;
10701 ppd->host_link_state = HLS_VERIFY_CAP;
10702 break;
10703 case HLS_GOING_UP:
10704 if (ppd->host_link_state != HLS_VERIFY_CAP)
10705 goto unexpected;
10706
10707 ret1 = set_physical_link_state(dd, PLS_LINKUP);
10708 if (ret1 != HCMD_SUCCESS) {
10709 dd_dev_err(dd,
17fb4f29
JJ		 10710 "Failed to transition to link up state, return 0x%x\n",
10711 ret1);
77241056
MM		 10712 ret = -EINVAL;
10713 break;
10714 }
10715 ppd->host_link_state = HLS_GOING_UP;
10716 break;
10717
10718 case HLS_GOING_OFFLINE: /* transient within goto_offline() */
10719 case HLS_LINK_COOLDOWN: /* transient within goto_offline() */
10720 default:
10721 dd_dev_info(dd, "%s: state 0x%x: not supported\n",
17fb4f29 10722 __func__, state);
77241056
MM		 10723 ret = -EINVAL;
10724 break;
10725 }
10726
77241056
MM		 10727 goto done;
10728
10729unexpected:
10730 dd_dev_err(dd, "%s: unexpected state transition from %s to %s\n",
17fb4f29
JJ		 10731 __func__, link_state_name(ppd->host_link_state),
10732 link_state_name(state));
77241056
MM		 10733 ret = -EINVAL;
10734
10735done:
10736 mutex_unlock(&ppd->hls_lock);
10737
10738 if (event.device)
10739 ib_dispatch_event(&event);
10740
10741 return ret;
10742}
10743
10744int hfi1_set_ib_cfg(struct hfi1_pportdata *ppd, int which, u32 val)
10745{
10746 u64 reg;
10747 int ret = 0;
10748
10749 switch (which) {
10750 case HFI1_IB_CFG_LIDLMC:
10751 set_lidlmc(ppd);
10752 break;
10753 case HFI1_IB_CFG_VL_HIGH_LIMIT:
10754 /*
10755 * The VL Arbitrator high limit is sent in units of 4k
10756 * bytes, while HFI stores it in units of 64 bytes.
10757 */
8638b77f 10758 val *= 4096 / 64;
77241056
MM		 10759 reg = ((u64)val & SEND_HIGH_PRIORITY_LIMIT_LIMIT_MASK)
10760 << SEND_HIGH_PRIORITY_LIMIT_LIMIT_SHIFT;
10761 write_csr(ppd->dd, SEND_HIGH_PRIORITY_LIMIT, reg);
10762 break;
10763 case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
10764 /* HFI only supports POLL as the default link down state */
10765 if (val != HLS_DN_POLL)
10766 ret = -EINVAL;
10767 break;
10768 case HFI1_IB_CFG_OP_VLS:
10769 if (ppd->vls_operational != val) {
10770 ppd->vls_operational = val;
10771 if (!ppd->port)
10772 ret = -EINVAL;
77241056
MM		 10773 }
10774 break;
10775 /*
10776 * For link width, link width downgrade, and speed enable, always AND
10777 * the setting with what is actually supported. This has two benefits.
10778 * First, enabled can't have unsupported values, no matter what the
10779 * SM or FM might want. Second, the ALL_SUPPORTED wildcards that mean
10780 * "fill in with your supported value" have all the bits in the
10781 * field set, so simply ANDing with supported has the desired result.
10782 */
10783 case HFI1_IB_CFG_LWID_ENB: /* set allowed Link-width */
10784 ppd->link_width_enabled = val & ppd->link_width_supported;
10785 break;
10786 case HFI1_IB_CFG_LWID_DG_ENB: /* set allowed link width downgrade */
10787 ppd->link_width_downgrade_enabled =
10788 val & ppd->link_width_downgrade_supported;
10789 break;
10790 case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */
10791 ppd->link_speed_enabled = val & ppd->link_speed_supported;
10792 break;
10793 case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
10794 /*
10795 * HFI does not follow IB specs, save this value
10796 * so we can report it, if asked.
10797 */
10798 ppd->overrun_threshold = val;
10799 break;
10800 case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
10801 /*
10802 * HFI does not follow IB specs, save this value
10803 * so we can report it, if asked.
10804 */
10805 ppd->phy_error_threshold = val;
10806 break;
10807
10808 case HFI1_IB_CFG_MTU:
10809 set_send_length(ppd);
10810 break;
10811
10812 case HFI1_IB_CFG_PKEYS:
10813 if (HFI1_CAP_IS_KSET(PKEY_CHECK))
10814 set_partition_keys(ppd);
10815 break;
10816
10817 default:
10818 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
10819 dd_dev_info(ppd->dd,
17fb4f29
JJ		 10820 "%s: which %s, val 0x%x: not implemented\n",
10821 __func__, ib_cfg_name(which), val);
77241056
MM		 10822 break;
10823 }
10824 return ret;
10825}
10826
10827/* begin functions related to vl arbitration table caching */
10828static void init_vl_arb_caches(struct hfi1_pportdata *ppd)
10829{
10830 int i;
10831
10832 BUILD_BUG_ON(VL_ARB_TABLE_SIZE !=
10833 VL_ARB_LOW_PRIO_TABLE_SIZE);
10834 BUILD_BUG_ON(VL_ARB_TABLE_SIZE !=
10835 VL_ARB_HIGH_PRIO_TABLE_SIZE);
10836
10837 /*
10838 * Note that we always return values directly from the
10839 * 'vl_arb_cache' (and do no CSR reads) in response to a
10840 * 'Get(VLArbTable)'. This is obviously correct after a
10841 * 'Set(VLArbTable)', since the cache will then be up to
10842 * date. But it's also correct prior to any 'Set(VLArbTable)'
10843 * since then both the cache, and the relevant h/w registers
10844 * will be zeroed.
10845 */
10846
10847 for (i = 0; i < MAX_PRIO_TABLE; i++)
10848 spin_lock_init(&ppd->vl_arb_cache[i].lock);
10849}
10850
10851/*
10852 * vl_arb_lock_cache
10853 *
10854 * All other vl_arb_* functions should be called only after locking
10855 * the cache.
10856 */
10857static inline struct vl_arb_cache *
10858vl_arb_lock_cache(struct hfi1_pportdata *ppd, int idx)
10859{
10860 if (idx != LO_PRIO_TABLE && idx != HI_PRIO_TABLE)
10861 return NULL;
10862 spin_lock(&ppd->vl_arb_cache[idx].lock);
10863 return &ppd->vl_arb_cache[idx];
10864}
10865
10866static inline void vl_arb_unlock_cache(struct hfi1_pportdata *ppd, int idx)
10867{
10868 spin_unlock(&ppd->vl_arb_cache[idx].lock);
10869}
10870
10871static void vl_arb_get_cache(struct vl_arb_cache *cache,
10872 struct ib_vl_weight_elem *vl)
10873{
10874 memcpy(vl, cache->table, VL_ARB_TABLE_SIZE * sizeof(*vl));
10875}
10876
10877static void vl_arb_set_cache(struct vl_arb_cache *cache,
10878 struct ib_vl_weight_elem *vl)
10879{
10880 memcpy(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl));
10881}
10882
10883static int vl_arb_match_cache(struct vl_arb_cache *cache,
10884 struct ib_vl_weight_elem *vl)
10885{
10886 return !memcmp(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl));
10887}
f4d507cd 10888
77241056
MM		 10889/* end functions related to vl arbitration table caching */
10890
10891static int set_vl_weights(struct hfi1_pportdata *ppd, u32 target,
10892 u32 size, struct ib_vl_weight_elem *vl)
10893{
10894 struct hfi1_devdata *dd = ppd->dd;
10895 u64 reg;
10896 unsigned int i, is_up = 0;
10897 int drain, ret = 0;
10898
10899 mutex_lock(&ppd->hls_lock);
10900
10901 if (ppd->host_link_state & HLS_UP)
10902 is_up = 1;
10903
10904 drain = !is_ax(dd) && is_up;
10905
10906 if (drain)
10907 /*
10908 * Before adjusting VL arbitration weights, empty per-VL
10909 * FIFOs, otherwise a packet whose VL weight is being
10910 * set to 0 could get stuck in a FIFO with no chance to
10911 * egress.
10912 */
10913 ret = stop_drain_data_vls(dd);
10914
10915 if (ret) {
10916 dd_dev_err(
10917 dd,
10918 "%s: cannot stop/drain VLs - refusing to change VL arbitration weights\n",
10919 __func__);
10920 goto err;
10921 }
10922
10923 for (i = 0; i < size; i++, vl++) {
10924 /*
10925 * NOTE: The low priority shift and mask are used here, but
10926 * they are the same for both the low and high registers.
10927 */
10928 reg = (((u64)vl->vl & SEND_LOW_PRIORITY_LIST_VL_MASK)
10929 << SEND_LOW_PRIORITY_LIST_VL_SHIFT)
10930 | (((u64)vl->weight
10931 & SEND_LOW_PRIORITY_LIST_WEIGHT_MASK)
10932 << SEND_LOW_PRIORITY_LIST_WEIGHT_SHIFT);
10933 write_csr(dd, target + (i * 8), reg);
10934 }
10935 pio_send_control(dd, PSC_GLOBAL_VLARB_ENABLE);
10936
10937 if (drain)
10938 open_fill_data_vls(dd); /* reopen all VLs */
10939
10940err:
10941 mutex_unlock(&ppd->hls_lock);
10942
10943 return ret;
10944}
10945
10946/*
10947 * Read one credit merge VL register.
10948 */
10949static void read_one_cm_vl(struct hfi1_devdata *dd, u32 csr,
10950 struct vl_limit *vll)
10951{
10952 u64 reg = read_csr(dd, csr);
10953
10954 vll->dedicated = cpu_to_be16(
10955 (reg >> SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT)
10956 & SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_MASK);
10957 vll->shared = cpu_to_be16(
10958 (reg >> SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT)
10959 & SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_MASK);
10960}
10961
10962/*
10963 * Read the current credit merge limits.
10964 */
10965static int get_buffer_control(struct hfi1_devdata *dd,
10966 struct buffer_control *bc, u16 *overall_limit)
10967{
10968 u64 reg;
10969 int i;
10970
10971 /* not all entries are filled in */
10972 memset(bc, 0, sizeof(*bc));
10973
10974 /* OPA and HFI have a 1-1 mapping */
10975 for (i = 0; i < TXE_NUM_DATA_VL; i++)
8638b77f 10976 read_one_cm_vl(dd, SEND_CM_CREDIT_VL + (8 * i), &bc->vl[i]);
77241056
MM		 10977
10978 /* NOTE: assumes that VL* and VL15 CSRs are bit-wise identical */
10979 read_one_cm_vl(dd, SEND_CM_CREDIT_VL15, &bc->vl[15]);
10980
10981 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
10982 bc->overall_shared_limit = cpu_to_be16(
10983 (reg >> SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT)
10984 & SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_MASK);
10985 if (overall_limit)
10986 *overall_limit = (reg
10987 >> SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT)
10988 & SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_MASK;
10989 return sizeof(struct buffer_control);
10990}
10991
10992static int get_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp)
10993{
10994 u64 reg;
10995 int i;
10996
10997 /* each register contains 16 SC->VLnt mappings, 4 bits each */
10998 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_15_0);
10999 for (i = 0; i < sizeof(u64); i++) {
11000 u8 byte = *(((u8 *)&reg) + i);
11001
11002 dp->vlnt[2 * i] = byte & 0xf;
11003 dp->vlnt[(2 * i) + 1] = (byte & 0xf0) >> 4;
11004 }
11005
11006 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_31_16);
11007 for (i = 0; i < sizeof(u64); i++) {
11008 u8 byte = *(((u8 *)&reg) + i);
11009
11010 dp->vlnt[16 + (2 * i)] = byte & 0xf;
11011 dp->vlnt[16 + (2 * i) + 1] = (byte & 0xf0) >> 4;
11012 }
11013 return sizeof(struct sc2vlnt);
11014}
11015
11016static void get_vlarb_preempt(struct hfi1_devdata *dd, u32 nelems,
11017 struct ib_vl_weight_elem *vl)
11018{
11019 unsigned int i;
11020
11021 for (i = 0; i < nelems; i++, vl++) {
11022 vl->vl = 0xf;
11023 vl->weight = 0;
11024 }
11025}
11026
11027static void set_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp)
11028{
11029 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0,
17fb4f29
JJ		 11030 DC_SC_VL_VAL(15_0,
11031 0, dp->vlnt[0] & 0xf,
11032 1, dp->vlnt[1] & 0xf,
11033 2, dp->vlnt[2] & 0xf,
11034 3, dp->vlnt[3] & 0xf,
11035 4, dp->vlnt[4] & 0xf,
11036 5, dp->vlnt[5] & 0xf,
11037 6, dp->vlnt[6] & 0xf,
11038 7, dp->vlnt[7] & 0xf,
11039 8, dp->vlnt[8] & 0xf,
11040 9, dp->vlnt[9] & 0xf,
11041 10, dp->vlnt[10] & 0xf,
11042 11, dp->vlnt[11] & 0xf,
11043 12, dp->vlnt[12] & 0xf,
11044 13, dp->vlnt[13] & 0xf,
11045 14, dp->vlnt[14] & 0xf,
11046 15, dp->vlnt[15] & 0xf));
77241056 11047 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16,
17fb4f29
JJ		 11048 DC_SC_VL_VAL(31_16,
11049 16, dp->vlnt[16] & 0xf,
11050 17, dp->vlnt[17] & 0xf,
11051 18, dp->vlnt[18] & 0xf,
11052 19, dp->vlnt[19] & 0xf,
11053 20, dp->vlnt[20] & 0xf,
11054 21, dp->vlnt[21] & 0xf,
11055 22, dp->vlnt[22] & 0xf,
11056 23, dp->vlnt[23] & 0xf,
11057 24, dp->vlnt[24] & 0xf,
11058 25, dp->vlnt[25] & 0xf,
11059 26, dp->vlnt[26] & 0xf,
11060 27, dp->vlnt[27] & 0xf,
11061 28, dp->vlnt[28] & 0xf,
11062 29, dp->vlnt[29] & 0xf,
11063 30, dp->vlnt[30] & 0xf,
11064 31, dp->vlnt[31] & 0xf));
77241056
MM		 11065}
11066
11067static void nonzero_msg(struct hfi1_devdata *dd, int idx, const char *what,
11068 u16 limit)
11069{
11070 if (limit != 0)
11071 dd_dev_info(dd, "Invalid %s limit %d on VL %d, ignoring\n",
17fb4f29 11072 what, (int)limit, idx);
77241056
MM		 11073}
11074
11075/* change only the shared limit portion of SendCmGLobalCredit */
11076static void set_global_shared(struct hfi1_devdata *dd, u16 limit)
11077{
11078 u64 reg;
11079
11080 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
11081 reg &= ~SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK;
11082 reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT;
11083 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
11084}
11085
11086/* change only the total credit limit portion of SendCmGLobalCredit */
11087static void set_global_limit(struct hfi1_devdata *dd, u16 limit)
11088{
11089 u64 reg;
11090
11091 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
11092 reg &= ~SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK;
11093 reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT;
11094 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
11095}
11096
11097/* set the given per-VL shared limit */
11098static void set_vl_shared(struct hfi1_devdata *dd, int vl, u16 limit)
11099{
11100 u64 reg;
11101 u32 addr;
11102
11103 if (vl < TXE_NUM_DATA_VL)
11104 addr = SEND_CM_CREDIT_VL + (8 * vl);
11105 else
11106 addr = SEND_CM_CREDIT_VL15;
11107
11108 reg = read_csr(dd, addr);
11109 reg &= ~SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SMASK;
11110 reg |= (u64)limit << SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT;
11111 write_csr(dd, addr, reg);
11112}
11113
11114/* set the given per-VL dedicated limit */
11115static void set_vl_dedicated(struct hfi1_devdata *dd, int vl, u16 limit)
11116{
11117 u64 reg;
11118 u32 addr;
11119
11120 if (vl < TXE_NUM_DATA_VL)
11121 addr = SEND_CM_CREDIT_VL + (8 * vl);
11122 else
11123 addr = SEND_CM_CREDIT_VL15;
11124
11125 reg = read_csr(dd, addr);
11126 reg &= ~SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SMASK;
11127 reg |= (u64)limit << SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT;
11128 write_csr(dd, addr, reg);
11129}
11130
11131/* spin until the given per-VL status mask bits clear */
11132static void wait_for_vl_status_clear(struct hfi1_devdata *dd, u64 mask,
11133 const char *which)
11134{
11135 unsigned long timeout;
11136 u64 reg;
11137
11138 timeout = jiffies + msecs_to_jiffies(VL_STATUS_CLEAR_TIMEOUT);
11139 while (1) {
11140 reg = read_csr(dd, SEND_CM_CREDIT_USED_STATUS) & mask;
11141
11142 if (reg == 0)
11143 return; /* success */
11144 if (time_after(jiffies, timeout))
11145 break; /* timed out */
11146 udelay(1);
11147 }
11148
11149 dd_dev_err(dd,
17fb4f29
JJ		 11150 "%s credit change status not clearing after %dms, mask 0x%llx, not clear 0x%llx\n",
11151 which, VL_STATUS_CLEAR_TIMEOUT, mask, reg);
77241056
MM		 11152 /*
11153 * If this occurs, it is likely there was a credit loss on the link.
11154 * The only recovery from that is a link bounce.
11155 */
11156 dd_dev_err(dd,
17fb4f29 11157 "Continuing anyway. A credit loss may occur. Suggest a link bounce\n");
77241056
MM		 11158}
11159
11160/*
11161 * The number of credits on the VLs may be changed while everything
11162 * is "live", but the following algorithm must be followed due to
11163 * how the hardware is actually implemented. In particular,
11164 * Return_Credit_Status[] is the only correct status check.
11165 *
11166 * if (reducing Global_Shared_Credit_Limit or any shared limit changing)
11167 * set Global_Shared_Credit_Limit = 0
11168 * use_all_vl = 1
11169 * mask0 = all VLs that are changing either dedicated or shared limits
11170 * set Shared_Limit[mask0] = 0
11171 * spin until Return_Credit_Status[use_all_vl ? all VL : mask0] == 0
11172 * if (changing any dedicated limit)
11173 * mask1 = all VLs that are lowering dedicated limits
11174 * lower Dedicated_Limit[mask1]
11175 * spin until Return_Credit_Status[mask1] == 0
11176 * raise Dedicated_Limits
11177 * raise Shared_Limits
11178 * raise Global_Shared_Credit_Limit
11179 *
11180 * lower = if the new limit is lower, set the limit to the new value
11181 * raise = if the new limit is higher than the current value (may be changed
11182 * earlier in the algorithm), set the new limit to the new value
11183 */
8a4d3444
MM		 11184int set_buffer_control(struct hfi1_pportdata *ppd,
11185 struct buffer_control *new_bc)
77241056 11186{
8a4d3444 11187 struct hfi1_devdata *dd = ppd->dd;
77241056
MM		 11188 u64 changing_mask, ld_mask, stat_mask;
11189 int change_count;
11190 int i, use_all_mask;
11191 int this_shared_changing;
8a4d3444 11192 int vl_count = 0, ret;
77241056
MM		 11193 /*
11194 * A0: add the variable any_shared_limit_changing below and in the
11195 * algorithm above. If removing A0 support, it can be removed.
11196 */
11197 int any_shared_limit_changing;
11198 struct buffer_control cur_bc;
11199 u8 changing[OPA_MAX_VLS];
11200 u8 lowering_dedicated[OPA_MAX_VLS];
11201 u16 cur_total;
11202 u32 new_total = 0;
11203 const u64 all_mask =
11204 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK
11205 | SEND_CM_CREDIT_USED_STATUS_VL1_RETURN_CREDIT_STATUS_SMASK
11206 | SEND_CM_CREDIT_USED_STATUS_VL2_RETURN_CREDIT_STATUS_SMASK
11207 | SEND_CM_CREDIT_USED_STATUS_VL3_RETURN_CREDIT_STATUS_SMASK
11208 | SEND_CM_CREDIT_USED_STATUS_VL4_RETURN_CREDIT_STATUS_SMASK
11209 | SEND_CM_CREDIT_USED_STATUS_VL5_RETURN_CREDIT_STATUS_SMASK
11210 | SEND_CM_CREDIT_USED_STATUS_VL6_RETURN_CREDIT_STATUS_SMASK
11211 | SEND_CM_CREDIT_USED_STATUS_VL7_RETURN_CREDIT_STATUS_SMASK
11212 | SEND_CM_CREDIT_USED_STATUS_VL15_RETURN_CREDIT_STATUS_SMASK;
11213
11214#define valid_vl(idx) ((idx) < TXE_NUM_DATA_VL || (idx) == 15)
11215#define NUM_USABLE_VLS 16 /* look at VL15 and less */
11216
77241056
MM		 11217 /* find the new total credits, do sanity check on unused VLs */
11218 for (i = 0; i < OPA_MAX_VLS; i++) {
11219 if (valid_vl(i)) {
11220 new_total += be16_to_cpu(new_bc->vl[i].dedicated);
11221 continue;
11222 }
11223 nonzero_msg(dd, i, "dedicated",
17fb4f29 11224 be16_to_cpu(new_bc->vl[i].dedicated));
77241056 11225 nonzero_msg(dd, i, "shared",
17fb4f29 11226 be16_to_cpu(new_bc->vl[i].shared));
77241056
MM		 11227 new_bc->vl[i].dedicated = 0;
11228 new_bc->vl[i].shared = 0;
11229 }
11230 new_total += be16_to_cpu(new_bc->overall_shared_limit);
bff14bb6 11231
77241056
MM		 11232 /* fetch the current values */
11233 get_buffer_control(dd, &cur_bc, &cur_total);
11234
11235 /*
11236 * Create the masks we will use.
11237 */
11238 memset(changing, 0, sizeof(changing));
11239 memset(lowering_dedicated, 0, sizeof(lowering_dedicated));
4d114fdd
JJ		 11240 /*
11241 * NOTE: Assumes that the individual VL bits are adjacent and in
11242 * increasing order
11243 */
77241056
MM		 11244 stat_mask =
11245 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK;
11246 changing_mask = 0;
11247 ld_mask = 0;
11248 change_count = 0;
11249 any_shared_limit_changing = 0;
11250 for (i = 0; i < NUM_USABLE_VLS; i++, stat_mask <<= 1) {
11251 if (!valid_vl(i))
11252 continue;
11253 this_shared_changing = new_bc->vl[i].shared
11254 != cur_bc.vl[i].shared;
11255 if (this_shared_changing)
11256 any_shared_limit_changing = 1;
d0d236ea
JJ		 11257 if (new_bc->vl[i].dedicated != cur_bc.vl[i].dedicated ||
11258 this_shared_changing) {
77241056
MM		 11259 changing[i] = 1;
11260 changing_mask |= stat_mask;
11261 change_count++;
11262 }
11263 if (be16_to_cpu(new_bc->vl[i].dedicated) <
11264 be16_to_cpu(cur_bc.vl[i].dedicated)) {
11265 lowering_dedicated[i] = 1;
11266 ld_mask |= stat_mask;
11267 }
11268 }
11269
11270 /* bracket the credit change with a total adjustment */
11271 if (new_total > cur_total)
11272 set_global_limit(dd, new_total);
11273
11274 /*
11275 * Start the credit change algorithm.
11276 */
11277 use_all_mask = 0;
11278 if ((be16_to_cpu(new_bc->overall_shared_limit) <
995deafa
MM		 11279 be16_to_cpu(cur_bc.overall_shared_limit)) ||
11280 (is_ax(dd) && any_shared_limit_changing)) {
77241056
MM		 11281 set_global_shared(dd, 0);
11282 cur_bc.overall_shared_limit = 0;
11283 use_all_mask = 1;
11284 }
11285
11286 for (i = 0; i < NUM_USABLE_VLS; i++) {
11287 if (!valid_vl(i))
11288 continue;
11289
11290 if (changing[i]) {
11291 set_vl_shared(dd, i, 0);
11292 cur_bc.vl[i].shared = 0;
11293 }
11294 }
11295
11296 wait_for_vl_status_clear(dd, use_all_mask ? all_mask : changing_mask,
17fb4f29 11297 "shared");
77241056
MM		 11298
11299 if (change_count > 0) {
11300 for (i = 0; i < NUM_USABLE_VLS; i++) {
11301 if (!valid_vl(i))
11302 continue;
11303
11304 if (lowering_dedicated[i]) {
11305 set_vl_dedicated(dd, i,
17fb4f29
JJ		 11306 be16_to_cpu(new_bc->
11307 vl[i].dedicated));
77241056
MM		 11308 cur_bc.vl[i].dedicated =
11309 new_bc->vl[i].dedicated;
11310 }
11311 }
11312
11313 wait_for_vl_status_clear(dd, ld_mask, "dedicated");
11314
11315 /* now raise all dedicated that are going up */
11316 for (i = 0; i < NUM_USABLE_VLS; i++) {
11317 if (!valid_vl(i))
11318 continue;
11319
11320 if (be16_to_cpu(new_bc->vl[i].dedicated) >
11321 be16_to_cpu(cur_bc.vl[i].dedicated))
11322 set_vl_dedicated(dd, i,
17fb4f29
JJ		 11323 be16_to_cpu(new_bc->
11324 vl[i].dedicated));
77241056
MM		 11325 }
11326 }
11327
11328 /* next raise all shared that are going up */
11329 for (i = 0; i < NUM_USABLE_VLS; i++) {
11330 if (!valid_vl(i))
11331 continue;
11332
11333 if (be16_to_cpu(new_bc->vl[i].shared) >
11334 be16_to_cpu(cur_bc.vl[i].shared))
11335 set_vl_shared(dd, i, be16_to_cpu(new_bc->vl[i].shared));
11336 }
11337
11338 /* finally raise the global shared */
11339 if (be16_to_cpu(new_bc->overall_shared_limit) >
17fb4f29 11340 be16_to_cpu(cur_bc.overall_shared_limit))
77241056 11341 set_global_shared(dd,
17fb4f29 11342 be16_to_cpu(new_bc->overall_shared_limit));
77241056
MM		 11343
11344 /* bracket the credit change with a total adjustment */
11345 if (new_total < cur_total)
11346 set_global_limit(dd, new_total);
8a4d3444
MM		 11347
11348 /*
11349 * Determine the actual number of operational VLS using the number of
11350 * dedicated and shared credits for each VL.
11351 */
11352 if (change_count > 0) {
11353 for (i = 0; i < TXE_NUM_DATA_VL; i++)
11354 if (be16_to_cpu(new_bc->vl[i].dedicated) > 0 ||
11355 be16_to_cpu(new_bc->vl[i].shared) > 0)
11356 vl_count++;
11357 ppd->actual_vls_operational = vl_count;
11358 ret = sdma_map_init(dd, ppd->port - 1, vl_count ?
11359 ppd->actual_vls_operational :
11360 ppd->vls_operational,
11361 NULL);
11362 if (ret == 0)
11363 ret = pio_map_init(dd, ppd->port - 1, vl_count ?
11364 ppd->actual_vls_operational :
11365 ppd->vls_operational, NULL);
11366 if (ret)
11367 return ret;
11368 }
77241056
MM		 11369 return 0;
11370}
11371
11372/*
11373 * Read the given fabric manager table. Return the size of the
11374 * table (in bytes) on success, and a negative error code on
11375 * failure.
11376 */
11377int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t)
11378
11379{
11380 int size;
11381 struct vl_arb_cache *vlc;
11382
11383 switch (which) {
11384 case FM_TBL_VL_HIGH_ARB:
11385 size = 256;
11386 /*
11387 * OPA specifies 128 elements (of 2 bytes each), though
11388 * HFI supports only 16 elements in h/w.
11389 */
11390 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE);
11391 vl_arb_get_cache(vlc, t);
11392 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
11393 break;
11394 case FM_TBL_VL_LOW_ARB:
11395 size = 256;
11396 /*
11397 * OPA specifies 128 elements (of 2 bytes each), though
11398 * HFI supports only 16 elements in h/w.
11399 */
11400 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE);
11401 vl_arb_get_cache(vlc, t);
11402 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
11403 break;
11404 case FM_TBL_BUFFER_CONTROL:
11405 size = get_buffer_control(ppd->dd, t, NULL);
11406 break;
11407 case FM_TBL_SC2VLNT:
11408 size = get_sc2vlnt(ppd->dd, t);
11409 break;
11410 case FM_TBL_VL_PREEMPT_ELEMS:
11411 size = 256;
11412 /* OPA specifies 128 elements, of 2 bytes each */
11413 get_vlarb_preempt(ppd->dd, OPA_MAX_VLS, t);
11414 break;
11415 case FM_TBL_VL_PREEMPT_MATRIX:
11416 size = 256;
11417 /*
11418 * OPA specifies that this is the same size as the VL
11419 * arbitration tables (i.e., 256 bytes).
11420 */
11421 break;
11422 default:
11423 return -EINVAL;
11424 }
11425 return size;
11426}
11427
11428/*
11429 * Write the given fabric manager table.
11430 */
11431int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t)
11432{
11433 int ret = 0;
11434 struct vl_arb_cache *vlc;
11435
11436 switch (which) {
11437 case FM_TBL_VL_HIGH_ARB:
11438 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE);
11439 if (vl_arb_match_cache(vlc, t)) {
11440 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
11441 break;
11442 }
11443 vl_arb_set_cache(vlc, t);
11444 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
11445 ret = set_vl_weights(ppd, SEND_HIGH_PRIORITY_LIST,
11446 VL_ARB_HIGH_PRIO_TABLE_SIZE, t);
11447 break;
11448 case FM_TBL_VL_LOW_ARB:
11449 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE);
11450 if (vl_arb_match_cache(vlc, t)) {
11451 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
11452 break;
11453 }
11454 vl_arb_set_cache(vlc, t);
11455 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
11456 ret = set_vl_weights(ppd, SEND_LOW_PRIORITY_LIST,
11457 VL_ARB_LOW_PRIO_TABLE_SIZE, t);
11458 break;
11459 case FM_TBL_BUFFER_CONTROL:
8a4d3444 11460 ret = set_buffer_control(ppd, t);
77241056
MM		 11461 break;
11462 case FM_TBL_SC2VLNT:
11463 set_sc2vlnt(ppd->dd, t);
11464 break;
11465 default:
11466 ret = -EINVAL;
11467 }
11468 return ret;
11469}
11470
11471/*
11472 * Disable all data VLs.
11473 *
11474 * Return 0 if disabled, non-zero if the VLs cannot be disabled.
11475 */
11476static int disable_data_vls(struct hfi1_devdata *dd)
11477{
995deafa 11478 if (is_ax(dd))
77241056
MM		 11479 return 1;
11480
11481 pio_send_control(dd, PSC_DATA_VL_DISABLE);
11482
11483 return 0;
11484}
11485
11486/*
11487 * open_fill_data_vls() - the counterpart to stop_drain_data_vls().
11488 * Just re-enables all data VLs (the "fill" part happens
11489 * automatically - the name was chosen for symmetry with
11490 * stop_drain_data_vls()).
11491 *
11492 * Return 0 if successful, non-zero if the VLs cannot be enabled.
11493 */
11494int open_fill_data_vls(struct hfi1_devdata *dd)
11495{
995deafa 11496 if (is_ax(dd))
77241056
MM		 11497 return 1;
11498
11499 pio_send_control(dd, PSC_DATA_VL_ENABLE);
11500
11501 return 0;
11502}
11503
11504/*
11505 * drain_data_vls() - assumes that disable_data_vls() has been called,
11506 * wait for occupancy (of per-VL FIFOs) for all contexts, and SDMA
11507 * engines to drop to 0.
11508 */
11509static void drain_data_vls(struct hfi1_devdata *dd)
11510{
11511 sc_wait(dd);
11512 sdma_wait(dd);
11513 pause_for_credit_return(dd);
11514}
11515
11516/*
11517 * stop_drain_data_vls() - disable, then drain all per-VL fifos.
11518 *
11519 * Use open_fill_data_vls() to resume using data VLs. This pair is
11520 * meant to be used like this:
11521 *
11522 * stop_drain_data_vls(dd);
11523 * // do things with per-VL resources
11524 * open_fill_data_vls(dd);
11525 */
11526int stop_drain_data_vls(struct hfi1_devdata *dd)
11527{
11528 int ret;
11529
11530 ret = disable_data_vls(dd);
11531 if (ret == 0)
11532 drain_data_vls(dd);
11533
11534 return ret;
11535}
11536
11537/*
11538 * Convert a nanosecond time to a cclock count. No matter how slow
11539 * the cclock, a non-zero ns will always have a non-zero result.
11540 */
11541u32 ns_to_cclock(struct hfi1_devdata *dd, u32 ns)
11542{
11543 u32 cclocks;
11544
11545 if (dd->icode == ICODE_FPGA_EMULATION)
11546 cclocks = (ns * 1000) / FPGA_CCLOCK_PS;
11547 else /* simulation pretends to be ASIC */
11548 cclocks = (ns * 1000) / ASIC_CCLOCK_PS;
11549 if (ns && !cclocks) /* if ns nonzero, must be at least 1 */
11550 cclocks = 1;
11551 return cclocks;
11552}
11553
11554/*
11555 * Convert a cclock count to nanoseconds. Not matter how slow
11556 * the cclock, a non-zero cclocks will always have a non-zero result.
11557 */
11558u32 cclock_to_ns(struct hfi1_devdata *dd, u32 cclocks)
11559{
11560 u32 ns;
11561
11562 if (dd->icode == ICODE_FPGA_EMULATION)
11563 ns = (cclocks * FPGA_CCLOCK_PS) / 1000;
11564 else /* simulation pretends to be ASIC */
11565 ns = (cclocks * ASIC_CCLOCK_PS) / 1000;
11566 if (cclocks && !ns)
11567 ns = 1;
11568 return ns;
11569}
11570
11571/*
11572 * Dynamically adjust the receive interrupt timeout for a context based on
11573 * incoming packet rate.
11574 *
11575 * NOTE: Dynamic adjustment does not allow rcv_intr_count to be zero.
11576 */
11577static void adjust_rcv_timeout(struct hfi1_ctxtdata *rcd, u32 npkts)
11578{
11579 struct hfi1_devdata *dd = rcd->dd;
11580 u32 timeout = rcd->rcvavail_timeout;
11581
11582 /*
11583 * This algorithm doubles or halves the timeout depending on whether
11584 * the number of packets received in this interrupt were less than or
11585 * greater equal the interrupt count.
11586 *
11587 * The calculations below do not allow a steady state to be achieved.
11588 * Only at the endpoints it is possible to have an unchanging
11589 * timeout.
11590 */
11591 if (npkts < rcv_intr_count) {
11592 /*
11593 * Not enough packets arrived before the timeout, adjust
11594 * timeout downward.
11595 */
11596 if (timeout < 2) /* already at minimum? */
11597 return;
11598 timeout >>= 1;
11599 } else {
11600 /*
11601 * More than enough packets arrived before the timeout, adjust
11602 * timeout upward.
11603 */
11604 if (timeout >= dd->rcv_intr_timeout_csr) /* already at max? */
11605 return;
11606 timeout = min(timeout << 1, dd->rcv_intr_timeout_csr);
11607 }
11608
11609 rcd->rcvavail_timeout = timeout;
4d114fdd
JJ		 11610 /*
11611 * timeout cannot be larger than rcv_intr_timeout_csr which has already
11612 * been verified to be in range
11613 */
77241056 11614 write_kctxt_csr(dd, rcd->ctxt, RCV_AVAIL_TIME_OUT,
17fb4f29
JJ		 11615 (u64)timeout <<
11616 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
77241056
MM		 11617}
11618
11619void update_usrhead(struct hfi1_ctxtdata *rcd, u32 hd, u32 updegr, u32 egrhd,
11620 u32 intr_adjust, u32 npkts)
11621{
11622 struct hfi1_devdata *dd = rcd->dd;
11623 u64 reg;
11624 u32 ctxt = rcd->ctxt;
11625
11626 /*
11627 * Need to write timeout register before updating RcvHdrHead to ensure
11628 * that a new value is used when the HW decides to restart counting.
11629 */
11630 if (intr_adjust)
11631 adjust_rcv_timeout(rcd, npkts);
11632 if (updegr) {
11633 reg = (egrhd & RCV_EGR_INDEX_HEAD_HEAD_MASK)
11634 << RCV_EGR_INDEX_HEAD_HEAD_SHIFT;
11635 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, reg);
11636 }
11637 mmiowb();
11638 reg = ((u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT) |
11639 (((u64)hd & RCV_HDR_HEAD_HEAD_MASK)
11640 << RCV_HDR_HEAD_HEAD_SHIFT);
11641 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg);
11642 mmiowb();
11643}
11644
11645u32 hdrqempty(struct hfi1_ctxtdata *rcd)
11646{
11647 u32 head, tail;
11648
11649 head = (read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_HEAD)
11650 & RCV_HDR_HEAD_HEAD_SMASK) >> RCV_HDR_HEAD_HEAD_SHIFT;
11651
11652 if (rcd->rcvhdrtail_kvaddr)
11653 tail = get_rcvhdrtail(rcd);
11654 else
11655 tail = read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
11656
11657 return head == tail;
11658}
11659
11660/*
11661 * Context Control and Receive Array encoding for buffer size:
11662 * 0x0 invalid
11663 * 0x1 4 KB
11664 * 0x2 8 KB
11665 * 0x3 16 KB
11666 * 0x4 32 KB
11667 * 0x5 64 KB
11668 * 0x6 128 KB
11669 * 0x7 256 KB
11670 * 0x8 512 KB (Receive Array only)
11671 * 0x9 1 MB (Receive Array only)
11672 * 0xa 2 MB (Receive Array only)
11673 *
11674 * 0xB-0xF - reserved (Receive Array only)
11675 *
11676 *
11677 * This routine assumes that the value has already been sanity checked.
11678 */
11679static u32 encoded_size(u32 size)
11680{
11681 switch (size) {
8638b77f
JJ		 11682 case 4 * 1024: return 0x1;
11683 case 8 * 1024: return 0x2;
11684 case 16 * 1024: return 0x3;
11685 case 32 * 1024: return 0x4;
11686 case 64 * 1024: return 0x5;
11687 case 128 * 1024: return 0x6;
11688 case 256 * 1024: return 0x7;
11689 case 512 * 1024: return 0x8;
11690 case 1 * 1024 * 1024: return 0x9;
11691 case 2 * 1024 * 1024: return 0xa;
77241056
MM		 11692 }
11693 return 0x1; /* if invalid, go with the minimum size */
11694}
11695
11696void hfi1_rcvctrl(struct hfi1_devdata *dd, unsigned int op, int ctxt)
11697{
11698 struct hfi1_ctxtdata *rcd;
11699 u64 rcvctrl, reg;
11700 int did_enable = 0;
11701
11702 rcd = dd->rcd[ctxt];
11703 if (!rcd)
11704 return;
11705
11706 hfi1_cdbg(RCVCTRL, "ctxt %d op 0x%x", ctxt, op);
11707
11708 rcvctrl = read_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL);
11709 /* if the context already enabled, don't do the extra steps */
d0d236ea
JJ		 11710 if ((op & HFI1_RCVCTRL_CTXT_ENB) &&
11711 !(rcvctrl & RCV_CTXT_CTRL_ENABLE_SMASK)) {
77241056
MM		 11712 /* reset the tail and hdr addresses, and sequence count */
11713 write_kctxt_csr(dd, ctxt, RCV_HDR_ADDR,
60368186 11714 rcd->rcvhdrq_dma);
77241056
MM		 11715 if (HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL))
11716 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
60368186 11717 rcd->rcvhdrqtailaddr_dma);
77241056
MM		 11718 rcd->seq_cnt = 1;
11719
11720 /* reset the cached receive header queue head value */
11721 rcd->head = 0;
11722
11723 /*
11724 * Zero the receive header queue so we don't get false
11725 * positives when checking the sequence number. The
11726 * sequence numbers could land exactly on the same spot.
11727 * E.g. a rcd restart before the receive header wrapped.
11728 */
11729 memset(rcd->rcvhdrq, 0, rcd->rcvhdrq_size);
11730
11731 /* starting timeout */
11732 rcd->rcvavail_timeout = dd->rcv_intr_timeout_csr;
11733
11734 /* enable the context */
11735 rcvctrl |= RCV_CTXT_CTRL_ENABLE_SMASK;
11736
11737 /* clean the egr buffer size first */
11738 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK;
11739 rcvctrl |= ((u64)encoded_size(rcd->egrbufs.rcvtid_size)
11740 & RCV_CTXT_CTRL_EGR_BUF_SIZE_MASK)
11741 << RCV_CTXT_CTRL_EGR_BUF_SIZE_SHIFT;
11742
11743 /* zero RcvHdrHead - set RcvHdrHead.Counter after enable */
11744 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0);
11745 did_enable = 1;
11746
11747 /* zero RcvEgrIndexHead */
11748 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, 0);
11749
11750 /* set eager count and base index */
11751 reg = (((u64)(rcd->egrbufs.alloced >> RCV_SHIFT)
11752 & RCV_EGR_CTRL_EGR_CNT_MASK)
11753 << RCV_EGR_CTRL_EGR_CNT_SHIFT) |
11754 (((rcd->eager_base >> RCV_SHIFT)
11755 & RCV_EGR_CTRL_EGR_BASE_INDEX_MASK)
11756 << RCV_EGR_CTRL_EGR_BASE_INDEX_SHIFT);
11757 write_kctxt_csr(dd, ctxt, RCV_EGR_CTRL, reg);
11758
11759 /*
11760 * Set TID (expected) count and base index.
11761 * rcd->expected_count is set to individual RcvArray entries,
11762 * not pairs, and the CSR takes a pair-count in groups of
11763 * four, so divide by 8.
11764 */
11765 reg = (((rcd->expected_count >> RCV_SHIFT)
11766 & RCV_TID_CTRL_TID_PAIR_CNT_MASK)
11767 << RCV_TID_CTRL_TID_PAIR_CNT_SHIFT) |
11768 (((rcd->expected_base >> RCV_SHIFT)
11769 & RCV_TID_CTRL_TID_BASE_INDEX_MASK)
11770 << RCV_TID_CTRL_TID_BASE_INDEX_SHIFT);
11771 write_kctxt_csr(dd, ctxt, RCV_TID_CTRL, reg);
82c2611d
NV		 11772 if (ctxt == HFI1_CTRL_CTXT)
11773 write_csr(dd, RCV_VL15, HFI1_CTRL_CTXT);
77241056
MM		 11774 }
11775 if (op & HFI1_RCVCTRL_CTXT_DIS) {
11776 write_csr(dd, RCV_VL15, 0);
46b010d3
MB		 11777 /*
11778 * When receive context is being disabled turn on tail
11779 * update with a dummy tail address and then disable
11780 * receive context.
11781 */
60368186 11782 if (dd->rcvhdrtail_dummy_dma) {
46b010d3 11783 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
60368186 11784 dd->rcvhdrtail_dummy_dma);
566c157c 11785 /* Enabling RcvCtxtCtrl.TailUpd is intentional. */
46b010d3
MB		 11786 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11787 }
11788
77241056
MM		 11789 rcvctrl &= ~RCV_CTXT_CTRL_ENABLE_SMASK;
11790 }
11791 if (op & HFI1_RCVCTRL_INTRAVAIL_ENB)
11792 rcvctrl |= RCV_CTXT_CTRL_INTR_AVAIL_SMASK;
11793 if (op & HFI1_RCVCTRL_INTRAVAIL_DIS)
11794 rcvctrl &= ~RCV_CTXT_CTRL_INTR_AVAIL_SMASK;
60368186 11795 if (op & HFI1_RCVCTRL_TAILUPD_ENB && rcd->rcvhdrqtailaddr_dma)
77241056 11796 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK;
566c157c
MH		 11797 if (op & HFI1_RCVCTRL_TAILUPD_DIS) {
11798 /* See comment on RcvCtxtCtrl.TailUpd above */
11799 if (!(op & HFI1_RCVCTRL_CTXT_DIS))
11800 rcvctrl &= ~RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11801 }
77241056
MM		 11802 if (op & HFI1_RCVCTRL_TIDFLOW_ENB)
11803 rcvctrl |= RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK;
11804 if (op & HFI1_RCVCTRL_TIDFLOW_DIS)
11805 rcvctrl &= ~RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK;
11806 if (op & HFI1_RCVCTRL_ONE_PKT_EGR_ENB) {
4d114fdd
JJ		 11807 /*
11808 * In one-packet-per-eager mode, the size comes from
11809 * the RcvArray entry.
11810 */
77241056
MM		 11811 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK;
11812 rcvctrl |= RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK;
11813 }
11814 if (op & HFI1_RCVCTRL_ONE_PKT_EGR_DIS)
11815 rcvctrl &= ~RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK;
11816 if (op & HFI1_RCVCTRL_NO_RHQ_DROP_ENB)
11817 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK;
11818 if (op & HFI1_RCVCTRL_NO_RHQ_DROP_DIS)
11819 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK;
11820 if (op & HFI1_RCVCTRL_NO_EGR_DROP_ENB)
11821 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK;
11822 if (op & HFI1_RCVCTRL_NO_EGR_DROP_DIS)
11823 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK;
11824 rcd->rcvctrl = rcvctrl;
11825 hfi1_cdbg(RCVCTRL, "ctxt %d rcvctrl 0x%llx\n", ctxt, rcvctrl);
11826 write_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL, rcd->rcvctrl);
11827
11828 /* work around sticky RcvCtxtStatus.BlockedRHQFull */
d0d236ea
JJ		 11829 if (did_enable &&
11830 (rcvctrl & RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK)) {
77241056
MM		 11831 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS);
11832 if (reg != 0) {
11833 dd_dev_info(dd, "ctxt %d status %lld (blocked)\n",
17fb4f29 11834 ctxt, reg);
77241056
MM		 11835 read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD);
11836 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x10);
11837 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x00);
11838 read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD);
11839 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS);
11840 dd_dev_info(dd, "ctxt %d status %lld (%s blocked)\n",
17fb4f29 11841 ctxt, reg, reg == 0 ? "not" : "still");
77241056
MM		 11842 }
11843 }
11844
11845 if (did_enable) {
11846 /*
11847 * The interrupt timeout and count must be set after
11848 * the context is enabled to take effect.
11849 */
11850 /* set interrupt timeout */
11851 write_kctxt_csr(dd, ctxt, RCV_AVAIL_TIME_OUT,
17fb4f29 11852 (u64)rcd->rcvavail_timeout <<
77241056
MM		 11853 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
11854
11855 /* set RcvHdrHead.Counter, zero RcvHdrHead.Head (again) */
11856 reg = (u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT;
11857 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg);
11858 }
11859
11860 if (op & (HFI1_RCVCTRL_TAILUPD_DIS | HFI1_RCVCTRL_CTXT_DIS))
11861 /*
11862 * If the context has been disabled and the Tail Update has
46b010d3
MB		 11863 * been cleared, set the RCV_HDR_TAIL_ADDR CSR to dummy address
11864 * so it doesn't contain an address that is invalid.
77241056 11865 */
46b010d3 11866 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
60368186 11867 dd->rcvhdrtail_dummy_dma);
77241056
MM		 11868}
11869
582e05c3 11870u32 hfi1_read_cntrs(struct hfi1_devdata *dd, char **namep, u64 **cntrp)
77241056
MM		 11871{
11872 int ret;
11873 u64 val = 0;
11874
11875 if (namep) {
11876 ret = dd->cntrnameslen;
77241056
MM		 11877 *namep = dd->cntrnames;
11878 } else {
11879 const struct cntr_entry *entry;
11880 int i, j;
11881
11882 ret = (dd->ndevcntrs) * sizeof(u64);
77241056
MM		 11883
11884 /* Get the start of the block of counters */
11885 *cntrp = dd->cntrs;
11886
11887 /*
11888 * Now go and fill in each counter in the block.
11889 */
11890 for (i = 0; i < DEV_CNTR_LAST; i++) {
11891 entry = &dev_cntrs[i];
11892 hfi1_cdbg(CNTR, "reading %s", entry->name);
11893 if (entry->flags & CNTR_DISABLED) {
11894 /* Nothing */
11895 hfi1_cdbg(CNTR, "\tDisabled\n");
11896 } else {
11897 if (entry->flags & CNTR_VL) {
11898 hfi1_cdbg(CNTR, "\tPer VL\n");
11899 for (j = 0; j < C_VL_COUNT; j++) {
11900 val = entry->rw_cntr(entry,
11901 dd, j,
11902 CNTR_MODE_R,
11903 0);
11904 hfi1_cdbg(
11905 CNTR,
11906 "\t\tRead 0x%llx for %d\n",
11907 val, j);
11908 dd->cntrs[entry->offset + j] =
11909 val;
11910 }
a699c6c2
VM		 11911 } else if (entry->flags & CNTR_SDMA) {
11912 hfi1_cdbg(CNTR,
11913 "\t Per SDMA Engine\n");
11914 for (j = 0; j < dd->chip_sdma_engines;
11915 j++) {
11916 val =
11917 entry->rw_cntr(entry, dd, j,
11918 CNTR_MODE_R, 0);
11919 hfi1_cdbg(CNTR,
11920 "\t\tRead 0x%llx for %d\n",
11921 val, j);
11922 dd->cntrs[entry->offset + j] =
11923 val;
11924 }
77241056
MM		 11925 } else {
11926 val = entry->rw_cntr(entry, dd,
11927 CNTR_INVALID_VL,
11928 CNTR_MODE_R, 0);
11929 dd->cntrs[entry->offset] = val;
11930 hfi1_cdbg(CNTR, "\tRead 0x%llx", val);
11931 }
11932 }
11933 }
11934 }
11935 return ret;
11936}
11937
11938/*
11939 * Used by sysfs to create files for hfi stats to read
11940 */
582e05c3 11941u32 hfi1_read_portcntrs(struct hfi1_pportdata *ppd, char **namep, u64 **cntrp)
77241056
MM		 11942{
11943 int ret;
11944 u64 val = 0;
11945
11946 if (namep) {
582e05c3
DL		 11947 ret = ppd->dd->portcntrnameslen;
11948 *namep = ppd->dd->portcntrnames;
77241056
MM		 11949 } else {
11950 const struct cntr_entry *entry;
77241056
MM		 11951 int i, j;
11952
582e05c3 11953 ret = ppd->dd->nportcntrs * sizeof(u64);
77241056
MM		 11954 *cntrp = ppd->cntrs;
11955
11956 for (i = 0; i < PORT_CNTR_LAST; i++) {
11957 entry = &port_cntrs[i];
11958 hfi1_cdbg(CNTR, "reading %s", entry->name);
11959 if (entry->flags & CNTR_DISABLED) {
11960 /* Nothing */
11961 hfi1_cdbg(CNTR, "\tDisabled\n");
11962 continue;
11963 }
11964
11965 if (entry->flags & CNTR_VL) {
11966 hfi1_cdbg(CNTR, "\tPer VL");
11967 for (j = 0; j < C_VL_COUNT; j++) {
11968 val = entry->rw_cntr(entry, ppd, j,
11969 CNTR_MODE_R,
11970 0);
11971 hfi1_cdbg(
11972 CNTR,
11973 "\t\tRead 0x%llx for %d",
11974 val, j);
11975 ppd->cntrs[entry->offset + j] = val;
11976 }
11977 } else {
11978 val = entry->rw_cntr(entry, ppd,
11979 CNTR_INVALID_VL,
11980 CNTR_MODE_R,
11981 0);
11982 ppd->cntrs[entry->offset] = val;
11983 hfi1_cdbg(CNTR, "\tRead 0x%llx", val);
11984 }
11985 }
11986 }
11987 return ret;
11988}
11989
11990static void free_cntrs(struct hfi1_devdata *dd)
11991{
11992 struct hfi1_pportdata *ppd;
11993 int i;
11994
11995 if (dd->synth_stats_timer.data)
11996 del_timer_sync(&dd->synth_stats_timer);
11997 dd->synth_stats_timer.data = 0;
11998 ppd = (struct hfi1_pportdata *)(dd + 1);
11999 for (i = 0; i < dd->num_pports; i++, ppd++) {
12000 kfree(ppd->cntrs);
12001 kfree(ppd->scntrs);
4eb06882
DD		 12002 free_percpu(ppd->ibport_data.rvp.rc_acks);
12003 free_percpu(ppd->ibport_data.rvp.rc_qacks);
12004 free_percpu(ppd->ibport_data.rvp.rc_delayed_comp);
77241056
MM		 12005 ppd->cntrs = NULL;
12006 ppd->scntrs = NULL;
4eb06882
DD		 12007 ppd->ibport_data.rvp.rc_acks = NULL;
12008 ppd->ibport_data.rvp.rc_qacks = NULL;
12009 ppd->ibport_data.rvp.rc_delayed_comp = NULL;
77241056
MM		 12010 }
12011 kfree(dd->portcntrnames);
12012 dd->portcntrnames = NULL;
12013 kfree(dd->cntrs);
12014 dd->cntrs = NULL;
12015 kfree(dd->scntrs);
12016 dd->scntrs = NULL;
12017 kfree(dd->cntrnames);
12018 dd->cntrnames = NULL;
22546b74
TS		 12019 if (dd->update_cntr_wq) {
12020 destroy_workqueue(dd->update_cntr_wq);
12021 dd->update_cntr_wq = NULL;
12022 }
77241056
MM		 12023}
12024
77241056
MM		 12025static u64 read_dev_port_cntr(struct hfi1_devdata *dd, struct cntr_entry *entry,
12026 u64 *psval, void *context, int vl)
12027{
12028 u64 val;
12029 u64 sval = *psval;
12030
12031 if (entry->flags & CNTR_DISABLED) {
12032 dd_dev_err(dd, "Counter %s not enabled", entry->name);
12033 return 0;
12034 }
12035
12036 hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);
12037
12038 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_R, 0);
12039
12040 /* If its a synthetic counter there is more work we need to do */
12041 if (entry->flags & CNTR_SYNTH) {
12042 if (sval == CNTR_MAX) {
12043 /* No need to read already saturated */
12044 return CNTR_MAX;
12045 }
12046
12047 if (entry->flags & CNTR_32BIT) {
12048 /* 32bit counters can wrap multiple times */
12049 u64 upper = sval >> 32;
12050 u64 lower = (sval << 32) >> 32;
12051
12052 if (lower > val) { /* hw wrapped */
12053 if (upper == CNTR_32BIT_MAX)
12054 val = CNTR_MAX;
12055 else
12056 upper++;
12057 }
12058
12059 if (val != CNTR_MAX)
12060 val = (upper << 32) | val;
12061
12062 } else {
12063 /* If we rolled we are saturated */
12064 if ((val < sval) || (val > CNTR_MAX))
12065 val = CNTR_MAX;
12066 }
12067 }
12068
12069 *psval = val;
12070
12071 hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);
12072
12073 return val;
12074}
12075
12076static u64 write_dev_port_cntr(struct hfi1_devdata *dd,
12077 struct cntr_entry *entry,
12078 u64 *psval, void *context, int vl, u64 data)
12079{
12080 u64 val;
12081
12082 if (entry->flags & CNTR_DISABLED) {
12083 dd_dev_err(dd, "Counter %s not enabled", entry->name);
12084 return 0;
12085 }
12086
12087 hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);
12088
12089 if (entry->flags & CNTR_SYNTH) {
12090 *psval = data;
12091 if (entry->flags & CNTR_32BIT) {
12092 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W,
12093 (data << 32) >> 32);
12094 val = data; /* return the full 64bit value */
12095 } else {
12096 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W,
12097 data);
12098 }
12099 } else {
12100 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, data);
12101 }
12102
12103 *psval = val;
12104
12105 hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);
12106
12107 return val;
12108}
12109
12110u64 read_dev_cntr(struct hfi1_devdata *dd, int index, int vl)
12111{
12112 struct cntr_entry *entry;
12113 u64 *sval;
12114
12115 entry = &dev_cntrs[index];
12116 sval = dd->scntrs + entry->offset;
12117
12118 if (vl != CNTR_INVALID_VL)
12119 sval += vl;
12120
12121 return read_dev_port_cntr(dd, entry, sval, dd, vl);
12122}
12123
12124u64 write_dev_cntr(struct hfi1_devdata *dd, int index, int vl, u64 data)
12125{
12126 struct cntr_entry *entry;
12127 u64 *sval;
12128
12129 entry = &dev_cntrs[index];
12130 sval = dd->scntrs + entry->offset;
12131
12132 if (vl != CNTR_INVALID_VL)
12133 sval += vl;
12134
12135 return write_dev_port_cntr(dd, entry, sval, dd, vl, data);
12136}
12137
12138u64 read_port_cntr(struct hfi1_pportdata *ppd, int index, int vl)
12139{
12140 struct cntr_entry *entry;
12141 u64 *sval;
12142
12143 entry = &port_cntrs[index];
12144 sval = ppd->scntrs + entry->offset;
12145
12146 if (vl != CNTR_INVALID_VL)
12147 sval += vl;
12148
12149 if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) &&
12150 (index <= C_RCV_HDR_OVF_LAST)) {
12151 /* We do not want to bother for disabled contexts */
12152 return 0;
12153 }
12154
12155 return read_dev_port_cntr(ppd->dd, entry, sval, ppd, vl);
12156}
12157
12158u64 write_port_cntr(struct hfi1_pportdata *ppd, int index, int vl, u64 data)
12159{
12160 struct cntr_entry *entry;
12161 u64 *sval;
12162
12163 entry = &port_cntrs[index];
12164 sval = ppd->scntrs + entry->offset;
12165
12166 if (vl != CNTR_INVALID_VL)
12167 sval += vl;
12168
12169 if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) &&
12170 (index <= C_RCV_HDR_OVF_LAST)) {
12171 /* We do not want to bother for disabled contexts */
12172 return 0;
12173 }
12174
12175 return write_dev_port_cntr(ppd->dd, entry, sval, ppd, vl, data);
12176}
12177
22546b74 12178static void do_update_synth_timer(struct work_struct *work)
77241056
MM		 12179{
12180 u64 cur_tx;
12181 u64 cur_rx;
12182 u64 total_flits;
12183 u8 update = 0;
12184 int i, j, vl;
12185 struct hfi1_pportdata *ppd;
12186 struct cntr_entry *entry;
22546b74
TS		 12187 struct hfi1_devdata *dd = container_of(work, struct hfi1_devdata,
12188 update_cntr_work);
77241056
MM		 12189
12190 /*
12191 * Rather than keep beating on the CSRs pick a minimal set that we can
12192 * check to watch for potential roll over. We can do this by looking at
12193 * the number of flits sent/recv. If the total flits exceeds 32bits then
12194 * we have to iterate all the counters and update.
12195 */
12196 entry = &dev_cntrs[C_DC_RCV_FLITS];
12197 cur_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0);
12198
12199 entry = &dev_cntrs[C_DC_XMIT_FLITS];
12200 cur_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0);
12201
12202 hfi1_cdbg(
12203 CNTR,
12204 "[%d] curr tx=0x%llx rx=0x%llx :: last tx=0x%llx rx=0x%llx\n",
12205 dd->unit, cur_tx, cur_rx, dd->last_tx, dd->last_rx);
12206
12207 if ((cur_tx < dd->last_tx) || (cur_rx < dd->last_rx)) {
12208 /*
12209 * May not be strictly necessary to update but it won't hurt and
12210 * simplifies the logic here.
12211 */
12212 update = 1;
12213 hfi1_cdbg(CNTR, "[%d] Tripwire counter rolled, updating",
12214 dd->unit);
12215 } else {
12216 total_flits = (cur_tx - dd->last_tx) + (cur_rx - dd->last_rx);
12217 hfi1_cdbg(CNTR,
12218 "[%d] total flits 0x%llx limit 0x%llx\n", dd->unit,
12219 total_flits, (u64)CNTR_32BIT_MAX);
12220 if (total_flits >= CNTR_32BIT_MAX) {
12221 hfi1_cdbg(CNTR, "[%d] 32bit limit hit, updating",
12222 dd->unit);
12223 update = 1;
12224 }
12225 }
12226
12227 if (update) {
12228 hfi1_cdbg(CNTR, "[%d] Updating dd and ppd counters", dd->unit);
12229 for (i = 0; i < DEV_CNTR_LAST; i++) {
12230 entry = &dev_cntrs[i];
12231 if (entry->flags & CNTR_VL) {
12232 for (vl = 0; vl < C_VL_COUNT; vl++)
12233 read_dev_cntr(dd, i, vl);
12234 } else {
12235 read_dev_cntr(dd, i, CNTR_INVALID_VL);
12236 }
12237 }
12238 ppd = (struct hfi1_pportdata *)(dd + 1);
12239 for (i = 0; i < dd->num_pports; i++, ppd++) {
12240 for (j = 0; j < PORT_CNTR_LAST; j++) {
12241 entry = &port_cntrs[j];
12242 if (entry->flags & CNTR_VL) {
12243 for (vl = 0; vl < C_VL_COUNT; vl++)
12244 read_port_cntr(ppd, j, vl);
12245 } else {
12246 read_port_cntr(ppd, j, CNTR_INVALID_VL);
12247 }
12248 }
12249 }
12250
12251 /*
12252 * We want the value in the register. The goal is to keep track
12253 * of the number of "ticks" not the counter value. In other
12254 * words if the register rolls we want to notice it and go ahead
12255 * and force an update.
12256 */
12257 entry = &dev_cntrs[C_DC_XMIT_FLITS];
12258 dd->last_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL,
12259 CNTR_MODE_R, 0);
12260
12261 entry = &dev_cntrs[C_DC_RCV_FLITS];
12262 dd->last_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL,
12263 CNTR_MODE_R, 0);
12264
12265 hfi1_cdbg(CNTR, "[%d] setting last tx/rx to 0x%llx 0x%llx",
12266 dd->unit, dd->last_tx, dd->last_rx);
12267
12268 } else {
12269 hfi1_cdbg(CNTR, "[%d] No update necessary", dd->unit);
12270 }
22546b74 12271}
77241056 12272
22546b74
TS		 12273static void update_synth_timer(unsigned long opaque)
12274{
12275 struct hfi1_devdata *dd = (struct hfi1_devdata *)opaque;
12276
12277 queue_work(dd->update_cntr_wq, &dd->update_cntr_work);
48a0cc13 12278 mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME);
77241056
MM		 12279}
12280
09a7908b 12281#define C_MAX_NAME 16 /* 15 chars + one for /0 */
77241056
MM		 12282static int init_cntrs(struct hfi1_devdata *dd)
12283{
c024c554 12284 int i, rcv_ctxts, j;
77241056
MM		 12285 size_t sz;
12286 char *p;
12287 char name[C_MAX_NAME];
12288 struct hfi1_pportdata *ppd;
11d2b114
SS		 12289 const char *bit_type_32 = ",32";
12290 const int bit_type_32_sz = strlen(bit_type_32);
77241056
MM		 12291
12292 /* set up the stats timer; the add_timer is done at the end */
24523a94
MFW		 12293 setup_timer(&dd->synth_stats_timer, update_synth_timer,
12294 (unsigned long)dd);
77241056
MM		 12295
12296 /***********************/
12297 /* per device counters */
12298 /***********************/
12299
12300 /* size names and determine how many we have*/
12301 dd->ndevcntrs = 0;
12302 sz = 0;
77241056
MM		 12303
12304 for (i = 0; i < DEV_CNTR_LAST; i++) {
77241056
MM		 12305 if (dev_cntrs[i].flags & CNTR_DISABLED) {
12306 hfi1_dbg_early("\tSkipping %s\n", dev_cntrs[i].name);
12307 continue;
12308 }
12309
12310 if (dev_cntrs[i].flags & CNTR_VL) {
c024c554 12311 dev_cntrs[i].offset = dd->ndevcntrs;
77241056 12312 for (j = 0; j < C_VL_COUNT; j++) {
77241056 12313 snprintf(name, C_MAX_NAME, "%s%d",
17fb4f29 12314 dev_cntrs[i].name, vl_from_idx(j));
77241056 12315 sz += strlen(name);
11d2b114
SS		 12316 /* Add ",32" for 32-bit counters */
12317 if (dev_cntrs[i].flags & CNTR_32BIT)
12318 sz += bit_type_32_sz;
77241056 12319 sz++;
77241056 12320 dd->ndevcntrs++;
77241056 12321 }
a699c6c2 12322 } else if (dev_cntrs[i].flags & CNTR_SDMA) {
c024c554 12323 dev_cntrs[i].offset = dd->ndevcntrs;
a699c6c2 12324 for (j = 0; j < dd->chip_sdma_engines; j++) {
a699c6c2
VM		 12325 snprintf(name, C_MAX_NAME, "%s%d",
12326 dev_cntrs[i].name, j);
77241056 12327 sz += strlen(name);
11d2b114
SS		 12328 /* Add ",32" for 32-bit counters */
12329 if (dev_cntrs[i].flags & CNTR_32BIT)
12330 sz += bit_type_32_sz;
77241056 12331 sz++;
77241056 12332 dd->ndevcntrs++;
77241056
MM		 12333 }
12334 } else {
11d2b114 12335 /* +1 for newline. */
77241056 12336 sz += strlen(dev_cntrs[i].name) + 1;
11d2b114
SS		 12337 /* Add ",32" for 32-bit counters */
12338 if (dev_cntrs[i].flags & CNTR_32BIT)
12339 sz += bit_type_32_sz;
c024c554 12340 dev_cntrs[i].offset = dd->ndevcntrs;
77241056 12341 dd->ndevcntrs++;
77241056
MM		 12342 }
12343 }
12344
12345 /* allocate space for the counter values */
c024c554 12346 dd->cntrs = kcalloc(dd->ndevcntrs, sizeof(u64), GFP_KERNEL);
77241056
MM		 12347 if (!dd->cntrs)
12348 goto bail;
12349
c024c554 12350 dd->scntrs = kcalloc(dd->ndevcntrs, sizeof(u64), GFP_KERNEL);
77241056
MM		 12351 if (!dd->scntrs)
12352 goto bail;
12353
77241056
MM		 12354 /* allocate space for the counter names */
12355 dd->cntrnameslen = sz;
12356 dd->cntrnames = kmalloc(sz, GFP_KERNEL);
12357 if (!dd->cntrnames)
12358 goto bail;
12359
12360 /* fill in the names */
c024c554 12361 for (p = dd->cntrnames, i = 0; i < DEV_CNTR_LAST; i++) {
77241056
MM		 12362 if (dev_cntrs[i].flags & CNTR_DISABLED) {
12363 /* Nothing */
11d2b114
SS		 12364 } else if (dev_cntrs[i].flags & CNTR_VL) {
12365 for (j = 0; j < C_VL_COUNT; j++) {
11d2b114
SS		 12366 snprintf(name, C_MAX_NAME, "%s%d",
12367 dev_cntrs[i].name,
12368 vl_from_idx(j));
12369 memcpy(p, name, strlen(name));
12370 p += strlen(name);
12371
12372 /* Counter is 32 bits */
12373 if (dev_cntrs[i].flags & CNTR_32BIT) {
12374 memcpy(p, bit_type_32, bit_type_32_sz);
12375 p += bit_type_32_sz;
77241056 12376 }
11d2b114
SS		 12377
12378 *p++ = '\n';
12379 }
12380 } else if (dev_cntrs[i].flags & CNTR_SDMA) {
12381 for (j = 0; j < dd->chip_sdma_engines; j++) {
11d2b114
SS		 12382 snprintf(name, C_MAX_NAME, "%s%d",
12383 dev_cntrs[i].name, j);
12384 memcpy(p, name, strlen(name));
12385 p += strlen(name);
12386
12387 /* Counter is 32 bits */
12388 if (dev_cntrs[i].flags & CNTR_32BIT) {
12389 memcpy(p, bit_type_32, bit_type_32_sz);
12390 p += bit_type_32_sz;
a699c6c2 12391 }
11d2b114 12392
77241056
MM		 12393 *p++ = '\n';
12394 }
11d2b114
SS		 12395 } else {
12396 memcpy(p, dev_cntrs[i].name, strlen(dev_cntrs[i].name));
12397 p += strlen(dev_cntrs[i].name);
12398
12399 /* Counter is 32 bits */
12400 if (dev_cntrs[i].flags & CNTR_32BIT) {
12401 memcpy(p, bit_type_32, bit_type_32_sz);
12402 p += bit_type_32_sz;
12403 }
12404
12405 *p++ = '\n';
77241056
MM		 12406 }
12407 }
12408
12409 /*********************/
12410 /* per port counters */
12411 /*********************/
12412
12413 /*
12414 * Go through the counters for the overflows and disable the ones we
12415 * don't need. This varies based on platform so we need to do it
12416 * dynamically here.
12417 */
12418 rcv_ctxts = dd->num_rcv_contexts;
12419 for (i = C_RCV_HDR_OVF_FIRST + rcv_ctxts;
12420 i <= C_RCV_HDR_OVF_LAST; i++) {
12421 port_cntrs[i].flags |= CNTR_DISABLED;
12422 }
12423
12424 /* size port counter names and determine how many we have*/
12425 sz = 0;
12426 dd->nportcntrs = 0;
12427 for (i = 0; i < PORT_CNTR_LAST; i++) {
77241056
MM		 12428 if (port_cntrs[i].flags & CNTR_DISABLED) {
12429 hfi1_dbg_early("\tSkipping %s\n", port_cntrs[i].name);
12430 continue;
12431 }
12432
12433 if (port_cntrs[i].flags & CNTR_VL) {
77241056
MM		 12434 port_cntrs[i].offset = dd->nportcntrs;
12435 for (j = 0; j < C_VL_COUNT; j++) {
77241056 12436 snprintf(name, C_MAX_NAME, "%s%d",
17fb4f29 12437 port_cntrs[i].name, vl_from_idx(j));
77241056 12438 sz += strlen(name);
11d2b114
SS		 12439 /* Add ",32" for 32-bit counters */
12440 if (port_cntrs[i].flags & CNTR_32BIT)
12441 sz += bit_type_32_sz;
77241056 12442 sz++;
77241056
MM		 12443 dd->nportcntrs++;
12444 }
12445 } else {
11d2b114 12446 /* +1 for newline */
77241056 12447 sz += strlen(port_cntrs[i].name) + 1;
11d2b114
SS		 12448 /* Add ",32" for 32-bit counters */
12449 if (port_cntrs[i].flags & CNTR_32BIT)
12450 sz += bit_type_32_sz;
77241056
MM		 12451 port_cntrs[i].offset = dd->nportcntrs;
12452 dd->nportcntrs++;
77241056
MM		 12453 }
12454 }
12455
12456 /* allocate space for the counter names */
12457 dd->portcntrnameslen = sz;
12458 dd->portcntrnames = kmalloc(sz, GFP_KERNEL);
12459 if (!dd->portcntrnames)
12460 goto bail;
12461
12462 /* fill in port cntr names */
12463 for (p = dd->portcntrnames, i = 0; i < PORT_CNTR_LAST; i++) {
12464 if (port_cntrs[i].flags & CNTR_DISABLED)
12465 continue;
12466
12467 if (port_cntrs[i].flags & CNTR_VL) {
12468 for (j = 0; j < C_VL_COUNT; j++) {
77241056 12469 snprintf(name, C_MAX_NAME, "%s%d",
17fb4f29 12470 port_cntrs[i].name, vl_from_idx(j));
77241056
MM		 12471 memcpy(p, name, strlen(name));
12472 p += strlen(name);
11d2b114
SS		 12473
12474 /* Counter is 32 bits */
12475 if (port_cntrs[i].flags & CNTR_32BIT) {
12476 memcpy(p, bit_type_32, bit_type_32_sz);
12477 p += bit_type_32_sz;
12478 }
12479
77241056
MM		 12480 *p++ = '\n';
12481 }
12482 } else {
12483 memcpy(p, port_cntrs[i].name,
12484 strlen(port_cntrs[i].name));
12485 p += strlen(port_cntrs[i].name);
11d2b114
SS		 12486
12487 /* Counter is 32 bits */
12488 if (port_cntrs[i].flags & CNTR_32BIT) {
12489 memcpy(p, bit_type_32, bit_type_32_sz);
12490 p += bit_type_32_sz;
12491 }
12492
77241056
MM		 12493 *p++ = '\n';
12494 }
12495 }
12496
12497 /* allocate per port storage for counter values */
12498 ppd = (struct hfi1_pportdata *)(dd + 1);
12499 for (i = 0; i < dd->num_pports; i++, ppd++) {
12500 ppd->cntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL);
12501 if (!ppd->cntrs)
12502 goto bail;
12503
12504 ppd->scntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL);
12505 if (!ppd->scntrs)
12506 goto bail;
12507 }
12508
12509 /* CPU counters need to be allocated and zeroed */
12510 if (init_cpu_counters(dd))
12511 goto bail;
12512
22546b74
TS		 12513 dd->update_cntr_wq = alloc_ordered_workqueue("hfi1_update_cntr_%d",
12514 WQ_MEM_RECLAIM, dd->unit);
12515 if (!dd->update_cntr_wq)
12516 goto bail;
12517
12518 INIT_WORK(&dd->update_cntr_work, do_update_synth_timer);
12519
77241056
MM		 12520 mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME);
12521 return 0;
12522bail:
12523 free_cntrs(dd);
12524 return -ENOMEM;
12525}
12526
77241056
MM		 12527static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate)
12528{
12529 switch (chip_lstate) {
12530 default:
12531 dd_dev_err(dd,
17fb4f29
JJ		 12532 "Unknown logical state 0x%x, reporting IB_PORT_DOWN\n",
12533 chip_lstate);
77241056
MM		 12534 /* fall through */
12535 case LSTATE_DOWN:
12536 return IB_PORT_DOWN;
12537 case LSTATE_INIT:
12538 return IB_PORT_INIT;
12539 case LSTATE_ARMED:
12540 return IB_PORT_ARMED;
12541 case LSTATE_ACTIVE:
12542 return IB_PORT_ACTIVE;
12543 }
12544}
12545
12546u32 chip_to_opa_pstate(struct hfi1_devdata *dd, u32 chip_pstate)
12547{
12548 /* look at the HFI meta-states only */
12549 switch (chip_pstate & 0xf0) {
12550 default:
12551 dd_dev_err(dd, "Unexpected chip physical state of 0x%x\n",
17fb4f29 12552 chip_pstate);
77241056
MM		 12553 /* fall through */
12554 case PLS_DISABLED:
12555 return IB_PORTPHYSSTATE_DISABLED;
12556 case PLS_OFFLINE:
12557 return OPA_PORTPHYSSTATE_OFFLINE;
12558 case PLS_POLLING:
12559 return IB_PORTPHYSSTATE_POLLING;
12560 case PLS_CONFIGPHY:
12561 return IB_PORTPHYSSTATE_TRAINING;
12562 case PLS_LINKUP:
12563 return IB_PORTPHYSSTATE_LINKUP;
12564 case PLS_PHYTEST:
12565 return IB_PORTPHYSSTATE_PHY_TEST;
12566 }
12567}
12568
12569/* return the OPA port logical state name */
12570const char *opa_lstate_name(u32 lstate)
12571{
12572 static const char * const port_logical_names[] = {
12573 "PORT_NOP",
12574 "PORT_DOWN",
12575 "PORT_INIT",
12576 "PORT_ARMED",
12577 "PORT_ACTIVE",
12578 "PORT_ACTIVE_DEFER",
12579 };
12580 if (lstate < ARRAY_SIZE(port_logical_names))
12581 return port_logical_names[lstate];
12582 return "unknown";
12583}
12584
12585/* return the OPA port physical state name */
12586const char *opa_pstate_name(u32 pstate)
12587{
12588 static const char * const port_physical_names[] = {
12589 "PHYS_NOP",
12590 "reserved1",
12591 "PHYS_POLL",
12592 "PHYS_DISABLED",
12593 "PHYS_TRAINING",
12594 "PHYS_LINKUP",
12595 "PHYS_LINK_ERR_RECOVER",
12596 "PHYS_PHY_TEST",
12597 "reserved8",
12598 "PHYS_OFFLINE",
12599 "PHYS_GANGED",
12600 "PHYS_TEST",
12601 };
12602 if (pstate < ARRAY_SIZE(port_physical_names))
12603 return port_physical_names[pstate];
12604 return "unknown";
12605}
12606
12607/*
12608 * Read the hardware link state and set the driver's cached value of it.
12609 * Return the (new) current value.
12610 */
12611u32 get_logical_state(struct hfi1_pportdata *ppd)
12612{
12613 u32 new_state;
12614
12615 new_state = chip_to_opa_lstate(ppd->dd, read_logical_state(ppd->dd));
12616 if (new_state != ppd->lstate) {
12617 dd_dev_info(ppd->dd, "logical state changed to %s (0x%x)\n",
17fb4f29 12618 opa_lstate_name(new_state), new_state);
77241056
MM		 12619 ppd->lstate = new_state;
12620 }
12621 /*
12622 * Set port status flags in the page mapped into userspace
12623 * memory. Do it here to ensure a reliable state - this is
12624 * the only function called by all state handling code.
12625 * Always set the flags due to the fact that the cache value
12626 * might have been changed explicitly outside of this
12627 * function.
12628 */
12629 if (ppd->statusp) {
12630 switch (ppd->lstate) {
12631 case IB_PORT_DOWN:
12632 case IB_PORT_INIT:
12633 *ppd->statusp &= ~(HFI1_STATUS_IB_CONF |
12634 HFI1_STATUS_IB_READY);
12635 break;
12636 case IB_PORT_ARMED:
12637 *ppd->statusp |= HFI1_STATUS_IB_CONF;
12638 break;
12639 case IB_PORT_ACTIVE:
12640 *ppd->statusp |= HFI1_STATUS_IB_READY;
12641 break;
12642 }
12643 }
12644 return ppd->lstate;
12645}
12646
12647/**
12648 * wait_logical_linkstate - wait for an IB link state change to occur
12649 * @ppd: port device
12650 * @state: the state to wait for
12651 * @msecs: the number of milliseconds to wait
12652 *
12653 * Wait up to msecs milliseconds for IB link state change to occur.
12654 * For now, take the easy polling route.
12655 * Returns 0 if state reached, otherwise -ETIMEDOUT.
12656 */
12657static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state,
12658 int msecs)
12659{
12660 unsigned long timeout;
12661
12662 timeout = jiffies + msecs_to_jiffies(msecs);
12663 while (1) {
12664 if (get_logical_state(ppd) == state)
12665 return 0;
12666 if (time_after(jiffies, timeout))
12667 break;
12668 msleep(20);
12669 }
12670 dd_dev_err(ppd->dd, "timeout waiting for link state 0x%x\n", state);
12671
12672 return -ETIMEDOUT;
12673}
12674
12675u8 hfi1_ibphys_portstate(struct hfi1_pportdata *ppd)
12676{
77241056
MM		 12677 u32 pstate;
12678 u32 ib_pstate;
12679
12680 pstate = read_physical_state(ppd->dd);
12681 ib_pstate = chip_to_opa_pstate(ppd->dd, pstate);
f45c8dc8 12682 if (ppd->last_pstate != ib_pstate) {
77241056 12683 dd_dev_info(ppd->dd,
17fb4f29
JJ		 12684 "%s: physical state changed to %s (0x%x), phy 0x%x\n",
12685 __func__, opa_pstate_name(ib_pstate), ib_pstate,
12686 pstate);
f45c8dc8 12687 ppd->last_pstate = ib_pstate;
77241056
MM		 12688 }
12689 return ib_pstate;
12690}
12691
77241056
MM		 12692#define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \
12693(r &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
12694
12695#define SET_STATIC_RATE_CONTROL_SMASK(r) \
12696(r |= SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
12697
9b60d2cb 12698void hfi1_init_ctxt(struct send_context *sc)
77241056 12699{
d125a6c6 12700 if (sc) {
77241056
MM		 12701 struct hfi1_devdata *dd = sc->dd;
12702 u64 reg;
12703 u8 set = (sc->type == SC_USER ?
12704 HFI1_CAP_IS_USET(STATIC_RATE_CTRL) :
12705 HFI1_CAP_IS_KSET(STATIC_RATE_CTRL));
12706 reg = read_kctxt_csr(dd, sc->hw_context,
12707 SEND_CTXT_CHECK_ENABLE);
12708 if (set)
12709 CLEAR_STATIC_RATE_CONTROL_SMASK(reg);
12710 else
12711 SET_STATIC_RATE_CONTROL_SMASK(reg);
12712 write_kctxt_csr(dd, sc->hw_context,
12713 SEND_CTXT_CHECK_ENABLE, reg);
12714 }
77241056
MM		 12715}
12716
12717int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp)
12718{
12719 int ret = 0;
12720 u64 reg;
12721
12722 if (dd->icode != ICODE_RTL_SILICON) {
12723 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
12724 dd_dev_info(dd, "%s: tempsense not supported by HW\n",
12725 __func__);
12726 return -EINVAL;
12727 }
12728 reg = read_csr(dd, ASIC_STS_THERM);
12729 temp->curr = ((reg >> ASIC_STS_THERM_CURR_TEMP_SHIFT) &
12730 ASIC_STS_THERM_CURR_TEMP_MASK);
12731 temp->lo_lim = ((reg >> ASIC_STS_THERM_LO_TEMP_SHIFT) &
12732 ASIC_STS_THERM_LO_TEMP_MASK);
12733 temp->hi_lim = ((reg >> ASIC_STS_THERM_HI_TEMP_SHIFT) &
12734 ASIC_STS_THERM_HI_TEMP_MASK);
12735 temp->crit_lim = ((reg >> ASIC_STS_THERM_CRIT_TEMP_SHIFT) &
12736 ASIC_STS_THERM_CRIT_TEMP_MASK);
12737 /* triggers is a 3-bit value - 1 bit per trigger. */
12738 temp->triggers = (u8)((reg >> ASIC_STS_THERM_LOW_SHIFT) & 0x7);
12739
12740 return ret;
12741}
12742
12743/* ========================================================================= */
12744
12745/*
12746 * Enable/disable chip from delivering interrupts.
12747 */
12748void set_intr_state(struct hfi1_devdata *dd, u32 enable)
12749{
12750 int i;
12751
12752 /*
12753 * In HFI, the mask needs to be 1 to allow interrupts.
12754 */
12755 if (enable) {
77241056
MM		 12756 /* enable all interrupts */
12757 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
8638b77f 12758 write_csr(dd, CCE_INT_MASK + (8 * i), ~(u64)0);
77241056 12759
8ebd4cf1 12760 init_qsfp_int(dd);
77241056
MM		 12761 } else {
12762 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
8638b77f 12763 write_csr(dd, CCE_INT_MASK + (8 * i), 0ull);
77241056
MM		 12764 }
12765}
12766
12767/*
12768 * Clear all interrupt sources on the chip.
12769 */
12770static void clear_all_interrupts(struct hfi1_devdata *dd)
12771{
12772 int i;
12773
12774 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
8638b77f 12775 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~(u64)0);
77241056
MM		 12776
12777 write_csr(dd, CCE_ERR_CLEAR, ~(u64)0);
12778 write_csr(dd, MISC_ERR_CLEAR, ~(u64)0);
12779 write_csr(dd, RCV_ERR_CLEAR, ~(u64)0);
12780 write_csr(dd, SEND_ERR_CLEAR, ~(u64)0);
12781 write_csr(dd, SEND_PIO_ERR_CLEAR, ~(u64)0);
12782 write_csr(dd, SEND_DMA_ERR_CLEAR, ~(u64)0);
12783 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~(u64)0);
12784 for (i = 0; i < dd->chip_send_contexts; i++)
12785 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~(u64)0);
12786 for (i = 0; i < dd->chip_sdma_engines; i++)
12787 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~(u64)0);
12788
12789 write_csr(dd, DCC_ERR_FLG_CLR, ~(u64)0);
12790 write_csr(dd, DC_LCB_ERR_CLR, ~(u64)0);
12791 write_csr(dd, DC_DC8051_ERR_CLR, ~(u64)0);
12792}
12793
12794/* Move to pcie.c? */
12795static void disable_intx(struct pci_dev *pdev)
12796{
12797 pci_intx(pdev, 0);
12798}
12799
12800static void clean_up_interrupts(struct hfi1_devdata *dd)
12801{
12802 int i;
12803
12804 /* remove irqs - must happen before disabling/turning off */
12805 if (dd->num_msix_entries) {
12806 /* MSI-X */
12807 struct hfi1_msix_entry *me = dd->msix_entries;
12808
12809 for (i = 0; i < dd->num_msix_entries; i++, me++) {
d125a6c6 12810 if (!me->arg) /* => no irq, no affinity */
957558c9
MH		 12811 continue;
12812 hfi1_put_irq_affinity(dd, &dd->msix_entries[i]);
77241056
MM		 12813 free_irq(me->msix.vector, me->arg);
12814 }
12815 } else {
12816 /* INTx */
12817 if (dd->requested_intx_irq) {
12818 free_irq(dd->pcidev->irq, dd);
12819 dd->requested_intx_irq = 0;
12820 }
12821 }
12822
12823 /* turn off interrupts */
12824 if (dd->num_msix_entries) {
12825 /* MSI-X */
6e5b6131 12826 pci_disable_msix(dd->pcidev);
77241056
MM		 12827 } else {
12828 /* INTx */
12829 disable_intx(dd->pcidev);
12830 }
12831
12832 /* clean structures */
77241056
MM		 12833 kfree(dd->msix_entries);
12834 dd->msix_entries = NULL;
12835 dd->num_msix_entries = 0;
12836}
12837
12838/*
12839 * Remap the interrupt source from the general handler to the given MSI-X
12840 * interrupt.
12841 */
12842static void remap_intr(struct hfi1_devdata *dd, int isrc, int msix_intr)
12843{
12844 u64 reg;
12845 int m, n;
12846
12847 /* clear from the handled mask of the general interrupt */
12848 m = isrc / 64;
12849 n = isrc % 64;
91647f4c
DD		 12850 if (likely(m < CCE_NUM_INT_CSRS)) {
12851 dd->gi_mask[m] &= ~((u64)1 << n);
12852 } else {
12853 dd_dev_err(dd, "remap interrupt err\n");
12854 return;
12855 }
77241056
MM		 12856
12857 /* direct the chip source to the given MSI-X interrupt */
12858 m = isrc / 8;
12859 n = isrc % 8;
8638b77f
JJ		 12860 reg = read_csr(dd, CCE_INT_MAP + (8 * m));
12861 reg &= ~((u64)0xff << (8 * n));
12862 reg |= ((u64)msix_intr & 0xff) << (8 * n);
12863 write_csr(dd, CCE_INT_MAP + (8 * m), reg);
77241056
MM		 12864}
12865
12866static void remap_sdma_interrupts(struct hfi1_devdata *dd,
12867 int engine, int msix_intr)
12868{
12869 /*
12870 * SDMA engine interrupt sources grouped by type, rather than
12871 * engine. Per-engine interrupts are as follows:
12872 * SDMA
12873 * SDMAProgress
12874 * SDMAIdle
12875 */
8638b77f 12876 remap_intr(dd, IS_SDMA_START + 0 * TXE_NUM_SDMA_ENGINES + engine,
17fb4f29 12877 msix_intr);
8638b77f 12878 remap_intr(dd, IS_SDMA_START + 1 * TXE_NUM_SDMA_ENGINES + engine,
17fb4f29 12879 msix_intr);
8638b77f 12880 remap_intr(dd, IS_SDMA_START + 2 * TXE_NUM_SDMA_ENGINES + engine,
17fb4f29 12881 msix_intr);
77241056
MM		 12882}
12883
77241056
MM		 12884static int request_intx_irq(struct hfi1_devdata *dd)
12885{
12886 int ret;
12887
9805071e
JJ		 12888 snprintf(dd->intx_name, sizeof(dd->intx_name), DRIVER_NAME "_%d",
12889 dd->unit);
77241056 12890 ret = request_irq(dd->pcidev->irq, general_interrupt,
17fb4f29 12891 IRQF_SHARED, dd->intx_name, dd);
77241056
MM		 12892 if (ret)
12893 dd_dev_err(dd, "unable to request INTx interrupt, err %d\n",
17fb4f29 12894 ret);
77241056
MM		 12895 else
12896 dd->requested_intx_irq = 1;
12897 return ret;
12898}
12899
12900static int request_msix_irqs(struct hfi1_devdata *dd)
12901{
77241056
MM		 12902 int first_general, last_general;
12903 int first_sdma, last_sdma;
12904 int first_rx, last_rx;
957558c9 12905 int i, ret = 0;
77241056
MM		 12906
12907 /* calculate the ranges we are going to use */
12908 first_general = 0;
f3ff8189
JJ		 12909 last_general = first_general + 1;
12910 first_sdma = last_general;
12911 last_sdma = first_sdma + dd->num_sdma;
12912 first_rx = last_sdma;
2280740f
VN		 12913 last_rx = first_rx + dd->n_krcv_queues + HFI1_NUM_VNIC_CTXT;
12914
12915 /* VNIC MSIx interrupts get mapped when VNIC contexts are created */
12916 dd->first_dyn_msix_idx = first_rx + dd->n_krcv_queues;
77241056 12917
77241056
MM		 12918 /*
12919 * Sanity check - the code expects all SDMA chip source
12920 * interrupts to be in the same CSR, starting at bit 0. Verify
12921 * that this is true by checking the bit location of the start.
12922 */
12923 BUILD_BUG_ON(IS_SDMA_START % 64);
12924
12925 for (i = 0; i < dd->num_msix_entries; i++) {
12926 struct hfi1_msix_entry *me = &dd->msix_entries[i];
12927 const char *err_info;
12928 irq_handler_t handler;
f4f30031 12929 irq_handler_t thread = NULL;
2280740f 12930 void *arg = NULL;
77241056
MM		 12931 int idx;
12932 struct hfi1_ctxtdata *rcd = NULL;
12933 struct sdma_engine *sde = NULL;
12934
12935 /* obtain the arguments to request_irq */
12936 if (first_general <= i && i < last_general) {
12937 idx = i - first_general;
12938 handler = general_interrupt;
12939 arg = dd;
12940 snprintf(me->name, sizeof(me->name),
9805071e 12941 DRIVER_NAME "_%d", dd->unit);
77241056 12942 err_info = "general";
957558c9 12943 me->type = IRQ_GENERAL;
77241056
MM		 12944 } else if (first_sdma <= i && i < last_sdma) {
12945 idx = i - first_sdma;
12946 sde = &dd->per_sdma[idx];
12947 handler = sdma_interrupt;
12948 arg = sde;
12949 snprintf(me->name, sizeof(me->name),
9805071e 12950 DRIVER_NAME "_%d sdma%d", dd->unit, idx);
77241056
MM		 12951 err_info = "sdma";
12952 remap_sdma_interrupts(dd, idx, i);
957558c9 12953 me->type = IRQ_SDMA;
77241056
MM		 12954 } else if (first_rx <= i && i < last_rx) {
12955 idx = i - first_rx;
12956 rcd = dd->rcd[idx];
2280740f
VN		 12957 if (rcd) {
12958 /*
12959 * Set the interrupt register and mask for this
12960 * context's interrupt.
12961 */
12962 rcd->ireg = (IS_RCVAVAIL_START + idx) / 64;
12963 rcd->imask = ((u64)1) <<
12964 ((IS_RCVAVAIL_START + idx) % 64);
12965 handler = receive_context_interrupt;
12966 thread = receive_context_thread;
12967 arg = rcd;
12968 snprintf(me->name, sizeof(me->name),
12969 DRIVER_NAME "_%d kctxt%d",
12970 dd->unit, idx);
12971 err_info = "receive context";
12972 remap_intr(dd, IS_RCVAVAIL_START + idx, i);
12973 me->type = IRQ_RCVCTXT;
12974 rcd->msix_intr = i;
12975 }
77241056
MM		 12976 } else {
12977 /* not in our expected range - complain, then
4d114fdd
JJ		 12978 * ignore it
12979 */
77241056 12980 dd_dev_err(dd,
17fb4f29 12981 "Unexpected extra MSI-X interrupt %d\n", i);
77241056
MM		 12982 continue;
12983 }
12984 /* no argument, no interrupt */
d125a6c6 12985 if (!arg)
77241056
MM		 12986 continue;
12987 /* make sure the name is terminated */
8638b77f 12988 me->name[sizeof(me->name) - 1] = 0;
77241056 12989
f4f30031 12990 ret = request_threaded_irq(me->msix.vector, handler, thread, 0,
17fb4f29 12991 me->name, arg);
77241056
MM		 12992 if (ret) {
12993 dd_dev_err(dd,
17fb4f29
JJ		 12994 "unable to allocate %s interrupt, vector %d, index %d, err %d\n",
12995 err_info, me->msix.vector, idx, ret);
77241056
MM		 12996 return ret;
12997 }
12998 /*
12999 * assign arg after request_irq call, so it will be
13000 * cleaned up
13001 */
13002 me->arg = arg;
13003
957558c9
MH		 13004 ret = hfi1_get_irq_affinity(dd, me);
13005 if (ret)
13006 dd_dev_err(dd,
13007 "unable to pin IRQ %d\n", ret);
77241056
MM		 13008 }
13009
77241056 13010 return ret;
77241056
MM		 13011}
13012
2280740f
VN		 13013void hfi1_vnic_synchronize_irq(struct hfi1_devdata *dd)
13014{
13015 int i;
13016
13017 if (!dd->num_msix_entries) {
13018 synchronize_irq(dd->pcidev->irq);
13019 return;
13020 }
13021
13022 for (i = 0; i < dd->vnic.num_ctxt; i++) {
13023 struct hfi1_ctxtdata *rcd = dd->vnic.ctxt[i];
13024 struct hfi1_msix_entry *me = &dd->msix_entries[rcd->msix_intr];
13025
13026 synchronize_irq(me->msix.vector);
13027 }
13028}
13029
13030void hfi1_reset_vnic_msix_info(struct hfi1_ctxtdata *rcd)
13031{
13032 struct hfi1_devdata *dd = rcd->dd;
13033 struct hfi1_msix_entry *me = &dd->msix_entries[rcd->msix_intr];
13034
13035 if (!me->arg) /* => no irq, no affinity */
13036 return;
13037
13038 hfi1_put_irq_affinity(dd, me);
13039 free_irq(me->msix.vector, me->arg);
13040
13041 me->arg = NULL;
13042}
13043
13044void hfi1_set_vnic_msix_info(struct hfi1_ctxtdata *rcd)
13045{
13046 struct hfi1_devdata *dd = rcd->dd;
13047 struct hfi1_msix_entry *me;
13048 int idx = rcd->ctxt;
13049 void *arg = rcd;
13050 int ret;
13051
13052 rcd->msix_intr = dd->vnic.msix_idx++;
13053 me = &dd->msix_entries[rcd->msix_intr];
13054
13055 /*
13056 * Set the interrupt register and mask for this
13057 * context's interrupt.
13058 */
13059 rcd->ireg = (IS_RCVAVAIL_START + idx) / 64;
13060 rcd->imask = ((u64)1) <<
13061 ((IS_RCVAVAIL_START + idx) % 64);
13062
13063 snprintf(me->name, sizeof(me->name),
13064 DRIVER_NAME "_%d kctxt%d", dd->unit, idx);
13065 me->name[sizeof(me->name) - 1] = 0;
13066 me->type = IRQ_RCVCTXT;
13067
13068 remap_intr(dd, IS_RCVAVAIL_START + idx, rcd->msix_intr);
13069
13070 ret = request_threaded_irq(me->msix.vector, receive_context_interrupt,
13071 receive_context_thread, 0, me->name, arg);
13072 if (ret) {
13073 dd_dev_err(dd, "vnic irq request (vector %d, idx %d) fail %d\n",
13074 me->msix.vector, idx, ret);
13075 return;
13076 }
13077 /*
13078 * assign arg after request_irq call, so it will be
13079 * cleaned up
13080 */
13081 me->arg = arg;
13082
13083 ret = hfi1_get_irq_affinity(dd, me);
13084 if (ret) {
13085 dd_dev_err(dd,
13086 "unable to pin IRQ %d\n", ret);
13087 free_irq(me->msix.vector, me->arg);
13088 }
13089}
13090
77241056
MM		 13091/*
13092 * Set the general handler to accept all interrupts, remap all
13093 * chip interrupts back to MSI-X 0.
13094 */
13095static void reset_interrupts(struct hfi1_devdata *dd)
13096{
13097 int i;
13098
13099 /* all interrupts handled by the general handler */
13100 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
13101 dd->gi_mask[i] = ~(u64)0;
13102
13103 /* all chip interrupts map to MSI-X 0 */
13104 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
8638b77f 13105 write_csr(dd, CCE_INT_MAP + (8 * i), 0);
77241056
MM		 13106}
13107
13108static int set_up_interrupts(struct hfi1_devdata *dd)
13109{
13110 struct hfi1_msix_entry *entries;
13111 u32 total, request;
13112 int i, ret;
13113 int single_interrupt = 0; /* we expect to have all the interrupts */
13114
13115 /*
13116 * Interrupt count:
13117 * 1 general, "slow path" interrupt (includes the SDMA engines
13118 * slow source, SDMACleanupDone)
13119 * N interrupts - one per used SDMA engine
13120 * M interrupt - one per kernel receive context
13121 */
2280740f 13122 total = 1 + dd->num_sdma + dd->n_krcv_queues + HFI1_NUM_VNIC_CTXT;
77241056
MM		 13123
13124 entries = kcalloc(total, sizeof(*entries), GFP_KERNEL);
13125 if (!entries) {
77241056
MM		 13126 ret = -ENOMEM;
13127 goto fail;
13128 }
13129 /* 1-1 MSI-X entry assignment */
13130 for (i = 0; i < total; i++)
13131 entries[i].msix.entry = i;
13132
13133 /* ask for MSI-X interrupts */
13134 request = total;
13135 request_msix(dd, &request, entries);
13136
13137 if (request == 0) {
13138 /* using INTx */
13139 /* dd->num_msix_entries already zero */
13140 kfree(entries);
13141 single_interrupt = 1;
13142 dd_dev_err(dd, "MSI-X failed, using INTx interrupts\n");
13143 } else {
13144 /* using MSI-X */
13145 dd->num_msix_entries = request;
13146 dd->msix_entries = entries;
13147
13148 if (request != total) {
13149 /* using MSI-X, with reduced interrupts */
13150 dd_dev_err(
13151 dd,
13152 "cannot handle reduced interrupt case, want %u, got %u\n",
13153 total, request);
13154 ret = -EINVAL;
13155 goto fail;
13156 }
13157 dd_dev_info(dd, "%u MSI-X interrupts allocated\n", total);
13158 }
13159
13160 /* mask all interrupts */
13161 set_intr_state(dd, 0);
13162 /* clear all pending interrupts */
13163 clear_all_interrupts(dd);
13164
13165 /* reset general handler mask, chip MSI-X mappings */
13166 reset_interrupts(dd);
13167
13168 if (single_interrupt)
13169 ret = request_intx_irq(dd);
13170 else
13171 ret = request_msix_irqs(dd);
13172 if (ret)
13173 goto fail;
13174
13175 return 0;
13176
13177fail:
13178 clean_up_interrupts(dd);
13179 return ret;
13180}
13181
13182/*
13183 * Set up context values in dd. Sets:
13184 *
13185 * num_rcv_contexts - number of contexts being used
13186 * n_krcv_queues - number of kernel contexts
2280740f
VN		 13187 * first_dyn_alloc_ctxt - first dynamically allocated context
13188 * in array of contexts
77241056
MM		 13189 * freectxts - number of free user contexts
13190 * num_send_contexts - number of PIO send contexts being used
13191 */
13192static int set_up_context_variables(struct hfi1_devdata *dd)
13193{
429b6a72 13194 unsigned long num_kernel_contexts;
77241056
MM		 13195 int total_contexts;
13196 int ret;
13197 unsigned ngroups;
8f000f7f
DL		 13198 int qos_rmt_count;
13199 int user_rmt_reduced;
77241056
MM		 13200
13201 /*
33a9eb52 13202 * Kernel receive contexts:
82c2611d 13203 * - Context 0 - control context (VL15/multicast/error)
33a9eb52
DL		 13204 * - Context 1 - first kernel context
13205 * - Context 2 - second kernel context
13206 * ...
77241056
MM		 13207 */
13208 if (n_krcvqs)
82c2611d 13209 /*
33a9eb52
DL		 13210 * n_krcvqs is the sum of module parameter kernel receive
13211 * contexts, krcvqs[]. It does not include the control
13212 * context, so add that.
82c2611d 13213 */
33a9eb52 13214 num_kernel_contexts = n_krcvqs + 1;
77241056 13215 else
8784ac02 13216 num_kernel_contexts = DEFAULT_KRCVQS + 1;
77241056
MM		 13217 /*
13218 * Every kernel receive context needs an ACK send context.
13219 * one send context is allocated for each VL{0-7} and VL15
13220 */
13221 if (num_kernel_contexts > (dd->chip_send_contexts - num_vls - 1)) {
13222 dd_dev_err(dd,
429b6a72 13223 "Reducing # kernel rcv contexts to: %d, from %lu\n",
77241056 13224 (int)(dd->chip_send_contexts - num_vls - 1),
429b6a72 13225 num_kernel_contexts);
77241056
MM		 13226 num_kernel_contexts = dd->chip_send_contexts - num_vls - 1;
13227 }
13228 /*
0852d241
JJ		 13229 * User contexts:
13230 * - default to 1 user context per real (non-HT) CPU core if
13231 * num_user_contexts is negative
77241056 13232 */
2ce6bf22 13233 if (num_user_contexts < 0)
0852d241 13234 num_user_contexts =
4197344b 13235 cpumask_weight(&node_affinity.real_cpu_mask);
77241056
MM		 13236
13237 total_contexts = num_kernel_contexts + num_user_contexts;
13238
13239 /*
13240 * Adjust the counts given a global max.
13241 */
13242 if (total_contexts > dd->chip_rcv_contexts) {
13243 dd_dev_err(dd,
13244 "Reducing # user receive contexts to: %d, from %d\n",
13245 (int)(dd->chip_rcv_contexts - num_kernel_contexts),
13246 (int)num_user_contexts);
13247 num_user_contexts = dd->chip_rcv_contexts - num_kernel_contexts;
13248 /* recalculate */
13249 total_contexts = num_kernel_contexts + num_user_contexts;
13250 }
13251
8f000f7f
DL		 13252 /* each user context requires an entry in the RMT */
13253 qos_rmt_count = qos_rmt_entries(dd, NULL, NULL);
13254 if (qos_rmt_count + num_user_contexts > NUM_MAP_ENTRIES) {
13255 user_rmt_reduced = NUM_MAP_ENTRIES - qos_rmt_count;
13256 dd_dev_err(dd,
13257 "RMT size is reducing the number of user receive contexts from %d to %d\n",
13258 (int)num_user_contexts,
13259 user_rmt_reduced);
13260 /* recalculate */
13261 num_user_contexts = user_rmt_reduced;
13262 total_contexts = num_kernel_contexts + num_user_contexts;
13263 }
13264
2280740f
VN		 13265 /* Accommodate VNIC contexts */
13266 if ((total_contexts + HFI1_NUM_VNIC_CTXT) <= dd->chip_rcv_contexts)
13267 total_contexts += HFI1_NUM_VNIC_CTXT;
13268
13269 /* the first N are kernel contexts, the rest are user/vnic contexts */
77241056
MM		 13270 dd->num_rcv_contexts = total_contexts;
13271 dd->n_krcv_queues = num_kernel_contexts;
2280740f 13272 dd->first_dyn_alloc_ctxt = num_kernel_contexts;
affa48de 13273 dd->num_user_contexts = num_user_contexts;
77241056
MM		 13274 dd->freectxts = num_user_contexts;
13275 dd_dev_info(dd,
17fb4f29
JJ		 13276 "rcv contexts: chip %d, used %d (kernel %d, user %d)\n",
13277 (int)dd->chip_rcv_contexts,
13278 (int)dd->num_rcv_contexts,
13279 (int)dd->n_krcv_queues,
13280 (int)dd->num_rcv_contexts - dd->n_krcv_queues);
77241056
MM		 13281
13282 /*
13283 * Receive array allocation:
13284 * All RcvArray entries are divided into groups of 8. This
13285 * is required by the hardware and will speed up writes to
13286 * consecutive entries by using write-combining of the entire
13287 * cacheline.
13288 *
13289 * The number of groups are evenly divided among all contexts.
13290 * any left over groups will be given to the first N user
13291 * contexts.
13292 */
13293 dd->rcv_entries.group_size = RCV_INCREMENT;
13294 ngroups = dd->chip_rcv_array_count / dd->rcv_entries.group_size;
13295 dd->rcv_entries.ngroups = ngroups / dd->num_rcv_contexts;
13296 dd->rcv_entries.nctxt_extra = ngroups -
13297 (dd->num_rcv_contexts * dd->rcv_entries.ngroups);
13298 dd_dev_info(dd, "RcvArray groups %u, ctxts extra %u\n",
13299 dd->rcv_entries.ngroups,
13300 dd->rcv_entries.nctxt_extra);
13301 if (dd->rcv_entries.ngroups * dd->rcv_entries.group_size >
13302 MAX_EAGER_ENTRIES * 2) {
13303 dd->rcv_entries.ngroups = (MAX_EAGER_ENTRIES * 2) /
13304 dd->rcv_entries.group_size;
13305 dd_dev_info(dd,
17fb4f29
JJ		 13306 "RcvArray group count too high, change to %u\n",
13307 dd->rcv_entries.ngroups);
77241056
MM		 13308 dd->rcv_entries.nctxt_extra = 0;
13309 }
13310 /*
13311 * PIO send contexts
13312 */
13313 ret = init_sc_pools_and_sizes(dd);
13314 if (ret >= 0) { /* success */
13315 dd->num_send_contexts = ret;
13316 dd_dev_info(
13317 dd,
44306f15 13318 "send contexts: chip %d, used %d (kernel %d, ack %d, user %d, vl15 %d)\n",
77241056
MM		 13319 dd->chip_send_contexts,
13320 dd->num_send_contexts,
13321 dd->sc_sizes[SC_KERNEL].count,
13322 dd->sc_sizes[SC_ACK].count,
44306f15
JX		 13323 dd->sc_sizes[SC_USER].count,
13324 dd->sc_sizes[SC_VL15].count);
77241056
MM		 13325 ret = 0; /* success */
13326 }
13327
13328 return ret;
13329}
13330
13331/*
13332 * Set the device/port partition key table. The MAD code
13333 * will ensure that, at least, the partial management
13334 * partition key is present in the table.
13335 */
13336static void set_partition_keys(struct hfi1_pportdata *ppd)
13337{
13338 struct hfi1_devdata *dd = ppd->dd;
13339 u64 reg = 0;
13340 int i;
13341
13342 dd_dev_info(dd, "Setting partition keys\n");
13343 for (i = 0; i < hfi1_get_npkeys(dd); i++) {
13344 reg |= (ppd->pkeys[i] &
13345 RCV_PARTITION_KEY_PARTITION_KEY_A_MASK) <<
13346 ((i % 4) *
13347 RCV_PARTITION_KEY_PARTITION_KEY_B_SHIFT);
13348 /* Each register holds 4 PKey values. */
13349 if ((i % 4) == 3) {
13350 write_csr(dd, RCV_PARTITION_KEY +
13351 ((i - 3) * 2), reg);
13352 reg = 0;
13353 }
13354 }
13355
13356 /* Always enable HW pkeys check when pkeys table is set */
13357 add_rcvctrl(dd, RCV_CTRL_RCV_PARTITION_KEY_ENABLE_SMASK);
13358}
13359
13360/*
13361 * These CSRs and memories are uninitialized on reset and must be
13362 * written before reading to set the ECC/parity bits.
13363 *
13364 * NOTE: All user context CSRs that are not mmaped write-only
13365 * (e.g. the TID flows) must be initialized even if the driver never
13366 * reads them.
13367 */
13368static void write_uninitialized_csrs_and_memories(struct hfi1_devdata *dd)
13369{
13370 int i, j;
13371
13372 /* CceIntMap */
13373 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
8638b77f 13374 write_csr(dd, CCE_INT_MAP + (8 * i), 0);
77241056
MM		 13375
13376 /* SendCtxtCreditReturnAddr */
13377 for (i = 0; i < dd->chip_send_contexts; i++)
13378 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0);
13379
13380 /* PIO Send buffers */
13381 /* SDMA Send buffers */
4d114fdd
JJ		 13382 /*
13383 * These are not normally read, and (presently) have no method
13384 * to be read, so are not pre-initialized
13385 */
77241056
MM		 13386
13387 /* RcvHdrAddr */
13388 /* RcvHdrTailAddr */
13389 /* RcvTidFlowTable */
13390 for (i = 0; i < dd->chip_rcv_contexts; i++) {
13391 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0);
13392 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0);
13393 for (j = 0; j < RXE_NUM_TID_FLOWS; j++)
8638b77f 13394 write_uctxt_csr(dd, i, RCV_TID_FLOW_TABLE + (8 * j), 0);
77241056
MM		 13395 }
13396
13397 /* RcvArray */
13398 for (i = 0; i < dd->chip_rcv_array_count; i++)
8638b77f 13399 write_csr(dd, RCV_ARRAY + (8 * i),
17fb4f29 13400 RCV_ARRAY_RT_WRITE_ENABLE_SMASK);
77241056
MM		 13401
13402 /* RcvQPMapTable */
13403 for (i = 0; i < 32; i++)
13404 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
13405}
13406
13407/*
13408 * Use the ctrl_bits in CceCtrl to clear the status_bits in CceStatus.
13409 */
13410static void clear_cce_status(struct hfi1_devdata *dd, u64 status_bits,
13411 u64 ctrl_bits)
13412{
13413 unsigned long timeout;
13414 u64 reg;
13415
13416 /* is the condition present? */
13417 reg = read_csr(dd, CCE_STATUS);
13418 if ((reg & status_bits) == 0)
13419 return;
13420
13421 /* clear the condition */
13422 write_csr(dd, CCE_CTRL, ctrl_bits);
13423
13424 /* wait for the condition to clear */
13425 timeout = jiffies + msecs_to_jiffies(CCE_STATUS_TIMEOUT);
13426 while (1) {
13427 reg = read_csr(dd, CCE_STATUS);
13428 if ((reg & status_bits) == 0)
13429 return;
13430 if (time_after(jiffies, timeout)) {
13431 dd_dev_err(dd,
17fb4f29
JJ		 13432 "Timeout waiting for CceStatus to clear bits 0x%llx, remaining 0x%llx\n",
13433 status_bits, reg & status_bits);
77241056
MM		 13434 return;
13435 }
13436 udelay(1);
13437 }
13438}
13439
13440/* set CCE CSRs to chip reset defaults */
13441static void reset_cce_csrs(struct hfi1_devdata *dd)
13442{
13443 int i;
13444
13445 /* CCE_REVISION read-only */
13446 /* CCE_REVISION2 read-only */
13447 /* CCE_CTRL - bits clear automatically */
13448 /* CCE_STATUS read-only, use CceCtrl to clear */
13449 clear_cce_status(dd, ALL_FROZE, CCE_CTRL_SPC_UNFREEZE_SMASK);
13450 clear_cce_status(dd, ALL_TXE_PAUSE, CCE_CTRL_TXE_RESUME_SMASK);
13451 clear_cce_status(dd, ALL_RXE_PAUSE, CCE_CTRL_RXE_RESUME_SMASK);
13452 for (i = 0; i < CCE_NUM_SCRATCH; i++)
13453 write_csr(dd, CCE_SCRATCH + (8 * i), 0);
13454 /* CCE_ERR_STATUS read-only */
13455 write_csr(dd, CCE_ERR_MASK, 0);
13456 write_csr(dd, CCE_ERR_CLEAR, ~0ull);
13457 /* CCE_ERR_FORCE leave alone */
13458 for (i = 0; i < CCE_NUM_32_BIT_COUNTERS; i++)
13459 write_csr(dd, CCE_COUNTER_ARRAY32 + (8 * i), 0);
13460 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_RESETCSR);
13461 /* CCE_PCIE_CTRL leave alone */
13462 for (i = 0; i < CCE_NUM_MSIX_VECTORS; i++) {
13463 write_csr(dd, CCE_MSIX_TABLE_LOWER + (8 * i), 0);
13464 write_csr(dd, CCE_MSIX_TABLE_UPPER + (8 * i),
17fb4f29 13465 CCE_MSIX_TABLE_UPPER_RESETCSR);
77241056
MM		 13466 }
13467 for (i = 0; i < CCE_NUM_MSIX_PBAS; i++) {
13468 /* CCE_MSIX_PBA read-only */
13469 write_csr(dd, CCE_MSIX_INT_GRANTED, ~0ull);
13470 write_csr(dd, CCE_MSIX_VEC_CLR_WITHOUT_INT, ~0ull);
13471 }
13472 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
13473 write_csr(dd, CCE_INT_MAP, 0);
13474 for (i = 0; i < CCE_NUM_INT_CSRS; i++) {
13475 /* CCE_INT_STATUS read-only */
13476 write_csr(dd, CCE_INT_MASK + (8 * i), 0);
13477 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~0ull);
13478 /* CCE_INT_FORCE leave alone */
13479 /* CCE_INT_BLOCKED read-only */
13480 }
13481 for (i = 0; i < CCE_NUM_32_BIT_INT_COUNTERS; i++)
13482 write_csr(dd, CCE_INT_COUNTER_ARRAY32 + (8 * i), 0);
13483}
13484
77241056
MM		 13485/* set MISC CSRs to chip reset defaults */
13486static void reset_misc_csrs(struct hfi1_devdata *dd)
13487{
13488 int i;
13489
13490 for (i = 0; i < 32; i++) {
13491 write_csr(dd, MISC_CFG_RSA_R2 + (8 * i), 0);
13492 write_csr(dd, MISC_CFG_RSA_SIGNATURE + (8 * i), 0);
13493 write_csr(dd, MISC_CFG_RSA_MODULUS + (8 * i), 0);
13494 }
4d114fdd
JJ		 13495 /*
13496 * MISC_CFG_SHA_PRELOAD leave alone - always reads 0 and can
13497 * only be written 128-byte chunks
13498 */
77241056
MM		 13499 /* init RSA engine to clear lingering errors */
13500 write_csr(dd, MISC_CFG_RSA_CMD, 1);
13501 write_csr(dd, MISC_CFG_RSA_MU, 0);
13502 write_csr(dd, MISC_CFG_FW_CTRL, 0);
13503 /* MISC_STS_8051_DIGEST read-only */
13504 /* MISC_STS_SBM_DIGEST read-only */
13505 /* MISC_STS_PCIE_DIGEST read-only */
13506 /* MISC_STS_FAB_DIGEST read-only */
13507 /* MISC_ERR_STATUS read-only */
13508 write_csr(dd, MISC_ERR_MASK, 0);
13509 write_csr(dd, MISC_ERR_CLEAR, ~0ull);
13510 /* MISC_ERR_FORCE leave alone */
13511}
13512
13513/* set TXE CSRs to chip reset defaults */
13514static void reset_txe_csrs(struct hfi1_devdata *dd)
13515{
13516 int i;
13517
13518 /*
13519 * TXE Kernel CSRs
13520 */
13521 write_csr(dd, SEND_CTRL, 0);
13522 __cm_reset(dd, 0); /* reset CM internal state */
13523 /* SEND_CONTEXTS read-only */
13524 /* SEND_DMA_ENGINES read-only */
13525 /* SEND_PIO_MEM_SIZE read-only */
13526 /* SEND_DMA_MEM_SIZE read-only */
13527 write_csr(dd, SEND_HIGH_PRIORITY_LIMIT, 0);
13528 pio_reset_all(dd); /* SEND_PIO_INIT_CTXT */
13529 /* SEND_PIO_ERR_STATUS read-only */
13530 write_csr(dd, SEND_PIO_ERR_MASK, 0);
13531 write_csr(dd, SEND_PIO_ERR_CLEAR, ~0ull);
13532 /* SEND_PIO_ERR_FORCE leave alone */
13533 /* SEND_DMA_ERR_STATUS read-only */
13534 write_csr(dd, SEND_DMA_ERR_MASK, 0);
13535 write_csr(dd, SEND_DMA_ERR_CLEAR, ~0ull);
13536 /* SEND_DMA_ERR_FORCE leave alone */
13537 /* SEND_EGRESS_ERR_STATUS read-only */
13538 write_csr(dd, SEND_EGRESS_ERR_MASK, 0);
13539 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~0ull);
13540 /* SEND_EGRESS_ERR_FORCE leave alone */
13541 write_csr(dd, SEND_BTH_QP, 0);
13542 write_csr(dd, SEND_STATIC_RATE_CONTROL, 0);
13543 write_csr(dd, SEND_SC2VLT0, 0);
13544 write_csr(dd, SEND_SC2VLT1, 0);
13545 write_csr(dd, SEND_SC2VLT2, 0);
13546 write_csr(dd, SEND_SC2VLT3, 0);
13547 write_csr(dd, SEND_LEN_CHECK0, 0);
13548 write_csr(dd, SEND_LEN_CHECK1, 0);
13549 /* SEND_ERR_STATUS read-only */
13550 write_csr(dd, SEND_ERR_MASK, 0);
13551 write_csr(dd, SEND_ERR_CLEAR, ~0ull);
13552 /* SEND_ERR_FORCE read-only */
13553 for (i = 0; i < VL_ARB_LOW_PRIO_TABLE_SIZE; i++)
8638b77f 13554 write_csr(dd, SEND_LOW_PRIORITY_LIST + (8 * i), 0);
77241056 13555 for (i = 0; i < VL_ARB_HIGH_PRIO_TABLE_SIZE; i++)
8638b77f
JJ		 13556 write_csr(dd, SEND_HIGH_PRIORITY_LIST + (8 * i), 0);
13557 for (i = 0; i < dd->chip_send_contexts / NUM_CONTEXTS_PER_SET; i++)
13558 write_csr(dd, SEND_CONTEXT_SET_CTRL + (8 * i), 0);
77241056 13559 for (i = 0; i < TXE_NUM_32_BIT_COUNTER; i++)
8638b77f 13560 write_csr(dd, SEND_COUNTER_ARRAY32 + (8 * i), 0);
77241056 13561 for (i = 0; i < TXE_NUM_64_BIT_COUNTER; i++)
8638b77f 13562 write_csr(dd, SEND_COUNTER_ARRAY64 + (8 * i), 0);
77241056 13563 write_csr(dd, SEND_CM_CTRL, SEND_CM_CTRL_RESETCSR);
17fb4f29 13564 write_csr(dd, SEND_CM_GLOBAL_CREDIT, SEND_CM_GLOBAL_CREDIT_RESETCSR);
77241056
MM		 13565 /* SEND_CM_CREDIT_USED_STATUS read-only */
13566 write_csr(dd, SEND_CM_TIMER_CTRL, 0);
13567 write_csr(dd, SEND_CM_LOCAL_AU_TABLE0_TO3, 0);
13568 write_csr(dd, SEND_CM_LOCAL_AU_TABLE4_TO7, 0);
13569 write_csr(dd, SEND_CM_REMOTE_AU_TABLE0_TO3, 0);
13570 write_csr(dd, SEND_CM_REMOTE_AU_TABLE4_TO7, 0);
13571 for (i = 0; i < TXE_NUM_DATA_VL; i++)
8638b77f 13572 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
77241056
MM		 13573 write_csr(dd, SEND_CM_CREDIT_VL15, 0);
13574 /* SEND_CM_CREDIT_USED_VL read-only */
13575 /* SEND_CM_CREDIT_USED_VL15 read-only */
13576 /* SEND_EGRESS_CTXT_STATUS read-only */
13577 /* SEND_EGRESS_SEND_DMA_STATUS read-only */
13578 write_csr(dd, SEND_EGRESS_ERR_INFO, ~0ull);
13579 /* SEND_EGRESS_ERR_INFO read-only */
13580 /* SEND_EGRESS_ERR_SOURCE read-only */
13581
13582 /*
13583 * TXE Per-Context CSRs
13584 */
13585 for (i = 0; i < dd->chip_send_contexts; i++) {
13586 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0);
13587 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_CTRL, 0);
13588 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0);
13589 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_FORCE, 0);
13590 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, 0);
13591 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~0ull);
13592 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_ENABLE, 0);
13593 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_VL, 0);
13594 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_JOB_KEY, 0);
13595 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_PARTITION_KEY, 0);
13596 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, 0);
13597 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_OPCODE, 0);
13598 }
13599
13600 /*
13601 * TXE Per-SDMA CSRs
13602 */
13603 for (i = 0; i < dd->chip_sdma_engines; i++) {
13604 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0);
13605 /* SEND_DMA_STATUS read-only */
13606 write_kctxt_csr(dd, i, SEND_DMA_BASE_ADDR, 0);
13607 write_kctxt_csr(dd, i, SEND_DMA_LEN_GEN, 0);
13608 write_kctxt_csr(dd, i, SEND_DMA_TAIL, 0);
13609 /* SEND_DMA_HEAD read-only */
13610 write_kctxt_csr(dd, i, SEND_DMA_HEAD_ADDR, 0);
13611 write_kctxt_csr(dd, i, SEND_DMA_PRIORITY_THLD, 0);
13612 /* SEND_DMA_IDLE_CNT read-only */
13613 write_kctxt_csr(dd, i, SEND_DMA_RELOAD_CNT, 0);
13614 write_kctxt_csr(dd, i, SEND_DMA_DESC_CNT, 0);
13615 /* SEND_DMA_DESC_FETCHED_CNT read-only */
13616 /* SEND_DMA_ENG_ERR_STATUS read-only */
13617 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, 0);
13618 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~0ull);
13619 /* SEND_DMA_ENG_ERR_FORCE leave alone */
13620 write_kctxt_csr(dd, i, SEND_DMA_CHECK_ENABLE, 0);
13621 write_kctxt_csr(dd, i, SEND_DMA_CHECK_VL, 0);
13622 write_kctxt_csr(dd, i, SEND_DMA_CHECK_JOB_KEY, 0);
13623 write_kctxt_csr(dd, i, SEND_DMA_CHECK_PARTITION_KEY, 0);
13624 write_kctxt_csr(dd, i, SEND_DMA_CHECK_SLID, 0);
13625 write_kctxt_csr(dd, i, SEND_DMA_CHECK_OPCODE, 0);
13626 write_kctxt_csr(dd, i, SEND_DMA_MEMORY, 0);
13627 }
13628}
13629
13630/*
13631 * Expect on entry:
13632 * o Packet ingress is disabled, i.e. RcvCtrl.RcvPortEnable == 0
13633 */
13634static void init_rbufs(struct hfi1_devdata *dd)
13635{
13636 u64 reg;
13637 int count;
13638
13639 /*
13640 * Wait for DMA to stop: RxRbufPktPending and RxPktInProgress are
13641 * clear.
13642 */
13643 count = 0;
13644 while (1) {
13645 reg = read_csr(dd, RCV_STATUS);
13646 if ((reg & (RCV_STATUS_RX_RBUF_PKT_PENDING_SMASK
13647 | RCV_STATUS_RX_PKT_IN_PROGRESS_SMASK)) == 0)
13648 break;
13649 /*
13650 * Give up after 1ms - maximum wait time.
13651 *
e8a70af2 13652 * RBuf size is 136KiB. Slowest possible is PCIe Gen1 x1 at
77241056 13653 * 250MB/s bandwidth. Lower rate to 66% for overhead to get:
e8a70af2 13654 * 136 KB / (66% * 250MB/s) = 844us
77241056
MM		 13655 */
13656 if (count++ > 500) {
13657 dd_dev_err(dd,
17fb4f29
JJ		 13658 "%s: in-progress DMA not clearing: RcvStatus 0x%llx, continuing\n",
13659 __func__, reg);
77241056
MM		 13660 break;
13661 }
13662 udelay(2); /* do not busy-wait the CSR */
13663 }
13664
13665 /* start the init - expect RcvCtrl to be 0 */
13666 write_csr(dd, RCV_CTRL, RCV_CTRL_RX_RBUF_INIT_SMASK);
13667
13668 /*
13669 * Read to force the write of Rcvtrl.RxRbufInit. There is a brief
13670 * period after the write before RcvStatus.RxRbufInitDone is valid.
13671 * The delay in the first run through the loop below is sufficient and
13672 * required before the first read of RcvStatus.RxRbufInintDone.
13673 */
13674 read_csr(dd, RCV_CTRL);
13675
13676 /* wait for the init to finish */
13677 count = 0;
13678 while (1) {
13679 /* delay is required first time through - see above */
13680 udelay(2); /* do not busy-wait the CSR */
13681 reg = read_csr(dd, RCV_STATUS);
13682 if (reg & (RCV_STATUS_RX_RBUF_INIT_DONE_SMASK))
13683 break;
13684
13685 /* give up after 100us - slowest possible at 33MHz is 73us */
13686 if (count++ > 50) {
13687 dd_dev_err(dd,
17fb4f29
JJ		 13688 "%s: RcvStatus.RxRbufInit not set, continuing\n",
13689 __func__);
77241056
MM		 13690 break;
13691 }
13692 }
13693}
13694
13695/* set RXE CSRs to chip reset defaults */
13696static void reset_rxe_csrs(struct hfi1_devdata *dd)
13697{
13698 int i, j;
13699
13700 /*
13701 * RXE Kernel CSRs
13702 */
13703 write_csr(dd, RCV_CTRL, 0);
13704 init_rbufs(dd);
13705 /* RCV_STATUS read-only */
13706 /* RCV_CONTEXTS read-only */
13707 /* RCV_ARRAY_CNT read-only */
13708 /* RCV_BUF_SIZE read-only */
13709 write_csr(dd, RCV_BTH_QP, 0);
13710 write_csr(dd, RCV_MULTICAST, 0);
13711 write_csr(dd, RCV_BYPASS, 0);
13712 write_csr(dd, RCV_VL15, 0);
13713 /* this is a clear-down */
13714 write_csr(dd, RCV_ERR_INFO,
17fb4f29 13715 RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SMASK);
77241056
MM		 13716 /* RCV_ERR_STATUS read-only */
13717 write_csr(dd, RCV_ERR_MASK, 0);
13718 write_csr(dd, RCV_ERR_CLEAR, ~0ull);
13719 /* RCV_ERR_FORCE leave alone */
13720 for (i = 0; i < 32; i++)
13721 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
13722 for (i = 0; i < 4; i++)
13723 write_csr(dd, RCV_PARTITION_KEY + (8 * i), 0);
13724 for (i = 0; i < RXE_NUM_32_BIT_COUNTERS; i++)
13725 write_csr(dd, RCV_COUNTER_ARRAY32 + (8 * i), 0);
13726 for (i = 0; i < RXE_NUM_64_BIT_COUNTERS; i++)
13727 write_csr(dd, RCV_COUNTER_ARRAY64 + (8 * i), 0);
2280740f
VN		 13728 for (i = 0; i < RXE_NUM_RSM_INSTANCES; i++)
13729 clear_rsm_rule(dd, i);
77241056
MM		 13730 for (i = 0; i < 32; i++)
13731 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), 0);
13732
13733 /*
13734 * RXE Kernel and User Per-Context CSRs
13735 */
13736 for (i = 0; i < dd->chip_rcv_contexts; i++) {
13737 /* kernel */
13738 write_kctxt_csr(dd, i, RCV_CTXT_CTRL, 0);
13739 /* RCV_CTXT_STATUS read-only */
13740 write_kctxt_csr(dd, i, RCV_EGR_CTRL, 0);
13741 write_kctxt_csr(dd, i, RCV_TID_CTRL, 0);
13742 write_kctxt_csr(dd, i, RCV_KEY_CTRL, 0);
13743 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0);
13744 write_kctxt_csr(dd, i, RCV_HDR_CNT, 0);
13745 write_kctxt_csr(dd, i, RCV_HDR_ENT_SIZE, 0);
13746 write_kctxt_csr(dd, i, RCV_HDR_SIZE, 0);
13747 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0);
13748 write_kctxt_csr(dd, i, RCV_AVAIL_TIME_OUT, 0);
13749 write_kctxt_csr(dd, i, RCV_HDR_OVFL_CNT, 0);
13750
13751 /* user */
13752 /* RCV_HDR_TAIL read-only */
13753 write_uctxt_csr(dd, i, RCV_HDR_HEAD, 0);
13754 /* RCV_EGR_INDEX_TAIL read-only */
13755 write_uctxt_csr(dd, i, RCV_EGR_INDEX_HEAD, 0);
13756 /* RCV_EGR_OFFSET_TAIL read-only */
13757 for (j = 0; j < RXE_NUM_TID_FLOWS; j++) {
17fb4f29
JJ		 13758 write_uctxt_csr(dd, i,
13759 RCV_TID_FLOW_TABLE + (8 * j), 0);
77241056
MM		 13760 }
13761 }
13762}
13763
13764/*
13765 * Set sc2vl tables.
13766 *
13767 * They power on to zeros, so to avoid send context errors
13768 * they need to be set:
13769 *
13770 * SC 0-7 -> VL 0-7 (respectively)
13771 * SC 15 -> VL 15
13772 * otherwise
13773 * -> VL 0
13774 */
13775static void init_sc2vl_tables(struct hfi1_devdata *dd)
13776{
13777 int i;
13778 /* init per architecture spec, constrained by hardware capability */
13779
13780 /* HFI maps sent packets */
13781 write_csr(dd, SEND_SC2VLT0, SC2VL_VAL(
13782 0,
13783 0, 0, 1, 1,
13784 2, 2, 3, 3,
13785 4, 4, 5, 5,
13786 6, 6, 7, 7));
13787 write_csr(dd, SEND_SC2VLT1, SC2VL_VAL(
13788 1,
13789 8, 0, 9, 0,
13790 10, 0, 11, 0,
13791 12, 0, 13, 0,
13792 14, 0, 15, 15));
13793 write_csr(dd, SEND_SC2VLT2, SC2VL_VAL(
13794 2,
13795 16, 0, 17, 0,
13796 18, 0, 19, 0,
13797 20, 0, 21, 0,
13798 22, 0, 23, 0));
13799 write_csr(dd, SEND_SC2VLT3, SC2VL_VAL(
13800 3,
13801 24, 0, 25, 0,
13802 26, 0, 27, 0,
13803 28, 0, 29, 0,
13804 30, 0, 31, 0));
13805
13806 /* DC maps received packets */
13807 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, DC_SC_VL_VAL(
13808 15_0,
13809 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
13810 8, 0, 9, 0, 10, 0, 11, 0, 12, 0, 13, 0, 14, 0, 15, 15));
13811 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, DC_SC_VL_VAL(
13812 31_16,
13813 16, 0, 17, 0, 18, 0, 19, 0, 20, 0, 21, 0, 22, 0, 23, 0,
13814 24, 0, 25, 0, 26, 0, 27, 0, 28, 0, 29, 0, 30, 0, 31, 0));
13815
13816 /* initialize the cached sc2vl values consistently with h/w */
13817 for (i = 0; i < 32; i++) {
13818 if (i < 8 || i == 15)
13819 *((u8 *)(dd->sc2vl) + i) = (u8)i;
13820 else
13821 *((u8 *)(dd->sc2vl) + i) = 0;
13822 }
13823}
13824
13825/*
13826 * Read chip sizes and then reset parts to sane, disabled, values. We cannot
13827 * depend on the chip going through a power-on reset - a driver may be loaded
13828 * and unloaded many times.
13829 *
13830 * Do not write any CSR values to the chip in this routine - there may be
13831 * a reset following the (possible) FLR in this routine.
13832 *
13833 */
13834static void init_chip(struct hfi1_devdata *dd)
13835{
13836 int i;
13837
13838 /*
13839 * Put the HFI CSRs in a known state.
13840 * Combine this with a DC reset.
13841 *
13842 * Stop the device from doing anything while we do a
13843 * reset. We know there are no other active users of
13844 * the device since we are now in charge. Turn off
13845 * off all outbound and inbound traffic and make sure
13846 * the device does not generate any interrupts.
13847 */
13848
13849 /* disable send contexts and SDMA engines */
13850 write_csr(dd, SEND_CTRL, 0);
13851 for (i = 0; i < dd->chip_send_contexts; i++)
13852 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0);
13853 for (i = 0; i < dd->chip_sdma_engines; i++)
13854 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0);
13855 /* disable port (turn off RXE inbound traffic) and contexts */
13856 write_csr(dd, RCV_CTRL, 0);
13857 for (i = 0; i < dd->chip_rcv_contexts; i++)
13858 write_csr(dd, RCV_CTXT_CTRL, 0);
13859 /* mask all interrupt sources */
13860 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
8638b77f 13861 write_csr(dd, CCE_INT_MASK + (8 * i), 0ull);
77241056
MM		 13862
13863 /*
13864 * DC Reset: do a full DC reset before the register clear.
13865 * A recommended length of time to hold is one CSR read,
13866 * so reread the CceDcCtrl. Then, hold the DC in reset
13867 * across the clear.
13868 */
13869 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK);
50e5dcbe 13870 (void)read_csr(dd, CCE_DC_CTRL);
77241056
MM		 13871
13872 if (use_flr) {
13873 /*
13874 * A FLR will reset the SPC core and part of the PCIe.
13875 * The parts that need to be restored have already been
13876 * saved.
13877 */
13878 dd_dev_info(dd, "Resetting CSRs with FLR\n");
13879
13880 /* do the FLR, the DC reset will remain */
21c433a7 13881 pcie_flr(dd->pcidev);
77241056
MM		 13882
13883 /* restore command and BARs */
13884 restore_pci_variables(dd);
13885
995deafa 13886 if (is_ax(dd)) {
77241056 13887 dd_dev_info(dd, "Resetting CSRs with FLR\n");
21c433a7 13888 pcie_flr(dd->pcidev);
77241056
MM		 13889 restore_pci_variables(dd);
13890 }
77241056
MM		 13891 } else {
13892 dd_dev_info(dd, "Resetting CSRs with writes\n");
13893 reset_cce_csrs(dd);
13894 reset_txe_csrs(dd);
13895 reset_rxe_csrs(dd);
77241056
MM		 13896 reset_misc_csrs(dd);
13897 }
13898 /* clear the DC reset */
13899 write_csr(dd, CCE_DC_CTRL, 0);
7c03ed85 13900
77241056 13901 /* Set the LED off */
773d0451
SS		 13902 setextled(dd, 0);
13903
77241056
MM		 13904 /*
13905 * Clear the QSFP reset.
72a67ba2 13906 * An FLR enforces a 0 on all out pins. The driver does not touch
77241056 13907 * ASIC_QSFPn_OUT otherwise. This leaves RESET_N low and
72a67ba2 13908 * anything plugged constantly in reset, if it pays attention
77241056 13909 * to RESET_N.
72a67ba2 13910 * Prime examples of this are optical cables. Set all pins high.
77241056
MM		 13911 * I2CCLK and I2CDAT will change per direction, and INT_N and
13912 * MODPRS_N are input only and their value is ignored.
13913 */
72a67ba2
EH		 13914 write_csr(dd, ASIC_QSFP1_OUT, 0x1f);
13915 write_csr(dd, ASIC_QSFP2_OUT, 0x1f);
a2ee27a4 13916 init_chip_resources(dd);
77241056
MM		 13917}
13918
13919static void init_early_variables(struct hfi1_devdata *dd)
13920{
13921 int i;
13922
13923 /* assign link credit variables */
13924 dd->vau = CM_VAU;
13925 dd->link_credits = CM_GLOBAL_CREDITS;
995deafa 13926 if (is_ax(dd))
77241056
MM		 13927 dd->link_credits--;
13928 dd->vcu = cu_to_vcu(hfi1_cu);
13929 /* enough room for 8 MAD packets plus header - 17K */
13930 dd->vl15_init = (8 * (2048 + 128)) / vau_to_au(dd->vau);
13931 if (dd->vl15_init > dd->link_credits)
13932 dd->vl15_init = dd->link_credits;
13933
13934 write_uninitialized_csrs_and_memories(dd);
13935
13936 if (HFI1_CAP_IS_KSET(PKEY_CHECK))
13937 for (i = 0; i < dd->num_pports; i++) {
13938 struct hfi1_pportdata *ppd = &dd->pport[i];
13939
13940 set_partition_keys(ppd);
13941 }
13942 init_sc2vl_tables(dd);
13943}
13944
13945static void init_kdeth_qp(struct hfi1_devdata *dd)
13946{
13947 /* user changed the KDETH_QP */
13948 if (kdeth_qp != 0 && kdeth_qp >= 0xff) {
13949 /* out of range or illegal value */
13950 dd_dev_err(dd, "Invalid KDETH queue pair prefix, ignoring");
13951 kdeth_qp = 0;
13952 }
13953 if (kdeth_qp == 0) /* not set, or failed range check */
13954 kdeth_qp = DEFAULT_KDETH_QP;
13955
13956 write_csr(dd, SEND_BTH_QP,
17fb4f29
JJ		 13957 (kdeth_qp & SEND_BTH_QP_KDETH_QP_MASK) <<
13958 SEND_BTH_QP_KDETH_QP_SHIFT);
77241056
MM		 13959
13960 write_csr(dd, RCV_BTH_QP,
17fb4f29
JJ		 13961 (kdeth_qp & RCV_BTH_QP_KDETH_QP_MASK) <<
13962 RCV_BTH_QP_KDETH_QP_SHIFT);
77241056
MM		 13963}
13964
13965/**
13966 * init_qpmap_table
13967 * @dd - device data
13968 * @first_ctxt - first context
13969 * @last_ctxt - first context
13970 *
13971 * This return sets the qpn mapping table that
13972 * is indexed by qpn[8:1].
13973 *
13974 * The routine will round robin the 256 settings
13975 * from first_ctxt to last_ctxt.
13976 *
13977 * The first/last looks ahead to having specialized
13978 * receive contexts for mgmt and bypass. Normal
13979 * verbs traffic will assumed to be on a range
13980 * of receive contexts.
13981 */
13982static void init_qpmap_table(struct hfi1_devdata *dd,
13983 u32 first_ctxt,
13984 u32 last_ctxt)
13985{
13986 u64 reg = 0;
13987 u64 regno = RCV_QP_MAP_TABLE;
13988 int i;
13989 u64 ctxt = first_ctxt;
13990
60d585ad 13991 for (i = 0; i < 256; i++) {
77241056 13992 reg |= ctxt << (8 * (i % 8));
77241056
MM		 13993 ctxt++;
13994 if (ctxt > last_ctxt)
13995 ctxt = first_ctxt;
60d585ad 13996 if (i % 8 == 7) {
77241056
MM		 13997 write_csr(dd, regno, reg);
13998 reg = 0;
13999 regno += 8;
14000 }
14001 }
77241056
MM		 14002
14003 add_rcvctrl(dd, RCV_CTRL_RCV_QP_MAP_ENABLE_SMASK
14004 | RCV_CTRL_RCV_BYPASS_ENABLE_SMASK);
14005}
14006
372cc85a
DL		 14007struct rsm_map_table {
14008 u64 map[NUM_MAP_REGS];
14009 unsigned int used;
14010};
14011
b12349ae
DL		 14012struct rsm_rule_data {
14013 u8 offset;
14014 u8 pkt_type;
14015 u32 field1_off;
14016 u32 field2_off;
14017 u32 index1_off;
14018 u32 index1_width;
14019 u32 index2_off;
14020 u32 index2_width;
14021 u32 mask1;
14022 u32 value1;
14023 u32 mask2;
14024 u32 value2;
14025};
14026
372cc85a
DL		 14027/*
14028 * Return an initialized RMT map table for users to fill in. OK if it
14029 * returns NULL, indicating no table.
14030 */
14031static struct rsm_map_table *alloc_rsm_map_table(struct hfi1_devdata *dd)
14032{
14033 struct rsm_map_table *rmt;
14034 u8 rxcontext = is_ax(dd) ? 0 : 0xff; /* 0 is default if a0 ver. */
14035
14036 rmt = kmalloc(sizeof(*rmt), GFP_KERNEL);
14037 if (rmt) {
14038 memset(rmt->map, rxcontext, sizeof(rmt->map));
14039 rmt->used = 0;
14040 }
14041
14042 return rmt;
14043}
14044
14045/*
14046 * Write the final RMT map table to the chip and free the table. OK if
14047 * table is NULL.
14048 */
14049static void complete_rsm_map_table(struct hfi1_devdata *dd,
14050 struct rsm_map_table *rmt)
14051{
14052 int i;
14053
14054 if (rmt) {
14055 /* write table to chip */
14056 for (i = 0; i < NUM_MAP_REGS; i++)
14057 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), rmt->map[i]);
14058
14059 /* enable RSM */
14060 add_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK);
14061 }
14062}
14063
b12349ae
DL		 14064/*
14065 * Add a receive side mapping rule.
14066 */
14067static void add_rsm_rule(struct hfi1_devdata *dd, u8 rule_index,
14068 struct rsm_rule_data *rrd)
14069{
14070 write_csr(dd, RCV_RSM_CFG + (8 * rule_index),
14071 (u64)rrd->offset << RCV_RSM_CFG_OFFSET_SHIFT |
14072 1ull << rule_index | /* enable bit */
14073 (u64)rrd->pkt_type << RCV_RSM_CFG_PACKET_TYPE_SHIFT);
14074 write_csr(dd, RCV_RSM_SELECT + (8 * rule_index),
14075 (u64)rrd->field1_off << RCV_RSM_SELECT_FIELD1_OFFSET_SHIFT |
14076 (u64)rrd->field2_off << RCV_RSM_SELECT_FIELD2_OFFSET_SHIFT |
14077 (u64)rrd->index1_off << RCV_RSM_SELECT_INDEX1_OFFSET_SHIFT |
14078 (u64)rrd->index1_width << RCV_RSM_SELECT_INDEX1_WIDTH_SHIFT |
14079 (u64)rrd->index2_off << RCV_RSM_SELECT_INDEX2_OFFSET_SHIFT |
14080 (u64)rrd->index2_width << RCV_RSM_SELECT_INDEX2_WIDTH_SHIFT);
14081 write_csr(dd, RCV_RSM_MATCH + (8 * rule_index),
14082 (u64)rrd->mask1 << RCV_RSM_MATCH_MASK1_SHIFT |
14083 (u64)rrd->value1 << RCV_RSM_MATCH_VALUE1_SHIFT |
14084 (u64)rrd->mask2 << RCV_RSM_MATCH_MASK2_SHIFT |
14085 (u64)rrd->value2 << RCV_RSM_MATCH_VALUE2_SHIFT);
14086}
14087
2280740f
VN		 14088/*
14089 * Clear a receive side mapping rule.
14090 */
14091static void clear_rsm_rule(struct hfi1_devdata *dd, u8 rule_index)
14092{
14093 write_csr(dd, RCV_RSM_CFG + (8 * rule_index), 0);
14094 write_csr(dd, RCV_RSM_SELECT + (8 * rule_index), 0);
14095 write_csr(dd, RCV_RSM_MATCH + (8 * rule_index), 0);
14096}
14097
4a818bed
DL		 14098/* return the number of RSM map table entries that will be used for QOS */
14099static int qos_rmt_entries(struct hfi1_devdata *dd, unsigned int *mp,
14100 unsigned int *np)
14101{
14102 int i;
14103 unsigned int m, n;
14104 u8 max_by_vl = 0;
14105
14106 /* is QOS active at all? */
14107 if (dd->n_krcv_queues <= MIN_KERNEL_KCTXTS ||
14108 num_vls == 1 ||
14109 krcvqsset <= 1)
14110 goto no_qos;
14111
14112 /* determine bits for qpn */
14113 for (i = 0; i < min_t(unsigned int, num_vls, krcvqsset); i++)
14114 if (krcvqs[i] > max_by_vl)
14115 max_by_vl = krcvqs[i];
14116 if (max_by_vl > 32)
14117 goto no_qos;
14118 m = ilog2(__roundup_pow_of_two(max_by_vl));
14119
14120 /* determine bits for vl */
14121 n = ilog2(__roundup_pow_of_two(num_vls));
14122
14123 /* reject if too much is used */
14124 if ((m + n) > 7)
14125 goto no_qos;
14126
14127 if (mp)
14128 *mp = m;
14129 if (np)
14130 *np = n;
14131
14132 return 1 << (m + n);
14133
14134no_qos:
14135 if (mp)
14136 *mp = 0;
14137 if (np)
14138 *np = 0;
14139 return 0;
14140}
14141
77241056
MM		 14142/**
14143 * init_qos - init RX qos
14144 * @dd - device data
372cc85a 14145 * @rmt - RSM map table
77241056 14146 *
33a9eb52
DL		 14147 * This routine initializes Rule 0 and the RSM map table to implement
14148 * quality of service (qos).
77241056 14149 *
33a9eb52
DL		 14150 * If all of the limit tests succeed, qos is applied based on the array
14151 * interpretation of krcvqs where entry 0 is VL0.
77241056 14152 *
33a9eb52
DL		 14153 * The number of vl bits (n) and the number of qpn bits (m) are computed to
14154 * feed both the RSM map table and the single rule.
77241056 14155 */
372cc85a 14156static void init_qos(struct hfi1_devdata *dd, struct rsm_map_table *rmt)
77241056 14157{
b12349ae 14158 struct rsm_rule_data rrd;
77241056 14159 unsigned qpns_per_vl, ctxt, i, qpn, n = 1, m;
372cc85a 14160 unsigned int rmt_entries;
77241056 14161 u64 reg;
77241056 14162
4a818bed 14163 if (!rmt)
77241056 14164 goto bail;
4a818bed
DL		 14165 rmt_entries = qos_rmt_entries(dd, &m, &n);
14166 if (rmt_entries == 0)
77241056 14167 goto bail;
4a818bed
DL		 14168 qpns_per_vl = 1 << m;
14169
372cc85a
DL		 14170 /* enough room in the map table? */
14171 rmt_entries = 1 << (m + n);
14172 if (rmt->used + rmt_entries >= NUM_MAP_ENTRIES)
859bcad9 14173 goto bail;
4a818bed 14174
372cc85a 14175 /* add qos entries to the the RSM map table */
33a9eb52 14176 for (i = 0, ctxt = FIRST_KERNEL_KCTXT; i < num_vls; i++) {
77241056
MM		 14177 unsigned tctxt;
14178
14179 for (qpn = 0, tctxt = ctxt;
14180 krcvqs[i] && qpn < qpns_per_vl; qpn++) {
14181 unsigned idx, regoff, regidx;
14182
372cc85a
DL		 14183 /* generate the index the hardware will produce */
14184 idx = rmt->used + ((qpn << n) ^ i);
77241056
MM		 14185 regoff = (idx % 8) * 8;
14186 regidx = idx / 8;
372cc85a
DL		 14187 /* replace default with context number */
14188 reg = rmt->map[regidx];
77241056
MM		 14189 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK
14190 << regoff);
14191 reg |= (u64)(tctxt++) << regoff;
372cc85a 14192 rmt->map[regidx] = reg;
77241056
MM		 14193 if (tctxt == ctxt + krcvqs[i])
14194 tctxt = ctxt;
14195 }
14196 ctxt += krcvqs[i];
14197 }
b12349ae
DL		 14198
14199 rrd.offset = rmt->used;
14200 rrd.pkt_type = 2;
14201 rrd.field1_off = LRH_BTH_MATCH_OFFSET;
14202 rrd.field2_off = LRH_SC_MATCH_OFFSET;
14203 rrd.index1_off = LRH_SC_SELECT_OFFSET;
14204 rrd.index1_width = n;
14205 rrd.index2_off = QPN_SELECT_OFFSET;
14206 rrd.index2_width = m + n;
14207 rrd.mask1 = LRH_BTH_MASK;
14208 rrd.value1 = LRH_BTH_VALUE;
14209 rrd.mask2 = LRH_SC_MASK;
14210 rrd.value2 = LRH_SC_VALUE;
14211
14212 /* add rule 0 */
2280740f 14213 add_rsm_rule(dd, RSM_INS_VERBS, &rrd);
b12349ae 14214
372cc85a
DL		 14215 /* mark RSM map entries as used */
14216 rmt->used += rmt_entries;
33a9eb52
DL		 14217 /* map everything else to the mcast/err/vl15 context */
14218 init_qpmap_table(dd, HFI1_CTRL_CTXT, HFI1_CTRL_CTXT);
77241056
MM		 14219 dd->qos_shift = n + 1;
14220 return;
14221bail:
14222 dd->qos_shift = 1;
82c2611d 14223 init_qpmap_table(dd, FIRST_KERNEL_KCTXT, dd->n_krcv_queues - 1);
77241056
MM		 14224}
14225
8f000f7f
DL		 14226static void init_user_fecn_handling(struct hfi1_devdata *dd,
14227 struct rsm_map_table *rmt)
14228{
14229 struct rsm_rule_data rrd;
14230 u64 reg;
14231 int i, idx, regoff, regidx;
14232 u8 offset;
14233
14234 /* there needs to be enough room in the map table */
14235 if (rmt->used + dd->num_user_contexts >= NUM_MAP_ENTRIES) {
14236 dd_dev_err(dd, "User FECN handling disabled - too many user contexts allocated\n");
14237 return;
14238 }
14239
14240 /*
14241 * RSM will extract the destination context as an index into the
14242 * map table. The destination contexts are a sequential block
2280740f 14243 * in the range first_dyn_alloc_ctxt...num_rcv_contexts-1 (inclusive).
8f000f7f
DL		 14244 * Map entries are accessed as offset + extracted value. Adjust
14245 * the added offset so this sequence can be placed anywhere in
14246 * the table - as long as the entries themselves do not wrap.
14247 * There are only enough bits in offset for the table size, so
14248 * start with that to allow for a "negative" offset.
14249 */
14250 offset = (u8)(NUM_MAP_ENTRIES + (int)rmt->used -
2280740f 14251 (int)dd->first_dyn_alloc_ctxt);
8f000f7f 14252
2280740f 14253 for (i = dd->first_dyn_alloc_ctxt, idx = rmt->used;
8f000f7f
DL		 14254 i < dd->num_rcv_contexts; i++, idx++) {
14255 /* replace with identity mapping */
14256 regoff = (idx % 8) * 8;
14257 regidx = idx / 8;
14258 reg = rmt->map[regidx];
14259 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK << regoff);
14260 reg |= (u64)i << regoff;
14261 rmt->map[regidx] = reg;
14262 }
14263
14264 /*
14265 * For RSM intercept of Expected FECN packets:
14266 * o packet type 0 - expected
14267 * o match on F (bit 95), using select/match 1, and
14268 * o match on SH (bit 133), using select/match 2.
14269 *
14270 * Use index 1 to extract the 8-bit receive context from DestQP
14271 * (start at bit 64). Use that as the RSM map table index.
14272 */
14273 rrd.offset = offset;
14274 rrd.pkt_type = 0;
14275 rrd.field1_off = 95;
14276 rrd.field2_off = 133;
14277 rrd.index1_off = 64;
14278 rrd.index1_width = 8;
14279 rrd.index2_off = 0;
14280 rrd.index2_width = 0;
14281 rrd.mask1 = 1;
14282 rrd.value1 = 1;
14283 rrd.mask2 = 1;
14284 rrd.value2 = 1;
14285
14286 /* add rule 1 */
2280740f 14287 add_rsm_rule(dd, RSM_INS_FECN, &rrd);
8f000f7f
DL		 14288
14289 rmt->used += dd->num_user_contexts;
14290}
14291
2280740f
VN		 14292/* Initialize RSM for VNIC */
14293void hfi1_init_vnic_rsm(struct hfi1_devdata *dd)
14294{
14295 u8 i, j;
14296 u8 ctx_id = 0;
14297 u64 reg;
14298 u32 regoff;
14299 struct rsm_rule_data rrd;
14300
14301 if (hfi1_vnic_is_rsm_full(dd, NUM_VNIC_MAP_ENTRIES)) {
14302 dd_dev_err(dd, "Vnic RSM disabled, rmt entries used = %d\n",
14303 dd->vnic.rmt_start);
14304 return;
14305 }
14306
14307 dev_dbg(&(dd)->pcidev->dev, "Vnic rsm start = %d, end %d\n",
14308 dd->vnic.rmt_start,
14309 dd->vnic.rmt_start + NUM_VNIC_MAP_ENTRIES);
14310
14311 /* Update RSM mapping table, 32 regs, 256 entries - 1 ctx per byte */
14312 regoff = RCV_RSM_MAP_TABLE + (dd->vnic.rmt_start / 8) * 8;
14313 reg = read_csr(dd, regoff);
14314 for (i = 0; i < NUM_VNIC_MAP_ENTRIES; i++) {
14315 /* Update map register with vnic context */
14316 j = (dd->vnic.rmt_start + i) % 8;
14317 reg &= ~(0xffllu << (j * 8));
14318 reg |= (u64)dd->vnic.ctxt[ctx_id++]->ctxt << (j * 8);
14319 /* Wrap up vnic ctx index */
14320 ctx_id %= dd->vnic.num_ctxt;
14321 /* Write back map register */
14322 if (j == 7 || ((i + 1) == NUM_VNIC_MAP_ENTRIES)) {
14323 dev_dbg(&(dd)->pcidev->dev,
14324 "Vnic rsm map reg[%d] =0x%llx\n",
14325 regoff - RCV_RSM_MAP_TABLE, reg);
14326
14327 write_csr(dd, regoff, reg);
14328 regoff += 8;
14329 if (i < (NUM_VNIC_MAP_ENTRIES - 1))
14330 reg = read_csr(dd, regoff);
14331 }
14332 }
14333
14334 /* Add rule for vnic */
14335 rrd.offset = dd->vnic.rmt_start;
14336 rrd.pkt_type = 4;
14337 /* Match 16B packets */
14338 rrd.field1_off = L2_TYPE_MATCH_OFFSET;
14339 rrd.mask1 = L2_TYPE_MASK;
14340 rrd.value1 = L2_16B_VALUE;
14341 /* Match ETH L4 packets */
14342 rrd.field2_off = L4_TYPE_MATCH_OFFSET;
14343 rrd.mask2 = L4_16B_TYPE_MASK;
14344 rrd.value2 = L4_16B_ETH_VALUE;
14345 /* Calc context from veswid and entropy */
14346 rrd.index1_off = L4_16B_HDR_VESWID_OFFSET;
14347 rrd.index1_width = ilog2(NUM_VNIC_MAP_ENTRIES);
14348 rrd.index2_off = L2_16B_ENTROPY_OFFSET;
14349 rrd.index2_width = ilog2(NUM_VNIC_MAP_ENTRIES);
14350 add_rsm_rule(dd, RSM_INS_VNIC, &rrd);
14351
14352 /* Enable RSM if not already enabled */
14353 add_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK);
14354}
14355
14356void hfi1_deinit_vnic_rsm(struct hfi1_devdata *dd)
14357{
14358 clear_rsm_rule(dd, RSM_INS_VNIC);
14359
14360 /* Disable RSM if used only by vnic */
14361 if (dd->vnic.rmt_start == 0)
14362 clear_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK);
14363}
14364
77241056
MM		 14365static void init_rxe(struct hfi1_devdata *dd)
14366{
372cc85a
DL		 14367 struct rsm_map_table *rmt;
14368
77241056
MM		 14369 /* enable all receive errors */
14370 write_csr(dd, RCV_ERR_MASK, ~0ull);
372cc85a
DL		 14371
14372 rmt = alloc_rsm_map_table(dd);
14373 /* set up QOS, including the QPN map table */
14374 init_qos(dd, rmt);
8f000f7f 14375 init_user_fecn_handling(dd, rmt);
372cc85a 14376 complete_rsm_map_table(dd, rmt);
2280740f
VN		 14377 /* record number of used rsm map entries for vnic */
14378 dd->vnic.rmt_start = rmt->used;
372cc85a
DL		 14379 kfree(rmt);
14380
77241056
MM		 14381 /*
14382 * make sure RcvCtrl.RcvWcb <= PCIe Device Control
14383 * Register Max_Payload_Size (PCI_EXP_DEVCTL in Linux PCIe config
14384 * space, PciCfgCap2.MaxPayloadSize in HFI). There is only one
14385 * invalid configuration: RcvCtrl.RcvWcb set to its max of 256 and
14386 * Max_PayLoad_Size set to its minimum of 128.
14387 *
14388 * Presently, RcvCtrl.RcvWcb is not modified from its default of 0
14389 * (64 bytes). Max_Payload_Size is possibly modified upward in
14390 * tune_pcie_caps() which is called after this routine.
14391 */
14392}
14393
14394static void init_other(struct hfi1_devdata *dd)
14395{
14396 /* enable all CCE errors */
14397 write_csr(dd, CCE_ERR_MASK, ~0ull);
14398 /* enable *some* Misc errors */
14399 write_csr(dd, MISC_ERR_MASK, DRIVER_MISC_MASK);
14400 /* enable all DC errors, except LCB */
14401 write_csr(dd, DCC_ERR_FLG_EN, ~0ull);
14402 write_csr(dd, DC_DC8051_ERR_EN, ~0ull);
14403}
14404
14405/*
14406 * Fill out the given AU table using the given CU. A CU is defined in terms
14407 * AUs. The table is a an encoding: given the index, how many AUs does that
14408 * represent?
14409 *
14410 * NOTE: Assumes that the register layout is the same for the
14411 * local and remote tables.
14412 */
14413static void assign_cm_au_table(struct hfi1_devdata *dd, u32 cu,
14414 u32 csr0to3, u32 csr4to7)
14415{
14416 write_csr(dd, csr0to3,
17fb4f29
JJ		 14417 0ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE0_SHIFT |
14418 1ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE1_SHIFT |
14419 2ull * cu <<
14420 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE2_SHIFT |
14421 4ull * cu <<
14422 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE3_SHIFT);
77241056 14423 write_csr(dd, csr4to7,
17fb4f29
JJ		 14424 8ull * cu <<
14425 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE4_SHIFT |
14426 16ull * cu <<
14427 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE5_SHIFT |
14428 32ull * cu <<
14429 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE6_SHIFT |
14430 64ull * cu <<
14431 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE7_SHIFT);
77241056
MM		 14432}
14433
14434static void assign_local_cm_au_table(struct hfi1_devdata *dd, u8 vcu)
14435{
14436 assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_LOCAL_AU_TABLE0_TO3,
17fb4f29 14437 SEND_CM_LOCAL_AU_TABLE4_TO7);
77241056
MM		 14438}
14439
14440void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu)
14441{
14442 assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_REMOTE_AU_TABLE0_TO3,
17fb4f29 14443 SEND_CM_REMOTE_AU_TABLE4_TO7);
77241056
MM		 14444}
14445
14446static void init_txe(struct hfi1_devdata *dd)
14447{
14448 int i;
14449
14450 /* enable all PIO, SDMA, general, and Egress errors */
14451 write_csr(dd, SEND_PIO_ERR_MASK, ~0ull);
14452 write_csr(dd, SEND_DMA_ERR_MASK, ~0ull);
14453 write_csr(dd, SEND_ERR_MASK, ~0ull);
14454 write_csr(dd, SEND_EGRESS_ERR_MASK, ~0ull);
14455
14456 /* enable all per-context and per-SDMA engine errors */
14457 for (i = 0; i < dd->chip_send_contexts; i++)
14458 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, ~0ull);
14459 for (i = 0; i < dd->chip_sdma_engines; i++)
14460 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, ~0ull);
14461
14462 /* set the local CU to AU mapping */
14463 assign_local_cm_au_table(dd, dd->vcu);
14464
14465 /*
14466 * Set reasonable default for Credit Return Timer
14467 * Don't set on Simulator - causes it to choke.
14468 */
14469 if (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)
14470 write_csr(dd, SEND_CM_TIMER_CTRL, HFI1_CREDIT_RETURN_RATE);
14471}
14472
14473int hfi1_set_ctxt_jkey(struct hfi1_devdata *dd, unsigned ctxt, u16 jkey)
14474{
14475 struct hfi1_ctxtdata *rcd = dd->rcd[ctxt];
14476 unsigned sctxt;
14477 int ret = 0;
14478 u64 reg;
14479
14480 if (!rcd || !rcd->sc) {
14481 ret = -EINVAL;
14482 goto done;
14483 }
14484 sctxt = rcd->sc->hw_context;
14485 reg = SEND_CTXT_CHECK_JOB_KEY_MASK_SMASK | /* mask is always 1's */
14486 ((jkey & SEND_CTXT_CHECK_JOB_KEY_VALUE_MASK) <<
14487 SEND_CTXT_CHECK_JOB_KEY_VALUE_SHIFT);
14488 /* JOB_KEY_ALLOW_PERMISSIVE is not allowed by default */
14489 if (HFI1_CAP_KGET_MASK(rcd->flags, ALLOW_PERM_JKEY))
14490 reg |= SEND_CTXT_CHECK_JOB_KEY_ALLOW_PERMISSIVE_SMASK;
14491 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_JOB_KEY, reg);
14492 /*
14493 * Enable send-side J_KEY integrity check, unless this is A0 h/w
77241056 14494 */
995deafa 14495 if (!is_ax(dd)) {
77241056
MM		 14496 reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
14497 reg |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
14498 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
14499 }
14500
14501 /* Enable J_KEY check on receive context. */
14502 reg = RCV_KEY_CTRL_JOB_KEY_ENABLE_SMASK |
14503 ((jkey & RCV_KEY_CTRL_JOB_KEY_VALUE_MASK) <<
14504 RCV_KEY_CTRL_JOB_KEY_VALUE_SHIFT);
14505 write_kctxt_csr(dd, ctxt, RCV_KEY_CTRL, reg);
14506done:
14507 return ret;
14508}
14509
14510int hfi1_clear_ctxt_jkey(struct hfi1_devdata *dd, unsigned ctxt)
14511{
14512 struct hfi1_ctxtdata *rcd = dd->rcd[ctxt];
14513 unsigned sctxt;
14514 int ret = 0;
14515 u64 reg;
14516
14517 if (!rcd || !rcd->sc) {
14518 ret = -EINVAL;
14519 goto done;
14520 }
14521 sctxt = rcd->sc->hw_context;
14522 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_JOB_KEY, 0);
14523 /*
14524 * Disable send-side J_KEY integrity check, unless this is A0 h/w.
14525 * This check would not have been enabled for A0 h/w, see
14526 * set_ctxt_jkey().
14527 */
995deafa 14528 if (!is_ax(dd)) {
77241056
MM		 14529 reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
14530 reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
14531 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
14532 }
14533 /* Turn off the J_KEY on the receive side */
14534 write_kctxt_csr(dd, ctxt, RCV_KEY_CTRL, 0);
14535done:
14536 return ret;
14537}
14538
14539int hfi1_set_ctxt_pkey(struct hfi1_devdata *dd, unsigned ctxt, u16 pkey)
14540{
14541 struct hfi1_ctxtdata *rcd;
14542 unsigned sctxt;
14543 int ret = 0;
14544 u64 reg;
14545
e490974e 14546 if (ctxt < dd->num_rcv_contexts) {
77241056 14547 rcd = dd->rcd[ctxt];
e490974e 14548 } else {
77241056
MM		 14549 ret = -EINVAL;
14550 goto done;
14551 }
14552 if (!rcd || !rcd->sc) {
14553 ret = -EINVAL;
14554 goto done;
14555 }
14556 sctxt = rcd->sc->hw_context;
14557 reg = ((u64)pkey & SEND_CTXT_CHECK_PARTITION_KEY_VALUE_MASK) <<
14558 SEND_CTXT_CHECK_PARTITION_KEY_VALUE_SHIFT;
14559 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_PARTITION_KEY, reg);
14560 reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
14561 reg |= SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK;
e38d1e4f 14562 reg &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK;
77241056
MM		 14563 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
14564done:
14565 return ret;
14566}
14567
637a9a7f 14568int hfi1_clear_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *ctxt)
77241056 14569{
637a9a7f 14570 u8 hw_ctxt;
77241056
MM		 14571 u64 reg;
14572
637a9a7f
MR		 14573 if (!ctxt || !ctxt->sc)
14574 return -EINVAL;
14575
14576 if (ctxt->ctxt >= dd->num_rcv_contexts)
14577 return -EINVAL;
14578
14579 hw_ctxt = ctxt->sc->hw_context;
14580 reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE);
77241056 14581 reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK;
637a9a7f
MR		 14582 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg);
14583 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_PARTITION_KEY, 0);
14584
14585 return 0;
77241056
MM		 14586}
14587
14588/*
14589 * Start doing the clean up the the chip. Our clean up happens in multiple
14590 * stages and this is just the first.
14591 */
14592void hfi1_start_cleanup(struct hfi1_devdata *dd)
14593{
affa48de 14594 aspm_exit(dd);
77241056
MM		 14595 free_cntrs(dd);
14596 free_rcverr(dd);
14597 clean_up_interrupts(dd);
a2ee27a4 14598 finish_chip_resources(dd);
77241056
MM		 14599}
14600
14601#define HFI_BASE_GUID(dev) \
14602 ((dev)->base_guid & ~(1ULL << GUID_HFI_INDEX_SHIFT))
14603
14604/*
78eb129d
DL		 14605 * Information can be shared between the two HFIs on the same ASIC
14606 * in the same OS. This function finds the peer device and sets
14607 * up a shared structure.
77241056 14608 */
78eb129d 14609static int init_asic_data(struct hfi1_devdata *dd)
77241056
MM		 14610{
14611 unsigned long flags;
14612 struct hfi1_devdata *tmp, *peer = NULL;
98f179a5 14613 struct hfi1_asic_data *asic_data;
78eb129d 14614 int ret = 0;
77241056 14615
98f179a5
TS		 14616 /* pre-allocate the asic structure in case we are the first device */
14617 asic_data = kzalloc(sizeof(*dd->asic_data), GFP_KERNEL);
14618 if (!asic_data)
14619 return -ENOMEM;
14620
77241056
MM		 14621 spin_lock_irqsave(&hfi1_devs_lock, flags);
14622 /* Find our peer device */
14623 list_for_each_entry(tmp, &hfi1_dev_list, list) {
14624 if ((HFI_BASE_GUID(dd) == HFI_BASE_GUID(tmp)) &&
14625 dd->unit != tmp->unit) {
14626 peer = tmp;
14627 break;
14628 }
14629 }
14630
78eb129d 14631 if (peer) {
98f179a5 14632 /* use already allocated structure */
78eb129d 14633 dd->asic_data = peer->asic_data;
98f179a5 14634 kfree(asic_data);
78eb129d 14635 } else {
98f179a5 14636 dd->asic_data = asic_data;
78eb129d
DL		 14637 mutex_init(&dd->asic_data->asic_resource_mutex);
14638 }
14639 dd->asic_data->dds[dd->hfi1_id] = dd; /* self back-pointer */
77241056 14640 spin_unlock_irqrestore(&hfi1_devs_lock, flags);
dba715f0
DL		 14641
14642 /* first one through - set up i2c devices */
14643 if (!peer)
14644 ret = set_up_i2c(dd, dd->asic_data);
14645
78eb129d 14646 return ret;
77241056
MM		 14647}
14648
5d9157aa
DL		 14649/*
14650 * Set dd->boardname. Use a generic name if a name is not returned from
14651 * EFI variable space.
14652 *
14653 * Return 0 on success, -ENOMEM if space could not be allocated.
14654 */
14655static int obtain_boardname(struct hfi1_devdata *dd)
14656{
14657 /* generic board description */
14658 const char generic[] =
14659 "Intel Omni-Path Host Fabric Interface Adapter 100 Series";
14660 unsigned long size;
14661 int ret;
14662
14663 ret = read_hfi1_efi_var(dd, "description", &size,
14664 (void **)&dd->boardname);
14665 if (ret) {
845f876d 14666 dd_dev_info(dd, "Board description not found\n");
5d9157aa
DL		 14667 /* use generic description */
14668 dd->boardname = kstrdup(generic, GFP_KERNEL);
14669 if (!dd->boardname)
14670 return -ENOMEM;
14671 }
14672 return 0;
14673}
14674
24487dd3
KW		 14675/*
14676 * Check the interrupt registers to make sure that they are mapped correctly.
14677 * It is intended to help user identify any mismapping by VMM when the driver
14678 * is running in a VM. This function should only be called before interrupt
14679 * is set up properly.
14680 *
14681 * Return 0 on success, -EINVAL on failure.
14682 */
14683static int check_int_registers(struct hfi1_devdata *dd)
14684{
14685 u64 reg;
14686 u64 all_bits = ~(u64)0;
14687 u64 mask;
14688
14689 /* Clear CceIntMask[0] to avoid raising any interrupts */
14690 mask = read_csr(dd, CCE_INT_MASK);
14691 write_csr(dd, CCE_INT_MASK, 0ull);
14692 reg = read_csr(dd, CCE_INT_MASK);
14693 if (reg)
14694 goto err_exit;
14695
14696 /* Clear all interrupt status bits */
14697 write_csr(dd, CCE_INT_CLEAR, all_bits);
14698 reg = read_csr(dd, CCE_INT_STATUS);
14699 if (reg)
14700 goto err_exit;
14701
14702 /* Set all interrupt status bits */
14703 write_csr(dd, CCE_INT_FORCE, all_bits);
14704 reg = read_csr(dd, CCE_INT_STATUS);
14705 if (reg != all_bits)
14706 goto err_exit;
14707
14708 /* Restore the interrupt mask */
14709 write_csr(dd, CCE_INT_CLEAR, all_bits);
14710 write_csr(dd, CCE_INT_MASK, mask);
14711
14712 return 0;
14713err_exit:
14714 write_csr(dd, CCE_INT_MASK, mask);
14715 dd_dev_err(dd, "Interrupt registers not properly mapped by VMM\n");
14716 return -EINVAL;
14717}
14718
77241056 14719/**
7c03ed85 14720 * Allocate and initialize the device structure for the hfi.
77241056
MM		 14721 * @dev: the pci_dev for hfi1_ib device
14722 * @ent: pci_device_id struct for this dev
14723 *
14724 * Also allocates, initializes, and returns the devdata struct for this
14725 * device instance
14726 *
14727 * This is global, and is called directly at init to set up the
14728 * chip-specific function pointers for later use.
14729 */
14730struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev,
14731 const struct pci_device_id *ent)
14732{
14733 struct hfi1_devdata *dd;
14734 struct hfi1_pportdata *ppd;
14735 u64 reg;
14736 int i, ret;
14737 static const char * const inames[] = { /* implementation names */
14738 "RTL silicon",
14739 "RTL VCS simulation",
14740 "RTL FPGA emulation",
14741 "Functional simulator"
14742 };
24487dd3 14743 struct pci_dev *parent = pdev->bus->self;
77241056 14744
17fb4f29
JJ		 14745 dd = hfi1_alloc_devdata(pdev, NUM_IB_PORTS *
14746 sizeof(struct hfi1_pportdata));
77241056
MM		 14747 if (IS_ERR(dd))
14748 goto bail;
14749 ppd = dd->pport;
14750 for (i = 0; i < dd->num_pports; i++, ppd++) {
14751 int vl;
14752 /* init common fields */
14753 hfi1_init_pportdata(pdev, ppd, dd, 0, 1);
14754 /* DC supports 4 link widths */
14755 ppd->link_width_supported =
14756 OPA_LINK_WIDTH_1X | OPA_LINK_WIDTH_2X |
14757 OPA_LINK_WIDTH_3X | OPA_LINK_WIDTH_4X;
14758 ppd->link_width_downgrade_supported =
14759 ppd->link_width_supported;
14760 /* start out enabling only 4X */
14761 ppd->link_width_enabled = OPA_LINK_WIDTH_4X;
14762 ppd->link_width_downgrade_enabled =
14763 ppd->link_width_downgrade_supported;
14764 /* link width active is 0 when link is down */
14765 /* link width downgrade active is 0 when link is down */
14766
d0d236ea
JJ		 14767 if (num_vls < HFI1_MIN_VLS_SUPPORTED ||
14768 num_vls > HFI1_MAX_VLS_SUPPORTED) {
77241056
MM		 14769 hfi1_early_err(&pdev->dev,
14770 "Invalid num_vls %u, using %u VLs\n",
14771 num_vls, HFI1_MAX_VLS_SUPPORTED);
14772 num_vls = HFI1_MAX_VLS_SUPPORTED;
14773 }
14774 ppd->vls_supported = num_vls;
14775 ppd->vls_operational = ppd->vls_supported;
8a4d3444 14776 ppd->actual_vls_operational = ppd->vls_supported;
77241056
MM		 14777 /* Set the default MTU. */
14778 for (vl = 0; vl < num_vls; vl++)
14779 dd->vld[vl].mtu = hfi1_max_mtu;
14780 dd->vld[15].mtu = MAX_MAD_PACKET;
14781 /*
14782 * Set the initial values to reasonable default, will be set
14783 * for real when link is up.
14784 */
14785 ppd->lstate = IB_PORT_DOWN;
14786 ppd->overrun_threshold = 0x4;
14787 ppd->phy_error_threshold = 0xf;
14788 ppd->port_crc_mode_enabled = link_crc_mask;
14789 /* initialize supported LTP CRC mode */
14790 ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8;
14791 /* initialize enabled LTP CRC mode */
14792 ppd->port_ltp_crc_mode |= cap_to_port_ltp(link_crc_mask) << 4;
14793 /* start in offline */
14794 ppd->host_link_state = HLS_DN_OFFLINE;
14795 init_vl_arb_caches(ppd);
f45c8dc8 14796 ppd->last_pstate = 0xff; /* invalid value */
77241056
MM		 14797 }
14798
14799 dd->link_default = HLS_DN_POLL;
14800
14801 /*
14802 * Do remaining PCIe setup and save PCIe values in dd.
14803 * Any error printing is already done by the init code.
14804 * On return, we have the chip mapped.
14805 */
26ea2544 14806 ret = hfi1_pcie_ddinit(dd, pdev);
77241056
MM		 14807 if (ret < 0)
14808 goto bail_free;
14809
14810 /* verify that reads actually work, save revision for reset check */
14811 dd->revision = read_csr(dd, CCE_REVISION);
14812 if (dd->revision == ~(u64)0) {
14813 dd_dev_err(dd, "cannot read chip CSRs\n");
14814 ret = -EINVAL;
14815 goto bail_cleanup;
14816 }
14817 dd->majrev = (dd->revision >> CCE_REVISION_CHIP_REV_MAJOR_SHIFT)
14818 & CCE_REVISION_CHIP_REV_MAJOR_MASK;
14819 dd->minrev = (dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT)
14820 & CCE_REVISION_CHIP_REV_MINOR_MASK;
14821
24487dd3
KW		 14822 /*
14823 * Check interrupt registers mapping if the driver has no access to
14824 * the upstream component. In this case, it is likely that the driver
14825 * is running in a VM.
14826 */
14827 if (!parent) {
14828 ret = check_int_registers(dd);
14829 if (ret)
14830 goto bail_cleanup;
14831 }
14832
4d114fdd
JJ		 14833 /*
14834 * obtain the hardware ID - NOT related to unit, which is a
14835 * software enumeration
14836 */
77241056
MM		 14837 reg = read_csr(dd, CCE_REVISION2);
14838 dd->hfi1_id = (reg >> CCE_REVISION2_HFI_ID_SHIFT)
14839 & CCE_REVISION2_HFI_ID_MASK;
14840 /* the variable size will remove unwanted bits */
14841 dd->icode = reg >> CCE_REVISION2_IMPL_CODE_SHIFT;
14842 dd->irev = reg >> CCE_REVISION2_IMPL_REVISION_SHIFT;
14843 dd_dev_info(dd, "Implementation: %s, revision 0x%x\n",
17fb4f29
JJ		 14844 dd->icode < ARRAY_SIZE(inames) ?
14845 inames[dd->icode] : "unknown", (int)dd->irev);
77241056
MM		 14846
14847 /* speeds the hardware can support */
14848 dd->pport->link_speed_supported = OPA_LINK_SPEED_25G;
14849 /* speeds allowed to run at */
14850 dd->pport->link_speed_enabled = dd->pport->link_speed_supported;
14851 /* give a reasonable active value, will be set on link up */
14852 dd->pport->link_speed_active = OPA_LINK_SPEED_25G;
14853
14854 dd->chip_rcv_contexts = read_csr(dd, RCV_CONTEXTS);
14855 dd->chip_send_contexts = read_csr(dd, SEND_CONTEXTS);
14856 dd->chip_sdma_engines = read_csr(dd, SEND_DMA_ENGINES);
14857 dd->chip_pio_mem_size = read_csr(dd, SEND_PIO_MEM_SIZE);
14858 dd->chip_sdma_mem_size = read_csr(dd, SEND_DMA_MEM_SIZE);
14859 /* fix up link widths for emulation _p */
14860 ppd = dd->pport;
14861 if (dd->icode == ICODE_FPGA_EMULATION && is_emulator_p(dd)) {
14862 ppd->link_width_supported =
14863 ppd->link_width_enabled =
14864 ppd->link_width_downgrade_supported =
14865 ppd->link_width_downgrade_enabled =
14866 OPA_LINK_WIDTH_1X;
14867 }
14868 /* insure num_vls isn't larger than number of sdma engines */
14869 if (HFI1_CAP_IS_KSET(SDMA) && num_vls > dd->chip_sdma_engines) {
14870 dd_dev_err(dd, "num_vls %u too large, using %u VLs\n",
11a5909b
DL		 14871 num_vls, dd->chip_sdma_engines);
14872 num_vls = dd->chip_sdma_engines;
14873 ppd->vls_supported = dd->chip_sdma_engines;
8a4d3444 14874 ppd->vls_operational = ppd->vls_supported;
77241056
MM		 14875 }
14876
14877 /*
14878 * Convert the ns parameter to the 64 * cclocks used in the CSR.
14879 * Limit the max if larger than the field holds. If timeout is
14880 * non-zero, then the calculated field will be at least 1.
14881 *
14882 * Must be after icode is set up - the cclock rate depends
14883 * on knowing the hardware being used.
14884 */
14885 dd->rcv_intr_timeout_csr = ns_to_cclock(dd, rcv_intr_timeout) / 64;
14886 if (dd->rcv_intr_timeout_csr >
14887 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK)
14888 dd->rcv_intr_timeout_csr =
14889 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK;
14890 else if (dd->rcv_intr_timeout_csr == 0 && rcv_intr_timeout)
14891 dd->rcv_intr_timeout_csr = 1;
14892
7c03ed85
EH		 14893 /* needs to be done before we look for the peer device */
14894 read_guid(dd);
14895
78eb129d
DL		 14896 /* set up shared ASIC data with peer device */
14897 ret = init_asic_data(dd);
14898 if (ret)
14899 goto bail_cleanup;
7c03ed85 14900
77241056
MM		 14901 /* obtain chip sizes, reset chip CSRs */
14902 init_chip(dd);
14903
14904 /* read in the PCIe link speed information */
14905 ret = pcie_speeds(dd);
14906 if (ret)
14907 goto bail_cleanup;
14908
e83eba21
DL		 14909 /* call before get_platform_config(), after init_chip_resources() */
14910 ret = eprom_init(dd);
14911 if (ret)
14912 goto bail_free_rcverr;
14913
c3838b39
EH		 14914 /* Needs to be called before hfi1_firmware_init */
14915 get_platform_config(dd);
14916
77241056
MM		 14917 /* read in firmware */
14918 ret = hfi1_firmware_init(dd);
14919 if (ret)
14920 goto bail_cleanup;
14921
14922 /*
14923 * In general, the PCIe Gen3 transition must occur after the
14924 * chip has been idled (so it won't initiate any PCIe transactions
14925 * e.g. an interrupt) and before the driver changes any registers
14926 * (the transition will reset the registers).
14927 *
14928 * In particular, place this call after:
14929 * - init_chip() - the chip will not initiate any PCIe transactions
14930 * - pcie_speeds() - reads the current link speed
14931 * - hfi1_firmware_init() - the needed firmware is ready to be
14932 * downloaded
14933 */
14934 ret = do_pcie_gen3_transition(dd);
14935 if (ret)
14936 goto bail_cleanup;
14937
14938 /* start setting dd values and adjusting CSRs */
14939 init_early_variables(dd);
14940
14941 parse_platform_config(dd);
14942
5d9157aa
DL		 14943 ret = obtain_boardname(dd);
14944 if (ret)
77241056 14945 goto bail_cleanup;
77241056
MM		 14946
14947 snprintf(dd->boardversion, BOARD_VERS_MAX,
5d9157aa 14948 "ChipABI %u.%u, ChipRev %u.%u, SW Compat %llu\n",
77241056 14949 HFI1_CHIP_VERS_MAJ, HFI1_CHIP_VERS_MIN,
77241056
MM		 14950 (u32)dd->majrev,
14951 (u32)dd->minrev,
14952 (dd->revision >> CCE_REVISION_SW_SHIFT)
14953 & CCE_REVISION_SW_MASK);
14954
14955 ret = set_up_context_variables(dd);
14956 if (ret)
14957 goto bail_cleanup;
14958
14959 /* set initial RXE CSRs */
14960 init_rxe(dd);
14961 /* set initial TXE CSRs */
14962 init_txe(dd);
14963 /* set initial non-RXE, non-TXE CSRs */
14964 init_other(dd);
14965 /* set up KDETH QP prefix in both RX and TX CSRs */
14966 init_kdeth_qp(dd);
14967
4197344b
DD		 14968 ret = hfi1_dev_affinity_init(dd);
14969 if (ret)
14970 goto bail_cleanup;
957558c9 14971
77241056
MM		 14972 /* send contexts must be set up before receive contexts */
14973 ret = init_send_contexts(dd);
14974 if (ret)
14975 goto bail_cleanup;
14976
14977 ret = hfi1_create_ctxts(dd);
14978 if (ret)
14979 goto bail_cleanup;
14980
14981 dd->rcvhdrsize = DEFAULT_RCVHDRSIZE;
14982 /*
14983 * rcd[0] is guaranteed to be valid by this point. Also, all
14984 * context are using the same value, as per the module parameter.
14985 */
14986 dd->rhf_offset = dd->rcd[0]->rcvhdrqentsize - sizeof(u64) / sizeof(u32);
14987
14988 ret = init_pervl_scs(dd);
14989 if (ret)
14990 goto bail_cleanup;
14991
14992 /* sdma init */
14993 for (i = 0; i < dd->num_pports; ++i) {
14994 ret = sdma_init(dd, i);
14995 if (ret)
14996 goto bail_cleanup;
14997 }
14998
14999 /* use contexts created by hfi1_create_ctxts */
15000 ret = set_up_interrupts(dd);
15001 if (ret)
15002 goto bail_cleanup;
15003
15004 /* set up LCB access - must be after set_up_interrupts() */
15005 init_lcb_access(dd);
15006
fc0b76c0
IW		 15007 /*
15008 * Serial number is created from the base guid:
15009 * [27:24] = base guid [38:35]
15010 * [23: 0] = base guid [23: 0]
15011 */
77241056 15012 snprintf(dd->serial, SERIAL_MAX, "0x%08llx\n",
fc0b76c0
IW		 15013 (dd->base_guid & 0xFFFFFF) |
15014 ((dd->base_guid >> 11) & 0xF000000));
77241056
MM		 15015
15016 dd->oui1 = dd->base_guid >> 56 & 0xFF;
15017 dd->oui2 = dd->base_guid >> 48 & 0xFF;
15018 dd->oui3 = dd->base_guid >> 40 & 0xFF;
15019
15020 ret = load_firmware(dd); /* asymmetric with dispose_firmware() */
15021 if (ret)
15022 goto bail_clear_intr;
77241056
MM		 15023
15024 thermal_init(dd);
15025
15026 ret = init_cntrs(dd);
15027 if (ret)
15028 goto bail_clear_intr;
15029
15030 ret = init_rcverr(dd);
15031 if (ret)
15032 goto bail_free_cntrs;
15033
acd7c8fe
TS		 15034 init_completion(&dd->user_comp);
15035
15036 /* The user refcount starts with one to inidicate an active device */
15037 atomic_set(&dd->user_refcount, 1);
15038
77241056
MM		 15039 goto bail;
15040
15041bail_free_rcverr:
15042 free_rcverr(dd);
15043bail_free_cntrs:
15044 free_cntrs(dd);
15045bail_clear_intr:
15046 clean_up_interrupts(dd);
15047bail_cleanup:
15048 hfi1_pcie_ddcleanup(dd);
15049bail_free:
15050 hfi1_free_devdata(dd);
15051 dd = ERR_PTR(ret);
15052bail:
15053 return dd;
15054}
15055
15056static u16 delay_cycles(struct hfi1_pportdata *ppd, u32 desired_egress_rate,
15057 u32 dw_len)
15058{
15059 u32 delta_cycles;
15060 u32 current_egress_rate = ppd->current_egress_rate;
15061 /* rates here are in units of 10^6 bits/sec */
15062
15063 if (desired_egress_rate == -1)
15064 return 0; /* shouldn't happen */
15065
15066 if (desired_egress_rate >= current_egress_rate)
15067 return 0; /* we can't help go faster, only slower */
15068
15069 delta_cycles = egress_cycles(dw_len * 4, desired_egress_rate) -
15070 egress_cycles(dw_len * 4, current_egress_rate);
15071
15072 return (u16)delta_cycles;
15073}
15074
77241056
MM		 15075/**
15076 * create_pbc - build a pbc for transmission
15077 * @flags: special case flags or-ed in built pbc
15078 * @srate: static rate
15079 * @vl: vl
15080 * @dwlen: dword length (header words + data words + pbc words)
15081 *
15082 * Create a PBC with the given flags, rate, VL, and length.
15083 *
15084 * NOTE: The PBC created will not insert any HCRC - all callers but one are
15085 * for verbs, which does not use this PSM feature. The lone other caller
15086 * is for the diagnostic interface which calls this if the user does not
15087 * supply their own PBC.
15088 */
15089u64 create_pbc(struct hfi1_pportdata *ppd, u64 flags, int srate_mbs, u32 vl,
15090 u32 dw_len)
15091{
15092 u64 pbc, delay = 0;
15093
15094 if (unlikely(srate_mbs))
15095 delay = delay_cycles(ppd, srate_mbs, dw_len);
15096
15097 pbc = flags
15098 | (delay << PBC_STATIC_RATE_CONTROL_COUNT_SHIFT)
15099 | ((u64)PBC_IHCRC_NONE << PBC_INSERT_HCRC_SHIFT)
15100 | (vl & PBC_VL_MASK) << PBC_VL_SHIFT
15101 | (dw_len & PBC_LENGTH_DWS_MASK)
15102 << PBC_LENGTH_DWS_SHIFT;
15103
15104 return pbc;
15105}
15106
15107#define SBUS_THERMAL 0x4f
15108#define SBUS_THERM_MONITOR_MODE 0x1
15109
15110#define THERM_FAILURE(dev, ret, reason) \
15111 dd_dev_err((dd), \
15112 "Thermal sensor initialization failed: %s (%d)\n", \
15113 (reason), (ret))
15114
15115/*
cde10afa 15116 * Initialize the thermal sensor.
77241056
MM		 15117 *
15118 * After initialization, enable polling of thermal sensor through
15119 * SBus interface. In order for this to work, the SBus Master
15120 * firmware has to be loaded due to the fact that the HW polling
15121 * logic uses SBus interrupts, which are not supported with
15122 * default firmware. Otherwise, no data will be returned through
15123 * the ASIC_STS_THERM CSR.
15124 */
15125static int thermal_init(struct hfi1_devdata *dd)
15126{
15127 int ret = 0;
15128
15129 if (dd->icode != ICODE_RTL_SILICON ||
a453698b 15130 check_chip_resource(dd, CR_THERM_INIT, NULL))
77241056
MM		 15131 return ret;
15132
576531fd
DL		 15133 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT);
15134 if (ret) {
15135 THERM_FAILURE(dd, ret, "Acquire SBus");
15136 return ret;
15137 }
15138
77241056 15139 dd_dev_info(dd, "Initializing thermal sensor\n");
4ef98989
JAQ		 15140 /* Disable polling of thermal readings */
15141 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0);
15142 msleep(100);
77241056
MM		 15143 /* Thermal Sensor Initialization */
15144 /* Step 1: Reset the Thermal SBus Receiver */
15145 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
15146 RESET_SBUS_RECEIVER, 0);
15147 if (ret) {
15148 THERM_FAILURE(dd, ret, "Bus Reset");
15149 goto done;
15150 }
15151 /* Step 2: Set Reset bit in Thermal block */
15152 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
15153 WRITE_SBUS_RECEIVER, 0x1);
15154 if (ret) {
15155 THERM_FAILURE(dd, ret, "Therm Block Reset");
15156 goto done;
15157 }
15158 /* Step 3: Write clock divider value (100MHz -> 2MHz) */
15159 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x1,
15160 WRITE_SBUS_RECEIVER, 0x32);
15161 if (ret) {
15162 THERM_FAILURE(dd, ret, "Write Clock Div");
15163 goto done;
15164 }
15165 /* Step 4: Select temperature mode */
15166 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x3,
15167 WRITE_SBUS_RECEIVER,
15168 SBUS_THERM_MONITOR_MODE);
15169 if (ret) {
15170 THERM_FAILURE(dd, ret, "Write Mode Sel");
15171 goto done;
15172 }
15173 /* Step 5: De-assert block reset and start conversion */
15174 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
15175 WRITE_SBUS_RECEIVER, 0x2);
15176 if (ret) {
15177 THERM_FAILURE(dd, ret, "Write Reset Deassert");
15178 goto done;
15179 }
15180 /* Step 5.1: Wait for first conversion (21.5ms per spec) */
15181 msleep(22);
15182
15183 /* Enable polling of thermal readings */
15184 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1);
a453698b
DL		 15185
15186 /* Set initialized flag */
15187 ret = acquire_chip_resource(dd, CR_THERM_INIT, 0);
15188 if (ret)
15189 THERM_FAILURE(dd, ret, "Unable to set thermal init flag");
15190
77241056 15191done:
576531fd 15192 release_chip_resource(dd, CR_SBUS);
77241056
MM		 15193 return ret;
15194}
15195
15196static void handle_temp_err(struct hfi1_devdata *dd)
15197{
15198 struct hfi1_pportdata *ppd = &dd->pport[0];
15199 /*
15200 * Thermal Critical Interrupt
15201 * Put the device into forced freeze mode, take link down to
15202 * offline, and put DC into reset.
15203 */
15204 dd_dev_emerg(dd,
15205 "Critical temperature reached! Forcing device into freeze mode!\n");
15206 dd->flags |= HFI1_FORCED_FREEZE;
8638b77f 15207 start_freeze_handling(ppd, FREEZE_SELF | FREEZE_ABORT);
77241056
MM		 15208 /*
15209 * Shut DC down as much and as quickly as possible.
15210 *
15211 * Step 1: Take the link down to OFFLINE. This will cause the
15212 * 8051 to put the Serdes in reset. However, we don't want to
15213 * go through the entire link state machine since we want to
15214 * shutdown ASAP. Furthermore, this is not a graceful shutdown
15215 * but rather an attempt to save the chip.
15216 * Code below is almost the same as quiet_serdes() but avoids
15217 * all the extra work and the sleeps.
15218 */
15219 ppd->driver_link_ready = 0;
15220 ppd->link_enabled = 0;
bf640096
HC		 15221 set_physical_link_state(dd, (OPA_LINKDOWN_REASON_SMA_DISABLED << 8) |
15222 PLS_OFFLINE);
77241056
MM		 15223 /*
15224 * Step 2: Shutdown LCB and 8051
15225 * After shutdown, do not restore DC_CFG_RESET value.
15226 */
15227 dc_shutdown(dd);
15228}
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