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77241056 MM |
1 | #ifndef _HFI1_KERNEL_H |
2 | #define _HFI1_KERNEL_H | |
3 | /* | |
d4829ea6 | 4 | * Copyright(c) 2015-2017 Intel Corporation. |
77241056 MM |
5 | * |
6 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
7 | * redistributing this file, you may do so under either license. | |
8 | * | |
9 | * GPL LICENSE SUMMARY | |
10 | * | |
77241056 MM |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of version 2 of the GNU General Public License as | |
13 | * published by the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but | |
16 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * General Public License for more details. | |
19 | * | |
20 | * BSD LICENSE | |
21 | * | |
77241056 MM |
22 | * Redistribution and use in source and binary forms, with or without |
23 | * modification, are permitted provided that the following conditions | |
24 | * are met: | |
25 | * | |
26 | * - Redistributions of source code must retain the above copyright | |
27 | * notice, this list of conditions and the following disclaimer. | |
28 | * - Redistributions in binary form must reproduce the above copyright | |
29 | * notice, this list of conditions and the following disclaimer in | |
30 | * the documentation and/or other materials provided with the | |
31 | * distribution. | |
32 | * - Neither the name of Intel Corporation nor the names of its | |
33 | * contributors may be used to endorse or promote products derived | |
34 | * from this software without specific prior written permission. | |
35 | * | |
36 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
37 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
38 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
39 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
40 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
41 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
42 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
43 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
44 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
45 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
46 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
47 | * | |
48 | */ | |
49 | ||
50 | #include <linux/interrupt.h> | |
51 | #include <linux/pci.h> | |
52 | #include <linux/dma-mapping.h> | |
53 | #include <linux/mutex.h> | |
54 | #include <linux/list.h> | |
55 | #include <linux/scatterlist.h> | |
56 | #include <linux/slab.h> | |
2280740f | 57 | #include <linux/idr.h> |
77241056 MM |
58 | #include <linux/io.h> |
59 | #include <linux/fs.h> | |
60 | #include <linux/completion.h> | |
61 | #include <linux/kref.h> | |
62 | #include <linux/sched.h> | |
63 | #include <linux/cdev.h> | |
64 | #include <linux/delay.h> | |
65 | #include <linux/kthread.h> | |
dba715f0 DL |
66 | #include <linux/i2c.h> |
67 | #include <linux/i2c-algo-bit.h> | |
261a4351 | 68 | #include <rdma/ib_hdrs.h> |
0cb2aa69 | 69 | #include <linux/rhashtable.h> |
2280740f | 70 | #include <linux/netdevice.h> |
ec3f2c12 | 71 | #include <rdma/rdma_vt.h> |
77241056 MM |
72 | |
73 | #include "chip_registers.h" | |
74 | #include "common.h" | |
75 | #include "verbs.h" | |
76 | #include "pio.h" | |
77 | #include "chip.h" | |
78 | #include "mad.h" | |
79 | #include "qsfp.h" | |
8ebd4cf1 | 80 | #include "platform.h" |
957558c9 | 81 | #include "affinity.h" |
77241056 MM |
82 | |
83 | /* bumped 1 from s/w major version of TrueScale */ | |
84 | #define HFI1_CHIP_VERS_MAJ 3U | |
85 | ||
86 | /* don't care about this except printing */ | |
87 | #define HFI1_CHIP_VERS_MIN 0U | |
88 | ||
89 | /* The Organization Unique Identifier (Mfg code), and its position in GUID */ | |
90 | #define HFI1_OUI 0x001175 | |
91 | #define HFI1_OUI_LSB 40 | |
92 | ||
93 | #define DROP_PACKET_OFF 0 | |
94 | #define DROP_PACKET_ON 1 | |
95 | ||
96 | extern unsigned long hfi1_cap_mask; | |
97 | #define HFI1_CAP_KGET_MASK(mask, cap) ((mask) & HFI1_CAP_##cap) | |
98 | #define HFI1_CAP_UGET_MASK(mask, cap) \ | |
99 | (((mask) >> HFI1_CAP_USER_SHIFT) & HFI1_CAP_##cap) | |
100 | #define HFI1_CAP_KGET(cap) (HFI1_CAP_KGET_MASK(hfi1_cap_mask, cap)) | |
101 | #define HFI1_CAP_UGET(cap) (HFI1_CAP_UGET_MASK(hfi1_cap_mask, cap)) | |
102 | #define HFI1_CAP_IS_KSET(cap) (!!HFI1_CAP_KGET(cap)) | |
103 | #define HFI1_CAP_IS_USET(cap) (!!HFI1_CAP_UGET(cap)) | |
104 | #define HFI1_MISC_GET() ((hfi1_cap_mask >> HFI1_CAP_MISC_SHIFT) & \ | |
105 | HFI1_CAP_MISC_MASK) | |
a9c05e35 BM |
106 | /* Offline Disabled Reason is 4-bits */ |
107 | #define HFI1_ODR_MASK(rsn) ((rsn) & OPA_PI_MASK_OFFLINE_REASON) | |
77241056 | 108 | |
82c2611d NV |
109 | /* |
110 | * Control context is always 0 and handles the error packets. | |
111 | * It also handles the VL15 and multicast packets. | |
112 | */ | |
113 | #define HFI1_CTRL_CTXT 0 | |
114 | ||
2c5b521a JR |
115 | /* |
116 | * Driver context will store software counters for each of the events | |
117 | * associated with these status registers | |
118 | */ | |
119 | #define NUM_CCE_ERR_STATUS_COUNTERS 41 | |
120 | #define NUM_RCV_ERR_STATUS_COUNTERS 64 | |
121 | #define NUM_MISC_ERR_STATUS_COUNTERS 13 | |
122 | #define NUM_SEND_PIO_ERR_STATUS_COUNTERS 36 | |
123 | #define NUM_SEND_DMA_ERR_STATUS_COUNTERS 4 | |
124 | #define NUM_SEND_EGRESS_ERR_STATUS_COUNTERS 64 | |
125 | #define NUM_SEND_ERR_STATUS_COUNTERS 3 | |
126 | #define NUM_SEND_CTXT_ERR_STATUS_COUNTERS 5 | |
127 | #define NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS 24 | |
128 | ||
77241056 MM |
129 | /* |
130 | * per driver stats, either not device nor port-specific, or | |
131 | * summed over all of the devices and ports. | |
132 | * They are described by name via ipathfs filesystem, so layout | |
133 | * and number of elements can change without breaking compatibility. | |
134 | * If members are added or deleted hfi1_statnames[] in debugfs.c must | |
135 | * change to match. | |
136 | */ | |
137 | struct hfi1_ib_stats { | |
138 | __u64 sps_ints; /* number of interrupts handled */ | |
139 | __u64 sps_errints; /* number of error interrupts */ | |
140 | __u64 sps_txerrs; /* tx-related packet errors */ | |
141 | __u64 sps_rcverrs; /* non-crc rcv packet errors */ | |
142 | __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */ | |
143 | __u64 sps_nopiobufs; /* no pio bufs avail from kernel */ | |
144 | __u64 sps_ctxts; /* number of contexts currently open */ | |
145 | __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */ | |
146 | __u64 sps_buffull; | |
147 | __u64 sps_hdrfull; | |
148 | }; | |
149 | ||
150 | extern struct hfi1_ib_stats hfi1_stats; | |
151 | extern const struct pci_error_handlers hfi1_pci_err_handler; | |
152 | ||
153 | /* | |
154 | * First-cut criterion for "device is active" is | |
155 | * two thousand dwords combined Tx, Rx traffic per | |
156 | * 5-second interval. SMA packets are 64 dwords, | |
157 | * and occur "a few per second", presumably each way. | |
158 | */ | |
159 | #define HFI1_TRAFFIC_ACTIVE_THRESHOLD (2000) | |
160 | ||
161 | /* | |
162 | * Below contains all data related to a single context (formerly called port). | |
163 | */ | |
164 | ||
165 | #ifdef CONFIG_DEBUG_FS | |
166 | struct hfi1_opcode_stats_perctx; | |
167 | #endif | |
168 | ||
77241056 MM |
169 | struct ctxt_eager_bufs { |
170 | ssize_t size; /* total size of eager buffers */ | |
171 | u32 count; /* size of buffers array */ | |
172 | u32 numbufs; /* number of buffers allocated */ | |
173 | u32 alloced; /* number of rcvarray entries used */ | |
174 | u32 rcvtid_size; /* size of each eager rcv tid */ | |
175 | u32 threshold; /* head update threshold */ | |
176 | struct eager_buffer { | |
177 | void *addr; | |
60368186 | 178 | dma_addr_t dma; |
77241056 MM |
179 | ssize_t len; |
180 | } *buffers; | |
181 | struct { | |
182 | void *addr; | |
60368186 | 183 | dma_addr_t dma; |
77241056 MM |
184 | } *rcvtids; |
185 | }; | |
186 | ||
a86cd357 MH |
187 | struct exp_tid_set { |
188 | struct list_head list; | |
189 | u32 count; | |
190 | }; | |
191 | ||
77241056 MM |
192 | struct hfi1_ctxtdata { |
193 | /* shadow the ctxt's RcvCtrl register */ | |
194 | u64 rcvctrl; | |
195 | /* rcvhdrq base, needs mmap before useful */ | |
196 | void *rcvhdrq; | |
197 | /* kernel virtual address where hdrqtail is updated */ | |
198 | volatile __le64 *rcvhdrtail_kvaddr; | |
77241056 MM |
199 | /* when waiting for rcv or pioavail */ |
200 | wait_queue_head_t wait; | |
201 | /* rcvhdrq size (for freeing) */ | |
202 | size_t rcvhdrq_size; | |
203 | /* number of rcvhdrq entries */ | |
204 | u16 rcvhdrq_cnt; | |
205 | /* size of each of the rcvhdrq entries */ | |
206 | u16 rcvhdrqentsize; | |
207 | /* mmap of hdrq, must fit in 44 bits */ | |
60368186 TK |
208 | dma_addr_t rcvhdrq_dma; |
209 | dma_addr_t rcvhdrqtailaddr_dma; | |
77241056 MM |
210 | struct ctxt_eager_bufs egrbufs; |
211 | /* this receive context's assigned PIO ACK send context */ | |
212 | struct send_context *sc; | |
213 | ||
214 | /* dynamic receive available interrupt timeout */ | |
215 | u32 rcvavail_timeout; | |
216 | /* | |
217 | * number of opens (including slave sub-contexts) on this instance | |
218 | * (ignoring forks, dup, etc. for now) | |
219 | */ | |
220 | int cnt; | |
9b60d2cb MR |
221 | /* Device context index */ |
222 | unsigned ctxt; | |
77241056 | 223 | /* |
9b60d2cb | 224 | * non-zero if ctxt can be shared, and defines the maximum number of |
8737ce95 | 225 | * sub-contexts for this device context. |
77241056 | 226 | */ |
77241056 MM |
227 | u16 subctxt_cnt; |
228 | /* non-zero if ctxt is being shared. */ | |
229 | u16 subctxt_id; | |
230 | u8 uuid[16]; | |
231 | /* job key */ | |
232 | u16 jkey; | |
233 | /* number of RcvArray groups for this context. */ | |
234 | u32 rcv_array_groups; | |
235 | /* index of first eager TID entry. */ | |
236 | u32 eager_base; | |
237 | /* number of expected TID entries */ | |
238 | u32 expected_count; | |
239 | /* index of first expected TID entry. */ | |
240 | u32 expected_base; | |
a86cd357 MH |
241 | |
242 | struct exp_tid_set tid_group_list; | |
243 | struct exp_tid_set tid_used_list; | |
244 | struct exp_tid_set tid_full_list; | |
245 | ||
77241056 | 246 | /* lock protecting all Expected TID data */ |
463e6ebc | 247 | struct mutex exp_lock; |
77241056 MM |
248 | /* number of pio bufs for this ctxt (all procs, if shared) */ |
249 | u32 piocnt; | |
250 | /* first pio buffer for this ctxt */ | |
251 | u32 pio_base; | |
252 | /* chip offset of PIO buffers for this ctxt */ | |
253 | u32 piobufs; | |
254 | /* per-context configuration flags */ | |
bdf7752e | 255 | unsigned long flags; |
77241056 MM |
256 | /* per-context event flags for fileops/intr communication */ |
257 | unsigned long event_flags; | |
258 | /* WAIT_RCV that timed out, no interrupt */ | |
259 | u32 rcvwait_to; | |
260 | /* WAIT_PIO that timed out, no interrupt */ | |
261 | u32 piowait_to; | |
262 | /* WAIT_RCV already happened, no wait */ | |
263 | u32 rcvnowait; | |
264 | /* WAIT_PIO already happened, no wait */ | |
265 | u32 pionowait; | |
266 | /* total number of polled urgent packets */ | |
267 | u32 urgent; | |
268 | /* saved total number of polled urgent packets for poll edge trigger */ | |
269 | u32 urgent_poll; | |
77241056 | 270 | /* same size as task_struct .comm[], command that opened context */ |
c3af8a28 | 271 | char comm[TASK_COMM_LEN]; |
77241056 MM |
272 | /* so file ops can get at unit */ |
273 | struct hfi1_devdata *dd; | |
274 | /* so functions that need physical port can get it easily */ | |
275 | struct hfi1_pportdata *ppd; | |
2280740f VN |
276 | /* associated msix interrupt */ |
277 | u32 msix_intr; | |
77241056 MM |
278 | /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */ |
279 | void *subctxt_uregbase; | |
280 | /* An array of pages for the eager receive buffers * N */ | |
281 | void *subctxt_rcvegrbuf; | |
282 | /* An array of pages for the eager header queue entries * N */ | |
283 | void *subctxt_rcvhdr_base; | |
8737ce95 MR |
284 | /* Bitmask of in use context(s) */ |
285 | DECLARE_BITMAP(in_use_ctxts, HFI1_MAX_SHARED_CTXTS); | |
77241056 MM |
286 | /* The version of the library which opened this ctxt */ |
287 | u32 userversion; | |
77241056 MM |
288 | /* Type of packets or conditions we want to poll for */ |
289 | u16 poll_type; | |
290 | /* receive packet sequence counter */ | |
291 | u8 seq_cnt; | |
292 | u8 redirect_seq_cnt; | |
293 | /* ctxt rcvhdrq head offset */ | |
294 | u32 head; | |
295 | u32 pkt_count; | |
296 | /* QPs waiting for context processing */ | |
297 | struct list_head qp_wait_list; | |
298 | /* interrupt handling */ | |
299 | u64 imask; /* clear interrupt mask */ | |
300 | int ireg; /* clear interrupt register */ | |
301 | unsigned numa_id; /* numa node of this context */ | |
302 | /* verbs stats per CTX */ | |
303 | struct hfi1_opcode_stats_perctx *opstats; | |
304 | /* | |
305 | * This is the kernel thread that will keep making | |
306 | * progress on the user sdma requests behind the scenes. | |
307 | * There is one per context (shared contexts use the master's). | |
308 | */ | |
309 | struct task_struct *progress; | |
310 | struct list_head sdma_queues; | |
6a14c5ea | 311 | /* protect sdma queues */ |
77241056 MM |
312 | spinlock_t sdma_qlock; |
313 | ||
affa48de AD |
314 | /* Is ASPM interrupt supported for this context */ |
315 | bool aspm_intr_supported; | |
316 | /* ASPM state (enabled/disabled) for this context */ | |
317 | bool aspm_enabled; | |
318 | /* Timer for re-enabling ASPM if interrupt activity quietens down */ | |
319 | struct timer_list aspm_timer; | |
320 | /* Lock to serialize between intr, timer intr and user threads */ | |
321 | spinlock_t aspm_lock; | |
322 | /* Is ASPM processing enabled for this context (in intr context) */ | |
323 | bool aspm_intr_enable; | |
324 | /* Last interrupt timestamp */ | |
325 | ktime_t aspm_ts_last_intr; | |
326 | /* Last timestamp at which we scheduled a timer for this context */ | |
327 | ktime_t aspm_ts_timer_sched; | |
328 | ||
77241056 MM |
329 | /* |
330 | * The interrupt handler for a particular receive context can vary | |
331 | * throughout it's lifetime. This is not a lock protected data member so | |
332 | * it must be updated atomically and the prev and new value must always | |
333 | * be valid. Worst case is we process an extra interrupt and up to 64 | |
334 | * packets with the wrong interrupt handler. | |
335 | */ | |
f4f30031 | 336 | int (*do_interrupt)(struct hfi1_ctxtdata *rcd, int threaded); |
d4829ea6 VN |
337 | |
338 | /* Indicates that this is vnic context */ | |
339 | bool is_vnic; | |
340 | ||
341 | /* vnic queue index this context is mapped to */ | |
342 | u8 vnic_q_idx; | |
77241056 MM |
343 | }; |
344 | ||
345 | /* | |
346 | * Represents a single packet at a high level. Put commonly computed things in | |
347 | * here so we do not have to keep doing them over and over. The rule of thumb is | |
348 | * if something is used one time to derive some value, store that something in | |
349 | * here. If it is used multiple times, then store the result of that derivation | |
350 | * in here. | |
351 | */ | |
352 | struct hfi1_packet { | |
353 | void *ebuf; | |
354 | void *hdr; | |
355 | struct hfi1_ctxtdata *rcd; | |
356 | __le32 *rhf_addr; | |
895420dd | 357 | struct rvt_qp *qp; |
261a4351 | 358 | struct ib_other_headers *ohdr; |
77241056 MM |
359 | u64 rhf; |
360 | u32 maxcnt; | |
361 | u32 rhqoff; | |
77241056 | 362 | u16 tlen; |
77241056 | 363 | s16 etail; |
76327627 SS |
364 | u8 hlen; |
365 | u8 numpkt; | |
366 | u8 rsize; | |
77241056 MM |
367 | u8 updegr; |
368 | u8 rcv_flags; | |
369 | u8 etype; | |
370 | }; | |
371 | ||
895420dd | 372 | struct rvt_sge_state; |
77241056 MM |
373 | |
374 | /* | |
375 | * Get/Set IB link-level config parameters for f_get/set_ib_cfg() | |
376 | * Mostly for MADs that set or query link parameters, also ipath | |
377 | * config interfaces | |
378 | */ | |
379 | #define HFI1_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */ | |
380 | #define HFI1_IB_CFG_LWID_DG_ENB 1 /* allowed Link-width downgrade */ | |
381 | #define HFI1_IB_CFG_LWID_ENB 2 /* allowed Link-width */ | |
382 | #define HFI1_IB_CFG_LWID 3 /* currently active Link-width */ | |
383 | #define HFI1_IB_CFG_SPD_ENB 4 /* allowed Link speeds */ | |
384 | #define HFI1_IB_CFG_SPD 5 /* current Link spd */ | |
385 | #define HFI1_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */ | |
386 | #define HFI1_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */ | |
387 | #define HFI1_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */ | |
388 | #define HFI1_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */ | |
389 | #define HFI1_IB_CFG_OP_VLS 10 /* operational VLs */ | |
390 | #define HFI1_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */ | |
391 | #define HFI1_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */ | |
392 | #define HFI1_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */ | |
393 | #define HFI1_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */ | |
394 | #define HFI1_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */ | |
395 | #define HFI1_IB_CFG_PKEYS 16 /* update partition keys */ | |
396 | #define HFI1_IB_CFG_MTU 17 /* update MTU in IBC */ | |
397 | #define HFI1_IB_CFG_VL_HIGH_LIMIT 19 | |
398 | #define HFI1_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */ | |
399 | #define HFI1_IB_CFG_PORT 21 /* switch port we are connected to */ | |
400 | ||
401 | /* | |
402 | * HFI or Host Link States | |
403 | * | |
404 | * These describe the states the driver thinks the logical and physical | |
405 | * states are in. Used as an argument to set_link_state(). Implemented | |
406 | * as bits for easy multi-state checking. The actual state can only be | |
407 | * one. | |
408 | */ | |
409 | #define __HLS_UP_INIT_BP 0 | |
410 | #define __HLS_UP_ARMED_BP 1 | |
411 | #define __HLS_UP_ACTIVE_BP 2 | |
412 | #define __HLS_DN_DOWNDEF_BP 3 /* link down default */ | |
413 | #define __HLS_DN_POLL_BP 4 | |
414 | #define __HLS_DN_DISABLE_BP 5 | |
415 | #define __HLS_DN_OFFLINE_BP 6 | |
416 | #define __HLS_VERIFY_CAP_BP 7 | |
417 | #define __HLS_GOING_UP_BP 8 | |
418 | #define __HLS_GOING_OFFLINE_BP 9 | |
419 | #define __HLS_LINK_COOLDOWN_BP 10 | |
420 | ||
349ac71f | 421 | #define HLS_UP_INIT BIT(__HLS_UP_INIT_BP) |
422 | #define HLS_UP_ARMED BIT(__HLS_UP_ARMED_BP) | |
423 | #define HLS_UP_ACTIVE BIT(__HLS_UP_ACTIVE_BP) | |
424 | #define HLS_DN_DOWNDEF BIT(__HLS_DN_DOWNDEF_BP) /* link down default */ | |
425 | #define HLS_DN_POLL BIT(__HLS_DN_POLL_BP) | |
426 | #define HLS_DN_DISABLE BIT(__HLS_DN_DISABLE_BP) | |
427 | #define HLS_DN_OFFLINE BIT(__HLS_DN_OFFLINE_BP) | |
428 | #define HLS_VERIFY_CAP BIT(__HLS_VERIFY_CAP_BP) | |
429 | #define HLS_GOING_UP BIT(__HLS_GOING_UP_BP) | |
430 | #define HLS_GOING_OFFLINE BIT(__HLS_GOING_OFFLINE_BP) | |
431 | #define HLS_LINK_COOLDOWN BIT(__HLS_LINK_COOLDOWN_BP) | |
77241056 MM |
432 | |
433 | #define HLS_UP (HLS_UP_INIT | HLS_UP_ARMED | HLS_UP_ACTIVE) | |
0c7f77af | 434 | #define HLS_DOWN ~(HLS_UP) |
77241056 MM |
435 | |
436 | /* use this MTU size if none other is given */ | |
ef699e84 | 437 | #define HFI1_DEFAULT_ACTIVE_MTU 10240 |
77241056 | 438 | /* use this MTU size as the default maximum */ |
ef699e84 | 439 | #define HFI1_DEFAULT_MAX_MTU 10240 |
77241056 MM |
440 | /* default partition key */ |
441 | #define DEFAULT_PKEY 0xffff | |
442 | ||
443 | /* | |
444 | * Possible fabric manager config parameters for fm_{get,set}_table() | |
445 | */ | |
446 | #define FM_TBL_VL_HIGH_ARB 1 /* Get/set VL high prio weights */ | |
447 | #define FM_TBL_VL_LOW_ARB 2 /* Get/set VL low prio weights */ | |
448 | #define FM_TBL_BUFFER_CONTROL 3 /* Get/set Buffer Control */ | |
449 | #define FM_TBL_SC2VLNT 4 /* Get/set SC->VLnt */ | |
450 | #define FM_TBL_VL_PREEMPT_ELEMS 5 /* Get (no set) VL preempt elems */ | |
451 | #define FM_TBL_VL_PREEMPT_MATRIX 6 /* Get (no set) VL preempt matrix */ | |
452 | ||
453 | /* | |
454 | * Possible "operations" for f_rcvctrl(ppd, op, ctxt) | |
455 | * these are bits so they can be combined, e.g. | |
456 | * HFI1_RCVCTRL_INTRAVAIL_ENB | HFI1_RCVCTRL_CTXT_ENB | |
457 | */ | |
458 | #define HFI1_RCVCTRL_TAILUPD_ENB 0x01 | |
459 | #define HFI1_RCVCTRL_TAILUPD_DIS 0x02 | |
460 | #define HFI1_RCVCTRL_CTXT_ENB 0x04 | |
461 | #define HFI1_RCVCTRL_CTXT_DIS 0x08 | |
462 | #define HFI1_RCVCTRL_INTRAVAIL_ENB 0x10 | |
463 | #define HFI1_RCVCTRL_INTRAVAIL_DIS 0x20 | |
464 | #define HFI1_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */ | |
465 | #define HFI1_RCVCTRL_PKEY_DIS 0x80 | |
466 | #define HFI1_RCVCTRL_TIDFLOW_ENB 0x0400 | |
467 | #define HFI1_RCVCTRL_TIDFLOW_DIS 0x0800 | |
468 | #define HFI1_RCVCTRL_ONE_PKT_EGR_ENB 0x1000 | |
469 | #define HFI1_RCVCTRL_ONE_PKT_EGR_DIS 0x2000 | |
470 | #define HFI1_RCVCTRL_NO_RHQ_DROP_ENB 0x4000 | |
471 | #define HFI1_RCVCTRL_NO_RHQ_DROP_DIS 0x8000 | |
472 | #define HFI1_RCVCTRL_NO_EGR_DROP_ENB 0x10000 | |
473 | #define HFI1_RCVCTRL_NO_EGR_DROP_DIS 0x20000 | |
474 | ||
475 | /* partition enforcement flags */ | |
476 | #define HFI1_PART_ENFORCE_IN 0x1 | |
477 | #define HFI1_PART_ENFORCE_OUT 0x2 | |
478 | ||
479 | /* how often we check for synthetic counter wrap around */ | |
22546b74 | 480 | #define SYNTH_CNT_TIME 3 |
77241056 MM |
481 | |
482 | /* Counter flags */ | |
483 | #define CNTR_NORMAL 0x0 /* Normal counters, just read register */ | |
484 | #define CNTR_SYNTH 0x1 /* Synthetic counters, saturate at all 1s */ | |
485 | #define CNTR_DISABLED 0x2 /* Disable this counter */ | |
486 | #define CNTR_32BIT 0x4 /* Simulate 64 bits for this counter */ | |
487 | #define CNTR_VL 0x8 /* Per VL counter */ | |
a699c6c2 | 488 | #define CNTR_SDMA 0x10 |
77241056 MM |
489 | #define CNTR_INVALID_VL -1 /* Specifies invalid VL */ |
490 | #define CNTR_MODE_W 0x0 | |
491 | #define CNTR_MODE_R 0x1 | |
492 | ||
493 | /* VLs Supported/Operational */ | |
494 | #define HFI1_MIN_VLS_SUPPORTED 1 | |
495 | #define HFI1_MAX_VLS_SUPPORTED 8 | |
496 | ||
a6cd5f08 JP |
497 | #define HFI1_GUIDS_PER_PORT 5 |
498 | #define HFI1_PORT_GUID_INDEX 0 | |
499 | ||
77241056 MM |
500 | static inline void incr_cntr64(u64 *cntr) |
501 | { | |
502 | if (*cntr < (u64)-1LL) | |
503 | (*cntr)++; | |
504 | } | |
505 | ||
506 | static inline void incr_cntr32(u32 *cntr) | |
507 | { | |
508 | if (*cntr < (u32)-1LL) | |
509 | (*cntr)++; | |
510 | } | |
511 | ||
512 | #define MAX_NAME_SIZE 64 | |
513 | struct hfi1_msix_entry { | |
957558c9 | 514 | enum irq_type type; |
77241056 MM |
515 | struct msix_entry msix; |
516 | void *arg; | |
517 | char name[MAX_NAME_SIZE]; | |
957558c9 | 518 | cpumask_t mask; |
2d01c37d | 519 | struct irq_affinity_notify notify; |
77241056 MM |
520 | }; |
521 | ||
522 | /* per-SL CCA information */ | |
523 | struct cca_timer { | |
524 | struct hrtimer hrtimer; | |
525 | struct hfi1_pportdata *ppd; /* read-only */ | |
526 | int sl; /* read-only */ | |
527 | u16 ccti; /* read/write - current value of CCTI */ | |
528 | }; | |
529 | ||
530 | struct link_down_reason { | |
531 | /* | |
532 | * SMA-facing value. Should be set from .latest when | |
533 | * HLS_UP_* -> HLS_DN_* transition actually occurs. | |
534 | */ | |
535 | u8 sma; | |
536 | u8 latest; | |
537 | }; | |
538 | ||
539 | enum { | |
540 | LO_PRIO_TABLE, | |
541 | HI_PRIO_TABLE, | |
542 | MAX_PRIO_TABLE | |
543 | }; | |
544 | ||
545 | struct vl_arb_cache { | |
6a14c5ea | 546 | /* protect vl arb cache */ |
77241056 MM |
547 | spinlock_t lock; |
548 | struct ib_vl_weight_elem table[VL_ARB_TABLE_SIZE]; | |
549 | }; | |
550 | ||
551 | /* | |
552 | * The structure below encapsulates data relevant to a physical IB Port. | |
553 | * Current chips support only one such port, but the separation | |
554 | * clarifies things a bit. Note that to conform to IB conventions, | |
555 | * port-numbers are one-based. The first or only port is port1. | |
556 | */ | |
557 | struct hfi1_pportdata { | |
558 | struct hfi1_ibport ibport_data; | |
559 | ||
560 | struct hfi1_devdata *dd; | |
561 | struct kobject pport_cc_kobj; | |
562 | struct kobject sc2vl_kobj; | |
563 | struct kobject sl2sc_kobj; | |
564 | struct kobject vl2mtu_kobj; | |
565 | ||
8ebd4cf1 | 566 | /* PHY support */ |
77241056 | 567 | struct qsfp_data qsfp_info; |
fe4d9243 EH |
568 | /* Values for SI tuning of SerDes */ |
569 | u32 port_type; | |
570 | u32 tx_preset_eq; | |
571 | u32 tx_preset_noeq; | |
572 | u32 rx_preset; | |
573 | u8 local_atten; | |
574 | u8 remote_atten; | |
575 | u8 default_atten; | |
576 | u8 max_power_class; | |
77241056 | 577 | |
a6cd5f08 JP |
578 | /* GUIDs for this interface, in host order, guids[0] is a port guid */ |
579 | u64 guids[HFI1_GUIDS_PER_PORT]; | |
77241056 | 580 | |
77241056 MM |
581 | /* GUID for peer interface, in host order */ |
582 | u64 neighbor_guid; | |
583 | ||
584 | /* up or down physical link state */ | |
585 | u32 linkup; | |
586 | ||
587 | /* | |
588 | * this address is mapped read-only into user processes so they can | |
589 | * get status cheaply, whenever they want. One qword of status per port | |
590 | */ | |
591 | u64 *statusp; | |
592 | ||
593 | /* SendDMA related entries */ | |
594 | ||
595 | struct workqueue_struct *hfi1_wq; | |
596 | ||
597 | /* move out of interrupt context */ | |
598 | struct work_struct link_vc_work; | |
599 | struct work_struct link_up_work; | |
600 | struct work_struct link_down_work; | |
601 | struct work_struct sma_message_work; | |
602 | struct work_struct freeze_work; | |
603 | struct work_struct link_downgrade_work; | |
604 | struct work_struct link_bounce_work; | |
673b975f | 605 | struct delayed_work start_link_work; |
77241056 MM |
606 | /* host link state variables */ |
607 | struct mutex hls_lock; | |
608 | u32 host_link_state; | |
609 | ||
77241056 MM |
610 | u32 lstate; /* logical link state */ |
611 | ||
612 | /* these are the "32 bit" regs */ | |
613 | ||
614 | u32 ibmtu; /* The MTU programmed for this unit */ | |
615 | /* | |
616 | * Current max size IB packet (in bytes) including IB headers, that | |
617 | * we can send. Changes when ibmtu changes. | |
618 | */ | |
619 | u32 ibmaxlen; | |
620 | u32 current_egress_rate; /* units [10^6 bits/sec] */ | |
621 | /* LID programmed for this instance */ | |
622 | u16 lid; | |
623 | /* list of pkeys programmed; 0 if not set */ | |
624 | u16 pkeys[MAX_PKEY_VALUES]; | |
625 | u16 link_width_supported; | |
626 | u16 link_width_downgrade_supported; | |
627 | u16 link_speed_supported; | |
628 | u16 link_width_enabled; | |
629 | u16 link_width_downgrade_enabled; | |
630 | u16 link_speed_enabled; | |
631 | u16 link_width_active; | |
632 | u16 link_width_downgrade_tx_active; | |
633 | u16 link_width_downgrade_rx_active; | |
634 | u16 link_speed_active; | |
635 | u8 vls_supported; | |
636 | u8 vls_operational; | |
8a4d3444 | 637 | u8 actual_vls_operational; |
77241056 MM |
638 | /* LID mask control */ |
639 | u8 lmc; | |
640 | /* Rx Polarity inversion (compensate for ~tx on partner) */ | |
641 | u8 rx_pol_inv; | |
642 | ||
643 | u8 hw_pidx; /* physical port index */ | |
644 | u8 port; /* IB port number and index into dd->pports - 1 */ | |
645 | /* type of neighbor node */ | |
646 | u8 neighbor_type; | |
647 | u8 neighbor_normal; | |
648 | u8 neighbor_fm_security; /* 1 if firmware checking is disabled */ | |
649 | u8 neighbor_port_number; | |
650 | u8 is_sm_config_started; | |
651 | u8 offline_disabled_reason; | |
652 | u8 is_active_optimize_enabled; | |
653 | u8 driver_link_ready; /* driver ready for active link */ | |
654 | u8 link_enabled; /* link enabled? */ | |
655 | u8 linkinit_reason; | |
656 | u8 local_tx_rate; /* rate given to 8051 firmware */ | |
f45c8dc8 | 657 | u8 last_pstate; /* info only */ |
673b975f | 658 | u8 qsfp_retry_count; |
77241056 MM |
659 | |
660 | /* placeholders for IB MAD packet settings */ | |
661 | u8 overrun_threshold; | |
662 | u8 phy_error_threshold; | |
663 | ||
91ab4ed3 EH |
664 | /* Used to override LED behavior for things like maintenance beaconing*/ |
665 | /* | |
666 | * Alternates per phase of blink | |
667 | * [0] holds LED off duration, [1] holds LED on duration | |
668 | */ | |
669 | unsigned long led_override_vals[2]; | |
670 | u8 led_override_phase; /* LSB picks from vals[] */ | |
77241056 MM |
671 | atomic_t led_override_timer_active; |
672 | /* Used to flash LEDs in override mode */ | |
673 | struct timer_list led_override_timer; | |
91ab4ed3 | 674 | |
77241056 MM |
675 | u32 sm_trap_qp; |
676 | u32 sa_qp; | |
677 | ||
678 | /* | |
679 | * cca_timer_lock protects access to the per-SL cca_timer | |
680 | * structures (specifically the ccti member). | |
681 | */ | |
682 | spinlock_t cca_timer_lock ____cacheline_aligned_in_smp; | |
683 | struct cca_timer cca_timer[OPA_MAX_SLS]; | |
684 | ||
685 | /* List of congestion control table entries */ | |
686 | struct ib_cc_table_entry_shadow ccti_entries[CC_TABLE_SHADOW_MAX]; | |
687 | ||
688 | /* congestion entries, each entry corresponding to a SL */ | |
689 | struct opa_congestion_setting_entry_shadow | |
690 | congestion_entries[OPA_MAX_SLS]; | |
691 | ||
692 | /* | |
693 | * cc_state_lock protects (write) access to the per-port | |
694 | * struct cc_state. | |
695 | */ | |
696 | spinlock_t cc_state_lock ____cacheline_aligned_in_smp; | |
697 | ||
698 | struct cc_state __rcu *cc_state; | |
699 | ||
700 | /* Total number of congestion control table entries */ | |
701 | u16 total_cct_entry; | |
702 | ||
703 | /* Bit map identifying service level */ | |
704 | u32 cc_sl_control_map; | |
705 | ||
706 | /* CA's max number of 64 entry units in the congestion control table */ | |
707 | u8 cc_max_table_entries; | |
708 | ||
4d114fdd JJ |
709 | /* |
710 | * begin congestion log related entries | |
711 | * cc_log_lock protects all congestion log related data | |
712 | */ | |
77241056 | 713 | spinlock_t cc_log_lock ____cacheline_aligned_in_smp; |
8638b77f | 714 | u8 threshold_cong_event_map[OPA_MAX_SLS / 8]; |
77241056 MM |
715 | u16 threshold_event_counter; |
716 | struct opa_hfi1_cong_log_event_internal cc_events[OPA_CONG_LOG_ELEMS]; | |
717 | int cc_log_idx; /* index for logging events */ | |
718 | int cc_mad_idx; /* index for reporting events */ | |
719 | /* end congestion log related entries */ | |
720 | ||
721 | struct vl_arb_cache vl_arb_cache[MAX_PRIO_TABLE]; | |
722 | ||
723 | /* port relative counter buffer */ | |
724 | u64 *cntrs; | |
725 | /* port relative synthetic counter buffer */ | |
726 | u64 *scntrs; | |
69a00b8e | 727 | /* port_xmit_discards are synthesized from different egress errors */ |
77241056 | 728 | u64 port_xmit_discards; |
69a00b8e | 729 | u64 port_xmit_discards_vl[C_VL_COUNT]; |
77241056 MM |
730 | u64 port_xmit_constraint_errors; |
731 | u64 port_rcv_constraint_errors; | |
732 | /* count of 'link_err' interrupts from DC */ | |
733 | u64 link_downed; | |
734 | /* number of times link retrained successfully */ | |
735 | u64 link_up; | |
6d014530 DL |
736 | /* number of times a link unknown frame was reported */ |
737 | u64 unknown_frame_count; | |
77241056 MM |
738 | /* port_ltp_crc_mode is returned in 'portinfo' MADs */ |
739 | u16 port_ltp_crc_mode; | |
740 | /* port_crc_mode_enabled is the crc we support */ | |
741 | u8 port_crc_mode_enabled; | |
742 | /* mgmt_allowed is also returned in 'portinfo' MADs */ | |
743 | u8 mgmt_allowed; | |
744 | u8 part_enforce; /* partition enforcement flags */ | |
745 | struct link_down_reason local_link_down_reason; | |
746 | struct link_down_reason neigh_link_down_reason; | |
747 | /* Value to be sent to link peer on LinkDown .*/ | |
748 | u8 remote_link_down_reason; | |
749 | /* Error events that will cause a port bounce. */ | |
750 | u32 port_error_action; | |
fb9036dd | 751 | struct work_struct linkstate_active_work; |
6c9e50f8 VM |
752 | /* Does this port need to prescan for FECNs */ |
753 | bool cc_prescan; | |
77241056 MM |
754 | }; |
755 | ||
756 | typedef int (*rhf_rcv_function_ptr)(struct hfi1_packet *packet); | |
757 | ||
758 | typedef void (*opcode_handler)(struct hfi1_packet *packet); | |
759 | ||
760 | /* return values for the RHF receive functions */ | |
761 | #define RHF_RCV_CONTINUE 0 /* keep going */ | |
762 | #define RHF_RCV_DONE 1 /* stop, this packet processed */ | |
763 | #define RHF_RCV_REPROCESS 2 /* stop. retain this packet */ | |
764 | ||
765 | struct rcv_array_data { | |
766 | u8 group_size; | |
767 | u16 ngroups; | |
768 | u16 nctxt_extra; | |
769 | }; | |
770 | ||
771 | struct per_vl_data { | |
772 | u16 mtu; | |
773 | struct send_context *sc; | |
774 | }; | |
775 | ||
776 | /* 16 to directly index */ | |
777 | #define PER_VL_SEND_CONTEXTS 16 | |
778 | ||
779 | struct err_info_rcvport { | |
780 | u8 status_and_code; | |
781 | u64 packet_flit1; | |
782 | u64 packet_flit2; | |
783 | }; | |
784 | ||
785 | struct err_info_constraint { | |
786 | u8 status; | |
787 | u16 pkey; | |
788 | u32 slid; | |
789 | }; | |
790 | ||
791 | struct hfi1_temp { | |
792 | unsigned int curr; /* current temperature */ | |
793 | unsigned int lo_lim; /* low temperature limit */ | |
794 | unsigned int hi_lim; /* high temperature limit */ | |
795 | unsigned int crit_lim; /* critical temperature limit */ | |
796 | u8 triggers; /* temperature triggers */ | |
797 | }; | |
798 | ||
dba715f0 DL |
799 | struct hfi1_i2c_bus { |
800 | struct hfi1_devdata *controlling_dd; /* current controlling device */ | |
801 | struct i2c_adapter adapter; /* bus details */ | |
802 | struct i2c_algo_bit_data algo; /* bus algorithm details */ | |
803 | int num; /* bus number, 0 or 1 */ | |
804 | }; | |
805 | ||
78eb129d DL |
806 | /* common data between shared ASIC HFIs */ |
807 | struct hfi1_asic_data { | |
808 | struct hfi1_devdata *dds[2]; /* back pointers */ | |
809 | struct mutex asic_resource_mutex; | |
dba715f0 DL |
810 | struct hfi1_i2c_bus *i2c_bus0; |
811 | struct hfi1_i2c_bus *i2c_bus1; | |
78eb129d DL |
812 | }; |
813 | ||
2280740f VN |
814 | /* sizes for both the QP and RSM map tables */ |
815 | #define NUM_MAP_ENTRIES 256 | |
816 | #define NUM_MAP_REGS 32 | |
817 | ||
d4829ea6 VN |
818 | /* |
819 | * Number of VNIC contexts used. Ensure it is less than or equal to | |
820 | * max queues supported by VNIC (HFI1_VNIC_MAX_QUEUE). | |
821 | */ | |
822 | #define HFI1_NUM_VNIC_CTXT 8 | |
823 | ||
2280740f VN |
824 | /* Number of VNIC RSM entries */ |
825 | #define NUM_VNIC_MAP_ENTRIES 8 | |
826 | ||
d4829ea6 VN |
827 | /* Virtual NIC information */ |
828 | struct hfi1_vnic_data { | |
2280740f | 829 | struct hfi1_ctxtdata *ctxt[HFI1_NUM_VNIC_CTXT]; |
64551ede | 830 | struct kmem_cache *txreq_cache; |
2280740f | 831 | u8 num_vports; |
d4829ea6 | 832 | struct idr vesw_idr; |
2280740f VN |
833 | u8 rmt_start; |
834 | u8 num_ctxt; | |
835 | u32 msix_idx; | |
d4829ea6 VN |
836 | }; |
837 | ||
838 | struct hfi1_vnic_vport_info; | |
839 | ||
77241056 MM |
840 | /* device data struct now contains only "general per-device" info. |
841 | * fields related to a physical IB port are in a hfi1_pportdata struct. | |
842 | */ | |
843 | struct sdma_engine; | |
844 | struct sdma_vl_map; | |
845 | ||
846 | #define BOARD_VERS_MAX 96 /* how long the version string can be */ | |
847 | #define SERIAL_MAX 16 /* length of the serial number */ | |
848 | ||
14553ca1 | 849 | typedef int (*send_routine)(struct rvt_qp *, struct hfi1_pkt_state *, u64); |
77241056 MM |
850 | struct hfi1_devdata { |
851 | struct hfi1_ibdev verbs_dev; /* must be first */ | |
852 | struct list_head list; | |
853 | /* pointers to related structs for this device */ | |
854 | /* pci access data structure */ | |
855 | struct pci_dev *pcidev; | |
856 | struct cdev user_cdev; | |
857 | struct cdev diag_cdev; | |
858 | struct cdev ui_cdev; | |
859 | struct device *user_device; | |
860 | struct device *diag_device; | |
861 | struct device *ui_device; | |
862 | ||
863 | /* mem-mapped pointer to base of chip regs */ | |
864 | u8 __iomem *kregbase; | |
865 | /* end of mem-mapped chip space excluding sendbuf and user regs */ | |
866 | u8 __iomem *kregend; | |
867 | /* physical address of chip for io_remap, etc. */ | |
868 | resource_size_t physaddr; | |
6e768f06 SS |
869 | /* Per VL data. Enough for all VLs but not all elements are set/used. */ |
870 | struct per_vl_data vld[PER_VL_SEND_CONTEXTS]; | |
77241056 MM |
871 | /* send context data */ |
872 | struct send_context_info *send_contexts; | |
873 | /* map hardware send contexts to software index */ | |
874 | u8 *hw_to_sw; | |
875 | /* spinlock for allocating and releasing send context resources */ | |
876 | spinlock_t sc_lock; | |
35f6befc JJ |
877 | /* lock for pio_map */ |
878 | spinlock_t pio_map_lock; | |
6e768f06 SS |
879 | /* Send Context initialization lock. */ |
880 | spinlock_t sc_init_lock; | |
881 | /* lock for sdma_map */ | |
882 | spinlock_t sde_map_lock; | |
35f6befc JJ |
883 | /* array of kernel send contexts */ |
884 | struct send_context **kernel_send_context; | |
885 | /* array of vl maps */ | |
886 | struct pio_vl_map __rcu *pio_map; | |
6e768f06 SS |
887 | /* default flags to last descriptor */ |
888 | u64 default_desc1; | |
77241056 MM |
889 | |
890 | /* fields common to all SDMA engines */ | |
891 | ||
77241056 MM |
892 | volatile __le64 *sdma_heads_dma; /* DMA'ed by chip */ |
893 | dma_addr_t sdma_heads_phys; | |
894 | void *sdma_pad_dma; /* DMA'ed by chip */ | |
895 | dma_addr_t sdma_pad_phys; | |
896 | /* for deallocation */ | |
897 | size_t sdma_heads_size; | |
898 | /* number from the chip */ | |
899 | u32 chip_sdma_engines; | |
900 | /* num used */ | |
901 | u32 num_sdma; | |
77241056 MM |
902 | /* array of engines sized by num_sdma */ |
903 | struct sdma_engine *per_sdma; | |
904 | /* array of vl maps */ | |
905 | struct sdma_vl_map __rcu *sdma_map; | |
906 | /* SPC freeze waitqueue and variable */ | |
907 | wait_queue_head_t sdma_unfreeze_wq; | |
908 | atomic_t sdma_unfreeze_count; | |
909 | ||
6e768f06 SS |
910 | u32 lcb_access_count; /* count of LCB users */ |
911 | ||
78eb129d DL |
912 | /* common data between shared ASIC HFIs in this OS */ |
913 | struct hfi1_asic_data *asic_data; | |
914 | ||
77241056 MM |
915 | /* mem-mapped pointer to base of PIO buffers */ |
916 | void __iomem *piobase; | |
917 | /* | |
918 | * write-combining mem-mapped pointer to base of RcvArray | |
919 | * memory. | |
920 | */ | |
921 | void __iomem *rcvarray_wc; | |
922 | /* | |
923 | * credit return base - a per-NUMA range of DMA address that | |
924 | * the chip will use to update the per-context free counter | |
925 | */ | |
926 | struct credit_return_base *cr_base; | |
927 | ||
928 | /* send context numbers and sizes for each type */ | |
929 | struct sc_config_sizes sc_sizes[SC_MAX]; | |
930 | ||
77241056 MM |
931 | char *boardname; /* human readable board info */ |
932 | ||
77241056 MM |
933 | /* reset value */ |
934 | u64 z_int_counter; | |
935 | u64 z_rcv_limit; | |
89abfc8d | 936 | u64 z_send_schedule; |
6e768f06 | 937 | |
89abfc8d | 938 | u64 __percpu *send_schedule; |
77241056 MM |
939 | /* number of receive contexts in use by the driver */ |
940 | u32 num_rcv_contexts; | |
941 | /* number of pio send contexts in use by the driver */ | |
942 | u32 num_send_contexts; | |
943 | /* | |
944 | * number of ctxts available for PSM open | |
945 | */ | |
946 | u32 freectxts; | |
affa48de AD |
947 | /* total number of available user/PSM contexts */ |
948 | u32 num_user_contexts; | |
77241056 MM |
949 | /* base receive interrupt timeout, in CSR units */ |
950 | u32 rcv_intr_timeout_csr; | |
951 | ||
6e768f06 | 952 | u32 freezelen; /* max length of freezemsg */ |
77241056 MM |
953 | u64 __iomem *egrtidbase; |
954 | spinlock_t sendctrl_lock; /* protect changes to SendCtrl */ | |
955 | spinlock_t rcvctrl_lock; /* protect changes to RcvCtrl */ | |
956 | /* around rcd and (user ctxts) ctxt_cnt use (intr vs free) */ | |
957 | spinlock_t uctxt_lock; /* rcd and user context changes */ | |
22546b74 TS |
958 | struct mutex dc8051_lock; /* exclusive access to 8051 */ |
959 | struct workqueue_struct *update_cntr_wq; | |
960 | struct work_struct update_cntr_work; | |
77241056 MM |
961 | /* exclusive access to 8051 memory */ |
962 | spinlock_t dc8051_memlock; | |
963 | int dc8051_timed_out; /* remember if the 8051 timed out */ | |
964 | /* | |
965 | * A page that will hold event notification bitmaps for all | |
966 | * contexts. This page will be mapped into all processes. | |
967 | */ | |
968 | unsigned long *events; | |
969 | /* | |
970 | * per unit status, see also portdata statusp | |
971 | * mapped read-only into user processes so they can get unit and | |
972 | * IB link status cheaply | |
973 | */ | |
974 | struct hfi1_status *status; | |
77241056 MM |
975 | |
976 | /* revision register shadow */ | |
977 | u64 revision; | |
978 | /* Base GUID for device (network order) */ | |
979 | u64 base_guid; | |
980 | ||
981 | /* these are the "32 bit" regs */ | |
982 | ||
983 | /* value we put in kr_rcvhdrsize */ | |
984 | u32 rcvhdrsize; | |
985 | /* number of receive contexts the chip supports */ | |
986 | u32 chip_rcv_contexts; | |
987 | /* number of receive array entries */ | |
988 | u32 chip_rcv_array_count; | |
989 | /* number of PIO send contexts the chip supports */ | |
990 | u32 chip_send_contexts; | |
991 | /* number of bytes in the PIO memory buffer */ | |
992 | u32 chip_pio_mem_size; | |
993 | /* number of bytes in the SDMA memory buffer */ | |
994 | u32 chip_sdma_mem_size; | |
995 | ||
996 | /* size of each rcvegrbuffer */ | |
997 | u32 rcvegrbufsize; | |
998 | /* log2 of above */ | |
999 | u16 rcvegrbufsize_shift; | |
1000 | /* both sides of the PCIe link are gen3 capable */ | |
1001 | u8 link_gen3_capable; | |
6e768f06 SS |
1002 | /* default link down value (poll/sleep) */ |
1003 | u8 link_default; | |
77241056 MM |
1004 | /* localbus width (1, 2,4,8,16,32) from config space */ |
1005 | u32 lbus_width; | |
1006 | /* localbus speed in MHz */ | |
1007 | u32 lbus_speed; | |
1008 | int unit; /* unit # of this chip */ | |
1009 | int node; /* home node of this chip */ | |
1010 | ||
1011 | /* save these PCI fields to restore after a reset */ | |
1012 | u32 pcibar0; | |
1013 | u32 pcibar1; | |
1014 | u32 pci_rom; | |
1015 | u16 pci_command; | |
1016 | u16 pcie_devctl; | |
1017 | u16 pcie_lnkctl; | |
1018 | u16 pcie_devctl2; | |
1019 | u32 pci_msix0; | |
1020 | u32 pci_lnkctl3; | |
1021 | u32 pci_tph2; | |
1022 | ||
1023 | /* | |
1024 | * ASCII serial number, from flash, large enough for original | |
1025 | * all digit strings, and longer serial number format | |
1026 | */ | |
1027 | u8 serial[SERIAL_MAX]; | |
1028 | /* human readable board version */ | |
1029 | u8 boardversion[BOARD_VERS_MAX]; | |
1030 | u8 lbus_info[32]; /* human readable localbus info */ | |
1031 | /* chip major rev, from CceRevision */ | |
1032 | u8 majrev; | |
1033 | /* chip minor rev, from CceRevision */ | |
1034 | u8 minrev; | |
1035 | /* hardware ID */ | |
1036 | u8 hfi1_id; | |
1037 | /* implementation code */ | |
1038 | u8 icode; | |
77241056 MM |
1039 | /* vAU of this device */ |
1040 | u8 vau; | |
1041 | /* vCU of this device */ | |
1042 | u8 vcu; | |
1043 | /* link credits of this device */ | |
1044 | u16 link_credits; | |
1045 | /* initial vl15 credits to use */ | |
1046 | u16 vl15_init; | |
1047 | ||
b3e6b4bd BJ |
1048 | /* |
1049 | * Cached value for vl15buf, read during verify cap interrupt. VL15 | |
1050 | * credits are to be kept at 0 and set when handling the link-up | |
1051 | * interrupt. This removes the possibility of receiving VL15 MAD | |
1052 | * packets before this HFI is ready. | |
1053 | */ | |
1054 | u16 vl15buf_cached; | |
1055 | ||
77241056 | 1056 | /* Misc small ints */ |
77241056 MM |
1057 | u8 n_krcv_queues; |
1058 | u8 qos_shift; | |
77241056 | 1059 | |
77241056 | 1060 | u16 irev; /* implementation revision */ |
5e6e9424 | 1061 | u32 dc8051_ver; /* 8051 firmware version */ |
77241056 | 1062 | |
6e768f06 | 1063 | spinlock_t hfi1_diag_trans_lock; /* protect diag observer ops */ |
c3838b39 | 1064 | struct platform_config platform_config; |
77241056 | 1065 | struct platform_config_cache pcfg_cache; |
77241056 MM |
1066 | |
1067 | struct diag_client *diag_client; | |
77241056 MM |
1068 | |
1069 | /* MSI-X information */ | |
1070 | struct hfi1_msix_entry *msix_entries; | |
1071 | u32 num_msix_entries; | |
2280740f | 1072 | u32 first_dyn_msix_idx; |
77241056 MM |
1073 | |
1074 | /* INTx information */ | |
1075 | u32 requested_intx_irq; /* did we request one? */ | |
1076 | char intx_name[MAX_NAME_SIZE]; /* INTx name */ | |
1077 | ||
1078 | /* general interrupt: mask of handled interrupts */ | |
1079 | u64 gi_mask[CCE_NUM_INT_CSRS]; | |
1080 | ||
1081 | struct rcv_array_data rcv_entries; | |
1082 | ||
6e768f06 SS |
1083 | /* cycle length of PS* counters in HW (in picoseconds) */ |
1084 | u16 psxmitwait_check_rate; | |
1085 | ||
77241056 MM |
1086 | /* |
1087 | * 64 bit synthetic counters | |
1088 | */ | |
1089 | struct timer_list synth_stats_timer; | |
1090 | ||
1091 | /* | |
1092 | * device counters | |
1093 | */ | |
1094 | char *cntrnames; | |
1095 | size_t cntrnameslen; | |
1096 | size_t ndevcntrs; | |
1097 | u64 *cntrs; | |
1098 | u64 *scntrs; | |
1099 | ||
1100 | /* | |
1101 | * remembered values for synthetic counters | |
1102 | */ | |
1103 | u64 last_tx; | |
1104 | u64 last_rx; | |
1105 | ||
1106 | /* | |
1107 | * per-port counters | |
1108 | */ | |
1109 | size_t nportcntrs; | |
1110 | char *portcntrnames; | |
1111 | size_t portcntrnameslen; | |
1112 | ||
77241056 MM |
1113 | struct err_info_rcvport err_info_rcvport; |
1114 | struct err_info_constraint err_info_rcv_constraint; | |
1115 | struct err_info_constraint err_info_xmit_constraint; | |
77241056 MM |
1116 | |
1117 | atomic_t drop_packet; | |
1118 | u8 do_drop; | |
6e768f06 SS |
1119 | u8 err_info_uncorrectable; |
1120 | u8 err_info_fmconfig; | |
77241056 | 1121 | |
2c5b521a JR |
1122 | /* |
1123 | * Software counters for the status bits defined by the | |
1124 | * associated error status registers | |
1125 | */ | |
1126 | u64 cce_err_status_cnt[NUM_CCE_ERR_STATUS_COUNTERS]; | |
1127 | u64 rcv_err_status_cnt[NUM_RCV_ERR_STATUS_COUNTERS]; | |
1128 | u64 misc_err_status_cnt[NUM_MISC_ERR_STATUS_COUNTERS]; | |
1129 | u64 send_pio_err_status_cnt[NUM_SEND_PIO_ERR_STATUS_COUNTERS]; | |
1130 | u64 send_dma_err_status_cnt[NUM_SEND_DMA_ERR_STATUS_COUNTERS]; | |
1131 | u64 send_egress_err_status_cnt[NUM_SEND_EGRESS_ERR_STATUS_COUNTERS]; | |
1132 | u64 send_err_status_cnt[NUM_SEND_ERR_STATUS_COUNTERS]; | |
1133 | ||
1134 | /* Software counter that spans all contexts */ | |
1135 | u64 sw_ctxt_err_status_cnt[NUM_SEND_CTXT_ERR_STATUS_COUNTERS]; | |
1136 | /* Software counter that spans all DMA engines */ | |
1137 | u64 sw_send_dma_eng_err_status_cnt[ | |
1138 | NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS]; | |
1139 | /* Software counter that aggregates all cce_err_status errors */ | |
1140 | u64 sw_cce_err_status_aggregate; | |
2b719046 JP |
1141 | /* Software counter that aggregates all bypass packet rcv errors */ |
1142 | u64 sw_rcv_bypass_packet_errors; | |
6e768f06 | 1143 | /* receive interrupt function */ |
77241056 MM |
1144 | rhf_rcv_function_ptr normal_rhf_rcv_functions[8]; |
1145 | ||
6e768f06 SS |
1146 | /* Save the enabled LCB error bits */ |
1147 | u64 lcb_err_en; | |
1148 | ||
77241056 | 1149 | /* |
eacc830f DD |
1150 | * Capability to have different send engines simply by changing a |
1151 | * pointer value. | |
77241056 | 1152 | */ |
6e768f06 | 1153 | send_routine process_pio_send ____cacheline_aligned_in_smp; |
14553ca1 | 1154 | send_routine process_dma_send; |
77241056 MM |
1155 | void (*pio_inline_send)(struct hfi1_devdata *dd, struct pio_buf *pbuf, |
1156 | u64 pbc, const void *from, size_t count); | |
d4829ea6 VN |
1157 | int (*process_vnic_dma_send)(struct hfi1_devdata *dd, u8 q_idx, |
1158 | struct hfi1_vnic_vport_info *vinfo, | |
1159 | struct sk_buff *skb, u64 pbc, u8 plen); | |
6e768f06 SS |
1160 | /* hfi1_pportdata, points to array of (physical) port-specific |
1161 | * data structs, indexed by pidx (0..n-1) | |
1162 | */ | |
1163 | struct hfi1_pportdata *pport; | |
1164 | /* receive context data */ | |
1165 | struct hfi1_ctxtdata **rcd; | |
1166 | u64 __percpu *int_counter; | |
1167 | /* device (not port) flags, basically device capabilities */ | |
1168 | u16 flags; | |
1169 | /* Number of physical ports available */ | |
1170 | u8 num_pports; | |
2280740f VN |
1171 | /* Lowest context number which can be used by user processes or VNIC */ |
1172 | u8 first_dyn_alloc_ctxt; | |
6e768f06 SS |
1173 | /* adding a new field here would make it part of this cacheline */ |
1174 | ||
1175 | /* seqlock for sc2vl */ | |
1176 | seqlock_t sc2vl_lock ____cacheline_aligned_in_smp; | |
1177 | u64 sc2vl[4]; | |
1178 | /* receive interrupt functions */ | |
1179 | rhf_rcv_function_ptr *rhf_rcv_function_map; | |
1180 | u64 __percpu *rcv_limit; | |
1181 | u16 rhf_offset; /* offset of RHF within receive header entry */ | |
1182 | /* adding a new field here would make it part of this cacheline */ | |
77241056 MM |
1183 | |
1184 | /* OUI comes from the HW. Used everywhere as 3 separate bytes. */ | |
1185 | u8 oui1; | |
1186 | u8 oui2; | |
1187 | u8 oui3; | |
6e768f06 SS |
1188 | u8 dc_shutdown; |
1189 | ||
77241056 MM |
1190 | /* Timer and counter used to detect RcvBufOvflCnt changes */ |
1191 | struct timer_list rcverr_timer; | |
77241056 | 1192 | |
77241056 MM |
1193 | wait_queue_head_t event_queue; |
1194 | ||
46b010d3 MB |
1195 | /* receive context tail dummy address */ |
1196 | __le64 *rcvhdrtail_dummy_kvaddr; | |
60368186 | 1197 | dma_addr_t rcvhdrtail_dummy_dma; |
affa48de | 1198 | |
6e768f06 | 1199 | u32 rcv_ovfl_cnt; |
affa48de AD |
1200 | /* Serialize ASPM enable/disable between multiple verbs contexts */ |
1201 | spinlock_t aspm_lock; | |
1202 | /* Number of verbs contexts which have disabled ASPM */ | |
1203 | atomic_t aspm_disabled_cnt; | |
acd7c8fe TS |
1204 | /* Keeps track of user space clients */ |
1205 | atomic_t user_refcount; | |
1206 | /* Used to wait for outstanding user space clients before dev removal */ | |
1207 | struct completion user_comp; | |
957558c9 | 1208 | |
6e768f06 SS |
1209 | bool eprom_available; /* true if EPROM is available for this device */ |
1210 | bool aspm_supported; /* Does HW support ASPM */ | |
1211 | bool aspm_enabled; /* ASPM state: enabled/disabled */ | |
5a52a7ac | 1212 | struct rhashtable *sdma_rht; |
6e768f06 | 1213 | |
e11ffbd5 | 1214 | struct kobject kobj; |
d4829ea6 VN |
1215 | |
1216 | /* vnic data */ | |
1217 | struct hfi1_vnic_data vnic; | |
77241056 MM |
1218 | }; |
1219 | ||
2280740f VN |
1220 | static inline bool hfi1_vnic_is_rsm_full(struct hfi1_devdata *dd, int spare) |
1221 | { | |
1222 | return (dd->vnic.rmt_start + spare) > NUM_MAP_ENTRIES; | |
1223 | } | |
1224 | ||
77241056 | 1225 | /* 8051 firmware version helper */ |
5e6e9424 MR |
1226 | #define dc8051_ver(a, b, c) ((a) << 16 | (b) << 8 | (c)) |
1227 | #define dc8051_ver_maj(a) (((a) & 0xff0000) >> 16) | |
1228 | #define dc8051_ver_min(a) (((a) & 0x00ff00) >> 8) | |
1229 | #define dc8051_ver_patch(a) ((a) & 0x0000ff) | |
77241056 MM |
1230 | |
1231 | /* f_put_tid types */ | |
1232 | #define PT_EXPECTED 0 | |
1233 | #define PT_EAGER 1 | |
1234 | #define PT_INVALID 2 | |
1235 | ||
06e0ffa6 | 1236 | struct tid_rb_node; |
f727a0c3 | 1237 | struct mmu_rb_node; |
e0b09ac5 | 1238 | struct mmu_rb_handler; |
f727a0c3 | 1239 | |
77241056 MM |
1240 | /* Private data for file operations */ |
1241 | struct hfi1_filedata { | |
5fbded48 | 1242 | struct hfi1_devdata *dd; |
77241056 | 1243 | struct hfi1_ctxtdata *uctxt; |
77241056 MM |
1244 | struct hfi1_user_sdma_comp_q *cq; |
1245 | struct hfi1_user_sdma_pkt_q *pq; | |
8737ce95 | 1246 | u16 subctxt; |
77241056 MM |
1247 | /* for cpu affinity; -1 if none */ |
1248 | int rec_cpu_num; | |
a7922f7d | 1249 | u32 tid_n_pinned; |
e0b09ac5 | 1250 | struct mmu_rb_handler *handler; |
06e0ffa6 | 1251 | struct tid_rb_node **entry_to_rb; |
a86cd357 MH |
1252 | spinlock_t tid_lock; /* protect tid_[limit,used] counters */ |
1253 | u32 tid_limit; | |
1254 | u32 tid_used; | |
a86cd357 MH |
1255 | u32 *invalid_tids; |
1256 | u32 invalid_tid_idx; | |
06e0ffa6 MH |
1257 | /* protect invalid_tids array and invalid_tid_idx */ |
1258 | spinlock_t invalid_lock; | |
3faa3d9a | 1259 | struct mm_struct *mm; |
77241056 MM |
1260 | }; |
1261 | ||
1262 | extern struct list_head hfi1_dev_list; | |
1263 | extern spinlock_t hfi1_devs_lock; | |
1264 | struct hfi1_devdata *hfi1_lookup(int unit); | |
1265 | extern u32 hfi1_cpulist_count; | |
1266 | extern unsigned long *hfi1_cpulist; | |
1267 | ||
f4cd8765 | 1268 | int hfi1_init(struct hfi1_devdata *dd, int reinit); |
77241056 MM |
1269 | int hfi1_count_active_units(void); |
1270 | ||
f4cd8765 MR |
1271 | int hfi1_diag_add(struct hfi1_devdata *dd); |
1272 | void hfi1_diag_remove(struct hfi1_devdata *dd); | |
77241056 MM |
1273 | void handle_linkup_change(struct hfi1_devdata *dd, u32 linkup); |
1274 | ||
1275 | void handle_user_interrupt(struct hfi1_ctxtdata *rcd); | |
1276 | ||
f4cd8765 MR |
1277 | int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd); |
1278 | int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *rcd); | |
77241056 | 1279 | int hfi1_create_ctxts(struct hfi1_devdata *dd); |
f4cd8765 MR |
1280 | struct hfi1_ctxtdata *hfi1_create_ctxtdata(struct hfi1_pportdata *ppd, u32 ctxt, |
1281 | int numa); | |
1282 | void hfi1_init_pportdata(struct pci_dev *pdev, struct hfi1_pportdata *ppd, | |
1283 | struct hfi1_devdata *dd, u8 hw_pidx, u8 port); | |
1284 | void hfi1_free_ctxtdata(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd); | |
1285 | ||
1286 | int handle_receive_interrupt(struct hfi1_ctxtdata *rcd, int thread); | |
1287 | int handle_receive_interrupt_nodma_rtail(struct hfi1_ctxtdata *rcd, int thread); | |
1288 | int handle_receive_interrupt_dma_rtail(struct hfi1_ctxtdata *rcd, int thread); | |
fb9036dd | 1289 | void set_all_slowpath(struct hfi1_devdata *dd); |
2280740f VN |
1290 | void hfi1_vnic_synchronize_irq(struct hfi1_devdata *dd); |
1291 | void hfi1_set_vnic_msix_info(struct hfi1_ctxtdata *rcd); | |
1292 | void hfi1_reset_vnic_msix_info(struct hfi1_ctxtdata *rcd); | |
f4f30031 | 1293 | |
d6373019 SS |
1294 | extern const struct pci_device_id hfi1_pci_tbl[]; |
1295 | ||
f4f30031 DL |
1296 | /* receive packet handler dispositions */ |
1297 | #define RCV_PKT_OK 0x0 /* keep going */ | |
1298 | #define RCV_PKT_LIMIT 0x1 /* stop, hit limit, start thread */ | |
1299 | #define RCV_PKT_DONE 0x2 /* stop, no more packets detected */ | |
1300 | ||
1301 | /* calculate the current RHF address */ | |
1302 | static inline __le32 *get_rhf_addr(struct hfi1_ctxtdata *rcd) | |
1303 | { | |
1304 | return (__le32 *)rcd->rcvhdrq + rcd->head + rcd->dd->rhf_offset; | |
1305 | } | |
1306 | ||
77241056 MM |
1307 | int hfi1_reset_device(int); |
1308 | ||
1309 | /* return the driver's idea of the logical OPA port state */ | |
1310 | static inline u32 driver_lstate(struct hfi1_pportdata *ppd) | |
1311 | { | |
98b9ee20 SS |
1312 | /* |
1313 | * The driver does some processing from the time the logical | |
1314 | * link state is at INIT to the time the SM can be notified | |
1315 | * as such. Return IB_PORT_DOWN until the software state | |
1316 | * is ready. | |
1317 | */ | |
1318 | if (ppd->lstate == IB_PORT_INIT && !(ppd->host_link_state & HLS_UP)) | |
1319 | return IB_PORT_DOWN; | |
1320 | else | |
1321 | return ppd->lstate; | |
77241056 MM |
1322 | } |
1323 | ||
fb9036dd JS |
1324 | void receive_interrupt_work(struct work_struct *work); |
1325 | ||
1326 | /* extract service channel from header and rhf */ | |
aad559c2 | 1327 | static inline int hfi1_9B_get_sc5(struct ib_header *hdr, u64 rhf) |
fb9036dd | 1328 | { |
cb427057 | 1329 | return ib_get_sc(hdr) | ((!!(rhf_dc_info(rhf))) << 4); |
fb9036dd JS |
1330 | } |
1331 | ||
08fe16f6 MH |
1332 | #define HFI1_JKEY_WIDTH 16 |
1333 | #define HFI1_JKEY_MASK (BIT(16) - 1) | |
1334 | #define HFI1_ADMIN_JKEY_RANGE 32 | |
1335 | ||
1336 | /* | |
1337 | * J_KEYs are split and allocated in the following groups: | |
1338 | * 0 - 31 - users with administrator privileges | |
1339 | * 32 - 63 - kernel protocols using KDETH packets | |
1340 | * 64 - 65535 - all other users using KDETH packets | |
1341 | */ | |
77241056 MM |
1342 | static inline u16 generate_jkey(kuid_t uid) |
1343 | { | |
08fe16f6 MH |
1344 | u16 jkey = from_kuid(current_user_ns(), uid) & HFI1_JKEY_MASK; |
1345 | ||
1346 | if (capable(CAP_SYS_ADMIN)) | |
1347 | jkey &= HFI1_ADMIN_JKEY_RANGE - 1; | |
1348 | else if (jkey < 64) | |
1349 | jkey |= BIT(HFI1_JKEY_WIDTH - 1); | |
1350 | ||
1351 | return jkey; | |
77241056 MM |
1352 | } |
1353 | ||
1354 | /* | |
1355 | * active_egress_rate | |
1356 | * | |
1357 | * returns the active egress rate in units of [10^6 bits/sec] | |
1358 | */ | |
1359 | static inline u32 active_egress_rate(struct hfi1_pportdata *ppd) | |
1360 | { | |
1361 | u16 link_speed = ppd->link_speed_active; | |
1362 | u16 link_width = ppd->link_width_active; | |
1363 | u32 egress_rate; | |
1364 | ||
1365 | if (link_speed == OPA_LINK_SPEED_25G) | |
1366 | egress_rate = 25000; | |
1367 | else /* assume OPA_LINK_SPEED_12_5G */ | |
1368 | egress_rate = 12500; | |
1369 | ||
1370 | switch (link_width) { | |
1371 | case OPA_LINK_WIDTH_4X: | |
1372 | egress_rate *= 4; | |
1373 | break; | |
1374 | case OPA_LINK_WIDTH_3X: | |
1375 | egress_rate *= 3; | |
1376 | break; | |
1377 | case OPA_LINK_WIDTH_2X: | |
1378 | egress_rate *= 2; | |
1379 | break; | |
1380 | default: | |
1381 | /* assume IB_WIDTH_1X */ | |
1382 | break; | |
1383 | } | |
1384 | ||
1385 | return egress_rate; | |
1386 | } | |
1387 | ||
1388 | /* | |
1389 | * egress_cycles | |
1390 | * | |
1391 | * Returns the number of 'fabric clock cycles' to egress a packet | |
1392 | * of length 'len' bytes, at 'rate' Mbit/s. Since the fabric clock | |
1393 | * rate is (approximately) 805 MHz, the units of the returned value | |
1394 | * are (1/805 MHz). | |
1395 | */ | |
1396 | static inline u32 egress_cycles(u32 len, u32 rate) | |
1397 | { | |
1398 | u32 cycles; | |
1399 | ||
1400 | /* | |
1401 | * cycles is: | |
1402 | * | |
1403 | * (length) [bits] / (rate) [bits/sec] | |
1404 | * --------------------------------------------------- | |
1405 | * fabric_clock_period == 1 /(805 * 10^6) [cycles/sec] | |
1406 | */ | |
1407 | ||
1408 | cycles = len * 8; /* bits */ | |
1409 | cycles *= 805; | |
1410 | cycles /= rate; | |
1411 | ||
1412 | return cycles; | |
1413 | } | |
1414 | ||
1415 | void set_link_ipg(struct hfi1_pportdata *ppd); | |
1416 | void process_becn(struct hfi1_pportdata *ppd, u8 sl, u16 rlid, u32 lqpn, | |
1417 | u32 rqpn, u8 svc_type); | |
895420dd | 1418 | void return_cnp(struct hfi1_ibport *ibp, struct rvt_qp *qp, u32 remote_qpn, |
77241056 MM |
1419 | u32 pkey, u32 slid, u32 dlid, u8 sc5, |
1420 | const struct ib_grh *old_grh); | |
e38d1e4f SS |
1421 | #define PKEY_CHECK_INVALID -1 |
1422 | int egress_pkey_check(struct hfi1_pportdata *ppd, __be16 *lrh, __be32 *bth, | |
1423 | u8 sc5, int8_t s_pkey_index); | |
77241056 MM |
1424 | |
1425 | #define PACKET_EGRESS_TIMEOUT 350 | |
1426 | static inline void pause_for_credit_return(struct hfi1_devdata *dd) | |
1427 | { | |
1428 | /* Pause at least 1us, to ensure chip returns all credits */ | |
1429 | u32 usec = cclock_to_ns(dd, PACKET_EGRESS_TIMEOUT) / 1000; | |
1430 | ||
1431 | udelay(usec ? usec : 1); | |
1432 | } | |
1433 | ||
1434 | /** | |
1435 | * sc_to_vlt() reverse lookup sc to vl | |
1436 | * @dd - devdata | |
1437 | * @sc5 - 5 bit sc | |
1438 | */ | |
1439 | static inline u8 sc_to_vlt(struct hfi1_devdata *dd, u8 sc5) | |
1440 | { | |
1441 | unsigned seq; | |
1442 | u8 rval; | |
1443 | ||
1444 | if (sc5 >= OPA_MAX_SCS) | |
1445 | return (u8)(0xff); | |
1446 | ||
1447 | do { | |
1448 | seq = read_seqbegin(&dd->sc2vl_lock); | |
1449 | rval = *(((u8 *)dd->sc2vl) + sc5); | |
1450 | } while (read_seqretry(&dd->sc2vl_lock, seq)); | |
1451 | ||
1452 | return rval; | |
1453 | } | |
1454 | ||
1455 | #define PKEY_MEMBER_MASK 0x8000 | |
1456 | #define PKEY_LOW_15_MASK 0x7fff | |
1457 | ||
1458 | /* | |
1459 | * ingress_pkey_matches_entry - return 1 if the pkey matches ent (ent | |
1460 | * being an entry from the ingress partition key table), return 0 | |
1461 | * otherwise. Use the matching criteria for ingress partition keys | |
1462 | * specified in the OPAv1 spec., section 9.10.14. | |
1463 | */ | |
1464 | static inline int ingress_pkey_matches_entry(u16 pkey, u16 ent) | |
1465 | { | |
1466 | u16 mkey = pkey & PKEY_LOW_15_MASK; | |
1467 | u16 ment = ent & PKEY_LOW_15_MASK; | |
1468 | ||
1469 | if (mkey == ment) { | |
1470 | /* | |
1471 | * If pkey[15] is clear (limited partition member), | |
1472 | * is bit 15 in the corresponding table element | |
1473 | * clear (limited member)? | |
1474 | */ | |
1475 | if (!(pkey & PKEY_MEMBER_MASK)) | |
1476 | return !!(ent & PKEY_MEMBER_MASK); | |
1477 | return 1; | |
1478 | } | |
1479 | return 0; | |
1480 | } | |
1481 | ||
1482 | /* | |
1483 | * ingress_pkey_table_search - search the entire pkey table for | |
1484 | * an entry which matches 'pkey'. return 0 if a match is found, | |
1485 | * and 1 otherwise. | |
1486 | */ | |
1487 | static int ingress_pkey_table_search(struct hfi1_pportdata *ppd, u16 pkey) | |
1488 | { | |
1489 | int i; | |
1490 | ||
1491 | for (i = 0; i < MAX_PKEY_VALUES; i++) { | |
1492 | if (ingress_pkey_matches_entry(pkey, ppd->pkeys[i])) | |
1493 | return 0; | |
1494 | } | |
1495 | return 1; | |
1496 | } | |
1497 | ||
1498 | /* | |
1499 | * ingress_pkey_table_fail - record a failure of ingress pkey validation, | |
1500 | * i.e., increment port_rcv_constraint_errors for the port, and record | |
1501 | * the 'error info' for this failure. | |
1502 | */ | |
1503 | static void ingress_pkey_table_fail(struct hfi1_pportdata *ppd, u16 pkey, | |
1504 | u16 slid) | |
1505 | { | |
1506 | struct hfi1_devdata *dd = ppd->dd; | |
1507 | ||
1508 | incr_cntr64(&ppd->port_rcv_constraint_errors); | |
1509 | if (!(dd->err_info_rcv_constraint.status & OPA_EI_STATUS_SMASK)) { | |
1510 | dd->err_info_rcv_constraint.status |= OPA_EI_STATUS_SMASK; | |
1511 | dd->err_info_rcv_constraint.slid = slid; | |
1512 | dd->err_info_rcv_constraint.pkey = pkey; | |
1513 | } | |
1514 | } | |
1515 | ||
1516 | /* | |
1517 | * ingress_pkey_check - Return 0 if the ingress pkey is valid, return 1 | |
1518 | * otherwise. Use the criteria in the OPAv1 spec, section 9.10.14. idx | |
1519 | * is a hint as to the best place in the partition key table to begin | |
1520 | * searching. This function should not be called on the data path because | |
1521 | * of performance reasons. On datapath pkey check is expected to be done | |
1522 | * by HW and rcv_pkey_check function should be called instead. | |
1523 | */ | |
1524 | static inline int ingress_pkey_check(struct hfi1_pportdata *ppd, u16 pkey, | |
1525 | u8 sc5, u8 idx, u16 slid) | |
1526 | { | |
1527 | if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN)) | |
1528 | return 0; | |
1529 | ||
1530 | /* If SC15, pkey[0:14] must be 0x7fff */ | |
1531 | if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK)) | |
1532 | goto bad; | |
1533 | ||
1534 | /* Is the pkey = 0x0, or 0x8000? */ | |
1535 | if ((pkey & PKEY_LOW_15_MASK) == 0) | |
1536 | goto bad; | |
1537 | ||
1538 | /* The most likely matching pkey has index 'idx' */ | |
1539 | if (ingress_pkey_matches_entry(pkey, ppd->pkeys[idx])) | |
1540 | return 0; | |
1541 | ||
1542 | /* no match - try the whole table */ | |
1543 | if (!ingress_pkey_table_search(ppd, pkey)) | |
1544 | return 0; | |
1545 | ||
1546 | bad: | |
1547 | ingress_pkey_table_fail(ppd, pkey, slid); | |
1548 | return 1; | |
1549 | } | |
1550 | ||
1551 | /* | |
1552 | * rcv_pkey_check - Return 0 if the ingress pkey is valid, return 1 | |
1553 | * otherwise. It only ensures pkey is vlid for QP0. This function | |
1554 | * should be called on the data path instead of ingress_pkey_check | |
1555 | * as on data path, pkey check is done by HW (except for QP0). | |
1556 | */ | |
1557 | static inline int rcv_pkey_check(struct hfi1_pportdata *ppd, u16 pkey, | |
1558 | u8 sc5, u16 slid) | |
1559 | { | |
1560 | if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN)) | |
1561 | return 0; | |
1562 | ||
1563 | /* If SC15, pkey[0:14] must be 0x7fff */ | |
1564 | if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK)) | |
1565 | goto bad; | |
1566 | ||
1567 | return 0; | |
1568 | bad: | |
1569 | ingress_pkey_table_fail(ppd, pkey, slid); | |
1570 | return 1; | |
1571 | } | |
1572 | ||
1573 | /* MTU handling */ | |
1574 | ||
1575 | /* MTU enumeration, 256-4k match IB */ | |
1576 | #define OPA_MTU_0 0 | |
1577 | #define OPA_MTU_256 1 | |
1578 | #define OPA_MTU_512 2 | |
1579 | #define OPA_MTU_1024 3 | |
1580 | #define OPA_MTU_2048 4 | |
1581 | #define OPA_MTU_4096 5 | |
1582 | ||
1583 | u32 lrh_max_header_bytes(struct hfi1_devdata *dd); | |
1584 | int mtu_to_enum(u32 mtu, int default_if_bad); | |
f4cd8765 | 1585 | u16 enum_to_mtu(int mtu); |
77241056 MM |
1586 | static inline int valid_ib_mtu(unsigned int mtu) |
1587 | { | |
1588 | return mtu == 256 || mtu == 512 || | |
1589 | mtu == 1024 || mtu == 2048 || | |
1590 | mtu == 4096; | |
1591 | } | |
f4d507cd | 1592 | |
77241056 MM |
1593 | static inline int valid_opa_max_mtu(unsigned int mtu) |
1594 | { | |
1595 | return mtu >= 2048 && | |
1596 | (valid_ib_mtu(mtu) || mtu == 8192 || mtu == 10240); | |
1597 | } | |
1598 | ||
f4cd8765 | 1599 | int set_mtu(struct hfi1_pportdata *ppd); |
77241056 | 1600 | |
f4cd8765 MR |
1601 | int hfi1_set_lid(struct hfi1_pportdata *ppd, u32 lid, u8 lmc); |
1602 | void hfi1_disable_after_error(struct hfi1_devdata *dd); | |
1603 | int hfi1_set_uevent_bits(struct hfi1_pportdata *ppd, const int evtbit); | |
1604 | int hfi1_rcvbuf_validate(u32 size, u8 type, u16 *encode); | |
77241056 | 1605 | |
f4cd8765 MR |
1606 | int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t); |
1607 | int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t); | |
77241056 | 1608 | |
b3e6b4bd BJ |
1609 | void set_up_vau(struct hfi1_devdata *dd, u8 vau); |
1610 | void set_up_vl15(struct hfi1_devdata *dd, u16 vl15buf); | |
77241056 MM |
1611 | void reset_link_credits(struct hfi1_devdata *dd); |
1612 | void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu); | |
1613 | ||
8a4d3444 | 1614 | int set_buffer_control(struct hfi1_pportdata *ppd, struct buffer_control *bc); |
77241056 | 1615 | |
77241056 MM |
1616 | static inline struct hfi1_devdata *dd_from_ppd(struct hfi1_pportdata *ppd) |
1617 | { | |
1618 | return ppd->dd; | |
1619 | } | |
1620 | ||
1621 | static inline struct hfi1_devdata *dd_from_dev(struct hfi1_ibdev *dev) | |
1622 | { | |
1623 | return container_of(dev, struct hfi1_devdata, verbs_dev); | |
1624 | } | |
1625 | ||
1626 | static inline struct hfi1_devdata *dd_from_ibdev(struct ib_device *ibdev) | |
1627 | { | |
1628 | return dd_from_dev(to_idev(ibdev)); | |
1629 | } | |
1630 | ||
1631 | static inline struct hfi1_pportdata *ppd_from_ibp(struct hfi1_ibport *ibp) | |
1632 | { | |
1633 | return container_of(ibp, struct hfi1_pportdata, ibport_data); | |
1634 | } | |
1635 | ||
45b59eef HC |
1636 | static inline struct hfi1_ibdev *dev_from_rdi(struct rvt_dev_info *rdi) |
1637 | { | |
1638 | return container_of(rdi, struct hfi1_ibdev, rdi); | |
1639 | } | |
1640 | ||
77241056 MM |
1641 | static inline struct hfi1_ibport *to_iport(struct ib_device *ibdev, u8 port) |
1642 | { | |
1643 | struct hfi1_devdata *dd = dd_from_ibdev(ibdev); | |
1644 | unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */ | |
1645 | ||
1646 | WARN_ON(pidx >= dd->num_pports); | |
1647 | return &dd->pport[pidx].ibport_data; | |
1648 | } | |
1649 | ||
f3e862cb SS |
1650 | static inline struct hfi1_ibport *rcd_to_iport(struct hfi1_ctxtdata *rcd) |
1651 | { | |
1652 | return &rcd->ppd->ibport_data; | |
1653 | } | |
1654 | ||
5fd2b562 MH |
1655 | void hfi1_process_ecn_slowpath(struct rvt_qp *qp, struct hfi1_packet *pkt, |
1656 | bool do_cnp); | |
1657 | static inline bool process_ecn(struct rvt_qp *qp, struct hfi1_packet *pkt, | |
1658 | bool do_cnp) | |
1659 | { | |
261a4351 | 1660 | struct ib_other_headers *ohdr = pkt->ohdr; |
5fd2b562 MH |
1661 | u32 bth1; |
1662 | ||
1663 | bth1 = be32_to_cpu(ohdr->bth[1]); | |
3d591099 | 1664 | if (unlikely(bth1 & (IB_BECN_SMASK | IB_FECN_SMASK))) { |
5fd2b562 | 1665 | hfi1_process_ecn_slowpath(qp, pkt, do_cnp); |
4608e4c8 | 1666 | return !!(bth1 & IB_FECN_SMASK); |
5fd2b562 MH |
1667 | } |
1668 | return false; | |
1669 | } | |
1670 | ||
77241056 MM |
1671 | /* |
1672 | * Return the indexed PKEY from the port PKEY table. | |
1673 | */ | |
1674 | static inline u16 hfi1_get_pkey(struct hfi1_ibport *ibp, unsigned index) | |
1675 | { | |
1676 | struct hfi1_pportdata *ppd = ppd_from_ibp(ibp); | |
1677 | u16 ret; | |
1678 | ||
1679 | if (index >= ARRAY_SIZE(ppd->pkeys)) | |
1680 | ret = 0; | |
1681 | else | |
1682 | ret = ppd->pkeys[index]; | |
1683 | ||
1684 | return ret; | |
1685 | } | |
1686 | ||
a6cd5f08 JP |
1687 | /* |
1688 | * Return the indexed GUID from the port GUIDs table. | |
1689 | */ | |
1690 | static inline __be64 get_sguid(struct hfi1_ibport *ibp, unsigned int index) | |
1691 | { | |
1692 | struct hfi1_pportdata *ppd = ppd_from_ibp(ibp); | |
1693 | ||
1694 | WARN_ON(index >= HFI1_GUIDS_PER_PORT); | |
1695 | return cpu_to_be64(ppd->guids[index]); | |
1696 | } | |
1697 | ||
77241056 | 1698 | /* |
8adf71fa | 1699 | * Called by readers of cc_state only, must call under rcu_read_lock(). |
77241056 MM |
1700 | */ |
1701 | static inline struct cc_state *get_cc_state(struct hfi1_pportdata *ppd) | |
1702 | { | |
1703 | return rcu_dereference(ppd->cc_state); | |
1704 | } | |
1705 | ||
8adf71fa JX |
1706 | /* |
1707 | * Called by writers of cc_state only, must call under cc_state_lock. | |
1708 | */ | |
1709 | static inline | |
1710 | struct cc_state *get_cc_state_protected(struct hfi1_pportdata *ppd) | |
1711 | { | |
1712 | return rcu_dereference_protected(ppd->cc_state, | |
1713 | lockdep_is_held(&ppd->cc_state_lock)); | |
1714 | } | |
1715 | ||
77241056 MM |
1716 | /* |
1717 | * values for dd->flags (_device_ related flags) | |
1718 | */ | |
1719 | #define HFI1_INITTED 0x1 /* chip and driver up and initted */ | |
1720 | #define HFI1_PRESENT 0x2 /* chip accesses can be done */ | |
1721 | #define HFI1_FROZEN 0x4 /* chip in SPC freeze */ | |
1722 | #define HFI1_HAS_SDMA_TIMEOUT 0x8 | |
1723 | #define HFI1_HAS_SEND_DMA 0x10 /* Supports Send DMA */ | |
1724 | #define HFI1_FORCED_FREEZE 0x80 /* driver forced freeze mode */ | |
77241056 MM |
1725 | |
1726 | /* IB dword length mask in PBC (lower 11 bits); same for all chips */ | |
1727 | #define HFI1_PBC_LENGTH_MASK ((1 << 11) - 1) | |
1728 | ||
77241056 | 1729 | /* ctxt_flag bit offsets */ |
62239fc6 MR |
1730 | /* base context has not finished initializing */ |
1731 | #define HFI1_CTXT_BASE_UNINIT 1 | |
1732 | /* base context initaliation failed */ | |
1733 | #define HFI1_CTXT_BASE_FAILED 2 | |
77241056 | 1734 | /* waiting for a packet to arrive */ |
62239fc6 | 1735 | #define HFI1_CTXT_WAITING_RCV 3 |
77241056 | 1736 | /* waiting for an urgent packet to arrive */ |
62239fc6 | 1737 | #define HFI1_CTXT_WAITING_URG 4 |
77241056 MM |
1738 | |
1739 | /* free up any allocated data at closes */ | |
f4cd8765 MR |
1740 | struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev, |
1741 | const struct pci_device_id *ent); | |
1742 | void hfi1_free_devdata(struct hfi1_devdata *dd); | |
77241056 MM |
1743 | struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev, size_t extra); |
1744 | ||
2243472e EH |
1745 | /* LED beaconing functions */ |
1746 | void hfi1_start_led_override(struct hfi1_pportdata *ppd, unsigned int timeon, | |
1747 | unsigned int timeoff); | |
91ab4ed3 | 1748 | void shutdown_led_override(struct hfi1_pportdata *ppd); |
77241056 MM |
1749 | |
1750 | #define HFI1_CREDIT_RETURN_RATE (100) | |
1751 | ||
1752 | /* | |
1753 | * The number of words for the KDETH protocol field. If this is | |
1754 | * larger then the actual field used, then part of the payload | |
1755 | * will be in the header. | |
1756 | * | |
1757 | * Optimally, we want this sized so that a typical case will | |
1758 | * use full cache lines. The typical local KDETH header would | |
1759 | * be: | |
1760 | * | |
1761 | * Bytes Field | |
1762 | * 8 LRH | |
1763 | * 12 BHT | |
1764 | * ?? KDETH | |
1765 | * 8 RHF | |
1766 | * --- | |
1767 | * 28 + KDETH | |
1768 | * | |
1769 | * For a 64-byte cache line, KDETH would need to be 36 bytes or 9 DWORDS | |
1770 | */ | |
1771 | #define DEFAULT_RCVHDRSIZE 9 | |
1772 | ||
1773 | /* | |
1774 | * Maximal header byte count: | |
1775 | * | |
1776 | * Bytes Field | |
1777 | * 8 LRH | |
1778 | * 40 GRH (optional) | |
1779 | * 12 BTH | |
1780 | * ?? KDETH | |
1781 | * 8 RHF | |
1782 | * --- | |
1783 | * 68 + KDETH | |
1784 | * | |
1785 | * We also want to maintain a cache line alignment to assist DMA'ing | |
1786 | * of the header bytes. Round up to a good size. | |
1787 | */ | |
1788 | #define DEFAULT_RCVHDR_ENTSIZE 32 | |
1789 | ||
3faa3d9a IW |
1790 | bool hfi1_can_pin_pages(struct hfi1_devdata *dd, struct mm_struct *mm, |
1791 | u32 nlocked, u32 npages); | |
1792 | int hfi1_acquire_user_pages(struct mm_struct *mm, unsigned long vaddr, | |
1793 | size_t npages, bool writable, struct page **pages); | |
ac335e7e IW |
1794 | void hfi1_release_user_pages(struct mm_struct *mm, struct page **p, |
1795 | size_t npages, bool dirty); | |
77241056 MM |
1796 | |
1797 | static inline void clear_rcvhdrtail(const struct hfi1_ctxtdata *rcd) | |
1798 | { | |
50e5dcbe | 1799 | *((u64 *)rcd->rcvhdrtail_kvaddr) = 0ULL; |
77241056 MM |
1800 | } |
1801 | ||
1802 | static inline u32 get_rcvhdrtail(const struct hfi1_ctxtdata *rcd) | |
1803 | { | |
1804 | /* | |
1805 | * volatile because it's a DMA target from the chip, routine is | |
1806 | * inlined, and don't want register caching or reordering. | |
1807 | */ | |
50e5dcbe | 1808 | return (u32)le64_to_cpu(*rcd->rcvhdrtail_kvaddr); |
77241056 MM |
1809 | } |
1810 | ||
1811 | /* | |
1812 | * sysfs interface. | |
1813 | */ | |
1814 | ||
1815 | extern const char ib_hfi1_version[]; | |
1816 | ||
f4cd8765 MR |
1817 | int hfi1_device_create(struct hfi1_devdata *dd); |
1818 | void hfi1_device_remove(struct hfi1_devdata *dd); | |
77241056 MM |
1819 | |
1820 | int hfi1_create_port_files(struct ib_device *ibdev, u8 port_num, | |
1821 | struct kobject *kobj); | |
f4cd8765 MR |
1822 | int hfi1_verbs_register_sysfs(struct hfi1_devdata *dd); |
1823 | void hfi1_verbs_unregister_sysfs(struct hfi1_devdata *dd); | |
77241056 MM |
1824 | /* Hook for sysfs read of QSFP */ |
1825 | int qsfp_dump(struct hfi1_pportdata *ppd, char *buf, int len); | |
1826 | ||
f4cd8765 MR |
1827 | int hfi1_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent); |
1828 | void hfi1_pcie_cleanup(struct pci_dev *pdev); | |
1829 | int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev); | |
77241056 | 1830 | void hfi1_pcie_ddcleanup(struct hfi1_devdata *); |
f4cd8765 MR |
1831 | int pcie_speeds(struct hfi1_devdata *dd); |
1832 | void request_msix(struct hfi1_devdata *dd, u32 *nent, | |
1833 | struct hfi1_msix_entry *entry); | |
1834 | void hfi1_enable_intx(struct pci_dev *pdev); | |
77241056 MM |
1835 | void restore_pci_variables(struct hfi1_devdata *dd); |
1836 | int do_pcie_gen3_transition(struct hfi1_devdata *dd); | |
1837 | int parse_platform_config(struct hfi1_devdata *dd); | |
1838 | int get_platform_config_field(struct hfi1_devdata *dd, | |
17fb4f29 JJ |
1839 | enum platform_config_table_type_encoding |
1840 | table_type, int table_index, int field_index, | |
1841 | u32 *data, u32 len); | |
77241056 | 1842 | |
77241056 | 1843 | const char *get_unit_name(int unit); |
49dbb6cf DD |
1844 | const char *get_card_name(struct rvt_dev_info *rdi); |
1845 | struct pci_dev *get_pci_dev(struct rvt_dev_info *rdi); | |
77241056 MM |
1846 | |
1847 | /* | |
1848 | * Flush write combining store buffers (if present) and perform a write | |
1849 | * barrier. | |
1850 | */ | |
1851 | static inline void flush_wc(void) | |
1852 | { | |
1853 | asm volatile("sfence" : : : "memory"); | |
1854 | } | |
1855 | ||
1856 | void handle_eflags(struct hfi1_packet *packet); | |
1857 | int process_receive_ib(struct hfi1_packet *packet); | |
1858 | int process_receive_bypass(struct hfi1_packet *packet); | |
1859 | int process_receive_error(struct hfi1_packet *packet); | |
1860 | int kdeth_process_expected(struct hfi1_packet *packet); | |
1861 | int kdeth_process_eager(struct hfi1_packet *packet); | |
1862 | int process_receive_invalid(struct hfi1_packet *packet); | |
1863 | ||
77241056 MM |
1864 | /* global module parameter variables */ |
1865 | extern unsigned int hfi1_max_mtu; | |
1866 | extern unsigned int hfi1_cu; | |
1867 | extern unsigned int user_credit_return_threshold; | |
2ce6bf22 | 1868 | extern int num_user_contexts; |
429b6a72 | 1869 | extern unsigned long n_krcvqs; |
5b55ea3b | 1870 | extern uint krcvqs[]; |
77241056 MM |
1871 | extern int krcvqsset; |
1872 | extern uint kdeth_qp; | |
1873 | extern uint loopback; | |
1874 | extern uint quick_linkup; | |
1875 | extern uint rcv_intr_timeout; | |
1876 | extern uint rcv_intr_count; | |
1877 | extern uint rcv_intr_dynamic; | |
1878 | extern ushort link_crc_mask; | |
1879 | ||
1880 | extern struct mutex hfi1_mutex; | |
1881 | ||
1882 | /* Number of seconds before our card status check... */ | |
1883 | #define STATUS_TIMEOUT 60 | |
1884 | ||
1885 | #define DRIVER_NAME "hfi1" | |
1886 | #define HFI1_USER_MINOR_BASE 0 | |
1887 | #define HFI1_TRACE_MINOR 127 | |
77241056 MM |
1888 | #define HFI1_NMINORS 255 |
1889 | ||
1890 | #define PCI_VENDOR_ID_INTEL 0x8086 | |
1891 | #define PCI_DEVICE_ID_INTEL0 0x24f0 | |
1892 | #define PCI_DEVICE_ID_INTEL1 0x24f1 | |
1893 | ||
1894 | #define HFI1_PKT_USER_SC_INTEGRITY \ | |
1895 | (SEND_CTXT_CHECK_ENABLE_DISALLOW_NON_KDETH_PACKETS_SMASK \ | |
e38d1e4f | 1896 | | SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK \ |
77241056 MM |
1897 | | SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_SMASK \ |
1898 | | SEND_CTXT_CHECK_ENABLE_DISALLOW_GRH_SMASK) | |
1899 | ||
1900 | #define HFI1_PKT_KERNEL_SC_INTEGRITY \ | |
1901 | (SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK) | |
1902 | ||
1903 | static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd, | |
1904 | u16 ctxt_type) | |
1905 | { | |
d9ac4555 JP |
1906 | u64 base_sc_integrity; |
1907 | ||
1908 | /* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */ | |
1909 | if (HFI1_CAP_IS_KSET(NO_INTEGRITY)) | |
1910 | return 0; | |
1911 | ||
1912 | base_sc_integrity = | |
77241056 MM |
1913 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK |
1914 | | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK | |
1915 | | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK | |
1916 | | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK | |
1917 | | SEND_CTXT_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK | |
1918 | | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK | |
1919 | | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK | |
1920 | | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK | |
1921 | | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK | |
1922 | | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_SMASK | |
1923 | | SEND_CTXT_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK | |
1924 | | SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK | |
1925 | | SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK | |
1926 | | SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK | |
77241056 MM |
1927 | | SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK |
1928 | | SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK; | |
1929 | ||
1930 | if (ctxt_type == SC_USER) | |
1931 | base_sc_integrity |= HFI1_PKT_USER_SC_INTEGRITY; | |
1932 | else | |
1933 | base_sc_integrity |= HFI1_PKT_KERNEL_SC_INTEGRITY; | |
1934 | ||
d9ac4555 JP |
1935 | /* turn on send-side job key checks if !A0 */ |
1936 | if (!is_ax(dd)) | |
1937 | base_sc_integrity |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; | |
1938 | ||
77241056 MM |
1939 | return base_sc_integrity; |
1940 | } | |
1941 | ||
1942 | static inline u64 hfi1_pkt_base_sdma_integrity(struct hfi1_devdata *dd) | |
1943 | { | |
d9ac4555 JP |
1944 | u64 base_sdma_integrity; |
1945 | ||
1946 | /* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */ | |
1947 | if (HFI1_CAP_IS_KSET(NO_INTEGRITY)) | |
1948 | return 0; | |
1949 | ||
1950 | base_sdma_integrity = | |
77241056 | 1951 | SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK |
77241056 MM |
1952 | | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK |
1953 | | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK | |
1954 | | SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK | |
1955 | | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK | |
1956 | | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK | |
1957 | | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK | |
1958 | | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_SMASK | |
1959 | | SEND_DMA_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK | |
1960 | | SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK | |
1961 | | SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK | |
1962 | | SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK | |
77241056 MM |
1963 | | SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK |
1964 | | SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK; | |
1965 | ||
d9ac4555 JP |
1966 | if (!HFI1_CAP_IS_KSET(STATIC_RATE_CTRL)) |
1967 | base_sdma_integrity |= | |
1968 | SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK; | |
1969 | ||
1970 | /* turn on send-side job key checks if !A0 */ | |
1971 | if (!is_ax(dd)) | |
1972 | base_sdma_integrity |= | |
1973 | SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; | |
1974 | ||
77241056 MM |
1975 | return base_sdma_integrity; |
1976 | } | |
1977 | ||
1978 | /* | |
1979 | * hfi1_early_err is used (only!) to print early errors before devdata is | |
1980 | * allocated, or when dd->pcidev may not be valid, and at the tail end of | |
1981 | * cleanup when devdata may have been freed, etc. hfi1_dev_porterr is | |
1982 | * the same as dd_dev_err, but is used when the message really needs | |
1983 | * the IB port# to be definitive as to what's happening.. | |
1984 | */ | |
1985 | #define hfi1_early_err(dev, fmt, ...) \ | |
1986 | dev_err(dev, fmt, ##__VA_ARGS__) | |
1987 | ||
1988 | #define hfi1_early_info(dev, fmt, ...) \ | |
1989 | dev_info(dev, fmt, ##__VA_ARGS__) | |
1990 | ||
1991 | #define dd_dev_emerg(dd, fmt, ...) \ | |
1992 | dev_emerg(&(dd)->pcidev->dev, "%s: " fmt, \ | |
1993 | get_unit_name((dd)->unit), ##__VA_ARGS__) | |
1994 | #define dd_dev_err(dd, fmt, ...) \ | |
1995 | dev_err(&(dd)->pcidev->dev, "%s: " fmt, \ | |
1996 | get_unit_name((dd)->unit), ##__VA_ARGS__) | |
1997 | #define dd_dev_warn(dd, fmt, ...) \ | |
1998 | dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \ | |
1999 | get_unit_name((dd)->unit), ##__VA_ARGS__) | |
2000 | ||
2001 | #define dd_dev_warn_ratelimited(dd, fmt, ...) \ | |
2002 | dev_warn_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \ | |
2003 | get_unit_name((dd)->unit), ##__VA_ARGS__) | |
2004 | ||
2005 | #define dd_dev_info(dd, fmt, ...) \ | |
2006 | dev_info(&(dd)->pcidev->dev, "%s: " fmt, \ | |
2007 | get_unit_name((dd)->unit), ##__VA_ARGS__) | |
2008 | ||
c27aad00 JB |
2009 | #define dd_dev_info_ratelimited(dd, fmt, ...) \ |
2010 | dev_info_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \ | |
2011 | get_unit_name((dd)->unit), ##__VA_ARGS__) | |
2012 | ||
a1edc18a IW |
2013 | #define dd_dev_dbg(dd, fmt, ...) \ |
2014 | dev_dbg(&(dd)->pcidev->dev, "%s: " fmt, \ | |
2015 | get_unit_name((dd)->unit), ##__VA_ARGS__) | |
2016 | ||
77241056 | 2017 | #define hfi1_dev_porterr(dd, port, fmt, ...) \ |
cde10afa JP |
2018 | dev_err(&(dd)->pcidev->dev, "%s: port %u: " fmt, \ |
2019 | get_unit_name((dd)->unit), (port), ##__VA_ARGS__) | |
77241056 MM |
2020 | |
2021 | /* | |
2022 | * this is used for formatting hw error messages... | |
2023 | */ | |
2024 | struct hfi1_hwerror_msgs { | |
2025 | u64 mask; | |
2026 | const char *msg; | |
2027 | size_t sz; | |
2028 | }; | |
2029 | ||
2030 | /* in intr.c... */ | |
2031 | void hfi1_format_hwerrors(u64 hwerrs, | |
2032 | const struct hfi1_hwerror_msgs *hwerrmsgs, | |
2033 | size_t nhwerrmsgs, char *msg, size_t lmsg); | |
2034 | ||
2035 | #define USER_OPCODE_CHECK_VAL 0xC0 | |
2036 | #define USER_OPCODE_CHECK_MASK 0xC0 | |
2037 | #define OPCODE_CHECK_VAL_DISABLED 0x0 | |
2038 | #define OPCODE_CHECK_MASK_DISABLED 0x0 | |
2039 | ||
2040 | static inline void hfi1_reset_cpu_counters(struct hfi1_devdata *dd) | |
2041 | { | |
2042 | struct hfi1_pportdata *ppd; | |
2043 | int i; | |
2044 | ||
2045 | dd->z_int_counter = get_all_cpu_total(dd->int_counter); | |
2046 | dd->z_rcv_limit = get_all_cpu_total(dd->rcv_limit); | |
89abfc8d | 2047 | dd->z_send_schedule = get_all_cpu_total(dd->send_schedule); |
77241056 MM |
2048 | |
2049 | ppd = (struct hfi1_pportdata *)(dd + 1); | |
2050 | for (i = 0; i < dd->num_pports; i++, ppd++) { | |
4eb06882 DD |
2051 | ppd->ibport_data.rvp.z_rc_acks = |
2052 | get_all_cpu_total(ppd->ibport_data.rvp.rc_acks); | |
2053 | ppd->ibport_data.rvp.z_rc_qacks = | |
2054 | get_all_cpu_total(ppd->ibport_data.rvp.rc_qacks); | |
77241056 MM |
2055 | } |
2056 | } | |
2057 | ||
2058 | /* Control LED state */ | |
2059 | static inline void setextled(struct hfi1_devdata *dd, u32 on) | |
2060 | { | |
2061 | if (on) | |
2062 | write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F); | |
2063 | else | |
2064 | write_csr(dd, DCC_CFG_LED_CNTRL, 0x10); | |
2065 | } | |
2066 | ||
765a6fac DL |
2067 | /* return the i2c resource given the target */ |
2068 | static inline u32 i2c_target(u32 target) | |
2069 | { | |
2070 | return target ? CR_I2C2 : CR_I2C1; | |
2071 | } | |
2072 | ||
2073 | /* return the i2c chain chip resource that this HFI uses for QSFP */ | |
2074 | static inline u32 qsfp_resource(struct hfi1_devdata *dd) | |
2075 | { | |
2076 | return i2c_target(dd->hfi1_id); | |
2077 | } | |
2078 | ||
fe4d9243 EH |
2079 | /* Is this device integrated or discrete? */ |
2080 | static inline bool is_integrated(struct hfi1_devdata *dd) | |
2081 | { | |
2082 | return dd->pcidev->device == PCI_DEVICE_ID_INTEL1; | |
2083 | } | |
2084 | ||
77241056 MM |
2085 | int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp); |
2086 | ||
462b6b21 SS |
2087 | #define DD_DEV_ENTRY(dd) __string(dev, dev_name(&(dd)->pcidev->dev)) |
2088 | #define DD_DEV_ASSIGN(dd) __assign_str(dev, dev_name(&(dd)->pcidev->dev)) | |
2089 | ||
2090 | #define packettype_name(etype) { RHF_RCV_TYPE_##etype, #etype } | |
2091 | #define show_packettype(etype) \ | |
2092 | __print_symbolic(etype, \ | |
2093 | packettype_name(EXPECTED), \ | |
2094 | packettype_name(EAGER), \ | |
2095 | packettype_name(IB), \ | |
2096 | packettype_name(ERROR), \ | |
2097 | packettype_name(BYPASS)) | |
2098 | ||
2099 | #define ib_opcode_name(opcode) { IB_OPCODE_##opcode, #opcode } | |
2100 | #define show_ib_opcode(opcode) \ | |
2101 | __print_symbolic(opcode, \ | |
2102 | ib_opcode_name(RC_SEND_FIRST), \ | |
2103 | ib_opcode_name(RC_SEND_MIDDLE), \ | |
2104 | ib_opcode_name(RC_SEND_LAST), \ | |
2105 | ib_opcode_name(RC_SEND_LAST_WITH_IMMEDIATE), \ | |
2106 | ib_opcode_name(RC_SEND_ONLY), \ | |
2107 | ib_opcode_name(RC_SEND_ONLY_WITH_IMMEDIATE), \ | |
2108 | ib_opcode_name(RC_RDMA_WRITE_FIRST), \ | |
2109 | ib_opcode_name(RC_RDMA_WRITE_MIDDLE), \ | |
2110 | ib_opcode_name(RC_RDMA_WRITE_LAST), \ | |
2111 | ib_opcode_name(RC_RDMA_WRITE_LAST_WITH_IMMEDIATE), \ | |
2112 | ib_opcode_name(RC_RDMA_WRITE_ONLY), \ | |
2113 | ib_opcode_name(RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE), \ | |
2114 | ib_opcode_name(RC_RDMA_READ_REQUEST), \ | |
2115 | ib_opcode_name(RC_RDMA_READ_RESPONSE_FIRST), \ | |
2116 | ib_opcode_name(RC_RDMA_READ_RESPONSE_MIDDLE), \ | |
2117 | ib_opcode_name(RC_RDMA_READ_RESPONSE_LAST), \ | |
2118 | ib_opcode_name(RC_RDMA_READ_RESPONSE_ONLY), \ | |
2119 | ib_opcode_name(RC_ACKNOWLEDGE), \ | |
2120 | ib_opcode_name(RC_ATOMIC_ACKNOWLEDGE), \ | |
2121 | ib_opcode_name(RC_COMPARE_SWAP), \ | |
2122 | ib_opcode_name(RC_FETCH_ADD), \ | |
2123 | ib_opcode_name(UC_SEND_FIRST), \ | |
2124 | ib_opcode_name(UC_SEND_MIDDLE), \ | |
2125 | ib_opcode_name(UC_SEND_LAST), \ | |
2126 | ib_opcode_name(UC_SEND_LAST_WITH_IMMEDIATE), \ | |
2127 | ib_opcode_name(UC_SEND_ONLY), \ | |
2128 | ib_opcode_name(UC_SEND_ONLY_WITH_IMMEDIATE), \ | |
2129 | ib_opcode_name(UC_RDMA_WRITE_FIRST), \ | |
2130 | ib_opcode_name(UC_RDMA_WRITE_MIDDLE), \ | |
2131 | ib_opcode_name(UC_RDMA_WRITE_LAST), \ | |
2132 | ib_opcode_name(UC_RDMA_WRITE_LAST_WITH_IMMEDIATE), \ | |
2133 | ib_opcode_name(UC_RDMA_WRITE_ONLY), \ | |
2134 | ib_opcode_name(UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE), \ | |
2135 | ib_opcode_name(UD_SEND_ONLY), \ | |
2136 | ib_opcode_name(UD_SEND_ONLY_WITH_IMMEDIATE), \ | |
2137 | ib_opcode_name(CNP)) | |
77241056 | 2138 | #endif /* _HFI1_KERNEL_H */ |