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Merge tag 'asoc-v5.7' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / hfi1 / hfi.h
CommitLineData
77241056
MM		 1#ifndef _HFI1_KERNEL_H
2#define _HFI1_KERNEL_H
3/*
a74d5307 4 * Copyright(c) 2015-2018 Intel Corporation.
77241056
MM		 5 *
6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license.
8 *
9 * GPL LICENSE SUMMARY
10 *
77241056
MM		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * BSD LICENSE
21 *
77241056
MM		 22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions
24 * are met:
25 *
26 * - Redistributions of source code must retain the above copyright
27 * notice, this list of conditions and the following disclaimer.
28 * - Redistributions in binary form must reproduce the above copyright
29 * notice, this list of conditions and the following disclaimer in
30 * the documentation and/or other materials provided with the
31 * distribution.
32 * - Neither the name of Intel Corporation nor the names of its
33 * contributors may be used to endorse or promote products derived
34 * from this software without specific prior written permission.
35 *
36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
37 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
38 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
39 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
40 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
41 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
42 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
43 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
44 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
45 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
46 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
47 *
48 */
49
50#include <linux/interrupt.h>
51#include <linux/pci.h>
52#include <linux/dma-mapping.h>
53#include <linux/mutex.h>
54#include <linux/list.h>
55#include <linux/scatterlist.h>
56#include <linux/slab.h>
57#include <linux/io.h>
58#include <linux/fs.h>
59#include <linux/completion.h>
60#include <linux/kref.h>
61#include <linux/sched.h>
62#include <linux/cdev.h>
63#include <linux/delay.h>
64#include <linux/kthread.h>
dba715f0
DL		 65#include <linux/i2c.h>
66#include <linux/i2c-algo-bit.h>
03b92789 67#include <linux/xarray.h>
261a4351 68#include <rdma/ib_hdrs.h>
72c07e2b 69#include <rdma/opa_addr.h>
0cb2aa69 70#include <linux/rhashtable.h>
2280740f 71#include <linux/netdevice.h>
ec3f2c12 72#include <rdma/rdma_vt.h>
77241056
MM		 73
74#include "chip_registers.h"
75#include "common.h"
44e43d91 76#include "opfn.h"
77241056
MM		 77#include "verbs.h"
78#include "pio.h"
79#include "chip.h"
80#include "mad.h"
81#include "qsfp.h"
8ebd4cf1 82#include "platform.h"
957558c9 83#include "affinity.h"
09e71899 84#include "msix.h"
77241056
MM		 85
86/* bumped 1 from s/w major version of TrueScale */
87#define HFI1_CHIP_VERS_MAJ 3U
88
89/* don't care about this except printing */
90#define HFI1_CHIP_VERS_MIN 0U
91
92/* The Organization Unique Identifier (Mfg code), and its position in GUID */
93#define HFI1_OUI 0x001175
94#define HFI1_OUI_LSB 40
95
96#define DROP_PACKET_OFF 0
97#define DROP_PACKET_ON 1
98
641f348b
JS		 99#define NEIGHBOR_TYPE_HFI 0
100#define NEIGHBOR_TYPE_SWITCH 1
101
f01b4d5a
KW		 102#define HFI1_MAX_ACTIVE_WORKQUEUE_ENTRIES 5
103
77241056
MM		 104extern unsigned long hfi1_cap_mask;
105#define HFI1_CAP_KGET_MASK(mask, cap) ((mask) & HFI1_CAP_##cap)
106#define HFI1_CAP_UGET_MASK(mask, cap) \
107 (((mask) >> HFI1_CAP_USER_SHIFT) & HFI1_CAP_##cap)
108#define HFI1_CAP_KGET(cap) (HFI1_CAP_KGET_MASK(hfi1_cap_mask, cap))
109#define HFI1_CAP_UGET(cap) (HFI1_CAP_UGET_MASK(hfi1_cap_mask, cap))
110#define HFI1_CAP_IS_KSET(cap) (!!HFI1_CAP_KGET(cap))
111#define HFI1_CAP_IS_USET(cap) (!!HFI1_CAP_UGET(cap))
112#define HFI1_MISC_GET() ((hfi1_cap_mask >> HFI1_CAP_MISC_SHIFT) & \
113 HFI1_CAP_MISC_MASK)
a9c05e35
BM		 114/* Offline Disabled Reason is 4-bits */
115#define HFI1_ODR_MASK(rsn) ((rsn) & OPA_PI_MASK_OFFLINE_REASON)
77241056 116
82c2611d
NV		 117/*
118 * Control context is always 0 and handles the error packets.
119 * It also handles the VL15 and multicast packets.
120 */
121#define HFI1_CTRL_CTXT 0
122
2c5b521a
JR		 123/*
124 * Driver context will store software counters for each of the events
125 * associated with these status registers
126 */
127#define NUM_CCE_ERR_STATUS_COUNTERS 41
128#define NUM_RCV_ERR_STATUS_COUNTERS 64
129#define NUM_MISC_ERR_STATUS_COUNTERS 13
130#define NUM_SEND_PIO_ERR_STATUS_COUNTERS 36
131#define NUM_SEND_DMA_ERR_STATUS_COUNTERS 4
132#define NUM_SEND_EGRESS_ERR_STATUS_COUNTERS 64
133#define NUM_SEND_ERR_STATUS_COUNTERS 3
134#define NUM_SEND_CTXT_ERR_STATUS_COUNTERS 5
135#define NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS 24
136
77241056
MM		 137/*
138 * per driver stats, either not device nor port-specific, or
139 * summed over all of the devices and ports.
140 * They are described by name via ipathfs filesystem, so layout
141 * and number of elements can change without breaking compatibility.
142 * If members are added or deleted hfi1_statnames[] in debugfs.c must
143 * change to match.
144 */
145struct hfi1_ib_stats {
146 __u64 sps_ints; /* number of interrupts handled */
147 __u64 sps_errints; /* number of error interrupts */
148 __u64 sps_txerrs; /* tx-related packet errors */
149 __u64 sps_rcverrs; /* non-crc rcv packet errors */
150 __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */
151 __u64 sps_nopiobufs; /* no pio bufs avail from kernel */
152 __u64 sps_ctxts; /* number of contexts currently open */
153 __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */
154 __u64 sps_buffull;
155 __u64 sps_hdrfull;
156};
157
158extern struct hfi1_ib_stats hfi1_stats;
159extern const struct pci_error_handlers hfi1_pci_err_handler;
160
36d84219
PS		 161extern int num_driver_cntrs;
162
77241056
MM		 163/*
164 * First-cut criterion for "device is active" is
165 * two thousand dwords combined Tx, Rx traffic per
166 * 5-second interval. SMA packets are 64 dwords,
167 * and occur "a few per second", presumably each way.
168 */
169#define HFI1_TRAFFIC_ACTIVE_THRESHOLD (2000)
170
171/*
172 * Below contains all data related to a single context (formerly called port).
173 */
174
77241056 175struct hfi1_opcode_stats_perctx;
77241056 176
77241056 177struct ctxt_eager_bufs {
77241056
MM		 178 struct eager_buffer {
179 void *addr;
60368186 180 dma_addr_t dma;
77241056
MM		 181 ssize_t len;
182 } *buffers;
183 struct {
184 void *addr;
60368186 185 dma_addr_t dma;
77241056 186 } *rcvtids;
4b0b76bd
MM		 187 u32 size; /* total size of eager buffers */
188 u32 rcvtid_size; /* size of each eager rcv tid */
189 u16 count; /* size of buffers array */
190 u16 numbufs; /* number of buffers allocated */
191 u16 alloced; /* number of rcvarray entries used */
192 u16 threshold; /* head update threshold */
77241056
MM		 193};
194
a86cd357
MH		 195struct exp_tid_set {
196 struct list_head list;
197 u32 count;
198};
199
01c7fc50
MM		 200struct hfi1_ctxtdata;
201typedef int (*intr_handler)(struct hfi1_ctxtdata *rcd, int data);
d791d294 202typedef void (*rhf_rcv_function_ptr)(struct hfi1_packet *packet);
37356e78
KW		 203
204struct tid_queue {
205 struct list_head queue_head;
206 /* queue head for QP TID resource waiters */
207 u32 enqueue; /* count of tid enqueues */
208 u32 dequeue; /* count of tid dequeues */
209};
210
77241056 211struct hfi1_ctxtdata {
77241056
MM		 212 /* rcvhdrq base, needs mmap before useful */
213 void *rcvhdrq;
214 /* kernel virtual address where hdrqtail is updated */
215 volatile __le64 *rcvhdrtail_kvaddr;
071e4fec
MM		 216 /* so functions that need physical port can get it easily */
217 struct hfi1_pportdata *ppd;
218 /* so file ops can get at unit */
219 struct hfi1_devdata *dd;
220 /* this receive context's assigned PIO ACK send context */
221 struct send_context *sc;
222 /* per context recv functions */
223 const rhf_rcv_function_ptr *rhf_rcv_function_map;
224 /*
225 * The interrupt handler for a particular receive context can vary
226 * throughout it's lifetime. This is not a lock protected data member so
227 * it must be updated atomically and the prev and new value must always
228 * be valid. Worst case is we process an extra interrupt and up to 64
229 * packets with the wrong interrupt handler.
230 */
01c7fc50
MM		 231 intr_handler do_interrupt;
232 /** fast handler after autoactive */
233 intr_handler fast_handler;
234 /** slow handler */
235 intr_handler slow_handler;
071e4fec
MM		 236 /* verbs rx_stats per rcd */
237 struct hfi1_opcode_stats_perctx *opstats;
238 /* clear interrupt mask */
239 u64 imask;
240 /* ctxt rcvhdrq head offset */
241 u32 head;
77241056
MM		 242 /* number of rcvhdrq entries */
243 u16 rcvhdrq_cnt;
071e4fec
MM		 244 u8 ireg; /* clear interrupt register */
245 /* receive packet sequence counter */
246 u8 seq_cnt;
77241056 247 /* size of each of the rcvhdrq entries */
40442b30
MM		 248 u8 rcvhdrqentsize;
249 /* offset of RHF within receive header entry */
250 u8 rhf_offset;
071e4fec
MM		 251 /* dynamic receive available interrupt timeout */
252 u8 rcvavail_timeout;
253 /* Indicates that this is vnic context */
254 bool is_vnic;
255 /* vnic queue index this context is mapped to */
256 u8 vnic_q_idx;
257 /* Is ASPM interrupt supported for this context */
258 bool aspm_intr_supported;
259 /* ASPM state (enabled/disabled) for this context */
260 bool aspm_enabled;
261 /* Is ASPM processing enabled for this context (in intr context) */
262 bool aspm_intr_enable;
263 struct ctxt_eager_bufs egrbufs;
264 /* QPs waiting for context processing */
265 struct list_head qp_wait_list;
266 /* tid allocation lists */
267 struct exp_tid_set tid_group_list;
268 struct exp_tid_set tid_used_list;
269 struct exp_tid_set tid_full_list;
270
271 /* Timer for re-enabling ASPM if interrupt activity quiets down */
272 struct timer_list aspm_timer;
273 /* per-context configuration flags */
274 unsigned long flags;
275 /* array of tid_groups */
276 struct tid_group *groups;
77241056 277 /* mmap of hdrq, must fit in 44 bits */
60368186
TK		 278 dma_addr_t rcvhdrq_dma;
279 dma_addr_t rcvhdrqtailaddr_dma;
071e4fec
MM		 280 /* Last interrupt timestamp */
281 ktime_t aspm_ts_last_intr;
282 /* Last timestamp at which we scheduled a timer for this context */
283 ktime_t aspm_ts_timer_sched;
284 /* Lock to serialize between intr, timer intr and user threads */
285 spinlock_t aspm_lock;
f683c80c
MR		 286 /* Reference count the base context usage */
287 struct kref kref;
071e4fec
MM		 288 /* numa node of this context */
289 int numa_id;
290 /* associated msix interrupt. */
291 s16 msix_intr;
77241056
MM		 292 /* job key */
293 u16 jkey;
294 /* number of RcvArray groups for this context. */
c8314811 295 u16 rcv_array_groups;
77241056 296 /* index of first eager TID entry. */
c8314811 297 u16 eager_base;
77241056 298 /* number of expected TID entries */
c8314811 299 u16 expected_count;
77241056 300 /* index of first expected TID entry. */
c8314811 301 u16 expected_base;
071e4fec
MM		 302 /* Device context index */
303 u8 ctxt;
a86cd357 304
071e4fec
MM		 305 /* PSM Specific fields */
306 /* lock protecting all Expected TID data */
ed71e86a 307 struct mutex exp_mutex;
37356e78
KW		 308 /* lock protecting all Expected TID data of kernel contexts */
309 spinlock_t exp_lock;
310 /* Queue for QP's waiting for HW TID flows */
311 struct tid_queue flow_queue;
838b6fd2
KW		 312 /* Queue for QP's waiting for HW receive array entries */
313 struct tid_queue rarr_queue;
071e4fec
MM		 314 /* when waiting for rcv or pioavail */
315 wait_queue_head_t wait;
316 /* uuid from PSM */
317 u8 uuid[16];
77241056 318 /* same size as task_struct .comm[], command that opened context */
c3af8a28 319 char comm[TASK_COMM_LEN];
071e4fec
MM		 320 /* Bitmask of in use context(s) */
321 DECLARE_BITMAP(in_use_ctxts, HFI1_MAX_SHARED_CTXTS);
322 /* per-context event flags for fileops/intr communication */
323 unsigned long event_flags;
77241056
MM		 324 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */
325 void *subctxt_uregbase;
326 /* An array of pages for the eager receive buffers * N */
327 void *subctxt_rcvegrbuf;
328 /* An array of pages for the eager header queue entries * N */
329 void *subctxt_rcvhdr_base;
071e4fec
MM		 330 /* total number of polled urgent packets */
331 u32 urgent;
332 /* saved total number of polled urgent packets for poll edge trigger */
333 u32 urgent_poll;
77241056
MM		 334 /* Type of packets or conditions we want to poll for */
335 u16 poll_type;
071e4fec
MM		 336 /* non-zero if ctxt is being shared. */
337 u16 subctxt_id;
338 /* The version of the library which opened this ctxt */
339 u32 userversion;
77241056 340 /*
071e4fec
MM		 341 * non-zero if ctxt can be shared, and defines the maximum number of
342 * sub-contexts for this device context.
77241056 343 */
071e4fec 344 u8 subctxt_cnt;
d4829ea6 345
37356e78
KW		 346 /* Bit mask to track free TID RDMA HW flows */
347 unsigned long flow_mask;
348 struct tid_flow_state flows[RXE_NUM_TID_FLOWS];
77241056
MM		 349};
350
b2578431
MM		 351/**
352 * rcvhdrq_size - return total size in bytes for header queue
353 * @rcd: the receive context
354 *
355 * rcvhdrqentsize is in DWs, so we have to convert to bytes
356 *
357 */
358static inline u32 rcvhdrq_size(struct hfi1_ctxtdata *rcd)
359{
360 return PAGE_ALIGN(rcd->rcvhdrq_cnt *
361 rcd->rcvhdrqentsize * sizeof(u32));
362}
363
77241056
MM		 364/*
365 * Represents a single packet at a high level. Put commonly computed things in
366 * here so we do not have to keep doing them over and over. The rule of thumb is
367 * if something is used one time to derive some value, store that something in
368 * here. If it is used multiple times, then store the result of that derivation
369 * in here.
370 */
371struct hfi1_packet {
372 void *ebuf;
373 void *hdr;
72c07e2b 374 void *payload;
77241056
MM		 375 struct hfi1_ctxtdata *rcd;
376 __le32 *rhf_addr;
895420dd 377 struct rvt_qp *qp;
261a4351 378 struct ib_other_headers *ohdr;
9039746c 379 struct ib_grh *grh;
81cd3891 380 struct opa_16b_mgmt *mgmt;
77241056
MM		 381 u64 rhf;
382 u32 maxcnt;
383 u32 rhqoff;
9039746c
DH		 384 u32 dlid;
385 u32 slid;
77241056 386 u16 tlen;
77241056 387 s16 etail;
6d6b8848 388 u16 pkey;
76327627
SS		 389 u8 hlen;
390 u8 numpkt;
391 u8 rsize;
77241056 392 u8 updegr;
77241056 393 u8 etype;
9039746c
DH		 394 u8 extra_byte;
395 u8 pad;
396 u8 sc;
397 u8 sl;
398 u8 opcode;
6d6b8848 399 bool migrated;
77241056
MM		 400};
401
d98bb7f7
DH		 402/* Packet types */
403#define HFI1_PKT_TYPE_9B 0
404#define HFI1_PKT_TYPE_16B 1
405
72c07e2b
DH		 406/*
407 * OPA 16B Header
408 */
409#define OPA_16B_L4_MASK 0xFFull
410#define OPA_16B_SC_MASK 0x1F00000ull
411#define OPA_16B_SC_SHIFT 20
412#define OPA_16B_LID_MASK 0xFFFFFull
413#define OPA_16B_DLID_MASK 0xF000ull
414#define OPA_16B_DLID_SHIFT 20
415#define OPA_16B_DLID_HIGH_SHIFT 12
416#define OPA_16B_SLID_MASK 0xF00ull
417#define OPA_16B_SLID_SHIFT 20
418#define OPA_16B_SLID_HIGH_SHIFT 8
419#define OPA_16B_BECN_MASK 0x80000000ull
420#define OPA_16B_BECN_SHIFT 31
421#define OPA_16B_FECN_MASK 0x10000000ull
422#define OPA_16B_FECN_SHIFT 28
423#define OPA_16B_L2_MASK 0x60000000ull
424#define OPA_16B_L2_SHIFT 29
5786adf3
DH		 425#define OPA_16B_PKEY_MASK 0xFFFF0000ull
426#define OPA_16B_PKEY_SHIFT 16
427#define OPA_16B_LEN_MASK 0x7FF00000ull
428#define OPA_16B_LEN_SHIFT 20
863cf89d
DH		 429#define OPA_16B_RC_MASK 0xE000000ull
430#define OPA_16B_RC_SHIFT 25
431#define OPA_16B_AGE_MASK 0xFF0000ull
432#define OPA_16B_AGE_SHIFT 16
433#define OPA_16B_ENTROPY_MASK 0xFFFFull
72c07e2b
DH		 434
435/*
436 * OPA 16B L2/L4 Encodings
437 */
e08aa594 438#define OPA_16B_L4_9B 0x00
72c07e2b 439#define OPA_16B_L2_TYPE 0x02
4171a693 440#define OPA_16B_L4_FM 0x08
72c07e2b
DH		 441#define OPA_16B_L4_IB_LOCAL 0x09
442#define OPA_16B_L4_IB_GLOBAL 0x0A
443#define OPA_16B_L4_ETHR OPA_VNIC_L4_ETHR
444
81cd3891
DH		 445/*
446 * OPA 16B Management
447 */
448#define OPA_16B_L4_FM_PAD 3 /* fixed 3B pad */
449#define OPA_16B_L4_FM_HLEN 24 /* 16B(16) + L4_FM(8) */
450
72c07e2b
DH		 451static inline u8 hfi1_16B_get_l4(struct hfi1_16b_header *hdr)
452{
453 return (u8)(hdr->lrh[2] & OPA_16B_L4_MASK);
454}
455
456static inline u8 hfi1_16B_get_sc(struct hfi1_16b_header *hdr)
457{
458 return (u8)((hdr->lrh[1] & OPA_16B_SC_MASK) >> OPA_16B_SC_SHIFT);
459}
460
461static inline u32 hfi1_16B_get_dlid(struct hfi1_16b_header *hdr)
462{
463 return (u32)((hdr->lrh[1] & OPA_16B_LID_MASK) |
464 (((hdr->lrh[2] & OPA_16B_DLID_MASK) >>
465 OPA_16B_DLID_HIGH_SHIFT) << OPA_16B_DLID_SHIFT));
466}
467
468static inline u32 hfi1_16B_get_slid(struct hfi1_16b_header *hdr)
469{
470 return (u32)((hdr->lrh[0] & OPA_16B_LID_MASK) |
471 (((hdr->lrh[2] & OPA_16B_SLID_MASK) >>
472 OPA_16B_SLID_HIGH_SHIFT) << OPA_16B_SLID_SHIFT));
473}
474
475static inline u8 hfi1_16B_get_becn(struct hfi1_16b_header *hdr)
476{
477 return (u8)((hdr->lrh[0] & OPA_16B_BECN_MASK) >> OPA_16B_BECN_SHIFT);
478}
479
480static inline u8 hfi1_16B_get_fecn(struct hfi1_16b_header *hdr)
481{
482 return (u8)((hdr->lrh[1] & OPA_16B_FECN_MASK) >> OPA_16B_FECN_SHIFT);
483}
484
485static inline u8 hfi1_16B_get_l2(struct hfi1_16b_header *hdr)
486{
487 return (u8)((hdr->lrh[1] & OPA_16B_L2_MASK) >> OPA_16B_L2_SHIFT);
488}
489
5786adf3
DH		 490static inline u16 hfi1_16B_get_pkey(struct hfi1_16b_header *hdr)
491{
492 return (u16)((hdr->lrh[2] & OPA_16B_PKEY_MASK) >> OPA_16B_PKEY_SHIFT);
493}
494
863cf89d
DH		 495static inline u8 hfi1_16B_get_rc(struct hfi1_16b_header *hdr)
496{
497 return (u8)((hdr->lrh[1] & OPA_16B_RC_MASK) >> OPA_16B_RC_SHIFT);
498}
499
500static inline u8 hfi1_16B_get_age(struct hfi1_16b_header *hdr)
501{
502 return (u8)((hdr->lrh[3] & OPA_16B_AGE_MASK) >> OPA_16B_AGE_SHIFT);
503}
504
505static inline u16 hfi1_16B_get_len(struct hfi1_16b_header *hdr)
506{
507 return (u16)((hdr->lrh[0] & OPA_16B_LEN_MASK) >> OPA_16B_LEN_SHIFT);
508}
509
510static inline u16 hfi1_16B_get_entropy(struct hfi1_16b_header *hdr)
511{
512 return (u16)(hdr->lrh[3] & OPA_16B_ENTROPY_MASK);
513}
514
5b6cabb0
DH		 515#define OPA_16B_MAKE_QW(low_dw, high_dw) (((u64)(high_dw) << 32) | (low_dw))
516
72c07e2b
DH		 517/*
518 * BTH
519 */
520#define OPA_16B_BTH_PAD_MASK 7
521static inline u8 hfi1_16B_bth_get_pad(struct ib_other_headers *ohdr)
522{
523 return (u8)((be32_to_cpu(ohdr->bth[0]) >> IB_BTH_PAD_SHIFT) &
524 OPA_16B_BTH_PAD_MASK);
525}
526
81cd3891
DH		 527/*
528 * 16B Management
529 */
530#define OPA_16B_MGMT_QPN_MASK 0xFFFFFF
531static inline u32 hfi1_16B_get_dest_qpn(struct opa_16b_mgmt *mgmt)
532{
533 return be32_to_cpu(mgmt->dest_qpn) & OPA_16B_MGMT_QPN_MASK;
534}
535
536static inline u32 hfi1_16B_get_src_qpn(struct opa_16b_mgmt *mgmt)
537{
538 return be32_to_cpu(mgmt->src_qpn) & OPA_16B_MGMT_QPN_MASK;
539}
540
541static inline void hfi1_16B_set_qpn(struct opa_16b_mgmt *mgmt,
542 u32 dest_qp, u32 src_qp)
543{
544 mgmt->dest_qpn = cpu_to_be32(dest_qp & OPA_16B_MGMT_QPN_MASK);
545 mgmt->src_qpn = cpu_to_be32(src_qp & OPA_16B_MGMT_QPN_MASK);
546}
547
9755f724
MM		 548/**
549 * hfi1_get_rc_ohdr - get extended header
550 * @opah - the opaheader
551 */
552static inline struct ib_other_headers *
553hfi1_get_rc_ohdr(struct hfi1_opa_header *opah)
554{
555 struct ib_other_headers *ohdr;
556 struct ib_header *hdr = NULL;
557 struct hfi1_16b_header *hdr_16b = NULL;
558
559 /* Find out where the BTH is */
560 if (opah->hdr_type == HFI1_PKT_TYPE_9B) {
561 hdr = &opah->ibh;
562 if (ib_get_lnh(hdr) == HFI1_LRH_BTH)
563 ohdr = &hdr->u.oth;
564 else
565 ohdr = &hdr->u.l.oth;
566 } else {
567 u8 l4;
568
569 hdr_16b = &opah->opah;
570 l4 = hfi1_16B_get_l4(hdr_16b);
571 if (l4 == OPA_16B_L4_IB_LOCAL)
572 ohdr = &hdr_16b->u.oth;
573 else
574 ohdr = &hdr_16b->u.l.oth;
575 }
576 return ohdr;
577}
578
895420dd 579struct rvt_sge_state;
77241056
MM		 580
581/*
582 * Get/Set IB link-level config parameters for f_get/set_ib_cfg()
583 * Mostly for MADs that set or query link parameters, also ipath
584 * config interfaces
585 */
586#define HFI1_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */
587#define HFI1_IB_CFG_LWID_DG_ENB 1 /* allowed Link-width downgrade */
588#define HFI1_IB_CFG_LWID_ENB 2 /* allowed Link-width */
589#define HFI1_IB_CFG_LWID 3 /* currently active Link-width */
590#define HFI1_IB_CFG_SPD_ENB 4 /* allowed Link speeds */
591#define HFI1_IB_CFG_SPD 5 /* current Link spd */
592#define HFI1_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */
593#define HFI1_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */
594#define HFI1_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */
595#define HFI1_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */
596#define HFI1_IB_CFG_OP_VLS 10 /* operational VLs */
597#define HFI1_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */
598#define HFI1_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */
599#define HFI1_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */
600#define HFI1_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */
601#define HFI1_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */
602#define HFI1_IB_CFG_PKEYS 16 /* update partition keys */
603#define HFI1_IB_CFG_MTU 17 /* update MTU in IBC */
604#define HFI1_IB_CFG_VL_HIGH_LIMIT 19
605#define HFI1_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */
606#define HFI1_IB_CFG_PORT 21 /* switch port we are connected to */
607
608/*
609 * HFI or Host Link States
610 *
611 * These describe the states the driver thinks the logical and physical
612 * states are in. Used as an argument to set_link_state(). Implemented
613 * as bits for easy multi-state checking. The actual state can only be
614 * one.
615 */
616#define __HLS_UP_INIT_BP 0
617#define __HLS_UP_ARMED_BP 1
618#define __HLS_UP_ACTIVE_BP 2
619#define __HLS_DN_DOWNDEF_BP 3 /* link down default */
620#define __HLS_DN_POLL_BP 4
621#define __HLS_DN_DISABLE_BP 5
622#define __HLS_DN_OFFLINE_BP 6
623#define __HLS_VERIFY_CAP_BP 7
624#define __HLS_GOING_UP_BP 8
625#define __HLS_GOING_OFFLINE_BP 9
626#define __HLS_LINK_COOLDOWN_BP 10
627
349ac71f 628#define HLS_UP_INIT BIT(__HLS_UP_INIT_BP)
629#define HLS_UP_ARMED BIT(__HLS_UP_ARMED_BP)
630#define HLS_UP_ACTIVE BIT(__HLS_UP_ACTIVE_BP)
631#define HLS_DN_DOWNDEF BIT(__HLS_DN_DOWNDEF_BP) /* link down default */
632#define HLS_DN_POLL BIT(__HLS_DN_POLL_BP)
633#define HLS_DN_DISABLE BIT(__HLS_DN_DISABLE_BP)
634#define HLS_DN_OFFLINE BIT(__HLS_DN_OFFLINE_BP)
635#define HLS_VERIFY_CAP BIT(__HLS_VERIFY_CAP_BP)
636#define HLS_GOING_UP BIT(__HLS_GOING_UP_BP)
637#define HLS_GOING_OFFLINE BIT(__HLS_GOING_OFFLINE_BP)
638#define HLS_LINK_COOLDOWN BIT(__HLS_LINK_COOLDOWN_BP)
77241056
MM		 639
640#define HLS_UP (HLS_UP_INIT | HLS_UP_ARMED | HLS_UP_ACTIVE)
0c7f77af 641#define HLS_DOWN ~(HLS_UP)
77241056 642
156d24d7
IW		 643#define HLS_DEFAULT HLS_DN_POLL
644
77241056 645/* use this MTU size if none other is given */
ef699e84 646#define HFI1_DEFAULT_ACTIVE_MTU 10240
77241056 647/* use this MTU size as the default maximum */
ef699e84 648#define HFI1_DEFAULT_MAX_MTU 10240
77241056
MM		 649/* default partition key */
650#define DEFAULT_PKEY 0xffff
651
652/*
653 * Possible fabric manager config parameters for fm_{get,set}_table()
654 */
655#define FM_TBL_VL_HIGH_ARB 1 /* Get/set VL high prio weights */
656#define FM_TBL_VL_LOW_ARB 2 /* Get/set VL low prio weights */
657#define FM_TBL_BUFFER_CONTROL 3 /* Get/set Buffer Control */
658#define FM_TBL_SC2VLNT 4 /* Get/set SC->VLnt */
659#define FM_TBL_VL_PREEMPT_ELEMS 5 /* Get (no set) VL preempt elems */
660#define FM_TBL_VL_PREEMPT_MATRIX 6 /* Get (no set) VL preempt matrix */
661
662/*
663 * Possible "operations" for f_rcvctrl(ppd, op, ctxt)
664 * these are bits so they can be combined, e.g.
665 * HFI1_RCVCTRL_INTRAVAIL_ENB | HFI1_RCVCTRL_CTXT_ENB
666 */
667#define HFI1_RCVCTRL_TAILUPD_ENB 0x01
668#define HFI1_RCVCTRL_TAILUPD_DIS 0x02
669#define HFI1_RCVCTRL_CTXT_ENB 0x04
670#define HFI1_RCVCTRL_CTXT_DIS 0x08
671#define HFI1_RCVCTRL_INTRAVAIL_ENB 0x10
672#define HFI1_RCVCTRL_INTRAVAIL_DIS 0x20
673#define HFI1_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */
674#define HFI1_RCVCTRL_PKEY_DIS 0x80
675#define HFI1_RCVCTRL_TIDFLOW_ENB 0x0400
676#define HFI1_RCVCTRL_TIDFLOW_DIS 0x0800
677#define HFI1_RCVCTRL_ONE_PKT_EGR_ENB 0x1000
678#define HFI1_RCVCTRL_ONE_PKT_EGR_DIS 0x2000
679#define HFI1_RCVCTRL_NO_RHQ_DROP_ENB 0x4000
680#define HFI1_RCVCTRL_NO_RHQ_DROP_DIS 0x8000
681#define HFI1_RCVCTRL_NO_EGR_DROP_ENB 0x10000
682#define HFI1_RCVCTRL_NO_EGR_DROP_DIS 0x20000
dc9f5d0f
MR		 683#define HFI1_RCVCTRL_URGENT_ENB 0x40000
684#define HFI1_RCVCTRL_URGENT_DIS 0x80000
77241056
MM		 685
686/* partition enforcement flags */
687#define HFI1_PART_ENFORCE_IN 0x1
688#define HFI1_PART_ENFORCE_OUT 0x2
689
690/* how often we check for synthetic counter wrap around */
22546b74 691#define SYNTH_CNT_TIME 3
77241056
MM		 692
693/* Counter flags */
694#define CNTR_NORMAL 0x0 /* Normal counters, just read register */
695#define CNTR_SYNTH 0x1 /* Synthetic counters, saturate at all 1s */
696#define CNTR_DISABLED 0x2 /* Disable this counter */
697#define CNTR_32BIT 0x4 /* Simulate 64 bits for this counter */
698#define CNTR_VL 0x8 /* Per VL counter */
a699c6c2 699#define CNTR_SDMA 0x10
77241056
MM		 700#define CNTR_INVALID_VL -1 /* Specifies invalid VL */
701#define CNTR_MODE_W 0x0
702#define CNTR_MODE_R 0x1
703
704/* VLs Supported/Operational */
705#define HFI1_MIN_VLS_SUPPORTED 1
706#define HFI1_MAX_VLS_SUPPORTED 8
707
a6cd5f08
JP		 708#define HFI1_GUIDS_PER_PORT 5
709#define HFI1_PORT_GUID_INDEX 0
710
77241056
MM		 711static inline void incr_cntr64(u64 *cntr)
712{
713 if (*cntr < (u64)-1LL)
714 (*cntr)++;
715}
716
717static inline void incr_cntr32(u32 *cntr)
718{
719 if (*cntr < (u32)-1LL)
720 (*cntr)++;
721}
722
723#define MAX_NAME_SIZE 64
724struct hfi1_msix_entry {
957558c9 725 enum irq_type type;
bb7dde87 726 int irq;
77241056 727 void *arg;
957558c9 728 cpumask_t mask;
2d01c37d 729 struct irq_affinity_notify notify;
77241056
MM		 730};
731
6eb4eb10
MR		 732struct hfi1_msix_info {
733 /* lock to synchronize in_use_msix access */
734 spinlock_t msix_lock;
735 DECLARE_BITMAP(in_use_msix, CCE_NUM_MSIX_VECTORS);
736 struct hfi1_msix_entry *msix_entries;
737 u16 max_requested;
738};
739
77241056
MM		 740/* per-SL CCA information */
741struct cca_timer {
742 struct hrtimer hrtimer;
743 struct hfi1_pportdata *ppd; /* read-only */
744 int sl; /* read-only */
745 u16 ccti; /* read/write - current value of CCTI */
746};
747
748struct link_down_reason {
749 /*
750 * SMA-facing value. Should be set from .latest when
751 * HLS_UP_* -> HLS_DN_* transition actually occurs.
752 */
753 u8 sma;
754 u8 latest;
755};
756
757enum {
758 LO_PRIO_TABLE,
759 HI_PRIO_TABLE,
760 MAX_PRIO_TABLE
761};
762
763struct vl_arb_cache {
6a14c5ea 764 /* protect vl arb cache */
77241056
MM		 765 spinlock_t lock;
766 struct ib_vl_weight_elem table[VL_ARB_TABLE_SIZE];
767};
768
769/*
770 * The structure below encapsulates data relevant to a physical IB Port.
771 * Current chips support only one such port, but the separation
772 * clarifies things a bit. Note that to conform to IB conventions,
773 * port-numbers are one-based. The first or only port is port1.
774 */
775struct hfi1_pportdata {
776 struct hfi1_ibport ibport_data;
777
778 struct hfi1_devdata *dd;
779 struct kobject pport_cc_kobj;
780 struct kobject sc2vl_kobj;
781 struct kobject sl2sc_kobj;
782 struct kobject vl2mtu_kobj;
783
8ebd4cf1 784 /* PHY support */
77241056 785 struct qsfp_data qsfp_info;
fe4d9243
EH		 786 /* Values for SI tuning of SerDes */
787 u32 port_type;
788 u32 tx_preset_eq;
789 u32 tx_preset_noeq;
790 u32 rx_preset;
791 u8 local_atten;
792 u8 remote_atten;
793 u8 default_atten;
794 u8 max_power_class;
77241056 795
91618604
JB		 796 /* did we read platform config from scratch registers? */
797 bool config_from_scratch;
798
a6cd5f08
JP		 799 /* GUIDs for this interface, in host order, guids[0] is a port guid */
800 u64 guids[HFI1_GUIDS_PER_PORT];
77241056 801
77241056
MM		 802 /* GUID for peer interface, in host order */
803 u64 neighbor_guid;
804
805 /* up or down physical link state */
806 u32 linkup;
807
808 /*
809 * this address is mapped read-only into user processes so they can
810 * get status cheaply, whenever they want. One qword of status per port
811 */
812 u64 *statusp;
813
814 /* SendDMA related entries */
815
816 struct workqueue_struct *hfi1_wq;
71d47008 817 struct workqueue_struct *link_wq;
77241056
MM		 818
819 /* move out of interrupt context */
820 struct work_struct link_vc_work;
821 struct work_struct link_up_work;
822 struct work_struct link_down_work;
823 struct work_struct sma_message_work;
824 struct work_struct freeze_work;
825 struct work_struct link_downgrade_work;
826 struct work_struct link_bounce_work;
673b975f 827 struct delayed_work start_link_work;
77241056
MM		 828 /* host link state variables */
829 struct mutex hls_lock;
830 u32 host_link_state;
831
77241056
MM		 832 /* these are the "32 bit" regs */
833
834 u32 ibmtu; /* The MTU programmed for this unit */
835 /*
836 * Current max size IB packet (in bytes) including IB headers, that
837 * we can send. Changes when ibmtu changes.
838 */
839 u32 ibmaxlen;
840 u32 current_egress_rate; /* units [10^6 bits/sec] */
841 /* LID programmed for this instance */
51e658f5 842 u32 lid;
77241056
MM		 843 /* list of pkeys programmed; 0 if not set */
844 u16 pkeys[MAX_PKEY_VALUES];
845 u16 link_width_supported;
846 u16 link_width_downgrade_supported;
847 u16 link_speed_supported;
848 u16 link_width_enabled;
849 u16 link_width_downgrade_enabled;
850 u16 link_speed_enabled;
851 u16 link_width_active;
852 u16 link_width_downgrade_tx_active;
853 u16 link_width_downgrade_rx_active;
854 u16 link_speed_active;
855 u8 vls_supported;
856 u8 vls_operational;
8a4d3444 857 u8 actual_vls_operational;
77241056
MM		 858 /* LID mask control */
859 u8 lmc;
860 /* Rx Polarity inversion (compensate for ~tx on partner) */
861 u8 rx_pol_inv;
862
863 u8 hw_pidx; /* physical port index */
864 u8 port; /* IB port number and index into dd->pports - 1 */
865 /* type of neighbor node */
866 u8 neighbor_type;
867 u8 neighbor_normal;
868 u8 neighbor_fm_security; /* 1 if firmware checking is disabled */
869 u8 neighbor_port_number;
870 u8 is_sm_config_started;
871 u8 offline_disabled_reason;
872 u8 is_active_optimize_enabled;
873 u8 driver_link_ready; /* driver ready for active link */
874 u8 link_enabled; /* link enabled? */
875 u8 linkinit_reason;
876 u8 local_tx_rate; /* rate given to 8051 firmware */
673b975f 877 u8 qsfp_retry_count;
77241056
MM		 878
879 /* placeholders for IB MAD packet settings */
880 u8 overrun_threshold;
881 u8 phy_error_threshold;
626c077c 882 unsigned int is_link_down_queued;
77241056 883
91ab4ed3
EH		 884 /* Used to override LED behavior for things like maintenance beaconing*/
885 /*
886 * Alternates per phase of blink
887 * [0] holds LED off duration, [1] holds LED on duration
888 */
889 unsigned long led_override_vals[2];
890 u8 led_override_phase; /* LSB picks from vals[] */
77241056
MM		 891 atomic_t led_override_timer_active;
892 /* Used to flash LEDs in override mode */
893 struct timer_list led_override_timer;
91ab4ed3 894
77241056
MM		 895 u32 sm_trap_qp;
896 u32 sa_qp;
897
898 /*
899 * cca_timer_lock protects access to the per-SL cca_timer
900 * structures (specifically the ccti member).
901 */
902 spinlock_t cca_timer_lock ____cacheline_aligned_in_smp;
903 struct cca_timer cca_timer[OPA_MAX_SLS];
904
905 /* List of congestion control table entries */
906 struct ib_cc_table_entry_shadow ccti_entries[CC_TABLE_SHADOW_MAX];
907
908 /* congestion entries, each entry corresponding to a SL */
909 struct opa_congestion_setting_entry_shadow
910 congestion_entries[OPA_MAX_SLS];
911
912 /*
913 * cc_state_lock protects (write) access to the per-port
914 * struct cc_state.
915 */
916 spinlock_t cc_state_lock ____cacheline_aligned_in_smp;
917
918 struct cc_state __rcu *cc_state;
919
920 /* Total number of congestion control table entries */
921 u16 total_cct_entry;
922
923 /* Bit map identifying service level */
924 u32 cc_sl_control_map;
925
926 /* CA's max number of 64 entry units in the congestion control table */
927 u8 cc_max_table_entries;
928
4d114fdd
JJ		 929 /*
930 * begin congestion log related entries
931 * cc_log_lock protects all congestion log related data
932 */
77241056 933 spinlock_t cc_log_lock ____cacheline_aligned_in_smp;
8638b77f 934 u8 threshold_cong_event_map[OPA_MAX_SLS / 8];
77241056
MM		 935 u16 threshold_event_counter;
936 struct opa_hfi1_cong_log_event_internal cc_events[OPA_CONG_LOG_ELEMS];
937 int cc_log_idx; /* index for logging events */
938 int cc_mad_idx; /* index for reporting events */
939 /* end congestion log related entries */
940
941 struct vl_arb_cache vl_arb_cache[MAX_PRIO_TABLE];
942
943 /* port relative counter buffer */
944 u64 *cntrs;
945 /* port relative synthetic counter buffer */
946 u64 *scntrs;
69a00b8e 947 /* port_xmit_discards are synthesized from different egress errors */
77241056 948 u64 port_xmit_discards;
69a00b8e 949 u64 port_xmit_discards_vl[C_VL_COUNT];
77241056
MM		 950 u64 port_xmit_constraint_errors;
951 u64 port_rcv_constraint_errors;
952 /* count of 'link_err' interrupts from DC */
953 u64 link_downed;
954 /* number of times link retrained successfully */
955 u64 link_up;
6d014530
DL		 956 /* number of times a link unknown frame was reported */
957 u64 unknown_frame_count;
77241056
MM		 958 /* port_ltp_crc_mode is returned in 'portinfo' MADs */
959 u16 port_ltp_crc_mode;
960 /* port_crc_mode_enabled is the crc we support */
961 u8 port_crc_mode_enabled;
962 /* mgmt_allowed is also returned in 'portinfo' MADs */
963 u8 mgmt_allowed;
964 u8 part_enforce; /* partition enforcement flags */
965 struct link_down_reason local_link_down_reason;
966 struct link_down_reason neigh_link_down_reason;
967 /* Value to be sent to link peer on LinkDown .*/
968 u8 remote_link_down_reason;
969 /* Error events that will cause a port bounce. */
970 u32 port_error_action;
fb9036dd 971 struct work_struct linkstate_active_work;
6c9e50f8
VM		 972 /* Does this port need to prescan for FECNs */
973 bool cc_prescan;
07190076
KA		 974 /*
975 * Sample sendWaitCnt & sendWaitVlCnt during link transition
976 * and counter request.
977 */
978 u64 port_vl_xmit_wait_last[C_VL_COUNT + 1];
979 u16 prev_link_width;
980 u64 vl_xmit_flit_cnt[C_VL_COUNT + 1];
77241056
MM		 981};
982
77241056 983typedef void (*opcode_handler)(struct hfi1_packet *packet);
88733e3b
DH		 984typedef void (*hfi1_make_req)(struct rvt_qp *qp,
985 struct hfi1_pkt_state *ps,
986 struct rvt_swqe *wqe);
b0ba3c18 987extern const rhf_rcv_function_ptr normal_rhf_rcv_functions[];
88733e3b 988
77241056
MM		 989
990/* return values for the RHF receive functions */
991#define RHF_RCV_CONTINUE 0 /* keep going */
992#define RHF_RCV_DONE 1 /* stop, this packet processed */
993#define RHF_RCV_REPROCESS 2 /* stop. retain this packet */
994
995struct rcv_array_data {
77241056
MM		 996 u16 ngroups;
997 u16 nctxt_extra;
c8314811 998 u8 group_size;
77241056
MM		 999};
1000
1001struct per_vl_data {
1002 u16 mtu;
1003 struct send_context *sc;
1004};
1005
1006/* 16 to directly index */
1007#define PER_VL_SEND_CONTEXTS 16
1008
1009struct err_info_rcvport {
1010 u8 status_and_code;
1011 u64 packet_flit1;
1012 u64 packet_flit2;
1013};
1014
1015struct err_info_constraint {
1016 u8 status;
1017 u16 pkey;
1018 u32 slid;
1019};
1020
1021struct hfi1_temp {
1022 unsigned int curr; /* current temperature */
1023 unsigned int lo_lim; /* low temperature limit */
1024 unsigned int hi_lim; /* high temperature limit */
1025 unsigned int crit_lim; /* critical temperature limit */
1026 u8 triggers; /* temperature triggers */
1027};
1028
dba715f0
DL		 1029struct hfi1_i2c_bus {
1030 struct hfi1_devdata *controlling_dd; /* current controlling device */
1031 struct i2c_adapter adapter; /* bus details */
1032 struct i2c_algo_bit_data algo; /* bus algorithm details */
1033 int num; /* bus number, 0 or 1 */
1034};
1035
78eb129d
DL		 1036/* common data between shared ASIC HFIs */
1037struct hfi1_asic_data {
1038 struct hfi1_devdata *dds[2]; /* back pointers */
1039 struct mutex asic_resource_mutex;
dba715f0
DL		 1040 struct hfi1_i2c_bus *i2c_bus0;
1041 struct hfi1_i2c_bus *i2c_bus1;
78eb129d
DL		 1042};
1043
2280740f
VN		 1044/* sizes for both the QP and RSM map tables */
1045#define NUM_MAP_ENTRIES 256
1046#define NUM_MAP_REGS 32
1047
d4829ea6
VN		 1048/*
1049 * Number of VNIC contexts used. Ensure it is less than or equal to
1050 * max queues supported by VNIC (HFI1_VNIC_MAX_QUEUE).
1051 */
1052#define HFI1_NUM_VNIC_CTXT 8
1053
2280740f
VN		 1054/* Number of VNIC RSM entries */
1055#define NUM_VNIC_MAP_ENTRIES 8
1056
d4829ea6
VN		 1057/* Virtual NIC information */
1058struct hfi1_vnic_data {
2280740f 1059 struct hfi1_ctxtdata *ctxt[HFI1_NUM_VNIC_CTXT];
64551ede 1060 struct kmem_cache *txreq_cache;
0ee3b915 1061 struct xarray vesws;
2280740f 1062 u8 num_vports;
2280740f
VN		 1063 u8 rmt_start;
1064 u8 num_ctxt;
d4829ea6
VN		 1065};
1066
1067struct hfi1_vnic_vport_info;
1068
77241056
MM		 1069/* device data struct now contains only "general per-device" info.
1070 * fields related to a physical IB port are in a hfi1_pportdata struct.
1071 */
1072struct sdma_engine;
1073struct sdma_vl_map;
1074
1075#define BOARD_VERS_MAX 96 /* how long the version string can be */
1076#define SERIAL_MAX 16 /* length of the serial number */
1077
14553ca1 1078typedef int (*send_routine)(struct rvt_qp *, struct hfi1_pkt_state *, u64);
77241056
MM		 1079struct hfi1_devdata {
1080 struct hfi1_ibdev verbs_dev; /* must be first */
77241056
MM		 1081 /* pointers to related structs for this device */
1082 /* pci access data structure */
1083 struct pci_dev *pcidev;
1084 struct cdev user_cdev;
1085 struct cdev diag_cdev;
1086 struct cdev ui_cdev;
1087 struct device *user_device;
1088 struct device *diag_device;
1089 struct device *ui_device;
1090
cb51c5d2
MM		 1091 /* first mapping up to RcvArray */
1092 u8 __iomem *kregbase1;
77241056 1093 resource_size_t physaddr;
cb51c5d2
MM		 1094
1095 /* second uncached mapping from RcvArray to pio send buffers */
1096 u8 __iomem *kregbase2;
1097 /* for detecting offset above kregbase2 address */
1098 u32 base2_start;
1099
6e768f06
SS		 1100 /* Per VL data. Enough for all VLs but not all elements are set/used. */
1101 struct per_vl_data vld[PER_VL_SEND_CONTEXTS];
77241056
MM		 1102 /* send context data */
1103 struct send_context_info *send_contexts;
1104 /* map hardware send contexts to software index */
1105 u8 *hw_to_sw;
1106 /* spinlock for allocating and releasing send context resources */
1107 spinlock_t sc_lock;
35f6befc
JJ		 1108 /* lock for pio_map */
1109 spinlock_t pio_map_lock;
6e768f06
SS		 1110 /* Send Context initialization lock. */
1111 spinlock_t sc_init_lock;
1112 /* lock for sdma_map */
1113 spinlock_t sde_map_lock;
35f6befc
JJ		 1114 /* array of kernel send contexts */
1115 struct send_context **kernel_send_context;
1116 /* array of vl maps */
1117 struct pio_vl_map __rcu *pio_map;
6e768f06
SS		 1118 /* default flags to last descriptor */
1119 u64 default_desc1;
77241056
MM		 1120
1121 /* fields common to all SDMA engines */
1122
77241056
MM		 1123 volatile __le64 *sdma_heads_dma; /* DMA'ed by chip */
1124 dma_addr_t sdma_heads_phys;
1125 void *sdma_pad_dma; /* DMA'ed by chip */
1126 dma_addr_t sdma_pad_phys;
1127 /* for deallocation */
1128 size_t sdma_heads_size;
77241056
MM		 1129 /* num used */
1130 u32 num_sdma;
77241056
MM		 1131 /* array of engines sized by num_sdma */
1132 struct sdma_engine *per_sdma;
1133 /* array of vl maps */
1134 struct sdma_vl_map __rcu *sdma_map;
1135 /* SPC freeze waitqueue and variable */
1136 wait_queue_head_t sdma_unfreeze_wq;
1137 atomic_t sdma_unfreeze_count;
1138
6e768f06
SS		 1139 u32 lcb_access_count; /* count of LCB users */
1140
78eb129d
DL		 1141 /* common data between shared ASIC HFIs in this OS */
1142 struct hfi1_asic_data *asic_data;
1143
77241056
MM		 1144 /* mem-mapped pointer to base of PIO buffers */
1145 void __iomem *piobase;
1146 /*
1147 * write-combining mem-mapped pointer to base of RcvArray
1148 * memory.
1149 */
1150 void __iomem *rcvarray_wc;
1151 /*
1152 * credit return base - a per-NUMA range of DMA address that
1153 * the chip will use to update the per-context free counter
1154 */
1155 struct credit_return_base *cr_base;
1156
1157 /* send context numbers and sizes for each type */
1158 struct sc_config_sizes sc_sizes[SC_MAX];
1159
77241056
MM		 1160 char *boardname; /* human readable board info */
1161
5ffd0486
MM		 1162 u64 ctx0_seq_drop;
1163
77241056
MM		 1164 /* reset value */
1165 u64 z_int_counter;
1166 u64 z_rcv_limit;
89abfc8d 1167 u64 z_send_schedule;
6e768f06 1168
89abfc8d 1169 u64 __percpu *send_schedule;
d7d62617
MR		 1170 /* number of reserved contexts for VNIC usage */
1171 u16 num_vnic_contexts;
77241056
MM		 1172 /* number of receive contexts in use by the driver */
1173 u32 num_rcv_contexts;
1174 /* number of pio send contexts in use by the driver */
1175 u32 num_send_contexts;
1176 /*
1177 * number of ctxts available for PSM open
1178 */
1179 u32 freectxts;
affa48de
AD		 1180 /* total number of available user/PSM contexts */
1181 u32 num_user_contexts;
77241056
MM		 1182 /* base receive interrupt timeout, in CSR units */
1183 u32 rcv_intr_timeout_csr;
1184
77241056
MM		 1185 spinlock_t sendctrl_lock; /* protect changes to SendCtrl */
1186 spinlock_t rcvctrl_lock; /* protect changes to RcvCtrl */
d295dbeb 1187 spinlock_t uctxt_lock; /* protect rcd changes */
22546b74
TS		 1188 struct mutex dc8051_lock; /* exclusive access to 8051 */
1189 struct workqueue_struct *update_cntr_wq;
1190 struct work_struct update_cntr_work;
77241056
MM		 1191 /* exclusive access to 8051 memory */
1192 spinlock_t dc8051_memlock;
1193 int dc8051_timed_out; /* remember if the 8051 timed out */
1194 /*
1195 * A page that will hold event notification bitmaps for all
1196 * contexts. This page will be mapped into all processes.
1197 */
1198 unsigned long *events;
1199 /*
1200 * per unit status, see also portdata statusp
1201 * mapped read-only into user processes so they can get unit and
1202 * IB link status cheaply
1203 */
1204 struct hfi1_status *status;
77241056
MM		 1205
1206 /* revision register shadow */
1207 u64 revision;
1208 /* Base GUID for device (network order) */
1209 u64 base_guid;
1210
77241056
MM		 1211 /* both sides of the PCIe link are gen3 capable */
1212 u8 link_gen3_capable;
156d24d7 1213 u8 dc_shutdown;
77241056
MM		 1214 /* localbus width (1, 2,4,8,16,32) from config space */
1215 u32 lbus_width;
1216 /* localbus speed in MHz */
1217 u32 lbus_speed;
1218 int unit; /* unit # of this chip */
1219 int node; /* home node of this chip */
1220
1221 /* save these PCI fields to restore after a reset */
1222 u32 pcibar0;
1223 u32 pcibar1;
1224 u32 pci_rom;
1225 u16 pci_command;
1226 u16 pcie_devctl;
1227 u16 pcie_lnkctl;
1228 u16 pcie_devctl2;
1229 u32 pci_msix0;
77241056
MM		 1230 u32 pci_tph2;
1231
1232 /*
1233 * ASCII serial number, from flash, large enough for original
1234 * all digit strings, and longer serial number format
1235 */
1236 u8 serial[SERIAL_MAX];
1237 /* human readable board version */
1238 u8 boardversion[BOARD_VERS_MAX];
1239 u8 lbus_info[32]; /* human readable localbus info */
1240 /* chip major rev, from CceRevision */
1241 u8 majrev;
1242 /* chip minor rev, from CceRevision */
1243 u8 minrev;
1244 /* hardware ID */
1245 u8 hfi1_id;
1246 /* implementation code */
1247 u8 icode;
77241056
MM		 1248 /* vAU of this device */
1249 u8 vau;
1250 /* vCU of this device */
1251 u8 vcu;
1252 /* link credits of this device */
1253 u16 link_credits;
1254 /* initial vl15 credits to use */
1255 u16 vl15_init;
1256
b3e6b4bd
BJ		 1257 /*
1258 * Cached value for vl15buf, read during verify cap interrupt. VL15
1259 * credits are to be kept at 0 and set when handling the link-up
1260 * interrupt. This removes the possibility of receiving VL15 MAD
1261 * packets before this HFI is ready.
1262 */
1263 u16 vl15buf_cached;
1264
77241056 1265 /* Misc small ints */
77241056
MM		 1266 u8 n_krcv_queues;
1267 u8 qos_shift;
77241056 1268
77241056 1269 u16 irev; /* implementation revision */
5e6e9424 1270 u32 dc8051_ver; /* 8051 firmware version */
77241056 1271
6e768f06 1272 spinlock_t hfi1_diag_trans_lock; /* protect diag observer ops */
c3838b39 1273 struct platform_config platform_config;
77241056 1274 struct platform_config_cache pcfg_cache;
77241056
MM		 1275
1276 struct diag_client *diag_client;
77241056 1277
77241056
MM		 1278 /* general interrupt: mask of handled interrupts */
1279 u64 gi_mask[CCE_NUM_INT_CSRS];
1280
1281 struct rcv_array_data rcv_entries;
1282
6e768f06
SS		 1283 /* cycle length of PS* counters in HW (in picoseconds) */
1284 u16 psxmitwait_check_rate;
1285
77241056
MM		 1286 /*
1287 * 64 bit synthetic counters
1288 */
1289 struct timer_list synth_stats_timer;
1290
a2f7bbdc
MR		 1291 /* MSI-X information */
1292 struct hfi1_msix_info msix_info;
1293
77241056
MM		 1294 /*
1295 * device counters
1296 */
1297 char *cntrnames;
1298 size_t cntrnameslen;
1299 size_t ndevcntrs;
1300 u64 *cntrs;
1301 u64 *scntrs;
1302
1303 /*
1304 * remembered values for synthetic counters
1305 */
1306 u64 last_tx;
1307 u64 last_rx;
1308
1309 /*
1310 * per-port counters
1311 */
1312 size_t nportcntrs;
1313 char *portcntrnames;
1314 size_t portcntrnameslen;
1315
77241056
MM		 1316 struct err_info_rcvport err_info_rcvport;
1317 struct err_info_constraint err_info_rcv_constraint;
1318 struct err_info_constraint err_info_xmit_constraint;
77241056
MM		 1319
1320 atomic_t drop_packet;
cd47b594 1321 bool do_drop;
6e768f06
SS		 1322 u8 err_info_uncorrectable;
1323 u8 err_info_fmconfig;
77241056 1324
2c5b521a
JR		 1325 /*
1326 * Software counters for the status bits defined by the
1327 * associated error status registers
1328 */
1329 u64 cce_err_status_cnt[NUM_CCE_ERR_STATUS_COUNTERS];
1330 u64 rcv_err_status_cnt[NUM_RCV_ERR_STATUS_COUNTERS];
1331 u64 misc_err_status_cnt[NUM_MISC_ERR_STATUS_COUNTERS];
1332 u64 send_pio_err_status_cnt[NUM_SEND_PIO_ERR_STATUS_COUNTERS];
1333 u64 send_dma_err_status_cnt[NUM_SEND_DMA_ERR_STATUS_COUNTERS];
1334 u64 send_egress_err_status_cnt[NUM_SEND_EGRESS_ERR_STATUS_COUNTERS];
1335 u64 send_err_status_cnt[NUM_SEND_ERR_STATUS_COUNTERS];
1336
1337 /* Software counter that spans all contexts */
1338 u64 sw_ctxt_err_status_cnt[NUM_SEND_CTXT_ERR_STATUS_COUNTERS];
1339 /* Software counter that spans all DMA engines */
1340 u64 sw_send_dma_eng_err_status_cnt[
1341 NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS];
1342 /* Software counter that aggregates all cce_err_status errors */
1343 u64 sw_cce_err_status_aggregate;
2b719046
JP		 1344 /* Software counter that aggregates all bypass packet rcv errors */
1345 u64 sw_rcv_bypass_packet_errors;
77241056 1346
6e768f06
SS		 1347 /* Save the enabled LCB error bits */
1348 u64 lcb_err_en;
5d18ee67
SS		 1349 struct cpu_mask_set *comp_vect;
1350 int *comp_vect_mappings;
1351 u32 comp_vect_possible_cpus;
6e768f06 1352
77241056 1353 /*
eacc830f
DD		 1354 * Capability to have different send engines simply by changing a
1355 * pointer value.
77241056 1356 */
6e768f06 1357 send_routine process_pio_send ____cacheline_aligned_in_smp;
14553ca1 1358 send_routine process_dma_send;
77241056
MM		 1359 void (*pio_inline_send)(struct hfi1_devdata *dd, struct pio_buf *pbuf,
1360 u64 pbc, const void *from, size_t count);
d4829ea6
VN		 1361 int (*process_vnic_dma_send)(struct hfi1_devdata *dd, u8 q_idx,
1362 struct hfi1_vnic_vport_info *vinfo,
1363 struct sk_buff *skb, u64 pbc, u8 plen);
6e768f06
SS		 1364 /* hfi1_pportdata, points to array of (physical) port-specific
1365 * data structs, indexed by pidx (0..n-1)
1366 */
1367 struct hfi1_pportdata *pport;
1368 /* receive context data */
1369 struct hfi1_ctxtdata **rcd;
1370 u64 __percpu *int_counter;
1b311f89
MM		 1371 /* verbs tx opcode stats */
1372 struct hfi1_opcode_stats_perctx __percpu *tx_opstats;
6e768f06
SS		 1373 /* device (not port) flags, basically device capabilities */
1374 u16 flags;
1375 /* Number of physical ports available */
1376 u8 num_pports;
2280740f
VN		 1377 /* Lowest context number which can be used by user processes or VNIC */
1378 u8 first_dyn_alloc_ctxt;
6e768f06
SS		 1379 /* adding a new field here would make it part of this cacheline */
1380
1381 /* seqlock for sc2vl */
1382 seqlock_t sc2vl_lock ____cacheline_aligned_in_smp;
1383 u64 sc2vl[4];
6e768f06 1384 u64 __percpu *rcv_limit;
6e768f06 1385 /* adding a new field here would make it part of this cacheline */
77241056
MM		 1386
1387 /* OUI comes from the HW. Used everywhere as 3 separate bytes. */
1388 u8 oui1;
1389 u8 oui2;
1390 u8 oui3;
6e768f06 1391
77241056
MM		 1392 /* Timer and counter used to detect RcvBufOvflCnt changes */
1393 struct timer_list rcverr_timer;
77241056 1394
77241056
MM		 1395 wait_queue_head_t event_queue;
1396
46b010d3
MB		 1397 /* receive context tail dummy address */
1398 __le64 *rcvhdrtail_dummy_kvaddr;
60368186 1399 dma_addr_t rcvhdrtail_dummy_dma;
affa48de 1400
6e768f06 1401 u32 rcv_ovfl_cnt;
affa48de
AD		 1402 /* Serialize ASPM enable/disable between multiple verbs contexts */
1403 spinlock_t aspm_lock;
1404 /* Number of verbs contexts which have disabled ASPM */
1405 atomic_t aspm_disabled_cnt;
acd7c8fe
TS		 1406 /* Keeps track of user space clients */
1407 atomic_t user_refcount;
1408 /* Used to wait for outstanding user space clients before dev removal */
1409 struct completion user_comp;
957558c9 1410
6e768f06
SS		 1411 bool eprom_available; /* true if EPROM is available for this device */
1412 bool aspm_supported; /* Does HW support ASPM */
1413 bool aspm_enabled; /* ASPM state: enabled/disabled */
5a52a7ac 1414 struct rhashtable *sdma_rht;
6e768f06 1415
e11ffbd5 1416 struct kobject kobj;
d4829ea6
VN		 1417
1418 /* vnic data */
1419 struct hfi1_vnic_data vnic;
a2f7bbdc
MR		 1420 /* Lock to protect IRQ SRC register access */
1421 spinlock_t irq_src_lock;
77241056
MM		 1422};
1423
2280740f
VN		 1424static inline bool hfi1_vnic_is_rsm_full(struct hfi1_devdata *dd, int spare)
1425{
1426 return (dd->vnic.rmt_start + spare) > NUM_MAP_ENTRIES;
1427}
1428
77241056 1429/* 8051 firmware version helper */
5e6e9424
MR		 1430#define dc8051_ver(a, b, c) ((a) << 16 | (b) << 8 | (c))
1431#define dc8051_ver_maj(a) (((a) & 0xff0000) >> 16)
1432#define dc8051_ver_min(a) (((a) & 0x00ff00) >> 8)
1433#define dc8051_ver_patch(a) ((a) & 0x0000ff)
77241056
MM		 1434
1435/* f_put_tid types */
cb51c5d2
MM		 1436#define PT_EXPECTED 0
1437#define PT_EAGER 1
1438#define PT_INVALID_FLUSH 2
1439#define PT_INVALID 3
77241056 1440
06e0ffa6 1441struct tid_rb_node;
f727a0c3 1442struct mmu_rb_node;
e0b09ac5 1443struct mmu_rb_handler;
f727a0c3 1444
77241056
MM		 1445/* Private data for file operations */
1446struct hfi1_filedata {
be863834 1447 struct srcu_struct pq_srcu;
5fbded48 1448 struct hfi1_devdata *dd;
77241056 1449 struct hfi1_ctxtdata *uctxt;
77241056 1450 struct hfi1_user_sdma_comp_q *cq;
be863834
MM		 1451 /* update side lock for SRCU */
1452 spinlock_t pq_rcu_lock;
1453 struct hfi1_user_sdma_pkt_q __rcu *pq;
8737ce95 1454 u16 subctxt;
77241056
MM		 1455 /* for cpu affinity; -1 if none */
1456 int rec_cpu_num;
a7922f7d 1457 u32 tid_n_pinned;
3889551d 1458 bool use_mn;
06e0ffa6 1459 struct tid_rb_node **entry_to_rb;
a86cd357
MH		 1460 spinlock_t tid_lock; /* protect tid_[limit,used] counters */
1461 u32 tid_limit;
1462 u32 tid_used;
a86cd357
MH		 1463 u32 *invalid_tids;
1464 u32 invalid_tid_idx;
06e0ffa6
MH		 1465 /* protect invalid_tids array and invalid_tid_idx */
1466 spinlock_t invalid_lock;
3faa3d9a 1467 struct mm_struct *mm;
77241056
MM		 1468};
1469
03b92789 1470extern struct xarray hfi1_dev_table;
77241056 1471struct hfi1_devdata *hfi1_lookup(int unit);
77241056 1472
21e5acc0
MR		 1473static inline unsigned long uctxt_offset(struct hfi1_ctxtdata *uctxt)
1474{
1475 return (uctxt->ctxt - uctxt->dd->first_dyn_alloc_ctxt) *
1476 HFI1_MAX_SHARED_CTXTS;
1477}
1478
f4cd8765 1479int hfi1_init(struct hfi1_devdata *dd, int reinit);
77241056
MM		 1480int hfi1_count_active_units(void);
1481
f4cd8765
MR		 1482int hfi1_diag_add(struct hfi1_devdata *dd);
1483void hfi1_diag_remove(struct hfi1_devdata *dd);
77241056
MM		 1484void handle_linkup_change(struct hfi1_devdata *dd, u32 linkup);
1485
1486void handle_user_interrupt(struct hfi1_ctxtdata *rcd);
1487
f4cd8765
MR		 1488int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd);
1489int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *rcd);
f2a3bc00
MR		 1490int hfi1_create_kctxts(struct hfi1_devdata *dd);
1491int hfi1_create_ctxtdata(struct hfi1_pportdata *ppd, int numa,
1492 struct hfi1_ctxtdata **rcd);
d295dbeb 1493void hfi1_free_ctxt(struct hfi1_ctxtdata *rcd);
f4cd8765
MR		 1494void hfi1_init_pportdata(struct pci_dev *pdev, struct hfi1_pportdata *ppd,
1495 struct hfi1_devdata *dd, u8 hw_pidx, u8 port);
1496void hfi1_free_ctxtdata(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd);
f683c80c 1497int hfi1_rcd_put(struct hfi1_ctxtdata *rcd);
bc5add09 1498int hfi1_rcd_get(struct hfi1_ctxtdata *rcd);
d59075ad
MR		 1499struct hfi1_ctxtdata *hfi1_rcd_get_by_index_safe(struct hfi1_devdata *dd,
1500 u16 ctxt);
d295dbeb 1501struct hfi1_ctxtdata *hfi1_rcd_get_by_index(struct hfi1_devdata *dd, u16 ctxt);
f4cd8765
MR		 1502int handle_receive_interrupt(struct hfi1_ctxtdata *rcd, int thread);
1503int handle_receive_interrupt_nodma_rtail(struct hfi1_ctxtdata *rcd, int thread);
1504int handle_receive_interrupt_dma_rtail(struct hfi1_ctxtdata *rcd, int thread);
fb9036dd 1505void set_all_slowpath(struct hfi1_devdata *dd);
f4f30031 1506
d6373019 1507extern const struct pci_device_id hfi1_pci_tbl[];
88733e3b
DH		 1508void hfi1_make_ud_req_9B(struct rvt_qp *qp,
1509 struct hfi1_pkt_state *ps,
1510 struct rvt_swqe *wqe);
1511
1512void hfi1_make_ud_req_16B(struct rvt_qp *qp,
1513 struct hfi1_pkt_state *ps,
1514 struct rvt_swqe *wqe);
d6373019 1515
f4f30031
DL		 1516/* receive packet handler dispositions */
1517#define RCV_PKT_OK 0x0 /* keep going */
1518#define RCV_PKT_LIMIT 0x1 /* stop, hit limit, start thread */
1519#define RCV_PKT_DONE 0x2 /* stop, no more packets detected */
1520
2fb3b5ae
MM		 1521/**
1522 * hfi1_rcd_head - add accessor for rcd head
1523 * @rcd: the context
1524 */
1525static inline u32 hfi1_rcd_head(struct hfi1_ctxtdata *rcd)
1526{
1527 return rcd->head;
1528}
1529
1530/**
1531 * hfi1_set_rcd_head - add accessor for rcd head
1532 * @rcd: the context
1533 * @head: the new head
1534 */
1535static inline void hfi1_set_rcd_head(struct hfi1_ctxtdata *rcd, u32 head)
1536{
1537 rcd->head = head;
1538}
1539
f4f30031
DL		 1540/* calculate the current RHF address */
1541static inline __le32 *get_rhf_addr(struct hfi1_ctxtdata *rcd)
1542{
40442b30 1543 return (__le32 *)rcd->rcvhdrq + rcd->head + rcd->rhf_offset;
f4f30031
DL		 1544}
1545
2fb3b5ae
MM		 1546/* return DMA_RTAIL configuration */
1547static inline bool get_dma_rtail_setting(struct hfi1_ctxtdata *rcd)
1548{
1549 return !!HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL);
1550}
1551
1552/**
1553 * hfi1_seq_incr_wrap - wrapping increment for sequence
1554 * @seq: the current sequence number
1555 *
1556 * Returns: the incremented seq
1557 */
1558static inline u8 hfi1_seq_incr_wrap(u8 seq)
1559{
1560 if (++seq > RHF_MAX_SEQ)
1561 seq = 1;
1562 return seq;
1563}
1564
1565/**
1566 * hfi1_seq_cnt - return seq_cnt member
1567 * @rcd: the receive context
1568 *
1569 * Return seq_cnt member
1570 */
1571static inline u8 hfi1_seq_cnt(struct hfi1_ctxtdata *rcd)
1572{
1573 return rcd->seq_cnt;
1574}
1575
1576/**
1577 * hfi1_set_seq_cnt - return seq_cnt member
1578 * @rcd: the receive context
1579 *
1580 * Return seq_cnt member
1581 */
1582static inline void hfi1_set_seq_cnt(struct hfi1_ctxtdata *rcd, u8 cnt)
1583{
1584 rcd->seq_cnt = cnt;
1585}
1586
1587/**
1588 * last_rcv_seq - is last
1589 * @rcd: the receive context
1590 * @seq: sequence
1591 *
1592 * return true if last packet
1593 */
1594static inline bool last_rcv_seq(struct hfi1_ctxtdata *rcd, u32 seq)
1595{
1596 return seq != rcd->seq_cnt;
1597}
1598
1599/**
1600 * rcd_seq_incr - increment context sequence number
1601 * @rcd: the receive context
1602 * @seq: the current sequence number
1603 *
1604 * Returns: true if the this was the last packet
1605 */
1606static inline bool hfi1_seq_incr(struct hfi1_ctxtdata *rcd, u32 seq)
1607{
1608 rcd->seq_cnt = hfi1_seq_incr_wrap(rcd->seq_cnt);
1609 return last_rcv_seq(rcd, seq);
1610}
1611
1612/**
1613 * get_hdrqentsize - return hdrq entry size
1614 * @rcd: the receive context
1615 */
1616static inline u8 get_hdrqentsize(struct hfi1_ctxtdata *rcd)
1617{
1618 return rcd->rcvhdrqentsize;
1619}
1620
1621/**
1622 * get_hdrq_cnt - return hdrq count
1623 * @rcd: the receive context
1624 */
1625static inline u16 get_hdrq_cnt(struct hfi1_ctxtdata *rcd)
1626{
1627 return rcd->rcvhdrq_cnt;
1628}
1629
01c7fc50
MM		 1630/**
1631 * hfi1_is_slowpath - check if this context is slow path
1632 * @rcd: the receive context
1633 */
1634static inline bool hfi1_is_slowpath(struct hfi1_ctxtdata *rcd)
1635{
1636 return rcd->do_interrupt == rcd->slow_handler;
1637}
1638
1639/**
1640 * hfi1_is_fastpath - check if this context is fast path
1641 * @rcd: the receive context
1642 */
1643static inline bool hfi1_is_fastpath(struct hfi1_ctxtdata *rcd)
1644{
1645 if (rcd->ctxt == HFI1_CTRL_CTXT)
1646 return false;
1647
1648 return rcd->do_interrupt == rcd->fast_handler;
1649}
1650
1651/**
1652 * hfi1_set_fast - change to the fast handler
1653 * @rcd: the receive context
1654 */
1655static inline void hfi1_set_fast(struct hfi1_ctxtdata *rcd)
1656{
1657 if (unlikely(!rcd))
1658 return;
1659 if (unlikely(!hfi1_is_fastpath(rcd)))
1660 rcd->do_interrupt = rcd->fast_handler;
1661}
1662
77241056
MM		 1663int hfi1_reset_device(int);
1664
fb9036dd
JS		 1665void receive_interrupt_work(struct work_struct *work);
1666
1667/* extract service channel from header and rhf */
aad559c2 1668static inline int hfi1_9B_get_sc5(struct ib_header *hdr, u64 rhf)
fb9036dd 1669{
cb427057 1670 return ib_get_sc(hdr) | ((!!(rhf_dc_info(rhf))) << 4);
fb9036dd
JS		 1671}
1672
08fe16f6
MH		 1673#define HFI1_JKEY_WIDTH 16
1674#define HFI1_JKEY_MASK (BIT(16) - 1)
1675#define HFI1_ADMIN_JKEY_RANGE 32
1676
1677/*
1678 * J_KEYs are split and allocated in the following groups:
1679 * 0 - 31 - users with administrator privileges
1680 * 32 - 63 - kernel protocols using KDETH packets
1681 * 64 - 65535 - all other users using KDETH packets
1682 */
77241056
MM		 1683static inline u16 generate_jkey(kuid_t uid)
1684{
08fe16f6
MH		 1685 u16 jkey = from_kuid(current_user_ns(), uid) & HFI1_JKEY_MASK;
1686
1687 if (capable(CAP_SYS_ADMIN))
1688 jkey &= HFI1_ADMIN_JKEY_RANGE - 1;
1689 else if (jkey < 64)
1690 jkey |= BIT(HFI1_JKEY_WIDTH - 1);
1691
1692 return jkey;
77241056
MM		 1693}
1694
1695/*
1696 * active_egress_rate
1697 *
1698 * returns the active egress rate in units of [10^6 bits/sec]
1699 */
1700static inline u32 active_egress_rate(struct hfi1_pportdata *ppd)
1701{
1702 u16 link_speed = ppd->link_speed_active;
1703 u16 link_width = ppd->link_width_active;
1704 u32 egress_rate;
1705
1706 if (link_speed == OPA_LINK_SPEED_25G)
1707 egress_rate = 25000;
1708 else /* assume OPA_LINK_SPEED_12_5G */
1709 egress_rate = 12500;
1710
1711 switch (link_width) {
1712 case OPA_LINK_WIDTH_4X:
1713 egress_rate *= 4;
1714 break;
1715 case OPA_LINK_WIDTH_3X:
1716 egress_rate *= 3;
1717 break;
1718 case OPA_LINK_WIDTH_2X:
1719 egress_rate *= 2;
1720 break;
1721 default:
1722 /* assume IB_WIDTH_1X */
1723 break;
1724 }
1725
1726 return egress_rate;
1727}
1728
1729/*
1730 * egress_cycles
1731 *
1732 * Returns the number of 'fabric clock cycles' to egress a packet
1733 * of length 'len' bytes, at 'rate' Mbit/s. Since the fabric clock
1734 * rate is (approximately) 805 MHz, the units of the returned value
1735 * are (1/805 MHz).
1736 */
1737static inline u32 egress_cycles(u32 len, u32 rate)
1738{
1739 u32 cycles;
1740
1741 /*
1742 * cycles is:
1743 *
1744 * (length) [bits] / (rate) [bits/sec]
1745 * ---------------------------------------------------
1746 * fabric_clock_period == 1 /(805 * 10^6) [cycles/sec]
1747 */
1748
1749 cycles = len * 8; /* bits */
1750 cycles *= 805;
1751 cycles /= rate;
1752
1753 return cycles;
1754}
1755
1756void set_link_ipg(struct hfi1_pportdata *ppd);
5b6cabb0 1757void process_becn(struct hfi1_pportdata *ppd, u8 sl, u32 rlid, u32 lqpn,
77241056 1758 u32 rqpn, u8 svc_type);
895420dd 1759void return_cnp(struct hfi1_ibport *ibp, struct rvt_qp *qp, u32 remote_qpn,
f59fb9e0 1760 u16 pkey, u32 slid, u32 dlid, u8 sc5,
77241056 1761 const struct ib_grh *old_grh);
88733e3b 1762void return_cnp_16B(struct hfi1_ibport *ibp, struct rvt_qp *qp,
f59fb9e0 1763 u32 remote_qpn, u16 pkey, u32 slid, u32 dlid,
88733e3b
DH		 1764 u8 sc5, const struct ib_grh *old_grh);
1765typedef void (*hfi1_handle_cnp)(struct hfi1_ibport *ibp, struct rvt_qp *qp,
f59fb9e0 1766 u32 remote_qpn, u16 pkey, u32 slid, u32 dlid,
88733e3b
DH		 1767 u8 sc5, const struct ib_grh *old_grh);
1768
e38d1e4f 1769#define PKEY_CHECK_INVALID -1
566d53a8 1770int egress_pkey_check(struct hfi1_pportdata *ppd, u32 slid, u16 pkey,
e38d1e4f 1771 u8 sc5, int8_t s_pkey_index);
77241056
MM		 1772
1773#define PACKET_EGRESS_TIMEOUT 350
1774static inline void pause_for_credit_return(struct hfi1_devdata *dd)
1775{
1776 /* Pause at least 1us, to ensure chip returns all credits */
1777 u32 usec = cclock_to_ns(dd, PACKET_EGRESS_TIMEOUT) / 1000;
1778
1779 udelay(usec ? usec : 1);
1780}
1781
1782/**
1783 * sc_to_vlt() reverse lookup sc to vl
1784 * @dd - devdata
1785 * @sc5 - 5 bit sc
1786 */
1787static inline u8 sc_to_vlt(struct hfi1_devdata *dd, u8 sc5)
1788{
1789 unsigned seq;
1790 u8 rval;
1791
1792 if (sc5 >= OPA_MAX_SCS)
1793 return (u8)(0xff);
1794
1795 do {
1796 seq = read_seqbegin(&dd->sc2vl_lock);
1797 rval = *(((u8 *)dd->sc2vl) + sc5);
1798 } while (read_seqretry(&dd->sc2vl_lock, seq));
1799
1800 return rval;
1801}
1802
1803#define PKEY_MEMBER_MASK 0x8000
1804#define PKEY_LOW_15_MASK 0x7fff
1805
1806/*
1807 * ingress_pkey_matches_entry - return 1 if the pkey matches ent (ent
1808 * being an entry from the ingress partition key table), return 0
1809 * otherwise. Use the matching criteria for ingress partition keys
1810 * specified in the OPAv1 spec., section 9.10.14.
1811 */
1812static inline int ingress_pkey_matches_entry(u16 pkey, u16 ent)
1813{
1814 u16 mkey = pkey & PKEY_LOW_15_MASK;
1815 u16 ment = ent & PKEY_LOW_15_MASK;
1816
1817 if (mkey == ment) {
1818 /*
1819 * If pkey[15] is clear (limited partition member),
1820 * is bit 15 in the corresponding table element
1821 * clear (limited member)?
1822 */
1823 if (!(pkey & PKEY_MEMBER_MASK))
1824 return !!(ent & PKEY_MEMBER_MASK);
1825 return 1;
1826 }
1827 return 0;
1828}
1829
1830/*
1831 * ingress_pkey_table_search - search the entire pkey table for
1832 * an entry which matches 'pkey'. return 0 if a match is found,
1833 * and 1 otherwise.
1834 */
1835static int ingress_pkey_table_search(struct hfi1_pportdata *ppd, u16 pkey)
1836{
1837 int i;
1838
1839 for (i = 0; i < MAX_PKEY_VALUES; i++) {
1840 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[i]))
1841 return 0;
1842 }
1843 return 1;
1844}
1845
1846/*
1847 * ingress_pkey_table_fail - record a failure of ingress pkey validation,
1848 * i.e., increment port_rcv_constraint_errors for the port, and record
1849 * the 'error info' for this failure.
1850 */
1851static void ingress_pkey_table_fail(struct hfi1_pportdata *ppd, u16 pkey,
2e903b61 1852 u32 slid)
77241056
MM		 1853{
1854 struct hfi1_devdata *dd = ppd->dd;
1855
1856 incr_cntr64(&ppd->port_rcv_constraint_errors);
1857 if (!(dd->err_info_rcv_constraint.status & OPA_EI_STATUS_SMASK)) {
1858 dd->err_info_rcv_constraint.status |= OPA_EI_STATUS_SMASK;
1859 dd->err_info_rcv_constraint.slid = slid;
1860 dd->err_info_rcv_constraint.pkey = pkey;
1861 }
1862}
1863
1864/*
1865 * ingress_pkey_check - Return 0 if the ingress pkey is valid, return 1
1866 * otherwise. Use the criteria in the OPAv1 spec, section 9.10.14. idx
1867 * is a hint as to the best place in the partition key table to begin
1868 * searching. This function should not be called on the data path because
1869 * of performance reasons. On datapath pkey check is expected to be done
1870 * by HW and rcv_pkey_check function should be called instead.
1871 */
1872static inline int ingress_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
5786adf3 1873 u8 sc5, u8 idx, u32 slid, bool force)
77241056 1874{
5786adf3 1875 if (!(force) && !(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
77241056
MM		 1876 return 0;
1877
1878 /* If SC15, pkey[0:14] must be 0x7fff */
1879 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1880 goto bad;
1881
1882 /* Is the pkey = 0x0, or 0x8000? */
1883 if ((pkey & PKEY_LOW_15_MASK) == 0)
1884 goto bad;
1885
1886 /* The most likely matching pkey has index 'idx' */
1887 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[idx]))
1888 return 0;
1889
1890 /* no match - try the whole table */
1891 if (!ingress_pkey_table_search(ppd, pkey))
1892 return 0;
1893
1894bad:
1895 ingress_pkey_table_fail(ppd, pkey, slid);
1896 return 1;
1897}
1898
1899/*
1900 * rcv_pkey_check - Return 0 if the ingress pkey is valid, return 1
1901 * otherwise. It only ensures pkey is vlid for QP0. This function
1902 * should be called on the data path instead of ingress_pkey_check
1903 * as on data path, pkey check is done by HW (except for QP0).
1904 */
1905static inline int rcv_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
1906 u8 sc5, u16 slid)
1907{
1908 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
1909 return 0;
1910
1911 /* If SC15, pkey[0:14] must be 0x7fff */
1912 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1913 goto bad;
1914
1915 return 0;
1916bad:
1917 ingress_pkey_table_fail(ppd, pkey, slid);
1918 return 1;
1919}
1920
1921/* MTU handling */
1922
1923/* MTU enumeration, 256-4k match IB */
1924#define OPA_MTU_0 0
1925#define OPA_MTU_256 1
1926#define OPA_MTU_512 2
1927#define OPA_MTU_1024 3
1928#define OPA_MTU_2048 4
1929#define OPA_MTU_4096 5
1930
1931u32 lrh_max_header_bytes(struct hfi1_devdata *dd);
1932int mtu_to_enum(u32 mtu, int default_if_bad);
f4cd8765 1933u16 enum_to_mtu(int mtu);
77241056
MM		 1934static inline int valid_ib_mtu(unsigned int mtu)
1935{
1936 return mtu == 256 || mtu == 512 ||
1937 mtu == 1024 || mtu == 2048 ||
1938 mtu == 4096;
1939}
f4d507cd 1940
77241056
MM		 1941static inline int valid_opa_max_mtu(unsigned int mtu)
1942{
1943 return mtu >= 2048 &&
1944 (valid_ib_mtu(mtu) || mtu == 8192 || mtu == 10240);
1945}
1946
f4cd8765 1947int set_mtu(struct hfi1_pportdata *ppd);
77241056 1948
f4cd8765
MR		 1949int hfi1_set_lid(struct hfi1_pportdata *ppd, u32 lid, u8 lmc);
1950void hfi1_disable_after_error(struct hfi1_devdata *dd);
1951int hfi1_set_uevent_bits(struct hfi1_pportdata *ppd, const int evtbit);
1952int hfi1_rcvbuf_validate(u32 size, u8 type, u16 *encode);
77241056 1953
f4cd8765
MR		 1954int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t);
1955int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t);
77241056 1956
b3e6b4bd
BJ		 1957void set_up_vau(struct hfi1_devdata *dd, u8 vau);
1958void set_up_vl15(struct hfi1_devdata *dd, u16 vl15buf);
77241056
MM		 1959void reset_link_credits(struct hfi1_devdata *dd);
1960void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu);
1961
8a4d3444 1962int set_buffer_control(struct hfi1_pportdata *ppd, struct buffer_control *bc);
77241056 1963
77241056
MM		 1964static inline struct hfi1_devdata *dd_from_ppd(struct hfi1_pportdata *ppd)
1965{
1966 return ppd->dd;
1967}
1968
1969static inline struct hfi1_devdata *dd_from_dev(struct hfi1_ibdev *dev)
1970{
1971 return container_of(dev, struct hfi1_devdata, verbs_dev);
1972}
1973
1974static inline struct hfi1_devdata *dd_from_ibdev(struct ib_device *ibdev)
1975{
1976 return dd_from_dev(to_idev(ibdev));
1977}
1978
1979static inline struct hfi1_pportdata *ppd_from_ibp(struct hfi1_ibport *ibp)
1980{
1981 return container_of(ibp, struct hfi1_pportdata, ibport_data);
1982}
1983
45b59eef
HC		 1984static inline struct hfi1_ibdev *dev_from_rdi(struct rvt_dev_info *rdi)
1985{
1986 return container_of(rdi, struct hfi1_ibdev, rdi);
1987}
1988
77241056
MM		 1989static inline struct hfi1_ibport *to_iport(struct ib_device *ibdev, u8 port)
1990{
1991 struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1992 unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */
1993
1994 WARN_ON(pidx >= dd->num_pports);
1995 return &dd->pport[pidx].ibport_data;
1996}
1997
f3e862cb
SS		 1998static inline struct hfi1_ibport *rcd_to_iport(struct hfi1_ctxtdata *rcd)
1999{
2000 return &rcd->ppd->ibport_data;
2001}
2002
fe4dd423
MH		 2003/**
2004 * hfi1_may_ecn - Check whether FECN or BECN processing should be done
2005 * @pkt: the packet to be evaluated
2006 *
2007 * Check whether the FECN or BECN bits in the packet's header are
2008 * enabled, depending on packet type.
2009 *
2010 * This function only checks for FECN and BECN bits. Additional checks
2011 * are done in the slowpath (hfi1_process_ecn_slowpath()) in order to
2012 * ensure correct handling.
2013 */
2014static inline bool hfi1_may_ecn(struct hfi1_packet *pkt)
5fd2b562 2015{
fe4dd423 2016 bool fecn, becn;
88733e3b
DH		 2017
2018 if (pkt->etype == RHF_RCV_TYPE_BYPASS) {
2019 fecn = hfi1_16B_get_fecn(pkt->hdr);
2020 becn = hfi1_16B_get_becn(pkt->hdr);
2021 } else {
ca85bb1c
SS		 2022 fecn = ib_bth_get_fecn(pkt->ohdr);
2023 becn = ib_bth_get_becn(pkt->ohdr);
88733e3b 2024 }
fe4dd423
MH		 2025 return fecn || becn;
2026}
2027
2028bool hfi1_process_ecn_slowpath(struct rvt_qp *qp, struct hfi1_packet *pkt,
2029 bool prescan);
2030static inline bool process_ecn(struct rvt_qp *qp, struct hfi1_packet *pkt)
2031{
2032 bool do_work;
2033
2034 do_work = hfi1_may_ecn(pkt);
2035 if (unlikely(do_work))
2036 return hfi1_process_ecn_slowpath(qp, pkt, false);
5fd2b562
MH		 2037 return false;
2038}
2039
77241056
MM		 2040/*
2041 * Return the indexed PKEY from the port PKEY table.
2042 */
2043static inline u16 hfi1_get_pkey(struct hfi1_ibport *ibp, unsigned index)
2044{
2045 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
2046 u16 ret;
2047
2048 if (index >= ARRAY_SIZE(ppd->pkeys))
2049 ret = 0;
2050 else
2051 ret = ppd->pkeys[index];
2052
2053 return ret;
2054}
2055
a6cd5f08
JP		 2056/*
2057 * Return the indexed GUID from the port GUIDs table.
2058 */
2059static inline __be64 get_sguid(struct hfi1_ibport *ibp, unsigned int index)
2060{
2061 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
2062
2063 WARN_ON(index >= HFI1_GUIDS_PER_PORT);
2064 return cpu_to_be64(ppd->guids[index]);
2065}
2066
77241056 2067/*
8adf71fa 2068 * Called by readers of cc_state only, must call under rcu_read_lock().
77241056
MM		 2069 */
2070static inline struct cc_state *get_cc_state(struct hfi1_pportdata *ppd)
2071{
2072 return rcu_dereference(ppd->cc_state);
2073}
2074
8adf71fa
JX		 2075/*
2076 * Called by writers of cc_state only, must call under cc_state_lock.
2077 */
2078static inline
2079struct cc_state *get_cc_state_protected(struct hfi1_pportdata *ppd)
2080{
2081 return rcu_dereference_protected(ppd->cc_state,
2082 lockdep_is_held(&ppd->cc_state_lock));
2083}
2084
77241056
MM		 2085/*
2086 * values for dd->flags (_device_ related flags)
2087 */
2088#define HFI1_INITTED 0x1 /* chip and driver up and initted */
2089#define HFI1_PRESENT 0x2 /* chip accesses can be done */
2090#define HFI1_FROZEN 0x4 /* chip in SPC freeze */
2091#define HFI1_HAS_SDMA_TIMEOUT 0x8
2092#define HFI1_HAS_SEND_DMA 0x10 /* Supports Send DMA */
2093#define HFI1_FORCED_FREEZE 0x80 /* driver forced freeze mode */
8d3e7113 2094#define HFI1_SHUTDOWN 0x100 /* device is shutting down */
77241056
MM		 2095
2096/* IB dword length mask in PBC (lower 11 bits); same for all chips */
2097#define HFI1_PBC_LENGTH_MASK ((1 << 11) - 1)
2098
77241056 2099/* ctxt_flag bit offsets */
62239fc6
MR		 2100 /* base context has not finished initializing */
2101#define HFI1_CTXT_BASE_UNINIT 1
2102 /* base context initaliation failed */
2103#define HFI1_CTXT_BASE_FAILED 2
77241056 2104 /* waiting for a packet to arrive */
62239fc6 2105#define HFI1_CTXT_WAITING_RCV 3
77241056 2106 /* waiting for an urgent packet to arrive */
62239fc6 2107#define HFI1_CTXT_WAITING_URG 4
77241056
MM		 2108
2109/* free up any allocated data at closes */
57f97e96 2110int hfi1_init_dd(struct hfi1_devdata *dd);
f4cd8765 2111void hfi1_free_devdata(struct hfi1_devdata *dd);
77241056 2112
2243472e
EH		 2113/* LED beaconing functions */
2114void hfi1_start_led_override(struct hfi1_pportdata *ppd, unsigned int timeon,
2115 unsigned int timeoff);
91ab4ed3 2116void shutdown_led_override(struct hfi1_pportdata *ppd);
77241056
MM		 2117
2118#define HFI1_CREDIT_RETURN_RATE (100)
2119
2120/*
2121 * The number of words for the KDETH protocol field. If this is
2122 * larger then the actual field used, then part of the payload
2123 * will be in the header.
2124 *
2125 * Optimally, we want this sized so that a typical case will
2126 * use full cache lines. The typical local KDETH header would
2127 * be:
2128 *
2129 * Bytes Field
2130 * 8 LRH
2131 * 12 BHT
2132 * ?? KDETH
2133 * 8 RHF
2134 * ---
2135 * 28 + KDETH
2136 *
2137 * For a 64-byte cache line, KDETH would need to be 36 bytes or 9 DWORDS
2138 */
2139#define DEFAULT_RCVHDRSIZE 9
2140
2141/*
2142 * Maximal header byte count:
2143 *
2144 * Bytes Field
2145 * 8 LRH
2146 * 40 GRH (optional)
2147 * 12 BTH
2148 * ?? KDETH
2149 * 8 RHF
2150 * ---
2151 * 68 + KDETH
2152 *
2153 * We also want to maintain a cache line alignment to assist DMA'ing
2154 * of the header bytes. Round up to a good size.
2155 */
2156#define DEFAULT_RCVHDR_ENTSIZE 32
2157
3faa3d9a
IW		 2158bool hfi1_can_pin_pages(struct hfi1_devdata *dd, struct mm_struct *mm,
2159 u32 nlocked, u32 npages);
2160int hfi1_acquire_user_pages(struct mm_struct *mm, unsigned long vaddr,
2161 size_t npages, bool writable, struct page **pages);
ac335e7e
IW		 2162void hfi1_release_user_pages(struct mm_struct *mm, struct page **p,
2163 size_t npages, bool dirty);
77241056 2164
2fb3b5ae
MM		 2165/**
2166 * hfi1_rcvhdrtail_kvaddr - return tail kvaddr
2167 * @rcd - the receive context
2168 */
2169static inline __le64 *hfi1_rcvhdrtail_kvaddr(const struct hfi1_ctxtdata *rcd)
2170{
2171 return (__le64 *)rcd->rcvhdrtail_kvaddr;
2172}
2173
77241056
MM		 2174static inline void clear_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
2175{
2fb3b5ae
MM		 2176 u64 *kv = (u64 *)hfi1_rcvhdrtail_kvaddr(rcd);
2177
2178 if (kv)
2179 *kv = 0ULL;
77241056
MM		 2180}
2181
2182static inline u32 get_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
2183{
2184 /*
2185 * volatile because it's a DMA target from the chip, routine is
2186 * inlined, and don't want register caching or reordering.
2187 */
2fb3b5ae
MM		 2188 return (u32)le64_to_cpu(*hfi1_rcvhdrtail_kvaddr(rcd));
2189}
2190
2191static inline bool hfi1_packet_present(struct hfi1_ctxtdata *rcd)
2192{
2193 if (likely(!rcd->rcvhdrtail_kvaddr)) {
2194 u32 seq = rhf_rcv_seq(rhf_to_cpu(get_rhf_addr(rcd)));
2195
2196 return !last_rcv_seq(rcd, seq);
2197 }
2198 return hfi1_rcd_head(rcd) != get_rcvhdrtail(rcd);
77241056
MM		 2199}
2200
2201/*
2202 * sysfs interface.
2203 */
2204
2205extern const char ib_hfi1_version[];
508a523f 2206extern const struct attribute_group ib_hfi1_attr_group;
77241056 2207
f4cd8765
MR		 2208int hfi1_device_create(struct hfi1_devdata *dd);
2209void hfi1_device_remove(struct hfi1_devdata *dd);
77241056
MM		 2210
2211int hfi1_create_port_files(struct ib_device *ibdev, u8 port_num,
2212 struct kobject *kobj);
f4cd8765
MR		 2213int hfi1_verbs_register_sysfs(struct hfi1_devdata *dd);
2214void hfi1_verbs_unregister_sysfs(struct hfi1_devdata *dd);
77241056
MM		 2215/* Hook for sysfs read of QSFP */
2216int qsfp_dump(struct hfi1_pportdata *ppd, char *buf, int len);
2217
57f97e96 2218int hfi1_pcie_init(struct hfi1_devdata *dd);
f4cd8765
MR		 2219void hfi1_pcie_cleanup(struct pci_dev *pdev);
2220int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev);
77241056 2221void hfi1_pcie_ddcleanup(struct hfi1_devdata *);
f4cd8765 2222int pcie_speeds(struct hfi1_devdata *dd);
c53df62c 2223int restore_pci_variables(struct hfi1_devdata *dd);
a618b7e4 2224int save_pci_variables(struct hfi1_devdata *dd);
77241056 2225int do_pcie_gen3_transition(struct hfi1_devdata *dd);
6a516bc9 2226void tune_pcie_caps(struct hfi1_devdata *dd);
77241056
MM		 2227int parse_platform_config(struct hfi1_devdata *dd);
2228int get_platform_config_field(struct hfi1_devdata *dd,
17fb4f29
JJ		 2229 enum platform_config_table_type_encoding
2230 table_type, int table_index, int field_index,
2231 u32 *data, u32 len);
77241056 2232
49dbb6cf 2233struct pci_dev *get_pci_dev(struct rvt_dev_info *rdi);
77241056
MM		 2234
2235/*
2236 * Flush write combining store buffers (if present) and perform a write
2237 * barrier.
2238 */
2239static inline void flush_wc(void)
2240{
2241 asm volatile("sfence" : : : "memory");
2242}
2243
2244void handle_eflags(struct hfi1_packet *packet);
bf808b50 2245void seqfile_dump_rcd(struct seq_file *s, struct hfi1_ctxtdata *rcd);
77241056 2246
77241056
MM		 2247/* global module parameter variables */
2248extern unsigned int hfi1_max_mtu;
2249extern unsigned int hfi1_cu;
2250extern unsigned int user_credit_return_threshold;
2ce6bf22 2251extern int num_user_contexts;
429b6a72 2252extern unsigned long n_krcvqs;
5b55ea3b 2253extern uint krcvqs[];
77241056
MM		 2254extern int krcvqsset;
2255extern uint kdeth_qp;
2256extern uint loopback;
2257extern uint quick_linkup;
2258extern uint rcv_intr_timeout;
2259extern uint rcv_intr_count;
2260extern uint rcv_intr_dynamic;
2261extern ushort link_crc_mask;
2262
2263extern struct mutex hfi1_mutex;
2264
2265/* Number of seconds before our card status check... */
2266#define STATUS_TIMEOUT 60
2267
2268#define DRIVER_NAME "hfi1"
2269#define HFI1_USER_MINOR_BASE 0
2270#define HFI1_TRACE_MINOR 127
77241056
MM		 2271#define HFI1_NMINORS 255
2272
2273#define PCI_VENDOR_ID_INTEL 0x8086
2274#define PCI_DEVICE_ID_INTEL0 0x24f0
2275#define PCI_DEVICE_ID_INTEL1 0x24f1
2276
2277#define HFI1_PKT_USER_SC_INTEGRITY \
2278 (SEND_CTXT_CHECK_ENABLE_DISALLOW_NON_KDETH_PACKETS_SMASK \
e38d1e4f 2279 | SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK \
77241056
MM		 2280 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_SMASK \
2281 | SEND_CTXT_CHECK_ENABLE_DISALLOW_GRH_SMASK)
2282
2283#define HFI1_PKT_KERNEL_SC_INTEGRITY \
2284 (SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK)
2285
2286static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd,
2287 u16 ctxt_type)
2288{
d9ac4555
JP		 2289 u64 base_sc_integrity;
2290
2291 /* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */
2292 if (HFI1_CAP_IS_KSET(NO_INTEGRITY))
2293 return 0;
2294
2295 base_sc_integrity =
77241056
MM		 2296 SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
2297 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK
2298 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
2299 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
2300 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
a74d5307 2301#ifndef CONFIG_FAULT_INJECTION
77241056 2302 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK
a74d5307 2303#endif
77241056
MM		 2304 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
2305 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
2306 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
2307 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_SMASK
2308 | SEND_CTXT_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
2309 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
2310 | SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK
2311 | SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK
77241056
MM		 2312 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK
2313 | SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK;
2314
2315 if (ctxt_type == SC_USER)
a74d5307
MH		 2316 base_sc_integrity |=
2317#ifndef CONFIG_FAULT_INJECTION
2318 SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK |
2319#endif
2320 HFI1_PKT_USER_SC_INTEGRITY;
22d136d7 2321 else if (ctxt_type != SC_KERNEL)
77241056
MM		 2322 base_sc_integrity |= HFI1_PKT_KERNEL_SC_INTEGRITY;
2323
d9ac4555
JP		 2324 /* turn on send-side job key checks if !A0 */
2325 if (!is_ax(dd))
2326 base_sc_integrity |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
2327
77241056
MM		 2328 return base_sc_integrity;
2329}
2330
2331static inline u64 hfi1_pkt_base_sdma_integrity(struct hfi1_devdata *dd)
2332{
d9ac4555
JP		 2333 u64 base_sdma_integrity;
2334
2335 /* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */
2336 if (HFI1_CAP_IS_KSET(NO_INTEGRITY))
2337 return 0;
2338
2339 base_sdma_integrity =
77241056 2340 SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
77241056
MM		 2341 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
2342 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
2343 | SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
2344 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
2345 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
2346 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
2347 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_SMASK
2348 | SEND_DMA_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
2349 | SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
2350 | SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK
2351 | SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK
77241056
MM		 2352 | SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK
2353 | SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK;
2354
d9ac4555
JP		 2355 if (!HFI1_CAP_IS_KSET(STATIC_RATE_CTRL))
2356 base_sdma_integrity |=
2357 SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK;
2358
2359 /* turn on send-side job key checks if !A0 */
2360 if (!is_ax(dd))
2361 base_sdma_integrity |=
2362 SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
2363
77241056
MM		 2364 return base_sdma_integrity;
2365}
2366
77241056
MM		 2367#define dd_dev_emerg(dd, fmt, ...) \
2368 dev_emerg(&(dd)->pcidev->dev, "%s: " fmt, \
11f0e897 2369 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
de42de80 2370
77241056
MM		 2371#define dd_dev_err(dd, fmt, ...) \
2372 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \
11f0e897 2373 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
de42de80
GM		 2374
2375#define dd_dev_err_ratelimited(dd, fmt, ...) \
2376 dev_err_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
11f0e897
MR		 2377 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), \
2378 ##__VA_ARGS__)
de42de80 2379
77241056
MM		 2380#define dd_dev_warn(dd, fmt, ...) \
2381 dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \
11f0e897 2382 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
77241056
MM		 2383
2384#define dd_dev_warn_ratelimited(dd, fmt, ...) \
2385 dev_warn_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
11f0e897
MR		 2386 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), \
2387 ##__VA_ARGS__)
77241056
MM		 2388
2389#define dd_dev_info(dd, fmt, ...) \
2390 dev_info(&(dd)->pcidev->dev, "%s: " fmt, \
11f0e897 2391 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
77241056 2392
c27aad00
JB		 2393#define dd_dev_info_ratelimited(dd, fmt, ...) \
2394 dev_info_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
11f0e897
MR		 2395 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), \
2396 ##__VA_ARGS__)
c27aad00 2397
a1edc18a
IW		 2398#define dd_dev_dbg(dd, fmt, ...) \
2399 dev_dbg(&(dd)->pcidev->dev, "%s: " fmt, \
11f0e897 2400 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
a1edc18a 2401
77241056 2402#define hfi1_dev_porterr(dd, port, fmt, ...) \
cde10afa 2403 dev_err(&(dd)->pcidev->dev, "%s: port %u: " fmt, \
11f0e897 2404 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), (port), ##__VA_ARGS__)
77241056
MM		 2405
2406/*
2407 * this is used for formatting hw error messages...
2408 */
2409struct hfi1_hwerror_msgs {
2410 u64 mask;
2411 const char *msg;
2412 size_t sz;
2413};
2414
2415/* in intr.c... */
2416void hfi1_format_hwerrors(u64 hwerrs,
2417 const struct hfi1_hwerror_msgs *hwerrmsgs,
2418 size_t nhwerrmsgs, char *msg, size_t lmsg);
2419
2420#define USER_OPCODE_CHECK_VAL 0xC0
2421#define USER_OPCODE_CHECK_MASK 0xC0
2422#define OPCODE_CHECK_VAL_DISABLED 0x0
2423#define OPCODE_CHECK_MASK_DISABLED 0x0
2424
2425static inline void hfi1_reset_cpu_counters(struct hfi1_devdata *dd)
2426{
2427 struct hfi1_pportdata *ppd;
2428 int i;
2429
2430 dd->z_int_counter = get_all_cpu_total(dd->int_counter);
2431 dd->z_rcv_limit = get_all_cpu_total(dd->rcv_limit);
89abfc8d 2432 dd->z_send_schedule = get_all_cpu_total(dd->send_schedule);
77241056
MM		 2433
2434 ppd = (struct hfi1_pportdata *)(dd + 1);
2435 for (i = 0; i < dd->num_pports; i++, ppd++) {
4eb06882
DD		 2436 ppd->ibport_data.rvp.z_rc_acks =
2437 get_all_cpu_total(ppd->ibport_data.rvp.rc_acks);
2438 ppd->ibport_data.rvp.z_rc_qacks =
2439 get_all_cpu_total(ppd->ibport_data.rvp.rc_qacks);
77241056
MM		 2440 }
2441}
2442
2443/* Control LED state */
2444static inline void setextled(struct hfi1_devdata *dd, u32 on)
2445{
2446 if (on)
2447 write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F);
2448 else
2449 write_csr(dd, DCC_CFG_LED_CNTRL, 0x10);
2450}
2451
765a6fac
DL		 2452/* return the i2c resource given the target */
2453static inline u32 i2c_target(u32 target)
2454{
2455 return target ? CR_I2C2 : CR_I2C1;
2456}
2457
2458/* return the i2c chain chip resource that this HFI uses for QSFP */
2459static inline u32 qsfp_resource(struct hfi1_devdata *dd)
2460{
2461 return i2c_target(dd->hfi1_id);
2462}
2463
fe4d9243
EH		 2464/* Is this device integrated or discrete? */
2465static inline bool is_integrated(struct hfi1_devdata *dd)
2466{
2467 return dd->pcidev->device == PCI_DEVICE_ID_INTEL1;
2468}
2469
cd47b594
MM		 2470/**
2471 * hfi1_need_drop - detect need for drop
2472 * @dd: - the device
2473 *
2474 * In some cases, the first packet needs to be dropped.
2475 *
2476 * Return true is the current packet needs to be dropped and false otherwise.
2477 */
2478static inline bool hfi1_need_drop(struct hfi1_devdata *dd)
2479{
2480 if (unlikely(dd->do_drop &&
2481 atomic_xchg(&dd->drop_packet, DROP_PACKET_OFF) ==
2482 DROP_PACKET_ON)) {
2483 dd->do_drop = false;
2484 return true;
2485 }
2486 return false;
2487}
2488
77241056
MM		 2489int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp);
2490
462b6b21
SS		 2491#define DD_DEV_ENTRY(dd) __string(dev, dev_name(&(dd)->pcidev->dev))
2492#define DD_DEV_ASSIGN(dd) __assign_str(dev, dev_name(&(dd)->pcidev->dev))
9039746c 2493
d98bb7f7
DH		 2494static inline void hfi1_update_ah_attr(struct ib_device *ibdev,
2495 struct rdma_ah_attr *attr)
2496{
2497 struct hfi1_pportdata *ppd;
2498 struct hfi1_ibport *ibp;
2499 u32 dlid = rdma_ah_get_dlid(attr);
2500
2501 /*
2502 * Kernel clients may not have setup GRH information
2503 * Set that here.
2504 */
2505 ibp = to_iport(ibdev, rdma_ah_get_port_num(attr));
2506 ppd = ppd_from_ibp(ibp);
2507 if ((((dlid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) ||
2508 (ppd->lid >= be16_to_cpu(IB_MULTICAST_LID_BASE))) &&
2509 (dlid != be32_to_cpu(OPA_LID_PERMISSIVE)) &&
2510 (dlid != be16_to_cpu(IB_LID_PERMISSIVE)) &&
2511 (!(rdma_ah_get_ah_flags(attr) & IB_AH_GRH))) ||
2512 (rdma_ah_get_make_grd(attr))) {
2513 rdma_ah_set_ah_flags(attr, IB_AH_GRH);
2514 rdma_ah_set_interface_id(attr, OPA_MAKE_ID(dlid));
2515 rdma_ah_set_subnet_prefix(attr, ibp->rvp.gid_prefix);
2516 }
2517}
2518
9039746c
DH		 2519/*
2520 * hfi1_check_mcast- Check if the given lid is
72c07e2b
DH		 2521 * in the OPA multicast range.
2522 *
2523 * The LID might either reside in ah.dlid or might be
2524 * in the GRH of the address handle as DGID if extended
2525 * addresses are in use.
9039746c 2526 */
72c07e2b
DH		 2527static inline bool hfi1_check_mcast(u32 lid)
2528{
2529 return ((lid >= opa_get_mcast_base(OPA_MCAST_NR)) &&
2530 (lid != be32_to_cpu(OPA_LID_PERMISSIVE)));
2531}
2532
2533#define opa_get_lid(lid, format) \
2534 __opa_get_lid(lid, OPA_PORT_PACKET_FORMAT_##format)
2535
2536/* Convert a lid to a specific lid space */
2537static inline u32 __opa_get_lid(u32 lid, u8 format)
2538{
2539 bool is_mcast = hfi1_check_mcast(lid);
2540
2541 switch (format) {
2542 case OPA_PORT_PACKET_FORMAT_8B:
2543 case OPA_PORT_PACKET_FORMAT_10B:
2544 if (is_mcast)
2545 return (lid - opa_get_mcast_base(OPA_MCAST_NR) +
2546 0xF0000);
2547 return lid & 0xFFFFF;
2548 case OPA_PORT_PACKET_FORMAT_16B:
2549 if (is_mcast)
2550 return (lid - opa_get_mcast_base(OPA_MCAST_NR) +
2551 0xF00000);
2552 return lid & 0xFFFFFF;
2553 case OPA_PORT_PACKET_FORMAT_9B:
2554 if (is_mcast)
2555 return (lid -
2556 opa_get_mcast_base(OPA_MCAST_NR) +
2557 be16_to_cpu(IB_MULTICAST_LID_BASE));
2558 else
2559 return lid & 0xFFFF;
2560 default:
2561 return lid;
2562 }
2563}
2564
2565/* Return true if the given lid is the OPA 16B multicast range */
2566static inline bool hfi1_is_16B_mcast(u32 lid)
9039746c 2567{
72c07e2b
DH		 2568 return ((lid >=
2569 opa_get_lid(opa_get_mcast_base(OPA_MCAST_NR), 16B)) &&
2570 (lid != opa_get_lid(be32_to_cpu(OPA_LID_PERMISSIVE), 16B)));
9039746c 2571}
d98bb7f7
DH		 2572
2573static inline void hfi1_make_opa_lid(struct rdma_ah_attr *attr)
2574{
2575 const struct ib_global_route *grh = rdma_ah_read_grh(attr);
2576 u32 dlid = rdma_ah_get_dlid(attr);
2577
2578 /* Modify ah_attr.dlid to be in the 32 bit LID space.
2579 * This is how the address will be laid out:
2580 * Assuming MCAST_NR to be 4,
2581 * 32 bit permissive LID = 0xFFFFFFFF
2582 * Multicast LID range = 0xFFFFFFFE to 0xF0000000
2583 * Unicast LID range = 0xEFFFFFFF to 1
2584 * Invalid LID = 0
2585 */
2586 if (ib_is_opa_gid(&grh->dgid))
2587 dlid = opa_get_lid_from_gid(&grh->dgid);
2588 else if ((dlid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) &&
2589 (dlid != be16_to_cpu(IB_LID_PERMISSIVE)) &&
2590 (dlid != be32_to_cpu(OPA_LID_PERMISSIVE)))
2591 dlid = dlid - be16_to_cpu(IB_MULTICAST_LID_BASE) +
2592 opa_get_mcast_base(OPA_MCAST_NR);
2593 else if (dlid == be16_to_cpu(IB_LID_PERMISSIVE))
2594 dlid = be32_to_cpu(OPA_LID_PERMISSIVE);
2595
2596 rdma_ah_set_dlid(attr, dlid);
2597}
2598
2599static inline u8 hfi1_get_packet_type(u32 lid)
2600{
2601 /* 9B if lid > 0xF0000000 */
2602 if (lid >= opa_get_mcast_base(OPA_MCAST_NR))
2603 return HFI1_PKT_TYPE_9B;
2604
2605 /* 16B if lid > 0xC000 */
2606 if (lid >= opa_get_lid(opa_get_mcast_base(OPA_MCAST_NR), 9B))
2607 return HFI1_PKT_TYPE_16B;
2608
2609 return HFI1_PKT_TYPE_9B;
2610}
2611
2612static inline bool hfi1_get_hdr_type(u32 lid, struct rdma_ah_attr *attr)
2613{
2614 /*
2615 * If there was an incoming 16B packet with permissive
2616 * LIDs, OPA GIDs would have been programmed when those
2617 * packets were received. A 16B packet will have to
2618 * be sent in response to that packet. Return a 16B
2619 * header type if that's the case.
2620 */
2621 if (rdma_ah_get_dlid(attr) == be32_to_cpu(OPA_LID_PERMISSIVE))
2622 return (ib_is_opa_gid(&rdma_ah_read_grh(attr)->dgid)) ?
2623 HFI1_PKT_TYPE_16B : HFI1_PKT_TYPE_9B;
2624
2625 /*
2626 * Return a 16B header type if either the the destination
2627 * or source lid is extended.
2628 */
2629 if (hfi1_get_packet_type(rdma_ah_get_dlid(attr)) == HFI1_PKT_TYPE_16B)
2630 return HFI1_PKT_TYPE_16B;
2631
2632 return hfi1_get_packet_type(lid);
2633}
88733e3b
DH		 2634
2635static inline void hfi1_make_ext_grh(struct hfi1_packet *packet,
2636 struct ib_grh *grh, u32 slid,
2637 u32 dlid)
2638{
2639 struct hfi1_ibport *ibp = &packet->rcd->ppd->ibport_data;
2640 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
2641
2642 if (!ibp)
2643 return;
2644
2645 grh->hop_limit = 1;
2646 grh->sgid.global.subnet_prefix = ibp->rvp.gid_prefix;
2647 if (slid == opa_get_lid(be32_to_cpu(OPA_LID_PERMISSIVE), 16B))
2648 grh->sgid.global.interface_id =
2649 OPA_MAKE_ID(be32_to_cpu(OPA_LID_PERMISSIVE));
2650 else
2651 grh->sgid.global.interface_id = OPA_MAKE_ID(slid);
2652
2653 /*
2654 * Upper layers (like mad) may compare the dgid in the
2655 * wc that is obtained here with the sgid_index in
2656 * the wr. Since sgid_index in wr is always 0 for
2657 * extended lids, set the dgid here to the default
2658 * IB gid.
2659 */
2660 grh->dgid.global.subnet_prefix = ibp->rvp.gid_prefix;
2661 grh->dgid.global.interface_id =
2662 cpu_to_be64(ppd->guids[HFI1_PORT_GUID_INDEX]);
2663}
2664
2665static inline int hfi1_get_16b_padding(u32 hdr_size, u32 payload)
2666{
2667 return -(hdr_size + payload + (SIZE_OF_CRC << 2) +
2668 SIZE_OF_LT) & 0x7;
2669}
2670
2671static inline void hfi1_make_ib_hdr(struct ib_header *hdr,
2672 u16 lrh0, u16 len,
2673 u16 dlid, u16 slid)
2674{
2675 hdr->lrh[0] = cpu_to_be16(lrh0);
2676 hdr->lrh[1] = cpu_to_be16(dlid);
2677 hdr->lrh[2] = cpu_to_be16(len);
2678 hdr->lrh[3] = cpu_to_be16(slid);
2679}
2680
2681static inline void hfi1_make_16b_hdr(struct hfi1_16b_header *hdr,
2682 u32 slid, u32 dlid,
2683 u16 len, u16 pkey,
ca85bb1c 2684 bool becn, bool fecn, u8 l4,
88733e3b
DH		 2685 u8 sc)
2686{
2687 u32 lrh0 = 0;
2688 u32 lrh1 = 0x40000000;
2689 u32 lrh2 = 0;
2690 u32 lrh3 = 0;
2691
2692 lrh0 = (lrh0 & ~OPA_16B_BECN_MASK) | (becn << OPA_16B_BECN_SHIFT);
2693 lrh0 = (lrh0 & ~OPA_16B_LEN_MASK) | (len << OPA_16B_LEN_SHIFT);
2694 lrh0 = (lrh0 & ~OPA_16B_LID_MASK) | (slid & OPA_16B_LID_MASK);
2695 lrh1 = (lrh1 & ~OPA_16B_FECN_MASK) | (fecn << OPA_16B_FECN_SHIFT);
2696 lrh1 = (lrh1 & ~OPA_16B_SC_MASK) | (sc << OPA_16B_SC_SHIFT);
2697 lrh1 = (lrh1 & ~OPA_16B_LID_MASK) | (dlid & OPA_16B_LID_MASK);
2698 lrh2 = (lrh2 & ~OPA_16B_SLID_MASK) |
2699 ((slid >> OPA_16B_SLID_SHIFT) << OPA_16B_SLID_HIGH_SHIFT);
2700 lrh2 = (lrh2 & ~OPA_16B_DLID_MASK) |
2701 ((dlid >> OPA_16B_DLID_SHIFT) << OPA_16B_DLID_HIGH_SHIFT);
f59fb9e0 2702 lrh2 = (lrh2 & ~OPA_16B_PKEY_MASK) | ((u32)pkey << OPA_16B_PKEY_SHIFT);
88733e3b
DH		 2703 lrh2 = (lrh2 & ~OPA_16B_L4_MASK) | l4;
2704
2705 hdr->lrh[0] = lrh0;
2706 hdr->lrh[1] = lrh1;
2707 hdr->lrh[2] = lrh2;
2708 hdr->lrh[3] = lrh3;
2709}
77241056 2710#endif /* _HFI1_KERNEL_H */
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