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8ebd4cf1 | 1 | /* |
05d6ac1d | 2 | * Copyright(c) 2015, 2016 Intel Corporation. |
8ebd4cf1 EH |
3 | * |
4 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
5 | * redistributing this file, you may do so under either license. | |
6 | * | |
7 | * GPL LICENSE SUMMARY | |
8 | * | |
8ebd4cf1 EH |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of version 2 of the GNU General Public License as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * BSD LICENSE | |
19 | * | |
8ebd4cf1 EH |
20 | * Redistribution and use in source and binary forms, with or without |
21 | * modification, are permitted provided that the following conditions | |
22 | * are met: | |
23 | * | |
24 | * - Redistributions of source code must retain the above copyright | |
25 | * notice, this list of conditions and the following disclaimer. | |
26 | * - Redistributions in binary form must reproduce the above copyright | |
27 | * notice, this list of conditions and the following disclaimer in | |
28 | * the documentation and/or other materials provided with the | |
29 | * distribution. | |
30 | * - Neither the name of Intel Corporation nor the names of its | |
31 | * contributors may be used to endorse or promote products derived | |
32 | * from this software without specific prior written permission. | |
33 | * | |
34 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
35 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
36 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
37 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
38 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
39 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
40 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
41 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
42 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
43 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
44 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
45 | * | |
46 | */ | |
c3838b39 | 47 | |
8ebd4cf1 | 48 | #include "hfi.h" |
c3838b39 | 49 | #include "efivar.h" |
e83eba21 | 50 | #include "eprom.h" |
c3838b39 EH |
51 | |
52 | void get_platform_config(struct hfi1_devdata *dd) | |
53 | { | |
54 | int ret = 0; | |
55 | unsigned long size = 0; | |
56 | u8 *temp_platform_config = NULL; | |
e83eba21 DL |
57 | u32 esize; |
58 | ||
59 | ret = eprom_read_platform_config(dd, (void **)&temp_platform_config, | |
60 | &esize); | |
61 | if (!ret) { | |
62 | /* success */ | |
63 | size = esize; | |
64 | goto success; | |
65 | } | |
66 | /* fail, try EFI variable */ | |
c3838b39 EH |
67 | |
68 | ret = read_hfi1_efi_var(dd, "configuration", &size, | |
69 | (void **)&temp_platform_config); | |
e83eba21 DL |
70 | if (!ret) |
71 | goto success; | |
c3838b39 | 72 | |
e83eba21 DL |
73 | dd_dev_info(dd, |
74 | "%s: Failed to get platform config from UEFI, falling back to request firmware\n", | |
75 | __func__); | |
76 | /* fall back to request firmware */ | |
77 | platform_config_load = 1; | |
78 | return; | |
79 | ||
80 | success: | |
c3838b39 EH |
81 | dd->platform_config.data = temp_platform_config; |
82 | dd->platform_config.size = size; | |
c3838b39 EH |
83 | } |
84 | ||
85 | void free_platform_config(struct hfi1_devdata *dd) | |
86 | { | |
87 | if (!platform_config_load) { | |
88 | /* | |
89 | * was loaded from EFI, release memory | |
90 | * allocated by read_efi_var | |
91 | */ | |
92 | kfree(dd->platform_config.data); | |
93 | } | |
94 | /* | |
95 | * else do nothing, dispose_firmware will release | |
96 | * struct firmware platform_config on driver exit | |
97 | */ | |
98 | } | |
8ebd4cf1 | 99 | |
9775a991 EH |
100 | void get_port_type(struct hfi1_pportdata *ppd) |
101 | { | |
102 | int ret; | |
103 | ||
104 | ret = get_platform_config_field(ppd->dd, PLATFORM_CONFIG_PORT_TABLE, 0, | |
105 | PORT_TABLE_PORT_TYPE, &ppd->port_type, | |
106 | 4); | |
107 | if (ret) | |
108 | ppd->port_type = PORT_TYPE_UNKNOWN; | |
109 | } | |
110 | ||
8ebd4cf1 EH |
111 | int set_qsfp_tx(struct hfi1_pportdata *ppd, int on) |
112 | { | |
113 | u8 tx_ctrl_byte = on ? 0x0 : 0xF; | |
114 | int ret = 0; | |
115 | ||
116 | ret = qsfp_write(ppd, ppd->dd->hfi1_id, QSFP_TX_CTRL_BYTE_OFFS, | |
117 | &tx_ctrl_byte, 1); | |
118 | /* we expected 1, so consider 0 an error */ | |
119 | if (ret == 0) | |
120 | ret = -EIO; | |
121 | else if (ret == 1) | |
122 | ret = 0; | |
123 | return ret; | |
124 | } | |
125 | ||
126 | static int qual_power(struct hfi1_pportdata *ppd) | |
127 | { | |
128 | u32 cable_power_class = 0, power_class_max = 0; | |
129 | u8 *cache = ppd->qsfp_info.cache; | |
130 | int ret = 0; | |
131 | ||
132 | ret = get_platform_config_field( | |
133 | ppd->dd, PLATFORM_CONFIG_SYSTEM_TABLE, 0, | |
134 | SYSTEM_TABLE_QSFP_POWER_CLASS_MAX, &power_class_max, 4); | |
135 | if (ret) | |
136 | return ret; | |
137 | ||
145dd2b3 | 138 | cable_power_class = get_qsfp_power_class(cache[QSFP_MOD_PWR_OFFS]); |
8ebd4cf1 | 139 | |
145dd2b3 | 140 | if (cable_power_class > power_class_max) |
8ebd4cf1 EH |
141 | ppd->offline_disabled_reason = |
142 | HFI1_ODR_MASK(OPA_LINKDOWN_REASON_POWER_POLICY); | |
8ebd4cf1 EH |
143 | |
144 | if (ppd->offline_disabled_reason == | |
145 | HFI1_ODR_MASK(OPA_LINKDOWN_REASON_POWER_POLICY)) { | |
146 | dd_dev_info( | |
147 | ppd->dd, | |
148 | "%s: Port disabled due to system power restrictions\n", | |
149 | __func__); | |
150 | ret = -EPERM; | |
151 | } | |
152 | return ret; | |
153 | } | |
154 | ||
155 | static int qual_bitrate(struct hfi1_pportdata *ppd) | |
156 | { | |
157 | u16 lss = ppd->link_speed_supported, lse = ppd->link_speed_enabled; | |
158 | u8 *cache = ppd->qsfp_info.cache; | |
159 | ||
160 | if ((lss & OPA_LINK_SPEED_25G) && (lse & OPA_LINK_SPEED_25G) && | |
161 | cache[QSFP_NOM_BIT_RATE_250_OFFS] < 0x64) | |
162 | ppd->offline_disabled_reason = | |
163 | HFI1_ODR_MASK(OPA_LINKDOWN_REASON_LINKSPEED_POLICY); | |
164 | ||
165 | if ((lss & OPA_LINK_SPEED_12_5G) && (lse & OPA_LINK_SPEED_12_5G) && | |
166 | cache[QSFP_NOM_BIT_RATE_100_OFFS] < 0x7D) | |
167 | ppd->offline_disabled_reason = | |
168 | HFI1_ODR_MASK(OPA_LINKDOWN_REASON_LINKSPEED_POLICY); | |
169 | ||
170 | if (ppd->offline_disabled_reason == | |
171 | HFI1_ODR_MASK(OPA_LINKDOWN_REASON_LINKSPEED_POLICY)) { | |
172 | dd_dev_info( | |
173 | ppd->dd, | |
174 | "%s: Cable failed bitrate check, disabling port\n", | |
175 | __func__); | |
176 | return -EPERM; | |
177 | } | |
178 | return 0; | |
179 | } | |
180 | ||
181 | static int set_qsfp_high_power(struct hfi1_pportdata *ppd) | |
182 | { | |
183 | u8 cable_power_class = 0, power_ctrl_byte = 0; | |
184 | u8 *cache = ppd->qsfp_info.cache; | |
185 | int ret; | |
186 | ||
145dd2b3 | 187 | cable_power_class = get_qsfp_power_class(cache[QSFP_MOD_PWR_OFFS]); |
8ebd4cf1 | 188 | |
145dd2b3 | 189 | if (cable_power_class > QSFP_POWER_CLASS_1) { |
8ebd4cf1 EH |
190 | power_ctrl_byte = cache[QSFP_PWR_CTRL_BYTE_OFFS]; |
191 | ||
192 | power_ctrl_byte |= 1; | |
193 | power_ctrl_byte &= ~(0x2); | |
194 | ||
195 | ret = qsfp_write(ppd, ppd->dd->hfi1_id, | |
196 | QSFP_PWR_CTRL_BYTE_OFFS, | |
197 | &power_ctrl_byte, 1); | |
198 | if (ret != 1) | |
199 | return -EIO; | |
200 | ||
145dd2b3 | 201 | if (cable_power_class > QSFP_POWER_CLASS_4) { |
8ebd4cf1 EH |
202 | power_ctrl_byte |= (1 << 2); |
203 | ret = qsfp_write(ppd, ppd->dd->hfi1_id, | |
204 | QSFP_PWR_CTRL_BYTE_OFFS, | |
205 | &power_ctrl_byte, 1); | |
206 | if (ret != 1) | |
207 | return -EIO; | |
208 | } | |
209 | ||
210 | /* SFF 8679 rev 1.7 LPMode Deassert time */ | |
211 | msleep(300); | |
212 | } | |
213 | return 0; | |
214 | } | |
215 | ||
216 | static void apply_rx_cdr(struct hfi1_pportdata *ppd, | |
217 | u32 rx_preset_index, | |
218 | u8 *cdr_ctrl_byte) | |
219 | { | |
220 | u32 rx_preset; | |
221 | u8 *cache = ppd->qsfp_info.cache; | |
145dd2b3 | 222 | int cable_power_class; |
8ebd4cf1 EH |
223 | |
224 | if (!((cache[QSFP_MOD_PWR_OFFS] & 0x4) && | |
225 | (cache[QSFP_CDR_INFO_OFFS] & 0x40))) | |
226 | return; | |
227 | ||
145dd2b3 EH |
228 | /* RX CDR present, bypass supported */ |
229 | cable_power_class = get_qsfp_power_class(cache[QSFP_MOD_PWR_OFFS]); | |
230 | ||
231 | if (cable_power_class <= QSFP_POWER_CLASS_3) { | |
232 | /* Power class <= 3, ignore config & turn RX CDR on */ | |
233 | *cdr_ctrl_byte |= 0xF; | |
234 | return; | |
235 | } | |
236 | ||
8ebd4cf1 EH |
237 | get_platform_config_field( |
238 | ppd->dd, PLATFORM_CONFIG_RX_PRESET_TABLE, | |
239 | rx_preset_index, RX_PRESET_TABLE_QSFP_RX_CDR_APPLY, | |
240 | &rx_preset, 4); | |
241 | ||
242 | if (!rx_preset) { | |
243 | dd_dev_info( | |
244 | ppd->dd, | |
245 | "%s: RX_CDR_APPLY is set to disabled\n", | |
246 | __func__); | |
247 | return; | |
248 | } | |
249 | get_platform_config_field( | |
250 | ppd->dd, PLATFORM_CONFIG_RX_PRESET_TABLE, | |
251 | rx_preset_index, RX_PRESET_TABLE_QSFP_RX_CDR, | |
252 | &rx_preset, 4); | |
253 | ||
254 | /* Expand cdr setting to all 4 lanes */ | |
255 | rx_preset = (rx_preset | (rx_preset << 1) | | |
256 | (rx_preset << 2) | (rx_preset << 3)); | |
257 | ||
258 | if (rx_preset) { | |
259 | *cdr_ctrl_byte |= rx_preset; | |
260 | } else { | |
261 | *cdr_ctrl_byte &= rx_preset; | |
262 | /* Preserve current TX CDR status */ | |
263 | *cdr_ctrl_byte |= (cache[QSFP_CDR_CTRL_BYTE_OFFS] & 0xF0); | |
264 | } | |
265 | } | |
266 | ||
267 | static void apply_tx_cdr(struct hfi1_pportdata *ppd, | |
268 | u32 tx_preset_index, | |
145dd2b3 | 269 | u8 *cdr_ctrl_byte) |
8ebd4cf1 EH |
270 | { |
271 | u32 tx_preset; | |
272 | u8 *cache = ppd->qsfp_info.cache; | |
145dd2b3 | 273 | int cable_power_class; |
8ebd4cf1 EH |
274 | |
275 | if (!((cache[QSFP_MOD_PWR_OFFS] & 0x8) && | |
276 | (cache[QSFP_CDR_INFO_OFFS] & 0x80))) | |
277 | return; | |
278 | ||
145dd2b3 EH |
279 | /* TX CDR present, bypass supported */ |
280 | cable_power_class = get_qsfp_power_class(cache[QSFP_MOD_PWR_OFFS]); | |
281 | ||
282 | if (cable_power_class <= QSFP_POWER_CLASS_3) { | |
283 | /* Power class <= 3, ignore config & turn TX CDR on */ | |
284 | *cdr_ctrl_byte |= 0xF0; | |
285 | return; | |
286 | } | |
287 | ||
8ebd4cf1 EH |
288 | get_platform_config_field( |
289 | ppd->dd, | |
290 | PLATFORM_CONFIG_TX_PRESET_TABLE, tx_preset_index, | |
291 | TX_PRESET_TABLE_QSFP_TX_CDR_APPLY, &tx_preset, 4); | |
292 | ||
293 | if (!tx_preset) { | |
294 | dd_dev_info( | |
295 | ppd->dd, | |
296 | "%s: TX_CDR_APPLY is set to disabled\n", | |
297 | __func__); | |
298 | return; | |
299 | } | |
300 | get_platform_config_field( | |
301 | ppd->dd, | |
302 | PLATFORM_CONFIG_TX_PRESET_TABLE, | |
303 | tx_preset_index, | |
304 | TX_PRESET_TABLE_QSFP_TX_CDR, &tx_preset, 4); | |
305 | ||
306 | /* Expand cdr setting to all 4 lanes */ | |
307 | tx_preset = (tx_preset | (tx_preset << 1) | | |
308 | (tx_preset << 2) | (tx_preset << 3)); | |
309 | ||
310 | if (tx_preset) | |
145dd2b3 | 311 | *cdr_ctrl_byte |= (tx_preset << 4); |
8ebd4cf1 EH |
312 | else |
313 | /* Preserve current/determined RX CDR status */ | |
145dd2b3 | 314 | *cdr_ctrl_byte &= ((tx_preset << 4) | 0xF); |
8ebd4cf1 EH |
315 | } |
316 | ||
317 | static void apply_cdr_settings( | |
318 | struct hfi1_pportdata *ppd, u32 rx_preset_index, | |
319 | u32 tx_preset_index) | |
320 | { | |
321 | u8 *cache = ppd->qsfp_info.cache; | |
322 | u8 cdr_ctrl_byte = cache[QSFP_CDR_CTRL_BYTE_OFFS]; | |
323 | ||
324 | apply_rx_cdr(ppd, rx_preset_index, &cdr_ctrl_byte); | |
325 | ||
326 | apply_tx_cdr(ppd, tx_preset_index, &cdr_ctrl_byte); | |
327 | ||
328 | qsfp_write(ppd, ppd->dd->hfi1_id, QSFP_CDR_CTRL_BYTE_OFFS, | |
329 | &cdr_ctrl_byte, 1); | |
330 | } | |
331 | ||
332 | static void apply_tx_eq_auto(struct hfi1_pportdata *ppd) | |
333 | { | |
334 | u8 *cache = ppd->qsfp_info.cache; | |
335 | u8 tx_eq; | |
336 | ||
337 | if (!(cache[QSFP_EQ_INFO_OFFS] & 0x8)) | |
338 | return; | |
339 | /* Disable adaptive TX EQ if present */ | |
340 | tx_eq = cache[(128 * 3) + 241]; | |
341 | tx_eq &= 0xF0; | |
342 | qsfp_write(ppd, ppd->dd->hfi1_id, (256 * 3) + 241, &tx_eq, 1); | |
343 | } | |
344 | ||
345 | static void apply_tx_eq_prog(struct hfi1_pportdata *ppd, u32 tx_preset_index) | |
346 | { | |
347 | u8 *cache = ppd->qsfp_info.cache; | |
348 | u32 tx_preset; | |
349 | u8 tx_eq; | |
350 | ||
351 | if (!(cache[QSFP_EQ_INFO_OFFS] & 0x4)) | |
352 | return; | |
353 | ||
354 | get_platform_config_field( | |
355 | ppd->dd, PLATFORM_CONFIG_TX_PRESET_TABLE, | |
356 | tx_preset_index, TX_PRESET_TABLE_QSFP_TX_EQ_APPLY, | |
357 | &tx_preset, 4); | |
358 | if (!tx_preset) { | |
359 | dd_dev_info( | |
360 | ppd->dd, | |
361 | "%s: TX_EQ_APPLY is set to disabled\n", | |
362 | __func__); | |
363 | return; | |
364 | } | |
365 | get_platform_config_field( | |
366 | ppd->dd, PLATFORM_CONFIG_TX_PRESET_TABLE, | |
367 | tx_preset_index, TX_PRESET_TABLE_QSFP_TX_EQ, | |
368 | &tx_preset, 4); | |
369 | ||
370 | if (((cache[(128 * 3) + 224] & 0xF0) >> 4) < tx_preset) { | |
371 | dd_dev_info( | |
372 | ppd->dd, | |
373 | "%s: TX EQ %x unsupported\n", | |
374 | __func__, tx_preset); | |
375 | ||
376 | dd_dev_info( | |
377 | ppd->dd, | |
378 | "%s: Applying EQ %x\n", | |
379 | __func__, cache[608] & 0xF0); | |
380 | ||
381 | tx_preset = (cache[608] & 0xF0) >> 4; | |
382 | } | |
383 | ||
384 | tx_eq = tx_preset | (tx_preset << 4); | |
385 | qsfp_write(ppd, ppd->dd->hfi1_id, (256 * 3) + 234, &tx_eq, 1); | |
386 | qsfp_write(ppd, ppd->dd->hfi1_id, (256 * 3) + 235, &tx_eq, 1); | |
387 | } | |
388 | ||
389 | static void apply_rx_eq_emp(struct hfi1_pportdata *ppd, u32 rx_preset_index) | |
390 | { | |
391 | u32 rx_preset; | |
392 | u8 rx_eq, *cache = ppd->qsfp_info.cache; | |
393 | ||
394 | if (!(cache[QSFP_EQ_INFO_OFFS] & 0x2)) | |
395 | return; | |
396 | get_platform_config_field( | |
397 | ppd->dd, PLATFORM_CONFIG_RX_PRESET_TABLE, | |
398 | rx_preset_index, RX_PRESET_TABLE_QSFP_RX_EMP_APPLY, | |
399 | &rx_preset, 4); | |
400 | ||
401 | if (!rx_preset) { | |
402 | dd_dev_info( | |
403 | ppd->dd, | |
404 | "%s: RX_EMP_APPLY is set to disabled\n", | |
405 | __func__); | |
406 | return; | |
407 | } | |
408 | get_platform_config_field( | |
409 | ppd->dd, PLATFORM_CONFIG_RX_PRESET_TABLE, | |
410 | rx_preset_index, RX_PRESET_TABLE_QSFP_RX_EMP, | |
411 | &rx_preset, 4); | |
412 | ||
413 | if ((cache[(128 * 3) + 224] & 0xF) < rx_preset) { | |
414 | dd_dev_info( | |
415 | ppd->dd, | |
416 | "%s: Requested RX EMP %x\n", | |
417 | __func__, rx_preset); | |
418 | ||
419 | dd_dev_info( | |
420 | ppd->dd, | |
421 | "%s: Applying supported EMP %x\n", | |
422 | __func__, cache[608] & 0xF); | |
423 | ||
424 | rx_preset = cache[608] & 0xF; | |
425 | } | |
426 | ||
427 | rx_eq = rx_preset | (rx_preset << 4); | |
428 | ||
429 | qsfp_write(ppd, ppd->dd->hfi1_id, (256 * 3) + 236, &rx_eq, 1); | |
430 | qsfp_write(ppd, ppd->dd->hfi1_id, (256 * 3) + 237, &rx_eq, 1); | |
431 | } | |
432 | ||
433 | static void apply_eq_settings(struct hfi1_pportdata *ppd, | |
434 | u32 rx_preset_index, u32 tx_preset_index) | |
435 | { | |
436 | u8 *cache = ppd->qsfp_info.cache; | |
437 | ||
438 | /* no point going on w/o a page 3 */ | |
439 | if (cache[2] & 4) { | |
440 | dd_dev_info(ppd->dd, | |
441 | "%s: Upper page 03 not present\n", | |
442 | __func__); | |
443 | return; | |
444 | } | |
445 | ||
446 | apply_tx_eq_auto(ppd); | |
447 | ||
448 | apply_tx_eq_prog(ppd, tx_preset_index); | |
449 | ||
450 | apply_rx_eq_emp(ppd, rx_preset_index); | |
451 | } | |
452 | ||
453 | static void apply_rx_amplitude_settings( | |
454 | struct hfi1_pportdata *ppd, u32 rx_preset_index, | |
455 | u32 tx_preset_index) | |
456 | { | |
457 | u32 rx_preset; | |
458 | u8 rx_amp = 0, i = 0, preferred = 0, *cache = ppd->qsfp_info.cache; | |
459 | ||
460 | /* no point going on w/o a page 3 */ | |
461 | if (cache[2] & 4) { | |
462 | dd_dev_info(ppd->dd, | |
463 | "%s: Upper page 03 not present\n", | |
464 | __func__); | |
465 | return; | |
466 | } | |
467 | if (!(cache[QSFP_EQ_INFO_OFFS] & 0x1)) { | |
468 | dd_dev_info(ppd->dd, | |
469 | "%s: RX_AMP_APPLY is set to disabled\n", | |
470 | __func__); | |
471 | return; | |
472 | } | |
473 | ||
474 | get_platform_config_field(ppd->dd, | |
475 | PLATFORM_CONFIG_RX_PRESET_TABLE, | |
476 | rx_preset_index, | |
477 | RX_PRESET_TABLE_QSFP_RX_AMP_APPLY, | |
478 | &rx_preset, 4); | |
479 | ||
480 | if (!rx_preset) { | |
481 | dd_dev_info(ppd->dd, | |
482 | "%s: RX_AMP_APPLY is set to disabled\n", | |
483 | __func__); | |
484 | return; | |
485 | } | |
486 | get_platform_config_field(ppd->dd, | |
487 | PLATFORM_CONFIG_RX_PRESET_TABLE, | |
488 | rx_preset_index, | |
489 | RX_PRESET_TABLE_QSFP_RX_AMP, | |
490 | &rx_preset, 4); | |
491 | ||
492 | dd_dev_info(ppd->dd, | |
493 | "%s: Requested RX AMP %x\n", | |
494 | __func__, | |
495 | rx_preset); | |
496 | ||
497 | for (i = 0; i < 4; i++) { | |
498 | if (cache[(128 * 3) + 225] & (1 << i)) { | |
499 | preferred = i; | |
500 | if (preferred == rx_preset) | |
501 | break; | |
502 | } | |
503 | } | |
504 | ||
505 | /* | |
506 | * Verify that preferred RX amplitude is not just a | |
507 | * fall through of the default | |
508 | */ | |
509 | if (!preferred && !(cache[(128 * 3) + 225] & 0x1)) { | |
510 | dd_dev_info(ppd->dd, "No supported RX AMP, not applying\n"); | |
511 | return; | |
512 | } | |
513 | ||
514 | dd_dev_info(ppd->dd, | |
515 | "%s: Applying RX AMP %x\n", __func__, preferred); | |
516 | ||
517 | rx_amp = preferred | (preferred << 4); | |
518 | qsfp_write(ppd, ppd->dd->hfi1_id, (256 * 3) + 238, &rx_amp, 1); | |
519 | qsfp_write(ppd, ppd->dd->hfi1_id, (256 * 3) + 239, &rx_amp, 1); | |
520 | } | |
521 | ||
522 | #define OPA_INVALID_INDEX 0xFFF | |
523 | ||
97167e81 EH |
524 | static void apply_tx_lanes(struct hfi1_pportdata *ppd, u8 field_id, |
525 | u32 config_data, const char *message) | |
8ebd4cf1 EH |
526 | { |
527 | u8 i; | |
528 | int ret = HCMD_SUCCESS; | |
529 | ||
530 | for (i = 0; i < 4; i++) { | |
97167e81 | 531 | ret = load_8051_config(ppd->dd, field_id, i, config_data); |
8ebd4cf1 EH |
532 | if (ret != HCMD_SUCCESS) { |
533 | dd_dev_err( | |
534 | ppd->dd, | |
535 | "%s: %s for lane %u failed\n", | |
536 | message, __func__, i); | |
537 | } | |
538 | } | |
539 | } | |
540 | ||
541 | static void apply_tunings( | |
542 | struct hfi1_pportdata *ppd, u32 tx_preset_index, | |
543 | u8 tuning_method, u32 total_atten, u8 limiting_active) | |
544 | { | |
545 | int ret = 0; | |
546 | u32 config_data = 0, tx_preset = 0; | |
547 | u8 precur = 0, attn = 0, postcur = 0, external_device_config = 0; | |
548 | u8 *cache = ppd->qsfp_info.cache; | |
549 | ||
97167e81 | 550 | /* Pass tuning method to 8051 */ |
8ebd4cf1 EH |
551 | read_8051_config(ppd->dd, LINK_TUNING_PARAMETERS, GENERAL_CONFIG, |
552 | &config_data); | |
f6de3d39 DL |
553 | config_data &= ~(0xff << TUNING_METHOD_SHIFT); |
554 | config_data |= ((u32)tuning_method << TUNING_METHOD_SHIFT); | |
8ebd4cf1 EH |
555 | ret = load_8051_config(ppd->dd, LINK_TUNING_PARAMETERS, GENERAL_CONFIG, |
556 | config_data); | |
557 | if (ret != HCMD_SUCCESS) | |
558 | dd_dev_err(ppd->dd, "%s: Failed to set tuning method\n", | |
559 | __func__); | |
560 | ||
97167e81 EH |
561 | /* Set same channel loss for both TX and RX */ |
562 | config_data = 0 | (total_atten << 16) | (total_atten << 24); | |
563 | apply_tx_lanes(ppd, CHANNEL_LOSS_SETTINGS, config_data, | |
564 | "Setting channel loss"); | |
565 | ||
566 | /* Inform 8051 of cable capabilities */ | |
567 | if (ppd->qsfp_info.cache_valid) { | |
568 | external_device_config = | |
569 | ((cache[QSFP_MOD_PWR_OFFS] & 0x4) << 3) | | |
570 | ((cache[QSFP_MOD_PWR_OFFS] & 0x8) << 2) | | |
571 | ((cache[QSFP_EQ_INFO_OFFS] & 0x2) << 1) | | |
572 | (cache[QSFP_EQ_INFO_OFFS] & 0x4); | |
573 | ret = read_8051_config(ppd->dd, DC_HOST_COMM_SETTINGS, | |
574 | GENERAL_CONFIG, &config_data); | |
575 | /* Clear, then set the external device config field */ | |
27a340f6 EH |
576 | config_data &= ~(u32)0xFF; |
577 | config_data |= external_device_config; | |
97167e81 EH |
578 | ret = load_8051_config(ppd->dd, DC_HOST_COMM_SETTINGS, |
579 | GENERAL_CONFIG, config_data); | |
580 | if (ret != HCMD_SUCCESS) | |
581 | dd_dev_info(ppd->dd, | |
582 | "%s: Failed set ext device config params\n", | |
583 | __func__); | |
584 | } | |
8ebd4cf1 | 585 | |
97167e81 EH |
586 | if (tx_preset_index == OPA_INVALID_INDEX) { |
587 | if (ppd->port_type == PORT_TYPE_QSFP && limiting_active) | |
588 | dd_dev_info(ppd->dd, "%s: Invalid Tx preset index\n", | |
589 | __func__); | |
8ebd4cf1 | 590 | return; |
97167e81 | 591 | } |
8ebd4cf1 | 592 | |
97167e81 | 593 | /* Following for limiting active channels only */ |
8ebd4cf1 EH |
594 | get_platform_config_field( |
595 | ppd->dd, PLATFORM_CONFIG_TX_PRESET_TABLE, tx_preset_index, | |
596 | TX_PRESET_TABLE_PRECUR, &tx_preset, 4); | |
597 | precur = tx_preset; | |
598 | ||
599 | get_platform_config_field( | |
600 | ppd->dd, PLATFORM_CONFIG_TX_PRESET_TABLE, | |
601 | tx_preset_index, TX_PRESET_TABLE_ATTN, &tx_preset, 4); | |
602 | attn = tx_preset; | |
603 | ||
604 | get_platform_config_field( | |
605 | ppd->dd, PLATFORM_CONFIG_TX_PRESET_TABLE, | |
606 | tx_preset_index, TX_PRESET_TABLE_POSTCUR, &tx_preset, 4); | |
607 | postcur = tx_preset; | |
608 | ||
609 | config_data = precur | (attn << 8) | (postcur << 16); | |
610 | ||
97167e81 EH |
611 | apply_tx_lanes(ppd, TX_EQ_SETTINGS, config_data, |
612 | "Applying TX settings"); | |
8ebd4cf1 EH |
613 | } |
614 | ||
e4e0e39c | 615 | /* Must be holding the QSFP i2c resource */ |
8ebd4cf1 EH |
616 | static int tune_active_qsfp(struct hfi1_pportdata *ppd, u32 *ptr_tx_preset, |
617 | u32 *ptr_rx_preset, u32 *ptr_total_atten) | |
618 | { | |
765a6fac | 619 | int ret; |
8ebd4cf1 EH |
620 | u16 lss = ppd->link_speed_supported, lse = ppd->link_speed_enabled; |
621 | u8 *cache = ppd->qsfp_info.cache; | |
622 | ||
623 | ppd->qsfp_info.limiting_active = 1; | |
624 | ||
625 | ret = set_qsfp_tx(ppd, 0); | |
626 | if (ret) | |
e4e0e39c | 627 | return ret; |
8ebd4cf1 EH |
628 | |
629 | ret = qual_power(ppd); | |
630 | if (ret) | |
e4e0e39c | 631 | return ret; |
8ebd4cf1 EH |
632 | |
633 | ret = qual_bitrate(ppd); | |
634 | if (ret) | |
e4e0e39c | 635 | return ret; |
8ebd4cf1 | 636 | |
b5e71019 EH |
637 | /* |
638 | * We'll change the QSFP memory contents from here on out, thus we set a | |
639 | * flag here to remind ourselves to reset the QSFP module. This prevents | |
640 | * reuse of stale settings established in our previous pass through. | |
641 | */ | |
8ebd4cf1 EH |
642 | if (ppd->qsfp_info.reset_needed) { |
643 | reset_qsfp(ppd); | |
8ebd4cf1 EH |
644 | refresh_qsfp_cache(ppd, &ppd->qsfp_info); |
645 | } else { | |
646 | ppd->qsfp_info.reset_needed = 1; | |
647 | } | |
648 | ||
649 | ret = set_qsfp_high_power(ppd); | |
650 | if (ret) | |
e4e0e39c | 651 | return ret; |
8ebd4cf1 EH |
652 | |
653 | if (cache[QSFP_EQ_INFO_OFFS] & 0x4) { | |
654 | ret = get_platform_config_field( | |
655 | ppd->dd, | |
656 | PLATFORM_CONFIG_PORT_TABLE, 0, | |
657 | PORT_TABLE_TX_PRESET_IDX_ACTIVE_EQ, | |
658 | ptr_tx_preset, 4); | |
659 | if (ret) { | |
660 | *ptr_tx_preset = OPA_INVALID_INDEX; | |
e4e0e39c | 661 | return ret; |
8ebd4cf1 EH |
662 | } |
663 | } else { | |
664 | ret = get_platform_config_field( | |
665 | ppd->dd, | |
666 | PLATFORM_CONFIG_PORT_TABLE, 0, | |
667 | PORT_TABLE_TX_PRESET_IDX_ACTIVE_NO_EQ, | |
668 | ptr_tx_preset, 4); | |
669 | if (ret) { | |
670 | *ptr_tx_preset = OPA_INVALID_INDEX; | |
e4e0e39c | 671 | return ret; |
8ebd4cf1 EH |
672 | } |
673 | } | |
674 | ||
675 | ret = get_platform_config_field( | |
676 | ppd->dd, PLATFORM_CONFIG_PORT_TABLE, 0, | |
677 | PORT_TABLE_RX_PRESET_IDX, ptr_rx_preset, 4); | |
678 | if (ret) { | |
679 | *ptr_rx_preset = OPA_INVALID_INDEX; | |
e4e0e39c | 680 | return ret; |
8ebd4cf1 EH |
681 | } |
682 | ||
683 | if ((lss & OPA_LINK_SPEED_25G) && (lse & OPA_LINK_SPEED_25G)) | |
684 | get_platform_config_field( | |
685 | ppd->dd, PLATFORM_CONFIG_PORT_TABLE, 0, | |
686 | PORT_TABLE_LOCAL_ATTEN_25G, ptr_total_atten, 4); | |
687 | else if ((lss & OPA_LINK_SPEED_12_5G) && (lse & OPA_LINK_SPEED_12_5G)) | |
688 | get_platform_config_field( | |
689 | ppd->dd, PLATFORM_CONFIG_PORT_TABLE, 0, | |
690 | PORT_TABLE_LOCAL_ATTEN_12G, ptr_total_atten, 4); | |
691 | ||
692 | apply_cdr_settings(ppd, *ptr_rx_preset, *ptr_tx_preset); | |
693 | ||
694 | apply_eq_settings(ppd, *ptr_rx_preset, *ptr_tx_preset); | |
695 | ||
696 | apply_rx_amplitude_settings(ppd, *ptr_rx_preset, *ptr_tx_preset); | |
697 | ||
698 | ret = set_qsfp_tx(ppd, 1); | |
765a6fac | 699 | |
8ebd4cf1 EH |
700 | return ret; |
701 | } | |
702 | ||
703 | static int tune_qsfp(struct hfi1_pportdata *ppd, | |
704 | u32 *ptr_tx_preset, u32 *ptr_rx_preset, | |
705 | u8 *ptr_tuning_method, u32 *ptr_total_atten) | |
706 | { | |
707 | u32 cable_atten = 0, remote_atten = 0, platform_atten = 0; | |
708 | u16 lss = ppd->link_speed_supported, lse = ppd->link_speed_enabled; | |
709 | int ret = 0; | |
710 | u8 *cache = ppd->qsfp_info.cache; | |
711 | ||
712 | switch ((cache[QSFP_MOD_TECH_OFFS] & 0xF0) >> 4) { | |
713 | case 0xA ... 0xB: | |
714 | ret = get_platform_config_field( | |
715 | ppd->dd, | |
716 | PLATFORM_CONFIG_PORT_TABLE, 0, | |
717 | PORT_TABLE_LOCAL_ATTEN_25G, | |
718 | &platform_atten, 4); | |
719 | if (ret) | |
720 | return ret; | |
721 | ||
722 | if ((lss & OPA_LINK_SPEED_25G) && (lse & OPA_LINK_SPEED_25G)) | |
723 | cable_atten = cache[QSFP_CU_ATTEN_12G_OFFS]; | |
724 | else if ((lss & OPA_LINK_SPEED_12_5G) && | |
725 | (lse & OPA_LINK_SPEED_12_5G)) | |
726 | cable_atten = cache[QSFP_CU_ATTEN_7G_OFFS]; | |
727 | ||
728 | /* Fallback to configured attenuation if cable memory is bad */ | |
729 | if (cable_atten == 0 || cable_atten > 36) { | |
730 | ret = get_platform_config_field( | |
731 | ppd->dd, | |
732 | PLATFORM_CONFIG_SYSTEM_TABLE, 0, | |
733 | SYSTEM_TABLE_QSFP_ATTENUATION_DEFAULT_25G, | |
734 | &cable_atten, 4); | |
735 | if (ret) | |
736 | return ret; | |
737 | } | |
738 | ||
739 | ret = get_platform_config_field( | |
740 | ppd->dd, PLATFORM_CONFIG_PORT_TABLE, 0, | |
741 | PORT_TABLE_REMOTE_ATTEN_25G, &remote_atten, 4); | |
742 | if (ret) | |
743 | return ret; | |
744 | ||
745 | *ptr_total_atten = platform_atten + cable_atten + remote_atten; | |
746 | ||
747 | *ptr_tuning_method = OPA_PASSIVE_TUNING; | |
748 | break; | |
749 | case 0x0 ... 0x9: /* fallthrough */ | |
750 | case 0xC: /* fallthrough */ | |
751 | case 0xE: | |
752 | ret = tune_active_qsfp(ppd, ptr_tx_preset, ptr_rx_preset, | |
753 | ptr_total_atten); | |
754 | if (ret) | |
755 | return ret; | |
756 | ||
757 | *ptr_tuning_method = OPA_ACTIVE_TUNING; | |
758 | break; | |
759 | case 0xD: /* fallthrough */ | |
760 | case 0xF: | |
761 | default: | |
762 | dd_dev_info(ppd->dd, "%s: Unknown/unsupported cable\n", | |
763 | __func__); | |
764 | break; | |
765 | } | |
766 | return ret; | |
767 | } | |
768 | ||
769 | /* | |
770 | * This function communicates its success or failure via ppd->driver_link_ready | |
771 | * Thus, it depends on its association with start_link(...) which checks | |
772 | * driver_link_ready before proceeding with the link negotiation and | |
773 | * initialization process. | |
774 | */ | |
775 | void tune_serdes(struct hfi1_pportdata *ppd) | |
776 | { | |
777 | int ret = 0; | |
778 | u32 total_atten = 0; | |
779 | u32 remote_atten = 0, platform_atten = 0; | |
780 | u32 rx_preset_index, tx_preset_index; | |
97167e81 | 781 | u8 tuning_method = 0, limiting_active = 0; |
8ebd4cf1 EH |
782 | struct hfi1_devdata *dd = ppd->dd; |
783 | ||
784 | rx_preset_index = OPA_INVALID_INDEX; | |
785 | tx_preset_index = OPA_INVALID_INDEX; | |
786 | ||
787 | /* the link defaults to enabled */ | |
788 | ppd->link_enabled = 1; | |
789 | /* the driver link ready state defaults to not ready */ | |
790 | ppd->driver_link_ready = 0; | |
791 | ppd->offline_disabled_reason = HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE); | |
792 | ||
715c430c EH |
793 | /* Skip the tuning for testing (loopback != none) and simulations */ |
794 | if (loopback != LOOPBACK_NONE || | |
c3838b39 | 795 | ppd->dd->icode == ICODE_FUNCTIONAL_SIMULATOR) { |
8ebd4cf1 EH |
796 | ppd->driver_link_ready = 1; |
797 | return; | |
798 | } | |
799 | ||
8ebd4cf1 EH |
800 | switch (ppd->port_type) { |
801 | case PORT_TYPE_DISCONNECTED: | |
802 | ppd->offline_disabled_reason = | |
803 | HFI1_ODR_MASK(OPA_LINKDOWN_REASON_DISCONNECTED); | |
804 | dd_dev_info(dd, "%s: Port disconnected, disabling port\n", | |
805 | __func__); | |
806 | goto bail; | |
807 | case PORT_TYPE_FIXED: | |
808 | /* platform_atten, remote_atten pre-zeroed to catch error */ | |
809 | get_platform_config_field( | |
810 | ppd->dd, PLATFORM_CONFIG_PORT_TABLE, 0, | |
811 | PORT_TABLE_LOCAL_ATTEN_25G, &platform_atten, 4); | |
812 | ||
813 | get_platform_config_field( | |
814 | ppd->dd, PLATFORM_CONFIG_PORT_TABLE, 0, | |
815 | PORT_TABLE_REMOTE_ATTEN_25G, &remote_atten, 4); | |
816 | ||
817 | total_atten = platform_atten + remote_atten; | |
818 | ||
819 | tuning_method = OPA_PASSIVE_TUNING; | |
820 | break; | |
821 | case PORT_TYPE_VARIABLE: | |
822 | if (qsfp_mod_present(ppd)) { | |
823 | /* | |
824 | * platform_atten, remote_atten pre-zeroed to | |
825 | * catch error | |
826 | */ | |
827 | get_platform_config_field( | |
828 | ppd->dd, PLATFORM_CONFIG_PORT_TABLE, 0, | |
829 | PORT_TABLE_LOCAL_ATTEN_25G, | |
830 | &platform_atten, 4); | |
831 | ||
832 | get_platform_config_field( | |
833 | ppd->dd, PLATFORM_CONFIG_PORT_TABLE, 0, | |
834 | PORT_TABLE_REMOTE_ATTEN_25G, | |
835 | &remote_atten, 4); | |
836 | ||
837 | total_atten = platform_atten + remote_atten; | |
838 | ||
839 | tuning_method = OPA_PASSIVE_TUNING; | |
623bba2d | 840 | } else { |
8ebd4cf1 EH |
841 | ppd->offline_disabled_reason = |
842 | HFI1_ODR_MASK(OPA_LINKDOWN_REASON_CHASSIS_CONFIG); | |
623bba2d EH |
843 | goto bail; |
844 | } | |
8ebd4cf1 EH |
845 | break; |
846 | case PORT_TYPE_QSFP: | |
847 | if (qsfp_mod_present(ppd)) { | |
e4e0e39c DL |
848 | ret = acquire_chip_resource(ppd->dd, |
849 | qsfp_resource(ppd->dd), | |
850 | QSFP_WAIT); | |
851 | if (ret) { | |
852 | dd_dev_err(ppd->dd, "%s: hfi%d: cannot lock i2c chain\n", | |
853 | __func__, (int)ppd->dd->hfi1_id); | |
854 | goto bail; | |
855 | } | |
8ebd4cf1 EH |
856 | refresh_qsfp_cache(ppd, &ppd->qsfp_info); |
857 | ||
858 | if (ppd->qsfp_info.cache_valid) { | |
859 | ret = tune_qsfp(ppd, | |
860 | &tx_preset_index, | |
861 | &rx_preset_index, | |
862 | &tuning_method, | |
863 | &total_atten); | |
c3838b39 EH |
864 | |
865 | /* | |
866 | * We may have modified the QSFP memory, so | |
867 | * update the cache to reflect the changes | |
868 | */ | |
869 | refresh_qsfp_cache(ppd, &ppd->qsfp_info); | |
97167e81 EH |
870 | limiting_active = |
871 | ppd->qsfp_info.limiting_active; | |
8ebd4cf1 EH |
872 | } else { |
873 | dd_dev_err(dd, | |
874 | "%s: Reading QSFP memory failed\n", | |
875 | __func__); | |
e4e0e39c | 876 | ret = -EINVAL; /* a fail indication */ |
8ebd4cf1 | 877 | } |
e4e0e39c DL |
878 | release_chip_resource(ppd->dd, qsfp_resource(ppd->dd)); |
879 | if (ret) | |
880 | goto bail; | |
623bba2d | 881 | } else { |
8ebd4cf1 EH |
882 | ppd->offline_disabled_reason = |
883 | HFI1_ODR_MASK( | |
e1bf0d5e | 884 | OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED); |
623bba2d EH |
885 | goto bail; |
886 | } | |
8ebd4cf1 EH |
887 | break; |
888 | default: | |
889 | dd_dev_info(ppd->dd, "%s: Unknown port type\n", __func__); | |
97167e81 EH |
890 | ppd->port_type = PORT_TYPE_UNKNOWN; |
891 | tuning_method = OPA_UNKNOWN_TUNING; | |
892 | total_atten = 0; | |
893 | limiting_active = 0; | |
894 | tx_preset_index = OPA_INVALID_INDEX; | |
895 | break; | |
8ebd4cf1 | 896 | } |
97167e81 | 897 | |
8ebd4cf1 EH |
898 | if (ppd->offline_disabled_reason == |
899 | HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE)) | |
900 | apply_tunings(ppd, tx_preset_index, tuning_method, | |
97167e81 | 901 | total_atten, limiting_active); |
8ebd4cf1 | 902 | |
c3838b39 EH |
903 | if (!ret) |
904 | ppd->driver_link_ready = 1; | |
8ebd4cf1 EH |
905 | |
906 | return; | |
907 | bail: | |
908 | ppd->driver_link_ready = 0; | |
909 | } |