]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - drivers/infiniband/hw/hns/hns_roce_device.h
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
RDMA/hns: Fix inconsistent warning
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / hns / hns_roce_device.h
CommitLineData
9a443537 1/*
2 * Copyright (c) 2016 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef _HNS_ROCE_DEVICE_H
34#define _HNS_ROCE_DEVICE_H
35
36#include <rdma/ib_verbs.h>
37
38#define DRV_NAME "hns_roce"
39
8f3e9f3e
WHX		 40#define HNS_ROCE_HW_VER1 ('h' << 24 | 'i' << 16 | '0' << 8 | '6')
41
9a443537 42#define MAC_ADDR_OCTET_NUM 6
43#define HNS_ROCE_MAX_MSG_LEN 0x80000000
44
45#define HNS_ROCE_ALOGN_UP(a, b) ((((a) + (b) - 1) / (b)) * (b))
46
47#define HNS_ROCE_IB_MIN_SQ_STRIDE 6
48
49#define HNS_ROCE_BA_SIZE (32 * 4096)
50
51/* Hardware specification only for v1 engine */
52#define HNS_ROCE_MIN_CQE_NUM 0x40
53#define HNS_ROCE_MIN_WQE_NUM 0x20
54
55/* Hardware specification only for v1 engine */
56#define HNS_ROCE_MAX_INNER_MTPT_NUM 0x7
57#define HNS_ROCE_MAX_MTPT_PBL_NUM 0x100000
58
afb6b092
SX		 59#define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS 20
60#define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT \
61 (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS)
62#define HNS_ROCE_CQE_WCMD_EMPTY_BIT 0x2
63#define HNS_ROCE_MIN_CQE_CNT 16
64
9a443537 65#define HNS_ROCE_MAX_IRQ_NUM 34
66
67#define HNS_ROCE_COMP_VEC_NUM 32
68
69#define HNS_ROCE_AEQE_VEC_NUM 1
70#define HNS_ROCE_AEQE_OF_VEC_NUM 1
71
72/* 4G/4K = 1M */
ac11125b 73#define HNS_ROCE_SL_SHIFT 28
9a443537 74#define HNS_ROCE_TCLASS_SHIFT 20
75#define HNS_ROCE_FLOW_LABLE_MASK 0xfffff
76
77#define HNS_ROCE_MAX_PORTS 6
78#define HNS_ROCE_MAX_GID_NUM 16
79#define HNS_ROCE_GID_SIZE 16
80
a25d13cb
SX		 81#define HNS_ROCE_HOP_NUM_0 0xff
82
5e6ff78a
WHX		 83#define BITMAP_NO_RR 0
84#define BITMAP_RR 1
85
9a443537 86#define MR_TYPE_MR 0x00
87#define MR_TYPE_DMA 0x03
88
89#define PKEY_ID 0xffff
31644665 90#define GUID_LEN 8
9a443537 91#define NODE_DESC_SIZE 64
509bf0c2 92#define DB_REG_OFFSET 0x1000
9a443537 93
94#define SERV_TYPE_RC 0
95#define SERV_TYPE_RD 1
96#define SERV_TYPE_UC 2
97#define SERV_TYPE_UD 3
98
99#define PAGES_SHIFT_8 8
100#define PAGES_SHIFT_16 16
101#define PAGES_SHIFT_24 24
102#define PAGES_SHIFT_32 32
103
104enum hns_roce_qp_state {
105 HNS_ROCE_QP_STATE_RST,
106 HNS_ROCE_QP_STATE_INIT,
107 HNS_ROCE_QP_STATE_RTR,
108 HNS_ROCE_QP_STATE_RTS,
109 HNS_ROCE_QP_STATE_SQD,
110 HNS_ROCE_QP_STATE_ERR,
111 HNS_ROCE_QP_NUM_STATE,
112};
113
114enum hns_roce_event {
115 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01,
116 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02,
117 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03,
118 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04,
119 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
120 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06,
121 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07,
122 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08,
123 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09,
124 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a,
125 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b,
126 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c,
127 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d,
128 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f,
129 /* 0x10 and 0x11 is unused in currently application case */
130 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12,
131 HNS_ROCE_EVENT_TYPE_MB = 0x13,
132 HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW = 0x14,
133};
134
135/* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */
136enum {
137 HNS_ROCE_LWQCE_QPC_ERROR = 1,
138 HNS_ROCE_LWQCE_MTU_ERROR = 2,
139 HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR = 3,
140 HNS_ROCE_LWQCE_WQE_ADDR_ERROR = 4,
141 HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR = 5,
142 HNS_ROCE_LWQCE_SL_ERROR = 6,
143 HNS_ROCE_LWQCE_PORT_ERROR = 7,
144};
145
146/* Local Access Violation Work Queue Error,SUBTYPE 0x7 */
147enum {
148 HNS_ROCE_LAVWQE_R_KEY_VIOLATION = 1,
149 HNS_ROCE_LAVWQE_LENGTH_ERROR = 2,
150 HNS_ROCE_LAVWQE_VA_ERROR = 3,
151 HNS_ROCE_LAVWQE_PD_ERROR = 4,
152 HNS_ROCE_LAVWQE_RW_ACC_ERROR = 5,
153 HNS_ROCE_LAVWQE_KEY_STATE_ERROR = 6,
154 HNS_ROCE_LAVWQE_MR_OPERATION_ERROR = 7,
155};
156
157/* DOORBELL overflow subtype */
158enum {
159 HNS_ROCE_DB_SUBTYPE_SDB_OVF = 1,
160 HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF = 2,
161 HNS_ROCE_DB_SUBTYPE_ODB_OVF = 3,
162 HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF = 4,
163 HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP = 5,
164 HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP = 6,
165};
166
167enum {
168 /* RQ&SRQ related operations */
169 HNS_ROCE_OPCODE_SEND_DATA_RECEIVE = 0x06,
170 HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE = 0x07,
171};
172
9766edc3
SX		 173enum hns_roce_mtt_type {
174 MTT_TYPE_WQE = 0,
175 MTT_TYPE_CQE,
176};
177
9a443537 178#define HNS_ROCE_CMD_SUCCESS 1
179
180#define HNS_ROCE_PORT_DOWN 0
181#define HNS_ROCE_PORT_UP 1
182
183#define HNS_ROCE_MTT_ENTRY_PER_SEG 8
184
185#define PAGE_ADDR_SHIFT 12
186
187struct hns_roce_uar {
188 u64 pfn;
189 unsigned long index;
190};
191
192struct hns_roce_ucontext {
193 struct ib_ucontext ibucontext;
194 struct hns_roce_uar uar;
195};
196
197struct hns_roce_pd {
198 struct ib_pd ibpd;
199 unsigned long pdn;
200};
201
202struct hns_roce_bitmap {
203 /* Bitmap Traversal last a bit which is 1 */
204 unsigned long last;
205 unsigned long top;
206 unsigned long max;
207 unsigned long reserved_top;
208 unsigned long mask;
209 spinlock_t lock;
210 unsigned long *table;
211};
212
213/* Order bitmap length -- bit num compute formula: 1 << (max_order - order) */
214/* Order = 0: bitmap is biggest, order = max bitmap is least (only a bit) */
215/* Every bit repesent to a partner free/used status in bitmap */
216/*
e84e40be
S		 217 * Initial, bits of other bitmap are all 0 except that a bit of max_order is 1
218 * Bit = 1 represent to idle and available; bit = 0: not available
219 */
9a443537 220struct hns_roce_buddy {
221 /* Members point to every order level bitmap */
222 unsigned long **bits;
223 /* Represent to avail bits of the order level bitmap */
224 u32 *num_free;
225 int max_order;
226 spinlock_t lock;
227};
228
229/* For Hardware Entry Memory */
230struct hns_roce_hem_table {
231 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */
232 u32 type;
233 /* HEM array elment num */
234 unsigned long num_hem;
235 /* HEM entry record obj total num */
236 unsigned long num_obj;
237 /*Single obj size */
238 unsigned long obj_size;
239 int lowmem;
240 struct mutex mutex;
241 struct hns_roce_hem **hem;
a25d13cb
SX		 242 u64 **bt_l1;
243 dma_addr_t *bt_l1_dma_addr;
244 u64 **bt_l0;
245 dma_addr_t *bt_l0_dma_addr;
9a443537 246};
247
248struct hns_roce_mtt {
9766edc3
SX		 249 unsigned long first_seg;
250 int order;
251 int page_shift;
252 enum hns_roce_mtt_type mtt_type;
9a443537 253};
254
255/* Only support 4K page size for mr register */
256#define MR_SIZE_4K 0
257
258struct hns_roce_mr {
259 struct ib_mr ibmr;
260 struct ib_umem *umem;
261 u64 iova; /* MR's virtual orignal addr */
262 u64 size; /* Address range of MR */
263 u32 key; /* Key of MR */
264 u32 pd; /* PD num of MR */
265 u32 access;/* Access permission of MR */
266 int enabled; /* MR's active status */
267 int type; /* MR's register type */
268 u64 *pbl_buf;/* MR's PBL space */
269 dma_addr_t pbl_dma_addr; /* MR's PBL space PA */
ff795f71
WHX		 270 u32 pbl_size;/* PA number in the PBL */
271 u64 pbl_ba;/* page table address */
272 u32 l0_chunk_last_num;/* L0 last number */
273 u32 l1_chunk_last_num;/* L1 last number */
274 u64 **pbl_bt_l2;/* PBL BT L2 */
275 u64 **pbl_bt_l1;/* PBL BT L1 */
276 u64 *pbl_bt_l0;/* PBL BT L0 */
277 dma_addr_t *pbl_l2_dma_addr;/* PBL BT L2 dma addr */
278 dma_addr_t *pbl_l1_dma_addr;/* PBL BT L1 dma addr */
279 dma_addr_t pbl_l0_dma_addr;/* PBL BT L0 dma addr */
280 u32 pbl_ba_pg_sz;/* BT chunk page size */
281 u32 pbl_buf_pg_sz;/* buf chunk page size */
282 u32 pbl_hop_num;/* multi-hop number */
9a443537 283};
284
285struct hns_roce_mr_table {
286 struct hns_roce_bitmap mtpt_bitmap;
287 struct hns_roce_buddy mtt_buddy;
288 struct hns_roce_hem_table mtt_table;
289 struct hns_roce_hem_table mtpt_table;
9766edc3
SX		 290 struct hns_roce_buddy mtt_cqe_buddy;
291 struct hns_roce_hem_table mtt_cqe_table;
9a443537 292};
293
294struct hns_roce_wq {
295 u64 *wrid; /* Work request ID */
296 spinlock_t lock;
297 int wqe_cnt; /* WQE num */
298 u32 max_post;
299 int max_gs;
300 int offset;
301 int wqe_shift;/* WQE size */
302 u32 head;
303 u32 tail;
304 void __iomem *db_reg_l;
305};
306
926a01dc
WHX		 307struct hns_roce_sge {
308 int sge_cnt; /* SGE num */
309 int offset;
310 int sge_shift;/* SGE size */
311};
312
9a443537 313struct hns_roce_buf_list {
314 void *buf;
315 dma_addr_t map;
316};
317
318struct hns_roce_buf {
319 struct hns_roce_buf_list direct;
320 struct hns_roce_buf_list *page_list;
321 int nbufs;
322 u32 npages;
323 int page_shift;
324};
325
326struct hns_roce_cq_buf {
327 struct hns_roce_buf hr_buf;
328 struct hns_roce_mtt hr_mtt;
329};
330
9a443537 331struct hns_roce_cq {
332 struct ib_cq ib_cq;
333 struct hns_roce_cq_buf hr_buf;
9a443537 334 spinlock_t lock;
9a443537 335 struct ib_umem *umem;
9a443537 336 void (*comp)(struct hns_roce_cq *);
337 void (*event)(struct hns_roce_cq *, enum hns_roce_event);
338
339 struct hns_roce_uar *uar;
340 u32 cq_depth;
341 u32 cons_index;
342 void __iomem *cq_db_l;
8f3e9f3e 343 u16 *tptr_addr;
9a443537 344 unsigned long cqn;
345 u32 vector;
346 atomic_t refcount;
347 struct completion free;
348};
349
350struct hns_roce_srq {
351 struct ib_srq ibsrq;
352 int srqn;
353};
354
355struct hns_roce_uar_table {
356 struct hns_roce_bitmap bitmap;
357};
358
359struct hns_roce_qp_table {
360 struct hns_roce_bitmap bitmap;
361 spinlock_t lock;
362 struct hns_roce_hem_table qp_table;
363 struct hns_roce_hem_table irrl_table;
364};
365
366struct hns_roce_cq_table {
367 struct hns_roce_bitmap bitmap;
368 spinlock_t lock;
369 struct radix_tree_root tree;
370 struct hns_roce_hem_table table;
371};
372
373struct hns_roce_raq_table {
374 struct hns_roce_buf_list *e_raq_buf;
375};
376
377struct hns_roce_av {
378 __le32 port_pd;
379 u8 gid_index;
380 u8 stat_rate;
381 u8 hop_limit;
382 __le32 sl_tclass_flowlabel;
383 u8 dgid[HNS_ROCE_GID_SIZE];
384 u8 mac[6];
385 __le16 vlan;
386};
387
388struct hns_roce_ah {
389 struct ib_ah ibah;
390 struct hns_roce_av av;
391};
392
393struct hns_roce_cmd_context {
394 struct completion done;
395 int result;
396 int next;
397 u64 out_param;
398 u16 token;
399};
400
401struct hns_roce_cmdq {
402 struct dma_pool *pool;
9a443537 403 struct mutex hcr_mutex;
404 struct semaphore poll_sem;
405 /*
e84e40be
S		 406 * Event mode: cmd register mutex protection,
407 * ensure to not exceed max_cmds and user use limit region
408 */
9a443537 409 struct semaphore event_sem;
410 int max_cmds;
411 spinlock_t context_lock;
412 int free_head;
413 struct hns_roce_cmd_context *context;
414 /*
e84e40be
S		 415 * Result of get integer part
416 * which max_comds compute according a power of 2
417 */
9a443537 418 u16 token_mask;
419 /*
e84e40be
S		 420 * Process whether use event mode, init default non-zero
421 * After the event queue of cmd event ready,
422 * can switch into event mode
423 * close device, switch into poll mode(non event mode)
424 */
9a443537 425 u8 use_events;
426 u8 toggle;
427};
428
bfcc681b
SX		 429struct hns_roce_cmd_mailbox {
430 void *buf;
431 dma_addr_t dma;
432};
433
9a443537 434struct hns_roce_dev;
435
436struct hns_roce_qp {
437 struct ib_qp ibqp;
438 struct hns_roce_buf hr_buf;
439 struct hns_roce_wq rq;
440 __le64 doorbell_qpn;
441 __le32 sq_signal_bits;
442 u32 sq_next_wqe;
443 int sq_max_wqes_per_wr;
444 int sq_spare_wqes;
445 struct hns_roce_wq sq;
446
447 struct ib_umem *umem;
448 struct hns_roce_mtt mtt;
449 u32 buff_size;
450 struct mutex mutex;
451 u8 port;
7716809e 452 u8 phy_port;
9a443537 453 u8 sl;
454 u8 resp_depth;
455 u8 state;
456 u32 access_flags;
457 u32 pkey_index;
458 void (*event)(struct hns_roce_qp *,
459 enum hns_roce_event);
460 unsigned long qpn;
461
462 atomic_t refcount;
463 struct completion free;
926a01dc
WHX		 464
465 struct hns_roce_sge sge;
466 u32 next_sge;
9a443537 467};
468
469struct hns_roce_sqp {
470 struct hns_roce_qp hr_qp;
471};
472
473struct hns_roce_ib_iboe {
474 spinlock_t lock;
475 struct net_device *netdevs[HNS_ROCE_MAX_PORTS];
476 struct notifier_block nb;
477 struct notifier_block nb_inet;
9a443537 478 u8 phy_port[HNS_ROCE_MAX_PORTS];
479};
480
481struct hns_roce_eq {
482 struct hns_roce_dev *hr_dev;
483 void __iomem *doorbell;
484
485 int type_flag;/* Aeq:1 ceq:0 */
486 int eqn;
487 u32 entries;
488 int log_entries;
489 int eqe_size;
490 int irq;
491 int log_page_size;
492 int cons_index;
493 struct hns_roce_buf_list *buf_list;
494};
495
496struct hns_roce_eq_table {
497 struct hns_roce_eq *eq;
498 void __iomem **eqc_base;
499};
500
501struct hns_roce_caps {
502 u8 num_ports;
503 int gid_table_len[HNS_ROCE_MAX_PORTS];
504 int pkey_table_len[HNS_ROCE_MAX_PORTS];
505 int local_ca_ack_delay;
506 int num_uars;
507 u32 phy_num_uars;
508 u32 max_sq_sg; /* 2 */
509 u32 max_sq_inline; /* 32 */
510 u32 max_rq_sg; /* 2 */
511 int num_qps; /* 256k */
512 u32 max_wqes; /* 16k */
513 u32 max_sq_desc_sz; /* 64 */
514 u32 max_rq_desc_sz; /* 64 */
cfc85f3e 515 u32 max_srq_desc_sz;
9a443537 516 int max_qp_init_rdma;
517 int max_qp_dest_rdma;
9a443537 518 int num_cqs;
519 int max_cqes;
93aa2187 520 int min_cqes;
926a01dc 521 u32 min_wqes;
9a443537 522 int reserved_cqs;
523 int num_aeq_vectors; /* 1 */
524 int num_comp_vectors; /* 32 ceq */
525 int num_other_vectors;
526 int num_mtpts;
527 u32 num_mtt_segs;
cfc85f3e 528 u32 num_cqe_segs;
9a443537 529 int reserved_mrws;
530 int reserved_uars;
531 int num_pds;
532 int reserved_pds;
533 u32 mtt_entry_sz;
534 u32 cq_entry_sz;
535 u32 page_size_cap;
536 u32 reserved_lkey;
537 int mtpt_entry_sz;
538 int qpc_entry_sz;
539 int irrl_entry_sz;
540 int cqc_entry_sz;
ff795f71
WHX		 541 u32 pbl_ba_pg_sz;
542 u32 pbl_buf_pg_sz;
543 u32 pbl_hop_num;
9a443537 544 int aeqe_depth;
545 int ceqe_depth[HNS_ROCE_COMP_VEC_NUM];
546 enum ib_mtu max_mtu;
cfc85f3e
WHX		 547 u32 qpc_bt_num;
548 u32 srqc_bt_num;
549 u32 cqc_bt_num;
550 u32 mpt_bt_num;
a25d13cb
SX		 551 u32 qpc_ba_pg_sz;
552 u32 qpc_buf_pg_sz;
553 u32 qpc_hop_num;
554 u32 srqc_ba_pg_sz;
555 u32 srqc_buf_pg_sz;
556 u32 srqc_hop_num;
557 u32 cqc_ba_pg_sz;
558 u32 cqc_buf_pg_sz;
559 u32 cqc_hop_num;
560 u32 mpt_ba_pg_sz;
561 u32 mpt_buf_pg_sz;
562 u32 mpt_hop_num;
6a93c77a
SX		 563 u32 mtt_ba_pg_sz;
564 u32 mtt_buf_pg_sz;
565 u32 mtt_hop_num;
566 u32 cqe_ba_pg_sz;
567 u32 cqe_buf_pg_sz;
568 u32 cqe_hop_num;
9a443537 569};
570
571struct hns_roce_hw {
572 int (*reset)(struct hns_roce_dev *hr_dev, bool enable);
a04ff739
WHX		 573 int (*cmq_init)(struct hns_roce_dev *hr_dev);
574 void (*cmq_exit)(struct hns_roce_dev *hr_dev);
cfc85f3e 575 int (*hw_profile)(struct hns_roce_dev *hr_dev);
9a443537 576 int (*hw_init)(struct hns_roce_dev *hr_dev);
577 void (*hw_exit)(struct hns_roce_dev *hr_dev);
a680f2f3
WHX		 578 int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param,
579 u64 out_param, u32 in_modifier, u8 op_modifier, u16 op,
580 u16 token, int event);
581 int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned long timeout);
9a443537 582 void (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index,
583 union ib_gid *gid);
584 void (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr);
585 void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port,
586 enum ib_mtu mtu);
587 int (*write_mtpt)(void *mb_buf, struct hns_roce_mr *mr,
588 unsigned long mtpt_idx);
589 void (*write_cqc)(struct hns_roce_dev *hr_dev,
590 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
591 dma_addr_t dma_handle, int nent, u32 vector);
a25d13cb
SX		 592 int (*set_hem)(struct hns_roce_dev *hr_dev,
593 struct hns_roce_hem_table *table, int obj, int step_idx);
97f0e39f 594 int (*clear_hem)(struct hns_roce_dev *hr_dev,
a25d13cb
SX		 595 struct hns_roce_hem_table *table, int obj,
596 int step_idx);
9a443537 597 int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
598 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr);
599 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
600 int attr_mask, enum ib_qp_state cur_state,
601 enum ib_qp_state new_state);
602 int (*destroy_qp)(struct ib_qp *ibqp);
603 int (*post_send)(struct ib_qp *ibqp, struct ib_send_wr *wr,
604 struct ib_send_wr **bad_wr);
605 int (*post_recv)(struct ib_qp *qp, struct ib_recv_wr *recv_wr,
606 struct ib_recv_wr **bad_recv_wr);
607 int (*req_notify_cq)(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
608 int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
bfcc681b 609 int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr);
afb6b092 610 int (*destroy_cq)(struct ib_cq *ibcq);
9a443537 611};
612
613struct hns_roce_dev {
614 struct ib_device ib_dev;
615 struct platform_device *pdev;
dd74282d
WHX		 616 struct pci_dev *pci_dev;
617 struct device *dev;
9a443537 618 struct hns_roce_uar priv_uar;
528f1deb 619 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM];
9a443537 620 spinlock_t sm_lock;
9a443537 621 spinlock_t bt_cmd_lock;
622 struct hns_roce_ib_iboe iboe;
623
624 int irq[HNS_ROCE_MAX_IRQ_NUM];
625 u8 __iomem *reg_base;
626 struct hns_roce_caps caps;
627 struct radix_tree_root qp_table_tree;
628
629 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][MAC_ADDR_OCTET_NUM];
630 u64 sys_image_guid;
631 u32 vendor_id;
632 u32 vendor_part_id;
633 u32 hw_rev;
634 void __iomem *priv_addr;
635
636 struct hns_roce_cmdq cmd;
637 struct hns_roce_bitmap pd_bitmap;
638 struct hns_roce_uar_table uar_table;
639 struct hns_roce_mr_table mr_table;
640 struct hns_roce_cq_table cq_table;
641 struct hns_roce_qp_table qp_table;
642 struct hns_roce_eq_table eq_table;
643
644 int cmd_mod;
645 int loop_idc;
2d407888
WHX		 646 u32 sdb_offset;
647 u32 odb_offset;
8f3e9f3e
WHX		 648 dma_addr_t tptr_dma_addr; /*only for hw v1*/
649 u32 tptr_size; /*only for hw v1*/
08805fdb 650 const struct hns_roce_hw *hw;
016a0059 651 void *priv;
9a443537 652};
653
654static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)
655{
656 return container_of(ib_dev, struct hns_roce_dev, ib_dev);
657}
658
659static inline struct hns_roce_ucontext
660 *to_hr_ucontext(struct ib_ucontext *ibucontext)
661{
662 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext);
663}
664
665static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd)
666{
667 return container_of(ibpd, struct hns_roce_pd, ibpd);
668}
669
670static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah)
671{
672 return container_of(ibah, struct hns_roce_ah, ibah);
673}
674
675static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr)
676{
677 return container_of(ibmr, struct hns_roce_mr, ibmr);
678}
679
680static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp)
681{
682 return container_of(ibqp, struct hns_roce_qp, ibqp);
683}
684
685static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq)
686{
687 return container_of(ib_cq, struct hns_roce_cq, ib_cq);
688}
689
690static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq)
691{
692 return container_of(ibsrq, struct hns_roce_srq, ibsrq);
693}
694
695static inline struct hns_roce_sqp *hr_to_hr_sqp(struct hns_roce_qp *hr_qp)
696{
697 return container_of(hr_qp, struct hns_roce_sqp, hr_qp);
698}
699
700static inline void hns_roce_write64_k(__be32 val[2], void __iomem *dest)
701{
702 __raw_writeq(*(u64 *) val, dest);
703}
704
705static inline struct hns_roce_qp
706 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn)
707{
708 return radix_tree_lookup(&hr_dev->qp_table_tree,
709 qpn & (hr_dev->caps.num_qps - 1));
710}
711
712static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, int offset)
713{
714 u32 bits_per_long_val = BITS_PER_LONG;
715
716 if (bits_per_long_val == 64 || buf->nbufs == 1)
717 return (char *)(buf->direct.buf) + offset;
718 else
719 return (char *)(buf->page_list[offset >> PAGE_SHIFT].buf) +
720 (offset & (PAGE_SIZE - 1));
721}
722
723int hns_roce_init_uar_table(struct hns_roce_dev *dev);
724int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
725void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
726void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev);
727
728int hns_roce_cmd_init(struct hns_roce_dev *hr_dev);
729void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev);
730void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
731 u64 out_param);
732int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev);
733void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev);
734
735int hns_roce_mtt_init(struct hns_roce_dev *hr_dev, int npages, int page_shift,
736 struct hns_roce_mtt *mtt);
737void hns_roce_mtt_cleanup(struct hns_roce_dev *hr_dev,
738 struct hns_roce_mtt *mtt);
739int hns_roce_buf_write_mtt(struct hns_roce_dev *hr_dev,
740 struct hns_roce_mtt *mtt, struct hns_roce_buf *buf);
741
742int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev);
743int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
744int hns_roce_init_eq_table(struct hns_roce_dev *hr_dev);
745int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev);
746int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev);
747
748void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev);
749void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev);
750void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev);
751void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
752void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);
753
754int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj);
5e6ff78a
WHX		 755void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj,
756 int rr);
9a443537 757int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask,
758 u32 reserved_bot, u32 resetrved_top);
759void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap);
760void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev);
761int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt,
762 int align, unsigned long *obj);
763void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap,
5e6ff78a
WHX		 764 unsigned long obj, int cnt,
765 int rr);
9a443537 766
90898850
DC		 767struct ib_ah *hns_roce_create_ah(struct ib_pd *pd,
768 struct rdma_ah_attr *ah_attr,
477864c8 769 struct ib_udata *udata);
90898850 770int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
9a443537 771int hns_roce_destroy_ah(struct ib_ah *ah);
772
773struct ib_pd *hns_roce_alloc_pd(struct ib_device *ib_dev,
774 struct ib_ucontext *context,
775 struct ib_udata *udata);
776int hns_roce_dealloc_pd(struct ib_pd *pd);
777
778struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc);
779struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
780 u64 virt_addr, int access_flags,
781 struct ib_udata *udata);
782int hns_roce_dereg_mr(struct ib_mr *ibmr);
bfcc681b
SX		 783int hns_roce_hw2sw_mpt(struct hns_roce_dev *hr_dev,
784 struct hns_roce_cmd_mailbox *mailbox,
785 unsigned long mpt_index);
786unsigned long key_to_hw_index(u32 key);
9a443537 787
788void hns_roce_buf_free(struct hns_roce_dev *hr_dev, u32 size,
789 struct hns_roce_buf *buf);
790int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct,
791 struct hns_roce_buf *buf);
792
793int hns_roce_ib_umem_write_mtt(struct hns_roce_dev *hr_dev,
794 struct hns_roce_mtt *mtt, struct ib_umem *umem);
795
796struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd,
797 struct ib_qp_init_attr *init_attr,
798 struct ib_udata *udata);
799int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
800 int attr_mask, struct ib_udata *udata);
801void *get_recv_wqe(struct hns_roce_qp *hr_qp, int n);
802void *get_send_wqe(struct hns_roce_qp *hr_qp, int n);
926a01dc 803void *get_send_extend_sge(struct hns_roce_qp *hr_qp, int n);
9a443537 804bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq,
805 struct ib_cq *ib_cq);
806enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state);
807void hns_roce_lock_cqs(struct hns_roce_cq *send_cq,
808 struct hns_roce_cq *recv_cq);
809void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
810 struct hns_roce_cq *recv_cq);
811void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
812void hns_roce_qp_free(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
813void hns_roce_release_range_qp(struct hns_roce_dev *hr_dev, int base_qpn,
814 int cnt);
815__be32 send_ieth(struct ib_send_wr *wr);
816int to_hr_qp_type(int qp_type);
817
818struct ib_cq *hns_roce_ib_create_cq(struct ib_device *ib_dev,
819 const struct ib_cq_init_attr *attr,
820 struct ib_ucontext *context,
821 struct ib_udata *udata);
822
823int hns_roce_ib_destroy_cq(struct ib_cq *ib_cq);
afb6b092 824void hns_roce_free_cq(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq);
9a443537 825
826void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
827void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
828void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
829int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index);
08805fdb
WHX		 830int hns_roce_init(struct hns_roce_dev *hr_dev);
831void hns_roce_exit(struct hns_roce_dev *hr_dev);
9a443537 832
833#endif /* _HNS_ROCE_DEVICE_H */
Ubuntu Hirsute Linux kernel mirror