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9a443537 | 1 | /* |
2 | * Copyright (c) 2016 Hisilicon Limited. | |
3 | * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. | |
4 | * | |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the | |
9 | * OpenIB.org BSD license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or | |
12 | * without modification, are permitted provided that the following | |
13 | * conditions are met: | |
14 | * | |
15 | * - Redistributions of source code must retain the above | |
16 | * copyright notice, this list of conditions and the following | |
17 | * disclaimer. | |
18 | * | |
19 | * - Redistributions in binary form must reproduce the above | |
20 | * copyright notice, this list of conditions and the following | |
21 | * disclaimer in the documentation and/or other materials | |
22 | * provided with the distribution. | |
23 | * | |
24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
31 | * SOFTWARE. | |
32 | */ | |
33 | ||
05ad5482 | 34 | #include <linux/pci.h> |
9a443537 | 35 | #include <linux/platform_device.h> |
cb814642 | 36 | #include <rdma/ib_addr.h> |
9a443537 | 37 | #include <rdma/ib_umem.h> |
89944450 | 38 | #include <rdma/uverbs_ioctl.h> |
9a443537 | 39 | #include "hns_roce_common.h" |
40 | #include "hns_roce_device.h" | |
41 | #include "hns_roce_hem.h" | |
4d409958 | 42 | #include <rdma/hns-abi.h> |
9a443537 | 43 | |
1ca5b253 | 44 | #define SQP_NUM (2 * HNS_ROCE_MAX_PORTS) |
9a443537 | 45 | |
8365f30e YL |
46 | static void flush_work_handle(struct work_struct *work) |
47 | { | |
48 | struct hns_roce_work *flush_work = container_of(work, | |
49 | struct hns_roce_work, work); | |
50 | struct hns_roce_qp *hr_qp = container_of(flush_work, | |
51 | struct hns_roce_qp, flush_work); | |
52 | struct device *dev = flush_work->hr_dev->dev; | |
53 | struct ib_qp_attr attr; | |
54 | int attr_mask; | |
55 | int ret; | |
56 | ||
57 | attr_mask = IB_QP_STATE; | |
58 | attr.qp_state = IB_QPS_ERR; | |
59 | ||
5fe36e8b YL |
60 | if (test_and_clear_bit(HNS_ROCE_FLUSH_FLAG, &hr_qp->flush_flag)) { |
61 | ret = hns_roce_modify_qp(&hr_qp->ibqp, &attr, attr_mask, NULL); | |
62 | if (ret) | |
63 | dev_err(dev, "Modify QP to error state failed(%d) during CQE flush\n", | |
64 | ret); | |
65 | } | |
8365f30e YL |
66 | |
67 | /* | |
68 | * make sure we signal QP destroy leg that flush QP was completed | |
69 | * so that it can safely proceed ahead now and destroy QP | |
70 | */ | |
71 | if (atomic_dec_and_test(&hr_qp->refcount)) | |
72 | complete(&hr_qp->free); | |
73 | } | |
74 | ||
75 | void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) | |
76 | { | |
77 | struct hns_roce_work *flush_work = &hr_qp->flush_work; | |
78 | ||
79 | flush_work->hr_dev = hr_dev; | |
80 | INIT_WORK(&flush_work->work, flush_work_handle); | |
81 | atomic_inc(&hr_qp->refcount); | |
82 | queue_work(hr_dev->irq_workq, &flush_work->work); | |
83 | } | |
84 | ||
9a443537 | 85 | void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type) |
86 | { | |
13ca970e | 87 | struct device *dev = hr_dev->dev; |
9a443537 | 88 | struct hns_roce_qp *qp; |
89 | ||
736b5a70 | 90 | xa_lock(&hr_dev->qp_table_xa); |
9a443537 | 91 | qp = __hns_roce_qp_lookup(hr_dev, qpn); |
92 | if (qp) | |
93 | atomic_inc(&qp->refcount); | |
736b5a70 | 94 | xa_unlock(&hr_dev->qp_table_xa); |
9a443537 | 95 | |
96 | if (!qp) { | |
97 | dev_warn(dev, "Async event for bogus QP %08x\n", qpn); | |
98 | return; | |
99 | } | |
100 | ||
67010be8 YL |
101 | if (hr_dev->hw_rev != HNS_ROCE_HW_VER1 && |
102 | (event_type == HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR || | |
103 | event_type == HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR || | |
104 | event_type == HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR)) { | |
105 | qp->state = IB_QPS_ERR; | |
106 | if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag)) | |
107 | init_flush_work(hr_dev, qp); | |
108 | } | |
109 | ||
9a443537 | 110 | qp->event(qp, (enum hns_roce_event)event_type); |
111 | ||
112 | if (atomic_dec_and_test(&qp->refcount)) | |
113 | complete(&qp->free); | |
114 | } | |
115 | ||
116 | static void hns_roce_ib_qp_event(struct hns_roce_qp *hr_qp, | |
117 | enum hns_roce_event type) | |
118 | { | |
119 | struct ib_event event; | |
120 | struct ib_qp *ibqp = &hr_qp->ibqp; | |
121 | ||
122 | if (ibqp->event_handler) { | |
123 | event.device = ibqp->device; | |
124 | event.element.qp = ibqp; | |
125 | switch (type) { | |
126 | case HNS_ROCE_EVENT_TYPE_PATH_MIG: | |
127 | event.event = IB_EVENT_PATH_MIG; | |
128 | break; | |
129 | case HNS_ROCE_EVENT_TYPE_COMM_EST: | |
130 | event.event = IB_EVENT_COMM_EST; | |
131 | break; | |
132 | case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: | |
133 | event.event = IB_EVENT_SQ_DRAINED; | |
134 | break; | |
135 | case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: | |
136 | event.event = IB_EVENT_QP_LAST_WQE_REACHED; | |
137 | break; | |
138 | case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: | |
139 | event.event = IB_EVENT_QP_FATAL; | |
140 | break; | |
141 | case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: | |
142 | event.event = IB_EVENT_PATH_MIG_ERR; | |
143 | break; | |
144 | case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: | |
145 | event.event = IB_EVENT_QP_REQ_ERR; | |
146 | break; | |
147 | case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: | |
148 | event.event = IB_EVENT_QP_ACCESS_ERR; | |
149 | break; | |
150 | default: | |
fecd02eb | 151 | dev_dbg(ibqp->device->dev.parent, "roce_ib: Unexpected event type %d on QP %06lx\n", |
9a443537 | 152 | type, hr_qp->qpn); |
153 | return; | |
154 | } | |
155 | ibqp->event_handler(&event, ibqp->qp_context); | |
156 | } | |
157 | } | |
158 | ||
159 | static int hns_roce_reserve_range_qp(struct hns_roce_dev *hr_dev, int cnt, | |
160 | int align, unsigned long *base) | |
161 | { | |
162 | struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; | |
9a443537 | 163 | |
a1ceeca6 GP |
164 | return hns_roce_bitmap_alloc_range(&qp_table->bitmap, cnt, align, |
165 | base) ? | |
166 | -ENOMEM : | |
167 | 0; | |
9a443537 | 168 | } |
169 | ||
170 | enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state) | |
171 | { | |
172 | switch (state) { | |
173 | case IB_QPS_RESET: | |
174 | return HNS_ROCE_QP_STATE_RST; | |
175 | case IB_QPS_INIT: | |
176 | return HNS_ROCE_QP_STATE_INIT; | |
177 | case IB_QPS_RTR: | |
178 | return HNS_ROCE_QP_STATE_RTR; | |
179 | case IB_QPS_RTS: | |
180 | return HNS_ROCE_QP_STATE_RTS; | |
181 | case IB_QPS_SQD: | |
182 | return HNS_ROCE_QP_STATE_SQD; | |
183 | case IB_QPS_ERR: | |
184 | return HNS_ROCE_QP_STATE_ERR; | |
185 | default: | |
186 | return HNS_ROCE_QP_NUM_STATE; | |
187 | } | |
188 | } | |
189 | ||
d08c74b1 XW |
190 | static void add_qp_to_list(struct hns_roce_dev *hr_dev, |
191 | struct hns_roce_qp *hr_qp, | |
192 | struct ib_cq *send_cq, struct ib_cq *recv_cq) | |
193 | { | |
194 | struct hns_roce_cq *hr_send_cq, *hr_recv_cq; | |
195 | unsigned long flags; | |
196 | ||
197 | hr_send_cq = send_cq ? to_hr_cq(send_cq) : NULL; | |
198 | hr_recv_cq = recv_cq ? to_hr_cq(recv_cq) : NULL; | |
199 | ||
200 | spin_lock_irqsave(&hr_dev->qp_list_lock, flags); | |
201 | hns_roce_lock_cqs(hr_send_cq, hr_recv_cq); | |
202 | ||
203 | list_add_tail(&hr_qp->node, &hr_dev->qp_list); | |
204 | if (hr_send_cq) | |
205 | list_add_tail(&hr_qp->sq_node, &hr_send_cq->sq_list); | |
206 | if (hr_recv_cq) | |
207 | list_add_tail(&hr_qp->rq_node, &hr_recv_cq->rq_list); | |
208 | ||
209 | hns_roce_unlock_cqs(hr_send_cq, hr_recv_cq); | |
210 | spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); | |
211 | } | |
212 | ||
213 | static int hns_roce_qp_store(struct hns_roce_dev *hr_dev, | |
214 | struct hns_roce_qp *hr_qp, | |
215 | struct ib_qp_init_attr *init_attr) | |
9a443537 | 216 | { |
736b5a70 | 217 | struct xarray *xa = &hr_dev->qp_table_xa; |
9a443537 | 218 | int ret; |
219 | ||
d08c74b1 | 220 | if (!hr_qp->qpn) |
9a443537 | 221 | return -EINVAL; |
222 | ||
d08c74b1 | 223 | ret = xa_err(xa_store_irq(xa, hr_qp->qpn, hr_qp, GFP_KERNEL)); |
736b5a70 | 224 | if (ret) |
d08c74b1 XW |
225 | dev_err(hr_dev->dev, "Failed to xa store for QPC\n"); |
226 | else | |
227 | /* add QP to device's QP list for softwc */ | |
228 | add_qp_to_list(hr_dev, hr_qp, init_attr->send_cq, | |
229 | init_attr->recv_cq); | |
9a443537 | 230 | |
231 | return ret; | |
232 | } | |
233 | ||
d08c74b1 | 234 | static int alloc_qpc(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) |
9a443537 | 235 | { |
236 | struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; | |
13ca970e | 237 | struct device *dev = hr_dev->dev; |
9a443537 | 238 | int ret; |
239 | ||
d08c74b1 | 240 | if (!hr_qp->qpn) |
9a443537 | 241 | return -EINVAL; |
242 | ||
d08c74b1 XW |
243 | /* In v1 engine, GSI QP context is saved in the RoCE hw's register */ |
244 | if (hr_qp->ibqp.qp_type == IB_QPT_GSI && | |
245 | hr_dev->hw_rev == HNS_ROCE_HW_VER1) | |
246 | return 0; | |
9a443537 | 247 | |
248 | /* Alloc memory for QPC */ | |
249 | ret = hns_roce_table_get(hr_dev, &qp_table->qp_table, hr_qp->qpn); | |
250 | if (ret) { | |
d08c74b1 | 251 | dev_err(dev, "Failed to get QPC table\n"); |
9a443537 | 252 | goto err_out; |
253 | } | |
254 | ||
255 | /* Alloc memory for IRRL */ | |
256 | ret = hns_roce_table_get(hr_dev, &qp_table->irrl_table, hr_qp->qpn); | |
257 | if (ret) { | |
d08c74b1 | 258 | dev_err(dev, "Failed to get IRRL table\n"); |
9a443537 | 259 | goto err_put_qp; |
260 | } | |
261 | ||
e92f2c18 | 262 | if (hr_dev->caps.trrl_entry_sz) { |
263 | /* Alloc memory for TRRL */ | |
264 | ret = hns_roce_table_get(hr_dev, &qp_table->trrl_table, | |
265 | hr_qp->qpn); | |
266 | if (ret) { | |
d08c74b1 | 267 | dev_err(dev, "Failed to get TRRL table\n"); |
e92f2c18 | 268 | goto err_put_irrl; |
269 | } | |
270 | } | |
271 | ||
6a157f7d YL |
272 | if (hr_dev->caps.sccc_entry_sz) { |
273 | /* Alloc memory for SCC CTX */ | |
274 | ret = hns_roce_table_get(hr_dev, &qp_table->sccc_table, | |
275 | hr_qp->qpn); | |
276 | if (ret) { | |
d08c74b1 | 277 | dev_err(dev, "Failed to get SCC CTX table\n"); |
6a157f7d YL |
278 | goto err_put_trrl; |
279 | } | |
280 | } | |
281 | ||
9a443537 | 282 | return 0; |
283 | ||
e92f2c18 | 284 | err_put_trrl: |
285 | if (hr_dev->caps.trrl_entry_sz) | |
286 | hns_roce_table_put(hr_dev, &qp_table->trrl_table, hr_qp->qpn); | |
287 | ||
9a443537 | 288 | err_put_irrl: |
289 | hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn); | |
290 | ||
291 | err_put_qp: | |
292 | hns_roce_table_put(hr_dev, &qp_table->qp_table, hr_qp->qpn); | |
293 | ||
294 | err_out: | |
295 | return ret; | |
296 | } | |
297 | ||
298 | void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) | |
299 | { | |
736b5a70 | 300 | struct xarray *xa = &hr_dev->qp_table_xa; |
9a443537 | 301 | unsigned long flags; |
302 | ||
d08c74b1 XW |
303 | list_del(&hr_qp->node); |
304 | list_del(&hr_qp->sq_node); | |
305 | list_del(&hr_qp->rq_node); | |
306 | ||
736b5a70 MW |
307 | xa_lock_irqsave(xa, flags); |
308 | __xa_erase(xa, hr_qp->qpn & (hr_dev->caps.num_qps - 1)); | |
309 | xa_unlock_irqrestore(xa, flags); | |
9a443537 | 310 | } |
311 | ||
d08c74b1 | 312 | static void free_qpc(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) |
9a443537 | 313 | { |
314 | struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; | |
315 | ||
d08c74b1 XW |
316 | /* In v1 engine, GSI QP context is saved in the RoCE hw's register */ |
317 | if (hr_qp->ibqp.qp_type == IB_QPT_GSI && | |
318 | hr_dev->hw_rev == HNS_ROCE_HW_VER1) | |
319 | return; | |
9a443537 | 320 | |
d08c74b1 XW |
321 | if (hr_dev->caps.trrl_entry_sz) |
322 | hns_roce_table_put(hr_dev, &qp_table->trrl_table, hr_qp->qpn); | |
323 | hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn); | |
9a443537 | 324 | } |
325 | ||
326 | void hns_roce_release_range_qp(struct hns_roce_dev *hr_dev, int base_qpn, | |
327 | int cnt) | |
328 | { | |
329 | struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; | |
330 | ||
21b97f53 | 331 | if (base_qpn < hr_dev->caps.reserved_qps) |
9a443537 | 332 | return; |
333 | ||
5e6ff78a | 334 | hns_roce_bitmap_free_range(&qp_table->bitmap, base_qpn, cnt, BITMAP_RR); |
9a443537 | 335 | } |
336 | ||
337 | static int hns_roce_set_rq_size(struct hns_roce_dev *hr_dev, | |
e00b64f7 | 338 | struct ib_qp_cap *cap, bool is_user, int has_rq, |
9a443537 | 339 | struct hns_roce_qp *hr_qp) |
340 | { | |
13ca970e | 341 | struct device *dev = hr_dev->dev; |
9a443537 | 342 | u32 max_cnt; |
9a443537 | 343 | |
344 | /* Check the validity of QP support capacity */ | |
345 | if (cap->max_recv_wr > hr_dev->caps.max_wqes || | |
346 | cap->max_recv_sge > hr_dev->caps.max_rq_sg) { | |
347 | dev_err(dev, "RQ WR or sge error!max_recv_wr=%d max_recv_sge=%d\n", | |
348 | cap->max_recv_wr, cap->max_recv_sge); | |
349 | return -EINVAL; | |
350 | } | |
351 | ||
c7bcb134 LO |
352 | /* If srq exist, set zero for relative number of rq */ |
353 | if (!has_rq) { | |
354 | hr_qp->rq.wqe_cnt = 0; | |
355 | hr_qp->rq.max_gs = 0; | |
356 | cap->max_recv_wr = 0; | |
357 | cap->max_recv_sge = 0; | |
9a443537 | 358 | } else { |
359 | if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge)) { | |
360 | dev_err(dev, "user space no need config max_recv_wr max_recv_sge\n"); | |
361 | return -EINVAL; | |
362 | } | |
363 | ||
926a01dc WHX |
364 | if (hr_dev->caps.min_wqes) |
365 | max_cnt = max(cap->max_recv_wr, hr_dev->caps.min_wqes); | |
366 | else | |
367 | max_cnt = cap->max_recv_wr; | |
368 | ||
9a443537 | 369 | hr_qp->rq.wqe_cnt = roundup_pow_of_two(max_cnt); |
370 | ||
371 | if ((u32)hr_qp->rq.wqe_cnt > hr_dev->caps.max_wqes) { | |
926a01dc | 372 | dev_err(dev, "while setting rq size, rq.wqe_cnt too large\n"); |
9a443537 | 373 | return -EINVAL; |
374 | } | |
375 | ||
376 | max_cnt = max(1U, cap->max_recv_sge); | |
377 | hr_qp->rq.max_gs = roundup_pow_of_two(max_cnt); | |
b7f5a64a | 378 | if (hr_dev->caps.max_rq_sg <= HNS_ROCE_SGE_IN_WQE) |
926a01dc WHX |
379 | hr_qp->rq.wqe_shift = |
380 | ilog2(hr_dev->caps.max_rq_desc_sz); | |
381 | else | |
382 | hr_qp->rq.wqe_shift = | |
383 | ilog2(hr_dev->caps.max_rq_desc_sz | |
384 | * hr_qp->rq.max_gs); | |
9a443537 | 385 | } |
386 | ||
765745c7 | 387 | cap->max_recv_wr = hr_qp->rq.wqe_cnt; |
9a443537 | 388 | cap->max_recv_sge = hr_qp->rq.max_gs; |
389 | ||
390 | return 0; | |
391 | } | |
392 | ||
cc95b23c LO |
393 | static int check_sq_size_with_integrity(struct hns_roce_dev *hr_dev, |
394 | struct ib_qp_cap *cap, | |
395 | struct hns_roce_ib_create_qp *ucmd) | |
9a443537 | 396 | { |
397 | u32 roundup_sq_stride = roundup_pow_of_two(hr_dev->caps.max_sq_desc_sz); | |
398 | u8 max_sq_stride = ilog2(roundup_sq_stride); | |
399 | ||
400 | /* Sanity check SQ size before proceeding */ | |
429ce97b JG |
401 | if (ucmd->log_sq_stride > max_sq_stride || |
402 | ucmd->log_sq_stride < HNS_ROCE_IB_MIN_SQ_STRIDE) { | |
db50077b | 403 | ibdev_err(&hr_dev->ib_dev, "check SQ size error!\n"); |
9a443537 | 404 | return -EINVAL; |
405 | } | |
406 | ||
926a01dc | 407 | if (cap->max_send_sge > hr_dev->caps.max_sq_sg) { |
db50077b LO |
408 | ibdev_err(&hr_dev->ib_dev, "SQ sge error! max_send_sge=%d\n", |
409 | cap->max_send_sge); | |
926a01dc WHX |
410 | return -EINVAL; |
411 | } | |
412 | ||
cc95b23c LO |
413 | return 0; |
414 | } | |
415 | ||
416 | static int hns_roce_set_user_sq_size(struct hns_roce_dev *hr_dev, | |
417 | struct ib_qp_cap *cap, | |
418 | struct hns_roce_qp *hr_qp, | |
419 | struct hns_roce_ib_create_qp *ucmd) | |
420 | { | |
421 | u32 ex_sge_num; | |
422 | u32 page_size; | |
423 | u32 max_cnt; | |
424 | int ret; | |
425 | ||
429ce97b JG |
426 | if (check_shl_overflow(1, ucmd->log_sq_bb_count, &hr_qp->sq.wqe_cnt) || |
427 | hr_qp->sq.wqe_cnt > hr_dev->caps.max_wqes) | |
428 | return -EINVAL; | |
429 | ||
cc95b23c LO |
430 | ret = check_sq_size_with_integrity(hr_dev, cap, ucmd); |
431 | if (ret) { | |
432 | ibdev_err(&hr_dev->ib_dev, "Sanity check sq size failed\n"); | |
433 | return ret; | |
434 | } | |
435 | ||
9a443537 | 436 | hr_qp->sq.wqe_shift = ucmd->log_sq_stride; |
437 | ||
926a01dc | 438 | max_cnt = max(1U, cap->max_send_sge); |
b7f5a64a | 439 | if (hr_dev->hw_rev == HNS_ROCE_HW_VER1) |
926a01dc WHX |
440 | hr_qp->sq.max_gs = roundup_pow_of_two(max_cnt); |
441 | else | |
442 | hr_qp->sq.max_gs = max_cnt; | |
443 | ||
b7f5a64a | 444 | if (hr_qp->sq.max_gs > HNS_ROCE_SGE_IN_WQE) |
926a01dc WHX |
445 | hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt * |
446 | (hr_qp->sq.max_gs - 2)); | |
05ad5482 | 447 | |
b7f5a64a LC |
448 | if (hr_qp->sq.max_gs > HNS_ROCE_SGE_IN_WQE && |
449 | hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08_A) { | |
05ad5482 LO |
450 | if (hr_qp->sge.sge_cnt > hr_dev->caps.max_extend_sg) { |
451 | dev_err(hr_dev->dev, | |
452 | "The extended sge cnt error! sge_cnt=%d\n", | |
453 | hr_qp->sge.sge_cnt); | |
454 | return -EINVAL; | |
455 | } | |
456 | } | |
457 | ||
926a01dc | 458 | hr_qp->sge.sge_shift = 4; |
b28ca7cc | 459 | ex_sge_num = hr_qp->sge.sge_cnt; |
926a01dc | 460 | |
9a443537 | 461 | /* Get buf size, SQ and RQ are aligned to page_szie */ |
b7f5a64a | 462 | if (hr_dev->hw_rev == HNS_ROCE_HW_VER1) { |
b02f2326 | 463 | hr_qp->buff_size = round_up((hr_qp->rq.wqe_cnt << |
9a443537 | 464 | hr_qp->rq.wqe_shift), PAGE_SIZE) + |
b02f2326 | 465 | round_up((hr_qp->sq.wqe_cnt << |
9a443537 | 466 | hr_qp->sq.wqe_shift), PAGE_SIZE); |
467 | ||
926a01dc | 468 | hr_qp->sq.offset = 0; |
b02f2326 | 469 | hr_qp->rq.offset = round_up((hr_qp->sq.wqe_cnt << |
9a443537 | 470 | hr_qp->sq.wqe_shift), PAGE_SIZE); |
926a01dc | 471 | } else { |
9a8982dc | 472 | page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT); |
e0222d18 LO |
473 | hr_qp->sge.sge_cnt = ex_sge_num ? |
474 | max(page_size / (1 << hr_qp->sge.sge_shift), ex_sge_num) : 0; | |
b02f2326 | 475 | hr_qp->buff_size = round_up((hr_qp->rq.wqe_cnt << |
9a8982dc | 476 | hr_qp->rq.wqe_shift), page_size) + |
b02f2326 | 477 | round_up((hr_qp->sge.sge_cnt << |
9a8982dc | 478 | hr_qp->sge.sge_shift), page_size) + |
b02f2326 | 479 | round_up((hr_qp->sq.wqe_cnt << |
9a8982dc | 480 | hr_qp->sq.wqe_shift), page_size); |
926a01dc WHX |
481 | |
482 | hr_qp->sq.offset = 0; | |
b28ca7cc | 483 | if (ex_sge_num) { |
b02f2326 WL |
484 | hr_qp->sge.offset = round_up((hr_qp->sq.wqe_cnt << |
485 | hr_qp->sq.wqe_shift), | |
486 | page_size); | |
926a01dc | 487 | hr_qp->rq.offset = hr_qp->sge.offset + |
b02f2326 WL |
488 | round_up((hr_qp->sge.sge_cnt << |
489 | hr_qp->sge.sge_shift), | |
490 | page_size); | |
926a01dc | 491 | } else { |
b02f2326 WL |
492 | hr_qp->rq.offset = round_up((hr_qp->sq.wqe_cnt << |
493 | hr_qp->sq.wqe_shift), | |
494 | page_size); | |
926a01dc WHX |
495 | } |
496 | } | |
9a443537 | 497 | |
498 | return 0; | |
499 | } | |
500 | ||
8d18ad83 LO |
501 | static int split_wqe_buf_region(struct hns_roce_dev *hr_dev, |
502 | struct hns_roce_qp *hr_qp, | |
503 | struct hns_roce_buf_region *regions, | |
504 | int region_max, int page_shift) | |
505 | { | |
506 | int page_size = 1 << page_shift; | |
507 | bool is_extend_sge; | |
508 | int region_cnt = 0; | |
509 | int buf_size; | |
510 | int buf_cnt; | |
511 | ||
512 | if (hr_qp->buff_size < 1 || region_max < 1) | |
513 | return region_cnt; | |
514 | ||
515 | if (hr_qp->sge.sge_cnt > 0) | |
516 | is_extend_sge = true; | |
517 | else | |
518 | is_extend_sge = false; | |
519 | ||
520 | /* sq region */ | |
521 | if (is_extend_sge) | |
522 | buf_size = hr_qp->sge.offset - hr_qp->sq.offset; | |
523 | else | |
524 | buf_size = hr_qp->rq.offset - hr_qp->sq.offset; | |
525 | ||
526 | if (buf_size > 0 && region_cnt < region_max) { | |
527 | buf_cnt = DIV_ROUND_UP(buf_size, page_size); | |
528 | hns_roce_init_buf_region(®ions[region_cnt], | |
529 | hr_dev->caps.wqe_sq_hop_num, | |
530 | hr_qp->sq.offset / page_size, | |
531 | buf_cnt); | |
532 | region_cnt++; | |
533 | } | |
534 | ||
535 | /* sge region */ | |
536 | if (is_extend_sge) { | |
537 | buf_size = hr_qp->rq.offset - hr_qp->sge.offset; | |
538 | if (buf_size > 0 && region_cnt < region_max) { | |
539 | buf_cnt = DIV_ROUND_UP(buf_size, page_size); | |
540 | hns_roce_init_buf_region(®ions[region_cnt], | |
541 | hr_dev->caps.wqe_sge_hop_num, | |
542 | hr_qp->sge.offset / page_size, | |
543 | buf_cnt); | |
544 | region_cnt++; | |
545 | } | |
546 | } | |
547 | ||
548 | /* rq region */ | |
549 | buf_size = hr_qp->buff_size - hr_qp->rq.offset; | |
550 | if (buf_size > 0) { | |
551 | buf_cnt = DIV_ROUND_UP(buf_size, page_size); | |
552 | hns_roce_init_buf_region(®ions[region_cnt], | |
553 | hr_dev->caps.wqe_rq_hop_num, | |
554 | hr_qp->rq.offset / page_size, | |
555 | buf_cnt); | |
556 | region_cnt++; | |
557 | } | |
558 | ||
559 | return region_cnt; | |
560 | } | |
561 | ||
562 | static int calc_wqe_bt_page_shift(struct hns_roce_dev *hr_dev, | |
563 | struct hns_roce_buf_region *regions, | |
564 | int region_cnt) | |
565 | { | |
566 | int bt_pg_shift; | |
567 | int ba_num; | |
568 | int ret; | |
569 | ||
570 | bt_pg_shift = PAGE_SHIFT + hr_dev->caps.mtt_ba_pg_sz; | |
571 | ||
572 | /* all root ba entries must in one bt page */ | |
573 | do { | |
574 | ba_num = (1 << bt_pg_shift) / BA_BYTE_LEN; | |
575 | ret = hns_roce_hem_list_calc_root_ba(regions, region_cnt, | |
576 | ba_num); | |
577 | if (ret <= ba_num) | |
578 | break; | |
579 | ||
580 | bt_pg_shift++; | |
581 | } while (ret > ba_num); | |
582 | ||
583 | return bt_pg_shift - PAGE_SHIFT; | |
584 | } | |
585 | ||
947441ea LO |
586 | static int set_extend_sge_param(struct hns_roce_dev *hr_dev, |
587 | struct hns_roce_qp *hr_qp) | |
588 | { | |
589 | struct device *dev = hr_dev->dev; | |
590 | ||
591 | if (hr_qp->sq.max_gs > 2) { | |
592 | hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt * | |
593 | (hr_qp->sq.max_gs - 2)); | |
594 | hr_qp->sge.sge_shift = 4; | |
595 | } | |
596 | ||
597 | /* ud sqwqe's sge use extend sge */ | |
b7f5a64a LC |
598 | if (hr_dev->hw_rev != HNS_ROCE_HW_VER1 && |
599 | hr_qp->ibqp.qp_type == IB_QPT_GSI) { | |
947441ea LO |
600 | hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt * |
601 | hr_qp->sq.max_gs); | |
602 | hr_qp->sge.sge_shift = 4; | |
603 | } | |
604 | ||
b7f5a64a LC |
605 | if (hr_qp->sq.max_gs > 2 && |
606 | hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08_A) { | |
947441ea LO |
607 | if (hr_qp->sge.sge_cnt > hr_dev->caps.max_extend_sg) { |
608 | dev_err(dev, "The extended sge cnt error! sge_cnt=%d\n", | |
609 | hr_qp->sge.sge_cnt); | |
610 | return -EINVAL; | |
611 | } | |
612 | } | |
613 | ||
614 | return 0; | |
615 | } | |
616 | ||
9a443537 | 617 | static int hns_roce_set_kernel_sq_size(struct hns_roce_dev *hr_dev, |
618 | struct ib_qp_cap *cap, | |
9a443537 | 619 | struct hns_roce_qp *hr_qp) |
620 | { | |
13ca970e | 621 | struct device *dev = hr_dev->dev; |
9a8982dc | 622 | u32 page_size; |
9a443537 | 623 | u32 max_cnt; |
926a01dc | 624 | int size; |
947441ea | 625 | int ret; |
9a443537 | 626 | |
627 | if (cap->max_send_wr > hr_dev->caps.max_wqes || | |
628 | cap->max_send_sge > hr_dev->caps.max_sq_sg || | |
629 | cap->max_inline_data > hr_dev->caps.max_sq_inline) { | |
926a01dc | 630 | dev_err(dev, "SQ WR or sge or inline data error!\n"); |
9a443537 | 631 | return -EINVAL; |
632 | } | |
633 | ||
634 | hr_qp->sq.wqe_shift = ilog2(hr_dev->caps.max_sq_desc_sz); | |
9a443537 | 635 | |
926a01dc WHX |
636 | if (hr_dev->caps.min_wqes) |
637 | max_cnt = max(cap->max_send_wr, hr_dev->caps.min_wqes); | |
638 | else | |
639 | max_cnt = cap->max_send_wr; | |
640 | ||
9a443537 | 641 | hr_qp->sq.wqe_cnt = roundup_pow_of_two(max_cnt); |
642 | if ((u32)hr_qp->sq.wqe_cnt > hr_dev->caps.max_wqes) { | |
926a01dc | 643 | dev_err(dev, "while setting kernel sq size, sq.wqe_cnt too large\n"); |
9a443537 | 644 | return -EINVAL; |
645 | } | |
646 | ||
647 | /* Get data_seg numbers */ | |
648 | max_cnt = max(1U, cap->max_send_sge); | |
b7f5a64a | 649 | if (hr_dev->hw_rev == HNS_ROCE_HW_VER1) |
926a01dc WHX |
650 | hr_qp->sq.max_gs = roundup_pow_of_two(max_cnt); |
651 | else | |
652 | hr_qp->sq.max_gs = max_cnt; | |
9a443537 | 653 | |
947441ea LO |
654 | ret = set_extend_sge_param(hr_dev, hr_qp); |
655 | if (ret) { | |
656 | dev_err(dev, "set extend sge parameters fail\n"); | |
657 | return ret; | |
05ad5482 LO |
658 | } |
659 | ||
926a01dc | 660 | /* Get buf size, SQ and RQ are aligned to PAGE_SIZE */ |
9a8982dc | 661 | page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT); |
9a443537 | 662 | hr_qp->sq.offset = 0; |
b02f2326 | 663 | size = round_up(hr_qp->sq.wqe_cnt << hr_qp->sq.wqe_shift, page_size); |
926a01dc | 664 | |
b7f5a64a | 665 | if (hr_dev->hw_rev != HNS_ROCE_HW_VER1 && hr_qp->sge.sge_cnt) { |
b28ca7cc | 666 | hr_qp->sge.sge_cnt = max(page_size/(1 << hr_qp->sge.sge_shift), |
b02f2326 | 667 | (u32)hr_qp->sge.sge_cnt); |
926a01dc | 668 | hr_qp->sge.offset = size; |
b02f2326 WL |
669 | size += round_up(hr_qp->sge.sge_cnt << hr_qp->sge.sge_shift, |
670 | page_size); | |
926a01dc WHX |
671 | } |
672 | ||
673 | hr_qp->rq.offset = size; | |
b02f2326 | 674 | size += round_up((hr_qp->rq.wqe_cnt << hr_qp->rq.wqe_shift), page_size); |
926a01dc | 675 | hr_qp->buff_size = size; |
9a443537 | 676 | |
677 | /* Get wr and sge number which send */ | |
765745c7 | 678 | cap->max_send_wr = hr_qp->sq.wqe_cnt; |
9a443537 | 679 | cap->max_send_sge = hr_qp->sq.max_gs; |
680 | ||
681 | /* We don't support inline sends for kernel QPs (yet) */ | |
682 | cap->max_inline_data = 0; | |
683 | ||
684 | return 0; | |
685 | } | |
686 | ||
0425e3e6 YL |
687 | static int hns_roce_qp_has_sq(struct ib_qp_init_attr *attr) |
688 | { | |
2557fabd | 689 | if (attr->qp_type == IB_QPT_XRC_TGT || !attr->cap.max_send_wr) |
0425e3e6 YL |
690 | return 0; |
691 | ||
692 | return 1; | |
693 | } | |
694 | ||
e088a685 YL |
695 | static int hns_roce_qp_has_rq(struct ib_qp_init_attr *attr) |
696 | { | |
697 | if (attr->qp_type == IB_QPT_XRC_INI || | |
4d103905 LO |
698 | attr->qp_type == IB_QPT_XRC_TGT || attr->srq || |
699 | !attr->cap.max_recv_wr) | |
e088a685 YL |
700 | return 0; |
701 | ||
702 | return 1; | |
703 | } | |
704 | ||
395b59a1 LO |
705 | static int alloc_rq_inline_buf(struct hns_roce_qp *hr_qp, |
706 | struct ib_qp_init_attr *init_attr) | |
707 | { | |
708 | u32 max_recv_sge = init_attr->cap.max_recv_sge; | |
709 | struct hns_roce_rinl_wqe *wqe_list; | |
710 | u32 wqe_cnt = hr_qp->rq.wqe_cnt; | |
711 | int i; | |
712 | ||
713 | /* allocate recv inline buf */ | |
714 | wqe_list = kcalloc(wqe_cnt, sizeof(struct hns_roce_rinl_wqe), | |
715 | GFP_KERNEL); | |
716 | ||
717 | if (!wqe_list) | |
718 | goto err; | |
719 | ||
720 | /* Allocate a continuous buffer for all inline sge we need */ | |
721 | wqe_list[0].sg_list = kcalloc(wqe_cnt, (max_recv_sge * | |
722 | sizeof(struct hns_roce_rinl_sge)), | |
723 | GFP_KERNEL); | |
724 | if (!wqe_list[0].sg_list) | |
725 | goto err_wqe_list; | |
726 | ||
727 | /* Assign buffers of sg_list to each inline wqe */ | |
728 | for (i = 1; i < wqe_cnt; i++) | |
729 | wqe_list[i].sg_list = &wqe_list[0].sg_list[i * max_recv_sge]; | |
730 | ||
731 | hr_qp->rq_inl_buf.wqe_list = wqe_list; | |
732 | hr_qp->rq_inl_buf.wqe_cnt = wqe_cnt; | |
733 | ||
734 | return 0; | |
735 | ||
736 | err_wqe_list: | |
737 | kfree(wqe_list); | |
738 | ||
739 | err: | |
740 | return -ENOMEM; | |
741 | } | |
742 | ||
743 | static void free_rq_inline_buf(struct hns_roce_qp *hr_qp) | |
744 | { | |
745 | kfree(hr_qp->rq_inl_buf.wqe_list[0].sg_list); | |
746 | kfree(hr_qp->rq_inl_buf.wqe_list); | |
747 | } | |
748 | ||
9a443537 | 749 | static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev, |
750 | struct ib_pd *ib_pd, | |
751 | struct ib_qp_init_attr *init_attr, | |
752 | struct ib_udata *udata, unsigned long sqpn, | |
753 | struct hns_roce_qp *hr_qp) | |
754 | { | |
bfe86035 | 755 | dma_addr_t *buf_list[ARRAY_SIZE(hr_qp->regions)] = { NULL }; |
13ca970e | 756 | struct device *dev = hr_dev->dev; |
9a443537 | 757 | struct hns_roce_ib_create_qp ucmd; |
7b48221c | 758 | struct hns_roce_ib_create_qp_resp resp = {}; |
89944450 SR |
759 | struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context( |
760 | udata, struct hns_roce_ucontext, ibucontext); | |
8d18ad83 | 761 | struct hns_roce_buf_region *r; |
9a443537 | 762 | unsigned long qpn = 0; |
9a8982dc | 763 | u32 page_shift; |
8d18ad83 LO |
764 | int buf_count; |
765 | int ret; | |
0009c2db | 766 | int i; |
9a443537 | 767 | |
768 | mutex_init(&hr_qp->mutex); | |
769 | spin_lock_init(&hr_qp->sq.lock); | |
770 | spin_lock_init(&hr_qp->rq.lock); | |
771 | ||
772 | hr_qp->state = IB_QPS_RESET; | |
5fe36e8b | 773 | hr_qp->flush_flag = 0; |
9a443537 | 774 | |
b66efc93 | 775 | hr_qp->ibqp.qp_type = init_attr->qp_type; |
776 | ||
9a443537 | 777 | if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) |
bfe86035 | 778 | hr_qp->sq_signal_bits = IB_SIGNAL_ALL_WR; |
9a443537 | 779 | else |
bfe86035 | 780 | hr_qp->sq_signal_bits = IB_SIGNAL_REQ_WR; |
9a443537 | 781 | |
e00b64f7 | 782 | ret = hns_roce_set_rq_size(hr_dev, &init_attr->cap, udata, |
c7bcb134 | 783 | hns_roce_qp_has_rq(init_attr), hr_qp); |
9a443537 | 784 | if (ret) { |
785 | dev_err(dev, "hns_roce_set_rq_size failed\n"); | |
786 | goto err_out; | |
787 | } | |
788 | ||
c7bcb134 LO |
789 | if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) && |
790 | hns_roce_qp_has_rq(init_attr)) { | |
395b59a1 LO |
791 | ret = alloc_rq_inline_buf(hr_qp, init_attr); |
792 | if (ret) { | |
793 | dev_err(dev, "allocate receive inline buffer failed\n"); | |
0009c2db | 794 | goto err_out; |
795 | } | |
0009c2db | 796 | } |
797 | ||
8d18ad83 | 798 | page_shift = PAGE_SHIFT + hr_dev->caps.mtt_buf_pg_sz; |
e00b64f7 | 799 | if (udata) { |
9a443537 | 800 | if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { |
801 | dev_err(dev, "ib_copy_from_udata error for create qp\n"); | |
802 | ret = -EFAULT; | |
395b59a1 | 803 | goto err_alloc_rq_inline_buf; |
9a443537 | 804 | } |
805 | ||
926a01dc WHX |
806 | ret = hns_roce_set_user_sq_size(hr_dev, &init_attr->cap, hr_qp, |
807 | &ucmd); | |
9a443537 | 808 | if (ret) { |
809 | dev_err(dev, "hns_roce_set_user_sq_size error for create qp\n"); | |
395b59a1 | 810 | goto err_alloc_rq_inline_buf; |
9a443537 | 811 | } |
812 | ||
b0ea0fa5 | 813 | hr_qp->umem = ib_umem_get(udata, ucmd.buf_addr, |
6bcdda0d | 814 | hr_qp->buff_size, 0); |
9a443537 | 815 | if (IS_ERR(hr_qp->umem)) { |
816 | dev_err(dev, "ib_umem_get error for create qp\n"); | |
817 | ret = PTR_ERR(hr_qp->umem); | |
395b59a1 | 818 | goto err_alloc_rq_inline_buf; |
9a443537 | 819 | } |
8d18ad83 LO |
820 | hr_qp->region_cnt = split_wqe_buf_region(hr_dev, hr_qp, |
821 | hr_qp->regions, ARRAY_SIZE(hr_qp->regions), | |
822 | page_shift); | |
823 | ret = hns_roce_alloc_buf_list(hr_qp->regions, buf_list, | |
824 | hr_qp->region_cnt); | |
9a443537 | 825 | if (ret) { |
8d18ad83 LO |
826 | dev_err(dev, "alloc buf_list error for create qp\n"); |
827 | goto err_alloc_list; | |
9a443537 | 828 | } |
829 | ||
8d18ad83 LO |
830 | for (i = 0; i < hr_qp->region_cnt; i++) { |
831 | r = &hr_qp->regions[i]; | |
832 | buf_count = hns_roce_get_umem_bufs(hr_dev, | |
833 | buf_list[i], r->count, r->offset, | |
834 | hr_qp->umem, page_shift); | |
835 | if (buf_count != r->count) { | |
836 | dev_err(dev, | |
837 | "get umem buf err, expect %d,ret %d.\n", | |
838 | r->count, buf_count); | |
839 | ret = -ENOBUFS; | |
840 | goto err_get_bufs; | |
841 | } | |
9a443537 | 842 | } |
e088a685 | 843 | |
0425e3e6 YL |
844 | if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SQ_RECORD_DB) && |
845 | (udata->inlen >= sizeof(ucmd)) && | |
846 | (udata->outlen >= sizeof(resp)) && | |
847 | hns_roce_qp_has_sq(init_attr)) { | |
89944450 SR |
848 | ret = hns_roce_db_map_user(uctx, udata, ucmd.sdb_addr, |
849 | &hr_qp->sdb); | |
0425e3e6 YL |
850 | if (ret) { |
851 | dev_err(dev, "sq record doorbell map failed!\n"); | |
8d18ad83 | 852 | goto err_get_bufs; |
0425e3e6 YL |
853 | } |
854 | ||
855 | /* indicate kernel supports sq record db */ | |
856 | resp.cap_flags |= HNS_ROCE_SUPPORT_SQ_RECORD_DB; | |
857 | hr_qp->sdb_en = 1; | |
858 | } | |
859 | ||
e088a685 | 860 | if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) && |
7b48221c | 861 | (udata->outlen >= sizeof(resp)) && |
e088a685 | 862 | hns_roce_qp_has_rq(init_attr)) { |
89944450 SR |
863 | ret = hns_roce_db_map_user(uctx, udata, ucmd.db_addr, |
864 | &hr_qp->rdb); | |
e088a685 | 865 | if (ret) { |
ab178849 | 866 | dev_err(dev, "rq record doorbell map failed!\n"); |
0425e3e6 | 867 | goto err_sq_dbmap; |
e088a685 | 868 | } |
de77503a LO |
869 | |
870 | /* indicate kernel supports rq record db */ | |
871 | resp.cap_flags |= HNS_ROCE_SUPPORT_RQ_RECORD_DB; | |
872 | hr_qp->rdb_en = 1; | |
e088a685 | 873 | } |
9a443537 | 874 | } else { |
875 | if (init_attr->create_flags & | |
876 | IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { | |
877 | dev_err(dev, "init_attr->create_flags error!\n"); | |
878 | ret = -EINVAL; | |
395b59a1 | 879 | goto err_alloc_rq_inline_buf; |
9a443537 | 880 | } |
881 | ||
882 | if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) { | |
883 | dev_err(dev, "init_attr->create_flags error!\n"); | |
884 | ret = -EINVAL; | |
395b59a1 | 885 | goto err_alloc_rq_inline_buf; |
9a443537 | 886 | } |
887 | ||
888 | /* Set SQ size */ | |
889 | ret = hns_roce_set_kernel_sq_size(hr_dev, &init_attr->cap, | |
76445703 | 890 | hr_qp); |
9a443537 | 891 | if (ret) { |
892 | dev_err(dev, "hns_roce_set_kernel_sq_size error!\n"); | |
395b59a1 | 893 | goto err_alloc_rq_inline_buf; |
9a443537 | 894 | } |
895 | ||
896 | /* QP doorbell register address */ | |
2d407888 | 897 | hr_qp->sq.db_reg_l = hr_dev->reg_base + hr_dev->sdb_offset + |
9a443537 | 898 | DB_REG_OFFSET * hr_dev->priv_uar.index; |
2d407888 | 899 | hr_qp->rq.db_reg_l = hr_dev->reg_base + hr_dev->odb_offset + |
9a443537 | 900 | DB_REG_OFFSET * hr_dev->priv_uar.index; |
901 | ||
472bc0fb YL |
902 | if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) && |
903 | hns_roce_qp_has_rq(init_attr)) { | |
904 | ret = hns_roce_alloc_db(hr_dev, &hr_qp->rdb, 0); | |
905 | if (ret) { | |
906 | dev_err(dev, "rq record doorbell alloc failed!\n"); | |
395b59a1 | 907 | goto err_alloc_rq_inline_buf; |
472bc0fb YL |
908 | } |
909 | *hr_qp->rdb.db_record = 0; | |
3a39bbec | 910 | hr_qp->rdb_en = 1; |
472bc0fb YL |
911 | } |
912 | ||
9a443537 | 913 | /* Allocate QP buf */ |
9a8982dc WHX |
914 | if (hns_roce_buf_alloc(hr_dev, hr_qp->buff_size, |
915 | (1 << page_shift) * 2, | |
916 | &hr_qp->hr_buf, page_shift)) { | |
9a443537 | 917 | dev_err(dev, "hns_roce_buf_alloc error!\n"); |
918 | ret = -ENOMEM; | |
472bc0fb | 919 | goto err_db; |
9a443537 | 920 | } |
8d18ad83 LO |
921 | hr_qp->region_cnt = split_wqe_buf_region(hr_dev, hr_qp, |
922 | hr_qp->regions, ARRAY_SIZE(hr_qp->regions), | |
923 | page_shift); | |
924 | ret = hns_roce_alloc_buf_list(hr_qp->regions, buf_list, | |
925 | hr_qp->region_cnt); | |
9a443537 | 926 | if (ret) { |
8d18ad83 LO |
927 | dev_err(dev, "alloc buf_list error for create qp!\n"); |
928 | goto err_alloc_list; | |
9a443537 | 929 | } |
930 | ||
8d18ad83 LO |
931 | for (i = 0; i < hr_qp->region_cnt; i++) { |
932 | r = &hr_qp->regions[i]; | |
933 | buf_count = hns_roce_get_kmem_bufs(hr_dev, | |
934 | buf_list[i], r->count, r->offset, | |
935 | &hr_qp->hr_buf); | |
936 | if (buf_count != r->count) { | |
937 | dev_err(dev, | |
938 | "get kmem buf err, expect %d,ret %d.\n", | |
939 | r->count, buf_count); | |
940 | ret = -ENOBUFS; | |
941 | goto err_get_bufs; | |
942 | } | |
9a443537 | 943 | } |
944 | ||
f7f27a5f YL |
945 | hr_qp->sq.wrid = kcalloc(hr_qp->sq.wqe_cnt, sizeof(u64), |
946 | GFP_KERNEL); | |
76827087 | 947 | if (ZERO_OR_NULL_PTR(hr_qp->sq.wrid)) { |
9a443537 | 948 | ret = -ENOMEM; |
76827087 LO |
949 | goto err_get_bufs; |
950 | } | |
951 | ||
952 | if (hr_qp->rq.wqe_cnt) { | |
953 | hr_qp->rq.wrid = kcalloc(hr_qp->rq.wqe_cnt, sizeof(u64), | |
954 | GFP_KERNEL); | |
955 | if (ZERO_OR_NULL_PTR(hr_qp->rq.wrid)) { | |
956 | ret = -ENOMEM; | |
957 | goto err_sq_wrid; | |
958 | } | |
9a443537 | 959 | } |
960 | } | |
961 | ||
962 | if (sqpn) { | |
963 | qpn = sqpn; | |
964 | } else { | |
965 | /* Get QPN */ | |
966 | ret = hns_roce_reserve_range_qp(hr_dev, 1, 1, &qpn); | |
967 | if (ret) { | |
968 | dev_err(dev, "hns_roce_reserve_range_qp alloc qpn error\n"); | |
969 | goto err_wrid; | |
970 | } | |
971 | } | |
972 | ||
d08c74b1 XW |
973 | hr_qp->qpn = qpn; |
974 | ||
8d18ad83 LO |
975 | hr_qp->wqe_bt_pg_shift = calc_wqe_bt_page_shift(hr_dev, hr_qp->regions, |
976 | hr_qp->region_cnt); | |
977 | hns_roce_mtr_init(&hr_qp->mtr, PAGE_SHIFT + hr_qp->wqe_bt_pg_shift, | |
978 | page_shift); | |
979 | ret = hns_roce_mtr_attach(hr_dev, &hr_qp->mtr, buf_list, | |
980 | hr_qp->regions, hr_qp->region_cnt); | |
981 | if (ret) { | |
10dcc744 | 982 | dev_err(dev, "mtr attach error for create qp\n"); |
8d18ad83 LO |
983 | goto err_mtr; |
984 | } | |
985 | ||
d08c74b1 XW |
986 | ret = alloc_qpc(hr_dev, hr_qp); |
987 | if (ret) { | |
988 | ibdev_err(&hr_dev->ib_dev, "Failed to alloc QP context\n"); | |
989 | goto err_qpn; | |
990 | } | |
991 | ||
992 | ret = hns_roce_qp_store(hr_dev, hr_qp, init_attr); | |
993 | if (ret) { | |
994 | ibdev_err(&hr_dev->ib_dev, "Failed to store QP\n"); | |
995 | goto err_qpc; | |
9a443537 | 996 | } |
997 | ||
998 | if (sqpn) | |
999 | hr_qp->doorbell_qpn = 1; | |
1000 | else | |
bfe86035 | 1001 | hr_qp->doorbell_qpn = (u32)hr_qp->qpn; |
9a443537 | 1002 | |
de77503a LO |
1003 | if (udata) { |
1004 | ret = ib_copy_to_udata(udata, &resp, | |
1005 | min(udata->outlen, sizeof(resp))); | |
e088a685 | 1006 | if (ret) |
d08c74b1 | 1007 | goto err_store; |
e088a685 | 1008 | } |
aa84fa18 YL |
1009 | |
1010 | if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) { | |
1011 | ret = hr_dev->hw->qp_flow_control_init(hr_dev, hr_qp); | |
1012 | if (ret) | |
d08c74b1 | 1013 | goto err_store; |
aa84fa18 YL |
1014 | } |
1015 | ||
9a443537 | 1016 | hr_qp->event = hns_roce_ib_qp_event; |
d08c74b1 XW |
1017 | atomic_set(&hr_qp->refcount, 1); |
1018 | init_completion(&hr_qp->free); | |
90e9dc85 | 1019 | |
8d18ad83 | 1020 | hns_roce_free_buf_list(buf_list, hr_qp->region_cnt); |
9a443537 | 1021 | |
1022 | return 0; | |
1023 | ||
d08c74b1 XW |
1024 | err_store: |
1025 | hns_roce_qp_remove(hr_dev, hr_qp); | |
1026 | ||
1027 | err_qpc: | |
1028 | free_qpc(hr_dev, hr_qp); | |
e088a685 | 1029 | |
9a443537 | 1030 | err_qpn: |
1031 | if (!sqpn) | |
1032 | hns_roce_release_range_qp(hr_dev, qpn, 1); | |
1033 | ||
8d18ad83 LO |
1034 | err_mtr: |
1035 | hns_roce_mtr_cleanup(hr_dev, &hr_qp->mtr); | |
1036 | ||
9a443537 | 1037 | err_wrid: |
e00b64f7 | 1038 | if (udata) { |
e088a685 | 1039 | if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) && |
7b48221c | 1040 | (udata->outlen >= sizeof(resp)) && |
e088a685 | 1041 | hns_roce_qp_has_rq(init_attr)) |
89944450 | 1042 | hns_roce_db_unmap_user(uctx, &hr_qp->rdb); |
e088a685 | 1043 | } else { |
76827087 LO |
1044 | if (hr_qp->rq.wqe_cnt) |
1045 | kfree(hr_qp->rq.wrid); | |
e088a685 | 1046 | } |
9a443537 | 1047 | |
0425e3e6 | 1048 | err_sq_dbmap: |
e00b64f7 | 1049 | if (udata) |
0425e3e6 YL |
1050 | if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SQ_RECORD_DB) && |
1051 | (udata->inlen >= sizeof(ucmd)) && | |
1052 | (udata->outlen >= sizeof(resp)) && | |
1053 | hns_roce_qp_has_sq(init_attr)) | |
89944450 | 1054 | hns_roce_db_unmap_user(uctx, &hr_qp->sdb); |
0425e3e6 | 1055 | |
76827087 LO |
1056 | err_sq_wrid: |
1057 | if (!udata) | |
1058 | kfree(hr_qp->sq.wrid); | |
1059 | ||
8d18ad83 LO |
1060 | err_get_bufs: |
1061 | hns_roce_free_buf_list(buf_list, hr_qp->region_cnt); | |
9a443537 | 1062 | |
8d18ad83 | 1063 | err_alloc_list: |
836a0fbb | 1064 | if (!hr_qp->umem) |
9a443537 | 1065 | hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf); |
836a0fbb | 1066 | ib_umem_release(hr_qp->umem); |
9a443537 | 1067 | |
472bc0fb | 1068 | err_db: |
e00b64f7 | 1069 | if (!udata && hns_roce_qp_has_rq(init_attr) && |
472bc0fb YL |
1070 | (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB)) |
1071 | hns_roce_free_db(hr_dev, &hr_qp->rdb); | |
1072 | ||
395b59a1 | 1073 | err_alloc_rq_inline_buf: |
947441ea LO |
1074 | if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) && |
1075 | hns_roce_qp_has_rq(init_attr)) | |
395b59a1 | 1076 | free_rq_inline_buf(hr_qp); |
0009c2db | 1077 | |
9a443537 | 1078 | err_out: |
1079 | return ret; | |
1080 | } | |
1081 | ||
8831aa4c XW |
1082 | void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, |
1083 | struct ib_udata *udata) | |
1084 | { | |
d08c74b1 XW |
1085 | if (atomic_dec_and_test(&hr_qp->refcount)) |
1086 | complete(&hr_qp->free); | |
1087 | wait_for_completion(&hr_qp->free); | |
1088 | ||
1089 | free_qpc(hr_dev, hr_qp); | |
8831aa4c XW |
1090 | |
1091 | /* Not special_QP, free their QPN */ | |
1092 | if (hr_qp->ibqp.qp_type != IB_QPT_GSI) | |
1093 | hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1); | |
1094 | ||
1095 | hns_roce_mtr_cleanup(hr_dev, &hr_qp->mtr); | |
1096 | ||
1097 | if (udata) { | |
1098 | struct hns_roce_ucontext *context = | |
1099 | rdma_udata_to_drv_context( | |
1100 | udata, | |
1101 | struct hns_roce_ucontext, | |
1102 | ibucontext); | |
1103 | ||
1104 | if (hr_qp->sq.wqe_cnt && (hr_qp->sdb_en == 1)) | |
1105 | hns_roce_db_unmap_user(context, &hr_qp->sdb); | |
1106 | ||
1107 | if (hr_qp->rq.wqe_cnt && (hr_qp->rdb_en == 1)) | |
1108 | hns_roce_db_unmap_user(context, &hr_qp->rdb); | |
1109 | } else { | |
1110 | kfree(hr_qp->sq.wrid); | |
1111 | kfree(hr_qp->rq.wrid); | |
1112 | hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf); | |
1113 | if (hr_qp->rq.wqe_cnt) | |
1114 | hns_roce_free_db(hr_dev, &hr_qp->rdb); | |
1115 | } | |
1116 | ib_umem_release(hr_qp->umem); | |
1117 | ||
1118 | if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) && | |
1119 | hr_qp->rq.wqe_cnt) { | |
1120 | kfree(hr_qp->rq_inl_buf.wqe_list[0].sg_list); | |
1121 | kfree(hr_qp->rq_inl_buf.wqe_list); | |
1122 | } | |
1123 | ||
1124 | kfree(hr_qp); | |
1125 | } | |
1126 | ||
9a443537 | 1127 | struct ib_qp *hns_roce_create_qp(struct ib_pd *pd, |
1128 | struct ib_qp_init_attr *init_attr, | |
1129 | struct ib_udata *udata) | |
1130 | { | |
1131 | struct hns_roce_dev *hr_dev = to_hr_dev(pd->device); | |
db50077b | 1132 | struct ib_device *ibdev = &hr_dev->ib_dev; |
9a443537 | 1133 | struct hns_roce_qp *hr_qp; |
1134 | int ret; | |
1135 | ||
1136 | switch (init_attr->qp_type) { | |
1137 | case IB_QPT_RC: { | |
1138 | hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL); | |
1139 | if (!hr_qp) | |
1140 | return ERR_PTR(-ENOMEM); | |
1141 | ||
1142 | ret = hns_roce_create_qp_common(hr_dev, pd, init_attr, udata, 0, | |
1143 | hr_qp); | |
1144 | if (ret) { | |
abcd6693 | 1145 | ibdev_err(ibdev, "Create QP 0x%06lx failed(%d)\n", |
db50077b | 1146 | hr_qp->qpn, ret); |
9a443537 | 1147 | kfree(hr_qp); |
1148 | return ERR_PTR(ret); | |
1149 | } | |
1150 | ||
1151 | hr_qp->ibqp.qp_num = hr_qp->qpn; | |
1152 | ||
1153 | break; | |
1154 | } | |
1155 | case IB_QPT_GSI: { | |
1156 | /* Userspace is not allowed to create special QPs: */ | |
e00b64f7 | 1157 | if (udata) { |
db50077b | 1158 | ibdev_err(ibdev, "not support usr space GSI\n"); |
9a443537 | 1159 | return ERR_PTR(-EINVAL); |
1160 | } | |
1161 | ||
9bd24d99 LC |
1162 | hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL); |
1163 | if (!hr_qp) | |
9a443537 | 1164 | return ERR_PTR(-ENOMEM); |
1165 | ||
7716809e LO |
1166 | hr_qp->port = init_attr->port_num - 1; |
1167 | hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; | |
b66efc93 | 1168 | |
1169 | /* when hw version is v1, the sqpn is allocated */ | |
b7f5a64a | 1170 | if (hr_dev->hw_rev == HNS_ROCE_HW_VER1) |
b66efc93 | 1171 | hr_qp->ibqp.qp_num = HNS_ROCE_MAX_PORTS + |
1172 | hr_dev->iboe.phy_port[hr_qp->port]; | |
1173 | else | |
1174 | hr_qp->ibqp.qp_num = 1; | |
9a443537 | 1175 | |
1176 | ret = hns_roce_create_qp_common(hr_dev, pd, init_attr, udata, | |
7716809e | 1177 | hr_qp->ibqp.qp_num, hr_qp); |
9a443537 | 1178 | if (ret) { |
db50077b | 1179 | ibdev_err(ibdev, "Create GSI QP failed!\n"); |
9bd24d99 | 1180 | kfree(hr_qp); |
9a443537 | 1181 | return ERR_PTR(ret); |
1182 | } | |
1183 | ||
9a443537 | 1184 | break; |
1185 | } | |
1186 | default:{ | |
db50077b LO |
1187 | ibdev_err(ibdev, "not support QP type %d\n", |
1188 | init_attr->qp_type); | |
9a443537 | 1189 | return ERR_PTR(-EINVAL); |
1190 | } | |
1191 | } | |
1192 | ||
1193 | return &hr_qp->ibqp; | |
1194 | } | |
1195 | ||
1196 | int to_hr_qp_type(int qp_type) | |
1197 | { | |
1198 | int transport_type; | |
1199 | ||
1200 | if (qp_type == IB_QPT_RC) | |
1201 | transport_type = SERV_TYPE_RC; | |
1202 | else if (qp_type == IB_QPT_UC) | |
1203 | transport_type = SERV_TYPE_UC; | |
1204 | else if (qp_type == IB_QPT_UD) | |
1205 | transport_type = SERV_TYPE_UD; | |
1206 | else if (qp_type == IB_QPT_GSI) | |
1207 | transport_type = SERV_TYPE_UD; | |
1208 | else | |
1209 | transport_type = -1; | |
1210 | ||
1211 | return transport_type; | |
1212 | } | |
1213 | ||
8ea417ff LO |
1214 | static int check_mtu_validate(struct hns_roce_dev *hr_dev, |
1215 | struct hns_roce_qp *hr_qp, | |
1216 | struct ib_qp_attr *attr, int attr_mask) | |
9a443537 | 1217 | { |
cb814642 | 1218 | enum ib_mtu active_mtu; |
8ea417ff | 1219 | int p; |
9a443537 | 1220 | |
8ea417ff | 1221 | p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port; |
a7325af7 | 1222 | active_mtu = iboe_get_mtu(hr_dev->iboe.netdevs[p]->mtu); |
de77503a | 1223 | |
8ea417ff LO |
1224 | if ((hr_dev->caps.max_mtu >= IB_MTU_2048 && |
1225 | attr->path_mtu > hr_dev->caps.max_mtu) || | |
1226 | attr->path_mtu < IB_MTU_256 || attr->path_mtu > active_mtu) { | |
db50077b LO |
1227 | ibdev_err(&hr_dev->ib_dev, |
1228 | "attr path_mtu(%d)invalid while modify qp", | |
8ea417ff LO |
1229 | attr->path_mtu); |
1230 | return -EINVAL; | |
0425e3e6 YL |
1231 | } |
1232 | ||
8ea417ff LO |
1233 | return 0; |
1234 | } | |
1235 | ||
1236 | static int hns_roce_check_qp_attr(struct ib_qp *ibqp, struct ib_qp_attr *attr, | |
1237 | int attr_mask) | |
1238 | { | |
1239 | struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); | |
1240 | struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); | |
8ea417ff | 1241 | int p; |
9a443537 | 1242 | |
1243 | if ((attr_mask & IB_QP_PORT) && | |
1244 | (attr->port_num == 0 || attr->port_num > hr_dev->caps.num_ports)) { | |
db50077b LO |
1245 | ibdev_err(&hr_dev->ib_dev, |
1246 | "attr port_num invalid.attr->port_num=%d\n", | |
9a443537 | 1247 | attr->port_num); |
8ea417ff | 1248 | return -EINVAL; |
9a443537 | 1249 | } |
1250 | ||
1251 | if (attr_mask & IB_QP_PKEY_INDEX) { | |
1252 | p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port; | |
1253 | if (attr->pkey_index >= hr_dev->caps.pkey_table_len[p]) { | |
db50077b LO |
1254 | ibdev_err(&hr_dev->ib_dev, |
1255 | "attr pkey_index invalid.attr->pkey_index=%d\n", | |
9a443537 | 1256 | attr->pkey_index); |
8ea417ff | 1257 | return -EINVAL; |
cb814642 LO |
1258 | } |
1259 | } | |
1260 | ||
9a443537 | 1261 | if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && |
1262 | attr->max_rd_atomic > hr_dev->caps.max_qp_init_rdma) { | |
db50077b LO |
1263 | ibdev_err(&hr_dev->ib_dev, |
1264 | "attr max_rd_atomic invalid.attr->max_rd_atomic=%d\n", | |
9a443537 | 1265 | attr->max_rd_atomic); |
8ea417ff | 1266 | return -EINVAL; |
9a443537 | 1267 | } |
1268 | ||
1269 | if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && | |
1270 | attr->max_dest_rd_atomic > hr_dev->caps.max_qp_dest_rdma) { | |
db50077b LO |
1271 | ibdev_err(&hr_dev->ib_dev, |
1272 | "attr max_dest_rd_atomic invalid.attr->max_dest_rd_atomic=%d\n", | |
9a443537 | 1273 | attr->max_dest_rd_atomic); |
8ea417ff LO |
1274 | return -EINVAL; |
1275 | } | |
1276 | ||
1277 | if (attr_mask & IB_QP_PATH_MTU) | |
1278 | return check_mtu_validate(hr_dev, hr_qp, attr, attr_mask); | |
1279 | ||
1280 | return 0; | |
1281 | } | |
1282 | ||
1283 | int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, | |
1284 | int attr_mask, struct ib_udata *udata) | |
1285 | { | |
1286 | struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); | |
1287 | struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); | |
1288 | enum ib_qp_state cur_state, new_state; | |
8ea417ff LO |
1289 | int ret = -EINVAL; |
1290 | ||
1291 | mutex_lock(&hr_qp->mutex); | |
1292 | ||
1293 | cur_state = attr_mask & IB_QP_CUR_STATE ? | |
1294 | attr->cur_qp_state : (enum ib_qp_state)hr_qp->state; | |
1295 | new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; | |
1296 | ||
1297 | if (ibqp->uobject && | |
1298 | (attr_mask & IB_QP_STATE) && new_state == IB_QPS_ERR) { | |
1299 | if (hr_qp->sdb_en == 1) { | |
1300 | hr_qp->sq.head = *(int *)(hr_qp->sdb.virt_addr); | |
1301 | ||
1302 | if (hr_qp->rdb_en == 1) | |
1303 | hr_qp->rq.head = *(int *)(hr_qp->rdb.virt_addr); | |
1304 | } else { | |
db50077b LO |
1305 | ibdev_warn(&hr_dev->ib_dev, |
1306 | "flush cqe is not supported in userspace!\n"); | |
8ea417ff LO |
1307 | goto out; |
1308 | } | |
1309 | } | |
1310 | ||
1311 | if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, | |
1312 | attr_mask)) { | |
db50077b | 1313 | ibdev_err(&hr_dev->ib_dev, "ib_modify_qp_is_ok failed\n"); |
9a443537 | 1314 | goto out; |
1315 | } | |
1316 | ||
8ea417ff LO |
1317 | ret = hns_roce_check_qp_attr(ibqp, attr, attr_mask); |
1318 | if (ret) | |
1319 | goto out; | |
1320 | ||
9a443537 | 1321 | if (cur_state == new_state && cur_state == IB_QPS_RESET) { |
391bd5fc | 1322 | if (hr_dev->caps.min_wqes) { |
1323 | ret = -EPERM; | |
db50077b LO |
1324 | ibdev_err(&hr_dev->ib_dev, |
1325 | "cur_state=%d new_state=%d\n", cur_state, | |
391bd5fc | 1326 | new_state); |
1327 | } else { | |
1328 | ret = 0; | |
1329 | } | |
1330 | ||
9a443537 | 1331 | goto out; |
1332 | } | |
1333 | ||
1334 | ret = hr_dev->hw->modify_qp(ibqp, attr, attr_mask, cur_state, | |
1335 | new_state); | |
1336 | ||
1337 | out: | |
1338 | mutex_unlock(&hr_qp->mutex); | |
1339 | ||
1340 | return ret; | |
1341 | } | |
1342 | ||
1343 | void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, struct hns_roce_cq *recv_cq) | |
1344 | __acquires(&send_cq->lock) __acquires(&recv_cq->lock) | |
1345 | { | |
90e9dc85 XW |
1346 | if (unlikely(send_cq == NULL && recv_cq == NULL)) { |
1347 | __acquire(&send_cq->lock); | |
1348 | __acquire(&recv_cq->lock); | |
1349 | } else if (unlikely(send_cq != NULL && recv_cq == NULL)) { | |
1350 | spin_lock_irq(&send_cq->lock); | |
1351 | __acquire(&recv_cq->lock); | |
1352 | } else if (unlikely(send_cq == NULL && recv_cq != NULL)) { | |
1353 | spin_lock_irq(&recv_cq->lock); | |
1354 | __acquire(&send_cq->lock); | |
1355 | } else if (send_cq == recv_cq) { | |
9a443537 | 1356 | spin_lock_irq(&send_cq->lock); |
1357 | __acquire(&recv_cq->lock); | |
1358 | } else if (send_cq->cqn < recv_cq->cqn) { | |
1359 | spin_lock_irq(&send_cq->lock); | |
1360 | spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING); | |
1361 | } else { | |
1362 | spin_lock_irq(&recv_cq->lock); | |
1363 | spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING); | |
1364 | } | |
1365 | } | |
1366 | ||
1367 | void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, | |
1368 | struct hns_roce_cq *recv_cq) __releases(&send_cq->lock) | |
1369 | __releases(&recv_cq->lock) | |
1370 | { | |
90e9dc85 XW |
1371 | if (unlikely(send_cq == NULL && recv_cq == NULL)) { |
1372 | __release(&recv_cq->lock); | |
1373 | __release(&send_cq->lock); | |
1374 | } else if (unlikely(send_cq != NULL && recv_cq == NULL)) { | |
1375 | __release(&recv_cq->lock); | |
1376 | spin_unlock(&send_cq->lock); | |
1377 | } else if (unlikely(send_cq == NULL && recv_cq != NULL)) { | |
1378 | __release(&send_cq->lock); | |
1379 | spin_unlock(&recv_cq->lock); | |
1380 | } else if (send_cq == recv_cq) { | |
9a443537 | 1381 | __release(&recv_cq->lock); |
1382 | spin_unlock_irq(&send_cq->lock); | |
1383 | } else if (send_cq->cqn < recv_cq->cqn) { | |
1384 | spin_unlock(&recv_cq->lock); | |
1385 | spin_unlock_irq(&send_cq->lock); | |
1386 | } else { | |
1387 | spin_unlock(&send_cq->lock); | |
1388 | spin_unlock_irq(&recv_cq->lock); | |
1389 | } | |
1390 | } | |
1391 | ||
9a443537 | 1392 | static void *get_wqe(struct hns_roce_qp *hr_qp, int offset) |
1393 | { | |
1394 | ||
1395 | return hns_roce_buf_offset(&hr_qp->hr_buf, offset); | |
1396 | } | |
1397 | ||
1398 | void *get_recv_wqe(struct hns_roce_qp *hr_qp, int n) | |
1399 | { | |
9a443537 | 1400 | return get_wqe(hr_qp, hr_qp->rq.offset + (n << hr_qp->rq.wqe_shift)); |
1401 | } | |
1402 | ||
1403 | void *get_send_wqe(struct hns_roce_qp *hr_qp, int n) | |
1404 | { | |
9a443537 | 1405 | return get_wqe(hr_qp, hr_qp->sq.offset + (n << hr_qp->sq.wqe_shift)); |
1406 | } | |
1407 | ||
926a01dc WHX |
1408 | void *get_send_extend_sge(struct hns_roce_qp *hr_qp, int n) |
1409 | { | |
1410 | return hns_roce_buf_offset(&hr_qp->hr_buf, hr_qp->sge.offset + | |
1411 | (n << hr_qp->sge.sge_shift)); | |
1412 | } | |
926a01dc | 1413 | |
9a443537 | 1414 | bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq, |
1415 | struct ib_cq *ib_cq) | |
1416 | { | |
1417 | struct hns_roce_cq *hr_cq; | |
1418 | u32 cur; | |
1419 | ||
1420 | cur = hr_wq->head - hr_wq->tail; | |
765745c7 | 1421 | if (likely(cur + nreq < hr_wq->wqe_cnt)) |
3756c7f5 | 1422 | return false; |
9a443537 | 1423 | |
1424 | hr_cq = to_hr_cq(ib_cq); | |
1425 | spin_lock(&hr_cq->lock); | |
1426 | cur = hr_wq->head - hr_wq->tail; | |
1427 | spin_unlock(&hr_cq->lock); | |
1428 | ||
765745c7 | 1429 | return cur + nreq >= hr_wq->wqe_cnt; |
9a443537 | 1430 | } |
1431 | ||
1432 | int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev) | |
1433 | { | |
1434 | struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; | |
1435 | int reserved_from_top = 0; | |
06ef0ee4 | 1436 | int reserved_from_bot; |
9a443537 | 1437 | int ret; |
1438 | ||
aa84fa18 | 1439 | mutex_init(&qp_table->scc_mutex); |
736b5a70 | 1440 | xa_init(&hr_dev->qp_table_xa); |
9a443537 | 1441 | |
21b97f53 | 1442 | reserved_from_bot = hr_dev->caps.reserved_qps; |
06ef0ee4 | 1443 | |
9a443537 | 1444 | ret = hns_roce_bitmap_init(&qp_table->bitmap, hr_dev->caps.num_qps, |
06ef0ee4 | 1445 | hr_dev->caps.num_qps - 1, reserved_from_bot, |
9a443537 | 1446 | reserved_from_top); |
1447 | if (ret) { | |
13ca970e | 1448 | dev_err(hr_dev->dev, "qp bitmap init failed!error=%d\n", |
9a443537 | 1449 | ret); |
1450 | return ret; | |
1451 | } | |
1452 | ||
1453 | return 0; | |
1454 | } | |
1455 | ||
1456 | void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev) | |
1457 | { | |
1458 | hns_roce_bitmap_cleanup(&hr_dev->qp_table.bitmap); | |
1459 | } |