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86dbcd0f FL |
1 | /******************************************************************************* |
2 | * | |
3 | * Copyright (c) 2015-2016 Intel Corporation. All rights reserved. | |
4 | * | |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the | |
9 | * OpenFabrics.org BSD license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or | |
12 | * without modification, are permitted provided that the following | |
13 | * conditions are met: | |
14 | * | |
15 | * - Redistributions of source code must retain the above | |
16 | * copyright notice, this list of conditions and the following | |
17 | * disclaimer. | |
18 | * | |
19 | * - Redistributions in binary form must reproduce the above | |
20 | * copyright notice, this list of conditions and the following | |
21 | * disclaimer in the documentation and/or other materials | |
22 | * provided with the distribution. | |
23 | * | |
24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
31 | * SOFTWARE. | |
32 | * | |
33 | *******************************************************************************/ | |
34 | ||
35 | #include "i40iw_osdep.h" | |
36 | #include "i40iw_register.h" | |
37 | #include "i40iw_status.h" | |
38 | #include "i40iw_hmc.h" | |
39 | ||
40 | #include "i40iw_d.h" | |
41 | #include "i40iw_type.h" | |
42 | #include "i40iw_p.h" | |
43 | #include "i40iw_vf.h" | |
44 | #include "i40iw_virtchnl.h" | |
45 | ||
46 | /** | |
47 | * i40iw_insert_wqe_hdr - write wqe header | |
48 | * @wqe: cqp wqe for header | |
49 | * @header: header for the cqp wqe | |
50 | */ | |
43bfc24e | 51 | void i40iw_insert_wqe_hdr(u64 *wqe, u64 header) |
86dbcd0f FL |
52 | { |
53 | wmb(); /* make sure WQE is populated before polarity is set */ | |
54 | set_64bit_val(wqe, 24, header); | |
55 | } | |
56 | ||
d26875b4 SS |
57 | void i40iw_check_cqp_progress(struct i40iw_cqp_timeout *cqp_timeout, struct i40iw_sc_dev *dev) |
58 | { | |
59 | if (cqp_timeout->compl_cqp_cmds != dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS]) { | |
60 | cqp_timeout->compl_cqp_cmds = dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS]; | |
61 | cqp_timeout->count = 0; | |
62 | } else { | |
63 | if (dev->cqp_cmd_stats[OP_REQUESTED_COMMANDS] != cqp_timeout->compl_cqp_cmds) | |
64 | cqp_timeout->count++; | |
65 | } | |
66 | } | |
67 | ||
86dbcd0f FL |
68 | /** |
69 | * i40iw_get_cqp_reg_info - get head and tail for cqp using registers | |
70 | * @cqp: struct for cqp hw | |
71 | * @val: cqp tail register value | |
72 | * @tail:wqtail register value | |
73 | * @error: cqp processing err | |
74 | */ | |
75 | static inline void i40iw_get_cqp_reg_info(struct i40iw_sc_cqp *cqp, | |
76 | u32 *val, | |
77 | u32 *tail, | |
78 | u32 *error) | |
79 | { | |
80 | if (cqp->dev->is_pf) { | |
81 | *val = i40iw_rd32(cqp->dev->hw, I40E_PFPE_CQPTAIL); | |
82 | *tail = RS_32(*val, I40E_PFPE_CQPTAIL_WQTAIL); | |
83 | *error = RS_32(*val, I40E_PFPE_CQPTAIL_CQP_OP_ERR); | |
84 | } else { | |
85 | *val = i40iw_rd32(cqp->dev->hw, I40E_VFPE_CQPTAIL1); | |
86 | *tail = RS_32(*val, I40E_VFPE_CQPTAIL_WQTAIL); | |
87 | *error = RS_32(*val, I40E_VFPE_CQPTAIL_CQP_OP_ERR); | |
88 | } | |
89 | } | |
90 | ||
91 | /** | |
92 | * i40iw_cqp_poll_registers - poll cqp registers | |
93 | * @cqp: struct for cqp hw | |
94 | * @tail:wqtail register value | |
95 | * @count: how many times to try for completion | |
96 | */ | |
97 | static enum i40iw_status_code i40iw_cqp_poll_registers( | |
98 | struct i40iw_sc_cqp *cqp, | |
99 | u32 tail, | |
100 | u32 count) | |
101 | { | |
102 | u32 i = 0; | |
103 | u32 newtail, error, val; | |
104 | ||
105 | while (i < count) { | |
106 | i++; | |
107 | i40iw_get_cqp_reg_info(cqp, &val, &newtail, &error); | |
108 | if (error) { | |
109 | error = (cqp->dev->is_pf) ? | |
110 | i40iw_rd32(cqp->dev->hw, I40E_PFPE_CQPERRCODES) : | |
111 | i40iw_rd32(cqp->dev->hw, I40E_VFPE_CQPERRCODES1); | |
112 | return I40IW_ERR_CQP_COMPL_ERROR; | |
113 | } | |
114 | if (newtail != tail) { | |
115 | /* SUCCESS */ | |
116 | I40IW_RING_MOVE_TAIL(cqp->sq_ring); | |
d6f7bbcc | 117 | cqp->dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS]++; |
86dbcd0f FL |
118 | return 0; |
119 | } | |
120 | udelay(I40IW_SLEEP_COUNT); | |
121 | } | |
122 | return I40IW_ERR_TIMEOUT; | |
123 | } | |
124 | ||
125 | /** | |
126 | * i40iw_sc_parse_fpm_commit_buf - parse fpm commit buffer | |
127 | * @buf: ptr to fpm commit buffer | |
128 | * @info: ptr to i40iw_hmc_obj_info struct | |
fa415379 | 129 | * @sd: number of SDs for HMC objects |
86dbcd0f FL |
130 | * |
131 | * parses fpm commit info and copy base value | |
132 | * of hmc objects in hmc_info | |
133 | */ | |
134 | static enum i40iw_status_code i40iw_sc_parse_fpm_commit_buf( | |
135 | u64 *buf, | |
fa415379 IM |
136 | struct i40iw_hmc_obj_info *info, |
137 | u32 *sd) | |
86dbcd0f FL |
138 | { |
139 | u64 temp; | |
fa415379 IM |
140 | u64 size; |
141 | u64 base = 0; | |
86dbcd0f | 142 | u32 i, j; |
fa415379 | 143 | u32 k = 0; |
86dbcd0f FL |
144 | |
145 | /* copy base values in obj_info */ | |
f67ace2d CTT |
146 | for (i = I40IW_HMC_IW_QP, j = 0; i <= I40IW_HMC_IW_PBLE; i++, j += 8) { |
147 | if ((i == I40IW_HMC_IW_SRQ) || | |
148 | (i == I40IW_HMC_IW_FSIMC) || | |
149 | (i == I40IW_HMC_IW_FSIAV)) { | |
150 | info[i].base = 0; | |
151 | info[i].cnt = 0; | |
152 | continue; | |
153 | } | |
86dbcd0f FL |
154 | get_64bit_val(buf, j, &temp); |
155 | info[i].base = RS_64_1(temp, 32) * 512; | |
fa415379 IM |
156 | if (info[i].base > base) { |
157 | base = info[i].base; | |
158 | k = i; | |
159 | } | |
f67ace2d CTT |
160 | if (i == I40IW_HMC_IW_APBVT_ENTRY) { |
161 | info[i].cnt = 1; | |
162 | continue; | |
163 | } | |
164 | if (i == I40IW_HMC_IW_QP) | |
165 | info[i].cnt = (u32)RS_64(temp, I40IW_QUERY_FPM_MAX_QPS); | |
166 | else if (i == I40IW_HMC_IW_CQ) | |
167 | info[i].cnt = (u32)RS_64(temp, I40IW_QUERY_FPM_MAX_CQS); | |
168 | else | |
169 | info[i].cnt = (u32)(temp); | |
86dbcd0f | 170 | } |
fa415379 IM |
171 | size = info[k].cnt * info[k].size + info[k].base; |
172 | if (size & 0x1FFFFF) | |
173 | *sd = (u32)((size >> 21) + 1); /* add 1 for remainder */ | |
174 | else | |
175 | *sd = (u32)(size >> 21); | |
176 | ||
86dbcd0f FL |
177 | return 0; |
178 | } | |
179 | ||
f67ace2d CTT |
180 | /** |
181 | * i40iw_sc_decode_fpm_query() - Decode a 64 bit value into max count and size | |
182 | * @buf: ptr to fpm query buffer | |
183 | * @buf_idx: index into buf | |
184 | * @info: ptr to i40iw_hmc_obj_info struct | |
185 | * @rsrc_idx: resource index into info | |
186 | * | |
187 | * Decode a 64 bit value from fpm query buffer into max count and size | |
188 | */ | |
189 | static u64 i40iw_sc_decode_fpm_query(u64 *buf, | |
190 | u32 buf_idx, | |
191 | struct i40iw_hmc_obj_info *obj_info, | |
192 | u32 rsrc_idx) | |
193 | { | |
194 | u64 temp; | |
195 | u32 size; | |
196 | ||
197 | get_64bit_val(buf, buf_idx, &temp); | |
198 | obj_info[rsrc_idx].max_cnt = (u32)temp; | |
199 | size = (u32)RS_64_1(temp, 32); | |
200 | obj_info[rsrc_idx].size = LS_64_1(1, size); | |
201 | ||
202 | return temp; | |
203 | } | |
204 | ||
86dbcd0f FL |
205 | /** |
206 | * i40iw_sc_parse_fpm_query_buf() - parses fpm query buffer | |
207 | * @buf: ptr to fpm query buffer | |
208 | * @info: ptr to i40iw_hmc_obj_info struct | |
209 | * @hmc_fpm_misc: ptr to fpm data | |
210 | * | |
211 | * parses fpm query buffer and copy max_cnt and | |
212 | * size value of hmc objects in hmc_info | |
213 | */ | |
214 | static enum i40iw_status_code i40iw_sc_parse_fpm_query_buf( | |
215 | u64 *buf, | |
216 | struct i40iw_hmc_info *hmc_info, | |
217 | struct i40iw_hmc_fpm_misc *hmc_fpm_misc) | |
218 | { | |
86dbcd0f | 219 | struct i40iw_hmc_obj_info *obj_info; |
f67ace2d CTT |
220 | u64 temp; |
221 | u32 size; | |
86dbcd0f FL |
222 | u16 max_pe_sds; |
223 | ||
224 | obj_info = hmc_info->hmc_obj; | |
225 | ||
226 | get_64bit_val(buf, 0, &temp); | |
227 | hmc_info->first_sd_index = (u16)RS_64(temp, I40IW_QUERY_FPM_FIRST_PE_SD_INDEX); | |
228 | max_pe_sds = (u16)RS_64(temp, I40IW_QUERY_FPM_MAX_PE_SDS); | |
229 | ||
230 | /* Reduce SD count for VFs by 1 to account for PBLE backing page rounding */ | |
231 | if (hmc_info->hmc_fn_id >= I40IW_FIRST_VF_FPM_ID) | |
232 | max_pe_sds--; | |
233 | hmc_fpm_misc->max_sds = max_pe_sds; | |
234 | hmc_info->sd_table.sd_cnt = max_pe_sds + hmc_info->first_sd_index; | |
235 | ||
f67ace2d CTT |
236 | get_64bit_val(buf, 8, &temp); |
237 | obj_info[I40IW_HMC_IW_QP].max_cnt = (u32)RS_64(temp, I40IW_QUERY_FPM_MAX_QPS); | |
238 | size = (u32)RS_64_1(temp, 32); | |
239 | obj_info[I40IW_HMC_IW_QP].size = LS_64_1(1, size); | |
86dbcd0f | 240 | |
f67ace2d CTT |
241 | get_64bit_val(buf, 16, &temp); |
242 | obj_info[I40IW_HMC_IW_CQ].max_cnt = (u32)RS_64(temp, I40IW_QUERY_FPM_MAX_CQS); | |
243 | size = (u32)RS_64_1(temp, 32); | |
244 | obj_info[I40IW_HMC_IW_CQ].size = LS_64_1(1, size); | |
245 | ||
246 | i40iw_sc_decode_fpm_query(buf, 32, obj_info, I40IW_HMC_IW_HTE); | |
247 | i40iw_sc_decode_fpm_query(buf, 40, obj_info, I40IW_HMC_IW_ARP); | |
248 | ||
249 | obj_info[I40IW_HMC_IW_APBVT_ENTRY].size = 8192; | |
250 | obj_info[I40IW_HMC_IW_APBVT_ENTRY].max_cnt = 1; | |
251 | ||
252 | i40iw_sc_decode_fpm_query(buf, 48, obj_info, I40IW_HMC_IW_MR); | |
253 | i40iw_sc_decode_fpm_query(buf, 56, obj_info, I40IW_HMC_IW_XF); | |
86dbcd0f | 254 | |
86dbcd0f | 255 | get_64bit_val(buf, 64, &temp); |
f67ace2d CTT |
256 | obj_info[I40IW_HMC_IW_XFFL].max_cnt = (u32)temp; |
257 | obj_info[I40IW_HMC_IW_XFFL].size = 4; | |
86dbcd0f FL |
258 | hmc_fpm_misc->xf_block_size = RS_64(temp, I40IW_QUERY_FPM_XFBLOCKSIZE); |
259 | if (!hmc_fpm_misc->xf_block_size) | |
260 | return I40IW_ERR_INVALID_SIZE; | |
f67ace2d CTT |
261 | |
262 | i40iw_sc_decode_fpm_query(buf, 72, obj_info, I40IW_HMC_IW_Q1); | |
263 | ||
86dbcd0f | 264 | get_64bit_val(buf, 80, &temp); |
f67ace2d CTT |
265 | obj_info[I40IW_HMC_IW_Q1FL].max_cnt = (u32)temp; |
266 | obj_info[I40IW_HMC_IW_Q1FL].size = 4; | |
86dbcd0f FL |
267 | hmc_fpm_misc->q1_block_size = RS_64(temp, I40IW_QUERY_FPM_Q1BLOCKSIZE); |
268 | if (!hmc_fpm_misc->q1_block_size) | |
269 | return I40IW_ERR_INVALID_SIZE; | |
f67ace2d CTT |
270 | |
271 | i40iw_sc_decode_fpm_query(buf, 88, obj_info, I40IW_HMC_IW_TIMER); | |
272 | ||
273 | get_64bit_val(buf, 112, &temp); | |
274 | obj_info[I40IW_HMC_IW_PBLE].max_cnt = (u32)temp; | |
275 | obj_info[I40IW_HMC_IW_PBLE].size = 8; | |
276 | ||
277 | get_64bit_val(buf, 120, &temp); | |
278 | hmc_fpm_misc->max_ceqs = (u8)RS_64(temp, I40IW_QUERY_FPM_MAX_CEQS); | |
279 | hmc_fpm_misc->ht_multiplier = RS_64(temp, I40IW_QUERY_FPM_HTMULTIPLIER); | |
280 | hmc_fpm_misc->timer_bucket = RS_64(temp, I40IW_QUERY_FPM_TIMERBUCKET); | |
281 | ||
86dbcd0f FL |
282 | return 0; |
283 | } | |
284 | ||
0fc2dc58 HO |
285 | /** |
286 | * i40iw_fill_qos_list - Change all unknown qs handles to available ones | |
287 | * @qs_list: list of qs_handles to be fixed with valid qs_handles | |
288 | */ | |
289 | static void i40iw_fill_qos_list(u16 *qs_list) | |
290 | { | |
291 | u16 qshandle = qs_list[0]; | |
292 | int i; | |
293 | ||
294 | for (i = 0; i < I40IW_MAX_USER_PRIORITY; i++) { | |
295 | if (qs_list[i] == QS_HANDLE_UNKNOWN) | |
296 | qs_list[i] = qshandle; | |
297 | else | |
298 | qshandle = qs_list[i]; | |
299 | } | |
300 | } | |
301 | ||
302 | /** | |
303 | * i40iw_qp_from_entry - Given entry, get to the qp structure | |
304 | * @entry: Points to list of qp structure | |
305 | */ | |
306 | static struct i40iw_sc_qp *i40iw_qp_from_entry(struct list_head *entry) | |
307 | { | |
308 | if (!entry) | |
309 | return NULL; | |
310 | ||
311 | return (struct i40iw_sc_qp *)((char *)entry - offsetof(struct i40iw_sc_qp, list)); | |
312 | } | |
313 | ||
314 | /** | |
315 | * i40iw_get_qp - get the next qp from the list given current qp | |
316 | * @head: Listhead of qp's | |
317 | * @qp: current qp | |
318 | */ | |
319 | static struct i40iw_sc_qp *i40iw_get_qp(struct list_head *head, struct i40iw_sc_qp *qp) | |
320 | { | |
321 | struct list_head *entry = NULL; | |
322 | struct list_head *lastentry; | |
323 | ||
324 | if (list_empty(head)) | |
325 | return NULL; | |
326 | ||
327 | if (!qp) { | |
328 | entry = head->next; | |
329 | } else { | |
330 | lastentry = &qp->list; | |
331 | entry = (lastentry != head) ? lastentry->next : NULL; | |
332 | } | |
333 | ||
334 | return i40iw_qp_from_entry(entry); | |
335 | } | |
336 | ||
337 | /** | |
338 | * i40iw_change_l2params - given the new l2 parameters, change all qp | |
d6f7bbcc | 339 | * @vsi: pointer to the vsi structure |
0fc2dc58 HO |
340 | * @l2params: New paramaters from l2 |
341 | */ | |
d6f7bbcc | 342 | void i40iw_change_l2params(struct i40iw_sc_vsi *vsi, struct i40iw_l2params *l2params) |
0fc2dc58 | 343 | { |
d6f7bbcc | 344 | struct i40iw_sc_dev *dev = vsi->dev; |
0fc2dc58 HO |
345 | struct i40iw_sc_qp *qp = NULL; |
346 | bool qs_handle_change = false; | |
0fc2dc58 HO |
347 | unsigned long flags; |
348 | u16 qs_handle; | |
349 | int i; | |
350 | ||
5b4a1a8b SS |
351 | if (vsi->mtu != l2params->mtu) { |
352 | vsi->mtu = l2params->mtu; | |
353 | i40iw_reinitialize_ieq(dev); | |
354 | } | |
0fc2dc58 HO |
355 | |
356 | i40iw_fill_qos_list(l2params->qs_handle_list); | |
357 | for (i = 0; i < I40IW_MAX_USER_PRIORITY; i++) { | |
358 | qs_handle = l2params->qs_handle_list[i]; | |
d6f7bbcc | 359 | if (vsi->qos[i].qs_handle != qs_handle) |
0fc2dc58 | 360 | qs_handle_change = true; |
d6f7bbcc HO |
361 | spin_lock_irqsave(&vsi->qos[i].lock, flags); |
362 | qp = i40iw_get_qp(&vsi->qos[i].qplist, qp); | |
0fc2dc58 | 363 | while (qp) { |
0fc2dc58 HO |
364 | if (qs_handle_change) { |
365 | qp->qs_handle = qs_handle; | |
366 | /* issue cqp suspend command */ | |
367 | i40iw_qp_suspend_resume(dev, qp, true); | |
368 | } | |
d6f7bbcc | 369 | qp = i40iw_get_qp(&vsi->qos[i].qplist, qp); |
0fc2dc58 | 370 | } |
d6f7bbcc HO |
371 | spin_unlock_irqrestore(&vsi->qos[i].lock, flags); |
372 | vsi->qos[i].qs_handle = qs_handle; | |
0fc2dc58 HO |
373 | } |
374 | } | |
375 | ||
376 | /** | |
377 | * i40iw_qp_rem_qos - remove qp from qos lists during destroy qp | |
0fc2dc58 HO |
378 | * @qp: qp to be removed from qos |
379 | */ | |
f535b56c | 380 | void i40iw_qp_rem_qos(struct i40iw_sc_qp *qp) |
0fc2dc58 | 381 | { |
d6f7bbcc | 382 | struct i40iw_sc_vsi *vsi = qp->vsi; |
0fc2dc58 HO |
383 | unsigned long flags; |
384 | ||
385 | if (!qp->on_qoslist) | |
386 | return; | |
d6f7bbcc | 387 | spin_lock_irqsave(&vsi->qos[qp->user_pri].lock, flags); |
0fc2dc58 | 388 | list_del(&qp->list); |
d6f7bbcc | 389 | spin_unlock_irqrestore(&vsi->qos[qp->user_pri].lock, flags); |
0fc2dc58 HO |
390 | } |
391 | ||
392 | /** | |
393 | * i40iw_qp_add_qos - called during setctx fot qp to be added to qos | |
0fc2dc58 HO |
394 | * @qp: qp to be added to qos |
395 | */ | |
d6f7bbcc | 396 | void i40iw_qp_add_qos(struct i40iw_sc_qp *qp) |
0fc2dc58 | 397 | { |
d6f7bbcc | 398 | struct i40iw_sc_vsi *vsi = qp->vsi; |
0fc2dc58 HO |
399 | unsigned long flags; |
400 | ||
d6f7bbcc HO |
401 | if (qp->on_qoslist) |
402 | return; | |
403 | spin_lock_irqsave(&vsi->qos[qp->user_pri].lock, flags); | |
404 | qp->qs_handle = vsi->qos[qp->user_pri].qs_handle; | |
405 | list_add(&qp->list, &vsi->qos[qp->user_pri].qplist); | |
0fc2dc58 | 406 | qp->on_qoslist = true; |
d6f7bbcc | 407 | spin_unlock_irqrestore(&vsi->qos[qp->user_pri].lock, flags); |
0fc2dc58 HO |
408 | } |
409 | ||
86dbcd0f FL |
410 | /** |
411 | * i40iw_sc_pd_init - initialize sc pd struct | |
412 | * @dev: sc device struct | |
413 | * @pd: sc pd ptr | |
414 | * @pd_id: pd_id for allocated pd | |
61f51b7b | 415 | * @abi_ver: ABI version from user context, -1 if not valid |
86dbcd0f FL |
416 | */ |
417 | static void i40iw_sc_pd_init(struct i40iw_sc_dev *dev, | |
418 | struct i40iw_sc_pd *pd, | |
61f51b7b CTT |
419 | u16 pd_id, |
420 | int abi_ver) | |
86dbcd0f FL |
421 | { |
422 | pd->size = sizeof(*pd); | |
423 | pd->pd_id = pd_id; | |
61f51b7b | 424 | pd->abi_ver = abi_ver; |
86dbcd0f FL |
425 | pd->dev = dev; |
426 | } | |
427 | ||
428 | /** | |
429 | * i40iw_get_encoded_wqe_size - given wq size, returns hardware encoded size | |
430 | * @wqsize: size of the wq (sq, rq, srq) to encoded_size | |
431 | * @cqpsq: encoded size for sq for cqp as its encoded size is 1+ other wq's | |
432 | */ | |
433 | u8 i40iw_get_encoded_wqe_size(u32 wqsize, bool cqpsq) | |
434 | { | |
435 | u8 encoded_size = 0; | |
436 | ||
437 | /* cqp sq's hw coded value starts from 1 for size of 4 | |
438 | * while it starts from 0 for qp' wq's. | |
439 | */ | |
440 | if (cqpsq) | |
441 | encoded_size = 1; | |
442 | wqsize >>= 2; | |
443 | while (wqsize >>= 1) | |
444 | encoded_size++; | |
445 | return encoded_size; | |
446 | } | |
447 | ||
448 | /** | |
449 | * i40iw_sc_cqp_init - Initialize buffers for a control Queue Pair | |
450 | * @cqp: IWARP control queue pair pointer | |
451 | * @info: IWARP control queue pair init info pointer | |
452 | * | |
453 | * Initializes the object and context buffers for a control Queue Pair. | |
454 | */ | |
455 | static enum i40iw_status_code i40iw_sc_cqp_init(struct i40iw_sc_cqp *cqp, | |
456 | struct i40iw_cqp_init_info *info) | |
457 | { | |
458 | u8 hw_sq_size; | |
459 | ||
460 | if ((info->sq_size > I40IW_CQP_SW_SQSIZE_2048) || | |
461 | (info->sq_size < I40IW_CQP_SW_SQSIZE_4) || | |
462 | ((info->sq_size & (info->sq_size - 1)))) | |
463 | return I40IW_ERR_INVALID_SIZE; | |
464 | ||
465 | hw_sq_size = i40iw_get_encoded_wqe_size(info->sq_size, true); | |
466 | cqp->size = sizeof(*cqp); | |
467 | cqp->sq_size = info->sq_size; | |
468 | cqp->hw_sq_size = hw_sq_size; | |
469 | cqp->sq_base = info->sq; | |
470 | cqp->host_ctx = info->host_ctx; | |
471 | cqp->sq_pa = info->sq_pa; | |
472 | cqp->host_ctx_pa = info->host_ctx_pa; | |
473 | cqp->dev = info->dev; | |
474 | cqp->struct_ver = info->struct_ver; | |
475 | cqp->scratch_array = info->scratch_array; | |
476 | cqp->polarity = 0; | |
477 | cqp->en_datacenter_tcp = info->en_datacenter_tcp; | |
478 | cqp->enabled_vf_count = info->enabled_vf_count; | |
479 | cqp->hmc_profile = info->hmc_profile; | |
480 | info->dev->cqp = cqp; | |
481 | ||
482 | I40IW_RING_INIT(cqp->sq_ring, cqp->sq_size); | |
d6f7bbcc HO |
483 | cqp->dev->cqp_cmd_stats[OP_REQUESTED_COMMANDS] = 0; |
484 | cqp->dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS] = 0; | |
d2782739 | 485 | INIT_LIST_HEAD(&cqp->dev->cqp_cmd_head); /* for the cqp commands backlog. */ |
d6f7bbcc | 486 | |
56b2f523 CB |
487 | i40iw_wr32(cqp->dev->hw, I40E_PFPE_CQPTAIL, 0); |
488 | i40iw_wr32(cqp->dev->hw, I40E_PFPE_CQPDB, 0); | |
489 | ||
86dbcd0f FL |
490 | i40iw_debug(cqp->dev, I40IW_DEBUG_WQE, |
491 | "%s: sq_size[%04d] hw_sq_size[%04d] sq_base[%p] sq_pa[%llxh] cqp[%p] polarity[x%04X]\n", | |
492 | __func__, cqp->sq_size, cqp->hw_sq_size, | |
493 | cqp->sq_base, cqp->sq_pa, cqp, cqp->polarity); | |
494 | return 0; | |
495 | } | |
496 | ||
497 | /** | |
498 | * i40iw_sc_cqp_create - create cqp during bringup | |
499 | * @cqp: struct for cqp hw | |
86dbcd0f FL |
500 | * @maj_err: If error, major err number |
501 | * @min_err: If error, minor err number | |
502 | */ | |
503 | static enum i40iw_status_code i40iw_sc_cqp_create(struct i40iw_sc_cqp *cqp, | |
86dbcd0f FL |
504 | u16 *maj_err, |
505 | u16 *min_err) | |
506 | { | |
507 | u64 temp; | |
508 | u32 cnt = 0, p1, p2, val = 0, err_code; | |
509 | enum i40iw_status_code ret_code; | |
510 | ||
3f9fade5 SS |
511 | *maj_err = 0; |
512 | *min_err = 0; | |
513 | ||
86dbcd0f FL |
514 | ret_code = i40iw_allocate_dma_mem(cqp->dev->hw, |
515 | &cqp->sdbuf, | |
100d6de2 | 516 | I40IW_UPDATE_SD_BUF_SIZE * cqp->sq_size, |
86dbcd0f FL |
517 | I40IW_SD_BUF_ALIGNMENT); |
518 | ||
519 | if (ret_code) | |
520 | goto exit; | |
521 | ||
522 | temp = LS_64(cqp->hw_sq_size, I40IW_CQPHC_SQSIZE) | | |
523 | LS_64(cqp->struct_ver, I40IW_CQPHC_SVER); | |
524 | ||
86dbcd0f FL |
525 | set_64bit_val(cqp->host_ctx, 0, temp); |
526 | set_64bit_val(cqp->host_ctx, 8, cqp->sq_pa); | |
527 | temp = LS_64(cqp->enabled_vf_count, I40IW_CQPHC_ENABLED_VFS) | | |
528 | LS_64(cqp->hmc_profile, I40IW_CQPHC_HMC_PROFILE); | |
529 | set_64bit_val(cqp->host_ctx, 16, temp); | |
530 | set_64bit_val(cqp->host_ctx, 24, (uintptr_t)cqp); | |
531 | set_64bit_val(cqp->host_ctx, 32, 0); | |
532 | set_64bit_val(cqp->host_ctx, 40, 0); | |
533 | set_64bit_val(cqp->host_ctx, 48, 0); | |
534 | set_64bit_val(cqp->host_ctx, 56, 0); | |
535 | ||
536 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CQP_HOST_CTX", | |
537 | cqp->host_ctx, I40IW_CQP_CTX_SIZE * 8); | |
538 | ||
539 | p1 = RS_32_1(cqp->host_ctx_pa, 32); | |
540 | p2 = (u32)cqp->host_ctx_pa; | |
541 | ||
542 | if (cqp->dev->is_pf) { | |
543 | i40iw_wr32(cqp->dev->hw, I40E_PFPE_CCQPHIGH, p1); | |
544 | i40iw_wr32(cqp->dev->hw, I40E_PFPE_CCQPLOW, p2); | |
545 | } else { | |
546 | i40iw_wr32(cqp->dev->hw, I40E_VFPE_CCQPHIGH1, p1); | |
547 | i40iw_wr32(cqp->dev->hw, I40E_VFPE_CCQPLOW1, p2); | |
548 | } | |
549 | do { | |
550 | if (cnt++ > I40IW_DONE_COUNT) { | |
551 | i40iw_free_dma_mem(cqp->dev->hw, &cqp->sdbuf); | |
552 | ret_code = I40IW_ERR_TIMEOUT; | |
553 | /* | |
554 | * read PFPE_CQPERRORCODES register to get the minor | |
555 | * and major error code | |
556 | */ | |
557 | if (cqp->dev->is_pf) | |
558 | err_code = i40iw_rd32(cqp->dev->hw, I40E_PFPE_CQPERRCODES); | |
559 | else | |
560 | err_code = i40iw_rd32(cqp->dev->hw, I40E_VFPE_CQPERRCODES1); | |
561 | *min_err = RS_32(err_code, I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE); | |
562 | *maj_err = RS_32(err_code, I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE); | |
563 | goto exit; | |
564 | } | |
565 | udelay(I40IW_SLEEP_COUNT); | |
566 | if (cqp->dev->is_pf) | |
567 | val = i40iw_rd32(cqp->dev->hw, I40E_PFPE_CCQPSTATUS); | |
568 | else | |
569 | val = i40iw_rd32(cqp->dev->hw, I40E_VFPE_CCQPSTATUS1); | |
570 | } while (!val); | |
571 | ||
572 | exit: | |
573 | if (!ret_code) | |
574 | cqp->process_cqp_sds = i40iw_update_sds_noccq; | |
575 | return ret_code; | |
576 | } | |
577 | ||
578 | /** | |
579 | * i40iw_sc_cqp_post_sq - post of cqp's sq | |
580 | * @cqp: struct for cqp hw | |
581 | */ | |
582 | void i40iw_sc_cqp_post_sq(struct i40iw_sc_cqp *cqp) | |
583 | { | |
584 | if (cqp->dev->is_pf) | |
585 | i40iw_wr32(cqp->dev->hw, I40E_PFPE_CQPDB, I40IW_RING_GETCURRENT_HEAD(cqp->sq_ring)); | |
586 | else | |
587 | i40iw_wr32(cqp->dev->hw, I40E_VFPE_CQPDB1, I40IW_RING_GETCURRENT_HEAD(cqp->sq_ring)); | |
588 | ||
589 | i40iw_debug(cqp->dev, | |
590 | I40IW_DEBUG_WQE, | |
591 | "%s: HEAD_TAIL[%04d,%04d,%04d]\n", | |
592 | __func__, | |
593 | cqp->sq_ring.head, | |
594 | cqp->sq_ring.tail, | |
595 | cqp->sq_ring.size); | |
596 | } | |
597 | ||
598 | /** | |
100d6de2 CTT |
599 | * i40iw_sc_cqp_get_next_send_wqe_idx - get next WQE on CQP SQ and pass back the index |
600 | * @cqp: pointer to CQP structure | |
601 | * @scratch: private data for CQP WQE | |
602 | * @wqe_idx: WQE index for next WQE on CQP SQ | |
86dbcd0f | 603 | */ |
100d6de2 CTT |
604 | static u64 *i40iw_sc_cqp_get_next_send_wqe_idx(struct i40iw_sc_cqp *cqp, |
605 | u64 scratch, u32 *wqe_idx) | |
86dbcd0f FL |
606 | { |
607 | u64 *wqe = NULL; | |
86dbcd0f FL |
608 | enum i40iw_status_code ret_code; |
609 | ||
610 | if (I40IW_RING_FULL_ERR(cqp->sq_ring)) { | |
611 | i40iw_debug(cqp->dev, | |
612 | I40IW_DEBUG_WQE, | |
613 | "%s: ring is full head %x tail %x size %x\n", | |
614 | __func__, | |
615 | cqp->sq_ring.head, | |
616 | cqp->sq_ring.tail, | |
617 | cqp->sq_ring.size); | |
618 | return NULL; | |
619 | } | |
100d6de2 | 620 | I40IW_ATOMIC_RING_MOVE_HEAD(cqp->sq_ring, *wqe_idx, ret_code); |
d6f7bbcc | 621 | cqp->dev->cqp_cmd_stats[OP_REQUESTED_COMMANDS]++; |
86dbcd0f FL |
622 | if (ret_code) |
623 | return NULL; | |
100d6de2 | 624 | if (!*wqe_idx) |
86dbcd0f FL |
625 | cqp->polarity = !cqp->polarity; |
626 | ||
100d6de2 CTT |
627 | wqe = cqp->sq_base[*wqe_idx].elem; |
628 | cqp->scratch_array[*wqe_idx] = scratch; | |
86dbcd0f FL |
629 | I40IW_CQP_INIT_WQE(wqe); |
630 | ||
631 | return wqe; | |
632 | } | |
633 | ||
100d6de2 CTT |
634 | /** |
635 | * i40iw_sc_cqp_get_next_send_wqe - get next wqe on cqp sq | |
636 | * @cqp: struct for cqp hw | |
637 | * @scratch: private data for CQP WQE | |
638 | */ | |
639 | u64 *i40iw_sc_cqp_get_next_send_wqe(struct i40iw_sc_cqp *cqp, u64 scratch) | |
640 | { | |
641 | u32 wqe_idx; | |
642 | ||
643 | return i40iw_sc_cqp_get_next_send_wqe_idx(cqp, scratch, &wqe_idx); | |
644 | } | |
645 | ||
86dbcd0f FL |
646 | /** |
647 | * i40iw_sc_cqp_destroy - destroy cqp during close | |
648 | * @cqp: struct for cqp hw | |
649 | */ | |
650 | static enum i40iw_status_code i40iw_sc_cqp_destroy(struct i40iw_sc_cqp *cqp) | |
651 | { | |
652 | u32 cnt = 0, val = 1; | |
653 | enum i40iw_status_code ret_code = 0; | |
654 | u32 cqpstat_addr; | |
655 | ||
656 | if (cqp->dev->is_pf) { | |
657 | i40iw_wr32(cqp->dev->hw, I40E_PFPE_CCQPHIGH, 0); | |
658 | i40iw_wr32(cqp->dev->hw, I40E_PFPE_CCQPLOW, 0); | |
659 | cqpstat_addr = I40E_PFPE_CCQPSTATUS; | |
660 | } else { | |
661 | i40iw_wr32(cqp->dev->hw, I40E_VFPE_CCQPHIGH1, 0); | |
662 | i40iw_wr32(cqp->dev->hw, I40E_VFPE_CCQPLOW1, 0); | |
663 | cqpstat_addr = I40E_VFPE_CCQPSTATUS1; | |
664 | } | |
665 | do { | |
666 | if (cnt++ > I40IW_DONE_COUNT) { | |
667 | ret_code = I40IW_ERR_TIMEOUT; | |
668 | break; | |
669 | } | |
670 | udelay(I40IW_SLEEP_COUNT); | |
671 | val = i40iw_rd32(cqp->dev->hw, cqpstat_addr); | |
672 | } while (val); | |
673 | ||
674 | i40iw_free_dma_mem(cqp->dev->hw, &cqp->sdbuf); | |
675 | return ret_code; | |
676 | } | |
677 | ||
678 | /** | |
679 | * i40iw_sc_ccq_arm - enable intr for control cq | |
680 | * @ccq: ccq sc struct | |
681 | */ | |
682 | static void i40iw_sc_ccq_arm(struct i40iw_sc_cq *ccq) | |
683 | { | |
684 | u64 temp_val; | |
685 | u16 sw_cq_sel; | |
686 | u8 arm_next_se; | |
687 | u8 arm_seq_num; | |
688 | ||
689 | /* write to cq doorbell shadow area */ | |
690 | /* arm next se should always be zero */ | |
691 | get_64bit_val(ccq->cq_uk.shadow_area, 32, &temp_val); | |
692 | ||
693 | sw_cq_sel = (u16)RS_64(temp_val, I40IW_CQ_DBSA_SW_CQ_SELECT); | |
694 | arm_next_se = (u8)RS_64(temp_val, I40IW_CQ_DBSA_ARM_NEXT_SE); | |
695 | ||
696 | arm_seq_num = (u8)RS_64(temp_val, I40IW_CQ_DBSA_ARM_SEQ_NUM); | |
697 | arm_seq_num++; | |
698 | ||
699 | temp_val = LS_64(arm_seq_num, I40IW_CQ_DBSA_ARM_SEQ_NUM) | | |
700 | LS_64(sw_cq_sel, I40IW_CQ_DBSA_SW_CQ_SELECT) | | |
701 | LS_64(arm_next_se, I40IW_CQ_DBSA_ARM_NEXT_SE) | | |
702 | LS_64(1, I40IW_CQ_DBSA_ARM_NEXT); | |
703 | ||
704 | set_64bit_val(ccq->cq_uk.shadow_area, 32, temp_val); | |
705 | ||
706 | wmb(); /* make sure shadow area is updated before arming */ | |
707 | ||
708 | if (ccq->dev->is_pf) | |
709 | i40iw_wr32(ccq->dev->hw, I40E_PFPE_CQARM, ccq->cq_uk.cq_id); | |
710 | else | |
711 | i40iw_wr32(ccq->dev->hw, I40E_VFPE_CQARM1, ccq->cq_uk.cq_id); | |
712 | } | |
713 | ||
714 | /** | |
715 | * i40iw_sc_ccq_get_cqe_info - get ccq's cq entry | |
716 | * @ccq: ccq sc struct | |
717 | * @info: completion q entry to return | |
718 | */ | |
719 | static enum i40iw_status_code i40iw_sc_ccq_get_cqe_info( | |
720 | struct i40iw_sc_cq *ccq, | |
721 | struct i40iw_ccq_cqe_info *info) | |
722 | { | |
723 | u64 qp_ctx, temp, temp1; | |
724 | u64 *cqe; | |
725 | struct i40iw_sc_cqp *cqp; | |
726 | u32 wqe_idx; | |
727 | u8 polarity; | |
728 | enum i40iw_status_code ret_code = 0; | |
729 | ||
730 | if (ccq->cq_uk.avoid_mem_cflct) | |
731 | cqe = (u64 *)I40IW_GET_CURRENT_EXTENDED_CQ_ELEMENT(&ccq->cq_uk); | |
732 | else | |
733 | cqe = (u64 *)I40IW_GET_CURRENT_CQ_ELEMENT(&ccq->cq_uk); | |
734 | ||
735 | get_64bit_val(cqe, 24, &temp); | |
736 | polarity = (u8)RS_64(temp, I40IW_CQ_VALID); | |
737 | if (polarity != ccq->cq_uk.polarity) | |
738 | return I40IW_ERR_QUEUE_EMPTY; | |
739 | ||
740 | get_64bit_val(cqe, 8, &qp_ctx); | |
741 | cqp = (struct i40iw_sc_cqp *)(unsigned long)qp_ctx; | |
742 | info->error = (bool)RS_64(temp, I40IW_CQ_ERROR); | |
743 | info->min_err_code = (u16)RS_64(temp, I40IW_CQ_MINERR); | |
744 | if (info->error) { | |
745 | info->maj_err_code = (u16)RS_64(temp, I40IW_CQ_MAJERR); | |
746 | info->min_err_code = (u16)RS_64(temp, I40IW_CQ_MINERR); | |
747 | } | |
748 | wqe_idx = (u32)RS_64(temp, I40IW_CQ_WQEIDX); | |
749 | info->scratch = cqp->scratch_array[wqe_idx]; | |
750 | ||
751 | get_64bit_val(cqe, 16, &temp1); | |
752 | info->op_ret_val = (u32)RS_64(temp1, I40IW_CCQ_OPRETVAL); | |
753 | get_64bit_val(cqp->sq_base[wqe_idx].elem, 24, &temp1); | |
754 | info->op_code = (u8)RS_64(temp1, I40IW_CQPSQ_OPCODE); | |
755 | info->cqp = cqp; | |
756 | ||
757 | /* move the head for cq */ | |
758 | I40IW_RING_MOVE_HEAD(ccq->cq_uk.cq_ring, ret_code); | |
759 | if (I40IW_RING_GETCURRENT_HEAD(ccq->cq_uk.cq_ring) == 0) | |
760 | ccq->cq_uk.polarity ^= 1; | |
761 | ||
762 | /* update cq tail in cq shadow memory also */ | |
763 | I40IW_RING_MOVE_TAIL(ccq->cq_uk.cq_ring); | |
764 | set_64bit_val(ccq->cq_uk.shadow_area, | |
765 | 0, | |
766 | I40IW_RING_GETCURRENT_HEAD(ccq->cq_uk.cq_ring)); | |
767 | wmb(); /* write shadow area before tail */ | |
768 | I40IW_RING_MOVE_TAIL(cqp->sq_ring); | |
d6f7bbcc HO |
769 | ccq->dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS]++; |
770 | ||
86dbcd0f FL |
771 | return ret_code; |
772 | } | |
773 | ||
774 | /** | |
775 | * i40iw_sc_poll_for_cqp_op_done - Waits for last write to complete in CQP SQ | |
776 | * @cqp: struct for cqp hw | |
777 | * @op_code: cqp opcode for completion | |
778 | * @info: completion q entry to return | |
779 | */ | |
780 | static enum i40iw_status_code i40iw_sc_poll_for_cqp_op_done( | |
781 | struct i40iw_sc_cqp *cqp, | |
782 | u8 op_code, | |
783 | struct i40iw_ccq_cqe_info *compl_info) | |
784 | { | |
785 | struct i40iw_ccq_cqe_info info; | |
786 | struct i40iw_sc_cq *ccq; | |
787 | enum i40iw_status_code ret_code = 0; | |
788 | u32 cnt = 0; | |
789 | ||
790 | memset(&info, 0, sizeof(info)); | |
791 | ccq = cqp->dev->ccq; | |
792 | while (1) { | |
793 | if (cnt++ > I40IW_DONE_COUNT) | |
794 | return I40IW_ERR_TIMEOUT; | |
795 | ||
796 | if (i40iw_sc_ccq_get_cqe_info(ccq, &info)) { | |
797 | udelay(I40IW_SLEEP_COUNT); | |
798 | continue; | |
799 | } | |
800 | ||
801 | if (info.error) { | |
802 | ret_code = I40IW_ERR_CQP_COMPL_ERROR; | |
803 | break; | |
804 | } | |
805 | /* check if opcode is cq create */ | |
806 | if (op_code != info.op_code) { | |
807 | i40iw_debug(cqp->dev, I40IW_DEBUG_WQE, | |
808 | "%s: opcode mismatch for my op code 0x%x, returned opcode %x\n", | |
809 | __func__, op_code, info.op_code); | |
810 | } | |
811 | /* success, exit out of the loop */ | |
812 | if (op_code == info.op_code) | |
813 | break; | |
814 | } | |
815 | ||
816 | if (compl_info) | |
817 | memcpy(compl_info, &info, sizeof(*compl_info)); | |
818 | ||
819 | return ret_code; | |
820 | } | |
821 | ||
822 | /** | |
823 | * i40iw_sc_manage_push_page - Handle push page | |
824 | * @cqp: struct for cqp hw | |
825 | * @info: push page info | |
826 | * @scratch: u64 saved to be used during cqp completion | |
827 | * @post_sq: flag for cqp db to ring | |
828 | */ | |
829 | static enum i40iw_status_code i40iw_sc_manage_push_page( | |
830 | struct i40iw_sc_cqp *cqp, | |
831 | struct i40iw_cqp_manage_push_page_info *info, | |
832 | u64 scratch, | |
833 | bool post_sq) | |
834 | { | |
835 | u64 *wqe; | |
836 | u64 header; | |
837 | ||
838 | if (info->push_idx >= I40IW_MAX_PUSH_PAGE_COUNT) | |
839 | return I40IW_ERR_INVALID_PUSH_PAGE_INDEX; | |
840 | ||
841 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
842 | if (!wqe) | |
843 | return I40IW_ERR_RING_FULL; | |
844 | ||
845 | set_64bit_val(wqe, 16, info->qs_handle); | |
846 | ||
847 | header = LS_64(info->push_idx, I40IW_CQPSQ_MPP_PPIDX) | | |
848 | LS_64(I40IW_CQP_OP_MANAGE_PUSH_PAGES, I40IW_CQPSQ_OPCODE) | | |
849 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID) | | |
850 | LS_64(info->free_page, I40IW_CQPSQ_MPP_FREE_PAGE); | |
851 | ||
852 | i40iw_insert_wqe_hdr(wqe, header); | |
853 | ||
854 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "MANAGE_PUSH_PAGES WQE", | |
855 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
856 | ||
857 | if (post_sq) | |
858 | i40iw_sc_cqp_post_sq(cqp); | |
859 | return 0; | |
860 | } | |
861 | ||
862 | /** | |
863 | * i40iw_sc_manage_hmc_pm_func_table - manage of function table | |
864 | * @cqp: struct for cqp hw | |
865 | * @scratch: u64 saved to be used during cqp completion | |
866 | * @vf_index: vf index for cqp | |
867 | * @free_pm_fcn: function number | |
868 | * @post_sq: flag for cqp db to ring | |
869 | */ | |
870 | static enum i40iw_status_code i40iw_sc_manage_hmc_pm_func_table( | |
871 | struct i40iw_sc_cqp *cqp, | |
872 | u64 scratch, | |
873 | u8 vf_index, | |
874 | bool free_pm_fcn, | |
875 | bool post_sq) | |
876 | { | |
877 | u64 *wqe; | |
878 | u64 header; | |
879 | ||
880 | if (vf_index >= I40IW_MAX_VF_PER_PF) | |
881 | return I40IW_ERR_INVALID_VF_ID; | |
882 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
883 | if (!wqe) | |
884 | return I40IW_ERR_RING_FULL; | |
885 | ||
886 | header = LS_64(vf_index, I40IW_CQPSQ_MHMC_VFIDX) | | |
887 | LS_64(I40IW_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE, I40IW_CQPSQ_OPCODE) | | |
888 | LS_64(free_pm_fcn, I40IW_CQPSQ_MHMC_FREEPMFN) | | |
889 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
890 | ||
891 | i40iw_insert_wqe_hdr(wqe, header); | |
892 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "MANAGE_HMC_PM_FUNC_TABLE WQE", | |
893 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
894 | if (post_sq) | |
895 | i40iw_sc_cqp_post_sq(cqp); | |
896 | return 0; | |
897 | } | |
898 | ||
899 | /** | |
900 | * i40iw_sc_set_hmc_resource_profile - cqp wqe for hmc profile | |
901 | * @cqp: struct for cqp hw | |
902 | * @scratch: u64 saved to be used during cqp completion | |
903 | * @hmc_profile_type: type of profile to set | |
904 | * @vf_num: vf number for profile | |
905 | * @post_sq: flag for cqp db to ring | |
906 | * @poll_registers: flag to poll register for cqp completion | |
907 | */ | |
908 | static enum i40iw_status_code i40iw_sc_set_hmc_resource_profile( | |
909 | struct i40iw_sc_cqp *cqp, | |
910 | u64 scratch, | |
911 | u8 hmc_profile_type, | |
912 | u8 vf_num, bool post_sq, | |
913 | bool poll_registers) | |
914 | { | |
915 | u64 *wqe; | |
916 | u64 header; | |
917 | u32 val, tail, error; | |
918 | enum i40iw_status_code ret_code = 0; | |
919 | ||
920 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
921 | if (!wqe) | |
922 | return I40IW_ERR_RING_FULL; | |
923 | ||
924 | set_64bit_val(wqe, 16, | |
925 | (LS_64(hmc_profile_type, I40IW_CQPSQ_SHMCRP_HMC_PROFILE) | | |
926 | LS_64(vf_num, I40IW_CQPSQ_SHMCRP_VFNUM))); | |
927 | ||
928 | header = LS_64(I40IW_CQP_OP_SET_HMC_RESOURCE_PROFILE, I40IW_CQPSQ_OPCODE) | | |
929 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
930 | ||
931 | i40iw_insert_wqe_hdr(wqe, header); | |
932 | ||
933 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "MANAGE_HMC_PM_FUNC_TABLE WQE", | |
934 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
935 | ||
936 | i40iw_get_cqp_reg_info(cqp, &val, &tail, &error); | |
937 | if (error) | |
938 | return I40IW_ERR_CQP_COMPL_ERROR; | |
939 | ||
940 | if (post_sq) { | |
941 | i40iw_sc_cqp_post_sq(cqp); | |
942 | if (poll_registers) | |
943 | ret_code = i40iw_cqp_poll_registers(cqp, tail, 1000000); | |
944 | else | |
945 | ret_code = i40iw_sc_poll_for_cqp_op_done(cqp, | |
946 | I40IW_CQP_OP_SHMC_PAGES_ALLOCATED, | |
947 | NULL); | |
948 | } | |
949 | ||
950 | return ret_code; | |
951 | } | |
952 | ||
953 | /** | |
954 | * i40iw_sc_manage_hmc_pm_func_table_done - wait for cqp wqe completion for function table | |
955 | * @cqp: struct for cqp hw | |
956 | */ | |
957 | static enum i40iw_status_code i40iw_sc_manage_hmc_pm_func_table_done(struct i40iw_sc_cqp *cqp) | |
958 | { | |
959 | return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE, NULL); | |
960 | } | |
961 | ||
962 | /** | |
963 | * i40iw_sc_commit_fpm_values_done - wait for cqp eqe completion for fpm commit | |
964 | * @cqp: struct for cqp hw | |
965 | */ | |
966 | static enum i40iw_status_code i40iw_sc_commit_fpm_values_done(struct i40iw_sc_cqp *cqp) | |
967 | { | |
968 | return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_COMMIT_FPM_VALUES, NULL); | |
969 | } | |
970 | ||
971 | /** | |
972 | * i40iw_sc_commit_fpm_values - cqp wqe for commit fpm values | |
973 | * @cqp: struct for cqp hw | |
974 | * @scratch: u64 saved to be used during cqp completion | |
975 | * @hmc_fn_id: hmc function id | |
976 | * @commit_fpm_mem; Memory for fpm values | |
977 | * @post_sq: flag for cqp db to ring | |
978 | * @wait_type: poll ccq or cqp registers for cqp completion | |
979 | */ | |
980 | static enum i40iw_status_code i40iw_sc_commit_fpm_values( | |
981 | struct i40iw_sc_cqp *cqp, | |
982 | u64 scratch, | |
983 | u8 hmc_fn_id, | |
984 | struct i40iw_dma_mem *commit_fpm_mem, | |
985 | bool post_sq, | |
986 | u8 wait_type) | |
987 | { | |
988 | u64 *wqe; | |
989 | u64 header; | |
990 | u32 tail, val, error; | |
991 | enum i40iw_status_code ret_code = 0; | |
992 | ||
993 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
994 | if (!wqe) | |
995 | return I40IW_ERR_RING_FULL; | |
996 | ||
997 | set_64bit_val(wqe, 16, hmc_fn_id); | |
998 | set_64bit_val(wqe, 32, commit_fpm_mem->pa); | |
999 | ||
1000 | header = LS_64(I40IW_CQP_OP_COMMIT_FPM_VALUES, I40IW_CQPSQ_OPCODE) | | |
1001 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
1002 | ||
1003 | i40iw_insert_wqe_hdr(wqe, header); | |
1004 | ||
1005 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "COMMIT_FPM_VALUES WQE", | |
1006 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
1007 | ||
1008 | i40iw_get_cqp_reg_info(cqp, &val, &tail, &error); | |
1009 | if (error) | |
1010 | return I40IW_ERR_CQP_COMPL_ERROR; | |
1011 | ||
1012 | if (post_sq) { | |
1013 | i40iw_sc_cqp_post_sq(cqp); | |
1014 | ||
1015 | if (wait_type == I40IW_CQP_WAIT_POLL_REGS) | |
1016 | ret_code = i40iw_cqp_poll_registers(cqp, tail, I40IW_DONE_COUNT); | |
1017 | else if (wait_type == I40IW_CQP_WAIT_POLL_CQ) | |
1018 | ret_code = i40iw_sc_commit_fpm_values_done(cqp); | |
1019 | } | |
1020 | ||
1021 | return ret_code; | |
1022 | } | |
1023 | ||
1024 | /** | |
1025 | * i40iw_sc_query_fpm_values_done - poll for cqp wqe completion for query fpm | |
1026 | * @cqp: struct for cqp hw | |
1027 | */ | |
1028 | static enum i40iw_status_code i40iw_sc_query_fpm_values_done(struct i40iw_sc_cqp *cqp) | |
1029 | { | |
1030 | return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_QUERY_FPM_VALUES, NULL); | |
1031 | } | |
1032 | ||
1033 | /** | |
1034 | * i40iw_sc_query_fpm_values - cqp wqe query fpm values | |
1035 | * @cqp: struct for cqp hw | |
1036 | * @scratch: u64 saved to be used during cqp completion | |
1037 | * @hmc_fn_id: hmc function id | |
1038 | * @query_fpm_mem: memory for return fpm values | |
1039 | * @post_sq: flag for cqp db to ring | |
1040 | * @wait_type: poll ccq or cqp registers for cqp completion | |
1041 | */ | |
1042 | static enum i40iw_status_code i40iw_sc_query_fpm_values( | |
1043 | struct i40iw_sc_cqp *cqp, | |
1044 | u64 scratch, | |
1045 | u8 hmc_fn_id, | |
1046 | struct i40iw_dma_mem *query_fpm_mem, | |
1047 | bool post_sq, | |
1048 | u8 wait_type) | |
1049 | { | |
1050 | u64 *wqe; | |
1051 | u64 header; | |
1052 | u32 tail, val, error; | |
1053 | enum i40iw_status_code ret_code = 0; | |
1054 | ||
1055 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
1056 | if (!wqe) | |
1057 | return I40IW_ERR_RING_FULL; | |
1058 | ||
1059 | set_64bit_val(wqe, 16, hmc_fn_id); | |
1060 | set_64bit_val(wqe, 32, query_fpm_mem->pa); | |
1061 | ||
1062 | header = LS_64(I40IW_CQP_OP_QUERY_FPM_VALUES, I40IW_CQPSQ_OPCODE) | | |
1063 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
1064 | ||
1065 | i40iw_insert_wqe_hdr(wqe, header); | |
1066 | ||
1067 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QUERY_FPM WQE", | |
1068 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
1069 | ||
1070 | /* read the tail from CQP_TAIL register */ | |
1071 | i40iw_get_cqp_reg_info(cqp, &val, &tail, &error); | |
1072 | ||
1073 | if (error) | |
1074 | return I40IW_ERR_CQP_COMPL_ERROR; | |
1075 | ||
1076 | if (post_sq) { | |
1077 | i40iw_sc_cqp_post_sq(cqp); | |
1078 | if (wait_type == I40IW_CQP_WAIT_POLL_REGS) | |
1079 | ret_code = i40iw_cqp_poll_registers(cqp, tail, I40IW_DONE_COUNT); | |
1080 | else if (wait_type == I40IW_CQP_WAIT_POLL_CQ) | |
1081 | ret_code = i40iw_sc_query_fpm_values_done(cqp); | |
1082 | } | |
1083 | ||
1084 | return ret_code; | |
1085 | } | |
1086 | ||
1087 | /** | |
1088 | * i40iw_sc_add_arp_cache_entry - cqp wqe add arp cache entry | |
1089 | * @cqp: struct for cqp hw | |
1090 | * @info: arp entry information | |
1091 | * @scratch: u64 saved to be used during cqp completion | |
1092 | * @post_sq: flag for cqp db to ring | |
1093 | */ | |
1094 | static enum i40iw_status_code i40iw_sc_add_arp_cache_entry( | |
1095 | struct i40iw_sc_cqp *cqp, | |
1096 | struct i40iw_add_arp_cache_entry_info *info, | |
1097 | u64 scratch, | |
1098 | bool post_sq) | |
1099 | { | |
1100 | u64 *wqe; | |
1101 | u64 temp, header; | |
1102 | ||
1103 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
1104 | if (!wqe) | |
1105 | return I40IW_ERR_RING_FULL; | |
1106 | set_64bit_val(wqe, 8, info->reach_max); | |
1107 | ||
1108 | temp = info->mac_addr[5] | | |
1109 | LS_64_1(info->mac_addr[4], 8) | | |
1110 | LS_64_1(info->mac_addr[3], 16) | | |
1111 | LS_64_1(info->mac_addr[2], 24) | | |
1112 | LS_64_1(info->mac_addr[1], 32) | | |
1113 | LS_64_1(info->mac_addr[0], 40); | |
1114 | ||
1115 | set_64bit_val(wqe, 16, temp); | |
1116 | ||
1117 | header = info->arp_index | | |
1118 | LS_64(I40IW_CQP_OP_MANAGE_ARP, I40IW_CQPSQ_OPCODE) | | |
1119 | LS_64((info->permanent ? 1 : 0), I40IW_CQPSQ_MAT_PERMANENT) | | |
1120 | LS_64(1, I40IW_CQPSQ_MAT_ENTRYVALID) | | |
1121 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
1122 | ||
1123 | i40iw_insert_wqe_hdr(wqe, header); | |
1124 | ||
1125 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "ARP_CACHE_ENTRY WQE", | |
1126 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
1127 | ||
1128 | if (post_sq) | |
1129 | i40iw_sc_cqp_post_sq(cqp); | |
1130 | return 0; | |
1131 | } | |
1132 | ||
1133 | /** | |
1134 | * i40iw_sc_del_arp_cache_entry - dele arp cache entry | |
1135 | * @cqp: struct for cqp hw | |
1136 | * @scratch: u64 saved to be used during cqp completion | |
1137 | * @arp_index: arp index to delete arp entry | |
1138 | * @post_sq: flag for cqp db to ring | |
1139 | */ | |
1140 | static enum i40iw_status_code i40iw_sc_del_arp_cache_entry( | |
1141 | struct i40iw_sc_cqp *cqp, | |
1142 | u64 scratch, | |
1143 | u16 arp_index, | |
1144 | bool post_sq) | |
1145 | { | |
1146 | u64 *wqe; | |
1147 | u64 header; | |
1148 | ||
1149 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
1150 | if (!wqe) | |
1151 | return I40IW_ERR_RING_FULL; | |
1152 | ||
1153 | header = arp_index | | |
1154 | LS_64(I40IW_CQP_OP_MANAGE_ARP, I40IW_CQPSQ_OPCODE) | | |
1155 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
1156 | i40iw_insert_wqe_hdr(wqe, header); | |
1157 | ||
1158 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "ARP_CACHE_DEL_ENTRY WQE", | |
1159 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
1160 | ||
1161 | if (post_sq) | |
1162 | i40iw_sc_cqp_post_sq(cqp); | |
1163 | return 0; | |
1164 | } | |
1165 | ||
1166 | /** | |
1167 | * i40iw_sc_query_arp_cache_entry - cqp wqe to query arp and arp index | |
1168 | * @cqp: struct for cqp hw | |
1169 | * @scratch: u64 saved to be used during cqp completion | |
1170 | * @arp_index: arp index to delete arp entry | |
1171 | * @post_sq: flag for cqp db to ring | |
1172 | */ | |
1173 | static enum i40iw_status_code i40iw_sc_query_arp_cache_entry( | |
1174 | struct i40iw_sc_cqp *cqp, | |
1175 | u64 scratch, | |
1176 | u16 arp_index, | |
1177 | bool post_sq) | |
1178 | { | |
1179 | u64 *wqe; | |
1180 | u64 header; | |
1181 | ||
1182 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
1183 | if (!wqe) | |
1184 | return I40IW_ERR_RING_FULL; | |
1185 | ||
1186 | header = arp_index | | |
1187 | LS_64(I40IW_CQP_OP_MANAGE_ARP, I40IW_CQPSQ_OPCODE) | | |
1188 | LS_64(1, I40IW_CQPSQ_MAT_QUERY) | | |
1189 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
1190 | ||
1191 | i40iw_insert_wqe_hdr(wqe, header); | |
1192 | ||
1193 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QUERY_ARP_CACHE_ENTRY WQE", | |
1194 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
1195 | ||
1196 | if (post_sq) | |
1197 | i40iw_sc_cqp_post_sq(cqp); | |
1198 | return 0; | |
1199 | } | |
1200 | ||
1201 | /** | |
1202 | * i40iw_sc_manage_apbvt_entry - for adding and deleting apbvt entries | |
1203 | * @cqp: struct for cqp hw | |
1204 | * @info: info for apbvt entry to add or delete | |
1205 | * @scratch: u64 saved to be used during cqp completion | |
1206 | * @post_sq: flag for cqp db to ring | |
1207 | */ | |
1208 | static enum i40iw_status_code i40iw_sc_manage_apbvt_entry( | |
1209 | struct i40iw_sc_cqp *cqp, | |
1210 | struct i40iw_apbvt_info *info, | |
1211 | u64 scratch, | |
1212 | bool post_sq) | |
1213 | { | |
1214 | u64 *wqe; | |
1215 | u64 header; | |
1216 | ||
1217 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
1218 | if (!wqe) | |
1219 | return I40IW_ERR_RING_FULL; | |
1220 | ||
1221 | set_64bit_val(wqe, 16, info->port); | |
1222 | ||
1223 | header = LS_64(I40IW_CQP_OP_MANAGE_APBVT, I40IW_CQPSQ_OPCODE) | | |
1224 | LS_64(info->add, I40IW_CQPSQ_MAPT_ADDPORT) | | |
1225 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
1226 | ||
1227 | i40iw_insert_wqe_hdr(wqe, header); | |
1228 | ||
1229 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "MANAGE_APBVT WQE", | |
1230 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
1231 | ||
1232 | if (post_sq) | |
1233 | i40iw_sc_cqp_post_sq(cqp); | |
1234 | return 0; | |
1235 | } | |
1236 | ||
1237 | /** | |
1238 | * i40iw_sc_manage_qhash_table_entry - manage quad hash entries | |
1239 | * @cqp: struct for cqp hw | |
1240 | * @info: info for quad hash to manage | |
1241 | * @scratch: u64 saved to be used during cqp completion | |
1242 | * @post_sq: flag for cqp db to ring | |
1243 | * | |
1244 | * This is called before connection establishment is started. For passive connections, when | |
1245 | * listener is created, it will call with entry type of I40IW_QHASH_TYPE_TCP_SYN with local | |
1246 | * ip address and tcp port. When SYN is received (passive connections) or | |
1247 | * sent (active connections), this routine is called with entry type of | |
1248 | * I40IW_QHASH_TYPE_TCP_ESTABLISHED and quad is passed in info. | |
1249 | * | |
1250 | * When iwarp connection is done and its state moves to RTS, the quad hash entry in | |
1251 | * the hardware will point to iwarp's qp number and requires no calls from the driver. | |
1252 | */ | |
1253 | static enum i40iw_status_code i40iw_sc_manage_qhash_table_entry( | |
1254 | struct i40iw_sc_cqp *cqp, | |
1255 | struct i40iw_qhash_table_info *info, | |
1256 | u64 scratch, | |
1257 | bool post_sq) | |
1258 | { | |
1259 | u64 *wqe; | |
1260 | u64 qw1 = 0; | |
1261 | u64 qw2 = 0; | |
1262 | u64 temp; | |
d6f7bbcc | 1263 | struct i40iw_sc_vsi *vsi = info->vsi; |
86dbcd0f FL |
1264 | |
1265 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
1266 | if (!wqe) | |
1267 | return I40IW_ERR_RING_FULL; | |
1268 | ||
1269 | temp = info->mac_addr[5] | | |
1270 | LS_64_1(info->mac_addr[4], 8) | | |
1271 | LS_64_1(info->mac_addr[3], 16) | | |
1272 | LS_64_1(info->mac_addr[2], 24) | | |
1273 | LS_64_1(info->mac_addr[1], 32) | | |
1274 | LS_64_1(info->mac_addr[0], 40); | |
1275 | ||
1276 | set_64bit_val(wqe, 0, temp); | |
1277 | ||
1278 | qw1 = LS_64(info->qp_num, I40IW_CQPSQ_QHASH_QPN) | | |
1279 | LS_64(info->dest_port, I40IW_CQPSQ_QHASH_DEST_PORT); | |
1280 | if (info->ipv4_valid) { | |
1281 | set_64bit_val(wqe, | |
1282 | 48, | |
1283 | LS_64(info->dest_ip[0], I40IW_CQPSQ_QHASH_ADDR3)); | |
1284 | } else { | |
1285 | set_64bit_val(wqe, | |
1286 | 56, | |
1287 | LS_64(info->dest_ip[0], I40IW_CQPSQ_QHASH_ADDR0) | | |
1288 | LS_64(info->dest_ip[1], I40IW_CQPSQ_QHASH_ADDR1)); | |
1289 | ||
1290 | set_64bit_val(wqe, | |
1291 | 48, | |
1292 | LS_64(info->dest_ip[2], I40IW_CQPSQ_QHASH_ADDR2) | | |
1293 | LS_64(info->dest_ip[3], I40IW_CQPSQ_QHASH_ADDR3)); | |
1294 | } | |
d6f7bbcc | 1295 | qw2 = LS_64(vsi->qos[info->user_pri].qs_handle, I40IW_CQPSQ_QHASH_QS_HANDLE); |
86dbcd0f FL |
1296 | if (info->vlan_valid) |
1297 | qw2 |= LS_64(info->vlan_id, I40IW_CQPSQ_QHASH_VLANID); | |
1298 | set_64bit_val(wqe, 16, qw2); | |
1299 | if (info->entry_type == I40IW_QHASH_TYPE_TCP_ESTABLISHED) { | |
1300 | qw1 |= LS_64(info->src_port, I40IW_CQPSQ_QHASH_SRC_PORT); | |
1301 | if (!info->ipv4_valid) { | |
1302 | set_64bit_val(wqe, | |
1303 | 40, | |
1304 | LS_64(info->src_ip[0], I40IW_CQPSQ_QHASH_ADDR0) | | |
1305 | LS_64(info->src_ip[1], I40IW_CQPSQ_QHASH_ADDR1)); | |
1306 | set_64bit_val(wqe, | |
1307 | 32, | |
1308 | LS_64(info->src_ip[2], I40IW_CQPSQ_QHASH_ADDR2) | | |
1309 | LS_64(info->src_ip[3], I40IW_CQPSQ_QHASH_ADDR3)); | |
1310 | } else { | |
1311 | set_64bit_val(wqe, | |
1312 | 32, | |
1313 | LS_64(info->src_ip[0], I40IW_CQPSQ_QHASH_ADDR3)); | |
1314 | } | |
1315 | } | |
1316 | ||
1317 | set_64bit_val(wqe, 8, qw1); | |
1318 | temp = LS_64(cqp->polarity, I40IW_CQPSQ_QHASH_WQEVALID) | | |
1319 | LS_64(I40IW_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY, I40IW_CQPSQ_QHASH_OPCODE) | | |
1320 | LS_64(info->manage, I40IW_CQPSQ_QHASH_MANAGE) | | |
1321 | LS_64(info->ipv4_valid, I40IW_CQPSQ_QHASH_IPV4VALID) | | |
1322 | LS_64(info->vlan_valid, I40IW_CQPSQ_QHASH_VLANVALID) | | |
1323 | LS_64(info->entry_type, I40IW_CQPSQ_QHASH_ENTRYTYPE); | |
1324 | ||
1325 | i40iw_insert_wqe_hdr(wqe, temp); | |
1326 | ||
1327 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "MANAGE_QHASH WQE", | |
1328 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
1329 | ||
1330 | if (post_sq) | |
1331 | i40iw_sc_cqp_post_sq(cqp); | |
1332 | return 0; | |
1333 | } | |
1334 | ||
1335 | /** | |
1336 | * i40iw_sc_alloc_local_mac_ipaddr_entry - cqp wqe for loc mac entry | |
1337 | * @cqp: struct for cqp hw | |
1338 | * @scratch: u64 saved to be used during cqp completion | |
1339 | * @post_sq: flag for cqp db to ring | |
1340 | */ | |
1341 | static enum i40iw_status_code i40iw_sc_alloc_local_mac_ipaddr_entry( | |
1342 | struct i40iw_sc_cqp *cqp, | |
1343 | u64 scratch, | |
1344 | bool post_sq) | |
1345 | { | |
1346 | u64 *wqe; | |
1347 | u64 header; | |
1348 | ||
1349 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
1350 | if (!wqe) | |
1351 | return I40IW_ERR_RING_FULL; | |
1352 | header = LS_64(I40IW_CQP_OP_ALLOCATE_LOC_MAC_IP_TABLE_ENTRY, I40IW_CQPSQ_OPCODE) | | |
1353 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
1354 | ||
1355 | i40iw_insert_wqe_hdr(wqe, header); | |
1356 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "ALLOCATE_LOCAL_MAC_IPADDR WQE", | |
1357 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
1358 | if (post_sq) | |
1359 | i40iw_sc_cqp_post_sq(cqp); | |
1360 | return 0; | |
1361 | } | |
1362 | ||
1363 | /** | |
1364 | * i40iw_sc_add_local_mac_ipaddr_entry - add mac enry | |
1365 | * @cqp: struct for cqp hw | |
1366 | * @info:mac addr info | |
1367 | * @scratch: u64 saved to be used during cqp completion | |
1368 | * @post_sq: flag for cqp db to ring | |
1369 | */ | |
1370 | static enum i40iw_status_code i40iw_sc_add_local_mac_ipaddr_entry( | |
1371 | struct i40iw_sc_cqp *cqp, | |
1372 | struct i40iw_local_mac_ipaddr_entry_info *info, | |
1373 | u64 scratch, | |
1374 | bool post_sq) | |
1375 | { | |
1376 | u64 *wqe; | |
1377 | u64 temp, header; | |
1378 | ||
1379 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
1380 | if (!wqe) | |
1381 | return I40IW_ERR_RING_FULL; | |
1382 | temp = info->mac_addr[5] | | |
1383 | LS_64_1(info->mac_addr[4], 8) | | |
1384 | LS_64_1(info->mac_addr[3], 16) | | |
1385 | LS_64_1(info->mac_addr[2], 24) | | |
1386 | LS_64_1(info->mac_addr[1], 32) | | |
1387 | LS_64_1(info->mac_addr[0], 40); | |
1388 | ||
1389 | set_64bit_val(wqe, 32, temp); | |
1390 | ||
1391 | header = LS_64(info->entry_idx, I40IW_CQPSQ_MLIPA_IPTABLEIDX) | | |
1392 | LS_64(I40IW_CQP_OP_MANAGE_LOC_MAC_IP_TABLE, I40IW_CQPSQ_OPCODE) | | |
1393 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
1394 | ||
1395 | i40iw_insert_wqe_hdr(wqe, header); | |
1396 | ||
1397 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "ADD_LOCAL_MAC_IPADDR WQE", | |
1398 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
1399 | ||
1400 | if (post_sq) | |
1401 | i40iw_sc_cqp_post_sq(cqp); | |
1402 | return 0; | |
1403 | } | |
1404 | ||
1405 | /** | |
1406 | * i40iw_sc_del_local_mac_ipaddr_entry - cqp wqe to dele local mac | |
1407 | * @cqp: struct for cqp hw | |
1408 | * @scratch: u64 saved to be used during cqp completion | |
1409 | * @entry_idx: index of mac entry | |
1410 | * @ ignore_ref_count: to force mac adde delete | |
1411 | * @post_sq: flag for cqp db to ring | |
1412 | */ | |
1413 | static enum i40iw_status_code i40iw_sc_del_local_mac_ipaddr_entry( | |
1414 | struct i40iw_sc_cqp *cqp, | |
1415 | u64 scratch, | |
1416 | u8 entry_idx, | |
1417 | u8 ignore_ref_count, | |
1418 | bool post_sq) | |
1419 | { | |
1420 | u64 *wqe; | |
1421 | u64 header; | |
1422 | ||
1423 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
1424 | if (!wqe) | |
1425 | return I40IW_ERR_RING_FULL; | |
1426 | header = LS_64(entry_idx, I40IW_CQPSQ_MLIPA_IPTABLEIDX) | | |
1427 | LS_64(I40IW_CQP_OP_MANAGE_LOC_MAC_IP_TABLE, I40IW_CQPSQ_OPCODE) | | |
1428 | LS_64(1, I40IW_CQPSQ_MLIPA_FREEENTRY) | | |
1429 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID) | | |
1430 | LS_64(ignore_ref_count, I40IW_CQPSQ_MLIPA_IGNORE_REF_CNT); | |
1431 | ||
1432 | i40iw_insert_wqe_hdr(wqe, header); | |
1433 | ||
1434 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "DEL_LOCAL_MAC_IPADDR WQE", | |
1435 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
1436 | ||
1437 | if (post_sq) | |
1438 | i40iw_sc_cqp_post_sq(cqp); | |
1439 | return 0; | |
1440 | } | |
1441 | ||
1442 | /** | |
1443 | * i40iw_sc_cqp_nop - send a nop wqe | |
1444 | * @cqp: struct for cqp hw | |
1445 | * @scratch: u64 saved to be used during cqp completion | |
1446 | * @post_sq: flag for cqp db to ring | |
1447 | */ | |
1448 | static enum i40iw_status_code i40iw_sc_cqp_nop(struct i40iw_sc_cqp *cqp, | |
1449 | u64 scratch, | |
1450 | bool post_sq) | |
1451 | { | |
1452 | u64 *wqe; | |
1453 | u64 header; | |
1454 | ||
1455 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
1456 | if (!wqe) | |
1457 | return I40IW_ERR_RING_FULL; | |
1458 | header = LS_64(I40IW_CQP_OP_NOP, I40IW_CQPSQ_OPCODE) | | |
1459 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
1460 | i40iw_insert_wqe_hdr(wqe, header); | |
1461 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "NOP WQE", | |
1462 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
1463 | ||
1464 | if (post_sq) | |
1465 | i40iw_sc_cqp_post_sq(cqp); | |
1466 | return 0; | |
1467 | } | |
1468 | ||
1469 | /** | |
1470 | * i40iw_sc_ceq_init - initialize ceq | |
1471 | * @ceq: ceq sc structure | |
1472 | * @info: ceq initialization info | |
1473 | */ | |
1474 | static enum i40iw_status_code i40iw_sc_ceq_init(struct i40iw_sc_ceq *ceq, | |
1475 | struct i40iw_ceq_init_info *info) | |
1476 | { | |
1477 | u32 pble_obj_cnt; | |
1478 | ||
1479 | if ((info->elem_cnt < I40IW_MIN_CEQ_ENTRIES) || | |
1480 | (info->elem_cnt > I40IW_MAX_CEQ_ENTRIES)) | |
1481 | return I40IW_ERR_INVALID_SIZE; | |
1482 | ||
1483 | if (info->ceq_id >= I40IW_MAX_CEQID) | |
1484 | return I40IW_ERR_INVALID_CEQ_ID; | |
1485 | ||
1486 | pble_obj_cnt = info->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt; | |
1487 | ||
1488 | if (info->virtual_map && (info->first_pm_pbl_idx >= pble_obj_cnt)) | |
1489 | return I40IW_ERR_INVALID_PBLE_INDEX; | |
1490 | ||
1491 | ceq->size = sizeof(*ceq); | |
1492 | ceq->ceqe_base = (struct i40iw_ceqe *)info->ceqe_base; | |
1493 | ceq->ceq_id = info->ceq_id; | |
1494 | ceq->dev = info->dev; | |
1495 | ceq->elem_cnt = info->elem_cnt; | |
1496 | ceq->ceq_elem_pa = info->ceqe_pa; | |
1497 | ceq->virtual_map = info->virtual_map; | |
1498 | ||
1499 | ceq->pbl_chunk_size = (ceq->virtual_map ? info->pbl_chunk_size : 0); | |
1500 | ceq->first_pm_pbl_idx = (ceq->virtual_map ? info->first_pm_pbl_idx : 0); | |
1501 | ceq->pbl_list = (ceq->virtual_map ? info->pbl_list : NULL); | |
1502 | ||
1503 | ceq->tph_en = info->tph_en; | |
1504 | ceq->tph_val = info->tph_val; | |
1505 | ceq->polarity = 1; | |
1506 | I40IW_RING_INIT(ceq->ceq_ring, ceq->elem_cnt); | |
1507 | ceq->dev->ceq[info->ceq_id] = ceq; | |
1508 | ||
1509 | return 0; | |
1510 | } | |
1511 | ||
1512 | /** | |
1513 | * i40iw_sc_ceq_create - create ceq wqe | |
1514 | * @ceq: ceq sc structure | |
1515 | * @scratch: u64 saved to be used during cqp completion | |
1516 | * @post_sq: flag for cqp db to ring | |
1517 | */ | |
1518 | static enum i40iw_status_code i40iw_sc_ceq_create(struct i40iw_sc_ceq *ceq, | |
1519 | u64 scratch, | |
1520 | bool post_sq) | |
1521 | { | |
1522 | struct i40iw_sc_cqp *cqp; | |
1523 | u64 *wqe; | |
1524 | u64 header; | |
1525 | ||
1526 | cqp = ceq->dev->cqp; | |
1527 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
1528 | if (!wqe) | |
1529 | return I40IW_ERR_RING_FULL; | |
1530 | set_64bit_val(wqe, 16, ceq->elem_cnt); | |
1531 | set_64bit_val(wqe, 32, (ceq->virtual_map ? 0 : ceq->ceq_elem_pa)); | |
1532 | set_64bit_val(wqe, 48, (ceq->virtual_map ? ceq->first_pm_pbl_idx : 0)); | |
1533 | set_64bit_val(wqe, 56, LS_64(ceq->tph_val, I40IW_CQPSQ_TPHVAL)); | |
1534 | ||
1535 | header = ceq->ceq_id | | |
1536 | LS_64(I40IW_CQP_OP_CREATE_CEQ, I40IW_CQPSQ_OPCODE) | | |
1537 | LS_64(ceq->pbl_chunk_size, I40IW_CQPSQ_CEQ_LPBLSIZE) | | |
1538 | LS_64(ceq->virtual_map, I40IW_CQPSQ_CEQ_VMAP) | | |
1539 | LS_64(ceq->tph_en, I40IW_CQPSQ_TPHEN) | | |
1540 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
1541 | ||
1542 | i40iw_insert_wqe_hdr(wqe, header); | |
1543 | ||
1544 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CEQ_CREATE WQE", | |
1545 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
1546 | ||
1547 | if (post_sq) | |
1548 | i40iw_sc_cqp_post_sq(cqp); | |
1549 | return 0; | |
1550 | } | |
1551 | ||
1552 | /** | |
1553 | * i40iw_sc_cceq_create_done - poll for control ceq wqe to complete | |
1554 | * @ceq: ceq sc structure | |
1555 | */ | |
1556 | static enum i40iw_status_code i40iw_sc_cceq_create_done(struct i40iw_sc_ceq *ceq) | |
1557 | { | |
1558 | struct i40iw_sc_cqp *cqp; | |
1559 | ||
1560 | cqp = ceq->dev->cqp; | |
1561 | return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_CREATE_CEQ, NULL); | |
1562 | } | |
1563 | ||
1564 | /** | |
1565 | * i40iw_sc_cceq_destroy_done - poll for destroy cceq to complete | |
1566 | * @ceq: ceq sc structure | |
1567 | */ | |
1568 | static enum i40iw_status_code i40iw_sc_cceq_destroy_done(struct i40iw_sc_ceq *ceq) | |
1569 | { | |
1570 | struct i40iw_sc_cqp *cqp; | |
1571 | ||
1572 | cqp = ceq->dev->cqp; | |
1573 | cqp->process_cqp_sds = i40iw_update_sds_noccq; | |
1574 | return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_DESTROY_CEQ, NULL); | |
1575 | } | |
1576 | ||
1577 | /** | |
1578 | * i40iw_sc_cceq_create - create cceq | |
1579 | * @ceq: ceq sc structure | |
1580 | * @scratch: u64 saved to be used during cqp completion | |
1581 | */ | |
1582 | static enum i40iw_status_code i40iw_sc_cceq_create(struct i40iw_sc_ceq *ceq, u64 scratch) | |
1583 | { | |
1584 | enum i40iw_status_code ret_code; | |
1585 | ||
1586 | ret_code = i40iw_sc_ceq_create(ceq, scratch, true); | |
1587 | if (!ret_code) | |
1588 | ret_code = i40iw_sc_cceq_create_done(ceq); | |
1589 | return ret_code; | |
1590 | } | |
1591 | ||
1592 | /** | |
1593 | * i40iw_sc_ceq_destroy - destroy ceq | |
1594 | * @ceq: ceq sc structure | |
1595 | * @scratch: u64 saved to be used during cqp completion | |
1596 | * @post_sq: flag for cqp db to ring | |
1597 | */ | |
1598 | static enum i40iw_status_code i40iw_sc_ceq_destroy(struct i40iw_sc_ceq *ceq, | |
1599 | u64 scratch, | |
1600 | bool post_sq) | |
1601 | { | |
1602 | struct i40iw_sc_cqp *cqp; | |
1603 | u64 *wqe; | |
1604 | u64 header; | |
1605 | ||
1606 | cqp = ceq->dev->cqp; | |
1607 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
1608 | if (!wqe) | |
1609 | return I40IW_ERR_RING_FULL; | |
1610 | set_64bit_val(wqe, 16, ceq->elem_cnt); | |
1611 | set_64bit_val(wqe, 48, ceq->first_pm_pbl_idx); | |
1612 | header = ceq->ceq_id | | |
1613 | LS_64(I40IW_CQP_OP_DESTROY_CEQ, I40IW_CQPSQ_OPCODE) | | |
1614 | LS_64(ceq->pbl_chunk_size, I40IW_CQPSQ_CEQ_LPBLSIZE) | | |
1615 | LS_64(ceq->virtual_map, I40IW_CQPSQ_CEQ_VMAP) | | |
1616 | LS_64(ceq->tph_en, I40IW_CQPSQ_TPHEN) | | |
1617 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
1618 | i40iw_insert_wqe_hdr(wqe, header); | |
1619 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CEQ_DESTROY WQE", | |
1620 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
1621 | ||
1622 | if (post_sq) | |
1623 | i40iw_sc_cqp_post_sq(cqp); | |
1624 | return 0; | |
1625 | } | |
1626 | ||
1627 | /** | |
1628 | * i40iw_sc_process_ceq - process ceq | |
1629 | * @dev: sc device struct | |
1630 | * @ceq: ceq sc structure | |
1631 | */ | |
1632 | static void *i40iw_sc_process_ceq(struct i40iw_sc_dev *dev, struct i40iw_sc_ceq *ceq) | |
1633 | { | |
1634 | u64 temp; | |
1635 | u64 *ceqe; | |
1636 | struct i40iw_sc_cq *cq = NULL; | |
1637 | u8 polarity; | |
1638 | ||
1639 | ceqe = (u64 *)I40IW_GET_CURRENT_CEQ_ELEMENT(ceq); | |
1640 | get_64bit_val(ceqe, 0, &temp); | |
1641 | polarity = (u8)RS_64(temp, I40IW_CEQE_VALID); | |
1642 | if (polarity != ceq->polarity) | |
1643 | return cq; | |
1644 | ||
1645 | cq = (struct i40iw_sc_cq *)(unsigned long)LS_64_1(temp, 1); | |
1646 | ||
1647 | I40IW_RING_MOVE_TAIL(ceq->ceq_ring); | |
1648 | if (I40IW_RING_GETCURRENT_TAIL(ceq->ceq_ring) == 0) | |
1649 | ceq->polarity ^= 1; | |
1650 | ||
1651 | if (dev->is_pf) | |
1652 | i40iw_wr32(dev->hw, I40E_PFPE_CQACK, cq->cq_uk.cq_id); | |
1653 | else | |
1654 | i40iw_wr32(dev->hw, I40E_VFPE_CQACK1, cq->cq_uk.cq_id); | |
1655 | ||
1656 | return cq; | |
1657 | } | |
1658 | ||
1659 | /** | |
1660 | * i40iw_sc_aeq_init - initialize aeq | |
1661 | * @aeq: aeq structure ptr | |
1662 | * @info: aeq initialization info | |
1663 | */ | |
1664 | static enum i40iw_status_code i40iw_sc_aeq_init(struct i40iw_sc_aeq *aeq, | |
1665 | struct i40iw_aeq_init_info *info) | |
1666 | { | |
1667 | u32 pble_obj_cnt; | |
1668 | ||
1669 | if ((info->elem_cnt < I40IW_MIN_AEQ_ENTRIES) || | |
1670 | (info->elem_cnt > I40IW_MAX_AEQ_ENTRIES)) | |
1671 | return I40IW_ERR_INVALID_SIZE; | |
1672 | pble_obj_cnt = info->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt; | |
1673 | ||
1674 | if (info->virtual_map && (info->first_pm_pbl_idx >= pble_obj_cnt)) | |
1675 | return I40IW_ERR_INVALID_PBLE_INDEX; | |
1676 | ||
1677 | aeq->size = sizeof(*aeq); | |
1678 | aeq->polarity = 1; | |
1679 | aeq->aeqe_base = (struct i40iw_sc_aeqe *)info->aeqe_base; | |
1680 | aeq->dev = info->dev; | |
1681 | aeq->elem_cnt = info->elem_cnt; | |
1682 | ||
1683 | aeq->aeq_elem_pa = info->aeq_elem_pa; | |
1684 | I40IW_RING_INIT(aeq->aeq_ring, aeq->elem_cnt); | |
1685 | info->dev->aeq = aeq; | |
1686 | ||
1687 | aeq->virtual_map = info->virtual_map; | |
1688 | aeq->pbl_list = (aeq->virtual_map ? info->pbl_list : NULL); | |
1689 | aeq->pbl_chunk_size = (aeq->virtual_map ? info->pbl_chunk_size : 0); | |
1690 | aeq->first_pm_pbl_idx = (aeq->virtual_map ? info->first_pm_pbl_idx : 0); | |
1691 | info->dev->aeq = aeq; | |
1692 | return 0; | |
1693 | } | |
1694 | ||
1695 | /** | |
1696 | * i40iw_sc_aeq_create - create aeq | |
1697 | * @aeq: aeq structure ptr | |
1698 | * @scratch: u64 saved to be used during cqp completion | |
1699 | * @post_sq: flag for cqp db to ring | |
1700 | */ | |
1701 | static enum i40iw_status_code i40iw_sc_aeq_create(struct i40iw_sc_aeq *aeq, | |
1702 | u64 scratch, | |
1703 | bool post_sq) | |
1704 | { | |
1705 | u64 *wqe; | |
1706 | struct i40iw_sc_cqp *cqp; | |
1707 | u64 header; | |
1708 | ||
1709 | cqp = aeq->dev->cqp; | |
1710 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
1711 | if (!wqe) | |
1712 | return I40IW_ERR_RING_FULL; | |
1713 | set_64bit_val(wqe, 16, aeq->elem_cnt); | |
1714 | set_64bit_val(wqe, 32, | |
1715 | (aeq->virtual_map ? 0 : aeq->aeq_elem_pa)); | |
1716 | set_64bit_val(wqe, 48, | |
1717 | (aeq->virtual_map ? aeq->first_pm_pbl_idx : 0)); | |
1718 | ||
1719 | header = LS_64(I40IW_CQP_OP_CREATE_AEQ, I40IW_CQPSQ_OPCODE) | | |
1720 | LS_64(aeq->pbl_chunk_size, I40IW_CQPSQ_AEQ_LPBLSIZE) | | |
1721 | LS_64(aeq->virtual_map, I40IW_CQPSQ_AEQ_VMAP) | | |
1722 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
1723 | ||
1724 | i40iw_insert_wqe_hdr(wqe, header); | |
1725 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "AEQ_CREATE WQE", | |
1726 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
1727 | if (post_sq) | |
1728 | i40iw_sc_cqp_post_sq(cqp); | |
1729 | return 0; | |
1730 | } | |
1731 | ||
1732 | /** | |
1733 | * i40iw_sc_aeq_destroy - destroy aeq during close | |
1734 | * @aeq: aeq structure ptr | |
1735 | * @scratch: u64 saved to be used during cqp completion | |
1736 | * @post_sq: flag for cqp db to ring | |
1737 | */ | |
1738 | static enum i40iw_status_code i40iw_sc_aeq_destroy(struct i40iw_sc_aeq *aeq, | |
1739 | u64 scratch, | |
1740 | bool post_sq) | |
1741 | { | |
1742 | u64 *wqe; | |
1743 | struct i40iw_sc_cqp *cqp; | |
1744 | u64 header; | |
1745 | ||
1746 | cqp = aeq->dev->cqp; | |
1747 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
1748 | if (!wqe) | |
1749 | return I40IW_ERR_RING_FULL; | |
1750 | set_64bit_val(wqe, 16, aeq->elem_cnt); | |
1751 | set_64bit_val(wqe, 48, aeq->first_pm_pbl_idx); | |
1752 | header = LS_64(I40IW_CQP_OP_DESTROY_AEQ, I40IW_CQPSQ_OPCODE) | | |
1753 | LS_64(aeq->pbl_chunk_size, I40IW_CQPSQ_AEQ_LPBLSIZE) | | |
1754 | LS_64(aeq->virtual_map, I40IW_CQPSQ_AEQ_VMAP) | | |
1755 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
1756 | i40iw_insert_wqe_hdr(wqe, header); | |
1757 | ||
1758 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "AEQ_DESTROY WQE", | |
1759 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
1760 | if (post_sq) | |
1761 | i40iw_sc_cqp_post_sq(cqp); | |
1762 | return 0; | |
1763 | } | |
1764 | ||
1765 | /** | |
1766 | * i40iw_sc_get_next_aeqe - get next aeq entry | |
1767 | * @aeq: aeq structure ptr | |
1768 | * @info: aeqe info to be returned | |
1769 | */ | |
1770 | static enum i40iw_status_code i40iw_sc_get_next_aeqe(struct i40iw_sc_aeq *aeq, | |
1771 | struct i40iw_aeqe_info *info) | |
1772 | { | |
1773 | u64 temp, compl_ctx; | |
1774 | u64 *aeqe; | |
1775 | u16 wqe_idx; | |
1776 | u8 ae_src; | |
1777 | u8 polarity; | |
1778 | ||
1779 | aeqe = (u64 *)I40IW_GET_CURRENT_AEQ_ELEMENT(aeq); | |
1780 | get_64bit_val(aeqe, 0, &compl_ctx); | |
1781 | get_64bit_val(aeqe, 8, &temp); | |
1782 | polarity = (u8)RS_64(temp, I40IW_AEQE_VALID); | |
1783 | ||
1784 | if (aeq->polarity != polarity) | |
1785 | return I40IW_ERR_QUEUE_EMPTY; | |
1786 | ||
1787 | i40iw_debug_buf(aeq->dev, I40IW_DEBUG_WQE, "AEQ_ENTRY", aeqe, 16); | |
1788 | ||
1789 | ae_src = (u8)RS_64(temp, I40IW_AEQE_AESRC); | |
1790 | wqe_idx = (u16)RS_64(temp, I40IW_AEQE_WQDESCIDX); | |
1791 | info->qp_cq_id = (u32)RS_64(temp, I40IW_AEQE_QPCQID); | |
1792 | info->ae_id = (u16)RS_64(temp, I40IW_AEQE_AECODE); | |
1793 | info->tcp_state = (u8)RS_64(temp, I40IW_AEQE_TCPSTATE); | |
1794 | info->iwarp_state = (u8)RS_64(temp, I40IW_AEQE_IWSTATE); | |
1795 | info->q2_data_written = (u8)RS_64(temp, I40IW_AEQE_Q2DATA); | |
1796 | info->aeqe_overflow = (bool)RS_64(temp, I40IW_AEQE_OVERFLOW); | |
4236f4b9 MI |
1797 | |
1798 | switch (info->ae_id) { | |
1799 | case I40IW_AE_PRIV_OPERATION_DENIED: | |
1800 | case I40IW_AE_UDA_XMIT_DGRAM_TOO_LONG: | |
1801 | case I40IW_AE_UDA_XMIT_DGRAM_TOO_SHORT: | |
1802 | case I40IW_AE_BAD_CLOSE: | |
1803 | case I40IW_AE_RDMAP_ROE_BAD_LLP_CLOSE: | |
1804 | case I40IW_AE_RDMA_READ_WHILE_ORD_ZERO: | |
1805 | case I40IW_AE_STAG_ZERO_INVALID: | |
1806 | case I40IW_AE_IB_RREQ_AND_Q1_FULL: | |
1807 | case I40IW_AE_WQE_UNEXPECTED_OPCODE: | |
1808 | case I40IW_AE_DDP_UBE_INVALID_DDP_VERSION: | |
1809 | case I40IW_AE_DDP_UBE_INVALID_MO: | |
1810 | case I40IW_AE_DDP_UBE_INVALID_QN: | |
1811 | case I40IW_AE_DDP_NO_L_BIT: | |
1812 | case I40IW_AE_RDMAP_ROE_INVALID_RDMAP_VERSION: | |
1813 | case I40IW_AE_RDMAP_ROE_UNEXPECTED_OPCODE: | |
1814 | case I40IW_AE_ROE_INVALID_RDMA_READ_REQUEST: | |
1815 | case I40IW_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP: | |
1816 | case I40IW_AE_INVALID_ARP_ENTRY: | |
1817 | case I40IW_AE_INVALID_TCP_OPTION_RCVD: | |
1818 | case I40IW_AE_STALE_ARP_ENTRY: | |
1819 | case I40IW_AE_LLP_CLOSE_COMPLETE: | |
1820 | case I40IW_AE_LLP_CONNECTION_RESET: | |
1821 | case I40IW_AE_LLP_FIN_RECEIVED: | |
1822 | case I40IW_AE_LLP_RECEIVED_MPA_CRC_ERROR: | |
1823 | case I40IW_AE_LLP_SEGMENT_TOO_SMALL: | |
1824 | case I40IW_AE_LLP_SYN_RECEIVED: | |
1825 | case I40IW_AE_LLP_TERMINATE_RECEIVED: | |
1826 | case I40IW_AE_LLP_TOO_MANY_RETRIES: | |
1827 | case I40IW_AE_LLP_DOUBT_REACHABILITY: | |
1828 | case I40IW_AE_RESET_SENT: | |
1829 | case I40IW_AE_TERMINATE_SENT: | |
1830 | case I40IW_AE_RESET_NOT_SENT: | |
1831 | case I40IW_AE_LCE_QP_CATASTROPHIC: | |
1832 | case I40IW_AE_QP_SUSPEND_COMPLETE: | |
1833 | info->qp = true; | |
1834 | info->compl_ctx = compl_ctx; | |
1835 | ae_src = I40IW_AE_SOURCE_RSVD; | |
1836 | break; | |
1837 | case I40IW_AE_LCE_CQ_CATASTROPHIC: | |
1838 | info->cq = true; | |
1839 | info->compl_ctx = LS_64_1(compl_ctx, 1); | |
1840 | ae_src = I40IW_AE_SOURCE_RSVD; | |
1841 | break; | |
1842 | } | |
1843 | ||
86dbcd0f FL |
1844 | switch (ae_src) { |
1845 | case I40IW_AE_SOURCE_RQ: | |
1846 | case I40IW_AE_SOURCE_RQ_0011: | |
1847 | info->qp = true; | |
1848 | info->wqe_idx = wqe_idx; | |
1849 | info->compl_ctx = compl_ctx; | |
1850 | break; | |
1851 | case I40IW_AE_SOURCE_CQ: | |
1852 | case I40IW_AE_SOURCE_CQ_0110: | |
1853 | case I40IW_AE_SOURCE_CQ_1010: | |
1854 | case I40IW_AE_SOURCE_CQ_1110: | |
1855 | info->cq = true; | |
1856 | info->compl_ctx = LS_64_1(compl_ctx, 1); | |
1857 | break; | |
1858 | case I40IW_AE_SOURCE_SQ: | |
1859 | case I40IW_AE_SOURCE_SQ_0111: | |
1860 | info->qp = true; | |
1861 | info->sq = true; | |
1862 | info->wqe_idx = wqe_idx; | |
1863 | info->compl_ctx = compl_ctx; | |
1864 | break; | |
1865 | case I40IW_AE_SOURCE_IN_RR_WR: | |
1866 | case I40IW_AE_SOURCE_IN_RR_WR_1011: | |
1867 | info->qp = true; | |
1868 | info->compl_ctx = compl_ctx; | |
1869 | info->in_rdrsp_wr = true; | |
1870 | break; | |
1871 | case I40IW_AE_SOURCE_OUT_RR: | |
1872 | case I40IW_AE_SOURCE_OUT_RR_1111: | |
1873 | info->qp = true; | |
1874 | info->compl_ctx = compl_ctx; | |
1875 | info->out_rdrsp = true; | |
1876 | break; | |
4236f4b9 MI |
1877 | case I40IW_AE_SOURCE_RSVD: |
1878 | /* fallthrough */ | |
86dbcd0f FL |
1879 | default: |
1880 | break; | |
1881 | } | |
1882 | I40IW_RING_MOVE_TAIL(aeq->aeq_ring); | |
1883 | if (I40IW_RING_GETCURRENT_TAIL(aeq->aeq_ring) == 0) | |
1884 | aeq->polarity ^= 1; | |
1885 | return 0; | |
1886 | } | |
1887 | ||
1888 | /** | |
1889 | * i40iw_sc_repost_aeq_entries - repost completed aeq entries | |
1890 | * @dev: sc device struct | |
1891 | * @count: allocate count | |
1892 | */ | |
1893 | static enum i40iw_status_code i40iw_sc_repost_aeq_entries(struct i40iw_sc_dev *dev, | |
1894 | u32 count) | |
1895 | { | |
1896 | if (count > I40IW_MAX_AEQ_ALLOCATE_COUNT) | |
1897 | return I40IW_ERR_INVALID_SIZE; | |
1898 | ||
1899 | if (dev->is_pf) | |
1900 | i40iw_wr32(dev->hw, I40E_PFPE_AEQALLOC, count); | |
1901 | else | |
1902 | i40iw_wr32(dev->hw, I40E_VFPE_AEQALLOC1, count); | |
1903 | ||
1904 | return 0; | |
1905 | } | |
1906 | ||
1907 | /** | |
1908 | * i40iw_sc_aeq_create_done - create aeq | |
1909 | * @aeq: aeq structure ptr | |
1910 | */ | |
1911 | static enum i40iw_status_code i40iw_sc_aeq_create_done(struct i40iw_sc_aeq *aeq) | |
1912 | { | |
1913 | struct i40iw_sc_cqp *cqp; | |
1914 | ||
1915 | cqp = aeq->dev->cqp; | |
1916 | return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_CREATE_AEQ, NULL); | |
1917 | } | |
1918 | ||
1919 | /** | |
1920 | * i40iw_sc_aeq_destroy_done - destroy of aeq during close | |
1921 | * @aeq: aeq structure ptr | |
1922 | */ | |
1923 | static enum i40iw_status_code i40iw_sc_aeq_destroy_done(struct i40iw_sc_aeq *aeq) | |
1924 | { | |
1925 | struct i40iw_sc_cqp *cqp; | |
1926 | ||
1927 | cqp = aeq->dev->cqp; | |
1928 | return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_DESTROY_AEQ, NULL); | |
1929 | } | |
1930 | ||
1931 | /** | |
1932 | * i40iw_sc_ccq_init - initialize control cq | |
1933 | * @cq: sc's cq ctruct | |
1934 | * @info: info for control cq initialization | |
1935 | */ | |
1936 | static enum i40iw_status_code i40iw_sc_ccq_init(struct i40iw_sc_cq *cq, | |
1937 | struct i40iw_ccq_init_info *info) | |
1938 | { | |
1939 | u32 pble_obj_cnt; | |
1940 | ||
1941 | if (info->num_elem < I40IW_MIN_CQ_SIZE || info->num_elem > I40IW_MAX_CQ_SIZE) | |
1942 | return I40IW_ERR_INVALID_SIZE; | |
1943 | ||
1944 | if (info->ceq_id > I40IW_MAX_CEQID) | |
1945 | return I40IW_ERR_INVALID_CEQ_ID; | |
1946 | ||
1947 | pble_obj_cnt = info->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt; | |
1948 | ||
1949 | if (info->virtual_map && (info->first_pm_pbl_idx >= pble_obj_cnt)) | |
1950 | return I40IW_ERR_INVALID_PBLE_INDEX; | |
1951 | ||
1952 | cq->cq_pa = info->cq_pa; | |
1953 | cq->cq_uk.cq_base = info->cq_base; | |
1954 | cq->shadow_area_pa = info->shadow_area_pa; | |
1955 | cq->cq_uk.shadow_area = info->shadow_area; | |
1956 | cq->shadow_read_threshold = info->shadow_read_threshold; | |
1957 | cq->dev = info->dev; | |
1958 | cq->ceq_id = info->ceq_id; | |
1959 | cq->cq_uk.cq_size = info->num_elem; | |
1960 | cq->cq_type = I40IW_CQ_TYPE_CQP; | |
1961 | cq->ceqe_mask = info->ceqe_mask; | |
1962 | I40IW_RING_INIT(cq->cq_uk.cq_ring, info->num_elem); | |
1963 | ||
1964 | cq->cq_uk.cq_id = 0; /* control cq is id 0 always */ | |
1965 | cq->ceq_id_valid = info->ceq_id_valid; | |
1966 | cq->tph_en = info->tph_en; | |
1967 | cq->tph_val = info->tph_val; | |
1968 | cq->cq_uk.avoid_mem_cflct = info->avoid_mem_cflct; | |
1969 | ||
1970 | cq->pbl_list = info->pbl_list; | |
1971 | cq->virtual_map = info->virtual_map; | |
1972 | cq->pbl_chunk_size = info->pbl_chunk_size; | |
1973 | cq->first_pm_pbl_idx = info->first_pm_pbl_idx; | |
1974 | cq->cq_uk.polarity = true; | |
1975 | ||
1976 | /* following are only for iw cqs so initialize them to zero */ | |
1977 | cq->cq_uk.cqe_alloc_reg = NULL; | |
1978 | info->dev->ccq = cq; | |
1979 | return 0; | |
1980 | } | |
1981 | ||
1982 | /** | |
1983 | * i40iw_sc_ccq_create_done - poll cqp for ccq create | |
1984 | * @ccq: ccq sc struct | |
1985 | */ | |
1986 | static enum i40iw_status_code i40iw_sc_ccq_create_done(struct i40iw_sc_cq *ccq) | |
1987 | { | |
1988 | struct i40iw_sc_cqp *cqp; | |
1989 | ||
1990 | cqp = ccq->dev->cqp; | |
1991 | return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_CREATE_CQ, NULL); | |
1992 | } | |
1993 | ||
1994 | /** | |
1995 | * i40iw_sc_ccq_create - create control cq | |
1996 | * @ccq: ccq sc struct | |
1997 | * @scratch: u64 saved to be used during cqp completion | |
1998 | * @check_overflow: overlow flag for ccq | |
1999 | * @post_sq: flag for cqp db to ring | |
2000 | */ | |
2001 | static enum i40iw_status_code i40iw_sc_ccq_create(struct i40iw_sc_cq *ccq, | |
2002 | u64 scratch, | |
2003 | bool check_overflow, | |
2004 | bool post_sq) | |
2005 | { | |
2006 | u64 *wqe; | |
2007 | struct i40iw_sc_cqp *cqp; | |
2008 | u64 header; | |
2009 | enum i40iw_status_code ret_code; | |
2010 | ||
2011 | cqp = ccq->dev->cqp; | |
2012 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
2013 | if (!wqe) | |
2014 | return I40IW_ERR_RING_FULL; | |
2015 | set_64bit_val(wqe, 0, ccq->cq_uk.cq_size); | |
2016 | set_64bit_val(wqe, 8, RS_64_1(ccq, 1)); | |
2017 | set_64bit_val(wqe, 16, | |
2018 | LS_64(ccq->shadow_read_threshold, I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD)); | |
2019 | set_64bit_val(wqe, 32, (ccq->virtual_map ? 0 : ccq->cq_pa)); | |
2020 | set_64bit_val(wqe, 40, ccq->shadow_area_pa); | |
2021 | set_64bit_val(wqe, 48, | |
2022 | (ccq->virtual_map ? ccq->first_pm_pbl_idx : 0)); | |
2023 | set_64bit_val(wqe, 56, | |
2024 | LS_64(ccq->tph_val, I40IW_CQPSQ_TPHVAL)); | |
2025 | ||
2026 | header = ccq->cq_uk.cq_id | | |
2027 | LS_64((ccq->ceq_id_valid ? ccq->ceq_id : 0), I40IW_CQPSQ_CQ_CEQID) | | |
2028 | LS_64(I40IW_CQP_OP_CREATE_CQ, I40IW_CQPSQ_OPCODE) | | |
2029 | LS_64(ccq->pbl_chunk_size, I40IW_CQPSQ_CQ_LPBLSIZE) | | |
2030 | LS_64(check_overflow, I40IW_CQPSQ_CQ_CHKOVERFLOW) | | |
2031 | LS_64(ccq->virtual_map, I40IW_CQPSQ_CQ_VIRTMAP) | | |
2032 | LS_64(ccq->ceqe_mask, I40IW_CQPSQ_CQ_ENCEQEMASK) | | |
2033 | LS_64(ccq->ceq_id_valid, I40IW_CQPSQ_CQ_CEQIDVALID) | | |
2034 | LS_64(ccq->tph_en, I40IW_CQPSQ_TPHEN) | | |
2035 | LS_64(ccq->cq_uk.avoid_mem_cflct, I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT) | | |
2036 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
2037 | ||
2038 | i40iw_insert_wqe_hdr(wqe, header); | |
2039 | ||
2040 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CCQ_CREATE WQE", | |
2041 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
2042 | ||
2043 | if (post_sq) { | |
2044 | i40iw_sc_cqp_post_sq(cqp); | |
2045 | ret_code = i40iw_sc_ccq_create_done(ccq); | |
2046 | if (ret_code) | |
2047 | return ret_code; | |
2048 | } | |
2049 | cqp->process_cqp_sds = i40iw_cqp_sds_cmd; | |
2050 | ||
2051 | return 0; | |
2052 | } | |
2053 | ||
2054 | /** | |
2055 | * i40iw_sc_ccq_destroy - destroy ccq during close | |
2056 | * @ccq: ccq sc struct | |
2057 | * @scratch: u64 saved to be used during cqp completion | |
2058 | * @post_sq: flag for cqp db to ring | |
2059 | */ | |
2060 | static enum i40iw_status_code i40iw_sc_ccq_destroy(struct i40iw_sc_cq *ccq, | |
2061 | u64 scratch, | |
2062 | bool post_sq) | |
2063 | { | |
2064 | struct i40iw_sc_cqp *cqp; | |
2065 | u64 *wqe; | |
2066 | u64 header; | |
2067 | enum i40iw_status_code ret_code = 0; | |
2068 | u32 tail, val, error; | |
2069 | ||
2070 | cqp = ccq->dev->cqp; | |
2071 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
2072 | if (!wqe) | |
2073 | return I40IW_ERR_RING_FULL; | |
2074 | set_64bit_val(wqe, 0, ccq->cq_uk.cq_size); | |
2075 | set_64bit_val(wqe, 8, RS_64_1(ccq, 1)); | |
2076 | set_64bit_val(wqe, 40, ccq->shadow_area_pa); | |
2077 | ||
2078 | header = ccq->cq_uk.cq_id | | |
2079 | LS_64((ccq->ceq_id_valid ? ccq->ceq_id : 0), I40IW_CQPSQ_CQ_CEQID) | | |
2080 | LS_64(I40IW_CQP_OP_DESTROY_CQ, I40IW_CQPSQ_OPCODE) | | |
2081 | LS_64(ccq->ceqe_mask, I40IW_CQPSQ_CQ_ENCEQEMASK) | | |
2082 | LS_64(ccq->ceq_id_valid, I40IW_CQPSQ_CQ_CEQIDVALID) | | |
2083 | LS_64(ccq->tph_en, I40IW_CQPSQ_TPHEN) | | |
2084 | LS_64(ccq->cq_uk.avoid_mem_cflct, I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT) | | |
2085 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
2086 | ||
2087 | i40iw_insert_wqe_hdr(wqe, header); | |
2088 | ||
2089 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CCQ_DESTROY WQE", | |
2090 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
2091 | ||
2092 | i40iw_get_cqp_reg_info(cqp, &val, &tail, &error); | |
2093 | if (error) | |
2094 | return I40IW_ERR_CQP_COMPL_ERROR; | |
2095 | ||
2096 | if (post_sq) { | |
2097 | i40iw_sc_cqp_post_sq(cqp); | |
2098 | ret_code = i40iw_cqp_poll_registers(cqp, tail, 1000); | |
2099 | } | |
2100 | ||
415920aa MI |
2101 | cqp->process_cqp_sds = i40iw_update_sds_noccq; |
2102 | ||
86dbcd0f FL |
2103 | return ret_code; |
2104 | } | |
2105 | ||
2106 | /** | |
2107 | * i40iw_sc_cq_init - initialize completion q | |
2108 | * @cq: cq struct | |
2109 | * @info: cq initialization info | |
2110 | */ | |
2111 | static enum i40iw_status_code i40iw_sc_cq_init(struct i40iw_sc_cq *cq, | |
2112 | struct i40iw_cq_init_info *info) | |
2113 | { | |
2114 | u32 __iomem *cqe_alloc_reg = NULL; | |
2115 | enum i40iw_status_code ret_code; | |
2116 | u32 pble_obj_cnt; | |
2117 | u32 arm_offset; | |
2118 | ||
2119 | pble_obj_cnt = info->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt; | |
2120 | ||
2121 | if (info->virtual_map && (info->first_pm_pbl_idx >= pble_obj_cnt)) | |
2122 | return I40IW_ERR_INVALID_PBLE_INDEX; | |
2123 | ||
2124 | cq->cq_pa = info->cq_base_pa; | |
2125 | cq->dev = info->dev; | |
2126 | cq->ceq_id = info->ceq_id; | |
2127 | arm_offset = (info->dev->is_pf) ? I40E_PFPE_CQARM : I40E_VFPE_CQARM1; | |
2128 | if (i40iw_get_hw_addr(cq->dev)) | |
2129 | cqe_alloc_reg = (u32 __iomem *)(i40iw_get_hw_addr(cq->dev) + | |
2130 | arm_offset); | |
2131 | info->cq_uk_init_info.cqe_alloc_reg = cqe_alloc_reg; | |
2132 | ret_code = i40iw_cq_uk_init(&cq->cq_uk, &info->cq_uk_init_info); | |
2133 | if (ret_code) | |
2134 | return ret_code; | |
2135 | cq->virtual_map = info->virtual_map; | |
2136 | cq->pbl_chunk_size = info->pbl_chunk_size; | |
2137 | cq->ceqe_mask = info->ceqe_mask; | |
2138 | cq->cq_type = (info->type) ? info->type : I40IW_CQ_TYPE_IWARP; | |
2139 | ||
2140 | cq->shadow_area_pa = info->shadow_area_pa; | |
2141 | cq->shadow_read_threshold = info->shadow_read_threshold; | |
2142 | ||
2143 | cq->ceq_id_valid = info->ceq_id_valid; | |
2144 | cq->tph_en = info->tph_en; | |
2145 | cq->tph_val = info->tph_val; | |
2146 | ||
2147 | cq->first_pm_pbl_idx = info->first_pm_pbl_idx; | |
2148 | ||
2149 | return 0; | |
2150 | } | |
2151 | ||
2152 | /** | |
2153 | * i40iw_sc_cq_create - create completion q | |
2154 | * @cq: cq struct | |
2155 | * @scratch: u64 saved to be used during cqp completion | |
2156 | * @check_overflow: flag for overflow check | |
2157 | * @post_sq: flag for cqp db to ring | |
2158 | */ | |
2159 | static enum i40iw_status_code i40iw_sc_cq_create(struct i40iw_sc_cq *cq, | |
2160 | u64 scratch, | |
2161 | bool check_overflow, | |
2162 | bool post_sq) | |
2163 | { | |
2164 | u64 *wqe; | |
2165 | struct i40iw_sc_cqp *cqp; | |
2166 | u64 header; | |
2167 | ||
2168 | if (cq->cq_uk.cq_id > I40IW_MAX_CQID) | |
2169 | return I40IW_ERR_INVALID_CQ_ID; | |
2170 | ||
2171 | if (cq->ceq_id > I40IW_MAX_CEQID) | |
2172 | return I40IW_ERR_INVALID_CEQ_ID; | |
2173 | ||
2174 | cqp = cq->dev->cqp; | |
2175 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
2176 | if (!wqe) | |
2177 | return I40IW_ERR_RING_FULL; | |
2178 | ||
2179 | set_64bit_val(wqe, 0, cq->cq_uk.cq_size); | |
2180 | set_64bit_val(wqe, 8, RS_64_1(cq, 1)); | |
2181 | set_64bit_val(wqe, | |
2182 | 16, | |
2183 | LS_64(cq->shadow_read_threshold, I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD)); | |
2184 | ||
2185 | set_64bit_val(wqe, 32, (cq->virtual_map ? 0 : cq->cq_pa)); | |
2186 | ||
2187 | set_64bit_val(wqe, 40, cq->shadow_area_pa); | |
2188 | set_64bit_val(wqe, 48, (cq->virtual_map ? cq->first_pm_pbl_idx : 0)); | |
2189 | set_64bit_val(wqe, 56, LS_64(cq->tph_val, I40IW_CQPSQ_TPHVAL)); | |
2190 | ||
2191 | header = cq->cq_uk.cq_id | | |
2192 | LS_64((cq->ceq_id_valid ? cq->ceq_id : 0), I40IW_CQPSQ_CQ_CEQID) | | |
2193 | LS_64(I40IW_CQP_OP_CREATE_CQ, I40IW_CQPSQ_OPCODE) | | |
2194 | LS_64(cq->pbl_chunk_size, I40IW_CQPSQ_CQ_LPBLSIZE) | | |
2195 | LS_64(check_overflow, I40IW_CQPSQ_CQ_CHKOVERFLOW) | | |
2196 | LS_64(cq->virtual_map, I40IW_CQPSQ_CQ_VIRTMAP) | | |
2197 | LS_64(cq->ceqe_mask, I40IW_CQPSQ_CQ_ENCEQEMASK) | | |
2198 | LS_64(cq->ceq_id_valid, I40IW_CQPSQ_CQ_CEQIDVALID) | | |
2199 | LS_64(cq->tph_en, I40IW_CQPSQ_TPHEN) | | |
2200 | LS_64(cq->cq_uk.avoid_mem_cflct, I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT) | | |
2201 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
2202 | ||
2203 | i40iw_insert_wqe_hdr(wqe, header); | |
2204 | ||
2205 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CQ_CREATE WQE", | |
2206 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
2207 | ||
2208 | if (post_sq) | |
2209 | i40iw_sc_cqp_post_sq(cqp); | |
2210 | return 0; | |
2211 | } | |
2212 | ||
2213 | /** | |
2214 | * i40iw_sc_cq_destroy - destroy completion q | |
2215 | * @cq: cq struct | |
2216 | * @scratch: u64 saved to be used during cqp completion | |
2217 | * @post_sq: flag for cqp db to ring | |
2218 | */ | |
2219 | static enum i40iw_status_code i40iw_sc_cq_destroy(struct i40iw_sc_cq *cq, | |
2220 | u64 scratch, | |
2221 | bool post_sq) | |
2222 | { | |
2223 | struct i40iw_sc_cqp *cqp; | |
2224 | u64 *wqe; | |
2225 | u64 header; | |
2226 | ||
2227 | cqp = cq->dev->cqp; | |
2228 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
2229 | if (!wqe) | |
2230 | return I40IW_ERR_RING_FULL; | |
2231 | set_64bit_val(wqe, 0, cq->cq_uk.cq_size); | |
2232 | set_64bit_val(wqe, 8, RS_64_1(cq, 1)); | |
2233 | set_64bit_val(wqe, 40, cq->shadow_area_pa); | |
2234 | set_64bit_val(wqe, 48, (cq->virtual_map ? cq->first_pm_pbl_idx : 0)); | |
2235 | ||
2236 | header = cq->cq_uk.cq_id | | |
2237 | LS_64((cq->ceq_id_valid ? cq->ceq_id : 0), I40IW_CQPSQ_CQ_CEQID) | | |
2238 | LS_64(I40IW_CQP_OP_DESTROY_CQ, I40IW_CQPSQ_OPCODE) | | |
2239 | LS_64(cq->pbl_chunk_size, I40IW_CQPSQ_CQ_LPBLSIZE) | | |
2240 | LS_64(cq->virtual_map, I40IW_CQPSQ_CQ_VIRTMAP) | | |
2241 | LS_64(cq->ceqe_mask, I40IW_CQPSQ_CQ_ENCEQEMASK) | | |
2242 | LS_64(cq->ceq_id_valid, I40IW_CQPSQ_CQ_CEQIDVALID) | | |
2243 | LS_64(cq->tph_en, I40IW_CQPSQ_TPHEN) | | |
2244 | LS_64(cq->cq_uk.avoid_mem_cflct, I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT) | | |
2245 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
2246 | ||
2247 | i40iw_insert_wqe_hdr(wqe, header); | |
2248 | ||
2249 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CQ_DESTROY WQE", | |
2250 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
2251 | ||
2252 | if (post_sq) | |
2253 | i40iw_sc_cqp_post_sq(cqp); | |
2254 | return 0; | |
2255 | } | |
2256 | ||
2257 | /** | |
2258 | * i40iw_sc_cq_modify - modify a Completion Queue | |
2259 | * @cq: cq struct | |
2260 | * @info: modification info struct | |
2261 | * @scratch: | |
2262 | * @post_sq: flag to post to sq | |
2263 | */ | |
2264 | static enum i40iw_status_code i40iw_sc_cq_modify(struct i40iw_sc_cq *cq, | |
2265 | struct i40iw_modify_cq_info *info, | |
2266 | u64 scratch, | |
2267 | bool post_sq) | |
2268 | { | |
2269 | struct i40iw_sc_cqp *cqp; | |
2270 | u64 *wqe; | |
2271 | u64 header; | |
2272 | u32 cq_size, ceq_id, first_pm_pbl_idx; | |
2273 | u8 pbl_chunk_size; | |
2274 | bool virtual_map, ceq_id_valid, check_overflow; | |
2275 | u32 pble_obj_cnt; | |
2276 | ||
2277 | if (info->ceq_valid && (info->ceq_id > I40IW_MAX_CEQID)) | |
2278 | return I40IW_ERR_INVALID_CEQ_ID; | |
2279 | ||
2280 | pble_obj_cnt = cq->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt; | |
2281 | ||
2282 | if (info->cq_resize && info->virtual_map && | |
2283 | (info->first_pm_pbl_idx >= pble_obj_cnt)) | |
2284 | return I40IW_ERR_INVALID_PBLE_INDEX; | |
2285 | ||
2286 | cqp = cq->dev->cqp; | |
2287 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
2288 | if (!wqe) | |
2289 | return I40IW_ERR_RING_FULL; | |
2290 | ||
2291 | cq->pbl_list = info->pbl_list; | |
2292 | cq->cq_pa = info->cq_pa; | |
2293 | cq->first_pm_pbl_idx = info->first_pm_pbl_idx; | |
2294 | ||
2295 | cq_size = info->cq_resize ? info->cq_size : cq->cq_uk.cq_size; | |
2296 | if (info->ceq_change) { | |
2297 | ceq_id_valid = true; | |
2298 | ceq_id = info->ceq_id; | |
2299 | } else { | |
2300 | ceq_id_valid = cq->ceq_id_valid; | |
2301 | ceq_id = ceq_id_valid ? cq->ceq_id : 0; | |
2302 | } | |
2303 | virtual_map = info->cq_resize ? info->virtual_map : cq->virtual_map; | |
2304 | first_pm_pbl_idx = (info->cq_resize ? | |
2305 | (info->virtual_map ? info->first_pm_pbl_idx : 0) : | |
2306 | (cq->virtual_map ? cq->first_pm_pbl_idx : 0)); | |
2307 | pbl_chunk_size = (info->cq_resize ? | |
2308 | (info->virtual_map ? info->pbl_chunk_size : 0) : | |
2309 | (cq->virtual_map ? cq->pbl_chunk_size : 0)); | |
2310 | check_overflow = info->check_overflow_change ? info->check_overflow : | |
2311 | cq->check_overflow; | |
2312 | cq->cq_uk.cq_size = cq_size; | |
2313 | cq->ceq_id_valid = ceq_id_valid; | |
2314 | cq->ceq_id = ceq_id; | |
2315 | cq->virtual_map = virtual_map; | |
2316 | cq->first_pm_pbl_idx = first_pm_pbl_idx; | |
2317 | cq->pbl_chunk_size = pbl_chunk_size; | |
2318 | cq->check_overflow = check_overflow; | |
2319 | ||
2320 | set_64bit_val(wqe, 0, cq_size); | |
2321 | set_64bit_val(wqe, 8, RS_64_1(cq, 1)); | |
2322 | set_64bit_val(wqe, 16, | |
2323 | LS_64(info->shadow_read_threshold, I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD)); | |
2324 | set_64bit_val(wqe, 32, (cq->virtual_map ? 0 : cq->cq_pa)); | |
2325 | set_64bit_val(wqe, 40, cq->shadow_area_pa); | |
2326 | set_64bit_val(wqe, 48, (cq->virtual_map ? first_pm_pbl_idx : 0)); | |
2327 | set_64bit_val(wqe, 56, LS_64(cq->tph_val, I40IW_CQPSQ_TPHVAL)); | |
2328 | ||
2329 | header = cq->cq_uk.cq_id | | |
2330 | LS_64(ceq_id, I40IW_CQPSQ_CQ_CEQID) | | |
2331 | LS_64(I40IW_CQP_OP_MODIFY_CQ, I40IW_CQPSQ_OPCODE) | | |
2332 | LS_64(info->cq_resize, I40IW_CQPSQ_CQ_CQRESIZE) | | |
2333 | LS_64(pbl_chunk_size, I40IW_CQPSQ_CQ_LPBLSIZE) | | |
2334 | LS_64(check_overflow, I40IW_CQPSQ_CQ_CHKOVERFLOW) | | |
2335 | LS_64(virtual_map, I40IW_CQPSQ_CQ_VIRTMAP) | | |
2336 | LS_64(cq->ceqe_mask, I40IW_CQPSQ_CQ_ENCEQEMASK) | | |
2337 | LS_64(ceq_id_valid, I40IW_CQPSQ_CQ_CEQIDVALID) | | |
2338 | LS_64(cq->tph_en, I40IW_CQPSQ_TPHEN) | | |
2339 | LS_64(cq->cq_uk.avoid_mem_cflct, I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT) | | |
2340 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
2341 | ||
2342 | i40iw_insert_wqe_hdr(wqe, header); | |
2343 | ||
2344 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CQ_MODIFY WQE", | |
2345 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
2346 | ||
2347 | if (post_sq) | |
2348 | i40iw_sc_cqp_post_sq(cqp); | |
2349 | return 0; | |
2350 | } | |
2351 | ||
2352 | /** | |
2353 | * i40iw_sc_qp_init - initialize qp | |
2354 | * @qp: sc qp | |
2355 | * @info: initialization qp info | |
2356 | */ | |
2357 | static enum i40iw_status_code i40iw_sc_qp_init(struct i40iw_sc_qp *qp, | |
2358 | struct i40iw_qp_init_info *info) | |
2359 | { | |
2360 | u32 __iomem *wqe_alloc_reg = NULL; | |
2361 | enum i40iw_status_code ret_code; | |
2362 | u32 pble_obj_cnt; | |
2363 | u8 wqe_size; | |
2364 | u32 offset; | |
2365 | ||
2366 | qp->dev = info->pd->dev; | |
d6f7bbcc | 2367 | qp->vsi = info->vsi; |
86dbcd0f FL |
2368 | qp->sq_pa = info->sq_pa; |
2369 | qp->rq_pa = info->rq_pa; | |
2370 | qp->hw_host_ctx_pa = info->host_ctx_pa; | |
2371 | qp->q2_pa = info->q2_pa; | |
2372 | qp->shadow_area_pa = info->shadow_area_pa; | |
2373 | ||
2374 | qp->q2_buf = info->q2; | |
2375 | qp->pd = info->pd; | |
2376 | qp->hw_host_ctx = info->host_ctx; | |
2377 | offset = (qp->pd->dev->is_pf) ? I40E_PFPE_WQEALLOC : I40E_VFPE_WQEALLOC1; | |
2378 | if (i40iw_get_hw_addr(qp->pd->dev)) | |
2379 | wqe_alloc_reg = (u32 __iomem *)(i40iw_get_hw_addr(qp->pd->dev) + | |
2380 | offset); | |
2381 | ||
2382 | info->qp_uk_init_info.wqe_alloc_reg = wqe_alloc_reg; | |
61f51b7b | 2383 | info->qp_uk_init_info.abi_ver = qp->pd->abi_ver; |
86dbcd0f FL |
2384 | ret_code = i40iw_qp_uk_init(&qp->qp_uk, &info->qp_uk_init_info); |
2385 | if (ret_code) | |
2386 | return ret_code; | |
2387 | qp->virtual_map = info->virtual_map; | |
2388 | ||
2389 | pble_obj_cnt = info->pd->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt; | |
2390 | ||
2391 | if ((info->virtual_map && (info->sq_pa >= pble_obj_cnt)) || | |
2392 | (info->virtual_map && (info->rq_pa >= pble_obj_cnt))) | |
2393 | return I40IW_ERR_INVALID_PBLE_INDEX; | |
2394 | ||
2395 | qp->llp_stream_handle = (void *)(-1); | |
2396 | qp->qp_type = (info->type) ? info->type : I40IW_QP_TYPE_IWARP; | |
2397 | ||
2398 | qp->hw_sq_size = i40iw_get_encoded_wqe_size(qp->qp_uk.sq_ring.size, | |
2399 | false); | |
2400 | i40iw_debug(qp->dev, I40IW_DEBUG_WQE, "%s: hw_sq_size[%04d] sq_ring.size[%04d]\n", | |
2401 | __func__, qp->hw_sq_size, qp->qp_uk.sq_ring.size); | |
61f51b7b CTT |
2402 | |
2403 | switch (qp->pd->abi_ver) { | |
2404 | case 4: | |
2405 | ret_code = i40iw_fragcnt_to_wqesize_rq(qp->qp_uk.max_rq_frag_cnt, | |
2406 | &wqe_size); | |
2407 | if (ret_code) | |
2408 | return ret_code; | |
2409 | break; | |
2410 | case 5: /* fallthrough until next ABI version */ | |
2411 | default: | |
2412 | if (qp->qp_uk.max_rq_frag_cnt > I40IW_MAX_WQ_FRAGMENT_COUNT) | |
2413 | return I40IW_ERR_INVALID_FRAG_COUNT; | |
2414 | wqe_size = I40IW_MAX_WQE_SIZE_RQ; | |
2415 | break; | |
2416 | } | |
86dbcd0f FL |
2417 | qp->hw_rq_size = i40iw_get_encoded_wqe_size(qp->qp_uk.rq_size * |
2418 | (wqe_size / I40IW_QP_WQE_MIN_SIZE), false); | |
2419 | i40iw_debug(qp->dev, I40IW_DEBUG_WQE, | |
2420 | "%s: hw_rq_size[%04d] qp_uk.rq_size[%04d] wqe_size[%04d]\n", | |
2421 | __func__, qp->hw_rq_size, qp->qp_uk.rq_size, wqe_size); | |
2422 | qp->sq_tph_val = info->sq_tph_val; | |
2423 | qp->rq_tph_val = info->rq_tph_val; | |
2424 | qp->sq_tph_en = info->sq_tph_en; | |
2425 | qp->rq_tph_en = info->rq_tph_en; | |
2426 | qp->rcv_tph_en = info->rcv_tph_en; | |
2427 | qp->xmit_tph_en = info->xmit_tph_en; | |
d6f7bbcc | 2428 | qp->qs_handle = qp->vsi->qos[qp->user_pri].qs_handle; |
86dbcd0f FL |
2429 | |
2430 | return 0; | |
2431 | } | |
2432 | ||
2433 | /** | |
2434 | * i40iw_sc_qp_create - create qp | |
2435 | * @qp: sc qp | |
2436 | * @info: qp create info | |
2437 | * @scratch: u64 saved to be used during cqp completion | |
2438 | * @post_sq: flag for cqp db to ring | |
2439 | */ | |
2440 | static enum i40iw_status_code i40iw_sc_qp_create( | |
2441 | struct i40iw_sc_qp *qp, | |
2442 | struct i40iw_create_qp_info *info, | |
2443 | u64 scratch, | |
2444 | bool post_sq) | |
2445 | { | |
2446 | struct i40iw_sc_cqp *cqp; | |
2447 | u64 *wqe; | |
2448 | u64 header; | |
2449 | ||
2450 | if ((qp->qp_uk.qp_id < I40IW_MIN_IW_QP_ID) || | |
2451 | (qp->qp_uk.qp_id > I40IW_MAX_IW_QP_ID)) | |
2452 | return I40IW_ERR_INVALID_QP_ID; | |
2453 | ||
2454 | cqp = qp->pd->dev->cqp; | |
2455 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
2456 | if (!wqe) | |
2457 | return I40IW_ERR_RING_FULL; | |
2458 | ||
2459 | set_64bit_val(wqe, 16, qp->hw_host_ctx_pa); | |
2460 | ||
2461 | set_64bit_val(wqe, 40, qp->shadow_area_pa); | |
2462 | ||
2463 | header = qp->qp_uk.qp_id | | |
2464 | LS_64(I40IW_CQP_OP_CREATE_QP, I40IW_CQPSQ_OPCODE) | | |
2465 | LS_64((info->ord_valid ? 1 : 0), I40IW_CQPSQ_QP_ORDVALID) | | |
2466 | LS_64(info->tcp_ctx_valid, I40IW_CQPSQ_QP_TOECTXVALID) | | |
2467 | LS_64(qp->qp_type, I40IW_CQPSQ_QP_QPTYPE) | | |
2468 | LS_64(qp->virtual_map, I40IW_CQPSQ_QP_VQ) | | |
2469 | LS_64(info->cq_num_valid, I40IW_CQPSQ_QP_CQNUMVALID) | | |
86dbcd0f FL |
2470 | LS_64(info->arp_cache_idx_valid, I40IW_CQPSQ_QP_ARPTABIDXVALID) | |
2471 | LS_64(info->next_iwarp_state, I40IW_CQPSQ_QP_NEXTIWSTATE) | | |
2472 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
2473 | ||
2474 | i40iw_insert_wqe_hdr(wqe, header); | |
2475 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QP_CREATE WQE", | |
2476 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
2477 | ||
2478 | if (post_sq) | |
2479 | i40iw_sc_cqp_post_sq(cqp); | |
2480 | return 0; | |
2481 | } | |
2482 | ||
2483 | /** | |
2484 | * i40iw_sc_qp_modify - modify qp cqp wqe | |
2485 | * @qp: sc qp | |
2486 | * @info: modify qp info | |
2487 | * @scratch: u64 saved to be used during cqp completion | |
2488 | * @post_sq: flag for cqp db to ring | |
2489 | */ | |
2490 | static enum i40iw_status_code i40iw_sc_qp_modify( | |
2491 | struct i40iw_sc_qp *qp, | |
2492 | struct i40iw_modify_qp_info *info, | |
2493 | u64 scratch, | |
2494 | bool post_sq) | |
2495 | { | |
2496 | u64 *wqe; | |
2497 | struct i40iw_sc_cqp *cqp; | |
2498 | u64 header; | |
2499 | u8 term_actions = 0; | |
2500 | u8 term_len = 0; | |
2501 | ||
2502 | cqp = qp->pd->dev->cqp; | |
2503 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
2504 | if (!wqe) | |
2505 | return I40IW_ERR_RING_FULL; | |
2506 | if (info->next_iwarp_state == I40IW_QP_STATE_TERMINATE) { | |
2507 | if (info->dont_send_fin) | |
2508 | term_actions += I40IWQP_TERM_SEND_TERM_ONLY; | |
2509 | if (info->dont_send_term) | |
2510 | term_actions += I40IWQP_TERM_SEND_FIN_ONLY; | |
2511 | if ((term_actions == I40IWQP_TERM_SEND_TERM_AND_FIN) || | |
2512 | (term_actions == I40IWQP_TERM_SEND_TERM_ONLY)) | |
2513 | term_len = info->termlen; | |
2514 | } | |
2515 | ||
2516 | set_64bit_val(wqe, | |
2517 | 8, | |
86dbcd0f FL |
2518 | LS_64(term_len, I40IW_CQPSQ_QP_TERMLEN)); |
2519 | ||
2520 | set_64bit_val(wqe, 16, qp->hw_host_ctx_pa); | |
2521 | set_64bit_val(wqe, 40, qp->shadow_area_pa); | |
2522 | ||
2523 | header = qp->qp_uk.qp_id | | |
2524 | LS_64(I40IW_CQP_OP_MODIFY_QP, I40IW_CQPSQ_OPCODE) | | |
2525 | LS_64(info->ord_valid, I40IW_CQPSQ_QP_ORDVALID) | | |
2526 | LS_64(info->tcp_ctx_valid, I40IW_CQPSQ_QP_TOECTXVALID) | | |
2527 | LS_64(info->cached_var_valid, I40IW_CQPSQ_QP_CACHEDVARVALID) | | |
2528 | LS_64(qp->virtual_map, I40IW_CQPSQ_QP_VQ) | | |
2529 | LS_64(info->cq_num_valid, I40IW_CQPSQ_QP_CQNUMVALID) | | |
2530 | LS_64(info->force_loopback, I40IW_CQPSQ_QP_FORCELOOPBACK) | | |
2531 | LS_64(qp->qp_type, I40IW_CQPSQ_QP_QPTYPE) | | |
86dbcd0f FL |
2532 | LS_64(info->remove_hash_idx, I40IW_CQPSQ_QP_REMOVEHASHENTRY) | |
2533 | LS_64(term_actions, I40IW_CQPSQ_QP_TERMACT) | | |
2534 | LS_64(info->reset_tcp_conn, I40IW_CQPSQ_QP_RESETCON) | | |
2535 | LS_64(info->arp_cache_idx_valid, I40IW_CQPSQ_QP_ARPTABIDXVALID) | | |
2536 | LS_64(info->next_iwarp_state, I40IW_CQPSQ_QP_NEXTIWSTATE) | | |
2537 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
2538 | ||
2539 | i40iw_insert_wqe_hdr(wqe, header); | |
2540 | ||
2541 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QP_MODIFY WQE", | |
2542 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
2543 | ||
2544 | if (post_sq) | |
2545 | i40iw_sc_cqp_post_sq(cqp); | |
2546 | return 0; | |
2547 | } | |
2548 | ||
2549 | /** | |
2550 | * i40iw_sc_qp_destroy - cqp destroy qp | |
2551 | * @qp: sc qp | |
2552 | * @scratch: u64 saved to be used during cqp completion | |
2553 | * @remove_hash_idx: flag if to remove hash idx | |
2554 | * @ignore_mw_bnd: memory window bind flag | |
2555 | * @post_sq: flag for cqp db to ring | |
2556 | */ | |
2557 | static enum i40iw_status_code i40iw_sc_qp_destroy( | |
2558 | struct i40iw_sc_qp *qp, | |
2559 | u64 scratch, | |
2560 | bool remove_hash_idx, | |
2561 | bool ignore_mw_bnd, | |
2562 | bool post_sq) | |
2563 | { | |
2564 | u64 *wqe; | |
2565 | struct i40iw_sc_cqp *cqp; | |
2566 | u64 header; | |
2567 | ||
d6f7bbcc | 2568 | i40iw_qp_rem_qos(qp); |
86dbcd0f FL |
2569 | cqp = qp->pd->dev->cqp; |
2570 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
2571 | if (!wqe) | |
2572 | return I40IW_ERR_RING_FULL; | |
2573 | set_64bit_val(wqe, 16, qp->hw_host_ctx_pa); | |
2574 | set_64bit_val(wqe, 40, qp->shadow_area_pa); | |
2575 | ||
2576 | header = qp->qp_uk.qp_id | | |
2577 | LS_64(I40IW_CQP_OP_DESTROY_QP, I40IW_CQPSQ_OPCODE) | | |
2578 | LS_64(qp->qp_type, I40IW_CQPSQ_QP_QPTYPE) | | |
2579 | LS_64(ignore_mw_bnd, I40IW_CQPSQ_QP_IGNOREMWBOUND) | | |
2580 | LS_64(remove_hash_idx, I40IW_CQPSQ_QP_REMOVEHASHENTRY) | | |
2581 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
2582 | ||
2583 | i40iw_insert_wqe_hdr(wqe, header); | |
2584 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QP_DESTROY WQE", | |
2585 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
2586 | ||
2587 | if (post_sq) | |
2588 | i40iw_sc_cqp_post_sq(cqp); | |
2589 | return 0; | |
2590 | } | |
2591 | ||
2592 | /** | |
2593 | * i40iw_sc_qp_flush_wqes - flush qp's wqe | |
2594 | * @qp: sc qp | |
2595 | * @info: dlush information | |
2596 | * @scratch: u64 saved to be used during cqp completion | |
2597 | * @post_sq: flag for cqp db to ring | |
2598 | */ | |
2599 | static enum i40iw_status_code i40iw_sc_qp_flush_wqes( | |
2600 | struct i40iw_sc_qp *qp, | |
2601 | struct i40iw_qp_flush_info *info, | |
2602 | u64 scratch, | |
2603 | bool post_sq) | |
2604 | { | |
2605 | u64 temp = 0; | |
2606 | u64 *wqe; | |
2607 | struct i40iw_sc_cqp *cqp; | |
2608 | u64 header; | |
2609 | bool flush_sq = false, flush_rq = false; | |
2610 | ||
2611 | if (info->rq && !qp->flush_rq) | |
2612 | flush_rq = true; | |
2613 | ||
2614 | if (info->sq && !qp->flush_sq) | |
2615 | flush_sq = true; | |
2616 | ||
2617 | qp->flush_sq |= flush_sq; | |
2618 | qp->flush_rq |= flush_rq; | |
2619 | if (!flush_sq && !flush_rq) { | |
2620 | if (info->ae_code != I40IW_AE_LLP_RECEIVED_MPA_CRC_ERROR) | |
2621 | return 0; | |
2622 | } | |
2623 | ||
2624 | cqp = qp->pd->dev->cqp; | |
2625 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
2626 | if (!wqe) | |
2627 | return I40IW_ERR_RING_FULL; | |
2628 | if (info->userflushcode) { | |
2629 | if (flush_rq) { | |
2630 | temp |= LS_64(info->rq_minor_code, I40IW_CQPSQ_FWQE_RQMNERR) | | |
2631 | LS_64(info->rq_major_code, I40IW_CQPSQ_FWQE_RQMJERR); | |
2632 | } | |
2633 | if (flush_sq) { | |
2634 | temp |= LS_64(info->sq_minor_code, I40IW_CQPSQ_FWQE_SQMNERR) | | |
2635 | LS_64(info->sq_major_code, I40IW_CQPSQ_FWQE_SQMJERR); | |
2636 | } | |
2637 | } | |
2638 | set_64bit_val(wqe, 16, temp); | |
2639 | ||
2640 | temp = (info->generate_ae) ? | |
2641 | info->ae_code | LS_64(info->ae_source, I40IW_CQPSQ_FWQE_AESOURCE) : 0; | |
2642 | ||
2643 | set_64bit_val(wqe, 8, temp); | |
2644 | ||
2645 | header = qp->qp_uk.qp_id | | |
2646 | LS_64(I40IW_CQP_OP_FLUSH_WQES, I40IW_CQPSQ_OPCODE) | | |
2647 | LS_64(info->generate_ae, I40IW_CQPSQ_FWQE_GENERATE_AE) | | |
2648 | LS_64(info->userflushcode, I40IW_CQPSQ_FWQE_USERFLCODE) | | |
2649 | LS_64(flush_sq, I40IW_CQPSQ_FWQE_FLUSHSQ) | | |
2650 | LS_64(flush_rq, I40IW_CQPSQ_FWQE_FLUSHRQ) | | |
2651 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
2652 | ||
2653 | i40iw_insert_wqe_hdr(wqe, header); | |
2654 | ||
2655 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QP_FLUSH WQE", | |
2656 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
2657 | ||
2658 | if (post_sq) | |
2659 | i40iw_sc_cqp_post_sq(cqp); | |
2660 | return 0; | |
2661 | } | |
2662 | ||
2663 | /** | |
2664 | * i40iw_sc_qp_upload_context - upload qp's context | |
2665 | * @dev: sc device struct | |
2666 | * @info: upload context info ptr for return | |
2667 | * @scratch: u64 saved to be used during cqp completion | |
2668 | * @post_sq: flag for cqp db to ring | |
2669 | */ | |
2670 | static enum i40iw_status_code i40iw_sc_qp_upload_context( | |
2671 | struct i40iw_sc_dev *dev, | |
2672 | struct i40iw_upload_context_info *info, | |
2673 | u64 scratch, | |
2674 | bool post_sq) | |
2675 | { | |
2676 | u64 *wqe; | |
2677 | struct i40iw_sc_cqp *cqp; | |
2678 | u64 header; | |
2679 | ||
2680 | cqp = dev->cqp; | |
2681 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
2682 | if (!wqe) | |
2683 | return I40IW_ERR_RING_FULL; | |
2684 | set_64bit_val(wqe, 16, info->buf_pa); | |
2685 | ||
2686 | header = LS_64(info->qp_id, I40IW_CQPSQ_UCTX_QPID) | | |
2687 | LS_64(I40IW_CQP_OP_UPLOAD_CONTEXT, I40IW_CQPSQ_OPCODE) | | |
2688 | LS_64(info->qp_type, I40IW_CQPSQ_UCTX_QPTYPE) | | |
2689 | LS_64(info->raw_format, I40IW_CQPSQ_UCTX_RAWFORMAT) | | |
2690 | LS_64(info->freeze_qp, I40IW_CQPSQ_UCTX_FREEZEQP) | | |
2691 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
2692 | ||
2693 | i40iw_insert_wqe_hdr(wqe, header); | |
2694 | ||
2695 | i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "QP_UPLOAD_CTX WQE", | |
2696 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
2697 | ||
2698 | if (post_sq) | |
2699 | i40iw_sc_cqp_post_sq(cqp); | |
2700 | return 0; | |
2701 | } | |
2702 | ||
2703 | /** | |
2704 | * i40iw_sc_qp_setctx - set qp's context | |
2705 | * @qp: sc qp | |
2706 | * @qp_ctx: context ptr | |
2707 | * @info: ctx info | |
2708 | */ | |
2709 | static enum i40iw_status_code i40iw_sc_qp_setctx( | |
2710 | struct i40iw_sc_qp *qp, | |
2711 | u64 *qp_ctx, | |
2712 | struct i40iw_qp_host_ctx_info *info) | |
2713 | { | |
2714 | struct i40iwarp_offload_info *iw; | |
2715 | struct i40iw_tcp_offload_info *tcp; | |
d6f7bbcc HO |
2716 | struct i40iw_sc_vsi *vsi; |
2717 | struct i40iw_sc_dev *dev; | |
86dbcd0f FL |
2718 | u64 qw0, qw3, qw7 = 0; |
2719 | ||
2720 | iw = info->iwarp_info; | |
2721 | tcp = info->tcp_info; | |
d6f7bbcc HO |
2722 | vsi = qp->vsi; |
2723 | dev = qp->dev; | |
0fc2dc58 HO |
2724 | if (info->add_to_qoslist) { |
2725 | qp->user_pri = info->user_pri; | |
d6f7bbcc | 2726 | i40iw_qp_add_qos(qp); |
0fc2dc58 HO |
2727 | i40iw_debug(qp->dev, I40IW_DEBUG_DCB, "%s qp[%d] UP[%d] qset[%d]\n", |
2728 | __func__, qp->qp_uk.qp_id, qp->user_pri, qp->qs_handle); | |
2729 | } | |
86dbcd0f FL |
2730 | qw0 = LS_64(qp->qp_uk.rq_wqe_size, I40IWQPC_RQWQESIZE) | |
2731 | LS_64(info->err_rq_idx_valid, I40IWQPC_ERR_RQ_IDX_VALID) | | |
2732 | LS_64(qp->rcv_tph_en, I40IWQPC_RCVTPHEN) | | |
2733 | LS_64(qp->xmit_tph_en, I40IWQPC_XMITTPHEN) | | |
2734 | LS_64(qp->rq_tph_en, I40IWQPC_RQTPHEN) | | |
2735 | LS_64(qp->sq_tph_en, I40IWQPC_SQTPHEN) | | |
2736 | LS_64(info->push_idx, I40IWQPC_PPIDX) | | |
2737 | LS_64(info->push_mode_en, I40IWQPC_PMENA); | |
2738 | ||
2739 | set_64bit_val(qp_ctx, 8, qp->sq_pa); | |
2740 | set_64bit_val(qp_ctx, 16, qp->rq_pa); | |
2741 | ||
2742 | qw3 = LS_64(qp->src_mac_addr_idx, I40IWQPC_SRCMACADDRIDX) | | |
2743 | LS_64(qp->hw_rq_size, I40IWQPC_RQSIZE) | | |
2744 | LS_64(qp->hw_sq_size, I40IWQPC_SQSIZE); | |
2745 | ||
2746 | set_64bit_val(qp_ctx, | |
2747 | 128, | |
2748 | LS_64(info->err_rq_idx, I40IWQPC_ERR_RQ_IDX)); | |
2749 | ||
2750 | set_64bit_val(qp_ctx, | |
2751 | 136, | |
2752 | LS_64(info->send_cq_num, I40IWQPC_TXCQNUM) | | |
2753 | LS_64(info->rcv_cq_num, I40IWQPC_RXCQNUM)); | |
2754 | ||
2755 | set_64bit_val(qp_ctx, | |
2756 | 168, | |
2757 | LS_64(info->qp_compl_ctx, I40IWQPC_QPCOMPCTX)); | |
2758 | set_64bit_val(qp_ctx, | |
2759 | 176, | |
2760 | LS_64(qp->sq_tph_val, I40IWQPC_SQTPHVAL) | | |
2761 | LS_64(qp->rq_tph_val, I40IWQPC_RQTPHVAL) | | |
2762 | LS_64(qp->qs_handle, I40IWQPC_QSHANDLE) | | |
66f49f88 | 2763 | LS_64(vsi->exception_lan_queue, I40IWQPC_EXCEPTION_LAN_QUEUE)); |
86dbcd0f FL |
2764 | |
2765 | if (info->iwarp_info_valid) { | |
2766 | qw0 |= LS_64(iw->ddp_ver, I40IWQPC_DDP_VER) | | |
2767 | LS_64(iw->rdmap_ver, I40IWQPC_RDMAP_VER); | |
2768 | ||
2769 | qw7 |= LS_64(iw->pd_id, I40IWQPC_PDIDX); | |
d6f7bbcc HO |
2770 | set_64bit_val(qp_ctx, |
2771 | 144, | |
2772 | LS_64(qp->q2_pa, I40IWQPC_Q2ADDR) | | |
2773 | LS_64(vsi->fcn_id, I40IWQPC_STAT_INDEX)); | |
86dbcd0f FL |
2774 | set_64bit_val(qp_ctx, |
2775 | 152, | |
2776 | LS_64(iw->last_byte_sent, I40IWQPC_LASTBYTESENT)); | |
2777 | ||
86dbcd0f FL |
2778 | set_64bit_val(qp_ctx, |
2779 | 160, | |
2780 | LS_64(iw->ord_size, I40IWQPC_ORDSIZE) | | |
2781 | LS_64(iw->ird_size, I40IWQPC_IRDSIZE) | | |
2782 | LS_64(iw->wr_rdresp_en, I40IWQPC_WRRDRSPOK) | | |
2783 | LS_64(iw->rd_enable, I40IWQPC_RDOK) | | |
2784 | LS_64(iw->snd_mark_en, I40IWQPC_SNDMARKERS) | | |
2785 | LS_64(iw->bind_en, I40IWQPC_BINDEN) | | |
2786 | LS_64(iw->fast_reg_en, I40IWQPC_FASTREGEN) | | |
2787 | LS_64(iw->priv_mode_en, I40IWQPC_PRIVEN) | | |
d6f7bbcc HO |
2788 | LS_64((((vsi->stats_fcn_id_alloc) && |
2789 | (dev->is_pf) && (vsi->fcn_id >= I40IW_FIRST_NON_PF_STAT)) ? 1 : 0), | |
2790 | I40IWQPC_USESTATSINSTANCE) | | |
86dbcd0f FL |
2791 | LS_64(1, I40IWQPC_IWARPMODE) | |
2792 | LS_64(iw->rcv_mark_en, I40IWQPC_RCVMARKERS) | | |
2793 | LS_64(iw->align_hdrs, I40IWQPC_ALIGNHDRS) | | |
2794 | LS_64(iw->rcv_no_mpa_crc, I40IWQPC_RCVNOMPACRC) | | |
2795 | LS_64(iw->rcv_mark_offset, I40IWQPC_RCVMARKOFFSET) | | |
2796 | LS_64(iw->snd_mark_offset, I40IWQPC_SNDMARKOFFSET)); | |
2797 | } | |
2798 | if (info->tcp_info_valid) { | |
2799 | qw0 |= LS_64(tcp->ipv4, I40IWQPC_IPV4) | | |
2800 | LS_64(tcp->no_nagle, I40IWQPC_NONAGLE) | | |
2801 | LS_64(tcp->insert_vlan_tag, I40IWQPC_INSERTVLANTAG) | | |
2802 | LS_64(tcp->time_stamp, I40IWQPC_TIMESTAMP) | | |
2803 | LS_64(tcp->cwnd_inc_limit, I40IWQPC_LIMIT) | | |
2804 | LS_64(tcp->drop_ooo_seg, I40IWQPC_DROPOOOSEG) | | |
2805 | LS_64(tcp->dup_ack_thresh, I40IWQPC_DUPACK_THRESH); | |
2806 | ||
2807 | qw3 |= LS_64(tcp->ttl, I40IWQPC_TTL) | | |
2808 | LS_64(tcp->src_mac_addr_idx, I40IWQPC_SRCMACADDRIDX) | | |
2809 | LS_64(tcp->avoid_stretch_ack, I40IWQPC_AVOIDSTRETCHACK) | | |
2810 | LS_64(tcp->tos, I40IWQPC_TOS) | | |
2811 | LS_64(tcp->src_port, I40IWQPC_SRCPORTNUM) | | |
2812 | LS_64(tcp->dst_port, I40IWQPC_DESTPORTNUM); | |
2813 | ||
2814 | qp->src_mac_addr_idx = tcp->src_mac_addr_idx; | |
2815 | set_64bit_val(qp_ctx, | |
2816 | 32, | |
2817 | LS_64(tcp->dest_ip_addr2, I40IWQPC_DESTIPADDR2) | | |
2818 | LS_64(tcp->dest_ip_addr3, I40IWQPC_DESTIPADDR3)); | |
2819 | ||
2820 | set_64bit_val(qp_ctx, | |
2821 | 40, | |
2822 | LS_64(tcp->dest_ip_addr0, I40IWQPC_DESTIPADDR0) | | |
2823 | LS_64(tcp->dest_ip_addr1, I40IWQPC_DESTIPADDR1)); | |
2824 | ||
2825 | set_64bit_val(qp_ctx, | |
2826 | 48, | |
2827 | LS_64(tcp->snd_mss, I40IWQPC_SNDMSS) | | |
2828 | LS_64(tcp->vlan_tag, I40IWQPC_VLANTAG) | | |
2829 | LS_64(tcp->arp_idx, I40IWQPC_ARPIDX)); | |
2830 | ||
2831 | qw7 |= LS_64(tcp->flow_label, I40IWQPC_FLOWLABEL) | | |
2832 | LS_64(tcp->wscale, I40IWQPC_WSCALE) | | |
2833 | LS_64(tcp->ignore_tcp_opt, I40IWQPC_IGNORE_TCP_OPT) | | |
2834 | LS_64(tcp->ignore_tcp_uns_opt, I40IWQPC_IGNORE_TCP_UNS_OPT) | | |
2835 | LS_64(tcp->tcp_state, I40IWQPC_TCPSTATE) | | |
2836 | LS_64(tcp->rcv_wscale, I40IWQPC_RCVSCALE) | | |
2837 | LS_64(tcp->snd_wscale, I40IWQPC_SNDSCALE); | |
2838 | ||
2839 | set_64bit_val(qp_ctx, | |
2840 | 72, | |
2841 | LS_64(tcp->time_stamp_recent, I40IWQPC_TIMESTAMP_RECENT) | | |
2842 | LS_64(tcp->time_stamp_age, I40IWQPC_TIMESTAMP_AGE)); | |
2843 | set_64bit_val(qp_ctx, | |
2844 | 80, | |
2845 | LS_64(tcp->snd_nxt, I40IWQPC_SNDNXT) | | |
2846 | LS_64(tcp->snd_wnd, I40IWQPC_SNDWND)); | |
2847 | ||
2848 | set_64bit_val(qp_ctx, | |
2849 | 88, | |
2850 | LS_64(tcp->rcv_nxt, I40IWQPC_RCVNXT) | | |
2851 | LS_64(tcp->rcv_wnd, I40IWQPC_RCVWND)); | |
2852 | set_64bit_val(qp_ctx, | |
2853 | 96, | |
2854 | LS_64(tcp->snd_max, I40IWQPC_SNDMAX) | | |
2855 | LS_64(tcp->snd_una, I40IWQPC_SNDUNA)); | |
2856 | set_64bit_val(qp_ctx, | |
2857 | 104, | |
2858 | LS_64(tcp->srtt, I40IWQPC_SRTT) | | |
2859 | LS_64(tcp->rtt_var, I40IWQPC_RTTVAR)); | |
2860 | set_64bit_val(qp_ctx, | |
2861 | 112, | |
2862 | LS_64(tcp->ss_thresh, I40IWQPC_SSTHRESH) | | |
2863 | LS_64(tcp->cwnd, I40IWQPC_CWND)); | |
2864 | set_64bit_val(qp_ctx, | |
2865 | 120, | |
2866 | LS_64(tcp->snd_wl1, I40IWQPC_SNDWL1) | | |
2867 | LS_64(tcp->snd_wl2, I40IWQPC_SNDWL2)); | |
2868 | set_64bit_val(qp_ctx, | |
2869 | 128, | |
2870 | LS_64(tcp->max_snd_window, I40IWQPC_MAXSNDWND) | | |
2871 | LS_64(tcp->rexmit_thresh, I40IWQPC_REXMIT_THRESH)); | |
2872 | set_64bit_val(qp_ctx, | |
2873 | 184, | |
2874 | LS_64(tcp->local_ipaddr3, I40IWQPC_LOCAL_IPADDR3) | | |
2875 | LS_64(tcp->local_ipaddr2, I40IWQPC_LOCAL_IPADDR2)); | |
2876 | set_64bit_val(qp_ctx, | |
2877 | 192, | |
2878 | LS_64(tcp->local_ipaddr1, I40IWQPC_LOCAL_IPADDR1) | | |
2879 | LS_64(tcp->local_ipaddr0, I40IWQPC_LOCAL_IPADDR0)); | |
2880 | } | |
2881 | ||
2882 | set_64bit_val(qp_ctx, 0, qw0); | |
2883 | set_64bit_val(qp_ctx, 24, qw3); | |
2884 | set_64bit_val(qp_ctx, 56, qw7); | |
2885 | ||
2886 | i40iw_debug_buf(qp->dev, I40IW_DEBUG_WQE, "QP_HOST)CTX WQE", | |
2887 | qp_ctx, I40IW_QP_CTX_SIZE); | |
2888 | return 0; | |
2889 | } | |
2890 | ||
2891 | /** | |
2892 | * i40iw_sc_alloc_stag - mr stag alloc | |
2893 | * @dev: sc device struct | |
2894 | * @info: stag info | |
2895 | * @scratch: u64 saved to be used during cqp completion | |
2896 | * @post_sq: flag for cqp db to ring | |
2897 | */ | |
2898 | static enum i40iw_status_code i40iw_sc_alloc_stag( | |
2899 | struct i40iw_sc_dev *dev, | |
2900 | struct i40iw_allocate_stag_info *info, | |
2901 | u64 scratch, | |
2902 | bool post_sq) | |
2903 | { | |
2904 | u64 *wqe; | |
2905 | struct i40iw_sc_cqp *cqp; | |
2906 | u64 header; | |
68583ca2 | 2907 | enum i40iw_page_size page_size; |
86dbcd0f | 2908 | |
68583ca2 | 2909 | page_size = (info->page_size == 0x200000) ? I40IW_PAGE_SIZE_2M : I40IW_PAGE_SIZE_4K; |
86dbcd0f FL |
2910 | cqp = dev->cqp; |
2911 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
2912 | if (!wqe) | |
2913 | return I40IW_ERR_RING_FULL; | |
2914 | set_64bit_val(wqe, | |
2915 | 8, | |
2916 | LS_64(info->pd_id, I40IW_CQPSQ_STAG_PDID) | | |
2917 | LS_64(info->total_len, I40IW_CQPSQ_STAG_STAGLEN)); | |
2918 | set_64bit_val(wqe, | |
2919 | 16, | |
2920 | LS_64(info->stag_idx, I40IW_CQPSQ_STAG_IDX)); | |
2921 | set_64bit_val(wqe, | |
2922 | 40, | |
2923 | LS_64(info->hmc_fcn_index, I40IW_CQPSQ_STAG_HMCFNIDX)); | |
2924 | ||
2925 | header = LS_64(I40IW_CQP_OP_ALLOC_STAG, I40IW_CQPSQ_OPCODE) | | |
2926 | LS_64(1, I40IW_CQPSQ_STAG_MR) | | |
2927 | LS_64(info->access_rights, I40IW_CQPSQ_STAG_ARIGHTS) | | |
2928 | LS_64(info->chunk_size, I40IW_CQPSQ_STAG_LPBLSIZE) | | |
68583ca2 | 2929 | LS_64(page_size, I40IW_CQPSQ_STAG_HPAGESIZE) | |
86dbcd0f FL |
2930 | LS_64(info->remote_access, I40IW_CQPSQ_STAG_REMACCENABLED) | |
2931 | LS_64(info->use_hmc_fcn_index, I40IW_CQPSQ_STAG_USEHMCFNIDX) | | |
2932 | LS_64(info->use_pf_rid, I40IW_CQPSQ_STAG_USEPFRID) | | |
2933 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
2934 | ||
2935 | i40iw_insert_wqe_hdr(wqe, header); | |
2936 | ||
2937 | i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "ALLOC_STAG WQE", | |
2938 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
2939 | ||
2940 | if (post_sq) | |
2941 | i40iw_sc_cqp_post_sq(cqp); | |
2942 | return 0; | |
2943 | } | |
2944 | ||
2945 | /** | |
2946 | * i40iw_sc_mr_reg_non_shared - non-shared mr registration | |
2947 | * @dev: sc device struct | |
2948 | * @info: mr info | |
2949 | * @scratch: u64 saved to be used during cqp completion | |
2950 | * @post_sq: flag for cqp db to ring | |
2951 | */ | |
2952 | static enum i40iw_status_code i40iw_sc_mr_reg_non_shared( | |
2953 | struct i40iw_sc_dev *dev, | |
2954 | struct i40iw_reg_ns_stag_info *info, | |
2955 | u64 scratch, | |
2956 | bool post_sq) | |
2957 | { | |
2958 | u64 *wqe; | |
2959 | u64 temp; | |
2960 | struct i40iw_sc_cqp *cqp; | |
2961 | u64 header; | |
2962 | u32 pble_obj_cnt; | |
2963 | bool remote_access; | |
2964 | u8 addr_type; | |
68583ca2 | 2965 | enum i40iw_page_size page_size; |
86dbcd0f | 2966 | |
68583ca2 | 2967 | page_size = (info->page_size == 0x200000) ? I40IW_PAGE_SIZE_2M : I40IW_PAGE_SIZE_4K; |
86dbcd0f FL |
2968 | if (info->access_rights & (I40IW_ACCESS_FLAGS_REMOTEREAD_ONLY | |
2969 | I40IW_ACCESS_FLAGS_REMOTEWRITE_ONLY)) | |
2970 | remote_access = true; | |
2971 | else | |
2972 | remote_access = false; | |
2973 | ||
2974 | pble_obj_cnt = dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt; | |
2975 | ||
2976 | if (info->chunk_size && (info->first_pm_pbl_index >= pble_obj_cnt)) | |
2977 | return I40IW_ERR_INVALID_PBLE_INDEX; | |
2978 | ||
2979 | cqp = dev->cqp; | |
2980 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
2981 | if (!wqe) | |
2982 | return I40IW_ERR_RING_FULL; | |
2983 | ||
2984 | temp = (info->addr_type == I40IW_ADDR_TYPE_VA_BASED) ? (uintptr_t)info->va : info->fbo; | |
2985 | set_64bit_val(wqe, 0, temp); | |
2986 | ||
2987 | set_64bit_val(wqe, | |
2988 | 8, | |
2989 | LS_64(info->total_len, I40IW_CQPSQ_STAG_STAGLEN) | | |
2990 | LS_64(info->pd_id, I40IW_CQPSQ_STAG_PDID)); | |
2991 | ||
2992 | set_64bit_val(wqe, | |
2993 | 16, | |
2994 | LS_64(info->stag_key, I40IW_CQPSQ_STAG_KEY) | | |
2995 | LS_64(info->stag_idx, I40IW_CQPSQ_STAG_IDX)); | |
2996 | if (!info->chunk_size) { | |
2997 | set_64bit_val(wqe, 32, info->reg_addr_pa); | |
2998 | set_64bit_val(wqe, 48, 0); | |
2999 | } else { | |
3000 | set_64bit_val(wqe, 32, 0); | |
3001 | set_64bit_val(wqe, 48, info->first_pm_pbl_index); | |
3002 | } | |
3003 | set_64bit_val(wqe, 40, info->hmc_fcn_index); | |
3004 | set_64bit_val(wqe, 56, 0); | |
3005 | ||
3006 | addr_type = (info->addr_type == I40IW_ADDR_TYPE_VA_BASED) ? 1 : 0; | |
3007 | header = LS_64(I40IW_CQP_OP_REG_MR, I40IW_CQPSQ_OPCODE) | | |
3008 | LS_64(1, I40IW_CQPSQ_STAG_MR) | | |
3009 | LS_64(info->chunk_size, I40IW_CQPSQ_STAG_LPBLSIZE) | | |
68583ca2 | 3010 | LS_64(page_size, I40IW_CQPSQ_STAG_HPAGESIZE) | |
86dbcd0f FL |
3011 | LS_64(info->access_rights, I40IW_CQPSQ_STAG_ARIGHTS) | |
3012 | LS_64(remote_access, I40IW_CQPSQ_STAG_REMACCENABLED) | | |
3013 | LS_64(addr_type, I40IW_CQPSQ_STAG_VABASEDTO) | | |
3014 | LS_64(info->use_hmc_fcn_index, I40IW_CQPSQ_STAG_USEHMCFNIDX) | | |
3015 | LS_64(info->use_pf_rid, I40IW_CQPSQ_STAG_USEPFRID) | | |
3016 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
3017 | ||
3018 | i40iw_insert_wqe_hdr(wqe, header); | |
3019 | ||
3020 | i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "MR_REG_NS WQE", | |
3021 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
3022 | ||
3023 | if (post_sq) | |
3024 | i40iw_sc_cqp_post_sq(cqp); | |
3025 | return 0; | |
3026 | } | |
3027 | ||
3028 | /** | |
3029 | * i40iw_sc_mr_reg_shared - registered shared memory region | |
3030 | * @dev: sc device struct | |
3031 | * @info: info for shared memory registeration | |
3032 | * @scratch: u64 saved to be used during cqp completion | |
3033 | * @post_sq: flag for cqp db to ring | |
3034 | */ | |
3035 | static enum i40iw_status_code i40iw_sc_mr_reg_shared( | |
3036 | struct i40iw_sc_dev *dev, | |
3037 | struct i40iw_register_shared_stag *info, | |
3038 | u64 scratch, | |
3039 | bool post_sq) | |
3040 | { | |
3041 | u64 *wqe; | |
3042 | struct i40iw_sc_cqp *cqp; | |
3043 | u64 temp, va64, fbo, header; | |
3044 | u32 va32; | |
3045 | bool remote_access; | |
3046 | u8 addr_type; | |
3047 | ||
3048 | if (info->access_rights & (I40IW_ACCESS_FLAGS_REMOTEREAD_ONLY | | |
3049 | I40IW_ACCESS_FLAGS_REMOTEWRITE_ONLY)) | |
3050 | remote_access = true; | |
3051 | else | |
3052 | remote_access = false; | |
3053 | cqp = dev->cqp; | |
3054 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
3055 | if (!wqe) | |
3056 | return I40IW_ERR_RING_FULL; | |
3057 | va64 = (uintptr_t)(info->va); | |
3058 | va32 = (u32)(va64 & 0x00000000FFFFFFFF); | |
3059 | fbo = (u64)(va32 & (4096 - 1)); | |
3060 | ||
3061 | set_64bit_val(wqe, | |
3062 | 0, | |
3063 | (info->addr_type == I40IW_ADDR_TYPE_VA_BASED ? (uintptr_t)info->va : fbo)); | |
3064 | ||
3065 | set_64bit_val(wqe, | |
3066 | 8, | |
3067 | LS_64(info->pd_id, I40IW_CQPSQ_STAG_PDID)); | |
3068 | temp = LS_64(info->new_stag_key, I40IW_CQPSQ_STAG_KEY) | | |
3069 | LS_64(info->new_stag_idx, I40IW_CQPSQ_STAG_IDX) | | |
3070 | LS_64(info->parent_stag_idx, I40IW_CQPSQ_STAG_PARENTSTAGIDX); | |
3071 | set_64bit_val(wqe, 16, temp); | |
3072 | ||
3073 | addr_type = (info->addr_type == I40IW_ADDR_TYPE_VA_BASED) ? 1 : 0; | |
3074 | header = LS_64(I40IW_CQP_OP_REG_SMR, I40IW_CQPSQ_OPCODE) | | |
3075 | LS_64(1, I40IW_CQPSQ_STAG_MR) | | |
3076 | LS_64(info->access_rights, I40IW_CQPSQ_STAG_ARIGHTS) | | |
3077 | LS_64(remote_access, I40IW_CQPSQ_STAG_REMACCENABLED) | | |
3078 | LS_64(addr_type, I40IW_CQPSQ_STAG_VABASEDTO) | | |
3079 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
3080 | ||
3081 | i40iw_insert_wqe_hdr(wqe, header); | |
3082 | ||
3083 | i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "MR_REG_SHARED WQE", | |
3084 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
3085 | ||
3086 | if (post_sq) | |
3087 | i40iw_sc_cqp_post_sq(cqp); | |
3088 | return 0; | |
3089 | } | |
3090 | ||
3091 | /** | |
3092 | * i40iw_sc_dealloc_stag - deallocate stag | |
3093 | * @dev: sc device struct | |
3094 | * @info: dealloc stag info | |
3095 | * @scratch: u64 saved to be used during cqp completion | |
3096 | * @post_sq: flag for cqp db to ring | |
3097 | */ | |
3098 | static enum i40iw_status_code i40iw_sc_dealloc_stag( | |
3099 | struct i40iw_sc_dev *dev, | |
3100 | struct i40iw_dealloc_stag_info *info, | |
3101 | u64 scratch, | |
3102 | bool post_sq) | |
3103 | { | |
3104 | u64 header; | |
3105 | u64 *wqe; | |
3106 | struct i40iw_sc_cqp *cqp; | |
3107 | ||
3108 | cqp = dev->cqp; | |
3109 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
3110 | if (!wqe) | |
3111 | return I40IW_ERR_RING_FULL; | |
3112 | set_64bit_val(wqe, | |
3113 | 8, | |
3114 | LS_64(info->pd_id, I40IW_CQPSQ_STAG_PDID)); | |
3115 | set_64bit_val(wqe, | |
3116 | 16, | |
3117 | LS_64(info->stag_idx, I40IW_CQPSQ_STAG_IDX)); | |
3118 | ||
3119 | header = LS_64(I40IW_CQP_OP_DEALLOC_STAG, I40IW_CQPSQ_OPCODE) | | |
3120 | LS_64(info->mr, I40IW_CQPSQ_STAG_MR) | | |
3121 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
3122 | ||
3123 | i40iw_insert_wqe_hdr(wqe, header); | |
3124 | ||
3125 | i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "DEALLOC_STAG WQE", | |
3126 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
3127 | ||
3128 | if (post_sq) | |
3129 | i40iw_sc_cqp_post_sq(cqp); | |
3130 | return 0; | |
3131 | } | |
3132 | ||
3133 | /** | |
3134 | * i40iw_sc_query_stag - query hardware for stag | |
3135 | * @dev: sc device struct | |
3136 | * @scratch: u64 saved to be used during cqp completion | |
3137 | * @stag_index: stag index for query | |
3138 | * @post_sq: flag for cqp db to ring | |
3139 | */ | |
3140 | static enum i40iw_status_code i40iw_sc_query_stag(struct i40iw_sc_dev *dev, | |
3141 | u64 scratch, | |
3142 | u32 stag_index, | |
3143 | bool post_sq) | |
3144 | { | |
3145 | u64 header; | |
3146 | u64 *wqe; | |
3147 | struct i40iw_sc_cqp *cqp; | |
3148 | ||
3149 | cqp = dev->cqp; | |
3150 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
3151 | if (!wqe) | |
3152 | return I40IW_ERR_RING_FULL; | |
3153 | set_64bit_val(wqe, | |
3154 | 16, | |
3155 | LS_64(stag_index, I40IW_CQPSQ_QUERYSTAG_IDX)); | |
3156 | ||
3157 | header = LS_64(I40IW_CQP_OP_QUERY_STAG, I40IW_CQPSQ_OPCODE) | | |
3158 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
3159 | ||
3160 | i40iw_insert_wqe_hdr(wqe, header); | |
3161 | ||
3162 | i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "QUERY_STAG WQE", | |
3163 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
3164 | ||
3165 | if (post_sq) | |
3166 | i40iw_sc_cqp_post_sq(cqp); | |
3167 | return 0; | |
3168 | } | |
3169 | ||
3170 | /** | |
3171 | * i40iw_sc_mw_alloc - mw allocate | |
3172 | * @dev: sc device struct | |
3173 | * @scratch: u64 saved to be used during cqp completion | |
3174 | * @mw_stag_index:stag index | |
3175 | * @pd_id: pd is for this mw | |
3176 | * @post_sq: flag for cqp db to ring | |
3177 | */ | |
3178 | static enum i40iw_status_code i40iw_sc_mw_alloc( | |
3179 | struct i40iw_sc_dev *dev, | |
3180 | u64 scratch, | |
3181 | u32 mw_stag_index, | |
3182 | u16 pd_id, | |
3183 | bool post_sq) | |
3184 | { | |
3185 | u64 header; | |
3186 | struct i40iw_sc_cqp *cqp; | |
3187 | u64 *wqe; | |
3188 | ||
3189 | cqp = dev->cqp; | |
3190 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
3191 | if (!wqe) | |
3192 | return I40IW_ERR_RING_FULL; | |
3193 | set_64bit_val(wqe, 8, LS_64(pd_id, I40IW_CQPSQ_STAG_PDID)); | |
3194 | set_64bit_val(wqe, | |
3195 | 16, | |
3196 | LS_64(mw_stag_index, I40IW_CQPSQ_STAG_IDX)); | |
3197 | ||
3198 | header = LS_64(I40IW_CQP_OP_ALLOC_STAG, I40IW_CQPSQ_OPCODE) | | |
3199 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
3200 | ||
3201 | i40iw_insert_wqe_hdr(wqe, header); | |
3202 | ||
3203 | i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "MW_ALLOC WQE", | |
3204 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
3205 | ||
3206 | if (post_sq) | |
3207 | i40iw_sc_cqp_post_sq(cqp); | |
3208 | return 0; | |
3209 | } | |
3210 | ||
b7aee855 IM |
3211 | /** |
3212 | * i40iw_sc_mr_fast_register - Posts RDMA fast register mr WR to iwarp qp | |
3213 | * @qp: sc qp struct | |
3214 | * @info: fast mr info | |
3215 | * @post_sq: flag for cqp db to ring | |
3216 | */ | |
3217 | enum i40iw_status_code i40iw_sc_mr_fast_register( | |
3218 | struct i40iw_sc_qp *qp, | |
3219 | struct i40iw_fast_reg_stag_info *info, | |
3220 | bool post_sq) | |
3221 | { | |
3222 | u64 temp, header; | |
3223 | u64 *wqe; | |
3224 | u32 wqe_idx; | |
68583ca2 | 3225 | enum i40iw_page_size page_size; |
b7aee855 | 3226 | |
68583ca2 | 3227 | page_size = (info->page_size == 0x200000) ? I40IW_PAGE_SIZE_2M : I40IW_PAGE_SIZE_4K; |
b7aee855 IM |
3228 | wqe = i40iw_qp_get_next_send_wqe(&qp->qp_uk, &wqe_idx, I40IW_QP_WQE_MIN_SIZE, |
3229 | 0, info->wr_id); | |
3230 | if (!wqe) | |
3231 | return I40IW_ERR_QP_TOOMANY_WRS_POSTED; | |
3232 | ||
3233 | i40iw_debug(qp->dev, I40IW_DEBUG_MR, "%s: wr_id[%llxh] wqe_idx[%04d] location[%p]\n", | |
3234 | __func__, info->wr_id, wqe_idx, | |
3235 | &qp->qp_uk.sq_wrtrk_array[wqe_idx].wrid); | |
3236 | temp = (info->addr_type == I40IW_ADDR_TYPE_VA_BASED) ? (uintptr_t)info->va : info->fbo; | |
3237 | set_64bit_val(wqe, 0, temp); | |
3238 | ||
3239 | temp = RS_64(info->first_pm_pbl_index >> 16, I40IWQPSQ_FIRSTPMPBLIDXHI); | |
3240 | set_64bit_val(wqe, | |
3241 | 8, | |
3242 | LS_64(temp, I40IWQPSQ_FIRSTPMPBLIDXHI) | | |
3243 | LS_64(info->reg_addr_pa >> I40IWQPSQ_PBLADDR_SHIFT, I40IWQPSQ_PBLADDR)); | |
3244 | ||
3245 | set_64bit_val(wqe, | |
3246 | 16, | |
3247 | info->total_len | | |
3248 | LS_64(info->first_pm_pbl_index, I40IWQPSQ_FIRSTPMPBLIDXLO)); | |
3249 | ||
3250 | header = LS_64(info->stag_key, I40IWQPSQ_STAGKEY) | | |
3251 | LS_64(info->stag_idx, I40IWQPSQ_STAGINDEX) | | |
3252 | LS_64(I40IWQP_OP_FAST_REGISTER, I40IWQPSQ_OPCODE) | | |
3253 | LS_64(info->chunk_size, I40IWQPSQ_LPBLSIZE) | | |
68583ca2 | 3254 | LS_64(page_size, I40IWQPSQ_HPAGESIZE) | |
b7aee855 IM |
3255 | LS_64(info->access_rights, I40IWQPSQ_STAGRIGHTS) | |
3256 | LS_64(info->addr_type, I40IWQPSQ_VABASEDTO) | | |
3257 | LS_64(info->read_fence, I40IWQPSQ_READFENCE) | | |
3258 | LS_64(info->local_fence, I40IWQPSQ_LOCALFENCE) | | |
3259 | LS_64(info->signaled, I40IWQPSQ_SIGCOMPL) | | |
3260 | LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID); | |
3261 | ||
3262 | i40iw_insert_wqe_hdr(wqe, header); | |
3263 | ||
3264 | i40iw_debug_buf(qp->dev, I40IW_DEBUG_WQE, "FAST_REG WQE", | |
3265 | wqe, I40IW_QP_WQE_MIN_SIZE); | |
3266 | ||
3267 | if (post_sq) | |
3268 | i40iw_qp_post_wr(&qp->qp_uk); | |
3269 | return 0; | |
3270 | } | |
3271 | ||
86dbcd0f FL |
3272 | /** |
3273 | * i40iw_sc_send_lsmm - send last streaming mode message | |
3274 | * @qp: sc qp struct | |
3275 | * @lsmm_buf: buffer with lsmm message | |
3276 | * @size: size of lsmm buffer | |
3277 | * @stag: stag of lsmm buffer | |
3278 | */ | |
3279 | static void i40iw_sc_send_lsmm(struct i40iw_sc_qp *qp, | |
3280 | void *lsmm_buf, | |
3281 | u32 size, | |
3282 | i40iw_stag stag) | |
3283 | { | |
3284 | u64 *wqe; | |
3285 | u64 header; | |
3286 | struct i40iw_qp_uk *qp_uk; | |
3287 | ||
3288 | qp_uk = &qp->qp_uk; | |
3289 | wqe = qp_uk->sq_base->elem; | |
3290 | ||
3291 | set_64bit_val(wqe, 0, (uintptr_t)lsmm_buf); | |
3292 | ||
3293 | set_64bit_val(wqe, 8, (size | LS_64(stag, I40IWQPSQ_FRAG_STAG))); | |
3294 | ||
3295 | set_64bit_val(wqe, 16, 0); | |
3296 | ||
3297 | header = LS_64(I40IWQP_OP_RDMA_SEND, I40IWQPSQ_OPCODE) | | |
3298 | LS_64(1, I40IWQPSQ_STREAMMODE) | | |
3299 | LS_64(1, I40IWQPSQ_WAITFORRCVPDU) | | |
3300 | LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID); | |
3301 | ||
3302 | i40iw_insert_wqe_hdr(wqe, header); | |
3303 | ||
3304 | i40iw_debug_buf(qp->dev, I40IW_DEBUG_QP, "SEND_LSMM WQE", | |
3305 | wqe, I40IW_QP_WQE_MIN_SIZE); | |
3306 | } | |
3307 | ||
3308 | /** | |
3309 | * i40iw_sc_send_lsmm_nostag - for privilege qp | |
3310 | * @qp: sc qp struct | |
3311 | * @lsmm_buf: buffer with lsmm message | |
3312 | * @size: size of lsmm buffer | |
3313 | */ | |
3314 | static void i40iw_sc_send_lsmm_nostag(struct i40iw_sc_qp *qp, | |
3315 | void *lsmm_buf, | |
3316 | u32 size) | |
3317 | { | |
3318 | u64 *wqe; | |
3319 | u64 header; | |
3320 | struct i40iw_qp_uk *qp_uk; | |
3321 | ||
3322 | qp_uk = &qp->qp_uk; | |
3323 | wqe = qp_uk->sq_base->elem; | |
3324 | ||
3325 | set_64bit_val(wqe, 0, (uintptr_t)lsmm_buf); | |
3326 | ||
3327 | set_64bit_val(wqe, 8, size); | |
3328 | ||
3329 | set_64bit_val(wqe, 16, 0); | |
3330 | ||
3331 | header = LS_64(I40IWQP_OP_RDMA_SEND, I40IWQPSQ_OPCODE) | | |
3332 | LS_64(1, I40IWQPSQ_STREAMMODE) | | |
3333 | LS_64(1, I40IWQPSQ_WAITFORRCVPDU) | | |
3334 | LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID); | |
3335 | ||
3336 | i40iw_insert_wqe_hdr(wqe, header); | |
3337 | ||
3338 | i40iw_debug_buf(qp->dev, I40IW_DEBUG_WQE, "SEND_LSMM_NOSTAG WQE", | |
3339 | wqe, I40IW_QP_WQE_MIN_SIZE); | |
3340 | } | |
3341 | ||
3342 | /** | |
3343 | * i40iw_sc_send_rtt - send last read0 or write0 | |
3344 | * @qp: sc qp struct | |
3345 | * @read: Do read0 or write0 | |
3346 | */ | |
3347 | static void i40iw_sc_send_rtt(struct i40iw_sc_qp *qp, bool read) | |
3348 | { | |
3349 | u64 *wqe; | |
3350 | u64 header; | |
3351 | struct i40iw_qp_uk *qp_uk; | |
3352 | ||
3353 | qp_uk = &qp->qp_uk; | |
3354 | wqe = qp_uk->sq_base->elem; | |
3355 | ||
3356 | set_64bit_val(wqe, 0, 0); | |
3357 | set_64bit_val(wqe, 8, 0); | |
3358 | set_64bit_val(wqe, 16, 0); | |
3359 | if (read) { | |
3360 | header = LS_64(0x1234, I40IWQPSQ_REMSTAG) | | |
3361 | LS_64(I40IWQP_OP_RDMA_READ, I40IWQPSQ_OPCODE) | | |
3362 | LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID); | |
3363 | set_64bit_val(wqe, 8, ((u64)0xabcd << 32)); | |
3364 | } else { | |
3365 | header = LS_64(I40IWQP_OP_RDMA_WRITE, I40IWQPSQ_OPCODE) | | |
3366 | LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID); | |
3367 | } | |
3368 | ||
3369 | i40iw_insert_wqe_hdr(wqe, header); | |
3370 | ||
3371 | i40iw_debug_buf(qp->dev, I40IW_DEBUG_WQE, "RTR WQE", | |
3372 | wqe, I40IW_QP_WQE_MIN_SIZE); | |
3373 | } | |
3374 | ||
3375 | /** | |
3376 | * i40iw_sc_post_wqe0 - send wqe with opcode | |
3377 | * @qp: sc qp struct | |
3378 | * @opcode: opcode to use for wqe0 | |
3379 | */ | |
3380 | static enum i40iw_status_code i40iw_sc_post_wqe0(struct i40iw_sc_qp *qp, u8 opcode) | |
3381 | { | |
3382 | u64 *wqe; | |
3383 | u64 header; | |
3384 | struct i40iw_qp_uk *qp_uk; | |
3385 | ||
3386 | qp_uk = &qp->qp_uk; | |
3387 | wqe = qp_uk->sq_base->elem; | |
3388 | ||
3389 | if (!wqe) | |
3390 | return I40IW_ERR_QP_TOOMANY_WRS_POSTED; | |
3391 | switch (opcode) { | |
3392 | case I40IWQP_OP_NOP: | |
3393 | set_64bit_val(wqe, 0, 0); | |
3394 | set_64bit_val(wqe, 8, 0); | |
3395 | set_64bit_val(wqe, 16, 0); | |
3396 | header = LS_64(I40IWQP_OP_NOP, I40IWQPSQ_OPCODE) | | |
3397 | LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID); | |
3398 | ||
3399 | i40iw_insert_wqe_hdr(wqe, header); | |
3400 | break; | |
3401 | case I40IWQP_OP_RDMA_SEND: | |
3402 | set_64bit_val(wqe, 0, 0); | |
3403 | set_64bit_val(wqe, 8, 0); | |
3404 | set_64bit_val(wqe, 16, 0); | |
3405 | header = LS_64(I40IWQP_OP_RDMA_SEND, I40IWQPSQ_OPCODE) | | |
3406 | LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID) | | |
3407 | LS_64(1, I40IWQPSQ_STREAMMODE) | | |
3408 | LS_64(1, I40IWQPSQ_WAITFORRCVPDU); | |
3409 | ||
3410 | i40iw_insert_wqe_hdr(wqe, header); | |
3411 | break; | |
3412 | default: | |
3413 | i40iw_debug(qp->dev, I40IW_DEBUG_QP, "%s: Invalid WQE zero opcode\n", | |
3414 | __func__); | |
3415 | break; | |
3416 | } | |
3417 | return 0; | |
3418 | } | |
3419 | ||
3420 | /** | |
3421 | * i40iw_sc_init_iw_hmc() - queries fpm values using cqp and populates hmc_info | |
3422 | * @dev : ptr to i40iw_dev struct | |
3423 | * @hmc_fn_id: hmc function id | |
3424 | */ | |
3425 | enum i40iw_status_code i40iw_sc_init_iw_hmc(struct i40iw_sc_dev *dev, u8 hmc_fn_id) | |
3426 | { | |
3427 | struct i40iw_hmc_info *hmc_info; | |
3428 | struct i40iw_dma_mem query_fpm_mem; | |
3429 | struct i40iw_virt_mem virt_mem; | |
3430 | struct i40iw_vfdev *vf_dev = NULL; | |
3431 | u32 mem_size; | |
3432 | enum i40iw_status_code ret_code = 0; | |
3433 | bool poll_registers = true; | |
3434 | u16 iw_vf_idx; | |
3435 | u8 wait_type; | |
3436 | ||
3437 | if (hmc_fn_id >= I40IW_MAX_VF_FPM_ID || | |
3438 | (dev->hmc_fn_id != hmc_fn_id && hmc_fn_id < I40IW_FIRST_VF_FPM_ID)) | |
3439 | return I40IW_ERR_INVALID_HMCFN_ID; | |
3440 | ||
3441 | i40iw_debug(dev, I40IW_DEBUG_HMC, "hmc_fn_id %u, dev->hmc_fn_id %u\n", hmc_fn_id, | |
3442 | dev->hmc_fn_id); | |
3443 | if (hmc_fn_id == dev->hmc_fn_id) { | |
3444 | hmc_info = dev->hmc_info; | |
3445 | query_fpm_mem.pa = dev->fpm_query_buf_pa; | |
3446 | query_fpm_mem.va = dev->fpm_query_buf; | |
3447 | } else { | |
3448 | vf_dev = i40iw_vfdev_from_fpm(dev, hmc_fn_id); | |
3449 | if (!vf_dev) | |
3450 | return I40IW_ERR_INVALID_VF_ID; | |
3451 | ||
3452 | hmc_info = &vf_dev->hmc_info; | |
3453 | iw_vf_idx = vf_dev->iw_vf_idx; | |
3454 | i40iw_debug(dev, I40IW_DEBUG_HMC, "vf_dev %p, hmc_info %p, hmc_obj %p\n", vf_dev, | |
3455 | hmc_info, hmc_info->hmc_obj); | |
3456 | if (!vf_dev->fpm_query_buf) { | |
3457 | if (!dev->vf_fpm_query_buf[iw_vf_idx].va) { | |
3458 | ret_code = i40iw_alloc_query_fpm_buf(dev, | |
3459 | &dev->vf_fpm_query_buf[iw_vf_idx]); | |
3460 | if (ret_code) | |
3461 | return ret_code; | |
3462 | } | |
3463 | vf_dev->fpm_query_buf = dev->vf_fpm_query_buf[iw_vf_idx].va; | |
3464 | vf_dev->fpm_query_buf_pa = dev->vf_fpm_query_buf[iw_vf_idx].pa; | |
3465 | } | |
3466 | query_fpm_mem.pa = vf_dev->fpm_query_buf_pa; | |
3467 | query_fpm_mem.va = vf_dev->fpm_query_buf; | |
3468 | /** | |
3469 | * It is HARDWARE specific: | |
3470 | * this call is done by PF for VF and | |
3471 | * i40iw_sc_query_fpm_values needs ccq poll | |
3472 | * because PF ccq is already created. | |
3473 | */ | |
3474 | poll_registers = false; | |
3475 | } | |
3476 | ||
3477 | hmc_info->hmc_fn_id = hmc_fn_id; | |
3478 | ||
3479 | if (hmc_fn_id != dev->hmc_fn_id) { | |
3480 | ret_code = | |
3481 | i40iw_cqp_query_fpm_values_cmd(dev, &query_fpm_mem, hmc_fn_id); | |
3482 | } else { | |
3483 | wait_type = poll_registers ? (u8)I40IW_CQP_WAIT_POLL_REGS : | |
3484 | (u8)I40IW_CQP_WAIT_POLL_CQ; | |
3485 | ||
3486 | ret_code = i40iw_sc_query_fpm_values( | |
3487 | dev->cqp, | |
3488 | 0, | |
3489 | hmc_info->hmc_fn_id, | |
3490 | &query_fpm_mem, | |
3491 | true, | |
3492 | wait_type); | |
3493 | } | |
3494 | if (ret_code) | |
3495 | return ret_code; | |
3496 | ||
3497 | /* parse the fpm_query_buf and fill hmc obj info */ | |
3498 | ret_code = | |
3499 | i40iw_sc_parse_fpm_query_buf((u64 *)query_fpm_mem.va, | |
3500 | hmc_info, | |
3501 | &dev->hmc_fpm_misc); | |
3502 | if (ret_code) | |
3503 | return ret_code; | |
3504 | i40iw_debug_buf(dev, I40IW_DEBUG_HMC, "QUERY FPM BUFFER", | |
3505 | query_fpm_mem.va, I40IW_QUERY_FPM_BUF_SIZE); | |
3506 | ||
3507 | if (hmc_fn_id != dev->hmc_fn_id) { | |
3508 | i40iw_cqp_commit_fpm_values_cmd(dev, &query_fpm_mem, hmc_fn_id); | |
3509 | ||
3510 | /* parse the fpm_commit_buf and fill hmc obj info */ | |
fa415379 | 3511 | i40iw_sc_parse_fpm_commit_buf((u64 *)query_fpm_mem.va, hmc_info->hmc_obj, &hmc_info->sd_table.sd_cnt); |
86dbcd0f FL |
3512 | mem_size = sizeof(struct i40iw_hmc_sd_entry) * |
3513 | (hmc_info->sd_table.sd_cnt + hmc_info->first_sd_index); | |
3514 | ret_code = i40iw_allocate_virt_mem(dev->hw, &virt_mem, mem_size); | |
3515 | if (ret_code) | |
3516 | return ret_code; | |
3517 | hmc_info->sd_table.sd_entry = virt_mem.va; | |
3518 | } | |
3519 | ||
86dbcd0f FL |
3520 | return ret_code; |
3521 | } | |
3522 | ||
3523 | /** | |
3524 | * i40iw_sc_configure_iw_fpm() - commits hmc obj cnt values using cqp command and | |
3525 | * populates fpm base address in hmc_info | |
3526 | * @dev : ptr to i40iw_dev struct | |
3527 | * @hmc_fn_id: hmc function id | |
3528 | */ | |
3529 | static enum i40iw_status_code i40iw_sc_configure_iw_fpm(struct i40iw_sc_dev *dev, | |
3530 | u8 hmc_fn_id) | |
3531 | { | |
3532 | struct i40iw_hmc_info *hmc_info; | |
3533 | struct i40iw_hmc_obj_info *obj_info; | |
3534 | u64 *buf; | |
3535 | struct i40iw_dma_mem commit_fpm_mem; | |
3536 | u32 i, j; | |
3537 | enum i40iw_status_code ret_code = 0; | |
3538 | bool poll_registers = true; | |
3539 | u8 wait_type; | |
3540 | ||
3541 | if (hmc_fn_id >= I40IW_MAX_VF_FPM_ID || | |
3542 | (dev->hmc_fn_id != hmc_fn_id && hmc_fn_id < I40IW_FIRST_VF_FPM_ID)) | |
3543 | return I40IW_ERR_INVALID_HMCFN_ID; | |
3544 | ||
3545 | if (hmc_fn_id == dev->hmc_fn_id) { | |
3546 | hmc_info = dev->hmc_info; | |
3547 | } else { | |
3548 | hmc_info = i40iw_vf_hmcinfo_from_fpm(dev, hmc_fn_id); | |
3549 | poll_registers = false; | |
3550 | } | |
3551 | if (!hmc_info) | |
3552 | return I40IW_ERR_BAD_PTR; | |
3553 | ||
3554 | obj_info = hmc_info->hmc_obj; | |
3555 | buf = dev->fpm_commit_buf; | |
3556 | ||
3557 | /* copy cnt values in commit buf */ | |
3558 | for (i = I40IW_HMC_IW_QP, j = 0; i <= I40IW_HMC_IW_PBLE; | |
3559 | i++, j += 8) | |
3560 | set_64bit_val(buf, j, (u64)obj_info[i].cnt); | |
3561 | ||
3562 | set_64bit_val(buf, 40, 0); /* APBVT rsvd */ | |
3563 | ||
3564 | commit_fpm_mem.pa = dev->fpm_commit_buf_pa; | |
3565 | commit_fpm_mem.va = dev->fpm_commit_buf; | |
3566 | wait_type = poll_registers ? (u8)I40IW_CQP_WAIT_POLL_REGS : | |
3567 | (u8)I40IW_CQP_WAIT_POLL_CQ; | |
3568 | ret_code = i40iw_sc_commit_fpm_values( | |
3569 | dev->cqp, | |
3570 | 0, | |
3571 | hmc_info->hmc_fn_id, | |
3572 | &commit_fpm_mem, | |
3573 | true, | |
3574 | wait_type); | |
3575 | ||
3576 | /* parse the fpm_commit_buf and fill hmc obj info */ | |
3577 | if (!ret_code) | |
fa415379 IM |
3578 | ret_code = i40iw_sc_parse_fpm_commit_buf(dev->fpm_commit_buf, |
3579 | hmc_info->hmc_obj, | |
3580 | &hmc_info->sd_table.sd_cnt); | |
86dbcd0f FL |
3581 | |
3582 | i40iw_debug_buf(dev, I40IW_DEBUG_HMC, "COMMIT FPM BUFFER", | |
3583 | commit_fpm_mem.va, I40IW_COMMIT_FPM_BUF_SIZE); | |
3584 | ||
3585 | return ret_code; | |
3586 | } | |
3587 | ||
3588 | /** | |
3589 | * cqp_sds_wqe_fill - fill cqp wqe doe sd | |
3590 | * @cqp: struct for cqp hw | |
3591 | * @info; sd info for wqe | |
3592 | * @scratch: u64 saved to be used during cqp completion | |
3593 | */ | |
3594 | static enum i40iw_status_code cqp_sds_wqe_fill(struct i40iw_sc_cqp *cqp, | |
3595 | struct i40iw_update_sds_info *info, | |
3596 | u64 scratch) | |
3597 | { | |
3598 | u64 data; | |
3599 | u64 header; | |
3600 | u64 *wqe; | |
3601 | int mem_entries, wqe_entries; | |
3602 | struct i40iw_dma_mem *sdbuf = &cqp->sdbuf; | |
100d6de2 CTT |
3603 | u64 offset; |
3604 | u32 wqe_idx; | |
86dbcd0f | 3605 | |
100d6de2 | 3606 | wqe = i40iw_sc_cqp_get_next_send_wqe_idx(cqp, scratch, &wqe_idx); |
86dbcd0f FL |
3607 | if (!wqe) |
3608 | return I40IW_ERR_RING_FULL; | |
3609 | ||
3610 | I40IW_CQP_INIT_WQE(wqe); | |
3611 | wqe_entries = (info->cnt > 3) ? 3 : info->cnt; | |
3612 | mem_entries = info->cnt - wqe_entries; | |
3613 | ||
3614 | header = LS_64(I40IW_CQP_OP_UPDATE_PE_SDS, I40IW_CQPSQ_OPCODE) | | |
3615 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID) | | |
3616 | LS_64(mem_entries, I40IW_CQPSQ_UPESD_ENTRY_COUNT); | |
3617 | ||
3618 | if (mem_entries) { | |
100d6de2 CTT |
3619 | offset = wqe_idx * I40IW_UPDATE_SD_BUF_SIZE; |
3620 | memcpy((char *)sdbuf->va + offset, &info->entry[3], | |
3621 | mem_entries << 4); | |
3622 | data = (u64)sdbuf->pa + offset; | |
86dbcd0f FL |
3623 | } else { |
3624 | data = 0; | |
3625 | } | |
3626 | data |= LS_64(info->hmc_fn_id, I40IW_CQPSQ_UPESD_HMCFNID); | |
3627 | ||
3628 | set_64bit_val(wqe, 16, data); | |
3629 | ||
3630 | switch (wqe_entries) { | |
3631 | case 3: | |
3632 | set_64bit_val(wqe, 48, | |
3633 | (LS_64(info->entry[2].cmd, I40IW_CQPSQ_UPESD_SDCMD) | | |
3634 | LS_64(1, I40IW_CQPSQ_UPESD_ENTRY_VALID))); | |
3635 | ||
3636 | set_64bit_val(wqe, 56, info->entry[2].data); | |
3637 | /* fallthrough */ | |
3638 | case 2: | |
3639 | set_64bit_val(wqe, 32, | |
3640 | (LS_64(info->entry[1].cmd, I40IW_CQPSQ_UPESD_SDCMD) | | |
3641 | LS_64(1, I40IW_CQPSQ_UPESD_ENTRY_VALID))); | |
3642 | ||
3643 | set_64bit_val(wqe, 40, info->entry[1].data); | |
3644 | /* fallthrough */ | |
3645 | case 1: | |
3646 | set_64bit_val(wqe, 0, | |
3647 | LS_64(info->entry[0].cmd, I40IW_CQPSQ_UPESD_SDCMD)); | |
3648 | ||
3649 | set_64bit_val(wqe, 8, info->entry[0].data); | |
3650 | break; | |
3651 | default: | |
3652 | break; | |
3653 | } | |
3654 | ||
3655 | i40iw_insert_wqe_hdr(wqe, header); | |
3656 | ||
3657 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "UPDATE_PE_SDS WQE", | |
3658 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
3659 | return 0; | |
3660 | } | |
3661 | ||
3662 | /** | |
3663 | * i40iw_update_pe_sds - cqp wqe for sd | |
3664 | * @dev: ptr to i40iw_dev struct | |
3665 | * @info: sd info for sd's | |
3666 | * @scratch: u64 saved to be used during cqp completion | |
3667 | */ | |
3668 | static enum i40iw_status_code i40iw_update_pe_sds(struct i40iw_sc_dev *dev, | |
3669 | struct i40iw_update_sds_info *info, | |
3670 | u64 scratch) | |
3671 | { | |
3672 | struct i40iw_sc_cqp *cqp = dev->cqp; | |
3673 | enum i40iw_status_code ret_code; | |
3674 | ||
3675 | ret_code = cqp_sds_wqe_fill(cqp, info, scratch); | |
3676 | if (!ret_code) | |
3677 | i40iw_sc_cqp_post_sq(cqp); | |
3678 | ||
3679 | return ret_code; | |
3680 | } | |
3681 | ||
3682 | /** | |
3683 | * i40iw_update_sds_noccq - update sd before ccq created | |
3684 | * @dev: sc device struct | |
3685 | * @info: sd info for sd's | |
3686 | */ | |
3687 | enum i40iw_status_code i40iw_update_sds_noccq(struct i40iw_sc_dev *dev, | |
3688 | struct i40iw_update_sds_info *info) | |
3689 | { | |
3690 | u32 error, val, tail; | |
3691 | struct i40iw_sc_cqp *cqp = dev->cqp; | |
3692 | enum i40iw_status_code ret_code; | |
3693 | ||
3694 | ret_code = cqp_sds_wqe_fill(cqp, info, 0); | |
3695 | if (ret_code) | |
3696 | return ret_code; | |
3697 | i40iw_get_cqp_reg_info(cqp, &val, &tail, &error); | |
3698 | if (error) | |
3699 | return I40IW_ERR_CQP_COMPL_ERROR; | |
3700 | ||
3701 | i40iw_sc_cqp_post_sq(cqp); | |
3702 | ret_code = i40iw_cqp_poll_registers(cqp, tail, I40IW_DONE_COUNT); | |
3703 | ||
3704 | return ret_code; | |
3705 | } | |
3706 | ||
3707 | /** | |
3708 | * i40iw_sc_suspend_qp - suspend qp for param change | |
3709 | * @cqp: struct for cqp hw | |
3710 | * @qp: sc qp struct | |
3711 | * @scratch: u64 saved to be used during cqp completion | |
3712 | */ | |
3713 | enum i40iw_status_code i40iw_sc_suspend_qp(struct i40iw_sc_cqp *cqp, | |
3714 | struct i40iw_sc_qp *qp, | |
3715 | u64 scratch) | |
3716 | { | |
3717 | u64 header; | |
3718 | u64 *wqe; | |
3719 | ||
3720 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
3721 | if (!wqe) | |
3722 | return I40IW_ERR_RING_FULL; | |
3723 | header = LS_64(qp->qp_uk.qp_id, I40IW_CQPSQ_SUSPENDQP_QPID) | | |
3724 | LS_64(I40IW_CQP_OP_SUSPEND_QP, I40IW_CQPSQ_OPCODE) | | |
3725 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
3726 | ||
3727 | i40iw_insert_wqe_hdr(wqe, header); | |
3728 | ||
3729 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "SUSPEND_QP WQE", | |
3730 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
3731 | ||
3732 | i40iw_sc_cqp_post_sq(cqp); | |
3733 | return 0; | |
3734 | } | |
3735 | ||
3736 | /** | |
3737 | * i40iw_sc_resume_qp - resume qp after suspend | |
3738 | * @cqp: struct for cqp hw | |
3739 | * @qp: sc qp struct | |
3740 | * @scratch: u64 saved to be used during cqp completion | |
3741 | */ | |
3742 | enum i40iw_status_code i40iw_sc_resume_qp(struct i40iw_sc_cqp *cqp, | |
3743 | struct i40iw_sc_qp *qp, | |
3744 | u64 scratch) | |
3745 | { | |
3746 | u64 header; | |
3747 | u64 *wqe; | |
3748 | ||
3749 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
3750 | if (!wqe) | |
3751 | return I40IW_ERR_RING_FULL; | |
3752 | set_64bit_val(wqe, | |
3753 | 16, | |
3754 | LS_64(qp->qs_handle, I40IW_CQPSQ_RESUMEQP_QSHANDLE)); | |
3755 | ||
3756 | header = LS_64(qp->qp_uk.qp_id, I40IW_CQPSQ_RESUMEQP_QPID) | | |
3757 | LS_64(I40IW_CQP_OP_RESUME_QP, I40IW_CQPSQ_OPCODE) | | |
3758 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
3759 | ||
3760 | i40iw_insert_wqe_hdr(wqe, header); | |
3761 | ||
3762 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "RESUME_QP WQE", | |
3763 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
3764 | ||
3765 | i40iw_sc_cqp_post_sq(cqp); | |
3766 | return 0; | |
3767 | } | |
3768 | ||
3769 | /** | |
3770 | * i40iw_sc_static_hmc_pages_allocated - cqp wqe to allocate hmc pages | |
3771 | * @cqp: struct for cqp hw | |
3772 | * @scratch: u64 saved to be used during cqp completion | |
3773 | * @hmc_fn_id: hmc function id | |
3774 | * @post_sq: flag for cqp db to ring | |
3775 | * @poll_registers: flag to poll register for cqp completion | |
3776 | */ | |
3777 | enum i40iw_status_code i40iw_sc_static_hmc_pages_allocated( | |
3778 | struct i40iw_sc_cqp *cqp, | |
3779 | u64 scratch, | |
3780 | u8 hmc_fn_id, | |
3781 | bool post_sq, | |
3782 | bool poll_registers) | |
3783 | { | |
3784 | u64 header; | |
3785 | u64 *wqe; | |
3786 | u32 tail, val, error; | |
3787 | enum i40iw_status_code ret_code = 0; | |
3788 | ||
3789 | wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); | |
3790 | if (!wqe) | |
3791 | return I40IW_ERR_RING_FULL; | |
3792 | set_64bit_val(wqe, | |
3793 | 16, | |
3794 | LS_64(hmc_fn_id, I40IW_SHMC_PAGE_ALLOCATED_HMC_FN_ID)); | |
3795 | ||
3796 | header = LS_64(I40IW_CQP_OP_SHMC_PAGES_ALLOCATED, I40IW_CQPSQ_OPCODE) | | |
3797 | LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); | |
3798 | ||
3799 | i40iw_insert_wqe_hdr(wqe, header); | |
3800 | ||
3801 | i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "SHMC_PAGES_ALLOCATED WQE", | |
3802 | wqe, I40IW_CQP_WQE_SIZE * 8); | |
3803 | i40iw_get_cqp_reg_info(cqp, &val, &tail, &error); | |
3804 | if (error) { | |
3805 | ret_code = I40IW_ERR_CQP_COMPL_ERROR; | |
3806 | return ret_code; | |
3807 | } | |
3808 | if (post_sq) { | |
3809 | i40iw_sc_cqp_post_sq(cqp); | |
3810 | if (poll_registers) | |
3811 | /* check for cqp sq tail update */ | |
3812 | ret_code = i40iw_cqp_poll_registers(cqp, tail, 1000); | |
3813 | else | |
3814 | ret_code = i40iw_sc_poll_for_cqp_op_done(cqp, | |
3815 | I40IW_CQP_OP_SHMC_PAGES_ALLOCATED, | |
3816 | NULL); | |
3817 | } | |
3818 | ||
3819 | return ret_code; | |
3820 | } | |
3821 | ||
3822 | /** | |
3823 | * i40iw_ring_full - check if cqp ring is full | |
3824 | * @cqp: struct for cqp hw | |
3825 | */ | |
3826 | static bool i40iw_ring_full(struct i40iw_sc_cqp *cqp) | |
3827 | { | |
3828 | return I40IW_RING_FULL_ERR(cqp->sq_ring); | |
3829 | } | |
3830 | ||
fa415379 IM |
3831 | /** |
3832 | * i40iw_est_sd - returns approximate number of SDs for HMC | |
3833 | * @dev: sc device struct | |
3834 | * @hmc_info: hmc structure, size and count for HMC objects | |
3835 | */ | |
3836 | static u64 i40iw_est_sd(struct i40iw_sc_dev *dev, struct i40iw_hmc_info *hmc_info) | |
3837 | { | |
3838 | int i; | |
3839 | u64 size = 0; | |
3840 | u64 sd; | |
3841 | ||
3842 | for (i = I40IW_HMC_IW_QP; i < I40IW_HMC_IW_PBLE; i++) | |
3843 | size += hmc_info->hmc_obj[i].cnt * hmc_info->hmc_obj[i].size; | |
3844 | ||
3845 | if (dev->is_pf) | |
3846 | size += hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt * hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].size; | |
3847 | ||
3848 | if (size & 0x1FFFFF) | |
3849 | sd = (size >> 21) + 1; /* add 1 for remainder */ | |
3850 | else | |
3851 | sd = size >> 21; | |
3852 | ||
3853 | if (!dev->is_pf) { | |
3854 | /* 2MB alignment for VF PBLE HMC */ | |
3855 | size = hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt * hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].size; | |
3856 | if (size & 0x1FFFFF) | |
3857 | sd += (size >> 21) + 1; /* add 1 for remainder */ | |
3858 | else | |
3859 | sd += size >> 21; | |
3860 | } | |
3861 | ||
3862 | return sd; | |
3863 | } | |
3864 | ||
86dbcd0f FL |
3865 | /** |
3866 | * i40iw_config_fpm_values - configure HMC objects | |
3867 | * @dev: sc device struct | |
3868 | * @qp_count: desired qp count | |
3869 | */ | |
3870 | enum i40iw_status_code i40iw_config_fpm_values(struct i40iw_sc_dev *dev, u32 qp_count) | |
3871 | { | |
3872 | struct i40iw_virt_mem virt_mem; | |
3873 | u32 i, mem_size; | |
3874 | u32 qpwantedoriginal, qpwanted, mrwanted, pblewanted; | |
3875 | u32 powerof2; | |
fa415379 | 3876 | u64 sd_needed; |
86dbcd0f FL |
3877 | u32 loop_count = 0; |
3878 | ||
3879 | struct i40iw_hmc_info *hmc_info; | |
3880 | struct i40iw_hmc_fpm_misc *hmc_fpm_misc; | |
3881 | enum i40iw_status_code ret_code = 0; | |
3882 | ||
3883 | hmc_info = dev->hmc_info; | |
3884 | hmc_fpm_misc = &dev->hmc_fpm_misc; | |
3885 | ||
3886 | ret_code = i40iw_sc_init_iw_hmc(dev, dev->hmc_fn_id); | |
3887 | if (ret_code) { | |
3888 | i40iw_debug(dev, I40IW_DEBUG_HMC, | |
3889 | "i40iw_sc_init_iw_hmc returned error_code = %d\n", | |
3890 | ret_code); | |
3891 | return ret_code; | |
3892 | } | |
3893 | ||
fa415379 | 3894 | for (i = I40IW_HMC_IW_QP; i < I40IW_HMC_IW_MAX; i++) |
86dbcd0f | 3895 | hmc_info->hmc_obj[i].cnt = hmc_info->hmc_obj[i].max_cnt; |
fa415379 | 3896 | sd_needed = i40iw_est_sd(dev, hmc_info); |
86dbcd0f FL |
3897 | i40iw_debug(dev, I40IW_DEBUG_HMC, |
3898 | "%s: FW initial max sd_count[%08lld] first_sd_index[%04d]\n", | |
3899 | __func__, sd_needed, hmc_info->first_sd_index); | |
3900 | i40iw_debug(dev, I40IW_DEBUG_HMC, | |
fa415379 IM |
3901 | "%s: sd count %d where max sd is %d\n", |
3902 | __func__, hmc_info->sd_table.sd_cnt, | |
86dbcd0f FL |
3903 | hmc_fpm_misc->max_sds); |
3904 | ||
3905 | qpwanted = min(qp_count, hmc_info->hmc_obj[I40IW_HMC_IW_QP].max_cnt); | |
3906 | qpwantedoriginal = qpwanted; | |
3907 | mrwanted = hmc_info->hmc_obj[I40IW_HMC_IW_MR].max_cnt; | |
3908 | pblewanted = hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].max_cnt; | |
3909 | ||
3910 | i40iw_debug(dev, I40IW_DEBUG_HMC, | |
3911 | "req_qp=%d max_sd=%d, max_qp = %d, max_cq=%d, max_mr=%d, max_pble=%d\n", | |
3912 | qp_count, hmc_fpm_misc->max_sds, | |
3913 | hmc_info->hmc_obj[I40IW_HMC_IW_QP].max_cnt, | |
3914 | hmc_info->hmc_obj[I40IW_HMC_IW_CQ].max_cnt, | |
3915 | hmc_info->hmc_obj[I40IW_HMC_IW_MR].max_cnt, | |
3916 | hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].max_cnt); | |
3917 | ||
3918 | do { | |
3919 | ++loop_count; | |
3920 | hmc_info->hmc_obj[I40IW_HMC_IW_QP].cnt = qpwanted; | |
3921 | hmc_info->hmc_obj[I40IW_HMC_IW_CQ].cnt = | |
3922 | min(2 * qpwanted, hmc_info->hmc_obj[I40IW_HMC_IW_CQ].cnt); | |
3923 | hmc_info->hmc_obj[I40IW_HMC_IW_SRQ].cnt = 0x00; /* Reserved */ | |
3924 | hmc_info->hmc_obj[I40IW_HMC_IW_HTE].cnt = | |
3925 | qpwanted * hmc_fpm_misc->ht_multiplier; | |
3926 | hmc_info->hmc_obj[I40IW_HMC_IW_ARP].cnt = | |
3927 | hmc_info->hmc_obj[I40IW_HMC_IW_ARP].max_cnt; | |
3928 | hmc_info->hmc_obj[I40IW_HMC_IW_APBVT_ENTRY].cnt = 1; | |
3929 | hmc_info->hmc_obj[I40IW_HMC_IW_MR].cnt = mrwanted; | |
3930 | ||
3931 | hmc_info->hmc_obj[I40IW_HMC_IW_XF].cnt = I40IW_MAX_WQ_ENTRIES * qpwanted; | |
3932 | hmc_info->hmc_obj[I40IW_HMC_IW_Q1].cnt = 4 * I40IW_MAX_IRD_SIZE * qpwanted; | |
3933 | hmc_info->hmc_obj[I40IW_HMC_IW_XFFL].cnt = | |
3934 | hmc_info->hmc_obj[I40IW_HMC_IW_XF].cnt / hmc_fpm_misc->xf_block_size; | |
3935 | hmc_info->hmc_obj[I40IW_HMC_IW_Q1FL].cnt = | |
3936 | hmc_info->hmc_obj[I40IW_HMC_IW_Q1].cnt / hmc_fpm_misc->q1_block_size; | |
3937 | hmc_info->hmc_obj[I40IW_HMC_IW_TIMER].cnt = | |
3938 | ((qpwanted) / 512 + 1) * hmc_fpm_misc->timer_bucket; | |
3939 | hmc_info->hmc_obj[I40IW_HMC_IW_FSIMC].cnt = 0x00; | |
3940 | hmc_info->hmc_obj[I40IW_HMC_IW_FSIAV].cnt = 0x00; | |
3941 | hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt = pblewanted; | |
3942 | ||
3943 | /* How much memory is needed for all the objects. */ | |
fa415379 | 3944 | sd_needed = i40iw_est_sd(dev, hmc_info); |
86dbcd0f FL |
3945 | if ((loop_count > 1000) || |
3946 | ((!(loop_count % 10)) && | |
3947 | (qpwanted > qpwantedoriginal * 2 / 3))) { | |
3948 | if (qpwanted > FPM_MULTIPLIER) { | |
3949 | qpwanted -= FPM_MULTIPLIER; | |
3950 | powerof2 = 1; | |
3951 | while (powerof2 < qpwanted) | |
3952 | powerof2 *= 2; | |
3953 | powerof2 /= 2; | |
3954 | qpwanted = powerof2; | |
3955 | } else { | |
3956 | qpwanted /= 2; | |
3957 | } | |
3958 | } | |
3959 | if (mrwanted > FPM_MULTIPLIER * 10) | |
3960 | mrwanted -= FPM_MULTIPLIER * 10; | |
3961 | if (pblewanted > FPM_MULTIPLIER * 1000) | |
3962 | pblewanted -= FPM_MULTIPLIER * 1000; | |
3963 | } while (sd_needed > hmc_fpm_misc->max_sds && loop_count < 2000); | |
3964 | ||
fa415379 | 3965 | sd_needed = i40iw_est_sd(dev, hmc_info); |
86dbcd0f FL |
3966 | |
3967 | i40iw_debug(dev, I40IW_DEBUG_HMC, | |
3968 | "loop_cnt=%d, sd_needed=%lld, qpcnt = %d, cqcnt=%d, mrcnt=%d, pblecnt=%d\n", | |
3969 | loop_count, sd_needed, | |
3970 | hmc_info->hmc_obj[I40IW_HMC_IW_QP].cnt, | |
3971 | hmc_info->hmc_obj[I40IW_HMC_IW_CQ].cnt, | |
3972 | hmc_info->hmc_obj[I40IW_HMC_IW_MR].cnt, | |
3973 | hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt); | |
3974 | ||
3975 | ret_code = i40iw_sc_configure_iw_fpm(dev, dev->hmc_fn_id); | |
3976 | if (ret_code) { | |
3977 | i40iw_debug(dev, I40IW_DEBUG_HMC, | |
3978 | "configure_iw_fpm returned error_code[x%08X]\n", | |
3979 | i40iw_rd32(dev->hw, dev->is_pf ? I40E_PFPE_CQPERRCODES : I40E_VFPE_CQPERRCODES1)); | |
3980 | return ret_code; | |
3981 | } | |
3982 | ||
86dbcd0f FL |
3983 | mem_size = sizeof(struct i40iw_hmc_sd_entry) * |
3984 | (hmc_info->sd_table.sd_cnt + hmc_info->first_sd_index + 1); | |
3985 | ret_code = i40iw_allocate_virt_mem(dev->hw, &virt_mem, mem_size); | |
3986 | if (ret_code) { | |
3987 | i40iw_debug(dev, I40IW_DEBUG_HMC, | |
3988 | "%s: failed to allocate memory for sd_entry buffer\n", | |
3989 | __func__); | |
3990 | return ret_code; | |
3991 | } | |
3992 | hmc_info->sd_table.sd_entry = virt_mem.va; | |
3993 | ||
3994 | return ret_code; | |
3995 | } | |
3996 | ||
3997 | /** | |
3998 | * i40iw_exec_cqp_cmd - execute cqp cmd when wqe are available | |
3999 | * @dev: rdma device | |
4000 | * @pcmdinfo: cqp command info | |
4001 | */ | |
4002 | static enum i40iw_status_code i40iw_exec_cqp_cmd(struct i40iw_sc_dev *dev, | |
4003 | struct cqp_commands_info *pcmdinfo) | |
4004 | { | |
4005 | enum i40iw_status_code status; | |
4006 | struct i40iw_dma_mem values_mem; | |
4007 | ||
4008 | dev->cqp_cmd_stats[pcmdinfo->cqp_cmd]++; | |
4009 | switch (pcmdinfo->cqp_cmd) { | |
4010 | case OP_DELETE_LOCAL_MAC_IPADDR_ENTRY: | |
4011 | status = i40iw_sc_del_local_mac_ipaddr_entry( | |
4012 | pcmdinfo->in.u.del_local_mac_ipaddr_entry.cqp, | |
4013 | pcmdinfo->in.u.del_local_mac_ipaddr_entry.scratch, | |
4014 | pcmdinfo->in.u.del_local_mac_ipaddr_entry.entry_idx, | |
4015 | pcmdinfo->in.u.del_local_mac_ipaddr_entry.ignore_ref_count, | |
4016 | pcmdinfo->post_sq); | |
4017 | break; | |
4018 | case OP_CEQ_DESTROY: | |
4019 | status = i40iw_sc_ceq_destroy(pcmdinfo->in.u.ceq_destroy.ceq, | |
4020 | pcmdinfo->in.u.ceq_destroy.scratch, | |
4021 | pcmdinfo->post_sq); | |
4022 | break; | |
4023 | case OP_AEQ_DESTROY: | |
4024 | status = i40iw_sc_aeq_destroy(pcmdinfo->in.u.aeq_destroy.aeq, | |
4025 | pcmdinfo->in.u.aeq_destroy.scratch, | |
4026 | pcmdinfo->post_sq); | |
4027 | ||
4028 | break; | |
4029 | case OP_DELETE_ARP_CACHE_ENTRY: | |
4030 | status = i40iw_sc_del_arp_cache_entry( | |
4031 | pcmdinfo->in.u.del_arp_cache_entry.cqp, | |
4032 | pcmdinfo->in.u.del_arp_cache_entry.scratch, | |
4033 | pcmdinfo->in.u.del_arp_cache_entry.arp_index, | |
4034 | pcmdinfo->post_sq); | |
4035 | break; | |
4036 | case OP_MANAGE_APBVT_ENTRY: | |
4037 | status = i40iw_sc_manage_apbvt_entry( | |
4038 | pcmdinfo->in.u.manage_apbvt_entry.cqp, | |
4039 | &pcmdinfo->in.u.manage_apbvt_entry.info, | |
4040 | pcmdinfo->in.u.manage_apbvt_entry.scratch, | |
4041 | pcmdinfo->post_sq); | |
4042 | break; | |
4043 | case OP_CEQ_CREATE: | |
4044 | status = i40iw_sc_ceq_create(pcmdinfo->in.u.ceq_create.ceq, | |
4045 | pcmdinfo->in.u.ceq_create.scratch, | |
4046 | pcmdinfo->post_sq); | |
4047 | break; | |
4048 | case OP_AEQ_CREATE: | |
4049 | status = i40iw_sc_aeq_create(pcmdinfo->in.u.aeq_create.aeq, | |
4050 | pcmdinfo->in.u.aeq_create.scratch, | |
4051 | pcmdinfo->post_sq); | |
4052 | break; | |
4053 | case OP_ALLOC_LOCAL_MAC_IPADDR_ENTRY: | |
4054 | status = i40iw_sc_alloc_local_mac_ipaddr_entry( | |
4055 | pcmdinfo->in.u.alloc_local_mac_ipaddr_entry.cqp, | |
4056 | pcmdinfo->in.u.alloc_local_mac_ipaddr_entry.scratch, | |
4057 | pcmdinfo->post_sq); | |
4058 | break; | |
4059 | case OP_ADD_LOCAL_MAC_IPADDR_ENTRY: | |
4060 | status = i40iw_sc_add_local_mac_ipaddr_entry( | |
4061 | pcmdinfo->in.u.add_local_mac_ipaddr_entry.cqp, | |
4062 | &pcmdinfo->in.u.add_local_mac_ipaddr_entry.info, | |
4063 | pcmdinfo->in.u.add_local_mac_ipaddr_entry.scratch, | |
4064 | pcmdinfo->post_sq); | |
4065 | break; | |
4066 | case OP_MANAGE_QHASH_TABLE_ENTRY: | |
4067 | status = i40iw_sc_manage_qhash_table_entry( | |
4068 | pcmdinfo->in.u.manage_qhash_table_entry.cqp, | |
4069 | &pcmdinfo->in.u.manage_qhash_table_entry.info, | |
4070 | pcmdinfo->in.u.manage_qhash_table_entry.scratch, | |
4071 | pcmdinfo->post_sq); | |
4072 | ||
4073 | break; | |
4074 | case OP_QP_MODIFY: | |
4075 | status = i40iw_sc_qp_modify( | |
4076 | pcmdinfo->in.u.qp_modify.qp, | |
4077 | &pcmdinfo->in.u.qp_modify.info, | |
4078 | pcmdinfo->in.u.qp_modify.scratch, | |
4079 | pcmdinfo->post_sq); | |
4080 | ||
4081 | break; | |
4082 | case OP_QP_UPLOAD_CONTEXT: | |
4083 | status = i40iw_sc_qp_upload_context( | |
4084 | pcmdinfo->in.u.qp_upload_context.dev, | |
4085 | &pcmdinfo->in.u.qp_upload_context.info, | |
4086 | pcmdinfo->in.u.qp_upload_context.scratch, | |
4087 | pcmdinfo->post_sq); | |
4088 | ||
4089 | break; | |
4090 | case OP_CQ_CREATE: | |
4091 | status = i40iw_sc_cq_create( | |
4092 | pcmdinfo->in.u.cq_create.cq, | |
4093 | pcmdinfo->in.u.cq_create.scratch, | |
4094 | pcmdinfo->in.u.cq_create.check_overflow, | |
4095 | pcmdinfo->post_sq); | |
4096 | break; | |
4097 | case OP_CQ_DESTROY: | |
4098 | status = i40iw_sc_cq_destroy( | |
4099 | pcmdinfo->in.u.cq_destroy.cq, | |
4100 | pcmdinfo->in.u.cq_destroy.scratch, | |
4101 | pcmdinfo->post_sq); | |
4102 | ||
4103 | break; | |
4104 | case OP_QP_CREATE: | |
4105 | status = i40iw_sc_qp_create( | |
4106 | pcmdinfo->in.u.qp_create.qp, | |
4107 | &pcmdinfo->in.u.qp_create.info, | |
4108 | pcmdinfo->in.u.qp_create.scratch, | |
4109 | pcmdinfo->post_sq); | |
4110 | break; | |
4111 | case OP_QP_DESTROY: | |
4112 | status = i40iw_sc_qp_destroy( | |
4113 | pcmdinfo->in.u.qp_destroy.qp, | |
4114 | pcmdinfo->in.u.qp_destroy.scratch, | |
4115 | pcmdinfo->in.u.qp_destroy.remove_hash_idx, | |
4116 | pcmdinfo->in.u.qp_destroy. | |
4117 | ignore_mw_bnd, | |
4118 | pcmdinfo->post_sq); | |
4119 | ||
4120 | break; | |
4121 | case OP_ALLOC_STAG: | |
4122 | status = i40iw_sc_alloc_stag( | |
4123 | pcmdinfo->in.u.alloc_stag.dev, | |
4124 | &pcmdinfo->in.u.alloc_stag.info, | |
4125 | pcmdinfo->in.u.alloc_stag.scratch, | |
4126 | pcmdinfo->post_sq); | |
4127 | break; | |
4128 | case OP_MR_REG_NON_SHARED: | |
4129 | status = i40iw_sc_mr_reg_non_shared( | |
4130 | pcmdinfo->in.u.mr_reg_non_shared.dev, | |
4131 | &pcmdinfo->in.u.mr_reg_non_shared.info, | |
4132 | pcmdinfo->in.u.mr_reg_non_shared.scratch, | |
4133 | pcmdinfo->post_sq); | |
4134 | ||
4135 | break; | |
4136 | case OP_DEALLOC_STAG: | |
4137 | status = i40iw_sc_dealloc_stag( | |
4138 | pcmdinfo->in.u.dealloc_stag.dev, | |
4139 | &pcmdinfo->in.u.dealloc_stag.info, | |
4140 | pcmdinfo->in.u.dealloc_stag.scratch, | |
4141 | pcmdinfo->post_sq); | |
4142 | ||
4143 | break; | |
4144 | case OP_MW_ALLOC: | |
4145 | status = i40iw_sc_mw_alloc( | |
4146 | pcmdinfo->in.u.mw_alloc.dev, | |
4147 | pcmdinfo->in.u.mw_alloc.scratch, | |
4148 | pcmdinfo->in.u.mw_alloc.mw_stag_index, | |
4149 | pcmdinfo->in.u.mw_alloc.pd_id, | |
4150 | pcmdinfo->post_sq); | |
4151 | ||
4152 | break; | |
4153 | case OP_QP_FLUSH_WQES: | |
4154 | status = i40iw_sc_qp_flush_wqes( | |
4155 | pcmdinfo->in.u.qp_flush_wqes.qp, | |
4156 | &pcmdinfo->in.u.qp_flush_wqes.info, | |
4157 | pcmdinfo->in.u.qp_flush_wqes. | |
4158 | scratch, pcmdinfo->post_sq); | |
4159 | break; | |
4160 | case OP_ADD_ARP_CACHE_ENTRY: | |
4161 | status = i40iw_sc_add_arp_cache_entry( | |
4162 | pcmdinfo->in.u.add_arp_cache_entry.cqp, | |
4163 | &pcmdinfo->in.u.add_arp_cache_entry.info, | |
4164 | pcmdinfo->in.u.add_arp_cache_entry.scratch, | |
4165 | pcmdinfo->post_sq); | |
4166 | break; | |
4167 | case OP_MANAGE_PUSH_PAGE: | |
4168 | status = i40iw_sc_manage_push_page( | |
4169 | pcmdinfo->in.u.manage_push_page.cqp, | |
4170 | &pcmdinfo->in.u.manage_push_page.info, | |
4171 | pcmdinfo->in.u.manage_push_page.scratch, | |
4172 | pcmdinfo->post_sq); | |
4173 | break; | |
4174 | case OP_UPDATE_PE_SDS: | |
4175 | /* case I40IW_CQP_OP_UPDATE_PE_SDS */ | |
4176 | status = i40iw_update_pe_sds( | |
4177 | pcmdinfo->in.u.update_pe_sds.dev, | |
4178 | &pcmdinfo->in.u.update_pe_sds.info, | |
4179 | pcmdinfo->in.u.update_pe_sds. | |
4180 | scratch); | |
4181 | ||
4182 | break; | |
4183 | case OP_MANAGE_HMC_PM_FUNC_TABLE: | |
4184 | status = i40iw_sc_manage_hmc_pm_func_table( | |
4185 | pcmdinfo->in.u.manage_hmc_pm.dev->cqp, | |
4186 | pcmdinfo->in.u.manage_hmc_pm.scratch, | |
4187 | (u8)pcmdinfo->in.u.manage_hmc_pm.info.vf_id, | |
4188 | pcmdinfo->in.u.manage_hmc_pm.info.free_fcn, | |
4189 | true); | |
4190 | break; | |
4191 | case OP_SUSPEND: | |
4192 | status = i40iw_sc_suspend_qp( | |
4193 | pcmdinfo->in.u.suspend_resume.cqp, | |
4194 | pcmdinfo->in.u.suspend_resume.qp, | |
4195 | pcmdinfo->in.u.suspend_resume.scratch); | |
4196 | break; | |
4197 | case OP_RESUME: | |
4198 | status = i40iw_sc_resume_qp( | |
4199 | pcmdinfo->in.u.suspend_resume.cqp, | |
4200 | pcmdinfo->in.u.suspend_resume.qp, | |
4201 | pcmdinfo->in.u.suspend_resume.scratch); | |
4202 | break; | |
4203 | case OP_MANAGE_VF_PBLE_BP: | |
4204 | status = i40iw_manage_vf_pble_bp( | |
4205 | pcmdinfo->in.u.manage_vf_pble_bp.cqp, | |
4206 | &pcmdinfo->in.u.manage_vf_pble_bp.info, | |
4207 | pcmdinfo->in.u.manage_vf_pble_bp.scratch, true); | |
4208 | break; | |
4209 | case OP_QUERY_FPM_VALUES: | |
4210 | values_mem.pa = pcmdinfo->in.u.query_fpm_values.fpm_values_pa; | |
4211 | values_mem.va = pcmdinfo->in.u.query_fpm_values.fpm_values_va; | |
4212 | status = i40iw_sc_query_fpm_values( | |
4213 | pcmdinfo->in.u.query_fpm_values.cqp, | |
4214 | pcmdinfo->in.u.query_fpm_values.scratch, | |
4215 | pcmdinfo->in.u.query_fpm_values.hmc_fn_id, | |
4216 | &values_mem, true, I40IW_CQP_WAIT_EVENT); | |
4217 | break; | |
4218 | case OP_COMMIT_FPM_VALUES: | |
4219 | values_mem.pa = pcmdinfo->in.u.commit_fpm_values.fpm_values_pa; | |
4220 | values_mem.va = pcmdinfo->in.u.commit_fpm_values.fpm_values_va; | |
4221 | status = i40iw_sc_commit_fpm_values( | |
4222 | pcmdinfo->in.u.commit_fpm_values.cqp, | |
4223 | pcmdinfo->in.u.commit_fpm_values.scratch, | |
4224 | pcmdinfo->in.u.commit_fpm_values.hmc_fn_id, | |
4225 | &values_mem, | |
4226 | true, | |
4227 | I40IW_CQP_WAIT_EVENT); | |
4228 | break; | |
4229 | default: | |
4230 | status = I40IW_NOT_SUPPORTED; | |
4231 | break; | |
4232 | } | |
4233 | ||
4234 | return status; | |
4235 | } | |
4236 | ||
4237 | /** | |
4238 | * i40iw_process_cqp_cmd - process all cqp commands | |
4239 | * @dev: sc device struct | |
4240 | * @pcmdinfo: cqp command info | |
4241 | */ | |
4242 | enum i40iw_status_code i40iw_process_cqp_cmd(struct i40iw_sc_dev *dev, | |
4243 | struct cqp_commands_info *pcmdinfo) | |
4244 | { | |
4245 | enum i40iw_status_code status = 0; | |
0fc2dc58 | 4246 | unsigned long flags; |
86dbcd0f FL |
4247 | |
4248 | spin_lock_irqsave(&dev->cqp_lock, flags); | |
4249 | if (list_empty(&dev->cqp_cmd_head) && !i40iw_ring_full(dev->cqp)) | |
4250 | status = i40iw_exec_cqp_cmd(dev, pcmdinfo); | |
4251 | else | |
4252 | list_add_tail(&pcmdinfo->cqp_cmd_entry, &dev->cqp_cmd_head); | |
4253 | spin_unlock_irqrestore(&dev->cqp_lock, flags); | |
4254 | return status; | |
4255 | } | |
4256 | ||
4257 | /** | |
4258 | * i40iw_process_bh - called from tasklet for cqp list | |
4259 | * @dev: sc device struct | |
4260 | */ | |
4261 | enum i40iw_status_code i40iw_process_bh(struct i40iw_sc_dev *dev) | |
4262 | { | |
4263 | enum i40iw_status_code status = 0; | |
4264 | struct cqp_commands_info *pcmdinfo; | |
0fc2dc58 | 4265 | unsigned long flags; |
86dbcd0f FL |
4266 | |
4267 | spin_lock_irqsave(&dev->cqp_lock, flags); | |
4268 | while (!list_empty(&dev->cqp_cmd_head) && !i40iw_ring_full(dev->cqp)) { | |
4269 | pcmdinfo = (struct cqp_commands_info *)i40iw_remove_head(&dev->cqp_cmd_head); | |
4270 | ||
4271 | status = i40iw_exec_cqp_cmd(dev, pcmdinfo); | |
4272 | if (status) | |
4273 | break; | |
4274 | } | |
4275 | spin_unlock_irqrestore(&dev->cqp_lock, flags); | |
4276 | return status; | |
4277 | } | |
4278 | ||
4279 | /** | |
4280 | * i40iw_iwarp_opcode - determine if incoming is rdma layer | |
4281 | * @info: aeq info for the packet | |
4282 | * @pkt: packet for error | |
4283 | */ | |
4284 | static u32 i40iw_iwarp_opcode(struct i40iw_aeqe_info *info, u8 *pkt) | |
4285 | { | |
20c61f7e | 4286 | __be16 *mpa; |
86dbcd0f FL |
4287 | u32 opcode = 0xffffffff; |
4288 | ||
4289 | if (info->q2_data_written) { | |
20c61f7e | 4290 | mpa = (__be16 *)pkt; |
86dbcd0f FL |
4291 | opcode = ntohs(mpa[1]) & 0xf; |
4292 | } | |
4293 | return opcode; | |
4294 | } | |
4295 | ||
4296 | /** | |
4297 | * i40iw_locate_mpa - return pointer to mpa in the pkt | |
4298 | * @pkt: packet with data | |
4299 | */ | |
4300 | static u8 *i40iw_locate_mpa(u8 *pkt) | |
4301 | { | |
4302 | /* skip over ethernet header */ | |
4303 | pkt += I40IW_MAC_HLEN; | |
4304 | ||
4305 | /* Skip over IP and TCP headers */ | |
4306 | pkt += 4 * (pkt[0] & 0x0f); | |
4307 | pkt += 4 * ((pkt[12] >> 4) & 0x0f); | |
4308 | return pkt; | |
4309 | } | |
4310 | ||
4311 | /** | |
4312 | * i40iw_setup_termhdr - termhdr for terminate pkt | |
4313 | * @qp: sc qp ptr for pkt | |
4314 | * @hdr: term hdr | |
4315 | * @opcode: flush opcode for termhdr | |
4316 | * @layer_etype: error layer + error type | |
4317 | * @err: error cod ein the header | |
4318 | */ | |
4319 | static void i40iw_setup_termhdr(struct i40iw_sc_qp *qp, | |
4320 | struct i40iw_terminate_hdr *hdr, | |
4321 | enum i40iw_flush_opcode opcode, | |
4322 | u8 layer_etype, | |
4323 | u8 err) | |
4324 | { | |
4325 | qp->flush_code = opcode; | |
4326 | hdr->layer_etype = layer_etype; | |
4327 | hdr->error_code = err; | |
4328 | } | |
4329 | ||
4330 | /** | |
4331 | * i40iw_bld_terminate_hdr - build terminate message header | |
4332 | * @qp: qp associated with received terminate AE | |
4333 | * @info: the struct contiaing AE information | |
4334 | */ | |
4335 | static int i40iw_bld_terminate_hdr(struct i40iw_sc_qp *qp, | |
4336 | struct i40iw_aeqe_info *info) | |
4337 | { | |
4338 | u8 *pkt = qp->q2_buf + Q2_BAD_FRAME_OFFSET; | |
4339 | u16 ddp_seg_len; | |
4340 | int copy_len = 0; | |
4341 | u8 is_tagged = 0; | |
86dbcd0f FL |
4342 | u32 opcode; |
4343 | struct i40iw_terminate_hdr *termhdr; | |
4344 | ||
4345 | termhdr = (struct i40iw_terminate_hdr *)qp->q2_buf; | |
4346 | memset(termhdr, 0, Q2_BAD_FRAME_OFFSET); | |
4347 | ||
4348 | if (info->q2_data_written) { | |
4349 | /* Use data from offending packet to fill in ddp & rdma hdrs */ | |
4350 | pkt = i40iw_locate_mpa(pkt); | |
20c61f7e | 4351 | ddp_seg_len = ntohs(*(__be16 *)pkt); |
86dbcd0f FL |
4352 | if (ddp_seg_len) { |
4353 | copy_len = 2; | |
4354 | termhdr->hdrct = DDP_LEN_FLAG; | |
4355 | if (pkt[2] & 0x80) { | |
4356 | is_tagged = 1; | |
4357 | if (ddp_seg_len >= TERM_DDP_LEN_TAGGED) { | |
4358 | copy_len += TERM_DDP_LEN_TAGGED; | |
4359 | termhdr->hdrct |= DDP_HDR_FLAG; | |
4360 | } | |
4361 | } else { | |
4362 | if (ddp_seg_len >= TERM_DDP_LEN_UNTAGGED) { | |
4363 | copy_len += TERM_DDP_LEN_UNTAGGED; | |
4364 | termhdr->hdrct |= DDP_HDR_FLAG; | |
4365 | } | |
4366 | ||
4367 | if (ddp_seg_len >= (TERM_DDP_LEN_UNTAGGED + TERM_RDMA_LEN)) { | |
4368 | if ((pkt[3] & RDMA_OPCODE_MASK) == RDMA_READ_REQ_OPCODE) { | |
4369 | copy_len += TERM_RDMA_LEN; | |
4370 | termhdr->hdrct |= RDMA_HDR_FLAG; | |
4371 | } | |
4372 | } | |
4373 | } | |
4374 | } | |
4375 | } | |
4376 | ||
4377 | opcode = i40iw_iwarp_opcode(info, pkt); | |
4378 | ||
4379 | switch (info->ae_id) { | |
4380 | case I40IW_AE_AMP_UNALLOCATED_STAG: | |
4381 | qp->eventtype = TERM_EVENT_QP_ACCESS_ERR; | |
4382 | if (opcode == I40IW_OP_TYPE_RDMA_WRITE) | |
4383 | i40iw_setup_termhdr(qp, termhdr, FLUSH_PROT_ERR, | |
4384 | (LAYER_DDP << 4) | DDP_TAGGED_BUFFER, DDP_TAGGED_INV_STAG); | |
4385 | else | |
4386 | i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR, | |
4387 | (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_INV_STAG); | |
4388 | break; | |
4389 | case I40IW_AE_AMP_BOUNDS_VIOLATION: | |
4390 | qp->eventtype = TERM_EVENT_QP_ACCESS_ERR; | |
4391 | if (info->q2_data_written) | |
4392 | i40iw_setup_termhdr(qp, termhdr, FLUSH_PROT_ERR, | |
4393 | (LAYER_DDP << 4) | DDP_TAGGED_BUFFER, DDP_TAGGED_BOUNDS); | |
4394 | else | |
4395 | i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR, | |
4396 | (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_INV_BOUNDS); | |
4397 | break; | |
4398 | case I40IW_AE_AMP_BAD_PD: | |
4399 | switch (opcode) { | |
4400 | case I40IW_OP_TYPE_RDMA_WRITE: | |
4401 | i40iw_setup_termhdr(qp, termhdr, FLUSH_PROT_ERR, | |
4402 | (LAYER_DDP << 4) | DDP_TAGGED_BUFFER, DDP_TAGGED_UNASSOC_STAG); | |
4403 | break; | |
4404 | case I40IW_OP_TYPE_SEND_INV: | |
4405 | case I40IW_OP_TYPE_SEND_SOL_INV: | |
4406 | i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR, | |
4407 | (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_CANT_INV_STAG); | |
4408 | break; | |
4409 | default: | |
4410 | i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR, | |
4411 | (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_UNASSOC_STAG); | |
4412 | } | |
4413 | break; | |
4414 | case I40IW_AE_AMP_INVALID_STAG: | |
4415 | qp->eventtype = TERM_EVENT_QP_ACCESS_ERR; | |
4416 | i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR, | |
4417 | (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_INV_STAG); | |
4418 | break; | |
4419 | case I40IW_AE_AMP_BAD_QP: | |
4420 | i40iw_setup_termhdr(qp, termhdr, FLUSH_LOC_QP_OP_ERR, | |
4421 | (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_QN); | |
4422 | break; | |
4423 | case I40IW_AE_AMP_BAD_STAG_KEY: | |
4424 | case I40IW_AE_AMP_BAD_STAG_INDEX: | |
4425 | qp->eventtype = TERM_EVENT_QP_ACCESS_ERR; | |
4426 | switch (opcode) { | |
4427 | case I40IW_OP_TYPE_SEND_INV: | |
4428 | case I40IW_OP_TYPE_SEND_SOL_INV: | |
4429 | i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_OP_ERR, | |
4430 | (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, RDMAP_CANT_INV_STAG); | |
4431 | break; | |
4432 | default: | |
4433 | i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR, | |
4434 | (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, RDMAP_INV_STAG); | |
4435 | } | |
4436 | break; | |
4437 | case I40IW_AE_AMP_RIGHTS_VIOLATION: | |
4438 | case I40IW_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS: | |
4439 | case I40IW_AE_PRIV_OPERATION_DENIED: | |
4440 | qp->eventtype = TERM_EVENT_QP_ACCESS_ERR; | |
4441 | i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR, | |
4442 | (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_ACCESS); | |
4443 | break; | |
4444 | case I40IW_AE_AMP_TO_WRAP: | |
4445 | qp->eventtype = TERM_EVENT_QP_ACCESS_ERR; | |
4446 | i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR, | |
4447 | (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_TO_WRAP); | |
4448 | break; | |
86dbcd0f FL |
4449 | case I40IW_AE_LLP_RECEIVED_MPA_CRC_ERROR: |
4450 | i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR, | |
4451 | (LAYER_MPA << 4) | DDP_LLP, MPA_CRC); | |
4452 | break; | |
4453 | case I40IW_AE_LLP_SEGMENT_TOO_LARGE: | |
4454 | case I40IW_AE_LLP_SEGMENT_TOO_SMALL: | |
4455 | i40iw_setup_termhdr(qp, termhdr, FLUSH_LOC_LEN_ERR, | |
4456 | (LAYER_DDP << 4) | DDP_CATASTROPHIC, DDP_CATASTROPHIC_LOCAL); | |
4457 | break; | |
4458 | case I40IW_AE_LCE_QP_CATASTROPHIC: | |
4459 | case I40IW_AE_DDP_NO_L_BIT: | |
4460 | i40iw_setup_termhdr(qp, termhdr, FLUSH_FATAL_ERR, | |
4461 | (LAYER_DDP << 4) | DDP_CATASTROPHIC, DDP_CATASTROPHIC_LOCAL); | |
4462 | break; | |
4463 | case I40IW_AE_DDP_INVALID_MSN_GAP_IN_MSN: | |
86dbcd0f FL |
4464 | i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR, |
4465 | (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_MSN_RANGE); | |
4466 | break; | |
4467 | case I40IW_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER: | |
4468 | qp->eventtype = TERM_EVENT_QP_ACCESS_ERR; | |
4469 | i40iw_setup_termhdr(qp, termhdr, FLUSH_LOC_LEN_ERR, | |
4470 | (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_TOO_LONG); | |
4471 | break; | |
4472 | case I40IW_AE_DDP_UBE_INVALID_DDP_VERSION: | |
4473 | if (is_tagged) | |
4474 | i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR, | |
4475 | (LAYER_DDP << 4) | DDP_TAGGED_BUFFER, DDP_TAGGED_INV_DDP_VER); | |
4476 | else | |
4477 | i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR, | |
4478 | (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_DDP_VER); | |
4479 | break; | |
4480 | case I40IW_AE_DDP_UBE_INVALID_MO: | |
4481 | i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR, | |
4482 | (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_MO); | |
4483 | break; | |
4484 | case I40IW_AE_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE: | |
4485 | i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_OP_ERR, | |
4486 | (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_MSN_NO_BUF); | |
4487 | break; | |
4488 | case I40IW_AE_DDP_UBE_INVALID_QN: | |
4489 | i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR, | |
4490 | (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_QN); | |
4491 | break; | |
4492 | case I40IW_AE_RDMAP_ROE_INVALID_RDMAP_VERSION: | |
4493 | i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR, | |
4494 | (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, RDMAP_INV_RDMAP_VER); | |
4495 | break; | |
4496 | case I40IW_AE_RDMAP_ROE_UNEXPECTED_OPCODE: | |
4497 | i40iw_setup_termhdr(qp, termhdr, FLUSH_LOC_QP_OP_ERR, | |
4498 | (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, RDMAP_UNEXPECTED_OP); | |
4499 | break; | |
4500 | default: | |
4501 | i40iw_setup_termhdr(qp, termhdr, FLUSH_FATAL_ERR, | |
4502 | (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, RDMAP_UNSPECIFIED); | |
4503 | break; | |
4504 | } | |
4505 | ||
4506 | if (copy_len) | |
4507 | memcpy(termhdr + 1, pkt, copy_len); | |
4508 | ||
86dbcd0f FL |
4509 | return sizeof(struct i40iw_terminate_hdr) + copy_len; |
4510 | } | |
4511 | ||
4512 | /** | |
4513 | * i40iw_terminate_send_fin() - Send fin for terminate message | |
4514 | * @qp: qp associated with received terminate AE | |
4515 | */ | |
4516 | void i40iw_terminate_send_fin(struct i40iw_sc_qp *qp) | |
4517 | { | |
4518 | /* Send the fin only */ | |
4519 | i40iw_term_modify_qp(qp, | |
4520 | I40IW_QP_STATE_TERMINATE, | |
4521 | I40IWQP_TERM_SEND_FIN_ONLY, | |
4522 | 0); | |
4523 | } | |
4524 | ||
4525 | /** | |
4526 | * i40iw_terminate_connection() - Bad AE and send terminate to remote QP | |
4527 | * @qp: qp associated with received terminate AE | |
4528 | * @info: the struct contiaing AE information | |
4529 | */ | |
4530 | void i40iw_terminate_connection(struct i40iw_sc_qp *qp, struct i40iw_aeqe_info *info) | |
4531 | { | |
4532 | u8 termlen = 0; | |
4533 | ||
4534 | if (qp->term_flags & I40IW_TERM_SENT) | |
4535 | return; /* Sanity check */ | |
4536 | ||
4537 | /* Eventtype can change from bld_terminate_hdr */ | |
4538 | qp->eventtype = TERM_EVENT_QP_FATAL; | |
4539 | termlen = i40iw_bld_terminate_hdr(qp, info); | |
4540 | i40iw_terminate_start_timer(qp); | |
4541 | qp->term_flags |= I40IW_TERM_SENT; | |
4542 | i40iw_term_modify_qp(qp, I40IW_QP_STATE_TERMINATE, | |
4543 | I40IWQP_TERM_SEND_TERM_ONLY, termlen); | |
4544 | } | |
4545 | ||
4546 | /** | |
4547 | * i40iw_terminate_received - handle terminate received AE | |
4548 | * @qp: qp associated with received terminate AE | |
4549 | * @info: the struct contiaing AE information | |
4550 | */ | |
4551 | void i40iw_terminate_received(struct i40iw_sc_qp *qp, struct i40iw_aeqe_info *info) | |
4552 | { | |
4553 | u8 *pkt = qp->q2_buf + Q2_BAD_FRAME_OFFSET; | |
20c61f7e | 4554 | __be32 *mpa; |
86dbcd0f FL |
4555 | u8 ddp_ctl; |
4556 | u8 rdma_ctl; | |
4557 | u16 aeq_id = 0; | |
4558 | struct i40iw_terminate_hdr *termhdr; | |
4559 | ||
20c61f7e | 4560 | mpa = (__be32 *)i40iw_locate_mpa(pkt); |
86dbcd0f FL |
4561 | if (info->q2_data_written) { |
4562 | /* did not validate the frame - do it now */ | |
4563 | ddp_ctl = (ntohl(mpa[0]) >> 8) & 0xff; | |
4564 | rdma_ctl = ntohl(mpa[0]) & 0xff; | |
4565 | if ((ddp_ctl & 0xc0) != 0x40) | |
4566 | aeq_id = I40IW_AE_LCE_QP_CATASTROPHIC; | |
4567 | else if ((ddp_ctl & 0x03) != 1) | |
4568 | aeq_id = I40IW_AE_DDP_UBE_INVALID_DDP_VERSION; | |
4569 | else if (ntohl(mpa[2]) != 2) | |
4570 | aeq_id = I40IW_AE_DDP_UBE_INVALID_QN; | |
4571 | else if (ntohl(mpa[3]) != 1) | |
4572 | aeq_id = I40IW_AE_DDP_INVALID_MSN_GAP_IN_MSN; | |
4573 | else if (ntohl(mpa[4]) != 0) | |
4574 | aeq_id = I40IW_AE_DDP_UBE_INVALID_MO; | |
4575 | else if ((rdma_ctl & 0xc0) != 0x40) | |
4576 | aeq_id = I40IW_AE_RDMAP_ROE_INVALID_RDMAP_VERSION; | |
4577 | ||
4578 | info->ae_id = aeq_id; | |
4579 | if (info->ae_id) { | |
4580 | /* Bad terminate recvd - send back a terminate */ | |
4581 | i40iw_terminate_connection(qp, info); | |
4582 | return; | |
4583 | } | |
4584 | } | |
4585 | ||
4586 | qp->term_flags |= I40IW_TERM_RCVD; | |
4587 | qp->eventtype = TERM_EVENT_QP_FATAL; | |
4588 | termhdr = (struct i40iw_terminate_hdr *)&mpa[5]; | |
4589 | if (termhdr->layer_etype == RDMAP_REMOTE_PROT || | |
4590 | termhdr->layer_etype == RDMAP_REMOTE_OP) { | |
4591 | i40iw_terminate_done(qp, 0); | |
4592 | } else { | |
4593 | i40iw_terminate_start_timer(qp); | |
4594 | i40iw_terminate_send_fin(qp); | |
4595 | } | |
4596 | } | |
4597 | ||
4598 | /** | |
d6f7bbcc HO |
4599 | * i40iw_sc_vsi_init - Initialize virtual device |
4600 | * @vsi: pointer to the vsi structure | |
4601 | * @info: parameters to initialize vsi | |
4602 | **/ | |
4603 | void i40iw_sc_vsi_init(struct i40iw_sc_vsi *vsi, struct i40iw_vsi_init_info *info) | |
4604 | { | |
4605 | int i; | |
4606 | ||
4607 | vsi->dev = info->dev; | |
4608 | vsi->back_vsi = info->back_vsi; | |
343d86bd | 4609 | vsi->mtu = info->params->mtu; |
66f49f88 | 4610 | vsi->exception_lan_queue = info->exception_lan_queue; |
d6f7bbcc HO |
4611 | i40iw_fill_qos_list(info->params->qs_handle_list); |
4612 | ||
4613 | for (i = 0; i < I40IW_MAX_USER_PRIORITY; i++) { | |
820cd30a DC |
4614 | vsi->qos[i].qs_handle = info->params->qs_handle_list[i]; |
4615 | i40iw_debug(vsi->dev, I40IW_DEBUG_DCB, "qset[%d]: %d\n", i, | |
4616 | vsi->qos[i].qs_handle); | |
d6f7bbcc HO |
4617 | spin_lock_init(&vsi->qos[i].lock); |
4618 | INIT_LIST_HEAD(&vsi->qos[i].qplist); | |
4619 | } | |
4620 | } | |
4621 | ||
4622 | /** | |
4623 | * i40iw_hw_stats_init - Initiliaze HW stats table | |
4624 | * @stats: pestat struct | |
86dbcd0f | 4625 | * @fcn_idx: PCI fn id |
86dbcd0f FL |
4626 | * @is_pf: Is it a PF? |
4627 | * | |
d6f7bbcc HO |
4628 | * Populate the HW stats table with register offset addr for each |
4629 | * stats. And start the perioidic stats timer. | |
86dbcd0f | 4630 | */ |
d6f7bbcc | 4631 | void i40iw_hw_stats_init(struct i40iw_vsi_pestat *stats, u8 fcn_idx, bool is_pf) |
86dbcd0f | 4632 | { |
d6f7bbcc HO |
4633 | u32 stats_reg_offset; |
4634 | u32 stats_index; | |
4635 | struct i40iw_dev_hw_stats_offsets *stats_table = | |
4636 | &stats->hw_stats_offsets; | |
4637 | struct i40iw_dev_hw_stats *last_rd_stats = &stats->last_read_hw_stats; | |
86dbcd0f FL |
4638 | |
4639 | if (is_pf) { | |
d6f7bbcc | 4640 | stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4RXDISCARD] = |
86dbcd0f | 4641 | I40E_GLPES_PFIP4RXDISCARD(fcn_idx); |
d6f7bbcc | 4642 | stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4RXTRUNC] = |
86dbcd0f | 4643 | I40E_GLPES_PFIP4RXTRUNC(fcn_idx); |
d6f7bbcc | 4644 | stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4TXNOROUTE] = |
86dbcd0f | 4645 | I40E_GLPES_PFIP4TXNOROUTE(fcn_idx); |
d6f7bbcc | 4646 | stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6RXDISCARD] = |
86dbcd0f | 4647 | I40E_GLPES_PFIP6RXDISCARD(fcn_idx); |
d6f7bbcc | 4648 | stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6RXTRUNC] = |
86dbcd0f | 4649 | I40E_GLPES_PFIP6RXTRUNC(fcn_idx); |
d6f7bbcc | 4650 | stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6TXNOROUTE] = |
86dbcd0f | 4651 | I40E_GLPES_PFIP6TXNOROUTE(fcn_idx); |
d6f7bbcc | 4652 | stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRTXSEG] = |
86dbcd0f | 4653 | I40E_GLPES_PFTCPRTXSEG(fcn_idx); |
d6f7bbcc | 4654 | stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRXOPTERR] = |
86dbcd0f | 4655 | I40E_GLPES_PFTCPRXOPTERR(fcn_idx); |
d6f7bbcc | 4656 | stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRXPROTOERR] = |
86dbcd0f FL |
4657 | I40E_GLPES_PFTCPRXPROTOERR(fcn_idx); |
4658 | ||
d6f7bbcc | 4659 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXOCTS] = |
86dbcd0f | 4660 | I40E_GLPES_PFIP4RXOCTSLO(fcn_idx); |
d6f7bbcc | 4661 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXPKTS] = |
86dbcd0f | 4662 | I40E_GLPES_PFIP4RXPKTSLO(fcn_idx); |
d6f7bbcc | 4663 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXFRAGS] = |
86dbcd0f | 4664 | I40E_GLPES_PFIP4RXFRAGSLO(fcn_idx); |
d6f7bbcc | 4665 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXMCPKTS] = |
86dbcd0f | 4666 | I40E_GLPES_PFIP4RXMCPKTSLO(fcn_idx); |
d6f7bbcc | 4667 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXOCTS] = |
86dbcd0f | 4668 | I40E_GLPES_PFIP4TXOCTSLO(fcn_idx); |
d6f7bbcc | 4669 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXPKTS] = |
86dbcd0f | 4670 | I40E_GLPES_PFIP4TXPKTSLO(fcn_idx); |
d6f7bbcc | 4671 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXFRAGS] = |
86dbcd0f | 4672 | I40E_GLPES_PFIP4TXFRAGSLO(fcn_idx); |
d6f7bbcc | 4673 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXMCPKTS] = |
86dbcd0f | 4674 | I40E_GLPES_PFIP4TXMCPKTSLO(fcn_idx); |
d6f7bbcc | 4675 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXOCTS] = |
86dbcd0f | 4676 | I40E_GLPES_PFIP6RXOCTSLO(fcn_idx); |
d6f7bbcc | 4677 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXPKTS] = |
86dbcd0f | 4678 | I40E_GLPES_PFIP6RXPKTSLO(fcn_idx); |
d6f7bbcc | 4679 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXFRAGS] = |
86dbcd0f | 4680 | I40E_GLPES_PFIP6RXFRAGSLO(fcn_idx); |
d6f7bbcc | 4681 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXMCPKTS] = |
86dbcd0f | 4682 | I40E_GLPES_PFIP6RXMCPKTSLO(fcn_idx); |
d6f7bbcc | 4683 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXOCTS] = |
86dbcd0f | 4684 | I40E_GLPES_PFIP6TXOCTSLO(fcn_idx); |
d6f7bbcc | 4685 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXPKTS] = |
86dbcd0f | 4686 | I40E_GLPES_PFIP6TXPKTSLO(fcn_idx); |
d6f7bbcc | 4687 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXPKTS] = |
86dbcd0f | 4688 | I40E_GLPES_PFIP6TXPKTSLO(fcn_idx); |
d6f7bbcc | 4689 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXFRAGS] = |
86dbcd0f | 4690 | I40E_GLPES_PFIP6TXFRAGSLO(fcn_idx); |
d6f7bbcc | 4691 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_TCPRXSEGS] = |
86dbcd0f | 4692 | I40E_GLPES_PFTCPRXSEGSLO(fcn_idx); |
d6f7bbcc | 4693 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_TCPTXSEG] = |
86dbcd0f | 4694 | I40E_GLPES_PFTCPTXSEGLO(fcn_idx); |
d6f7bbcc | 4695 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXRDS] = |
86dbcd0f | 4696 | I40E_GLPES_PFRDMARXRDSLO(fcn_idx); |
d6f7bbcc | 4697 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXSNDS] = |
86dbcd0f | 4698 | I40E_GLPES_PFRDMARXSNDSLO(fcn_idx); |
d6f7bbcc | 4699 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXWRS] = |
86dbcd0f | 4700 | I40E_GLPES_PFRDMARXWRSLO(fcn_idx); |
d6f7bbcc | 4701 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXRDS] = |
86dbcd0f | 4702 | I40E_GLPES_PFRDMATXRDSLO(fcn_idx); |
d6f7bbcc | 4703 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXSNDS] = |
86dbcd0f | 4704 | I40E_GLPES_PFRDMATXSNDSLO(fcn_idx); |
d6f7bbcc | 4705 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXWRS] = |
86dbcd0f | 4706 | I40E_GLPES_PFRDMATXWRSLO(fcn_idx); |
d6f7bbcc | 4707 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMAVBND] = |
86dbcd0f | 4708 | I40E_GLPES_PFRDMAVBNDLO(fcn_idx); |
d6f7bbcc | 4709 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMAVINV] = |
86dbcd0f FL |
4710 | I40E_GLPES_PFRDMAVINVLO(fcn_idx); |
4711 | } else { | |
d6f7bbcc | 4712 | stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4RXDISCARD] = |
86dbcd0f | 4713 | I40E_GLPES_VFIP4RXDISCARD(fcn_idx); |
d6f7bbcc | 4714 | stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4RXTRUNC] = |
86dbcd0f | 4715 | I40E_GLPES_VFIP4RXTRUNC(fcn_idx); |
d6f7bbcc | 4716 | stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4TXNOROUTE] = |
86dbcd0f | 4717 | I40E_GLPES_VFIP4TXNOROUTE(fcn_idx); |
d6f7bbcc | 4718 | stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6RXDISCARD] = |
86dbcd0f | 4719 | I40E_GLPES_VFIP6RXDISCARD(fcn_idx); |
d6f7bbcc | 4720 | stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6RXTRUNC] = |
86dbcd0f | 4721 | I40E_GLPES_VFIP6RXTRUNC(fcn_idx); |
d6f7bbcc | 4722 | stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6TXNOROUTE] = |
86dbcd0f | 4723 | I40E_GLPES_VFIP6TXNOROUTE(fcn_idx); |
d6f7bbcc | 4724 | stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRTXSEG] = |
86dbcd0f | 4725 | I40E_GLPES_VFTCPRTXSEG(fcn_idx); |
d6f7bbcc | 4726 | stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRXOPTERR] = |
86dbcd0f | 4727 | I40E_GLPES_VFTCPRXOPTERR(fcn_idx); |
d6f7bbcc | 4728 | stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRXPROTOERR] = |
86dbcd0f FL |
4729 | I40E_GLPES_VFTCPRXPROTOERR(fcn_idx); |
4730 | ||
d6f7bbcc | 4731 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXOCTS] = |
86dbcd0f | 4732 | I40E_GLPES_VFIP4RXOCTSLO(fcn_idx); |
d6f7bbcc | 4733 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXPKTS] = |
86dbcd0f | 4734 | I40E_GLPES_VFIP4RXPKTSLO(fcn_idx); |
d6f7bbcc | 4735 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXFRAGS] = |
86dbcd0f | 4736 | I40E_GLPES_VFIP4RXFRAGSLO(fcn_idx); |
d6f7bbcc | 4737 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXMCPKTS] = |
86dbcd0f | 4738 | I40E_GLPES_VFIP4RXMCPKTSLO(fcn_idx); |
d6f7bbcc | 4739 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXOCTS] = |
86dbcd0f | 4740 | I40E_GLPES_VFIP4TXOCTSLO(fcn_idx); |
d6f7bbcc | 4741 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXPKTS] = |
86dbcd0f | 4742 | I40E_GLPES_VFIP4TXPKTSLO(fcn_idx); |
d6f7bbcc | 4743 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXFRAGS] = |
86dbcd0f | 4744 | I40E_GLPES_VFIP4TXFRAGSLO(fcn_idx); |
d6f7bbcc | 4745 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXMCPKTS] = |
86dbcd0f | 4746 | I40E_GLPES_VFIP4TXMCPKTSLO(fcn_idx); |
d6f7bbcc | 4747 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXOCTS] = |
86dbcd0f | 4748 | I40E_GLPES_VFIP6RXOCTSLO(fcn_idx); |
d6f7bbcc | 4749 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXPKTS] = |
86dbcd0f | 4750 | I40E_GLPES_VFIP6RXPKTSLO(fcn_idx); |
d6f7bbcc | 4751 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXFRAGS] = |
86dbcd0f | 4752 | I40E_GLPES_VFIP6RXFRAGSLO(fcn_idx); |
d6f7bbcc | 4753 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXMCPKTS] = |
86dbcd0f | 4754 | I40E_GLPES_VFIP6RXMCPKTSLO(fcn_idx); |
d6f7bbcc | 4755 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXOCTS] = |
86dbcd0f | 4756 | I40E_GLPES_VFIP6TXOCTSLO(fcn_idx); |
d6f7bbcc | 4757 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXPKTS] = |
86dbcd0f | 4758 | I40E_GLPES_VFIP6TXPKTSLO(fcn_idx); |
d6f7bbcc | 4759 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXPKTS] = |
86dbcd0f | 4760 | I40E_GLPES_VFIP6TXPKTSLO(fcn_idx); |
d6f7bbcc | 4761 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXFRAGS] = |
86dbcd0f | 4762 | I40E_GLPES_VFIP6TXFRAGSLO(fcn_idx); |
d6f7bbcc | 4763 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_TCPRXSEGS] = |
86dbcd0f | 4764 | I40E_GLPES_VFTCPRXSEGSLO(fcn_idx); |
d6f7bbcc | 4765 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_TCPTXSEG] = |
86dbcd0f | 4766 | I40E_GLPES_VFTCPTXSEGLO(fcn_idx); |
d6f7bbcc | 4767 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXRDS] = |
86dbcd0f | 4768 | I40E_GLPES_VFRDMARXRDSLO(fcn_idx); |
d6f7bbcc | 4769 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXSNDS] = |
86dbcd0f | 4770 | I40E_GLPES_VFRDMARXSNDSLO(fcn_idx); |
d6f7bbcc | 4771 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXWRS] = |
86dbcd0f | 4772 | I40E_GLPES_VFRDMARXWRSLO(fcn_idx); |
d6f7bbcc | 4773 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXRDS] = |
86dbcd0f | 4774 | I40E_GLPES_VFRDMATXRDSLO(fcn_idx); |
d6f7bbcc | 4775 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXSNDS] = |
86dbcd0f | 4776 | I40E_GLPES_VFRDMATXSNDSLO(fcn_idx); |
d6f7bbcc | 4777 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXWRS] = |
86dbcd0f | 4778 | I40E_GLPES_VFRDMATXWRSLO(fcn_idx); |
d6f7bbcc | 4779 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMAVBND] = |
86dbcd0f | 4780 | I40E_GLPES_VFRDMAVBNDLO(fcn_idx); |
d6f7bbcc | 4781 | stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMAVINV] = |
86dbcd0f FL |
4782 | I40E_GLPES_VFRDMAVINVLO(fcn_idx); |
4783 | } | |
4784 | ||
d6f7bbcc HO |
4785 | for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_64; |
4786 | stats_index++) { | |
4787 | stats_reg_offset = stats_table->stats_offset_64[stats_index]; | |
4788 | last_rd_stats->stats_value_64[stats_index] = | |
4789 | readq(stats->hw->hw_addr + stats_reg_offset); | |
86dbcd0f FL |
4790 | } |
4791 | ||
d6f7bbcc HO |
4792 | for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_32; |
4793 | stats_index++) { | |
4794 | stats_reg_offset = stats_table->stats_offset_32[stats_index]; | |
4795 | last_rd_stats->stats_value_32[stats_index] = | |
4796 | i40iw_rd32(stats->hw, stats_reg_offset); | |
86dbcd0f FL |
4797 | } |
4798 | } | |
4799 | ||
4800 | /** | |
d6f7bbcc HO |
4801 | * i40iw_hw_stats_read_32 - Read 32-bit HW stats counters and accommodates for roll-overs. |
4802 | * @stat: pestat struct | |
4803 | * @index: index in HW stats table which contains offset reg-addr | |
4804 | * @value: hw stats value | |
86dbcd0f | 4805 | */ |
d6f7bbcc HO |
4806 | void i40iw_hw_stats_read_32(struct i40iw_vsi_pestat *stats, |
4807 | enum i40iw_hw_stats_index_32b index, | |
4808 | u64 *value) | |
86dbcd0f | 4809 | { |
d6f7bbcc HO |
4810 | struct i40iw_dev_hw_stats_offsets *stats_table = |
4811 | &stats->hw_stats_offsets; | |
4812 | struct i40iw_dev_hw_stats *last_rd_stats = &stats->last_read_hw_stats; | |
4813 | struct i40iw_dev_hw_stats *hw_stats = &stats->hw_stats; | |
4814 | u64 new_stats_value = 0; | |
4815 | u32 stats_reg_offset = stats_table->stats_offset_32[index]; | |
4816 | ||
4817 | new_stats_value = i40iw_rd32(stats->hw, stats_reg_offset); | |
86dbcd0f | 4818 | /*roll-over case */ |
d6f7bbcc HO |
4819 | if (new_stats_value < last_rd_stats->stats_value_32[index]) |
4820 | hw_stats->stats_value_32[index] += new_stats_value; | |
86dbcd0f | 4821 | else |
d6f7bbcc HO |
4822 | hw_stats->stats_value_32[index] += |
4823 | new_stats_value - last_rd_stats->stats_value_32[index]; | |
4824 | last_rd_stats->stats_value_32[index] = new_stats_value; | |
4825 | *value = hw_stats->stats_value_32[index]; | |
86dbcd0f FL |
4826 | } |
4827 | ||
4828 | /** | |
d6f7bbcc HO |
4829 | * i40iw_hw_stats_read_64 - Read HW stats counters (greater than 32-bit) and accommodates for roll-overs. |
4830 | * @stats: pestat struct | |
4831 | * @index: index in HW stats table which contains offset reg-addr | |
4832 | * @value: hw stats value | |
86dbcd0f | 4833 | */ |
d6f7bbcc HO |
4834 | void i40iw_hw_stats_read_64(struct i40iw_vsi_pestat *stats, |
4835 | enum i40iw_hw_stats_index_64b index, | |
4836 | u64 *value) | |
86dbcd0f | 4837 | { |
d6f7bbcc HO |
4838 | struct i40iw_dev_hw_stats_offsets *stats_table = |
4839 | &stats->hw_stats_offsets; | |
4840 | struct i40iw_dev_hw_stats *last_rd_stats = &stats->last_read_hw_stats; | |
4841 | struct i40iw_dev_hw_stats *hw_stats = &stats->hw_stats; | |
4842 | u64 new_stats_value = 0; | |
4843 | u32 stats_reg_offset = stats_table->stats_offset_64[index]; | |
4844 | ||
4845 | new_stats_value = readq(stats->hw->hw_addr + stats_reg_offset); | |
86dbcd0f | 4846 | /*roll-over case */ |
d6f7bbcc HO |
4847 | if (new_stats_value < last_rd_stats->stats_value_64[index]) |
4848 | hw_stats->stats_value_64[index] += new_stats_value; | |
86dbcd0f | 4849 | else |
d6f7bbcc HO |
4850 | hw_stats->stats_value_64[index] += |
4851 | new_stats_value - last_rd_stats->stats_value_64[index]; | |
4852 | last_rd_stats->stats_value_64[index] = new_stats_value; | |
4853 | *value = hw_stats->stats_value_64[index]; | |
86dbcd0f FL |
4854 | } |
4855 | ||
4856 | /** | |
d6f7bbcc HO |
4857 | * i40iw_hw_stats_read_all - read all HW stat counters |
4858 | * @stats: pestat struct | |
4859 | * @stats_values: hw stats structure | |
86dbcd0f FL |
4860 | * |
4861 | * Read all the HW stat counters and populates hw_stats structure | |
d6f7bbcc | 4862 | * of passed-in vsi's pestat as well as copy created in stat_values. |
86dbcd0f | 4863 | */ |
d6f7bbcc HO |
4864 | void i40iw_hw_stats_read_all(struct i40iw_vsi_pestat *stats, |
4865 | struct i40iw_dev_hw_stats *stats_values) | |
86dbcd0f | 4866 | { |
d6f7bbcc HO |
4867 | u32 stats_index; |
4868 | unsigned long flags; | |
4869 | ||
4870 | spin_lock_irqsave(&stats->lock, flags); | |
4871 | ||
4872 | for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_32; | |
4873 | stats_index++) | |
4874 | i40iw_hw_stats_read_32(stats, stats_index, | |
4875 | &stats_values->stats_value_32[stats_index]); | |
4876 | for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_64; | |
4877 | stats_index++) | |
4878 | i40iw_hw_stats_read_64(stats, stats_index, | |
4879 | &stats_values->stats_value_64[stats_index]); | |
4880 | spin_unlock_irqrestore(&stats->lock, flags); | |
86dbcd0f FL |
4881 | } |
4882 | ||
4883 | /** | |
d6f7bbcc HO |
4884 | * i40iw_hw_stats_refresh_all - Update all HW stats structs |
4885 | * @stats: pestat struct | |
86dbcd0f | 4886 | * |
d6f7bbcc | 4887 | * Read all the HW stats counters to refresh values in hw_stats structure |
86dbcd0f FL |
4888 | * of passed-in dev's pestat |
4889 | */ | |
d6f7bbcc HO |
4890 | void i40iw_hw_stats_refresh_all(struct i40iw_vsi_pestat *stats) |
4891 | { | |
4892 | u64 stats_value; | |
4893 | u32 stats_index; | |
4894 | unsigned long flags; | |
4895 | ||
4896 | spin_lock_irqsave(&stats->lock, flags); | |
4897 | ||
4898 | for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_32; | |
4899 | stats_index++) | |
4900 | i40iw_hw_stats_read_32(stats, stats_index, &stats_value); | |
4901 | for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_64; | |
4902 | stats_index++) | |
4903 | i40iw_hw_stats_read_64(stats, stats_index, &stats_value); | |
4904 | spin_unlock_irqrestore(&stats->lock, flags); | |
4905 | } | |
4906 | ||
4907 | /** | |
4908 | * i40iw_get_fcn_id - Return the function id | |
4909 | * @dev: pointer to the device | |
4910 | */ | |
4911 | static u8 i40iw_get_fcn_id(struct i40iw_sc_dev *dev) | |
4912 | { | |
4913 | u8 fcn_id = I40IW_INVALID_FCN_ID; | |
4914 | u8 i; | |
4915 | ||
4916 | for (i = I40IW_FIRST_NON_PF_STAT; i < I40IW_MAX_STATS_COUNT; i++) | |
4917 | if (!dev->fcn_id_array[i]) { | |
4918 | fcn_id = i; | |
4919 | dev->fcn_id_array[i] = true; | |
4920 | break; | |
4921 | } | |
4922 | return fcn_id; | |
4923 | } | |
4924 | ||
4925 | /** | |
4926 | * i40iw_vsi_stats_init - Initialize the vsi statistics | |
4927 | * @vsi: pointer to the vsi structure | |
4928 | * @info: The info structure used for initialization | |
4929 | */ | |
4930 | enum i40iw_status_code i40iw_vsi_stats_init(struct i40iw_sc_vsi *vsi, struct i40iw_vsi_stats_info *info) | |
86dbcd0f | 4931 | { |
d6f7bbcc HO |
4932 | u8 fcn_id = info->fcn_id; |
4933 | ||
4934 | if (info->alloc_fcn_id) | |
4935 | fcn_id = i40iw_get_fcn_id(vsi->dev); | |
4936 | ||
4937 | if (fcn_id == I40IW_INVALID_FCN_ID) | |
4938 | return I40IW_ERR_NOT_READY; | |
4939 | ||
4940 | vsi->pestat = info->pestat; | |
4941 | vsi->pestat->hw = vsi->dev->hw; | |
605cbb2c | 4942 | vsi->pestat->vsi = vsi; |
d6f7bbcc HO |
4943 | |
4944 | if (info->stats_initialize) { | |
4945 | i40iw_hw_stats_init(vsi->pestat, fcn_id, true); | |
4946 | spin_lock_init(&vsi->pestat->lock); | |
4947 | i40iw_hw_stats_start_timer(vsi); | |
4948 | } | |
4949 | vsi->stats_fcn_id_alloc = info->alloc_fcn_id; | |
4950 | vsi->fcn_id = fcn_id; | |
4951 | return I40IW_SUCCESS; | |
4952 | } | |
4953 | ||
4954 | /** | |
4955 | * i40iw_vsi_stats_free - Free the vsi stats | |
4956 | * @vsi: pointer to the vsi structure | |
4957 | */ | |
4958 | void i40iw_vsi_stats_free(struct i40iw_sc_vsi *vsi) | |
4959 | { | |
4960 | u8 fcn_id = vsi->fcn_id; | |
4961 | ||
aa939c12 | 4962 | if (vsi->stats_fcn_id_alloc && fcn_id < I40IW_MAX_STATS_COUNT) |
d6f7bbcc HO |
4963 | vsi->dev->fcn_id_array[fcn_id] = false; |
4964 | i40iw_hw_stats_stop_timer(vsi); | |
86dbcd0f FL |
4965 | } |
4966 | ||
4967 | static struct i40iw_cqp_ops iw_cqp_ops = { | |
7f6856b7 KC |
4968 | .cqp_init = i40iw_sc_cqp_init, |
4969 | .cqp_create = i40iw_sc_cqp_create, | |
4970 | .cqp_post_sq = i40iw_sc_cqp_post_sq, | |
4971 | .cqp_get_next_send_wqe = i40iw_sc_cqp_get_next_send_wqe, | |
4972 | .cqp_destroy = i40iw_sc_cqp_destroy, | |
4973 | .poll_for_cqp_op_done = i40iw_sc_poll_for_cqp_op_done | |
86dbcd0f FL |
4974 | }; |
4975 | ||
4976 | static struct i40iw_ccq_ops iw_ccq_ops = { | |
7f6856b7 KC |
4977 | .ccq_init = i40iw_sc_ccq_init, |
4978 | .ccq_create = i40iw_sc_ccq_create, | |
4979 | .ccq_destroy = i40iw_sc_ccq_destroy, | |
4980 | .ccq_create_done = i40iw_sc_ccq_create_done, | |
4981 | .ccq_get_cqe_info = i40iw_sc_ccq_get_cqe_info, | |
4982 | .ccq_arm = i40iw_sc_ccq_arm | |
86dbcd0f FL |
4983 | }; |
4984 | ||
4985 | static struct i40iw_ceq_ops iw_ceq_ops = { | |
7f6856b7 KC |
4986 | .ceq_init = i40iw_sc_ceq_init, |
4987 | .ceq_create = i40iw_sc_ceq_create, | |
4988 | .cceq_create_done = i40iw_sc_cceq_create_done, | |
4989 | .cceq_destroy_done = i40iw_sc_cceq_destroy_done, | |
4990 | .cceq_create = i40iw_sc_cceq_create, | |
4991 | .ceq_destroy = i40iw_sc_ceq_destroy, | |
4992 | .process_ceq = i40iw_sc_process_ceq | |
86dbcd0f FL |
4993 | }; |
4994 | ||
4995 | static struct i40iw_aeq_ops iw_aeq_ops = { | |
7f6856b7 KC |
4996 | .aeq_init = i40iw_sc_aeq_init, |
4997 | .aeq_create = i40iw_sc_aeq_create, | |
4998 | .aeq_destroy = i40iw_sc_aeq_destroy, | |
4999 | .get_next_aeqe = i40iw_sc_get_next_aeqe, | |
5000 | .repost_aeq_entries = i40iw_sc_repost_aeq_entries, | |
5001 | .aeq_create_done = i40iw_sc_aeq_create_done, | |
5002 | .aeq_destroy_done = i40iw_sc_aeq_destroy_done | |
86dbcd0f FL |
5003 | }; |
5004 | ||
5005 | /* iwarp pd ops */ | |
5006 | static struct i40iw_pd_ops iw_pd_ops = { | |
7f6856b7 | 5007 | .pd_init = i40iw_sc_pd_init, |
86dbcd0f FL |
5008 | }; |
5009 | ||
5010 | static struct i40iw_priv_qp_ops iw_priv_qp_ops = { | |
b7aee855 IM |
5011 | .qp_init = i40iw_sc_qp_init, |
5012 | .qp_create = i40iw_sc_qp_create, | |
5013 | .qp_modify = i40iw_sc_qp_modify, | |
5014 | .qp_destroy = i40iw_sc_qp_destroy, | |
5015 | .qp_flush_wqes = i40iw_sc_qp_flush_wqes, | |
5016 | .qp_upload_context = i40iw_sc_qp_upload_context, | |
5017 | .qp_setctx = i40iw_sc_qp_setctx, | |
5018 | .qp_send_lsmm = i40iw_sc_send_lsmm, | |
5019 | .qp_send_lsmm_nostag = i40iw_sc_send_lsmm_nostag, | |
5020 | .qp_send_rtt = i40iw_sc_send_rtt, | |
5021 | .qp_post_wqe0 = i40iw_sc_post_wqe0, | |
5022 | .iw_mr_fast_register = i40iw_sc_mr_fast_register | |
86dbcd0f FL |
5023 | }; |
5024 | ||
5025 | static struct i40iw_priv_cq_ops iw_priv_cq_ops = { | |
7f6856b7 KC |
5026 | .cq_init = i40iw_sc_cq_init, |
5027 | .cq_create = i40iw_sc_cq_create, | |
5028 | .cq_destroy = i40iw_sc_cq_destroy, | |
5029 | .cq_modify = i40iw_sc_cq_modify, | |
86dbcd0f FL |
5030 | }; |
5031 | ||
5032 | static struct i40iw_mr_ops iw_mr_ops = { | |
7f6856b7 KC |
5033 | .alloc_stag = i40iw_sc_alloc_stag, |
5034 | .mr_reg_non_shared = i40iw_sc_mr_reg_non_shared, | |
5035 | .mr_reg_shared = i40iw_sc_mr_reg_shared, | |
5036 | .dealloc_stag = i40iw_sc_dealloc_stag, | |
5037 | .query_stag = i40iw_sc_query_stag, | |
5038 | .mw_alloc = i40iw_sc_mw_alloc | |
86dbcd0f FL |
5039 | }; |
5040 | ||
5041 | static struct i40iw_cqp_misc_ops iw_cqp_misc_ops = { | |
7f6856b7 KC |
5042 | .manage_push_page = i40iw_sc_manage_push_page, |
5043 | .manage_hmc_pm_func_table = i40iw_sc_manage_hmc_pm_func_table, | |
5044 | .set_hmc_resource_profile = i40iw_sc_set_hmc_resource_profile, | |
5045 | .commit_fpm_values = i40iw_sc_commit_fpm_values, | |
5046 | .query_fpm_values = i40iw_sc_query_fpm_values, | |
5047 | .static_hmc_pages_allocated = i40iw_sc_static_hmc_pages_allocated, | |
5048 | .add_arp_cache_entry = i40iw_sc_add_arp_cache_entry, | |
5049 | .del_arp_cache_entry = i40iw_sc_del_arp_cache_entry, | |
5050 | .query_arp_cache_entry = i40iw_sc_query_arp_cache_entry, | |
5051 | .manage_apbvt_entry = i40iw_sc_manage_apbvt_entry, | |
5052 | .manage_qhash_table_entry = i40iw_sc_manage_qhash_table_entry, | |
5053 | .alloc_local_mac_ipaddr_table_entry = i40iw_sc_alloc_local_mac_ipaddr_entry, | |
5054 | .add_local_mac_ipaddr_entry = i40iw_sc_add_local_mac_ipaddr_entry, | |
5055 | .del_local_mac_ipaddr_entry = i40iw_sc_del_local_mac_ipaddr_entry, | |
5056 | .cqp_nop = i40iw_sc_cqp_nop, | |
5057 | .commit_fpm_values_done = i40iw_sc_commit_fpm_values_done, | |
5058 | .query_fpm_values_done = i40iw_sc_query_fpm_values_done, | |
5059 | .manage_hmc_pm_func_table_done = i40iw_sc_manage_hmc_pm_func_table_done, | |
5060 | .update_suspend_qp = i40iw_sc_suspend_qp, | |
5061 | .update_resume_qp = i40iw_sc_resume_qp | |
86dbcd0f FL |
5062 | }; |
5063 | ||
5064 | static struct i40iw_hmc_ops iw_hmc_ops = { | |
7f6856b7 KC |
5065 | .init_iw_hmc = i40iw_sc_init_iw_hmc, |
5066 | .parse_fpm_query_buf = i40iw_sc_parse_fpm_query_buf, | |
5067 | .configure_iw_fpm = i40iw_sc_configure_iw_fpm, | |
5068 | .parse_fpm_commit_buf = i40iw_sc_parse_fpm_commit_buf, | |
5069 | .create_hmc_object = i40iw_sc_create_hmc_obj, | |
5070 | .del_hmc_object = i40iw_sc_del_hmc_obj | |
86dbcd0f FL |
5071 | }; |
5072 | ||
86dbcd0f FL |
5073 | /** |
5074 | * i40iw_device_init - Initialize IWARP device | |
5075 | * @dev: IWARP device pointer | |
5076 | * @info: IWARP init info | |
5077 | */ | |
5078 | enum i40iw_status_code i40iw_device_init(struct i40iw_sc_dev *dev, | |
5079 | struct i40iw_device_init_info *info) | |
5080 | { | |
5081 | u32 val; | |
5082 | u32 vchnl_ver = 0; | |
5083 | u16 hmc_fcn = 0; | |
5084 | enum i40iw_status_code ret_code = 0; | |
5085 | u8 db_size; | |
5086 | ||
5087 | spin_lock_init(&dev->cqp_lock); | |
86dbcd0f FL |
5088 | |
5089 | i40iw_device_init_uk(&dev->dev_uk); | |
5090 | ||
5091 | dev->debug_mask = info->debug_mask; | |
5092 | ||
86dbcd0f | 5093 | dev->hmc_fn_id = info->hmc_fn_id; |
86dbcd0f FL |
5094 | dev->is_pf = info->is_pf; |
5095 | ||
5096 | dev->fpm_query_buf_pa = info->fpm_query_buf_pa; | |
5097 | dev->fpm_query_buf = info->fpm_query_buf; | |
5098 | ||
5099 | dev->fpm_commit_buf_pa = info->fpm_commit_buf_pa; | |
5100 | dev->fpm_commit_buf = info->fpm_commit_buf; | |
5101 | ||
5102 | dev->hw = info->hw; | |
5103 | dev->hw->hw_addr = info->bar0; | |
5104 | ||
86dbcd0f | 5105 | if (dev->is_pf) { |
d6f7bbcc HO |
5106 | val = i40iw_rd32(dev->hw, I40E_GLPCI_DREVID); |
5107 | dev->hw_rev = (u8)RS_32(val, I40E_GLPCI_DREVID_DEFAULT_REVID); | |
5108 | ||
86dbcd0f FL |
5109 | val = i40iw_rd32(dev->hw, I40E_GLPCI_LBARCTRL); |
5110 | db_size = (u8)RS_32(val, I40E_GLPCI_LBARCTRL_PE_DB_SIZE); | |
5111 | if ((db_size != I40IW_PE_DB_SIZE_4M) && | |
5112 | (db_size != I40IW_PE_DB_SIZE_8M)) { | |
5113 | i40iw_debug(dev, I40IW_DEBUG_DEV, | |
5114 | "%s: PE doorbell is not enabled in CSR val 0x%x\n", | |
5115 | __func__, val); | |
5116 | ret_code = I40IW_ERR_PE_DOORBELL_NOT_ENABLED; | |
5117 | return ret_code; | |
5118 | } | |
5119 | dev->db_addr = dev->hw->hw_addr + I40IW_DB_ADDR_OFFSET; | |
5120 | dev->vchnl_if.vchnl_recv = i40iw_vchnl_recv_pf; | |
5121 | } else { | |
5122 | dev->db_addr = dev->hw->hw_addr + I40IW_VF_DB_ADDR_OFFSET; | |
5123 | } | |
5124 | ||
5125 | dev->cqp_ops = &iw_cqp_ops; | |
5126 | dev->ccq_ops = &iw_ccq_ops; | |
5127 | dev->ceq_ops = &iw_ceq_ops; | |
5128 | dev->aeq_ops = &iw_aeq_ops; | |
5129 | dev->cqp_misc_ops = &iw_cqp_misc_ops; | |
5130 | dev->iw_pd_ops = &iw_pd_ops; | |
5131 | dev->iw_priv_qp_ops = &iw_priv_qp_ops; | |
5132 | dev->iw_priv_cq_ops = &iw_priv_cq_ops; | |
5133 | dev->mr_ops = &iw_mr_ops; | |
5134 | dev->hmc_ops = &iw_hmc_ops; | |
5135 | dev->vchnl_if.vchnl_send = info->vchnl_send; | |
5136 | if (dev->vchnl_if.vchnl_send) | |
5137 | dev->vchnl_up = true; | |
5138 | else | |
5139 | dev->vchnl_up = false; | |
5140 | if (!dev->is_pf) { | |
5141 | dev->vchnl_if.vchnl_recv = i40iw_vchnl_recv_vf; | |
5142 | ret_code = i40iw_vchnl_vf_get_ver(dev, &vchnl_ver); | |
5143 | if (!ret_code) { | |
5144 | i40iw_debug(dev, I40IW_DEBUG_DEV, | |
5145 | "%s: Get Channel version rc = 0x%0x, version is %u\n", | |
5146 | __func__, ret_code, vchnl_ver); | |
5147 | ret_code = i40iw_vchnl_vf_get_hmc_fcn(dev, &hmc_fcn); | |
5148 | if (!ret_code) { | |
5149 | i40iw_debug(dev, I40IW_DEBUG_DEV, | |
5150 | "%s Get HMC function rc = 0x%0x, hmc fcn is %u\n", | |
5151 | __func__, ret_code, hmc_fcn); | |
5152 | dev->hmc_fn_id = (u8)hmc_fcn; | |
5153 | } | |
5154 | } | |
5155 | } | |
5156 | dev->iw_vf_cqp_ops = &iw_vf_cqp_ops; | |
5157 | ||
5158 | return ret_code; | |
5159 | } |