[mirror_ubuntu-artful-kernel.git] / drivers / infiniband / hw / i40iw / i40iw_puda.h

/*******************************************************************************
*
* Copyright (c) 2015-2016 Intel Corporation.  All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses.  You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenFabrics.org BSD license below:
*
*   Redistribution and use in source and binary forms, with or
*   without modification, are permitted provided that the following
*   conditions are met:
*
*    - Redistributions of source code must retain the above
*	copyright notice, this list of conditions and the following
*	disclaimer.
*
*    - Redistributions in binary form must reproduce the above
*	copyright notice, this list of conditions and the following
*	disclaimer in the documentation and/or other materials
*	provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
*******************************************************************************/

#ifndef I40IW_PUDA_H
#define I40IW_PUDA_H

#define I40IW_IEQ_MPA_FRAMING 6

struct i40iw_sc_dev;
struct i40iw_sc_qp;
struct i40iw_sc_cq;

enum puda_resource_type {
	I40IW_PUDA_RSRC_TYPE_ILQ = 1,
	I40IW_PUDA_RSRC_TYPE_IEQ
};

enum puda_rsrc_complete {
	PUDA_CQ_CREATED = 1,
	PUDA_QP_CREATED,
	PUDA_TX_COMPLETE,
	PUDA_RX_COMPLETE,
	PUDA_HASH_CRC_COMPLETE
};

struct i40iw_puda_completion_info {
	struct i40iw_qp_uk *qp;
	u8 q_type;
	u8 vlan_valid;
	u8 l3proto;
	u8 l4proto;
	u16 payload_len;
	u32 compl_error;	/* No_err=0, else major and minor err code */
	u32 qp_id;
	u32 wqe_idx;
};

struct i40iw_puda_send_info {
	u64 paddr;		/* Physical address */
	u32 len;
	u8 tcplen;
	u8 maclen;
	bool ipv4;
	bool doloopback;
	void *scratch;
};

struct i40iw_puda_buf {
	struct list_head list;	/* MUST be first entry */
	struct i40iw_dma_mem mem;	/* DMA memory for the buffer */
	struct i40iw_puda_buf *next;	/* for alloclist in rsrc struct */
	struct i40iw_virt_mem buf_mem;	/* Buffer memory for this buffer */
	void *scratch;
	u8 *iph;
	u8 *tcph;
	u8 *data;
	u16 datalen;
	u16 vlan_id;
	u8 tcphlen;		/* tcp length in bytes */
	u8 maclen;		/* mac length in bytes */
	u32 totallen;		/* machlen+iphlen+tcphlen+datalen */
	atomic_t refcount;
	u8 hdrlen;
	bool ipv4;
	u32 seqnum;
};

struct i40iw_puda_rsrc_info {
	enum puda_resource_type type;	/* ILQ or IEQ */
	u32 count;
	u16 pd_id;
	bool ceq_valid;
	u32 cq_id;
	u32 qp_id;
	u32 sq_size;
	u32 rq_size;
	u16 buf_size;
	u16 mss;
	u32 tx_buf_cnt;		/* total bufs allocated will be rq_size + tx_buf_cnt */
	void (*receive)(struct i40iw_sc_vsi *, struct i40iw_puda_buf *);
	void (*xmit_complete)(struct i40iw_sc_vsi *, void *);
};

struct i40iw_puda_rsrc {
	struct i40iw_sc_cq cq;
	struct i40iw_sc_qp qp;
	struct i40iw_sc_pd sc_pd;
	struct i40iw_sc_dev *dev;
	struct i40iw_sc_vsi *vsi;
	struct i40iw_dma_mem cqmem;
	struct i40iw_dma_mem qpmem;
	struct i40iw_virt_mem ilq_mem;
	enum puda_rsrc_complete completion;
	enum puda_resource_type type;
	u16 buf_size;		/*buffer must be max datalen + tcpip hdr + mac */
	u16 mss;
	bool ceq_valid;
	u32 cq_id;
	u32 qp_id;
	u32 sq_size;
	u32 rq_size;
	u32 cq_size;
	struct i40iw_sq_uk_wr_trk_info *sq_wrtrk_array;
	u64 *rq_wrid_array;
	u32 compl_rxwqe_idx;
	u32 rx_wqe_idx;
	u32 rxq_invalid_cnt;
	u32 tx_wqe_avail_cnt;
	bool check_crc;
	struct shash_desc *hash_desc;
	struct list_head txpend;
	struct list_head bufpool;	/* free buffers pool list for recv and xmit */
	u32 alloc_buf_count;
	u32 avail_buf_count;		/* snapshot of currently available buffers */
	spinlock_t bufpool_lock;
	struct i40iw_puda_buf *alloclist;
	void (*receive)(struct i40iw_sc_vsi *, struct i40iw_puda_buf *);
	void (*xmit_complete)(struct i40iw_sc_vsi *, void *);
	/* puda stats */
	u64 stats_buf_alloc_fail;
	u64 stats_pkt_rcvd;
	u64 stats_pkt_sent;
	u64 stats_rcvd_pkt_err;
	u64 stats_sent_pkt_q;
	u64 stats_bad_qp_id;
};

struct i40iw_puda_buf *i40iw_puda_get_bufpool(struct i40iw_puda_rsrc *rsrc);
void i40iw_puda_ret_bufpool(struct i40iw_puda_rsrc *rsrc,
			    struct i40iw_puda_buf *buf);
void i40iw_puda_send_buf(struct i40iw_puda_rsrc *rsrc,
			 struct i40iw_puda_buf *buf);
enum i40iw_status_code i40iw_puda_send(struct i40iw_sc_qp *qp,
				       struct i40iw_puda_send_info *info);
enum i40iw_status_code i40iw_puda_create_rsrc(struct i40iw_sc_vsi *vsi,
					      struct i40iw_puda_rsrc_info *info);
void i40iw_puda_dele_resources(struct i40iw_sc_vsi *vsi,
			       enum puda_resource_type type,
			       bool reset);
enum i40iw_status_code i40iw_puda_poll_completion(struct i40iw_sc_dev *dev,
						  struct i40iw_sc_cq *cq, u32 *compl_err);

struct i40iw_sc_qp *i40iw_ieq_get_qp(struct i40iw_sc_dev *dev,
				     struct i40iw_puda_buf *buf);
enum i40iw_status_code i40iw_puda_get_tcpip_info(struct i40iw_puda_completion_info *info,
						 struct i40iw_puda_buf *buf);
enum i40iw_status_code i40iw_ieq_check_mpacrc(struct shash_desc *desc,
					      void *addr, u32 length, u32 value);
enum i40iw_status_code i40iw_init_hash_desc(struct shash_desc **desc);
void i40iw_ieq_mpa_crc_ae(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp);
void i40iw_free_hash_desc(struct shash_desc *desc);
void i40iw_ieq_update_tcpip_info(struct i40iw_puda_buf *buf, u16 length,
				 u32 seqnum);
enum i40iw_status_code i40iw_cqp_qp_create_cmd(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp);
enum i40iw_status_code i40iw_cqp_cq_create_cmd(struct i40iw_sc_dev *dev, struct i40iw_sc_cq *cq);
void i40iw_cqp_qp_destroy_cmd(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp);
void i40iw_cqp_cq_destroy_cmd(struct i40iw_sc_dev *dev, struct i40iw_sc_cq *cq);
#endif
Commit	Line	Data
786c6adb FL	1	/*******************************************************************************
	2	*
	3	* Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
	4	*
	5	* This software is available to you under a choice of one of two
	6	* licenses. You may choose to be licensed under the terms of the GNU
	7	* General Public License (GPL) Version 2, available from the file
	8	* COPYING in the main directory of this source tree, or the
	9	* OpenFabrics.org BSD license below:
	10	*
	11	* Redistribution and use in source and binary forms, with or
	12	* without modification, are permitted provided that the following
	13	* conditions are met:
	14	*
	15	* - Redistributions of source code must retain the above
	16	* copyright notice, this list of conditions and the following
	17	* disclaimer.
	18	*
	19	* - Redistributions in binary form must reproduce the above
	20	* copyright notice, this list of conditions and the following
	21	* disclaimer in the documentation and/or other materials
	22	* provided with the distribution.
	23	*
	24	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	25	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	26	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	27	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	28	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	29	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	30	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	31	* SOFTWARE.
	32	*
	33	*******************************************************************************/
	34
	35	#ifndef I40IW_PUDA_H
	36	#define I40IW_PUDA_H
	37
	38	#define I40IW_IEQ_MPA_FRAMING 6
	39
	40	struct i40iw_sc_dev;
	41	struct i40iw_sc_qp;
	42	struct i40iw_sc_cq;
	43
	44	enum puda_resource_type {
	45	I40IW_PUDA_RSRC_TYPE_ILQ = 1,
	46	I40IW_PUDA_RSRC_TYPE_IEQ
	47	};
	48
	49	enum puda_rsrc_complete {
	50	PUDA_CQ_CREATED = 1,
	51	PUDA_QP_CREATED,
	52	PUDA_TX_COMPLETE,
	53	PUDA_RX_COMPLETE,
	54	PUDA_HASH_CRC_COMPLETE
	55	};
	56
	57	struct i40iw_puda_completion_info {
	58	struct i40iw_qp_uk *qp;
	59	u8 q_type;
	60	u8 vlan_valid;
	61	u8 l3proto;
	62	u8 l4proto;
	63	u16 payload_len;
	64	u32 compl_error; /* No_err=0, else major and minor err code */
65	u32 qp_id;
66	u32 wqe_idx;
67	};
68
69	struct i40iw_puda_send_info {
70	u64 paddr; /* Physical address */
71	u32 len;
72	u8 tcplen;
73	u8 maclen;
74	bool ipv4;
75	bool doloopback;
76	void *scratch;
77	};
78
79	struct i40iw_puda_buf {
80	struct list_head list; /* MUST be first entry */
81	struct i40iw_dma_mem mem; /* DMA memory for the buffer */
82	struct i40iw_puda_buf next; / for alloclist in rsrc struct */
83	struct i40iw_virt_mem buf_mem; /* Buffer memory for this buffer */
84	void *scratch;
85	u8 *iph;
86	u8 *tcph;
87	u8 *data;
88	u16 datalen;
89	u16 vlan_id;
90	u8 tcphlen; /* tcp length in bytes */
91	u8 maclen; /* mac length in bytes */
92	u32 totallen; /* machlen+iphlen+tcphlen+datalen */
93	atomic_t refcount;
94	u8 hdrlen;
95	bool ipv4;
96	u32 seqnum;
97	};
98
99	struct i40iw_puda_rsrc_info {
100	enum puda_resource_type type; /* ILQ or IEQ */
101	u32 count;
102	u16 pd_id;
d6f7bbcc	103	bool ceq_valid;
786c6adb FL	104	u32 cq_id;
	105	u32 qp_id;
	106	u32 sq_size;
	107	u32 rq_size;
	108	u16 buf_size;
	109	u16 mss;
	110	u32 tx_buf_cnt; /* total bufs allocated will be rq_size + tx_buf_cnt */
d6f7bbcc HO	111	void (receive)(struct i40iw_sc_vsi , struct i40iw_puda_buf *);
d6f7bbcc HO	112	void (xmit_complete)(struct i40iw_sc_vsi , void *);
786c6adb FL	113	};
	114
	115	struct i40iw_puda_rsrc {
	116	struct i40iw_sc_cq cq;
	117	struct i40iw_sc_qp qp;
	118	struct i40iw_sc_pd sc_pd;
	119	struct i40iw_sc_dev *dev;
d6f7bbcc	120	struct i40iw_sc_vsi *vsi;
786c6adb FL	121	struct i40iw_dma_mem cqmem;
	122	struct i40iw_dma_mem qpmem;
	123	struct i40iw_virt_mem ilq_mem;
	124	enum puda_rsrc_complete completion;
	125	enum puda_resource_type type;
	126	u16 buf_size; /buffer must be max datalen + tcpip hdr + mac /
	127	u16 mss;
d6f7bbcc	128	bool ceq_valid;
786c6adb FL	129	u32 cq_id;
	130	u32 qp_id;
	131	u32 sq_size;
	132	u32 rq_size;
	133	u32 cq_size;
	134	struct i40iw_sq_uk_wr_trk_info *sq_wrtrk_array;
	135	u64 *rq_wrid_array;
	136	u32 compl_rxwqe_idx;
	137	u32 rx_wqe_idx;
	138	u32 rxq_invalid_cnt;
	139	u32 tx_wqe_avail_cnt;
	140	bool check_crc;
34abf9ed	141	struct shash_desc *hash_desc;
786c6adb FL	142	struct list_head txpend;
	143	struct list_head bufpool; /* free buffers pool list for recv and xmit */
	144	u32 alloc_buf_count;
	145	u32 avail_buf_count; /* snapshot of currently available buffers */
	146	spinlock_t bufpool_lock;
	147	struct i40iw_puda_buf *alloclist;
d6f7bbcc HO	148	void (receive)(struct i40iw_sc_vsi , struct i40iw_puda_buf *);
d6f7bbcc HO	149	void (xmit_complete)(struct i40iw_sc_vsi , void *);
786c6adb FL	150	/* puda stats */
	151	u64 stats_buf_alloc_fail;
	152	u64 stats_pkt_rcvd;
	153	u64 stats_pkt_sent;
	154	u64 stats_rcvd_pkt_err;
	155	u64 stats_sent_pkt_q;
	156	u64 stats_bad_qp_id;
	157	};
	158
	159	struct i40iw_puda_buf i40iw_puda_get_bufpool(struct i40iw_puda_rsrc rsrc);
	160	void i40iw_puda_ret_bufpool(struct i40iw_puda_rsrc *rsrc,
	161	struct i40iw_puda_buf *buf);
	162	void i40iw_puda_send_buf(struct i40iw_puda_rsrc *rsrc,
	163	struct i40iw_puda_buf *buf);
	164	enum i40iw_status_code i40iw_puda_send(struct i40iw_sc_qp *qp,
	165	struct i40iw_puda_send_info *info);
d6f7bbcc	166	enum i40iw_status_code i40iw_puda_create_rsrc(struct i40iw_sc_vsi *vsi,
786c6adb	167	struct i40iw_puda_rsrc_info *info);
d6f7bbcc	168	void i40iw_puda_dele_resources(struct i40iw_sc_vsi *vsi,
786c6adb FL	169	enum puda_resource_type type,
	170	bool reset);
	171	enum i40iw_status_code i40iw_puda_poll_completion(struct i40iw_sc_dev *dev,
	172	struct i40iw_sc_cq cq, u32 compl_err);
786c6adb FL	173
	174	struct i40iw_sc_qp i40iw_ieq_get_qp(struct i40iw_sc_dev dev,
	175	struct i40iw_puda_buf *buf);
	176	enum i40iw_status_code i40iw_puda_get_tcpip_info(struct i40iw_puda_completion_info *info,
	177	struct i40iw_puda_buf *buf);
34abf9ed	178	enum i40iw_status_code i40iw_ieq_check_mpacrc(struct shash_desc *desc,
786c6adb	179	void *addr, u32 length, u32 value);
34abf9ed	180	enum i40iw_status_code i40iw_init_hash_desc(struct shash_desc **desc);
786c6adb	181	void i40iw_ieq_mpa_crc_ae(struct i40iw_sc_dev dev, struct i40iw_sc_qp qp);
34abf9ed	182	void i40iw_free_hash_desc(struct shash_desc *desc);
786c6adb FL	183	void i40iw_ieq_update_tcpip_info(struct i40iw_puda_buf *buf, u16 length,
786c6adb FL	184	u32 seqnum);
d6f7bbcc HO	185	enum i40iw_status_code i40iw_cqp_qp_create_cmd(struct i40iw_sc_dev dev, struct i40iw_sc_qp qp);
	186	enum i40iw_status_code i40iw_cqp_cq_create_cmd(struct i40iw_sc_dev dev, struct i40iw_sc_cq cq);
	187	void i40iw_cqp_qp_destroy_cmd(struct i40iw_sc_dev dev, struct i40iw_sc_qp qp);
	188	void i40iw_cqp_cq_destroy_cmd(struct i40iw_sc_dev dev, struct i40iw_sc_cq cq);
786c6adb	189	#endif