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Merge tag 'iio-for-4.13b' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23...
[mirror_ubuntu-artful-kernel.git] / drivers / infiniband / hw / i40iw / i40iw_type.h
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89517b55
FL		 1/*******************************************************************************
2*
3* Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
4*
5* This software is available to you under a choice of one of two
6* licenses. You may choose to be licensed under the terms of the GNU
7* General Public License (GPL) Version 2, available from the file
8* COPYING in the main directory of this source tree, or the
9* OpenFabrics.org BSD license below:
10*
11* Redistribution and use in source and binary forms, with or
12* without modification, are permitted provided that the following
13* conditions are met:
14*
15* - Redistributions of source code must retain the above
16* copyright notice, this list of conditions and the following
17* disclaimer.
18*
19* - Redistributions in binary form must reproduce the above
20* copyright notice, this list of conditions and the following
21* disclaimer in the documentation and/or other materials
22* provided with the distribution.
23*
24* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31* SOFTWARE.
32*
33*******************************************************************************/
34
35#ifndef I40IW_TYPE_H
36#define I40IW_TYPE_H
37#include "i40iw_user.h"
38#include "i40iw_hmc.h"
39#include "i40iw_vf.h"
40#include "i40iw_virtchnl.h"
41
42struct i40iw_cqp_sq_wqe {
43 u64 buf[I40IW_CQP_WQE_SIZE];
44};
45
46struct i40iw_sc_aeqe {
47 u64 buf[I40IW_AEQE_SIZE];
48};
49
50struct i40iw_ceqe {
51 u64 buf[I40IW_CEQE_SIZE];
52};
53
54struct i40iw_cqp_ctx {
55 u64 buf[I40IW_CQP_CTX_SIZE];
56};
57
58struct i40iw_cq_shadow_area {
59 u64 buf[I40IW_SHADOW_AREA_SIZE];
60};
61
62struct i40iw_sc_dev;
63struct i40iw_hmc_info;
d6f7bbcc 64struct i40iw_vsi_pestat;
89517b55
FL		 65
66struct i40iw_cqp_ops;
67struct i40iw_ccq_ops;
68struct i40iw_ceq_ops;
69struct i40iw_aeq_ops;
70struct i40iw_mr_ops;
71struct i40iw_cqp_misc_ops;
72struct i40iw_pd_ops;
73struct i40iw_priv_qp_ops;
74struct i40iw_priv_cq_ops;
75struct i40iw_hmc_ops;
76
68583ca2
HO		 77enum i40iw_page_size {
78 I40IW_PAGE_SIZE_4K,
79 I40IW_PAGE_SIZE_2M
80};
81
89517b55
FL		 82enum i40iw_resource_indicator_type {
83 I40IW_RSRC_INDICATOR_TYPE_ADAPTER = 0,
84 I40IW_RSRC_INDICATOR_TYPE_CQ,
85 I40IW_RSRC_INDICATOR_TYPE_QP,
86 I40IW_RSRC_INDICATOR_TYPE_SRQ
87};
88
89enum i40iw_hdrct_flags {
90 DDP_LEN_FLAG = 0x80,
91 DDP_HDR_FLAG = 0x40,
92 RDMA_HDR_FLAG = 0x20
93};
94
95enum i40iw_term_layers {
96 LAYER_RDMA = 0,
97 LAYER_DDP = 1,
98 LAYER_MPA = 2
99};
100
101enum i40iw_term_error_types {
102 RDMAP_REMOTE_PROT = 1,
103 RDMAP_REMOTE_OP = 2,
104 DDP_CATASTROPHIC = 0,
105 DDP_TAGGED_BUFFER = 1,
106 DDP_UNTAGGED_BUFFER = 2,
107 DDP_LLP = 3
108};
109
110enum i40iw_term_rdma_errors {
111 RDMAP_INV_STAG = 0x00,
112 RDMAP_INV_BOUNDS = 0x01,
113 RDMAP_ACCESS = 0x02,
114 RDMAP_UNASSOC_STAG = 0x03,
115 RDMAP_TO_WRAP = 0x04,
116 RDMAP_INV_RDMAP_VER = 0x05,
117 RDMAP_UNEXPECTED_OP = 0x06,
118 RDMAP_CATASTROPHIC_LOCAL = 0x07,
119 RDMAP_CATASTROPHIC_GLOBAL = 0x08,
120 RDMAP_CANT_INV_STAG = 0x09,
121 RDMAP_UNSPECIFIED = 0xff
122};
123
124enum i40iw_term_ddp_errors {
125 DDP_CATASTROPHIC_LOCAL = 0x00,
126 DDP_TAGGED_INV_STAG = 0x00,
127 DDP_TAGGED_BOUNDS = 0x01,
128 DDP_TAGGED_UNASSOC_STAG = 0x02,
129 DDP_TAGGED_TO_WRAP = 0x03,
130 DDP_TAGGED_INV_DDP_VER = 0x04,
131 DDP_UNTAGGED_INV_QN = 0x01,
132 DDP_UNTAGGED_INV_MSN_NO_BUF = 0x02,
133 DDP_UNTAGGED_INV_MSN_RANGE = 0x03,
134 DDP_UNTAGGED_INV_MO = 0x04,
135 DDP_UNTAGGED_INV_TOO_LONG = 0x05,
136 DDP_UNTAGGED_INV_DDP_VER = 0x06
137};
138
139enum i40iw_term_mpa_errors {
140 MPA_CLOSED = 0x01,
141 MPA_CRC = 0x02,
142 MPA_MARKER = 0x03,
143 MPA_REQ_RSP = 0x04,
144};
145
146enum i40iw_flush_opcode {
147 FLUSH_INVALID = 0,
148 FLUSH_PROT_ERR,
149 FLUSH_REM_ACCESS_ERR,
150 FLUSH_LOC_QP_OP_ERR,
151 FLUSH_REM_OP_ERR,
152 FLUSH_LOC_LEN_ERR,
153 FLUSH_GENERAL_ERR,
154 FLUSH_FATAL_ERR
155};
156
157enum i40iw_term_eventtypes {
158 TERM_EVENT_QP_FATAL,
159 TERM_EVENT_QP_ACCESS_ERR
160};
161
162struct i40iw_terminate_hdr {
163 u8 layer_etype;
164 u8 error_code;
165 u8 hdrct;
166 u8 rsvd;
167};
168
169enum i40iw_debug_flag {
170 I40IW_DEBUG_NONE = 0x00000000,
171 I40IW_DEBUG_ERR = 0x00000001,
172 I40IW_DEBUG_INIT = 0x00000002,
173 I40IW_DEBUG_DEV = 0x00000004,
174 I40IW_DEBUG_CM = 0x00000008,
175 I40IW_DEBUG_VERBS = 0x00000010,
176 I40IW_DEBUG_PUDA = 0x00000020,
177 I40IW_DEBUG_ILQ = 0x00000040,
178 I40IW_DEBUG_IEQ = 0x00000080,
179 I40IW_DEBUG_QP = 0x00000100,
180 I40IW_DEBUG_CQ = 0x00000200,
181 I40IW_DEBUG_MR = 0x00000400,
182 I40IW_DEBUG_PBLE = 0x00000800,
183 I40IW_DEBUG_WQE = 0x00001000,
184 I40IW_DEBUG_AEQ = 0x00002000,
185 I40IW_DEBUG_CQP = 0x00004000,
186 I40IW_DEBUG_HMC = 0x00008000,
187 I40IW_DEBUG_USER = 0x00010000,
188 I40IW_DEBUG_VIRT = 0x00020000,
189 I40IW_DEBUG_DCB = 0x00040000,
190 I40IW_DEBUG_CQE = 0x00800000,
191 I40IW_DEBUG_ALL = 0xFFFFFFFF
192};
193
d6f7bbcc 194enum i40iw_hw_stats_index_32b {
89517b55
FL		 195 I40IW_HW_STAT_INDEX_IP4RXDISCARD = 0,
196 I40IW_HW_STAT_INDEX_IP4RXTRUNC,
197 I40IW_HW_STAT_INDEX_IP4TXNOROUTE,
198 I40IW_HW_STAT_INDEX_IP6RXDISCARD,
199 I40IW_HW_STAT_INDEX_IP6RXTRUNC,
200 I40IW_HW_STAT_INDEX_IP6TXNOROUTE,
201 I40IW_HW_STAT_INDEX_TCPRTXSEG,
202 I40IW_HW_STAT_INDEX_TCPRXOPTERR,
203 I40IW_HW_STAT_INDEX_TCPRXPROTOERR,
204 I40IW_HW_STAT_INDEX_MAX_32
205};
206
d6f7bbcc 207enum i40iw_hw_stats_index_64b {
89517b55
FL		 208 I40IW_HW_STAT_INDEX_IP4RXOCTS = 0,
209 I40IW_HW_STAT_INDEX_IP4RXPKTS,
210 I40IW_HW_STAT_INDEX_IP4RXFRAGS,
211 I40IW_HW_STAT_INDEX_IP4RXMCPKTS,
212 I40IW_HW_STAT_INDEX_IP4TXOCTS,
213 I40IW_HW_STAT_INDEX_IP4TXPKTS,
214 I40IW_HW_STAT_INDEX_IP4TXFRAGS,
215 I40IW_HW_STAT_INDEX_IP4TXMCPKTS,
216 I40IW_HW_STAT_INDEX_IP6RXOCTS,
217 I40IW_HW_STAT_INDEX_IP6RXPKTS,
218 I40IW_HW_STAT_INDEX_IP6RXFRAGS,
219 I40IW_HW_STAT_INDEX_IP6RXMCPKTS,
220 I40IW_HW_STAT_INDEX_IP6TXOCTS,
221 I40IW_HW_STAT_INDEX_IP6TXPKTS,
222 I40IW_HW_STAT_INDEX_IP6TXFRAGS,
223 I40IW_HW_STAT_INDEX_IP6TXMCPKTS,
224 I40IW_HW_STAT_INDEX_TCPRXSEGS,
225 I40IW_HW_STAT_INDEX_TCPTXSEG,
226 I40IW_HW_STAT_INDEX_RDMARXRDS,
227 I40IW_HW_STAT_INDEX_RDMARXSNDS,
228 I40IW_HW_STAT_INDEX_RDMARXWRS,
229 I40IW_HW_STAT_INDEX_RDMATXRDS,
230 I40IW_HW_STAT_INDEX_RDMATXSNDS,
231 I40IW_HW_STAT_INDEX_RDMATXWRS,
232 I40IW_HW_STAT_INDEX_RDMAVBND,
233 I40IW_HW_STAT_INDEX_RDMAVINV,
234 I40IW_HW_STAT_INDEX_MAX_64
235};
236
d6f7bbcc
HO		 237struct i40iw_dev_hw_stats_offsets {
238 u32 stats_offset_32[I40IW_HW_STAT_INDEX_MAX_32];
239 u32 stats_offset_64[I40IW_HW_STAT_INDEX_MAX_64];
89517b55
FL		 240};
241
242struct i40iw_dev_hw_stats {
d6f7bbcc
HO		 243 u64 stats_value_32[I40IW_HW_STAT_INDEX_MAX_32];
244 u64 stats_value_64[I40IW_HW_STAT_INDEX_MAX_64];
89517b55
FL		 245};
246
d6f7bbcc 247struct i40iw_vsi_pestat {
89517b55 248 struct i40iw_hw *hw;
89517b55
FL		 249 struct i40iw_dev_hw_stats hw_stats;
250 struct i40iw_dev_hw_stats last_read_hw_stats;
d6f7bbcc 251 struct i40iw_dev_hw_stats_offsets hw_stats_offsets;
89517b55 252 struct timer_list stats_timer;
d6f7bbcc 253 spinlock_t lock; /* rdma stats lock */
89517b55
FL		 254};
255
256struct i40iw_hw {
257 u8 __iomem *hw_addr;
258 void *dev_context;
259 struct i40iw_hmc_info hmc;
260};
261
262struct i40iw_pfpdu {
263 struct list_head rxlist;
264 u32 rcv_nxt;
265 u32 fps;
266 u32 max_fpdu_data;
267 bool mode;
268 bool mpa_crc_err;
269 u64 total_ieq_bufs;
270 u64 fpdu_processed;
271 u64 bad_seq_num;
272 u64 crc_err;
273 u64 no_tx_bufs;
274 u64 tx_err;
275 u64 out_of_order;
276 u64 pmode_count;
277};
278
279struct i40iw_sc_pd {
280 u32 size;
281 struct i40iw_sc_dev *dev;
282 u16 pd_id;
61f51b7b 283 int abi_ver;
89517b55
FL		 284};
285
286struct i40iw_cqp_quanta {
287 u64 elem[I40IW_CQP_WQE_SIZE];
288};
289
290struct i40iw_sc_cqp {
291 u32 size;
292 u64 sq_pa;
293 u64 host_ctx_pa;
294 void *back_cqp;
295 struct i40iw_sc_dev *dev;
296 enum i40iw_status_code (*process_cqp_sds)(struct i40iw_sc_dev *,
297 struct i40iw_update_sds_info *);
298 struct i40iw_dma_mem sdbuf;
299 struct i40iw_ring sq_ring;
300 struct i40iw_cqp_quanta *sq_base;
301 u64 *host_ctx;
302 u64 *scratch_array;
303 u32 cqp_id;
304 u32 sq_size;
305 u32 hw_sq_size;
306 u8 struct_ver;
307 u8 polarity;
308 bool en_datacenter_tcp;
309 u8 hmc_profile;
310 u8 enabled_vf_count;
311 u8 timeout_count;
312};
313
314struct i40iw_sc_aeq {
315 u32 size;
316 u64 aeq_elem_pa;
317 struct i40iw_sc_dev *dev;
318 struct i40iw_sc_aeqe *aeqe_base;
319 void *pbl_list;
320 u32 elem_cnt;
321 struct i40iw_ring aeq_ring;
322 bool virtual_map;
323 u8 pbl_chunk_size;
324 u32 first_pm_pbl_idx;
325 u8 polarity;
326};
327
328struct i40iw_sc_ceq {
329 u32 size;
330 u64 ceq_elem_pa;
331 struct i40iw_sc_dev *dev;
332 struct i40iw_ceqe *ceqe_base;
333 void *pbl_list;
334 u32 ceq_id;
335 u32 elem_cnt;
336 struct i40iw_ring ceq_ring;
337 bool virtual_map;
338 u8 pbl_chunk_size;
339 bool tph_en;
340 u8 tph_val;
341 u32 first_pm_pbl_idx;
342 u8 polarity;
343};
344
345struct i40iw_sc_cq {
346 struct i40iw_cq_uk cq_uk;
347 u64 cq_pa;
348 u64 shadow_area_pa;
349 struct i40iw_sc_dev *dev;
d6f7bbcc 350 struct i40iw_sc_vsi *vsi;
89517b55
FL		 351 void *pbl_list;
352 void *back_cq;
353 u32 ceq_id;
354 u32 shadow_read_threshold;
355 bool ceqe_mask;
356 bool virtual_map;
357 u8 pbl_chunk_size;
358 u8 cq_type;
359 bool ceq_id_valid;
360 bool tph_en;
361 u8 tph_val;
362 u32 first_pm_pbl_idx;
363 bool check_overflow;
364};
365
366struct i40iw_sc_qp {
367 struct i40iw_qp_uk qp_uk;
368 u64 sq_pa;
369 u64 rq_pa;
370 u64 hw_host_ctx_pa;
371 u64 shadow_area_pa;
372 u64 q2_pa;
373 struct i40iw_sc_dev *dev;
d6f7bbcc 374 struct i40iw_sc_vsi *vsi;
89517b55
FL		 375 struct i40iw_sc_pd *pd;
376 u64 *hw_host_ctx;
377 void *llp_stream_handle;
378 void *back_qp;
379 struct i40iw_pfpdu pfpdu;
380 u8 *q2_buf;
381 u64 qp_compl_ctx;
382 u16 qs_handle;
383 u16 exception_lan_queue;
384 u16 push_idx;
385 u8 sq_tph_val;
386 u8 rq_tph_val;
387 u8 qp_state;
388 u8 qp_type;
389 u8 hw_sq_size;
390 u8 hw_rq_size;
391 u8 src_mac_addr_idx;
392 bool sq_tph_en;
393 bool rq_tph_en;
394 bool rcv_tph_en;
395 bool xmit_tph_en;
396 bool virtual_map;
397 bool flush_sq;
398 bool flush_rq;
0fc2dc58
HO		 399 u8 user_pri;
400 struct list_head list;
401 bool on_qoslist;
89517b55
FL		 402 bool sq_flush;
403 enum i40iw_flush_opcode flush_code;
404 enum i40iw_term_eventtypes eventtype;
405 u8 term_flags;
406};
407
408struct i40iw_hmc_fpm_misc {
409 u32 max_ceqs;
410 u32 max_sds;
411 u32 xf_block_size;
412 u32 q1_block_size;
413 u32 ht_multiplier;
414 u32 timer_bucket;
415};
416
417struct i40iw_vchnl_if {
418 enum i40iw_status_code (*vchnl_recv)(struct i40iw_sc_dev *, u32, u8 *, u16);
419 enum i40iw_status_code (*vchnl_send)(struct i40iw_sc_dev *dev, u32, u8 *, u16);
420};
421
422#define I40IW_VCHNL_MAX_VF_MSG_SIZE 512
423
424struct i40iw_vchnl_vf_msg_buffer {
425 struct i40iw_virtchnl_op_buf vchnl_msg;
426 char parm_buffer[I40IW_VCHNL_MAX_VF_MSG_SIZE - 1];
427};
428
0fc2dc58
HO		 429struct i40iw_qos {
430 struct list_head qplist;
431 spinlock_t lock; /* qos list */
432 u16 qs_handle;
433};
434
89517b55
FL		 435struct i40iw_vfdev {
436 struct i40iw_sc_dev *pf_dev;
437 u8 *hmc_info_mem;
d6f7bbcc 438 struct i40iw_vsi_pestat pestat;
89517b55
FL		 439 struct i40iw_hmc_pble_info *pble_info;
440 struct i40iw_hmc_info hmc_info;
441 struct i40iw_vchnl_vf_msg_buffer vf_msg_buffer;
442 u64 fpm_query_buf_pa;
443 u64 *fpm_query_buf;
444 u32 vf_id;
445 u32 msg_count;
446 bool pf_hmc_initialized;
447 u16 pmf_index;
448 u16 iw_vf_idx; /* VF Device table index */
449 bool stats_initialized;
450};
451
d6f7bbcc
HO		 452#define I40IW_INVALID_FCN_ID 0xff
453struct i40iw_sc_vsi {
454 struct i40iw_sc_dev *dev;
455 void *back_vsi; /* Owned by OS */
456 u32 ilq_count;
457 struct i40iw_virt_mem ilq_mem;
458 struct i40iw_puda_rsrc *ilq;
459 u32 ieq_count;
460 struct i40iw_virt_mem ieq_mem;
461 struct i40iw_puda_rsrc *ieq;
462 u16 mss;
463 u8 fcn_id;
464 bool stats_fcn_id_alloc;
465 struct i40iw_qos qos[I40IW_MAX_USER_PRIORITY];
466 struct i40iw_vsi_pestat *pestat;
467};
468
89517b55
FL		 469struct i40iw_sc_dev {
470 struct list_head cqp_cmd_head; /* head of the CQP command list */
471 spinlock_t cqp_lock; /* cqp list sync */
472 struct i40iw_dev_uk dev_uk;
d6f7bbcc 473 bool fcn_id_array[I40IW_MAX_STATS_COUNT];
89517b55
FL		 474 struct i40iw_dma_mem vf_fpm_query_buf[I40IW_MAX_PE_ENABLED_VF_COUNT];
475 u64 fpm_query_buf_pa;
476 u64 fpm_commit_buf_pa;
477 u64 *fpm_query_buf;
478 u64 *fpm_commit_buf;
479 void *back_dev;
480 struct i40iw_hw *hw;
481 u8 __iomem *db_addr;
482 struct i40iw_hmc_info *hmc_info;
483 struct i40iw_hmc_pble_info *pble_info;
484 struct i40iw_vfdev *vf_dev[I40IW_MAX_PE_ENABLED_VF_COUNT];
485 struct i40iw_sc_cqp *cqp;
486 struct i40iw_sc_aeq *aeq;
487 struct i40iw_sc_ceq *ceq[I40IW_CEQ_MAX_COUNT];
488 struct i40iw_sc_cq *ccq;
489 struct i40iw_cqp_ops *cqp_ops;
490 struct i40iw_ccq_ops *ccq_ops;
491 struct i40iw_ceq_ops *ceq_ops;
492 struct i40iw_aeq_ops *aeq_ops;
493 struct i40iw_pd_ops *iw_pd_ops;
494 struct i40iw_priv_qp_ops *iw_priv_qp_ops;
495 struct i40iw_priv_cq_ops *iw_priv_cq_ops;
496 struct i40iw_mr_ops *mr_ops;
497 struct i40iw_cqp_misc_ops *cqp_misc_ops;
498 struct i40iw_hmc_ops *hmc_ops;
499 struct i40iw_vchnl_if vchnl_if;
dc1badf6 500 const struct i40iw_vf_cqp_ops *iw_vf_cqp_ops;
89517b55
FL		 501
502 struct i40iw_hmc_fpm_misc hmc_fpm_misc;
f69c3331 503 u32 debug_mask;
89517b55
FL		 504 u16 exception_lan_queue;
505 u8 hmc_fn_id;
506 bool is_pf;
507 bool vchnl_up;
508 u8 vf_id;
f69c3331 509 wait_queue_head_t vf_reqs;
89517b55
FL		 510 u64 cqp_cmd_stats[OP_SIZE_CQP_STAT_ARRAY];
511 struct i40iw_vchnl_vf_msg_buffer vchnl_vf_msg_buf;
512 u8 hw_rev;
513};
514
515struct i40iw_modify_cq_info {
516 u64 cq_pa;
517 struct i40iw_cqe *cq_base;
518 void *pbl_list;
519 u32 ceq_id;
520 u32 cq_size;
521 u32 shadow_read_threshold;
522 bool virtual_map;
523 u8 pbl_chunk_size;
524 bool check_overflow;
525 bool cq_resize;
526 bool ceq_change;
527 bool check_overflow_change;
528 u32 first_pm_pbl_idx;
529 bool ceq_valid;
530};
531
532struct i40iw_create_qp_info {
533 u8 next_iwarp_state;
534 bool ord_valid;
535 bool tcp_ctx_valid;
536 bool cq_num_valid;
537 bool static_rsrc;
538 bool arp_cache_idx_valid;
539};
540
541struct i40iw_modify_qp_info {
542 u64 rx_win0;
543 u64 rx_win1;
89517b55
FL		 544 u8 next_iwarp_state;
545 u8 termlen;
546 bool ord_valid;
547 bool tcp_ctx_valid;
548 bool cq_num_valid;
549 bool static_rsrc;
550 bool arp_cache_idx_valid;
551 bool reset_tcp_conn;
552 bool remove_hash_idx;
553 bool dont_send_term;
554 bool dont_send_fin;
555 bool cached_var_valid;
89517b55
FL		 556 bool force_loopback;
557};
558
559struct i40iw_ccq_cqe_info {
560 struct i40iw_sc_cqp *cqp;
561 u64 scratch;
562 u32 op_ret_val;
563 u16 maj_err_code;
564 u16 min_err_code;
565 u8 op_code;
566 bool error;
567};
568
569struct i40iw_l2params {
570 u16 qs_handle_list[I40IW_MAX_USER_PRIORITY];
571 u16 mss;
572};
573
d6f7bbcc
HO		 574struct i40iw_vsi_init_info {
575 struct i40iw_sc_dev *dev;
576 void *back_vsi;
577 struct i40iw_l2params *params;
578};
579
580struct i40iw_vsi_stats_info {
581 struct i40iw_vsi_pestat *pestat;
582 u8 fcn_id;
583 bool alloc_fcn_id;
584 bool stats_initialize;
585};
586
89517b55
FL		 587struct i40iw_device_init_info {
588 u64 fpm_query_buf_pa;
589 u64 fpm_commit_buf_pa;
590 u64 *fpm_query_buf;
591 u64 *fpm_commit_buf;
592 struct i40iw_hw *hw;
593 void __iomem *bar0;
594 enum i40iw_status_code (*vchnl_send)(struct i40iw_sc_dev *, u32, u8 *, u16);
89517b55
FL		 595 u16 exception_lan_queue;
596 u8 hmc_fn_id;
597 bool is_pf;
598 u32 debug_mask;
599};
600
601enum i40iw_cqp_hmc_profile {
602 I40IW_HMC_PROFILE_DEFAULT = 1,
603 I40IW_HMC_PROFILE_FAVOR_VF = 2,
604 I40IW_HMC_PROFILE_EQUAL = 3,
605};
606
607struct i40iw_cqp_init_info {
608 u64 cqp_compl_ctx;
609 u64 host_ctx_pa;
610 u64 sq_pa;
611 struct i40iw_sc_dev *dev;
612 struct i40iw_cqp_quanta *sq;
613 u64 *host_ctx;
614 u64 *scratch_array;
615 u32 sq_size;
616 u8 struct_ver;
617 bool en_datacenter_tcp;
618 u8 hmc_profile;
619 u8 enabled_vf_count;
620};
621
622struct i40iw_ceq_init_info {
623 u64 ceqe_pa;
624 struct i40iw_sc_dev *dev;
625 u64 *ceqe_base;
626 void *pbl_list;
627 u32 elem_cnt;
628 u32 ceq_id;
629 bool virtual_map;
630 u8 pbl_chunk_size;
631 bool tph_en;
632 u8 tph_val;
633 u32 first_pm_pbl_idx;
634};
635
636struct i40iw_aeq_init_info {
637 u64 aeq_elem_pa;
638 struct i40iw_sc_dev *dev;
639 u32 *aeqe_base;
640 void *pbl_list;
641 u32 elem_cnt;
642 bool virtual_map;
643 u8 pbl_chunk_size;
644 u32 first_pm_pbl_idx;
645};
646
647struct i40iw_ccq_init_info {
648 u64 cq_pa;
649 u64 shadow_area_pa;
650 struct i40iw_sc_dev *dev;
651 struct i40iw_cqe *cq_base;
652 u64 *shadow_area;
653 void *pbl_list;
654 u32 num_elem;
655 u32 ceq_id;
656 u32 shadow_read_threshold;
657 bool ceqe_mask;
658 bool ceq_id_valid;
659 bool tph_en;
660 u8 tph_val;
661 bool avoid_mem_cflct;
662 bool virtual_map;
663 u8 pbl_chunk_size;
664 u32 first_pm_pbl_idx;
665};
666
667struct i40iwarp_offload_info {
668 u16 rcv_mark_offset;
669 u16 snd_mark_offset;
670 u16 pd_id;
671 u8 ddp_ver;
672 u8 rdmap_ver;
673 u8 ord_size;
674 u8 ird_size;
675 bool wr_rdresp_en;
676 bool rd_enable;
677 bool snd_mark_en;
678 bool rcv_mark_en;
679 bool bind_en;
680 bool fast_reg_en;
681 bool priv_mode_en;
682 bool lsmm_present;
683 u8 iwarp_mode;
684 bool align_hdrs;
685 bool rcv_no_mpa_crc;
686
687 u8 last_byte_sent;
688};
689
690struct i40iw_tcp_offload_info {
691 bool ipv4;
692 bool no_nagle;
693 bool insert_vlan_tag;
694 bool time_stamp;
695 u8 cwnd_inc_limit;
696 bool drop_ooo_seg;
8c1ea86d 697 u8 dup_ack_thresh;
89517b55
FL		 698 u8 ttl;
699 u8 src_mac_addr_idx;
700 bool avoid_stretch_ack;
701 u8 tos;
702 u16 src_port;
703 u16 dst_port;
704 u32 dest_ip_addr0;
705 u32 dest_ip_addr1;
706 u32 dest_ip_addr2;
707 u32 dest_ip_addr3;
708 u32 snd_mss;
709 u16 vlan_tag;
710 u16 arp_idx;
711 u32 flow_label;
712 bool wscale;
713 u8 tcp_state;
714 u8 snd_wscale;
715 u8 rcv_wscale;
716 u32 time_stamp_recent;
717 u32 time_stamp_age;
718 u32 snd_nxt;
719 u32 snd_wnd;
720 u32 rcv_nxt;
721 u32 rcv_wnd;
722 u32 snd_max;
723 u32 snd_una;
724 u32 srtt;
725 u32 rtt_var;
726 u32 ss_thresh;
727 u32 cwnd;
728 u32 snd_wl1;
729 u32 snd_wl2;
730 u32 max_snd_window;
731 u8 rexmit_thresh;
732 u32 local_ipaddr0;
733 u32 local_ipaddr1;
734 u32 local_ipaddr2;
735 u32 local_ipaddr3;
736 bool ignore_tcp_opt;
737 bool ignore_tcp_uns_opt;
738};
739
740struct i40iw_qp_host_ctx_info {
741 u64 qp_compl_ctx;
742 struct i40iw_tcp_offload_info *tcp_info;
743 struct i40iwarp_offload_info *iwarp_info;
744 u32 send_cq_num;
745 u32 rcv_cq_num;
746 u16 push_idx;
747 bool push_mode_en;
748 bool tcp_info_valid;
749 bool iwarp_info_valid;
750 bool err_rq_idx_valid;
751 u16 err_rq_idx;
0fc2dc58
HO		 752 bool add_to_qoslist;
753 u8 user_pri;
89517b55
FL		 754};
755
756struct i40iw_aeqe_info {
757 u64 compl_ctx;
758 u32 qp_cq_id;
759 u16 ae_id;
760 u16 wqe_idx;
761 u8 tcp_state;
762 u8 iwarp_state;
763 bool qp;
764 bool cq;
765 bool sq;
766 bool in_rdrsp_wr;
767 bool out_rdrsp;
768 u8 q2_data_written;
769 bool aeqe_overflow;
770};
771
772struct i40iw_allocate_stag_info {
773 u64 total_len;
774 u32 chunk_size;
775 u32 stag_idx;
776 u32 page_size;
777 u16 pd_id;
778 u16 access_rights;
779 bool remote_access;
780 bool use_hmc_fcn_index;
781 u8 hmc_fcn_index;
782 bool use_pf_rid;
783};
784
785struct i40iw_reg_ns_stag_info {
786 u64 reg_addr_pa;
787 u64 fbo;
788 void *va;
789 u64 total_len;
790 u32 page_size;
791 u32 chunk_size;
792 u32 first_pm_pbl_index;
793 enum i40iw_addressing_type addr_type;
794 i40iw_stag_index stag_idx;
795 u16 access_rights;
796 u16 pd_id;
797 i40iw_stag_key stag_key;
798 bool use_hmc_fcn_index;
799 u8 hmc_fcn_index;
800 bool use_pf_rid;
801};
802
803struct i40iw_fast_reg_stag_info {
804 u64 wr_id;
805 u64 reg_addr_pa;
806 u64 fbo;
807 void *va;
808 u64 total_len;
809 u32 page_size;
810 u32 chunk_size;
811 u32 first_pm_pbl_index;
812 enum i40iw_addressing_type addr_type;
813 i40iw_stag_index stag_idx;
814 u16 access_rights;
815 u16 pd_id;
816 i40iw_stag_key stag_key;
817 bool local_fence;
818 bool read_fence;
819 bool signaled;
820 bool use_hmc_fcn_index;
821 u8 hmc_fcn_index;
822 bool use_pf_rid;
823 bool defer_flag;
824};
825
826struct i40iw_dealloc_stag_info {
827 u32 stag_idx;
828 u16 pd_id;
829 bool mr;
830 bool dealloc_pbl;
831};
832
833struct i40iw_register_shared_stag {
834 void *va;
835 enum i40iw_addressing_type addr_type;
836 i40iw_stag_index new_stag_idx;
837 i40iw_stag_index parent_stag_idx;
838 u32 access_rights;
839 u16 pd_id;
840 i40iw_stag_key new_stag_key;
841};
842
843struct i40iw_qp_init_info {
844 struct i40iw_qp_uk_init_info qp_uk_init_info;
845 struct i40iw_sc_pd *pd;
d6f7bbcc 846 struct i40iw_sc_vsi *vsi;
89517b55
FL		 847 u64 *host_ctx;
848 u8 *q2;
849 u64 sq_pa;
850 u64 rq_pa;
851 u64 host_ctx_pa;
852 u64 q2_pa;
853 u64 shadow_area_pa;
61f51b7b 854 int abi_ver;
89517b55
FL		 855 u8 sq_tph_val;
856 u8 rq_tph_val;
857 u8 type;
858 bool sq_tph_en;
859 bool rq_tph_en;
860 bool rcv_tph_en;
861 bool xmit_tph_en;
862 bool virtual_map;
863};
864
865struct i40iw_cq_init_info {
866 struct i40iw_sc_dev *dev;
867 u64 cq_base_pa;
868 u64 shadow_area_pa;
869 u32 ceq_id;
870 u32 shadow_read_threshold;
871 bool virtual_map;
872 bool ceqe_mask;
873 u8 pbl_chunk_size;
874 u32 first_pm_pbl_idx;
875 bool ceq_id_valid;
876 bool tph_en;
877 u8 tph_val;
878 u8 type;
879 struct i40iw_cq_uk_init_info cq_uk_init_info;
880};
881
882struct i40iw_upload_context_info {
883 u64 buf_pa;
884 bool freeze_qp;
885 bool raw_format;
886 u32 qp_id;
887 u8 qp_type;
888};
889
890struct i40iw_add_arp_cache_entry_info {
891 u8 mac_addr[6];
892 u32 reach_max;
893 u16 arp_index;
894 bool permanent;
895};
896
897struct i40iw_apbvt_info {
898 u16 port;
899 bool add;
900};
901
902enum i40iw_quad_entry_type {
903 I40IW_QHASH_TYPE_TCP_ESTABLISHED = 1,
904 I40IW_QHASH_TYPE_TCP_SYN,
905};
906
907enum i40iw_quad_hash_manage_type {
908 I40IW_QHASH_MANAGE_TYPE_DELETE = 0,
909 I40IW_QHASH_MANAGE_TYPE_ADD,
910 I40IW_QHASH_MANAGE_TYPE_MODIFY
911};
912
913struct i40iw_qhash_table_info {
d6f7bbcc 914 struct i40iw_sc_vsi *vsi;
89517b55
FL		 915 enum i40iw_quad_hash_manage_type manage;
916 enum i40iw_quad_entry_type entry_type;
917 bool vlan_valid;
918 bool ipv4_valid;
919 u8 mac_addr[6];
920 u16 vlan_id;
0fc2dc58 921 u8 user_pri;
89517b55
FL		 922 u32 qp_num;
923 u32 dest_ip[4];
924 u32 src_ip[4];
20c61f7e
IM		 925 u16 dest_port;
926 u16 src_port;
89517b55
FL		 927};
928
929struct i40iw_local_mac_ipaddr_entry_info {
930 u8 mac_addr[6];
931 u8 entry_idx;
932};
933
934struct i40iw_cqp_manage_push_page_info {
935 u32 push_idx;
936 u16 qs_handle;
937 u8 free_page;
938};
939
940struct i40iw_qp_flush_info {
941 u16 sq_minor_code;
942 u16 sq_major_code;
943 u16 rq_minor_code;
944 u16 rq_major_code;
945 u16 ae_code;
946 u8 ae_source;
947 bool sq;
948 bool rq;
949 bool userflushcode;
950 bool generate_ae;
951};
952
953struct i40iw_cqp_commit_fpm_values {
954 u64 qp_base;
955 u64 cq_base;
956 u32 hte_base;
957 u32 arp_base;
958 u32 apbvt_inuse_base;
959 u32 mr_base;
960 u32 xf_base;
961 u32 xffl_base;
962 u32 q1_base;
963 u32 q1fl_base;
964 u32 fsimc_base;
965 u32 fsiav_base;
966 u32 pbl_base;
967
968 u32 qp_cnt;
969 u32 cq_cnt;
970 u32 hte_cnt;
971 u32 arp_cnt;
972 u32 mr_cnt;
973 u32 xf_cnt;
974 u32 xffl_cnt;
975 u32 q1_cnt;
976 u32 q1fl_cnt;
977 u32 fsimc_cnt;
978 u32 fsiav_cnt;
979 u32 pbl_cnt;
980};
981
982struct i40iw_cqp_query_fpm_values {
983 u16 first_pe_sd_index;
984 u32 qp_objsize;
985 u32 cq_objsize;
986 u32 hte_objsize;
987 u32 arp_objsize;
988 u32 mr_objsize;
989 u32 xf_objsize;
990 u32 q1_objsize;
991 u32 fsimc_objsize;
992 u32 fsiav_objsize;
993
994 u32 qp_max;
995 u32 cq_max;
996 u32 hte_max;
997 u32 arp_max;
998 u32 mr_max;
999 u32 xf_max;
1000 u32 xffl_max;
1001 u32 q1_max;
1002 u32 q1fl_max;
1003 u32 fsimc_max;
1004 u32 fsiav_max;
1005 u32 pbl_max;
1006};
1007
1008struct i40iw_cqp_ops {
1009 enum i40iw_status_code (*cqp_init)(struct i40iw_sc_cqp *,
1010 struct i40iw_cqp_init_info *);
d62d5634 1011 enum i40iw_status_code (*cqp_create)(struct i40iw_sc_cqp *, u16 *, u16 *);
89517b55
FL		 1012 void (*cqp_post_sq)(struct i40iw_sc_cqp *);
1013 u64 *(*cqp_get_next_send_wqe)(struct i40iw_sc_cqp *, u64 scratch);
1014 enum i40iw_status_code (*cqp_destroy)(struct i40iw_sc_cqp *);
1015 enum i40iw_status_code (*poll_for_cqp_op_done)(struct i40iw_sc_cqp *, u8,
1016 struct i40iw_ccq_cqe_info *);
1017};
1018
1019struct i40iw_ccq_ops {
1020 enum i40iw_status_code (*ccq_init)(struct i40iw_sc_cq *,
1021 struct i40iw_ccq_init_info *);
1022 enum i40iw_status_code (*ccq_create)(struct i40iw_sc_cq *, u64, bool, bool);
1023 enum i40iw_status_code (*ccq_destroy)(struct i40iw_sc_cq *, u64, bool);
1024 enum i40iw_status_code (*ccq_create_done)(struct i40iw_sc_cq *);
1025 enum i40iw_status_code (*ccq_get_cqe_info)(struct i40iw_sc_cq *,
1026 struct i40iw_ccq_cqe_info *);
1027 void (*ccq_arm)(struct i40iw_sc_cq *);
1028};
1029
1030struct i40iw_ceq_ops {
1031 enum i40iw_status_code (*ceq_init)(struct i40iw_sc_ceq *,
1032 struct i40iw_ceq_init_info *);
1033 enum i40iw_status_code (*ceq_create)(struct i40iw_sc_ceq *, u64, bool);
1034 enum i40iw_status_code (*cceq_create_done)(struct i40iw_sc_ceq *);
1035 enum i40iw_status_code (*cceq_destroy_done)(struct i40iw_sc_ceq *);
1036 enum i40iw_status_code (*cceq_create)(struct i40iw_sc_ceq *, u64);
1037 enum i40iw_status_code (*ceq_destroy)(struct i40iw_sc_ceq *, u64, bool);
1038 void *(*process_ceq)(struct i40iw_sc_dev *, struct i40iw_sc_ceq *);
1039};
1040
1041struct i40iw_aeq_ops {
1042 enum i40iw_status_code (*aeq_init)(struct i40iw_sc_aeq *,
1043 struct i40iw_aeq_init_info *);
1044 enum i40iw_status_code (*aeq_create)(struct i40iw_sc_aeq *, u64, bool);
1045 enum i40iw_status_code (*aeq_destroy)(struct i40iw_sc_aeq *, u64, bool);
1046 enum i40iw_status_code (*get_next_aeqe)(struct i40iw_sc_aeq *,
1047 struct i40iw_aeqe_info *);
1048 enum i40iw_status_code (*repost_aeq_entries)(struct i40iw_sc_dev *, u32);
1049 enum i40iw_status_code (*aeq_create_done)(struct i40iw_sc_aeq *);
1050 enum i40iw_status_code (*aeq_destroy_done)(struct i40iw_sc_aeq *);
1051};
1052
1053struct i40iw_pd_ops {
61f51b7b 1054 void (*pd_init)(struct i40iw_sc_dev *, struct i40iw_sc_pd *, u16, int);
89517b55
FL		 1055};
1056
1057struct i40iw_priv_qp_ops {
1058 enum i40iw_status_code (*qp_init)(struct i40iw_sc_qp *, struct i40iw_qp_init_info *);
1059 enum i40iw_status_code (*qp_create)(struct i40iw_sc_qp *,
1060 struct i40iw_create_qp_info *, u64, bool);
1061 enum i40iw_status_code (*qp_modify)(struct i40iw_sc_qp *,
1062 struct i40iw_modify_qp_info *, u64, bool);
1063 enum i40iw_status_code (*qp_destroy)(struct i40iw_sc_qp *, u64, bool, bool, bool);
1064 enum i40iw_status_code (*qp_flush_wqes)(struct i40iw_sc_qp *,
1065 struct i40iw_qp_flush_info *, u64, bool);
1066 enum i40iw_status_code (*qp_upload_context)(struct i40iw_sc_dev *,
1067 struct i40iw_upload_context_info *,
1068 u64, bool);
1069 enum i40iw_status_code (*qp_setctx)(struct i40iw_sc_qp *, u64 *,
1070 struct i40iw_qp_host_ctx_info *);
1071
1072 void (*qp_send_lsmm)(struct i40iw_sc_qp *, void *, u32, i40iw_stag);
1073 void (*qp_send_lsmm_nostag)(struct i40iw_sc_qp *, void *, u32);
1074 void (*qp_send_rtt)(struct i40iw_sc_qp *, bool);
1075 enum i40iw_status_code (*qp_post_wqe0)(struct i40iw_sc_qp *, u8);
b7aee855
IM		 1076 enum i40iw_status_code (*iw_mr_fast_register)(struct i40iw_sc_qp *,
1077 struct i40iw_fast_reg_stag_info *,
1078 bool);
89517b55
FL		 1079};
1080
1081struct i40iw_priv_cq_ops {
1082 enum i40iw_status_code (*cq_init)(struct i40iw_sc_cq *, struct i40iw_cq_init_info *);
1083 enum i40iw_status_code (*cq_create)(struct i40iw_sc_cq *, u64, bool, bool);
1084 enum i40iw_status_code (*cq_destroy)(struct i40iw_sc_cq *, u64, bool);
1085 enum i40iw_status_code (*cq_modify)(struct i40iw_sc_cq *,
1086 struct i40iw_modify_cq_info *, u64, bool);
1087};
1088
1089struct i40iw_mr_ops {
1090 enum i40iw_status_code (*alloc_stag)(struct i40iw_sc_dev *,
1091 struct i40iw_allocate_stag_info *, u64, bool);
1092 enum i40iw_status_code (*mr_reg_non_shared)(struct i40iw_sc_dev *,
1093 struct i40iw_reg_ns_stag_info *,
1094 u64, bool);
1095 enum i40iw_status_code (*mr_reg_shared)(struct i40iw_sc_dev *,
1096 struct i40iw_register_shared_stag *,
1097 u64, bool);
1098 enum i40iw_status_code (*dealloc_stag)(struct i40iw_sc_dev *,
1099 struct i40iw_dealloc_stag_info *,
1100 u64, bool);
1101 enum i40iw_status_code (*query_stag)(struct i40iw_sc_dev *, u64, u32, bool);
1102 enum i40iw_status_code (*mw_alloc)(struct i40iw_sc_dev *, u64, u32, u16, bool);
1103};
1104
1105struct i40iw_cqp_misc_ops {
1106 enum i40iw_status_code (*manage_push_page)(struct i40iw_sc_cqp *,
1107 struct i40iw_cqp_manage_push_page_info *,
1108 u64, bool);
1109 enum i40iw_status_code (*manage_hmc_pm_func_table)(struct i40iw_sc_cqp *,
1110 u64, u8, bool, bool);
1111 enum i40iw_status_code (*set_hmc_resource_profile)(struct i40iw_sc_cqp *,
1112 u64, u8, u8, bool, bool);
1113 enum i40iw_status_code (*commit_fpm_values)(struct i40iw_sc_cqp *, u64, u8,
1114 struct i40iw_dma_mem *, bool, u8);
1115 enum i40iw_status_code (*query_fpm_values)(struct i40iw_sc_cqp *, u64, u8,
1116 struct i40iw_dma_mem *, bool, u8);
1117 enum i40iw_status_code (*static_hmc_pages_allocated)(struct i40iw_sc_cqp *,
1118 u64, u8, bool, bool);
1119 enum i40iw_status_code (*add_arp_cache_entry)(struct i40iw_sc_cqp *,
1120 struct i40iw_add_arp_cache_entry_info *,
1121 u64, bool);
1122 enum i40iw_status_code (*del_arp_cache_entry)(struct i40iw_sc_cqp *, u64, u16, bool);
1123 enum i40iw_status_code (*query_arp_cache_entry)(struct i40iw_sc_cqp *, u64, u16, bool);
1124 enum i40iw_status_code (*manage_apbvt_entry)(struct i40iw_sc_cqp *,
1125 struct i40iw_apbvt_info *, u64, bool);
1126 enum i40iw_status_code (*manage_qhash_table_entry)(struct i40iw_sc_cqp *,
1127 struct i40iw_qhash_table_info *, u64, bool);
1128 enum i40iw_status_code (*alloc_local_mac_ipaddr_table_entry)(struct i40iw_sc_cqp *, u64, bool);
1129 enum i40iw_status_code (*add_local_mac_ipaddr_entry)(struct i40iw_sc_cqp *,
1130 struct i40iw_local_mac_ipaddr_entry_info *,
1131 u64, bool);
1132 enum i40iw_status_code (*del_local_mac_ipaddr_entry)(struct i40iw_sc_cqp *, u64, u8, u8, bool);
1133 enum i40iw_status_code (*cqp_nop)(struct i40iw_sc_cqp *, u64, bool);
1134 enum i40iw_status_code (*commit_fpm_values_done)(struct i40iw_sc_cqp
1135 *);
1136 enum i40iw_status_code (*query_fpm_values_done)(struct i40iw_sc_cqp *);
1137 enum i40iw_status_code (*manage_hmc_pm_func_table_done)(struct i40iw_sc_cqp *);
1138 enum i40iw_status_code (*update_suspend_qp)(struct i40iw_sc_cqp *, struct i40iw_sc_qp *, u64);
1139 enum i40iw_status_code (*update_resume_qp)(struct i40iw_sc_cqp *, struct i40iw_sc_qp *, u64);
1140};
1141
1142struct i40iw_hmc_ops {
1143 enum i40iw_status_code (*init_iw_hmc)(struct i40iw_sc_dev *, u8);
1144 enum i40iw_status_code (*parse_fpm_query_buf)(u64 *, struct i40iw_hmc_info *,
1145 struct i40iw_hmc_fpm_misc *);
1146 enum i40iw_status_code (*configure_iw_fpm)(struct i40iw_sc_dev *, u8);
fa415379 1147 enum i40iw_status_code (*parse_fpm_commit_buf)(u64 *, struct i40iw_hmc_obj_info *, u32 *sd);
89517b55
FL		 1148 enum i40iw_status_code (*create_hmc_object)(struct i40iw_sc_dev *dev,
1149 struct i40iw_hmc_create_obj_info *);
1150 enum i40iw_status_code (*del_hmc_object)(struct i40iw_sc_dev *dev,
1151 struct i40iw_hmc_del_obj_info *,
1152 bool reset);
1153 enum i40iw_status_code (*pf_init_vfhmc)(struct i40iw_sc_dev *, u8, u32 *);
1154 enum i40iw_status_code (*vf_configure_vffpm)(struct i40iw_sc_dev *, u32 *);
1155};
1156
1157struct cqp_info {
1158 union {
1159 struct {
1160 struct i40iw_sc_qp *qp;
1161 struct i40iw_create_qp_info info;
1162 u64 scratch;
1163 } qp_create;
1164
1165 struct {
1166 struct i40iw_sc_qp *qp;
1167 struct i40iw_modify_qp_info info;
1168 u64 scratch;
1169 } qp_modify;
1170
1171 struct {
1172 struct i40iw_sc_qp *qp;
1173 u64 scratch;
1174 bool remove_hash_idx;
1175 bool ignore_mw_bnd;
1176 } qp_destroy;
1177
1178 struct {
1179 struct i40iw_sc_cq *cq;
1180 u64 scratch;
1181 bool check_overflow;
1182 } cq_create;
1183
1184 struct {
1185 struct i40iw_sc_cq *cq;
1186 u64 scratch;
1187 } cq_destroy;
1188
1189 struct {
1190 struct i40iw_sc_dev *dev;
1191 struct i40iw_allocate_stag_info info;
1192 u64 scratch;
1193 } alloc_stag;
1194
1195 struct {
1196 struct i40iw_sc_dev *dev;
1197 u64 scratch;
1198 u32 mw_stag_index;
1199 u16 pd_id;
1200 } mw_alloc;
1201
1202 struct {
1203 struct i40iw_sc_dev *dev;
1204 struct i40iw_reg_ns_stag_info info;
1205 u64 scratch;
1206 } mr_reg_non_shared;
1207
1208 struct {
1209 struct i40iw_sc_dev *dev;
1210 struct i40iw_dealloc_stag_info info;
1211 u64 scratch;
1212 } dealloc_stag;
1213
1214 struct {
1215 struct i40iw_sc_cqp *cqp;
1216 struct i40iw_local_mac_ipaddr_entry_info info;
1217 u64 scratch;
1218 } add_local_mac_ipaddr_entry;
1219
1220 struct {
1221 struct i40iw_sc_cqp *cqp;
1222 struct i40iw_add_arp_cache_entry_info info;
1223 u64 scratch;
1224 } add_arp_cache_entry;
1225
1226 struct {
1227 struct i40iw_sc_cqp *cqp;
1228 u64 scratch;
1229 u8 entry_idx;
1230 u8 ignore_ref_count;
1231 } del_local_mac_ipaddr_entry;
1232
1233 struct {
1234 struct i40iw_sc_cqp *cqp;
1235 u64 scratch;
1236 u16 arp_index;
1237 } del_arp_cache_entry;
1238
1239 struct {
1240 struct i40iw_sc_cqp *cqp;
1241 struct i40iw_manage_vf_pble_info info;
1242 u64 scratch;
1243 } manage_vf_pble_bp;
1244
1245 struct {
1246 struct i40iw_sc_cqp *cqp;
1247 struct i40iw_cqp_manage_push_page_info info;
1248 u64 scratch;
1249 } manage_push_page;
1250
1251 struct {
1252 struct i40iw_sc_dev *dev;
1253 struct i40iw_upload_context_info info;
1254 u64 scratch;
1255 } qp_upload_context;
1256
1257 struct {
1258 struct i40iw_sc_cqp *cqp;
1259 u64 scratch;
1260 } alloc_local_mac_ipaddr_entry;
1261
1262 struct {
1263 struct i40iw_sc_dev *dev;
1264 struct i40iw_hmc_fcn_info info;
1265 u64 scratch;
1266 } manage_hmc_pm;
1267
1268 struct {
1269 struct i40iw_sc_ceq *ceq;
1270 u64 scratch;
1271 } ceq_create;
1272
1273 struct {
1274 struct i40iw_sc_ceq *ceq;
1275 u64 scratch;
1276 } ceq_destroy;
1277
1278 struct {
1279 struct i40iw_sc_aeq *aeq;
1280 u64 scratch;
1281 } aeq_create;
1282
1283 struct {
1284 struct i40iw_sc_aeq *aeq;
1285 u64 scratch;
1286 } aeq_destroy;
1287
1288 struct {
1289 struct i40iw_sc_qp *qp;
1290 struct i40iw_qp_flush_info info;
1291 u64 scratch;
1292 } qp_flush_wqes;
1293
1294 struct {
1295 struct i40iw_sc_cqp *cqp;
1296 void *fpm_values_va;
1297 u64 fpm_values_pa;
1298 u8 hmc_fn_id;
1299 u64 scratch;
1300 } query_fpm_values;
1301
1302 struct {
1303 struct i40iw_sc_cqp *cqp;
1304 void *fpm_values_va;
1305 u64 fpm_values_pa;
1306 u8 hmc_fn_id;
1307 u64 scratch;
1308 } commit_fpm_values;
1309
1310 struct {
1311 struct i40iw_sc_cqp *cqp;
1312 struct i40iw_apbvt_info info;
1313 u64 scratch;
1314 } manage_apbvt_entry;
1315
1316 struct {
1317 struct i40iw_sc_cqp *cqp;
1318 struct i40iw_qhash_table_info info;
1319 u64 scratch;
1320 } manage_qhash_table_entry;
1321
1322 struct {
1323 struct i40iw_sc_dev *dev;
1324 struct i40iw_update_sds_info info;
1325 u64 scratch;
1326 } update_pe_sds;
1327
1328 struct {
1329 struct i40iw_sc_cqp *cqp;
1330 struct i40iw_sc_qp *qp;
1331 u64 scratch;
1332 } suspend_resume;
1333 } u;
1334};
1335
1336struct cqp_commands_info {
1337 struct list_head cqp_cmd_entry;
1338 u8 cqp_cmd;
1339 u8 post_sq;
1340 struct cqp_info in;
1341};
1342
1343struct i40iw_virtchnl_work_info {
1344 void (*callback_fcn)(void *vf_dev);
1345 void *worker_vf_dev;
1346};
1347
1348#endif
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