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i40iw: Utilize physically mapped memory regions
[mirror_ubuntu-artful-kernel.git] / drivers / infiniband / hw / i40iw / i40iw_verbs.c
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d3749841
FL		 1/*******************************************************************************
2*
3* Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
4*
5* This software is available to you under a choice of one of two
6* licenses. You may choose to be licensed under the terms of the GNU
7* General Public License (GPL) Version 2, available from the file
8* COPYING in the main directory of this source tree, or the
9* OpenFabrics.org BSD license below:
10*
11* Redistribution and use in source and binary forms, with or
12* without modification, are permitted provided that the following
13* conditions are met:
14*
15* - Redistributions of source code must retain the above
16* copyright notice, this list of conditions and the following
17* disclaimer.
18*
19* - Redistributions in binary form must reproduce the above
20* copyright notice, this list of conditions and the following
21* disclaimer in the documentation and/or other materials
22* provided with the distribution.
23*
24* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31* SOFTWARE.
32*
33*******************************************************************************/
34
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/random.h>
38#include <linux/highmem.h>
39#include <linux/time.h>
40#include <asm/byteorder.h>
41#include <net/ip.h>
42#include <rdma/ib_verbs.h>
43#include <rdma/iw_cm.h>
44#include <rdma/ib_user_verbs.h>
45#include <rdma/ib_umem.h>
46#include "i40iw.h"
47
48/**
49 * i40iw_query_device - get device attributes
50 * @ibdev: device pointer from stack
51 * @props: returning device attributes
52 * @udata: user data
53 */
54static int i40iw_query_device(struct ib_device *ibdev,
55 struct ib_device_attr *props,
56 struct ib_udata *udata)
57{
58 struct i40iw_device *iwdev = to_iwdev(ibdev);
59
60 if (udata->inlen || udata->outlen)
61 return -EINVAL;
62 memset(props, 0, sizeof(*props));
63 ether_addr_copy((u8 *)&props->sys_image_guid, iwdev->netdev->dev_addr);
64 props->fw_ver = I40IW_FW_VERSION;
65 props->device_cap_flags = iwdev->device_cap_flags;
4920dc31
IM		 66 props->vendor_id = iwdev->ldev->pcidev->vendor;
67 props->vendor_part_id = iwdev->ldev->pcidev->device;
d3749841
FL		 68 props->hw_ver = (u32)iwdev->sc_dev.hw_rev;
69 props->max_mr_size = I40IW_MAX_OUTBOUND_MESSAGE_SIZE;
85a87c90 70 props->max_qp = iwdev->max_qp - iwdev->used_qps;
d3749841
FL		 71 props->max_qp_wr = (I40IW_MAX_WQ_ENTRIES >> 2) - 1;
72 props->max_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
85a87c90 73 props->max_cq = iwdev->max_cq - iwdev->used_cqs;
d3749841 74 props->max_cqe = iwdev->max_cqe;
85a87c90
HO		 75 props->max_mr = iwdev->max_mr - iwdev->used_mrs;
76 props->max_pd = iwdev->max_pd - iwdev->used_pds;
6c2f7619 77 props->max_sge_rd = I40IW_MAX_SGE_RD;
d3749841
FL		 78 props->max_qp_rd_atom = I40IW_MAX_IRD_SIZE;
79 props->max_qp_init_rd_atom = props->max_qp_rd_atom;
80 props->atomic_cap = IB_ATOMIC_NONE;
81 props->max_map_per_fmr = 1;
0477e181 82 props->max_fast_reg_page_list_len = I40IW_MAX_PAGES_PER_FMR;
d3749841
FL		 83 return 0;
84}
85
86/**
87 * i40iw_query_port - get port attrubutes
88 * @ibdev: device pointer from stack
89 * @port: port number for query
90 * @props: returning device attributes
91 */
92static int i40iw_query_port(struct ib_device *ibdev,
93 u8 port,
94 struct ib_port_attr *props)
95{
96 struct i40iw_device *iwdev = to_iwdev(ibdev);
97 struct net_device *netdev = iwdev->netdev;
98
99 memset(props, 0, sizeof(*props));
100
101 props->max_mtu = IB_MTU_4096;
102 if (netdev->mtu >= 4096)
103 props->active_mtu = IB_MTU_4096;
104 else if (netdev->mtu >= 2048)
105 props->active_mtu = IB_MTU_2048;
106 else if (netdev->mtu >= 1024)
107 props->active_mtu = IB_MTU_1024;
108 else if (netdev->mtu >= 512)
109 props->active_mtu = IB_MTU_512;
110 else
111 props->active_mtu = IB_MTU_256;
112
113 props->lid = 1;
114 if (netif_carrier_ok(iwdev->netdev))
115 props->state = IB_PORT_ACTIVE;
116 else
117 props->state = IB_PORT_DOWN;
118 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
119 IB_PORT_VENDOR_CLASS_SUP | IB_PORT_BOOT_MGMT_SUP;
120 props->gid_tbl_len = 1;
121 props->pkey_tbl_len = 1;
122 props->active_width = IB_WIDTH_4X;
123 props->active_speed = 1;
bd57aeae 124 props->max_msg_sz = I40IW_MAX_OUTBOUND_MESSAGE_SIZE;
d3749841
FL		 125 return 0;
126}
127
128/**
129 * i40iw_alloc_ucontext - Allocate the user context data structure
130 * @ibdev: device pointer from stack
131 * @udata: user data
132 *
133 * This keeps track of all objects associated with a particular
134 * user-mode client.
135 */
136static struct ib_ucontext *i40iw_alloc_ucontext(struct ib_device *ibdev,
137 struct ib_udata *udata)
138{
139 struct i40iw_device *iwdev = to_iwdev(ibdev);
140 struct i40iw_alloc_ucontext_req req;
141 struct i40iw_alloc_ucontext_resp uresp;
142 struct i40iw_ucontext *ucontext;
143
144 if (ib_copy_from_udata(&req, udata, sizeof(req)))
145 return ERR_PTR(-EINVAL);
146
147 if (req.userspace_ver != I40IW_ABI_USERSPACE_VER) {
148 i40iw_pr_err("Invalid userspace driver version detected. Detected version %d, should be %d\n",
149 req.userspace_ver, I40IW_ABI_USERSPACE_VER);
150 return ERR_PTR(-EINVAL);
151 }
152
153 memset(&uresp, 0, sizeof(uresp));
154 uresp.max_qps = iwdev->max_qp;
155 uresp.max_pds = iwdev->max_pd;
156 uresp.wq_size = iwdev->max_qp_wr * 2;
157 uresp.kernel_ver = I40IW_ABI_KERNEL_VER;
158
159 ucontext = kzalloc(sizeof(*ucontext), GFP_KERNEL);
160 if (!ucontext)
161 return ERR_PTR(-ENOMEM);
162
163 ucontext->iwdev = iwdev;
164
165 if (ib_copy_to_udata(udata, &uresp, sizeof(uresp))) {
166 kfree(ucontext);
167 return ERR_PTR(-EFAULT);
168 }
169
170 INIT_LIST_HEAD(&ucontext->cq_reg_mem_list);
171 spin_lock_init(&ucontext->cq_reg_mem_list_lock);
172 INIT_LIST_HEAD(&ucontext->qp_reg_mem_list);
173 spin_lock_init(&ucontext->qp_reg_mem_list_lock);
174
175 return &ucontext->ibucontext;
176}
177
178/**
179 * i40iw_dealloc_ucontext - deallocate the user context data structure
180 * @context: user context created during alloc
181 */
182static int i40iw_dealloc_ucontext(struct ib_ucontext *context)
183{
184 struct i40iw_ucontext *ucontext = to_ucontext(context);
185 unsigned long flags;
186
187 spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
188 if (!list_empty(&ucontext->cq_reg_mem_list)) {
189 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
190 return -EBUSY;
191 }
192 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
193 spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
194 if (!list_empty(&ucontext->qp_reg_mem_list)) {
195 spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
196 return -EBUSY;
197 }
198 spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
199
200 kfree(ucontext);
201 return 0;
202}
203
204/**
205 * i40iw_mmap - user memory map
206 * @context: context created during alloc
207 * @vma: kernel info for user memory map
208 */
209static int i40iw_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
210{
211 struct i40iw_ucontext *ucontext;
212 u64 db_addr_offset;
213 u64 push_offset;
214
215 ucontext = to_ucontext(context);
216 if (ucontext->iwdev->sc_dev.is_pf) {
217 db_addr_offset = I40IW_DB_ADDR_OFFSET;
218 push_offset = I40IW_PUSH_OFFSET;
219 if (vma->vm_pgoff)
220 vma->vm_pgoff += I40IW_PF_FIRST_PUSH_PAGE_INDEX - 1;
221 } else {
222 db_addr_offset = I40IW_VF_DB_ADDR_OFFSET;
223 push_offset = I40IW_VF_PUSH_OFFSET;
224 if (vma->vm_pgoff)
225 vma->vm_pgoff += I40IW_VF_FIRST_PUSH_PAGE_INDEX - 1;
226 }
227
228 vma->vm_pgoff += db_addr_offset >> PAGE_SHIFT;
229
230 if (vma->vm_pgoff == (db_addr_offset >> PAGE_SHIFT)) {
231 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
232 vma->vm_private_data = ucontext;
233 } else {
234 if ((vma->vm_pgoff - (push_offset >> PAGE_SHIFT)) % 2)
235 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
236 else
237 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
238 }
239
240 if (io_remap_pfn_range(vma, vma->vm_start,
241 vma->vm_pgoff + (pci_resource_start(ucontext->iwdev->ldev->pcidev, 0) >> PAGE_SHIFT),
242 PAGE_SIZE, vma->vm_page_prot))
243 return -EAGAIN;
244
245 return 0;
246}
247
248/**
249 * i40iw_alloc_push_page - allocate a push page for qp
250 * @iwdev: iwarp device
251 * @qp: hardware control qp
252 */
253static void i40iw_alloc_push_page(struct i40iw_device *iwdev, struct i40iw_sc_qp *qp)
254{
255 struct i40iw_cqp_request *cqp_request;
256 struct cqp_commands_info *cqp_info;
d3749841
FL		 257 enum i40iw_status_code status;
258
259 if (qp->push_idx != I40IW_INVALID_PUSH_PAGE_INDEX)
260 return;
261
262 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
263 if (!cqp_request)
264 return;
265
266 atomic_inc(&cqp_request->refcount);
267
268 cqp_info = &cqp_request->info;
269 cqp_info->cqp_cmd = OP_MANAGE_PUSH_PAGE;
270 cqp_info->post_sq = 1;
271
0fc2dc58 272 cqp_info->in.u.manage_push_page.info.qs_handle = qp->qs_handle;
d3749841
FL		 273 cqp_info->in.u.manage_push_page.info.free_page = 0;
274 cqp_info->in.u.manage_push_page.cqp = &iwdev->cqp.sc_cqp;
275 cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request;
276
277 status = i40iw_handle_cqp_op(iwdev, cqp_request);
278 if (!status)
279 qp->push_idx = cqp_request->compl_info.op_ret_val;
280 else
281 i40iw_pr_err("CQP-OP Push page fail");
282 i40iw_put_cqp_request(&iwdev->cqp, cqp_request);
283}
284
285/**
286 * i40iw_dealloc_push_page - free a push page for qp
287 * @iwdev: iwarp device
288 * @qp: hardware control qp
289 */
290static void i40iw_dealloc_push_page(struct i40iw_device *iwdev, struct i40iw_sc_qp *qp)
291{
292 struct i40iw_cqp_request *cqp_request;
293 struct cqp_commands_info *cqp_info;
d3749841
FL		 294 enum i40iw_status_code status;
295
296 if (qp->push_idx == I40IW_INVALID_PUSH_PAGE_INDEX)
297 return;
298
299 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, false);
300 if (!cqp_request)
301 return;
302
303 cqp_info = &cqp_request->info;
304 cqp_info->cqp_cmd = OP_MANAGE_PUSH_PAGE;
305 cqp_info->post_sq = 1;
306
307 cqp_info->in.u.manage_push_page.info.push_idx = qp->push_idx;
0fc2dc58 308 cqp_info->in.u.manage_push_page.info.qs_handle = qp->qs_handle;
d3749841
FL		 309 cqp_info->in.u.manage_push_page.info.free_page = 1;
310 cqp_info->in.u.manage_push_page.cqp = &iwdev->cqp.sc_cqp;
311 cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request;
312
313 status = i40iw_handle_cqp_op(iwdev, cqp_request);
314 if (!status)
315 qp->push_idx = I40IW_INVALID_PUSH_PAGE_INDEX;
316 else
317 i40iw_pr_err("CQP-OP Push page fail");
318}
319
320/**
321 * i40iw_alloc_pd - allocate protection domain
322 * @ibdev: device pointer from stack
323 * @context: user context created during alloc
324 * @udata: user data
325 */
326static struct ib_pd *i40iw_alloc_pd(struct ib_device *ibdev,
327 struct ib_ucontext *context,
328 struct ib_udata *udata)
329{
330 struct i40iw_pd *iwpd;
331 struct i40iw_device *iwdev = to_iwdev(ibdev);
332 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
333 struct i40iw_alloc_pd_resp uresp;
334 struct i40iw_sc_pd *sc_pd;
335 u32 pd_id = 0;
336 int err;
337
338 err = i40iw_alloc_resource(iwdev, iwdev->allocated_pds,
339 iwdev->max_pd, &pd_id, &iwdev->next_pd);
340 if (err) {
341 i40iw_pr_err("alloc resource failed\n");
342 return ERR_PTR(err);
343 }
344
345 iwpd = kzalloc(sizeof(*iwpd), GFP_KERNEL);
346 if (!iwpd) {
347 err = -ENOMEM;
348 goto free_res;
349 }
350
351 sc_pd = &iwpd->sc_pd;
352 dev->iw_pd_ops->pd_init(dev, sc_pd, pd_id);
353
354 if (context) {
355 memset(&uresp, 0, sizeof(uresp));
356 uresp.pd_id = pd_id;
357 if (ib_copy_to_udata(udata, &uresp, sizeof(uresp))) {
358 err = -EFAULT;
359 goto error;
360 }
361 }
362
363 i40iw_add_pdusecount(iwpd);
364 return &iwpd->ibpd;
365error:
366 kfree(iwpd);
367free_res:
368 i40iw_free_resource(iwdev, iwdev->allocated_pds, pd_id);
369 return ERR_PTR(err);
370}
371
372/**
373 * i40iw_dealloc_pd - deallocate pd
374 * @ibpd: ptr of pd to be deallocated
375 */
376static int i40iw_dealloc_pd(struct ib_pd *ibpd)
377{
378 struct i40iw_pd *iwpd = to_iwpd(ibpd);
379 struct i40iw_device *iwdev = to_iwdev(ibpd->device);
380
381 i40iw_rem_pdusecount(iwpd, iwdev);
382 return 0;
383}
384
385/**
386 * i40iw_qp_roundup - return round up qp ring size
387 * @wr_ring_size: ring size to round up
388 */
389static int i40iw_qp_roundup(u32 wr_ring_size)
390{
391 int scount = 1;
392
393 if (wr_ring_size < I40IWQP_SW_MIN_WQSIZE)
394 wr_ring_size = I40IWQP_SW_MIN_WQSIZE;
395
396 for (wr_ring_size--; scount <= 16; scount *= 2)
397 wr_ring_size |= wr_ring_size >> scount;
398 return ++wr_ring_size;
399}
400
401/**
402 * i40iw_get_pbl - Retrieve pbl from a list given a virtual
403 * address
404 * @va: user virtual address
405 * @pbl_list: pbl list to search in (QP's or CQ's)
406 */
407static struct i40iw_pbl *i40iw_get_pbl(unsigned long va,
408 struct list_head *pbl_list)
409{
410 struct i40iw_pbl *iwpbl;
411
412 list_for_each_entry(iwpbl, pbl_list, list) {
413 if (iwpbl->user_base == va) {
414 list_del(&iwpbl->list);
415 return iwpbl;
416 }
417 }
418 return NULL;
419}
420
421/**
422 * i40iw_free_qp_resources - free up memory resources for qp
423 * @iwdev: iwarp device
424 * @iwqp: qp ptr (user or kernel)
425 * @qp_num: qp number assigned
426 */
427void i40iw_free_qp_resources(struct i40iw_device *iwdev,
428 struct i40iw_qp *iwqp,
429 u32 qp_num)
430{
431 i40iw_dealloc_push_page(iwdev, &iwqp->sc_qp);
432 if (qp_num)
433 i40iw_free_resource(iwdev, iwdev->allocated_qps, qp_num);
434 i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwqp->q2_ctx_mem);
435 i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwqp->kqp.dma_mem);
436 kfree(iwqp->kqp.wrid_mem);
437 iwqp->kqp.wrid_mem = NULL;
438 kfree(iwqp->allocated_buffer);
d3749841
FL		 439}
440
441/**
442 * i40iw_clean_cqes - clean cq entries for qp
443 * @iwqp: qp ptr (user or kernel)
444 * @iwcq: cq ptr
445 */
446static void i40iw_clean_cqes(struct i40iw_qp *iwqp, struct i40iw_cq *iwcq)
447{
448 struct i40iw_cq_uk *ukcq = &iwcq->sc_cq.cq_uk;
449
450 ukcq->ops.iw_cq_clean(&iwqp->sc_qp.qp_uk, ukcq);
451}
452
453/**
454 * i40iw_destroy_qp - destroy qp
455 * @ibqp: qp's ib pointer also to get to device's qp address
456 */
457static int i40iw_destroy_qp(struct ib_qp *ibqp)
458{
459 struct i40iw_qp *iwqp = to_iwqp(ibqp);
460
461 iwqp->destroyed = 1;
462
463 if (iwqp->ibqp_state >= IB_QPS_INIT && iwqp->ibqp_state < IB_QPS_RTS)
464 i40iw_next_iw_state(iwqp, I40IW_QP_STATE_ERROR, 0, 0, 0);
465
466 if (!iwqp->user_mode) {
467 if (iwqp->iwscq) {
468 i40iw_clean_cqes(iwqp, iwqp->iwscq);
469 if (iwqp->iwrcq != iwqp->iwscq)
470 i40iw_clean_cqes(iwqp, iwqp->iwrcq);
471 }
472 }
473
474 i40iw_rem_ref(&iwqp->ibqp);
475 return 0;
476}
477
478/**
479 * i40iw_setup_virt_qp - setup for allocation of virtual qp
480 * @dev: iwarp device
481 * @qp: qp ptr
482 * @init_info: initialize info to return
483 */
484static int i40iw_setup_virt_qp(struct i40iw_device *iwdev,
485 struct i40iw_qp *iwqp,
486 struct i40iw_qp_init_info *init_info)
487{
488 struct i40iw_pbl *iwpbl = iwqp->iwpbl;
489 struct i40iw_qp_mr *qpmr = &iwpbl->qp_mr;
490
491 iwqp->page = qpmr->sq_page;
492 init_info->shadow_area_pa = cpu_to_le64(qpmr->shadow);
493 if (iwpbl->pbl_allocated) {
494 init_info->virtual_map = true;
495 init_info->sq_pa = qpmr->sq_pbl.idx;
496 init_info->rq_pa = qpmr->rq_pbl.idx;
497 } else {
498 init_info->sq_pa = qpmr->sq_pbl.addr;
499 init_info->rq_pa = qpmr->rq_pbl.addr;
500 }
501 return 0;
502}
503
504/**
505 * i40iw_setup_kmode_qp - setup initialization for kernel mode qp
506 * @iwdev: iwarp device
507 * @iwqp: qp ptr (user or kernel)
508 * @info: initialize info to return
509 */
510static int i40iw_setup_kmode_qp(struct i40iw_device *iwdev,
511 struct i40iw_qp *iwqp,
512 struct i40iw_qp_init_info *info)
513{
514 struct i40iw_dma_mem *mem = &iwqp->kqp.dma_mem;
515 u32 sqdepth, rqdepth;
516 u32 sq_size, rq_size;
517 u8 sqshift, rqshift;
518 u32 size;
519 enum i40iw_status_code status;
520 struct i40iw_qp_uk_init_info *ukinfo = &info->qp_uk_init_info;
521
d3749841
FL		 522 sq_size = i40iw_qp_roundup(ukinfo->sq_size + 1);
523 rq_size = i40iw_qp_roundup(ukinfo->rq_size + 1);
524
23ef48ad 525 status = i40iw_get_wqe_shift(sq_size, ukinfo->max_sq_frag_cnt, ukinfo->max_inline_data, &sqshift);
d3749841 526 if (!status)
23ef48ad 527 status = i40iw_get_wqe_shift(rq_size, ukinfo->max_rq_frag_cnt, 0, &rqshift);
d3749841
FL		 528
529 if (status)
fe5d6e62 530 return -ENOMEM;
d3749841
FL		 531
532 sqdepth = sq_size << sqshift;
533 rqdepth = rq_size << rqshift;
534
535 size = sqdepth * sizeof(struct i40iw_sq_uk_wr_trk_info) + (rqdepth << 3);
536 iwqp->kqp.wrid_mem = kzalloc(size, GFP_KERNEL);
537
538 ukinfo->sq_wrtrk_array = (struct i40iw_sq_uk_wr_trk_info *)iwqp->kqp.wrid_mem;
539 if (!ukinfo->sq_wrtrk_array)
540 return -ENOMEM;
541
542 ukinfo->rq_wrid_array = (u64 *)&ukinfo->sq_wrtrk_array[sqdepth];
543
544 size = (sqdepth + rqdepth) * I40IW_QP_WQE_MIN_SIZE;
545 size += (I40IW_SHADOW_AREA_SIZE << 3);
546
547 status = i40iw_allocate_dma_mem(iwdev->sc_dev.hw, mem, size, 256);
548 if (status) {
549 kfree(ukinfo->sq_wrtrk_array);
550 ukinfo->sq_wrtrk_array = NULL;
551 return -ENOMEM;
552 }
553
554 ukinfo->sq = mem->va;
555 info->sq_pa = mem->pa;
556
557 ukinfo->rq = &ukinfo->sq[sqdepth];
558 info->rq_pa = info->sq_pa + (sqdepth * I40IW_QP_WQE_MIN_SIZE);
559
560 ukinfo->shadow_area = ukinfo->rq[rqdepth].elem;
561 info->shadow_area_pa = info->rq_pa + (rqdepth * I40IW_QP_WQE_MIN_SIZE);
562
563 ukinfo->sq_size = sq_size;
564 ukinfo->rq_size = rq_size;
565 ukinfo->qp_id = iwqp->ibqp.qp_num;
566 return 0;
567}
568
569/**
570 * i40iw_create_qp - create qp
571 * @ibpd: ptr of pd
572 * @init_attr: attributes for qp
573 * @udata: user data for create qp
574 */
575static struct ib_qp *i40iw_create_qp(struct ib_pd *ibpd,
576 struct ib_qp_init_attr *init_attr,
577 struct ib_udata *udata)
578{
579 struct i40iw_pd *iwpd = to_iwpd(ibpd);
580 struct i40iw_device *iwdev = to_iwdev(ibpd->device);
581 struct i40iw_cqp *iwcqp = &iwdev->cqp;
582 struct i40iw_qp *iwqp;
583 struct i40iw_ucontext *ucontext;
584 struct i40iw_create_qp_req req;
585 struct i40iw_create_qp_resp uresp;
586 u32 qp_num = 0;
587 void *mem;
588 enum i40iw_status_code ret;
589 int err_code;
590 int sq_size;
591 int rq_size;
592 struct i40iw_sc_qp *qp;
593 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
594 struct i40iw_qp_init_info init_info;
595 struct i40iw_create_qp_info *qp_info;
596 struct i40iw_cqp_request *cqp_request;
597 struct cqp_commands_info *cqp_info;
598
599 struct i40iw_qp_host_ctx_info *ctx_info;
600 struct i40iwarp_offload_info *iwarp_info;
601 unsigned long flags;
602
603 if (init_attr->create_flags)
604 return ERR_PTR(-EINVAL);
605 if (init_attr->cap.max_inline_data > I40IW_MAX_INLINE_DATA_SIZE)
606 init_attr->cap.max_inline_data = I40IW_MAX_INLINE_DATA_SIZE;
607
23ef48ad
IM		 608 if (init_attr->cap.max_send_sge > I40IW_MAX_WQ_FRAGMENT_COUNT)
609 init_attr->cap.max_send_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
610
01d0b367
HO		 611 if (init_attr->cap.max_recv_sge > I40IW_MAX_WQ_FRAGMENT_COUNT)
612 init_attr->cap.max_recv_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
613
d3749841
FL		 614 memset(&init_info, 0, sizeof(init_info));
615
616 sq_size = init_attr->cap.max_send_wr;
617 rq_size = init_attr->cap.max_recv_wr;
618
619 init_info.qp_uk_init_info.sq_size = sq_size;
620 init_info.qp_uk_init_info.rq_size = rq_size;
621 init_info.qp_uk_init_info.max_sq_frag_cnt = init_attr->cap.max_send_sge;
622 init_info.qp_uk_init_info.max_rq_frag_cnt = init_attr->cap.max_recv_sge;
23ef48ad 623 init_info.qp_uk_init_info.max_inline_data = init_attr->cap.max_inline_data;
d3749841
FL		 624
625 mem = kzalloc(sizeof(*iwqp), GFP_KERNEL);
626 if (!mem)
627 return ERR_PTR(-ENOMEM);
628
629 iwqp = (struct i40iw_qp *)mem;
630 qp = &iwqp->sc_qp;
631 qp->back_qp = (void *)iwqp;
632 qp->push_idx = I40IW_INVALID_PUSH_PAGE_INDEX;
633
634 iwqp->ctx_info.iwarp_info = &iwqp->iwarp_info;
635
636 if (i40iw_allocate_dma_mem(dev->hw,
637 &iwqp->q2_ctx_mem,
638 I40IW_Q2_BUFFER_SIZE + I40IW_QP_CTX_SIZE,
639 256)) {
640 i40iw_pr_err("dma_mem failed\n");
641 err_code = -ENOMEM;
642 goto error;
643 }
644
645 init_info.q2 = iwqp->q2_ctx_mem.va;
646 init_info.q2_pa = iwqp->q2_ctx_mem.pa;
647
648 init_info.host_ctx = (void *)init_info.q2 + I40IW_Q2_BUFFER_SIZE;
649 init_info.host_ctx_pa = init_info.q2_pa + I40IW_Q2_BUFFER_SIZE;
650
651 err_code = i40iw_alloc_resource(iwdev, iwdev->allocated_qps, iwdev->max_qp,
652 &qp_num, &iwdev->next_qp);
653 if (err_code) {
654 i40iw_pr_err("qp resource\n");
655 goto error;
656 }
657
658 iwqp->allocated_buffer = mem;
659 iwqp->iwdev = iwdev;
660 iwqp->iwpd = iwpd;
661 iwqp->ibqp.qp_num = qp_num;
662 qp = &iwqp->sc_qp;
663 iwqp->iwscq = to_iwcq(init_attr->send_cq);
664 iwqp->iwrcq = to_iwcq(init_attr->recv_cq);
665
666 iwqp->host_ctx.va = init_info.host_ctx;
667 iwqp->host_ctx.pa = init_info.host_ctx_pa;
668 iwqp->host_ctx.size = I40IW_QP_CTX_SIZE;
669
670 init_info.pd = &iwpd->sc_pd;
671 init_info.qp_uk_init_info.qp_id = iwqp->ibqp.qp_num;
672 iwqp->ctx_info.qp_compl_ctx = (uintptr_t)qp;
673
674 if (init_attr->qp_type != IB_QPT_RC) {
fe5d6e62 675 err_code = -EINVAL;
d3749841
FL		 676 goto error;
677 }
678 if (iwdev->push_mode)
679 i40iw_alloc_push_page(iwdev, qp);
680 if (udata) {
681 err_code = ib_copy_from_udata(&req, udata, sizeof(req));
682 if (err_code) {
683 i40iw_pr_err("ib_copy_from_data\n");
684 goto error;
685 }
686 iwqp->ctx_info.qp_compl_ctx = req.user_compl_ctx;
687 if (ibpd->uobject && ibpd->uobject->context) {
688 iwqp->user_mode = 1;
689 ucontext = to_ucontext(ibpd->uobject->context);
690
691 if (req.user_wqe_buffers) {
692 spin_lock_irqsave(
693 &ucontext->qp_reg_mem_list_lock, flags);
694 iwqp->iwpbl = i40iw_get_pbl(
695 (unsigned long)req.user_wqe_buffers,
696 &ucontext->qp_reg_mem_list);
697 spin_unlock_irqrestore(
698 &ucontext->qp_reg_mem_list_lock, flags);
699
700 if (!iwqp->iwpbl) {
701 err_code = -ENODATA;
702 i40iw_pr_err("no pbl info\n");
703 goto error;
704 }
705 }
706 }
707 err_code = i40iw_setup_virt_qp(iwdev, iwqp, &init_info);
708 } else {
709 err_code = i40iw_setup_kmode_qp(iwdev, iwqp, &init_info);
710 }
711
712 if (err_code) {
713 i40iw_pr_err("setup qp failed\n");
714 goto error;
715 }
716
717 init_info.type = I40IW_QP_TYPE_IWARP;
718 ret = dev->iw_priv_qp_ops->qp_init(qp, &init_info);
719 if (ret) {
720 err_code = -EPROTO;
721 i40iw_pr_err("qp_init fail\n");
722 goto error;
723 }
724 ctx_info = &iwqp->ctx_info;
725 iwarp_info = &iwqp->iwarp_info;
726 iwarp_info->rd_enable = true;
727 iwarp_info->wr_rdresp_en = true;
b7aee855
IM		 728 if (!iwqp->user_mode) {
729 iwarp_info->fast_reg_en = true;
d3749841 730 iwarp_info->priv_mode_en = true;
b7aee855 731 }
d3749841
FL		 732 iwarp_info->ddp_ver = 1;
733 iwarp_info->rdmap_ver = 1;
734
735 ctx_info->iwarp_info_valid = true;
736 ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
737 ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
738 if (qp->push_idx == I40IW_INVALID_PUSH_PAGE_INDEX) {
739 ctx_info->push_mode_en = false;
740 } else {
741 ctx_info->push_mode_en = true;
742 ctx_info->push_idx = qp->push_idx;
743 }
744
745 ret = dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp,
746 (u64 *)iwqp->host_ctx.va,
747 ctx_info);
748 ctx_info->iwarp_info_valid = false;
749 cqp_request = i40iw_get_cqp_request(iwcqp, true);
750 if (!cqp_request) {
751 err_code = -ENOMEM;
752 goto error;
753 }
754 cqp_info = &cqp_request->info;
755 qp_info = &cqp_request->info.in.u.qp_create.info;
756
757 memset(qp_info, 0, sizeof(*qp_info));
758
759 qp_info->cq_num_valid = true;
760 qp_info->next_iwarp_state = I40IW_QP_STATE_IDLE;
761
762 cqp_info->cqp_cmd = OP_QP_CREATE;
763 cqp_info->post_sq = 1;
764 cqp_info->in.u.qp_create.qp = qp;
765 cqp_info->in.u.qp_create.scratch = (uintptr_t)cqp_request;
766 ret = i40iw_handle_cqp_op(iwdev, cqp_request);
767 if (ret) {
768 i40iw_pr_err("CQP-OP QP create fail");
769 err_code = -EACCES;
770 goto error;
771 }
772
773 i40iw_add_ref(&iwqp->ibqp);
774 spin_lock_init(&iwqp->lock);
775 iwqp->sig_all = (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) ? 1 : 0;
776 iwdev->qp_table[qp_num] = iwqp;
777 i40iw_add_pdusecount(iwqp->iwpd);
778 if (ibpd->uobject && udata) {
779 memset(&uresp, 0, sizeof(uresp));
780 uresp.actual_sq_size = sq_size;
781 uresp.actual_rq_size = rq_size;
782 uresp.qp_id = qp_num;
783 uresp.push_idx = qp->push_idx;
784 err_code = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
785 if (err_code) {
786 i40iw_pr_err("copy_to_udata failed\n");
787 i40iw_destroy_qp(&iwqp->ibqp);
788 /* let the completion of the qp destroy free the qp */
789 return ERR_PTR(err_code);
790 }
791 }
c2b75ef7
IM		 792 init_completion(&iwqp->sq_drained);
793 init_completion(&iwqp->rq_drained);
d3749841
FL		 794
795 return &iwqp->ibqp;
796error:
797 i40iw_free_qp_resources(iwdev, iwqp, qp_num);
d3749841
FL		 798 return ERR_PTR(err_code);
799}
800
801/**
802 * i40iw_query - query qp attributes
803 * @ibqp: qp pointer
804 * @attr: attributes pointer
805 * @attr_mask: Not used
806 * @init_attr: qp attributes to return
807 */
808static int i40iw_query_qp(struct ib_qp *ibqp,
809 struct ib_qp_attr *attr,
810 int attr_mask,
811 struct ib_qp_init_attr *init_attr)
812{
813 struct i40iw_qp *iwqp = to_iwqp(ibqp);
814 struct i40iw_sc_qp *qp = &iwqp->sc_qp;
815
816 attr->qp_access_flags = 0;
817 attr->cap.max_send_wr = qp->qp_uk.sq_size;
818 attr->cap.max_recv_wr = qp->qp_uk.rq_size;
d3749841 819 attr->cap.max_inline_data = I40IW_MAX_INLINE_DATA_SIZE;
01d0b367
HO		 820 attr->cap.max_send_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
821 attr->cap.max_recv_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
d3749841
FL		 822 init_attr->event_handler = iwqp->ibqp.event_handler;
823 init_attr->qp_context = iwqp->ibqp.qp_context;
824 init_attr->send_cq = iwqp->ibqp.send_cq;
825 init_attr->recv_cq = iwqp->ibqp.recv_cq;
826 init_attr->srq = iwqp->ibqp.srq;
827 init_attr->cap = attr->cap;
828 return 0;
829}
830
831/**
832 * i40iw_hw_modify_qp - setup cqp for modify qp
833 * @iwdev: iwarp device
834 * @iwqp: qp ptr (user or kernel)
835 * @info: info for modify qp
836 * @wait: flag to wait or not for modify qp completion
837 */
838void i40iw_hw_modify_qp(struct i40iw_device *iwdev, struct i40iw_qp *iwqp,
839 struct i40iw_modify_qp_info *info, bool wait)
840{
841 enum i40iw_status_code status;
842 struct i40iw_cqp_request *cqp_request;
843 struct cqp_commands_info *cqp_info;
844 struct i40iw_modify_qp_info *m_info;
845
846 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, wait);
847 if (!cqp_request)
848 return;
849
850 cqp_info = &cqp_request->info;
851 m_info = &cqp_info->in.u.qp_modify.info;
852 memcpy(m_info, info, sizeof(*m_info));
853 cqp_info->cqp_cmd = OP_QP_MODIFY;
854 cqp_info->post_sq = 1;
855 cqp_info->in.u.qp_modify.qp = &iwqp->sc_qp;
856 cqp_info->in.u.qp_modify.scratch = (uintptr_t)cqp_request;
857 status = i40iw_handle_cqp_op(iwdev, cqp_request);
858 if (status)
859 i40iw_pr_err("CQP-OP Modify QP fail");
860}
861
862/**
863 * i40iw_modify_qp - modify qp request
864 * @ibqp: qp's pointer for modify
865 * @attr: access attributes
866 * @attr_mask: state mask
867 * @udata: user data
868 */
869int i40iw_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
870 int attr_mask, struct ib_udata *udata)
871{
872 struct i40iw_qp *iwqp = to_iwqp(ibqp);
873 struct i40iw_device *iwdev = iwqp->iwdev;
874 struct i40iw_qp_host_ctx_info *ctx_info;
875 struct i40iwarp_offload_info *iwarp_info;
876 struct i40iw_modify_qp_info info;
877 u8 issue_modify_qp = 0;
878 u8 dont_wait = 0;
879 u32 err;
880 unsigned long flags;
881
882 memset(&info, 0, sizeof(info));
883 ctx_info = &iwqp->ctx_info;
884 iwarp_info = &iwqp->iwarp_info;
885
886 spin_lock_irqsave(&iwqp->lock, flags);
887
888 if (attr_mask & IB_QP_STATE) {
889 switch (attr->qp_state) {
890 case IB_QPS_INIT:
891 case IB_QPS_RTR:
892 if (iwqp->iwarp_state > (u32)I40IW_QP_STATE_IDLE) {
893 err = -EINVAL;
894 goto exit;
895 }
896 if (iwqp->iwarp_state == I40IW_QP_STATE_INVALID) {
897 info.next_iwarp_state = I40IW_QP_STATE_IDLE;
898 issue_modify_qp = 1;
899 }
900 break;
901 case IB_QPS_RTS:
902 if ((iwqp->iwarp_state > (u32)I40IW_QP_STATE_RTS) ||
903 (!iwqp->cm_id)) {
904 err = -EINVAL;
905 goto exit;
906 }
907
908 issue_modify_qp = 1;
909 iwqp->hw_tcp_state = I40IW_TCP_STATE_ESTABLISHED;
910 iwqp->hte_added = 1;
911 info.next_iwarp_state = I40IW_QP_STATE_RTS;
912 info.tcp_ctx_valid = true;
913 info.ord_valid = true;
914 info.arp_cache_idx_valid = true;
915 info.cq_num_valid = true;
916 break;
917 case IB_QPS_SQD:
918 if (iwqp->hw_iwarp_state > (u32)I40IW_QP_STATE_RTS) {
919 err = 0;
920 goto exit;
921 }
922 if ((iwqp->iwarp_state == (u32)I40IW_QP_STATE_CLOSING) ||
923 (iwqp->iwarp_state < (u32)I40IW_QP_STATE_RTS)) {
924 err = 0;
925 goto exit;
926 }
927 if (iwqp->iwarp_state > (u32)I40IW_QP_STATE_CLOSING) {
928 err = -EINVAL;
929 goto exit;
930 }
931 info.next_iwarp_state = I40IW_QP_STATE_CLOSING;
932 issue_modify_qp = 1;
933 break;
934 case IB_QPS_SQE:
935 if (iwqp->iwarp_state >= (u32)I40IW_QP_STATE_TERMINATE) {
936 err = -EINVAL;
937 goto exit;
938 }
939 info.next_iwarp_state = I40IW_QP_STATE_TERMINATE;
940 issue_modify_qp = 1;
941 break;
942 case IB_QPS_ERR:
943 case IB_QPS_RESET:
944 if (iwqp->iwarp_state == (u32)I40IW_QP_STATE_ERROR) {
945 err = -EINVAL;
946 goto exit;
947 }
948 if (iwqp->sc_qp.term_flags)
949 del_timer(&iwqp->terminate_timer);
950 info.next_iwarp_state = I40IW_QP_STATE_ERROR;
951 if ((iwqp->hw_tcp_state > I40IW_TCP_STATE_CLOSED) &&
952 iwdev->iw_status &&
953 (iwqp->hw_tcp_state != I40IW_TCP_STATE_TIME_WAIT))
954 info.reset_tcp_conn = true;
955 else
956 dont_wait = 1;
957 issue_modify_qp = 1;
958 info.next_iwarp_state = I40IW_QP_STATE_ERROR;
959 break;
960 default:
961 err = -EINVAL;
962 goto exit;
963 }
964
965 iwqp->ibqp_state = attr->qp_state;
966
967 if (issue_modify_qp)
968 iwqp->iwarp_state = info.next_iwarp_state;
969 else
970 info.next_iwarp_state = iwqp->iwarp_state;
971 }
972 if (attr_mask & IB_QP_ACCESS_FLAGS) {
973 ctx_info->iwarp_info_valid = true;
974 if (attr->qp_access_flags & IB_ACCESS_LOCAL_WRITE)
975 iwarp_info->wr_rdresp_en = true;
976 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
977 iwarp_info->wr_rdresp_en = true;
978 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
979 iwarp_info->rd_enable = true;
980 if (attr->qp_access_flags & IB_ACCESS_MW_BIND)
981 iwarp_info->bind_en = true;
982
983 if (iwqp->user_mode) {
984 iwarp_info->rd_enable = true;
985 iwarp_info->wr_rdresp_en = true;
986 iwarp_info->priv_mode_en = false;
987 }
988 }
989
990 if (ctx_info->iwarp_info_valid) {
991 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
992 int ret;
993
994 ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
995 ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
996 ret = dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp,
997 (u64 *)iwqp->host_ctx.va,
998 ctx_info);
999 if (ret) {
1000 i40iw_pr_err("setting QP context\n");
1001 err = -EINVAL;
1002 goto exit;
1003 }
1004 }
1005
1006 spin_unlock_irqrestore(&iwqp->lock, flags);
1007
1008 if (issue_modify_qp)
1009 i40iw_hw_modify_qp(iwdev, iwqp, &info, true);
1010
1011 if (issue_modify_qp && (iwqp->ibqp_state > IB_QPS_RTS)) {
1012 if (dont_wait) {
1013 if (iwqp->cm_id && iwqp->hw_tcp_state) {
1014 spin_lock_irqsave(&iwqp->lock, flags);
1015 iwqp->hw_tcp_state = I40IW_TCP_STATE_CLOSED;
1016 iwqp->last_aeq = I40IW_AE_RESET_SENT;
1017 spin_unlock_irqrestore(&iwqp->lock, flags);
1018 }
1019 }
1020 }
1021 return 0;
1022exit:
1023 spin_unlock_irqrestore(&iwqp->lock, flags);
1024 return err;
1025}
1026
1027/**
1028 * cq_free_resources - free up recources for cq
1029 * @iwdev: iwarp device
1030 * @iwcq: cq ptr
1031 */
1032static void cq_free_resources(struct i40iw_device *iwdev, struct i40iw_cq *iwcq)
1033{
1034 struct i40iw_sc_cq *cq = &iwcq->sc_cq;
1035
1036 if (!iwcq->user_mode)
1037 i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwcq->kmem);
1038 i40iw_free_resource(iwdev, iwdev->allocated_cqs, cq->cq_uk.cq_id);
1039}
1040
1041/**
1042 * cq_wq_destroy - send cq destroy cqp
1043 * @iwdev: iwarp device
1044 * @cq: hardware control cq
1045 */
1046static void cq_wq_destroy(struct i40iw_device *iwdev, struct i40iw_sc_cq *cq)
1047{
1048 enum i40iw_status_code status;
1049 struct i40iw_cqp_request *cqp_request;
1050 struct cqp_commands_info *cqp_info;
1051
1052 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
1053 if (!cqp_request)
1054 return;
1055
1056 cqp_info = &cqp_request->info;
1057
1058 cqp_info->cqp_cmd = OP_CQ_DESTROY;
1059 cqp_info->post_sq = 1;
1060 cqp_info->in.u.cq_destroy.cq = cq;
1061 cqp_info->in.u.cq_destroy.scratch = (uintptr_t)cqp_request;
1062 status = i40iw_handle_cqp_op(iwdev, cqp_request);
1063 if (status)
1064 i40iw_pr_err("CQP-OP Destroy QP fail");
1065}
1066
1067/**
1068 * i40iw_destroy_cq - destroy cq
1069 * @ib_cq: cq pointer
1070 */
1071static int i40iw_destroy_cq(struct ib_cq *ib_cq)
1072{
1073 struct i40iw_cq *iwcq;
1074 struct i40iw_device *iwdev;
1075 struct i40iw_sc_cq *cq;
1076
1077 if (!ib_cq) {
1078 i40iw_pr_err("ib_cq == NULL\n");
1079 return 0;
1080 }
1081
1082 iwcq = to_iwcq(ib_cq);
1083 iwdev = to_iwdev(ib_cq->device);
1084 cq = &iwcq->sc_cq;
1085 cq_wq_destroy(iwdev, cq);
1086 cq_free_resources(iwdev, iwcq);
1087 kfree(iwcq);
1088 return 0;
1089}
1090
1091/**
1092 * i40iw_create_cq - create cq
1093 * @ibdev: device pointer from stack
1094 * @attr: attributes for cq
1095 * @context: user context created during alloc
1096 * @udata: user data
1097 */
1098static struct ib_cq *i40iw_create_cq(struct ib_device *ibdev,
1099 const struct ib_cq_init_attr *attr,
1100 struct ib_ucontext *context,
1101 struct ib_udata *udata)
1102{
1103 struct i40iw_device *iwdev = to_iwdev(ibdev);
1104 struct i40iw_cq *iwcq;
1105 struct i40iw_pbl *iwpbl;
1106 u32 cq_num = 0;
1107 struct i40iw_sc_cq *cq;
1108 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
1109 struct i40iw_cq_init_info info;
1110 enum i40iw_status_code status;
1111 struct i40iw_cqp_request *cqp_request;
1112 struct cqp_commands_info *cqp_info;
1113 struct i40iw_cq_uk_init_info *ukinfo = &info.cq_uk_init_info;
1114 unsigned long flags;
1115 int err_code;
1116 int entries = attr->cqe;
1117
1118 if (entries > iwdev->max_cqe)
1119 return ERR_PTR(-EINVAL);
1120
1121 iwcq = kzalloc(sizeof(*iwcq), GFP_KERNEL);
1122 if (!iwcq)
1123 return ERR_PTR(-ENOMEM);
1124
1125 memset(&info, 0, sizeof(info));
1126
1127 err_code = i40iw_alloc_resource(iwdev, iwdev->allocated_cqs,
1128 iwdev->max_cq, &cq_num,
1129 &iwdev->next_cq);
1130 if (err_code)
1131 goto error;
1132
1133 cq = &iwcq->sc_cq;
1134 cq->back_cq = (void *)iwcq;
1135 spin_lock_init(&iwcq->lock);
1136
1137 info.dev = dev;
1138 ukinfo->cq_size = max(entries, 4);
1139 ukinfo->cq_id = cq_num;
1140 iwcq->ibcq.cqe = info.cq_uk_init_info.cq_size;
1141 info.ceqe_mask = 0;
e69c5093
HO		 1142 if (attr->comp_vector < iwdev->ceqs_count)
1143 info.ceq_id = attr->comp_vector;
d3749841
FL		 1144 info.ceq_id_valid = true;
1145 info.ceqe_mask = 1;
1146 info.type = I40IW_CQ_TYPE_IWARP;
1147 if (context) {
1148 struct i40iw_ucontext *ucontext;
1149 struct i40iw_create_cq_req req;
1150 struct i40iw_cq_mr *cqmr;
1151
1152 memset(&req, 0, sizeof(req));
1153 iwcq->user_mode = true;
1154 ucontext = to_ucontext(context);
1155 if (ib_copy_from_udata(&req, udata, sizeof(struct i40iw_create_cq_req)))
1156 goto cq_free_resources;
1157
1158 spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
1159 iwpbl = i40iw_get_pbl((unsigned long)req.user_cq_buffer,
1160 &ucontext->cq_reg_mem_list);
1161 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
1162 if (!iwpbl) {
1163 err_code = -EPROTO;
1164 goto cq_free_resources;
1165 }
1166
1167 iwcq->iwpbl = iwpbl;
1168 iwcq->cq_mem_size = 0;
1169 cqmr = &iwpbl->cq_mr;
1170 info.shadow_area_pa = cpu_to_le64(cqmr->shadow);
1171 if (iwpbl->pbl_allocated) {
1172 info.virtual_map = true;
1173 info.pbl_chunk_size = 1;
1174 info.first_pm_pbl_idx = cqmr->cq_pbl.idx;
1175 } else {
1176 info.cq_base_pa = cqmr->cq_pbl.addr;
1177 }
1178 } else {
1179 /* Kmode allocations */
1180 int rsize;
1181 int shadow;
1182
1183 rsize = info.cq_uk_init_info.cq_size * sizeof(struct i40iw_cqe);
1184 rsize = round_up(rsize, 256);
1185 shadow = I40IW_SHADOW_AREA_SIZE << 3;
1186 status = i40iw_allocate_dma_mem(dev->hw, &iwcq->kmem,
1187 rsize + shadow, 256);
1188 if (status) {
1189 err_code = -ENOMEM;
1190 goto cq_free_resources;
1191 }
1192 ukinfo->cq_base = iwcq->kmem.va;
1193 info.cq_base_pa = iwcq->kmem.pa;
1194 info.shadow_area_pa = info.cq_base_pa + rsize;
1195 ukinfo->shadow_area = iwcq->kmem.va + rsize;
1196 }
1197
1198 if (dev->iw_priv_cq_ops->cq_init(cq, &info)) {
1199 i40iw_pr_err("init cq fail\n");
1200 err_code = -EPROTO;
1201 goto cq_free_resources;
1202 }
1203
1204 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
1205 if (!cqp_request) {
1206 err_code = -ENOMEM;
1207 goto cq_free_resources;
1208 }
1209
1210 cqp_info = &cqp_request->info;
1211 cqp_info->cqp_cmd = OP_CQ_CREATE;
1212 cqp_info->post_sq = 1;
1213 cqp_info->in.u.cq_create.cq = cq;
1214 cqp_info->in.u.cq_create.scratch = (uintptr_t)cqp_request;
1215 status = i40iw_handle_cqp_op(iwdev, cqp_request);
1216 if (status) {
1217 i40iw_pr_err("CQP-OP Create QP fail");
1218 err_code = -EPROTO;
1219 goto cq_free_resources;
1220 }
1221
1222 if (context) {
1223 struct i40iw_create_cq_resp resp;
1224
1225 memset(&resp, 0, sizeof(resp));
1226 resp.cq_id = info.cq_uk_init_info.cq_id;
1227 resp.cq_size = info.cq_uk_init_info.cq_size;
1228 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1229 i40iw_pr_err("copy to user data\n");
1230 err_code = -EPROTO;
1231 goto cq_destroy;
1232 }
1233 }
1234
1235 return (struct ib_cq *)iwcq;
1236
1237cq_destroy:
1238 cq_wq_destroy(iwdev, cq);
1239cq_free_resources:
1240 cq_free_resources(iwdev, iwcq);
1241error:
1242 kfree(iwcq);
1243 return ERR_PTR(err_code);
1244}
1245
1246/**
1247 * i40iw_get_user_access - get hw access from IB access
1248 * @acc: IB access to return hw access
1249 */
1250static inline u16 i40iw_get_user_access(int acc)
1251{
1252 u16 access = 0;
1253
1254 access |= (acc & IB_ACCESS_LOCAL_WRITE) ? I40IW_ACCESS_FLAGS_LOCALWRITE : 0;
1255 access |= (acc & IB_ACCESS_REMOTE_WRITE) ? I40IW_ACCESS_FLAGS_REMOTEWRITE : 0;
1256 access |= (acc & IB_ACCESS_REMOTE_READ) ? I40IW_ACCESS_FLAGS_REMOTEREAD : 0;
1257 access |= (acc & IB_ACCESS_MW_BIND) ? I40IW_ACCESS_FLAGS_BIND_WINDOW : 0;
1258 return access;
1259}
1260
1261/**
1262 * i40iw_free_stag - free stag resource
1263 * @iwdev: iwarp device
1264 * @stag: stag to free
1265 */
1266static void i40iw_free_stag(struct i40iw_device *iwdev, u32 stag)
1267{
1268 u32 stag_idx;
1269
1270 stag_idx = (stag & iwdev->mr_stagmask) >> I40IW_CQPSQ_STAG_IDX_SHIFT;
1271 i40iw_free_resource(iwdev, iwdev->allocated_mrs, stag_idx);
1272}
1273
1274/**
1275 * i40iw_create_stag - create random stag
1276 * @iwdev: iwarp device
1277 */
1278static u32 i40iw_create_stag(struct i40iw_device *iwdev)
1279{
1280 u32 stag = 0;
1281 u32 stag_index = 0;
1282 u32 next_stag_index;
1283 u32 driver_key;
1284 u32 random;
1285 u8 consumer_key;
1286 int ret;
1287
1288 get_random_bytes(&random, sizeof(random));
1289 consumer_key = (u8)random;
1290
1291 driver_key = random & ~iwdev->mr_stagmask;
1292 next_stag_index = (random & iwdev->mr_stagmask) >> 8;
1293 next_stag_index %= iwdev->max_mr;
1294
1295 ret = i40iw_alloc_resource(iwdev,
1296 iwdev->allocated_mrs, iwdev->max_mr,
1297 &stag_index, &next_stag_index);
1298 if (!ret) {
1299 stag = stag_index << I40IW_CQPSQ_STAG_IDX_SHIFT;
1300 stag |= driver_key;
1301 stag += (u32)consumer_key;
1302 }
1303 return stag;
1304}
1305
1306/**
1307 * i40iw_next_pbl_addr - Get next pbl address
1308 * @palloc: Poiner to allocated pbles
1309 * @pbl: pointer to a pble
1310 * @pinfo: info pointer
1311 * @idx: index
1312 */
1313static inline u64 *i40iw_next_pbl_addr(struct i40iw_pble_alloc *palloc,
1314 u64 *pbl,
1315 struct i40iw_pble_info **pinfo,
1316 u32 *idx)
1317{
1318 *idx += 1;
1319 if ((!(*pinfo)) || (*idx != (*pinfo)->cnt))
1320 return ++pbl;
1321 *idx = 0;
1322 (*pinfo)++;
1323 return (u64 *)(*pinfo)->addr;
1324}
1325
1326/**
1327 * i40iw_copy_user_pgaddrs - copy user page address to pble's os locally
1328 * @iwmr: iwmr for IB's user page addresses
1329 * @pbl: ple pointer to save 1 level or 0 level pble
1330 * @level: indicated level 0, 1 or 2
1331 */
1332static void i40iw_copy_user_pgaddrs(struct i40iw_mr *iwmr,
1333 u64 *pbl,
1334 enum i40iw_pble_level level)
1335{
1336 struct ib_umem *region = iwmr->region;
1337 struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
1338 int chunk_pages, entry, pg_shift, i;
1339 struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
1340 struct i40iw_pble_info *pinfo;
1341 struct scatterlist *sg;
1342 u32 idx = 0;
1343
1344 pinfo = (level == I40IW_LEVEL_1) ? NULL : palloc->level2.leaf;
1345 pg_shift = ffs(region->page_size) - 1;
1346 for_each_sg(region->sg_head.sgl, sg, region->nmap, entry) {
1347 chunk_pages = sg_dma_len(sg) >> pg_shift;
1348 if ((iwmr->type == IW_MEMREG_TYPE_QP) &&
1349 !iwpbl->qp_mr.sq_page)
1350 iwpbl->qp_mr.sq_page = sg_page(sg);
1351 for (i = 0; i < chunk_pages; i++) {
1352 *pbl = cpu_to_le64(sg_dma_address(sg) + region->page_size * i);
1353 pbl = i40iw_next_pbl_addr(palloc, pbl, &pinfo, &idx);
1354 }
1355 }
1356}
1357
b6a529da
HO		 1358/**
1359 * i40iw_check_mem_contiguous - check if pbls stored in arr are contiguous
1360 * @arr: lvl1 pbl array
1361 * @npages: page count
1362 * pg_size: page size
1363 *
1364 */
1365static bool i40iw_check_mem_contiguous(u64 *arr, u32 npages, u32 pg_size)
1366{
1367 u32 pg_idx;
1368
1369 for (pg_idx = 0; pg_idx < npages; pg_idx++) {
1370 if ((*arr + (pg_size * pg_idx)) != arr[pg_idx])
1371 return false;
1372 }
1373 return true;
1374}
1375
1376/**
1377 * i40iw_check_mr_contiguous - check if MR is physically contiguous
1378 * @palloc: pbl allocation struct
1379 * pg_size: page size
1380 */
1381static bool i40iw_check_mr_contiguous(struct i40iw_pble_alloc *palloc, u32 pg_size)
1382{
1383 struct i40iw_pble_level2 *lvl2 = &palloc->level2;
1384 struct i40iw_pble_info *leaf = lvl2->leaf;
1385 u64 *arr = NULL;
1386 u64 *start_addr = NULL;
1387 int i;
1388 bool ret;
1389
1390 if (palloc->level == I40IW_LEVEL_1) {
1391 arr = (u64 *)palloc->level1.addr;
1392 ret = i40iw_check_mem_contiguous(arr, palloc->total_cnt, pg_size);
1393 return ret;
1394 }
1395
1396 start_addr = (u64 *)leaf->addr;
1397
1398 for (i = 0; i < lvl2->leaf_cnt; i++, leaf++) {
1399 arr = (u64 *)leaf->addr;
1400 if ((*start_addr + (i * pg_size * PBLE_PER_PAGE)) != *arr)
1401 return false;
1402 ret = i40iw_check_mem_contiguous(arr, leaf->cnt, pg_size);
1403 if (!ret)
1404 return false;
1405 }
1406
1407 return true;
1408}
1409
d3749841
FL		 1410/**
1411 * i40iw_setup_pbles - copy user pg address to pble's
1412 * @iwdev: iwarp device
1413 * @iwmr: mr pointer for this memory registration
b6a529da 1414 * @use_pbles: flag if to use pble's
d3749841
FL		 1415 */
1416static int i40iw_setup_pbles(struct i40iw_device *iwdev,
1417 struct i40iw_mr *iwmr,
1418 bool use_pbles)
1419{
1420 struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
1421 struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
1422 struct i40iw_pble_info *pinfo;
1423 u64 *pbl;
1424 enum i40iw_status_code status;
1425 enum i40iw_pble_level level = I40IW_LEVEL_1;
1426
d3749841
FL		 1427 if (use_pbles) {
1428 mutex_lock(&iwdev->pbl_mutex);
1429 status = i40iw_get_pble(&iwdev->sc_dev, iwdev->pble_rsrc, palloc, iwmr->page_cnt);
1430 mutex_unlock(&iwdev->pbl_mutex);
1431 if (status)
1432 return -ENOMEM;
1433
1434 iwpbl->pbl_allocated = true;
1435 level = palloc->level;
1436 pinfo = (level == I40IW_LEVEL_1) ? &palloc->level1 : palloc->level2.leaf;
1437 pbl = (u64 *)pinfo->addr;
1438 } else {
1439 pbl = iwmr->pgaddrmem;
1440 }
1441
1442 i40iw_copy_user_pgaddrs(iwmr, pbl, level);
b6a529da
HO		 1443
1444 if (use_pbles)
1445 iwmr->pgaddrmem[0] = *pbl;
1446
d3749841
FL		 1447 return 0;
1448}
1449
1450/**
1451 * i40iw_handle_q_mem - handle memory for qp and cq
1452 * @iwdev: iwarp device
1453 * @req: information for q memory management
1454 * @iwpbl: pble struct
1455 * @use_pbles: flag to use pble
1456 */
1457static int i40iw_handle_q_mem(struct i40iw_device *iwdev,
1458 struct i40iw_mem_reg_req *req,
1459 struct i40iw_pbl *iwpbl,
1460 bool use_pbles)
1461{
1462 struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
1463 struct i40iw_mr *iwmr = iwpbl->iwmr;
1464 struct i40iw_qp_mr *qpmr = &iwpbl->qp_mr;
1465 struct i40iw_cq_mr *cqmr = &iwpbl->cq_mr;
1466 struct i40iw_hmc_pble *hmc_p;
1467 u64 *arr = iwmr->pgaddrmem;
b6a529da 1468 u32 pg_size;
d3749841
FL		 1469 int err;
1470 int total;
b6a529da 1471 bool ret = true;
d3749841
FL		 1472
1473 total = req->sq_pages + req->rq_pages + req->cq_pages;
b6a529da 1474 pg_size = iwmr->region->page_size;
d3749841
FL		 1475
1476 err = i40iw_setup_pbles(iwdev, iwmr, use_pbles);
1477 if (err)
1478 return err;
b6a529da 1479
d3749841
FL		 1480 if (use_pbles && (palloc->level != I40IW_LEVEL_1)) {
1481 i40iw_free_pble(iwdev->pble_rsrc, palloc);
1482 iwpbl->pbl_allocated = false;
1483 return -ENOMEM;
1484 }
1485
1486 if (use_pbles)
1487 arr = (u64 *)palloc->level1.addr;
b6a529da
HO		 1488
1489 if (iwmr->type == IW_MEMREG_TYPE_QP) {
d3749841
FL		 1490 hmc_p = &qpmr->sq_pbl;
1491 qpmr->shadow = (dma_addr_t)arr[total];
b6a529da 1492
d3749841 1493 if (use_pbles) {
b6a529da
HO		 1494 ret = i40iw_check_mem_contiguous(arr, req->sq_pages, pg_size);
1495 if (ret)
1496 ret = i40iw_check_mem_contiguous(&arr[req->sq_pages], req->rq_pages, pg_size);
1497 }
1498
1499 if (!ret) {
d3749841
FL		 1500 hmc_p->idx = palloc->level1.idx;
1501 hmc_p = &qpmr->rq_pbl;
1502 hmc_p->idx = palloc->level1.idx + req->sq_pages;
1503 } else {
1504 hmc_p->addr = arr[0];
1505 hmc_p = &qpmr->rq_pbl;
b6a529da 1506 hmc_p->addr = arr[req->sq_pages];
d3749841
FL		 1507 }
1508 } else { /* CQ */
1509 hmc_p = &cqmr->cq_pbl;
1510 cqmr->shadow = (dma_addr_t)arr[total];
b6a529da 1511
d3749841 1512 if (use_pbles)
b6a529da
HO		 1513 ret = i40iw_check_mem_contiguous(arr, req->cq_pages, pg_size);
1514
1515 if (!ret)
d3749841
FL		 1516 hmc_p->idx = palloc->level1.idx;
1517 else
1518 hmc_p->addr = arr[0];
1519 }
b6a529da
HO		 1520
1521 if (use_pbles && ret) {
1522 i40iw_free_pble(iwdev->pble_rsrc, palloc);
1523 iwpbl->pbl_allocated = false;
1524 }
1525
d3749841
FL		 1526 return err;
1527}
1528
b7aee855
IM		 1529/**
1530 * i40iw_hw_alloc_stag - cqp command to allocate stag
1531 * @iwdev: iwarp device
1532 * @iwmr: iwarp mr pointer
1533 */
1534static int i40iw_hw_alloc_stag(struct i40iw_device *iwdev, struct i40iw_mr *iwmr)
1535{
1536 struct i40iw_allocate_stag_info *info;
1537 struct i40iw_pd *iwpd = to_iwpd(iwmr->ibmr.pd);
1538 enum i40iw_status_code status;
1539 int err = 0;
1540 struct i40iw_cqp_request *cqp_request;
1541 struct cqp_commands_info *cqp_info;
1542
1543 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
1544 if (!cqp_request)
1545 return -ENOMEM;
1546
1547 cqp_info = &cqp_request->info;
1548 info = &cqp_info->in.u.alloc_stag.info;
1549 memset(info, 0, sizeof(*info));
1550 info->page_size = PAGE_SIZE;
1551 info->stag_idx = iwmr->stag >> I40IW_CQPSQ_STAG_IDX_SHIFT;
1552 info->pd_id = iwpd->sc_pd.pd_id;
1553 info->total_len = iwmr->length;
8e0e7aed 1554 info->remote_access = true;
b7aee855
IM		 1555 cqp_info->cqp_cmd = OP_ALLOC_STAG;
1556 cqp_info->post_sq = 1;
1557 cqp_info->in.u.alloc_stag.dev = &iwdev->sc_dev;
1558 cqp_info->in.u.alloc_stag.scratch = (uintptr_t)cqp_request;
1559
1560 status = i40iw_handle_cqp_op(iwdev, cqp_request);
1561 if (status) {
1562 err = -ENOMEM;
1563 i40iw_pr_err("CQP-OP MR Reg fail");
1564 }
1565 return err;
1566}
1567
1568/**
1569 * i40iw_alloc_mr - register stag for fast memory registration
1570 * @pd: ibpd pointer
1571 * @mr_type: memory for stag registrion
1572 * @max_num_sg: man number of pages
1573 */
1574static struct ib_mr *i40iw_alloc_mr(struct ib_pd *pd,
1575 enum ib_mr_type mr_type,
1576 u32 max_num_sg)
1577{
1578 struct i40iw_pd *iwpd = to_iwpd(pd);
1579 struct i40iw_device *iwdev = to_iwdev(pd->device);
1580 struct i40iw_pble_alloc *palloc;
1581 struct i40iw_pbl *iwpbl;
1582 struct i40iw_mr *iwmr;
1583 enum i40iw_status_code status;
1584 u32 stag;
1585 int err_code = -ENOMEM;
1586
1587 iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
1588 if (!iwmr)
1589 return ERR_PTR(-ENOMEM);
1590
1591 stag = i40iw_create_stag(iwdev);
1592 if (!stag) {
1593 err_code = -EOVERFLOW;
1594 goto err;
1595 }
1596 iwmr->stag = stag;
1597 iwmr->ibmr.rkey = stag;
1598 iwmr->ibmr.lkey = stag;
1599 iwmr->ibmr.pd = pd;
1600 iwmr->ibmr.device = pd->device;
1601 iwpbl = &iwmr->iwpbl;
1602 iwpbl->iwmr = iwmr;
1603 iwmr->type = IW_MEMREG_TYPE_MEM;
1604 palloc = &iwpbl->pble_alloc;
1605 iwmr->page_cnt = max_num_sg;
1606 mutex_lock(&iwdev->pbl_mutex);
1607 status = i40iw_get_pble(&iwdev->sc_dev, iwdev->pble_rsrc, palloc, iwmr->page_cnt);
1608 mutex_unlock(&iwdev->pbl_mutex);
ee23abd7 1609 if (status)
b7aee855
IM		 1610 goto err1;
1611
1612 if (palloc->level != I40IW_LEVEL_1)
1613 goto err2;
1614 err_code = i40iw_hw_alloc_stag(iwdev, iwmr);
1615 if (err_code)
1616 goto err2;
1617 iwpbl->pbl_allocated = true;
1618 i40iw_add_pdusecount(iwpd);
1619 return &iwmr->ibmr;
1620err2:
1621 i40iw_free_pble(iwdev->pble_rsrc, palloc);
1622err1:
1623 i40iw_free_stag(iwdev, stag);
1624err:
1625 kfree(iwmr);
1626 return ERR_PTR(err_code);
1627}
1628
1629/**
1630 * i40iw_set_page - populate pbl list for fmr
1631 * @ibmr: ib mem to access iwarp mr pointer
1632 * @addr: page dma address fro pbl list
1633 */
1634static int i40iw_set_page(struct ib_mr *ibmr, u64 addr)
1635{
1636 struct i40iw_mr *iwmr = to_iwmr(ibmr);
1637 struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
1638 struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
1639 u64 *pbl;
1640
1641 if (unlikely(iwmr->npages == iwmr->page_cnt))
1642 return -ENOMEM;
1643
1644 pbl = (u64 *)palloc->level1.addr;
1645 pbl[iwmr->npages++] = cpu_to_le64(addr);
1646 return 0;
1647}
1648
1649/**
1650 * i40iw_map_mr_sg - map of sg list for fmr
1651 * @ibmr: ib mem to access iwarp mr pointer
1652 * @sg: scatter gather list for fmr
1653 * @sg_nents: number of sg pages
1654 */
ff2ba993 1655static int i40iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg,
9aa8b321 1656 int sg_nents, unsigned int *sg_offset)
b7aee855
IM		 1657{
1658 struct i40iw_mr *iwmr = to_iwmr(ibmr);
1659
1660 iwmr->npages = 0;
ff2ba993 1661 return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, i40iw_set_page);
b7aee855
IM		 1662}
1663
c2b75ef7
IM		 1664/**
1665 * i40iw_drain_sq - drain the send queue
1666 * @ibqp: ib qp pointer
1667 */
1668static void i40iw_drain_sq(struct ib_qp *ibqp)
1669{
1670 struct i40iw_qp *iwqp = to_iwqp(ibqp);
1671 struct i40iw_sc_qp *qp = &iwqp->sc_qp;
1672
1673 if (I40IW_RING_MORE_WORK(qp->qp_uk.sq_ring))
1674 wait_for_completion(&iwqp->sq_drained);
1675}
1676
1677/**
1678 * i40iw_drain_rq - drain the receive queue
1679 * @ibqp: ib qp pointer
1680 */
1681static void i40iw_drain_rq(struct ib_qp *ibqp)
1682{
1683 struct i40iw_qp *iwqp = to_iwqp(ibqp);
1684 struct i40iw_sc_qp *qp = &iwqp->sc_qp;
1685
1686 if (I40IW_RING_MORE_WORK(qp->qp_uk.rq_ring))
1687 wait_for_completion(&iwqp->rq_drained);
1688}
1689
d3749841
FL		 1690/**
1691 * i40iw_hwreg_mr - send cqp command for memory registration
1692 * @iwdev: iwarp device
1693 * @iwmr: iwarp mr pointer
1694 * @access: access for MR
1695 */
1696static int i40iw_hwreg_mr(struct i40iw_device *iwdev,
1697 struct i40iw_mr *iwmr,
1698 u16 access)
1699{
1700 struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
1701 struct i40iw_reg_ns_stag_info *stag_info;
1702 struct i40iw_pd *iwpd = to_iwpd(iwmr->ibmr.pd);
1703 struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
1704 enum i40iw_status_code status;
1705 int err = 0;
1706 struct i40iw_cqp_request *cqp_request;
1707 struct cqp_commands_info *cqp_info;
1708
1709 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
1710 if (!cqp_request)
1711 return -ENOMEM;
1712
1713 cqp_info = &cqp_request->info;
1714 stag_info = &cqp_info->in.u.mr_reg_non_shared.info;
1715 memset(stag_info, 0, sizeof(*stag_info));
1716 stag_info->va = (void *)(unsigned long)iwpbl->user_base;
1717 stag_info->stag_idx = iwmr->stag >> I40IW_CQPSQ_STAG_IDX_SHIFT;
1718 stag_info->stag_key = (u8)iwmr->stag;
1719 stag_info->total_len = iwmr->length;
1720 stag_info->access_rights = access;
1721 stag_info->pd_id = iwpd->sc_pd.pd_id;
1722 stag_info->addr_type = I40IW_ADDR_TYPE_VA_BASED;
1723
b6a529da 1724 if (iwpbl->pbl_allocated) {
d3749841
FL		 1725 if (palloc->level == I40IW_LEVEL_1) {
1726 stag_info->first_pm_pbl_index = palloc->level1.idx;
1727 stag_info->chunk_size = 1;
1728 } else {
1729 stag_info->first_pm_pbl_index = palloc->level2.root.idx;
1730 stag_info->chunk_size = 3;
1731 }
1732 } else {
1733 stag_info->reg_addr_pa = iwmr->pgaddrmem[0];
1734 }
1735
1736 cqp_info->cqp_cmd = OP_MR_REG_NON_SHARED;
1737 cqp_info->post_sq = 1;
1738 cqp_info->in.u.mr_reg_non_shared.dev = &iwdev->sc_dev;
1739 cqp_info->in.u.mr_reg_non_shared.scratch = (uintptr_t)cqp_request;
1740
1741 status = i40iw_handle_cqp_op(iwdev, cqp_request);
1742 if (status) {
1743 err = -ENOMEM;
1744 i40iw_pr_err("CQP-OP MR Reg fail");
1745 }
1746 return err;
1747}
1748
1749/**
1750 * i40iw_reg_user_mr - Register a user memory region
1751 * @pd: ptr of pd
1752 * @start: virtual start address
1753 * @length: length of mr
1754 * @virt: virtual address
1755 * @acc: access of mr
1756 * @udata: user data
1757 */
1758static struct ib_mr *i40iw_reg_user_mr(struct ib_pd *pd,
1759 u64 start,
1760 u64 length,
1761 u64 virt,
1762 int acc,
1763 struct ib_udata *udata)
1764{
1765 struct i40iw_pd *iwpd = to_iwpd(pd);
1766 struct i40iw_device *iwdev = to_iwdev(pd->device);
1767 struct i40iw_ucontext *ucontext;
1768 struct i40iw_pble_alloc *palloc;
1769 struct i40iw_pbl *iwpbl;
1770 struct i40iw_mr *iwmr;
1771 struct ib_umem *region;
1772 struct i40iw_mem_reg_req req;
6b900365 1773 u64 pbl_depth = 0;
d3749841
FL		 1774 u32 stag = 0;
1775 u16 access;
6b900365 1776 u64 region_length;
d3749841
FL		 1777 bool use_pbles = false;
1778 unsigned long flags;
1779 int err = -ENOSYS;
b6a529da 1780 int ret;
d3749841 1781
6b900365
IM		 1782 if (length > I40IW_MAX_MR_SIZE)
1783 return ERR_PTR(-EINVAL);
d3749841
FL		 1784 region = ib_umem_get(pd->uobject->context, start, length, acc, 0);
1785 if (IS_ERR(region))
1786 return (struct ib_mr *)region;
1787
1788 if (ib_copy_from_udata(&req, udata, sizeof(req))) {
1789 ib_umem_release(region);
1790 return ERR_PTR(-EFAULT);
1791 }
1792
1793 iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
1794 if (!iwmr) {
1795 ib_umem_release(region);
1796 return ERR_PTR(-ENOMEM);
1797 }
1798
1799 iwpbl = &iwmr->iwpbl;
1800 iwpbl->iwmr = iwmr;
1801 iwmr->region = region;
1802 iwmr->ibmr.pd = pd;
1803 iwmr->ibmr.device = pd->device;
1804 ucontext = to_ucontext(pd->uobject->context);
1805 region_length = region->length + (start & 0xfff);
1806 pbl_depth = region_length >> 12;
1807 pbl_depth += (region_length & (4096 - 1)) ? 1 : 0;
1808 iwmr->length = region->length;
1809
1810 iwpbl->user_base = virt;
1811 palloc = &iwpbl->pble_alloc;
1812
1813 iwmr->type = req.reg_type;
6b900365 1814 iwmr->page_cnt = (u32)pbl_depth;
d3749841
FL		 1815
1816 switch (req.reg_type) {
1817 case IW_MEMREG_TYPE_QP:
1818 use_pbles = ((req.sq_pages + req.rq_pages) > 2);
1819 err = i40iw_handle_q_mem(iwdev, &req, iwpbl, use_pbles);
1820 if (err)
1821 goto error;
1822 spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
1823 list_add_tail(&iwpbl->list, &ucontext->qp_reg_mem_list);
1824 spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
1825 break;
1826 case IW_MEMREG_TYPE_CQ:
1827 use_pbles = (req.cq_pages > 1);
1828 err = i40iw_handle_q_mem(iwdev, &req, iwpbl, use_pbles);
1829 if (err)
1830 goto error;
1831
1832 spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
1833 list_add_tail(&iwpbl->list, &ucontext->cq_reg_mem_list);
1834 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
1835 break;
1836 case IW_MEMREG_TYPE_MEM:
b6a529da 1837 use_pbles = (iwmr->page_cnt != 1);
d3749841
FL		 1838 access = I40IW_ACCESS_FLAGS_LOCALREAD;
1839
d3749841
FL		 1840 err = i40iw_setup_pbles(iwdev, iwmr, use_pbles);
1841 if (err)
1842 goto error;
1843
b6a529da
HO		 1844 if (use_pbles) {
1845 ret = i40iw_check_mr_contiguous(palloc, region->page_size);
1846 if (ret) {
1847 i40iw_free_pble(iwdev->pble_rsrc, palloc);
1848 iwpbl->pbl_allocated = false;
1849 }
1850 }
1851
d3749841
FL		 1852 access |= i40iw_get_user_access(acc);
1853 stag = i40iw_create_stag(iwdev);
1854 if (!stag) {
1855 err = -ENOMEM;
1856 goto error;
1857 }
1858
1859 iwmr->stag = stag;
1860 iwmr->ibmr.rkey = stag;
1861 iwmr->ibmr.lkey = stag;
1862
1863 err = i40iw_hwreg_mr(iwdev, iwmr, access);
1864 if (err) {
1865 i40iw_free_stag(iwdev, stag);
1866 goto error;
1867 }
1868 break;
1869 default:
1870 goto error;
1871 }
1872
1873 iwmr->type = req.reg_type;
1874 if (req.reg_type == IW_MEMREG_TYPE_MEM)
1875 i40iw_add_pdusecount(iwpd);
1876 return &iwmr->ibmr;
1877
1878error:
b6a529da 1879 if (palloc->level != I40IW_LEVEL_0 && iwpbl->pbl_allocated)
d3749841
FL		 1880 i40iw_free_pble(iwdev->pble_rsrc, palloc);
1881 ib_umem_release(region);
1882 kfree(iwmr);
1883 return ERR_PTR(err);
1884}
1885
1886/**
1887 * i40iw_reg_phys_mr - register kernel physical memory
1888 * @pd: ibpd pointer
1889 * @addr: physical address of memory to register
1890 * @size: size of memory to register
1891 * @acc: Access rights
1892 * @iova_start: start of virtual address for physical buffers
1893 */
1894struct ib_mr *i40iw_reg_phys_mr(struct ib_pd *pd,
1895 u64 addr,
1896 u64 size,
1897 int acc,
1898 u64 *iova_start)
1899{
1900 struct i40iw_pd *iwpd = to_iwpd(pd);
1901 struct i40iw_device *iwdev = to_iwdev(pd->device);
1902 struct i40iw_pbl *iwpbl;
1903 struct i40iw_mr *iwmr;
1904 enum i40iw_status_code status;
1905 u32 stag;
1906 u16 access = I40IW_ACCESS_FLAGS_LOCALREAD;
1907 int ret;
1908
1909 iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
1910 if (!iwmr)
1911 return ERR_PTR(-ENOMEM);
1912 iwmr->ibmr.pd = pd;
1913 iwmr->ibmr.device = pd->device;
1914 iwpbl = &iwmr->iwpbl;
1915 iwpbl->iwmr = iwmr;
1916 iwmr->type = IW_MEMREG_TYPE_MEM;
1917 iwpbl->user_base = *iova_start;
1918 stag = i40iw_create_stag(iwdev);
1919 if (!stag) {
1920 ret = -EOVERFLOW;
1921 goto err;
1922 }
1923 access |= i40iw_get_user_access(acc);
1924 iwmr->stag = stag;
1925 iwmr->ibmr.rkey = stag;
1926 iwmr->ibmr.lkey = stag;
1927 iwmr->page_cnt = 1;
1928 iwmr->pgaddrmem[0] = addr;
342c387b 1929 iwmr->length = size;
d3749841
FL		 1930 status = i40iw_hwreg_mr(iwdev, iwmr, access);
1931 if (status) {
1932 i40iw_free_stag(iwdev, stag);
1933 ret = -ENOMEM;
1934 goto err;
1935 }
1936
1937 i40iw_add_pdusecount(iwpd);
1938 return &iwmr->ibmr;
1939 err:
1940 kfree(iwmr);
1941 return ERR_PTR(ret);
1942}
1943
1944/**
1945 * i40iw_get_dma_mr - register physical mem
1946 * @pd: ptr of pd
1947 * @acc: access for memory
1948 */
1949static struct ib_mr *i40iw_get_dma_mr(struct ib_pd *pd, int acc)
1950{
1951 u64 kva = 0;
1952
342c387b 1953 return i40iw_reg_phys_mr(pd, 0, 0, acc, &kva);
d3749841
FL		 1954}
1955
1956/**
1957 * i40iw_del_mem_list - Deleting pbl list entries for CQ/QP
1958 * @iwmr: iwmr for IB's user page addresses
1959 * @ucontext: ptr to user context
1960 */
1961static void i40iw_del_memlist(struct i40iw_mr *iwmr,
1962 struct i40iw_ucontext *ucontext)
1963{
1964 struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
1965 unsigned long flags;
1966
1967 switch (iwmr->type) {
1968 case IW_MEMREG_TYPE_CQ:
1969 spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
1970 if (!list_empty(&ucontext->cq_reg_mem_list))
1971 list_del(&iwpbl->list);
1972 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
1973 break;
1974 case IW_MEMREG_TYPE_QP:
1975 spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
1976 if (!list_empty(&ucontext->qp_reg_mem_list))
1977 list_del(&iwpbl->list);
1978 spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
1979 break;
1980 default:
1981 break;
1982 }
1983}
1984
1985/**
1986 * i40iw_dereg_mr - deregister mr
1987 * @ib_mr: mr ptr for dereg
1988 */
1989static int i40iw_dereg_mr(struct ib_mr *ib_mr)
1990{
1991 struct ib_pd *ibpd = ib_mr->pd;
1992 struct i40iw_pd *iwpd = to_iwpd(ibpd);
1993 struct i40iw_mr *iwmr = to_iwmr(ib_mr);
1994 struct i40iw_device *iwdev = to_iwdev(ib_mr->device);
1995 enum i40iw_status_code status;
1996 struct i40iw_dealloc_stag_info *info;
1997 struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
1998 struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
1999 struct i40iw_cqp_request *cqp_request;
2000 struct cqp_commands_info *cqp_info;
2001 u32 stag_idx;
2002
2003 if (iwmr->region)
2004 ib_umem_release(iwmr->region);
2005
2006 if (iwmr->type != IW_MEMREG_TYPE_MEM) {
2007 if (ibpd->uobject) {
2008 struct i40iw_ucontext *ucontext;
2009
2010 ucontext = to_ucontext(ibpd->uobject->context);
2011 i40iw_del_memlist(iwmr, ucontext);
2012 }
2013 if (iwpbl->pbl_allocated)
2014 i40iw_free_pble(iwdev->pble_rsrc, palloc);
433c5813 2015 kfree(iwmr);
d3749841
FL		 2016 return 0;
2017 }
2018
2019 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
2020 if (!cqp_request)
2021 return -ENOMEM;
2022
2023 cqp_info = &cqp_request->info;
2024 info = &cqp_info->in.u.dealloc_stag.info;
2025 memset(info, 0, sizeof(*info));
2026
2027 info->pd_id = cpu_to_le32(iwpd->sc_pd.pd_id & 0x00007fff);
2028 info->stag_idx = RS_64_1(ib_mr->rkey, I40IW_CQPSQ_STAG_IDX_SHIFT);
2029 stag_idx = info->stag_idx;
2030 info->mr = true;
2031 if (iwpbl->pbl_allocated)
2032 info->dealloc_pbl = true;
2033
2034 cqp_info->cqp_cmd = OP_DEALLOC_STAG;
2035 cqp_info->post_sq = 1;
2036 cqp_info->in.u.dealloc_stag.dev = &iwdev->sc_dev;
2037 cqp_info->in.u.dealloc_stag.scratch = (uintptr_t)cqp_request;
2038 status = i40iw_handle_cqp_op(iwdev, cqp_request);
2039 if (status)
2040 i40iw_pr_err("CQP-OP dealloc failed for stag_idx = 0x%x\n", stag_idx);
2041 i40iw_rem_pdusecount(iwpd, iwdev);
2042 i40iw_free_stag(iwdev, iwmr->stag);
2043 if (iwpbl->pbl_allocated)
2044 i40iw_free_pble(iwdev->pble_rsrc, palloc);
2045 kfree(iwmr);
2046 return 0;
2047}
2048
2049/**
2050 * i40iw_show_rev
2051 */
2052static ssize_t i40iw_show_rev(struct device *dev,
2053 struct device_attribute *attr, char *buf)
2054{
2055 struct i40iw_ib_device *iwibdev = container_of(dev,
2056 struct i40iw_ib_device,
2057 ibdev.dev);
2058 u32 hw_rev = iwibdev->iwdev->sc_dev.hw_rev;
2059
2060 return sprintf(buf, "%x\n", hw_rev);
2061}
2062
d3749841
FL		 2063/**
2064 * i40iw_show_hca
2065 */
2066static ssize_t i40iw_show_hca(struct device *dev,
2067 struct device_attribute *attr, char *buf)
2068{
2069 return sprintf(buf, "I40IW\n");
2070}
2071
2072/**
2073 * i40iw_show_board
2074 */
2075static ssize_t i40iw_show_board(struct device *dev,
2076 struct device_attribute *attr,
2077 char *buf)
2078{
2079 return sprintf(buf, "%.*s\n", 32, "I40IW Board ID");
2080}
2081
2082static DEVICE_ATTR(hw_rev, S_IRUGO, i40iw_show_rev, NULL);
d3749841
FL		 2083static DEVICE_ATTR(hca_type, S_IRUGO, i40iw_show_hca, NULL);
2084static DEVICE_ATTR(board_id, S_IRUGO, i40iw_show_board, NULL);
2085
2086static struct device_attribute *i40iw_dev_attributes[] = {
2087 &dev_attr_hw_rev,
d3749841
FL		 2088 &dev_attr_hca_type,
2089 &dev_attr_board_id
2090};
2091
2092/**
2093 * i40iw_copy_sg_list - copy sg list for qp
2094 * @sg_list: copied into sg_list
2095 * @sgl: copy from sgl
2096 * @num_sges: count of sg entries
2097 */
2098static void i40iw_copy_sg_list(struct i40iw_sge *sg_list, struct ib_sge *sgl, int num_sges)
2099{
2100 unsigned int i;
2101
2102 for (i = 0; (i < num_sges) && (i < I40IW_MAX_WQ_FRAGMENT_COUNT); i++) {
2103 sg_list[i].tag_off = sgl[i].addr;
2104 sg_list[i].len = sgl[i].length;
2105 sg_list[i].stag = sgl[i].lkey;
2106 }
2107}
2108
2109/**
2110 * i40iw_post_send - kernel application wr
2111 * @ibqp: qp ptr for wr
2112 * @ib_wr: work request ptr
2113 * @bad_wr: return of bad wr if err
2114 */
2115static int i40iw_post_send(struct ib_qp *ibqp,
2116 struct ib_send_wr *ib_wr,
2117 struct ib_send_wr **bad_wr)
2118{
2119 struct i40iw_qp *iwqp;
2120 struct i40iw_qp_uk *ukqp;
2121 struct i40iw_post_sq_info info;
2122 enum i40iw_status_code ret;
2123 int err = 0;
2124 unsigned long flags;
b7aee855 2125 bool inv_stag;
d3749841
FL		 2126
2127 iwqp = (struct i40iw_qp *)ibqp;
2128 ukqp = &iwqp->sc_qp.qp_uk;
2129
2130 spin_lock_irqsave(&iwqp->lock, flags);
2131 while (ib_wr) {
b7aee855 2132 inv_stag = false;
d3749841
FL		 2133 memset(&info, 0, sizeof(info));
2134 info.wr_id = (u64)(ib_wr->wr_id);
2135 if ((ib_wr->send_flags & IB_SEND_SIGNALED) || iwqp->sig_all)
2136 info.signaled = true;
2137 if (ib_wr->send_flags & IB_SEND_FENCE)
2138 info.read_fence = true;
2139
2140 switch (ib_wr->opcode) {
2141 case IB_WR_SEND:
b7aee855
IM		 2142 /* fall-through */
2143 case IB_WR_SEND_WITH_INV:
2144 if (ib_wr->opcode == IB_WR_SEND) {
2145 if (ib_wr->send_flags & IB_SEND_SOLICITED)
2146 info.op_type = I40IW_OP_TYPE_SEND_SOL;
2147 else
2148 info.op_type = I40IW_OP_TYPE_SEND;
2149 } else {
2150 if (ib_wr->send_flags & IB_SEND_SOLICITED)
2151 info.op_type = I40IW_OP_TYPE_SEND_SOL_INV;
2152 else
2153 info.op_type = I40IW_OP_TYPE_SEND_INV;
2154 }
d3749841
FL		 2155
2156 if (ib_wr->send_flags & IB_SEND_INLINE) {
2157 info.op.inline_send.data = (void *)(unsigned long)ib_wr->sg_list[0].addr;
2158 info.op.inline_send.len = ib_wr->sg_list[0].length;
b7aee855 2159 ret = ukqp->ops.iw_inline_send(ukqp, &info, ib_wr->ex.invalidate_rkey, false);
d3749841
FL		 2160 } else {
2161 info.op.send.num_sges = ib_wr->num_sge;
2162 info.op.send.sg_list = (struct i40iw_sge *)ib_wr->sg_list;
b7aee855 2163 ret = ukqp->ops.iw_send(ukqp, &info, ib_wr->ex.invalidate_rkey, false);
d3749841
FL		 2164 }
2165
fe5d6e62
SS		 2166 if (ret) {
2167 if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
2168 err = -ENOMEM;
2169 else
2170 err = -EINVAL;
2171 }
d3749841
FL		 2172 break;
2173 case IB_WR_RDMA_WRITE:
2174 info.op_type = I40IW_OP_TYPE_RDMA_WRITE;
2175
2176 if (ib_wr->send_flags & IB_SEND_INLINE) {
2177 info.op.inline_rdma_write.data = (void *)(unsigned long)ib_wr->sg_list[0].addr;
2178 info.op.inline_rdma_write.len = ib_wr->sg_list[0].length;
2179 info.op.inline_rdma_write.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr;
2180 info.op.inline_rdma_write.rem_addr.stag = rdma_wr(ib_wr)->rkey;
2181 info.op.inline_rdma_write.rem_addr.len = ib_wr->sg_list->length;
2182 ret = ukqp->ops.iw_inline_rdma_write(ukqp, &info, false);
2183 } else {
2184 info.op.rdma_write.lo_sg_list = (void *)ib_wr->sg_list;
2185 info.op.rdma_write.num_lo_sges = ib_wr->num_sge;
2186 info.op.rdma_write.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr;
2187 info.op.rdma_write.rem_addr.stag = rdma_wr(ib_wr)->rkey;
2188 info.op.rdma_write.rem_addr.len = ib_wr->sg_list->length;
2189 ret = ukqp->ops.iw_rdma_write(ukqp, &info, false);
2190 }
2191
fe5d6e62
SS		 2192 if (ret) {
2193 if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
2194 err = -ENOMEM;
2195 else
2196 err = -EINVAL;
2197 }
d3749841 2198 break;
b7aee855
IM		 2199 case IB_WR_RDMA_READ_WITH_INV:
2200 inv_stag = true;
2201 /* fall-through*/
d3749841 2202 case IB_WR_RDMA_READ:
6c2f7619
SS		 2203 if (ib_wr->num_sge > I40IW_MAX_SGE_RD) {
2204 err = -EINVAL;
2205 break;
2206 }
d3749841
FL		 2207 info.op_type = I40IW_OP_TYPE_RDMA_READ;
2208 info.op.rdma_read.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr;
2209 info.op.rdma_read.rem_addr.stag = rdma_wr(ib_wr)->rkey;
2210 info.op.rdma_read.rem_addr.len = ib_wr->sg_list->length;
2211 info.op.rdma_read.lo_addr.tag_off = ib_wr->sg_list->addr;
2212 info.op.rdma_read.lo_addr.stag = ib_wr->sg_list->lkey;
2213 info.op.rdma_read.lo_addr.len = ib_wr->sg_list->length;
b7aee855 2214 ret = ukqp->ops.iw_rdma_read(ukqp, &info, inv_stag, false);
fe5d6e62
SS		 2215 if (ret) {
2216 if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
2217 err = -ENOMEM;
2218 else
2219 err = -EINVAL;
2220 }
d3749841 2221 break;
b7aee855
IM		 2222 case IB_WR_LOCAL_INV:
2223 info.op_type = I40IW_OP_TYPE_INV_STAG;
2224 info.op.inv_local_stag.target_stag = ib_wr->ex.invalidate_rkey;
2225 ret = ukqp->ops.iw_stag_local_invalidate(ukqp, &info, true);
2226 if (ret)
fe5d6e62 2227 err = -ENOMEM;
b7aee855
IM		 2228 break;
2229 case IB_WR_REG_MR:
2230 {
2231 struct i40iw_mr *iwmr = to_iwmr(reg_wr(ib_wr)->mr);
b7aee855
IM		 2232 int flags = reg_wr(ib_wr)->access;
2233 struct i40iw_pble_alloc *palloc = &iwmr->iwpbl.pble_alloc;
2234 struct i40iw_sc_dev *dev = &iwqp->iwdev->sc_dev;
2235 struct i40iw_fast_reg_stag_info info;
2236
7748e499 2237 memset(&info, 0, sizeof(info));
b7aee855
IM		 2238 info.access_rights = I40IW_ACCESS_FLAGS_LOCALREAD;
2239 info.access_rights |= i40iw_get_user_access(flags);
2240 info.stag_key = reg_wr(ib_wr)->key & 0xff;
2241 info.stag_idx = reg_wr(ib_wr)->key >> 8;
e6779185 2242 info.page_size = reg_wr(ib_wr)->mr->page_size;
b7aee855
IM		 2243 info.wr_id = ib_wr->wr_id;
2244
2245 info.addr_type = I40IW_ADDR_TYPE_VA_BASED;
2246 info.va = (void *)(uintptr_t)iwmr->ibmr.iova;
2247 info.total_len = iwmr->ibmr.length;
7748e499 2248 info.reg_addr_pa = *(u64 *)palloc->level1.addr;
b7aee855
IM		 2249 info.first_pm_pbl_index = palloc->level1.idx;
2250 info.local_fence = ib_wr->send_flags & IB_SEND_FENCE;
2251 info.signaled = ib_wr->send_flags & IB_SEND_SIGNALED;
2252
7748e499
SS		 2253 if (iwmr->npages > I40IW_MIN_PAGES_PER_FMR)
2254 info.chunk_size = 1;
2255
b7aee855
IM		 2256 ret = dev->iw_priv_qp_ops->iw_mr_fast_register(&iwqp->sc_qp, &info, true);
2257 if (ret)
fe5d6e62 2258 err = -ENOMEM;
b7aee855
IM		 2259 break;
2260 }
d3749841
FL		 2261 default:
2262 err = -EINVAL;
2263 i40iw_pr_err(" upost_send bad opcode = 0x%x\n",
2264 ib_wr->opcode);
2265 break;
2266 }
2267
2268 if (err)
2269 break;
2270 ib_wr = ib_wr->next;
2271 }
2272
2273 if (err)
2274 *bad_wr = ib_wr;
2275 else
2276 ukqp->ops.iw_qp_post_wr(ukqp);
2277 spin_unlock_irqrestore(&iwqp->lock, flags);
2278
2279 return err;
2280}
2281
2282/**
2283 * i40iw_post_recv - post receive wr for kernel application
2284 * @ibqp: ib qp pointer
2285 * @ib_wr: work request for receive
2286 * @bad_wr: bad wr caused an error
2287 */
2288static int i40iw_post_recv(struct ib_qp *ibqp,
2289 struct ib_recv_wr *ib_wr,
2290 struct ib_recv_wr **bad_wr)
2291{
2292 struct i40iw_qp *iwqp;
2293 struct i40iw_qp_uk *ukqp;
2294 struct i40iw_post_rq_info post_recv;
2295 struct i40iw_sge sg_list[I40IW_MAX_WQ_FRAGMENT_COUNT];
2296 enum i40iw_status_code ret = 0;
2297 unsigned long flags;
fe5d6e62 2298 int err = 0;
d3749841
FL		 2299
2300 iwqp = (struct i40iw_qp *)ibqp;
2301 ukqp = &iwqp->sc_qp.qp_uk;
2302
2303 memset(&post_recv, 0, sizeof(post_recv));
2304 spin_lock_irqsave(&iwqp->lock, flags);
2305 while (ib_wr) {
2306 post_recv.num_sges = ib_wr->num_sge;
2307 post_recv.wr_id = ib_wr->wr_id;
2308 i40iw_copy_sg_list(sg_list, ib_wr->sg_list, ib_wr->num_sge);
2309 post_recv.sg_list = sg_list;
2310 ret = ukqp->ops.iw_post_receive(ukqp, &post_recv);
2311 if (ret) {
2312 i40iw_pr_err(" post_recv err %d\n", ret);
fe5d6e62
SS		 2313 if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
2314 err = -ENOMEM;
2315 else
2316 err = -EINVAL;
d3749841
FL		 2317 *bad_wr = ib_wr;
2318 goto out;
2319 }
2320 ib_wr = ib_wr->next;
2321 }
2322 out:
2323 spin_unlock_irqrestore(&iwqp->lock, flags);
fe5d6e62 2324 return err;
d3749841
FL		 2325}
2326
2327/**
2328 * i40iw_poll_cq - poll cq for completion (kernel apps)
2329 * @ibcq: cq to poll
2330 * @num_entries: number of entries to poll
2331 * @entry: wr of entry completed
2332 */
2333static int i40iw_poll_cq(struct ib_cq *ibcq,
2334 int num_entries,
2335 struct ib_wc *entry)
2336{
2337 struct i40iw_cq *iwcq;
2338 int cqe_count = 0;
2339 struct i40iw_cq_poll_info cq_poll_info;
2340 enum i40iw_status_code ret;
2341 struct i40iw_cq_uk *ukcq;
2342 struct i40iw_sc_qp *qp;
c2b75ef7 2343 struct i40iw_qp *iwqp;
d3749841
FL		 2344 unsigned long flags;
2345
2346 iwcq = (struct i40iw_cq *)ibcq;
2347 ukcq = &iwcq->sc_cq.cq_uk;
2348
2349 spin_lock_irqsave(&iwcq->lock, flags);
2350 while (cqe_count < num_entries) {
b54143be 2351 ret = ukcq->ops.iw_cq_poll_completion(ukcq, &cq_poll_info);
d3749841
FL		 2352 if (ret == I40IW_ERR_QUEUE_EMPTY) {
2353 break;
f8a4e76c
TN		 2354 } else if (ret == I40IW_ERR_QUEUE_DESTROYED) {
2355 continue;
d3749841
FL		 2356 } else if (ret) {
2357 if (!cqe_count)
2358 cqe_count = -1;
2359 break;
2360 }
2361 entry->wc_flags = 0;
2362 entry->wr_id = cq_poll_info.wr_id;
df35630a 2363 if (cq_poll_info.error) {
d3749841 2364 entry->status = IB_WC_WR_FLUSH_ERR;
df35630a
IM		 2365 entry->vendor_err = cq_poll_info.major_err << 16 | cq_poll_info.minor_err;
2366 } else {
2367 entry->status = IB_WC_SUCCESS;
2368 }
d3749841
FL		 2369
2370 switch (cq_poll_info.op_type) {
2371 case I40IW_OP_TYPE_RDMA_WRITE:
2372 entry->opcode = IB_WC_RDMA_WRITE;
2373 break;
2374 case I40IW_OP_TYPE_RDMA_READ_INV_STAG:
2375 case I40IW_OP_TYPE_RDMA_READ:
2376 entry->opcode = IB_WC_RDMA_READ;
2377 break;
2378 case I40IW_OP_TYPE_SEND_SOL:
2379 case I40IW_OP_TYPE_SEND_SOL_INV:
2380 case I40IW_OP_TYPE_SEND_INV:
2381 case I40IW_OP_TYPE_SEND:
2382 entry->opcode = IB_WC_SEND;
2383 break;
2384 case I40IW_OP_TYPE_REC:
2385 entry->opcode = IB_WC_RECV;
2386 break;
2387 default:
2388 entry->opcode = IB_WC_RECV;
2389 break;
2390 }
2391
d3749841
FL		 2392 entry->ex.imm_data = 0;
2393 qp = (struct i40iw_sc_qp *)cq_poll_info.qp_handle;
2394 entry->qp = (struct ib_qp *)qp->back_qp;
2395 entry->src_qp = cq_poll_info.qp_id;
c2b75ef7
IM		 2396 iwqp = (struct i40iw_qp *)qp->back_qp;
2397 if (iwqp->iwarp_state > I40IW_QP_STATE_RTS) {
2398 if (!I40IW_RING_MORE_WORK(qp->qp_uk.sq_ring))
2399 complete(&iwqp->sq_drained);
2400 if (!I40IW_RING_MORE_WORK(qp->qp_uk.rq_ring))
2401 complete(&iwqp->rq_drained);
2402 }
d3749841
FL		 2403 entry->byte_len = cq_poll_info.bytes_xfered;
2404 entry++;
2405 cqe_count++;
2406 }
2407 spin_unlock_irqrestore(&iwcq->lock, flags);
2408 return cqe_count;
2409}
2410
2411/**
2412 * i40iw_req_notify_cq - arm cq kernel application
2413 * @ibcq: cq to arm
2414 * @notify_flags: notofication flags
2415 */
2416static int i40iw_req_notify_cq(struct ib_cq *ibcq,
2417 enum ib_cq_notify_flags notify_flags)
2418{
2419 struct i40iw_cq *iwcq;
2420 struct i40iw_cq_uk *ukcq;
747f1c6d
SS		 2421 unsigned long flags;
2422 enum i40iw_completion_notify cq_notify = IW_CQ_COMPL_EVENT;
d3749841
FL		 2423
2424 iwcq = (struct i40iw_cq *)ibcq;
2425 ukcq = &iwcq->sc_cq.cq_uk;
747f1c6d
SS		 2426 if (notify_flags == IB_CQ_SOLICITED)
2427 cq_notify = IW_CQ_COMPL_SOLICITED;
2428 spin_lock_irqsave(&iwcq->lock, flags);
d3749841 2429 ukcq->ops.iw_cq_request_notification(ukcq, cq_notify);
747f1c6d 2430 spin_unlock_irqrestore(&iwcq->lock, flags);
d3749841
FL		 2431 return 0;
2432}
2433
2434/**
2435 * i40iw_port_immutable - return port's immutable data
2436 * @ibdev: ib dev struct
2437 * @port_num: port number
2438 * @immutable: immutable data for the port return
2439 */
2440static int i40iw_port_immutable(struct ib_device *ibdev, u8 port_num,
2441 struct ib_port_immutable *immutable)
2442{
2443 struct ib_port_attr attr;
2444 int err;
2445
2446 err = i40iw_query_port(ibdev, port_num, &attr);
2447
2448 if (err)
2449 return err;
2450
2451 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2452 immutable->gid_tbl_len = attr.gid_tbl_len;
2453 immutable->core_cap_flags = RDMA_CORE_PORT_IWARP;
2454
2455 return 0;
2456}
2457
b40f4757
CL		 2458static const char * const i40iw_hw_stat_names[] = {
2459 // 32bit names
2460 [I40IW_HW_STAT_INDEX_IP4RXDISCARD] = "ip4InDiscards",
2461 [I40IW_HW_STAT_INDEX_IP4RXTRUNC] = "ip4InTruncatedPkts",
2462 [I40IW_HW_STAT_INDEX_IP4TXNOROUTE] = "ip4OutNoRoutes",
2463 [I40IW_HW_STAT_INDEX_IP6RXDISCARD] = "ip6InDiscards",
2464 [I40IW_HW_STAT_INDEX_IP6RXTRUNC] = "ip6InTruncatedPkts",
2465 [I40IW_HW_STAT_INDEX_IP6TXNOROUTE] = "ip6OutNoRoutes",
2466 [I40IW_HW_STAT_INDEX_TCPRTXSEG] = "tcpRetransSegs",
2467 [I40IW_HW_STAT_INDEX_TCPRXOPTERR] = "tcpInOptErrors",
2468 [I40IW_HW_STAT_INDEX_TCPRXPROTOERR] = "tcpInProtoErrors",
2469 // 64bit names
2470 [I40IW_HW_STAT_INDEX_IP4RXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
2471 "ip4InOctets",
2472 [I40IW_HW_STAT_INDEX_IP4RXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2473 "ip4InPkts",
2474 [I40IW_HW_STAT_INDEX_IP4RXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
2475 "ip4InReasmRqd",
2476 [I40IW_HW_STAT_INDEX_IP4RXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2477 "ip4InMcastPkts",
2478 [I40IW_HW_STAT_INDEX_IP4TXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
2479 "ip4OutOctets",
2480 [I40IW_HW_STAT_INDEX_IP4TXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2481 "ip4OutPkts",
2482 [I40IW_HW_STAT_INDEX_IP4TXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
2483 "ip4OutSegRqd",
2484 [I40IW_HW_STAT_INDEX_IP4TXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2485 "ip4OutMcastPkts",
2486 [I40IW_HW_STAT_INDEX_IP6RXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
2487 "ip6InOctets",
2488 [I40IW_HW_STAT_INDEX_IP6RXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2489 "ip6InPkts",
2490 [I40IW_HW_STAT_INDEX_IP6RXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
2491 "ip6InReasmRqd",
2492 [I40IW_HW_STAT_INDEX_IP6RXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2493 "ip6InMcastPkts",
2494 [I40IW_HW_STAT_INDEX_IP6TXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
2495 "ip6OutOctets",
2496 [I40IW_HW_STAT_INDEX_IP6TXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2497 "ip6OutPkts",
2498 [I40IW_HW_STAT_INDEX_IP6TXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
2499 "ip6OutSegRqd",
2500 [I40IW_HW_STAT_INDEX_IP6TXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2501 "ip6OutMcastPkts",
2502 [I40IW_HW_STAT_INDEX_TCPRXSEGS + I40IW_HW_STAT_INDEX_MAX_32] =
2503 "tcpInSegs",
2504 [I40IW_HW_STAT_INDEX_TCPTXSEG + I40IW_HW_STAT_INDEX_MAX_32] =
2505 "tcpOutSegs",
2506 [I40IW_HW_STAT_INDEX_RDMARXRDS + I40IW_HW_STAT_INDEX_MAX_32] =
2507 "iwInRdmaReads",
2508 [I40IW_HW_STAT_INDEX_RDMARXSNDS + I40IW_HW_STAT_INDEX_MAX_32] =
2509 "iwInRdmaSends",
2510 [I40IW_HW_STAT_INDEX_RDMARXWRS + I40IW_HW_STAT_INDEX_MAX_32] =
2511 "iwInRdmaWrites",
2512 [I40IW_HW_STAT_INDEX_RDMATXRDS + I40IW_HW_STAT_INDEX_MAX_32] =
2513 "iwOutRdmaReads",
2514 [I40IW_HW_STAT_INDEX_RDMATXSNDS + I40IW_HW_STAT_INDEX_MAX_32] =
2515 "iwOutRdmaSends",
2516 [I40IW_HW_STAT_INDEX_RDMATXWRS + I40IW_HW_STAT_INDEX_MAX_32] =
2517 "iwOutRdmaWrites",
2518 [I40IW_HW_STAT_INDEX_RDMAVBND + I40IW_HW_STAT_INDEX_MAX_32] =
2519 "iwRdmaBnd",
2520 [I40IW_HW_STAT_INDEX_RDMAVINV + I40IW_HW_STAT_INDEX_MAX_32] =
2521 "iwRdmaInv"
2522};
2523
f65c52ca
IW		 2524static void i40iw_get_dev_fw_str(struct ib_device *dev, char *str,
2525 size_t str_len)
2526{
2527 u32 firmware_version = I40IW_FW_VERSION;
2528
2529 snprintf(str, str_len, "%u.%u", firmware_version,
2530 (firmware_version & 0x000000ff));
2531}
2532
d3749841 2533/**
b40f4757
CL		 2534 * i40iw_alloc_hw_stats - Allocate a hw stats structure
2535 * @ibdev: device pointer from stack
2536 * @port_num: port number
d3749841 2537 */
b40f4757
CL		 2538static struct rdma_hw_stats *i40iw_alloc_hw_stats(struct ib_device *ibdev,
2539 u8 port_num)
2540{
2541 struct i40iw_device *iwdev = to_iwdev(ibdev);
2542 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
2543 int num_counters = I40IW_HW_STAT_INDEX_MAX_32 +
2544 I40IW_HW_STAT_INDEX_MAX_64;
2545 unsigned long lifespan = RDMA_HW_STATS_DEFAULT_LIFESPAN;
2546
2547 BUILD_BUG_ON(ARRAY_SIZE(i40iw_hw_stat_names) !=
2548 (I40IW_HW_STAT_INDEX_MAX_32 +
2549 I40IW_HW_STAT_INDEX_MAX_64));
2550
2551 /*
2552 * PFs get the default update lifespan, but VFs only update once
2553 * per second
2554 */
2555 if (!dev->is_pf)
2556 lifespan = 1000;
2557 return rdma_alloc_hw_stats_struct(i40iw_hw_stat_names, num_counters,
2558 lifespan);
2559}
2560
2561/**
2562 * i40iw_get_hw_stats - Populates the rdma_hw_stats structure
2563 * @ibdev: device pointer from stack
2564 * @stats: stats pointer from stack
2565 * @port_num: port number
2566 * @index: which hw counter the stack is requesting we update
2567 */
2568static int i40iw_get_hw_stats(struct ib_device *ibdev,
2569 struct rdma_hw_stats *stats,
2570 u8 port_num, int index)
d3749841
FL		 2571{
2572 struct i40iw_device *iwdev = to_iwdev(ibdev);
2573 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
2574 struct i40iw_dev_pestat *devstat = &dev->dev_pestat;
2575 struct i40iw_dev_hw_stats *hw_stats = &devstat->hw_stats;
d3749841
FL		 2576 unsigned long flags;
2577
d3749841
FL		 2578 if (dev->is_pf) {
2579 spin_lock_irqsave(&devstat->stats_lock, flags);
2580 devstat->ops.iw_hw_stat_read_all(devstat,
2581 &devstat->hw_stats);
2582 spin_unlock_irqrestore(&devstat->stats_lock, flags);
2583 } else {
b40f4757
CL		 2584 if (i40iw_vchnl_vf_get_pe_stats(dev, &devstat->hw_stats))
2585 return -ENOSYS;
d3749841
FL		 2586 }
2587
b40f4757
CL		 2588 memcpy(&stats->value[0], &hw_stats, sizeof(*hw_stats));
2589
2590 return stats->num_counters;
d3749841
FL		 2591}
2592
2593/**
2594 * i40iw_query_gid - Query port GID
2595 * @ibdev: device pointer from stack
2596 * @port: port number
2597 * @index: Entry index
2598 * @gid: Global ID
2599 */
2600static int i40iw_query_gid(struct ib_device *ibdev,
2601 u8 port,
2602 int index,
2603 union ib_gid *gid)
2604{
2605 struct i40iw_device *iwdev = to_iwdev(ibdev);
2606
2607 memset(gid->raw, 0, sizeof(gid->raw));
2608 ether_addr_copy(gid->raw, iwdev->netdev->dev_addr);
2609 return 0;
2610}
2611
2612/**
2613 * i40iw_modify_port Modify port properties
2614 * @ibdev: device pointer from stack
2615 * @port: port number
2616 * @port_modify_mask: mask for port modifications
2617 * @props: port properties
2618 */
2619static int i40iw_modify_port(struct ib_device *ibdev,
2620 u8 port,
2621 int port_modify_mask,
2622 struct ib_port_modify *props)
2623{
fe5d6e62 2624 return -ENOSYS;
d3749841
FL		 2625}
2626
2627/**
2628 * i40iw_query_pkey - Query partition key
2629 * @ibdev: device pointer from stack
2630 * @port: port number
2631 * @index: index of pkey
2632 * @pkey: pointer to store the pkey
2633 */
2634static int i40iw_query_pkey(struct ib_device *ibdev,
2635 u8 port,
2636 u16 index,
2637 u16 *pkey)
2638{
2639 *pkey = 0;
2640 return 0;
2641}
2642
2643/**
2644 * i40iw_create_ah - create address handle
2645 * @ibpd: ptr of pd
2646 * @ah_attr: address handle attributes
2647 */
2648static struct ib_ah *i40iw_create_ah(struct ib_pd *ibpd,
2649 struct ib_ah_attr *attr)
2650{
2651 return ERR_PTR(-ENOSYS);
2652}
2653
2654/**
2655 * i40iw_destroy_ah - Destroy address handle
2656 * @ah: pointer to address handle
2657 */
2658static int i40iw_destroy_ah(struct ib_ah *ah)
2659{
2660 return -ENOSYS;
2661}
2662
2663/**
2664 * i40iw_init_rdma_device - initialization of iwarp device
2665 * @iwdev: iwarp device
2666 */
2667static struct i40iw_ib_device *i40iw_init_rdma_device(struct i40iw_device *iwdev)
2668{
2669 struct i40iw_ib_device *iwibdev;
2670 struct net_device *netdev = iwdev->netdev;
2671 struct pci_dev *pcidev = (struct pci_dev *)iwdev->hw.dev_context;
2672
2673 iwibdev = (struct i40iw_ib_device *)ib_alloc_device(sizeof(*iwibdev));
2674 if (!iwibdev) {
2675 i40iw_pr_err("iwdev == NULL\n");
2676 return NULL;
2677 }
2678 strlcpy(iwibdev->ibdev.name, "i40iw%d", IB_DEVICE_NAME_MAX);
2679 iwibdev->ibdev.owner = THIS_MODULE;
2680 iwdev->iwibdev = iwibdev;
2681 iwibdev->iwdev = iwdev;
2682
2683 iwibdev->ibdev.node_type = RDMA_NODE_RNIC;
2684 ether_addr_copy((u8 *)&iwibdev->ibdev.node_guid, netdev->dev_addr);
2685
2686 iwibdev->ibdev.uverbs_cmd_mask =
2687 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2688 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2689 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2690 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2691 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2692 (1ull << IB_USER_VERBS_CMD_REG_MR) |
2693 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2694 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2695 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2696 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2697 (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ) |
2698 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2699 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2700 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2701 (1ull << IB_USER_VERBS_CMD_POLL_CQ) |
2702 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
2703 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
2704 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2705 (1ull << IB_USER_VERBS_CMD_POST_RECV) |
2706 (1ull << IB_USER_VERBS_CMD_POST_SEND);
2707 iwibdev->ibdev.phys_port_cnt = 1;
e69c5093 2708 iwibdev->ibdev.num_comp_vectors = iwdev->ceqs_count;
d3749841
FL		 2709 iwibdev->ibdev.dma_device = &pcidev->dev;
2710 iwibdev->ibdev.dev.parent = &pcidev->dev;
2711 iwibdev->ibdev.query_port = i40iw_query_port;
2712 iwibdev->ibdev.modify_port = i40iw_modify_port;
2713 iwibdev->ibdev.query_pkey = i40iw_query_pkey;
2714 iwibdev->ibdev.query_gid = i40iw_query_gid;
2715 iwibdev->ibdev.alloc_ucontext = i40iw_alloc_ucontext;
2716 iwibdev->ibdev.dealloc_ucontext = i40iw_dealloc_ucontext;
2717 iwibdev->ibdev.mmap = i40iw_mmap;
2718 iwibdev->ibdev.alloc_pd = i40iw_alloc_pd;
2719 iwibdev->ibdev.dealloc_pd = i40iw_dealloc_pd;
2720 iwibdev->ibdev.create_qp = i40iw_create_qp;
2721 iwibdev->ibdev.modify_qp = i40iw_modify_qp;
2722 iwibdev->ibdev.query_qp = i40iw_query_qp;
2723 iwibdev->ibdev.destroy_qp = i40iw_destroy_qp;
2724 iwibdev->ibdev.create_cq = i40iw_create_cq;
2725 iwibdev->ibdev.destroy_cq = i40iw_destroy_cq;
2726 iwibdev->ibdev.get_dma_mr = i40iw_get_dma_mr;
2727 iwibdev->ibdev.reg_user_mr = i40iw_reg_user_mr;
2728 iwibdev->ibdev.dereg_mr = i40iw_dereg_mr;
b40f4757
CL		 2729 iwibdev->ibdev.alloc_hw_stats = i40iw_alloc_hw_stats;
2730 iwibdev->ibdev.get_hw_stats = i40iw_get_hw_stats;
d3749841
FL		 2731 iwibdev->ibdev.query_device = i40iw_query_device;
2732 iwibdev->ibdev.create_ah = i40iw_create_ah;
2733 iwibdev->ibdev.destroy_ah = i40iw_destroy_ah;
c2b75ef7
IM		 2734 iwibdev->ibdev.drain_sq = i40iw_drain_sq;
2735 iwibdev->ibdev.drain_rq = i40iw_drain_rq;
b7aee855
IM		 2736 iwibdev->ibdev.alloc_mr = i40iw_alloc_mr;
2737 iwibdev->ibdev.map_mr_sg = i40iw_map_mr_sg;
d3749841
FL		 2738 iwibdev->ibdev.iwcm = kzalloc(sizeof(*iwibdev->ibdev.iwcm), GFP_KERNEL);
2739 if (!iwibdev->ibdev.iwcm) {
2740 ib_dealloc_device(&iwibdev->ibdev);
2741 i40iw_pr_err("iwcm == NULL\n");
2742 return NULL;
2743 }
2744
2745 iwibdev->ibdev.iwcm->add_ref = i40iw_add_ref;
2746 iwibdev->ibdev.iwcm->rem_ref = i40iw_rem_ref;
2747 iwibdev->ibdev.iwcm->get_qp = i40iw_get_qp;
2748 iwibdev->ibdev.iwcm->connect = i40iw_connect;
2749 iwibdev->ibdev.iwcm->accept = i40iw_accept;
2750 iwibdev->ibdev.iwcm->reject = i40iw_reject;
2751 iwibdev->ibdev.iwcm->create_listen = i40iw_create_listen;
2752 iwibdev->ibdev.iwcm->destroy_listen = i40iw_destroy_listen;
8d8cd0bf
FL		 2753 memcpy(iwibdev->ibdev.iwcm->ifname, netdev->name,
2754 sizeof(iwibdev->ibdev.iwcm->ifname));
d3749841 2755 iwibdev->ibdev.get_port_immutable = i40iw_port_immutable;
f65c52ca 2756 iwibdev->ibdev.get_dev_fw_str = i40iw_get_dev_fw_str;
d3749841
FL		 2757 iwibdev->ibdev.poll_cq = i40iw_poll_cq;
2758 iwibdev->ibdev.req_notify_cq = i40iw_req_notify_cq;
2759 iwibdev->ibdev.post_send = i40iw_post_send;
2760 iwibdev->ibdev.post_recv = i40iw_post_recv;
8d8cd0bf 2761
d3749841
FL		 2762 return iwibdev;
2763}
2764
2765/**
2766 * i40iw_port_ibevent - indicate port event
2767 * @iwdev: iwarp device
2768 */
2769void i40iw_port_ibevent(struct i40iw_device *iwdev)
2770{
2771 struct i40iw_ib_device *iwibdev = iwdev->iwibdev;
2772 struct ib_event event;
2773
2774 event.device = &iwibdev->ibdev;
2775 event.element.port_num = 1;
2776 event.event = iwdev->iw_status ? IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2777 ib_dispatch_event(&event);
2778}
2779
2780/**
2781 * i40iw_unregister_rdma_device - unregister of iwarp from IB
2782 * @iwibdev: rdma device ptr
2783 */
2784static void i40iw_unregister_rdma_device(struct i40iw_ib_device *iwibdev)
2785{
2786 int i;
2787
2788 for (i = 0; i < ARRAY_SIZE(i40iw_dev_attributes); ++i)
2789 device_remove_file(&iwibdev->ibdev.dev,
2790 i40iw_dev_attributes[i]);
2791 ib_unregister_device(&iwibdev->ibdev);
2792}
2793
2794/**
2795 * i40iw_destroy_rdma_device - destroy rdma device and free resources
2796 * @iwibdev: IB device ptr
2797 */
2798void i40iw_destroy_rdma_device(struct i40iw_ib_device *iwibdev)
2799{
2800 if (!iwibdev)
2801 return;
2802
2803 i40iw_unregister_rdma_device(iwibdev);
2804 kfree(iwibdev->ibdev.iwcm);
2805 iwibdev->ibdev.iwcm = NULL;
2806 ib_dealloc_device(&iwibdev->ibdev);
2807}
2808
2809/**
2810 * i40iw_register_rdma_device - register iwarp device to IB
2811 * @iwdev: iwarp device
2812 */
2813int i40iw_register_rdma_device(struct i40iw_device *iwdev)
2814{
2815 int i, ret;
2816 struct i40iw_ib_device *iwibdev;
2817
2818 iwdev->iwibdev = i40iw_init_rdma_device(iwdev);
2819 if (!iwdev->iwibdev)
fe5d6e62 2820 return -ENOMEM;
d3749841
FL		 2821 iwibdev = iwdev->iwibdev;
2822
2823 ret = ib_register_device(&iwibdev->ibdev, NULL);
2824 if (ret)
2825 goto error;
2826
2827 for (i = 0; i < ARRAY_SIZE(i40iw_dev_attributes); ++i) {
2828 ret =
2829 device_create_file(&iwibdev->ibdev.dev,
2830 i40iw_dev_attributes[i]);
2831 if (ret) {
2832 while (i > 0) {
2833 i--;
2834 device_remove_file(&iwibdev->ibdev.dev, i40iw_dev_attributes[i]);
2835 }
2836 ib_unregister_device(&iwibdev->ibdev);
2837 goto error;
2838 }
2839 }
2840 return 0;
2841error:
2842 kfree(iwdev->iwibdev->ibdev.iwcm);
2843 iwdev->iwibdev->ibdev.iwcm = NULL;
2844 ib_dealloc_device(&iwdev->iwibdev->ibdev);
fe5d6e62 2845 return ret;
d3749841 2846}
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