[mirror_ubuntu-artful-kernel.git] / drivers / infiniband / hw / i40iw / i40iw_verbs.h

/*******************************************************************************
*
* Copyright (c) 2015-2016 Intel Corporation.  All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses.  You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenFabrics.org BSD license below:
*
*   Redistribution and use in source and binary forms, with or
*   without modification, are permitted provided that the following
*   conditions are met:
*
*    - Redistributions of source code must retain the above
*	copyright notice, this list of conditions and the following
*	disclaimer.
*
*    - Redistributions in binary form must reproduce the above
*	copyright notice, this list of conditions and the following
*	disclaimer in the documentation and/or other materials
*	provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
*******************************************************************************/

#ifndef I40IW_VERBS_H
#define I40IW_VERBS_H

struct i40iw_ucontext {
	struct ib_ucontext ibucontext;
	struct i40iw_device *iwdev;
	struct list_head cq_reg_mem_list;
	spinlock_t cq_reg_mem_list_lock; /* memory list for cq's */
	struct list_head qp_reg_mem_list;
	spinlock_t qp_reg_mem_list_lock; /* memory list for qp's */
	int abi_ver;
};

struct i40iw_pd {
	struct ib_pd ibpd;
	struct i40iw_sc_pd sc_pd;
	atomic_t usecount;
};

struct i40iw_hmc_pble {
	union {
		u32 idx;
		dma_addr_t addr;
	};
};

struct i40iw_cq_mr {
	struct i40iw_hmc_pble cq_pbl;
	dma_addr_t shadow;
};

struct i40iw_qp_mr {
	struct i40iw_hmc_pble sq_pbl;
	struct i40iw_hmc_pble rq_pbl;
	dma_addr_t shadow;
	struct page *sq_page;
};

struct i40iw_pbl {
	struct list_head list;
	union {
		struct i40iw_qp_mr qp_mr;
		struct i40iw_cq_mr cq_mr;
	};

	bool pbl_allocated;
	u64 user_base;
	struct i40iw_pble_alloc pble_alloc;
	struct i40iw_mr *iwmr;
};

#define MAX_SAVE_PAGE_ADDRS     4
struct i40iw_mr {
	union {
		struct ib_mr ibmr;
		struct ib_mw ibmw;
		struct ib_fmr ibfmr;
	};
	struct ib_umem *region;
	u16 type;
	u32 page_cnt;
	u32 page_size;
	u64 page_msk;
	u32 npages;
	u32 stag;
	u64 length;
	u64 pgaddrmem[MAX_SAVE_PAGE_ADDRS];
	struct i40iw_pbl iwpbl;
};

struct i40iw_cq {
	struct ib_cq ibcq;
	struct i40iw_sc_cq sc_cq;
	u16 cq_head;
	u16 cq_size;
	u16 cq_number;
	bool user_mode;
	u32 polled_completions;
	u32 cq_mem_size;
	struct i40iw_dma_mem kmem;
	spinlock_t lock; /* for poll cq */
	struct i40iw_pbl *iwpbl;
};

struct disconn_work {
	struct work_struct work;
	struct i40iw_qp *iwqp;
};

struct iw_cm_id;
struct ietf_mpa_frame;
struct i40iw_ud_file;

struct i40iw_qp_kmode {
	struct i40iw_dma_mem dma_mem;
	u64 *wrid_mem;
};

struct i40iw_qp {
	struct ib_qp ibqp;
	struct i40iw_sc_qp sc_qp;
	struct i40iw_device *iwdev;
	struct i40iw_cq *iwscq;
	struct i40iw_cq *iwrcq;
	struct i40iw_pd *iwpd;
	struct i40iw_qp_host_ctx_info ctx_info;
	struct i40iwarp_offload_info iwarp_info;
	void *allocated_buffer;
	atomic_t refcount;
	struct iw_cm_id *cm_id;
	void *cm_node;
	struct ib_mr *lsmm_mr;
	struct work_struct work;
	enum ib_qp_state ibqp_state;
	u32 iwarp_state;
	u32 qp_mem_size;
	u32 last_aeq;
	atomic_t close_timer_started;
	spinlock_t lock; /* for post work requests */
	struct i40iw_qp_context *iwqp_context;
	void *pbl_vbase;
	dma_addr_t pbl_pbase;
	struct page *page;
	u8 active_conn:1;
	u8 user_mode:1;
	u8 hte_added:1;
	u8 flush_issued:1;
	u8 destroyed:1;
	u8 sig_all:1;
	u8 pau_mode:1;
	u8 rsvd:1;
	u16 term_sq_flush_code;
	u16 term_rq_flush_code;
	u8 hw_iwarp_state;
	u8 hw_tcp_state;
	struct i40iw_qp_kmode kqp;
	struct i40iw_dma_mem host_ctx;
	struct timer_list terminate_timer;
	struct i40iw_pbl iwpbl;
	struct i40iw_dma_mem q2_ctx_mem;
	struct i40iw_dma_mem ietf_mem;
	struct completion sq_drained;
	struct completion rq_drained;
};
#endif
Commit	Line	Data
d3749841 FL	1	/*******************************************************************************
	2	*
	3	* Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
	4	*
	5	* This software is available to you under a choice of one of two
	6	* licenses. You may choose to be licensed under the terms of the GNU
	7	* General Public License (GPL) Version 2, available from the file
	8	* COPYING in the main directory of this source tree, or the
	9	* OpenFabrics.org BSD license below:
	10	*
	11	* Redistribution and use in source and binary forms, with or
	12	* without modification, are permitted provided that the following
	13	* conditions are met:
	14	*
	15	* - Redistributions of source code must retain the above
	16	* copyright notice, this list of conditions and the following
	17	* disclaimer.
	18	*
	19	* - Redistributions in binary form must reproduce the above
	20	* copyright notice, this list of conditions and the following
	21	* disclaimer in the documentation and/or other materials
	22	* provided with the distribution.
	23	*
	24	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	25	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	26	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	27	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	28	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	29	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	30	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	31	* SOFTWARE.
	32	*
	33	*******************************************************************************/
	34
	35	#ifndef I40IW_VERBS_H
	36	#define I40IW_VERBS_H
	37
	38	struct i40iw_ucontext {
	39	struct ib_ucontext ibucontext;
	40	struct i40iw_device *iwdev;
	41	struct list_head cq_reg_mem_list;
	42	spinlock_t cq_reg_mem_list_lock; /* memory list for cq's */
	43	struct list_head qp_reg_mem_list;
	44	spinlock_t qp_reg_mem_list_lock; /* memory list for qp's */
61f51b7b	45	int abi_ver;
d3749841 FL	46	};
	47
	48	struct i40iw_pd {
	49	struct ib_pd ibpd;
	50	struct i40iw_sc_pd sc_pd;
	51	atomic_t usecount;
	52	};
	53
	54	struct i40iw_hmc_pble {
	55	union {
	56	u32 idx;
	57	dma_addr_t addr;
	58	};
	59	};
	60
	61	struct i40iw_cq_mr {
	62	struct i40iw_hmc_pble cq_pbl;
	63	dma_addr_t shadow;
	64	};
	65
	66	struct i40iw_qp_mr {
	67	struct i40iw_hmc_pble sq_pbl;
	68	struct i40iw_hmc_pble rq_pbl;
	69	dma_addr_t shadow;
	70	struct page *sq_page;
	71	};
	72
	73	struct i40iw_pbl {
	74	struct list_head list;
	75	union {
	76	struct i40iw_qp_mr qp_mr;
	77	struct i40iw_cq_mr cq_mr;
	78	};
	79
	80	bool pbl_allocated;
	81	u64 user_base;
	82	struct i40iw_pble_alloc pble_alloc;
	83	struct i40iw_mr *iwmr;
	84	};
	85
	86	#define MAX_SAVE_PAGE_ADDRS 4
	87	struct i40iw_mr {
	88	union {
	89	struct ib_mr ibmr;
	90	struct ib_mw ibmw;
	91	struct ib_fmr ibfmr;
	92	};
	93	struct ib_umem *region;
	94	u16 type;
	95	u32 page_cnt;
f26c7c83 HO	96	u32 page_size;
f26c7c83 HO	97	u64 page_msk;
b7aee855	98	u32 npages;
d3749841 FL	99	u32 stag;
	100	u64 length;
	101	u64 pgaddrmem[MAX_SAVE_PAGE_ADDRS];
	102	struct i40iw_pbl iwpbl;
	103	};
	104
	105	struct i40iw_cq {
	106	struct ib_cq ibcq;
	107	struct i40iw_sc_cq sc_cq;
	108	u16 cq_head;
	109	u16 cq_size;
	110	u16 cq_number;
	111	bool user_mode;
	112	u32 polled_completions;
	113	u32 cq_mem_size;
	114	struct i40iw_dma_mem kmem;
	115	spinlock_t lock; /* for poll cq */
	116	struct i40iw_pbl *iwpbl;
	117	};
	118
	119	struct disconn_work {
	120	struct work_struct work;
	121	struct i40iw_qp *iwqp;
	122	};
	123
	124	struct iw_cm_id;
	125	struct ietf_mpa_frame;
	126	struct i40iw_ud_file;
	127
	128	struct i40iw_qp_kmode {
	129	struct i40iw_dma_mem dma_mem;
	130	u64 *wrid_mem;
	131	};
	132
	133	struct i40iw_qp {
	134	struct ib_qp ibqp;
	135	struct i40iw_sc_qp sc_qp;
	136	struct i40iw_device *iwdev;
	137	struct i40iw_cq *iwscq;
	138	struct i40iw_cq *iwrcq;
	139	struct i40iw_pd *iwpd;
	140	struct i40iw_qp_host_ctx_info ctx_info;
	141	struct i40iwarp_offload_info iwarp_info;
	142	void *allocated_buffer;
	143	atomic_t refcount;
	144	struct iw_cm_id *cm_id;
	145	void *cm_node;
	146	struct ib_mr *lsmm_mr;
	147	struct work_struct work;
	148	enum ib_qp_state ibqp_state;
	149	u32 iwarp_state;
	150	u32 qp_mem_size;
	151	u32 last_aeq;
	152	atomic_t close_timer_started;
	153	spinlock_t lock; /* for post work requests */
	154	struct i40iw_qp_context *iwqp_context;
	155	void *pbl_vbase;
	156	dma_addr_t pbl_pbase;
	157	struct page *page;
	158	u8 active_conn:1;
	159	u8 user_mode:1;
	160	u8 hte_added:1;
	161	u8 flush_issued:1;
	162	u8 destroyed:1;
163	u8 sig_all:1;
164	u8 pau_mode:1;
165	u8 rsvd:1;
166	u16 term_sq_flush_code;
167	u16 term_rq_flush_code;
168	u8 hw_iwarp_state;
169	u8 hw_tcp_state;
170	struct i40iw_qp_kmode kqp;
171	struct i40iw_dma_mem host_ctx;
172	struct timer_list terminate_timer;
af56e53c	173	struct i40iw_pbl iwpbl;
d3749841 FL	174	struct i40iw_dma_mem q2_ctx_mem;
d3749841 FL	175	struct i40iw_dma_mem ietf_mem;
c2b75ef7 IM	176	struct completion sq_drained;
c2b75ef7 IM	177	struct completion rq_drained;
d3749841 FL	178	};
d3749841 FL	179	#endif