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Commit | Line | Data |
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7bb206e3 | 1 | /* |
e7eacd36 | 2 | * Copyright (c) 2006, 2007, 2008 QLogic Corporation. All rights reserved. |
7bb206e3 BS |
3 | * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. |
4 | * | |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the | |
9 | * OpenIB.org BSD license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or | |
12 | * without modification, are permitted provided that the following | |
13 | * conditions are met: | |
14 | * | |
15 | * - Redistributions of source code must retain the above | |
16 | * copyright notice, this list of conditions and the following | |
17 | * disclaimer. | |
18 | * | |
19 | * - Redistributions in binary form must reproduce the above | |
20 | * copyright notice, this list of conditions and the following | |
21 | * disclaimer in the documentation and/or other materials | |
22 | * provided with the distribution. | |
23 | * | |
24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
31 | * SOFTWARE. | |
32 | */ | |
33 | ||
d43c36dc | 34 | #include <linux/sched.h> |
7bb206e3 BS |
35 | #include <linux/spinlock.h> |
36 | #include <linux/idr.h> | |
37 | #include <linux/pci.h> | |
9bec3992 | 38 | #include <linux/io.h> |
7bb206e3 BS |
39 | #include <linux/delay.h> |
40 | #include <linux/netdevice.h> | |
41 | #include <linux/vmalloc.h> | |
598cb6f3 | 42 | #include <linux/bitmap.h> |
5a0e3ad6 | 43 | #include <linux/slab.h> |
7bb206e3 BS |
44 | |
45 | #include "ipath_kernel.h" | |
b1c1b6a3 | 46 | #include "ipath_verbs.h" |
7bb206e3 BS |
47 | |
48 | static void ipath_update_pio_bufs(struct ipath_devdata *); | |
49 | ||
50 | const char *ipath_get_unit_name(int unit) | |
51 | { | |
52 | static char iname[16]; | |
53 | snprintf(iname, sizeof iname, "infinipath%u", unit); | |
54 | return iname; | |
55 | } | |
56 | ||
759d5768 | 57 | #define DRIVER_LOAD_MSG "QLogic " IPATH_DRV_NAME " loaded: " |
7bb206e3 BS |
58 | #define PFX IPATH_DRV_NAME ": " |
59 | ||
60 | /* | |
61 | * The size has to be longer than this string, so we can append | |
62 | * board/chip information to it in the init code. | |
63 | */ | |
b55f4f06 | 64 | const char ib_ipath_version[] = IPATH_IDSTR "\n"; |
7bb206e3 BS |
65 | |
66 | static struct idr unit_table; | |
67 | DEFINE_SPINLOCK(ipath_devs_lock); | |
68 | LIST_HEAD(ipath_dev_list); | |
69 | ||
0fd41363 | 70 | wait_queue_head_t ipath_state_wait; |
7bb206e3 BS |
71 | |
72 | unsigned ipath_debug = __IPATH_INFO; | |
73 | ||
74 | module_param_named(debug, ipath_debug, uint, S_IWUSR | S_IRUGO); | |
75 | MODULE_PARM_DESC(debug, "mask for debug prints"); | |
76 | EXPORT_SYMBOL_GPL(ipath_debug); | |
77 | ||
826d8010 DO |
78 | unsigned ipath_mtu4096 = 1; /* max 4KB IB mtu by default, if supported */ |
79 | module_param_named(mtu4096, ipath_mtu4096, uint, S_IRUGO); | |
80 | MODULE_PARM_DESC(mtu4096, "enable MTU of 4096 bytes, if supported"); | |
81 | ||
58411d1c JG |
82 | static unsigned ipath_hol_timeout_ms = 13000; |
83 | module_param_named(hol_timeout_ms, ipath_hol_timeout_ms, uint, S_IRUGO); | |
84 | MODULE_PARM_DESC(hol_timeout_ms, | |
85 | "duration of user app suspension after link failure"); | |
86 | ||
72708a0a DO |
87 | unsigned ipath_linkrecovery = 1; |
88 | module_param_named(linkrecovery, ipath_linkrecovery, uint, S_IWUSR | S_IRUGO); | |
89 | MODULE_PARM_DESC(linkrecovery, "enable workaround for link recovery issue"); | |
90 | ||
7bb206e3 | 91 | MODULE_LICENSE("GPL"); |
928e3e4b | 92 | MODULE_AUTHOR("QLogic <support@qlogic.com>"); |
759d5768 | 93 | MODULE_DESCRIPTION("QLogic InfiniPath driver"); |
7bb206e3 | 94 | |
bb917144 AJ |
95 | /* |
96 | * Table to translate the LINKTRAININGSTATE portion of | |
97 | * IBCStatus to a human-readable form. | |
98 | */ | |
7bb206e3 BS |
99 | const char *ipath_ibcstatus_str[] = { |
100 | "Disabled", | |
101 | "LinkUp", | |
102 | "PollActive", | |
103 | "PollQuiet", | |
104 | "SleepDelay", | |
105 | "SleepQuiet", | |
106 | "LState6", /* unused */ | |
107 | "LState7", /* unused */ | |
108 | "CfgDebounce", | |
109 | "CfgRcvfCfg", | |
110 | "CfgWaitRmt", | |
111 | "CfgIdle", | |
112 | "RecovRetrain", | |
bb917144 | 113 | "CfgTxRevLane", /* unused before IBA7220 */ |
7bb206e3 BS |
114 | "RecovWaitRmt", |
115 | "RecovIdle", | |
bb917144 AJ |
116 | /* below were added for IBA7220 */ |
117 | "CfgEnhanced", | |
118 | "CfgTest", | |
119 | "CfgWaitRmtTest", | |
120 | "CfgWaitCfgEnhanced", | |
121 | "SendTS_T", | |
122 | "SendTstIdles", | |
123 | "RcvTS_T", | |
124 | "SendTst_TS1s", | |
125 | "LTState18", "LTState19", "LTState1A", "LTState1B", | |
126 | "LTState1C", "LTState1D", "LTState1E", "LTState1F" | |
7bb206e3 BS |
127 | }; |
128 | ||
7bb206e3 BS |
129 | static void __devexit ipath_remove_one(struct pci_dev *); |
130 | static int __devinit ipath_init_one(struct pci_dev *, | |
131 | const struct pci_device_id *); | |
132 | ||
133 | /* Only needed for registration, nothing else needs this info */ | |
134 | #define PCI_VENDOR_ID_PATHSCALE 0x1fc1 | |
135 | #define PCI_DEVICE_ID_INFINIPATH_HT 0xd | |
7bb206e3 | 136 | |
3588423f AJ |
137 | /* Number of seconds before our card status check... */ |
138 | #define STATUS_TIMEOUT 60 | |
139 | ||
7bb206e3 | 140 | static const struct pci_device_id ipath_pci_tbl[] = { |
6f4bb3d8 | 141 | { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_HT) }, |
6f4bb3d8 | 142 | { 0, } |
7bb206e3 BS |
143 | }; |
144 | ||
145 | MODULE_DEVICE_TABLE(pci, ipath_pci_tbl); | |
146 | ||
147 | static struct pci_driver ipath_driver = { | |
148 | .name = IPATH_DRV_NAME, | |
149 | .probe = ipath_init_one, | |
150 | .remove = __devexit_p(ipath_remove_one), | |
151 | .id_table = ipath_pci_tbl, | |
23b9c1ab GKH |
152 | .driver = { |
153 | .groups = ipath_driver_attr_groups, | |
154 | }, | |
7bb206e3 BS |
155 | }; |
156 | ||
7bb206e3 BS |
157 | static inline void read_bars(struct ipath_devdata *dd, struct pci_dev *dev, |
158 | u32 *bar0, u32 *bar1) | |
159 | { | |
160 | int ret; | |
161 | ||
162 | ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, bar0); | |
163 | if (ret) | |
164 | ipath_dev_err(dd, "failed to read bar0 before enable: " | |
165 | "error %d\n", -ret); | |
166 | ||
167 | ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, bar1); | |
168 | if (ret) | |
169 | ipath_dev_err(dd, "failed to read bar1 before enable: " | |
170 | "error %d\n", -ret); | |
171 | ||
172 | ipath_dbg("Read bar0 %x bar1 %x\n", *bar0, *bar1); | |
173 | } | |
174 | ||
175 | static void ipath_free_devdata(struct pci_dev *pdev, | |
176 | struct ipath_devdata *dd) | |
177 | { | |
178 | unsigned long flags; | |
179 | ||
180 | pci_set_drvdata(pdev, NULL); | |
181 | ||
182 | if (dd->ipath_unit != -1) { | |
183 | spin_lock_irqsave(&ipath_devs_lock, flags); | |
184 | idr_remove(&unit_table, dd->ipath_unit); | |
185 | list_del(&dd->ipath_list); | |
186 | spin_unlock_irqrestore(&ipath_devs_lock, flags); | |
187 | } | |
06993ca6 | 188 | vfree(dd); |
7bb206e3 BS |
189 | } |
190 | ||
191 | static struct ipath_devdata *ipath_alloc_devdata(struct pci_dev *pdev) | |
192 | { | |
193 | unsigned long flags; | |
194 | struct ipath_devdata *dd; | |
7bb206e3 BS |
195 | int ret; |
196 | ||
197 | if (!idr_pre_get(&unit_table, GFP_KERNEL)) { | |
198 | dd = ERR_PTR(-ENOMEM); | |
199 | goto bail; | |
200 | } | |
201 | ||
948579cd | 202 | dd = vzalloc(sizeof(*dd)); |
7bb206e3 BS |
203 | if (!dd) { |
204 | dd = ERR_PTR(-ENOMEM); | |
205 | goto bail; | |
206 | } | |
7bb206e3 BS |
207 | dd->ipath_unit = -1; |
208 | ||
209 | spin_lock_irqsave(&ipath_devs_lock, flags); | |
210 | ||
211 | ret = idr_get_new(&unit_table, dd, &dd->ipath_unit); | |
212 | if (ret < 0) { | |
213 | printk(KERN_ERR IPATH_DRV_NAME | |
214 | ": Could not allocate unit ID: error %d\n", -ret); | |
215 | ipath_free_devdata(pdev, dd); | |
216 | dd = ERR_PTR(ret); | |
217 | goto bail_unlock; | |
218 | } | |
219 | ||
220 | dd->pcidev = pdev; | |
221 | pci_set_drvdata(pdev, dd); | |
222 | ||
223 | list_add(&dd->ipath_list, &ipath_dev_list); | |
224 | ||
225 | bail_unlock: | |
226 | spin_unlock_irqrestore(&ipath_devs_lock, flags); | |
227 | ||
228 | bail: | |
229 | return dd; | |
230 | } | |
231 | ||
232 | static inline struct ipath_devdata *__ipath_lookup(int unit) | |
233 | { | |
234 | return idr_find(&unit_table, unit); | |
235 | } | |
236 | ||
237 | struct ipath_devdata *ipath_lookup(int unit) | |
238 | { | |
239 | struct ipath_devdata *dd; | |
240 | unsigned long flags; | |
241 | ||
242 | spin_lock_irqsave(&ipath_devs_lock, flags); | |
243 | dd = __ipath_lookup(unit); | |
244 | spin_unlock_irqrestore(&ipath_devs_lock, flags); | |
245 | ||
246 | return dd; | |
247 | } | |
248 | ||
6ef6aee2 | 249 | int ipath_count_units(int *npresentp, int *nupp, int *maxportsp) |
7bb206e3 BS |
250 | { |
251 | int nunits, npresent, nup; | |
252 | struct ipath_devdata *dd; | |
253 | unsigned long flags; | |
6ef6aee2 | 254 | int maxports; |
7bb206e3 BS |
255 | |
256 | nunits = npresent = nup = maxports = 0; | |
257 | ||
258 | spin_lock_irqsave(&ipath_devs_lock, flags); | |
259 | ||
260 | list_for_each_entry(dd, &ipath_dev_list, ipath_list) { | |
261 | nunits++; | |
262 | if ((dd->ipath_flags & IPATH_PRESENT) && dd->ipath_kregbase) | |
263 | npresent++; | |
264 | if (dd->ipath_lid && | |
265 | !(dd->ipath_flags & (IPATH_DISABLED | IPATH_LINKDOWN | |
266 | | IPATH_LINKUNK))) | |
267 | nup++; | |
268 | if (dd->ipath_cfgports > maxports) | |
269 | maxports = dd->ipath_cfgports; | |
270 | } | |
271 | ||
272 | spin_unlock_irqrestore(&ipath_devs_lock, flags); | |
273 | ||
274 | if (npresentp) | |
275 | *npresentp = npresent; | |
276 | if (nupp) | |
277 | *nupp = nup; | |
278 | if (maxportsp) | |
279 | *maxportsp = maxports; | |
280 | ||
281 | return nunits; | |
282 | } | |
283 | ||
7bb206e3 BS |
284 | /* |
285 | * These next two routines are placeholders in case we don't have per-arch | |
286 | * code for controlling write combining. If explicit control of write | |
287 | * combining is not available, performance will probably be awful. | |
288 | */ | |
289 | ||
290 | int __attribute__((weak)) ipath_enable_wc(struct ipath_devdata *dd) | |
291 | { | |
292 | return -EOPNOTSUPP; | |
293 | } | |
294 | ||
295 | void __attribute__((weak)) ipath_disable_wc(struct ipath_devdata *dd) | |
296 | { | |
297 | } | |
298 | ||
9bec3992 DO |
299 | /* |
300 | * Perform a PIO buffer bandwidth write test, to verify proper system | |
301 | * configuration. Even when all the setup calls work, occasionally | |
302 | * BIOS or other issues can prevent write combining from working, or | |
303 | * can cause other bandwidth problems to the chip. | |
304 | * | |
305 | * This test simply writes the same buffer over and over again, and | |
306 | * measures close to the peak bandwidth to the chip (not testing | |
307 | * data bandwidth to the wire). On chips that use an address-based | |
308 | * trigger to send packets to the wire, this is easy. On chips that | |
309 | * use a count to trigger, we want to make sure that the packet doesn't | |
310 | * go out on the wire, or trigger flow control checks. | |
311 | */ | |
312 | static void ipath_verify_pioperf(struct ipath_devdata *dd) | |
313 | { | |
314 | u32 pbnum, cnt, lcnt; | |
315 | u32 __iomem *piobuf; | |
316 | u32 *addr; | |
317 | u64 msecs, emsecs; | |
318 | ||
c4b4d16e | 319 | piobuf = ipath_getpiobuf(dd, 0, &pbnum); |
9bec3992 DO |
320 | if (!piobuf) { |
321 | dev_info(&dd->pcidev->dev, | |
322 | "No PIObufs for checking perf, skipping\n"); | |
323 | return; | |
324 | } | |
325 | ||
326 | /* | |
327 | * Enough to give us a reasonable test, less than piobuf size, and | |
328 | * likely multiple of store buffer length. | |
329 | */ | |
330 | cnt = 1024; | |
331 | ||
332 | addr = vmalloc(cnt); | |
333 | if (!addr) { | |
334 | dev_info(&dd->pcidev->dev, | |
335 | "Couldn't get memory for checking PIO perf," | |
336 | " skipping\n"); | |
337 | goto done; | |
338 | } | |
339 | ||
340 | preempt_disable(); /* we want reasonably accurate elapsed time */ | |
341 | msecs = 1 + jiffies_to_msecs(jiffies); | |
342 | for (lcnt = 0; lcnt < 10000U; lcnt++) { | |
343 | /* wait until we cross msec boundary */ | |
344 | if (jiffies_to_msecs(jiffies) >= msecs) | |
345 | break; | |
346 | udelay(1); | |
347 | } | |
348 | ||
6ac50727 DO |
349 | ipath_disable_armlaunch(dd); |
350 | ||
bb917144 AJ |
351 | /* |
352 | * length 0, no dwords actually sent, and mark as VL15 | |
353 | * on chips where that may matter (due to IB flowcontrol) | |
354 | */ | |
355 | if ((dd->ipath_flags & IPATH_HAS_PBC_CNT)) | |
356 | writeq(1UL << 63, piobuf); | |
357 | else | |
358 | writeq(0, piobuf); | |
9bec3992 DO |
359 | ipath_flush_wc(); |
360 | ||
361 | /* | |
362 | * this is only roughly accurate, since even with preempt we | |
363 | * still take interrupts that could take a while. Running for | |
364 | * >= 5 msec seems to get us "close enough" to accurate values | |
365 | */ | |
366 | msecs = jiffies_to_msecs(jiffies); | |
367 | for (emsecs = lcnt = 0; emsecs <= 5UL; lcnt++) { | |
368 | __iowrite32_copy(piobuf + 64, addr, cnt >> 2); | |
369 | emsecs = jiffies_to_msecs(jiffies) - msecs; | |
370 | } | |
371 | ||
372 | /* 1 GiB/sec, slightly over IB SDR line rate */ | |
373 | if (lcnt < (emsecs * 1024U)) | |
374 | ipath_dev_err(dd, | |
375 | "Performance problem: bandwidth to PIO buffers is " | |
376 | "only %u MiB/sec\n", | |
377 | lcnt / (u32) emsecs); | |
378 | else | |
379 | ipath_dbg("PIO buffer bandwidth %u MiB/sec is OK\n", | |
380 | lcnt / (u32) emsecs); | |
381 | ||
382 | preempt_enable(); | |
383 | ||
384 | vfree(addr); | |
385 | ||
386 | done: | |
387 | /* disarm piobuf, so it's available again */ | |
388 | ipath_disarm_piobufs(dd, pbnum, 1); | |
6ac50727 | 389 | ipath_enable_armlaunch(dd); |
9bec3992 DO |
390 | } |
391 | ||
dccb816d BH |
392 | static void cleanup_device(struct ipath_devdata *dd); |
393 | ||
7bb206e3 BS |
394 | static int __devinit ipath_init_one(struct pci_dev *pdev, |
395 | const struct pci_device_id *ent) | |
396 | { | |
397 | int ret, len, j; | |
398 | struct ipath_devdata *dd; | |
399 | unsigned long long addr; | |
400 | u32 bar0 = 0, bar1 = 0; | |
bb917144 | 401 | u8 rev; |
7bb206e3 | 402 | |
7bb206e3 BS |
403 | dd = ipath_alloc_devdata(pdev); |
404 | if (IS_ERR(dd)) { | |
405 | ret = PTR_ERR(dd); | |
406 | printk(KERN_ERR IPATH_DRV_NAME | |
407 | ": Could not allocate devdata: error %d\n", -ret); | |
f37bda92 | 408 | goto bail; |
7bb206e3 BS |
409 | } |
410 | ||
411 | ipath_cdbg(VERBOSE, "initializing unit #%u\n", dd->ipath_unit); | |
412 | ||
7bb206e3 BS |
413 | ret = pci_enable_device(pdev); |
414 | if (ret) { | |
415 | /* This can happen iff: | |
416 | * | |
417 | * We did a chip reset, and then failed to reprogram the | |
418 | * BAR, or the chip reset due to an internal error. We then | |
419 | * unloaded the driver and reloaded it. | |
420 | * | |
421 | * Both reset cases set the BAR back to initial state. For | |
422 | * the latter case, the AER sticky error bit at offset 0x718 | |
423 | * should be set, but the Linux kernel doesn't yet know | |
424 | * about that, it appears. If the original BAR was retained | |
425 | * in the kernel data structures, this may be OK. | |
426 | */ | |
427 | ipath_dev_err(dd, "enable unit %d failed: error %d\n", | |
428 | dd->ipath_unit, -ret); | |
429 | goto bail_devdata; | |
430 | } | |
431 | addr = pci_resource_start(pdev, 0); | |
432 | len = pci_resource_len(pdev, 0); | |
bb917144 | 433 | ipath_cdbg(VERBOSE, "regbase (0) %llx len %d irq %d, vend %x/%x " |
7bb206e3 BS |
434 | "driver_data %lx\n", addr, len, pdev->irq, ent->vendor, |
435 | ent->device, ent->driver_data); | |
436 | ||
437 | read_bars(dd, pdev, &bar0, &bar1); | |
438 | ||
439 | if (!bar1 && !(bar0 & ~0xf)) { | |
440 | if (addr) { | |
441 | dev_info(&pdev->dev, "BAR is 0 (probable RESET), " | |
442 | "rewriting as %llx\n", addr); | |
443 | ret = pci_write_config_dword( | |
444 | pdev, PCI_BASE_ADDRESS_0, addr); | |
445 | if (ret) { | |
446 | ipath_dev_err(dd, "rewrite of BAR0 " | |
447 | "failed: err %d\n", -ret); | |
448 | goto bail_disable; | |
449 | } | |
450 | ret = pci_write_config_dword( | |
451 | pdev, PCI_BASE_ADDRESS_1, addr >> 32); | |
452 | if (ret) { | |
453 | ipath_dev_err(dd, "rewrite of BAR1 " | |
454 | "failed: err %d\n", -ret); | |
455 | goto bail_disable; | |
456 | } | |
457 | } else { | |
458 | ipath_dev_err(dd, "BAR is 0 (probable RESET), " | |
459 | "not usable until reboot\n"); | |
460 | ret = -ENODEV; | |
461 | goto bail_disable; | |
462 | } | |
463 | } | |
464 | ||
465 | ret = pci_request_regions(pdev, IPATH_DRV_NAME); | |
466 | if (ret) { | |
467 | dev_info(&pdev->dev, "pci_request_regions unit %u fails: " | |
468 | "err %d\n", dd->ipath_unit, -ret); | |
469 | goto bail_disable; | |
470 | } | |
471 | ||
6a35528a | 472 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); |
7bb206e3 | 473 | if (ret) { |
68dd43a1 BS |
474 | /* |
475 | * if the 64 bit setup fails, try 32 bit. Some systems | |
476 | * do not setup 64 bit maps on systems with 2GB or less | |
477 | * memory installed. | |
478 | */ | |
284901a9 | 479 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
68dd43a1 | 480 | if (ret) { |
b1d8865a BS |
481 | dev_info(&pdev->dev, |
482 | "Unable to set DMA mask for unit %u: %d\n", | |
483 | dd->ipath_unit, ret); | |
68dd43a1 BS |
484 | goto bail_regions; |
485 | } | |
b1d8865a | 486 | else { |
68dd43a1 | 487 | ipath_dbg("No 64bit DMA mask, used 32 bit mask\n"); |
284901a9 | 488 | ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
b1d8865a BS |
489 | if (ret) |
490 | dev_info(&pdev->dev, | |
491 | "Unable to set DMA consistent mask " | |
492 | "for unit %u: %d\n", | |
493 | dd->ipath_unit, ret); | |
494 | ||
495 | } | |
496 | } | |
497 | else { | |
6a35528a | 498 | ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
b1d8865a BS |
499 | if (ret) |
500 | dev_info(&pdev->dev, | |
501 | "Unable to set DMA consistent mask " | |
502 | "for unit %u: %d\n", | |
503 | dd->ipath_unit, ret); | |
7bb206e3 BS |
504 | } |
505 | ||
506 | pci_set_master(pdev); | |
507 | ||
508 | /* | |
509 | * Save BARs to rewrite after device reset. Save all 64 bits of | |
510 | * BAR, just in case. | |
511 | */ | |
512 | dd->ipath_pcibar0 = addr; | |
513 | dd->ipath_pcibar1 = addr >> 32; | |
514 | dd->ipath_deviceid = ent->device; /* save for later use */ | |
515 | dd->ipath_vendorid = ent->vendor; | |
516 | ||
517 | /* setup the chip-specific functions, as early as possible. */ | |
518 | switch (ent->device) { | |
519 | case PCI_DEVICE_ID_INFINIPATH_HT: | |
525d0ca1 | 520 | ipath_init_iba6110_funcs(dd); |
7bb206e3 | 521 | break; |
f6d60848 | 522 | |
7bb206e3 | 523 | default: |
759d5768 | 524 | ipath_dev_err(dd, "Found unknown QLogic deviceid 0x%x, " |
7bb206e3 BS |
525 | "failing\n", ent->device); |
526 | return -ENODEV; | |
527 | } | |
528 | ||
529 | for (j = 0; j < 6; j++) { | |
530 | if (!pdev->resource[j].start) | |
531 | continue; | |
1eba27e8 JP |
532 | ipath_cdbg(VERBOSE, "BAR %d %pR, len %llx\n", |
533 | j, &pdev->resource[j], | |
e29419ff | 534 | (unsigned long long)pci_resource_len(pdev, j)); |
7bb206e3 BS |
535 | } |
536 | ||
537 | if (!addr) { | |
538 | ipath_dev_err(dd, "No valid address in BAR 0!\n"); | |
539 | ret = -ENODEV; | |
540 | goto bail_regions; | |
541 | } | |
542 | ||
bb917144 AJ |
543 | ret = pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); |
544 | if (ret) { | |
545 | ipath_dev_err(dd, "Failed to read PCI revision ID unit " | |
546 | "%u: err %d\n", dd->ipath_unit, -ret); | |
547 | goto bail_regions; /* shouldn't ever happen */ | |
548 | } | |
549 | dd->ipath_pcirev = rev; | |
7bb206e3 | 550 | |
eb9dc6f4 BS |
551 | #if defined(__powerpc__) |
552 | /* There isn't a generic way to specify writethrough mappings */ | |
553 | dd->ipath_kregbase = __ioremap(addr, len, | |
554 | (_PAGE_NO_CACHE|_PAGE_WRITETHRU)); | |
555 | #else | |
7bb206e3 | 556 | dd->ipath_kregbase = ioremap_nocache(addr, len); |
eb9dc6f4 | 557 | #endif |
7bb206e3 BS |
558 | |
559 | if (!dd->ipath_kregbase) { | |
560 | ipath_dbg("Unable to map io addr %llx to kvirt, failing\n", | |
561 | addr); | |
562 | ret = -ENOMEM; | |
563 | goto bail_iounmap; | |
564 | } | |
565 | dd->ipath_kregend = (u64 __iomem *) | |
566 | ((void __iomem *)dd->ipath_kregbase + len); | |
567 | dd->ipath_physaddr = addr; /* used for io_remap, etc. */ | |
568 | /* for user mmap */ | |
b35f004d BS |
569 | ipath_cdbg(VERBOSE, "mapped io addr %llx to kregbase %p\n", |
570 | addr, dd->ipath_kregbase); | |
7bb206e3 | 571 | |
7bb206e3 BS |
572 | if (dd->ipath_f_bus(dd, pdev)) |
573 | ipath_dev_err(dd, "Failed to setup config space; " | |
574 | "continuing anyway\n"); | |
575 | ||
576 | /* | |
dace1453 | 577 | * set up our interrupt handler; IRQF_SHARED probably not needed, |
7bb206e3 BS |
578 | * since MSI interrupts shouldn't be shared but won't hurt for now. |
579 | * check 0 irq after we return from chip-specific bus setup, since | |
580 | * that can affect this due to setup | |
581 | */ | |
51f65ebc | 582 | if (!dd->ipath_irq) |
7bb206e3 BS |
583 | ipath_dev_err(dd, "irq is 0, BIOS error? Interrupts won't " |
584 | "work\n"); | |
585 | else { | |
51f65ebc | 586 | ret = request_irq(dd->ipath_irq, ipath_intr, IRQF_SHARED, |
7bb206e3 BS |
587 | IPATH_DRV_NAME, dd); |
588 | if (ret) { | |
589 | ipath_dev_err(dd, "Couldn't setup irq handler, " | |
51f65ebc | 590 | "irq=%d: %d\n", dd->ipath_irq, ret); |
7bb206e3 BS |
591 | goto bail_iounmap; |
592 | } | |
593 | } | |
594 | ||
595 | ret = ipath_init_chip(dd, 0); /* do the chip-specific init */ | |
596 | if (ret) | |
7b196e2f | 597 | goto bail_irqsetup; |
7bb206e3 BS |
598 | |
599 | ret = ipath_enable_wc(dd); | |
600 | ||
601 | if (ret) { | |
602 | ipath_dev_err(dd, "Write combining not enabled " | |
603 | "(err %d): performance may be poor\n", | |
604 | -ret); | |
605 | ret = 0; | |
606 | } | |
607 | ||
9bec3992 DO |
608 | ipath_verify_pioperf(dd); |
609 | ||
7bb206e3 BS |
610 | ipath_device_create_group(&pdev->dev, dd); |
611 | ipathfs_add_device(dd); | |
612 | ipath_user_add(dd); | |
a2acb2ff | 613 | ipath_diag_add(dd); |
b1c1b6a3 | 614 | ipath_register_ib_device(dd); |
7bb206e3 BS |
615 | |
616 | goto bail; | |
617 | ||
7b196e2f | 618 | bail_irqsetup: |
dccb816d BH |
619 | cleanup_device(dd); |
620 | ||
621 | if (dd->ipath_irq) | |
622 | dd->ipath_f_free_irq(dd); | |
623 | ||
624 | if (dd->ipath_f_cleanup) | |
625 | dd->ipath_f_cleanup(dd); | |
7b196e2f | 626 | |
7bb206e3 BS |
627 | bail_iounmap: |
628 | iounmap((volatile void __iomem *) dd->ipath_kregbase); | |
629 | ||
630 | bail_regions: | |
631 | pci_release_regions(pdev); | |
632 | ||
633 | bail_disable: | |
634 | pci_disable_device(pdev); | |
635 | ||
636 | bail_devdata: | |
637 | ipath_free_devdata(pdev, dd); | |
638 | ||
7bb206e3 BS |
639 | bail: |
640 | return ret; | |
641 | } | |
642 | ||
dccb816d | 643 | static void cleanup_device(struct ipath_devdata *dd) |
7bb206e3 | 644 | { |
7227aac4 | 645 | int port; |
3d089098 DO |
646 | struct ipath_portdata **tmp; |
647 | unsigned long flags; | |
7bb206e3 | 648 | |
7227aac4 BS |
649 | if (*dd->ipath_statusp & IPATH_STATUS_CHIP_PRESENT) { |
650 | /* can't do anything more with chip; needs re-init */ | |
651 | *dd->ipath_statusp &= ~IPATH_STATUS_CHIP_PRESENT; | |
652 | if (dd->ipath_kregbase) { | |
653 | /* | |
654 | * if we haven't already cleaned up before these are | |
655 | * to ensure any register reads/writes "fail" until | |
656 | * re-init | |
657 | */ | |
658 | dd->ipath_kregbase = NULL; | |
659 | dd->ipath_uregbase = 0; | |
660 | dd->ipath_sregbase = 0; | |
661 | dd->ipath_cregbase = 0; | |
662 | dd->ipath_kregsize = 0; | |
663 | } | |
664 | ipath_disable_wc(dd); | |
665 | } | |
c78f6415 | 666 | |
bb917144 AJ |
667 | if (dd->ipath_spectriggerhit) |
668 | dev_info(&dd->pcidev->dev, "%lu special trigger hits\n", | |
669 | dd->ipath_spectriggerhit); | |
670 | ||
7227aac4 BS |
671 | if (dd->ipath_pioavailregs_dma) { |
672 | dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE, | |
673 | (void *) dd->ipath_pioavailregs_dma, | |
674 | dd->ipath_pioavailregs_phys); | |
675 | dd->ipath_pioavailregs_dma = NULL; | |
676 | } | |
677 | if (dd->ipath_dummy_hdrq) { | |
678 | dma_free_coherent(&dd->pcidev->dev, | |
679 | dd->ipath_pd[0]->port_rcvhdrq_size, | |
680 | dd->ipath_dummy_hdrq, dd->ipath_dummy_hdrq_phys); | |
681 | dd->ipath_dummy_hdrq = NULL; | |
682 | } | |
683 | ||
684 | if (dd->ipath_pageshadow) { | |
685 | struct page **tmpp = dd->ipath_pageshadow; | |
686 | dma_addr_t *tmpd = dd->ipath_physshadow; | |
687 | int i, cnt = 0; | |
688 | ||
689 | ipath_cdbg(VERBOSE, "Unlocking any expTID pages still " | |
690 | "locked\n"); | |
691 | for (port = 0; port < dd->ipath_cfgports; port++) { | |
692 | int port_tidbase = port * dd->ipath_rcvtidcnt; | |
693 | int maxtid = port_tidbase + dd->ipath_rcvtidcnt; | |
694 | for (i = port_tidbase; i < maxtid; i++) { | |
695 | if (!tmpp[i]) | |
696 | continue; | |
697 | pci_unmap_page(dd->pcidev, tmpd[i], | |
698 | PAGE_SIZE, PCI_DMA_FROMDEVICE); | |
699 | ipath_release_user_pages(&tmpp[i], 1); | |
700 | tmpp[i] = NULL; | |
701 | cnt++; | |
702 | } | |
703 | } | |
704 | if (cnt) { | |
705 | ipath_stats.sps_pageunlocks += cnt; | |
706 | ipath_cdbg(VERBOSE, "There were still %u expTID " | |
707 | "entries locked\n", cnt); | |
708 | } | |
709 | if (ipath_stats.sps_pagelocks || | |
710 | ipath_stats.sps_pageunlocks) | |
711 | ipath_cdbg(VERBOSE, "%llu pages locked, %llu " | |
712 | "unlocked via ipath_m{un}lock\n", | |
713 | (unsigned long long) | |
714 | ipath_stats.sps_pagelocks, | |
715 | (unsigned long long) | |
716 | ipath_stats.sps_pageunlocks); | |
717 | ||
718 | ipath_cdbg(VERBOSE, "Free shadow page tid array at %p\n", | |
719 | dd->ipath_pageshadow); | |
9783ab40 | 720 | tmpp = dd->ipath_pageshadow; |
7227aac4 | 721 | dd->ipath_pageshadow = NULL; |
9783ab40 | 722 | vfree(tmpp); |
9355fb6a RC |
723 | |
724 | dd->ipath_egrtidbase = NULL; | |
c78f6415 BS |
725 | } |
726 | ||
7227aac4 BS |
727 | /* |
728 | * free any resources still in use (usually just kernel ports) | |
3d089098 DO |
729 | * at unload; we do for portcnt, because that's what we allocate. |
730 | * We acquire lock to be really paranoid that ipath_pd isn't being | |
731 | * accessed from some interrupt-related code (that should not happen, | |
732 | * but best to be sure). | |
7227aac4 | 733 | */ |
3d089098 DO |
734 | spin_lock_irqsave(&dd->ipath_uctxt_lock, flags); |
735 | tmp = dd->ipath_pd; | |
736 | dd->ipath_pd = NULL; | |
737 | spin_unlock_irqrestore(&dd->ipath_uctxt_lock, flags); | |
7227aac4 | 738 | for (port = 0; port < dd->ipath_portcnt; port++) { |
3d089098 DO |
739 | struct ipath_portdata *pd = tmp[port]; |
740 | tmp[port] = NULL; /* debugging paranoia */ | |
7227aac4 BS |
741 | ipath_free_pddata(dd, pd); |
742 | } | |
3d089098 | 743 | kfree(tmp); |
7227aac4 BS |
744 | } |
745 | ||
746 | static void __devexit ipath_remove_one(struct pci_dev *pdev) | |
747 | { | |
748 | struct ipath_devdata *dd = pci_get_drvdata(pdev); | |
749 | ||
750 | ipath_cdbg(VERBOSE, "removing, pdev=%p, dd=%p\n", pdev, dd); | |
751 | ||
53c1d2c9 BS |
752 | /* |
753 | * disable the IB link early, to be sure no new packets arrive, which | |
754 | * complicates the shutdown process | |
755 | */ | |
756 | ipath_shutdown_device(dd); | |
757 | ||
f0626710 | 758 | flush_workqueue(ib_wq); |
3588423f | 759 | |
7227aac4 BS |
760 | if (dd->verbs_dev) |
761 | ipath_unregister_ib_device(dd->verbs_dev); | |
762 | ||
a2acb2ff BS |
763 | ipath_diag_remove(dd); |
764 | ipath_user_remove(dd); | |
7bb206e3 BS |
765 | ipathfs_remove_device(dd); |
766 | ipath_device_remove_group(&pdev->dev, dd); | |
7227aac4 | 767 | |
7bb206e3 BS |
768 | ipath_cdbg(VERBOSE, "Releasing pci memory regions, dd %p, " |
769 | "unit %u\n", dd, (u32) dd->ipath_unit); | |
7227aac4 BS |
770 | |
771 | cleanup_device(dd); | |
772 | ||
773 | /* | |
774 | * turn off rcv, send, and interrupts for all ports, all drivers | |
775 | * should also hard reset the chip here? | |
776 | * free up port 0 (kernel) rcvhdr, egr bufs, and eventually tid bufs | |
777 | * for all versions of the driver, if they were allocated | |
778 | */ | |
51f65ebc BS |
779 | if (dd->ipath_irq) { |
780 | ipath_cdbg(VERBOSE, "unit %u free irq %d\n", | |
781 | dd->ipath_unit, dd->ipath_irq); | |
782 | dd->ipath_f_free_irq(dd); | |
7227aac4 BS |
783 | } else |
784 | ipath_dbg("irq is 0, not doing free_irq " | |
785 | "for unit %u\n", dd->ipath_unit); | |
786 | /* | |
787 | * we check for NULL here, because it's outside | |
788 | * the kregbase check, and we need to call it | |
789 | * after the free_irq. Thus it's possible that | |
790 | * the function pointers were never initialized. | |
791 | */ | |
792 | if (dd->ipath_f_cleanup) | |
793 | /* clean up chip-specific stuff */ | |
794 | dd->ipath_f_cleanup(dd); | |
795 | ||
796 | ipath_cdbg(VERBOSE, "Unmapping kregbase %p\n", dd->ipath_kregbase); | |
797 | iounmap((volatile void __iomem *) dd->ipath_kregbase); | |
7bb206e3 BS |
798 | pci_release_regions(pdev); |
799 | ipath_cdbg(VERBOSE, "calling pci_disable_device\n"); | |
800 | pci_disable_device(pdev); | |
801 | ||
802 | ipath_free_devdata(pdev, dd); | |
7bb206e3 BS |
803 | } |
804 | ||
805 | /* general driver use */ | |
806 | DEFINE_MUTEX(ipath_mutex); | |
807 | ||
808 | static DEFINE_SPINLOCK(ipath_pioavail_lock); | |
809 | ||
810 | /** | |
811 | * ipath_disarm_piobufs - cancel a range of PIO buffers | |
812 | * @dd: the infinipath device | |
813 | * @first: the first PIO buffer to cancel | |
814 | * @cnt: the number of PIO buffers to cancel | |
815 | * | |
816 | * cancel a range of PIO buffers, used when they might be armed, but | |
817 | * not triggered. Used at init to ensure buffer state, and also user | |
818 | * process close, in case it died while writing to a PIO buffer | |
819 | * Also after errors. | |
820 | */ | |
821 | void ipath_disarm_piobufs(struct ipath_devdata *dd, unsigned first, | |
822 | unsigned cnt) | |
823 | { | |
824 | unsigned i, last = first + cnt; | |
e342c119 | 825 | unsigned long flags; |
7bb206e3 BS |
826 | |
827 | ipath_cdbg(PKT, "disarm %u PIObufs first=%u\n", cnt, first); | |
7bb206e3 | 828 | for (i = first; i < last; i++) { |
e342c119 JG |
829 | spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags); |
830 | /* | |
831 | * The disarm-related bits are write-only, so it | |
832 | * is ok to OR them in with our copy of sendctrl | |
833 | * while we hold the lock. | |
834 | */ | |
7bb206e3 | 835 | ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, |
e342c119 JG |
836 | dd->ipath_sendctrl | INFINIPATH_S_DISARM | |
837 | (i << INFINIPATH_S_DISARMPIOBUF_SHIFT)); | |
838 | /* can't disarm bufs back-to-back per iba7220 spec */ | |
839 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); | |
840 | spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags); | |
7bb206e3 | 841 | } |
c4b4d16e RC |
842 | /* on some older chips, update may not happen after cancel */ |
843 | ipath_force_pio_avail_update(dd); | |
7bb206e3 BS |
844 | } |
845 | ||
846 | /** | |
847 | * ipath_wait_linkstate - wait for an IB link state change to occur | |
848 | * @dd: the infinipath device | |
849 | * @state: the state to wait for | |
850 | * @msecs: the number of milliseconds to wait | |
851 | * | |
852 | * wait up to msecs milliseconds for IB link state change to occur for | |
853 | * now, take the easy polling route. Currently used only by | |
34b2aafe | 854 | * ipath_set_linkstate. Returns 0 if state reached, otherwise |
7bb206e3 BS |
855 | * -ETIMEDOUT state can have multiple states set, for any of several |
856 | * transitions. | |
857 | */ | |
140277e9 | 858 | int ipath_wait_linkstate(struct ipath_devdata *dd, u32 state, int msecs) |
7bb206e3 | 859 | { |
0fd41363 BS |
860 | dd->ipath_state_wanted = state; |
861 | wait_event_interruptible_timeout(ipath_state_wait, | |
7bb206e3 BS |
862 | (dd->ipath_flags & state), |
863 | msecs_to_jiffies(msecs)); | |
0fd41363 | 864 | dd->ipath_state_wanted = 0; |
7bb206e3 BS |
865 | |
866 | if (!(dd->ipath_flags & state)) { | |
867 | u64 val; | |
0fd41363 BS |
868 | ipath_cdbg(VERBOSE, "Didn't reach linkstate %s within %u" |
869 | " ms\n", | |
7bb206e3 BS |
870 | /* test INIT ahead of DOWN, both can be set */ |
871 | (state & IPATH_LINKINIT) ? "INIT" : | |
872 | ((state & IPATH_LINKDOWN) ? "DOWN" : | |
873 | ((state & IPATH_LINKARMED) ? "ARM" : "ACTIVE")), | |
874 | msecs); | |
875 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus); | |
876 | ipath_cdbg(VERBOSE, "ibcc=%llx ibcstatus=%llx (%s)\n", | |
877 | (unsigned long long) ipath_read_kreg64( | |
878 | dd, dd->ipath_kregs->kr_ibcctrl), | |
879 | (unsigned long long) val, | |
bb917144 | 880 | ipath_ibcstatus_str[val & dd->ibcs_lts_mask]); |
7bb206e3 BS |
881 | } |
882 | return (dd->ipath_flags & state) ? 0 : -ETIMEDOUT; | |
883 | } | |
884 | ||
124b4dcb DO |
885 | static void decode_sdma_errs(struct ipath_devdata *dd, ipath_err_t err, |
886 | char *buf, size_t blen) | |
887 | { | |
888 | static const struct { | |
889 | ipath_err_t err; | |
890 | const char *msg; | |
891 | } errs[] = { | |
892 | { INFINIPATH_E_SDMAGENMISMATCH, "SDmaGenMismatch" }, | |
893 | { INFINIPATH_E_SDMAOUTOFBOUND, "SDmaOutOfBound" }, | |
894 | { INFINIPATH_E_SDMATAILOUTOFBOUND, "SDmaTailOutOfBound" }, | |
895 | { INFINIPATH_E_SDMABASE, "SDmaBase" }, | |
896 | { INFINIPATH_E_SDMA1STDESC, "SDma1stDesc" }, | |
897 | { INFINIPATH_E_SDMARPYTAG, "SDmaRpyTag" }, | |
898 | { INFINIPATH_E_SDMADWEN, "SDmaDwEn" }, | |
899 | { INFINIPATH_E_SDMAMISSINGDW, "SDmaMissingDw" }, | |
900 | { INFINIPATH_E_SDMAUNEXPDATA, "SDmaUnexpData" }, | |
901 | { INFINIPATH_E_SDMADESCADDRMISALIGN, "SDmaDescAddrMisalign" }, | |
902 | { INFINIPATH_E_SENDBUFMISUSE, "SendBufMisuse" }, | |
903 | { INFINIPATH_E_SDMADISABLED, "SDmaDisabled" }, | |
904 | }; | |
905 | int i; | |
906 | int expected; | |
907 | size_t bidx = 0; | |
908 | ||
909 | for (i = 0; i < ARRAY_SIZE(errs); i++) { | |
910 | expected = (errs[i].err != INFINIPATH_E_SDMADISABLED) ? 0 : | |
911 | test_bit(IPATH_SDMA_ABORTING, &dd->ipath_sdma_status); | |
912 | if ((err & errs[i].err) && !expected) | |
913 | bidx += snprintf(buf + bidx, blen - bidx, | |
914 | "%s ", errs[i].msg); | |
915 | } | |
916 | } | |
917 | ||
8ec1077b BS |
918 | /* |
919 | * Decode the error status into strings, deciding whether to always | |
920 | * print * it or not depending on "normal packet errors" vs everything | |
921 | * else. Return 1 if "real" errors, otherwise 0 if only packet | |
922 | * errors, so caller can decide what to print with the string. | |
923 | */ | |
124b4dcb DO |
924 | int ipath_decode_err(struct ipath_devdata *dd, char *buf, size_t blen, |
925 | ipath_err_t err) | |
7bb206e3 | 926 | { |
8ec1077b | 927 | int iserr = 1; |
7bb206e3 | 928 | *buf = '\0'; |
8ec1077b BS |
929 | if (err & INFINIPATH_E_PKTERRS) { |
930 | if (!(err & ~INFINIPATH_E_PKTERRS)) | |
931 | iserr = 0; // if only packet errors. | |
932 | if (ipath_debug & __IPATH_ERRPKTDBG) { | |
933 | if (err & INFINIPATH_E_REBP) | |
934 | strlcat(buf, "EBP ", blen); | |
935 | if (err & INFINIPATH_E_RVCRC) | |
936 | strlcat(buf, "VCRC ", blen); | |
937 | if (err & INFINIPATH_E_RICRC) { | |
938 | strlcat(buf, "CRC ", blen); | |
939 | // clear for check below, so only once | |
940 | err &= INFINIPATH_E_RICRC; | |
941 | } | |
942 | if (err & INFINIPATH_E_RSHORTPKTLEN) | |
943 | strlcat(buf, "rshortpktlen ", blen); | |
944 | if (err & INFINIPATH_E_SDROPPEDDATAPKT) | |
945 | strlcat(buf, "sdroppeddatapkt ", blen); | |
946 | if (err & INFINIPATH_E_SPKTLEN) | |
947 | strlcat(buf, "spktlen ", blen); | |
948 | } | |
949 | if ((err & INFINIPATH_E_RICRC) && | |
950 | !(err&(INFINIPATH_E_RVCRC|INFINIPATH_E_REBP))) | |
951 | strlcat(buf, "CRC ", blen); | |
952 | if (!iserr) | |
953 | goto done; | |
954 | } | |
7bb206e3 BS |
955 | if (err & INFINIPATH_E_RHDRLEN) |
956 | strlcat(buf, "rhdrlen ", blen); | |
957 | if (err & INFINIPATH_E_RBADTID) | |
958 | strlcat(buf, "rbadtid ", blen); | |
959 | if (err & INFINIPATH_E_RBADVERSION) | |
960 | strlcat(buf, "rbadversion ", blen); | |
961 | if (err & INFINIPATH_E_RHDR) | |
962 | strlcat(buf, "rhdr ", blen); | |
bb917144 AJ |
963 | if (err & INFINIPATH_E_SENDSPECIALTRIGGER) |
964 | strlcat(buf, "sendspecialtrigger ", blen); | |
7bb206e3 BS |
965 | if (err & INFINIPATH_E_RLONGPKTLEN) |
966 | strlcat(buf, "rlongpktlen ", blen); | |
7bb206e3 BS |
967 | if (err & INFINIPATH_E_RMAXPKTLEN) |
968 | strlcat(buf, "rmaxpktlen ", blen); | |
969 | if (err & INFINIPATH_E_RMINPKTLEN) | |
970 | strlcat(buf, "rminpktlen ", blen); | |
8ec1077b BS |
971 | if (err & INFINIPATH_E_SMINPKTLEN) |
972 | strlcat(buf, "sminpktlen ", blen); | |
7bb206e3 BS |
973 | if (err & INFINIPATH_E_RFORMATERR) |
974 | strlcat(buf, "rformaterr ", blen); | |
975 | if (err & INFINIPATH_E_RUNSUPVL) | |
976 | strlcat(buf, "runsupvl ", blen); | |
977 | if (err & INFINIPATH_E_RUNEXPCHAR) | |
978 | strlcat(buf, "runexpchar ", blen); | |
979 | if (err & INFINIPATH_E_RIBFLOW) | |
980 | strlcat(buf, "ribflow ", blen); | |
7bb206e3 BS |
981 | if (err & INFINIPATH_E_SUNDERRUN) |
982 | strlcat(buf, "sunderrun ", blen); | |
983 | if (err & INFINIPATH_E_SPIOARMLAUNCH) | |
984 | strlcat(buf, "spioarmlaunch ", blen); | |
985 | if (err & INFINIPATH_E_SUNEXPERRPKTNUM) | |
986 | strlcat(buf, "sunexperrpktnum ", blen); | |
7bb206e3 BS |
987 | if (err & INFINIPATH_E_SDROPPEDSMPPKT) |
988 | strlcat(buf, "sdroppedsmppkt ", blen); | |
989 | if (err & INFINIPATH_E_SMAXPKTLEN) | |
990 | strlcat(buf, "smaxpktlen ", blen); | |
7bb206e3 BS |
991 | if (err & INFINIPATH_E_SUNSUPVL) |
992 | strlcat(buf, "sunsupVL ", blen); | |
7bb206e3 BS |
993 | if (err & INFINIPATH_E_INVALIDADDR) |
994 | strlcat(buf, "invalidaddr ", blen); | |
7bb206e3 BS |
995 | if (err & INFINIPATH_E_RRCVEGRFULL) |
996 | strlcat(buf, "rcvegrfull ", blen); | |
997 | if (err & INFINIPATH_E_RRCVHDRFULL) | |
998 | strlcat(buf, "rcvhdrfull ", blen); | |
999 | if (err & INFINIPATH_E_IBSTATUSCHANGED) | |
1000 | strlcat(buf, "ibcstatuschg ", blen); | |
1001 | if (err & INFINIPATH_E_RIBLOSTLINK) | |
1002 | strlcat(buf, "riblostlink ", blen); | |
1003 | if (err & INFINIPATH_E_HARDWARE) | |
1004 | strlcat(buf, "hardware ", blen); | |
1005 | if (err & INFINIPATH_E_RESET) | |
1006 | strlcat(buf, "reset ", blen); | |
124b4dcb DO |
1007 | if (err & INFINIPATH_E_SDMAERRS) |
1008 | decode_sdma_errs(dd, err, buf, blen); | |
bb917144 AJ |
1009 | if (err & INFINIPATH_E_INVALIDEEPCMD) |
1010 | strlcat(buf, "invalideepromcmd ", blen); | |
8ec1077b BS |
1011 | done: |
1012 | return iserr; | |
7bb206e3 BS |
1013 | } |
1014 | ||
1015 | /** | |
1016 | * get_rhf_errstring - decode RHF errors | |
1017 | * @err: the err number | |
1018 | * @msg: the output buffer | |
1019 | * @len: the length of the output buffer | |
1020 | * | |
1021 | * only used one place now, may want more later | |
1022 | */ | |
1023 | static void get_rhf_errstring(u32 err, char *msg, size_t len) | |
1024 | { | |
1025 | /* if no errors, and so don't need to check what's first */ | |
1026 | *msg = '\0'; | |
1027 | ||
1028 | if (err & INFINIPATH_RHF_H_ICRCERR) | |
1029 | strlcat(msg, "icrcerr ", len); | |
1030 | if (err & INFINIPATH_RHF_H_VCRCERR) | |
1031 | strlcat(msg, "vcrcerr ", len); | |
1032 | if (err & INFINIPATH_RHF_H_PARITYERR) | |
1033 | strlcat(msg, "parityerr ", len); | |
1034 | if (err & INFINIPATH_RHF_H_LENERR) | |
1035 | strlcat(msg, "lenerr ", len); | |
1036 | if (err & INFINIPATH_RHF_H_MTUERR) | |
1037 | strlcat(msg, "mtuerr ", len); | |
1038 | if (err & INFINIPATH_RHF_H_IHDRERR) | |
1039 | /* infinipath hdr checksum error */ | |
1040 | strlcat(msg, "ipathhdrerr ", len); | |
1041 | if (err & INFINIPATH_RHF_H_TIDERR) | |
1042 | strlcat(msg, "tiderr ", len); | |
1043 | if (err & INFINIPATH_RHF_H_MKERR) | |
1044 | /* bad port, offset, etc. */ | |
1045 | strlcat(msg, "invalid ipathhdr ", len); | |
1046 | if (err & INFINIPATH_RHF_H_IBERR) | |
1047 | strlcat(msg, "iberr ", len); | |
1048 | if (err & INFINIPATH_RHF_L_SWA) | |
1049 | strlcat(msg, "swA ", len); | |
1050 | if (err & INFINIPATH_RHF_L_SWB) | |
1051 | strlcat(msg, "swB ", len); | |
1052 | } | |
1053 | ||
1054 | /** | |
1055 | * ipath_get_egrbuf - get an eager buffer | |
1056 | * @dd: the infinipath device | |
1057 | * @bufnum: the eager buffer to get | |
7bb206e3 BS |
1058 | * |
1059 | * must only be called if ipath_pd[port] is known to be allocated | |
1060 | */ | |
d65708f3 | 1061 | static inline void *ipath_get_egrbuf(struct ipath_devdata *dd, u32 bufnum) |
7bb206e3 | 1062 | { |
1fd3b40f BS |
1063 | return dd->ipath_port0_skbinfo ? |
1064 | (void *) dd->ipath_port0_skbinfo[bufnum].skb->data : NULL; | |
7bb206e3 BS |
1065 | } |
1066 | ||
1067 | /** | |
1068 | * ipath_alloc_skb - allocate an skb and buffer with possible constraints | |
1069 | * @dd: the infinipath device | |
1070 | * @gfp_mask: the sk_buff SFP mask | |
1071 | */ | |
1072 | struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd, | |
1073 | gfp_t gfp_mask) | |
1074 | { | |
1075 | struct sk_buff *skb; | |
1076 | u32 len; | |
1077 | ||
1078 | /* | |
1079 | * Only fully supported way to handle this is to allocate lots | |
1080 | * extra, align as needed, and then do skb_reserve(). That wastes | |
1081 | * a lot of memory... I'll have to hack this into infinipath_copy | |
1082 | * also. | |
1083 | */ | |
1084 | ||
1085 | /* | |
1fd3b40f BS |
1086 | * We need 2 extra bytes for ipath_ether data sent in the |
1087 | * key header. In order to keep everything dword aligned, | |
1088 | * we'll reserve 4 bytes. | |
7bb206e3 | 1089 | */ |
1fd3b40f BS |
1090 | len = dd->ipath_ibmaxlen + 4; |
1091 | ||
7bb206e3 | 1092 | if (dd->ipath_flags & IPATH_4BYTE_TID) { |
1fd3b40f | 1093 | /* We need a 2KB multiple alignment, and there is no way |
7bb206e3 BS |
1094 | * to do it except to allocate extra and then skb_reserve |
1095 | * enough to bring it up to the right alignment. | |
1096 | */ | |
1fd3b40f | 1097 | len += 2047; |
7bb206e3 | 1098 | } |
1fd3b40f | 1099 | |
7bb206e3 BS |
1100 | skb = __dev_alloc_skb(len, gfp_mask); |
1101 | if (!skb) { | |
1102 | ipath_dev_err(dd, "Failed to allocate skbuff, length %u\n", | |
1103 | len); | |
1104 | goto bail; | |
1105 | } | |
1fd3b40f BS |
1106 | |
1107 | skb_reserve(skb, 4); | |
1108 | ||
7bb206e3 | 1109 | if (dd->ipath_flags & IPATH_4BYTE_TID) { |
1fd3b40f | 1110 | u32 una = (unsigned long)skb->data & 2047; |
7bb206e3 | 1111 | if (una) |
1fd3b40f BS |
1112 | skb_reserve(skb, 2048 - una); |
1113 | } | |
7bb206e3 BS |
1114 | |
1115 | bail: | |
1116 | return skb; | |
1117 | } | |
1118 | ||
3d37b9e2 RC |
1119 | static void ipath_rcv_hdrerr(struct ipath_devdata *dd, |
1120 | u32 eflags, | |
1121 | u32 l, | |
1122 | u32 etail, | |
9355fb6a RC |
1123 | __le32 *rhf_addr, |
1124 | struct ipath_message_header *hdr) | |
3d37b9e2 RC |
1125 | { |
1126 | char emsg[128]; | |
3d37b9e2 RC |
1127 | |
1128 | get_rhf_errstring(eflags, emsg, sizeof emsg); | |
3d37b9e2 RC |
1129 | ipath_cdbg(PKT, "RHFerrs %x hdrqtail=%x typ=%u " |
1130 | "tlen=%x opcode=%x egridx=%x: %s\n", | |
1131 | eflags, l, | |
9355fb6a RC |
1132 | ipath_hdrget_rcv_type(rhf_addr), |
1133 | ipath_hdrget_length_in_bytes(rhf_addr), | |
3d37b9e2 RC |
1134 | be32_to_cpu(hdr->bth[0]) >> 24, |
1135 | etail, emsg); | |
1136 | ||
1137 | /* Count local link integrity errors. */ | |
1138 | if (eflags & (INFINIPATH_RHF_H_ICRCERR | INFINIPATH_RHF_H_VCRCERR)) { | |
1139 | u8 n = (dd->ipath_ibcctrl >> | |
1140 | INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT) & | |
1141 | INFINIPATH_IBCC_PHYERRTHRESHOLD_MASK; | |
1142 | ||
1143 | if (++dd->ipath_lli_counter > n) { | |
1144 | dd->ipath_lli_counter = 0; | |
1145 | dd->ipath_lli_errors++; | |
1146 | } | |
1147 | } | |
1148 | } | |
1149 | ||
7bb206e3 BS |
1150 | /* |
1151 | * ipath_kreceive - receive a packet | |
c59a80ac | 1152 | * @pd: the infinipath port |
7bb206e3 BS |
1153 | * |
1154 | * called from interrupt handler for errors or receive interrupt | |
1155 | */ | |
c59a80ac | 1156 | void ipath_kreceive(struct ipath_portdata *pd) |
7bb206e3 | 1157 | { |
c59a80ac | 1158 | struct ipath_devdata *dd = pd->port_dd; |
9355fb6a | 1159 | __le32 *rhf_addr; |
7bb206e3 BS |
1160 | void *ebuf; |
1161 | const u32 rsize = dd->ipath_rcvhdrentsize; /* words */ | |
1162 | const u32 maxcnt = dd->ipath_rcvhdrcnt * rsize; /* words */ | |
1163 | u32 etail = -1, l, hdrqtail; | |
27b678dd | 1164 | struct ipath_message_header *hdr; |
9355fb6a | 1165 | u32 eflags, i, etype, tlen, pkttot = 0, updegr = 0, reloop = 0; |
7bb206e3 | 1166 | static u64 totcalls; /* stats, may eventually remove */ |
9355fb6a | 1167 | int last; |
7bb206e3 | 1168 | |
c59a80ac | 1169 | l = pd->port_head; |
9355fb6a RC |
1170 | rhf_addr = (__le32 *) pd->port_rcvhdrq + l + dd->ipath_rhf_offset; |
1171 | if (dd->ipath_flags & IPATH_NODMA_RTAIL) { | |
1172 | u32 seq = ipath_hdrget_seq(rhf_addr); | |
7bb206e3 | 1173 | |
9355fb6a RC |
1174 | if (seq != pd->port_seq_cnt) |
1175 | goto bail; | |
1176 | hdrqtail = 0; | |
1177 | } else { | |
1178 | hdrqtail = ipath_get_rcvhdrtail(pd); | |
1179 | if (l == hdrqtail) | |
1180 | goto bail; | |
1181 | smp_rmb(); | |
1182 | } | |
7bb206e3 | 1183 | |
9355fb6a | 1184 | reloop: |
2889d1ef | 1185 | for (last = 0, i = 1; !last; i += !last) { |
9355fb6a RC |
1186 | hdr = dd->ipath_f_get_msgheader(dd, rhf_addr); |
1187 | eflags = ipath_hdrget_err_flags(rhf_addr); | |
1188 | etype = ipath_hdrget_rcv_type(rhf_addr); | |
7bb206e3 | 1189 | /* total length */ |
9355fb6a | 1190 | tlen = ipath_hdrget_length_in_bytes(rhf_addr); |
7bb206e3 | 1191 | ebuf = NULL; |
9355fb6a RC |
1192 | if ((dd->ipath_flags & IPATH_NODMA_RTAIL) ? |
1193 | ipath_hdrget_use_egr_buf(rhf_addr) : | |
1194 | (etype != RCVHQ_RCV_TYPE_EXPECTED)) { | |
7bb206e3 | 1195 | /* |
9355fb6a | 1196 | * It turns out that the chip uses an eager buffer |
7bb206e3 BS |
1197 | * for all non-expected packets, whether it "needs" |
1198 | * one or not. So always get the index, but don't | |
1199 | * set ebuf (so we try to copy data) unless the | |
1200 | * length requires it. | |
1201 | */ | |
9355fb6a RC |
1202 | etail = ipath_hdrget_index(rhf_addr); |
1203 | updegr = 1; | |
7bb206e3 BS |
1204 | if (tlen > sizeof(*hdr) || |
1205 | etype == RCVHQ_RCV_TYPE_NON_KD) | |
d65708f3 | 1206 | ebuf = ipath_get_egrbuf(dd, etail); |
7bb206e3 BS |
1207 | } |
1208 | ||
1209 | /* | |
1210 | * both tiderr and ipathhdrerr are set for all plain IB | |
1211 | * packets; only ipathhdrerr should be set. | |
1212 | */ | |
1213 | ||
9355fb6a RC |
1214 | if (etype != RCVHQ_RCV_TYPE_NON_KD && |
1215 | etype != RCVHQ_RCV_TYPE_ERROR && | |
1216 | ipath_hdrget_ipath_ver(hdr->iph.ver_port_tid_offset) != | |
1217 | IPS_PROTO_VERSION) | |
7bb206e3 BS |
1218 | ipath_cdbg(PKT, "Bad InfiniPath protocol version " |
1219 | "%x\n", etype); | |
7bb206e3 | 1220 | |
3d37b9e2 | 1221 | if (unlikely(eflags)) |
9355fb6a | 1222 | ipath_rcv_hdrerr(dd, eflags, l, etail, rhf_addr, hdr); |
3d37b9e2 | 1223 | else if (etype == RCVHQ_RCV_TYPE_NON_KD) { |
9355fb6a | 1224 | ipath_ib_rcv(dd->verbs_dev, (u32 *)hdr, ebuf, tlen); |
34b2aafe BS |
1225 | if (dd->ipath_lli_counter) |
1226 | dd->ipath_lli_counter--; | |
9355fb6a RC |
1227 | } else if (etype == RCVHQ_RCV_TYPE_EAGER) { |
1228 | u8 opcode = be32_to_cpu(hdr->bth[0]) >> 24; | |
1229 | u32 qp = be32_to_cpu(hdr->bth[1]) & 0xffffff; | |
34b2aafe BS |
1230 | ipath_cdbg(PKT, "typ %x, opcode %x (eager, " |
1231 | "qp=%x), len %x; ignored\n", | |
9355fb6a | 1232 | etype, opcode, qp, tlen); |
7bb206e3 BS |
1233 | } |
1234 | else if (etype == RCVHQ_RCV_TYPE_EXPECTED) | |
1235 | ipath_dbg("Bug: Expected TID, opcode %x; ignored\n", | |
9355fb6a | 1236 | be32_to_cpu(hdr->bth[0]) >> 24); |
3d37b9e2 | 1237 | else { |
7bb206e3 | 1238 | /* |
9e2ef36b | 1239 | * error packet, type of error unknown. |
7bb206e3 BS |
1240 | * Probably type 3, but we don't know, so don't |
1241 | * even try to print the opcode, etc. | |
9355fb6a RC |
1242 | * Usually caused by a "bad packet", that has no |
1243 | * BTH, when the LRH says it should. | |
7bb206e3 | 1244 | */ |
9355fb6a RC |
1245 | ipath_cdbg(ERRPKT, "Error Pkt, but no eflags! egrbuf" |
1246 | " %x, len %x hdrq+%x rhf: %Lx\n", | |
70117b9e | 1247 | etail, tlen, l, (unsigned long long) |
9355fb6a RC |
1248 | le64_to_cpu(*(__le64 *) rhf_addr)); |
1249 | if (ipath_debug & __IPATH_ERRPKTDBG) { | |
1250 | u32 j, *d, dw = rsize-2; | |
1251 | if (rsize > (tlen>>2)) | |
1252 | dw = tlen>>2; | |
1253 | d = (u32 *)hdr; | |
1254 | printk(KERN_DEBUG "EPkt rcvhdr(%x dw):\n", | |
1255 | dw); | |
1256 | for (j = 0; j < dw; j++) | |
1257 | printk(KERN_DEBUG "%8x%s", d[j], | |
1258 | (j%8) == 7 ? "\n" : " "); | |
1259 | printk(KERN_DEBUG ".\n"); | |
1260 | } | |
7bb206e3 BS |
1261 | } |
1262 | l += rsize; | |
1263 | if (l >= maxcnt) | |
1264 | l = 0; | |
9355fb6a RC |
1265 | rhf_addr = (__le32 *) pd->port_rcvhdrq + |
1266 | l + dd->ipath_rhf_offset; | |
1267 | if (dd->ipath_flags & IPATH_NODMA_RTAIL) { | |
1268 | u32 seq = ipath_hdrget_seq(rhf_addr); | |
1269 | ||
1270 | if (++pd->port_seq_cnt > 13) | |
1271 | pd->port_seq_cnt = 1; | |
1272 | if (seq != pd->port_seq_cnt) | |
1273 | last = 1; | |
1274 | } else if (l == hdrqtail) | |
1275 | last = 1; | |
7bb206e3 | 1276 | /* |
f5f99929 BS |
1277 | * update head regs on last packet, and every 16 packets. |
1278 | * Reduce bus traffic, while still trying to prevent | |
1279 | * rcvhdrq overflows, for when the queue is nearly full | |
7bb206e3 | 1280 | */ |
9355fb6a RC |
1281 | if (last || !(i & 0xf)) { |
1282 | u64 lval = l; | |
1283 | ||
1284 | /* request IBA6120 and 7220 interrupt only on last */ | |
1285 | if (last) | |
1286 | lval |= dd->ipath_rhdrhead_intr_off; | |
1287 | ipath_write_ureg(dd, ur_rcvhdrhead, lval, | |
1288 | pd->port_port); | |
f5f99929 | 1289 | if (updegr) { |
8c641d4b | 1290 | ipath_write_ureg(dd, ur_rcvegrindexhead, |
9355fb6a | 1291 | etail, pd->port_port); |
f5f99929 BS |
1292 | updegr = 0; |
1293 | } | |
1294 | } | |
7bb206e3 BS |
1295 | } |
1296 | ||
9355fb6a RC |
1297 | if (!dd->ipath_rhdrhead_intr_off && !reloop && |
1298 | !(dd->ipath_flags & IPATH_NODMA_RTAIL)) { | |
525d0ca1 | 1299 | /* IBA6110 workaround; we can have a race clearing chip |
57abad25 BS |
1300 | * interrupt with another interrupt about to be delivered, |
1301 | * and can clear it before it is delivered on the GPIO | |
1302 | * workaround. By doing the extra check here for the | |
1303 | * in-memory tail register updating while we were doing | |
1304 | * earlier packets, we "almost" guarantee we have covered | |
1305 | * that case. | |
1306 | */ | |
c59a80ac | 1307 | u32 hqtail = ipath_get_rcvhdrtail(pd); |
57abad25 BS |
1308 | if (hqtail != hdrqtail) { |
1309 | hdrqtail = hqtail; | |
1310 | reloop = 1; /* loop 1 extra time at most */ | |
1311 | goto reloop; | |
1312 | } | |
1313 | } | |
1314 | ||
7bb206e3 BS |
1315 | pkttot += i; |
1316 | ||
c59a80ac | 1317 | pd->port_head = l; |
7bb206e3 | 1318 | |
7bb206e3 BS |
1319 | if (pkttot > ipath_stats.sps_maxpkts_call) |
1320 | ipath_stats.sps_maxpkts_call = pkttot; | |
1321 | ipath_stats.sps_port0pkts += pkttot; | |
1322 | ipath_stats.sps_avgpkts_call = | |
1323 | ipath_stats.sps_port0pkts / ++totcalls; | |
1324 | ||
7bb206e3 BS |
1325 | bail:; |
1326 | } | |
1327 | ||
1328 | /** | |
1329 | * ipath_update_pio_bufs - update shadow copy of the PIO availability map | |
1330 | * @dd: the infinipath device | |
1331 | * | |
1332 | * called whenever our local copy indicates we have run out of send buffers | |
1333 | * NOTE: This can be called from interrupt context by some code | |
1334 | * and from non-interrupt context by ipath_getpiobuf(). | |
1335 | */ | |
1336 | ||
1337 | static void ipath_update_pio_bufs(struct ipath_devdata *dd) | |
1338 | { | |
1339 | unsigned long flags; | |
1340 | int i; | |
1341 | const unsigned piobregs = (unsigned)dd->ipath_pioavregs; | |
1342 | ||
1343 | /* If the generation (check) bits have changed, then we update the | |
1344 | * busy bit for the corresponding PIO buffer. This algorithm will | |
1345 | * modify positions to the value they already have in some cases | |
1346 | * (i.e., no change), but it's faster than changing only the bits | |
1347 | * that have changed. | |
1348 | * | |
1349 | * We would like to do this atomicly, to avoid spinlocks in the | |
1350 | * critical send path, but that's not really possible, given the | |
1351 | * type of changes, and that this routine could be called on | |
1352 | * multiple cpu's simultaneously, so we lock in this routine only, | |
1353 | * to avoid conflicting updates; all we change is the shadow, and | |
1354 | * it's a single 64 bit memory location, so by definition the update | |
1355 | * is atomic in terms of what other cpu's can see in testing the | |
1356 | * bits. The spin_lock overhead isn't too bad, since it only | |
1357 | * happens when all buffers are in use, so only cpu overhead, not | |
1358 | * latency or bandwidth is affected. | |
1359 | */ | |
7bb206e3 BS |
1360 | if (!dd->ipath_pioavailregs_dma) { |
1361 | ipath_dbg("Update shadow pioavail, but regs_dma NULL!\n"); | |
1362 | return; | |
1363 | } | |
1364 | if (ipath_debug & __IPATH_VERBDBG) { | |
1365 | /* only if packet debug and verbose */ | |
1366 | volatile __le64 *dma = dd->ipath_pioavailregs_dma; | |
1367 | unsigned long *shadow = dd->ipath_pioavailshadow; | |
1368 | ||
1369 | ipath_cdbg(PKT, "Refill avail, dma0=%llx shad0=%lx, " | |
1370 | "d1=%llx s1=%lx, d2=%llx s2=%lx, d3=%llx " | |
1371 | "s3=%lx\n", | |
1372 | (unsigned long long) le64_to_cpu(dma[0]), | |
1373 | shadow[0], | |
1374 | (unsigned long long) le64_to_cpu(dma[1]), | |
1375 | shadow[1], | |
1376 | (unsigned long long) le64_to_cpu(dma[2]), | |
1377 | shadow[2], | |
1378 | (unsigned long long) le64_to_cpu(dma[3]), | |
1379 | shadow[3]); | |
1380 | if (piobregs > 4) | |
1381 | ipath_cdbg( | |
1382 | PKT, "2nd group, dma4=%llx shad4=%lx, " | |
1383 | "d5=%llx s5=%lx, d6=%llx s6=%lx, " | |
1384 | "d7=%llx s7=%lx\n", | |
1385 | (unsigned long long) le64_to_cpu(dma[4]), | |
1386 | shadow[4], | |
1387 | (unsigned long long) le64_to_cpu(dma[5]), | |
1388 | shadow[5], | |
1389 | (unsigned long long) le64_to_cpu(dma[6]), | |
1390 | shadow[6], | |
1391 | (unsigned long long) le64_to_cpu(dma[7]), | |
1392 | shadow[7]); | |
1393 | } | |
1394 | spin_lock_irqsave(&ipath_pioavail_lock, flags); | |
1395 | for (i = 0; i < piobregs; i++) { | |
1396 | u64 pchbusy, pchg, piov, pnew; | |
1397 | /* | |
1398 | * Chip Errata: bug 6641; even and odd qwords>3 are swapped | |
1399 | */ | |
4ea61b54 RC |
1400 | if (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS)) |
1401 | piov = le64_to_cpu(dd->ipath_pioavailregs_dma[i ^ 1]); | |
1402 | else | |
7bb206e3 | 1403 | piov = le64_to_cpu(dd->ipath_pioavailregs_dma[i]); |
c4b4d16e | 1404 | pchg = dd->ipath_pioavailkernel[i] & |
7bb206e3 BS |
1405 | ~(dd->ipath_pioavailshadow[i] ^ piov); |
1406 | pchbusy = pchg << INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT; | |
1407 | if (pchg && (pchbusy & dd->ipath_pioavailshadow[i])) { | |
1408 | pnew = dd->ipath_pioavailshadow[i] & ~pchbusy; | |
1409 | pnew |= piov & pchbusy; | |
1410 | dd->ipath_pioavailshadow[i] = pnew; | |
1411 | } | |
1412 | } | |
1413 | spin_unlock_irqrestore(&ipath_pioavail_lock, flags); | |
1414 | } | |
1415 | ||
e2ab41ca DO |
1416 | /* |
1417 | * used to force update of pioavailshadow if we can't get a pio buffer. | |
1418 | * Needed primarily due to exitting freeze mode after recovering | |
1419 | * from errors. Done lazily, because it's safer (known to not | |
1420 | * be writing pio buffers). | |
1421 | */ | |
1422 | static void ipath_reset_availshadow(struct ipath_devdata *dd) | |
1423 | { | |
1424 | int i, im; | |
1425 | unsigned long flags; | |
1426 | ||
1427 | spin_lock_irqsave(&ipath_pioavail_lock, flags); | |
1428 | for (i = 0; i < dd->ipath_pioavregs; i++) { | |
1429 | u64 val, oldval; | |
1430 | /* deal with 6110 chip bug on high register #s */ | |
1431 | im = (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS)) ? | |
1432 | i ^ 1 : i; | |
1433 | val = le64_to_cpu(dd->ipath_pioavailregs_dma[im]); | |
1434 | /* | |
1435 | * busy out the buffers not in the kernel avail list, | |
1436 | * without changing the generation bits. | |
1437 | */ | |
1438 | oldval = dd->ipath_pioavailshadow[i]; | |
1439 | dd->ipath_pioavailshadow[i] = val | | |
1440 | ((~dd->ipath_pioavailkernel[i] << | |
1441 | INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT) & | |
1442 | 0xaaaaaaaaaaaaaaaaULL); /* All BUSY bits in qword */ | |
1443 | if (oldval != dd->ipath_pioavailshadow[i]) | |
1444 | ipath_dbg("shadow[%d] was %Lx, now %lx\n", | |
70117b9e AB |
1445 | i, (unsigned long long) oldval, |
1446 | dd->ipath_pioavailshadow[i]); | |
e2ab41ca DO |
1447 | } |
1448 | spin_unlock_irqrestore(&ipath_pioavail_lock, flags); | |
1449 | } | |
1450 | ||
7bb206e3 BS |
1451 | /** |
1452 | * ipath_setrcvhdrsize - set the receive header size | |
1453 | * @dd: the infinipath device | |
1454 | * @rhdrsize: the receive header size | |
1455 | * | |
1456 | * called from user init code, and also layered driver init | |
1457 | */ | |
1458 | int ipath_setrcvhdrsize(struct ipath_devdata *dd, unsigned rhdrsize) | |
1459 | { | |
1460 | int ret = 0; | |
1461 | ||
1462 | if (dd->ipath_flags & IPATH_RCVHDRSZ_SET) { | |
1463 | if (dd->ipath_rcvhdrsize != rhdrsize) { | |
1464 | dev_info(&dd->pcidev->dev, | |
1465 | "Error: can't set protocol header " | |
1466 | "size %u, already %u\n", | |
1467 | rhdrsize, dd->ipath_rcvhdrsize); | |
1468 | ret = -EAGAIN; | |
1469 | } else | |
1470 | ipath_cdbg(VERBOSE, "Reuse same protocol header " | |
1471 | "size %u\n", dd->ipath_rcvhdrsize); | |
1472 | } else if (rhdrsize > (dd->ipath_rcvhdrentsize - | |
1473 | (sizeof(u64) / sizeof(u32)))) { | |
1474 | ipath_dbg("Error: can't set protocol header size %u " | |
1475 | "(> max %u)\n", rhdrsize, | |
1476 | dd->ipath_rcvhdrentsize - | |
1477 | (u32) (sizeof(u64) / sizeof(u32))); | |
1478 | ret = -EOVERFLOW; | |
1479 | } else { | |
1480 | dd->ipath_flags |= IPATH_RCVHDRSZ_SET; | |
1481 | dd->ipath_rcvhdrsize = rhdrsize; | |
1482 | ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize, | |
1483 | dd->ipath_rcvhdrsize); | |
1484 | ipath_cdbg(VERBOSE, "Set protocol header size to %u\n", | |
1485 | dd->ipath_rcvhdrsize); | |
1486 | } | |
1487 | return ret; | |
1488 | } | |
1489 | ||
c4b4d16e RC |
1490 | /* |
1491 | * debugging code and stats updates if no pio buffers available. | |
1492 | */ | |
1493 | static noinline void no_pio_bufs(struct ipath_devdata *dd) | |
1494 | { | |
1495 | unsigned long *shadow = dd->ipath_pioavailshadow; | |
1496 | __le64 *dma = (__le64 *)dd->ipath_pioavailregs_dma; | |
1497 | ||
1498 | dd->ipath_upd_pio_shadow = 1; | |
1499 | ||
1500 | /* | |
1501 | * not atomic, but if we lose a stat count in a while, that's OK | |
1502 | */ | |
1503 | ipath_stats.sps_nopiobufs++; | |
1504 | if (!(++dd->ipath_consec_nopiobuf % 100000)) { | |
e2ab41ca DO |
1505 | ipath_force_pio_avail_update(dd); /* at start */ |
1506 | ipath_dbg("%u tries no piobufavail ts%lx; dmacopy: " | |
1507 | "%llx %llx %llx %llx\n" | |
1508 | "ipath shadow: %lx %lx %lx %lx\n", | |
c4b4d16e | 1509 | dd->ipath_consec_nopiobuf, |
e2ab41ca | 1510 | (unsigned long)get_cycles(), |
c4b4d16e RC |
1511 | (unsigned long long) le64_to_cpu(dma[0]), |
1512 | (unsigned long long) le64_to_cpu(dma[1]), | |
1513 | (unsigned long long) le64_to_cpu(dma[2]), | |
1514 | (unsigned long long) le64_to_cpu(dma[3]), | |
1515 | shadow[0], shadow[1], shadow[2], shadow[3]); | |
1516 | /* | |
1517 | * 4 buffers per byte, 4 registers above, cover rest | |
1518 | * below | |
1519 | */ | |
1520 | if ((dd->ipath_piobcnt2k + dd->ipath_piobcnt4k) > | |
1521 | (sizeof(shadow[0]) * 4 * 4)) | |
e2ab41ca DO |
1522 | ipath_dbg("2nd group: dmacopy: " |
1523 | "%llx %llx %llx %llx\n" | |
1524 | "ipath shadow: %lx %lx %lx %lx\n", | |
c4b4d16e RC |
1525 | (unsigned long long)le64_to_cpu(dma[4]), |
1526 | (unsigned long long)le64_to_cpu(dma[5]), | |
1527 | (unsigned long long)le64_to_cpu(dma[6]), | |
1528 | (unsigned long long)le64_to_cpu(dma[7]), | |
e2ab41ca DO |
1529 | shadow[4], shadow[5], shadow[6], shadow[7]); |
1530 | ||
1531 | /* at end, so update likely happened */ | |
1532 | ipath_reset_availshadow(dd); | |
c4b4d16e RC |
1533 | } |
1534 | } | |
1535 | ||
1536 | /* | |
1537 | * common code for normal driver pio buffer allocation, and reserved | |
1538 | * allocation. | |
7bb206e3 BS |
1539 | * |
1540 | * do appropriate marking as busy, etc. | |
1541 | * returns buffer number if one found (>=0), negative number is error. | |
7bb206e3 | 1542 | */ |
c4b4d16e RC |
1543 | static u32 __iomem *ipath_getpiobuf_range(struct ipath_devdata *dd, |
1544 | u32 *pbufnum, u32 first, u32 last, u32 firsti) | |
7bb206e3 | 1545 | { |
c4b4d16e RC |
1546 | int i, j, updated = 0; |
1547 | unsigned piobcnt; | |
7bb206e3 BS |
1548 | unsigned long flags; |
1549 | unsigned long *shadow = dd->ipath_pioavailshadow; | |
1550 | u32 __iomem *buf; | |
1551 | ||
c4b4d16e | 1552 | piobcnt = last - first; |
7bb206e3 BS |
1553 | if (dd->ipath_upd_pio_shadow) { |
1554 | /* | |
1555 | * Minor optimization. If we had no buffers on last call, | |
1556 | * start out by doing the update; continue and do scan even | |
1557 | * if no buffers were updated, to be paranoid | |
1558 | */ | |
1559 | ipath_update_pio_bufs(dd); | |
c4b4d16e RC |
1560 | updated++; |
1561 | i = first; | |
7bb206e3 | 1562 | } else |
c4b4d16e | 1563 | i = firsti; |
7bb206e3 BS |
1564 | rescan: |
1565 | /* | |
1566 | * while test_and_set_bit() is atomic, we do that and then the | |
1567 | * change_bit(), and the pair is not. See if this is the cause | |
1568 | * of the remaining armlaunch errors. | |
1569 | */ | |
1570 | spin_lock_irqsave(&ipath_pioavail_lock, flags); | |
c4b4d16e RC |
1571 | for (j = 0; j < piobcnt; j++, i++) { |
1572 | if (i >= last) | |
1573 | i = first; | |
1574 | if (__test_and_set_bit((2 * i) + 1, shadow)) | |
7bb206e3 BS |
1575 | continue; |
1576 | /* flip generation bit */ | |
c4b4d16e | 1577 | __change_bit(2 * i, shadow); |
7bb206e3 BS |
1578 | break; |
1579 | } | |
1580 | spin_unlock_irqrestore(&ipath_pioavail_lock, flags); | |
1581 | ||
c4b4d16e | 1582 | if (j == piobcnt) { |
7bb206e3 | 1583 | if (!updated) { |
c4b4d16e RC |
1584 | /* |
1585 | * first time through; shadow exhausted, but may be | |
1586 | * buffers available, try an update and then rescan. | |
1587 | */ | |
7bb206e3 | 1588 | ipath_update_pio_bufs(dd); |
c4b4d16e RC |
1589 | updated++; |
1590 | i = first; | |
7bb206e3 | 1591 | goto rescan; |
c4b4d16e RC |
1592 | } else if (updated == 1 && piobcnt <= |
1593 | ((dd->ipath_sendctrl | |
1594 | >> INFINIPATH_S_UPDTHRESH_SHIFT) & | |
1595 | INFINIPATH_S_UPDTHRESH_MASK)) { | |
7bb206e3 | 1596 | /* |
c4b4d16e RC |
1597 | * for chips supporting and using the update |
1598 | * threshold we need to force an update of the | |
1599 | * in-memory copy if the count is less than the | |
1600 | * thershold, then check one more time. | |
7bb206e3 | 1601 | */ |
c4b4d16e RC |
1602 | ipath_force_pio_avail_update(dd); |
1603 | ipath_update_pio_bufs(dd); | |
1604 | updated++; | |
1605 | i = first; | |
1606 | goto rescan; | |
7bb206e3 | 1607 | } |
c4b4d16e RC |
1608 | |
1609 | no_pio_bufs(dd); | |
7bb206e3 | 1610 | buf = NULL; |
c4b4d16e RC |
1611 | } else { |
1612 | if (i < dd->ipath_piobcnt2k) | |
1613 | buf = (u32 __iomem *) (dd->ipath_pio2kbase + | |
1614 | i * dd->ipath_palign); | |
1615 | else | |
1616 | buf = (u32 __iomem *) | |
1617 | (dd->ipath_pio4kbase + | |
1618 | (i - dd->ipath_piobcnt2k) * dd->ipath_4kalign); | |
1619 | if (pbufnum) | |
1620 | *pbufnum = i; | |
7bb206e3 BS |
1621 | } |
1622 | ||
c4b4d16e RC |
1623 | return buf; |
1624 | } | |
7bb206e3 | 1625 | |
c4b4d16e RC |
1626 | /** |
1627 | * ipath_getpiobuf - find an available pio buffer | |
1628 | * @dd: the infinipath device | |
1629 | * @plen: the size of the PIO buffer needed in 32-bit words | |
1630 | * @pbufnum: the buffer number is placed here | |
1631 | */ | |
1632 | u32 __iomem *ipath_getpiobuf(struct ipath_devdata *dd, u32 plen, u32 *pbufnum) | |
1633 | { | |
1634 | u32 __iomem *buf; | |
1635 | u32 pnum, nbufs; | |
1636 | u32 first, lasti; | |
1637 | ||
1638 | if (plen + 1 >= IPATH_SMALLBUF_DWORDS) { | |
1639 | first = dd->ipath_piobcnt2k; | |
1640 | lasti = dd->ipath_lastpioindexl; | |
1641 | } else { | |
1642 | first = 0; | |
1643 | lasti = dd->ipath_lastpioindex; | |
1644 | } | |
1645 | nbufs = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k; | |
1646 | buf = ipath_getpiobuf_range(dd, &pnum, first, nbufs, lasti); | |
1647 | ||
1648 | if (buf) { | |
1649 | /* | |
1650 | * Set next starting place. It's just an optimization, | |
1651 | * it doesn't matter who wins on this, so no locking | |
1652 | */ | |
1653 | if (plen + 1 >= IPATH_SMALLBUF_DWORDS) | |
1654 | dd->ipath_lastpioindexl = pnum + 1; | |
1655 | else | |
1656 | dd->ipath_lastpioindex = pnum + 1; | |
1657 | if (dd->ipath_upd_pio_shadow) | |
1658 | dd->ipath_upd_pio_shadow = 0; | |
1659 | if (dd->ipath_consec_nopiobuf) | |
1660 | dd->ipath_consec_nopiobuf = 0; | |
1661 | ipath_cdbg(VERBOSE, "Return piobuf%u %uk @ %p\n", | |
1662 | pnum, (pnum < dd->ipath_piobcnt2k) ? 2 : 4, buf); | |
1663 | if (pbufnum) | |
1664 | *pbufnum = pnum; | |
1665 | ||
1666 | } | |
7bb206e3 BS |
1667 | return buf; |
1668 | } | |
1669 | ||
c4b4d16e RC |
1670 | /** |
1671 | * ipath_chg_pioavailkernel - change which send buffers are available for kernel | |
1672 | * @dd: the infinipath device | |
1673 | * @start: the starting send buffer number | |
1674 | * @len: the number of send buffers | |
1675 | * @avail: true if the buffers are available for kernel use, false otherwise | |
1676 | */ | |
1677 | void ipath_chg_pioavailkernel(struct ipath_devdata *dd, unsigned start, | |
1678 | unsigned len, int avail) | |
1679 | { | |
1680 | unsigned long flags; | |
598cb6f3 | 1681 | unsigned end, cnt = 0; |
c4b4d16e RC |
1682 | |
1683 | /* There are two bits per send buffer (busy and generation) */ | |
1684 | start *= 2; | |
e2ab41ca | 1685 | end = start + len * 2; |
c4b4d16e | 1686 | |
c4b4d16e | 1687 | spin_lock_irqsave(&ipath_pioavail_lock, flags); |
e2ab41ca | 1688 | /* Set or clear the busy bit in the shadow. */ |
c4b4d16e RC |
1689 | while (start < end) { |
1690 | if (avail) { | |
e2ab41ca DO |
1691 | unsigned long dma; |
1692 | int i, im; | |
1693 | /* | |
1694 | * the BUSY bit will never be set, because we disarm | |
1695 | * the user buffers before we hand them back to the | |
1696 | * kernel. We do have to make sure the generation | |
1697 | * bit is set correctly in shadow, since it could | |
1698 | * have changed many times while allocated to user. | |
1699 | * We can't use the bitmap functions on the full | |
1700 | * dma array because it is always little-endian, so | |
1701 | * we have to flip to host-order first. | |
1702 | * BITS_PER_LONG is slightly wrong, since it's | |
1703 | * always 64 bits per register in chip... | |
1704 | * We only work on 64 bit kernels, so that's OK. | |
1705 | */ | |
1706 | /* deal with 6110 chip bug on high register #s */ | |
1707 | i = start / BITS_PER_LONG; | |
1708 | im = (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS)) ? | |
1709 | i ^ 1 : i; | |
1710 | __clear_bit(INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT | |
1711 | + start, dd->ipath_pioavailshadow); | |
1712 | dma = (unsigned long) le64_to_cpu( | |
1713 | dd->ipath_pioavailregs_dma[im]); | |
1714 | if (test_bit((INFINIPATH_SENDPIOAVAIL_CHECK_SHIFT | |
1715 | + start) % BITS_PER_LONG, &dma)) | |
1716 | __set_bit(INFINIPATH_SENDPIOAVAIL_CHECK_SHIFT | |
1717 | + start, dd->ipath_pioavailshadow); | |
1718 | else | |
1719 | __clear_bit(INFINIPATH_SENDPIOAVAIL_CHECK_SHIFT | |
1720 | + start, dd->ipath_pioavailshadow); | |
c4b4d16e RC |
1721 | __set_bit(start, dd->ipath_pioavailkernel); |
1722 | } else { | |
1723 | __set_bit(start + INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT, | |
1724 | dd->ipath_pioavailshadow); | |
1725 | __clear_bit(start, dd->ipath_pioavailkernel); | |
1726 | } | |
1727 | start += 2; | |
1728 | } | |
e2ab41ca DO |
1729 | |
1730 | if (dd->ipath_pioupd_thresh) { | |
1731 | end = 2 * (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k); | |
598cb6f3 | 1732 | cnt = bitmap_weight(dd->ipath_pioavailkernel, end); |
e2ab41ca | 1733 | } |
c4b4d16e | 1734 | spin_unlock_irqrestore(&ipath_pioavail_lock, flags); |
e2ab41ca DO |
1735 | |
1736 | /* | |
1737 | * When moving buffers from kernel to user, if number assigned to | |
1738 | * the user is less than the pio update threshold, and threshold | |
1739 | * is supported (cnt was computed > 0), drop the update threshold | |
1740 | * so we update at least once per allocated number of buffers. | |
1741 | * In any case, if the kernel buffers are less than the threshold, | |
1742 | * drop the threshold. We don't bother increasing it, having once | |
1743 | * decreased it, since it would typically just cycle back and forth. | |
1744 | * If we don't decrease below buffers in use, we can wait a long | |
1745 | * time for an update, until some other context uses PIO buffers. | |
1746 | */ | |
1747 | if (!avail && len < cnt) | |
1748 | cnt = len; | |
1749 | if (cnt < dd->ipath_pioupd_thresh) { | |
1750 | dd->ipath_pioupd_thresh = cnt; | |
1751 | ipath_dbg("Decreased pio update threshold to %u\n", | |
1752 | dd->ipath_pioupd_thresh); | |
1753 | spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags); | |
1754 | dd->ipath_sendctrl &= ~(INFINIPATH_S_UPDTHRESH_MASK | |
1755 | << INFINIPATH_S_UPDTHRESH_SHIFT); | |
1756 | dd->ipath_sendctrl |= dd->ipath_pioupd_thresh | |
1757 | << INFINIPATH_S_UPDTHRESH_SHIFT; | |
1758 | ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, | |
1759 | dd->ipath_sendctrl); | |
1760 | spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags); | |
1761 | } | |
c4b4d16e RC |
1762 | } |
1763 | ||
7bb206e3 BS |
1764 | /** |
1765 | * ipath_create_rcvhdrq - create a receive header queue | |
1766 | * @dd: the infinipath device | |
1767 | * @pd: the port data | |
1768 | * | |
f37bda92 BS |
1769 | * this must be contiguous memory (from an i/o perspective), and must be |
1770 | * DMA'able (which means for some systems, it will go through an IOMMU, | |
1771 | * or be forced into a low address range). | |
7bb206e3 BS |
1772 | */ |
1773 | int ipath_create_rcvhdrq(struct ipath_devdata *dd, | |
1774 | struct ipath_portdata *pd) | |
1775 | { | |
f37bda92 | 1776 | int ret = 0; |
7bb206e3 | 1777 | |
7bb206e3 | 1778 | if (!pd->port_rcvhdrq) { |
f37bda92 | 1779 | dma_addr_t phys_hdrqtail; |
7bb206e3 | 1780 | gfp_t gfp_flags = GFP_USER | __GFP_COMP; |
f37bda92 BS |
1781 | int amt = ALIGN(dd->ipath_rcvhdrcnt * dd->ipath_rcvhdrentsize * |
1782 | sizeof(u32), PAGE_SIZE); | |
7bb206e3 BS |
1783 | |
1784 | pd->port_rcvhdrq = dma_alloc_coherent( | |
1785 | &dd->pcidev->dev, amt, &pd->port_rcvhdrq_phys, | |
1786 | gfp_flags); | |
1787 | ||
1788 | if (!pd->port_rcvhdrq) { | |
1789 | ipath_dev_err(dd, "attempt to allocate %d bytes " | |
1790 | "for port %u rcvhdrq failed\n", | |
1791 | amt, pd->port_port); | |
1792 | ret = -ENOMEM; | |
1793 | goto bail; | |
1794 | } | |
9355fb6a RC |
1795 | |
1796 | if (!(dd->ipath_flags & IPATH_NODMA_RTAIL)) { | |
1797 | pd->port_rcvhdrtail_kvaddr = dma_alloc_coherent( | |
1798 | &dd->pcidev->dev, PAGE_SIZE, &phys_hdrqtail, | |
1799 | GFP_KERNEL); | |
1800 | if (!pd->port_rcvhdrtail_kvaddr) { | |
1801 | ipath_dev_err(dd, "attempt to allocate 1 page " | |
1802 | "for port %u rcvhdrqtailaddr " | |
1803 | "failed\n", pd->port_port); | |
1804 | ret = -ENOMEM; | |
1805 | dma_free_coherent(&dd->pcidev->dev, amt, | |
1806 | pd->port_rcvhdrq, | |
1807 | pd->port_rcvhdrq_phys); | |
1808 | pd->port_rcvhdrq = NULL; | |
1809 | goto bail; | |
1810 | } | |
1811 | pd->port_rcvhdrqtailaddr_phys = phys_hdrqtail; | |
1812 | ipath_cdbg(VERBOSE, "port %d hdrtailaddr, %llx " | |
1813 | "physical\n", pd->port_port, | |
1814 | (unsigned long long) phys_hdrqtail); | |
f37bda92 | 1815 | } |
7bb206e3 BS |
1816 | |
1817 | pd->port_rcvhdrq_size = amt; | |
1818 | ||
1819 | ipath_cdbg(VERBOSE, "%d pages at %p (phys %lx) size=%lu " | |
1820 | "for port %u rcvhdr Q\n", | |
1821 | amt >> PAGE_SHIFT, pd->port_rcvhdrq, | |
1822 | (unsigned long) pd->port_rcvhdrq_phys, | |
1823 | (unsigned long) pd->port_rcvhdrq_size, | |
1824 | pd->port_port); | |
7bb206e3 | 1825 | } |
f37bda92 BS |
1826 | else |
1827 | ipath_cdbg(VERBOSE, "reuse port %d rcvhdrq @%p %llx phys; " | |
1828 | "hdrtailaddr@%p %llx physical\n", | |
1829 | pd->port_port, pd->port_rcvhdrq, | |
1fd3b40f BS |
1830 | (unsigned long long) pd->port_rcvhdrq_phys, |
1831 | pd->port_rcvhdrtail_kvaddr, (unsigned long long) | |
1832 | pd->port_rcvhdrqtailaddr_phys); | |
f37bda92 BS |
1833 | |
1834 | /* clear for security and sanity on each use */ | |
1835 | memset(pd->port_rcvhdrq, 0, pd->port_rcvhdrq_size); | |
c59a80ac RC |
1836 | if (pd->port_rcvhdrtail_kvaddr) |
1837 | memset(pd->port_rcvhdrtail_kvaddr, 0, PAGE_SIZE); | |
7bb206e3 BS |
1838 | |
1839 | /* | |
1840 | * tell chip each time we init it, even if we are re-using previous | |
f37bda92 | 1841 | * memory (we zero the register at process close) |
7bb206e3 | 1842 | */ |
f37bda92 BS |
1843 | ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdrtailaddr, |
1844 | pd->port_port, pd->port_rcvhdrqtailaddr_phys); | |
7bb206e3 BS |
1845 | ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdraddr, |
1846 | pd->port_port, pd->port_rcvhdrq_phys); | |
1847 | ||
7bb206e3 BS |
1848 | bail: |
1849 | return ret; | |
1850 | } | |
1851 | ||
9380068f DO |
1852 | |
1853 | /* | |
1854 | * Flush all sends that might be in the ready to send state, as well as any | |
1855 | * that are in the process of being sent. Used whenever we need to be | |
1856 | * sure the send side is idle. Cleans up all buffer state by canceling | |
1857 | * all pio buffers, and issuing an abort, which cleans up anything in the | |
1858 | * launch fifo. The cancel is superfluous on some chip versions, but | |
1859 | * it's safer to always do it. | |
1860 | * PIOAvail bits are updated by the chip as if normal send had happened. | |
1861 | */ | |
3810f2a8 | 1862 | void ipath_cancel_sends(struct ipath_devdata *dd, int restore_sendctrl) |
9380068f | 1863 | { |
124b4dcb DO |
1864 | unsigned long flags; |
1865 | ||
bb917144 AJ |
1866 | if (dd->ipath_flags & IPATH_IB_AUTONEG_INPROG) { |
1867 | ipath_cdbg(VERBOSE, "Ignore while in autonegotiation\n"); | |
1868 | goto bail; | |
1869 | } | |
124b4dcb DO |
1870 | /* |
1871 | * If we have SDMA, and it's not disabled, we have to kick off the | |
1872 | * abort state machine, provided we aren't already aborting. | |
1873 | * If we are in the process of aborting SDMA (!DISABLED, but ABORTING), | |
1874 | * we skip the rest of this routine. It is already "in progress" | |
1875 | */ | |
1876 | if (dd->ipath_flags & IPATH_HAS_SEND_DMA) { | |
1877 | int skip_cancel; | |
f018c7e1 | 1878 | unsigned long *statp = &dd->ipath_sdma_status; |
124b4dcb DO |
1879 | |
1880 | spin_lock_irqsave(&dd->ipath_sdma_lock, flags); | |
1881 | skip_cancel = | |
ab69b3cf JG |
1882 | test_and_set_bit(IPATH_SDMA_ABORTING, statp) |
1883 | && !test_bit(IPATH_SDMA_DISABLED, statp); | |
124b4dcb DO |
1884 | spin_unlock_irqrestore(&dd->ipath_sdma_lock, flags); |
1885 | if (skip_cancel) | |
1886 | goto bail; | |
1887 | } | |
1888 | ||
9380068f | 1889 | ipath_dbg("Cancelling all in-progress send buffers\n"); |
2ba3f56e RC |
1890 | |
1891 | /* skip armlaunch errs for a while */ | |
1892 | dd->ipath_lastcancel = jiffies + HZ / 2; | |
1893 | ||
9380068f | 1894 | /* |
124b4dcb DO |
1895 | * The abort bit is auto-clearing. We also don't want pioavail |
1896 | * update happening during this, and we don't want any other | |
1897 | * sends going out, so turn those off for the duration. We read | |
1898 | * the scratch register to be sure that cancels and the abort | |
1899 | * have taken effect in the chip. Otherwise two parts are same | |
1900 | * as ipath_force_pio_avail_update() | |
9380068f | 1901 | */ |
124b4dcb DO |
1902 | spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags); |
1903 | dd->ipath_sendctrl &= ~(INFINIPATH_S_PIOBUFAVAILUPD | |
1904 | | INFINIPATH_S_PIOENABLE); | |
9380068f | 1905 | ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, |
124b4dcb | 1906 | dd->ipath_sendctrl | INFINIPATH_S_ABORT); |
9380068f | 1907 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); |
124b4dcb DO |
1908 | spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags); |
1909 | ||
1910 | /* disarm all send buffers */ | |
9380068f | 1911 | ipath_disarm_piobufs(dd, 0, |
124b4dcb DO |
1912 | dd->ipath_piobcnt2k + dd->ipath_piobcnt4k); |
1913 | ||
ab69b3cf JG |
1914 | if (dd->ipath_flags & IPATH_HAS_SEND_DMA) |
1915 | set_bit(IPATH_SDMA_DISARMED, &dd->ipath_sdma_status); | |
1916 | ||
124b4dcb DO |
1917 | if (restore_sendctrl) { |
1918 | /* else done by caller later if needed */ | |
1919 | spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags); | |
1920 | dd->ipath_sendctrl |= INFINIPATH_S_PIOBUFAVAILUPD | | |
1921 | INFINIPATH_S_PIOENABLE; | |
3810f2a8 | 1922 | ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, |
124b4dcb DO |
1923 | dd->ipath_sendctrl); |
1924 | /* and again, be sure all have hit the chip */ | |
1925 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); | |
1926 | spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags); | |
1927 | } | |
9380068f | 1928 | |
124b4dcb DO |
1929 | if ((dd->ipath_flags & IPATH_HAS_SEND_DMA) && |
1930 | !test_bit(IPATH_SDMA_DISABLED, &dd->ipath_sdma_status) && | |
1931 | test_bit(IPATH_SDMA_RUNNING, &dd->ipath_sdma_status)) { | |
1932 | spin_lock_irqsave(&dd->ipath_sdma_lock, flags); | |
1933 | /* only wait so long for intr */ | |
1934 | dd->ipath_sdma_abort_intr_timeout = jiffies + HZ; | |
1935 | dd->ipath_sdma_reset_wait = 200; | |
124b4dcb DO |
1936 | if (!test_bit(IPATH_SDMA_SHUTDOWN, &dd->ipath_sdma_status)) |
1937 | tasklet_hi_schedule(&dd->ipath_sdma_abort_task); | |
1938 | spin_unlock_irqrestore(&dd->ipath_sdma_lock, flags); | |
1939 | } | |
bb917144 | 1940 | bail:; |
9380068f DO |
1941 | } |
1942 | ||
c4b4d16e RC |
1943 | /* |
1944 | * Force an update of in-memory copy of the pioavail registers, when | |
1945 | * needed for any of a variety of reasons. We read the scratch register | |
1946 | * to make it highly likely that the update will have happened by the | |
1947 | * time we return. If already off (as in cancel_sends above), this | |
1948 | * routine is a nop, on the assumption that the caller will "do the | |
1949 | * right thing". | |
1950 | */ | |
1951 | void ipath_force_pio_avail_update(struct ipath_devdata *dd) | |
1952 | { | |
1953 | unsigned long flags; | |
1954 | ||
1955 | spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags); | |
1956 | if (dd->ipath_sendctrl & INFINIPATH_S_PIOBUFAVAILUPD) { | |
1957 | ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, | |
1958 | dd->ipath_sendctrl & ~INFINIPATH_S_PIOBUFAVAILUPD); | |
1959 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); | |
1960 | ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, | |
1961 | dd->ipath_sendctrl); | |
1962 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); | |
1963 | } | |
1964 | spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags); | |
1965 | } | |
1966 | ||
4330e4da MA |
1967 | static void ipath_set_ib_lstate(struct ipath_devdata *dd, int linkcmd, |
1968 | int linitcmd) | |
7bb206e3 | 1969 | { |
4330e4da | 1970 | u64 mod_wd; |
7bb206e3 | 1971 | static const char *what[4] = { |
140277e9 RC |
1972 | [0] = "NOP", |
1973 | [INFINIPATH_IBCC_LINKCMD_DOWN] = "DOWN", | |
7bb206e3 BS |
1974 | [INFINIPATH_IBCC_LINKCMD_ARMED] = "ARMED", |
1975 | [INFINIPATH_IBCC_LINKCMD_ACTIVE] = "ACTIVE" | |
1976 | }; | |
f37bda92 | 1977 | |
4330e4da MA |
1978 | if (linitcmd == INFINIPATH_IBCC_LINKINITCMD_DISABLE) { |
1979 | /* | |
1980 | * If we are told to disable, note that so link-recovery | |
1981 | * code does not attempt to bring us back up. | |
1982 | */ | |
1983 | preempt_disable(); | |
1984 | dd->ipath_flags |= IPATH_IB_LINK_DISABLED; | |
1985 | preempt_enable(); | |
1986 | } else if (linitcmd) { | |
1987 | /* | |
1988 | * Any other linkinitcmd will lead to LINKDOWN and then | |
1989 | * to INIT (if all is well), so clear flag to let | |
1990 | * link-recovery code attempt to bring us back up. | |
1991 | */ | |
1992 | preempt_disable(); | |
1993 | dd->ipath_flags &= ~IPATH_IB_LINK_DISABLED; | |
1994 | preempt_enable(); | |
1995 | } | |
1996 | ||
1997 | mod_wd = (linkcmd << dd->ibcc_lc_shift) | | |
1998 | (linitcmd << INFINIPATH_IBCC_LINKINITCMD_SHIFT); | |
1999 | ipath_cdbg(VERBOSE, | |
2000 | "Moving unit %u to %s (initcmd=0x%x), current ltstate is %s\n", | |
2001 | dd->ipath_unit, what[linkcmd], linitcmd, | |
2002 | ipath_ibcstatus_str[ipath_ib_linktrstate(dd, | |
58411d1c | 2003 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus))]); |
7bb206e3 BS |
2004 | |
2005 | ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, | |
4330e4da MA |
2006 | dd->ipath_ibcctrl | mod_wd); |
2007 | /* read from chip so write is flushed */ | |
2008 | (void) ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus); | |
7bb206e3 BS |
2009 | } |
2010 | ||
34b2aafe BS |
2011 | int ipath_set_linkstate(struct ipath_devdata *dd, u8 newstate) |
2012 | { | |
2013 | u32 lstate; | |
2014 | int ret; | |
2015 | ||
2016 | switch (newstate) { | |
140277e9 | 2017 | case IPATH_IB_LINKDOWN_ONLY: |
4330e4da | 2018 | ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN, 0); |
140277e9 RC |
2019 | /* don't wait */ |
2020 | ret = 0; | |
2021 | goto bail; | |
2022 | ||
34b2aafe | 2023 | case IPATH_IB_LINKDOWN: |
4330e4da MA |
2024 | ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN, |
2025 | INFINIPATH_IBCC_LINKINITCMD_POLL); | |
34b2aafe BS |
2026 | /* don't wait */ |
2027 | ret = 0; | |
2028 | goto bail; | |
2029 | ||
2030 | case IPATH_IB_LINKDOWN_SLEEP: | |
4330e4da MA |
2031 | ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN, |
2032 | INFINIPATH_IBCC_LINKINITCMD_SLEEP); | |
34b2aafe BS |
2033 | /* don't wait */ |
2034 | ret = 0; | |
2035 | goto bail; | |
2036 | ||
2037 | case IPATH_IB_LINKDOWN_DISABLE: | |
4330e4da MA |
2038 | ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN, |
2039 | INFINIPATH_IBCC_LINKINITCMD_DISABLE); | |
34b2aafe BS |
2040 | /* don't wait */ |
2041 | ret = 0; | |
2042 | goto bail; | |
2043 | ||
34b2aafe BS |
2044 | case IPATH_IB_LINKARM: |
2045 | if (dd->ipath_flags & IPATH_LINKARMED) { | |
2046 | ret = 0; | |
2047 | goto bail; | |
2048 | } | |
2049 | if (!(dd->ipath_flags & | |
2050 | (IPATH_LINKINIT | IPATH_LINKACTIVE))) { | |
2051 | ret = -EINVAL; | |
2052 | goto bail; | |
2053 | } | |
4330e4da MA |
2054 | ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_ARMED, 0); |
2055 | ||
34b2aafe BS |
2056 | /* |
2057 | * Since the port can transition to ACTIVE by receiving | |
2058 | * a non VL 15 packet, wait for either state. | |
2059 | */ | |
2060 | lstate = IPATH_LINKARMED | IPATH_LINKACTIVE; | |
2061 | break; | |
2062 | ||
2063 | case IPATH_IB_LINKACTIVE: | |
2064 | if (dd->ipath_flags & IPATH_LINKACTIVE) { | |
2065 | ret = 0; | |
2066 | goto bail; | |
2067 | } | |
2068 | if (!(dd->ipath_flags & IPATH_LINKARMED)) { | |
2069 | ret = -EINVAL; | |
2070 | goto bail; | |
2071 | } | |
4330e4da | 2072 | ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_ACTIVE, 0); |
34b2aafe BS |
2073 | lstate = IPATH_LINKACTIVE; |
2074 | break; | |
2075 | ||
946db67f BS |
2076 | case IPATH_IB_LINK_LOOPBACK: |
2077 | dev_info(&dd->pcidev->dev, "Enabling IB local loopback\n"); | |
2078 | dd->ipath_ibcctrl |= INFINIPATH_IBCC_LOOPBACK; | |
2079 | ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, | |
2080 | dd->ipath_ibcctrl); | |
b3e8f541 DO |
2081 | |
2082 | /* turn heartbeat off, as it causes loopback to fail */ | |
2083 | dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT, | |
2084 | IPATH_IB_HRTBT_OFF); | |
2085 | /* don't wait */ | |
946db67f | 2086 | ret = 0; |
b3e8f541 | 2087 | goto bail; |
946db67f BS |
2088 | |
2089 | case IPATH_IB_LINK_EXTERNAL: | |
b3e8f541 DO |
2090 | dev_info(&dd->pcidev->dev, |
2091 | "Disabling IB local loopback (normal)\n"); | |
2092 | dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT, | |
2093 | IPATH_IB_HRTBT_ON); | |
946db67f BS |
2094 | dd->ipath_ibcctrl &= ~INFINIPATH_IBCC_LOOPBACK; |
2095 | ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, | |
2096 | dd->ipath_ibcctrl); | |
b3e8f541 | 2097 | /* don't wait */ |
946db67f | 2098 | ret = 0; |
b3e8f541 DO |
2099 | goto bail; |
2100 | ||
2101 | /* | |
2102 | * Heartbeat can be explicitly enabled by the user via | |
2103 | * "hrtbt_enable" "file", and if disabled, trying to enable here | |
2104 | * will have no effect. Implicit changes (heartbeat off when | |
2105 | * loopback on, and vice versa) are included to ease testing. | |
2106 | */ | |
2107 | case IPATH_IB_LINK_HRTBT: | |
2108 | ret = dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT, | |
2109 | IPATH_IB_HRTBT_ON); | |
2110 | goto bail; | |
2111 | ||
2112 | case IPATH_IB_LINK_NO_HRTBT: | |
2113 | ret = dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT, | |
2114 | IPATH_IB_HRTBT_OFF); | |
2115 | goto bail; | |
946db67f | 2116 | |
34b2aafe BS |
2117 | default: |
2118 | ipath_dbg("Invalid linkstate 0x%x requested\n", newstate); | |
2119 | ret = -EINVAL; | |
2120 | goto bail; | |
2121 | } | |
2122 | ret = ipath_wait_linkstate(dd, lstate, 2000); | |
2123 | ||
2124 | bail: | |
2125 | return ret; | |
2126 | } | |
2127 | ||
2128 | /** | |
2129 | * ipath_set_mtu - set the MTU | |
2130 | * @dd: the infinipath device | |
2131 | * @arg: the new MTU | |
2132 | * | |
2133 | * we can handle "any" incoming size, the issue here is whether we | |
2134 | * need to restrict our outgoing size. For now, we don't do any | |
2135 | * sanity checking on this, and we don't deal with what happens to | |
2136 | * programs that are already running when the size changes. | |
2137 | * NOTE: changing the MTU will usually cause the IBC to go back to | |
124b4dcb | 2138 | * link INIT state... |
34b2aafe BS |
2139 | */ |
2140 | int ipath_set_mtu(struct ipath_devdata *dd, u16 arg) | |
2141 | { | |
2142 | u32 piosize; | |
2143 | int changed = 0; | |
2144 | int ret; | |
2145 | ||
2146 | /* | |
2147 | * mtu is IB data payload max. It's the largest power of 2 less | |
2148 | * than piosize (or even larger, since it only really controls the | |
2149 | * largest we can receive; we can send the max of the mtu and | |
2150 | * piosize). We check that it's one of the valid IB sizes. | |
2151 | */ | |
2152 | if (arg != 256 && arg != 512 && arg != 1024 && arg != 2048 && | |
826d8010 | 2153 | (arg != 4096 || !ipath_mtu4096)) { |
34b2aafe BS |
2154 | ipath_dbg("Trying to set invalid mtu %u, failing\n", arg); |
2155 | ret = -EINVAL; | |
2156 | goto bail; | |
2157 | } | |
2158 | if (dd->ipath_ibmtu == arg) { | |
2159 | ret = 0; /* same as current */ | |
2160 | goto bail; | |
2161 | } | |
2162 | ||
2163 | piosize = dd->ipath_ibmaxlen; | |
2164 | dd->ipath_ibmtu = arg; | |
2165 | ||
2166 | if (arg >= (piosize - IPATH_PIO_MAXIBHDR)) { | |
2167 | /* Only if it's not the initial value (or reset to it) */ | |
2168 | if (piosize != dd->ipath_init_ibmaxlen) { | |
826d8010 DO |
2169 | if (arg > piosize && arg <= dd->ipath_init_ibmaxlen) |
2170 | piosize = dd->ipath_init_ibmaxlen; | |
34b2aafe BS |
2171 | dd->ipath_ibmaxlen = piosize; |
2172 | changed = 1; | |
2173 | } | |
2174 | } else if ((arg + IPATH_PIO_MAXIBHDR) != dd->ipath_ibmaxlen) { | |
2175 | piosize = arg + IPATH_PIO_MAXIBHDR; | |
2176 | ipath_cdbg(VERBOSE, "ibmaxlen was 0x%x, setting to 0x%x " | |
2177 | "(mtu 0x%x)\n", dd->ipath_ibmaxlen, piosize, | |
2178 | arg); | |
2179 | dd->ipath_ibmaxlen = piosize; | |
2180 | changed = 1; | |
2181 | } | |
2182 | ||
2183 | if (changed) { | |
826d8010 | 2184 | u64 ibc = dd->ipath_ibcctrl, ibdw; |
34b2aafe | 2185 | /* |
826d8010 DO |
2186 | * update our housekeeping variables, and set IBC max |
2187 | * size, same as init code; max IBC is max we allow in | |
2188 | * buffer, less the qword pbc, plus 1 for ICRC, in dwords | |
34b2aafe | 2189 | */ |
826d8010 DO |
2190 | dd->ipath_ibmaxlen = piosize - 2 * sizeof(u32); |
2191 | ibdw = (dd->ipath_ibmaxlen >> 2) + 1; | |
34b2aafe | 2192 | ibc &= ~(INFINIPATH_IBCC_MAXPKTLEN_MASK << |
826d8010 DO |
2193 | dd->ibcc_mpl_shift); |
2194 | ibc |= ibdw << dd->ibcc_mpl_shift; | |
34b2aafe BS |
2195 | dd->ipath_ibcctrl = ibc; |
2196 | ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, | |
2197 | dd->ipath_ibcctrl); | |
2198 | dd->ipath_f_tidtemplate(dd); | |
2199 | } | |
2200 | ||
2201 | ret = 0; | |
2202 | ||
2203 | bail: | |
2204 | return ret; | |
2205 | } | |
2206 | ||
0ab6b2b9 | 2207 | int ipath_set_lid(struct ipath_devdata *dd, u32 lid, u8 lmc) |
34b2aafe | 2208 | { |
0ab6b2b9 | 2209 | dd->ipath_lid = lid; |
34b2aafe BS |
2210 | dd->ipath_lmc = lmc; |
2211 | ||
0ab6b2b9 DO |
2212 | dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_LIDLMC, lid | |
2213 | (~((1U << lmc) - 1)) << 16); | |
2214 | ||
2215 | dev_info(&dd->pcidev->dev, "We got a lid: 0x%x\n", lid); | |
2216 | ||
34b2aafe BS |
2217 | return 0; |
2218 | } | |
2219 | ||
7bb206e3 BS |
2220 | |
2221 | /** | |
2222 | * ipath_write_kreg_port - write a device's per-port 64-bit kernel register | |
2223 | * @dd: the infinipath device | |
2224 | * @regno: the register number to write | |
2225 | * @port: the port containing the register | |
2226 | * @value: the value to write | |
2227 | * | |
2228 | * Registers that vary with the chip implementation constants (port) | |
2229 | * use this routine. | |
2230 | */ | |
2231 | void ipath_write_kreg_port(const struct ipath_devdata *dd, ipath_kreg regno, | |
2232 | unsigned port, u64 value) | |
2233 | { | |
2234 | u16 where; | |
2235 | ||
2236 | if (port < dd->ipath_portcnt && | |
2237 | (regno == dd->ipath_kregs->kr_rcvhdraddr || | |
2238 | regno == dd->ipath_kregs->kr_rcvhdrtailaddr)) | |
2239 | where = regno + port; | |
2240 | else | |
2241 | where = -1; | |
2242 | ||
2243 | ipath_write_kreg(dd, where, value); | |
2244 | } | |
2245 | ||
82466f00 MA |
2246 | /* |
2247 | * Following deal with the "obviously simple" task of overriding the state | |
2248 | * of the LEDS, which normally indicate link physical and logical status. | |
2249 | * The complications arise in dealing with different hardware mappings | |
2250 | * and the board-dependent routine being called from interrupts. | |
2251 | * and then there's the requirement to _flash_ them. | |
2252 | */ | |
2253 | #define LED_OVER_FREQ_SHIFT 8 | |
2254 | #define LED_OVER_FREQ_MASK (0xFF<<LED_OVER_FREQ_SHIFT) | |
2255 | /* Below is "non-zero" to force override, but both actual LEDs are off */ | |
2256 | #define LED_OVER_BOTH_OFF (8) | |
2257 | ||
da9aec7b | 2258 | static void ipath_run_led_override(unsigned long opaque) |
82466f00 MA |
2259 | { |
2260 | struct ipath_devdata *dd = (struct ipath_devdata *)opaque; | |
2261 | int timeoff; | |
2262 | int pidx; | |
2263 | u64 lstate, ltstate, val; | |
2264 | ||
2265 | if (!(dd->ipath_flags & IPATH_INITTED)) | |
2266 | return; | |
2267 | ||
2268 | pidx = dd->ipath_led_override_phase++ & 1; | |
2269 | dd->ipath_led_override = dd->ipath_led_override_vals[pidx]; | |
2270 | timeoff = dd->ipath_led_override_timeoff; | |
2271 | ||
2272 | /* | |
2273 | * below potentially restores the LED values per current status, | |
2274 | * should also possibly setup the traffic-blink register, | |
2275 | * but leave that to per-chip functions. | |
2276 | */ | |
2277 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus); | |
124b4dcb DO |
2278 | ltstate = ipath_ib_linktrstate(dd, val); |
2279 | lstate = ipath_ib_linkstate(dd, val); | |
82466f00 MA |
2280 | |
2281 | dd->ipath_f_setextled(dd, lstate, ltstate); | |
2282 | mod_timer(&dd->ipath_led_override_timer, jiffies + timeoff); | |
2283 | } | |
2284 | ||
2285 | void ipath_set_led_override(struct ipath_devdata *dd, unsigned int val) | |
2286 | { | |
2287 | int timeoff, freq; | |
2288 | ||
2289 | if (!(dd->ipath_flags & IPATH_INITTED)) | |
2290 | return; | |
2291 | ||
2292 | /* First check if we are blinking. If not, use 1HZ polling */ | |
2293 | timeoff = HZ; | |
2294 | freq = (val & LED_OVER_FREQ_MASK) >> LED_OVER_FREQ_SHIFT; | |
2295 | ||
2296 | if (freq) { | |
2297 | /* For blink, set each phase from one nybble of val */ | |
2298 | dd->ipath_led_override_vals[0] = val & 0xF; | |
2299 | dd->ipath_led_override_vals[1] = (val >> 4) & 0xF; | |
2300 | timeoff = (HZ << 4)/freq; | |
2301 | } else { | |
2302 | /* Non-blink set both phases the same. */ | |
2303 | dd->ipath_led_override_vals[0] = val & 0xF; | |
2304 | dd->ipath_led_override_vals[1] = val & 0xF; | |
2305 | } | |
2306 | dd->ipath_led_override_timeoff = timeoff; | |
2307 | ||
2308 | /* | |
2309 | * If the timer has not already been started, do so. Use a "quick" | |
2310 | * timeout so the function will be called soon, to look at our request. | |
2311 | */ | |
2312 | if (atomic_inc_return(&dd->ipath_led_override_timer_active) == 1) { | |
2313 | /* Need to start timer */ | |
2314 | init_timer(&dd->ipath_led_override_timer); | |
2315 | dd->ipath_led_override_timer.function = | |
2316 | ipath_run_led_override; | |
2317 | dd->ipath_led_override_timer.data = (unsigned long) dd; | |
2318 | dd->ipath_led_override_timer.expires = jiffies + 1; | |
2319 | add_timer(&dd->ipath_led_override_timer); | |
2ba3f56e | 2320 | } else |
82466f00 | 2321 | atomic_dec(&dd->ipath_led_override_timer_active); |
82466f00 MA |
2322 | } |
2323 | ||
7bb206e3 BS |
2324 | /** |
2325 | * ipath_shutdown_device - shut down a device | |
2326 | * @dd: the infinipath device | |
2327 | * | |
2328 | * This is called to make the device quiet when we are about to | |
2329 | * unload the driver, and also when the device is administratively | |
2330 | * disabled. It does not free any data structures. | |
2331 | * Everything it does has to be setup again by ipath_init_chip(dd,1) | |
2332 | */ | |
2333 | void ipath_shutdown_device(struct ipath_devdata *dd) | |
2334 | { | |
e342c119 JG |
2335 | unsigned long flags; |
2336 | ||
7bb206e3 BS |
2337 | ipath_dbg("Shutting down the device\n"); |
2338 | ||
58411d1c JG |
2339 | ipath_hol_up(dd); /* make sure user processes aren't suspended */ |
2340 | ||
7bb206e3 BS |
2341 | dd->ipath_flags |= IPATH_LINKUNK; |
2342 | dd->ipath_flags &= ~(IPATH_INITTED | IPATH_LINKDOWN | | |
2343 | IPATH_LINKINIT | IPATH_LINKARMED | | |
2344 | IPATH_LINKACTIVE); | |
2345 | *dd->ipath_statusp &= ~(IPATH_STATUS_IB_CONF | | |
2346 | IPATH_STATUS_IB_READY); | |
2347 | ||
2348 | /* mask interrupts, but not errors */ | |
2349 | ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL); | |
2350 | ||
2351 | dd->ipath_rcvctrl = 0; | |
2352 | ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, | |
2353 | dd->ipath_rcvctrl); | |
2354 | ||
124b4dcb DO |
2355 | if (dd->ipath_flags & IPATH_HAS_SEND_DMA) |
2356 | teardown_sdma(dd); | |
2357 | ||
7bb206e3 BS |
2358 | /* |
2359 | * gracefully stop all sends allowing any in progress to trickle out | |
2360 | * first. | |
2361 | */ | |
e342c119 JG |
2362 | spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags); |
2363 | dd->ipath_sendctrl = 0; | |
2364 | ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl); | |
7bb206e3 | 2365 | /* flush it */ |
44f8e3f3 | 2366 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); |
e342c119 JG |
2367 | spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags); |
2368 | ||
7bb206e3 BS |
2369 | /* |
2370 | * enough for anything that's going to trickle out to have actually | |
2371 | * done so. | |
2372 | */ | |
2373 | udelay(5); | |
2374 | ||
124b4dcb DO |
2375 | dd->ipath_f_setextled(dd, 0, 0); /* make sure LEDs are off */ |
2376 | ||
4330e4da | 2377 | ipath_set_ib_lstate(dd, 0, INFINIPATH_IBCC_LINKINITCMD_DISABLE); |
3810f2a8 | 2378 | ipath_cancel_sends(dd, 0); |
7bb206e3 | 2379 | |
124b4dcb DO |
2380 | /* |
2381 | * we are shutting down, so tell components that care. We don't do | |
2382 | * this on just a link state change, much like ethernet, a cable | |
2383 | * unplug, etc. doesn't change driver state | |
2384 | */ | |
49739b3e RC |
2385 | signal_ib_event(dd, IB_EVENT_PORT_ERR); |
2386 | ||
7bb206e3 BS |
2387 | /* disable IBC */ |
2388 | dd->ipath_control &= ~INFINIPATH_C_LINKENABLE; | |
2389 | ipath_write_kreg(dd, dd->ipath_kregs->kr_control, | |
a40f55fc | 2390 | dd->ipath_control | INFINIPATH_C_FREEZEMODE); |
7bb206e3 BS |
2391 | |
2392 | /* | |
2393 | * clear SerdesEnable and turn the leds off; do this here because | |
2394 | * we are unloading, so don't count on interrupts to move along | |
25985edc | 2395 | * Turn the LEDs off explicitly for the same reason. |
7bb206e3 BS |
2396 | */ |
2397 | dd->ipath_f_quiet_serdes(dd); | |
7bb206e3 | 2398 | |
58411d1c JG |
2399 | /* stop all the timers that might still be running */ |
2400 | del_timer_sync(&dd->ipath_hol_timer); | |
7bb206e3 BS |
2401 | if (dd->ipath_stats_timer_active) { |
2402 | del_timer_sync(&dd->ipath_stats_timer); | |
2403 | dd->ipath_stats_timer_active = 0; | |
2404 | } | |
9b436eb4 DO |
2405 | if (dd->ipath_intrchk_timer.data) { |
2406 | del_timer_sync(&dd->ipath_intrchk_timer); | |
2407 | dd->ipath_intrchk_timer.data = 0; | |
2408 | } | |
124b4dcb DO |
2409 | if (atomic_read(&dd->ipath_led_override_timer_active)) { |
2410 | del_timer_sync(&dd->ipath_led_override_timer); | |
2411 | atomic_set(&dd->ipath_led_override_timer_active, 0); | |
2412 | } | |
7bb206e3 BS |
2413 | |
2414 | /* | |
2415 | * clear all interrupts and errors, so that the next time the driver | |
2416 | * is loaded or device is enabled, we know that whatever is set | |
2417 | * happened while we were unloaded | |
2418 | */ | |
2419 | ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear, | |
2420 | ~0ULL & ~INFINIPATH_HWE_MEMBISTFAILED); | |
2421 | ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL); | |
2422 | ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL); | |
aecd3b5a MA |
2423 | |
2424 | ipath_cdbg(VERBOSE, "Flush time and errors to EEPROM\n"); | |
2425 | ipath_update_eeprom_log(dd); | |
7bb206e3 BS |
2426 | } |
2427 | ||
2428 | /** | |
2429 | * ipath_free_pddata - free a port's allocated data | |
2430 | * @dd: the infinipath device | |
f37bda92 | 2431 | * @pd: the portdata structure |
7bb206e3 | 2432 | * |
f37bda92 BS |
2433 | * free up any allocated data for a port |
2434 | * This should not touch anything that would affect a simultaneous | |
2435 | * re-allocation of port data, because it is called after ipath_mutex | |
2436 | * is released (and can be called from reinit as well). | |
2437 | * It should never change any chip state, or global driver state. | |
2438 | * (The only exception to global state is freeing the port0 port0_skbs.) | |
7bb206e3 | 2439 | */ |
f37bda92 | 2440 | void ipath_free_pddata(struct ipath_devdata *dd, struct ipath_portdata *pd) |
7bb206e3 | 2441 | { |
7bb206e3 BS |
2442 | if (!pd) |
2443 | return; | |
f37bda92 BS |
2444 | |
2445 | if (pd->port_rcvhdrq) { | |
7bb206e3 BS |
2446 | ipath_cdbg(VERBOSE, "free closed port %d rcvhdrq @ %p " |
2447 | "(size=%lu)\n", pd->port_port, pd->port_rcvhdrq, | |
2448 | (unsigned long) pd->port_rcvhdrq_size); | |
2449 | dma_free_coherent(&dd->pcidev->dev, pd->port_rcvhdrq_size, | |
2450 | pd->port_rcvhdrq, pd->port_rcvhdrq_phys); | |
2451 | pd->port_rcvhdrq = NULL; | |
f37bda92 BS |
2452 | if (pd->port_rcvhdrtail_kvaddr) { |
2453 | dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE, | |
076fafcd | 2454 | pd->port_rcvhdrtail_kvaddr, |
f37bda92 BS |
2455 | pd->port_rcvhdrqtailaddr_phys); |
2456 | pd->port_rcvhdrtail_kvaddr = NULL; | |
2457 | } | |
7bb206e3 | 2458 | } |
f37bda92 BS |
2459 | if (pd->port_port && pd->port_rcvegrbuf) { |
2460 | unsigned e; | |
2461 | ||
2462 | for (e = 0; e < pd->port_rcvegrbuf_chunks; e++) { | |
2463 | void *base = pd->port_rcvegrbuf[e]; | |
2464 | size_t size = pd->port_rcvegrbuf_size; | |
2465 | ||
2466 | ipath_cdbg(VERBOSE, "egrbuf free(%p, %lu), " | |
2467 | "chunk %u/%u\n", base, | |
2468 | (unsigned long) size, | |
2469 | e, pd->port_rcvegrbuf_chunks); | |
2470 | dma_free_coherent(&dd->pcidev->dev, size, | |
2471 | base, pd->port_rcvegrbuf_phys[e]); | |
7bb206e3 | 2472 | } |
9929b0fb | 2473 | kfree(pd->port_rcvegrbuf); |
f37bda92 | 2474 | pd->port_rcvegrbuf = NULL; |
9929b0fb | 2475 | kfree(pd->port_rcvegrbuf_phys); |
f37bda92 | 2476 | pd->port_rcvegrbuf_phys = NULL; |
7bb206e3 | 2477 | pd->port_rcvegrbuf_chunks = 0; |
1fd3b40f | 2478 | } else if (pd->port_port == 0 && dd->ipath_port0_skbinfo) { |
7bb206e3 | 2479 | unsigned e; |
1fd3b40f | 2480 | struct ipath_skbinfo *skbinfo = dd->ipath_port0_skbinfo; |
7bb206e3 | 2481 | |
1fd3b40f BS |
2482 | dd->ipath_port0_skbinfo = NULL; |
2483 | ipath_cdbg(VERBOSE, "free closed port %d " | |
2484 | "ipath_port0_skbinfo @ %p\n", pd->port_port, | |
2485 | skbinfo); | |
9355fb6a | 2486 | for (e = 0; e < dd->ipath_p0_rcvegrcnt; e++) |
2ba3f56e RC |
2487 | if (skbinfo[e].skb) { |
2488 | pci_unmap_single(dd->pcidev, skbinfo[e].phys, | |
2489 | dd->ipath_ibmaxlen, | |
2490 | PCI_DMA_FROMDEVICE); | |
2491 | dev_kfree_skb(skbinfo[e].skb); | |
2492 | } | |
1fd3b40f | 2493 | vfree(skbinfo); |
7bb206e3 | 2494 | } |
f37bda92 | 2495 | kfree(pd->port_tid_pg_list); |
9929b0fb BS |
2496 | vfree(pd->subport_uregbase); |
2497 | vfree(pd->subport_rcvegrbuf); | |
2498 | vfree(pd->subport_rcvhdr_base); | |
f37bda92 | 2499 | kfree(pd); |
7bb206e3 BS |
2500 | } |
2501 | ||
ac2ae4c9 | 2502 | static int __init infinipath_init(void) |
7bb206e3 BS |
2503 | { |
2504 | int ret; | |
2505 | ||
39c0d0b9 BS |
2506 | if (ipath_debug & __IPATH_DBG) |
2507 | printk(KERN_INFO DRIVER_LOAD_MSG "%s", ib_ipath_version); | |
7bb206e3 BS |
2508 | |
2509 | /* | |
2510 | * These must be called before the driver is registered with | |
2511 | * the PCI subsystem. | |
2512 | */ | |
2513 | idr_init(&unit_table); | |
2514 | if (!idr_pre_get(&unit_table, GFP_KERNEL)) { | |
bb917144 | 2515 | printk(KERN_ERR IPATH_DRV_NAME ": idr_pre_get() failed\n"); |
7bb206e3 BS |
2516 | ret = -ENOMEM; |
2517 | goto bail; | |
2518 | } | |
2519 | ||
2520 | ret = pci_register_driver(&ipath_driver); | |
2521 | if (ret < 0) { | |
2522 | printk(KERN_ERR IPATH_DRV_NAME | |
2523 | ": Unable to register driver: error %d\n", -ret); | |
2524 | goto bail_unit; | |
2525 | } | |
2526 | ||
7bb206e3 BS |
2527 | ret = ipath_init_ipathfs(); |
2528 | if (ret < 0) { | |
2529 | printk(KERN_ERR IPATH_DRV_NAME ": Unable to create " | |
2530 | "ipathfs: error %d\n", -ret); | |
23b9c1ab | 2531 | goto bail_pci; |
7bb206e3 BS |
2532 | } |
2533 | ||
2534 | goto bail; | |
2535 | ||
7bb206e3 BS |
2536 | bail_pci: |
2537 | pci_unregister_driver(&ipath_driver); | |
2538 | ||
2539 | bail_unit: | |
2540 | idr_destroy(&unit_table); | |
2541 | ||
2542 | bail: | |
2543 | return ret; | |
2544 | } | |
2545 | ||
7bb206e3 BS |
2546 | static void __exit infinipath_cleanup(void) |
2547 | { | |
7bb206e3 BS |
2548 | ipath_exit_ipathfs(); |
2549 | ||
7bb206e3 BS |
2550 | ipath_cdbg(VERBOSE, "Unregistering pci driver\n"); |
2551 | pci_unregister_driver(&ipath_driver); | |
2552 | ||
2553 | idr_destroy(&unit_table); | |
2554 | } | |
2555 | ||
2556 | /** | |
2557 | * ipath_reset_device - reset the chip if possible | |
2558 | * @unit: the device to reset | |
2559 | * | |
2560 | * Whether or not reset is successful, we attempt to re-initialize the chip | |
2561 | * (that is, much like a driver unload/reload). We clear the INITTED flag | |
2562 | * so that the various entry points will fail until we reinitialize. For | |
2563 | * now, we only allow this if no user ports are open that use chip resources | |
2564 | */ | |
2565 | int ipath_reset_device(int unit) | |
2566 | { | |
2567 | int ret, i; | |
2568 | struct ipath_devdata *dd = ipath_lookup(unit); | |
3d089098 | 2569 | unsigned long flags; |
7bb206e3 BS |
2570 | |
2571 | if (!dd) { | |
2572 | ret = -ENODEV; | |
2573 | goto bail; | |
2574 | } | |
2575 | ||
82466f00 MA |
2576 | if (atomic_read(&dd->ipath_led_override_timer_active)) { |
2577 | /* Need to stop LED timer, _then_ shut off LEDs */ | |
2578 | del_timer_sync(&dd->ipath_led_override_timer); | |
2579 | atomic_set(&dd->ipath_led_override_timer_active, 0); | |
2580 | } | |
2581 | ||
2582 | /* Shut off LEDs after we are sure timer is not running */ | |
2583 | dd->ipath_led_override = LED_OVER_BOTH_OFF; | |
2584 | dd->ipath_f_setextled(dd, 0, 0); | |
2585 | ||
7bb206e3 BS |
2586 | dev_info(&dd->pcidev->dev, "Reset on unit %u requested\n", unit); |
2587 | ||
2588 | if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) { | |
2589 | dev_info(&dd->pcidev->dev, "Invalid unit number %u or " | |
2590 | "not initialized or not present\n", unit); | |
2591 | ret = -ENXIO; | |
2592 | goto bail; | |
2593 | } | |
2594 | ||
3d089098 | 2595 | spin_lock_irqsave(&dd->ipath_uctxt_lock, flags); |
7bb206e3 | 2596 | if (dd->ipath_pd) |
23e86a45 | 2597 | for (i = 1; i < dd->ipath_cfgports; i++) { |
3d089098 DO |
2598 | if (!dd->ipath_pd[i] || !dd->ipath_pd[i]->port_cnt) |
2599 | continue; | |
2600 | spin_unlock_irqrestore(&dd->ipath_uctxt_lock, flags); | |
2601 | ipath_dbg("unit %u port %d is in use " | |
2602 | "(PID %u cmd %s), can't reset\n", | |
2603 | unit, i, | |
2604 | pid_nr(dd->ipath_pd[i]->port_pid), | |
2605 | dd->ipath_pd[i]->port_comm); | |
2606 | ret = -EBUSY; | |
2607 | goto bail; | |
7bb206e3 | 2608 | } |
3d089098 | 2609 | spin_unlock_irqrestore(&dd->ipath_uctxt_lock, flags); |
7bb206e3 | 2610 | |
124b4dcb DO |
2611 | if (dd->ipath_flags & IPATH_HAS_SEND_DMA) |
2612 | teardown_sdma(dd); | |
2613 | ||
7bb206e3 | 2614 | dd->ipath_flags &= ~IPATH_INITTED; |
124b4dcb | 2615 | ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL); |
7bb206e3 | 2616 | ret = dd->ipath_f_reset(dd); |
124b4dcb DO |
2617 | if (ret == 1) { |
2618 | ipath_dbg("Reinitializing unit %u after reset attempt\n", | |
2619 | unit); | |
2620 | ret = ipath_init_chip(dd, 1); | |
2621 | } else | |
2622 | ret = -EAGAIN; | |
7bb206e3 BS |
2623 | if (ret) |
2624 | ipath_dev_err(dd, "Reinitialize unit %u after " | |
2625 | "reset failed with %d\n", unit, ret); | |
2626 | else | |
2627 | dev_info(&dd->pcidev->dev, "Reinitialized unit %u after " | |
2628 | "resetting\n", unit); | |
2629 | ||
2630 | bail: | |
2631 | return ret; | |
2632 | } | |
2633 | ||
58411d1c JG |
2634 | /* |
2635 | * send a signal to all the processes that have the driver open | |
2636 | * through the normal interfaces (i.e., everything other than diags | |
2637 | * interface). Returns number of signalled processes. | |
2638 | */ | |
2639 | static int ipath_signal_procs(struct ipath_devdata *dd, int sig) | |
2640 | { | |
2641 | int i, sub, any = 0; | |
40d97692 | 2642 | struct pid *pid; |
3d089098 | 2643 | unsigned long flags; |
58411d1c JG |
2644 | |
2645 | if (!dd->ipath_pd) | |
2646 | return 0; | |
3d089098 DO |
2647 | |
2648 | spin_lock_irqsave(&dd->ipath_uctxt_lock, flags); | |
58411d1c | 2649 | for (i = 1; i < dd->ipath_cfgports; i++) { |
40d97692 | 2650 | if (!dd->ipath_pd[i] || !dd->ipath_pd[i]->port_cnt) |
58411d1c JG |
2651 | continue; |
2652 | pid = dd->ipath_pd[i]->port_pid; | |
40d97692 PE |
2653 | if (!pid) |
2654 | continue; | |
2655 | ||
58411d1c JG |
2656 | dev_info(&dd->pcidev->dev, "context %d in use " |
2657 | "(PID %u), sending signal %d\n", | |
40d97692 PE |
2658 | i, pid_nr(pid), sig); |
2659 | kill_pid(pid, sig, 1); | |
58411d1c JG |
2660 | any++; |
2661 | for (sub = 0; sub < INFINIPATH_MAX_SUBPORT; sub++) { | |
2662 | pid = dd->ipath_pd[i]->port_subpid[sub]; | |
2663 | if (!pid) | |
2664 | continue; | |
2665 | dev_info(&dd->pcidev->dev, "sub-context " | |
2666 | "%d:%d in use (PID %u), sending " | |
40d97692 PE |
2667 | "signal %d\n", i, sub, pid_nr(pid), sig); |
2668 | kill_pid(pid, sig, 1); | |
58411d1c JG |
2669 | any++; |
2670 | } | |
2671 | } | |
3d089098 | 2672 | spin_unlock_irqrestore(&dd->ipath_uctxt_lock, flags); |
58411d1c JG |
2673 | return any; |
2674 | } | |
2675 | ||
2676 | static void ipath_hol_signal_down(struct ipath_devdata *dd) | |
2677 | { | |
2678 | if (ipath_signal_procs(dd, SIGSTOP)) | |
2679 | ipath_dbg("Stopped some processes\n"); | |
2680 | ipath_cancel_sends(dd, 1); | |
2681 | } | |
2682 | ||
2683 | ||
2684 | static void ipath_hol_signal_up(struct ipath_devdata *dd) | |
2685 | { | |
2686 | if (ipath_signal_procs(dd, SIGCONT)) | |
2687 | ipath_dbg("Continued some processes\n"); | |
2688 | } | |
2689 | ||
2690 | /* | |
2691 | * link is down, stop any users processes, and flush pending sends | |
2692 | * to prevent HoL blocking, then start the HoL timer that | |
2693 | * periodically continues, then stop procs, so they can detect | |
2694 | * link down if they want, and do something about it. | |
74019224 | 2695 | * Timer may already be running, so use mod_timer, not add_timer. |
58411d1c JG |
2696 | */ |
2697 | void ipath_hol_down(struct ipath_devdata *dd) | |
2698 | { | |
2699 | dd->ipath_hol_state = IPATH_HOL_DOWN; | |
2700 | ipath_hol_signal_down(dd); | |
2701 | dd->ipath_hol_next = IPATH_HOL_DOWNCONT; | |
2702 | dd->ipath_hol_timer.expires = jiffies + | |
2703 | msecs_to_jiffies(ipath_hol_timeout_ms); | |
74019224 | 2704 | mod_timer(&dd->ipath_hol_timer, dd->ipath_hol_timer.expires); |
58411d1c JG |
2705 | } |
2706 | ||
2707 | /* | |
2708 | * link is up, continue any user processes, and ensure timer | |
2709 | * is a nop, if running. Let timer keep running, if set; it | |
2710 | * will nop when it sees the link is up | |
2711 | */ | |
2712 | void ipath_hol_up(struct ipath_devdata *dd) | |
2713 | { | |
2714 | ipath_hol_signal_up(dd); | |
2715 | dd->ipath_hol_state = IPATH_HOL_UP; | |
2716 | } | |
2717 | ||
2718 | /* | |
2719 | * toggle the running/not running state of user proceses | |
2720 | * to prevent HoL blocking on chip resources, but still allow | |
2721 | * user processes to do link down special case handling. | |
2722 | * Should only be called via the timer | |
2723 | */ | |
2724 | void ipath_hol_event(unsigned long opaque) | |
2725 | { | |
2726 | struct ipath_devdata *dd = (struct ipath_devdata *)opaque; | |
2727 | ||
2728 | if (dd->ipath_hol_next == IPATH_HOL_DOWNSTOP | |
2729 | && dd->ipath_hol_state != IPATH_HOL_UP) { | |
2730 | dd->ipath_hol_next = IPATH_HOL_DOWNCONT; | |
2731 | ipath_dbg("Stopping processes\n"); | |
2732 | ipath_hol_signal_down(dd); | |
2733 | } else { /* may do "extra" if also in ipath_hol_up() */ | |
2734 | dd->ipath_hol_next = IPATH_HOL_DOWNSTOP; | |
2735 | ipath_dbg("Continuing processes\n"); | |
2736 | ipath_hol_signal_up(dd); | |
2737 | } | |
2738 | if (dd->ipath_hol_state == IPATH_HOL_UP) | |
2739 | ipath_dbg("link's up, don't resched timer\n"); | |
2740 | else { | |
2741 | dd->ipath_hol_timer.expires = jiffies + | |
2742 | msecs_to_jiffies(ipath_hol_timeout_ms); | |
74019224 | 2743 | mod_timer(&dd->ipath_hol_timer, |
58411d1c JG |
2744 | dd->ipath_hol_timer.expires); |
2745 | } | |
2746 | } | |
2747 | ||
30fc5c31 BS |
2748 | int ipath_set_rx_pol_inv(struct ipath_devdata *dd, u8 new_pol_inv) |
2749 | { | |
2750 | u64 val; | |
2ba3f56e RC |
2751 | |
2752 | if (new_pol_inv > INFINIPATH_XGXS_RX_POL_MASK) | |
30fc5c31 | 2753 | return -1; |
2ba3f56e | 2754 | if (dd->ipath_rx_pol_inv != new_pol_inv) { |
30fc5c31 BS |
2755 | dd->ipath_rx_pol_inv = new_pol_inv; |
2756 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig); | |
2757 | val &= ~(INFINIPATH_XGXS_RX_POL_MASK << | |
3cd96564 RD |
2758 | INFINIPATH_XGXS_RX_POL_SHIFT); |
2759 | val |= ((u64)dd->ipath_rx_pol_inv) << | |
2760 | INFINIPATH_XGXS_RX_POL_SHIFT; | |
30fc5c31 BS |
2761 | ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val); |
2762 | } | |
2763 | return 0; | |
2764 | } | |
6ac50727 DO |
2765 | |
2766 | /* | |
2767 | * Disable and enable the armlaunch error. Used for PIO bandwidth testing on | |
2768 | * the 7220, which is count-based, rather than trigger-based. Safe for the | |
2769 | * driver check, since it's at init. Not completely safe when used for | |
2770 | * user-mode checking, since some error checking can be lost, but not | |
2771 | * particularly risky, and only has problematic side-effects in the face of | |
2772 | * very buggy user code. There is no reference counting, but that's also | |
2773 | * fine, given the intended use. | |
2774 | */ | |
2775 | void ipath_enable_armlaunch(struct ipath_devdata *dd) | |
2776 | { | |
2777 | dd->ipath_lasterror &= ~INFINIPATH_E_SPIOARMLAUNCH; | |
2778 | ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, | |
2779 | INFINIPATH_E_SPIOARMLAUNCH); | |
2780 | dd->ipath_errormask |= INFINIPATH_E_SPIOARMLAUNCH; | |
2781 | ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask, | |
2782 | dd->ipath_errormask); | |
2783 | } | |
2784 | ||
2785 | void ipath_disable_armlaunch(struct ipath_devdata *dd) | |
2786 | { | |
2787 | /* so don't re-enable if already set */ | |
2788 | dd->ipath_maskederrs &= ~INFINIPATH_E_SPIOARMLAUNCH; | |
2789 | dd->ipath_errormask &= ~INFINIPATH_E_SPIOARMLAUNCH; | |
2790 | ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask, | |
2791 | dd->ipath_errormask); | |
2792 | } | |
2793 | ||
7bb206e3 BS |
2794 | module_init(infinipath_init); |
2795 | module_exit(infinipath_cleanup); |