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1 | #ifndef _IPATH_KERNEL_H |
2 | #define _IPATH_KERNEL_H | |
3 | /* | |
759d5768 | 4 | * Copyright (c) 2006 QLogic, Inc. All rights reserved. |
d41d3aeb BS |
5 | * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. |
6 | * | |
7 | * This software is available to you under a choice of one of two | |
8 | * licenses. You may choose to be licensed under the terms of the GNU | |
9 | * General Public License (GPL) Version 2, available from the file | |
10 | * COPYING in the main directory of this source tree, or the | |
11 | * OpenIB.org BSD license below: | |
12 | * | |
13 | * Redistribution and use in source and binary forms, with or | |
14 | * without modification, are permitted provided that the following | |
15 | * conditions are met: | |
16 | * | |
17 | * - Redistributions of source code must retain the above | |
18 | * copyright notice, this list of conditions and the following | |
19 | * disclaimer. | |
20 | * | |
21 | * - Redistributions in binary form must reproduce the above | |
22 | * copyright notice, this list of conditions and the following | |
23 | * disclaimer in the documentation and/or other materials | |
24 | * provided with the distribution. | |
25 | * | |
26 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
27 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
28 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
29 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
30 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
31 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
32 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
33 | * SOFTWARE. | |
34 | */ | |
35 | ||
36 | /* | |
37 | * This header file is the base header file for infinipath kernel code | |
38 | * ipath_user.h serves a similar purpose for user code. | |
39 | */ | |
40 | ||
41 | #include <linux/interrupt.h> | |
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42 | #include <linux/pci.h> |
43 | #include <linux/dma-mapping.h> | |
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44 | #include <asm/io.h> |
45 | ||
46 | #include "ipath_common.h" | |
47 | #include "ipath_debug.h" | |
48 | #include "ipath_registers.h" | |
49 | ||
50 | /* only s/w major version of InfiniPath we can handle */ | |
51 | #define IPATH_CHIP_VERS_MAJ 2U | |
52 | ||
53 | /* don't care about this except printing */ | |
54 | #define IPATH_CHIP_VERS_MIN 0U | |
55 | ||
56 | /* temporary, maybe always */ | |
57 | extern struct infinipath_stats ipath_stats; | |
58 | ||
59 | #define IPATH_CHIP_SWVERSION IPATH_CHIP_VERS_MAJ | |
60 | ||
61 | struct ipath_portdata { | |
62 | void **port_rcvegrbuf; | |
63 | dma_addr_t *port_rcvegrbuf_phys; | |
64 | /* rcvhdrq base, needs mmap before useful */ | |
65 | void *port_rcvhdrq; | |
66 | /* kernel virtual address where hdrqtail is updated */ | |
1fd3b40f | 67 | void *port_rcvhdrtail_kvaddr; |
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68 | /* |
69 | * temp buffer for expected send setup, allocated at open, instead | |
70 | * of each setup call | |
71 | */ | |
72 | void *port_tid_pg_list; | |
73 | /* when waiting for rcv or pioavail */ | |
74 | wait_queue_head_t port_wait; | |
75 | /* | |
76 | * rcvegr bufs base, physical, must fit | |
77 | * in 44 bits so 32 bit programs mmap64 44 bit works) | |
78 | */ | |
79 | dma_addr_t port_rcvegr_phys; | |
80 | /* mmap of hdrq, must fit in 44 bits */ | |
81 | dma_addr_t port_rcvhdrq_phys; | |
f37bda92 | 82 | dma_addr_t port_rcvhdrqtailaddr_phys; |
d41d3aeb | 83 | /* |
9929b0fb BS |
84 | * number of opens (including slave subports) on this instance |
85 | * (ignoring forks, dup, etc. for now) | |
d41d3aeb BS |
86 | */ |
87 | int port_cnt; | |
88 | /* | |
89 | * how much space to leave at start of eager TID entries for | |
90 | * protocol use, on each TID | |
91 | */ | |
92 | /* instead of calculating it */ | |
93 | unsigned port_port; | |
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94 | /* non-zero if port is being shared. */ |
95 | u16 port_subport_cnt; | |
96 | /* non-zero if port is being shared. */ | |
97 | u16 port_subport_id; | |
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98 | /* chip offset of PIO buffers for this port */ |
99 | u32 port_piobufs; | |
100 | /* how many alloc_pages() chunks in port_rcvegrbuf_pages */ | |
101 | u32 port_rcvegrbuf_chunks; | |
102 | /* how many egrbufs per chunk */ | |
103 | u32 port_rcvegrbufs_perchunk; | |
104 | /* order for port_rcvegrbuf_pages */ | |
105 | size_t port_rcvegrbuf_size; | |
106 | /* rcvhdrq size (for freeing) */ | |
107 | size_t port_rcvhdrq_size; | |
108 | /* next expected TID to check when looking for free */ | |
109 | u32 port_tidcursor; | |
110 | /* next expected TID to check */ | |
111 | unsigned long port_flag; | |
112 | /* WAIT_RCV that timed out, no interrupt */ | |
113 | u32 port_rcvwait_to; | |
114 | /* WAIT_PIO that timed out, no interrupt */ | |
115 | u32 port_piowait_to; | |
116 | /* WAIT_RCV already happened, no wait */ | |
117 | u32 port_rcvnowait; | |
118 | /* WAIT_PIO already happened, no wait */ | |
119 | u32 port_pionowait; | |
120 | /* total number of rcvhdrqfull errors */ | |
121 | u32 port_hdrqfull; | |
122 | /* pid of process using this port */ | |
123 | pid_t port_pid; | |
124 | /* same size as task_struct .comm[] */ | |
125 | char port_comm[16]; | |
126 | /* pkeys set by this use of this port */ | |
127 | u16 port_pkeys[4]; | |
128 | /* so file ops can get at unit */ | |
129 | struct ipath_devdata *port_dd; | |
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130 | /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */ |
131 | void *subport_uregbase; | |
132 | /* An array of pages for the eager receive buffers * N */ | |
133 | void *subport_rcvegrbuf; | |
134 | /* An array of pages for the eager header queue entries * N */ | |
135 | void *subport_rcvhdr_base; | |
136 | /* The version of the library which opened this port */ | |
137 | u32 userversion; | |
138 | /* Bitmask of active slaves */ | |
139 | u32 active_slaves; | |
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140 | }; |
141 | ||
142 | struct sk_buff; | |
143 | ||
144 | /* | |
145 | * control information for layered drivers | |
146 | */ | |
147 | struct _ipath_layer { | |
148 | void *l_arg; | |
149 | }; | |
150 | ||
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151 | struct ipath_skbinfo { |
152 | struct sk_buff *skb; | |
153 | dma_addr_t phys; | |
154 | }; | |
155 | ||
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156 | struct ipath_devdata { |
157 | struct list_head ipath_list; | |
158 | ||
159 | struct ipath_kregs const *ipath_kregs; | |
160 | struct ipath_cregs const *ipath_cregs; | |
161 | ||
162 | /* mem-mapped pointer to base of chip regs */ | |
163 | u64 __iomem *ipath_kregbase; | |
164 | /* end of mem-mapped chip space; range checking */ | |
165 | u64 __iomem *ipath_kregend; | |
166 | /* physical address of chip for io_remap, etc. */ | |
167 | unsigned long ipath_physaddr; | |
168 | /* base of memory alloced for ipath_kregbase, for free */ | |
169 | u64 *ipath_kregalloc; | |
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170 | /* |
171 | * virtual address where port0 rcvhdrqtail updated for this unit. | |
172 | * only written to by the chip, not the driver. | |
173 | */ | |
174 | volatile __le64 *ipath_hdrqtailptr; | |
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175 | /* ipath_cfgports pointers */ |
176 | struct ipath_portdata **ipath_pd; | |
177 | /* sk_buffs used by port 0 eager receive queue */ | |
1fd3b40f | 178 | struct ipath_skbinfo *ipath_port0_skbinfo; |
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179 | /* kvirt address of 1st 2k pio buffer */ |
180 | void __iomem *ipath_pio2kbase; | |
181 | /* kvirt address of 1st 4k pio buffer */ | |
182 | void __iomem *ipath_pio4kbase; | |
183 | /* | |
184 | * points to area where PIOavail registers will be DMA'ed. | |
185 | * Has to be on a page of it's own, because the page will be | |
186 | * mapped into user program space. This copy is *ONLY* ever | |
187 | * written by DMA, not by the driver! Need a copy per device | |
188 | * when we get to multiple devices | |
189 | */ | |
190 | volatile __le64 *ipath_pioavailregs_dma; | |
191 | /* physical address where updates occur */ | |
192 | dma_addr_t ipath_pioavailregs_phys; | |
193 | struct _ipath_layer ipath_layer; | |
194 | /* setup intr */ | |
195 | int (*ipath_f_intrsetup)(struct ipath_devdata *); | |
196 | /* setup on-chip bus config */ | |
197 | int (*ipath_f_bus)(struct ipath_devdata *, struct pci_dev *); | |
198 | /* hard reset chip */ | |
199 | int (*ipath_f_reset)(struct ipath_devdata *); | |
200 | int (*ipath_f_get_boardname)(struct ipath_devdata *, char *, | |
201 | size_t); | |
202 | void (*ipath_f_init_hwerrors)(struct ipath_devdata *); | |
203 | void (*ipath_f_handle_hwerrors)(struct ipath_devdata *, char *, | |
204 | size_t); | |
205 | void (*ipath_f_quiet_serdes)(struct ipath_devdata *); | |
206 | int (*ipath_f_bringup_serdes)(struct ipath_devdata *); | |
207 | int (*ipath_f_early_init)(struct ipath_devdata *); | |
208 | void (*ipath_f_clear_tids)(struct ipath_devdata *, unsigned); | |
209 | void (*ipath_f_put_tid)(struct ipath_devdata *, u64 __iomem*, | |
210 | u32, unsigned long); | |
211 | void (*ipath_f_tidtemplate)(struct ipath_devdata *); | |
212 | void (*ipath_f_cleanup)(struct ipath_devdata *); | |
213 | void (*ipath_f_setextled)(struct ipath_devdata *, u64, u64); | |
214 | /* fill out chip-specific fields */ | |
215 | int (*ipath_f_get_base_info)(struct ipath_portdata *, void *); | |
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216 | struct ipath_ibdev *verbs_dev; |
217 | struct timer_list verbs_timer; | |
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218 | /* total dwords sent (summed from counter) */ |
219 | u64 ipath_sword; | |
220 | /* total dwords rcvd (summed from counter) */ | |
221 | u64 ipath_rword; | |
222 | /* total packets sent (summed from counter) */ | |
223 | u64 ipath_spkts; | |
224 | /* total packets rcvd (summed from counter) */ | |
225 | u64 ipath_rpkts; | |
226 | /* ipath_statusp initially points to this. */ | |
227 | u64 _ipath_status; | |
228 | /* GUID for this interface, in network order */ | |
229 | __be64 ipath_guid; | |
230 | /* | |
231 | * aggregrate of error bits reported since last cleared, for | |
232 | * limiting of error reporting | |
233 | */ | |
234 | ipath_err_t ipath_lasterror; | |
235 | /* | |
236 | * aggregrate of error bits reported since last cleared, for | |
237 | * limiting of hwerror reporting | |
238 | */ | |
239 | ipath_err_t ipath_lasthwerror; | |
240 | /* | |
241 | * errors masked because they occur too fast, also includes errors | |
242 | * that are always ignored (ipath_ignorederrs) | |
243 | */ | |
244 | ipath_err_t ipath_maskederrs; | |
245 | /* time in jiffies at which to re-enable maskederrs */ | |
246 | unsigned long ipath_unmasktime; | |
247 | /* | |
248 | * errors always ignored (masked), at least for a given | |
249 | * chip/device, because they are wrong or not useful | |
250 | */ | |
251 | ipath_err_t ipath_ignorederrs; | |
252 | /* count of egrfull errors, combined for all ports */ | |
253 | u64 ipath_last_tidfull; | |
254 | /* for ipath_qcheck() */ | |
255 | u64 ipath_lastport0rcv_cnt; | |
256 | /* template for writing TIDs */ | |
257 | u64 ipath_tidtemplate; | |
258 | /* value to write to free TIDs */ | |
259 | u64 ipath_tidinvalid; | |
525d0ca1 | 260 | /* IBA6120 rcv interrupt setup */ |
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261 | u64 ipath_rhdrhead_intr_off; |
262 | ||
263 | /* size of memory at ipath_kregbase */ | |
264 | u32 ipath_kregsize; | |
265 | /* number of registers used for pioavail */ | |
266 | u32 ipath_pioavregs; | |
267 | /* IPATH_POLL, etc. */ | |
268 | u32 ipath_flags; | |
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269 | /* ipath_flags driver is waiting for */ |
270 | u32 ipath_state_wanted; | |
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271 | /* last buffer for user use, first buf for kernel use is this |
272 | * index. */ | |
273 | u32 ipath_lastport_piobuf; | |
274 | /* is a stats timer active */ | |
275 | u32 ipath_stats_timer_active; | |
276 | /* dwords sent read from counter */ | |
277 | u32 ipath_lastsword; | |
278 | /* dwords received read from counter */ | |
279 | u32 ipath_lastrword; | |
280 | /* sent packets read from counter */ | |
281 | u32 ipath_lastspkts; | |
282 | /* received packets read from counter */ | |
283 | u32 ipath_lastrpkts; | |
284 | /* pio bufs allocated per port */ | |
285 | u32 ipath_pbufsport; | |
286 | /* | |
287 | * number of ports configured as max; zero is set to number chip | |
288 | * supports, less gives more pio bufs/port, etc. | |
289 | */ | |
290 | u32 ipath_cfgports; | |
291 | /* port0 rcvhdrq head offset */ | |
292 | u32 ipath_port0head; | |
293 | /* count of port 0 hdrqfull errors */ | |
294 | u32 ipath_p0_hdrqfull; | |
295 | ||
296 | /* | |
297 | * (*cfgports) used to suppress multiple instances of same | |
298 | * port staying stuck at same point | |
299 | */ | |
300 | u32 *ipath_lastrcvhdrqtails; | |
301 | /* | |
302 | * (*cfgports) used to suppress multiple instances of same | |
303 | * port staying stuck at same point | |
304 | */ | |
305 | u32 *ipath_lastegrheads; | |
306 | /* | |
307 | * index of last piobuffer we used. Speeds up searching, by | |
308 | * starting at this point. Doesn't matter if multiple cpu's use and | |
309 | * update, last updater is only write that matters. Whenever it | |
310 | * wraps, we update shadow copies. Need a copy per device when we | |
311 | * get to multiple devices | |
312 | */ | |
313 | u32 ipath_lastpioindex; | |
314 | /* max length of freezemsg */ | |
315 | u32 ipath_freezelen; | |
316 | /* | |
317 | * consecutive times we wanted a PIO buffer but were unable to | |
318 | * get one | |
319 | */ | |
320 | u32 ipath_consec_nopiobuf; | |
321 | /* | |
322 | * hint that we should update ipath_pioavailshadow before | |
323 | * looking for a PIO buffer | |
324 | */ | |
325 | u32 ipath_upd_pio_shadow; | |
326 | /* so we can rewrite it after a chip reset */ | |
327 | u32 ipath_pcibar0; | |
328 | /* so we can rewrite it after a chip reset */ | |
329 | u32 ipath_pcibar1; | |
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330 | |
331 | /* HT/PCI Vendor ID (here for NodeInfo) */ | |
332 | u16 ipath_vendorid; | |
333 | /* HT/PCI Device ID (here for NodeInfo) */ | |
334 | u16 ipath_deviceid; | |
335 | /* offset in HT config space of slave/primary interface block */ | |
336 | u8 ipath_ht_slave_off; | |
337 | /* for write combining settings */ | |
338 | unsigned long ipath_wc_cookie; | |
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339 | unsigned long ipath_wc_base; |
340 | unsigned long ipath_wc_len; | |
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341 | /* ref count for each pkey */ |
342 | atomic_t ipath_pkeyrefs[4]; | |
343 | /* shadow copy of all exptids physaddr; used only by funcsim */ | |
344 | u64 *ipath_tidsimshadow; | |
345 | /* shadow copy of struct page *'s for exp tid pages */ | |
346 | struct page **ipath_pageshadow; | |
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347 | /* shadow copy of dma handles for exp tid pages */ |
348 | dma_addr_t *ipath_physshadow; | |
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349 | /* lock to workaround chip bug 9437 */ |
350 | spinlock_t ipath_tid_lock; | |
351 | ||
352 | /* | |
353 | * IPATH_STATUS_*, | |
354 | * this address is mapped readonly into user processes so they can | |
355 | * get status cheaply, whenever they want. | |
356 | */ | |
357 | u64 *ipath_statusp; | |
358 | /* freeze msg if hw error put chip in freeze */ | |
359 | char *ipath_freezemsg; | |
360 | /* pci access data structure */ | |
361 | struct pci_dev *pcidev; | |
a2acb2ff BS |
362 | struct cdev *user_cdev; |
363 | struct cdev *diag_cdev; | |
364 | struct class_device *user_class_dev; | |
365 | struct class_device *diag_class_dev; | |
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366 | /* timer used to prevent stats overflow, error throttling, etc. */ |
367 | struct timer_list ipath_stats_timer; | |
368 | /* check for stale messages in rcv queue */ | |
369 | /* only allow one intr at a time. */ | |
370 | unsigned long ipath_rcv_pending; | |
35783ec0 BS |
371 | void *ipath_dummy_hdrq; /* used after port close */ |
372 | dma_addr_t ipath_dummy_hdrq_phys; | |
d41d3aeb BS |
373 | |
374 | /* | |
375 | * Shadow copies of registers; size indicates read access size. | |
376 | * Most of them are readonly, but some are write-only register, | |
377 | * where we manipulate the bits in the shadow copy, and then write | |
378 | * the shadow copy to infinipath. | |
379 | * | |
380 | * We deliberately make most of these 32 bits, since they have | |
381 | * restricted range. For any that we read, we won't to generate 32 | |
382 | * bit accesses, since Opteron will generate 2 separate 32 bit HT | |
383 | * transactions for a 64 bit read, and we want to avoid unnecessary | |
384 | * HT transactions. | |
385 | */ | |
386 | ||
387 | /* This is the 64 bit group */ | |
388 | ||
389 | /* | |
390 | * shadow of pioavail, check to be sure it's large enough at | |
391 | * init time. | |
392 | */ | |
393 | unsigned long ipath_pioavailshadow[8]; | |
394 | /* shadow of kr_gpio_out, for rmw ops */ | |
395 | u64 ipath_gpio_out; | |
396 | /* kr_revision shadow */ | |
397 | u64 ipath_revision; | |
398 | /* | |
399 | * shadow of ibcctrl, for interrupt handling of link changes, | |
400 | * etc. | |
401 | */ | |
402 | u64 ipath_ibcctrl; | |
403 | /* | |
404 | * last ibcstatus, to suppress "duplicate" status change messages, | |
405 | * mostly from 2 to 3 | |
406 | */ | |
407 | u64 ipath_lastibcstat; | |
408 | /* hwerrmask shadow */ | |
409 | ipath_err_t ipath_hwerrmask; | |
410 | /* interrupt config reg shadow */ | |
411 | u64 ipath_intconfig; | |
412 | /* kr_sendpiobufbase value */ | |
413 | u64 ipath_piobufbase; | |
414 | ||
415 | /* these are the "32 bit" regs */ | |
416 | ||
417 | /* | |
418 | * number of GUIDs in the flash for this interface; may need some | |
419 | * rethinking for setting on other ifaces | |
420 | */ | |
421 | u32 ipath_nguid; | |
422 | /* | |
423 | * the following two are 32-bit bitmasks, but {test,clear,set}_bit | |
424 | * all expect bit fields to be "unsigned long" | |
425 | */ | |
426 | /* shadow kr_rcvctrl */ | |
427 | unsigned long ipath_rcvctrl; | |
428 | /* shadow kr_sendctrl */ | |
429 | unsigned long ipath_sendctrl; | |
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430 | /* ports waiting for PIOavail intr */ |
431 | unsigned long ipath_portpiowait; | |
432 | unsigned long ipath_lastcancel; /* to not count armlaunch after cancel */ | |
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433 | |
434 | /* value we put in kr_rcvhdrcnt */ | |
435 | u32 ipath_rcvhdrcnt; | |
436 | /* value we put in kr_rcvhdrsize */ | |
437 | u32 ipath_rcvhdrsize; | |
438 | /* value we put in kr_rcvhdrentsize */ | |
439 | u32 ipath_rcvhdrentsize; | |
440 | /* offset of last entry in rcvhdrq */ | |
441 | u32 ipath_hdrqlast; | |
442 | /* kr_portcnt value */ | |
443 | u32 ipath_portcnt; | |
444 | /* kr_pagealign value */ | |
445 | u32 ipath_palign; | |
446 | /* number of "2KB" PIO buffers */ | |
447 | u32 ipath_piobcnt2k; | |
448 | /* size in bytes of "2KB" PIO buffers */ | |
449 | u32 ipath_piosize2k; | |
450 | /* number of "4KB" PIO buffers */ | |
451 | u32 ipath_piobcnt4k; | |
452 | /* size in bytes of "4KB" PIO buffers */ | |
453 | u32 ipath_piosize4k; | |
454 | /* kr_rcvegrbase value */ | |
455 | u32 ipath_rcvegrbase; | |
456 | /* kr_rcvegrcnt value */ | |
457 | u32 ipath_rcvegrcnt; | |
458 | /* kr_rcvtidbase value */ | |
459 | u32 ipath_rcvtidbase; | |
460 | /* kr_rcvtidcnt value */ | |
461 | u32 ipath_rcvtidcnt; | |
462 | /* kr_sendregbase */ | |
463 | u32 ipath_sregbase; | |
464 | /* kr_userregbase */ | |
465 | u32 ipath_uregbase; | |
466 | /* kr_counterregbase */ | |
467 | u32 ipath_cregbase; | |
468 | /* shadow the control register contents */ | |
469 | u32 ipath_control; | |
470 | /* shadow the gpio output contents */ | |
471 | u32 ipath_extctrl; | |
472 | /* PCI revision register (HTC rev on FPGA) */ | |
473 | u32 ipath_pcirev; | |
474 | ||
475 | /* chip address space used by 4k pio buffers */ | |
476 | u32 ipath_4kalign; | |
477 | /* The MTU programmed for this unit */ | |
478 | u32 ipath_ibmtu; | |
479 | /* | |
480 | * The max size IB packet, included IB headers that we can send. | |
481 | * Starts same as ipath_piosize, but is affected when ibmtu is | |
482 | * changed, or by size of eager buffers | |
483 | */ | |
484 | u32 ipath_ibmaxlen; | |
485 | /* | |
486 | * ibmaxlen at init time, limited by chip and by receive buffer | |
487 | * size. Not changed after init. | |
488 | */ | |
489 | u32 ipath_init_ibmaxlen; | |
490 | /* size of each rcvegrbuffer */ | |
491 | u32 ipath_rcvegrbufsize; | |
492 | /* width (2,4,8,16,32) from HT config reg */ | |
493 | u32 ipath_htwidth; | |
494 | /* HT speed (200,400,800,1000) from HT config */ | |
495 | u32 ipath_htspeed; | |
d41d3aeb BS |
496 | /* |
497 | * number of sequential ibcstatus change for polling active/quiet | |
498 | * (i.e., link not coming up). | |
499 | */ | |
500 | u32 ipath_ibpollcnt; | |
501 | /* low and high portions of MSI capability/vector */ | |
502 | u32 ipath_msi_lo; | |
503 | /* saved after PCIe init for restore after reset */ | |
504 | u32 ipath_msi_hi; | |
505 | /* MSI data (vector) saved for restore */ | |
506 | u16 ipath_msi_data; | |
507 | /* MLID programmed for this instance */ | |
508 | u16 ipath_mlid; | |
509 | /* LID programmed for this instance */ | |
510 | u16 ipath_lid; | |
511 | /* list of pkeys programmed; 0 if not set */ | |
512 | u16 ipath_pkeys[4]; | |
8307c28e BS |
513 | /* |
514 | * ASCII serial number, from flash, large enough for original | |
515 | * all digit strings, and longer QLogic serial number format | |
516 | */ | |
517 | u8 ipath_serial[16]; | |
d41d3aeb BS |
518 | /* human readable board version */ |
519 | u8 ipath_boardversion[80]; | |
520 | /* chip major rev, from ipath_revision */ | |
521 | u8 ipath_majrev; | |
522 | /* chip minor rev, from ipath_revision */ | |
523 | u8 ipath_minrev; | |
524 | /* board rev, from ipath_revision */ | |
525 | u8 ipath_boardrev; | |
526 | /* unit # of this chip, if present */ | |
527 | int ipath_unit; | |
528 | /* saved for restore after reset */ | |
529 | u8 ipath_pci_cacheline; | |
530 | /* LID mask control */ | |
531 | u8 ipath_lmc; | |
30fc5c31 BS |
532 | /* Rx Polarity inversion (compensate for ~tx on partner) */ |
533 | u8 ipath_rx_pol_inv; | |
fba75200 BS |
534 | |
535 | /* local link integrity counter */ | |
536 | u32 ipath_lli_counter; | |
537 | /* local link integrity errors */ | |
538 | u32 ipath_lli_errors; | |
2c9446a1 BS |
539 | /* |
540 | * Above counts only cases where _successive_ LocalLinkIntegrity | |
541 | * errors were seen in the receive headers of kern-packets. | |
542 | * Below are the three (monotonically increasing) counters | |
543 | * maintained via GPIO interrupts on iba6120-rev2. | |
544 | */ | |
545 | u32 ipath_rxfc_unsupvl_errs; | |
546 | u32 ipath_overrun_thresh_errs; | |
547 | u32 ipath_lli_errs; | |
f62fe77a BS |
548 | |
549 | /* | |
550 | * Not all devices managed by a driver instance are the same | |
551 | * type, so these fields must be per-device. | |
552 | */ | |
553 | u64 ipath_i_bitsextant; | |
554 | ipath_err_t ipath_e_bitsextant; | |
555 | ipath_err_t ipath_hwe_bitsextant; | |
556 | ||
557 | /* | |
558 | * Below should be computable from number of ports, | |
559 | * since they are never modified. | |
560 | */ | |
561 | u32 ipath_i_rcvavail_mask; | |
562 | u32 ipath_i_rcvurg_mask; | |
563 | ||
564 | /* | |
565 | * Register bits for selecting i2c direction and values, used for | |
566 | * I2C serial flash. | |
567 | */ | |
568 | u16 ipath_gpio_sda_num; | |
569 | u16 ipath_gpio_scl_num; | |
570 | u64 ipath_gpio_sda; | |
571 | u64 ipath_gpio_scl; | |
d41d3aeb BS |
572 | }; |
573 | ||
9929b0fb BS |
574 | /* Private data for file operations */ |
575 | struct ipath_filedata { | |
576 | struct ipath_portdata *pd; | |
577 | unsigned subport; | |
578 | unsigned tidcursor; | |
579 | }; | |
d41d3aeb BS |
580 | extern struct list_head ipath_dev_list; |
581 | extern spinlock_t ipath_devs_lock; | |
582 | extern struct ipath_devdata *ipath_lookup(int unit); | |
583 | ||
d41d3aeb BS |
584 | int ipath_init_chip(struct ipath_devdata *, int); |
585 | int ipath_enable_wc(struct ipath_devdata *dd); | |
586 | void ipath_disable_wc(struct ipath_devdata *dd); | |
587 | int ipath_count_units(int *npresentp, int *nupp, u32 *maxportsp); | |
588 | void ipath_shutdown_device(struct ipath_devdata *); | |
89d1e09b | 589 | void ipath_disarm_senderrbufs(struct ipath_devdata *); |
d41d3aeb BS |
590 | |
591 | struct file_operations; | |
592 | int ipath_cdev_init(int minor, char *name, struct file_operations *fops, | |
593 | struct cdev **cdevp, struct class_device **class_devp); | |
594 | void ipath_cdev_cleanup(struct cdev **cdevp, | |
595 | struct class_device **class_devp); | |
596 | ||
a2acb2ff BS |
597 | int ipath_diag_add(struct ipath_devdata *); |
598 | void ipath_diag_remove(struct ipath_devdata *); | |
d41d3aeb | 599 | |
0fd41363 | 600 | extern wait_queue_head_t ipath_state_wait; |
d41d3aeb BS |
601 | |
602 | int ipath_user_add(struct ipath_devdata *dd); | |
a2acb2ff | 603 | void ipath_user_remove(struct ipath_devdata *dd); |
d41d3aeb BS |
604 | |
605 | struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd, gfp_t); | |
606 | ||
607 | extern int ipath_diag_inuse; | |
608 | ||
7d12e780 | 609 | irqreturn_t ipath_intr(int irq, void *devid); |
d41d3aeb BS |
610 | void ipath_decode_err(char *buf, size_t blen, ipath_err_t err); |
611 | #if __IPATH_INFO || __IPATH_DBG | |
612 | extern const char *ipath_ibcstatus_str[]; | |
613 | #endif | |
614 | ||
615 | /* clean up any per-chip chip-specific stuff */ | |
616 | void ipath_chip_cleanup(struct ipath_devdata *); | |
617 | /* clean up any chip type-specific stuff */ | |
618 | void ipath_chip_done(void); | |
619 | ||
620 | /* check to see if we have to force ordering for write combining */ | |
621 | int ipath_unordered_wc(void); | |
622 | ||
623 | void ipath_disarm_piobufs(struct ipath_devdata *, unsigned first, | |
624 | unsigned cnt); | |
625 | ||
626 | int ipath_create_rcvhdrq(struct ipath_devdata *, struct ipath_portdata *); | |
f37bda92 | 627 | void ipath_free_pddata(struct ipath_devdata *, struct ipath_portdata *); |
d41d3aeb BS |
628 | |
629 | int ipath_parse_ushort(const char *str, unsigned short *valp); | |
630 | ||
d41d3aeb BS |
631 | void ipath_kreceive(struct ipath_devdata *); |
632 | int ipath_setrcvhdrsize(struct ipath_devdata *, unsigned); | |
633 | int ipath_reset_device(int); | |
634 | void ipath_get_faststats(unsigned long); | |
34b2aafe BS |
635 | int ipath_set_linkstate(struct ipath_devdata *, u8); |
636 | int ipath_set_mtu(struct ipath_devdata *, u16); | |
637 | int ipath_set_lid(struct ipath_devdata *, u32, u8); | |
30fc5c31 | 638 | int ipath_set_rx_pol_inv(struct ipath_devdata *dd, u8 new_pol_inv); |
d41d3aeb BS |
639 | |
640 | /* for use in system calls, where we want to know device type, etc. */ | |
9929b0fb BS |
641 | #define port_fp(fp) ((struct ipath_filedata *)(fp)->private_data)->pd |
642 | #define subport_fp(fp) \ | |
643 | ((struct ipath_filedata *)(fp)->private_data)->subport | |
644 | #define tidcursor_fp(fp) \ | |
645 | ((struct ipath_filedata *)(fp)->private_data)->tidcursor | |
d41d3aeb BS |
646 | |
647 | /* | |
648 | * values for ipath_flags | |
649 | */ | |
650 | /* The chip is up and initted */ | |
651 | #define IPATH_INITTED 0x2 | |
652 | /* set if any user code has set kr_rcvhdrsize */ | |
653 | #define IPATH_RCVHDRSZ_SET 0x4 | |
654 | /* The chip is present and valid for accesses */ | |
655 | #define IPATH_PRESENT 0x8 | |
656 | /* HT link0 is only 8 bits wide, ignore upper byte crc | |
657 | * errors, etc. */ | |
658 | #define IPATH_8BIT_IN_HT0 0x10 | |
659 | /* HT link1 is only 8 bits wide, ignore upper byte crc | |
660 | * errors, etc. */ | |
661 | #define IPATH_8BIT_IN_HT1 0x20 | |
662 | /* The link is down */ | |
663 | #define IPATH_LINKDOWN 0x40 | |
664 | /* The link level is up (0x11) */ | |
665 | #define IPATH_LINKINIT 0x80 | |
666 | /* The link is in the armed (0x21) state */ | |
667 | #define IPATH_LINKARMED 0x100 | |
668 | /* The link is in the active (0x31) state */ | |
669 | #define IPATH_LINKACTIVE 0x200 | |
670 | /* link current state is unknown */ | |
671 | #define IPATH_LINKUNK 0x400 | |
672 | /* no IB cable, or no device on IB cable */ | |
673 | #define IPATH_NOCABLE 0x4000 | |
674 | /* Supports port zero per packet receive interrupts via | |
675 | * GPIO */ | |
676 | #define IPATH_GPIO_INTR 0x8000 | |
677 | /* uses the coded 4byte TID, not 8 byte */ | |
678 | #define IPATH_4BYTE_TID 0x10000 | |
679 | /* packet/word counters are 32 bit, else those 4 counters | |
680 | * are 64bit */ | |
681 | #define IPATH_32BITCOUNTERS 0x20000 | |
682 | /* can miss port0 rx interrupts */ | |
683 | #define IPATH_POLL_RX_INTR 0x40000 | |
684 | #define IPATH_DISABLED 0x80000 /* administratively disabled */ | |
2c9446a1 BS |
685 | /* Use GPIO interrupts for new counters */ |
686 | #define IPATH_GPIO_ERRINTRS 0x100000 | |
687 | ||
688 | /* Bits in GPIO for the added interrupts */ | |
689 | #define IPATH_GPIO_PORT0_BIT 2 | |
690 | #define IPATH_GPIO_RXUVL_BIT 3 | |
691 | #define IPATH_GPIO_OVRUN_BIT 4 | |
692 | #define IPATH_GPIO_LLI_BIT 5 | |
693 | #define IPATH_GPIO_ERRINTR_MASK 0x38 | |
d41d3aeb BS |
694 | |
695 | /* portdata flag bit offsets */ | |
696 | /* waiting for a packet to arrive */ | |
697 | #define IPATH_PORT_WAITING_RCV 2 | |
698 | /* waiting for a PIO buffer to be available */ | |
699 | #define IPATH_PORT_WAITING_PIO 3 | |
700 | ||
701 | /* free up any allocated data at closes */ | |
702 | void ipath_free_data(struct ipath_portdata *dd); | |
703 | int ipath_waitfor_mdio_cmdready(struct ipath_devdata *); | |
704 | int ipath_waitfor_complete(struct ipath_devdata *, ipath_kreg, u64, u64 *); | |
705 | u32 __iomem *ipath_getpiobuf(struct ipath_devdata *, u32 *); | |
525d0ca1 BS |
706 | void ipath_init_iba6120_funcs(struct ipath_devdata *); |
707 | void ipath_init_iba6110_funcs(struct ipath_devdata *); | |
f2080fa3 | 708 | void ipath_get_eeprom_info(struct ipath_devdata *); |
d41d3aeb BS |
709 | u64 ipath_snap_cntr(struct ipath_devdata *, ipath_creg); |
710 | ||
711 | /* | |
712 | * number of words used for protocol header if not set by ipath_userinit(); | |
713 | */ | |
714 | #define IPATH_DFLT_RCVHDRSIZE 9 | |
715 | ||
716 | #define IPATH_MDIO_CMD_WRITE 1 | |
717 | #define IPATH_MDIO_CMD_READ 2 | |
718 | #define IPATH_MDIO_CLD_DIV 25 /* to get 2.5 Mhz mdio clock */ | |
719 | #define IPATH_MDIO_CMDVALID 0x40000000 /* bit 30 */ | |
720 | #define IPATH_MDIO_DATAVALID 0x80000000 /* bit 31 */ | |
721 | #define IPATH_MDIO_CTRL_STD 0x0 | |
722 | ||
723 | static inline u64 ipath_mdio_req(int cmd, int dev, int reg, int data) | |
724 | { | |
725 | return (((u64) IPATH_MDIO_CLD_DIV) << 32) | | |
726 | (cmd << 26) | | |
727 | (dev << 21) | | |
728 | (reg << 16) | | |
729 | (data & 0xFFFF); | |
730 | } | |
731 | ||
732 | /* signal and fifo status, in bank 31 */ | |
733 | #define IPATH_MDIO_CTRL_XGXS_REG_8 0x8 | |
734 | /* controls loopback, redundancy */ | |
735 | #define IPATH_MDIO_CTRL_8355_REG_1 0x10 | |
736 | /* premph, encdec, etc. */ | |
737 | #define IPATH_MDIO_CTRL_8355_REG_2 0x11 | |
738 | /* Kchars, etc. */ | |
739 | #define IPATH_MDIO_CTRL_8355_REG_6 0x15 | |
740 | #define IPATH_MDIO_CTRL_8355_REG_9 0x18 | |
741 | #define IPATH_MDIO_CTRL_8355_REG_10 0x1D | |
742 | ||
743 | int ipath_get_user_pages(unsigned long, size_t, struct page **); | |
744 | int ipath_get_user_pages_nocopy(unsigned long, struct page **); | |
745 | void ipath_release_user_pages(struct page **, size_t); | |
746 | void ipath_release_user_pages_on_close(struct page **, size_t); | |
747 | int ipath_eeprom_read(struct ipath_devdata *, u8, void *, int); | |
748 | int ipath_eeprom_write(struct ipath_devdata *, u8, const void *, int); | |
749 | ||
750 | /* these are used for the registers that vary with port */ | |
751 | void ipath_write_kreg_port(const struct ipath_devdata *, ipath_kreg, | |
752 | unsigned, u64); | |
753 | u64 ipath_read_kreg64_port(const struct ipath_devdata *, ipath_kreg, | |
754 | unsigned); | |
755 | ||
756 | /* | |
757 | * We could have a single register get/put routine, that takes a group type, | |
758 | * but this is somewhat clearer and cleaner. It also gives us some error | |
759 | * checking. 64 bit register reads should always work, but are inefficient | |
760 | * on opteron (the northbridge always generates 2 separate HT 32 bit reads), | |
761 | * so we use kreg32 wherever possible. User register and counter register | |
762 | * reads are always 32 bit reads, so only one form of those routines. | |
763 | */ | |
764 | ||
765 | /* | |
766 | * At the moment, none of the s-registers are writable, so no | |
767 | * ipath_write_sreg(), and none of the c-registers are writable, so no | |
768 | * ipath_write_creg(). | |
769 | */ | |
770 | ||
771 | /** | |
772 | * ipath_read_ureg32 - read 32-bit virtualized per-port register | |
773 | * @dd: device | |
774 | * @regno: register number | |
775 | * @port: port number | |
776 | * | |
777 | * Return the contents of a register that is virtualized to be per port. | |
685f97e8 BS |
778 | * Returns -1 on errors (not distinguishable from valid contents at |
779 | * runtime; we may add a separate error variable at some point). | |
d41d3aeb BS |
780 | */ |
781 | static inline u32 ipath_read_ureg32(const struct ipath_devdata *dd, | |
782 | ipath_ureg regno, int port) | |
783 | { | |
c71c30dc | 784 | if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) |
d41d3aeb BS |
785 | return 0; |
786 | ||
787 | return readl(regno + (u64 __iomem *) | |
788 | (dd->ipath_uregbase + | |
789 | (char __iomem *)dd->ipath_kregbase + | |
790 | dd->ipath_palign * port)); | |
791 | } | |
792 | ||
793 | /** | |
794 | * ipath_write_ureg - write 32-bit virtualized per-port register | |
795 | * @dd: device | |
796 | * @regno: register number | |
797 | * @value: value | |
798 | * @port: port | |
799 | * | |
800 | * Write the contents of a register that is virtualized to be per port. | |
801 | */ | |
802 | static inline void ipath_write_ureg(const struct ipath_devdata *dd, | |
803 | ipath_ureg regno, u64 value, int port) | |
804 | { | |
805 | u64 __iomem *ubase = (u64 __iomem *) | |
806 | (dd->ipath_uregbase + (char __iomem *) dd->ipath_kregbase + | |
807 | dd->ipath_palign * port); | |
808 | if (dd->ipath_kregbase) | |
809 | writeq(value, &ubase[regno]); | |
810 | } | |
811 | ||
812 | static inline u32 ipath_read_kreg32(const struct ipath_devdata *dd, | |
813 | ipath_kreg regno) | |
814 | { | |
c71c30dc | 815 | if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) |
d41d3aeb BS |
816 | return -1; |
817 | return readl((u32 __iomem *) & dd->ipath_kregbase[regno]); | |
818 | } | |
819 | ||
820 | static inline u64 ipath_read_kreg64(const struct ipath_devdata *dd, | |
821 | ipath_kreg regno) | |
822 | { | |
c71c30dc | 823 | if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) |
d41d3aeb BS |
824 | return -1; |
825 | ||
826 | return readq(&dd->ipath_kregbase[regno]); | |
827 | } | |
828 | ||
829 | static inline void ipath_write_kreg(const struct ipath_devdata *dd, | |
830 | ipath_kreg regno, u64 value) | |
831 | { | |
832 | if (dd->ipath_kregbase) | |
833 | writeq(value, &dd->ipath_kregbase[regno]); | |
834 | } | |
835 | ||
836 | static inline u64 ipath_read_creg(const struct ipath_devdata *dd, | |
837 | ipath_sreg regno) | |
838 | { | |
c71c30dc | 839 | if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) |
d41d3aeb BS |
840 | return 0; |
841 | ||
842 | return readq(regno + (u64 __iomem *) | |
843 | (dd->ipath_cregbase + | |
844 | (char __iomem *)dd->ipath_kregbase)); | |
845 | } | |
846 | ||
847 | static inline u32 ipath_read_creg32(const struct ipath_devdata *dd, | |
848 | ipath_sreg regno) | |
849 | { | |
c71c30dc | 850 | if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) |
d41d3aeb BS |
851 | return 0; |
852 | return readl(regno + (u64 __iomem *) | |
853 | (dd->ipath_cregbase + | |
854 | (char __iomem *)dd->ipath_kregbase)); | |
855 | } | |
856 | ||
857 | /* | |
858 | * sysfs interface. | |
859 | */ | |
860 | ||
861 | struct device_driver; | |
862 | ||
b55f4f06 | 863 | extern const char ib_ipath_version[]; |
d41d3aeb BS |
864 | |
865 | int ipath_driver_create_group(struct device_driver *); | |
866 | void ipath_driver_remove_group(struct device_driver *); | |
867 | ||
868 | int ipath_device_create_group(struct device *, struct ipath_devdata *); | |
869 | void ipath_device_remove_group(struct device *, struct ipath_devdata *); | |
870 | int ipath_expose_reset(struct device *); | |
871 | ||
98341f26 BS |
872 | int ipath_diagpkt_add(void); |
873 | void ipath_diagpkt_remove(void); | |
874 | ||
d41d3aeb BS |
875 | int ipath_init_ipathfs(void); |
876 | void ipath_exit_ipathfs(void); | |
877 | int ipathfs_add_device(struct ipath_devdata *); | |
878 | int ipathfs_remove_device(struct ipath_devdata *); | |
879 | ||
1fd3b40f BS |
880 | /* |
881 | * dma_addr wrappers - all 0's invalid for hw | |
882 | */ | |
883 | dma_addr_t ipath_map_page(struct pci_dev *, struct page *, unsigned long, | |
884 | size_t, int); | |
885 | dma_addr_t ipath_map_single(struct pci_dev *, void *, size_t, int); | |
886 | ||
d41d3aeb BS |
887 | /* |
888 | * Flush write combining store buffers (if present) and perform a write | |
889 | * barrier. | |
890 | */ | |
891 | #if defined(CONFIG_X86_64) | |
892 | #define ipath_flush_wc() asm volatile("sfence" ::: "memory") | |
893 | #else | |
894 | #define ipath_flush_wc() wmb() | |
895 | #endif | |
896 | ||
897 | extern unsigned ipath_debug; /* debugging bit mask */ | |
898 | ||
899 | const char *ipath_get_unit_name(int unit); | |
900 | ||
901 | extern struct mutex ipath_mutex; | |
902 | ||
b55f4f06 | 903 | #define IPATH_DRV_NAME "ib_ipath" |
d41d3aeb | 904 | #define IPATH_MAJOR 233 |
a2acb2ff | 905 | #define IPATH_USER_MINOR_BASE 0 |
98341f26 | 906 | #define IPATH_DIAGPKT_MINOR 127 |
a2acb2ff BS |
907 | #define IPATH_DIAG_MINOR_BASE 129 |
908 | #define IPATH_NMINORS 255 | |
d41d3aeb BS |
909 | |
910 | #define ipath_dev_err(dd,fmt,...) \ | |
911 | do { \ | |
912 | const struct ipath_devdata *__dd = (dd); \ | |
913 | if (__dd->pcidev) \ | |
914 | dev_err(&__dd->pcidev->dev, "%s: " fmt, \ | |
915 | ipath_get_unit_name(__dd->ipath_unit), \ | |
916 | ##__VA_ARGS__); \ | |
917 | else \ | |
918 | printk(KERN_ERR IPATH_DRV_NAME ": %s: " fmt, \ | |
919 | ipath_get_unit_name(__dd->ipath_unit), \ | |
920 | ##__VA_ARGS__); \ | |
921 | } while (0) | |
922 | ||
923 | #if _IPATH_DEBUGGING | |
924 | ||
925 | # define __IPATH_DBG_WHICH(which,fmt,...) \ | |
926 | do { \ | |
927 | if(unlikely(ipath_debug&(which))) \ | |
928 | printk(KERN_DEBUG IPATH_DRV_NAME ": %s: " fmt, \ | |
929 | __func__,##__VA_ARGS__); \ | |
930 | } while(0) | |
931 | ||
932 | # define ipath_dbg(fmt,...) \ | |
933 | __IPATH_DBG_WHICH(__IPATH_DBG,fmt,##__VA_ARGS__) | |
934 | # define ipath_cdbg(which,fmt,...) \ | |
935 | __IPATH_DBG_WHICH(__IPATH_##which##DBG,fmt,##__VA_ARGS__) | |
936 | ||
937 | #else /* ! _IPATH_DEBUGGING */ | |
938 | ||
939 | # define ipath_dbg(fmt,...) | |
940 | # define ipath_cdbg(which,fmt,...) | |
941 | ||
942 | #endif /* _IPATH_DEBUGGING */ | |
943 | ||
8d588f8b BS |
944 | /* |
945 | * this is used for formatting hw error messages... | |
946 | */ | |
947 | struct ipath_hwerror_msgs { | |
948 | u64 mask; | |
949 | const char *msg; | |
950 | }; | |
951 | ||
952 | #define INFINIPATH_HWE_MSG(a, b) { .mask = INFINIPATH_HWE_##a, .msg = b } | |
953 | ||
954 | /* in ipath_intr.c... */ | |
955 | void ipath_format_hwerrors(u64 hwerrs, | |
956 | const struct ipath_hwerror_msgs *hwerrmsgs, | |
957 | size_t nhwerrmsgs, | |
958 | char *msg, size_t lmsg); | |
959 | ||
d41d3aeb | 960 | #endif /* _IPATH_KERNEL_H */ |