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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. | |
51a379d0 | 3 | * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
4 | * |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the | |
9 | * OpenIB.org BSD license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or | |
12 | * without modification, are permitted provided that the following | |
13 | * conditions are met: | |
14 | * | |
15 | * - Redistributions of source code must retain the above | |
16 | * copyright notice, this list of conditions and the following | |
17 | * disclaimer. | |
18 | * | |
19 | * - Redistributions in binary form must reproduce the above | |
20 | * copyright notice, this list of conditions and the following | |
21 | * disclaimer in the documentation and/or other materials | |
22 | * provided with the distribution. | |
23 | * | |
24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
31 | * SOFTWARE. | |
32 | */ | |
33 | ||
34 | #include <linux/module.h> | |
35 | #include <linux/init.h> | |
5a0e3ad6 | 36 | #include <linux/slab.h> |
225c7b1f | 37 | #include <linux/errno.h> |
fa417f7b EC |
38 | #include <linux/netdevice.h> |
39 | #include <linux/inetdevice.h> | |
40 | #include <linux/rtnetlink.h> | |
4c3eb3ca | 41 | #include <linux/if_vlan.h> |
6e84f315 | 42 | #include <linux/sched/mm.h> |
0881e7bd | 43 | #include <linux/sched/task.h> |
6e84f315 | 44 | |
d487ee77 MS |
45 | #include <net/ipv6.h> |
46 | #include <net/addrconf.h> | |
09d4d087 | 47 | #include <net/devlink.h> |
225c7b1f RD |
48 | |
49 | #include <rdma/ib_smi.h> | |
50 | #include <rdma/ib_user_verbs.h> | |
fa417f7b | 51 | #include <rdma/ib_addr.h> |
e26be1bf MS |
52 | #include <rdma/ib_cache.h> |
53 | ||
54 | #include <net/bonding.h> | |
225c7b1f RD |
55 | |
56 | #include <linux/mlx4/driver.h> | |
57 | #include <linux/mlx4/cmd.h> | |
9433c188 | 58 | #include <linux/mlx4/qp.h> |
225c7b1f RD |
59 | |
60 | #include "mlx4_ib.h" | |
9ce28a20 | 61 | #include <rdma/mlx4-abi.h> |
225c7b1f | 62 | |
b1d8eb5a | 63 | #define DRV_NAME MLX4_IB_DRV_NAME |
0a528ee9 | 64 | #define DRV_VERSION "4.0-0" |
225c7b1f | 65 | |
f77c0162 | 66 | #define MLX4_IB_FLOW_MAX_PRIO 0xFFF |
a37a1a42 | 67 | #define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF |
50e2ec91 | 68 | #define MLX4_IB_CARD_REV_A0 0xA0 |
f77c0162 | 69 | |
225c7b1f RD |
70 | MODULE_AUTHOR("Roland Dreier"); |
71 | MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver"); | |
72 | MODULE_LICENSE("Dual BSD/GPL"); | |
73 | MODULE_VERSION(DRV_VERSION); | |
74 | ||
56c1d233 | 75 | int mlx4_ib_sm_guid_assign = 0; |
a0c64a17 | 76 | module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444); |
56c1d233 | 77 | MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)"); |
a0c64a17 | 78 | |
68f3948d | 79 | static const char mlx4_ib_version[] = |
225c7b1f | 80 | DRV_NAME ": Mellanox ConnectX InfiniBand driver v" |
0a528ee9 | 81 | DRV_VERSION "\n"; |
225c7b1f | 82 | |
3806d08c JM |
83 | static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init); |
84 | ||
fa417f7b EC |
85 | static struct workqueue_struct *wq; |
86 | ||
225c7b1f RD |
87 | static void init_query_mad(struct ib_smp *mad) |
88 | { | |
89 | mad->base_version = 1; | |
90 | mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; | |
91 | mad->class_version = 1; | |
92 | mad->method = IB_MGMT_METHOD_GET; | |
93 | } | |
94 | ||
f77c0162 HHZ |
95 | static int check_flow_steering_support(struct mlx4_dev *dev) |
96 | { | |
0a9b7d59 | 97 | int eth_num_ports = 0; |
f77c0162 | 98 | int ib_num_ports = 0; |
f77c0162 | 99 | |
0a9b7d59 MB |
100 | int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED; |
101 | ||
102 | if (dmfs) { | |
103 | int i; | |
104 | mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) | |
105 | eth_num_ports++; | |
106 | mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) | |
107 | ib_num_ports++; | |
108 | dmfs &= (!ib_num_ports || | |
109 | (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) && | |
110 | (!eth_num_ports || | |
111 | (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)); | |
112 | if (ib_num_ports && mlx4_is_mfunc(dev)) { | |
113 | pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n"); | |
114 | dmfs = 0; | |
f77c0162 | 115 | } |
f77c0162 | 116 | } |
0a9b7d59 | 117 | return dmfs; |
f77c0162 HHZ |
118 | } |
119 | ||
3dec4878 JM |
120 | static int num_ib_ports(struct mlx4_dev *dev) |
121 | { | |
122 | int ib_ports = 0; | |
123 | int i; | |
124 | ||
125 | mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) | |
126 | ib_ports++; | |
127 | ||
128 | return ib_ports; | |
129 | } | |
130 | ||
e26be1bf MS |
131 | static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num) |
132 | { | |
133 | struct mlx4_ib_dev *ibdev = to_mdev(device); | |
134 | struct net_device *dev; | |
135 | ||
136 | rcu_read_lock(); | |
137 | dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num); | |
138 | ||
139 | if (dev) { | |
140 | if (mlx4_is_bonded(ibdev->dev)) { | |
141 | struct net_device *upper = NULL; | |
142 | ||
143 | upper = netdev_master_upper_dev_get_rcu(dev); | |
144 | if (upper) { | |
145 | struct net_device *active; | |
146 | ||
147 | active = bond_option_active_slave_get_rcu(netdev_priv(upper)); | |
148 | if (active) | |
149 | dev = active; | |
150 | } | |
151 | } | |
152 | } | |
153 | if (dev) | |
154 | dev_hold(dev); | |
155 | ||
156 | rcu_read_unlock(); | |
157 | return dev; | |
158 | } | |
159 | ||
7e57b85c MS |
160 | static int mlx4_ib_update_gids_v1(struct gid_entry *gids, |
161 | struct mlx4_ib_dev *ibdev, | |
162 | u8 port_num) | |
e26be1bf MS |
163 | { |
164 | struct mlx4_cmd_mailbox *mailbox; | |
165 | int err; | |
166 | struct mlx4_dev *dev = ibdev->dev; | |
167 | int i; | |
168 | union ib_gid *gid_tbl; | |
169 | ||
170 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
171 | if (IS_ERR(mailbox)) | |
172 | return -ENOMEM; | |
173 | ||
174 | gid_tbl = mailbox->buf; | |
175 | ||
176 | for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) | |
177 | memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid)); | |
178 | ||
179 | err = mlx4_cmd(dev, mailbox->dma, | |
180 | MLX4_SET_PORT_GID_TABLE << 8 | port_num, | |
181 | 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, | |
182 | MLX4_CMD_WRAPPED); | |
183 | if (mlx4_is_bonded(dev)) | |
184 | err += mlx4_cmd(dev, mailbox->dma, | |
185 | MLX4_SET_PORT_GID_TABLE << 8 | 2, | |
186 | 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, | |
187 | MLX4_CMD_WRAPPED); | |
188 | ||
189 | mlx4_free_cmd_mailbox(dev, mailbox); | |
190 | return err; | |
191 | } | |
192 | ||
7e57b85c MS |
193 | static int mlx4_ib_update_gids_v1_v2(struct gid_entry *gids, |
194 | struct mlx4_ib_dev *ibdev, | |
195 | u8 port_num) | |
196 | { | |
197 | struct mlx4_cmd_mailbox *mailbox; | |
198 | int err; | |
199 | struct mlx4_dev *dev = ibdev->dev; | |
200 | int i; | |
201 | struct { | |
202 | union ib_gid gid; | |
203 | __be32 rsrvd1[2]; | |
204 | __be16 rsrvd2; | |
205 | u8 type; | |
206 | u8 version; | |
207 | __be32 rsrvd3; | |
208 | } *gid_tbl; | |
209 | ||
210 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
211 | if (IS_ERR(mailbox)) | |
212 | return -ENOMEM; | |
213 | ||
214 | gid_tbl = mailbox->buf; | |
215 | for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) { | |
216 | memcpy(&gid_tbl[i].gid, &gids[i].gid, sizeof(union ib_gid)); | |
217 | if (gids[i].gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { | |
218 | gid_tbl[i].version = 2; | |
219 | if (!ipv6_addr_v4mapped((struct in6_addr *)&gids[i].gid)) | |
220 | gid_tbl[i].type = 1; | |
221 | else | |
222 | memset(&gid_tbl[i].gid, 0, 12); | |
223 | } | |
224 | } | |
225 | ||
226 | err = mlx4_cmd(dev, mailbox->dma, | |
227 | MLX4_SET_PORT_ROCE_ADDR << 8 | port_num, | |
228 | 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, | |
229 | MLX4_CMD_WRAPPED); | |
230 | if (mlx4_is_bonded(dev)) | |
231 | err += mlx4_cmd(dev, mailbox->dma, | |
232 | MLX4_SET_PORT_ROCE_ADDR << 8 | 2, | |
233 | 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, | |
234 | MLX4_CMD_WRAPPED); | |
235 | ||
236 | mlx4_free_cmd_mailbox(dev, mailbox); | |
237 | return err; | |
238 | } | |
239 | ||
240 | static int mlx4_ib_update_gids(struct gid_entry *gids, | |
241 | struct mlx4_ib_dev *ibdev, | |
242 | u8 port_num) | |
243 | { | |
244 | if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) | |
245 | return mlx4_ib_update_gids_v1_v2(gids, ibdev, port_num); | |
246 | ||
247 | return mlx4_ib_update_gids_v1(gids, ibdev, port_num); | |
248 | } | |
249 | ||
e26be1bf MS |
250 | static int mlx4_ib_add_gid(struct ib_device *device, |
251 | u8 port_num, | |
252 | unsigned int index, | |
253 | const union ib_gid *gid, | |
254 | const struct ib_gid_attr *attr, | |
255 | void **context) | |
256 | { | |
257 | struct mlx4_ib_dev *ibdev = to_mdev(device); | |
258 | struct mlx4_ib_iboe *iboe = &ibdev->iboe; | |
259 | struct mlx4_port_gid_table *port_gid_table; | |
260 | int free = -1, found = -1; | |
261 | int ret = 0; | |
262 | int hw_update = 0; | |
263 | int i; | |
264 | struct gid_entry *gids = NULL; | |
265 | ||
266 | if (!rdma_cap_roce_gid_table(device, port_num)) | |
267 | return -EINVAL; | |
268 | ||
269 | if (port_num > MLX4_MAX_PORTS) | |
270 | return -EINVAL; | |
271 | ||
272 | if (!context) | |
273 | return -EINVAL; | |
274 | ||
275 | port_gid_table = &iboe->gids[port_num - 1]; | |
276 | spin_lock_bh(&iboe->lock); | |
277 | for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) { | |
b699a859 MS |
278 | if (!memcmp(&port_gid_table->gids[i].gid, gid, sizeof(*gid)) && |
279 | (port_gid_table->gids[i].gid_type == attr->gid_type)) { | |
e26be1bf MS |
280 | found = i; |
281 | break; | |
282 | } | |
283 | if (free < 0 && !memcmp(&port_gid_table->gids[i].gid, &zgid, sizeof(*gid))) | |
284 | free = i; /* HW has space */ | |
285 | } | |
286 | ||
287 | if (found < 0) { | |
288 | if (free < 0) { | |
289 | ret = -ENOSPC; | |
290 | } else { | |
291 | port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC); | |
292 | if (!port_gid_table->gids[free].ctx) { | |
293 | ret = -ENOMEM; | |
294 | } else { | |
295 | *context = port_gid_table->gids[free].ctx; | |
296 | memcpy(&port_gid_table->gids[free].gid, gid, sizeof(*gid)); | |
b699a859 | 297 | port_gid_table->gids[free].gid_type = attr->gid_type; |
e26be1bf MS |
298 | port_gid_table->gids[free].ctx->real_index = free; |
299 | port_gid_table->gids[free].ctx->refcount = 1; | |
300 | hw_update = 1; | |
301 | } | |
302 | } | |
303 | } else { | |
304 | struct gid_cache_context *ctx = port_gid_table->gids[found].ctx; | |
305 | *context = ctx; | |
306 | ctx->refcount++; | |
307 | } | |
308 | if (!ret && hw_update) { | |
309 | gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC); | |
310 | if (!gids) { | |
311 | ret = -ENOMEM; | |
312 | } else { | |
b699a859 | 313 | for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) { |
e26be1bf | 314 | memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid)); |
b699a859 MS |
315 | gids[i].gid_type = port_gid_table->gids[i].gid_type; |
316 | } | |
e26be1bf MS |
317 | } |
318 | } | |
319 | spin_unlock_bh(&iboe->lock); | |
320 | ||
321 | if (!ret && hw_update) { | |
322 | ret = mlx4_ib_update_gids(gids, ibdev, port_num); | |
323 | kfree(gids); | |
324 | } | |
325 | ||
326 | return ret; | |
327 | } | |
328 | ||
329 | static int mlx4_ib_del_gid(struct ib_device *device, | |
330 | u8 port_num, | |
331 | unsigned int index, | |
332 | void **context) | |
333 | { | |
334 | struct gid_cache_context *ctx = *context; | |
335 | struct mlx4_ib_dev *ibdev = to_mdev(device); | |
336 | struct mlx4_ib_iboe *iboe = &ibdev->iboe; | |
337 | struct mlx4_port_gid_table *port_gid_table; | |
338 | int ret = 0; | |
339 | int hw_update = 0; | |
340 | struct gid_entry *gids = NULL; | |
341 | ||
342 | if (!rdma_cap_roce_gid_table(device, port_num)) | |
343 | return -EINVAL; | |
344 | ||
345 | if (port_num > MLX4_MAX_PORTS) | |
346 | return -EINVAL; | |
347 | ||
348 | port_gid_table = &iboe->gids[port_num - 1]; | |
349 | spin_lock_bh(&iboe->lock); | |
350 | if (ctx) { | |
351 | ctx->refcount--; | |
352 | if (!ctx->refcount) { | |
353 | unsigned int real_index = ctx->real_index; | |
354 | ||
355 | memcpy(&port_gid_table->gids[real_index].gid, &zgid, sizeof(zgid)); | |
356 | kfree(port_gid_table->gids[real_index].ctx); | |
357 | port_gid_table->gids[real_index].ctx = NULL; | |
358 | hw_update = 1; | |
359 | } | |
360 | } | |
361 | if (!ret && hw_update) { | |
362 | int i; | |
363 | ||
364 | gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC); | |
365 | if (!gids) { | |
366 | ret = -ENOMEM; | |
367 | } else { | |
368 | for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) | |
369 | memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid)); | |
370 | } | |
371 | } | |
372 | spin_unlock_bh(&iboe->lock); | |
373 | ||
374 | if (!ret && hw_update) { | |
375 | ret = mlx4_ib_update_gids(gids, ibdev, port_num); | |
376 | kfree(gids); | |
377 | } | |
378 | return ret; | |
379 | } | |
380 | ||
381 | int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev, | |
382 | u8 port_num, int index) | |
383 | { | |
384 | struct mlx4_ib_iboe *iboe = &ibdev->iboe; | |
385 | struct gid_cache_context *ctx = NULL; | |
386 | union ib_gid gid; | |
387 | struct mlx4_port_gid_table *port_gid_table; | |
388 | int real_index = -EINVAL; | |
389 | int i; | |
390 | int ret; | |
391 | unsigned long flags; | |
b699a859 | 392 | struct ib_gid_attr attr; |
e26be1bf MS |
393 | |
394 | if (port_num > MLX4_MAX_PORTS) | |
395 | return -EINVAL; | |
396 | ||
397 | if (mlx4_is_bonded(ibdev->dev)) | |
398 | port_num = 1; | |
399 | ||
400 | if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num)) | |
401 | return index; | |
402 | ||
b699a859 | 403 | ret = ib_get_cached_gid(&ibdev->ib_dev, port_num, index, &gid, &attr); |
e26be1bf MS |
404 | if (ret) |
405 | return ret; | |
406 | ||
b699a859 MS |
407 | if (attr.ndev) |
408 | dev_put(attr.ndev); | |
409 | ||
e26be1bf MS |
410 | if (!memcmp(&gid, &zgid, sizeof(gid))) |
411 | return -EINVAL; | |
412 | ||
413 | spin_lock_irqsave(&iboe->lock, flags); | |
414 | port_gid_table = &iboe->gids[port_num - 1]; | |
415 | ||
416 | for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) | |
b699a859 MS |
417 | if (!memcmp(&port_gid_table->gids[i].gid, &gid, sizeof(gid)) && |
418 | attr.gid_type == port_gid_table->gids[i].gid_type) { | |
e26be1bf MS |
419 | ctx = port_gid_table->gids[i].ctx; |
420 | break; | |
421 | } | |
422 | if (ctx) | |
423 | real_index = ctx->real_index; | |
424 | spin_unlock_irqrestore(&iboe->lock, flags); | |
425 | return real_index; | |
426 | } | |
427 | ||
225c7b1f | 428 | static int mlx4_ib_query_device(struct ib_device *ibdev, |
2528e33e MB |
429 | struct ib_device_attr *props, |
430 | struct ib_udata *uhw) | |
225c7b1f RD |
431 | { |
432 | struct mlx4_ib_dev *dev = to_mdev(ibdev); | |
433 | struct ib_smp *in_mad = NULL; | |
434 | struct ib_smp *out_mad = NULL; | |
46d0703f | 435 | int err; |
3dec4878 | 436 | int have_ib_ports; |
4b664c43 MB |
437 | struct mlx4_uverbs_ex_query_device cmd; |
438 | struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0}; | |
439 | struct mlx4_clock_params clock_params; | |
225c7b1f | 440 | |
4b664c43 MB |
441 | if (uhw->inlen) { |
442 | if (uhw->inlen < sizeof(cmd)) | |
443 | return -EINVAL; | |
444 | ||
445 | err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd)); | |
446 | if (err) | |
447 | return err; | |
448 | ||
449 | if (cmd.comp_mask) | |
450 | return -EINVAL; | |
451 | ||
452 | if (cmd.reserved) | |
453 | return -EINVAL; | |
454 | } | |
2528e33e | 455 | |
4b664c43 MB |
456 | resp.response_length = offsetof(typeof(resp), response_length) + |
457 | sizeof(resp.response_length); | |
225c7b1f RD |
458 | in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); |
459 | out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); | |
46d0703f | 460 | err = -ENOMEM; |
225c7b1f RD |
461 | if (!in_mad || !out_mad) |
462 | goto out; | |
463 | ||
464 | init_query_mad(in_mad); | |
465 | in_mad->attr_id = IB_SMP_ATTR_NODE_INFO; | |
466 | ||
0a9a0188 JM |
467 | err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS, |
468 | 1, NULL, NULL, in_mad, out_mad); | |
225c7b1f RD |
469 | if (err) |
470 | goto out; | |
471 | ||
472 | memset(props, 0, sizeof *props); | |
473 | ||
3dec4878 JM |
474 | have_ib_ports = num_ib_ports(dev->dev); |
475 | ||
225c7b1f RD |
476 | props->fw_ver = dev->dev->caps.fw_ver; |
477 | props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | | |
478 | IB_DEVICE_PORT_ACTIVE_EVENT | | |
479 | IB_DEVICE_SYS_IMAGE_GUID | | |
521e575b RL |
480 | IB_DEVICE_RC_RNR_NAK_GEN | |
481 | IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; | |
225c7b1f RD |
482 | if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR) |
483 | props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; | |
484 | if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR) | |
485 | props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; | |
3dec4878 | 486 | if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports) |
225c7b1f RD |
487 | props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; |
488 | if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT) | |
489 | props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE; | |
8ff095ec EC |
490 | if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) |
491 | props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; | |
50e2ec91 MS |
492 | if (dev->dev->caps.max_gso_sz && |
493 | (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) && | |
494 | (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH)) | |
b832be1e | 495 | props->device_cap_flags |= IB_DEVICE_UD_TSO; |
95d04f07 RD |
496 | if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY) |
497 | props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY; | |
498 | if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) && | |
499 | (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) && | |
500 | (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR)) | |
501 | props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; | |
0a1405da SH |
502 | if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) |
503 | props->device_cap_flags |= IB_DEVICE_XRC; | |
b425388d SM |
504 | if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW) |
505 | props->device_cap_flags |= IB_DEVICE_MEM_WINDOW; | |
506 | if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) { | |
507 | if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B) | |
508 | props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B; | |
509 | else | |
510 | props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A; | |
511 | } | |
ca920f5b BVA |
512 | if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED) |
513 | props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; | |
225c7b1f | 514 | |
070b3997 BW |
515 | props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; |
516 | ||
225c7b1f RD |
517 | props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) & |
518 | 0xffffff; | |
872bf2fb | 519 | props->vendor_part_id = dev->dev->persist->pdev->device; |
225c7b1f RD |
520 | props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32)); |
521 | memcpy(&props->sys_image_guid, out_mad->data + 4, 8); | |
522 | ||
523 | props->max_mr_size = ~0ull; | |
524 | props->page_size_cap = dev->dev->caps.page_size_cap; | |
5a0d0a61 | 525 | props->max_qp = dev->dev->quotas.qp; |
fc2d0044 | 526 | props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE; |
225c7b1f RD |
527 | props->max_sge = min(dev->dev->caps.max_sq_sg, |
528 | dev->dev->caps.max_rq_sg); | |
a5e14ba3 | 529 | props->max_sge_rd = MLX4_MAX_SGE_RD; |
5a0d0a61 | 530 | props->max_cq = dev->dev->quotas.cq; |
225c7b1f | 531 | props->max_cqe = dev->dev->caps.max_cqes; |
5a0d0a61 | 532 | props->max_mr = dev->dev->quotas.mpt; |
225c7b1f RD |
533 | props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds; |
534 | props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma; | |
535 | props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma; | |
536 | props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; | |
5a0d0a61 | 537 | props->max_srq = dev->dev->quotas.srq; |
c8681f14 | 538 | props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1; |
225c7b1f | 539 | props->max_srq_sge = dev->dev->caps.max_srq_sge; |
5a0fd094 | 540 | props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES; |
225c7b1f RD |
541 | props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay; |
542 | props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ? | |
543 | IB_ATOMIC_HCA : IB_ATOMIC_NONE; | |
47e956b2 | 544 | props->masked_atomic_cap = props->atomic_cap; |
5ae2a7a8 | 545 | props->max_pkeys = dev->dev->caps.pkey_table_len[1]; |
225c7b1f RD |
546 | props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms; |
547 | props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm; | |
548 | props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * | |
549 | props->max_mcast_grp; | |
a5bbe892 | 550 | props->max_map_per_fmr = dev->dev->caps.max_fmr_maps; |
4b664c43 MB |
551 | props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL; |
552 | props->timestamp_mask = 0xFFFFFFFFFFFFULL; | |
731e0415 | 553 | props->max_ah = INT_MAX; |
225c7b1f | 554 | |
8a7ff14d MB |
555 | if (!mlx4_is_slave(dev->dev)) |
556 | err = mlx4_get_internal_clock_params(dev->dev, &clock_params); | |
4b664c43 MB |
557 | |
558 | if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) { | |
4b664c43 | 559 | resp.response_length += sizeof(resp.hca_core_clock_offset); |
8a7ff14d MB |
560 | if (!err && !mlx4_is_slave(dev->dev)) { |
561 | resp.comp_mask |= QUERY_DEVICE_RESP_MASK_TIMESTAMP; | |
562 | resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE; | |
563 | } | |
4b664c43 MB |
564 | } |
565 | ||
566 | if (uhw->outlen) { | |
567 | err = ib_copy_to_udata(uhw, &resp, resp.response_length); | |
568 | if (err) | |
569 | goto out; | |
570 | } | |
225c7b1f RD |
571 | out: |
572 | kfree(in_mad); | |
573 | kfree(out_mad); | |
574 | ||
575 | return err; | |
576 | } | |
577 | ||
fa417f7b EC |
578 | static enum rdma_link_layer |
579 | mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num) | |
225c7b1f | 580 | { |
fa417f7b | 581 | struct mlx4_dev *dev = to_mdev(device)->dev; |
225c7b1f | 582 | |
65dab25d | 583 | return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ? |
fa417f7b EC |
584 | IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET; |
585 | } | |
225c7b1f | 586 | |
fa417f7b | 587 | static int ib_link_query_port(struct ib_device *ibdev, u8 port, |
0a9a0188 | 588 | struct ib_port_attr *props, int netw_view) |
fa417f7b | 589 | { |
a9c766bb OG |
590 | struct ib_smp *in_mad = NULL; |
591 | struct ib_smp *out_mad = NULL; | |
a5e12dff | 592 | int ext_active_speed; |
0a9a0188 | 593 | int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; |
a9c766bb OG |
594 | int err = -ENOMEM; |
595 | ||
596 | in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); | |
597 | out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); | |
598 | if (!in_mad || !out_mad) | |
599 | goto out; | |
600 | ||
601 | init_query_mad(in_mad); | |
602 | in_mad->attr_id = IB_SMP_ATTR_PORT_INFO; | |
603 | in_mad->attr_mod = cpu_to_be32(port); | |
604 | ||
0a9a0188 JM |
605 | if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view) |
606 | mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; | |
607 | ||
608 | err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, | |
a9c766bb OG |
609 | in_mad, out_mad); |
610 | if (err) | |
611 | goto out; | |
612 | ||
a5e12dff | 613 | |
225c7b1f RD |
614 | props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16)); |
615 | props->lmc = out_mad->data[34] & 0x7; | |
616 | props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18)); | |
617 | props->sm_sl = out_mad->data[36] & 0xf; | |
618 | props->state = out_mad->data[32] & 0xf; | |
619 | props->phys_state = out_mad->data[33] >> 4; | |
620 | props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20)); | |
0a9a0188 JM |
621 | if (netw_view) |
622 | props->gid_tbl_len = out_mad->data[50]; | |
623 | else | |
624 | props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port]; | |
149983af | 625 | props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz; |
5ae2a7a8 | 626 | props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port]; |
225c7b1f RD |
627 | props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46)); |
628 | props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48)); | |
629 | props->active_width = out_mad->data[31] & 0xf; | |
630 | props->active_speed = out_mad->data[35] >> 4; | |
631 | props->max_mtu = out_mad->data[41] & 0xf; | |
632 | props->active_mtu = out_mad->data[36] >> 4; | |
633 | props->subnet_timeout = out_mad->data[51] & 0x1f; | |
634 | props->max_vl_num = out_mad->data[37] >> 4; | |
635 | props->init_type_reply = out_mad->data[41] >> 4; | |
636 | ||
a5e12dff MA |
637 | /* Check if extended speeds (EDR/FDR/...) are supported */ |
638 | if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) { | |
639 | ext_active_speed = out_mad->data[62] >> 4; | |
640 | ||
641 | switch (ext_active_speed) { | |
642 | case 1: | |
2e96691c | 643 | props->active_speed = IB_SPEED_FDR; |
a5e12dff MA |
644 | break; |
645 | case 2: | |
2e96691c | 646 | props->active_speed = IB_SPEED_EDR; |
a5e12dff MA |
647 | break; |
648 | } | |
649 | } | |
650 | ||
651 | /* If reported active speed is QDR, check if is FDR-10 */ | |
2e96691c | 652 | if (props->active_speed == IB_SPEED_QDR) { |
8154c07f OG |
653 | init_query_mad(in_mad); |
654 | in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO; | |
655 | in_mad->attr_mod = cpu_to_be32(port); | |
656 | ||
0a9a0188 | 657 | err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, |
8154c07f OG |
658 | NULL, NULL, in_mad, out_mad); |
659 | if (err) | |
bf6b47de | 660 | goto out; |
8154c07f OG |
661 | |
662 | /* Checking LinkSpeedActive for FDR-10 */ | |
663 | if (out_mad->data[15] & 0x1) | |
664 | props->active_speed = IB_SPEED_FDR10; | |
a5e12dff | 665 | } |
d2ef4068 OG |
666 | |
667 | /* Avoid wrong speed value returned by FW if the IB link is down. */ | |
668 | if (props->state == IB_PORT_DOWN) | |
669 | props->active_speed = IB_SPEED_SDR; | |
670 | ||
a9c766bb OG |
671 | out: |
672 | kfree(in_mad); | |
673 | kfree(out_mad); | |
674 | return err; | |
fa417f7b EC |
675 | } |
676 | ||
677 | static u8 state_to_phys_state(enum ib_port_state state) | |
678 | { | |
679 | return state == IB_PORT_ACTIVE ? 5 : 3; | |
680 | } | |
681 | ||
682 | static int eth_link_query_port(struct ib_device *ibdev, u8 port, | |
850b7415 | 683 | struct ib_port_attr *props) |
fa417f7b | 684 | { |
a9c766bb OG |
685 | |
686 | struct mlx4_ib_dev *mdev = to_mdev(ibdev); | |
687 | struct mlx4_ib_iboe *iboe = &mdev->iboe; | |
fa417f7b EC |
688 | struct net_device *ndev; |
689 | enum ib_mtu tmp; | |
a9c766bb OG |
690 | struct mlx4_cmd_mailbox *mailbox; |
691 | int err = 0; | |
a5750090 | 692 | int is_bonded = mlx4_is_bonded(mdev->dev); |
a9c766bb OG |
693 | |
694 | mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); | |
695 | if (IS_ERR(mailbox)) | |
696 | return PTR_ERR(mailbox); | |
fa417f7b | 697 | |
a9c766bb OG |
698 | err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0, |
699 | MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, | |
700 | MLX4_CMD_WRAPPED); | |
701 | if (err) | |
702 | goto out; | |
703 | ||
6fa26208 SM |
704 | props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) || |
705 | (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ? | |
706 | IB_WIDTH_4X : IB_WIDTH_1X; | |
707 | props->active_speed = (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ? | |
708 | IB_SPEED_FDR : IB_SPEED_QDR; | |
b4a26a27 | 709 | props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_IP_BASED_GIDS; |
a9c766bb OG |
710 | props->gid_tbl_len = mdev->dev->caps.gid_table_len[port]; |
711 | props->max_msg_sz = mdev->dev->caps.max_msg_sz; | |
fa417f7b | 712 | props->pkey_tbl_len = 1; |
bcacb897 | 713 | props->max_mtu = IB_MTU_4096; |
a9c766bb | 714 | props->max_vl_num = 2; |
fa417f7b EC |
715 | props->state = IB_PORT_DOWN; |
716 | props->phys_state = state_to_phys_state(props->state); | |
717 | props->active_mtu = IB_MTU_256; | |
dba3ad2a | 718 | spin_lock_bh(&iboe->lock); |
fa417f7b | 719 | ndev = iboe->netdevs[port - 1]; |
5070cd22 MS |
720 | if (ndev && is_bonded) { |
721 | rcu_read_lock(); /* required to get upper dev */ | |
722 | ndev = netdev_master_upper_dev_get_rcu(ndev); | |
723 | rcu_read_unlock(); | |
724 | } | |
fa417f7b | 725 | if (!ndev) |
a9c766bb | 726 | goto out_unlock; |
fa417f7b EC |
727 | |
728 | tmp = iboe_get_mtu(ndev->mtu); | |
729 | props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256; | |
730 | ||
21d60609 | 731 | props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ? |
fa417f7b EC |
732 | IB_PORT_ACTIVE : IB_PORT_DOWN; |
733 | props->phys_state = state_to_phys_state(props->state); | |
a9c766bb | 734 | out_unlock: |
dba3ad2a | 735 | spin_unlock_bh(&iboe->lock); |
a9c766bb OG |
736 | out: |
737 | mlx4_free_cmd_mailbox(mdev->dev, mailbox); | |
738 | return err; | |
fa417f7b EC |
739 | } |
740 | ||
0a9a0188 JM |
741 | int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port, |
742 | struct ib_port_attr *props, int netw_view) | |
fa417f7b | 743 | { |
a9c766bb | 744 | int err; |
fa417f7b | 745 | |
c4550c63 | 746 | /* props being zeroed by the caller, avoid zeroing it here */ |
fa417f7b | 747 | |
fa417f7b | 748 | err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ? |
0a9a0188 | 749 | ib_link_query_port(ibdev, port, props, netw_view) : |
850b7415 | 750 | eth_link_query_port(ibdev, port, props); |
225c7b1f RD |
751 | |
752 | return err; | |
753 | } | |
754 | ||
0a9a0188 JM |
755 | static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port, |
756 | struct ib_port_attr *props) | |
757 | { | |
758 | /* returns host view */ | |
759 | return __mlx4_ib_query_port(ibdev, port, props, 0); | |
760 | } | |
761 | ||
a0c64a17 JM |
762 | int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index, |
763 | union ib_gid *gid, int netw_view) | |
225c7b1f RD |
764 | { |
765 | struct ib_smp *in_mad = NULL; | |
766 | struct ib_smp *out_mad = NULL; | |
767 | int err = -ENOMEM; | |
a0c64a17 JM |
768 | struct mlx4_ib_dev *dev = to_mdev(ibdev); |
769 | int clear = 0; | |
770 | int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; | |
225c7b1f RD |
771 | |
772 | in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); | |
773 | out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); | |
774 | if (!in_mad || !out_mad) | |
775 | goto out; | |
776 | ||
777 | init_query_mad(in_mad); | |
778 | in_mad->attr_id = IB_SMP_ATTR_PORT_INFO; | |
779 | in_mad->attr_mod = cpu_to_be32(port); | |
780 | ||
a0c64a17 JM |
781 | if (mlx4_is_mfunc(dev->dev) && netw_view) |
782 | mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; | |
783 | ||
784 | err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad); | |
225c7b1f RD |
785 | if (err) |
786 | goto out; | |
787 | ||
788 | memcpy(gid->raw, out_mad->data + 8, 8); | |
789 | ||
a0c64a17 JM |
790 | if (mlx4_is_mfunc(dev->dev) && !netw_view) { |
791 | if (index) { | |
792 | /* For any index > 0, return the null guid */ | |
793 | err = 0; | |
794 | clear = 1; | |
795 | goto out; | |
796 | } | |
797 | } | |
798 | ||
225c7b1f RD |
799 | init_query_mad(in_mad); |
800 | in_mad->attr_id = IB_SMP_ATTR_GUID_INFO; | |
801 | in_mad->attr_mod = cpu_to_be32(index / 8); | |
802 | ||
a0c64a17 | 803 | err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, |
0a9a0188 | 804 | NULL, NULL, in_mad, out_mad); |
225c7b1f RD |
805 | if (err) |
806 | goto out; | |
807 | ||
808 | memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8); | |
809 | ||
810 | out: | |
a0c64a17 JM |
811 | if (clear) |
812 | memset(gid->raw + 8, 0, 8); | |
225c7b1f RD |
813 | kfree(in_mad); |
814 | kfree(out_mad); | |
815 | return err; | |
816 | } | |
817 | ||
fa417f7b EC |
818 | static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index, |
819 | union ib_gid *gid) | |
820 | { | |
5070cd22 MS |
821 | int ret; |
822 | ||
823 | if (rdma_protocol_ib(ibdev, port)) | |
a0c64a17 | 824 | return __mlx4_ib_query_gid(ibdev, port, index, gid, 0); |
5070cd22 MS |
825 | |
826 | if (!rdma_protocol_roce(ibdev, port)) | |
827 | return -ENODEV; | |
828 | ||
829 | if (!rdma_cap_roce_gid_table(ibdev, port)) | |
830 | return -ENODEV; | |
831 | ||
55ee3ab2 | 832 | ret = ib_get_cached_gid(ibdev, port, index, gid, NULL); |
5070cd22 MS |
833 | if (ret == -EAGAIN) { |
834 | memcpy(gid, &zgid, sizeof(*gid)); | |
835 | return 0; | |
836 | } | |
837 | ||
838 | return ret; | |
fa417f7b EC |
839 | } |
840 | ||
fd10ed8e JM |
841 | static int mlx4_ib_query_sl2vl(struct ib_device *ibdev, u8 port, u64 *sl2vl_tbl) |
842 | { | |
843 | union sl2vl_tbl_to_u64 sl2vl64; | |
844 | struct ib_smp *in_mad = NULL; | |
845 | struct ib_smp *out_mad = NULL; | |
846 | int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; | |
847 | int err = -ENOMEM; | |
848 | int jj; | |
849 | ||
850 | if (mlx4_is_slave(to_mdev(ibdev)->dev)) { | |
851 | *sl2vl_tbl = 0; | |
852 | return 0; | |
853 | } | |
854 | ||
855 | in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL); | |
856 | out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL); | |
857 | if (!in_mad || !out_mad) | |
858 | goto out; | |
859 | ||
860 | init_query_mad(in_mad); | |
861 | in_mad->attr_id = IB_SMP_ATTR_SL_TO_VL_TABLE; | |
862 | in_mad->attr_mod = 0; | |
863 | ||
864 | if (mlx4_is_mfunc(to_mdev(ibdev)->dev)) | |
865 | mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; | |
866 | ||
867 | err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, | |
868 | in_mad, out_mad); | |
869 | if (err) | |
870 | goto out; | |
871 | ||
872 | for (jj = 0; jj < 8; jj++) | |
873 | sl2vl64.sl8[jj] = ((struct ib_smp *)out_mad)->data[jj]; | |
874 | *sl2vl_tbl = sl2vl64.sl64; | |
875 | ||
876 | out: | |
877 | kfree(in_mad); | |
878 | kfree(out_mad); | |
879 | return err; | |
880 | } | |
881 | ||
882 | static void mlx4_init_sl2vl_tbl(struct mlx4_ib_dev *mdev) | |
883 | { | |
884 | u64 sl2vl; | |
885 | int i; | |
886 | int err; | |
887 | ||
888 | for (i = 1; i <= mdev->dev->caps.num_ports; i++) { | |
889 | if (mdev->dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) | |
890 | continue; | |
891 | err = mlx4_ib_query_sl2vl(&mdev->ib_dev, i, &sl2vl); | |
892 | if (err) { | |
893 | pr_err("Unable to get default sl to vl mapping for port %d. Using all zeroes (%d)\n", | |
894 | i, err); | |
895 | sl2vl = 0; | |
896 | } | |
897 | atomic64_set(&mdev->sl2vl[i - 1], sl2vl); | |
898 | } | |
899 | } | |
900 | ||
0a9a0188 JM |
901 | int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, |
902 | u16 *pkey, int netw_view) | |
225c7b1f RD |
903 | { |
904 | struct ib_smp *in_mad = NULL; | |
905 | struct ib_smp *out_mad = NULL; | |
0a9a0188 | 906 | int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; |
225c7b1f RD |
907 | int err = -ENOMEM; |
908 | ||
909 | in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); | |
910 | out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); | |
911 | if (!in_mad || !out_mad) | |
912 | goto out; | |
913 | ||
914 | init_query_mad(in_mad); | |
915 | in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE; | |
916 | in_mad->attr_mod = cpu_to_be32(index / 32); | |
917 | ||
0a9a0188 JM |
918 | if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view) |
919 | mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; | |
920 | ||
921 | err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, | |
922 | in_mad, out_mad); | |
225c7b1f RD |
923 | if (err) |
924 | goto out; | |
925 | ||
926 | *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]); | |
927 | ||
928 | out: | |
929 | kfree(in_mad); | |
930 | kfree(out_mad); | |
931 | return err; | |
932 | } | |
933 | ||
0a9a0188 JM |
934 | static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey) |
935 | { | |
936 | return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0); | |
937 | } | |
938 | ||
225c7b1f RD |
939 | static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask, |
940 | struct ib_device_modify *props) | |
941 | { | |
d0d68b86 | 942 | struct mlx4_cmd_mailbox *mailbox; |
df7fba66 | 943 | unsigned long flags; |
d0d68b86 | 944 | |
225c7b1f RD |
945 | if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) |
946 | return -EOPNOTSUPP; | |
947 | ||
d0d68b86 JM |
948 | if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) |
949 | return 0; | |
950 | ||
992e8e6e JM |
951 | if (mlx4_is_slave(to_mdev(ibdev)->dev)) |
952 | return -EOPNOTSUPP; | |
953 | ||
df7fba66 | 954 | spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags); |
bd99fdea | 955 | memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); |
df7fba66 | 956 | spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags); |
d0d68b86 JM |
957 | |
958 | /* | |
959 | * If possible, pass node desc to FW, so it can generate | |
960 | * a 144 trap. If cmd fails, just ignore. | |
961 | */ | |
962 | mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev); | |
963 | if (IS_ERR(mailbox)) | |
964 | return 0; | |
965 | ||
bd99fdea | 966 | memcpy(mailbox->buf, props->node_desc, IB_DEVICE_NODE_DESC_MAX); |
d0d68b86 | 967 | mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0, |
992e8e6e | 968 | MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
d0d68b86 JM |
969 | |
970 | mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox); | |
225c7b1f RD |
971 | |
972 | return 0; | |
973 | } | |
974 | ||
61565013 JM |
975 | static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols, |
976 | u32 cap_mask) | |
225c7b1f RD |
977 | { |
978 | struct mlx4_cmd_mailbox *mailbox; | |
979 | int err; | |
980 | ||
981 | mailbox = mlx4_alloc_cmd_mailbox(dev->dev); | |
982 | if (IS_ERR(mailbox)) | |
983 | return PTR_ERR(mailbox); | |
984 | ||
5ae2a7a8 RD |
985 | if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { |
986 | *(u8 *) mailbox->buf = !!reset_qkey_viols << 6; | |
987 | ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask); | |
988 | } else { | |
989 | ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols; | |
990 | ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask); | |
991 | } | |
225c7b1f | 992 | |
a130b590 IS |
993 | err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE, |
994 | MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, | |
995 | MLX4_CMD_WRAPPED); | |
225c7b1f RD |
996 | |
997 | mlx4_free_cmd_mailbox(dev->dev, mailbox); | |
998 | return err; | |
999 | } | |
1000 | ||
1001 | static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, | |
1002 | struct ib_port_modify *props) | |
1003 | { | |
61565013 JM |
1004 | struct mlx4_ib_dev *mdev = to_mdev(ibdev); |
1005 | u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH; | |
225c7b1f RD |
1006 | struct ib_port_attr attr; |
1007 | u32 cap_mask; | |
1008 | int err; | |
1009 | ||
61565013 JM |
1010 | /* return OK if this is RoCE. CM calls ib_modify_port() regardless |
1011 | * of whether port link layer is ETH or IB. For ETH ports, qkey | |
1012 | * violations and port capabilities are not meaningful. | |
1013 | */ | |
1014 | if (is_eth) | |
1015 | return 0; | |
1016 | ||
1017 | mutex_lock(&mdev->cap_mask_mutex); | |
225c7b1f | 1018 | |
c4550c63 | 1019 | err = ib_query_port(ibdev, port, &attr); |
225c7b1f RD |
1020 | if (err) |
1021 | goto out; | |
1022 | ||
1023 | cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) & | |
1024 | ~props->clr_port_cap_mask; | |
1025 | ||
61565013 JM |
1026 | err = mlx4_ib_SET_PORT(mdev, port, |
1027 | !!(mask & IB_PORT_RESET_QKEY_CNTR), | |
1028 | cap_mask); | |
225c7b1f RD |
1029 | |
1030 | out: | |
1031 | mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex); | |
1032 | return err; | |
1033 | } | |
1034 | ||
1035 | static struct ib_ucontext *mlx4_ib_alloc_ucontext(struct ib_device *ibdev, | |
1036 | struct ib_udata *udata) | |
1037 | { | |
1038 | struct mlx4_ib_dev *dev = to_mdev(ibdev); | |
1039 | struct mlx4_ib_ucontext *context; | |
08ff3235 | 1040 | struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3; |
225c7b1f RD |
1041 | struct mlx4_ib_alloc_ucontext_resp resp; |
1042 | int err; | |
1043 | ||
3b4a8cd5 JM |
1044 | if (!dev->ib_active) |
1045 | return ERR_PTR(-EAGAIN); | |
1046 | ||
08ff3235 OG |
1047 | if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) { |
1048 | resp_v3.qp_tab_size = dev->dev->caps.num_qps; | |
1049 | resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size; | |
1050 | resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page; | |
1051 | } else { | |
1052 | resp.dev_caps = dev->dev->caps.userspace_caps; | |
1053 | resp.qp_tab_size = dev->dev->caps.num_qps; | |
1054 | resp.bf_reg_size = dev->dev->caps.bf_reg_size; | |
1055 | resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page; | |
1056 | resp.cqe_size = dev->dev->caps.cqe_size; | |
1057 | } | |
225c7b1f | 1058 | |
ae184dde | 1059 | context = kzalloc(sizeof(*context), GFP_KERNEL); |
225c7b1f RD |
1060 | if (!context) |
1061 | return ERR_PTR(-ENOMEM); | |
1062 | ||
1063 | err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar); | |
1064 | if (err) { | |
1065 | kfree(context); | |
1066 | return ERR_PTR(err); | |
1067 | } | |
1068 | ||
1069 | INIT_LIST_HEAD(&context->db_page_list); | |
1070 | mutex_init(&context->db_page_mutex); | |
1071 | ||
08ff3235 OG |
1072 | if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) |
1073 | err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3)); | |
1074 | else | |
1075 | err = ib_copy_to_udata(udata, &resp, sizeof(resp)); | |
1076 | ||
225c7b1f RD |
1077 | if (err) { |
1078 | mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar); | |
1079 | kfree(context); | |
1080 | return ERR_PTR(-EFAULT); | |
1081 | } | |
1082 | ||
1083 | return &context->ibucontext; | |
1084 | } | |
1085 | ||
1086 | static int mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) | |
1087 | { | |
1088 | struct mlx4_ib_ucontext *context = to_mucontext(ibcontext); | |
1089 | ||
1090 | mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar); | |
1091 | kfree(context); | |
1092 | ||
1093 | return 0; | |
1094 | } | |
1095 | ||
ae184dde YH |
1096 | static void mlx4_ib_vma_open(struct vm_area_struct *area) |
1097 | { | |
1098 | /* vma_open is called when a new VMA is created on top of our VMA. | |
1099 | * This is done through either mremap flow or split_vma (usually due | |
1100 | * to mlock, madvise, munmap, etc.). We do not support a clone of the | |
1101 | * vma, as this VMA is strongly hardware related. Therefore we set the | |
1102 | * vm_ops of the newly created/cloned VMA to NULL, to prevent it from | |
1103 | * calling us again and trying to do incorrect actions. We assume that | |
1104 | * the original vma size is exactly a single page that there will be no | |
1105 | * "splitting" operations on. | |
1106 | */ | |
1107 | area->vm_ops = NULL; | |
1108 | } | |
1109 | ||
1110 | static void mlx4_ib_vma_close(struct vm_area_struct *area) | |
1111 | { | |
1112 | struct mlx4_ib_vma_private_data *mlx4_ib_vma_priv_data; | |
1113 | ||
1114 | /* It's guaranteed that all VMAs opened on a FD are closed before the | |
1115 | * file itself is closed, therefore no sync is needed with the regular | |
1116 | * closing flow. (e.g. mlx4_ib_dealloc_ucontext) However need a sync | |
1117 | * with accessing the vma as part of mlx4_ib_disassociate_ucontext. | |
1118 | * The close operation is usually called under mm->mmap_sem except when | |
1119 | * process is exiting. The exiting case is handled explicitly as part | |
1120 | * of mlx4_ib_disassociate_ucontext. | |
1121 | */ | |
1122 | mlx4_ib_vma_priv_data = (struct mlx4_ib_vma_private_data *) | |
1123 | area->vm_private_data; | |
1124 | ||
1125 | /* set the vma context pointer to null in the mlx4_ib driver's private | |
1126 | * data to protect against a race condition in mlx4_ib_dissassociate_ucontext(). | |
1127 | */ | |
1128 | mlx4_ib_vma_priv_data->vma = NULL; | |
1129 | } | |
1130 | ||
1131 | static const struct vm_operations_struct mlx4_ib_vm_ops = { | |
1132 | .open = mlx4_ib_vma_open, | |
1133 | .close = mlx4_ib_vma_close | |
1134 | }; | |
1135 | ||
1136 | static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) | |
1137 | { | |
1138 | int i; | |
1139 | int ret = 0; | |
1140 | struct vm_area_struct *vma; | |
1141 | struct mlx4_ib_ucontext *context = to_mucontext(ibcontext); | |
1142 | struct task_struct *owning_process = NULL; | |
1143 | struct mm_struct *owning_mm = NULL; | |
1144 | ||
1145 | owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID); | |
1146 | if (!owning_process) | |
1147 | return; | |
1148 | ||
1149 | owning_mm = get_task_mm(owning_process); | |
1150 | if (!owning_mm) { | |
1151 | pr_info("no mm, disassociate ucontext is pending task termination\n"); | |
1152 | while (1) { | |
1153 | /* make sure that task is dead before returning, it may | |
1154 | * prevent a rare case of module down in parallel to a | |
1155 | * call to mlx4_ib_vma_close. | |
1156 | */ | |
1157 | put_task_struct(owning_process); | |
98e77d9f | 1158 | usleep_range(1000, 2000); |
ae184dde YH |
1159 | owning_process = get_pid_task(ibcontext->tgid, |
1160 | PIDTYPE_PID); | |
1161 | if (!owning_process || | |
1162 | owning_process->state == TASK_DEAD) { | |
1163 | pr_info("disassociate ucontext done, task was terminated\n"); | |
1164 | /* in case task was dead need to release the task struct */ | |
1165 | if (owning_process) | |
1166 | put_task_struct(owning_process); | |
1167 | return; | |
1168 | } | |
1169 | } | |
1170 | } | |
1171 | ||
1172 | /* need to protect from a race on closing the vma as part of | |
1173 | * mlx4_ib_vma_close(). | |
1174 | */ | |
22c3653d | 1175 | down_write(&owning_mm->mmap_sem); |
ae184dde YH |
1176 | for (i = 0; i < HW_BAR_COUNT; i++) { |
1177 | vma = context->hw_bar_info[i].vma; | |
1178 | if (!vma) | |
1179 | continue; | |
1180 | ||
1181 | ret = zap_vma_ptes(context->hw_bar_info[i].vma, | |
1182 | context->hw_bar_info[i].vma->vm_start, | |
1183 | PAGE_SIZE); | |
1184 | if (ret) { | |
1185 | pr_err("Error: zap_vma_ptes failed for index=%d, ret=%d\n", i, ret); | |
1186 | BUG_ON(1); | |
1187 | } | |
1188 | ||
ca37a664 MG |
1189 | context->hw_bar_info[i].vma->vm_flags &= |
1190 | ~(VM_SHARED | VM_MAYSHARE); | |
ae184dde YH |
1191 | /* context going to be destroyed, should not access ops any more */ |
1192 | context->hw_bar_info[i].vma->vm_ops = NULL; | |
1193 | } | |
1194 | ||
22c3653d | 1195 | up_write(&owning_mm->mmap_sem); |
ae184dde YH |
1196 | mmput(owning_mm); |
1197 | put_task_struct(owning_process); | |
1198 | } | |
1199 | ||
1200 | static void mlx4_ib_set_vma_data(struct vm_area_struct *vma, | |
1201 | struct mlx4_ib_vma_private_data *vma_private_data) | |
1202 | { | |
1203 | vma_private_data->vma = vma; | |
1204 | vma->vm_private_data = vma_private_data; | |
1205 | vma->vm_ops = &mlx4_ib_vm_ops; | |
1206 | } | |
1207 | ||
225c7b1f RD |
1208 | static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma) |
1209 | { | |
1210 | struct mlx4_ib_dev *dev = to_mdev(context->device); | |
ae184dde | 1211 | struct mlx4_ib_ucontext *mucontext = to_mucontext(context); |
225c7b1f RD |
1212 | |
1213 | if (vma->vm_end - vma->vm_start != PAGE_SIZE) | |
1214 | return -EINVAL; | |
1215 | ||
1216 | if (vma->vm_pgoff == 0) { | |
ae184dde YH |
1217 | /* We prevent double mmaping on same context */ |
1218 | if (mucontext->hw_bar_info[HW_BAR_DB].vma) | |
1219 | return -EINVAL; | |
1220 | ||
225c7b1f RD |
1221 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
1222 | ||
1223 | if (io_remap_pfn_range(vma, vma->vm_start, | |
1224 | to_mucontext(context)->uar.pfn, | |
1225 | PAGE_SIZE, vma->vm_page_prot)) | |
1226 | return -EAGAIN; | |
ae184dde YH |
1227 | |
1228 | mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_DB]); | |
1229 | ||
225c7b1f | 1230 | } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) { |
ae184dde YH |
1231 | /* We prevent double mmaping on same context */ |
1232 | if (mucontext->hw_bar_info[HW_BAR_BF].vma) | |
1233 | return -EINVAL; | |
1234 | ||
e1d60ec6 | 1235 | vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); |
225c7b1f RD |
1236 | |
1237 | if (io_remap_pfn_range(vma, vma->vm_start, | |
1238 | to_mucontext(context)->uar.pfn + | |
1239 | dev->dev->caps.num_uars, | |
1240 | PAGE_SIZE, vma->vm_page_prot)) | |
1241 | return -EAGAIN; | |
ae184dde YH |
1242 | |
1243 | mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_BF]); | |
1244 | ||
52033cfb MB |
1245 | } else if (vma->vm_pgoff == 3) { |
1246 | struct mlx4_clock_params params; | |
ae184dde YH |
1247 | int ret; |
1248 | ||
1249 | /* We prevent double mmaping on same context */ | |
1250 | if (mucontext->hw_bar_info[HW_BAR_CLOCK].vma) | |
1251 | return -EINVAL; | |
1252 | ||
1253 | ret = mlx4_get_internal_clock_params(dev->dev, ¶ms); | |
52033cfb MB |
1254 | |
1255 | if (ret) | |
1256 | return ret; | |
1257 | ||
1258 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | |
1259 | if (io_remap_pfn_range(vma, vma->vm_start, | |
1260 | (pci_resource_start(dev->dev->persist->pdev, | |
1261 | params.bar) + | |
1262 | params.offset) | |
1263 | >> PAGE_SHIFT, | |
1264 | PAGE_SIZE, vma->vm_page_prot)) | |
1265 | return -EAGAIN; | |
ae184dde YH |
1266 | |
1267 | mlx4_ib_set_vma_data(vma, | |
1268 | &mucontext->hw_bar_info[HW_BAR_CLOCK]); | |
52033cfb | 1269 | } else { |
225c7b1f | 1270 | return -EINVAL; |
52033cfb | 1271 | } |
225c7b1f RD |
1272 | |
1273 | return 0; | |
1274 | } | |
1275 | ||
1276 | static struct ib_pd *mlx4_ib_alloc_pd(struct ib_device *ibdev, | |
1277 | struct ib_ucontext *context, | |
1278 | struct ib_udata *udata) | |
1279 | { | |
1280 | struct mlx4_ib_pd *pd; | |
1281 | int err; | |
1282 | ||
1283 | pd = kmalloc(sizeof *pd, GFP_KERNEL); | |
1284 | if (!pd) | |
1285 | return ERR_PTR(-ENOMEM); | |
1286 | ||
1287 | err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn); | |
1288 | if (err) { | |
1289 | kfree(pd); | |
1290 | return ERR_PTR(err); | |
1291 | } | |
1292 | ||
1293 | if (context) | |
1294 | if (ib_copy_to_udata(udata, &pd->pdn, sizeof (__u32))) { | |
1295 | mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn); | |
1296 | kfree(pd); | |
1297 | return ERR_PTR(-EFAULT); | |
1298 | } | |
1299 | ||
1300 | return &pd->ibpd; | |
1301 | } | |
1302 | ||
1303 | static int mlx4_ib_dealloc_pd(struct ib_pd *pd) | |
1304 | { | |
1305 | mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn); | |
1306 | kfree(pd); | |
1307 | ||
1308 | return 0; | |
1309 | } | |
1310 | ||
012a8ff5 SH |
1311 | static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev, |
1312 | struct ib_ucontext *context, | |
1313 | struct ib_udata *udata) | |
1314 | { | |
1315 | struct mlx4_ib_xrcd *xrcd; | |
8e37210b | 1316 | struct ib_cq_init_attr cq_attr = {}; |
012a8ff5 SH |
1317 | int err; |
1318 | ||
1319 | if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)) | |
1320 | return ERR_PTR(-ENOSYS); | |
1321 | ||
1322 | xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL); | |
1323 | if (!xrcd) | |
1324 | return ERR_PTR(-ENOMEM); | |
1325 | ||
1326 | err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn); | |
1327 | if (err) | |
1328 | goto err1; | |
1329 | ||
ed082d36 | 1330 | xrcd->pd = ib_alloc_pd(ibdev, 0); |
012a8ff5 SH |
1331 | if (IS_ERR(xrcd->pd)) { |
1332 | err = PTR_ERR(xrcd->pd); | |
1333 | goto err2; | |
1334 | } | |
1335 | ||
8e37210b MB |
1336 | cq_attr.cqe = 1; |
1337 | xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, &cq_attr); | |
012a8ff5 SH |
1338 | if (IS_ERR(xrcd->cq)) { |
1339 | err = PTR_ERR(xrcd->cq); | |
1340 | goto err3; | |
1341 | } | |
1342 | ||
1343 | return &xrcd->ibxrcd; | |
1344 | ||
1345 | err3: | |
1346 | ib_dealloc_pd(xrcd->pd); | |
1347 | err2: | |
1348 | mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn); | |
1349 | err1: | |
1350 | kfree(xrcd); | |
1351 | return ERR_PTR(err); | |
1352 | } | |
1353 | ||
1354 | static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd) | |
1355 | { | |
1356 | ib_destroy_cq(to_mxrcd(xrcd)->cq); | |
1357 | ib_dealloc_pd(to_mxrcd(xrcd)->pd); | |
1358 | mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn); | |
1359 | kfree(xrcd); | |
1360 | ||
1361 | return 0; | |
1362 | } | |
1363 | ||
fa417f7b EC |
1364 | static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid) |
1365 | { | |
1366 | struct mlx4_ib_qp *mqp = to_mqp(ibqp); | |
1367 | struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); | |
1368 | struct mlx4_ib_gid_entry *ge; | |
1369 | ||
1370 | ge = kzalloc(sizeof *ge, GFP_KERNEL); | |
1371 | if (!ge) | |
1372 | return -ENOMEM; | |
1373 | ||
1374 | ge->gid = *gid; | |
1375 | if (mlx4_ib_add_mc(mdev, mqp, gid)) { | |
1376 | ge->port = mqp->port; | |
1377 | ge->added = 1; | |
1378 | } | |
1379 | ||
1380 | mutex_lock(&mqp->mutex); | |
1381 | list_add_tail(&ge->list, &mqp->gid_list); | |
1382 | mutex_unlock(&mqp->mutex); | |
1383 | ||
1384 | return 0; | |
1385 | } | |
1386 | ||
3ba8e31d EBE |
1387 | static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev, |
1388 | struct mlx4_ib_counters *ctr_table) | |
1389 | { | |
1390 | struct counter_index *counter, *tmp_count; | |
1391 | ||
1392 | mutex_lock(&ctr_table->mutex); | |
1393 | list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list, | |
1394 | list) { | |
1395 | if (counter->allocated) | |
1396 | mlx4_counter_free(ibdev->dev, counter->index); | |
1397 | list_del(&counter->list); | |
1398 | kfree(counter); | |
1399 | } | |
1400 | mutex_unlock(&ctr_table->mutex); | |
1401 | } | |
1402 | ||
fa417f7b EC |
1403 | int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, |
1404 | union ib_gid *gid) | |
1405 | { | |
fa417f7b EC |
1406 | struct net_device *ndev; |
1407 | int ret = 0; | |
1408 | ||
1409 | if (!mqp->port) | |
1410 | return 0; | |
1411 | ||
dba3ad2a | 1412 | spin_lock_bh(&mdev->iboe.lock); |
fa417f7b EC |
1413 | ndev = mdev->iboe.netdevs[mqp->port - 1]; |
1414 | if (ndev) | |
1415 | dev_hold(ndev); | |
dba3ad2a | 1416 | spin_unlock_bh(&mdev->iboe.lock); |
fa417f7b EC |
1417 | |
1418 | if (ndev) { | |
fa417f7b | 1419 | ret = 1; |
fa417f7b EC |
1420 | dev_put(ndev); |
1421 | } | |
1422 | ||
1423 | return ret; | |
1424 | } | |
1425 | ||
0ff1fb65 HHZ |
1426 | struct mlx4_ib_steering { |
1427 | struct list_head list; | |
146d6e19 | 1428 | struct mlx4_flow_reg_id reg_id; |
0ff1fb65 HHZ |
1429 | union ib_gid gid; |
1430 | }; | |
1431 | ||
1f02a09c MG |
1432 | #define LAST_ETH_FIELD vlan_tag |
1433 | #define LAST_IB_FIELD sl | |
1434 | #define LAST_IPV4_FIELD dst_ip | |
1435 | #define LAST_TCP_UDP_FIELD src_port | |
1436 | ||
1437 | /* Field is the last supported field */ | |
1438 | #define FIELDS_NOT_SUPPORTED(filter, field)\ | |
1439 | memchr_inv((void *)&filter.field +\ | |
1440 | sizeof(filter.field), 0,\ | |
1441 | sizeof(filter) -\ | |
1442 | offsetof(typeof(filter), field) -\ | |
1443 | sizeof(filter.field)) | |
1444 | ||
f77c0162 | 1445 | static int parse_flow_attr(struct mlx4_dev *dev, |
a37a1a42 | 1446 | u32 qp_num, |
f77c0162 HHZ |
1447 | union ib_flow_spec *ib_spec, |
1448 | struct _rule_hw *mlx4_spec) | |
1449 | { | |
1450 | enum mlx4_net_trans_rule_id type; | |
1451 | ||
1452 | switch (ib_spec->type) { | |
1453 | case IB_FLOW_SPEC_ETH: | |
1f02a09c MG |
1454 | if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) |
1455 | return -ENOTSUPP; | |
1456 | ||
f77c0162 HHZ |
1457 | type = MLX4_NET_TRANS_RULE_ID_ETH; |
1458 | memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac, | |
1459 | ETH_ALEN); | |
1460 | memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac, | |
1461 | ETH_ALEN); | |
1462 | mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag; | |
1463 | mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag; | |
1464 | break; | |
a37a1a42 | 1465 | case IB_FLOW_SPEC_IB: |
1f02a09c MG |
1466 | if (FIELDS_NOT_SUPPORTED(ib_spec->ib.mask, LAST_IB_FIELD)) |
1467 | return -ENOTSUPP; | |
1468 | ||
a37a1a42 MB |
1469 | type = MLX4_NET_TRANS_RULE_ID_IB; |
1470 | mlx4_spec->ib.l3_qpn = | |
1471 | cpu_to_be32(qp_num); | |
1472 | mlx4_spec->ib.qpn_mask = | |
1473 | cpu_to_be32(MLX4_IB_FLOW_QPN_MASK); | |
1474 | break; | |
1475 | ||
f77c0162 HHZ |
1476 | |
1477 | case IB_FLOW_SPEC_IPV4: | |
1f02a09c MG |
1478 | if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) |
1479 | return -ENOTSUPP; | |
1480 | ||
f77c0162 HHZ |
1481 | type = MLX4_NET_TRANS_RULE_ID_IPV4; |
1482 | mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip; | |
1483 | mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip; | |
1484 | mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip; | |
1485 | mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip; | |
1486 | break; | |
1487 | ||
1488 | case IB_FLOW_SPEC_TCP: | |
1489 | case IB_FLOW_SPEC_UDP: | |
1f02a09c MG |
1490 | if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, LAST_TCP_UDP_FIELD)) |
1491 | return -ENOTSUPP; | |
1492 | ||
f77c0162 HHZ |
1493 | type = ib_spec->type == IB_FLOW_SPEC_TCP ? |
1494 | MLX4_NET_TRANS_RULE_ID_TCP : | |
1495 | MLX4_NET_TRANS_RULE_ID_UDP; | |
1496 | mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port; | |
1497 | mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port; | |
1498 | mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port; | |
1499 | mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port; | |
1500 | break; | |
1501 | ||
1502 | default: | |
1503 | return -EINVAL; | |
1504 | } | |
1505 | if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 || | |
1506 | mlx4_hw_rule_sz(dev, type) < 0) | |
1507 | return -EINVAL; | |
1508 | mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type)); | |
1509 | mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2; | |
1510 | return mlx4_hw_rule_sz(dev, type); | |
1511 | } | |
1512 | ||
a37a1a42 MB |
1513 | struct default_rules { |
1514 | __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS]; | |
1515 | __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS]; | |
1516 | __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS]; | |
1517 | __u8 link_layer; | |
1518 | }; | |
1519 | static const struct default_rules default_table[] = { | |
1520 | { | |
1521 | .mandatory_fields = {IB_FLOW_SPEC_IPV4}, | |
1522 | .mandatory_not_fields = {IB_FLOW_SPEC_ETH}, | |
1523 | .rules_create_list = {IB_FLOW_SPEC_IB}, | |
1524 | .link_layer = IB_LINK_LAYER_INFINIBAND | |
1525 | } | |
1526 | }; | |
1527 | ||
1528 | static int __mlx4_ib_default_rules_match(struct ib_qp *qp, | |
1529 | struct ib_flow_attr *flow_attr) | |
1530 | { | |
1531 | int i, j, k; | |
1532 | void *ib_flow; | |
1533 | const struct default_rules *pdefault_rules = default_table; | |
1534 | u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port); | |
1535 | ||
a57f23f6 | 1536 | for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) { |
a37a1a42 MB |
1537 | __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS]; |
1538 | memset(&field_types, 0, sizeof(field_types)); | |
1539 | ||
1540 | if (link_layer != pdefault_rules->link_layer) | |
1541 | continue; | |
1542 | ||
1543 | ib_flow = flow_attr + 1; | |
1544 | /* we assume the specs are sorted */ | |
1545 | for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS && | |
1546 | j < flow_attr->num_of_specs; k++) { | |
1547 | union ib_flow_spec *current_flow = | |
1548 | (union ib_flow_spec *)ib_flow; | |
1549 | ||
1550 | /* same layer but different type */ | |
1551 | if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) == | |
1552 | (pdefault_rules->mandatory_fields[k] & | |
1553 | IB_FLOW_SPEC_LAYER_MASK)) && | |
1554 | (current_flow->type != | |
1555 | pdefault_rules->mandatory_fields[k])) | |
1556 | goto out; | |
1557 | ||
1558 | /* same layer, try match next one */ | |
1559 | if (current_flow->type == | |
1560 | pdefault_rules->mandatory_fields[k]) { | |
1561 | j++; | |
1562 | ib_flow += | |
1563 | ((union ib_flow_spec *)ib_flow)->size; | |
1564 | } | |
1565 | } | |
1566 | ||
1567 | ib_flow = flow_attr + 1; | |
1568 | for (j = 0; j < flow_attr->num_of_specs; | |
1569 | j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size) | |
1570 | for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++) | |
1571 | /* same layer and same type */ | |
1572 | if (((union ib_flow_spec *)ib_flow)->type == | |
1573 | pdefault_rules->mandatory_not_fields[k]) | |
1574 | goto out; | |
1575 | ||
1576 | return i; | |
1577 | } | |
1578 | out: | |
1579 | return -1; | |
1580 | } | |
1581 | ||
1582 | static int __mlx4_ib_create_default_rules( | |
1583 | struct mlx4_ib_dev *mdev, | |
1584 | struct ib_qp *qp, | |
1585 | const struct default_rules *pdefault_rules, | |
1586 | struct _rule_hw *mlx4_spec) { | |
1587 | int size = 0; | |
1588 | int i; | |
1589 | ||
a57f23f6 | 1590 | for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) { |
a37a1a42 MB |
1591 | int ret; |
1592 | union ib_flow_spec ib_spec; | |
1593 | switch (pdefault_rules->rules_create_list[i]) { | |
1594 | case 0: | |
1595 | /* no rule */ | |
1596 | continue; | |
1597 | case IB_FLOW_SPEC_IB: | |
1598 | ib_spec.type = IB_FLOW_SPEC_IB; | |
1599 | ib_spec.size = sizeof(struct ib_flow_spec_ib); | |
1600 | ||
1601 | break; | |
1602 | default: | |
1603 | /* invalid rule */ | |
1604 | return -EINVAL; | |
1605 | } | |
1606 | /* We must put empty rule, qpn is being ignored */ | |
1607 | ret = parse_flow_attr(mdev->dev, 0, &ib_spec, | |
1608 | mlx4_spec); | |
1609 | if (ret < 0) { | |
1610 | pr_info("invalid parsing\n"); | |
1611 | return -EINVAL; | |
1612 | } | |
1613 | ||
1614 | mlx4_spec = (void *)mlx4_spec + ret; | |
1615 | size += ret; | |
1616 | } | |
1617 | return size; | |
1618 | } | |
1619 | ||
f77c0162 HHZ |
1620 | static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr, |
1621 | int domain, | |
1622 | enum mlx4_net_trans_promisc_mode flow_type, | |
1623 | u64 *reg_id) | |
1624 | { | |
1625 | int ret, i; | |
1626 | int size = 0; | |
1627 | void *ib_flow; | |
1628 | struct mlx4_ib_dev *mdev = to_mdev(qp->device); | |
1629 | struct mlx4_cmd_mailbox *mailbox; | |
1630 | struct mlx4_net_trans_rule_hw_ctrl *ctrl; | |
a37a1a42 | 1631 | int default_flow; |
f77c0162 HHZ |
1632 | |
1633 | static const u16 __mlx4_domain[] = { | |
1634 | [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS, | |
1635 | [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL, | |
1636 | [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS, | |
1637 | [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC, | |
1638 | }; | |
1639 | ||
1640 | if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) { | |
1641 | pr_err("Invalid priority value %d\n", flow_attr->priority); | |
1642 | return -EINVAL; | |
1643 | } | |
1644 | ||
1645 | if (domain >= IB_FLOW_DOMAIN_NUM) { | |
1646 | pr_err("Invalid domain value %d\n", domain); | |
1647 | return -EINVAL; | |
1648 | } | |
1649 | ||
1650 | if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0) | |
1651 | return -EINVAL; | |
1652 | ||
1653 | mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); | |
1654 | if (IS_ERR(mailbox)) | |
1655 | return PTR_ERR(mailbox); | |
f77c0162 HHZ |
1656 | ctrl = mailbox->buf; |
1657 | ||
1658 | ctrl->prio = cpu_to_be16(__mlx4_domain[domain] | | |
1659 | flow_attr->priority); | |
1660 | ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type); | |
1661 | ctrl->port = flow_attr->port; | |
1662 | ctrl->qpn = cpu_to_be32(qp->qp_num); | |
1663 | ||
1664 | ib_flow = flow_attr + 1; | |
1665 | size += sizeof(struct mlx4_net_trans_rule_hw_ctrl); | |
a37a1a42 MB |
1666 | /* Add default flows */ |
1667 | default_flow = __mlx4_ib_default_rules_match(qp, flow_attr); | |
1668 | if (default_flow >= 0) { | |
1669 | ret = __mlx4_ib_create_default_rules( | |
1670 | mdev, qp, default_table + default_flow, | |
1671 | mailbox->buf + size); | |
1672 | if (ret < 0) { | |
1673 | mlx4_free_cmd_mailbox(mdev->dev, mailbox); | |
1674 | return -EINVAL; | |
1675 | } | |
1676 | size += ret; | |
1677 | } | |
f77c0162 | 1678 | for (i = 0; i < flow_attr->num_of_specs; i++) { |
a37a1a42 MB |
1679 | ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow, |
1680 | mailbox->buf + size); | |
f77c0162 HHZ |
1681 | if (ret < 0) { |
1682 | mlx4_free_cmd_mailbox(mdev->dev, mailbox); | |
1683 | return -EINVAL; | |
1684 | } | |
1685 | ib_flow += ((union ib_flow_spec *) ib_flow)->size; | |
1686 | size += ret; | |
1687 | } | |
1688 | ||
10b1c04e JM |
1689 | if (mlx4_is_master(mdev->dev) && flow_type == MLX4_FS_REGULAR && |
1690 | flow_attr->num_of_specs == 1) { | |
1691 | struct _rule_hw *rule_header = (struct _rule_hw *)(ctrl + 1); | |
1692 | enum ib_flow_spec_type header_spec = | |
1693 | ((union ib_flow_spec *)(flow_attr + 1))->type; | |
1694 | ||
1695 | if (header_spec == IB_FLOW_SPEC_ETH) | |
1696 | mlx4_handle_eth_header_mcast_prio(ctrl, rule_header); | |
1697 | } | |
1698 | ||
f77c0162 HHZ |
1699 | ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0, |
1700 | MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A, | |
10b1c04e | 1701 | MLX4_CMD_NATIVE); |
f77c0162 HHZ |
1702 | if (ret == -ENOMEM) |
1703 | pr_err("mcg table is full. Fail to register network rule.\n"); | |
1704 | else if (ret == -ENXIO) | |
1705 | pr_err("Device managed flow steering is disabled. Fail to register network rule.\n"); | |
1706 | else if (ret) | |
35fc7b7d | 1707 | pr_err("Invalid argument. Fail to register network rule.\n"); |
f77c0162 HHZ |
1708 | |
1709 | mlx4_free_cmd_mailbox(mdev->dev, mailbox); | |
1710 | return ret; | |
1711 | } | |
1712 | ||
1713 | static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id) | |
1714 | { | |
1715 | int err; | |
1716 | err = mlx4_cmd(dev, reg_id, 0, 0, | |
1717 | MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A, | |
10b1c04e | 1718 | MLX4_CMD_NATIVE); |
f77c0162 HHZ |
1719 | if (err) |
1720 | pr_err("Fail to detach network rule. registration id = 0x%llx\n", | |
1721 | reg_id); | |
1722 | return err; | |
1723 | } | |
1724 | ||
d2fce8a9 OG |
1725 | static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr, |
1726 | u64 *reg_id) | |
1727 | { | |
1728 | void *ib_flow; | |
1729 | union ib_flow_spec *ib_spec; | |
1730 | struct mlx4_dev *dev = to_mdev(qp->device)->dev; | |
1731 | int err = 0; | |
1732 | ||
5eff6dad OG |
1733 | if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN || |
1734 | dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) | |
d2fce8a9 OG |
1735 | return 0; /* do nothing */ |
1736 | ||
1737 | ib_flow = flow_attr + 1; | |
1738 | ib_spec = (union ib_flow_spec *)ib_flow; | |
1739 | ||
1740 | if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1) | |
1741 | return 0; /* do nothing */ | |
1742 | ||
1743 | err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac, | |
1744 | flow_attr->port, qp->qp_num, | |
1745 | MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff), | |
1746 | reg_id); | |
1747 | return err; | |
1748 | } | |
1749 | ||
0e451e88 MV |
1750 | static int mlx4_ib_add_dont_trap_rule(struct mlx4_dev *dev, |
1751 | struct ib_flow_attr *flow_attr, | |
1752 | enum mlx4_net_trans_promisc_mode *type) | |
1753 | { | |
1754 | int err = 0; | |
1755 | ||
1756 | if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER) || | |
1757 | (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) || | |
1758 | (flow_attr->num_of_specs > 1) || (flow_attr->priority != 0)) { | |
1759 | return -EOPNOTSUPP; | |
1760 | } | |
1761 | ||
1762 | if (flow_attr->num_of_specs == 0) { | |
1763 | type[0] = MLX4_FS_MC_SNIFFER; | |
1764 | type[1] = MLX4_FS_UC_SNIFFER; | |
1765 | } else { | |
1766 | union ib_flow_spec *ib_spec; | |
1767 | ||
1768 | ib_spec = (union ib_flow_spec *)(flow_attr + 1); | |
1769 | if (ib_spec->type != IB_FLOW_SPEC_ETH) | |
1770 | return -EINVAL; | |
1771 | ||
1772 | /* if all is zero than MC and UC */ | |
1773 | if (is_zero_ether_addr(ib_spec->eth.mask.dst_mac)) { | |
1774 | type[0] = MLX4_FS_MC_SNIFFER; | |
1775 | type[1] = MLX4_FS_UC_SNIFFER; | |
1776 | } else { | |
1777 | u8 mac[ETH_ALEN] = {ib_spec->eth.mask.dst_mac[0] ^ 0x01, | |
1778 | ib_spec->eth.mask.dst_mac[1], | |
1779 | ib_spec->eth.mask.dst_mac[2], | |
1780 | ib_spec->eth.mask.dst_mac[3], | |
1781 | ib_spec->eth.mask.dst_mac[4], | |
1782 | ib_spec->eth.mask.dst_mac[5]}; | |
1783 | ||
1784 | /* Above xor was only on MC bit, non empty mask is valid | |
1785 | * only if this bit is set and rest are zero. | |
1786 | */ | |
1787 | if (!is_zero_ether_addr(&mac[0])) | |
1788 | return -EINVAL; | |
1789 | ||
1790 | if (is_multicast_ether_addr(ib_spec->eth.val.dst_mac)) | |
1791 | type[0] = MLX4_FS_MC_SNIFFER; | |
1792 | else | |
1793 | type[0] = MLX4_FS_UC_SNIFFER; | |
1794 | } | |
1795 | } | |
1796 | ||
1797 | return err; | |
1798 | } | |
1799 | ||
f77c0162 HHZ |
1800 | static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp, |
1801 | struct ib_flow_attr *flow_attr, | |
1802 | int domain) | |
1803 | { | |
146d6e19 | 1804 | int err = 0, i = 0, j = 0; |
f77c0162 HHZ |
1805 | struct mlx4_ib_flow *mflow; |
1806 | enum mlx4_net_trans_promisc_mode type[2]; | |
146d6e19 MS |
1807 | struct mlx4_dev *dev = (to_mdev(qp->device))->dev; |
1808 | int is_bonded = mlx4_is_bonded(dev); | |
f77c0162 | 1809 | |
5533c18a YH |
1810 | if (flow_attr->port < 1 || flow_attr->port > qp->device->phys_port_cnt) |
1811 | return ERR_PTR(-EINVAL); | |
1812 | ||
0e451e88 MV |
1813 | if ((flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) && |
1814 | (flow_attr->type != IB_FLOW_ATTR_NORMAL)) | |
a3100a78 MV |
1815 | return ERR_PTR(-EOPNOTSUPP); |
1816 | ||
f77c0162 HHZ |
1817 | memset(type, 0, sizeof(type)); |
1818 | ||
1819 | mflow = kzalloc(sizeof(*mflow), GFP_KERNEL); | |
1820 | if (!mflow) { | |
1821 | err = -ENOMEM; | |
1822 | goto err_free; | |
1823 | } | |
1824 | ||
1825 | switch (flow_attr->type) { | |
1826 | case IB_FLOW_ATTR_NORMAL: | |
0e451e88 MV |
1827 | /* If dont trap flag (continue match) is set, under specific |
1828 | * condition traffic be replicated to given qp, | |
1829 | * without stealing it | |
1830 | */ | |
1831 | if (unlikely(flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)) { | |
1832 | err = mlx4_ib_add_dont_trap_rule(dev, | |
1833 | flow_attr, | |
1834 | type); | |
1835 | if (err) | |
1836 | goto err_free; | |
1837 | } else { | |
1838 | type[0] = MLX4_FS_REGULAR; | |
1839 | } | |
f77c0162 HHZ |
1840 | break; |
1841 | ||
1842 | case IB_FLOW_ATTR_ALL_DEFAULT: | |
1843 | type[0] = MLX4_FS_ALL_DEFAULT; | |
1844 | break; | |
1845 | ||
1846 | case IB_FLOW_ATTR_MC_DEFAULT: | |
1847 | type[0] = MLX4_FS_MC_DEFAULT; | |
1848 | break; | |
1849 | ||
1850 | case IB_FLOW_ATTR_SNIFFER: | |
0e451e88 MV |
1851 | type[0] = MLX4_FS_MIRROR_RX_PORT; |
1852 | type[1] = MLX4_FS_MIRROR_SX_PORT; | |
f77c0162 HHZ |
1853 | break; |
1854 | ||
1855 | default: | |
1856 | err = -EINVAL; | |
1857 | goto err_free; | |
1858 | } | |
1859 | ||
1860 | while (i < ARRAY_SIZE(type) && type[i]) { | |
1861 | err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i], | |
146d6e19 | 1862 | &mflow->reg_id[i].id); |
f77c0162 | 1863 | if (err) |
571e1b2c | 1864 | goto err_create_flow; |
146d6e19 | 1865 | if (is_bonded) { |
824c25c1 MS |
1866 | /* Application always sees one port so the mirror rule |
1867 | * must be on port #2 | |
1868 | */ | |
146d6e19 MS |
1869 | flow_attr->port = 2; |
1870 | err = __mlx4_ib_create_flow(qp, flow_attr, | |
1871 | domain, type[j], | |
1872 | &mflow->reg_id[j].mirror); | |
1873 | flow_attr->port = 1; | |
1874 | if (err) | |
1875 | goto err_create_flow; | |
1876 | j++; | |
1877 | } | |
1878 | ||
11562568 | 1879 | i++; |
f77c0162 HHZ |
1880 | } |
1881 | ||
d2fce8a9 | 1882 | if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) { |
146d6e19 MS |
1883 | err = mlx4_ib_tunnel_steer_add(qp, flow_attr, |
1884 | &mflow->reg_id[i].id); | |
d2fce8a9 | 1885 | if (err) |
571e1b2c | 1886 | goto err_create_flow; |
11562568 | 1887 | |
146d6e19 MS |
1888 | if (is_bonded) { |
1889 | flow_attr->port = 2; | |
1890 | err = mlx4_ib_tunnel_steer_add(qp, flow_attr, | |
1891 | &mflow->reg_id[j].mirror); | |
1892 | flow_attr->port = 1; | |
1893 | if (err) | |
1894 | goto err_create_flow; | |
1895 | j++; | |
1896 | } | |
1897 | /* function to create mirror rule */ | |
11562568 | 1898 | i++; |
d2fce8a9 OG |
1899 | } |
1900 | ||
f77c0162 HHZ |
1901 | return &mflow->ibflow; |
1902 | ||
571e1b2c OG |
1903 | err_create_flow: |
1904 | while (i) { | |
146d6e19 MS |
1905 | (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev, |
1906 | mflow->reg_id[i].id); | |
571e1b2c OG |
1907 | i--; |
1908 | } | |
146d6e19 MS |
1909 | |
1910 | while (j) { | |
1911 | (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev, | |
1912 | mflow->reg_id[j].mirror); | |
1913 | j--; | |
1914 | } | |
f77c0162 HHZ |
1915 | err_free: |
1916 | kfree(mflow); | |
1917 | return ERR_PTR(err); | |
1918 | } | |
1919 | ||
1920 | static int mlx4_ib_destroy_flow(struct ib_flow *flow_id) | |
1921 | { | |
1922 | int err, ret = 0; | |
1923 | int i = 0; | |
1924 | struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device); | |
1925 | struct mlx4_ib_flow *mflow = to_mflow(flow_id); | |
1926 | ||
146d6e19 MS |
1927 | while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) { |
1928 | err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id); | |
f77c0162 HHZ |
1929 | if (err) |
1930 | ret = err; | |
146d6e19 MS |
1931 | if (mflow->reg_id[i].mirror) { |
1932 | err = __mlx4_ib_destroy_flow(mdev->dev, | |
1933 | mflow->reg_id[i].mirror); | |
1934 | if (err) | |
1935 | ret = err; | |
1936 | } | |
f77c0162 HHZ |
1937 | i++; |
1938 | } | |
1939 | ||
1940 | kfree(mflow); | |
1941 | return ret; | |
1942 | } | |
1943 | ||
225c7b1f RD |
1944 | static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) |
1945 | { | |
fa417f7b EC |
1946 | int err; |
1947 | struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); | |
146d6e19 | 1948 | struct mlx4_dev *dev = mdev->dev; |
fa417f7b | 1949 | struct mlx4_ib_qp *mqp = to_mqp(ibqp); |
0ff1fb65 | 1950 | struct mlx4_ib_steering *ib_steering = NULL; |
e9a7faf1 | 1951 | enum mlx4_protocol prot = MLX4_PROT_IB_IPV6; |
146d6e19 | 1952 | struct mlx4_flow_reg_id reg_id; |
0ff1fb65 HHZ |
1953 | |
1954 | if (mdev->dev->caps.steering_mode == | |
1955 | MLX4_STEERING_MODE_DEVICE_MANAGED) { | |
1956 | ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL); | |
1957 | if (!ib_steering) | |
1958 | return -ENOMEM; | |
1959 | } | |
fa417f7b | 1960 | |
0ff1fb65 HHZ |
1961 | err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port, |
1962 | !!(mqp->flags & | |
1963 | MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK), | |
146d6e19 | 1964 | prot, ®_id.id); |
e9a7faf1 OG |
1965 | if (err) { |
1966 | pr_err("multicast attach op failed, err %d\n", err); | |
0ff1fb65 | 1967 | goto err_malloc; |
e9a7faf1 | 1968 | } |
fa417f7b | 1969 | |
146d6e19 MS |
1970 | reg_id.mirror = 0; |
1971 | if (mlx4_is_bonded(dev)) { | |
824c25c1 MS |
1972 | err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, |
1973 | (mqp->port == 1) ? 2 : 1, | |
146d6e19 MS |
1974 | !!(mqp->flags & |
1975 | MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK), | |
1976 | prot, ®_id.mirror); | |
1977 | if (err) | |
1978 | goto err_add; | |
1979 | } | |
1980 | ||
fa417f7b EC |
1981 | err = add_gid_entry(ibqp, gid); |
1982 | if (err) | |
1983 | goto err_add; | |
1984 | ||
0ff1fb65 HHZ |
1985 | if (ib_steering) { |
1986 | memcpy(ib_steering->gid.raw, gid->raw, 16); | |
1987 | ib_steering->reg_id = reg_id; | |
1988 | mutex_lock(&mqp->mutex); | |
1989 | list_add(&ib_steering->list, &mqp->steering_rules); | |
1990 | mutex_unlock(&mqp->mutex); | |
1991 | } | |
fa417f7b EC |
1992 | return 0; |
1993 | ||
1994 | err_add: | |
0ff1fb65 | 1995 | mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, |
146d6e19 MS |
1996 | prot, reg_id.id); |
1997 | if (reg_id.mirror) | |
1998 | mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, | |
1999 | prot, reg_id.mirror); | |
0ff1fb65 HHZ |
2000 | err_malloc: |
2001 | kfree(ib_steering); | |
2002 | ||
fa417f7b EC |
2003 | return err; |
2004 | } | |
2005 | ||
2006 | static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw) | |
2007 | { | |
2008 | struct mlx4_ib_gid_entry *ge; | |
2009 | struct mlx4_ib_gid_entry *tmp; | |
2010 | struct mlx4_ib_gid_entry *ret = NULL; | |
2011 | ||
2012 | list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { | |
2013 | if (!memcmp(raw, ge->gid.raw, 16)) { | |
2014 | ret = ge; | |
2015 | break; | |
2016 | } | |
2017 | } | |
2018 | ||
2019 | return ret; | |
225c7b1f RD |
2020 | } |
2021 | ||
2022 | static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) | |
2023 | { | |
fa417f7b EC |
2024 | int err; |
2025 | struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); | |
146d6e19 | 2026 | struct mlx4_dev *dev = mdev->dev; |
fa417f7b | 2027 | struct mlx4_ib_qp *mqp = to_mqp(ibqp); |
fa417f7b EC |
2028 | struct net_device *ndev; |
2029 | struct mlx4_ib_gid_entry *ge; | |
146d6e19 | 2030 | struct mlx4_flow_reg_id reg_id = {0, 0}; |
e9a7faf1 | 2031 | enum mlx4_protocol prot = MLX4_PROT_IB_IPV6; |
0ff1fb65 HHZ |
2032 | |
2033 | if (mdev->dev->caps.steering_mode == | |
2034 | MLX4_STEERING_MODE_DEVICE_MANAGED) { | |
2035 | struct mlx4_ib_steering *ib_steering; | |
2036 | ||
2037 | mutex_lock(&mqp->mutex); | |
2038 | list_for_each_entry(ib_steering, &mqp->steering_rules, list) { | |
2039 | if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) { | |
2040 | list_del(&ib_steering->list); | |
2041 | break; | |
2042 | } | |
2043 | } | |
2044 | mutex_unlock(&mqp->mutex); | |
2045 | if (&ib_steering->list == &mqp->steering_rules) { | |
2046 | pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n"); | |
2047 | return -EINVAL; | |
2048 | } | |
2049 | reg_id = ib_steering->reg_id; | |
2050 | kfree(ib_steering); | |
2051 | } | |
fa417f7b | 2052 | |
0ff1fb65 | 2053 | err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, |
146d6e19 | 2054 | prot, reg_id.id); |
fa417f7b EC |
2055 | if (err) |
2056 | return err; | |
2057 | ||
146d6e19 MS |
2058 | if (mlx4_is_bonded(dev)) { |
2059 | err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, | |
2060 | prot, reg_id.mirror); | |
2061 | if (err) | |
2062 | return err; | |
2063 | } | |
2064 | ||
fa417f7b EC |
2065 | mutex_lock(&mqp->mutex); |
2066 | ge = find_gid_entry(mqp, gid->raw); | |
2067 | if (ge) { | |
dba3ad2a | 2068 | spin_lock_bh(&mdev->iboe.lock); |
fa417f7b EC |
2069 | ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL; |
2070 | if (ndev) | |
2071 | dev_hold(ndev); | |
dba3ad2a | 2072 | spin_unlock_bh(&mdev->iboe.lock); |
d487ee77 | 2073 | if (ndev) |
fa417f7b | 2074 | dev_put(ndev); |
fa417f7b EC |
2075 | list_del(&ge->list); |
2076 | kfree(ge); | |
2077 | } else | |
987c8f8f | 2078 | pr_warn("could not find mgid entry\n"); |
fa417f7b EC |
2079 | |
2080 | mutex_unlock(&mqp->mutex); | |
2081 | ||
2082 | return 0; | |
225c7b1f RD |
2083 | } |
2084 | ||
2085 | static int init_node_data(struct mlx4_ib_dev *dev) | |
2086 | { | |
2087 | struct ib_smp *in_mad = NULL; | |
2088 | struct ib_smp *out_mad = NULL; | |
0a9a0188 | 2089 | int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; |
225c7b1f RD |
2090 | int err = -ENOMEM; |
2091 | ||
2092 | in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); | |
2093 | out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); | |
2094 | if (!in_mad || !out_mad) | |
2095 | goto out; | |
2096 | ||
2097 | init_query_mad(in_mad); | |
2098 | in_mad->attr_id = IB_SMP_ATTR_NODE_DESC; | |
0a9a0188 JM |
2099 | if (mlx4_is_master(dev->dev)) |
2100 | mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; | |
225c7b1f | 2101 | |
0a9a0188 | 2102 | err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad); |
225c7b1f RD |
2103 | if (err) |
2104 | goto out; | |
2105 | ||
bd99fdea | 2106 | memcpy(dev->ib_dev.node_desc, out_mad->data, IB_DEVICE_NODE_DESC_MAX); |
225c7b1f RD |
2107 | |
2108 | in_mad->attr_id = IB_SMP_ATTR_NODE_INFO; | |
2109 | ||
0a9a0188 | 2110 | err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad); |
225c7b1f RD |
2111 | if (err) |
2112 | goto out; | |
2113 | ||
992e8e6e | 2114 | dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32)); |
225c7b1f RD |
2115 | memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8); |
2116 | ||
2117 | out: | |
2118 | kfree(in_mad); | |
2119 | kfree(out_mad); | |
2120 | return err; | |
2121 | } | |
2122 | ||
f4e91eb4 TJ |
2123 | static ssize_t show_hca(struct device *device, struct device_attribute *attr, |
2124 | char *buf) | |
cd9281d8 | 2125 | { |
f4e91eb4 TJ |
2126 | struct mlx4_ib_dev *dev = |
2127 | container_of(device, struct mlx4_ib_dev, ib_dev.dev); | |
872bf2fb | 2128 | return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device); |
cd9281d8 JM |
2129 | } |
2130 | ||
f4e91eb4 TJ |
2131 | static ssize_t show_rev(struct device *device, struct device_attribute *attr, |
2132 | char *buf) | |
cd9281d8 | 2133 | { |
f4e91eb4 TJ |
2134 | struct mlx4_ib_dev *dev = |
2135 | container_of(device, struct mlx4_ib_dev, ib_dev.dev); | |
cd9281d8 JM |
2136 | return sprintf(buf, "%x\n", dev->dev->rev_id); |
2137 | } | |
2138 | ||
f4e91eb4 TJ |
2139 | static ssize_t show_board(struct device *device, struct device_attribute *attr, |
2140 | char *buf) | |
cd9281d8 | 2141 | { |
f4e91eb4 TJ |
2142 | struct mlx4_ib_dev *dev = |
2143 | container_of(device, struct mlx4_ib_dev, ib_dev.dev); | |
2144 | return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN, | |
2145 | dev->dev->board_id); | |
cd9281d8 JM |
2146 | } |
2147 | ||
f4e91eb4 | 2148 | static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); |
f4e91eb4 TJ |
2149 | static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); |
2150 | static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); | |
cd9281d8 | 2151 | |
f4e91eb4 TJ |
2152 | static struct device_attribute *mlx4_class_attributes[] = { |
2153 | &dev_attr_hw_rev, | |
f4e91eb4 TJ |
2154 | &dev_attr_hca_type, |
2155 | &dev_attr_board_id | |
cd9281d8 JM |
2156 | }; |
2157 | ||
3f85f2aa MB |
2158 | struct diag_counter { |
2159 | const char *name; | |
2160 | u32 offset; | |
2161 | }; | |
2162 | ||
2163 | #define DIAG_COUNTER(_name, _offset) \ | |
2164 | { .name = #_name, .offset = _offset } | |
2165 | ||
2166 | static const struct diag_counter diag_basic[] = { | |
2167 | DIAG_COUNTER(rq_num_lle, 0x00), | |
2168 | DIAG_COUNTER(sq_num_lle, 0x04), | |
2169 | DIAG_COUNTER(rq_num_lqpoe, 0x08), | |
2170 | DIAG_COUNTER(sq_num_lqpoe, 0x0C), | |
2171 | DIAG_COUNTER(rq_num_lpe, 0x18), | |
2172 | DIAG_COUNTER(sq_num_lpe, 0x1C), | |
2173 | DIAG_COUNTER(rq_num_wrfe, 0x20), | |
2174 | DIAG_COUNTER(sq_num_wrfe, 0x24), | |
2175 | DIAG_COUNTER(sq_num_mwbe, 0x2C), | |
2176 | DIAG_COUNTER(sq_num_bre, 0x34), | |
2177 | DIAG_COUNTER(sq_num_rire, 0x44), | |
2178 | DIAG_COUNTER(rq_num_rire, 0x48), | |
2179 | DIAG_COUNTER(sq_num_rae, 0x4C), | |
2180 | DIAG_COUNTER(rq_num_rae, 0x50), | |
2181 | DIAG_COUNTER(sq_num_roe, 0x54), | |
2182 | DIAG_COUNTER(sq_num_tree, 0x5C), | |
2183 | DIAG_COUNTER(sq_num_rree, 0x64), | |
2184 | DIAG_COUNTER(rq_num_rnr, 0x68), | |
2185 | DIAG_COUNTER(sq_num_rnr, 0x6C), | |
2186 | DIAG_COUNTER(rq_num_oos, 0x100), | |
2187 | DIAG_COUNTER(sq_num_oos, 0x104), | |
2188 | }; | |
2189 | ||
2190 | static const struct diag_counter diag_ext[] = { | |
2191 | DIAG_COUNTER(rq_num_dup, 0x130), | |
2192 | DIAG_COUNTER(sq_num_to, 0x134), | |
2193 | }; | |
2194 | ||
2195 | static const struct diag_counter diag_device_only[] = { | |
2196 | DIAG_COUNTER(num_cqovf, 0x1A0), | |
2197 | DIAG_COUNTER(rq_num_udsdprd, 0x118), | |
2198 | }; | |
2199 | ||
2200 | static struct rdma_hw_stats *mlx4_ib_alloc_hw_stats(struct ib_device *ibdev, | |
2201 | u8 port_num) | |
2202 | { | |
2203 | struct mlx4_ib_dev *dev = to_mdev(ibdev); | |
2204 | struct mlx4_ib_diag_counters *diag = dev->diag_counters; | |
2205 | ||
2206 | if (!diag[!!port_num].name) | |
2207 | return NULL; | |
2208 | ||
2209 | return rdma_alloc_hw_stats_struct(diag[!!port_num].name, | |
2210 | diag[!!port_num].num_counters, | |
2211 | RDMA_HW_STATS_DEFAULT_LIFESPAN); | |
2212 | } | |
2213 | ||
2214 | static int mlx4_ib_get_hw_stats(struct ib_device *ibdev, | |
2215 | struct rdma_hw_stats *stats, | |
2216 | u8 port, int index) | |
2217 | { | |
2218 | struct mlx4_ib_dev *dev = to_mdev(ibdev); | |
2219 | struct mlx4_ib_diag_counters *diag = dev->diag_counters; | |
2220 | u32 hw_value[ARRAY_SIZE(diag_device_only) + | |
2221 | ARRAY_SIZE(diag_ext) + ARRAY_SIZE(diag_basic)] = {}; | |
2222 | int ret; | |
2223 | int i; | |
2224 | ||
2225 | ret = mlx4_query_diag_counters(dev->dev, | |
2226 | MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS, | |
2227 | diag[!!port].offset, hw_value, | |
2228 | diag[!!port].num_counters, port); | |
2229 | ||
2230 | if (ret) | |
2231 | return ret; | |
2232 | ||
2233 | for (i = 0; i < diag[!!port].num_counters; i++) | |
2234 | stats->value[i] = hw_value[i]; | |
2235 | ||
2236 | return diag[!!port].num_counters; | |
2237 | } | |
2238 | ||
2239 | static int __mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev, | |
2240 | const char ***name, | |
2241 | u32 **offset, | |
2242 | u32 *num, | |
2243 | bool port) | |
2244 | { | |
2245 | u32 num_counters; | |
2246 | ||
2247 | num_counters = ARRAY_SIZE(diag_basic); | |
2248 | ||
2249 | if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) | |
2250 | num_counters += ARRAY_SIZE(diag_ext); | |
2251 | ||
2252 | if (!port) | |
2253 | num_counters += ARRAY_SIZE(diag_device_only); | |
2254 | ||
2255 | *name = kcalloc(num_counters, sizeof(**name), GFP_KERNEL); | |
2256 | if (!*name) | |
2257 | return -ENOMEM; | |
2258 | ||
2259 | *offset = kcalloc(num_counters, sizeof(**offset), GFP_KERNEL); | |
2260 | if (!*offset) | |
2261 | goto err_name; | |
2262 | ||
2263 | *num = num_counters; | |
2264 | ||
2265 | return 0; | |
2266 | ||
2267 | err_name: | |
2268 | kfree(*name); | |
2269 | return -ENOMEM; | |
2270 | } | |
2271 | ||
2272 | static void mlx4_ib_fill_diag_counters(struct mlx4_ib_dev *ibdev, | |
2273 | const char **name, | |
2274 | u32 *offset, | |
2275 | bool port) | |
2276 | { | |
2277 | int i; | |
2278 | int j; | |
2279 | ||
2280 | for (i = 0, j = 0; i < ARRAY_SIZE(diag_basic); i++, j++) { | |
2281 | name[i] = diag_basic[i].name; | |
2282 | offset[i] = diag_basic[i].offset; | |
2283 | } | |
2284 | ||
2285 | if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) { | |
2286 | for (i = 0; i < ARRAY_SIZE(diag_ext); i++, j++) { | |
2287 | name[j] = diag_ext[i].name; | |
2288 | offset[j] = diag_ext[i].offset; | |
2289 | } | |
2290 | } | |
2291 | ||
2292 | if (!port) { | |
2293 | for (i = 0; i < ARRAY_SIZE(diag_device_only); i++, j++) { | |
2294 | name[j] = diag_device_only[i].name; | |
2295 | offset[j] = diag_device_only[i].offset; | |
2296 | } | |
2297 | } | |
2298 | } | |
2299 | ||
2300 | static int mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev) | |
2301 | { | |
2302 | struct mlx4_ib_diag_counters *diag = ibdev->diag_counters; | |
2303 | int i; | |
2304 | int ret; | |
2305 | bool per_port = !!(ibdev->dev->caps.flags2 & | |
2306 | MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT); | |
2307 | ||
69d269d3 KH |
2308 | if (mlx4_is_slave(ibdev->dev)) |
2309 | return 0; | |
2310 | ||
3f85f2aa MB |
2311 | for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) { |
2312 | /* i == 1 means we are building port counters */ | |
2313 | if (i && !per_port) | |
2314 | continue; | |
2315 | ||
2316 | ret = __mlx4_ib_alloc_diag_counters(ibdev, &diag[i].name, | |
2317 | &diag[i].offset, | |
2318 | &diag[i].num_counters, i); | |
2319 | if (ret) | |
2320 | goto err_alloc; | |
2321 | ||
2322 | mlx4_ib_fill_diag_counters(ibdev, diag[i].name, | |
2323 | diag[i].offset, i); | |
2324 | } | |
2325 | ||
2326 | ibdev->ib_dev.get_hw_stats = mlx4_ib_get_hw_stats; | |
2327 | ibdev->ib_dev.alloc_hw_stats = mlx4_ib_alloc_hw_stats; | |
2328 | ||
2329 | return 0; | |
2330 | ||
2331 | err_alloc: | |
2332 | if (i) { | |
2333 | kfree(diag[i - 1].name); | |
2334 | kfree(diag[i - 1].offset); | |
2335 | } | |
2336 | ||
2337 | return ret; | |
2338 | } | |
2339 | ||
2340 | static void mlx4_ib_diag_cleanup(struct mlx4_ib_dev *ibdev) | |
2341 | { | |
2342 | int i; | |
2343 | ||
2344 | for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) { | |
2345 | kfree(ibdev->diag_counters[i].offset); | |
2346 | kfree(ibdev->diag_counters[i].name); | |
2347 | } | |
2348 | } | |
2349 | ||
9433c188 MB |
2350 | #define MLX4_IB_INVALID_MAC ((u64)-1) |
2351 | static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev, | |
2352 | struct net_device *dev, | |
2353 | int port) | |
2354 | { | |
2355 | u64 new_smac = 0; | |
2356 | u64 release_mac = MLX4_IB_INVALID_MAC; | |
2357 | struct mlx4_ib_qp *qp; | |
2358 | ||
2359 | read_lock(&dev_base_lock); | |
2360 | new_smac = mlx4_mac_to_u64(dev->dev_addr); | |
2361 | read_unlock(&dev_base_lock); | |
2362 | ||
3e0629cb JM |
2363 | atomic64_set(&ibdev->iboe.mac[port - 1], new_smac); |
2364 | ||
d24d9f43 JM |
2365 | /* no need for update QP1 and mac registration in non-SRIOV */ |
2366 | if (!mlx4_is_mfunc(ibdev->dev)) | |
2367 | return; | |
2368 | ||
9433c188 MB |
2369 | mutex_lock(&ibdev->qp1_proxy_lock[port - 1]); |
2370 | qp = ibdev->qp1_proxy[port - 1]; | |
2371 | if (qp) { | |
2372 | int new_smac_index; | |
25476b02 | 2373 | u64 old_smac; |
9433c188 MB |
2374 | struct mlx4_update_qp_params update_params; |
2375 | ||
25476b02 JM |
2376 | mutex_lock(&qp->mutex); |
2377 | old_smac = qp->pri.smac; | |
9433c188 MB |
2378 | if (new_smac == old_smac) |
2379 | goto unlock; | |
2380 | ||
2381 | new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac); | |
2382 | ||
2383 | if (new_smac_index < 0) | |
2384 | goto unlock; | |
2385 | ||
2386 | update_params.smac_index = new_smac_index; | |
09e05c3f | 2387 | if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC, |
9433c188 MB |
2388 | &update_params)) { |
2389 | release_mac = new_smac; | |
2390 | goto unlock; | |
2391 | } | |
25476b02 JM |
2392 | /* if old port was zero, no mac was yet registered for this QP */ |
2393 | if (qp->pri.smac_port) | |
2394 | release_mac = old_smac; | |
9433c188 | 2395 | qp->pri.smac = new_smac; |
25476b02 | 2396 | qp->pri.smac_port = port; |
9433c188 | 2397 | qp->pri.smac_index = new_smac_index; |
9433c188 MB |
2398 | } |
2399 | ||
2400 | unlock: | |
9433c188 MB |
2401 | if (release_mac != MLX4_IB_INVALID_MAC) |
2402 | mlx4_unregister_mac(ibdev->dev, port, release_mac); | |
25476b02 JM |
2403 | if (qp) |
2404 | mutex_unlock(&qp->mutex); | |
2405 | mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]); | |
9433c188 MB |
2406 | } |
2407 | ||
9433c188 MB |
2408 | static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev, |
2409 | struct net_device *dev, | |
2410 | unsigned long event) | |
2411 | ||
d487ee77 | 2412 | { |
fa417f7b | 2413 | struct mlx4_ib_iboe *iboe; |
9433c188 | 2414 | int update_qps_port = -1; |
fa417f7b EC |
2415 | int port; |
2416 | ||
5070cd22 MS |
2417 | ASSERT_RTNL(); |
2418 | ||
fa417f7b EC |
2419 | iboe = &ibdev->iboe; |
2420 | ||
dba3ad2a | 2421 | spin_lock_bh(&iboe->lock); |
fa417f7b | 2422 | mlx4_foreach_ib_transport_port(port, ibdev->dev) { |
ad4885d2 | 2423 | |
fa417f7b | 2424 | iboe->netdevs[port - 1] = |
0345584e | 2425 | mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port); |
fa417f7b | 2426 | |
9433c188 MB |
2427 | if (dev == iboe->netdevs[port - 1] && |
2428 | (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER || | |
2429 | event == NETDEV_UP || event == NETDEV_CHANGE)) | |
2430 | update_qps_port = port; | |
2431 | ||
d487ee77 | 2432 | } |
dba3ad2a | 2433 | spin_unlock_bh(&iboe->lock); |
9433c188 MB |
2434 | |
2435 | if (update_qps_port > 0) | |
2436 | mlx4_ib_update_qps(ibdev, dev, update_qps_port); | |
d487ee77 MS |
2437 | } |
2438 | ||
2439 | static int mlx4_ib_netdev_event(struct notifier_block *this, | |
2440 | unsigned long event, void *ptr) | |
2441 | { | |
2442 | struct net_device *dev = netdev_notifier_info_to_dev(ptr); | |
2443 | struct mlx4_ib_dev *ibdev; | |
2444 | ||
2445 | if (!net_eq(dev_net(dev), &init_net)) | |
2446 | return NOTIFY_DONE; | |
2447 | ||
2448 | ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb); | |
9433c188 | 2449 | mlx4_ib_scan_netdevs(ibdev, dev, event); |
fa417f7b EC |
2450 | |
2451 | return NOTIFY_DONE; | |
2452 | } | |
2453 | ||
54679e14 JM |
2454 | static void init_pkeys(struct mlx4_ib_dev *ibdev) |
2455 | { | |
2456 | int port; | |
2457 | int slave; | |
2458 | int i; | |
2459 | ||
2460 | if (mlx4_is_master(ibdev->dev)) { | |
872bf2fb YH |
2461 | for (slave = 0; slave <= ibdev->dev->persist->num_vfs; |
2462 | ++slave) { | |
54679e14 JM |
2463 | for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) { |
2464 | for (i = 0; | |
2465 | i < ibdev->dev->phys_caps.pkey_phys_table_len[port]; | |
2466 | ++i) { | |
2467 | ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] = | |
2468 | /* master has the identity virt2phys pkey mapping */ | |
2469 | (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i : | |
2470 | ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1; | |
2471 | mlx4_sync_pkey_table(ibdev->dev, slave, port, i, | |
2472 | ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]); | |
2473 | } | |
2474 | } | |
2475 | } | |
2476 | /* initialize pkey cache */ | |
2477 | for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) { | |
2478 | for (i = 0; | |
2479 | i < ibdev->dev->phys_caps.pkey_phys_table_len[port]; | |
2480 | ++i) | |
2481 | ibdev->pkeys.phys_pkey_cache[port-1][i] = | |
2482 | (i) ? 0 : 0xFFFF; | |
2483 | } | |
2484 | } | |
2485 | } | |
2486 | ||
e605b743 SP |
2487 | static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev) |
2488 | { | |
c66fa19c | 2489 | int i, j, eq = 0, total_eqs = 0; |
e605b743 | 2490 | |
c66fa19c MB |
2491 | ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors, |
2492 | sizeof(ibdev->eq_table[0]), GFP_KERNEL); | |
e605b743 SP |
2493 | if (!ibdev->eq_table) |
2494 | return; | |
2495 | ||
c66fa19c MB |
2496 | for (i = 1; i <= dev->caps.num_ports; i++) { |
2497 | for (j = 0; j < mlx4_get_eqs_per_port(dev, i); | |
2498 | j++, total_eqs++) { | |
2499 | if (i > 1 && mlx4_is_eq_shared(dev, total_eqs)) | |
2500 | continue; | |
2501 | ibdev->eq_table[eq] = total_eqs; | |
2502 | if (!mlx4_assign_eq(dev, i, | |
2503 | &ibdev->eq_table[eq])) | |
2504 | eq++; | |
2505 | else | |
2506 | ibdev->eq_table[eq] = -1; | |
e605b743 SP |
2507 | } |
2508 | } | |
2509 | ||
c66fa19c MB |
2510 | for (i = eq; i < dev->caps.num_comp_vectors; |
2511 | ibdev->eq_table[i++] = -1) | |
2512 | ; | |
e605b743 SP |
2513 | |
2514 | /* Advertise the new number of EQs to clients */ | |
c66fa19c | 2515 | ibdev->ib_dev.num_comp_vectors = eq; |
e605b743 SP |
2516 | } |
2517 | ||
2518 | static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev) | |
2519 | { | |
2520 | int i; | |
c66fa19c | 2521 | int total_eqs = ibdev->ib_dev.num_comp_vectors; |
3aac6ff1 | 2522 | |
c66fa19c | 2523 | /* no eqs were allocated */ |
3aac6ff1 SP |
2524 | if (!ibdev->eq_table) |
2525 | return; | |
e605b743 SP |
2526 | |
2527 | /* Reset the advertised EQ number */ | |
c66fa19c | 2528 | ibdev->ib_dev.num_comp_vectors = 0; |
e605b743 | 2529 | |
c66fa19c | 2530 | for (i = 0; i < total_eqs; i++) |
e605b743 | 2531 | mlx4_release_eq(dev, ibdev->eq_table[i]); |
e605b743 | 2532 | |
e605b743 | 2533 | kfree(ibdev->eq_table); |
c66fa19c | 2534 | ibdev->eq_table = NULL; |
e605b743 SP |
2535 | } |
2536 | ||
7738613e IW |
2537 | static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num, |
2538 | struct ib_port_immutable *immutable) | |
2539 | { | |
2540 | struct ib_port_attr attr; | |
4ed088e6 | 2541 | struct mlx4_ib_dev *mdev = to_mdev(ibdev); |
7738613e IW |
2542 | int err; |
2543 | ||
4ed088e6 | 2544 | if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND) { |
f9b22e35 | 2545 | immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB; |
bc63f9d5 | 2546 | immutable->max_mad_size = IB_MGMT_MAD_SIZE; |
4ed088e6 MB |
2547 | } else { |
2548 | if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE) | |
2549 | immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; | |
2550 | if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) | |
2551 | immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE | | |
2552 | RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; | |
bc63f9d5 OG |
2553 | immutable->core_cap_flags |= RDMA_CORE_PORT_RAW_PACKET; |
2554 | if (immutable->core_cap_flags & (RDMA_CORE_PORT_IBA_ROCE | | |
2555 | RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP)) | |
2556 | immutable->max_mad_size = IB_MGMT_MAD_SIZE; | |
4ed088e6 | 2557 | } |
f9b22e35 | 2558 | |
c4550c63 OG |
2559 | err = ib_query_port(ibdev, port_num, &attr); |
2560 | if (err) | |
2561 | return err; | |
2562 | ||
2563 | immutable->pkey_tbl_len = attr.pkey_tbl_len; | |
2564 | immutable->gid_tbl_len = attr.gid_tbl_len; | |
2565 | ||
7738613e IW |
2566 | return 0; |
2567 | } | |
2568 | ||
e9db59fc IW |
2569 | static void get_fw_ver_str(struct ib_device *device, char *str, |
2570 | size_t str_len) | |
2571 | { | |
2572 | struct mlx4_ib_dev *dev = | |
2573 | container_of(device, struct mlx4_ib_dev, ib_dev); | |
2574 | snprintf(str, str_len, "%d.%d.%d", | |
2575 | (int) (dev->dev->caps.fw_ver >> 32), | |
2576 | (int) (dev->dev->caps.fw_ver >> 16) & 0xffff, | |
2577 | (int) dev->dev->caps.fw_ver & 0xffff); | |
2578 | } | |
2579 | ||
225c7b1f RD |
2580 | static void *mlx4_ib_add(struct mlx4_dev *dev) |
2581 | { | |
2582 | struct mlx4_ib_dev *ibdev; | |
22e7ef9c | 2583 | int num_ports = 0; |
035b1032 | 2584 | int i, j; |
fa417f7b EC |
2585 | int err; |
2586 | struct mlx4_ib_iboe *iboe; | |
4196670b | 2587 | int ib_num_ports = 0; |
a5750090 | 2588 | int num_req_counters; |
c3abb51b EBE |
2589 | int allocated; |
2590 | u32 counter_index; | |
3ba8e31d | 2591 | struct counter_index *new_counter_index = NULL; |
225c7b1f | 2592 | |
987c8f8f | 2593 | pr_info_once("%s", mlx4_ib_version); |
68f3948d | 2594 | |
026149cb | 2595 | num_ports = 0; |
fa417f7b | 2596 | mlx4_foreach_ib_transport_port(i, dev) |
22e7ef9c RD |
2597 | num_ports++; |
2598 | ||
2599 | /* No point in registering a device with no ports... */ | |
2600 | if (num_ports == 0) | |
2601 | return NULL; | |
2602 | ||
225c7b1f RD |
2603 | ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev); |
2604 | if (!ibdev) { | |
872bf2fb YH |
2605 | dev_err(&dev->persist->pdev->dev, |
2606 | "Device struct alloc failed\n"); | |
225c7b1f RD |
2607 | return NULL; |
2608 | } | |
2609 | ||
fa417f7b EC |
2610 | iboe = &ibdev->iboe; |
2611 | ||
225c7b1f RD |
2612 | if (mlx4_pd_alloc(dev, &ibdev->priv_pdn)) |
2613 | goto err_dealloc; | |
2614 | ||
2615 | if (mlx4_uar_alloc(dev, &ibdev->priv_uar)) | |
2616 | goto err_pd; | |
2617 | ||
4979d18f RD |
2618 | ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT, |
2619 | PAGE_SIZE); | |
225c7b1f RD |
2620 | if (!ibdev->uar_map) |
2621 | goto err_uar; | |
26c6bc7b | 2622 | MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock); |
225c7b1f | 2623 | |
225c7b1f | 2624 | ibdev->dev = dev; |
c6215745 | 2625 | ibdev->bond_next_port = 0; |
225c7b1f RD |
2626 | |
2627 | strlcpy(ibdev->ib_dev.name, "mlx4_%d", IB_DEVICE_NAME_MAX); | |
2628 | ibdev->ib_dev.owner = THIS_MODULE; | |
2629 | ibdev->ib_dev.node_type = RDMA_NODE_IB_CA; | |
95d04f07 | 2630 | ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey; |
22e7ef9c | 2631 | ibdev->num_ports = num_ports; |
a5750090 MS |
2632 | ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ? |
2633 | 1 : ibdev->num_ports; | |
b8dd786f | 2634 | ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors; |
d66c88a8 | 2635 | ibdev->ib_dev.dev.parent = &dev->persist->pdev->dev; |
5070cd22 MS |
2636 | ibdev->ib_dev.get_netdev = mlx4_ib_get_netdev; |
2637 | ibdev->ib_dev.add_gid = mlx4_ib_add_gid; | |
2638 | ibdev->ib_dev.del_gid = mlx4_ib_del_gid; | |
225c7b1f | 2639 | |
08ff3235 OG |
2640 | if (dev->caps.userspace_caps) |
2641 | ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION; | |
2642 | else | |
2643 | ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION; | |
2644 | ||
225c7b1f RD |
2645 | ibdev->ib_dev.uverbs_cmd_mask = |
2646 | (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | | |
2647 | (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | | |
2648 | (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | | |
2649 | (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | | |
2650 | (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | | |
2651 | (1ull << IB_USER_VERBS_CMD_REG_MR) | | |
9376932d | 2652 | (1ull << IB_USER_VERBS_CMD_REREG_MR) | |
225c7b1f RD |
2653 | (1ull << IB_USER_VERBS_CMD_DEREG_MR) | |
2654 | (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | | |
2655 | (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | | |
bbf8eed1 | 2656 | (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | |
225c7b1f RD |
2657 | (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | |
2658 | (1ull << IB_USER_VERBS_CMD_CREATE_QP) | | |
2659 | (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | | |
6a775e2b | 2660 | (1ull << IB_USER_VERBS_CMD_QUERY_QP) | |
225c7b1f RD |
2661 | (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | |
2662 | (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | | |
2663 | (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | | |
2664 | (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | | |
2665 | (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | | |
65541cb7 | 2666 | (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | |
18abd5ea | 2667 | (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | |
42849b26 SH |
2668 | (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | |
2669 | (1ull << IB_USER_VERBS_CMD_OPEN_QP); | |
225c7b1f RD |
2670 | |
2671 | ibdev->ib_dev.query_device = mlx4_ib_query_device; | |
2672 | ibdev->ib_dev.query_port = mlx4_ib_query_port; | |
fa417f7b | 2673 | ibdev->ib_dev.get_link_layer = mlx4_ib_port_link_layer; |
225c7b1f RD |
2674 | ibdev->ib_dev.query_gid = mlx4_ib_query_gid; |
2675 | ibdev->ib_dev.query_pkey = mlx4_ib_query_pkey; | |
2676 | ibdev->ib_dev.modify_device = mlx4_ib_modify_device; | |
2677 | ibdev->ib_dev.modify_port = mlx4_ib_modify_port; | |
2678 | ibdev->ib_dev.alloc_ucontext = mlx4_ib_alloc_ucontext; | |
2679 | ibdev->ib_dev.dealloc_ucontext = mlx4_ib_dealloc_ucontext; | |
2680 | ibdev->ib_dev.mmap = mlx4_ib_mmap; | |
2681 | ibdev->ib_dev.alloc_pd = mlx4_ib_alloc_pd; | |
2682 | ibdev->ib_dev.dealloc_pd = mlx4_ib_dealloc_pd; | |
2683 | ibdev->ib_dev.create_ah = mlx4_ib_create_ah; | |
2684 | ibdev->ib_dev.query_ah = mlx4_ib_query_ah; | |
2685 | ibdev->ib_dev.destroy_ah = mlx4_ib_destroy_ah; | |
2686 | ibdev->ib_dev.create_srq = mlx4_ib_create_srq; | |
2687 | ibdev->ib_dev.modify_srq = mlx4_ib_modify_srq; | |
65541cb7 | 2688 | ibdev->ib_dev.query_srq = mlx4_ib_query_srq; |
225c7b1f RD |
2689 | ibdev->ib_dev.destroy_srq = mlx4_ib_destroy_srq; |
2690 | ibdev->ib_dev.post_srq_recv = mlx4_ib_post_srq_recv; | |
2691 | ibdev->ib_dev.create_qp = mlx4_ib_create_qp; | |
2692 | ibdev->ib_dev.modify_qp = mlx4_ib_modify_qp; | |
6a775e2b | 2693 | ibdev->ib_dev.query_qp = mlx4_ib_query_qp; |
225c7b1f RD |
2694 | ibdev->ib_dev.destroy_qp = mlx4_ib_destroy_qp; |
2695 | ibdev->ib_dev.post_send = mlx4_ib_post_send; | |
2696 | ibdev->ib_dev.post_recv = mlx4_ib_post_recv; | |
2697 | ibdev->ib_dev.create_cq = mlx4_ib_create_cq; | |
3fdcb97f | 2698 | ibdev->ib_dev.modify_cq = mlx4_ib_modify_cq; |
bbf8eed1 | 2699 | ibdev->ib_dev.resize_cq = mlx4_ib_resize_cq; |
225c7b1f RD |
2700 | ibdev->ib_dev.destroy_cq = mlx4_ib_destroy_cq; |
2701 | ibdev->ib_dev.poll_cq = mlx4_ib_poll_cq; | |
2702 | ibdev->ib_dev.req_notify_cq = mlx4_ib_arm_cq; | |
2703 | ibdev->ib_dev.get_dma_mr = mlx4_ib_get_dma_mr; | |
2704 | ibdev->ib_dev.reg_user_mr = mlx4_ib_reg_user_mr; | |
9376932d | 2705 | ibdev->ib_dev.rereg_user_mr = mlx4_ib_rereg_user_mr; |
225c7b1f | 2706 | ibdev->ib_dev.dereg_mr = mlx4_ib_dereg_mr; |
679e34d1 | 2707 | ibdev->ib_dev.alloc_mr = mlx4_ib_alloc_mr; |
1b2cd0fc | 2708 | ibdev->ib_dev.map_mr_sg = mlx4_ib_map_mr_sg; |
225c7b1f RD |
2709 | ibdev->ib_dev.attach_mcast = mlx4_ib_mcg_attach; |
2710 | ibdev->ib_dev.detach_mcast = mlx4_ib_mcg_detach; | |
2711 | ibdev->ib_dev.process_mad = mlx4_ib_process_mad; | |
7738613e | 2712 | ibdev->ib_dev.get_port_immutable = mlx4_port_immutable; |
e9db59fc | 2713 | ibdev->ib_dev.get_dev_fw_str = get_fw_ver_str; |
ae184dde | 2714 | ibdev->ib_dev.disassociate_ucontext = mlx4_ib_disassociate_ucontext; |
225c7b1f | 2715 | |
992e8e6e JM |
2716 | if (!mlx4_is_slave(ibdev->dev)) { |
2717 | ibdev->ib_dev.alloc_fmr = mlx4_ib_fmr_alloc; | |
2718 | ibdev->ib_dev.map_phys_fmr = mlx4_ib_map_phys_fmr; | |
2719 | ibdev->ib_dev.unmap_fmr = mlx4_ib_unmap_fmr; | |
2720 | ibdev->ib_dev.dealloc_fmr = mlx4_ib_fmr_dealloc; | |
2721 | } | |
8ad11fb6 | 2722 | |
b425388d SM |
2723 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || |
2724 | dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) { | |
2725 | ibdev->ib_dev.alloc_mw = mlx4_ib_alloc_mw; | |
b425388d SM |
2726 | ibdev->ib_dev.dealloc_mw = mlx4_ib_dealloc_mw; |
2727 | ||
2728 | ibdev->ib_dev.uverbs_cmd_mask |= | |
2729 | (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | | |
2730 | (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); | |
2731 | } | |
2732 | ||
012a8ff5 SH |
2733 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) { |
2734 | ibdev->ib_dev.alloc_xrcd = mlx4_ib_alloc_xrcd; | |
2735 | ibdev->ib_dev.dealloc_xrcd = mlx4_ib_dealloc_xrcd; | |
2736 | ibdev->ib_dev.uverbs_cmd_mask |= | |
2737 | (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | | |
2738 | (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); | |
2739 | } | |
2740 | ||
f77c0162 | 2741 | if (check_flow_steering_support(dev)) { |
0a9b7d59 | 2742 | ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED; |
f77c0162 HHZ |
2743 | ibdev->ib_dev.create_flow = mlx4_ib_create_flow; |
2744 | ibdev->ib_dev.destroy_flow = mlx4_ib_destroy_flow; | |
2745 | ||
f21519b2 YD |
2746 | ibdev->ib_dev.uverbs_ex_cmd_mask |= |
2747 | (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | | |
2748 | (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); | |
f77c0162 HHZ |
2749 | } |
2750 | ||
4b664c43 MB |
2751 | ibdev->ib_dev.uverbs_ex_cmd_mask |= |
2752 | (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | | |
fbfb6625 EBE |
2753 | (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | |
2754 | (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP); | |
4b664c43 | 2755 | |
e605b743 SP |
2756 | mlx4_ib_alloc_eqs(dev, ibdev); |
2757 | ||
fa417f7b EC |
2758 | spin_lock_init(&iboe->lock); |
2759 | ||
225c7b1f RD |
2760 | if (init_node_data(ibdev)) |
2761 | goto err_map; | |
fd10ed8e | 2762 | mlx4_init_sl2vl_tbl(ibdev); |
225c7b1f | 2763 | |
3ba8e31d EBE |
2764 | for (i = 0; i < ibdev->num_ports; ++i) { |
2765 | mutex_init(&ibdev->counters_table[i].mutex); | |
2766 | INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list); | |
2767 | } | |
2768 | ||
a5750090 MS |
2769 | num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports; |
2770 | for (i = 0; i < num_req_counters; ++i) { | |
9433c188 | 2771 | mutex_init(&ibdev->qp1_proxy_lock[i]); |
c3abb51b | 2772 | allocated = 0; |
cfcde11c OG |
2773 | if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) == |
2774 | IB_LINK_LAYER_ETHERNET) { | |
c3abb51b EBE |
2775 | err = mlx4_counter_alloc(ibdev->dev, &counter_index); |
2776 | /* if failed to allocate a new counter, use default */ | |
cfcde11c | 2777 | if (err) |
c3abb51b EBE |
2778 | counter_index = |
2779 | mlx4_get_default_counter_index(dev, | |
2780 | i + 1); | |
2781 | else | |
2782 | allocated = 1; | |
2783 | } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */ | |
2784 | counter_index = mlx4_get_default_counter_index(dev, | |
2785 | i + 1); | |
3839d8ac | 2786 | } |
3ba8e31d EBE |
2787 | new_counter_index = kmalloc(sizeof(*new_counter_index), |
2788 | GFP_KERNEL); | |
2789 | if (!new_counter_index) { | |
2790 | if (allocated) | |
2791 | mlx4_counter_free(ibdev->dev, counter_index); | |
2792 | goto err_counter; | |
2793 | } | |
2794 | new_counter_index->index = counter_index; | |
2795 | new_counter_index->allocated = allocated; | |
2796 | list_add_tail(&new_counter_index->list, | |
2797 | &ibdev->counters_table[i].counters_list); | |
2798 | ibdev->counters_table[i].default_counter = counter_index; | |
c3abb51b EBE |
2799 | pr_info("counter index %d for port %d allocated %d\n", |
2800 | counter_index, i + 1, allocated); | |
cfcde11c | 2801 | } |
a5750090 | 2802 | if (mlx4_is_bonded(dev)) |
c3abb51b | 2803 | for (i = 1; i < ibdev->num_ports ; ++i) { |
3ba8e31d EBE |
2804 | new_counter_index = |
2805 | kmalloc(sizeof(struct counter_index), | |
2806 | GFP_KERNEL); | |
2807 | if (!new_counter_index) | |
2808 | goto err_counter; | |
2809 | new_counter_index->index = counter_index; | |
2810 | new_counter_index->allocated = 0; | |
2811 | list_add_tail(&new_counter_index->list, | |
2812 | &ibdev->counters_table[i].counters_list); | |
2813 | ibdev->counters_table[i].default_counter = | |
2814 | counter_index; | |
c3abb51b | 2815 | } |
cfcde11c | 2816 | |
4196670b MB |
2817 | mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) |
2818 | ib_num_ports++; | |
2819 | ||
225c7b1f RD |
2820 | spin_lock_init(&ibdev->sm_lock); |
2821 | mutex_init(&ibdev->cap_mask_mutex); | |
35f05dab YH |
2822 | INIT_LIST_HEAD(&ibdev->qp_list); |
2823 | spin_lock_init(&ibdev->reset_flow_resource_lock); | |
225c7b1f | 2824 | |
4196670b MB |
2825 | if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED && |
2826 | ib_num_ports) { | |
c1c98501 MB |
2827 | ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS; |
2828 | err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count, | |
2829 | MLX4_IB_UC_STEER_QPN_ALIGN, | |
ddae0349 | 2830 | &ibdev->steer_qpn_base, 0); |
c1c98501 MB |
2831 | if (err) |
2832 | goto err_counter; | |
2833 | ||
2834 | ibdev->ib_uc_qpns_bitmap = | |
2835 | kmalloc(BITS_TO_LONGS(ibdev->steer_qpn_count) * | |
2836 | sizeof(long), | |
2837 | GFP_KERNEL); | |
15d4626e | 2838 | if (!ibdev->ib_uc_qpns_bitmap) |
c1c98501 | 2839 | goto err_steer_qp_release; |
c1c98501 | 2840 | |
1f22e454 EBE |
2841 | if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB) { |
2842 | bitmap_zero(ibdev->ib_uc_qpns_bitmap, | |
2843 | ibdev->steer_qpn_count); | |
2844 | err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE( | |
2845 | dev, ibdev->steer_qpn_base, | |
2846 | ibdev->steer_qpn_base + | |
2847 | ibdev->steer_qpn_count - 1); | |
2848 | if (err) | |
2849 | goto err_steer_free_bitmap; | |
2850 | } else { | |
2851 | bitmap_fill(ibdev->ib_uc_qpns_bitmap, | |
2852 | ibdev->steer_qpn_count); | |
2853 | } | |
c1c98501 MB |
2854 | } |
2855 | ||
3e0629cb JM |
2856 | for (j = 1; j <= ibdev->dev->caps.num_ports; j++) |
2857 | atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]); | |
2858 | ||
3f85f2aa | 2859 | if (mlx4_ib_alloc_diag_counters(ibdev)) |
c1c98501 | 2860 | goto err_steer_free_bitmap; |
225c7b1f | 2861 | |
3f85f2aa MB |
2862 | if (ib_register_device(&ibdev->ib_dev, NULL)) |
2863 | goto err_diag_counters; | |
2864 | ||
225c7b1f RD |
2865 | if (mlx4_ib_mad_init(ibdev)) |
2866 | goto err_reg; | |
2867 | ||
fc06573d JM |
2868 | if (mlx4_ib_init_sriov(ibdev)) |
2869 | goto err_mad; | |
2870 | ||
dd77abf8 MD |
2871 | if (!iboe->nb.notifier_call) { |
2872 | iboe->nb.notifier_call = mlx4_ib_netdev_event; | |
2873 | err = register_netdevice_notifier(&iboe->nb); | |
2874 | if (err) { | |
2875 | iboe->nb.notifier_call = NULL; | |
2876 | goto err_notif; | |
71a39bbb | 2877 | } |
fa417f7b | 2878 | } |
dd77abf8 MD |
2879 | if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) { |
2880 | err = mlx4_config_roce_v2_port(dev, ROCE_V2_UDP_DPORT); | |
2881 | if (err) | |
2882 | goto err_notif; | |
2883 | } | |
fa417f7b | 2884 | |
035b1032 | 2885 | for (j = 0; j < ARRAY_SIZE(mlx4_class_attributes); ++j) { |
f4e91eb4 | 2886 | if (device_create_file(&ibdev->ib_dev.dev, |
035b1032 | 2887 | mlx4_class_attributes[j])) |
fa417f7b | 2888 | goto err_notif; |
cd9281d8 JM |
2889 | } |
2890 | ||
3b4a8cd5 | 2891 | ibdev->ib_active = true; |
09d4d087 JP |
2892 | mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) |
2893 | devlink_port_type_ib_set(mlx4_get_devlink_port(dev, i), | |
2894 | &ibdev->ib_dev); | |
3b4a8cd5 | 2895 | |
54679e14 JM |
2896 | if (mlx4_is_mfunc(ibdev->dev)) |
2897 | init_pkeys(ibdev); | |
2898 | ||
3806d08c JM |
2899 | /* create paravirt contexts for any VFs which are active */ |
2900 | if (mlx4_is_master(ibdev->dev)) { | |
2901 | for (j = 0; j < MLX4_MFUNC_MAX; j++) { | |
2902 | if (j == mlx4_master_func_num(ibdev->dev)) | |
2903 | continue; | |
2904 | if (mlx4_is_slave_active(ibdev->dev, j)) | |
2905 | do_slave_init(ibdev, j, 1); | |
2906 | } | |
2907 | } | |
225c7b1f RD |
2908 | return ibdev; |
2909 | ||
fa417f7b | 2910 | err_notif: |
d487ee77 MS |
2911 | if (ibdev->iboe.nb.notifier_call) { |
2912 | if (unregister_netdevice_notifier(&ibdev->iboe.nb)) | |
2913 | pr_warn("failure unregistering notifier\n"); | |
2914 | ibdev->iboe.nb.notifier_call = NULL; | |
2915 | } | |
fa417f7b EC |
2916 | flush_workqueue(wq); |
2917 | ||
fc06573d JM |
2918 | mlx4_ib_close_sriov(ibdev); |
2919 | ||
2920 | err_mad: | |
2921 | mlx4_ib_mad_cleanup(ibdev); | |
2922 | ||
225c7b1f RD |
2923 | err_reg: |
2924 | ib_unregister_device(&ibdev->ib_dev); | |
2925 | ||
3f85f2aa MB |
2926 | err_diag_counters: |
2927 | mlx4_ib_diag_cleanup(ibdev); | |
2928 | ||
c1c98501 MB |
2929 | err_steer_free_bitmap: |
2930 | kfree(ibdev->ib_uc_qpns_bitmap); | |
2931 | ||
2932 | err_steer_qp_release: | |
2933 | if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED) | |
2934 | mlx4_qp_release_range(dev, ibdev->steer_qpn_base, | |
2935 | ibdev->steer_qpn_count); | |
cfcde11c | 2936 | err_counter: |
3ba8e31d EBE |
2937 | for (i = 0; i < ibdev->num_ports; ++i) |
2938 | mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]); | |
2939 | ||
225c7b1f | 2940 | err_map: |
99e68909 | 2941 | mlx4_ib_free_eqs(dev, ibdev); |
225c7b1f RD |
2942 | iounmap(ibdev->uar_map); |
2943 | ||
2944 | err_uar: | |
2945 | mlx4_uar_free(dev, &ibdev->priv_uar); | |
2946 | ||
2947 | err_pd: | |
2948 | mlx4_pd_free(dev, ibdev->priv_pdn); | |
2949 | ||
2950 | err_dealloc: | |
2951 | ib_dealloc_device(&ibdev->ib_dev); | |
2952 | ||
2953 | return NULL; | |
2954 | } | |
2955 | ||
c1c98501 MB |
2956 | int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn) |
2957 | { | |
2958 | int offset; | |
2959 | ||
2960 | WARN_ON(!dev->ib_uc_qpns_bitmap); | |
2961 | ||
2962 | offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap, | |
2963 | dev->steer_qpn_count, | |
2964 | get_count_order(count)); | |
2965 | if (offset < 0) | |
2966 | return offset; | |
2967 | ||
2968 | *qpn = dev->steer_qpn_base + offset; | |
2969 | return 0; | |
2970 | } | |
2971 | ||
2972 | void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count) | |
2973 | { | |
2974 | if (!qpn || | |
2975 | dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED) | |
2976 | return; | |
2977 | ||
2978 | BUG_ON(qpn < dev->steer_qpn_base); | |
2979 | ||
2980 | bitmap_release_region(dev->ib_uc_qpns_bitmap, | |
2981 | qpn - dev->steer_qpn_base, | |
2982 | get_count_order(count)); | |
2983 | } | |
2984 | ||
2985 | int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, | |
2986 | int is_attach) | |
2987 | { | |
2988 | int err; | |
2989 | size_t flow_size; | |
2990 | struct ib_flow_attr *flow = NULL; | |
2991 | struct ib_flow_spec_ib *ib_spec; | |
2992 | ||
2993 | if (is_attach) { | |
2994 | flow_size = sizeof(struct ib_flow_attr) + | |
2995 | sizeof(struct ib_flow_spec_ib); | |
2996 | flow = kzalloc(flow_size, GFP_KERNEL); | |
2997 | if (!flow) | |
2998 | return -ENOMEM; | |
2999 | flow->port = mqp->port; | |
3000 | flow->num_of_specs = 1; | |
3001 | flow->size = flow_size; | |
3002 | ib_spec = (struct ib_flow_spec_ib *)(flow + 1); | |
3003 | ib_spec->type = IB_FLOW_SPEC_IB; | |
3004 | ib_spec->size = sizeof(struct ib_flow_spec_ib); | |
3005 | /* Add an empty rule for IB L2 */ | |
3006 | memset(&ib_spec->mask, 0, sizeof(ib_spec->mask)); | |
3007 | ||
3008 | err = __mlx4_ib_create_flow(&mqp->ibqp, flow, | |
3009 | IB_FLOW_DOMAIN_NIC, | |
3010 | MLX4_FS_REGULAR, | |
3011 | &mqp->reg_id); | |
3012 | } else { | |
3013 | err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id); | |
3014 | } | |
3015 | kfree(flow); | |
3016 | return err; | |
3017 | } | |
3018 | ||
225c7b1f RD |
3019 | static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr) |
3020 | { | |
3021 | struct mlx4_ib_dev *ibdev = ibdev_ptr; | |
3022 | int p; | |
09d4d087 | 3023 | int i; |
225c7b1f | 3024 | |
09d4d087 JP |
3025 | mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) |
3026 | devlink_port_type_clear(mlx4_get_devlink_port(dev, i)); | |
4bf9715f MS |
3027 | ibdev->ib_active = false; |
3028 | flush_workqueue(wq); | |
3029 | ||
fc06573d | 3030 | mlx4_ib_close_sriov(ibdev); |
a6a47771 YP |
3031 | mlx4_ib_mad_cleanup(ibdev); |
3032 | ib_unregister_device(&ibdev->ib_dev); | |
3f85f2aa | 3033 | mlx4_ib_diag_cleanup(ibdev); |
fa417f7b EC |
3034 | if (ibdev->iboe.nb.notifier_call) { |
3035 | if (unregister_netdevice_notifier(&ibdev->iboe.nb)) | |
987c8f8f | 3036 | pr_warn("failure unregistering notifier\n"); |
fa417f7b EC |
3037 | ibdev->iboe.nb.notifier_call = NULL; |
3038 | } | |
c1c98501 MB |
3039 | |
3040 | if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED) { | |
3041 | mlx4_qp_release_range(dev, ibdev->steer_qpn_base, | |
3042 | ibdev->steer_qpn_count); | |
3043 | kfree(ibdev->ib_uc_qpns_bitmap); | |
3044 | } | |
3045 | ||
fa417f7b | 3046 | iounmap(ibdev->uar_map); |
cfcde11c | 3047 | for (p = 0; p < ibdev->num_ports; ++p) |
3ba8e31d EBE |
3048 | mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]); |
3049 | ||
fa417f7b | 3050 | mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB) |
225c7b1f RD |
3051 | mlx4_CLOSE_PORT(dev, p); |
3052 | ||
e605b743 SP |
3053 | mlx4_ib_free_eqs(dev, ibdev); |
3054 | ||
225c7b1f RD |
3055 | mlx4_uar_free(dev, &ibdev->priv_uar); |
3056 | mlx4_pd_free(dev, ibdev->priv_pdn); | |
3057 | ib_dealloc_device(&ibdev->ib_dev); | |
3058 | } | |
3059 | ||
fc06573d JM |
3060 | static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init) |
3061 | { | |
3062 | struct mlx4_ib_demux_work **dm = NULL; | |
3063 | struct mlx4_dev *dev = ibdev->dev; | |
3064 | int i; | |
3065 | unsigned long flags; | |
449fc488 MB |
3066 | struct mlx4_active_ports actv_ports; |
3067 | unsigned int ports; | |
3068 | unsigned int first_port; | |
fc06573d JM |
3069 | |
3070 | if (!mlx4_is_master(dev)) | |
3071 | return; | |
3072 | ||
449fc488 MB |
3073 | actv_ports = mlx4_get_active_ports(dev, slave); |
3074 | ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports); | |
3075 | first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports); | |
3076 | ||
3077 | dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC); | |
15d4626e | 3078 | if (!dm) |
a39a98ff | 3079 | return; |
fc06573d | 3080 | |
449fc488 | 3081 | for (i = 0; i < ports; i++) { |
fc06573d JM |
3082 | dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC); |
3083 | if (!dm[i]) { | |
a39a98ff MS |
3084 | while (--i >= 0) |
3085 | kfree(dm[i]); | |
fc06573d JM |
3086 | goto out; |
3087 | } | |
fc06573d | 3088 | INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work); |
449fc488 | 3089 | dm[i]->port = first_port + i + 1; |
fc06573d JM |
3090 | dm[i]->slave = slave; |
3091 | dm[i]->do_init = do_init; | |
3092 | dm[i]->dev = ibdev; | |
d9a047ae DL |
3093 | } |
3094 | /* initialize or tear down tunnel QPs for the slave */ | |
3095 | spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags); | |
3096 | if (!ibdev->sriov.is_going_down) { | |
3097 | for (i = 0; i < ports; i++) | |
fc06573d JM |
3098 | queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work); |
3099 | spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags); | |
d9a047ae DL |
3100 | } else { |
3101 | spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags); | |
3102 | for (i = 0; i < ports; i++) | |
3103 | kfree(dm[i]); | |
fc06573d JM |
3104 | } |
3105 | out: | |
c89d1271 | 3106 | kfree(dm); |
fc06573d JM |
3107 | return; |
3108 | } | |
3109 | ||
35f05dab YH |
3110 | static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev) |
3111 | { | |
3112 | struct mlx4_ib_qp *mqp; | |
3113 | unsigned long flags_qp; | |
3114 | unsigned long flags_cq; | |
3115 | struct mlx4_ib_cq *send_mcq, *recv_mcq; | |
3116 | struct list_head cq_notify_list; | |
3117 | struct mlx4_cq *mcq; | |
3118 | unsigned long flags; | |
3119 | ||
3120 | pr_warn("mlx4_ib_handle_catas_error was started\n"); | |
3121 | INIT_LIST_HEAD(&cq_notify_list); | |
3122 | ||
3123 | /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ | |
3124 | spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); | |
3125 | ||
3126 | list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { | |
3127 | spin_lock_irqsave(&mqp->sq.lock, flags_qp); | |
3128 | if (mqp->sq.tail != mqp->sq.head) { | |
3129 | send_mcq = to_mcq(mqp->ibqp.send_cq); | |
3130 | spin_lock_irqsave(&send_mcq->lock, flags_cq); | |
3131 | if (send_mcq->mcq.comp && | |
3132 | mqp->ibqp.send_cq->comp_handler) { | |
3133 | if (!send_mcq->mcq.reset_notify_added) { | |
3134 | send_mcq->mcq.reset_notify_added = 1; | |
3135 | list_add_tail(&send_mcq->mcq.reset_notify, | |
3136 | &cq_notify_list); | |
3137 | } | |
3138 | } | |
3139 | spin_unlock_irqrestore(&send_mcq->lock, flags_cq); | |
3140 | } | |
3141 | spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); | |
3142 | /* Now, handle the QP's receive queue */ | |
3143 | spin_lock_irqsave(&mqp->rq.lock, flags_qp); | |
3144 | /* no handling is needed for SRQ */ | |
3145 | if (!mqp->ibqp.srq) { | |
3146 | if (mqp->rq.tail != mqp->rq.head) { | |
3147 | recv_mcq = to_mcq(mqp->ibqp.recv_cq); | |
3148 | spin_lock_irqsave(&recv_mcq->lock, flags_cq); | |
3149 | if (recv_mcq->mcq.comp && | |
3150 | mqp->ibqp.recv_cq->comp_handler) { | |
3151 | if (!recv_mcq->mcq.reset_notify_added) { | |
3152 | recv_mcq->mcq.reset_notify_added = 1; | |
3153 | list_add_tail(&recv_mcq->mcq.reset_notify, | |
3154 | &cq_notify_list); | |
3155 | } | |
3156 | } | |
3157 | spin_unlock_irqrestore(&recv_mcq->lock, | |
3158 | flags_cq); | |
3159 | } | |
3160 | } | |
3161 | spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); | |
3162 | } | |
3163 | ||
3164 | list_for_each_entry(mcq, &cq_notify_list, reset_notify) { | |
3165 | mcq->comp(mcq); | |
3166 | } | |
3167 | spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); | |
3168 | pr_warn("mlx4_ib_handle_catas_error ended\n"); | |
3169 | } | |
3170 | ||
a5750090 MS |
3171 | static void handle_bonded_port_state_event(struct work_struct *work) |
3172 | { | |
3173 | struct ib_event_work *ew = | |
3174 | container_of(work, struct ib_event_work, work); | |
3175 | struct mlx4_ib_dev *ibdev = ew->ib_dev; | |
3176 | enum ib_port_state bonded_port_state = IB_PORT_NOP; | |
3177 | int i; | |
3178 | struct ib_event ibev; | |
3179 | ||
3180 | kfree(ew); | |
3181 | spin_lock_bh(&ibdev->iboe.lock); | |
3182 | for (i = 0; i < MLX4_MAX_PORTS; ++i) { | |
3183 | struct net_device *curr_netdev = ibdev->iboe.netdevs[i]; | |
217e8b16 | 3184 | enum ib_port_state curr_port_state; |
a5750090 | 3185 | |
217e8b16 MS |
3186 | if (!curr_netdev) |
3187 | continue; | |
3188 | ||
3189 | curr_port_state = | |
a5750090 MS |
3190 | (netif_running(curr_netdev) && |
3191 | netif_carrier_ok(curr_netdev)) ? | |
3192 | IB_PORT_ACTIVE : IB_PORT_DOWN; | |
3193 | ||
3194 | bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ? | |
3195 | curr_port_state : IB_PORT_ACTIVE; | |
3196 | } | |
3197 | spin_unlock_bh(&ibdev->iboe.lock); | |
3198 | ||
3199 | ibev.device = &ibdev->ib_dev; | |
3200 | ibev.element.port_num = 1; | |
3201 | ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ? | |
3202 | IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; | |
3203 | ||
3204 | ib_dispatch_event(&ibev); | |
3205 | } | |
3206 | ||
fd10ed8e JM |
3207 | void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port) |
3208 | { | |
3209 | u64 sl2vl; | |
3210 | int err; | |
3211 | ||
3212 | err = mlx4_ib_query_sl2vl(&mdev->ib_dev, port, &sl2vl); | |
3213 | if (err) { | |
3214 | pr_err("Unable to get current sl to vl mapping for port %d. Using all zeroes (%d)\n", | |
3215 | port, err); | |
3216 | sl2vl = 0; | |
3217 | } | |
3218 | atomic64_set(&mdev->sl2vl[port - 1], sl2vl); | |
3219 | } | |
3220 | ||
3221 | static void ib_sl2vl_update_work(struct work_struct *work) | |
3222 | { | |
3223 | struct ib_event_work *ew = container_of(work, struct ib_event_work, work); | |
3224 | struct mlx4_ib_dev *mdev = ew->ib_dev; | |
3225 | int port = ew->port; | |
3226 | ||
3227 | mlx4_ib_sl2vl_update(mdev, port); | |
3228 | ||
3229 | kfree(ew); | |
3230 | } | |
3231 | ||
3232 | void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev, | |
3233 | int port) | |
3234 | { | |
3235 | struct ib_event_work *ew; | |
3236 | ||
3237 | ew = kmalloc(sizeof(*ew), GFP_ATOMIC); | |
3238 | if (ew) { | |
3239 | INIT_WORK(&ew->work, ib_sl2vl_update_work); | |
3240 | ew->port = port; | |
3241 | ew->ib_dev = ibdev; | |
3242 | queue_work(wq, &ew->work); | |
fd10ed8e JM |
3243 | } |
3244 | } | |
3245 | ||
225c7b1f | 3246 | static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr, |
00f5ce99 | 3247 | enum mlx4_dev_event event, unsigned long param) |
225c7b1f RD |
3248 | { |
3249 | struct ib_event ibev; | |
7ff93f8b | 3250 | struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr); |
00f5ce99 JM |
3251 | struct mlx4_eqe *eqe = NULL; |
3252 | struct ib_event_work *ew; | |
fc06573d | 3253 | int p = 0; |
00f5ce99 | 3254 | |
a5750090 MS |
3255 | if (mlx4_is_bonded(dev) && |
3256 | ((event == MLX4_DEV_EVENT_PORT_UP) || | |
3257 | (event == MLX4_DEV_EVENT_PORT_DOWN))) { | |
3258 | ew = kmalloc(sizeof(*ew), GFP_ATOMIC); | |
3259 | if (!ew) | |
3260 | return; | |
3261 | INIT_WORK(&ew->work, handle_bonded_port_state_event); | |
3262 | ew->ib_dev = ibdev; | |
3263 | queue_work(wq, &ew->work); | |
3264 | return; | |
3265 | } | |
3266 | ||
00f5ce99 JM |
3267 | if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE) |
3268 | eqe = (struct mlx4_eqe *)param; | |
3269 | else | |
fc06573d | 3270 | p = (int) param; |
225c7b1f RD |
3271 | |
3272 | switch (event) { | |
37608eea | 3273 | case MLX4_DEV_EVENT_PORT_UP: |
fc06573d JM |
3274 | if (p > ibdev->num_ports) |
3275 | return; | |
fd10ed8e | 3276 | if (!mlx4_is_slave(dev) && |
a0c64a17 JM |
3277 | rdma_port_get_link_layer(&ibdev->ib_dev, p) == |
3278 | IB_LINK_LAYER_INFINIBAND) { | |
fd10ed8e JM |
3279 | if (mlx4_is_master(dev)) |
3280 | mlx4_ib_invalidate_all_guid_record(ibdev, p); | |
3281 | if (ibdev->dev->flags & MLX4_FLAG_SECURE_HOST && | |
3282 | !(ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT)) | |
3283 | mlx4_sched_ib_sl2vl_update_work(ibdev, p); | |
a0c64a17 | 3284 | } |
37608eea | 3285 | ibev.event = IB_EVENT_PORT_ACTIVE; |
225c7b1f RD |
3286 | break; |
3287 | ||
37608eea | 3288 | case MLX4_DEV_EVENT_PORT_DOWN: |
fc06573d JM |
3289 | if (p > ibdev->num_ports) |
3290 | return; | |
37608eea RD |
3291 | ibev.event = IB_EVENT_PORT_ERR; |
3292 | break; | |
3293 | ||
3294 | case MLX4_DEV_EVENT_CATASTROPHIC_ERROR: | |
3b4a8cd5 | 3295 | ibdev->ib_active = false; |
225c7b1f | 3296 | ibev.event = IB_EVENT_DEVICE_FATAL; |
35f05dab | 3297 | mlx4_ib_handle_catas_error(ibdev); |
225c7b1f RD |
3298 | break; |
3299 | ||
00f5ce99 JM |
3300 | case MLX4_DEV_EVENT_PORT_MGMT_CHANGE: |
3301 | ew = kmalloc(sizeof *ew, GFP_ATOMIC); | |
15d4626e | 3302 | if (!ew) |
00f5ce99 | 3303 | break; |
00f5ce99 JM |
3304 | |
3305 | INIT_WORK(&ew->work, handle_port_mgmt_change_event); | |
3306 | memcpy(&ew->ib_eqe, eqe, sizeof *eqe); | |
3307 | ew->ib_dev = ibdev; | |
992e8e6e JM |
3308 | /* need to queue only for port owner, which uses GEN_EQE */ |
3309 | if (mlx4_is_master(dev)) | |
3310 | queue_work(wq, &ew->work); | |
3311 | else | |
3312 | handle_port_mgmt_change_event(&ew->work); | |
00f5ce99 JM |
3313 | return; |
3314 | ||
fc06573d JM |
3315 | case MLX4_DEV_EVENT_SLAVE_INIT: |
3316 | /* here, p is the slave id */ | |
3317 | do_slave_init(ibdev, p, 1); | |
ee59fa0d YH |
3318 | if (mlx4_is_master(dev)) { |
3319 | int i; | |
3320 | ||
3321 | for (i = 1; i <= ibdev->num_ports; i++) { | |
3322 | if (rdma_port_get_link_layer(&ibdev->ib_dev, i) | |
3323 | == IB_LINK_LAYER_INFINIBAND) | |
3324 | mlx4_ib_slave_alias_guid_event(ibdev, | |
3325 | p, i, | |
3326 | 1); | |
3327 | } | |
3328 | } | |
fc06573d JM |
3329 | return; |
3330 | ||
3331 | case MLX4_DEV_EVENT_SLAVE_SHUTDOWN: | |
ee59fa0d YH |
3332 | if (mlx4_is_master(dev)) { |
3333 | int i; | |
3334 | ||
3335 | for (i = 1; i <= ibdev->num_ports; i++) { | |
3336 | if (rdma_port_get_link_layer(&ibdev->ib_dev, i) | |
3337 | == IB_LINK_LAYER_INFINIBAND) | |
3338 | mlx4_ib_slave_alias_guid_event(ibdev, | |
3339 | p, i, | |
3340 | 0); | |
3341 | } | |
3342 | } | |
fc06573d JM |
3343 | /* here, p is the slave id */ |
3344 | do_slave_init(ibdev, p, 0); | |
3345 | return; | |
3346 | ||
225c7b1f RD |
3347 | default: |
3348 | return; | |
3349 | } | |
3350 | ||
3351 | ibev.device = ibdev_ptr; | |
a5750090 | 3352 | ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p; |
225c7b1f RD |
3353 | |
3354 | ib_dispatch_event(&ibev); | |
3355 | } | |
3356 | ||
3357 | static struct mlx4_interface mlx4_ib_interface = { | |
fa417f7b EC |
3358 | .add = mlx4_ib_add, |
3359 | .remove = mlx4_ib_remove, | |
3360 | .event = mlx4_ib_event, | |
a5750090 MS |
3361 | .protocol = MLX4_PROT_IB_IPV6, |
3362 | .flags = MLX4_INTFF_BONDING | |
225c7b1f RD |
3363 | }; |
3364 | ||
3365 | static int __init mlx4_ib_init(void) | |
3366 | { | |
fa417f7b EC |
3367 | int err; |
3368 | ||
41cd3944 | 3369 | wq = alloc_ordered_workqueue("mlx4_ib", WQ_MEM_RECLAIM); |
fa417f7b EC |
3370 | if (!wq) |
3371 | return -ENOMEM; | |
3372 | ||
b9c5d6a6 OD |
3373 | err = mlx4_ib_mcg_init(); |
3374 | if (err) | |
3375 | goto clean_wq; | |
3376 | ||
fa417f7b | 3377 | err = mlx4_register_interface(&mlx4_ib_interface); |
b9c5d6a6 OD |
3378 | if (err) |
3379 | goto clean_mcg; | |
fa417f7b EC |
3380 | |
3381 | return 0; | |
b9c5d6a6 OD |
3382 | |
3383 | clean_mcg: | |
3384 | mlx4_ib_mcg_destroy(); | |
3385 | ||
3386 | clean_wq: | |
3387 | destroy_workqueue(wq); | |
3388 | return err; | |
225c7b1f RD |
3389 | } |
3390 | ||
3391 | static void __exit mlx4_ib_cleanup(void) | |
3392 | { | |
3393 | mlx4_unregister_interface(&mlx4_ib_interface); | |
b9c5d6a6 | 3394 | mlx4_ib_mcg_destroy(); |
fa417f7b | 3395 | destroy_workqueue(wq); |
225c7b1f RD |
3396 | } |
3397 | ||
3398 | module_init(mlx4_ib_init); | |
3399 | module_exit(mlx4_ib_cleanup); |