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[mirror_ubuntu-eoan-kernel.git] / drivers / infiniband / hw / mlx4 / main.c
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225c7b1f
RD		 1/*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34#include <linux/module.h>
35#include <linux/init.h>
5a0e3ad6 36#include <linux/slab.h>
225c7b1f 37#include <linux/errno.h>
fa417f7b
EC		 38#include <linux/netdevice.h>
39#include <linux/inetdevice.h>
40#include <linux/rtnetlink.h>
4c3eb3ca 41#include <linux/if_vlan.h>
6e84f315 42#include <linux/sched/mm.h>
0881e7bd 43#include <linux/sched/task.h>
6e84f315 44
d487ee77
MS		 45#include <net/ipv6.h>
46#include <net/addrconf.h>
09d4d087 47#include <net/devlink.h>
225c7b1f
RD		 48
49#include <rdma/ib_smi.h>
50#include <rdma/ib_user_verbs.h>
fa417f7b 51#include <rdma/ib_addr.h>
e26be1bf
MS		 52#include <rdma/ib_cache.h>
53
54#include <net/bonding.h>
225c7b1f
RD		 55
56#include <linux/mlx4/driver.h>
57#include <linux/mlx4/cmd.h>
9433c188 58#include <linux/mlx4/qp.h>
225c7b1f
RD		 59
60#include "mlx4_ib.h"
9ce28a20 61#include <rdma/mlx4-abi.h>
225c7b1f 62
b1d8eb5a 63#define DRV_NAME MLX4_IB_DRV_NAME
0a528ee9 64#define DRV_VERSION "4.0-0"
225c7b1f 65
f77c0162 66#define MLX4_IB_FLOW_MAX_PRIO 0xFFF
a37a1a42 67#define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF
50e2ec91 68#define MLX4_IB_CARD_REV_A0 0xA0
f77c0162 69
225c7b1f
RD		 70MODULE_AUTHOR("Roland Dreier");
71MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver");
72MODULE_LICENSE("Dual BSD/GPL");
225c7b1f 73
56c1d233 74int mlx4_ib_sm_guid_assign = 0;
a0c64a17 75module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444);
56c1d233 76MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)");
a0c64a17 77
68f3948d 78static const char mlx4_ib_version[] =
225c7b1f 79 DRV_NAME ": Mellanox ConnectX InfiniBand driver v"
0a528ee9 80 DRV_VERSION "\n";
225c7b1f 81
3806d08c 82static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init);
400b1ebc
GL		 83static enum rdma_link_layer mlx4_ib_port_link_layer(struct ib_device *device,
84 u8 port_num);
3806d08c 85
fa417f7b
EC		 86static struct workqueue_struct *wq;
87
225c7b1f
RD		 88static void init_query_mad(struct ib_smp *mad)
89{
90 mad->base_version = 1;
91 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
92 mad->class_version = 1;
93 mad->method = IB_MGMT_METHOD_GET;
94}
95
f77c0162
HHZ		 96static int check_flow_steering_support(struct mlx4_dev *dev)
97{
0a9b7d59 98 int eth_num_ports = 0;
f77c0162 99 int ib_num_ports = 0;
f77c0162 100
0a9b7d59
MB		 101 int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED;
102
103 if (dmfs) {
104 int i;
105 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH)
106 eth_num_ports++;
107 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
108 ib_num_ports++;
109 dmfs &= (!ib_num_ports ||
110 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) &&
111 (!eth_num_ports ||
112 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN));
113 if (ib_num_ports && mlx4_is_mfunc(dev)) {
114 pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n");
115 dmfs = 0;
f77c0162 116 }
f77c0162 117 }
0a9b7d59 118 return dmfs;
f77c0162
HHZ		 119}
120
3dec4878
JM		 121static int num_ib_ports(struct mlx4_dev *dev)
122{
123 int ib_ports = 0;
124 int i;
125
126 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
127 ib_ports++;
128
129 return ib_ports;
130}
131
e26be1bf
MS		 132static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num)
133{
134 struct mlx4_ib_dev *ibdev = to_mdev(device);
135 struct net_device *dev;
136
137 rcu_read_lock();
138 dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num);
139
140 if (dev) {
141 if (mlx4_is_bonded(ibdev->dev)) {
142 struct net_device *upper = NULL;
143
144 upper = netdev_master_upper_dev_get_rcu(dev);
145 if (upper) {
146 struct net_device *active;
147
148 active = bond_option_active_slave_get_rcu(netdev_priv(upper));
149 if (active)
150 dev = active;
151 }
152 }
153 }
154 if (dev)
155 dev_hold(dev);
156
157 rcu_read_unlock();
158 return dev;
159}
160
7e57b85c
MS		 161static int mlx4_ib_update_gids_v1(struct gid_entry *gids,
162 struct mlx4_ib_dev *ibdev,
163 u8 port_num)
e26be1bf
MS		 164{
165 struct mlx4_cmd_mailbox *mailbox;
166 int err;
167 struct mlx4_dev *dev = ibdev->dev;
168 int i;
169 union ib_gid *gid_tbl;
170
171 mailbox = mlx4_alloc_cmd_mailbox(dev);
172 if (IS_ERR(mailbox))
173 return -ENOMEM;
174
175 gid_tbl = mailbox->buf;
176
177 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
178 memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid));
179
180 err = mlx4_cmd(dev, mailbox->dma,
181 MLX4_SET_PORT_GID_TABLE << 8 | port_num,
182 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
183 MLX4_CMD_WRAPPED);
184 if (mlx4_is_bonded(dev))
185 err += mlx4_cmd(dev, mailbox->dma,
186 MLX4_SET_PORT_GID_TABLE << 8 | 2,
187 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
188 MLX4_CMD_WRAPPED);
189
190 mlx4_free_cmd_mailbox(dev, mailbox);
191 return err;
192}
193
7e57b85c
MS		 194static int mlx4_ib_update_gids_v1_v2(struct gid_entry *gids,
195 struct mlx4_ib_dev *ibdev,
196 u8 port_num)
197{
198 struct mlx4_cmd_mailbox *mailbox;
199 int err;
200 struct mlx4_dev *dev = ibdev->dev;
201 int i;
202 struct {
203 union ib_gid gid;
204 __be32 rsrvd1[2];
205 __be16 rsrvd2;
206 u8 type;
207 u8 version;
208 __be32 rsrvd3;
209 } *gid_tbl;
210
211 mailbox = mlx4_alloc_cmd_mailbox(dev);
212 if (IS_ERR(mailbox))
213 return -ENOMEM;
214
215 gid_tbl = mailbox->buf;
216 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
217 memcpy(&gid_tbl[i].gid, &gids[i].gid, sizeof(union ib_gid));
218 if (gids[i].gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
219 gid_tbl[i].version = 2;
220 if (!ipv6_addr_v4mapped((struct in6_addr *)&gids[i].gid))
221 gid_tbl[i].type = 1;
7e57b85c
MS		 222 }
223 }
224
225 err = mlx4_cmd(dev, mailbox->dma,
226 MLX4_SET_PORT_ROCE_ADDR << 8 | port_num,
227 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
228 MLX4_CMD_WRAPPED);
229 if (mlx4_is_bonded(dev))
230 err += mlx4_cmd(dev, mailbox->dma,
231 MLX4_SET_PORT_ROCE_ADDR << 8 | 2,
232 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
233 MLX4_CMD_WRAPPED);
234
235 mlx4_free_cmd_mailbox(dev, mailbox);
236 return err;
237}
238
239static int mlx4_ib_update_gids(struct gid_entry *gids,
240 struct mlx4_ib_dev *ibdev,
241 u8 port_num)
242{
243 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
244 return mlx4_ib_update_gids_v1_v2(gids, ibdev, port_num);
245
246 return mlx4_ib_update_gids_v1(gids, ibdev, port_num);
247}
248
414448d2 249static int mlx4_ib_add_gid(const union ib_gid *gid,
e26be1bf
MS		 250 const struct ib_gid_attr *attr,
251 void **context)
252{
414448d2 253 struct mlx4_ib_dev *ibdev = to_mdev(attr->device);
e26be1bf
MS		 254 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
255 struct mlx4_port_gid_table *port_gid_table;
256 int free = -1, found = -1;
257 int ret = 0;
258 int hw_update = 0;
259 int i;
260 struct gid_entry *gids = NULL;
261
414448d2 262 if (!rdma_cap_roce_gid_table(attr->device, attr->port_num))
e26be1bf
MS		 263 return -EINVAL;
264
414448d2 265 if (attr->port_num > MLX4_MAX_PORTS)
e26be1bf
MS		 266 return -EINVAL;
267
268 if (!context)
269 return -EINVAL;
270
414448d2 271 port_gid_table = &iboe->gids[attr->port_num - 1];
e26be1bf
MS		 272 spin_lock_bh(&iboe->lock);
273 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
b699a859
MS		 274 if (!memcmp(&port_gid_table->gids[i].gid, gid, sizeof(*gid)) &&
275 (port_gid_table->gids[i].gid_type == attr->gid_type)) {
e26be1bf
MS		 276 found = i;
277 break;
278 }
25e62655 279 if (free < 0 && rdma_is_zero_gid(&port_gid_table->gids[i].gid))
e26be1bf
MS		 280 free = i; /* HW has space */
281 }
282
283 if (found < 0) {
284 if (free < 0) {
285 ret = -ENOSPC;
286 } else {
287 port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC);
288 if (!port_gid_table->gids[free].ctx) {
289 ret = -ENOMEM;
290 } else {
291 *context = port_gid_table->gids[free].ctx;
292 memcpy(&port_gid_table->gids[free].gid, gid, sizeof(*gid));
b699a859 293 port_gid_table->gids[free].gid_type = attr->gid_type;
e26be1bf
MS		 294 port_gid_table->gids[free].ctx->real_index = free;
295 port_gid_table->gids[free].ctx->refcount = 1;
296 hw_update = 1;
297 }
298 }
299 } else {
300 struct gid_cache_context *ctx = port_gid_table->gids[found].ctx;
301 *context = ctx;
302 ctx->refcount++;
303 }
304 if (!ret && hw_update) {
6da2ec56
KC		 305 gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids),
306 GFP_ATOMIC);
e26be1bf
MS		 307 if (!gids) {
308 ret = -ENOMEM;
309 } else {
b699a859 310 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) {
e26be1bf 311 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
b699a859
MS		 312 gids[i].gid_type = port_gid_table->gids[i].gid_type;
313 }
e26be1bf
MS		 314 }
315 }
316 spin_unlock_bh(&iboe->lock);
317
318 if (!ret && hw_update) {
414448d2 319 ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num);
e26be1bf
MS		 320 kfree(gids);
321 }
322
323 return ret;
324}
325
414448d2 326static int mlx4_ib_del_gid(const struct ib_gid_attr *attr, void **context)
e26be1bf
MS		 327{
328 struct gid_cache_context *ctx = *context;
414448d2 329 struct mlx4_ib_dev *ibdev = to_mdev(attr->device);
e26be1bf
MS		 330 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
331 struct mlx4_port_gid_table *port_gid_table;
332 int ret = 0;
333 int hw_update = 0;
334 struct gid_entry *gids = NULL;
335
414448d2 336 if (!rdma_cap_roce_gid_table(attr->device, attr->port_num))
e26be1bf
MS		 337 return -EINVAL;
338
414448d2 339 if (attr->port_num > MLX4_MAX_PORTS)
e26be1bf
MS		 340 return -EINVAL;
341
414448d2 342 port_gid_table = &iboe->gids[attr->port_num - 1];
e26be1bf
MS		 343 spin_lock_bh(&iboe->lock);
344 if (ctx) {
345 ctx->refcount--;
346 if (!ctx->refcount) {
347 unsigned int real_index = ctx->real_index;
348
25e62655
PP		 349 memset(&port_gid_table->gids[real_index].gid, 0,
350 sizeof(port_gid_table->gids[real_index].gid));
e26be1bf
MS		 351 kfree(port_gid_table->gids[real_index].ctx);
352 port_gid_table->gids[real_index].ctx = NULL;
353 hw_update = 1;
354 }
355 }
356 if (!ret && hw_update) {
357 int i;
358
6da2ec56
KC		 359 gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids),
360 GFP_ATOMIC);
e26be1bf
MS		 361 if (!gids) {
362 ret = -ENOMEM;
363 } else {
a1817792
J		 364 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) {
365 memcpy(&gids[i].gid,
366 &port_gid_table->gids[i].gid,
367 sizeof(union ib_gid));
368 gids[i].gid_type =
369 port_gid_table->gids[i].gid_type;
370 }
e26be1bf
MS		 371 }
372 }
373 spin_unlock_bh(&iboe->lock);
374
375 if (!ret && hw_update) {
414448d2 376 ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num);
e26be1bf
MS		 377 kfree(gids);
378 }
379 return ret;
380}
381
382int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev,
383 u8 port_num, int index)
384{
385 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
386 struct gid_cache_context *ctx = NULL;
387 union ib_gid gid;
388 struct mlx4_port_gid_table *port_gid_table;
389 int real_index = -EINVAL;
390 int i;
391 int ret;
392 unsigned long flags;
b699a859 393 struct ib_gid_attr attr;
e26be1bf
MS		 394
395 if (port_num > MLX4_MAX_PORTS)
396 return -EINVAL;
397
398 if (mlx4_is_bonded(ibdev->dev))
399 port_num = 1;
400
401 if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num))
402 return index;
403
b699a859 404 ret = ib_get_cached_gid(&ibdev->ib_dev, port_num, index, &gid, &attr);
e26be1bf
MS		 405 if (ret)
406 return ret;
407
b699a859
MS		 408 if (attr.ndev)
409 dev_put(attr.ndev);
410
e26be1bf
MS		 411 spin_lock_irqsave(&iboe->lock, flags);
412 port_gid_table = &iboe->gids[port_num - 1];
413
414 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
b699a859
MS		 415 if (!memcmp(&port_gid_table->gids[i].gid, &gid, sizeof(gid)) &&
416 attr.gid_type == port_gid_table->gids[i].gid_type) {
e26be1bf
MS		 417 ctx = port_gid_table->gids[i].ctx;
418 break;
419 }
420 if (ctx)
421 real_index = ctx->real_index;
422 spin_unlock_irqrestore(&iboe->lock, flags);
423 return real_index;
424}
425
9c71172c
YH		 426#define field_avail(type, fld, sz) (offsetof(type, fld) + \
427 sizeof(((type *)0)->fld) <= (sz))
428
225c7b1f 429static int mlx4_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 430 struct ib_device_attr *props,
431 struct ib_udata *uhw)
225c7b1f
RD		 432{
433 struct mlx4_ib_dev *dev = to_mdev(ibdev);
434 struct ib_smp *in_mad = NULL;
435 struct ib_smp *out_mad = NULL;
46d0703f 436 int err;
3dec4878 437 int have_ib_ports;
4b664c43
MB		 438 struct mlx4_uverbs_ex_query_device cmd;
439 struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0};
440 struct mlx4_clock_params clock_params;
225c7b1f 441
4b664c43
MB		 442 if (uhw->inlen) {
443 if (uhw->inlen < sizeof(cmd))
444 return -EINVAL;
445
446 err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd));
447 if (err)
448 return err;
449
450 if (cmd.comp_mask)
451 return -EINVAL;
452
453 if (cmd.reserved)
454 return -EINVAL;
455 }
2528e33e 456
4b664c43
MB		 457 resp.response_length = offsetof(typeof(resp), response_length) +
458 sizeof(resp.response_length);
225c7b1f
RD		 459 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
460 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
46d0703f 461 err = -ENOMEM;
225c7b1f
RD		 462 if (!in_mad || !out_mad)
463 goto out;
464
465 init_query_mad(in_mad);
466 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
467
0a9a0188
JM		 468 err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS,
469 1, NULL, NULL, in_mad, out_mad);
225c7b1f
RD		 470 if (err)
471 goto out;
472
473 memset(props, 0, sizeof *props);
474
3dec4878
JM		 475 have_ib_ports = num_ib_ports(dev->dev);
476
225c7b1f
RD		 477 props->fw_ver = dev->dev->caps.fw_ver;
478 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
479 IB_DEVICE_PORT_ACTIVE_EVENT |
480 IB_DEVICE_SYS_IMAGE_GUID |
521e575b
RL		 481 IB_DEVICE_RC_RNR_NAK_GEN |
482 IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
225c7b1f
RD		 483 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR)
484 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
485 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR)
486 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
3dec4878 487 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports)
225c7b1f
RD		 488 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
489 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT)
490 props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
8ff095ec
EC		 491 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
492 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
50e2ec91
MS		 493 if (dev->dev->caps.max_gso_sz &&
494 (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) &&
495 (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH))
b832be1e 496 props->device_cap_flags |= IB_DEVICE_UD_TSO;
95d04f07
RD		 497 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY)
498 props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY;
499 if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) &&
500 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) &&
501 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR))
502 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
0a1405da
SH		 503 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)
504 props->device_cap_flags |= IB_DEVICE_XRC;
b425388d
SM		 505 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW)
506 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW;
507 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
508 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B)
509 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B;
510 else
511 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A;
512 }
ca920f5b
BVA		 513 if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
514 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
225c7b1f 515
070b3997
BW		 516 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
517
225c7b1f
RD		 518 props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) &
519 0xffffff;
872bf2fb 520 props->vendor_part_id = dev->dev->persist->pdev->device;
225c7b1f
RD		 521 props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32));
522 memcpy(&props->sys_image_guid, out_mad->data + 4, 8);
523
524 props->max_mr_size = ~0ull;
525 props->page_size_cap = dev->dev->caps.page_size_cap;
5a0d0a61 526 props->max_qp = dev->dev->quotas.qp;
fc2d0044 527 props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE;
225c7b1f
RD		 528 props->max_sge = min(dev->dev->caps.max_sq_sg,
529 dev->dev->caps.max_rq_sg);
a5e14ba3 530 props->max_sge_rd = MLX4_MAX_SGE_RD;
5a0d0a61 531 props->max_cq = dev->dev->quotas.cq;
225c7b1f 532 props->max_cqe = dev->dev->caps.max_cqes;
5a0d0a61 533 props->max_mr = dev->dev->quotas.mpt;
225c7b1f
RD		 534 props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds;
535 props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma;
536 props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma;
537 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
5a0d0a61 538 props->max_srq = dev->dev->quotas.srq;
c8681f14 539 props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1;
225c7b1f 540 props->max_srq_sge = dev->dev->caps.max_srq_sge;
5a0fd094 541 props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES;
225c7b1f
RD		 542 props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay;
543 props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ?
544 IB_ATOMIC_HCA : IB_ATOMIC_NONE;
47e956b2 545 props->masked_atomic_cap = props->atomic_cap;
5ae2a7a8 546 props->max_pkeys = dev->dev->caps.pkey_table_len[1];
225c7b1f
RD		 547 props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms;
548 props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm;
549 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
550 props->max_mcast_grp;
a5bbe892 551 props->max_map_per_fmr = dev->dev->caps.max_fmr_maps;
4b664c43
MB		 552 props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL;
553 props->timestamp_mask = 0xFFFFFFFFFFFFULL;
731e0415 554 props->max_ah = INT_MAX;
225c7b1f 555
6d06c9aa
GL		 556 if (mlx4_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET ||
557 mlx4_ib_port_link_layer(ibdev, 2) == IB_LINK_LAYER_ETHERNET) {
558 if (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) {
559 props->rss_caps.max_rwq_indirection_tables =
560 props->max_qp;
561 props->rss_caps.max_rwq_indirection_table_size =
562 dev->dev->caps.max_rss_tbl_sz;
563 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
564 props->max_wq_type_rq = props->max_qp;
565 }
566
567 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)
568 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
6afff1c7 569 }
400b1ebc 570
0fd586de
YC		 571 props->cq_caps.max_cq_moderation_count = MLX4_MAX_CQ_COUNT;
572 props->cq_caps.max_cq_moderation_period = MLX4_MAX_CQ_PERIOD;
573
8a7ff14d
MB		 574 if (!mlx4_is_slave(dev->dev))
575 err = mlx4_get_internal_clock_params(dev->dev, &clock_params);
4b664c43
MB		 576
577 if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) {
4b664c43 578 resp.response_length += sizeof(resp.hca_core_clock_offset);
8a7ff14d 579 if (!err && !mlx4_is_slave(dev->dev)) {
48962f5c 580 resp.comp_mask |= MLX4_IB_QUERY_DEV_RESP_MASK_CORE_CLOCK_OFFSET;
8a7ff14d
MB		 581 resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE;
582 }
4b664c43
MB		 583 }
584
ea30b966
MG		 585 if (uhw->outlen >= resp.response_length +
586 sizeof(resp.max_inl_recv_sz)) {
587 resp.response_length += sizeof(resp.max_inl_recv_sz);
588 resp.max_inl_recv_sz = dev->dev->caps.max_rq_sg *
589 sizeof(struct mlx4_wqe_data_seg);
590 }
591
9c71172c 592 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
09d208b2
GL		 593 if (props->rss_caps.supported_qpts) {
594 resp.rss_caps.rx_hash_function =
595 MLX4_IB_RX_HASH_FUNC_TOEPLITZ;
07d84f7b 596
09d208b2
GL		 597 resp.rss_caps.rx_hash_fields_mask =
598 MLX4_IB_RX_HASH_SRC_IPV4 |
599 MLX4_IB_RX_HASH_DST_IPV4 |
600 MLX4_IB_RX_HASH_SRC_IPV6 |
601 MLX4_IB_RX_HASH_DST_IPV6 |
602 MLX4_IB_RX_HASH_SRC_PORT_TCP |
603 MLX4_IB_RX_HASH_DST_PORT_TCP |
604 MLX4_IB_RX_HASH_SRC_PORT_UDP |
605 MLX4_IB_RX_HASH_DST_PORT_UDP;
07d84f7b
GL		 606
607 if (dev->dev->caps.tunnel_offload_mode ==
608 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
609 resp.rss_caps.rx_hash_fields_mask |=
610 MLX4_IB_RX_HASH_INNER;
09d208b2 611 }
9c71172c
YH		 612 resp.response_length = offsetof(typeof(resp), rss_caps) +
613 sizeof(resp.rss_caps);
614 }
615
616 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
617 if (dev->dev->caps.max_gso_sz &&
618 ((mlx4_ib_port_link_layer(ibdev, 1) ==
619 IB_LINK_LAYER_ETHERNET) ||
620 (mlx4_ib_port_link_layer(ibdev, 2) ==
621 IB_LINK_LAYER_ETHERNET))) {
622 resp.tso_caps.max_tso = dev->dev->caps.max_gso_sz;
623 resp.tso_caps.supported_qpts |=
624 1 << IB_QPT_RAW_PACKET;
625 }
626 resp.response_length = offsetof(typeof(resp), tso_caps) +
627 sizeof(resp.tso_caps);
09d208b2
GL		 628 }
629
4b664c43
MB		 630 if (uhw->outlen) {
631 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
632 if (err)
633 goto out;
634 }
225c7b1f
RD		 635out:
636 kfree(in_mad);
637 kfree(out_mad);
638
639 return err;
640}
641
fa417f7b
EC		 642static enum rdma_link_layer
643mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num)
225c7b1f 644{
fa417f7b 645 struct mlx4_dev *dev = to_mdev(device)->dev;
225c7b1f 646
65dab25d 647 return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ?
fa417f7b
EC		 648 IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET;
649}
225c7b1f 650
fa417f7b 651static int ib_link_query_port(struct ib_device *ibdev, u8 port,
0a9a0188 652 struct ib_port_attr *props, int netw_view)
fa417f7b 653{
a9c766bb
OG		 654 struct ib_smp *in_mad = NULL;
655 struct ib_smp *out_mad = NULL;
a5e12dff 656 int ext_active_speed;
0a9a0188 657 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
a9c766bb
OG		 658 int err = -ENOMEM;
659
660 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
661 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
662 if (!in_mad || !out_mad)
663 goto out;
664
665 init_query_mad(in_mad);
666 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
667 in_mad->attr_mod = cpu_to_be32(port);
668
0a9a0188
JM		 669 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
670 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
671
672 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
a9c766bb
OG		 673 in_mad, out_mad);
674 if (err)
675 goto out;
676
a5e12dff 677
225c7b1f
RD		 678 props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16));
679 props->lmc = out_mad->data[34] & 0x7;
680 props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18));
681 props->sm_sl = out_mad->data[36] & 0xf;
682 props->state = out_mad->data[32] & 0xf;
683 props->phys_state = out_mad->data[33] >> 4;
684 props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20));
0a9a0188
JM		 685 if (netw_view)
686 props->gid_tbl_len = out_mad->data[50];
687 else
688 props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port];
149983af 689 props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz;
5ae2a7a8 690 props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port];
225c7b1f
RD		 691 props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46));
692 props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48));
693 props->active_width = out_mad->data[31] & 0xf;
694 props->active_speed = out_mad->data[35] >> 4;
695 props->max_mtu = out_mad->data[41] & 0xf;
696 props->active_mtu = out_mad->data[36] >> 4;
697 props->subnet_timeout = out_mad->data[51] & 0x1f;
698 props->max_vl_num = out_mad->data[37] >> 4;
699 props->init_type_reply = out_mad->data[41] >> 4;
700
a5e12dff
MA		 701 /* Check if extended speeds (EDR/FDR/...) are supported */
702 if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) {
703 ext_active_speed = out_mad->data[62] >> 4;
704
705 switch (ext_active_speed) {
706 case 1:
2e96691c 707 props->active_speed = IB_SPEED_FDR;
a5e12dff
MA		 708 break;
709 case 2:
2e96691c 710 props->active_speed = IB_SPEED_EDR;
a5e12dff
MA		 711 break;
712 }
713 }
714
715 /* If reported active speed is QDR, check if is FDR-10 */
2e96691c 716 if (props->active_speed == IB_SPEED_QDR) {
8154c07f
OG		 717 init_query_mad(in_mad);
718 in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO;
719 in_mad->attr_mod = cpu_to_be32(port);
720
0a9a0188 721 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port,
8154c07f
OG		 722 NULL, NULL, in_mad, out_mad);
723 if (err)
bf6b47de 724 goto out;
8154c07f
OG		 725
726 /* Checking LinkSpeedActive for FDR-10 */
727 if (out_mad->data[15] & 0x1)
728 props->active_speed = IB_SPEED_FDR10;
a5e12dff 729 }
d2ef4068
OG		 730
731 /* Avoid wrong speed value returned by FW if the IB link is down. */
732 if (props->state == IB_PORT_DOWN)
733 props->active_speed = IB_SPEED_SDR;
734
a9c766bb
OG		 735out:
736 kfree(in_mad);
737 kfree(out_mad);
738 return err;
fa417f7b
EC		 739}
740
741static u8 state_to_phys_state(enum ib_port_state state)
742{
743 return state == IB_PORT_ACTIVE ? 5 : 3;
744}
745
746static int eth_link_query_port(struct ib_device *ibdev, u8 port,
850b7415 747 struct ib_port_attr *props)
fa417f7b 748{
a9c766bb
OG		 749
750 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
751 struct mlx4_ib_iboe *iboe = &mdev->iboe;
fa417f7b
EC		 752 struct net_device *ndev;
753 enum ib_mtu tmp;
a9c766bb
OG		 754 struct mlx4_cmd_mailbox *mailbox;
755 int err = 0;
a5750090 756 int is_bonded = mlx4_is_bonded(mdev->dev);
a9c766bb
OG		 757
758 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
759 if (IS_ERR(mailbox))
760 return PTR_ERR(mailbox);
fa417f7b 761
a9c766bb
OG		 762 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
763 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
764 MLX4_CMD_WRAPPED);
765 if (err)
766 goto out;
767
6fa26208
SM		 768 props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) ||
769 (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
770 IB_WIDTH_4X : IB_WIDTH_1X;
771 props->active_speed = (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
772 IB_SPEED_FDR : IB_SPEED_QDR;
b4a26a27 773 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_IP_BASED_GIDS;
a9c766bb
OG		 774 props->gid_tbl_len = mdev->dev->caps.gid_table_len[port];
775 props->max_msg_sz = mdev->dev->caps.max_msg_sz;
fa417f7b 776 props->pkey_tbl_len = 1;
bcacb897 777 props->max_mtu = IB_MTU_4096;
a9c766bb 778 props->max_vl_num = 2;
fa417f7b
EC		 779 props->state = IB_PORT_DOWN;
780 props->phys_state = state_to_phys_state(props->state);
781 props->active_mtu = IB_MTU_256;
dba3ad2a 782 spin_lock_bh(&iboe->lock);
fa417f7b 783 ndev = iboe->netdevs[port - 1];
5070cd22
MS		 784 if (ndev && is_bonded) {
785 rcu_read_lock(); /* required to get upper dev */
786 ndev = netdev_master_upper_dev_get_rcu(ndev);
787 rcu_read_unlock();
788 }
fa417f7b 789 if (!ndev)
a9c766bb 790 goto out_unlock;
fa417f7b
EC		 791
792 tmp = iboe_get_mtu(ndev->mtu);
793 props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256;
794
21d60609 795 props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ?
fa417f7b
EC		 796 IB_PORT_ACTIVE : IB_PORT_DOWN;
797 props->phys_state = state_to_phys_state(props->state);
a9c766bb 798out_unlock:
dba3ad2a 799 spin_unlock_bh(&iboe->lock);
a9c766bb
OG		 800out:
801 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
802 return err;
fa417f7b
EC		 803}
804
0a9a0188
JM		 805int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
806 struct ib_port_attr *props, int netw_view)
fa417f7b 807{
a9c766bb 808 int err;
fa417f7b 809
c4550c63 810 /* props being zeroed by the caller, avoid zeroing it here */
fa417f7b 811
fa417f7b 812 err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ?
0a9a0188 813 ib_link_query_port(ibdev, port, props, netw_view) :
850b7415 814 eth_link_query_port(ibdev, port, props);
225c7b1f
RD		 815
816 return err;
817}
818
0a9a0188
JM		 819static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
820 struct ib_port_attr *props)
821{
822 /* returns host view */
823 return __mlx4_ib_query_port(ibdev, port, props, 0);
824}
825
a0c64a17
JM		 826int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
827 union ib_gid *gid, int netw_view)
225c7b1f
RD		 828{
829 struct ib_smp *in_mad = NULL;
830 struct ib_smp *out_mad = NULL;
831 int err = -ENOMEM;
a0c64a17
JM		 832 struct mlx4_ib_dev *dev = to_mdev(ibdev);
833 int clear = 0;
834 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
225c7b1f
RD		 835
836 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
837 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
838 if (!in_mad || !out_mad)
839 goto out;
840
841 init_query_mad(in_mad);
842 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
843 in_mad->attr_mod = cpu_to_be32(port);
844
a0c64a17
JM		 845 if (mlx4_is_mfunc(dev->dev) && netw_view)
846 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
847
848 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad);
225c7b1f
RD		 849 if (err)
850 goto out;
851
852 memcpy(gid->raw, out_mad->data + 8, 8);
853
a0c64a17
JM		 854 if (mlx4_is_mfunc(dev->dev) && !netw_view) {
855 if (index) {
856 /* For any index > 0, return the null guid */
857 err = 0;
858 clear = 1;
859 goto out;
860 }
861 }
862
225c7b1f
RD		 863 init_query_mad(in_mad);
864 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
865 in_mad->attr_mod = cpu_to_be32(index / 8);
866
a0c64a17 867 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port,
0a9a0188 868 NULL, NULL, in_mad, out_mad);
225c7b1f
RD		 869 if (err)
870 goto out;
871
872 memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8);
873
874out:
a0c64a17
JM		 875 if (clear)
876 memset(gid->raw + 8, 0, 8);
225c7b1f
RD		 877 kfree(in_mad);
878 kfree(out_mad);
879 return err;
880}
881
fa417f7b
EC		 882static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
883 union ib_gid *gid)
884{
5070cd22 885 if (rdma_protocol_ib(ibdev, port))
a0c64a17 886 return __mlx4_ib_query_gid(ibdev, port, index, gid, 0);
0e1f9b92 887 return 0;
fa417f7b
EC		 888}
889
fd10ed8e
JM		 890static int mlx4_ib_query_sl2vl(struct ib_device *ibdev, u8 port, u64 *sl2vl_tbl)
891{
892 union sl2vl_tbl_to_u64 sl2vl64;
893 struct ib_smp *in_mad = NULL;
894 struct ib_smp *out_mad = NULL;
895 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
896 int err = -ENOMEM;
897 int jj;
898
899 if (mlx4_is_slave(to_mdev(ibdev)->dev)) {
900 *sl2vl_tbl = 0;
901 return 0;
902 }
903
904 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
905 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
906 if (!in_mad || !out_mad)
907 goto out;
908
909 init_query_mad(in_mad);
910 in_mad->attr_id = IB_SMP_ATTR_SL_TO_VL_TABLE;
911 in_mad->attr_mod = 0;
912
913 if (mlx4_is_mfunc(to_mdev(ibdev)->dev))
914 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
915
916 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
917 in_mad, out_mad);
918 if (err)
919 goto out;
920
921 for (jj = 0; jj < 8; jj++)
922 sl2vl64.sl8[jj] = ((struct ib_smp *)out_mad)->data[jj];
923 *sl2vl_tbl = sl2vl64.sl64;
924
925out:
926 kfree(in_mad);
927 kfree(out_mad);
928 return err;
929}
930
931static void mlx4_init_sl2vl_tbl(struct mlx4_ib_dev *mdev)
932{
933 u64 sl2vl;
934 int i;
935 int err;
936
937 for (i = 1; i <= mdev->dev->caps.num_ports; i++) {
938 if (mdev->dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
939 continue;
940 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, i, &sl2vl);
941 if (err) {
942 pr_err("Unable to get default sl to vl mapping for port %d. Using all zeroes (%d)\n",
943 i, err);
944 sl2vl = 0;
945 }
946 atomic64_set(&mdev->sl2vl[i - 1], sl2vl);
947 }
948}
949
0a9a0188
JM		 950int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
951 u16 *pkey, int netw_view)
225c7b1f
RD		 952{
953 struct ib_smp *in_mad = NULL;
954 struct ib_smp *out_mad = NULL;
0a9a0188 955 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
225c7b1f
RD		 956 int err = -ENOMEM;
957
958 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
959 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
960 if (!in_mad || !out_mad)
961 goto out;
962
963 init_query_mad(in_mad);
964 in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE;
965 in_mad->attr_mod = cpu_to_be32(index / 32);
966
0a9a0188
JM		 967 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
968 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
969
970 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
971 in_mad, out_mad);
225c7b1f
RD		 972 if (err)
973 goto out;
974
975 *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]);
976
977out:
978 kfree(in_mad);
979 kfree(out_mad);
980 return err;
981}
982
0a9a0188
JM		 983static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
984{
985 return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0);
986}
987
225c7b1f
RD		 988static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask,
989 struct ib_device_modify *props)
990{
d0d68b86 991 struct mlx4_cmd_mailbox *mailbox;
df7fba66 992 unsigned long flags;
d0d68b86 993
225c7b1f
RD		 994 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
995 return -EOPNOTSUPP;
996
d0d68b86
JM		 997 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
998 return 0;
999
992e8e6e
JM		 1000 if (mlx4_is_slave(to_mdev(ibdev)->dev))
1001 return -EOPNOTSUPP;
1002
df7fba66 1003 spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags);
bd99fdea 1004 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
df7fba66 1005 spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags);
d0d68b86
JM		 1006
1007 /*
1008 * If possible, pass node desc to FW, so it can generate
1009 * a 144 trap. If cmd fails, just ignore.
1010 */
1011 mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev);
1012 if (IS_ERR(mailbox))
1013 return 0;
1014
bd99fdea 1015 memcpy(mailbox->buf, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
d0d68b86 1016 mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0,
992e8e6e 1017 MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
d0d68b86
JM		 1018
1019 mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox);
225c7b1f
RD		 1020
1021 return 0;
1022}
1023
61565013
JM		 1024static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols,
1025 u32 cap_mask)
225c7b1f
RD		 1026{
1027 struct mlx4_cmd_mailbox *mailbox;
1028 int err;
1029
1030 mailbox = mlx4_alloc_cmd_mailbox(dev->dev);
1031 if (IS_ERR(mailbox))
1032 return PTR_ERR(mailbox);
1033
5ae2a7a8
RD		 1034 if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
1035 *(u8 *) mailbox->buf = !!reset_qkey_viols << 6;
1036 ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask);
1037 } else {
1038 ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols;
1039 ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask);
1040 }
225c7b1f 1041
a130b590
IS		 1042 err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE,
1043 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
1044 MLX4_CMD_WRAPPED);
225c7b1f
RD		 1045
1046 mlx4_free_cmd_mailbox(dev->dev, mailbox);
1047 return err;
1048}
1049
1050static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1051 struct ib_port_modify *props)
1052{
61565013
JM		 1053 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
1054 u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH;
225c7b1f
RD		 1055 struct ib_port_attr attr;
1056 u32 cap_mask;
1057 int err;
1058
61565013
JM		 1059 /* return OK if this is RoCE. CM calls ib_modify_port() regardless
1060 * of whether port link layer is ETH or IB. For ETH ports, qkey
1061 * violations and port capabilities are not meaningful.
1062 */
1063 if (is_eth)
1064 return 0;
1065
1066 mutex_lock(&mdev->cap_mask_mutex);
225c7b1f 1067
c4550c63 1068 err = ib_query_port(ibdev, port, &attr);
225c7b1f
RD		 1069 if (err)
1070 goto out;
1071
1072 cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) &
1073 ~props->clr_port_cap_mask;
1074
61565013
JM		 1075 err = mlx4_ib_SET_PORT(mdev, port,
1076 !!(mask & IB_PORT_RESET_QKEY_CNTR),
1077 cap_mask);
225c7b1f
RD		 1078
1079out:
1080 mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex);
1081 return err;
1082}
1083
1084static struct ib_ucontext *mlx4_ib_alloc_ucontext(struct ib_device *ibdev,
1085 struct ib_udata *udata)
1086{
1087 struct mlx4_ib_dev *dev = to_mdev(ibdev);
1088 struct mlx4_ib_ucontext *context;
08ff3235 1089 struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3;
225c7b1f
RD		 1090 struct mlx4_ib_alloc_ucontext_resp resp;
1091 int err;
1092
3b4a8cd5
JM		 1093 if (!dev->ib_active)
1094 return ERR_PTR(-EAGAIN);
1095
08ff3235
OG		 1096 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) {
1097 resp_v3.qp_tab_size = dev->dev->caps.num_qps;
1098 resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size;
1099 resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
1100 } else {
1101 resp.dev_caps = dev->dev->caps.userspace_caps;
1102 resp.qp_tab_size = dev->dev->caps.num_qps;
1103 resp.bf_reg_size = dev->dev->caps.bf_reg_size;
1104 resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
1105 resp.cqe_size = dev->dev->caps.cqe_size;
1106 }
225c7b1f 1107
ae184dde 1108 context = kzalloc(sizeof(*context), GFP_KERNEL);
225c7b1f
RD		 1109 if (!context)
1110 return ERR_PTR(-ENOMEM);
1111
1112 err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar);
1113 if (err) {
1114 kfree(context);
1115 return ERR_PTR(err);
1116 }
1117
1118 INIT_LIST_HEAD(&context->db_page_list);
1119 mutex_init(&context->db_page_mutex);
1120
400b1ebc
GL		 1121 INIT_LIST_HEAD(&context->wqn_ranges_list);
1122 mutex_init(&context->wqn_ranges_mutex);
1123
08ff3235
OG		 1124 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION)
1125 err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3));
1126 else
1127 err = ib_copy_to_udata(udata, &resp, sizeof(resp));
1128
225c7b1f
RD		 1129 if (err) {
1130 mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar);
1131 kfree(context);
1132 return ERR_PTR(-EFAULT);
1133 }
1134
1135 return &context->ibucontext;
1136}
1137
1138static int mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1139{
1140 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
1141
1142 mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar);
1143 kfree(context);
1144
1145 return 0;
1146}
1147
ae184dde
YH		 1148static void mlx4_ib_vma_open(struct vm_area_struct *area)
1149{
1150 /* vma_open is called when a new VMA is created on top of our VMA.
1151 * This is done through either mremap flow or split_vma (usually due
1152 * to mlock, madvise, munmap, etc.). We do not support a clone of the
1153 * vma, as this VMA is strongly hardware related. Therefore we set the
1154 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1155 * calling us again and trying to do incorrect actions. We assume that
1156 * the original vma size is exactly a single page that there will be no
1157 * "splitting" operations on.
1158 */
1159 area->vm_ops = NULL;
1160}
1161
1162static void mlx4_ib_vma_close(struct vm_area_struct *area)
1163{
1164 struct mlx4_ib_vma_private_data *mlx4_ib_vma_priv_data;
1165
1166 /* It's guaranteed that all VMAs opened on a FD are closed before the
1167 * file itself is closed, therefore no sync is needed with the regular
1168 * closing flow. (e.g. mlx4_ib_dealloc_ucontext) However need a sync
1169 * with accessing the vma as part of mlx4_ib_disassociate_ucontext.
1170 * The close operation is usually called under mm->mmap_sem except when
1171 * process is exiting. The exiting case is handled explicitly as part
1172 * of mlx4_ib_disassociate_ucontext.
1173 */
1174 mlx4_ib_vma_priv_data = (struct mlx4_ib_vma_private_data *)
1175 area->vm_private_data;
1176
1177 /* set the vma context pointer to null in the mlx4_ib driver's private
1178 * data to protect against a race condition in mlx4_ib_dissassociate_ucontext().
1179 */
1180 mlx4_ib_vma_priv_data->vma = NULL;
1181}
1182
1183static const struct vm_operations_struct mlx4_ib_vm_ops = {
1184 .open = mlx4_ib_vma_open,
1185 .close = mlx4_ib_vma_close
1186};
1187
1188static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1189{
1190 int i;
ae184dde
YH		 1191 struct vm_area_struct *vma;
1192 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
ae184dde
YH		 1193
1194 /* need to protect from a race on closing the vma as part of
1195 * mlx4_ib_vma_close().
1196 */
ae184dde
YH		 1197 for (i = 0; i < HW_BAR_COUNT; i++) {
1198 vma = context->hw_bar_info[i].vma;
1199 if (!vma)
1200 continue;
1201
7fc8ff26
LR		 1202 zap_vma_ptes(context->hw_bar_info[i].vma,
1203 context->hw_bar_info[i].vma->vm_start, PAGE_SIZE);
ae184dde 1204
ca37a664
MG		 1205 context->hw_bar_info[i].vma->vm_flags &=
1206 ~(VM_SHARED | VM_MAYSHARE);
ae184dde
YH		 1207 /* context going to be destroyed, should not access ops any more */
1208 context->hw_bar_info[i].vma->vm_ops = NULL;
1209 }
ae184dde
YH		 1210}
1211
1212static void mlx4_ib_set_vma_data(struct vm_area_struct *vma,
1213 struct mlx4_ib_vma_private_data *vma_private_data)
1214{
1215 vma_private_data->vma = vma;
1216 vma->vm_private_data = vma_private_data;
1217 vma->vm_ops = &mlx4_ib_vm_ops;
1218}
1219
225c7b1f
RD		 1220static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
1221{
1222 struct mlx4_ib_dev *dev = to_mdev(context->device);
ae184dde 1223 struct mlx4_ib_ucontext *mucontext = to_mucontext(context);
225c7b1f
RD		 1224
1225 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1226 return -EINVAL;
1227
1228 if (vma->vm_pgoff == 0) {
ae184dde
YH		 1229 /* We prevent double mmaping on same context */
1230 if (mucontext->hw_bar_info[HW_BAR_DB].vma)
1231 return -EINVAL;
1232
225c7b1f
RD		 1233 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1234
1235 if (io_remap_pfn_range(vma, vma->vm_start,
1236 to_mucontext(context)->uar.pfn,
1237 PAGE_SIZE, vma->vm_page_prot))
1238 return -EAGAIN;
ae184dde
YH		 1239
1240 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_DB]);
1241
225c7b1f 1242 } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) {
ae184dde
YH		 1243 /* We prevent double mmaping on same context */
1244 if (mucontext->hw_bar_info[HW_BAR_BF].vma)
1245 return -EINVAL;
1246
e1d60ec6 1247 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
225c7b1f
RD		 1248
1249 if (io_remap_pfn_range(vma, vma->vm_start,
1250 to_mucontext(context)->uar.pfn +
1251 dev->dev->caps.num_uars,
1252 PAGE_SIZE, vma->vm_page_prot))
1253 return -EAGAIN;
ae184dde
YH		 1254
1255 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_BF]);
1256
52033cfb
MB		 1257 } else if (vma->vm_pgoff == 3) {
1258 struct mlx4_clock_params params;
ae184dde
YH		 1259 int ret;
1260
1261 /* We prevent double mmaping on same context */
1262 if (mucontext->hw_bar_info[HW_BAR_CLOCK].vma)
1263 return -EINVAL;
1264
1265 ret = mlx4_get_internal_clock_params(dev->dev, &params);
52033cfb
MB		 1266
1267 if (ret)
1268 return ret;
1269
1270 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1271 if (io_remap_pfn_range(vma, vma->vm_start,
1272 (pci_resource_start(dev->dev->persist->pdev,
1273 params.bar) +
1274 params.offset)
1275 >> PAGE_SHIFT,
1276 PAGE_SIZE, vma->vm_page_prot))
1277 return -EAGAIN;
ae184dde
YH		 1278
1279 mlx4_ib_set_vma_data(vma,
1280 &mucontext->hw_bar_info[HW_BAR_CLOCK]);
52033cfb 1281 } else {
225c7b1f 1282 return -EINVAL;
52033cfb 1283 }
225c7b1f
RD		 1284
1285 return 0;
1286}
1287
1288static struct ib_pd *mlx4_ib_alloc_pd(struct ib_device *ibdev,
1289 struct ib_ucontext *context,
1290 struct ib_udata *udata)
1291{
1292 struct mlx4_ib_pd *pd;
1293 int err;
1294
52924434 1295 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
225c7b1f
RD		 1296 if (!pd)
1297 return ERR_PTR(-ENOMEM);
1298
1299 err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn);
1300 if (err) {
1301 kfree(pd);
1302 return ERR_PTR(err);
1303 }
1304
1305 if (context)
1306 if (ib_copy_to_udata(udata, &pd->pdn, sizeof (__u32))) {
1307 mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn);
1308 kfree(pd);
1309 return ERR_PTR(-EFAULT);
1310 }
225c7b1f
RD		 1311 return &pd->ibpd;
1312}
1313
1314static int mlx4_ib_dealloc_pd(struct ib_pd *pd)
1315{
1316 mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn);
1317 kfree(pd);
1318
1319 return 0;
1320}
1321
012a8ff5
SH		 1322static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev,
1323 struct ib_ucontext *context,
1324 struct ib_udata *udata)
1325{
1326 struct mlx4_ib_xrcd *xrcd;
8e37210b 1327 struct ib_cq_init_attr cq_attr = {};
012a8ff5
SH		 1328 int err;
1329
1330 if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1331 return ERR_PTR(-ENOSYS);
1332
1333 xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL);
1334 if (!xrcd)
1335 return ERR_PTR(-ENOMEM);
1336
1337 err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn);
1338 if (err)
1339 goto err1;
1340
ed082d36 1341 xrcd->pd = ib_alloc_pd(ibdev, 0);
012a8ff5
SH		 1342 if (IS_ERR(xrcd->pd)) {
1343 err = PTR_ERR(xrcd->pd);
1344 goto err2;
1345 }
1346
8e37210b
MB		 1347 cq_attr.cqe = 1;
1348 xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, &cq_attr);
012a8ff5
SH		 1349 if (IS_ERR(xrcd->cq)) {
1350 err = PTR_ERR(xrcd->cq);
1351 goto err3;
1352 }
1353
1354 return &xrcd->ibxrcd;
1355
1356err3:
1357 ib_dealloc_pd(xrcd->pd);
1358err2:
1359 mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn);
1360err1:
1361 kfree(xrcd);
1362 return ERR_PTR(err);
1363}
1364
1365static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
1366{
1367 ib_destroy_cq(to_mxrcd(xrcd)->cq);
1368 ib_dealloc_pd(to_mxrcd(xrcd)->pd);
1369 mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn);
1370 kfree(xrcd);
1371
1372 return 0;
1373}
1374
fa417f7b
EC		 1375static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid)
1376{
1377 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
1378 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
1379 struct mlx4_ib_gid_entry *ge;
1380
1381 ge = kzalloc(sizeof *ge, GFP_KERNEL);
1382 if (!ge)
1383 return -ENOMEM;
1384
1385 ge->gid = *gid;
1386 if (mlx4_ib_add_mc(mdev, mqp, gid)) {
1387 ge->port = mqp->port;
1388 ge->added = 1;
1389 }
1390
1391 mutex_lock(&mqp->mutex);
1392 list_add_tail(&ge->list, &mqp->gid_list);
1393 mutex_unlock(&mqp->mutex);
1394
1395 return 0;
1396}
1397
3ba8e31d
EBE		 1398static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev,
1399 struct mlx4_ib_counters *ctr_table)
1400{
1401 struct counter_index *counter, *tmp_count;
1402
1403 mutex_lock(&ctr_table->mutex);
1404 list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list,
1405 list) {
1406 if (counter->allocated)
1407 mlx4_counter_free(ibdev->dev, counter->index);
1408 list_del(&counter->list);
1409 kfree(counter);
1410 }
1411 mutex_unlock(&ctr_table->mutex);
1412}
1413
fa417f7b
EC		 1414int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
1415 union ib_gid *gid)
1416{
fa417f7b
EC		 1417 struct net_device *ndev;
1418 int ret = 0;
1419
1420 if (!mqp->port)
1421 return 0;
1422
dba3ad2a 1423 spin_lock_bh(&mdev->iboe.lock);
fa417f7b
EC		 1424 ndev = mdev->iboe.netdevs[mqp->port - 1];
1425 if (ndev)
1426 dev_hold(ndev);
dba3ad2a 1427 spin_unlock_bh(&mdev->iboe.lock);
fa417f7b
EC		 1428
1429 if (ndev) {
fa417f7b 1430 ret = 1;
fa417f7b
EC		 1431 dev_put(ndev);
1432 }
1433
1434 return ret;
1435}
1436
0ff1fb65
HHZ		 1437struct mlx4_ib_steering {
1438 struct list_head list;
146d6e19 1439 struct mlx4_flow_reg_id reg_id;
0ff1fb65
HHZ		 1440 union ib_gid gid;
1441};
1442
1f02a09c
MG		 1443#define LAST_ETH_FIELD vlan_tag
1444#define LAST_IB_FIELD sl
1445#define LAST_IPV4_FIELD dst_ip
1446#define LAST_TCP_UDP_FIELD src_port
1447
1448/* Field is the last supported field */
1449#define FIELDS_NOT_SUPPORTED(filter, field)\
1450 memchr_inv((void *)&filter.field +\
1451 sizeof(filter.field), 0,\
1452 sizeof(filter) -\
1453 offsetof(typeof(filter), field) -\
1454 sizeof(filter.field))
1455
f77c0162 1456static int parse_flow_attr(struct mlx4_dev *dev,
a37a1a42 1457 u32 qp_num,
f77c0162
HHZ		 1458 union ib_flow_spec *ib_spec,
1459 struct _rule_hw *mlx4_spec)
1460{
1461 enum mlx4_net_trans_rule_id type;
1462
1463 switch (ib_spec->type) {
1464 case IB_FLOW_SPEC_ETH:
1f02a09c
MG		 1465 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1466 return -ENOTSUPP;
1467
f77c0162
HHZ		 1468 type = MLX4_NET_TRANS_RULE_ID_ETH;
1469 memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac,
1470 ETH_ALEN);
1471 memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac,
1472 ETH_ALEN);
1473 mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag;
1474 mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag;
1475 break;
a37a1a42 1476 case IB_FLOW_SPEC_IB:
1f02a09c
MG		 1477 if (FIELDS_NOT_SUPPORTED(ib_spec->ib.mask, LAST_IB_FIELD))
1478 return -ENOTSUPP;
1479
a37a1a42
MB		 1480 type = MLX4_NET_TRANS_RULE_ID_IB;
1481 mlx4_spec->ib.l3_qpn =
1482 cpu_to_be32(qp_num);
1483 mlx4_spec->ib.qpn_mask =
1484 cpu_to_be32(MLX4_IB_FLOW_QPN_MASK);
1485 break;
1486
f77c0162
HHZ		 1487
1488 case IB_FLOW_SPEC_IPV4:
1f02a09c
MG		 1489 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1490 return -ENOTSUPP;
1491
f77c0162
HHZ		 1492 type = MLX4_NET_TRANS_RULE_ID_IPV4;
1493 mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip;
1494 mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip;
1495 mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip;
1496 mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip;
1497 break;
1498
1499 case IB_FLOW_SPEC_TCP:
1500 case IB_FLOW_SPEC_UDP:
1f02a09c
MG		 1501 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, LAST_TCP_UDP_FIELD))
1502 return -ENOTSUPP;
1503
f77c0162
HHZ		 1504 type = ib_spec->type == IB_FLOW_SPEC_TCP ?
1505 MLX4_NET_TRANS_RULE_ID_TCP :
1506 MLX4_NET_TRANS_RULE_ID_UDP;
1507 mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port;
1508 mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port;
1509 mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port;
1510 mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port;
1511 break;
1512
1513 default:
1514 return -EINVAL;
1515 }
1516 if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 ||
1517 mlx4_hw_rule_sz(dev, type) < 0)
1518 return -EINVAL;
1519 mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type));
1520 mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2;
1521 return mlx4_hw_rule_sz(dev, type);
1522}
1523
a37a1a42
MB		 1524struct default_rules {
1525 __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
1526 __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
1527 __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS];
1528 __u8 link_layer;
1529};
1530static const struct default_rules default_table[] = {
1531 {
1532 .mandatory_fields = {IB_FLOW_SPEC_IPV4},
1533 .mandatory_not_fields = {IB_FLOW_SPEC_ETH},
1534 .rules_create_list = {IB_FLOW_SPEC_IB},
1535 .link_layer = IB_LINK_LAYER_INFINIBAND
1536 }
1537};
1538
1539static int __mlx4_ib_default_rules_match(struct ib_qp *qp,
1540 struct ib_flow_attr *flow_attr)
1541{
1542 int i, j, k;
1543 void *ib_flow;
1544 const struct default_rules *pdefault_rules = default_table;
1545 u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port);
1546
a57f23f6 1547 for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) {
a37a1a42
MB		 1548 __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS];
1549 memset(&field_types, 0, sizeof(field_types));
1550
1551 if (link_layer != pdefault_rules->link_layer)
1552 continue;
1553
1554 ib_flow = flow_attr + 1;
1555 /* we assume the specs are sorted */
1556 for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS &&
1557 j < flow_attr->num_of_specs; k++) {
1558 union ib_flow_spec *current_flow =
1559 (union ib_flow_spec *)ib_flow;
1560
1561 /* same layer but different type */
1562 if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) ==
1563 (pdefault_rules->mandatory_fields[k] &
1564 IB_FLOW_SPEC_LAYER_MASK)) &&
1565 (current_flow->type !=
1566 pdefault_rules->mandatory_fields[k]))
1567 goto out;
1568
1569 /* same layer, try match next one */
1570 if (current_flow->type ==
1571 pdefault_rules->mandatory_fields[k]) {
1572 j++;
1573 ib_flow +=
1574 ((union ib_flow_spec *)ib_flow)->size;
1575 }
1576 }
1577
1578 ib_flow = flow_attr + 1;
1579 for (j = 0; j < flow_attr->num_of_specs;
1580 j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size)
1581 for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++)
1582 /* same layer and same type */
1583 if (((union ib_flow_spec *)ib_flow)->type ==
1584 pdefault_rules->mandatory_not_fields[k])
1585 goto out;
1586
1587 return i;
1588 }
1589out:
1590 return -1;
1591}
1592
1593static int __mlx4_ib_create_default_rules(
1594 struct mlx4_ib_dev *mdev,
1595 struct ib_qp *qp,
1596 const struct default_rules *pdefault_rules,
1597 struct _rule_hw *mlx4_spec) {
1598 int size = 0;
1599 int i;
1600
a57f23f6 1601 for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) {
a37a1a42
MB		 1602 int ret;
1603 union ib_flow_spec ib_spec;
1604 switch (pdefault_rules->rules_create_list[i]) {
1605 case 0:
1606 /* no rule */
1607 continue;
1608 case IB_FLOW_SPEC_IB:
1609 ib_spec.type = IB_FLOW_SPEC_IB;
1610 ib_spec.size = sizeof(struct ib_flow_spec_ib);
1611
1612 break;
1613 default:
1614 /* invalid rule */
1615 return -EINVAL;
1616 }
1617 /* We must put empty rule, qpn is being ignored */
1618 ret = parse_flow_attr(mdev->dev, 0, &ib_spec,
1619 mlx4_spec);
1620 if (ret < 0) {
1621 pr_info("invalid parsing\n");
1622 return -EINVAL;
1623 }
1624
1625 mlx4_spec = (void *)mlx4_spec + ret;
1626 size += ret;
1627 }
1628 return size;
1629}
1630
f77c0162
HHZ		 1631static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
1632 int domain,
1633 enum mlx4_net_trans_promisc_mode flow_type,
1634 u64 *reg_id)
1635{
1636 int ret, i;
1637 int size = 0;
1638 void *ib_flow;
1639 struct mlx4_ib_dev *mdev = to_mdev(qp->device);
1640 struct mlx4_cmd_mailbox *mailbox;
1641 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
a37a1a42 1642 int default_flow;
f77c0162
HHZ		 1643
1644 static const u16 __mlx4_domain[] = {
1645 [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS,
1646 [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL,
1647 [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS,
1648 [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC,
1649 };
1650
1651 if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) {
1652 pr_err("Invalid priority value %d\n", flow_attr->priority);
1653 return -EINVAL;
1654 }
1655
1656 if (domain >= IB_FLOW_DOMAIN_NUM) {
1657 pr_err("Invalid domain value %d\n", domain);
1658 return -EINVAL;
1659 }
1660
1661 if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0)
1662 return -EINVAL;
1663
1664 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
1665 if (IS_ERR(mailbox))
1666 return PTR_ERR(mailbox);
f77c0162
HHZ		 1667 ctrl = mailbox->buf;
1668
1669 ctrl->prio = cpu_to_be16(__mlx4_domain[domain] |
1670 flow_attr->priority);
1671 ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type);
1672 ctrl->port = flow_attr->port;
1673 ctrl->qpn = cpu_to_be32(qp->qp_num);
1674
1675 ib_flow = flow_attr + 1;
1676 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
a37a1a42
MB		 1677 /* Add default flows */
1678 default_flow = __mlx4_ib_default_rules_match(qp, flow_attr);
1679 if (default_flow >= 0) {
1680 ret = __mlx4_ib_create_default_rules(
1681 mdev, qp, default_table + default_flow,
1682 mailbox->buf + size);
1683 if (ret < 0) {
1684 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1685 return -EINVAL;
1686 }
1687 size += ret;
1688 }
f77c0162 1689 for (i = 0; i < flow_attr->num_of_specs; i++) {
a37a1a42
MB		 1690 ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow,
1691 mailbox->buf + size);
f77c0162
HHZ		 1692 if (ret < 0) {
1693 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1694 return -EINVAL;
1695 }
1696 ib_flow += ((union ib_flow_spec *) ib_flow)->size;
1697 size += ret;
1698 }
1699
10b1c04e
JM		 1700 if (mlx4_is_master(mdev->dev) && flow_type == MLX4_FS_REGULAR &&
1701 flow_attr->num_of_specs == 1) {
1702 struct _rule_hw *rule_header = (struct _rule_hw *)(ctrl + 1);
1703 enum ib_flow_spec_type header_spec =
1704 ((union ib_flow_spec *)(flow_attr + 1))->type;
1705
1706 if (header_spec == IB_FLOW_SPEC_ETH)
1707 mlx4_handle_eth_header_mcast_prio(ctrl, rule_header);
1708 }
1709
f77c0162
HHZ		 1710 ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0,
1711 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
10b1c04e 1712 MLX4_CMD_NATIVE);
f77c0162
HHZ		 1713 if (ret == -ENOMEM)
1714 pr_err("mcg table is full. Fail to register network rule.\n");
1715 else if (ret == -ENXIO)
1716 pr_err("Device managed flow steering is disabled. Fail to register network rule.\n");
1717 else if (ret)
35fc7b7d 1718 pr_err("Invalid argument. Fail to register network rule.\n");
f77c0162
HHZ		 1719
1720 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1721 return ret;
1722}
1723
1724static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id)
1725{
1726 int err;
1727 err = mlx4_cmd(dev, reg_id, 0, 0,
1728 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
10b1c04e 1729 MLX4_CMD_NATIVE);
f77c0162
HHZ		 1730 if (err)
1731 pr_err("Fail to detach network rule. registration id = 0x%llx\n",
1732 reg_id);
1733 return err;
1734}
1735
d2fce8a9
OG		 1736static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
1737 u64 *reg_id)
1738{
1739 void *ib_flow;
1740 union ib_flow_spec *ib_spec;
1741 struct mlx4_dev *dev = to_mdev(qp->device)->dev;
1742 int err = 0;
1743
5eff6dad
OG		 1744 if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
1745 dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
d2fce8a9
OG		 1746 return 0; /* do nothing */
1747
1748 ib_flow = flow_attr + 1;
1749 ib_spec = (union ib_flow_spec *)ib_flow;
1750
1751 if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1)
1752 return 0; /* do nothing */
1753
1754 err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac,
1755 flow_attr->port, qp->qp_num,
1756 MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff),
1757 reg_id);
1758 return err;
1759}
1760
0e451e88
MV		 1761static int mlx4_ib_add_dont_trap_rule(struct mlx4_dev *dev,
1762 struct ib_flow_attr *flow_attr,
1763 enum mlx4_net_trans_promisc_mode *type)
1764{
1765 int err = 0;
1766
1767 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER) ||
1768 (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) ||
1769 (flow_attr->num_of_specs > 1) || (flow_attr->priority != 0)) {
1770 return -EOPNOTSUPP;
1771 }
1772
1773 if (flow_attr->num_of_specs == 0) {
1774 type[0] = MLX4_FS_MC_SNIFFER;
1775 type[1] = MLX4_FS_UC_SNIFFER;
1776 } else {
1777 union ib_flow_spec *ib_spec;
1778
1779 ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1780 if (ib_spec->type != IB_FLOW_SPEC_ETH)
1781 return -EINVAL;
1782
1783 /* if all is zero than MC and UC */
1784 if (is_zero_ether_addr(ib_spec->eth.mask.dst_mac)) {
1785 type[0] = MLX4_FS_MC_SNIFFER;
1786 type[1] = MLX4_FS_UC_SNIFFER;
1787 } else {
1788 u8 mac[ETH_ALEN] = {ib_spec->eth.mask.dst_mac[0] ^ 0x01,
1789 ib_spec->eth.mask.dst_mac[1],
1790 ib_spec->eth.mask.dst_mac[2],
1791 ib_spec->eth.mask.dst_mac[3],
1792 ib_spec->eth.mask.dst_mac[4],
1793 ib_spec->eth.mask.dst_mac[5]};
1794
1795 /* Above xor was only on MC bit, non empty mask is valid
1796 * only if this bit is set and rest are zero.
1797 */
1798 if (!is_zero_ether_addr(&mac[0]))
1799 return -EINVAL;
1800
1801 if (is_multicast_ether_addr(ib_spec->eth.val.dst_mac))
1802 type[0] = MLX4_FS_MC_SNIFFER;
1803 else
1804 type[0] = MLX4_FS_UC_SNIFFER;
1805 }
1806 }
1807
1808 return err;
1809}
1810
f77c0162
HHZ		 1811static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp,
1812 struct ib_flow_attr *flow_attr,
59082a32 1813 int domain, struct ib_udata *udata)
f77c0162 1814{
146d6e19 1815 int err = 0, i = 0, j = 0;
f77c0162
HHZ		 1816 struct mlx4_ib_flow *mflow;
1817 enum mlx4_net_trans_promisc_mode type[2];
146d6e19
MS		 1818 struct mlx4_dev *dev = (to_mdev(qp->device))->dev;
1819 int is_bonded = mlx4_is_bonded(dev);
f77c0162 1820
5533c18a
YH		 1821 if (flow_attr->port < 1 || flow_attr->port > qp->device->phys_port_cnt)
1822 return ERR_PTR(-EINVAL);
1823
8510020d
BP		 1824 if (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)
1825 return ERR_PTR(-EOPNOTSUPP);
1826
0e451e88
MV		 1827 if ((flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) &&
1828 (flow_attr->type != IB_FLOW_ATTR_NORMAL))
a3100a78
MV		 1829 return ERR_PTR(-EOPNOTSUPP);
1830
59082a32
MB		 1831 if (udata &&
1832 udata->inlen && !ib_is_udata_cleared(udata, 0, udata->inlen))
1833 return ERR_PTR(-EOPNOTSUPP);
1834
f77c0162
HHZ		 1835 memset(type, 0, sizeof(type));
1836
1837 mflow = kzalloc(sizeof(*mflow), GFP_KERNEL);
1838 if (!mflow) {
1839 err = -ENOMEM;
1840 goto err_free;
1841 }
1842
1843 switch (flow_attr->type) {
1844 case IB_FLOW_ATTR_NORMAL:
0e451e88
MV		 1845 /* If dont trap flag (continue match) is set, under specific
1846 * condition traffic be replicated to given qp,
1847 * without stealing it
1848 */
1849 if (unlikely(flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)) {
1850 err = mlx4_ib_add_dont_trap_rule(dev,
1851 flow_attr,
1852 type);
1853 if (err)
1854 goto err_free;
1855 } else {
1856 type[0] = MLX4_FS_REGULAR;
1857 }
f77c0162
HHZ		 1858 break;
1859
1860 case IB_FLOW_ATTR_ALL_DEFAULT:
1861 type[0] = MLX4_FS_ALL_DEFAULT;
1862 break;
1863
1864 case IB_FLOW_ATTR_MC_DEFAULT:
1865 type[0] = MLX4_FS_MC_DEFAULT;
1866 break;
1867
1868 case IB_FLOW_ATTR_SNIFFER:
0e451e88
MV		 1869 type[0] = MLX4_FS_MIRROR_RX_PORT;
1870 type[1] = MLX4_FS_MIRROR_SX_PORT;
f77c0162
HHZ		 1871 break;
1872
1873 default:
1874 err = -EINVAL;
1875 goto err_free;
1876 }
1877
1878 while (i < ARRAY_SIZE(type) && type[i]) {
1879 err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i],
146d6e19 1880 &mflow->reg_id[i].id);
f77c0162 1881 if (err)
571e1b2c 1882 goto err_create_flow;
146d6e19 1883 if (is_bonded) {
824c25c1
MS		 1884 /* Application always sees one port so the mirror rule
1885 * must be on port #2
1886 */
146d6e19
MS		 1887 flow_attr->port = 2;
1888 err = __mlx4_ib_create_flow(qp, flow_attr,
1889 domain, type[j],
1890 &mflow->reg_id[j].mirror);
1891 flow_attr->port = 1;
1892 if (err)
1893 goto err_create_flow;
1894 j++;
1895 }
1896
11562568 1897 i++;
f77c0162
HHZ		 1898 }
1899
d2fce8a9 1900 if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) {
146d6e19
MS		 1901 err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
1902 &mflow->reg_id[i].id);
d2fce8a9 1903 if (err)
571e1b2c 1904 goto err_create_flow;
11562568 1905
146d6e19
MS		 1906 if (is_bonded) {
1907 flow_attr->port = 2;
1908 err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
1909 &mflow->reg_id[j].mirror);
1910 flow_attr->port = 1;
1911 if (err)
1912 goto err_create_flow;
1913 j++;
1914 }
1915 /* function to create mirror rule */
11562568 1916 i++;
d2fce8a9
OG		 1917 }
1918
f77c0162
HHZ		 1919 return &mflow->ibflow;
1920
571e1b2c
OG		 1921err_create_flow:
1922 while (i) {
146d6e19
MS		 1923 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
1924 mflow->reg_id[i].id);
571e1b2c
OG		 1925 i--;
1926 }
146d6e19
MS		 1927
1928 while (j) {
1929 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
1930 mflow->reg_id[j].mirror);
1931 j--;
1932 }
f77c0162
HHZ		 1933err_free:
1934 kfree(mflow);
1935 return ERR_PTR(err);
1936}
1937
1938static int mlx4_ib_destroy_flow(struct ib_flow *flow_id)
1939{
1940 int err, ret = 0;
1941 int i = 0;
1942 struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device);
1943 struct mlx4_ib_flow *mflow = to_mflow(flow_id);
1944
146d6e19
MS		 1945 while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) {
1946 err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id);
f77c0162
HHZ		 1947 if (err)
1948 ret = err;
146d6e19
MS		 1949 if (mflow->reg_id[i].mirror) {
1950 err = __mlx4_ib_destroy_flow(mdev->dev,
1951 mflow->reg_id[i].mirror);
1952 if (err)
1953 ret = err;
1954 }
f77c0162
HHZ		 1955 i++;
1956 }
1957
1958 kfree(mflow);
1959 return ret;
1960}
1961
225c7b1f
RD		 1962static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1963{
fa417f7b
EC		 1964 int err;
1965 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
146d6e19 1966 struct mlx4_dev *dev = mdev->dev;
fa417f7b 1967 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
0ff1fb65 1968 struct mlx4_ib_steering *ib_steering = NULL;
e9a7faf1 1969 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
146d6e19 1970 struct mlx4_flow_reg_id reg_id;
0ff1fb65
HHZ		 1971
1972 if (mdev->dev->caps.steering_mode ==
1973 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1974 ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL);
1975 if (!ib_steering)
1976 return -ENOMEM;
1977 }
fa417f7b 1978
0ff1fb65
HHZ		 1979 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port,
1980 !!(mqp->flags &
1981 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
146d6e19 1982 prot, &reg_id.id);
e9a7faf1
OG		 1983 if (err) {
1984 pr_err("multicast attach op failed, err %d\n", err);
0ff1fb65 1985 goto err_malloc;
e9a7faf1 1986 }
fa417f7b 1987
146d6e19
MS		 1988 reg_id.mirror = 0;
1989 if (mlx4_is_bonded(dev)) {
824c25c1
MS		 1990 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw,
1991 (mqp->port == 1) ? 2 : 1,
146d6e19
MS		 1992 !!(mqp->flags &
1993 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
1994 prot, &reg_id.mirror);
1995 if (err)
1996 goto err_add;
1997 }
1998
fa417f7b
EC		 1999 err = add_gid_entry(ibqp, gid);
2000 if (err)
2001 goto err_add;
2002
0ff1fb65
HHZ		 2003 if (ib_steering) {
2004 memcpy(ib_steering->gid.raw, gid->raw, 16);
2005 ib_steering->reg_id = reg_id;
2006 mutex_lock(&mqp->mutex);
2007 list_add(&ib_steering->list, &mqp->steering_rules);
2008 mutex_unlock(&mqp->mutex);
2009 }
fa417f7b
EC		 2010 return 0;
2011
2012err_add:
0ff1fb65 2013 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
146d6e19
MS		 2014 prot, reg_id.id);
2015 if (reg_id.mirror)
2016 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
2017 prot, reg_id.mirror);
0ff1fb65
HHZ		 2018err_malloc:
2019 kfree(ib_steering);
2020
fa417f7b
EC		 2021 return err;
2022}
2023
2024static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw)
2025{
2026 struct mlx4_ib_gid_entry *ge;
2027 struct mlx4_ib_gid_entry *tmp;
2028 struct mlx4_ib_gid_entry *ret = NULL;
2029
2030 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
2031 if (!memcmp(raw, ge->gid.raw, 16)) {
2032 ret = ge;
2033 break;
2034 }
2035 }
2036
2037 return ret;
225c7b1f
RD		 2038}
2039
2040static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2041{
fa417f7b
EC		 2042 int err;
2043 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
146d6e19 2044 struct mlx4_dev *dev = mdev->dev;
fa417f7b 2045 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
fa417f7b
EC		 2046 struct net_device *ndev;
2047 struct mlx4_ib_gid_entry *ge;
146d6e19 2048 struct mlx4_flow_reg_id reg_id = {0, 0};
e9a7faf1 2049 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
0ff1fb65
HHZ		 2050
2051 if (mdev->dev->caps.steering_mode ==
2052 MLX4_STEERING_MODE_DEVICE_MANAGED) {
2053 struct mlx4_ib_steering *ib_steering;
2054
2055 mutex_lock(&mqp->mutex);
2056 list_for_each_entry(ib_steering, &mqp->steering_rules, list) {
2057 if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) {
2058 list_del(&ib_steering->list);
2059 break;
2060 }
2061 }
2062 mutex_unlock(&mqp->mutex);
2063 if (&ib_steering->list == &mqp->steering_rules) {
2064 pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n");
2065 return -EINVAL;
2066 }
2067 reg_id = ib_steering->reg_id;
2068 kfree(ib_steering);
2069 }
fa417f7b 2070
0ff1fb65 2071 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
146d6e19 2072 prot, reg_id.id);
fa417f7b
EC		 2073 if (err)
2074 return err;
2075
146d6e19
MS		 2076 if (mlx4_is_bonded(dev)) {
2077 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
2078 prot, reg_id.mirror);
2079 if (err)
2080 return err;
2081 }
2082
fa417f7b
EC		 2083 mutex_lock(&mqp->mutex);
2084 ge = find_gid_entry(mqp, gid->raw);
2085 if (ge) {
dba3ad2a 2086 spin_lock_bh(&mdev->iboe.lock);
fa417f7b
EC		 2087 ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL;
2088 if (ndev)
2089 dev_hold(ndev);
dba3ad2a 2090 spin_unlock_bh(&mdev->iboe.lock);
d487ee77 2091 if (ndev)
fa417f7b 2092 dev_put(ndev);
fa417f7b
EC		 2093 list_del(&ge->list);
2094 kfree(ge);
2095 } else
987c8f8f 2096 pr_warn("could not find mgid entry\n");
fa417f7b
EC		 2097
2098 mutex_unlock(&mqp->mutex);
2099
2100 return 0;
225c7b1f
RD		 2101}
2102
2103static int init_node_data(struct mlx4_ib_dev *dev)
2104{
2105 struct ib_smp *in_mad = NULL;
2106 struct ib_smp *out_mad = NULL;
0a9a0188 2107 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
225c7b1f
RD		 2108 int err = -ENOMEM;
2109
2110 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
2111 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
2112 if (!in_mad || !out_mad)
2113 goto out;
2114
2115 init_query_mad(in_mad);
2116 in_mad->attr_id = IB_SMP_ATTR_NODE_DESC;
0a9a0188
JM		 2117 if (mlx4_is_master(dev->dev))
2118 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
225c7b1f 2119
0a9a0188 2120 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
225c7b1f
RD		 2121 if (err)
2122 goto out;
2123
bd99fdea 2124 memcpy(dev->ib_dev.node_desc, out_mad->data, IB_DEVICE_NODE_DESC_MAX);
225c7b1f
RD		 2125
2126 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
2127
0a9a0188 2128 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
225c7b1f
RD		 2129 if (err)
2130 goto out;
2131
992e8e6e 2132 dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32));
225c7b1f
RD		 2133 memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8);
2134
2135out:
2136 kfree(in_mad);
2137 kfree(out_mad);
2138 return err;
2139}
2140
f4e91eb4
TJ		 2141static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2142 char *buf)
cd9281d8 2143{
f4e91eb4
TJ		 2144 struct mlx4_ib_dev *dev =
2145 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
872bf2fb 2146 return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device);
cd9281d8
JM		 2147}
2148
f4e91eb4
TJ		 2149static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2150 char *buf)
cd9281d8 2151{
f4e91eb4
TJ		 2152 struct mlx4_ib_dev *dev =
2153 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
cd9281d8
JM		 2154 return sprintf(buf, "%x\n", dev->dev->rev_id);
2155}
2156
f4e91eb4
TJ		 2157static ssize_t show_board(struct device *device, struct device_attribute *attr,
2158 char *buf)
cd9281d8 2159{
f4e91eb4
TJ		 2160 struct mlx4_ib_dev *dev =
2161 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
2162 return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN,
2163 dev->dev->board_id);
cd9281d8
JM		 2164}
2165
f4e91eb4 2166static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
f4e91eb4
TJ		 2167static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2168static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
cd9281d8 2169
f4e91eb4
TJ		 2170static struct device_attribute *mlx4_class_attributes[] = {
2171 &dev_attr_hw_rev,
f4e91eb4
TJ		 2172 &dev_attr_hca_type,
2173 &dev_attr_board_id
cd9281d8
JM		 2174};
2175
3f85f2aa
MB		 2176struct diag_counter {
2177 const char *name;
2178 u32 offset;
2179};
2180
2181#define DIAG_COUNTER(_name, _offset) \
2182 { .name = #_name, .offset = _offset }
2183
2184static const struct diag_counter diag_basic[] = {
2185 DIAG_COUNTER(rq_num_lle, 0x00),
2186 DIAG_COUNTER(sq_num_lle, 0x04),
2187 DIAG_COUNTER(rq_num_lqpoe, 0x08),
2188 DIAG_COUNTER(sq_num_lqpoe, 0x0C),
2189 DIAG_COUNTER(rq_num_lpe, 0x18),
2190 DIAG_COUNTER(sq_num_lpe, 0x1C),
2191 DIAG_COUNTER(rq_num_wrfe, 0x20),
2192 DIAG_COUNTER(sq_num_wrfe, 0x24),
2193 DIAG_COUNTER(sq_num_mwbe, 0x2C),
2194 DIAG_COUNTER(sq_num_bre, 0x34),
2195 DIAG_COUNTER(sq_num_rire, 0x44),
2196 DIAG_COUNTER(rq_num_rire, 0x48),
2197 DIAG_COUNTER(sq_num_rae, 0x4C),
2198 DIAG_COUNTER(rq_num_rae, 0x50),
2199 DIAG_COUNTER(sq_num_roe, 0x54),
2200 DIAG_COUNTER(sq_num_tree, 0x5C),
2201 DIAG_COUNTER(sq_num_rree, 0x64),
2202 DIAG_COUNTER(rq_num_rnr, 0x68),
2203 DIAG_COUNTER(sq_num_rnr, 0x6C),
2204 DIAG_COUNTER(rq_num_oos, 0x100),
2205 DIAG_COUNTER(sq_num_oos, 0x104),
2206};
2207
2208static const struct diag_counter diag_ext[] = {
2209 DIAG_COUNTER(rq_num_dup, 0x130),
2210 DIAG_COUNTER(sq_num_to, 0x134),
2211};
2212
2213static const struct diag_counter diag_device_only[] = {
2214 DIAG_COUNTER(num_cqovf, 0x1A0),
2215 DIAG_COUNTER(rq_num_udsdprd, 0x118),
2216};
2217
2218static struct rdma_hw_stats *mlx4_ib_alloc_hw_stats(struct ib_device *ibdev,
2219 u8 port_num)
2220{
2221 struct mlx4_ib_dev *dev = to_mdev(ibdev);
2222 struct mlx4_ib_diag_counters *diag = dev->diag_counters;
2223
2224 if (!diag[!!port_num].name)
2225 return NULL;
2226
2227 return rdma_alloc_hw_stats_struct(diag[!!port_num].name,
2228 diag[!!port_num].num_counters,
2229 RDMA_HW_STATS_DEFAULT_LIFESPAN);
2230}
2231
2232static int mlx4_ib_get_hw_stats(struct ib_device *ibdev,
2233 struct rdma_hw_stats *stats,
2234 u8 port, int index)
2235{
2236 struct mlx4_ib_dev *dev = to_mdev(ibdev);
2237 struct mlx4_ib_diag_counters *diag = dev->diag_counters;
2238 u32 hw_value[ARRAY_SIZE(diag_device_only) +
2239 ARRAY_SIZE(diag_ext) + ARRAY_SIZE(diag_basic)] = {};
2240 int ret;
2241 int i;
2242
2243 ret = mlx4_query_diag_counters(dev->dev,
2244 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS,
2245 diag[!!port].offset, hw_value,
2246 diag[!!port].num_counters, port);
2247
2248 if (ret)
2249 return ret;
2250
2251 for (i = 0; i < diag[!!port].num_counters; i++)
2252 stats->value[i] = hw_value[i];
2253
2254 return diag[!!port].num_counters;
2255}
2256
2257static int __mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev,
2258 const char ***name,
2259 u32 **offset,
2260 u32 *num,
2261 bool port)
2262{
2263 u32 num_counters;
2264
2265 num_counters = ARRAY_SIZE(diag_basic);
2266
2267 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT)
2268 num_counters += ARRAY_SIZE(diag_ext);
2269
2270 if (!port)
2271 num_counters += ARRAY_SIZE(diag_device_only);
2272
2273 *name = kcalloc(num_counters, sizeof(**name), GFP_KERNEL);
2274 if (!*name)
2275 return -ENOMEM;
2276
2277 *offset = kcalloc(num_counters, sizeof(**offset), GFP_KERNEL);
2278 if (!*offset)
2279 goto err_name;
2280
2281 *num = num_counters;
2282
2283 return 0;
2284
2285err_name:
2286 kfree(*name);
2287 return -ENOMEM;
2288}
2289
2290static void mlx4_ib_fill_diag_counters(struct mlx4_ib_dev *ibdev,
2291 const char **name,
2292 u32 *offset,
2293 bool port)
2294{
2295 int i;
2296 int j;
2297
2298 for (i = 0, j = 0; i < ARRAY_SIZE(diag_basic); i++, j++) {
2299 name[i] = diag_basic[i].name;
2300 offset[i] = diag_basic[i].offset;
2301 }
2302
2303 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) {
2304 for (i = 0; i < ARRAY_SIZE(diag_ext); i++, j++) {
2305 name[j] = diag_ext[i].name;
2306 offset[j] = diag_ext[i].offset;
2307 }
2308 }
2309
2310 if (!port) {
2311 for (i = 0; i < ARRAY_SIZE(diag_device_only); i++, j++) {
2312 name[j] = diag_device_only[i].name;
2313 offset[j] = diag_device_only[i].offset;
2314 }
2315 }
2316}
2317
2318static int mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev)
2319{
2320 struct mlx4_ib_diag_counters *diag = ibdev->diag_counters;
2321 int i;
2322 int ret;
2323 bool per_port = !!(ibdev->dev->caps.flags2 &
2324 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT);
2325
69d269d3
KH		 2326 if (mlx4_is_slave(ibdev->dev))
2327 return 0;
2328
3f85f2aa
MB		 2329 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
2330 /* i == 1 means we are building port counters */
2331 if (i && !per_port)
2332 continue;
2333
2334 ret = __mlx4_ib_alloc_diag_counters(ibdev, &diag[i].name,
2335 &diag[i].offset,
2336 &diag[i].num_counters, i);
2337 if (ret)
2338 goto err_alloc;
2339
2340 mlx4_ib_fill_diag_counters(ibdev, diag[i].name,
2341 diag[i].offset, i);
2342 }
2343
2344 ibdev->ib_dev.get_hw_stats = mlx4_ib_get_hw_stats;
2345 ibdev->ib_dev.alloc_hw_stats = mlx4_ib_alloc_hw_stats;
2346
2347 return 0;
2348
2349err_alloc:
2350 if (i) {
2351 kfree(diag[i - 1].name);
2352 kfree(diag[i - 1].offset);
2353 }
2354
2355 return ret;
2356}
2357
2358static void mlx4_ib_diag_cleanup(struct mlx4_ib_dev *ibdev)
2359{
2360 int i;
2361
2362 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
2363 kfree(ibdev->diag_counters[i].offset);
2364 kfree(ibdev->diag_counters[i].name);
2365 }
2366}
2367
9433c188
MB		 2368#define MLX4_IB_INVALID_MAC ((u64)-1)
2369static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev,
2370 struct net_device *dev,
2371 int port)
2372{
2373 u64 new_smac = 0;
2374 u64 release_mac = MLX4_IB_INVALID_MAC;
2375 struct mlx4_ib_qp *qp;
2376
2377 read_lock(&dev_base_lock);
2378 new_smac = mlx4_mac_to_u64(dev->dev_addr);
2379 read_unlock(&dev_base_lock);
2380
3e0629cb
JM		 2381 atomic64_set(&ibdev->iboe.mac[port - 1], new_smac);
2382
d24d9f43
JM		 2383 /* no need for update QP1 and mac registration in non-SRIOV */
2384 if (!mlx4_is_mfunc(ibdev->dev))
2385 return;
2386
9433c188
MB		 2387 mutex_lock(&ibdev->qp1_proxy_lock[port - 1]);
2388 qp = ibdev->qp1_proxy[port - 1];
2389 if (qp) {
2390 int new_smac_index;
25476b02 2391 u64 old_smac;
9433c188
MB		 2392 struct mlx4_update_qp_params update_params;
2393
25476b02
JM		 2394 mutex_lock(&qp->mutex);
2395 old_smac = qp->pri.smac;
9433c188
MB		 2396 if (new_smac == old_smac)
2397 goto unlock;
2398
2399 new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac);
2400
2401 if (new_smac_index < 0)
2402 goto unlock;
2403
2404 update_params.smac_index = new_smac_index;
09e05c3f 2405 if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC,
9433c188
MB		 2406 &update_params)) {
2407 release_mac = new_smac;
2408 goto unlock;
2409 }
25476b02
JM		 2410 /* if old port was zero, no mac was yet registered for this QP */
2411 if (qp->pri.smac_port)
2412 release_mac = old_smac;
9433c188 2413 qp->pri.smac = new_smac;
25476b02 2414 qp->pri.smac_port = port;
9433c188 2415 qp->pri.smac_index = new_smac_index;
9433c188
MB		 2416 }
2417
2418unlock:
9433c188
MB		 2419 if (release_mac != MLX4_IB_INVALID_MAC)
2420 mlx4_unregister_mac(ibdev->dev, port, release_mac);
25476b02
JM		 2421 if (qp)
2422 mutex_unlock(&qp->mutex);
2423 mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]);
9433c188
MB		 2424}
2425
9433c188
MB		 2426static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev,
2427 struct net_device *dev,
2428 unsigned long event)
2429
d487ee77 2430{
fa417f7b 2431 struct mlx4_ib_iboe *iboe;
9433c188 2432 int update_qps_port = -1;
fa417f7b
EC		 2433 int port;
2434
5070cd22
MS		 2435 ASSERT_RTNL();
2436
fa417f7b
EC		 2437 iboe = &ibdev->iboe;
2438
dba3ad2a 2439 spin_lock_bh(&iboe->lock);
fa417f7b 2440 mlx4_foreach_ib_transport_port(port, ibdev->dev) {
ad4885d2 2441
fa417f7b 2442 iboe->netdevs[port - 1] =
0345584e 2443 mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port);
fa417f7b 2444
9433c188
MB		 2445 if (dev == iboe->netdevs[port - 1] &&
2446 (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER ||
2447 event == NETDEV_UP || event == NETDEV_CHANGE))
2448 update_qps_port = port;
2449
d487ee77 2450 }
dba3ad2a 2451 spin_unlock_bh(&iboe->lock);
9433c188
MB		 2452
2453 if (update_qps_port > 0)
2454 mlx4_ib_update_qps(ibdev, dev, update_qps_port);
d487ee77
MS		 2455}
2456
2457static int mlx4_ib_netdev_event(struct notifier_block *this,
2458 unsigned long event, void *ptr)
2459{
2460 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
2461 struct mlx4_ib_dev *ibdev;
2462
2463 if (!net_eq(dev_net(dev), &init_net))
2464 return NOTIFY_DONE;
2465
2466 ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb);
9433c188 2467 mlx4_ib_scan_netdevs(ibdev, dev, event);
fa417f7b
EC		 2468
2469 return NOTIFY_DONE;
2470}
2471
54679e14
JM		 2472static void init_pkeys(struct mlx4_ib_dev *ibdev)
2473{
2474 int port;
2475 int slave;
2476 int i;
2477
2478 if (mlx4_is_master(ibdev->dev)) {
872bf2fb
YH		 2479 for (slave = 0; slave <= ibdev->dev->persist->num_vfs;
2480 ++slave) {
54679e14
JM		 2481 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
2482 for (i = 0;
2483 i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
2484 ++i) {
2485 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] =
2486 /* master has the identity virt2phys pkey mapping */
2487 (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i :
2488 ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1;
2489 mlx4_sync_pkey_table(ibdev->dev, slave, port, i,
2490 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]);
2491 }
2492 }
2493 }
2494 /* initialize pkey cache */
2495 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
2496 for (i = 0;
2497 i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
2498 ++i)
2499 ibdev->pkeys.phys_pkey_cache[port-1][i] =
2500 (i) ? 0 : 0xFFFF;
2501 }
2502 }
2503}
2504
e605b743
SP		 2505static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
2506{
c66fa19c 2507 int i, j, eq = 0, total_eqs = 0;
e605b743 2508
c66fa19c
MB		 2509 ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors,
2510 sizeof(ibdev->eq_table[0]), GFP_KERNEL);
e605b743
SP		 2511 if (!ibdev->eq_table)
2512 return;
2513
c66fa19c
MB		 2514 for (i = 1; i <= dev->caps.num_ports; i++) {
2515 for (j = 0; j < mlx4_get_eqs_per_port(dev, i);
2516 j++, total_eqs++) {
2517 if (i > 1 && mlx4_is_eq_shared(dev, total_eqs))
2518 continue;
2519 ibdev->eq_table[eq] = total_eqs;
2520 if (!mlx4_assign_eq(dev, i,
2521 &ibdev->eq_table[eq]))
2522 eq++;
2523 else
2524 ibdev->eq_table[eq] = -1;
e605b743
SP		 2525 }
2526 }
2527
c66fa19c
MB		 2528 for (i = eq; i < dev->caps.num_comp_vectors;
2529 ibdev->eq_table[i++] = -1)
2530 ;
e605b743
SP		 2531
2532 /* Advertise the new number of EQs to clients */
c66fa19c 2533 ibdev->ib_dev.num_comp_vectors = eq;
e605b743
SP		 2534}
2535
2536static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
2537{
2538 int i;
c66fa19c 2539 int total_eqs = ibdev->ib_dev.num_comp_vectors;
3aac6ff1 2540
c66fa19c 2541 /* no eqs were allocated */
3aac6ff1
SP		 2542 if (!ibdev->eq_table)
2543 return;
e605b743
SP		 2544
2545 /* Reset the advertised EQ number */
c66fa19c 2546 ibdev->ib_dev.num_comp_vectors = 0;
e605b743 2547
c66fa19c 2548 for (i = 0; i < total_eqs; i++)
e605b743 2549 mlx4_release_eq(dev, ibdev->eq_table[i]);
e605b743 2550
e605b743 2551 kfree(ibdev->eq_table);
c66fa19c 2552 ibdev->eq_table = NULL;
e605b743
SP		 2553}
2554
7738613e
IW		 2555static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num,
2556 struct ib_port_immutable *immutable)
2557{
2558 struct ib_port_attr attr;
4ed088e6 2559 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
7738613e
IW		 2560 int err;
2561
4ed088e6 2562 if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND) {
f9b22e35 2563 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB;
bc63f9d5 2564 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
4ed088e6
MB		 2565 } else {
2566 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)
2567 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
2568 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
2569 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
2570 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
bc63f9d5
OG		 2571 immutable->core_cap_flags |= RDMA_CORE_PORT_RAW_PACKET;
2572 if (immutable->core_cap_flags & (RDMA_CORE_PORT_IBA_ROCE |
2573 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP))
2574 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
4ed088e6 2575 }
f9b22e35 2576
c4550c63
OG		 2577 err = ib_query_port(ibdev, port_num, &attr);
2578 if (err)
2579 return err;
2580
2581 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2582 immutable->gid_tbl_len = attr.gid_tbl_len;
2583
7738613e
IW		 2584 return 0;
2585}
2586
9abb0d1b 2587static void get_fw_ver_str(struct ib_device *device, char *str)
e9db59fc
IW		 2588{
2589 struct mlx4_ib_dev *dev =
2590 container_of(device, struct mlx4_ib_dev, ib_dev);
9abb0d1b 2591 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d",
e9db59fc
IW		 2592 (int) (dev->dev->caps.fw_ver >> 32),
2593 (int) (dev->dev->caps.fw_ver >> 16) & 0xffff,
2594 (int) dev->dev->caps.fw_ver & 0xffff);
2595}
2596
225c7b1f
RD		 2597static void *mlx4_ib_add(struct mlx4_dev *dev)
2598{
2599 struct mlx4_ib_dev *ibdev;
22e7ef9c 2600 int num_ports = 0;
035b1032 2601 int i, j;
fa417f7b
EC		 2602 int err;
2603 struct mlx4_ib_iboe *iboe;
4196670b 2604 int ib_num_ports = 0;
a5750090 2605 int num_req_counters;
c3abb51b
EBE		 2606 int allocated;
2607 u32 counter_index;
3ba8e31d 2608 struct counter_index *new_counter_index = NULL;
225c7b1f 2609
987c8f8f 2610 pr_info_once("%s", mlx4_ib_version);
68f3948d 2611
026149cb 2612 num_ports = 0;
fa417f7b 2613 mlx4_foreach_ib_transport_port(i, dev)
22e7ef9c
RD		 2614 num_ports++;
2615
2616 /* No point in registering a device with no ports... */
2617 if (num_ports == 0)
2618 return NULL;
2619
225c7b1f
RD		 2620 ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev);
2621 if (!ibdev) {
872bf2fb
YH		 2622 dev_err(&dev->persist->pdev->dev,
2623 "Device struct alloc failed\n");
225c7b1f
RD		 2624 return NULL;
2625 }
2626
fa417f7b
EC		 2627 iboe = &ibdev->iboe;
2628
225c7b1f
RD		 2629 if (mlx4_pd_alloc(dev, &ibdev->priv_pdn))
2630 goto err_dealloc;
2631
2632 if (mlx4_uar_alloc(dev, &ibdev->priv_uar))
2633 goto err_pd;
2634
4979d18f
RD		 2635 ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT,
2636 PAGE_SIZE);
225c7b1f
RD		 2637 if (!ibdev->uar_map)
2638 goto err_uar;
26c6bc7b 2639 MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock);
225c7b1f 2640
225c7b1f 2641 ibdev->dev = dev;
c6215745 2642 ibdev->bond_next_port = 0;
225c7b1f
RD		 2643
2644 strlcpy(ibdev->ib_dev.name, "mlx4_%d", IB_DEVICE_NAME_MAX);
2645 ibdev->ib_dev.owner = THIS_MODULE;
2646 ibdev->ib_dev.node_type = RDMA_NODE_IB_CA;
95d04f07 2647 ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey;
22e7ef9c 2648 ibdev->num_ports = num_ports;
a5750090
MS		 2649 ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ?
2650 1 : ibdev->num_ports;
b8dd786f 2651 ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors;
d66c88a8 2652 ibdev->ib_dev.dev.parent = &dev->persist->pdev->dev;
5070cd22
MS		 2653 ibdev->ib_dev.get_netdev = mlx4_ib_get_netdev;
2654 ibdev->ib_dev.add_gid = mlx4_ib_add_gid;
2655 ibdev->ib_dev.del_gid = mlx4_ib_del_gid;
225c7b1f 2656
08ff3235
OG		 2657 if (dev->caps.userspace_caps)
2658 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION;
2659 else
2660 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION;
2661
225c7b1f
RD		 2662 ibdev->ib_dev.uverbs_cmd_mask =
2663 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2664 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2665 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2666 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2667 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2668 (1ull << IB_USER_VERBS_CMD_REG_MR) |
9376932d 2669 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
225c7b1f
RD		 2670 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2671 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2672 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
bbf8eed1 2673 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
225c7b1f
RD		 2674 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2675 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2676 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
6a775e2b 2677 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
225c7b1f
RD		 2678 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2679 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2680 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2681 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2682 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
65541cb7 2683 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
18abd5ea 2684 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
42849b26
SH		 2685 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
2686 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
225c7b1f
RD		 2687
2688 ibdev->ib_dev.query_device = mlx4_ib_query_device;
2689 ibdev->ib_dev.query_port = mlx4_ib_query_port;
fa417f7b 2690 ibdev->ib_dev.get_link_layer = mlx4_ib_port_link_layer;
225c7b1f
RD		 2691 ibdev->ib_dev.query_gid = mlx4_ib_query_gid;
2692 ibdev->ib_dev.query_pkey = mlx4_ib_query_pkey;
2693 ibdev->ib_dev.modify_device = mlx4_ib_modify_device;
2694 ibdev->ib_dev.modify_port = mlx4_ib_modify_port;
2695 ibdev->ib_dev.alloc_ucontext = mlx4_ib_alloc_ucontext;
2696 ibdev->ib_dev.dealloc_ucontext = mlx4_ib_dealloc_ucontext;
2697 ibdev->ib_dev.mmap = mlx4_ib_mmap;
2698 ibdev->ib_dev.alloc_pd = mlx4_ib_alloc_pd;
2699 ibdev->ib_dev.dealloc_pd = mlx4_ib_dealloc_pd;
2700 ibdev->ib_dev.create_ah = mlx4_ib_create_ah;
2701 ibdev->ib_dev.query_ah = mlx4_ib_query_ah;
2702 ibdev->ib_dev.destroy_ah = mlx4_ib_destroy_ah;
2703 ibdev->ib_dev.create_srq = mlx4_ib_create_srq;
2704 ibdev->ib_dev.modify_srq = mlx4_ib_modify_srq;
65541cb7 2705 ibdev->ib_dev.query_srq = mlx4_ib_query_srq;
225c7b1f
RD		 2706 ibdev->ib_dev.destroy_srq = mlx4_ib_destroy_srq;
2707 ibdev->ib_dev.post_srq_recv = mlx4_ib_post_srq_recv;
2708 ibdev->ib_dev.create_qp = mlx4_ib_create_qp;
2709 ibdev->ib_dev.modify_qp = mlx4_ib_modify_qp;
6a775e2b 2710 ibdev->ib_dev.query_qp = mlx4_ib_query_qp;
225c7b1f
RD		 2711 ibdev->ib_dev.destroy_qp = mlx4_ib_destroy_qp;
2712 ibdev->ib_dev.post_send = mlx4_ib_post_send;
2713 ibdev->ib_dev.post_recv = mlx4_ib_post_recv;
2714 ibdev->ib_dev.create_cq = mlx4_ib_create_cq;
3fdcb97f 2715 ibdev->ib_dev.modify_cq = mlx4_ib_modify_cq;
bbf8eed1 2716 ibdev->ib_dev.resize_cq = mlx4_ib_resize_cq;
225c7b1f
RD		 2717 ibdev->ib_dev.destroy_cq = mlx4_ib_destroy_cq;
2718 ibdev->ib_dev.poll_cq = mlx4_ib_poll_cq;
2719 ibdev->ib_dev.req_notify_cq = mlx4_ib_arm_cq;
2720 ibdev->ib_dev.get_dma_mr = mlx4_ib_get_dma_mr;
2721 ibdev->ib_dev.reg_user_mr = mlx4_ib_reg_user_mr;
9376932d 2722 ibdev->ib_dev.rereg_user_mr = mlx4_ib_rereg_user_mr;
225c7b1f 2723 ibdev->ib_dev.dereg_mr = mlx4_ib_dereg_mr;
679e34d1 2724 ibdev->ib_dev.alloc_mr = mlx4_ib_alloc_mr;
1b2cd0fc 2725 ibdev->ib_dev.map_mr_sg = mlx4_ib_map_mr_sg;
225c7b1f
RD		 2726 ibdev->ib_dev.attach_mcast = mlx4_ib_mcg_attach;
2727 ibdev->ib_dev.detach_mcast = mlx4_ib_mcg_detach;
2728 ibdev->ib_dev.process_mad = mlx4_ib_process_mad;
7738613e 2729 ibdev->ib_dev.get_port_immutable = mlx4_port_immutable;
e9db59fc 2730 ibdev->ib_dev.get_dev_fw_str = get_fw_ver_str;
ae184dde 2731 ibdev->ib_dev.disassociate_ucontext = mlx4_ib_disassociate_ucontext;
225c7b1f 2732
34d9a270
YC		 2733 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2734 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
2735
400b1ebc
GL		 2736 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) &&
2737 ((mlx4_ib_port_link_layer(&ibdev->ib_dev, 1) ==
2738 IB_LINK_LAYER_ETHERNET) ||
2739 (mlx4_ib_port_link_layer(&ibdev->ib_dev, 2) ==
2740 IB_LINK_LAYER_ETHERNET))) {
2741 ibdev->ib_dev.create_wq = mlx4_ib_create_wq;
2742 ibdev->ib_dev.modify_wq = mlx4_ib_modify_wq;
2743 ibdev->ib_dev.destroy_wq = mlx4_ib_destroy_wq;
b8d46ca0
GL		 2744 ibdev->ib_dev.create_rwq_ind_table =
2745 mlx4_ib_create_rwq_ind_table;
2746 ibdev->ib_dev.destroy_rwq_ind_table =
2747 mlx4_ib_destroy_rwq_ind_table;
400b1ebc 2748 ibdev->ib_dev.uverbs_ex_cmd_mask |=
b8d46ca0
GL		 2749 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
2750 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
2751 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
2752 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
2753 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
400b1ebc
GL		 2754 }
2755
992e8e6e
JM		 2756 if (!mlx4_is_slave(ibdev->dev)) {
2757 ibdev->ib_dev.alloc_fmr = mlx4_ib_fmr_alloc;
2758 ibdev->ib_dev.map_phys_fmr = mlx4_ib_map_phys_fmr;
2759 ibdev->ib_dev.unmap_fmr = mlx4_ib_unmap_fmr;
2760 ibdev->ib_dev.dealloc_fmr = mlx4_ib_fmr_dealloc;
2761 }
8ad11fb6 2762
b425388d
SM		 2763 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2764 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
2765 ibdev->ib_dev.alloc_mw = mlx4_ib_alloc_mw;
b425388d
SM		 2766 ibdev->ib_dev.dealloc_mw = mlx4_ib_dealloc_mw;
2767
2768 ibdev->ib_dev.uverbs_cmd_mask |=
2769 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
2770 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
2771 }
2772
012a8ff5
SH		 2773 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) {
2774 ibdev->ib_dev.alloc_xrcd = mlx4_ib_alloc_xrcd;
2775 ibdev->ib_dev.dealloc_xrcd = mlx4_ib_dealloc_xrcd;
2776 ibdev->ib_dev.uverbs_cmd_mask |=
2777 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
2778 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
2779 }
2780
f77c0162 2781 if (check_flow_steering_support(dev)) {
0a9b7d59 2782 ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED;
f77c0162
HHZ		 2783 ibdev->ib_dev.create_flow = mlx4_ib_create_flow;
2784 ibdev->ib_dev.destroy_flow = mlx4_ib_destroy_flow;
2785
f21519b2
YD		 2786 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2787 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
2788 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
f77c0162
HHZ		 2789 }
2790
4b664c43
MB		 2791 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2792 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
fbfb6625
EBE		 2793 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
2794 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
4b664c43 2795
e605b743
SP		 2796 mlx4_ib_alloc_eqs(dev, ibdev);
2797
fa417f7b
EC		 2798 spin_lock_init(&iboe->lock);
2799
225c7b1f
RD		 2800 if (init_node_data(ibdev))
2801 goto err_map;
fd10ed8e 2802 mlx4_init_sl2vl_tbl(ibdev);
225c7b1f 2803
3ba8e31d
EBE		 2804 for (i = 0; i < ibdev->num_ports; ++i) {
2805 mutex_init(&ibdev->counters_table[i].mutex);
2806 INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list);
2807 }
2808
a5750090
MS		 2809 num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports;
2810 for (i = 0; i < num_req_counters; ++i) {
9433c188 2811 mutex_init(&ibdev->qp1_proxy_lock[i]);
c3abb51b 2812 allocated = 0;
cfcde11c
OG		 2813 if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) ==
2814 IB_LINK_LAYER_ETHERNET) {
f3301870
MS		 2815 err = mlx4_counter_alloc(ibdev->dev, &counter_index,
2816 MLX4_RES_USAGE_DRIVER);
c3abb51b 2817 /* if failed to allocate a new counter, use default */
cfcde11c 2818 if (err)
c3abb51b
EBE		 2819 counter_index =
2820 mlx4_get_default_counter_index(dev,
2821 i + 1);
2822 else
2823 allocated = 1;
2824 } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */
2825 counter_index = mlx4_get_default_counter_index(dev,
2826 i + 1);
3839d8ac 2827 }
3ba8e31d
EBE		 2828 new_counter_index = kmalloc(sizeof(*new_counter_index),
2829 GFP_KERNEL);
2830 if (!new_counter_index) {
2831 if (allocated)
2832 mlx4_counter_free(ibdev->dev, counter_index);
2833 goto err_counter;
2834 }
2835 new_counter_index->index = counter_index;
2836 new_counter_index->allocated = allocated;
2837 list_add_tail(&new_counter_index->list,
2838 &ibdev->counters_table[i].counters_list);
2839 ibdev->counters_table[i].default_counter = counter_index;
c3abb51b
EBE		 2840 pr_info("counter index %d for port %d allocated %d\n",
2841 counter_index, i + 1, allocated);
cfcde11c 2842 }
a5750090 2843 if (mlx4_is_bonded(dev))
c3abb51b 2844 for (i = 1; i < ibdev->num_ports ; ++i) {
3ba8e31d
EBE		 2845 new_counter_index =
2846 kmalloc(sizeof(struct counter_index),
2847 GFP_KERNEL);
2848 if (!new_counter_index)
2849 goto err_counter;
2850 new_counter_index->index = counter_index;
2851 new_counter_index->allocated = 0;
2852 list_add_tail(&new_counter_index->list,
2853 &ibdev->counters_table[i].counters_list);
2854 ibdev->counters_table[i].default_counter =
2855 counter_index;
c3abb51b 2856 }
cfcde11c 2857
4196670b
MB		 2858 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2859 ib_num_ports++;
2860
225c7b1f
RD		 2861 spin_lock_init(&ibdev->sm_lock);
2862 mutex_init(&ibdev->cap_mask_mutex);
35f05dab
YH		 2863 INIT_LIST_HEAD(&ibdev->qp_list);
2864 spin_lock_init(&ibdev->reset_flow_resource_lock);
225c7b1f 2865
4196670b
MB		 2866 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED &&
2867 ib_num_ports) {
c1c98501
MB		 2868 ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS;
2869 err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count,
2870 MLX4_IB_UC_STEER_QPN_ALIGN,
f3301870
MS		 2871 &ibdev->steer_qpn_base, 0,
2872 MLX4_RES_USAGE_DRIVER);
c1c98501
MB		 2873 if (err)
2874 goto err_counter;
2875
2876 ibdev->ib_uc_qpns_bitmap =
6da2ec56
KC		 2877 kmalloc_array(BITS_TO_LONGS(ibdev->steer_qpn_count),
2878 sizeof(long),
2879 GFP_KERNEL);
15d4626e 2880 if (!ibdev->ib_uc_qpns_bitmap)
c1c98501 2881 goto err_steer_qp_release;
c1c98501 2882
1f22e454
EBE		 2883 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB) {
2884 bitmap_zero(ibdev->ib_uc_qpns_bitmap,
2885 ibdev->steer_qpn_count);
2886 err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE(
2887 dev, ibdev->steer_qpn_base,
2888 ibdev->steer_qpn_base +
2889 ibdev->steer_qpn_count - 1);
2890 if (err)
2891 goto err_steer_free_bitmap;
2892 } else {
2893 bitmap_fill(ibdev->ib_uc_qpns_bitmap,
2894 ibdev->steer_qpn_count);
2895 }
c1c98501
MB		 2896 }
2897
3e0629cb
JM		 2898 for (j = 1; j <= ibdev->dev->caps.num_ports; j++)
2899 atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]);
2900
3f85f2aa 2901 if (mlx4_ib_alloc_diag_counters(ibdev))
c1c98501 2902 goto err_steer_free_bitmap;
225c7b1f 2903
0ede73bc 2904 ibdev->ib_dev.driver_id = RDMA_DRIVER_MLX4;
3f85f2aa
MB		 2905 if (ib_register_device(&ibdev->ib_dev, NULL))
2906 goto err_diag_counters;
2907
225c7b1f
RD		 2908 if (mlx4_ib_mad_init(ibdev))
2909 goto err_reg;
2910
fc06573d
JM		 2911 if (mlx4_ib_init_sriov(ibdev))
2912 goto err_mad;
2913
dd77abf8
MD		 2914 if (!iboe->nb.notifier_call) {
2915 iboe->nb.notifier_call = mlx4_ib_netdev_event;
2916 err = register_netdevice_notifier(&iboe->nb);
2917 if (err) {
2918 iboe->nb.notifier_call = NULL;
2919 goto err_notif;
71a39bbb 2920 }
fa417f7b 2921 }
dd77abf8
MD		 2922 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
2923 err = mlx4_config_roce_v2_port(dev, ROCE_V2_UDP_DPORT);
2924 if (err)
2925 goto err_notif;
2926 }
fa417f7b 2927
035b1032 2928 for (j = 0; j < ARRAY_SIZE(mlx4_class_attributes); ++j) {
f4e91eb4 2929 if (device_create_file(&ibdev->ib_dev.dev,
035b1032 2930 mlx4_class_attributes[j]))
fa417f7b 2931 goto err_notif;
cd9281d8
JM		 2932 }
2933
3b4a8cd5 2934 ibdev->ib_active = true;
09d4d087
JP		 2935 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2936 devlink_port_type_ib_set(mlx4_get_devlink_port(dev, i),
2937 &ibdev->ib_dev);
3b4a8cd5 2938
54679e14
JM		 2939 if (mlx4_is_mfunc(ibdev->dev))
2940 init_pkeys(ibdev);
2941
3806d08c
JM		 2942 /* create paravirt contexts for any VFs which are active */
2943 if (mlx4_is_master(ibdev->dev)) {
2944 for (j = 0; j < MLX4_MFUNC_MAX; j++) {
2945 if (j == mlx4_master_func_num(ibdev->dev))
2946 continue;
2947 if (mlx4_is_slave_active(ibdev->dev, j))
2948 do_slave_init(ibdev, j, 1);
2949 }
2950 }
225c7b1f
RD		 2951 return ibdev;
2952
fa417f7b 2953err_notif:
d487ee77
MS		 2954 if (ibdev->iboe.nb.notifier_call) {
2955 if (unregister_netdevice_notifier(&ibdev->iboe.nb))
2956 pr_warn("failure unregistering notifier\n");
2957 ibdev->iboe.nb.notifier_call = NULL;
2958 }
fa417f7b
EC		 2959 flush_workqueue(wq);
2960
fc06573d
JM		 2961 mlx4_ib_close_sriov(ibdev);
2962
2963err_mad:
2964 mlx4_ib_mad_cleanup(ibdev);
2965
225c7b1f
RD		 2966err_reg:
2967 ib_unregister_device(&ibdev->ib_dev);
2968
3f85f2aa
MB		 2969err_diag_counters:
2970 mlx4_ib_diag_cleanup(ibdev);
2971
c1c98501
MB		 2972err_steer_free_bitmap:
2973 kfree(ibdev->ib_uc_qpns_bitmap);
2974
2975err_steer_qp_release:
852f6927
JM		 2976 mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
2977 ibdev->steer_qpn_count);
cfcde11c 2978err_counter:
3ba8e31d
EBE		 2979 for (i = 0; i < ibdev->num_ports; ++i)
2980 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]);
2981
225c7b1f 2982err_map:
99e68909 2983 mlx4_ib_free_eqs(dev, ibdev);
225c7b1f
RD		 2984 iounmap(ibdev->uar_map);
2985
2986err_uar:
2987 mlx4_uar_free(dev, &ibdev->priv_uar);
2988
2989err_pd:
2990 mlx4_pd_free(dev, ibdev->priv_pdn);
2991
2992err_dealloc:
2993 ib_dealloc_device(&ibdev->ib_dev);
2994
2995 return NULL;
2996}
2997
c1c98501
MB		 2998int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn)
2999{
3000 int offset;
3001
3002 WARN_ON(!dev->ib_uc_qpns_bitmap);
3003
3004 offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap,
3005 dev->steer_qpn_count,
3006 get_count_order(count));
3007 if (offset < 0)
3008 return offset;
3009
3010 *qpn = dev->steer_qpn_base + offset;
3011 return 0;
3012}
3013
3014void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count)
3015{
3016 if (!qpn ||
3017 dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED)
3018 return;
3019
f77f3036
LR		 3020 if (WARN(qpn < dev->steer_qpn_base, "qpn = %u, steer_qpn_base = %u\n",
3021 qpn, dev->steer_qpn_base))
3022 /* not supposed to be here */
3023 return;
c1c98501
MB		 3024
3025 bitmap_release_region(dev->ib_uc_qpns_bitmap,
3026 qpn - dev->steer_qpn_base,
3027 get_count_order(count));
3028}
3029
3030int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
3031 int is_attach)
3032{
3033 int err;
3034 size_t flow_size;
3035 struct ib_flow_attr *flow = NULL;
3036 struct ib_flow_spec_ib *ib_spec;
3037
3038 if (is_attach) {
3039 flow_size = sizeof(struct ib_flow_attr) +
3040 sizeof(struct ib_flow_spec_ib);
3041 flow = kzalloc(flow_size, GFP_KERNEL);
3042 if (!flow)
3043 return -ENOMEM;
3044 flow->port = mqp->port;
3045 flow->num_of_specs = 1;
3046 flow->size = flow_size;
3047 ib_spec = (struct ib_flow_spec_ib *)(flow + 1);
3048 ib_spec->type = IB_FLOW_SPEC_IB;
3049 ib_spec->size = sizeof(struct ib_flow_spec_ib);
3050 /* Add an empty rule for IB L2 */
3051 memset(&ib_spec->mask, 0, sizeof(ib_spec->mask));
3052
3053 err = __mlx4_ib_create_flow(&mqp->ibqp, flow,
3054 IB_FLOW_DOMAIN_NIC,
3055 MLX4_FS_REGULAR,
3056 &mqp->reg_id);
3057 } else {
3058 err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id);
3059 }
3060 kfree(flow);
3061 return err;
3062}
3063
225c7b1f
RD		 3064static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr)
3065{
3066 struct mlx4_ib_dev *ibdev = ibdev_ptr;
3067 int p;
09d4d087 3068 int i;
225c7b1f 3069
09d4d087
JP		 3070 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
3071 devlink_port_type_clear(mlx4_get_devlink_port(dev, i));
4bf9715f
MS		 3072 ibdev->ib_active = false;
3073 flush_workqueue(wq);
3074
fc06573d 3075 mlx4_ib_close_sriov(ibdev);
a6a47771
YP		 3076 mlx4_ib_mad_cleanup(ibdev);
3077 ib_unregister_device(&ibdev->ib_dev);
3f85f2aa 3078 mlx4_ib_diag_cleanup(ibdev);
fa417f7b
EC		 3079 if (ibdev->iboe.nb.notifier_call) {
3080 if (unregister_netdevice_notifier(&ibdev->iboe.nb))
987c8f8f 3081 pr_warn("failure unregistering notifier\n");
fa417f7b
EC		 3082 ibdev->iboe.nb.notifier_call = NULL;
3083 }
c1c98501 3084
852f6927
JM		 3085 mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
3086 ibdev->steer_qpn_count);
3087 kfree(ibdev->ib_uc_qpns_bitmap);
c1c98501 3088
fa417f7b 3089 iounmap(ibdev->uar_map);
cfcde11c 3090 for (p = 0; p < ibdev->num_ports; ++p)
3ba8e31d
EBE		 3091 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]);
3092
fa417f7b 3093 mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB)
225c7b1f
RD		 3094 mlx4_CLOSE_PORT(dev, p);
3095
e605b743
SP		 3096 mlx4_ib_free_eqs(dev, ibdev);
3097
225c7b1f
RD		 3098 mlx4_uar_free(dev, &ibdev->priv_uar);
3099 mlx4_pd_free(dev, ibdev->priv_pdn);
3100 ib_dealloc_device(&ibdev->ib_dev);
3101}
3102
fc06573d
JM		 3103static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init)
3104{
3105 struct mlx4_ib_demux_work **dm = NULL;
3106 struct mlx4_dev *dev = ibdev->dev;
3107 int i;
3108 unsigned long flags;
449fc488
MB		 3109 struct mlx4_active_ports actv_ports;
3110 unsigned int ports;
3111 unsigned int first_port;
fc06573d
JM		 3112
3113 if (!mlx4_is_master(dev))
3114 return;
3115
449fc488
MB		 3116 actv_ports = mlx4_get_active_ports(dev, slave);
3117 ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
3118 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
3119
3120 dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC);
15d4626e 3121 if (!dm)
a39a98ff 3122 return;
fc06573d 3123
449fc488 3124 for (i = 0; i < ports; i++) {
fc06573d
JM		 3125 dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC);
3126 if (!dm[i]) {
a39a98ff
MS		 3127 while (--i >= 0)
3128 kfree(dm[i]);
fc06573d
JM		 3129 goto out;
3130 }
fc06573d 3131 INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work);
449fc488 3132 dm[i]->port = first_port + i + 1;
fc06573d
JM		 3133 dm[i]->slave = slave;
3134 dm[i]->do_init = do_init;
3135 dm[i]->dev = ibdev;
d9a047ae
DL		 3136 }
3137 /* initialize or tear down tunnel QPs for the slave */
3138 spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags);
3139 if (!ibdev->sriov.is_going_down) {
3140 for (i = 0; i < ports; i++)
fc06573d
JM		 3141 queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work);
3142 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
d9a047ae
DL		 3143 } else {
3144 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
3145 for (i = 0; i < ports; i++)
3146 kfree(dm[i]);
fc06573d
JM		 3147 }
3148out:
c89d1271 3149 kfree(dm);
fc06573d
JM		 3150 return;
3151}
3152
35f05dab
YH		 3153static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev)
3154{
3155 struct mlx4_ib_qp *mqp;
3156 unsigned long flags_qp;
3157 unsigned long flags_cq;
3158 struct mlx4_ib_cq *send_mcq, *recv_mcq;
3159 struct list_head cq_notify_list;
3160 struct mlx4_cq *mcq;
3161 unsigned long flags;
3162
3163 pr_warn("mlx4_ib_handle_catas_error was started\n");
3164 INIT_LIST_HEAD(&cq_notify_list);
3165
3166 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3167 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
3168
3169 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
3170 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
3171 if (mqp->sq.tail != mqp->sq.head) {
3172 send_mcq = to_mcq(mqp->ibqp.send_cq);
3173 spin_lock_irqsave(&send_mcq->lock, flags_cq);
3174 if (send_mcq->mcq.comp &&
3175 mqp->ibqp.send_cq->comp_handler) {
3176 if (!send_mcq->mcq.reset_notify_added) {
3177 send_mcq->mcq.reset_notify_added = 1;
3178 list_add_tail(&send_mcq->mcq.reset_notify,
3179 &cq_notify_list);
3180 }
3181 }
3182 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
3183 }
3184 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
3185 /* Now, handle the QP's receive queue */
3186 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
3187 /* no handling is needed for SRQ */
3188 if (!mqp->ibqp.srq) {
3189 if (mqp->rq.tail != mqp->rq.head) {
3190 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
3191 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
3192 if (recv_mcq->mcq.comp &&
3193 mqp->ibqp.recv_cq->comp_handler) {
3194 if (!recv_mcq->mcq.reset_notify_added) {
3195 recv_mcq->mcq.reset_notify_added = 1;
3196 list_add_tail(&recv_mcq->mcq.reset_notify,
3197 &cq_notify_list);
3198 }
3199 }
3200 spin_unlock_irqrestore(&recv_mcq->lock,
3201 flags_cq);
3202 }
3203 }
3204 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3205 }
3206
3207 list_for_each_entry(mcq, &cq_notify_list, reset_notify) {
3208 mcq->comp(mcq);
3209 }
3210 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3211 pr_warn("mlx4_ib_handle_catas_error ended\n");
3212}
3213
a5750090
MS		 3214static void handle_bonded_port_state_event(struct work_struct *work)
3215{
3216 struct ib_event_work *ew =
3217 container_of(work, struct ib_event_work, work);
3218 struct mlx4_ib_dev *ibdev = ew->ib_dev;
3219 enum ib_port_state bonded_port_state = IB_PORT_NOP;
3220 int i;
3221 struct ib_event ibev;
3222
3223 kfree(ew);
3224 spin_lock_bh(&ibdev->iboe.lock);
3225 for (i = 0; i < MLX4_MAX_PORTS; ++i) {
3226 struct net_device *curr_netdev = ibdev->iboe.netdevs[i];
217e8b16 3227 enum ib_port_state curr_port_state;
a5750090 3228
217e8b16
MS		 3229 if (!curr_netdev)
3230 continue;
3231
3232 curr_port_state =
a5750090
MS		 3233 (netif_running(curr_netdev) &&
3234 netif_carrier_ok(curr_netdev)) ?
3235 IB_PORT_ACTIVE : IB_PORT_DOWN;
3236
3237 bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ?
3238 curr_port_state : IB_PORT_ACTIVE;
3239 }
3240 spin_unlock_bh(&ibdev->iboe.lock);
3241
3242 ibev.device = &ibdev->ib_dev;
3243 ibev.element.port_num = 1;
3244 ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ?
3245 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
3246
3247 ib_dispatch_event(&ibev);
3248}
3249
fd10ed8e
JM		 3250void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port)
3251{
3252 u64 sl2vl;
3253 int err;
3254
3255 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, port, &sl2vl);
3256 if (err) {
3257 pr_err("Unable to get current sl to vl mapping for port %d. Using all zeroes (%d)\n",
3258 port, err);
3259 sl2vl = 0;
3260 }
3261 atomic64_set(&mdev->sl2vl[port - 1], sl2vl);
3262}
3263
3264static void ib_sl2vl_update_work(struct work_struct *work)
3265{
3266 struct ib_event_work *ew = container_of(work, struct ib_event_work, work);
3267 struct mlx4_ib_dev *mdev = ew->ib_dev;
3268 int port = ew->port;
3269
3270 mlx4_ib_sl2vl_update(mdev, port);
3271
3272 kfree(ew);
3273}
3274
3275void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev,
3276 int port)
3277{
3278 struct ib_event_work *ew;
3279
3280 ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
3281 if (ew) {
3282 INIT_WORK(&ew->work, ib_sl2vl_update_work);
3283 ew->port = port;
3284 ew->ib_dev = ibdev;
3285 queue_work(wq, &ew->work);
fd10ed8e
JM		 3286 }
3287}
3288
225c7b1f 3289static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr,
00f5ce99 3290 enum mlx4_dev_event event, unsigned long param)
225c7b1f
RD		 3291{
3292 struct ib_event ibev;
7ff93f8b 3293 struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr);
00f5ce99
JM		 3294 struct mlx4_eqe *eqe = NULL;
3295 struct ib_event_work *ew;
fc06573d 3296 int p = 0;
00f5ce99 3297
a5750090
MS		 3298 if (mlx4_is_bonded(dev) &&
3299 ((event == MLX4_DEV_EVENT_PORT_UP) ||
3300 (event == MLX4_DEV_EVENT_PORT_DOWN))) {
3301 ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
3302 if (!ew)
3303 return;
3304 INIT_WORK(&ew->work, handle_bonded_port_state_event);
3305 ew->ib_dev = ibdev;
3306 queue_work(wq, &ew->work);
3307 return;
3308 }
3309
00f5ce99
JM		 3310 if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE)
3311 eqe = (struct mlx4_eqe *)param;
3312 else
fc06573d 3313 p = (int) param;
225c7b1f
RD		 3314
3315 switch (event) {
37608eea 3316 case MLX4_DEV_EVENT_PORT_UP:
fc06573d
JM		 3317 if (p > ibdev->num_ports)
3318 return;
fd10ed8e 3319 if (!mlx4_is_slave(dev) &&
a0c64a17
JM		 3320 rdma_port_get_link_layer(&ibdev->ib_dev, p) ==
3321 IB_LINK_LAYER_INFINIBAND) {
fd10ed8e
JM		 3322 if (mlx4_is_master(dev))
3323 mlx4_ib_invalidate_all_guid_record(ibdev, p);
3324 if (ibdev->dev->flags & MLX4_FLAG_SECURE_HOST &&
3325 !(ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT))
3326 mlx4_sched_ib_sl2vl_update_work(ibdev, p);
a0c64a17 3327 }
37608eea 3328 ibev.event = IB_EVENT_PORT_ACTIVE;
225c7b1f
RD		 3329 break;
3330
37608eea 3331 case MLX4_DEV_EVENT_PORT_DOWN:
fc06573d
JM		 3332 if (p > ibdev->num_ports)
3333 return;
37608eea
RD		 3334 ibev.event = IB_EVENT_PORT_ERR;
3335 break;
3336
3337 case MLX4_DEV_EVENT_CATASTROPHIC_ERROR:
3b4a8cd5 3338 ibdev->ib_active = false;
225c7b1f 3339 ibev.event = IB_EVENT_DEVICE_FATAL;
35f05dab 3340 mlx4_ib_handle_catas_error(ibdev);
225c7b1f
RD		 3341 break;
3342
00f5ce99
JM		 3343 case MLX4_DEV_EVENT_PORT_MGMT_CHANGE:
3344 ew = kmalloc(sizeof *ew, GFP_ATOMIC);
15d4626e 3345 if (!ew)
00f5ce99 3346 break;
00f5ce99
JM		 3347
3348 INIT_WORK(&ew->work, handle_port_mgmt_change_event);
3349 memcpy(&ew->ib_eqe, eqe, sizeof *eqe);
3350 ew->ib_dev = ibdev;
992e8e6e
JM		 3351 /* need to queue only for port owner, which uses GEN_EQE */
3352 if (mlx4_is_master(dev))
3353 queue_work(wq, &ew->work);
3354 else
3355 handle_port_mgmt_change_event(&ew->work);
00f5ce99
JM		 3356 return;
3357
fc06573d
JM		 3358 case MLX4_DEV_EVENT_SLAVE_INIT:
3359 /* here, p is the slave id */
3360 do_slave_init(ibdev, p, 1);
ee59fa0d
YH		 3361 if (mlx4_is_master(dev)) {
3362 int i;
3363
3364 for (i = 1; i <= ibdev->num_ports; i++) {
3365 if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
3366 == IB_LINK_LAYER_INFINIBAND)
3367 mlx4_ib_slave_alias_guid_event(ibdev,
3368 p, i,
3369 1);
3370 }
3371 }
fc06573d
JM		 3372 return;
3373
3374 case MLX4_DEV_EVENT_SLAVE_SHUTDOWN:
ee59fa0d
YH		 3375 if (mlx4_is_master(dev)) {
3376 int i;
3377
3378 for (i = 1; i <= ibdev->num_ports; i++) {
3379 if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
3380 == IB_LINK_LAYER_INFINIBAND)
3381 mlx4_ib_slave_alias_guid_event(ibdev,
3382 p, i,
3383 0);
3384 }
3385 }
fc06573d
JM		 3386 /* here, p is the slave id */
3387 do_slave_init(ibdev, p, 0);
3388 return;
3389
225c7b1f
RD		 3390 default:
3391 return;
3392 }
3393
3394 ibev.device = ibdev_ptr;
a5750090 3395 ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p;
225c7b1f
RD		 3396
3397 ib_dispatch_event(&ibev);
3398}
3399
3400static struct mlx4_interface mlx4_ib_interface = {
fa417f7b
EC		 3401 .add = mlx4_ib_add,
3402 .remove = mlx4_ib_remove,
3403 .event = mlx4_ib_event,
a5750090
MS		 3404 .protocol = MLX4_PROT_IB_IPV6,
3405 .flags = MLX4_INTFF_BONDING
225c7b1f
RD		 3406};
3407
3408static int __init mlx4_ib_init(void)
3409{
fa417f7b
EC		 3410 int err;
3411
41cd3944 3412 wq = alloc_ordered_workqueue("mlx4_ib", WQ_MEM_RECLAIM);
fa417f7b
EC		 3413 if (!wq)
3414 return -ENOMEM;
3415
b9c5d6a6
OD		 3416 err = mlx4_ib_mcg_init();
3417 if (err)
3418 goto clean_wq;
3419
fa417f7b 3420 err = mlx4_register_interface(&mlx4_ib_interface);
b9c5d6a6
OD		 3421 if (err)
3422 goto clean_mcg;
fa417f7b
EC		 3423
3424 return 0;
b9c5d6a6
OD		 3425
3426clean_mcg:
3427 mlx4_ib_mcg_destroy();
3428
3429clean_wq:
3430 destroy_workqueue(wq);
3431 return err;
225c7b1f
RD		 3432}
3433
3434static void __exit mlx4_ib_cleanup(void)
3435{
3436 mlx4_unregister_interface(&mlx4_ib_interface);
b9c5d6a6 3437 mlx4_ib_mcg_destroy();
fa417f7b 3438 destroy_workqueue(wq);
225c7b1f
RD		 3439}
3440
3441module_init(mlx4_ib_init);
3442module_exit(mlx4_ib_cleanup);
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