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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2006, 2007 Cisco Systems. All rights reserved. | |
51a379d0 | 3 | * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
4 | * |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the | |
9 | * OpenIB.org BSD license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or | |
12 | * without modification, are permitted provided that the following | |
13 | * conditions are met: | |
14 | * | |
15 | * - Redistributions of source code must retain the above | |
16 | * copyright notice, this list of conditions and the following | |
17 | * disclaimer. | |
18 | * | |
19 | * - Redistributions in binary form must reproduce the above | |
20 | * copyright notice, this list of conditions and the following | |
21 | * disclaimer in the documentation and/or other materials | |
22 | * provided with the distribution. | |
23 | * | |
24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
31 | * SOFTWARE. | |
32 | */ | |
33 | ||
34 | #ifndef MLX4_IB_H | |
35 | #define MLX4_IB_H | |
36 | ||
37 | #include <linux/compiler.h> | |
38 | #include <linux/list.h> | |
63019d93 | 39 | #include <linux/mutex.h> |
b9c5d6a6 | 40 | #include <linux/idr.h> |
225c7b1f RD |
41 | |
42 | #include <rdma/ib_verbs.h> | |
43 | #include <rdma/ib_umem.h> | |
b9c5d6a6 | 44 | #include <rdma/ib_mad.h> |
a0c64a17 | 45 | #include <rdma/ib_sa.h> |
225c7b1f RD |
46 | |
47 | #include <linux/mlx4/device.h> | |
48 | #include <linux/mlx4/doorbell.h> | |
49 | ||
b1d8eb5a JM |
50 | #define MLX4_IB_DRV_NAME "mlx4_ib" |
51 | ||
52 | #ifdef pr_fmt | |
53 | #undef pr_fmt | |
54 | #endif | |
55 | #define pr_fmt(fmt) "<" MLX4_IB_DRV_NAME "> %s: " fmt, __func__ | |
56 | ||
57 | #define mlx4_ib_warn(ibdev, format, arg...) \ | |
d66c88a8 | 58 | dev_warn((ibdev)->dev.parent, MLX4_IB_DRV_NAME ": " format, ## arg) |
b1d8eb5a | 59 | |
fc2d0044 SG |
60 | enum { |
61 | MLX4_IB_SQ_MIN_WQE_SHIFT = 6, | |
62 | MLX4_IB_MAX_HEADROOM = 2048 | |
63 | }; | |
64 | ||
65 | #define MLX4_IB_SQ_HEADROOM(shift) ((MLX4_IB_MAX_HEADROOM >> (shift)) + 1) | |
66 | #define MLX4_IB_SQ_MAX_SPARE (MLX4_IB_SQ_HEADROOM(MLX4_IB_SQ_MIN_WQE_SHIFT)) | |
67 | ||
a0c64a17 JM |
68 | /*module param to indicate if SM assigns the alias_GUID*/ |
69 | extern int mlx4_ib_sm_guid_assign; | |
70 | ||
c1c98501 MB |
71 | #define MLX4_IB_UC_STEER_QPN_ALIGN 1 |
72 | #define MLX4_IB_UC_MAX_NUM_QPS 256 | |
ae184dde YH |
73 | |
74 | enum hw_bar_type { | |
75 | HW_BAR_BF, | |
76 | HW_BAR_DB, | |
77 | HW_BAR_CLOCK, | |
78 | HW_BAR_COUNT | |
79 | }; | |
80 | ||
81 | struct mlx4_ib_vma_private_data { | |
82 | struct vm_area_struct *vma; | |
83 | }; | |
84 | ||
225c7b1f RD |
85 | struct mlx4_ib_ucontext { |
86 | struct ib_ucontext ibucontext; | |
87 | struct mlx4_uar uar; | |
88 | struct list_head db_page_list; | |
89 | struct mutex db_page_mutex; | |
ae184dde | 90 | struct mlx4_ib_vma_private_data hw_bar_info[HW_BAR_COUNT]; |
225c7b1f RD |
91 | }; |
92 | ||
93 | struct mlx4_ib_pd { | |
94 | struct ib_pd ibpd; | |
95 | u32 pdn; | |
96 | }; | |
97 | ||
012a8ff5 SH |
98 | struct mlx4_ib_xrcd { |
99 | struct ib_xrcd ibxrcd; | |
100 | u32 xrcdn; | |
101 | struct ib_pd *pd; | |
102 | struct ib_cq *cq; | |
103 | }; | |
104 | ||
225c7b1f RD |
105 | struct mlx4_ib_cq_buf { |
106 | struct mlx4_buf buf; | |
107 | struct mlx4_mtt mtt; | |
08ff3235 | 108 | int entry_size; |
225c7b1f RD |
109 | }; |
110 | ||
bbf8eed1 VS |
111 | struct mlx4_ib_cq_resize { |
112 | struct mlx4_ib_cq_buf buf; | |
113 | int cqe; | |
114 | }; | |
115 | ||
225c7b1f RD |
116 | struct mlx4_ib_cq { |
117 | struct ib_cq ibcq; | |
118 | struct mlx4_cq mcq; | |
119 | struct mlx4_ib_cq_buf buf; | |
bbf8eed1 | 120 | struct mlx4_ib_cq_resize *resize_buf; |
6296883c | 121 | struct mlx4_db db; |
225c7b1f | 122 | spinlock_t lock; |
bbf8eed1 | 123 | struct mutex resize_mutex; |
225c7b1f | 124 | struct ib_umem *umem; |
bbf8eed1 | 125 | struct ib_umem *resize_umem; |
4b664c43 | 126 | int create_flags; |
35f05dab YH |
127 | /* List of qps that it serves.*/ |
128 | struct list_head send_qp_list; | |
129 | struct list_head recv_qp_list; | |
225c7b1f RD |
130 | }; |
131 | ||
1b2cd0fc SG |
132 | #define MLX4_MR_PAGES_ALIGN 0x40 |
133 | ||
225c7b1f RD |
134 | struct mlx4_ib_mr { |
135 | struct ib_mr ibmr; | |
1b2cd0fc SG |
136 | __be64 *pages; |
137 | dma_addr_t page_map; | |
138 | u32 npages; | |
139 | u32 max_pages; | |
225c7b1f RD |
140 | struct mlx4_mr mmr; |
141 | struct ib_umem *umem; | |
cbc9355a | 142 | size_t page_map_size; |
225c7b1f RD |
143 | }; |
144 | ||
804d6a89 SM |
145 | struct mlx4_ib_mw { |
146 | struct ib_mw ibmw; | |
147 | struct mlx4_mw mmw; | |
148 | }; | |
149 | ||
8ad11fb6 JM |
150 | struct mlx4_ib_fmr { |
151 | struct ib_fmr ibfmr; | |
152 | struct mlx4_fmr mfmr; | |
153 | }; | |
154 | ||
146d6e19 MS |
155 | #define MAX_REGS_PER_FLOW 2 |
156 | ||
157 | struct mlx4_flow_reg_id { | |
158 | u64 id; | |
159 | u64 mirror; | |
160 | }; | |
161 | ||
f77c0162 HHZ |
162 | struct mlx4_ib_flow { |
163 | struct ib_flow ibflow; | |
164 | /* translating DMFS verbs sniffer rule to FW API requires two reg IDs */ | |
146d6e19 | 165 | struct mlx4_flow_reg_id reg_id[MAX_REGS_PER_FLOW]; |
f77c0162 HHZ |
166 | }; |
167 | ||
225c7b1f RD |
168 | struct mlx4_ib_wq { |
169 | u64 *wrid; | |
170 | spinlock_t lock; | |
0e6e7416 RD |
171 | int wqe_cnt; |
172 | int max_post; | |
225c7b1f RD |
173 | int max_gs; |
174 | int offset; | |
175 | int wqe_shift; | |
176 | unsigned head; | |
177 | unsigned tail; | |
178 | }; | |
179 | ||
e1b866c6 MS |
180 | enum { |
181 | MLX4_IB_QP_CREATE_ROCE_V2_GSI = IB_QP_CREATE_RESERVED_START | |
182 | }; | |
183 | ||
b832be1e | 184 | enum mlx4_ib_qp_flags { |
1ffeb2eb JM |
185 | MLX4_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO, |
186 | MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, | |
c1c98501 | 187 | MLX4_IB_QP_NETIF = IB_QP_CREATE_NETIF_QP, |
40f2287b | 188 | MLX4_IB_QP_CREATE_USE_GFP_NOIO = IB_QP_CREATE_USE_GFP_NOIO, |
e1b866c6 MS |
189 | |
190 | /* Mellanox specific flags start from IB_QP_CREATE_RESERVED_START */ | |
191 | MLX4_IB_ROCE_V2_GSI_QP = MLX4_IB_QP_CREATE_ROCE_V2_GSI, | |
1ffeb2eb JM |
192 | MLX4_IB_SRIOV_TUNNEL_QP = 1 << 30, |
193 | MLX4_IB_SRIOV_SQP = 1 << 31, | |
b832be1e EC |
194 | }; |
195 | ||
fa417f7b EC |
196 | struct mlx4_ib_gid_entry { |
197 | struct list_head list; | |
198 | union ib_gid gid; | |
199 | int added; | |
200 | u8 port; | |
201 | }; | |
202 | ||
1ffeb2eb JM |
203 | enum mlx4_ib_qp_type { |
204 | /* | |
205 | * IB_QPT_SMI and IB_QPT_GSI have to be the first two entries | |
206 | * here (and in that order) since the MAD layer uses them as | |
207 | * indices into a 2-entry table. | |
208 | */ | |
209 | MLX4_IB_QPT_SMI = IB_QPT_SMI, | |
210 | MLX4_IB_QPT_GSI = IB_QPT_GSI, | |
211 | ||
212 | MLX4_IB_QPT_RC = IB_QPT_RC, | |
213 | MLX4_IB_QPT_UC = IB_QPT_UC, | |
214 | MLX4_IB_QPT_UD = IB_QPT_UD, | |
215 | MLX4_IB_QPT_RAW_IPV6 = IB_QPT_RAW_IPV6, | |
216 | MLX4_IB_QPT_RAW_ETHERTYPE = IB_QPT_RAW_ETHERTYPE, | |
217 | MLX4_IB_QPT_RAW_PACKET = IB_QPT_RAW_PACKET, | |
218 | MLX4_IB_QPT_XRC_INI = IB_QPT_XRC_INI, | |
219 | MLX4_IB_QPT_XRC_TGT = IB_QPT_XRC_TGT, | |
220 | ||
221 | MLX4_IB_QPT_PROXY_SMI_OWNER = 1 << 16, | |
222 | MLX4_IB_QPT_PROXY_SMI = 1 << 17, | |
223 | MLX4_IB_QPT_PROXY_GSI = 1 << 18, | |
224 | MLX4_IB_QPT_TUN_SMI_OWNER = 1 << 19, | |
225 | MLX4_IB_QPT_TUN_SMI = 1 << 20, | |
226 | MLX4_IB_QPT_TUN_GSI = 1 << 21, | |
227 | }; | |
228 | ||
229 | #define MLX4_IB_QPT_ANY_SRIOV (MLX4_IB_QPT_PROXY_SMI_OWNER | \ | |
230 | MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER | \ | |
231 | MLX4_IB_QPT_TUN_SMI | MLX4_IB_QPT_TUN_GSI) | |
232 | ||
0a9a0188 JM |
233 | enum mlx4_ib_mad_ifc_flags { |
234 | MLX4_MAD_IFC_IGNORE_MKEY = 1, | |
235 | MLX4_MAD_IFC_IGNORE_BKEY = 2, | |
236 | MLX4_MAD_IFC_IGNORE_KEYS = (MLX4_MAD_IFC_IGNORE_MKEY | | |
237 | MLX4_MAD_IFC_IGNORE_BKEY), | |
238 | MLX4_MAD_IFC_NET_VIEW = 4, | |
239 | }; | |
240 | ||
fc06573d JM |
241 | enum { |
242 | MLX4_NUM_TUNNEL_BUFS = 256, | |
243 | }; | |
244 | ||
1ffeb2eb JM |
245 | struct mlx4_ib_tunnel_header { |
246 | struct mlx4_av av; | |
247 | __be32 remote_qpn; | |
248 | __be32 qkey; | |
249 | __be16 vlan; | |
250 | u8 mac[6]; | |
251 | __be16 pkey_index; | |
252 | u8 reserved[6]; | |
253 | }; | |
254 | ||
255 | struct mlx4_ib_buf { | |
256 | void *addr; | |
257 | dma_addr_t map; | |
258 | }; | |
259 | ||
260 | struct mlx4_rcv_tunnel_hdr { | |
261 | __be32 flags_src_qp; /* flags[6:5] is defined for VLANs: | |
262 | * 0x0 - no vlan was in the packet | |
263 | * 0x01 - C-VLAN was in the packet */ | |
264 | u8 g_ml_path; /* gid bit stands for ipv6/4 header in RoCE */ | |
265 | u8 reserved; | |
266 | __be16 pkey_index; | |
267 | __be16 sl_vid; | |
268 | __be16 slid_mac_47_32; | |
269 | __be32 mac_31_0; | |
270 | }; | |
271 | ||
272 | struct mlx4_ib_proxy_sqp_hdr { | |
273 | struct ib_grh grh; | |
274 | struct mlx4_rcv_tunnel_hdr tun; | |
275 | } __packed; | |
276 | ||
2f5bb473 JM |
277 | struct mlx4_roce_smac_vlan_info { |
278 | u64 smac; | |
279 | int smac_index; | |
280 | int smac_port; | |
281 | u64 candidate_smac; | |
282 | int candidate_smac_index; | |
283 | int candidate_smac_port; | |
284 | u16 vid; | |
285 | int vlan_index; | |
286 | int vlan_port; | |
287 | u16 candidate_vid; | |
288 | int candidate_vlan_index; | |
289 | int candidate_vlan_port; | |
290 | int update_vid; | |
291 | }; | |
292 | ||
225c7b1f RD |
293 | struct mlx4_ib_qp { |
294 | struct ib_qp ibqp; | |
295 | struct mlx4_qp mqp; | |
296 | struct mlx4_buf buf; | |
297 | ||
6296883c | 298 | struct mlx4_db db; |
225c7b1f RD |
299 | struct mlx4_ib_wq rq; |
300 | ||
301 | u32 doorbell_qpn; | |
302 | __be32 sq_signal_bits; | |
ea54b10c JM |
303 | unsigned sq_next_wqe; |
304 | int sq_max_wqes_per_wr; | |
0e6e7416 | 305 | int sq_spare_wqes; |
225c7b1f RD |
306 | struct mlx4_ib_wq sq; |
307 | ||
1ffeb2eb | 308 | enum mlx4_ib_qp_type mlx4_ib_qp_type; |
225c7b1f RD |
309 | struct ib_umem *umem; |
310 | struct mlx4_mtt mtt; | |
311 | int buf_size; | |
312 | struct mutex mutex; | |
0a1405da | 313 | u16 xrcdn; |
b832be1e | 314 | u32 flags; |
225c7b1f RD |
315 | u8 port; |
316 | u8 alt_port; | |
317 | u8 atomic_rd_en; | |
318 | u8 resp_depth; | |
0e6e7416 | 319 | u8 sq_no_prefetch; |
225c7b1f | 320 | u8 state; |
fa417f7b EC |
321 | int mlx_type; |
322 | struct list_head gid_list; | |
0ff1fb65 | 323 | struct list_head steering_rules; |
1ffeb2eb | 324 | struct mlx4_ib_buf *sqp_proxy_rcv; |
2f5bb473 JM |
325 | struct mlx4_roce_smac_vlan_info pri; |
326 | struct mlx4_roce_smac_vlan_info alt; | |
c1c98501 | 327 | u64 reg_id; |
35f05dab YH |
328 | struct list_head qps_list; |
329 | struct list_head cq_recv_list; | |
330 | struct list_head cq_send_list; | |
7b59f0f9 | 331 | struct counter_index *counter_index; |
225c7b1f RD |
332 | }; |
333 | ||
334 | struct mlx4_ib_srq { | |
335 | struct ib_srq ibsrq; | |
336 | struct mlx4_srq msrq; | |
337 | struct mlx4_buf buf; | |
6296883c | 338 | struct mlx4_db db; |
225c7b1f RD |
339 | u64 *wrid; |
340 | spinlock_t lock; | |
341 | int head; | |
342 | int tail; | |
343 | u16 wqe_ctr; | |
344 | struct ib_umem *umem; | |
345 | struct mlx4_mtt mtt; | |
346 | struct mutex mutex; | |
347 | }; | |
348 | ||
349 | struct mlx4_ib_ah { | |
350 | struct ib_ah ibah; | |
fa417f7b EC |
351 | union mlx4_ext_av av; |
352 | }; | |
353 | ||
a0c64a17 JM |
354 | /****************************************/ |
355 | /* alias guid support */ | |
356 | /****************************************/ | |
357 | #define NUM_PORT_ALIAS_GUID 2 | |
358 | #define NUM_ALIAS_GUID_IN_REC 8 | |
359 | #define NUM_ALIAS_GUID_REC_IN_PORT 16 | |
360 | #define GUID_REC_SIZE 8 | |
361 | #define NUM_ALIAS_GUID_PER_PORT 128 | |
362 | #define MLX4_NOT_SET_GUID (0x00LL) | |
363 | #define MLX4_GUID_FOR_DELETE_VAL (~(0x00LL)) | |
364 | ||
365 | enum mlx4_guid_alias_rec_status { | |
366 | MLX4_GUID_INFO_STATUS_IDLE, | |
367 | MLX4_GUID_INFO_STATUS_SET, | |
a0c64a17 JM |
368 | }; |
369 | ||
f5479601 | 370 | #define GUID_STATE_NEED_PORT_INIT 0x01 |
a0c64a17 JM |
371 | |
372 | enum mlx4_guid_alias_rec_method { | |
373 | MLX4_GUID_INFO_RECORD_SET = IB_MGMT_METHOD_SET, | |
374 | MLX4_GUID_INFO_RECORD_DELETE = IB_SA_METHOD_DELETE, | |
375 | }; | |
376 | ||
377 | struct mlx4_sriov_alias_guid_info_rec_det { | |
378 | u8 all_recs[GUID_REC_SIZE * NUM_ALIAS_GUID_IN_REC]; | |
379 | ib_sa_comp_mask guid_indexes; /*indicates what from the 8 records are valid*/ | |
380 | enum mlx4_guid_alias_rec_status status; /*indicates the administraively status of the record.*/ | |
99ee4df6 YH |
381 | unsigned int guids_retry_schedule[NUM_ALIAS_GUID_IN_REC]; |
382 | u64 time_to_run; | |
a0c64a17 JM |
383 | }; |
384 | ||
385 | struct mlx4_sriov_alias_guid_port_rec_det { | |
386 | struct mlx4_sriov_alias_guid_info_rec_det all_rec_per_port[NUM_ALIAS_GUID_REC_IN_PORT]; | |
387 | struct workqueue_struct *wq; | |
388 | struct delayed_work alias_guid_work; | |
389 | u8 port; | |
f5479601 | 390 | u32 state_flags; |
a0c64a17 JM |
391 | struct mlx4_sriov_alias_guid *parent; |
392 | struct list_head cb_list; | |
393 | }; | |
394 | ||
395 | struct mlx4_sriov_alias_guid { | |
396 | struct mlx4_sriov_alias_guid_port_rec_det ports_guid[MLX4_MAX_PORTS]; | |
397 | spinlock_t ag_work_lock; | |
398 | struct ib_sa_client *sa_client; | |
399 | }; | |
400 | ||
fc06573d JM |
401 | struct mlx4_ib_demux_work { |
402 | struct work_struct work; | |
403 | struct mlx4_ib_dev *dev; | |
404 | int slave; | |
405 | int do_init; | |
406 | u8 port; | |
407 | ||
408 | }; | |
409 | ||
1ffeb2eb JM |
410 | struct mlx4_ib_tun_tx_buf { |
411 | struct mlx4_ib_buf buf; | |
412 | struct ib_ah *ah; | |
413 | }; | |
414 | ||
415 | struct mlx4_ib_demux_pv_qp { | |
416 | struct ib_qp *qp; | |
417 | enum ib_qp_type proxy_qpt; | |
418 | struct mlx4_ib_buf *ring; | |
419 | struct mlx4_ib_tun_tx_buf *tx_ring; | |
420 | spinlock_t tx_lock; | |
421 | unsigned tx_ix_head; | |
422 | unsigned tx_ix_tail; | |
423 | }; | |
424 | ||
fc06573d JM |
425 | enum mlx4_ib_demux_pv_state { |
426 | DEMUX_PV_STATE_DOWN, | |
427 | DEMUX_PV_STATE_STARTING, | |
428 | DEMUX_PV_STATE_ACTIVE, | |
429 | DEMUX_PV_STATE_DOWNING, | |
430 | }; | |
431 | ||
1ffeb2eb JM |
432 | struct mlx4_ib_demux_pv_ctx { |
433 | int port; | |
434 | int slave; | |
fc06573d | 435 | enum mlx4_ib_demux_pv_state state; |
1ffeb2eb JM |
436 | int has_smi; |
437 | struct ib_device *ib_dev; | |
438 | struct ib_cq *cq; | |
439 | struct ib_pd *pd; | |
1ffeb2eb JM |
440 | struct work_struct work; |
441 | struct workqueue_struct *wq; | |
442 | struct mlx4_ib_demux_pv_qp qp[2]; | |
443 | }; | |
444 | ||
445 | struct mlx4_ib_demux_ctx { | |
446 | struct ib_device *ib_dev; | |
447 | int port; | |
448 | struct workqueue_struct *wq; | |
449 | struct workqueue_struct *ud_wq; | |
450 | spinlock_t ud_lock; | |
8ec07bf8 | 451 | atomic64_t subnet_prefix; |
1ffeb2eb JM |
452 | __be64 guid_cache[128]; |
453 | struct mlx4_ib_dev *dev; | |
b9c5d6a6 OD |
454 | /* the following lock protects both mcg_table and mcg_mgid0_list */ |
455 | struct mutex mcg_table_lock; | |
456 | struct rb_root mcg_table; | |
457 | struct list_head mcg_mgid0_list; | |
458 | struct workqueue_struct *mcg_wq; | |
1ffeb2eb | 459 | struct mlx4_ib_demux_pv_ctx **tun; |
b9c5d6a6 OD |
460 | atomic_t tid; |
461 | int flushing; /* flushing the work queue */ | |
1ffeb2eb JM |
462 | }; |
463 | ||
464 | struct mlx4_ib_sriov { | |
465 | struct mlx4_ib_demux_ctx demux[MLX4_MAX_PORTS]; | |
466 | struct mlx4_ib_demux_pv_ctx *sqps[MLX4_MAX_PORTS]; | |
467 | /* when using this spinlock you should use "irq" because | |
468 | * it may be called from interrupt context.*/ | |
469 | spinlock_t going_down_lock; | |
470 | int is_going_down; | |
3cf69cc8 | 471 | |
a0c64a17 JM |
472 | struct mlx4_sriov_alias_guid alias_guid; |
473 | ||
3cf69cc8 AV |
474 | /* CM paravirtualization fields */ |
475 | struct list_head cm_list; | |
476 | spinlock_t id_map_lock; | |
477 | struct rb_root sl_id_map; | |
478 | struct idr pv_id_table; | |
1ffeb2eb JM |
479 | }; |
480 | ||
e26be1bf MS |
481 | struct gid_cache_context { |
482 | int real_index; | |
483 | int refcount; | |
484 | }; | |
485 | ||
486 | struct gid_entry { | |
487 | union ib_gid gid; | |
b699a859 | 488 | enum ib_gid_type gid_type; |
e26be1bf MS |
489 | struct gid_cache_context *ctx; |
490 | }; | |
491 | ||
492 | struct mlx4_port_gid_table { | |
493 | struct gid_entry gids[MLX4_MAX_PORT_GIDS]; | |
494 | }; | |
495 | ||
fa417f7b EC |
496 | struct mlx4_ib_iboe { |
497 | spinlock_t lock; | |
498 | struct net_device *netdevs[MLX4_MAX_PORTS]; | |
3e0629cb | 499 | atomic64_t mac[MLX4_MAX_PORTS]; |
fa417f7b | 500 | struct notifier_block nb; |
e26be1bf | 501 | struct mlx4_port_gid_table gids[MLX4_MAX_PORTS]; |
225c7b1f RD |
502 | }; |
503 | ||
fc06573d JM |
504 | struct pkey_mgt { |
505 | u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS]; | |
506 | u16 phys_pkey_cache[MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS]; | |
507 | struct list_head pkey_port_list[MLX4_MFUNC_MAX]; | |
508 | struct kobject *device_parent[MLX4_MFUNC_MAX]; | |
509 | }; | |
510 | ||
c1e7e466 JM |
511 | struct mlx4_ib_iov_sysfs_attr { |
512 | void *ctx; | |
513 | struct kobject *kobj; | |
514 | unsigned long data; | |
515 | u32 entry_num; | |
516 | char name[15]; | |
517 | struct device_attribute dentry; | |
518 | struct device *dev; | |
519 | }; | |
520 | ||
521 | struct mlx4_ib_iov_sysfs_attr_ar { | |
522 | struct mlx4_ib_iov_sysfs_attr dentries[3 * NUM_ALIAS_GUID_PER_PORT + 1]; | |
523 | }; | |
524 | ||
525 | struct mlx4_ib_iov_port { | |
526 | char name[100]; | |
527 | u8 num; | |
528 | struct mlx4_ib_dev *dev; | |
529 | struct list_head list; | |
530 | struct mlx4_ib_iov_sysfs_attr_ar *dentr_ar; | |
531 | struct ib_port_attr attr; | |
532 | struct kobject *cur_port; | |
533 | struct kobject *admin_alias_parent; | |
534 | struct kobject *gids_parent; | |
535 | struct kobject *pkeys_parent; | |
536 | struct kobject *mcgs_parent; | |
537 | struct mlx4_ib_iov_sysfs_attr mcg_dentry; | |
538 | }; | |
539 | ||
c3abb51b | 540 | struct counter_index { |
3ba8e31d | 541 | struct list_head list; |
c3abb51b EBE |
542 | u32 index; |
543 | u8 allocated; | |
544 | }; | |
545 | ||
3ba8e31d EBE |
546 | struct mlx4_ib_counters { |
547 | struct list_head counters_list; | |
548 | struct mutex mutex; /* mutex for accessing counters list */ | |
549 | u32 default_counter; | |
550 | }; | |
551 | ||
3f85f2aa MB |
552 | #define MLX4_DIAG_COUNTERS_TYPES 2 |
553 | ||
554 | struct mlx4_ib_diag_counters { | |
555 | const char **name; | |
556 | u32 *offset; | |
557 | u32 num_counters; | |
558 | }; | |
559 | ||
225c7b1f RD |
560 | struct mlx4_ib_dev { |
561 | struct ib_device ib_dev; | |
562 | struct mlx4_dev *dev; | |
7ff93f8b | 563 | int num_ports; |
225c7b1f RD |
564 | void __iomem *uar_map; |
565 | ||
225c7b1f RD |
566 | struct mlx4_uar priv_uar; |
567 | u32 priv_pdn; | |
568 | MLX4_DECLARE_DOORBELL_LOCK(uar_lock); | |
569 | ||
570 | struct ib_mad_agent *send_agent[MLX4_MAX_PORTS][2]; | |
571 | struct ib_ah *sm_ah[MLX4_MAX_PORTS]; | |
572 | spinlock_t sm_lock; | |
fd10ed8e | 573 | atomic64_t sl2vl[MLX4_MAX_PORTS]; |
1ffeb2eb | 574 | struct mlx4_ib_sriov sriov; |
225c7b1f RD |
575 | |
576 | struct mutex cap_mask_mutex; | |
3b4a8cd5 | 577 | bool ib_active; |
fa417f7b | 578 | struct mlx4_ib_iboe iboe; |
3ba8e31d | 579 | struct mlx4_ib_counters counters_table[MLX4_MAX_PORTS]; |
e605b743 | 580 | int *eq_table; |
c1e7e466 JM |
581 | struct kobject *iov_parent; |
582 | struct kobject *ports_parent; | |
583 | struct kobject *dev_ports_parent[MLX4_MFUNC_MAX]; | |
584 | struct mlx4_ib_iov_port iov_ports[MLX4_MAX_PORTS]; | |
fc06573d | 585 | struct pkey_mgt pkeys; |
c1c98501 MB |
586 | unsigned long *ib_uc_qpns_bitmap; |
587 | int steer_qpn_count; | |
588 | int steer_qpn_base; | |
0a9b7d59 | 589 | int steering_support; |
9433c188 MB |
590 | struct mlx4_ib_qp *qp1_proxy[MLX4_MAX_PORTS]; |
591 | /* lock when destroying qp1_proxy and getting netdev events */ | |
592 | struct mutex qp1_proxy_lock[MLX4_MAX_PORTS]; | |
c6215745 | 593 | u8 bond_next_port; |
35f05dab YH |
594 | /* protect resources needed as part of reset flow */ |
595 | spinlock_t reset_flow_resource_lock; | |
596 | struct list_head qp_list; | |
3f85f2aa | 597 | struct mlx4_ib_diag_counters diag_counters[MLX4_DIAG_COUNTERS_TYPES]; |
225c7b1f RD |
598 | }; |
599 | ||
00f5ce99 JM |
600 | struct ib_event_work { |
601 | struct work_struct work; | |
602 | struct mlx4_ib_dev *ib_dev; | |
603 | struct mlx4_eqe ib_eqe; | |
fd10ed8e | 604 | int port; |
00f5ce99 JM |
605 | }; |
606 | ||
1ffeb2eb JM |
607 | struct mlx4_ib_qp_tunnel_init_attr { |
608 | struct ib_qp_init_attr init_attr; | |
609 | int slave; | |
610 | enum ib_qp_type proxy_qp_type; | |
611 | u8 port; | |
612 | }; | |
613 | ||
4b664c43 MB |
614 | struct mlx4_uverbs_ex_query_device { |
615 | __u32 comp_mask; | |
616 | __u32 reserved; | |
617 | }; | |
618 | ||
619 | enum query_device_resp_mask { | |
620 | QUERY_DEVICE_RESP_MASK_TIMESTAMP = 1UL << 0, | |
621 | }; | |
622 | ||
623 | struct mlx4_uverbs_ex_query_device_resp { | |
624 | __u32 comp_mask; | |
625 | __u32 response_length; | |
626 | __u64 hca_core_clock_offset; | |
627 | }; | |
628 | ||
225c7b1f RD |
629 | static inline struct mlx4_ib_dev *to_mdev(struct ib_device *ibdev) |
630 | { | |
631 | return container_of(ibdev, struct mlx4_ib_dev, ib_dev); | |
632 | } | |
633 | ||
634 | static inline struct mlx4_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) | |
635 | { | |
636 | return container_of(ibucontext, struct mlx4_ib_ucontext, ibucontext); | |
637 | } | |
638 | ||
639 | static inline struct mlx4_ib_pd *to_mpd(struct ib_pd *ibpd) | |
640 | { | |
641 | return container_of(ibpd, struct mlx4_ib_pd, ibpd); | |
642 | } | |
643 | ||
012a8ff5 SH |
644 | static inline struct mlx4_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) |
645 | { | |
646 | return container_of(ibxrcd, struct mlx4_ib_xrcd, ibxrcd); | |
647 | } | |
648 | ||
225c7b1f RD |
649 | static inline struct mlx4_ib_cq *to_mcq(struct ib_cq *ibcq) |
650 | { | |
651 | return container_of(ibcq, struct mlx4_ib_cq, ibcq); | |
652 | } | |
653 | ||
654 | static inline struct mlx4_ib_cq *to_mibcq(struct mlx4_cq *mcq) | |
655 | { | |
656 | return container_of(mcq, struct mlx4_ib_cq, mcq); | |
657 | } | |
658 | ||
659 | static inline struct mlx4_ib_mr *to_mmr(struct ib_mr *ibmr) | |
660 | { | |
661 | return container_of(ibmr, struct mlx4_ib_mr, ibmr); | |
662 | } | |
663 | ||
804d6a89 SM |
664 | static inline struct mlx4_ib_mw *to_mmw(struct ib_mw *ibmw) |
665 | { | |
666 | return container_of(ibmw, struct mlx4_ib_mw, ibmw); | |
667 | } | |
668 | ||
8ad11fb6 JM |
669 | static inline struct mlx4_ib_fmr *to_mfmr(struct ib_fmr *ibfmr) |
670 | { | |
671 | return container_of(ibfmr, struct mlx4_ib_fmr, ibfmr); | |
672 | } | |
f77c0162 HHZ |
673 | |
674 | static inline struct mlx4_ib_flow *to_mflow(struct ib_flow *ibflow) | |
675 | { | |
676 | return container_of(ibflow, struct mlx4_ib_flow, ibflow); | |
677 | } | |
678 | ||
225c7b1f RD |
679 | static inline struct mlx4_ib_qp *to_mqp(struct ib_qp *ibqp) |
680 | { | |
681 | return container_of(ibqp, struct mlx4_ib_qp, ibqp); | |
682 | } | |
683 | ||
684 | static inline struct mlx4_ib_qp *to_mibqp(struct mlx4_qp *mqp) | |
685 | { | |
686 | return container_of(mqp, struct mlx4_ib_qp, mqp); | |
687 | } | |
688 | ||
689 | static inline struct mlx4_ib_srq *to_msrq(struct ib_srq *ibsrq) | |
690 | { | |
691 | return container_of(ibsrq, struct mlx4_ib_srq, ibsrq); | |
692 | } | |
693 | ||
694 | static inline struct mlx4_ib_srq *to_mibsrq(struct mlx4_srq *msrq) | |
695 | { | |
696 | return container_of(msrq, struct mlx4_ib_srq, msrq); | |
697 | } | |
698 | ||
699 | static inline struct mlx4_ib_ah *to_mah(struct ib_ah *ibah) | |
700 | { | |
701 | return container_of(ibah, struct mlx4_ib_ah, ibah); | |
702 | } | |
703 | ||
c6215745 MS |
704 | static inline u8 mlx4_ib_bond_next_port(struct mlx4_ib_dev *dev) |
705 | { | |
706 | dev->bond_next_port = (dev->bond_next_port + 1) % dev->num_ports; | |
707 | ||
708 | return dev->bond_next_port + 1; | |
709 | } | |
710 | ||
fc06573d JM |
711 | int mlx4_ib_init_sriov(struct mlx4_ib_dev *dev); |
712 | void mlx4_ib_close_sriov(struct mlx4_ib_dev *dev); | |
713 | ||
225c7b1f | 714 | int mlx4_ib_db_map_user(struct mlx4_ib_ucontext *context, unsigned long virt, |
6296883c YP |
715 | struct mlx4_db *db); |
716 | void mlx4_ib_db_unmap_user(struct mlx4_ib_ucontext *context, struct mlx4_db *db); | |
225c7b1f RD |
717 | |
718 | struct ib_mr *mlx4_ib_get_dma_mr(struct ib_pd *pd, int acc); | |
719 | int mlx4_ib_umem_write_mtt(struct mlx4_ib_dev *dev, struct mlx4_mtt *mtt, | |
720 | struct ib_umem *umem); | |
721 | struct ib_mr *mlx4_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, | |
722 | u64 virt_addr, int access_flags, | |
723 | struct ib_udata *udata); | |
724 | int mlx4_ib_dereg_mr(struct ib_mr *mr); | |
b2a239df MB |
725 | struct ib_mw *mlx4_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, |
726 | struct ib_udata *udata); | |
804d6a89 | 727 | int mlx4_ib_dealloc_mw(struct ib_mw *mw); |
679e34d1 SG |
728 | struct ib_mr *mlx4_ib_alloc_mr(struct ib_pd *pd, |
729 | enum ib_mr_type mr_type, | |
730 | u32 max_num_sg); | |
ff2ba993 | 731 | int mlx4_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, |
9aa8b321 | 732 | unsigned int *sg_offset); |
3fdcb97f | 733 | int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); |
bbf8eed1 | 734 | int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); |
bcf4c1ea MB |
735 | struct ib_cq *mlx4_ib_create_cq(struct ib_device *ibdev, |
736 | const struct ib_cq_init_attr *attr, | |
225c7b1f RD |
737 | struct ib_ucontext *context, |
738 | struct ib_udata *udata); | |
739 | int mlx4_ib_destroy_cq(struct ib_cq *cq); | |
740 | int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); | |
741 | int mlx4_ib_arm_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags); | |
742 | void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq); | |
743 | void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq); | |
744 | ||
477864c8 MS |
745 | struct ib_ah *mlx4_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr, |
746 | struct ib_udata *udata); | |
225c7b1f RD |
747 | int mlx4_ib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr); |
748 | int mlx4_ib_destroy_ah(struct ib_ah *ah); | |
749 | ||
750 | struct ib_srq *mlx4_ib_create_srq(struct ib_pd *pd, | |
751 | struct ib_srq_init_attr *init_attr, | |
752 | struct ib_udata *udata); | |
753 | int mlx4_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, | |
754 | enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); | |
65541cb7 | 755 | int mlx4_ib_query_srq(struct ib_srq *srq, struct ib_srq_attr *srq_attr); |
225c7b1f RD |
756 | int mlx4_ib_destroy_srq(struct ib_srq *srq); |
757 | void mlx4_ib_free_srq_wqe(struct mlx4_ib_srq *srq, int wqe_index); | |
758 | int mlx4_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr, | |
759 | struct ib_recv_wr **bad_wr); | |
760 | ||
761 | struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd, | |
762 | struct ib_qp_init_attr *init_attr, | |
763 | struct ib_udata *udata); | |
764 | int mlx4_ib_destroy_qp(struct ib_qp *qp); | |
765 | int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, | |
766 | int attr_mask, struct ib_udata *udata); | |
6a775e2b JM |
767 | int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, |
768 | struct ib_qp_init_attr *qp_init_attr); | |
225c7b1f RD |
769 | int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, |
770 | struct ib_send_wr **bad_wr); | |
771 | int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, | |
772 | struct ib_recv_wr **bad_wr); | |
773 | ||
0a9a0188 | 774 | int mlx4_MAD_IFC(struct mlx4_ib_dev *dev, int mad_ifc_flags, |
a97e2d86 IW |
775 | int port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, |
776 | const void *in_mad, void *response_mad); | |
225c7b1f | 777 | int mlx4_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, |
a97e2d86 | 778 | const struct ib_wc *in_wc, const struct ib_grh *in_grh, |
4cd7c947 IW |
779 | const struct ib_mad_hdr *in, size_t in_mad_size, |
780 | struct ib_mad_hdr *out, size_t *out_mad_size, | |
781 | u16 *out_mad_pkey_index); | |
225c7b1f RD |
782 | int mlx4_ib_mad_init(struct mlx4_ib_dev *dev); |
783 | void mlx4_ib_mad_cleanup(struct mlx4_ib_dev *dev); | |
784 | ||
8ad11fb6 JM |
785 | struct ib_fmr *mlx4_ib_fmr_alloc(struct ib_pd *pd, int mr_access_flags, |
786 | struct ib_fmr_attr *fmr_attr); | |
787 | int mlx4_ib_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list, int npages, | |
788 | u64 iova); | |
789 | int mlx4_ib_unmap_fmr(struct list_head *fmr_list); | |
790 | int mlx4_ib_fmr_dealloc(struct ib_fmr *fmr); | |
0a9a0188 JM |
791 | int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port, |
792 | struct ib_port_attr *props, int netw_view); | |
793 | int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, | |
794 | u16 *pkey, int netw_view); | |
8ad11fb6 | 795 | |
a0c64a17 JM |
796 | int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index, |
797 | union ib_gid *gid, int netw_view); | |
798 | ||
a29bec12 | 799 | static inline bool mlx4_ib_ah_grh_present(struct mlx4_ib_ah *ah) |
225c7b1f | 800 | { |
fa417f7b EC |
801 | u8 port = be32_to_cpu(ah->av.ib.port_pd) >> 24 & 3; |
802 | ||
803 | if (rdma_port_get_link_layer(ah->ibah.device, port) == IB_LINK_LAYER_ETHERNET) | |
a29bec12 | 804 | return true; |
fa417f7b EC |
805 | |
806 | return !!(ah->av.ib.g_slid & 0x80); | |
225c7b1f RD |
807 | } |
808 | ||
b9c5d6a6 OD |
809 | int mlx4_ib_mcg_port_init(struct mlx4_ib_demux_ctx *ctx); |
810 | void mlx4_ib_mcg_port_cleanup(struct mlx4_ib_demux_ctx *ctx, int destroy_wq); | |
811 | void clean_vf_mcast(struct mlx4_ib_demux_ctx *ctx, int slave); | |
812 | int mlx4_ib_mcg_init(void); | |
813 | void mlx4_ib_mcg_destroy(void); | |
814 | ||
815 | int mlx4_ib_find_real_gid(struct ib_device *ibdev, u8 port, __be64 guid); | |
816 | ||
817 | int mlx4_ib_mcg_multiplex_handler(struct ib_device *ibdev, int port, int slave, | |
818 | struct ib_sa_mad *sa_mad); | |
819 | int mlx4_ib_mcg_demux_handler(struct ib_device *ibdev, int port, int slave, | |
820 | struct ib_sa_mad *mad); | |
821 | ||
fa417f7b EC |
822 | int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, |
823 | union ib_gid *gid); | |
824 | ||
00f5ce99 JM |
825 | void mlx4_ib_dispatch_event(struct mlx4_ib_dev *dev, u8 port_num, |
826 | enum ib_event_type type); | |
827 | ||
fc06573d JM |
828 | void mlx4_ib_tunnels_update_work(struct work_struct *work); |
829 | ||
b9c5d6a6 OD |
830 | int mlx4_ib_send_to_slave(struct mlx4_ib_dev *dev, int slave, u8 port, |
831 | enum ib_qp_type qpt, struct ib_wc *wc, | |
832 | struct ib_grh *grh, struct ib_mad *mad); | |
5ea8bbfc | 833 | |
b9c5d6a6 OD |
834 | int mlx4_ib_send_to_wire(struct mlx4_ib_dev *dev, int slave, u8 port, |
835 | enum ib_qp_type dest_qpt, u16 pkey_index, u32 remote_qpn, | |
5ea8bbfc | 836 | u32 qkey, struct ib_ah_attr *attr, u8 *s_mac, |
dbf727de | 837 | u16 vlan_id, struct ib_mad *mad); |
5ea8bbfc | 838 | |
b9c5d6a6 OD |
839 | __be64 mlx4_ib_get_new_demux_tid(struct mlx4_ib_demux_ctx *ctx); |
840 | ||
3cf69cc8 AV |
841 | int mlx4_ib_demux_cm_handler(struct ib_device *ibdev, int port, int *slave, |
842 | struct ib_mad *mad); | |
843 | ||
844 | int mlx4_ib_multiplex_cm_handler(struct ib_device *ibdev, int port, int slave_id, | |
845 | struct ib_mad *mad); | |
846 | ||
847 | void mlx4_ib_cm_paravirt_init(struct mlx4_ib_dev *dev); | |
848 | void mlx4_ib_cm_paravirt_clean(struct mlx4_ib_dev *dev, int slave_id); | |
849 | ||
a0c64a17 JM |
850 | /* alias guid support */ |
851 | void mlx4_ib_init_alias_guid_work(struct mlx4_ib_dev *dev, int port); | |
852 | int mlx4_ib_init_alias_guid_service(struct mlx4_ib_dev *dev); | |
853 | void mlx4_ib_destroy_alias_guid_service(struct mlx4_ib_dev *dev); | |
854 | void mlx4_ib_invalidate_all_guid_record(struct mlx4_ib_dev *dev, int port); | |
855 | ||
856 | void mlx4_ib_notify_slaves_on_guid_change(struct mlx4_ib_dev *dev, | |
857 | int block_num, | |
858 | u8 port_num, u8 *p_data); | |
859 | ||
860 | void mlx4_ib_update_cache_on_guid_change(struct mlx4_ib_dev *dev, | |
861 | int block_num, u8 port_num, | |
862 | u8 *p_data); | |
863 | ||
c1e7e466 JM |
864 | int add_sysfs_port_mcg_attr(struct mlx4_ib_dev *device, int port_num, |
865 | struct attribute *attr); | |
866 | void del_sysfs_port_mcg_attr(struct mlx4_ib_dev *device, int port_num, | |
867 | struct attribute *attr); | |
868 | ib_sa_comp_mask mlx4_ib_get_aguid_comp_mask_from_ix(int index); | |
ee59fa0d YH |
869 | void mlx4_ib_slave_alias_guid_event(struct mlx4_ib_dev *dev, int slave, |
870 | int port, int slave_init); | |
c1e7e466 JM |
871 | |
872 | int mlx4_ib_device_register_sysfs(struct mlx4_ib_dev *device) ; | |
873 | ||
874 | void mlx4_ib_device_unregister_sysfs(struct mlx4_ib_dev *device); | |
875 | ||
afa8fd1d JM |
876 | __be64 mlx4_ib_gen_node_guid(void); |
877 | ||
c1c98501 MB |
878 | int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn); |
879 | void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count); | |
880 | int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, | |
881 | int is_attach); | |
9376932d MB |
882 | int mlx4_ib_rereg_user_mr(struct ib_mr *mr, int flags, |
883 | u64 start, u64 length, u64 virt_addr, | |
884 | int mr_access_flags, struct ib_pd *pd, | |
885 | struct ib_udata *udata); | |
e26be1bf MS |
886 | int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev, |
887 | u8 port_num, int index); | |
afa8fd1d | 888 | |
fd10ed8e JM |
889 | void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev, |
890 | int port); | |
891 | ||
892 | void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port); | |
893 | ||
225c7b1f | 894 | #endif /* MLX4_IB_H */ |