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1/*
2 * Copyright (c) 2006, 2007 Cisco Systems. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
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4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34#ifndef MLX4_IB_H
35#define MLX4_IB_H
36
37#include <linux/compiler.h>
38#include <linux/list.h>
63019d93 39#include <linux/mutex.h>
b9c5d6a6 40#include <linux/idr.h>
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41
42#include <rdma/ib_verbs.h>
43#include <rdma/ib_umem.h>
b9c5d6a6 44#include <rdma/ib_mad.h>
a0c64a17 45#include <rdma/ib_sa.h>
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46
47#include <linux/mlx4/device.h>
48#include <linux/mlx4/doorbell.h>
49
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50#define MLX4_IB_DRV_NAME "mlx4_ib"
51
52#ifdef pr_fmt
53#undef pr_fmt
54#endif
55#define pr_fmt(fmt) "<" MLX4_IB_DRV_NAME "> %s: " fmt, __func__
56
57#define mlx4_ib_warn(ibdev, format, arg...) \
d66c88a8 58 dev_warn((ibdev)->dev.parent, MLX4_IB_DRV_NAME ": " format, ## arg)
b1d8eb5a 59
fc2d0044
SG
60enum {
61 MLX4_IB_SQ_MIN_WQE_SHIFT = 6,
62 MLX4_IB_MAX_HEADROOM = 2048
63};
64
65#define MLX4_IB_SQ_HEADROOM(shift) ((MLX4_IB_MAX_HEADROOM >> (shift)) + 1)
66#define MLX4_IB_SQ_MAX_SPARE (MLX4_IB_SQ_HEADROOM(MLX4_IB_SQ_MIN_WQE_SHIFT))
67
a0c64a17
JM
68/*module param to indicate if SM assigns the alias_GUID*/
69extern int mlx4_ib_sm_guid_assign;
70
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MB
71#define MLX4_IB_UC_STEER_QPN_ALIGN 1
72#define MLX4_IB_UC_MAX_NUM_QPS 256
ae184dde
YH
73
74enum hw_bar_type {
75 HW_BAR_BF,
76 HW_BAR_DB,
77 HW_BAR_CLOCK,
78 HW_BAR_COUNT
79};
80
81struct mlx4_ib_vma_private_data {
82 struct vm_area_struct *vma;
83};
84
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85struct mlx4_ib_ucontext {
86 struct ib_ucontext ibucontext;
87 struct mlx4_uar uar;
88 struct list_head db_page_list;
89 struct mutex db_page_mutex;
ae184dde 90 struct mlx4_ib_vma_private_data hw_bar_info[HW_BAR_COUNT];
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91};
92
93struct mlx4_ib_pd {
94 struct ib_pd ibpd;
95 u32 pdn;
96};
97
012a8ff5
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98struct mlx4_ib_xrcd {
99 struct ib_xrcd ibxrcd;
100 u32 xrcdn;
101 struct ib_pd *pd;
102 struct ib_cq *cq;
103};
104
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105struct mlx4_ib_cq_buf {
106 struct mlx4_buf buf;
107 struct mlx4_mtt mtt;
08ff3235 108 int entry_size;
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109};
110
bbf8eed1
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111struct mlx4_ib_cq_resize {
112 struct mlx4_ib_cq_buf buf;
113 int cqe;
114};
115
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116struct mlx4_ib_cq {
117 struct ib_cq ibcq;
118 struct mlx4_cq mcq;
119 struct mlx4_ib_cq_buf buf;
bbf8eed1 120 struct mlx4_ib_cq_resize *resize_buf;
6296883c 121 struct mlx4_db db;
225c7b1f 122 spinlock_t lock;
bbf8eed1 123 struct mutex resize_mutex;
225c7b1f 124 struct ib_umem *umem;
bbf8eed1 125 struct ib_umem *resize_umem;
4b664c43 126 int create_flags;
35f05dab
YH
127 /* List of qps that it serves.*/
128 struct list_head send_qp_list;
129 struct list_head recv_qp_list;
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130};
131
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132#define MLX4_MR_PAGES_ALIGN 0x40
133
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134struct mlx4_ib_mr {
135 struct ib_mr ibmr;
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136 __be64 *pages;
137 dma_addr_t page_map;
138 u32 npages;
139 u32 max_pages;
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140 struct mlx4_mr mmr;
141 struct ib_umem *umem;
cbc9355a 142 size_t page_map_size;
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143};
144
804d6a89
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145struct mlx4_ib_mw {
146 struct ib_mw ibmw;
147 struct mlx4_mw mmw;
148};
149
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JM
150struct mlx4_ib_fmr {
151 struct ib_fmr ibfmr;
152 struct mlx4_fmr mfmr;
153};
154
146d6e19
MS
155#define MAX_REGS_PER_FLOW 2
156
157struct mlx4_flow_reg_id {
158 u64 id;
159 u64 mirror;
160};
161
f77c0162
HHZ
162struct mlx4_ib_flow {
163 struct ib_flow ibflow;
164 /* translating DMFS verbs sniffer rule to FW API requires two reg IDs */
146d6e19 165 struct mlx4_flow_reg_id reg_id[MAX_REGS_PER_FLOW];
f77c0162
HHZ
166};
167
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168struct mlx4_ib_wq {
169 u64 *wrid;
170 spinlock_t lock;
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171 int wqe_cnt;
172 int max_post;
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173 int max_gs;
174 int offset;
175 int wqe_shift;
176 unsigned head;
177 unsigned tail;
178};
179
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180enum {
181 MLX4_IB_QP_CREATE_ROCE_V2_GSI = IB_QP_CREATE_RESERVED_START
182};
183
b832be1e 184enum mlx4_ib_qp_flags {
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185 MLX4_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO,
186 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK,
c1c98501 187 MLX4_IB_QP_NETIF = IB_QP_CREATE_NETIF_QP,
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MS
188
189 /* Mellanox specific flags start from IB_QP_CREATE_RESERVED_START */
190 MLX4_IB_ROCE_V2_GSI_QP = MLX4_IB_QP_CREATE_ROCE_V2_GSI,
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191 MLX4_IB_SRIOV_TUNNEL_QP = 1 << 30,
192 MLX4_IB_SRIOV_SQP = 1 << 31,
b832be1e
EC
193};
194
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EC
195struct mlx4_ib_gid_entry {
196 struct list_head list;
197 union ib_gid gid;
198 int added;
199 u8 port;
200};
201
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202enum mlx4_ib_qp_type {
203 /*
204 * IB_QPT_SMI and IB_QPT_GSI have to be the first two entries
205 * here (and in that order) since the MAD layer uses them as
206 * indices into a 2-entry table.
207 */
208 MLX4_IB_QPT_SMI = IB_QPT_SMI,
209 MLX4_IB_QPT_GSI = IB_QPT_GSI,
210
211 MLX4_IB_QPT_RC = IB_QPT_RC,
212 MLX4_IB_QPT_UC = IB_QPT_UC,
213 MLX4_IB_QPT_UD = IB_QPT_UD,
214 MLX4_IB_QPT_RAW_IPV6 = IB_QPT_RAW_IPV6,
215 MLX4_IB_QPT_RAW_ETHERTYPE = IB_QPT_RAW_ETHERTYPE,
216 MLX4_IB_QPT_RAW_PACKET = IB_QPT_RAW_PACKET,
217 MLX4_IB_QPT_XRC_INI = IB_QPT_XRC_INI,
218 MLX4_IB_QPT_XRC_TGT = IB_QPT_XRC_TGT,
219
220 MLX4_IB_QPT_PROXY_SMI_OWNER = 1 << 16,
221 MLX4_IB_QPT_PROXY_SMI = 1 << 17,
222 MLX4_IB_QPT_PROXY_GSI = 1 << 18,
223 MLX4_IB_QPT_TUN_SMI_OWNER = 1 << 19,
224 MLX4_IB_QPT_TUN_SMI = 1 << 20,
225 MLX4_IB_QPT_TUN_GSI = 1 << 21,
226};
227
228#define MLX4_IB_QPT_ANY_SRIOV (MLX4_IB_QPT_PROXY_SMI_OWNER | \
229 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER | \
230 MLX4_IB_QPT_TUN_SMI | MLX4_IB_QPT_TUN_GSI)
231
0a9a0188
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232enum mlx4_ib_mad_ifc_flags {
233 MLX4_MAD_IFC_IGNORE_MKEY = 1,
234 MLX4_MAD_IFC_IGNORE_BKEY = 2,
235 MLX4_MAD_IFC_IGNORE_KEYS = (MLX4_MAD_IFC_IGNORE_MKEY |
236 MLX4_MAD_IFC_IGNORE_BKEY),
237 MLX4_MAD_IFC_NET_VIEW = 4,
238};
239
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240enum {
241 MLX4_NUM_TUNNEL_BUFS = 256,
242};
243
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244struct mlx4_ib_tunnel_header {
245 struct mlx4_av av;
246 __be32 remote_qpn;
247 __be32 qkey;
248 __be16 vlan;
249 u8 mac[6];
250 __be16 pkey_index;
251 u8 reserved[6];
252};
253
254struct mlx4_ib_buf {
255 void *addr;
256 dma_addr_t map;
257};
258
259struct mlx4_rcv_tunnel_hdr {
260 __be32 flags_src_qp; /* flags[6:5] is defined for VLANs:
261 * 0x0 - no vlan was in the packet
262 * 0x01 - C-VLAN was in the packet */
263 u8 g_ml_path; /* gid bit stands for ipv6/4 header in RoCE */
264 u8 reserved;
265 __be16 pkey_index;
266 __be16 sl_vid;
267 __be16 slid_mac_47_32;
268 __be32 mac_31_0;
269};
270
271struct mlx4_ib_proxy_sqp_hdr {
272 struct ib_grh grh;
273 struct mlx4_rcv_tunnel_hdr tun;
274} __packed;
275
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JM
276struct mlx4_roce_smac_vlan_info {
277 u64 smac;
278 int smac_index;
279 int smac_port;
280 u64 candidate_smac;
281 int candidate_smac_index;
282 int candidate_smac_port;
283 u16 vid;
284 int vlan_index;
285 int vlan_port;
286 u16 candidate_vid;
287 int candidate_vlan_index;
288 int candidate_vlan_port;
289 int update_vid;
290};
291
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292struct mlx4_ib_qp {
293 struct ib_qp ibqp;
294 struct mlx4_qp mqp;
295 struct mlx4_buf buf;
296
6296883c 297 struct mlx4_db db;
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298 struct mlx4_ib_wq rq;
299
300 u32 doorbell_qpn;
301 __be32 sq_signal_bits;
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JM
302 unsigned sq_next_wqe;
303 int sq_max_wqes_per_wr;
0e6e7416 304 int sq_spare_wqes;
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305 struct mlx4_ib_wq sq;
306
1ffeb2eb 307 enum mlx4_ib_qp_type mlx4_ib_qp_type;
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308 struct ib_umem *umem;
309 struct mlx4_mtt mtt;
310 int buf_size;
311 struct mutex mutex;
0a1405da 312 u16 xrcdn;
b832be1e 313 u32 flags;
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314 u8 port;
315 u8 alt_port;
316 u8 atomic_rd_en;
317 u8 resp_depth;
0e6e7416 318 u8 sq_no_prefetch;
225c7b1f 319 u8 state;
fa417f7b
EC
320 int mlx_type;
321 struct list_head gid_list;
0ff1fb65 322 struct list_head steering_rules;
1ffeb2eb 323 struct mlx4_ib_buf *sqp_proxy_rcv;
2f5bb473
JM
324 struct mlx4_roce_smac_vlan_info pri;
325 struct mlx4_roce_smac_vlan_info alt;
c1c98501 326 u64 reg_id;
35f05dab
YH
327 struct list_head qps_list;
328 struct list_head cq_recv_list;
329 struct list_head cq_send_list;
7b59f0f9 330 struct counter_index *counter_index;
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RD
331};
332
333struct mlx4_ib_srq {
334 struct ib_srq ibsrq;
335 struct mlx4_srq msrq;
336 struct mlx4_buf buf;
6296883c 337 struct mlx4_db db;
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RD
338 u64 *wrid;
339 spinlock_t lock;
340 int head;
341 int tail;
342 u16 wqe_ctr;
343 struct ib_umem *umem;
344 struct mlx4_mtt mtt;
345 struct mutex mutex;
346};
347
348struct mlx4_ib_ah {
349 struct ib_ah ibah;
fa417f7b
EC
350 union mlx4_ext_av av;
351};
352
a0c64a17
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353/****************************************/
354/* alias guid support */
355/****************************************/
356#define NUM_PORT_ALIAS_GUID 2
357#define NUM_ALIAS_GUID_IN_REC 8
358#define NUM_ALIAS_GUID_REC_IN_PORT 16
359#define GUID_REC_SIZE 8
360#define NUM_ALIAS_GUID_PER_PORT 128
361#define MLX4_NOT_SET_GUID (0x00LL)
362#define MLX4_GUID_FOR_DELETE_VAL (~(0x00LL))
363
364enum mlx4_guid_alias_rec_status {
365 MLX4_GUID_INFO_STATUS_IDLE,
366 MLX4_GUID_INFO_STATUS_SET,
a0c64a17
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367};
368
f5479601 369#define GUID_STATE_NEED_PORT_INIT 0x01
a0c64a17
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370
371enum mlx4_guid_alias_rec_method {
372 MLX4_GUID_INFO_RECORD_SET = IB_MGMT_METHOD_SET,
373 MLX4_GUID_INFO_RECORD_DELETE = IB_SA_METHOD_DELETE,
374};
375
376struct mlx4_sriov_alias_guid_info_rec_det {
377 u8 all_recs[GUID_REC_SIZE * NUM_ALIAS_GUID_IN_REC];
378 ib_sa_comp_mask guid_indexes; /*indicates what from the 8 records are valid*/
379 enum mlx4_guid_alias_rec_status status; /*indicates the administraively status of the record.*/
99ee4df6
YH
380 unsigned int guids_retry_schedule[NUM_ALIAS_GUID_IN_REC];
381 u64 time_to_run;
a0c64a17
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382};
383
384struct mlx4_sriov_alias_guid_port_rec_det {
385 struct mlx4_sriov_alias_guid_info_rec_det all_rec_per_port[NUM_ALIAS_GUID_REC_IN_PORT];
386 struct workqueue_struct *wq;
387 struct delayed_work alias_guid_work;
388 u8 port;
f5479601 389 u32 state_flags;
a0c64a17
JM
390 struct mlx4_sriov_alias_guid *parent;
391 struct list_head cb_list;
392};
393
394struct mlx4_sriov_alias_guid {
395 struct mlx4_sriov_alias_guid_port_rec_det ports_guid[MLX4_MAX_PORTS];
396 spinlock_t ag_work_lock;
397 struct ib_sa_client *sa_client;
398};
399
fc06573d
JM
400struct mlx4_ib_demux_work {
401 struct work_struct work;
402 struct mlx4_ib_dev *dev;
403 int slave;
404 int do_init;
405 u8 port;
406
407};
408
1ffeb2eb
JM
409struct mlx4_ib_tun_tx_buf {
410 struct mlx4_ib_buf buf;
411 struct ib_ah *ah;
412};
413
414struct mlx4_ib_demux_pv_qp {
415 struct ib_qp *qp;
416 enum ib_qp_type proxy_qpt;
417 struct mlx4_ib_buf *ring;
418 struct mlx4_ib_tun_tx_buf *tx_ring;
419 spinlock_t tx_lock;
420 unsigned tx_ix_head;
421 unsigned tx_ix_tail;
422};
423
fc06573d
JM
424enum mlx4_ib_demux_pv_state {
425 DEMUX_PV_STATE_DOWN,
426 DEMUX_PV_STATE_STARTING,
427 DEMUX_PV_STATE_ACTIVE,
428 DEMUX_PV_STATE_DOWNING,
429};
430
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431struct mlx4_ib_demux_pv_ctx {
432 int port;
433 int slave;
fc06573d 434 enum mlx4_ib_demux_pv_state state;
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435 int has_smi;
436 struct ib_device *ib_dev;
437 struct ib_cq *cq;
438 struct ib_pd *pd;
1ffeb2eb
JM
439 struct work_struct work;
440 struct workqueue_struct *wq;
441 struct mlx4_ib_demux_pv_qp qp[2];
442};
443
444struct mlx4_ib_demux_ctx {
445 struct ib_device *ib_dev;
446 int port;
447 struct workqueue_struct *wq;
448 struct workqueue_struct *ud_wq;
449 spinlock_t ud_lock;
8ec07bf8 450 atomic64_t subnet_prefix;
1ffeb2eb
JM
451 __be64 guid_cache[128];
452 struct mlx4_ib_dev *dev;
b9c5d6a6
OD
453 /* the following lock protects both mcg_table and mcg_mgid0_list */
454 struct mutex mcg_table_lock;
455 struct rb_root mcg_table;
456 struct list_head mcg_mgid0_list;
457 struct workqueue_struct *mcg_wq;
1ffeb2eb 458 struct mlx4_ib_demux_pv_ctx **tun;
b9c5d6a6
OD
459 atomic_t tid;
460 int flushing; /* flushing the work queue */
1ffeb2eb
JM
461};
462
463struct mlx4_ib_sriov {
464 struct mlx4_ib_demux_ctx demux[MLX4_MAX_PORTS];
465 struct mlx4_ib_demux_pv_ctx *sqps[MLX4_MAX_PORTS];
466 /* when using this spinlock you should use "irq" because
467 * it may be called from interrupt context.*/
468 spinlock_t going_down_lock;
469 int is_going_down;
3cf69cc8 470
a0c64a17
JM
471 struct mlx4_sriov_alias_guid alias_guid;
472
3cf69cc8
AV
473 /* CM paravirtualization fields */
474 struct list_head cm_list;
475 spinlock_t id_map_lock;
476 struct rb_root sl_id_map;
477 struct idr pv_id_table;
1ffeb2eb
JM
478};
479
e26be1bf
MS
480struct gid_cache_context {
481 int real_index;
482 int refcount;
483};
484
485struct gid_entry {
486 union ib_gid gid;
b699a859 487 enum ib_gid_type gid_type;
e26be1bf
MS
488 struct gid_cache_context *ctx;
489};
490
491struct mlx4_port_gid_table {
492 struct gid_entry gids[MLX4_MAX_PORT_GIDS];
493};
494
fa417f7b
EC
495struct mlx4_ib_iboe {
496 spinlock_t lock;
497 struct net_device *netdevs[MLX4_MAX_PORTS];
3e0629cb 498 atomic64_t mac[MLX4_MAX_PORTS];
fa417f7b 499 struct notifier_block nb;
e26be1bf 500 struct mlx4_port_gid_table gids[MLX4_MAX_PORTS];
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501};
502
fc06573d
JM
503struct pkey_mgt {
504 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
505 u16 phys_pkey_cache[MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
506 struct list_head pkey_port_list[MLX4_MFUNC_MAX];
507 struct kobject *device_parent[MLX4_MFUNC_MAX];
508};
509
c1e7e466
JM
510struct mlx4_ib_iov_sysfs_attr {
511 void *ctx;
512 struct kobject *kobj;
513 unsigned long data;
514 u32 entry_num;
515 char name[15];
516 struct device_attribute dentry;
517 struct device *dev;
518};
519
520struct mlx4_ib_iov_sysfs_attr_ar {
521 struct mlx4_ib_iov_sysfs_attr dentries[3 * NUM_ALIAS_GUID_PER_PORT + 1];
522};
523
524struct mlx4_ib_iov_port {
525 char name[100];
526 u8 num;
527 struct mlx4_ib_dev *dev;
528 struct list_head list;
529 struct mlx4_ib_iov_sysfs_attr_ar *dentr_ar;
530 struct ib_port_attr attr;
531 struct kobject *cur_port;
532 struct kobject *admin_alias_parent;
533 struct kobject *gids_parent;
534 struct kobject *pkeys_parent;
535 struct kobject *mcgs_parent;
536 struct mlx4_ib_iov_sysfs_attr mcg_dentry;
537};
538
c3abb51b 539struct counter_index {
3ba8e31d 540 struct list_head list;
c3abb51b
EBE
541 u32 index;
542 u8 allocated;
543};
544
3ba8e31d
EBE
545struct mlx4_ib_counters {
546 struct list_head counters_list;
547 struct mutex mutex; /* mutex for accessing counters list */
548 u32 default_counter;
549};
550
3f85f2aa
MB
551#define MLX4_DIAG_COUNTERS_TYPES 2
552
553struct mlx4_ib_diag_counters {
554 const char **name;
555 u32 *offset;
556 u32 num_counters;
557};
558
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559struct mlx4_ib_dev {
560 struct ib_device ib_dev;
561 struct mlx4_dev *dev;
7ff93f8b 562 int num_ports;
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RD
563 void __iomem *uar_map;
564
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565 struct mlx4_uar priv_uar;
566 u32 priv_pdn;
567 MLX4_DECLARE_DOORBELL_LOCK(uar_lock);
568
569 struct ib_mad_agent *send_agent[MLX4_MAX_PORTS][2];
570 struct ib_ah *sm_ah[MLX4_MAX_PORTS];
571 spinlock_t sm_lock;
fd10ed8e 572 atomic64_t sl2vl[MLX4_MAX_PORTS];
1ffeb2eb 573 struct mlx4_ib_sriov sriov;
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RD
574
575 struct mutex cap_mask_mutex;
3b4a8cd5 576 bool ib_active;
fa417f7b 577 struct mlx4_ib_iboe iboe;
3ba8e31d 578 struct mlx4_ib_counters counters_table[MLX4_MAX_PORTS];
e605b743 579 int *eq_table;
c1e7e466
JM
580 struct kobject *iov_parent;
581 struct kobject *ports_parent;
582 struct kobject *dev_ports_parent[MLX4_MFUNC_MAX];
583 struct mlx4_ib_iov_port iov_ports[MLX4_MAX_PORTS];
fc06573d 584 struct pkey_mgt pkeys;
c1c98501
MB
585 unsigned long *ib_uc_qpns_bitmap;
586 int steer_qpn_count;
587 int steer_qpn_base;
0a9b7d59 588 int steering_support;
9433c188
MB
589 struct mlx4_ib_qp *qp1_proxy[MLX4_MAX_PORTS];
590 /* lock when destroying qp1_proxy and getting netdev events */
591 struct mutex qp1_proxy_lock[MLX4_MAX_PORTS];
c6215745 592 u8 bond_next_port;
35f05dab
YH
593 /* protect resources needed as part of reset flow */
594 spinlock_t reset_flow_resource_lock;
595 struct list_head qp_list;
3f85f2aa 596 struct mlx4_ib_diag_counters diag_counters[MLX4_DIAG_COUNTERS_TYPES];
225c7b1f
RD
597};
598
00f5ce99
JM
599struct ib_event_work {
600 struct work_struct work;
601 struct mlx4_ib_dev *ib_dev;
602 struct mlx4_eqe ib_eqe;
fd10ed8e 603 int port;
00f5ce99
JM
604};
605
1ffeb2eb
JM
606struct mlx4_ib_qp_tunnel_init_attr {
607 struct ib_qp_init_attr init_attr;
608 int slave;
609 enum ib_qp_type proxy_qp_type;
610 u8 port;
611};
612
4b664c43
MB
613struct mlx4_uverbs_ex_query_device {
614 __u32 comp_mask;
615 __u32 reserved;
616};
617
618enum query_device_resp_mask {
619 QUERY_DEVICE_RESP_MASK_TIMESTAMP = 1UL << 0,
620};
621
622struct mlx4_uverbs_ex_query_device_resp {
623 __u32 comp_mask;
624 __u32 response_length;
625 __u64 hca_core_clock_offset;
626};
627
225c7b1f
RD
628static inline struct mlx4_ib_dev *to_mdev(struct ib_device *ibdev)
629{
630 return container_of(ibdev, struct mlx4_ib_dev, ib_dev);
631}
632
633static inline struct mlx4_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
634{
635 return container_of(ibucontext, struct mlx4_ib_ucontext, ibucontext);
636}
637
638static inline struct mlx4_ib_pd *to_mpd(struct ib_pd *ibpd)
639{
640 return container_of(ibpd, struct mlx4_ib_pd, ibpd);
641}
642
012a8ff5
SH
643static inline struct mlx4_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd)
644{
645 return container_of(ibxrcd, struct mlx4_ib_xrcd, ibxrcd);
646}
647
225c7b1f
RD
648static inline struct mlx4_ib_cq *to_mcq(struct ib_cq *ibcq)
649{
650 return container_of(ibcq, struct mlx4_ib_cq, ibcq);
651}
652
653static inline struct mlx4_ib_cq *to_mibcq(struct mlx4_cq *mcq)
654{
655 return container_of(mcq, struct mlx4_ib_cq, mcq);
656}
657
658static inline struct mlx4_ib_mr *to_mmr(struct ib_mr *ibmr)
659{
660 return container_of(ibmr, struct mlx4_ib_mr, ibmr);
661}
662
804d6a89
SM
663static inline struct mlx4_ib_mw *to_mmw(struct ib_mw *ibmw)
664{
665 return container_of(ibmw, struct mlx4_ib_mw, ibmw);
666}
667
8ad11fb6
JM
668static inline struct mlx4_ib_fmr *to_mfmr(struct ib_fmr *ibfmr)
669{
670 return container_of(ibfmr, struct mlx4_ib_fmr, ibfmr);
671}
f77c0162
HHZ
672
673static inline struct mlx4_ib_flow *to_mflow(struct ib_flow *ibflow)
674{
675 return container_of(ibflow, struct mlx4_ib_flow, ibflow);
676}
677
225c7b1f
RD
678static inline struct mlx4_ib_qp *to_mqp(struct ib_qp *ibqp)
679{
680 return container_of(ibqp, struct mlx4_ib_qp, ibqp);
681}
682
683static inline struct mlx4_ib_qp *to_mibqp(struct mlx4_qp *mqp)
684{
685 return container_of(mqp, struct mlx4_ib_qp, mqp);
686}
687
688static inline struct mlx4_ib_srq *to_msrq(struct ib_srq *ibsrq)
689{
690 return container_of(ibsrq, struct mlx4_ib_srq, ibsrq);
691}
692
693static inline struct mlx4_ib_srq *to_mibsrq(struct mlx4_srq *msrq)
694{
695 return container_of(msrq, struct mlx4_ib_srq, msrq);
696}
697
698static inline struct mlx4_ib_ah *to_mah(struct ib_ah *ibah)
699{
700 return container_of(ibah, struct mlx4_ib_ah, ibah);
701}
702
c6215745
MS
703static inline u8 mlx4_ib_bond_next_port(struct mlx4_ib_dev *dev)
704{
705 dev->bond_next_port = (dev->bond_next_port + 1) % dev->num_ports;
706
707 return dev->bond_next_port + 1;
708}
709
fc06573d
JM
710int mlx4_ib_init_sriov(struct mlx4_ib_dev *dev);
711void mlx4_ib_close_sriov(struct mlx4_ib_dev *dev);
712
225c7b1f 713int mlx4_ib_db_map_user(struct mlx4_ib_ucontext *context, unsigned long virt,
6296883c
YP
714 struct mlx4_db *db);
715void mlx4_ib_db_unmap_user(struct mlx4_ib_ucontext *context, struct mlx4_db *db);
225c7b1f
RD
716
717struct ib_mr *mlx4_ib_get_dma_mr(struct ib_pd *pd, int acc);
718int mlx4_ib_umem_write_mtt(struct mlx4_ib_dev *dev, struct mlx4_mtt *mtt,
719 struct ib_umem *umem);
720struct ib_mr *mlx4_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
721 u64 virt_addr, int access_flags,
722 struct ib_udata *udata);
723int mlx4_ib_dereg_mr(struct ib_mr *mr);
b2a239df
MB
724struct ib_mw *mlx4_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
725 struct ib_udata *udata);
804d6a89 726int mlx4_ib_dealloc_mw(struct ib_mw *mw);
679e34d1
SG
727struct ib_mr *mlx4_ib_alloc_mr(struct ib_pd *pd,
728 enum ib_mr_type mr_type,
729 u32 max_num_sg);
ff2ba993 730int mlx4_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
9aa8b321 731 unsigned int *sg_offset);
3fdcb97f 732int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
bbf8eed1 733int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata);
bcf4c1ea
MB
734struct ib_cq *mlx4_ib_create_cq(struct ib_device *ibdev,
735 const struct ib_cq_init_attr *attr,
225c7b1f
RD
736 struct ib_ucontext *context,
737 struct ib_udata *udata);
738int mlx4_ib_destroy_cq(struct ib_cq *cq);
739int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
740int mlx4_ib_arm_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags);
741void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq);
742void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq);
743
90898850 744struct ib_ah *mlx4_ib_create_ah(struct ib_pd *pd, struct rdma_ah_attr *ah_attr,
477864c8 745 struct ib_udata *udata);
90898850 746int mlx4_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
225c7b1f
RD
747int mlx4_ib_destroy_ah(struct ib_ah *ah);
748
749struct ib_srq *mlx4_ib_create_srq(struct ib_pd *pd,
750 struct ib_srq_init_attr *init_attr,
751 struct ib_udata *udata);
752int mlx4_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
753 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
65541cb7 754int mlx4_ib_query_srq(struct ib_srq *srq, struct ib_srq_attr *srq_attr);
225c7b1f
RD
755int mlx4_ib_destroy_srq(struct ib_srq *srq);
756void mlx4_ib_free_srq_wqe(struct mlx4_ib_srq *srq, int wqe_index);
757int mlx4_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
758 struct ib_recv_wr **bad_wr);
759
760struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
761 struct ib_qp_init_attr *init_attr,
762 struct ib_udata *udata);
763int mlx4_ib_destroy_qp(struct ib_qp *qp);
764int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
765 int attr_mask, struct ib_udata *udata);
6a775e2b
JM
766int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
767 struct ib_qp_init_attr *qp_init_attr);
225c7b1f
RD
768int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
769 struct ib_send_wr **bad_wr);
770int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
771 struct ib_recv_wr **bad_wr);
772
0a9a0188 773int mlx4_MAD_IFC(struct mlx4_ib_dev *dev, int mad_ifc_flags,
a97e2d86
IW
774 int port, const struct ib_wc *in_wc, const struct ib_grh *in_grh,
775 const void *in_mad, void *response_mad);
225c7b1f 776int mlx4_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
a97e2d86 777 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
4cd7c947
IW
778 const struct ib_mad_hdr *in, size_t in_mad_size,
779 struct ib_mad_hdr *out, size_t *out_mad_size,
780 u16 *out_mad_pkey_index);
225c7b1f
RD
781int mlx4_ib_mad_init(struct mlx4_ib_dev *dev);
782void mlx4_ib_mad_cleanup(struct mlx4_ib_dev *dev);
783
8ad11fb6
JM
784struct ib_fmr *mlx4_ib_fmr_alloc(struct ib_pd *pd, int mr_access_flags,
785 struct ib_fmr_attr *fmr_attr);
786int mlx4_ib_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list, int npages,
787 u64 iova);
788int mlx4_ib_unmap_fmr(struct list_head *fmr_list);
789int mlx4_ib_fmr_dealloc(struct ib_fmr *fmr);
0a9a0188
JM
790int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
791 struct ib_port_attr *props, int netw_view);
792int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
793 u16 *pkey, int netw_view);
8ad11fb6 794
a0c64a17
JM
795int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
796 union ib_gid *gid, int netw_view);
797
a29bec12 798static inline bool mlx4_ib_ah_grh_present(struct mlx4_ib_ah *ah)
225c7b1f 799{
fa417f7b
EC
800 u8 port = be32_to_cpu(ah->av.ib.port_pd) >> 24 & 3;
801
802 if (rdma_port_get_link_layer(ah->ibah.device, port) == IB_LINK_LAYER_ETHERNET)
a29bec12 803 return true;
fa417f7b
EC
804
805 return !!(ah->av.ib.g_slid & 0x80);
225c7b1f
RD
806}
807
b9c5d6a6
OD
808int mlx4_ib_mcg_port_init(struct mlx4_ib_demux_ctx *ctx);
809void mlx4_ib_mcg_port_cleanup(struct mlx4_ib_demux_ctx *ctx, int destroy_wq);
810void clean_vf_mcast(struct mlx4_ib_demux_ctx *ctx, int slave);
811int mlx4_ib_mcg_init(void);
812void mlx4_ib_mcg_destroy(void);
813
814int mlx4_ib_find_real_gid(struct ib_device *ibdev, u8 port, __be64 guid);
815
816int mlx4_ib_mcg_multiplex_handler(struct ib_device *ibdev, int port, int slave,
817 struct ib_sa_mad *sa_mad);
818int mlx4_ib_mcg_demux_handler(struct ib_device *ibdev, int port, int slave,
819 struct ib_sa_mad *mad);
820
fa417f7b
EC
821int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
822 union ib_gid *gid);
823
00f5ce99
JM
824void mlx4_ib_dispatch_event(struct mlx4_ib_dev *dev, u8 port_num,
825 enum ib_event_type type);
826
fc06573d
JM
827void mlx4_ib_tunnels_update_work(struct work_struct *work);
828
b9c5d6a6
OD
829int mlx4_ib_send_to_slave(struct mlx4_ib_dev *dev, int slave, u8 port,
830 enum ib_qp_type qpt, struct ib_wc *wc,
831 struct ib_grh *grh, struct ib_mad *mad);
5ea8bbfc 832
b9c5d6a6
OD
833int mlx4_ib_send_to_wire(struct mlx4_ib_dev *dev, int slave, u8 port,
834 enum ib_qp_type dest_qpt, u16 pkey_index, u32 remote_qpn,
90898850 835 u32 qkey, struct rdma_ah_attr *attr, u8 *s_mac,
dbf727de 836 u16 vlan_id, struct ib_mad *mad);
5ea8bbfc 837
b9c5d6a6
OD
838__be64 mlx4_ib_get_new_demux_tid(struct mlx4_ib_demux_ctx *ctx);
839
3cf69cc8
AV
840int mlx4_ib_demux_cm_handler(struct ib_device *ibdev, int port, int *slave,
841 struct ib_mad *mad);
842
843int mlx4_ib_multiplex_cm_handler(struct ib_device *ibdev, int port, int slave_id,
844 struct ib_mad *mad);
845
846void mlx4_ib_cm_paravirt_init(struct mlx4_ib_dev *dev);
847void mlx4_ib_cm_paravirt_clean(struct mlx4_ib_dev *dev, int slave_id);
848
a0c64a17
JM
849/* alias guid support */
850void mlx4_ib_init_alias_guid_work(struct mlx4_ib_dev *dev, int port);
851int mlx4_ib_init_alias_guid_service(struct mlx4_ib_dev *dev);
852void mlx4_ib_destroy_alias_guid_service(struct mlx4_ib_dev *dev);
853void mlx4_ib_invalidate_all_guid_record(struct mlx4_ib_dev *dev, int port);
854
855void mlx4_ib_notify_slaves_on_guid_change(struct mlx4_ib_dev *dev,
856 int block_num,
857 u8 port_num, u8 *p_data);
858
859void mlx4_ib_update_cache_on_guid_change(struct mlx4_ib_dev *dev,
860 int block_num, u8 port_num,
861 u8 *p_data);
862
c1e7e466
JM
863int add_sysfs_port_mcg_attr(struct mlx4_ib_dev *device, int port_num,
864 struct attribute *attr);
865void del_sysfs_port_mcg_attr(struct mlx4_ib_dev *device, int port_num,
866 struct attribute *attr);
867ib_sa_comp_mask mlx4_ib_get_aguid_comp_mask_from_ix(int index);
ee59fa0d
YH
868void mlx4_ib_slave_alias_guid_event(struct mlx4_ib_dev *dev, int slave,
869 int port, int slave_init);
c1e7e466
JM
870
871int mlx4_ib_device_register_sysfs(struct mlx4_ib_dev *device) ;
872
873void mlx4_ib_device_unregister_sysfs(struct mlx4_ib_dev *device);
874
afa8fd1d
JM
875__be64 mlx4_ib_gen_node_guid(void);
876
c1c98501
MB
877int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn);
878void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count);
879int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
880 int is_attach);
9376932d
MB
881int mlx4_ib_rereg_user_mr(struct ib_mr *mr, int flags,
882 u64 start, u64 length, u64 virt_addr,
883 int mr_access_flags, struct ib_pd *pd,
884 struct ib_udata *udata);
e26be1bf
MS
885int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev,
886 u8 port_num, int index);
afa8fd1d 887
fd10ed8e
JM
888void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev,
889 int port);
890
891void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port);
892
225c7b1f 893#endif /* MLX4_IB_H */