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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. | |
51a379d0 | 3 | * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
4 | * |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the | |
9 | * OpenIB.org BSD license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or | |
12 | * without modification, are permitted provided that the following | |
13 | * conditions are met: | |
14 | * | |
15 | * - Redistributions of source code must retain the above | |
16 | * copyright notice, this list of conditions and the following | |
17 | * disclaimer. | |
18 | * | |
19 | * - Redistributions in binary form must reproduce the above | |
20 | * copyright notice, this list of conditions and the following | |
21 | * disclaimer in the documentation and/or other materials | |
22 | * provided with the distribution. | |
23 | * | |
24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
31 | * SOFTWARE. | |
32 | */ | |
33 | ||
5a0e3ad6 | 34 | #include <linux/slab.h> |
b2a239df | 35 | #include <rdma/ib_user_verbs.h> |
5a0e3ad6 | 36 | |
225c7b1f RD |
37 | #include "mlx4_ib.h" |
38 | ||
39 | static u32 convert_access(int acc) | |
40 | { | |
41 | return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX4_PERM_ATOMIC : 0) | | |
42 | (acc & IB_ACCESS_REMOTE_WRITE ? MLX4_PERM_REMOTE_WRITE : 0) | | |
43 | (acc & IB_ACCESS_REMOTE_READ ? MLX4_PERM_REMOTE_READ : 0) | | |
44 | (acc & IB_ACCESS_LOCAL_WRITE ? MLX4_PERM_LOCAL_WRITE : 0) | | |
804d6a89 | 45 | (acc & IB_ACCESS_MW_BIND ? MLX4_PERM_BIND_MW : 0) | |
225c7b1f RD |
46 | MLX4_PERM_LOCAL_READ; |
47 | } | |
48 | ||
804d6a89 SM |
49 | static enum mlx4_mw_type to_mlx4_type(enum ib_mw_type type) |
50 | { | |
51 | switch (type) { | |
52 | case IB_MW_TYPE_1: return MLX4_MW_TYPE_1; | |
53 | case IB_MW_TYPE_2: return MLX4_MW_TYPE_2; | |
54 | default: return -1; | |
55 | } | |
56 | } | |
57 | ||
225c7b1f RD |
58 | struct ib_mr *mlx4_ib_get_dma_mr(struct ib_pd *pd, int acc) |
59 | { | |
60 | struct mlx4_ib_mr *mr; | |
61 | int err; | |
62 | ||
1b2cd0fc | 63 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); |
225c7b1f RD |
64 | if (!mr) |
65 | return ERR_PTR(-ENOMEM); | |
66 | ||
67 | err = mlx4_mr_alloc(to_mdev(pd->device)->dev, to_mpd(pd)->pdn, 0, | |
68 | ~0ull, convert_access(acc), 0, 0, &mr->mmr); | |
69 | if (err) | |
70 | goto err_free; | |
71 | ||
72 | err = mlx4_mr_enable(to_mdev(pd->device)->dev, &mr->mmr); | |
73 | if (err) | |
74 | goto err_mr; | |
75 | ||
76 | mr->ibmr.rkey = mr->ibmr.lkey = mr->mmr.key; | |
77 | mr->umem = NULL; | |
78 | ||
79 | return &mr->ibmr; | |
80 | ||
81 | err_mr: | |
61083720 | 82 | (void) mlx4_mr_free(to_mdev(pd->device)->dev, &mr->mmr); |
225c7b1f RD |
83 | |
84 | err_free: | |
85 | kfree(mr); | |
86 | ||
87 | return ERR_PTR(err); | |
88 | } | |
89 | ||
9901abf5 GL |
90 | enum { |
91 | MLX4_MAX_MTT_SHIFT = 31 | |
92 | }; | |
93 | ||
94 | static int mlx4_ib_umem_write_mtt_block(struct mlx4_ib_dev *dev, | |
95 | struct mlx4_mtt *mtt, | |
96 | u64 mtt_size, u64 mtt_shift, u64 len, | |
97 | u64 cur_start_addr, u64 *pages, | |
98 | int *start_index, int *npages) | |
99 | { | |
100 | u64 cur_end_addr = cur_start_addr + len; | |
101 | u64 cur_end_addr_aligned = 0; | |
102 | u64 mtt_entries; | |
103 | int err = 0; | |
104 | int k; | |
105 | ||
106 | len += (cur_start_addr & (mtt_size - 1ULL)); | |
107 | cur_end_addr_aligned = round_up(cur_end_addr, mtt_size); | |
108 | len += (cur_end_addr_aligned - cur_end_addr); | |
109 | if (len & (mtt_size - 1ULL)) { | |
110 | pr_warn("write_block: len %llx is not aligned to mtt_size %llx\n", | |
111 | len, mtt_size); | |
112 | return -EINVAL; | |
113 | } | |
114 | ||
115 | mtt_entries = (len >> mtt_shift); | |
116 | ||
117 | /* | |
118 | * Align the MTT start address to the mtt_size. | |
119 | * Required to handle cases when the MR starts in the middle of an MTT | |
120 | * record. Was not required in old code since the physical addresses | |
121 | * provided by the dma subsystem were page aligned, which was also the | |
122 | * MTT size. | |
123 | */ | |
124 | cur_start_addr = round_down(cur_start_addr, mtt_size); | |
125 | /* A new block is started ... */ | |
126 | for (k = 0; k < mtt_entries; ++k) { | |
127 | pages[*npages] = cur_start_addr + (mtt_size * k); | |
128 | (*npages)++; | |
129 | /* | |
130 | * Be friendly to mlx4_write_mtt() and pass it chunks of | |
131 | * appropriate size. | |
132 | */ | |
133 | if (*npages == PAGE_SIZE / sizeof(u64)) { | |
134 | err = mlx4_write_mtt(dev->dev, mtt, *start_index, | |
135 | *npages, pages); | |
136 | if (err) | |
137 | return err; | |
138 | ||
139 | (*start_index) += *npages; | |
140 | *npages = 0; | |
141 | } | |
142 | } | |
143 | ||
144 | return 0; | |
145 | } | |
146 | ||
147 | static inline u64 alignment_of(u64 ptr) | |
148 | { | |
149 | return ilog2(ptr & (~(ptr - 1))); | |
150 | } | |
151 | ||
152 | static int mlx4_ib_umem_calc_block_mtt(u64 next_block_start, | |
153 | u64 current_block_end, | |
154 | u64 block_shift) | |
155 | { | |
156 | /* Check whether the alignment of the new block is aligned as well as | |
157 | * the previous block. | |
158 | * Block address must start with zeros till size of entity_size. | |
159 | */ | |
160 | if ((next_block_start & ((1ULL << block_shift) - 1ULL)) != 0) | |
161 | /* | |
162 | * It is not as well aligned as the previous block-reduce the | |
163 | * mtt size accordingly. Here we take the last right bit which | |
164 | * is 1. | |
165 | */ | |
166 | block_shift = alignment_of(next_block_start); | |
167 | ||
168 | /* | |
169 | * Check whether the alignment of the end of previous block - is it | |
170 | * aligned as well as the start of the block | |
171 | */ | |
172 | if (((current_block_end) & ((1ULL << block_shift) - 1ULL)) != 0) | |
173 | /* | |
174 | * It is not as well aligned as the start of the block - | |
175 | * reduce the mtt size accordingly. | |
176 | */ | |
177 | block_shift = alignment_of(current_block_end); | |
178 | ||
179 | return block_shift; | |
180 | } | |
181 | ||
225c7b1f RD |
182 | int mlx4_ib_umem_write_mtt(struct mlx4_ib_dev *dev, struct mlx4_mtt *mtt, |
183 | struct ib_umem *umem) | |
184 | { | |
185 | u64 *pages; | |
9901abf5 | 186 | u64 len = 0; |
225c7b1f | 187 | int err = 0; |
9901abf5 GL |
188 | u64 mtt_size; |
189 | u64 cur_start_addr = 0; | |
190 | u64 mtt_shift; | |
191 | int start_index = 0; | |
192 | int npages = 0; | |
eeb8461e | 193 | struct scatterlist *sg; |
9901abf5 | 194 | int i; |
225c7b1f RD |
195 | |
196 | pages = (u64 *) __get_free_page(GFP_KERNEL); | |
197 | if (!pages) | |
198 | return -ENOMEM; | |
199 | ||
9901abf5 GL |
200 | mtt_shift = mtt->page_shift; |
201 | mtt_size = 1ULL << mtt_shift; | |
225c7b1f | 202 | |
9901abf5 GL |
203 | for_each_sg(umem->sg_head.sgl, sg, umem->nmap, i) { |
204 | if (cur_start_addr + len == sg_dma_address(sg)) { | |
205 | /* still the same block */ | |
206 | len += sg_dma_len(sg); | |
207 | continue; | |
225c7b1f | 208 | } |
9901abf5 GL |
209 | /* |
210 | * A new block is started ... | |
211 | * If len is malaligned, write an extra mtt entry to cover the | |
212 | * misaligned area (round up the division) | |
213 | */ | |
214 | err = mlx4_ib_umem_write_mtt_block(dev, mtt, mtt_size, | |
215 | mtt_shift, len, | |
216 | cur_start_addr, | |
217 | pages, &start_index, | |
218 | &npages); | |
219 | if (err) | |
220 | goto out; | |
221 | ||
222 | cur_start_addr = sg_dma_address(sg); | |
223 | len = sg_dma_len(sg); | |
224 | } | |
225 | ||
226 | /* Handle the last block */ | |
227 | if (len > 0) { | |
228 | /* | |
229 | * If len is malaligned, write an extra mtt entry to cover | |
230 | * the misaligned area (round up the division) | |
231 | */ | |
232 | err = mlx4_ib_umem_write_mtt_block(dev, mtt, mtt_size, | |
233 | mtt_shift, len, | |
234 | cur_start_addr, pages, | |
235 | &start_index, &npages); | |
236 | if (err) | |
237 | goto out; | |
eeb8461e | 238 | } |
225c7b1f | 239 | |
9901abf5 GL |
240 | if (npages) |
241 | err = mlx4_write_mtt(dev->dev, mtt, start_index, npages, pages); | |
225c7b1f RD |
242 | |
243 | out: | |
244 | free_page((unsigned long) pages); | |
245 | return err; | |
246 | } | |
247 | ||
9901abf5 GL |
248 | /* |
249 | * Calculate optimal mtt size based on contiguous pages. | |
250 | * Function will return also the number of pages that are not aligned to the | |
251 | * calculated mtt_size to be added to total number of pages. For that we should | |
252 | * check the first chunk length & last chunk length and if not aligned to | |
253 | * mtt_size we should increment the non_aligned_pages number. All chunks in the | |
254 | * middle already handled as part of mtt shift calculation for both their start | |
255 | * & end addresses. | |
256 | */ | |
ed8637d3 GL |
257 | int mlx4_ib_umem_calc_optimal_mtt_size(struct ib_umem *umem, u64 start_va, |
258 | int *num_of_mtts) | |
9901abf5 GL |
259 | { |
260 | u64 block_shift = MLX4_MAX_MTT_SHIFT; | |
261 | u64 min_shift = umem->page_shift; | |
262 | u64 last_block_aligned_end = 0; | |
263 | u64 current_block_start = 0; | |
264 | u64 first_block_start = 0; | |
265 | u64 current_block_len = 0; | |
266 | u64 last_block_end = 0; | |
267 | struct scatterlist *sg; | |
268 | u64 current_block_end; | |
269 | u64 misalignment_bits; | |
270 | u64 next_block_start; | |
271 | u64 total_len = 0; | |
272 | int i; | |
273 | ||
274 | for_each_sg(umem->sg_head.sgl, sg, umem->nmap, i) { | |
275 | /* | |
276 | * Initialization - save the first chunk start as the | |
277 | * current_block_start - block means contiguous pages. | |
278 | */ | |
279 | if (current_block_len == 0 && current_block_start == 0) { | |
280 | current_block_start = sg_dma_address(sg); | |
281 | first_block_start = current_block_start; | |
282 | /* | |
283 | * Find the bits that are different between the physical | |
284 | * address and the virtual address for the start of the | |
285 | * MR. | |
286 | * umem_get aligned the start_va to a page boundary. | |
287 | * Therefore, we need to align the start va to the same | |
288 | * boundary. | |
289 | * misalignment_bits is needed to handle the case of a | |
290 | * single memory region. In this case, the rest of the | |
291 | * logic will not reduce the block size. If we use a | |
292 | * block size which is bigger than the alignment of the | |
293 | * misalignment bits, we might use the virtual page | |
294 | * number instead of the physical page number, resulting | |
295 | * in access to the wrong data. | |
296 | */ | |
297 | misalignment_bits = | |
298 | (start_va & (~(((u64)(BIT(umem->page_shift))) - 1ULL))) | |
299 | ^ current_block_start; | |
300 | block_shift = min(alignment_of(misalignment_bits), | |
301 | block_shift); | |
302 | } | |
303 | ||
304 | /* | |
305 | * Go over the scatter entries and check if they continue the | |
306 | * previous scatter entry. | |
307 | */ | |
308 | next_block_start = sg_dma_address(sg); | |
309 | current_block_end = current_block_start + current_block_len; | |
310 | /* If we have a split (non-contig.) between two blocks */ | |
311 | if (current_block_end != next_block_start) { | |
312 | block_shift = mlx4_ib_umem_calc_block_mtt | |
313 | (next_block_start, | |
314 | current_block_end, | |
315 | block_shift); | |
316 | ||
317 | /* | |
318 | * If we reached the minimum shift for 4k page we stop | |
319 | * the loop. | |
320 | */ | |
321 | if (block_shift <= min_shift) | |
322 | goto end; | |
323 | ||
324 | /* | |
325 | * If not saved yet we are in first block - we save the | |
326 | * length of first block to calculate the | |
327 | * non_aligned_pages number at the end. | |
328 | */ | |
329 | total_len += current_block_len; | |
330 | ||
331 | /* Start a new block */ | |
332 | current_block_start = next_block_start; | |
333 | current_block_len = sg_dma_len(sg); | |
334 | continue; | |
335 | } | |
336 | /* The scatter entry is another part of the current block, | |
337 | * increase the block size. | |
338 | * An entry in the scatter can be larger than 4k (page) as of | |
339 | * dma mapping which merge some blocks together. | |
340 | */ | |
341 | current_block_len += sg_dma_len(sg); | |
342 | } | |
343 | ||
344 | /* Account for the last block in the total len */ | |
345 | total_len += current_block_len; | |
346 | /* Add to the first block the misalignment that it suffers from. */ | |
347 | total_len += (first_block_start & ((1ULL << block_shift) - 1ULL)); | |
348 | last_block_end = current_block_start + current_block_len; | |
b03bcde9 | 349 | last_block_aligned_end = round_up(last_block_end, 1ULL << block_shift); |
9901abf5 GL |
350 | total_len += (last_block_aligned_end - last_block_end); |
351 | ||
352 | if (total_len & ((1ULL << block_shift) - 1ULL)) | |
353 | pr_warn("misaligned total length detected (%llu, %llu)!", | |
354 | total_len, block_shift); | |
355 | ||
356 | *num_of_mtts = total_len >> block_shift; | |
357 | end: | |
358 | if (block_shift < min_shift) { | |
359 | /* | |
360 | * If shift is less than the min we set a warning and return the | |
361 | * min shift. | |
362 | */ | |
363 | pr_warn("umem_calc_optimal_mtt_size - unexpected shift %lld\n", block_shift); | |
364 | ||
365 | block_shift = min_shift; | |
366 | } | |
367 | return block_shift; | |
368 | } | |
369 | ||
b0ea0fa5 JG |
370 | static struct ib_umem *mlx4_get_umem_mr(struct ib_ucontext *context, |
371 | struct ib_udata *udata, u64 start, | |
d8f9cc32 JM |
372 | u64 length, u64 virt_addr, |
373 | int access_flags) | |
374 | { | |
375 | /* | |
376 | * Force registering the memory as writable if the underlying pages | |
377 | * are writable. This is so rereg can change the access permissions | |
378 | * from readable to writable without having to run through ib_umem_get | |
379 | * again | |
380 | */ | |
381 | if (!ib_access_writable(access_flags)) { | |
382 | struct vm_area_struct *vma; | |
383 | ||
384 | down_read(¤t->mm->mmap_sem); | |
385 | /* | |
386 | * FIXME: Ideally this would iterate over all the vmas that | |
387 | * cover the memory, but for now it requires a single vma to | |
388 | * entirely cover the MR to support RO mappings. | |
389 | */ | |
390 | vma = find_vma(current->mm, start); | |
391 | if (vma && vma->vm_end >= start + length && | |
392 | vma->vm_start <= start) { | |
393 | if (vma->vm_flags & VM_WRITE) | |
394 | access_flags |= IB_ACCESS_LOCAL_WRITE; | |
395 | } else { | |
396 | access_flags |= IB_ACCESS_LOCAL_WRITE; | |
397 | } | |
398 | ||
399 | up_read(¤t->mm->mmap_sem); | |
400 | } | |
401 | ||
b0ea0fa5 | 402 | return ib_umem_get(udata, start, length, access_flags, 0); |
d8f9cc32 JM |
403 | } |
404 | ||
225c7b1f RD |
405 | struct ib_mr *mlx4_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, |
406 | u64 virt_addr, int access_flags, | |
407 | struct ib_udata *udata) | |
408 | { | |
409 | struct mlx4_ib_dev *dev = to_mdev(pd->device); | |
410 | struct mlx4_ib_mr *mr; | |
411 | int shift; | |
412 | int err; | |
413 | int n; | |
414 | ||
1b2cd0fc | 415 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); |
225c7b1f RD |
416 | if (!mr) |
417 | return ERR_PTR(-ENOMEM); | |
418 | ||
b0ea0fa5 | 419 | mr->umem = mlx4_get_umem_mr(pd->uobject->context, udata, start, length, |
d8f9cc32 | 420 | virt_addr, access_flags); |
225c7b1f RD |
421 | if (IS_ERR(mr->umem)) { |
422 | err = PTR_ERR(mr->umem); | |
423 | goto err_free; | |
424 | } | |
425 | ||
426 | n = ib_umem_page_count(mr->umem); | |
9901abf5 | 427 | shift = mlx4_ib_umem_calc_optimal_mtt_size(mr->umem, start, &n); |
225c7b1f RD |
428 | |
429 | err = mlx4_mr_alloc(dev->dev, to_mpd(pd)->pdn, virt_addr, length, | |
430 | convert_access(access_flags), n, shift, &mr->mmr); | |
431 | if (err) | |
432 | goto err_umem; | |
433 | ||
434 | err = mlx4_ib_umem_write_mtt(dev, &mr->mmr.mtt, mr->umem); | |
435 | if (err) | |
436 | goto err_mr; | |
437 | ||
438 | err = mlx4_mr_enable(dev->dev, &mr->mmr); | |
439 | if (err) | |
440 | goto err_mr; | |
441 | ||
442 | mr->ibmr.rkey = mr->ibmr.lkey = mr->mmr.key; | |
e6f03301 SW |
443 | mr->ibmr.length = length; |
444 | mr->ibmr.iova = virt_addr; | |
445 | mr->ibmr.page_size = 1U << shift; | |
225c7b1f RD |
446 | |
447 | return &mr->ibmr; | |
448 | ||
449 | err_mr: | |
61083720 | 450 | (void) mlx4_mr_free(to_mdev(pd->device)->dev, &mr->mmr); |
225c7b1f RD |
451 | |
452 | err_umem: | |
453 | ib_umem_release(mr->umem); | |
454 | ||
455 | err_free: | |
456 | kfree(mr); | |
457 | ||
458 | return ERR_PTR(err); | |
459 | } | |
460 | ||
9376932d MB |
461 | int mlx4_ib_rereg_user_mr(struct ib_mr *mr, int flags, |
462 | u64 start, u64 length, u64 virt_addr, | |
463 | int mr_access_flags, struct ib_pd *pd, | |
464 | struct ib_udata *udata) | |
465 | { | |
466 | struct mlx4_ib_dev *dev = to_mdev(mr->device); | |
467 | struct mlx4_ib_mr *mmr = to_mmr(mr); | |
468 | struct mlx4_mpt_entry *mpt_entry; | |
469 | struct mlx4_mpt_entry **pmpt_entry = &mpt_entry; | |
470 | int err; | |
471 | ||
472 | /* Since we synchronize this call and mlx4_ib_dereg_mr via uverbs, | |
473 | * we assume that the calls can't run concurrently. Otherwise, a | |
474 | * race exists. | |
475 | */ | |
476 | err = mlx4_mr_hw_get_mpt(dev->dev, &mmr->mmr, &pmpt_entry); | |
477 | ||
478 | if (err) | |
479 | return err; | |
480 | ||
481 | if (flags & IB_MR_REREG_PD) { | |
482 | err = mlx4_mr_hw_change_pd(dev->dev, *pmpt_entry, | |
483 | to_mpd(pd)->pdn); | |
484 | ||
485 | if (err) | |
486 | goto release_mpt_entry; | |
487 | } | |
488 | ||
489 | if (flags & IB_MR_REREG_ACCESS) { | |
3dc7c7ba CJ |
490 | if (ib_access_writable(mr_access_flags) && |
491 | !mmr->umem->writable) { | |
492 | err = -EPERM; | |
493 | goto release_mpt_entry; | |
494 | } | |
d8f9cc32 | 495 | |
9376932d MB |
496 | err = mlx4_mr_hw_change_access(dev->dev, *pmpt_entry, |
497 | convert_access(mr_access_flags)); | |
498 | ||
499 | if (err) | |
500 | goto release_mpt_entry; | |
501 | } | |
502 | ||
503 | if (flags & IB_MR_REREG_TRANS) { | |
504 | int shift; | |
9376932d MB |
505 | int n; |
506 | ||
507 | mlx4_mr_rereg_mem_cleanup(dev->dev, &mmr->mmr); | |
508 | ib_umem_release(mmr->umem); | |
d8f9cc32 | 509 | mmr->umem = |
b0ea0fa5 JG |
510 | mlx4_get_umem_mr(mr->uobject->context, udata, start, |
511 | length, virt_addr, mr_access_flags); | |
9376932d MB |
512 | if (IS_ERR(mmr->umem)) { |
513 | err = PTR_ERR(mmr->umem); | |
4ff0acca | 514 | /* Prevent mlx4_ib_dereg_mr from free'ing invalid pointer */ |
9376932d MB |
515 | mmr->umem = NULL; |
516 | goto release_mpt_entry; | |
517 | } | |
518 | n = ib_umem_page_count(mmr->umem); | |
3e7e1193 | 519 | shift = mmr->umem->page_shift; |
9376932d | 520 | |
9376932d MB |
521 | err = mlx4_mr_rereg_mem_write(dev->dev, &mmr->mmr, |
522 | virt_addr, length, n, shift, | |
523 | *pmpt_entry); | |
524 | if (err) { | |
525 | ib_umem_release(mmr->umem); | |
526 | goto release_mpt_entry; | |
527 | } | |
4ff0acca MB |
528 | mmr->mmr.iova = virt_addr; |
529 | mmr->mmr.size = length; | |
9376932d MB |
530 | |
531 | err = mlx4_ib_umem_write_mtt(dev, &mmr->mmr.mtt, mmr->umem); | |
532 | if (err) { | |
533 | mlx4_mr_rereg_mem_cleanup(dev->dev, &mmr->mmr); | |
534 | ib_umem_release(mmr->umem); | |
535 | goto release_mpt_entry; | |
536 | } | |
537 | } | |
538 | ||
539 | /* If we couldn't transfer the MR to the HCA, just remember to | |
540 | * return a failure. But dereg_mr will free the resources. | |
541 | */ | |
542 | err = mlx4_mr_hw_write_mpt(dev->dev, &mmr->mmr, pmpt_entry); | |
4ff0acca MB |
543 | if (!err && flags & IB_MR_REREG_ACCESS) |
544 | mmr->mmr.access = mr_access_flags; | |
9376932d MB |
545 | |
546 | release_mpt_entry: | |
547 | mlx4_mr_hw_put_mpt(dev->dev, pmpt_entry); | |
548 | ||
549 | return err; | |
550 | } | |
551 | ||
1b2cd0fc SG |
552 | static int |
553 | mlx4_alloc_priv_pages(struct ib_device *device, | |
554 | struct mlx4_ib_mr *mr, | |
555 | int max_pages) | |
556 | { | |
1b2cd0fc SG |
557 | int ret; |
558 | ||
cbc9355a CL |
559 | /* Ensure that size is aligned to DMA cacheline |
560 | * requirements. | |
561 | * max_pages is limited to MLX4_MAX_FAST_REG_PAGES | |
562 | * so page_map_size will never cross PAGE_SIZE. | |
563 | */ | |
564 | mr->page_map_size = roundup(max_pages * sizeof(u64), | |
565 | MLX4_MR_PAGES_ALIGN); | |
1b2cd0fc | 566 | |
cbc9355a CL |
567 | /* Prevent cross page boundary allocation. */ |
568 | mr->pages = (__be64 *)get_zeroed_page(GFP_KERNEL); | |
569 | if (!mr->pages) | |
1b2cd0fc SG |
570 | return -ENOMEM; |
571 | ||
d66c88a8 | 572 | mr->page_map = dma_map_single(device->dev.parent, mr->pages, |
cbc9355a | 573 | mr->page_map_size, DMA_TO_DEVICE); |
1b2cd0fc | 574 | |
d66c88a8 | 575 | if (dma_mapping_error(device->dev.parent, mr->page_map)) { |
1b2cd0fc SG |
576 | ret = -ENOMEM; |
577 | goto err; | |
578 | } | |
579 | ||
580 | return 0; | |
1b2cd0fc | 581 | |
cbc9355a CL |
582 | err: |
583 | free_page((unsigned long)mr->pages); | |
1b2cd0fc SG |
584 | return ret; |
585 | } | |
586 | ||
587 | static void | |
588 | mlx4_free_priv_pages(struct mlx4_ib_mr *mr) | |
589 | { | |
590 | if (mr->pages) { | |
591 | struct ib_device *device = mr->ibmr.device; | |
1b2cd0fc | 592 | |
d66c88a8 | 593 | dma_unmap_single(device->dev.parent, mr->page_map, |
cbc9355a CL |
594 | mr->page_map_size, DMA_TO_DEVICE); |
595 | free_page((unsigned long)mr->pages); | |
1b2cd0fc SG |
596 | mr->pages = NULL; |
597 | } | |
598 | } | |
599 | ||
225c7b1f RD |
600 | int mlx4_ib_dereg_mr(struct ib_mr *ibmr) |
601 | { | |
602 | struct mlx4_ib_mr *mr = to_mmr(ibmr); | |
61083720 | 603 | int ret; |
225c7b1f | 604 | |
1b2cd0fc SG |
605 | mlx4_free_priv_pages(mr); |
606 | ||
61083720 SM |
607 | ret = mlx4_mr_free(to_mdev(ibmr->device)->dev, &mr->mmr); |
608 | if (ret) | |
609 | return ret; | |
225c7b1f RD |
610 | if (mr->umem) |
611 | ib_umem_release(mr->umem); | |
612 | kfree(mr); | |
613 | ||
614 | return 0; | |
615 | } | |
8ad11fb6 | 616 | |
b2a239df MB |
617 | struct ib_mw *mlx4_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, |
618 | struct ib_udata *udata) | |
804d6a89 SM |
619 | { |
620 | struct mlx4_ib_dev *dev = to_mdev(pd->device); | |
621 | struct mlx4_ib_mw *mw; | |
622 | int err; | |
623 | ||
624 | mw = kmalloc(sizeof(*mw), GFP_KERNEL); | |
625 | if (!mw) | |
626 | return ERR_PTR(-ENOMEM); | |
627 | ||
628 | err = mlx4_mw_alloc(dev->dev, to_mpd(pd)->pdn, | |
629 | to_mlx4_type(type), &mw->mmw); | |
630 | if (err) | |
631 | goto err_free; | |
632 | ||
633 | err = mlx4_mw_enable(dev->dev, &mw->mmw); | |
634 | if (err) | |
635 | goto err_mw; | |
636 | ||
637 | mw->ibmw.rkey = mw->mmw.key; | |
638 | ||
639 | return &mw->ibmw; | |
640 | ||
641 | err_mw: | |
642 | mlx4_mw_free(dev->dev, &mw->mmw); | |
643 | ||
644 | err_free: | |
645 | kfree(mw); | |
646 | ||
647 | return ERR_PTR(err); | |
648 | } | |
649 | ||
650 | int mlx4_ib_dealloc_mw(struct ib_mw *ibmw) | |
651 | { | |
652 | struct mlx4_ib_mw *mw = to_mmw(ibmw); | |
653 | ||
654 | mlx4_mw_free(to_mdev(ibmw->device)->dev, &mw->mmw); | |
655 | kfree(mw); | |
656 | ||
657 | return 0; | |
658 | } | |
659 | ||
679e34d1 SG |
660 | struct ib_mr *mlx4_ib_alloc_mr(struct ib_pd *pd, |
661 | enum ib_mr_type mr_type, | |
662 | u32 max_num_sg) | |
95d04f07 RD |
663 | { |
664 | struct mlx4_ib_dev *dev = to_mdev(pd->device); | |
665 | struct mlx4_ib_mr *mr; | |
666 | int err; | |
667 | ||
679e34d1 SG |
668 | if (mr_type != IB_MR_TYPE_MEM_REG || |
669 | max_num_sg > MLX4_MAX_FAST_REG_PAGES) | |
670 | return ERR_PTR(-EINVAL); | |
671 | ||
1b2cd0fc | 672 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); |
95d04f07 RD |
673 | if (!mr) |
674 | return ERR_PTR(-ENOMEM); | |
675 | ||
676 | err = mlx4_mr_alloc(dev->dev, to_mpd(pd)->pdn, 0, 0, 0, | |
679e34d1 | 677 | max_num_sg, 0, &mr->mmr); |
95d04f07 RD |
678 | if (err) |
679 | goto err_free; | |
680 | ||
1b2cd0fc SG |
681 | err = mlx4_alloc_priv_pages(pd->device, mr, max_num_sg); |
682 | if (err) | |
683 | goto err_free_mr; | |
684 | ||
685 | mr->max_pages = max_num_sg; | |
95d04f07 RD |
686 | err = mlx4_mr_enable(dev->dev, &mr->mmr); |
687 | if (err) | |
1b2cd0fc | 688 | goto err_free_pl; |
95d04f07 | 689 | |
4c246edd | 690 | mr->ibmr.rkey = mr->ibmr.lkey = mr->mmr.key; |
7f3abf5c | 691 | mr->umem = NULL; |
4c246edd | 692 | |
95d04f07 RD |
693 | return &mr->ibmr; |
694 | ||
1b2cd0fc | 695 | err_free_pl: |
5a371cf8 | 696 | mr->ibmr.device = pd->device; |
1b2cd0fc SG |
697 | mlx4_free_priv_pages(mr); |
698 | err_free_mr: | |
61083720 | 699 | (void) mlx4_mr_free(dev->dev, &mr->mmr); |
95d04f07 RD |
700 | err_free: |
701 | kfree(mr); | |
702 | return ERR_PTR(err); | |
703 | } | |
704 | ||
8ad11fb6 JM |
705 | struct ib_fmr *mlx4_ib_fmr_alloc(struct ib_pd *pd, int acc, |
706 | struct ib_fmr_attr *fmr_attr) | |
707 | { | |
708 | struct mlx4_ib_dev *dev = to_mdev(pd->device); | |
709 | struct mlx4_ib_fmr *fmr; | |
710 | int err = -ENOMEM; | |
711 | ||
712 | fmr = kmalloc(sizeof *fmr, GFP_KERNEL); | |
713 | if (!fmr) | |
714 | return ERR_PTR(-ENOMEM); | |
715 | ||
716 | err = mlx4_fmr_alloc(dev->dev, to_mpd(pd)->pdn, convert_access(acc), | |
717 | fmr_attr->max_pages, fmr_attr->max_maps, | |
718 | fmr_attr->page_shift, &fmr->mfmr); | |
719 | if (err) | |
720 | goto err_free; | |
721 | ||
e6028c0e | 722 | err = mlx4_fmr_enable(to_mdev(pd->device)->dev, &fmr->mfmr); |
8ad11fb6 JM |
723 | if (err) |
724 | goto err_mr; | |
725 | ||
726 | fmr->ibfmr.rkey = fmr->ibfmr.lkey = fmr->mfmr.mr.key; | |
727 | ||
728 | return &fmr->ibfmr; | |
729 | ||
730 | err_mr: | |
61083720 | 731 | (void) mlx4_mr_free(to_mdev(pd->device)->dev, &fmr->mfmr.mr); |
8ad11fb6 JM |
732 | |
733 | err_free: | |
734 | kfree(fmr); | |
735 | ||
736 | return ERR_PTR(err); | |
737 | } | |
738 | ||
739 | int mlx4_ib_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list, | |
740 | int npages, u64 iova) | |
741 | { | |
742 | struct mlx4_ib_fmr *ifmr = to_mfmr(ibfmr); | |
743 | struct mlx4_ib_dev *dev = to_mdev(ifmr->ibfmr.device); | |
744 | ||
745 | return mlx4_map_phys_fmr(dev->dev, &ifmr->mfmr, page_list, npages, iova, | |
746 | &ifmr->ibfmr.lkey, &ifmr->ibfmr.rkey); | |
747 | } | |
748 | ||
749 | int mlx4_ib_unmap_fmr(struct list_head *fmr_list) | |
750 | { | |
751 | struct ib_fmr *ibfmr; | |
752 | int err; | |
753 | struct mlx4_dev *mdev = NULL; | |
754 | ||
755 | list_for_each_entry(ibfmr, fmr_list, list) { | |
756 | if (mdev && to_mdev(ibfmr->device)->dev != mdev) | |
757 | return -EINVAL; | |
758 | mdev = to_mdev(ibfmr->device)->dev; | |
759 | } | |
760 | ||
761 | if (!mdev) | |
762 | return 0; | |
763 | ||
764 | list_for_each_entry(ibfmr, fmr_list, list) { | |
765 | struct mlx4_ib_fmr *ifmr = to_mfmr(ibfmr); | |
766 | ||
767 | mlx4_fmr_unmap(mdev, &ifmr->mfmr, &ifmr->ibfmr.lkey, &ifmr->ibfmr.rkey); | |
768 | } | |
769 | ||
770 | /* | |
771 | * Make sure all MPT status updates are visible before issuing | |
772 | * SYNC_TPT firmware command. | |
773 | */ | |
774 | wmb(); | |
775 | ||
776 | err = mlx4_SYNC_TPT(mdev); | |
777 | if (err) | |
987c8f8f | 778 | pr_warn("SYNC_TPT error %d when " |
8ad11fb6 JM |
779 | "unmapping FMRs\n", err); |
780 | ||
781 | return 0; | |
782 | } | |
783 | ||
784 | int mlx4_ib_fmr_dealloc(struct ib_fmr *ibfmr) | |
785 | { | |
786 | struct mlx4_ib_fmr *ifmr = to_mfmr(ibfmr); | |
787 | struct mlx4_ib_dev *dev = to_mdev(ibfmr->device); | |
788 | int err; | |
789 | ||
790 | err = mlx4_fmr_free(dev->dev, &ifmr->mfmr); | |
791 | ||
792 | if (!err) | |
793 | kfree(ifmr); | |
794 | ||
795 | return err; | |
796 | } | |
1b2cd0fc SG |
797 | |
798 | static int mlx4_set_page(struct ib_mr *ibmr, u64 addr) | |
799 | { | |
800 | struct mlx4_ib_mr *mr = to_mmr(ibmr); | |
801 | ||
802 | if (unlikely(mr->npages == mr->max_pages)) | |
803 | return -ENOMEM; | |
804 | ||
805 | mr->pages[mr->npages++] = cpu_to_be64(addr | MLX4_MTT_FLAG_PRESENT); | |
806 | ||
807 | return 0; | |
808 | } | |
809 | ||
ff2ba993 | 810 | int mlx4_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, |
9aa8b321 | 811 | unsigned int *sg_offset) |
1b2cd0fc SG |
812 | { |
813 | struct mlx4_ib_mr *mr = to_mmr(ibmr); | |
814 | int rc; | |
815 | ||
816 | mr->npages = 0; | |
817 | ||
818 | ib_dma_sync_single_for_cpu(ibmr->device, mr->page_map, | |
cbc9355a | 819 | mr->page_map_size, DMA_TO_DEVICE); |
1b2cd0fc | 820 | |
ff2ba993 | 821 | rc = ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, mlx4_set_page); |
1b2cd0fc SG |
822 | |
823 | ib_dma_sync_single_for_device(ibmr->device, mr->page_map, | |
cbc9355a | 824 | mr->page_map_size, DMA_TO_DEVICE); |
1b2cd0fc SG |
825 | |
826 | return rc; | |
827 | } |