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IB/mlx5: Fix wrong naming of port_rcv_data counter
[mirror_ubuntu-jammy-kernel.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
ea54b10c 34#include <linux/log2.h>
1049f138 35#include <linux/etherdevice.h>
3ef967a4 36#include <net/ip.h>
5a0e3ad6 37#include <linux/slab.h>
fa417f7b 38#include <linux/netdevice.h>
0ef2f05c 39#include <linux/vmalloc.h>
ea54b10c 40
225c7b1f
RD		 41#include <rdma/ib_cache.h>
42#include <rdma/ib_pack.h>
4c3eb3ca 43#include <rdma/ib_addr.h>
1ffeb2eb 44#include <rdma/ib_mad.h>
225c7b1f 45
2f48485d 46#include <linux/mlx4/driver.h>
225c7b1f
RD		 47#include <linux/mlx4/qp.h>
48
49#include "mlx4_ib.h"
50#include "user.h"
51
35f05dab
YH		 52static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
53 struct mlx4_ib_cq *recv_cq);
54static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
55 struct mlx4_ib_cq *recv_cq);
56
225c7b1f
RD		 57enum {
58 MLX4_IB_ACK_REQ_FREQ = 8,
59};
60
61enum {
62 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
fa417f7b
EC		 63 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
64 MLX4_IB_LINK_TYPE_IB = 0,
65 MLX4_IB_LINK_TYPE_ETH = 1
225c7b1f
RD		 66};
67
68enum {
69 /*
fa417f7b 70 * Largest possible UD header: send with GRH and immediate
4c3eb3ca
EC		 71 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
72 * tag. (LRH would only use 8 bytes, so Ethernet is the
73 * biggest case)
225c7b1f 74 */
4c3eb3ca 75 MLX4_IB_UD_HEADER_SIZE = 82,
417608c2 76 MLX4_IB_LSO_HEADER_SPARE = 128,
225c7b1f
RD		 77};
78
fa417f7b
EC		 79enum {
80 MLX4_IB_IBOE_ETHERTYPE = 0x8915
81};
82
225c7b1f
RD		 83struct mlx4_ib_sqp {
84 struct mlx4_ib_qp qp;
85 int pkey_index;
86 u32 qkey;
87 u32 send_psn;
88 struct ib_ud_header ud_header;
89 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
e1b866c6 90 struct ib_qp *roce_v2_gsi;
225c7b1f
RD		 91};
92
83904132 93enum {
417608c2
EC		 94 MLX4_IB_MIN_SQ_STRIDE = 6,
95 MLX4_IB_CACHE_LINE_SIZE = 64,
83904132
JM		 96};
97
3987a2d3
OG		 98enum {
99 MLX4_RAW_QP_MTU = 7,
100 MLX4_RAW_QP_MSGMAX = 31,
101};
102
297e0dad
MS		 103#ifndef ETH_ALEN
104#define ETH_ALEN 6
105#endif
297e0dad 106
225c7b1f 107static const __be32 mlx4_ib_opcode[] = {
6fa8f719
VS		 108 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
109 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
110 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
111 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
112 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
113 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
114 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
115 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
116 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
117 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
1b2cd0fc 118 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
6fa8f719
VS		 119 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
120 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
225c7b1f
RD		 121};
122
123static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
124{
125 return container_of(mqp, struct mlx4_ib_sqp, qp);
126}
127
1ffeb2eb
JM		 128static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
129{
130 if (!mlx4_is_master(dev->dev))
131 return 0;
132
47605df9
JM		 133 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
134 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
135 8 * MLX4_MFUNC_MAX;
1ffeb2eb
JM		 136}
137
225c7b1f
RD		 138static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
139{
47605df9
JM		 140 int proxy_sqp = 0;
141 int real_sqp = 0;
142 int i;
143 /* PPF or Native -- real SQP */
144 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
145 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
146 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
147 if (real_sqp)
148 return 1;
149 /* VF or PF -- proxy SQP */
150 if (mlx4_is_mfunc(dev->dev)) {
151 for (i = 0; i < dev->dev->caps.num_ports; i++) {
152 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
153 qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
154 proxy_sqp = 1;
155 break;
156 }
157 }
158 }
e1b866c6
MS		 159 if (proxy_sqp)
160 return 1;
161
162 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP);
225c7b1f
RD		 163}
164
1ffeb2eb 165/* used for INIT/CLOSE port logic */
225c7b1f
RD		 166static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
167{
47605df9
JM		 168 int proxy_qp0 = 0;
169 int real_qp0 = 0;
170 int i;
171 /* PPF or Native -- real QP0 */
172 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
173 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
174 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
175 if (real_qp0)
176 return 1;
177 /* VF or PF -- proxy QP0 */
178 if (mlx4_is_mfunc(dev->dev)) {
179 for (i = 0; i < dev->dev->caps.num_ports; i++) {
180 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
181 proxy_qp0 = 1;
182 break;
183 }
184 }
185 }
186 return proxy_qp0;
225c7b1f
RD		 187}
188
189static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
190{
1c69fc2a 191 return mlx4_buf_offset(&qp->buf, offset);
225c7b1f
RD		 192}
193
194static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
195{
196 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
197}
198
199static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
200{
201 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
202}
203
0e6e7416
RD		 204/*
205 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
ea54b10c
JM		 206 * first four bytes of every 64 byte chunk with
207 * 0x7FFFFFF | (invalid_ownership_value << 31).
208 *
209 * When the max work request size is less than or equal to the WQE
210 * basic block size, as an optimization, we can stamp all WQEs with
211 * 0xffffffff, and skip the very first chunk of each WQE.
0e6e7416 212 */
ea54b10c 213static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
0e6e7416 214{
d2ae16d5 215 __be32 *wqe;
0e6e7416 216 int i;
ea54b10c
JM		 217 int s;
218 int ind;
219 void *buf;
220 __be32 stamp;
9670e553 221 struct mlx4_wqe_ctrl_seg *ctrl;
ea54b10c 222
ea54b10c 223 if (qp->sq_max_wqes_per_wr > 1) {
9670e553 224 s = roundup(size, 1U << qp->sq.wqe_shift);
ea54b10c
JM		 225 for (i = 0; i < s; i += 64) {
226 ind = (i >> qp->sq.wqe_shift) + n;
227 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
228 cpu_to_be32(0xffffffff);
229 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
230 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
231 *wqe = stamp;
232 }
233 } else {
9670e553
EC		 234 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
235 s = (ctrl->fence_size & 0x3f) << 4;
ea54b10c
JM		 236 for (i = 64; i < s; i += 64) {
237 wqe = buf + i;
d2ae16d5 238 *wqe = cpu_to_be32(0xffffffff);
ea54b10c
JM		 239 }
240 }
241}
242
243static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
244{
245 struct mlx4_wqe_ctrl_seg *ctrl;
246 struct mlx4_wqe_inline_seg *inl;
247 void *wqe;
248 int s;
249
250 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
251 s = sizeof(struct mlx4_wqe_ctrl_seg);
252
253 if (qp->ibqp.qp_type == IB_QPT_UD) {
254 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
255 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
256 memset(dgram, 0, sizeof *dgram);
257 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
258 s += sizeof(struct mlx4_wqe_datagram_seg);
259 }
260
261 /* Pad the remainder of the WQE with an inline data segment. */
262 if (size > s) {
263 inl = wqe + s;
264 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
265 }
266 ctrl->srcrb_flags = 0;
267 ctrl->fence_size = size / 16;
268 /*
269 * Make sure descriptor is fully written before setting ownership bit
270 * (because HW can start executing as soon as we do).
271 */
272 wmb();
273
274 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
275 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
0e6e7416 276
ea54b10c
JM		 277 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
278}
279
280/* Post NOP WQE to prevent wrap-around in the middle of WR */
281static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
282{
283 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
284 if (unlikely(s < qp->sq_max_wqes_per_wr)) {
285 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
286 ind += s;
287 }
288 return ind;
0e6e7416
RD		 289}
290
225c7b1f
RD		 291static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
292{
293 struct ib_event event;
294 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
295
296 if (type == MLX4_EVENT_TYPE_PATH_MIG)
297 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
298
299 if (ibqp->event_handler) {
300 event.device = ibqp->device;
301 event.element.qp = ibqp;
302 switch (type) {
303 case MLX4_EVENT_TYPE_PATH_MIG:
304 event.event = IB_EVENT_PATH_MIG;
305 break;
306 case MLX4_EVENT_TYPE_COMM_EST:
307 event.event = IB_EVENT_COMM_EST;
308 break;
309 case MLX4_EVENT_TYPE_SQ_DRAINED:
310 event.event = IB_EVENT_SQ_DRAINED;
311 break;
312 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
313 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
314 break;
315 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
316 event.event = IB_EVENT_QP_FATAL;
317 break;
318 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
319 event.event = IB_EVENT_PATH_MIG_ERR;
320 break;
321 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
322 event.event = IB_EVENT_QP_REQ_ERR;
323 break;
324 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
325 event.event = IB_EVENT_QP_ACCESS_ERR;
326 break;
327 default:
987c8f8f 328 pr_warn("Unexpected event type %d "
225c7b1f
RD		 329 "on QP %06x\n", type, qp->qpn);
330 return;
331 }
332
333 ibqp->event_handler(&event, ibqp->qp_context);
334 }
335}
336
1ffeb2eb 337static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
225c7b1f
RD		 338{
339 /*
340 * UD WQEs must have a datagram segment.
341 * RC and UC WQEs might have a remote address segment.
342 * MLX WQEs need two extra inline data segments (for the UD
343 * header and space for the ICRC).
344 */
345 switch (type) {
1ffeb2eb 346 case MLX4_IB_QPT_UD:
225c7b1f 347 return sizeof (struct mlx4_wqe_ctrl_seg) +
b832be1e 348 sizeof (struct mlx4_wqe_datagram_seg) +
417608c2 349 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
1ffeb2eb
JM		 350 case MLX4_IB_QPT_PROXY_SMI_OWNER:
351 case MLX4_IB_QPT_PROXY_SMI:
352 case MLX4_IB_QPT_PROXY_GSI:
353 return sizeof (struct mlx4_wqe_ctrl_seg) +
354 sizeof (struct mlx4_wqe_datagram_seg) + 64;
355 case MLX4_IB_QPT_TUN_SMI_OWNER:
356 case MLX4_IB_QPT_TUN_GSI:
357 return sizeof (struct mlx4_wqe_ctrl_seg) +
358 sizeof (struct mlx4_wqe_datagram_seg);
359
360 case MLX4_IB_QPT_UC:
225c7b1f
RD		 361 return sizeof (struct mlx4_wqe_ctrl_seg) +
362 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb 363 case MLX4_IB_QPT_RC:
225c7b1f
RD		 364 return sizeof (struct mlx4_wqe_ctrl_seg) +
365 sizeof (struct mlx4_wqe_atomic_seg) +
366 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb
JM		 367 case MLX4_IB_QPT_SMI:
368 case MLX4_IB_QPT_GSI:
225c7b1f
RD		 369 return sizeof (struct mlx4_wqe_ctrl_seg) +
370 ALIGN(MLX4_IB_UD_HEADER_SIZE +
e61ef241
RD		 371 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
372 MLX4_INLINE_ALIGN) *
225c7b1f
RD		 373 sizeof (struct mlx4_wqe_inline_seg),
374 sizeof (struct mlx4_wqe_data_seg)) +
375 ALIGN(4 +
376 sizeof (struct mlx4_wqe_inline_seg),
377 sizeof (struct mlx4_wqe_data_seg));
378 default:
379 return sizeof (struct mlx4_wqe_ctrl_seg);
380 }
381}
382
2446304d 383static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
0a1405da 384 int is_user, int has_rq, struct mlx4_ib_qp *qp)
225c7b1f 385{
2446304d 386 /* Sanity check RQ size before proceeding */
fc2d0044
SG		 387 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
388 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
2446304d
EC		 389 return -EINVAL;
390
0a1405da 391 if (!has_rq) {
a4cd7ed8
RD		 392 if (cap->max_recv_wr)
393 return -EINVAL;
2446304d 394
0e6e7416 395 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
a4cd7ed8
RD		 396 } else {
397 /* HW requires >= 1 RQ entry with >= 1 gather entry */
398 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
399 return -EINVAL;
400
0e6e7416 401 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
42c059ea 402 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
a4cd7ed8
RD		 403 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
404 }
2446304d 405
fc2d0044
SG		 406 /* leave userspace return values as they were, so as not to break ABI */
407 if (is_user) {
408 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
409 cap->max_recv_sge = qp->rq.max_gs;
410 } else {
411 cap->max_recv_wr = qp->rq.max_post =
412 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
413 cap->max_recv_sge = min(qp->rq.max_gs,
414 min(dev->dev->caps.max_sq_sg,
415 dev->dev->caps.max_rq_sg));
416 }
2446304d
EC		 417
418 return 0;
419}
420
421static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
73898db0
HA		 422 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp,
423 bool shrink_wqe)
2446304d 424{
ea54b10c
JM		 425 int s;
426
2446304d 427 /* Sanity check SQ size before proceeding */
fc2d0044
SG		 428 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
429 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
b832be1e 430 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
225c7b1f
RD		 431 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
432 return -EINVAL;
433
434 /*
435 * For MLX transport we need 2 extra S/G entries:
436 * one for the header and one for the checksum at the end
437 */
1ffeb2eb
JM		 438 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
439 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
225c7b1f
RD		 440 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
441 return -EINVAL;
442
ea54b10c
JM		 443 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
444 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
b832be1e 445 send_wqe_overhead(type, qp->flags);
225c7b1f 446
cd155c1c
RD		 447 if (s > dev->dev->caps.max_sq_desc_sz)
448 return -EINVAL;
449
0e6e7416 450 /*
ea54b10c
JM		 451 * Hermon supports shrinking WQEs, such that a single work
452 * request can include multiple units of 1 << wqe_shift. This
453 * way, work requests can differ in size, and do not have to
454 * be a power of 2 in size, saving memory and speeding up send
455 * WR posting. Unfortunately, if we do this then the
456 * wqe_index field in CQEs can't be used to look up the WR ID
457 * anymore, so we do this only if selective signaling is off.
458 *
459 * Further, on 32-bit platforms, we can't use vmap() to make
af901ca1 460 * the QP buffer virtually contiguous. Thus we have to use
ea54b10c
JM		 461 * constant-sized WRs to make sure a WR is always fully within
462 * a single page-sized chunk.
463 *
464 * Finally, we use NOP work requests to pad the end of the
465 * work queue, to avoid wrap-around in the middle of WR. We
466 * set NEC bit to avoid getting completions with error for
467 * these NOP WRs, but since NEC is only supported starting
468 * with firmware 2.2.232, we use constant-sized WRs for older
469 * firmware.
470 *
471 * And, since MLX QPs only support SEND, we use constant-sized
472 * WRs in this case.
473 *
474 * We look for the smallest value of wqe_shift such that the
475 * resulting number of wqes does not exceed device
476 * capabilities.
477 *
478 * We set WQE size to at least 64 bytes, this way stamping
479 * invalidates each WQE.
0e6e7416 480 */
73898db0 481 if (shrink_wqe && dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
ea54b10c 482 qp->sq_signal_bits && BITS_PER_LONG == 64 &&
1ffeb2eb
JM		 483 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
484 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
485 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
ea54b10c
JM		 486 qp->sq.wqe_shift = ilog2(64);
487 else
488 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
489
490 for (;;) {
ea54b10c
JM		 491 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
492
493 /*
494 * We need to leave 2 KB + 1 WR of headroom in the SQ to
495 * allow HW to prefetch.
496 */
497 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
498 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
499 qp->sq_max_wqes_per_wr +
500 qp->sq_spare_wqes);
501
502 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
503 break;
504
505 if (qp->sq_max_wqes_per_wr <= 1)
506 return -EINVAL;
507
508 ++qp->sq.wqe_shift;
509 }
510
cd155c1c
RD		 511 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
512 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
b832be1e
EC		 513 send_wqe_overhead(type, qp->flags)) /
514 sizeof (struct mlx4_wqe_data_seg);
0e6e7416
RD		 515
516 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
517 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
225c7b1f
RD		 518 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
519 qp->rq.offset = 0;
0e6e7416 520 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
225c7b1f 521 } else {
0e6e7416 522 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
225c7b1f
RD		 523 qp->sq.offset = 0;
524 }
525
ea54b10c
JM		 526 cap->max_send_wr = qp->sq.max_post =
527 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
cd155c1c
RD		 528 cap->max_send_sge = min(qp->sq.max_gs,
529 min(dev->dev->caps.max_sq_sg,
530 dev->dev->caps.max_rq_sg));
54e95f8d
RD		 531 /* We don't support inline sends for kernel QPs (yet) */
532 cap->max_inline_data = 0;
225c7b1f
RD		 533
534 return 0;
535}
536
83904132
JM		 537static int set_user_sq_size(struct mlx4_ib_dev *dev,
538 struct mlx4_ib_qp *qp,
2446304d
EC		 539 struct mlx4_ib_create_qp *ucmd)
540{
83904132
JM		 541 /* Sanity check SQ size before proceeding */
542 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
543 ucmd->log_sq_stride >
544 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
545 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
546 return -EINVAL;
547
0e6e7416 548 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
2446304d
EC		 549 qp->sq.wqe_shift = ucmd->log_sq_stride;
550
0e6e7416
RD		 551 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
552 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
2446304d
EC		 553
554 return 0;
555}
556
1ffeb2eb
JM		 557static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
558{
559 int i;
560
561 qp->sqp_proxy_rcv =
562 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
563 GFP_KERNEL);
564 if (!qp->sqp_proxy_rcv)
565 return -ENOMEM;
566 for (i = 0; i < qp->rq.wqe_cnt; i++) {
567 qp->sqp_proxy_rcv[i].addr =
568 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
569 GFP_KERNEL);
570 if (!qp->sqp_proxy_rcv[i].addr)
571 goto err;
572 qp->sqp_proxy_rcv[i].map =
573 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
574 sizeof (struct mlx4_ib_proxy_sqp_hdr),
575 DMA_FROM_DEVICE);
cc47d369
SO		 576 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
577 kfree(qp->sqp_proxy_rcv[i].addr);
578 goto err;
579 }
1ffeb2eb
JM		 580 }
581 return 0;
582
583err:
584 while (i > 0) {
585 --i;
586 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
587 sizeof (struct mlx4_ib_proxy_sqp_hdr),
588 DMA_FROM_DEVICE);
589 kfree(qp->sqp_proxy_rcv[i].addr);
590 }
591 kfree(qp->sqp_proxy_rcv);
592 qp->sqp_proxy_rcv = NULL;
593 return -ENOMEM;
594}
595
596static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
597{
598 int i;
599
600 for (i = 0; i < qp->rq.wqe_cnt; i++) {
601 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
602 sizeof (struct mlx4_ib_proxy_sqp_hdr),
603 DMA_FROM_DEVICE);
604 kfree(qp->sqp_proxy_rcv[i].addr);
605 }
606 kfree(qp->sqp_proxy_rcv);
607}
608
0a1405da
SH		 609static int qp_has_rq(struct ib_qp_init_attr *attr)
610{
611 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
612 return 0;
613
614 return !attr->srq;
615}
616
99ec41d0
JM		 617static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
618{
619 int i;
620 for (i = 0; i < dev->caps.num_ports; i++) {
621 if (qpn == dev->caps.qp0_proxy[i])
622 return !!dev->caps.qp0_qkey[i];
623 }
624 return 0;
625}
626
7b59f0f9
EBE		 627static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
628 struct mlx4_ib_qp *qp)
629{
630 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
631 mlx4_counter_free(dev->dev, qp->counter_index->index);
632 list_del(&qp->counter_index->list);
633 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
634
635 kfree(qp->counter_index);
636 qp->counter_index = NULL;
637}
638
225c7b1f
RD		 639static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
640 struct ib_qp_init_attr *init_attr,
40f2287b
JK		 641 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp,
642 gfp_t gfp)
225c7b1f 643{
a3cdcbfa 644 int qpn;
225c7b1f 645 int err;
73898db0 646 struct ib_qp_cap backup_cap;
1ffeb2eb
JM		 647 struct mlx4_ib_sqp *sqp;
648 struct mlx4_ib_qp *qp;
649 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
35f05dab
YH		 650 struct mlx4_ib_cq *mcq;
651 unsigned long flags;
1ffeb2eb
JM		 652
653 /* When tunneling special qps, we use a plain UD qp */
654 if (sqpn) {
655 if (mlx4_is_mfunc(dev->dev) &&
656 (!mlx4_is_master(dev->dev) ||
657 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
658 if (init_attr->qp_type == IB_QPT_GSI)
659 qp_type = MLX4_IB_QPT_PROXY_GSI;
99ec41d0
JM		 660 else {
661 if (mlx4_is_master(dev->dev) ||
662 qp0_enabled_vf(dev->dev, sqpn))
663 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
664 else
665 qp_type = MLX4_IB_QPT_PROXY_SMI;
666 }
1ffeb2eb
JM		 667 }
668 qpn = sqpn;
669 /* add extra sg entry for tunneling */
670 init_attr->cap.max_recv_sge++;
671 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
672 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
673 container_of(init_attr,
674 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
675 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
676 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
677 !mlx4_is_master(dev->dev))
678 return -EINVAL;
679 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
680 qp_type = MLX4_IB_QPT_TUN_GSI;
99ec41d0
JM		 681 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
682 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
683 tnl_init->port))
1ffeb2eb
JM		 684 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
685 else
686 qp_type = MLX4_IB_QPT_TUN_SMI;
47605df9
JM		 687 /* we are definitely in the PPF here, since we are creating
688 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
689 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
690 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1ffeb2eb
JM		 691 sqpn = qpn;
692 }
693
694 if (!*caller_qp) {
695 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
696 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
697 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6fcd8d0d 698 sqp = kzalloc(sizeof (struct mlx4_ib_sqp), gfp);
1ffeb2eb
JM		 699 if (!sqp)
700 return -ENOMEM;
701 qp = &sqp->qp;
2f5bb473
JM		 702 qp->pri.vid = 0xFFFF;
703 qp->alt.vid = 0xFFFF;
1ffeb2eb 704 } else {
6fcd8d0d 705 qp = kzalloc(sizeof (struct mlx4_ib_qp), gfp);
1ffeb2eb
JM		 706 if (!qp)
707 return -ENOMEM;
2f5bb473
JM		 708 qp->pri.vid = 0xFFFF;
709 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 710 }
711 } else
712 qp = *caller_qp;
713
714 qp->mlx4_ib_qp_type = qp_type;
225c7b1f
RD		 715
716 mutex_init(&qp->mutex);
717 spin_lock_init(&qp->sq.lock);
718 spin_lock_init(&qp->rq.lock);
fa417f7b 719 INIT_LIST_HEAD(&qp->gid_list);
0ff1fb65 720 INIT_LIST_HEAD(&qp->steering_rules);
225c7b1f
RD		 721
722 qp->state = IB_QPS_RESET;
ea54b10c
JM		 723 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
724 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
225c7b1f 725
0a1405da 726 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
225c7b1f
RD		 727 if (err)
728 goto err;
729
730 if (pd->uobject) {
731 struct mlx4_ib_create_qp ucmd;
732
733 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
734 err = -EFAULT;
735 goto err;
736 }
737
0e6e7416
RD		 738 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
739
83904132 740 err = set_user_sq_size(dev, qp, &ucmd);
2446304d
EC		 741 if (err)
742 goto err;
743
225c7b1f 744 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
cb9fbc5c 745 qp->buf_size, 0, 0);
225c7b1f
RD		 746 if (IS_ERR(qp->umem)) {
747 err = PTR_ERR(qp->umem);
748 goto err;
749 }
750
751 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
752 ilog2(qp->umem->page_size), &qp->mtt);
753 if (err)
754 goto err_buf;
755
756 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
757 if (err)
758 goto err_mtt;
759
0a1405da 760 if (qp_has_rq(init_attr)) {
02d89b87
RD		 761 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
762 ucmd.db_addr, &qp->db);
763 if (err)
764 goto err_mtt;
765 }
225c7b1f 766 } else {
0e6e7416
RD		 767 qp->sq_no_prefetch = 0;
768
b832be1e
EC		 769 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
770 qp->flags |= MLX4_IB_QP_LSO;
771
c1c98501
MB		 772 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
773 if (dev->steering_support ==
774 MLX4_STEERING_MODE_DEVICE_MANAGED)
775 qp->flags |= MLX4_IB_QP_NETIF;
776 else
777 goto err;
778 }
779
73898db0
HA		 780 memcpy(&backup_cap, &init_attr->cap, sizeof(backup_cap));
781 err = set_kernel_sq_size(dev, &init_attr->cap,
782 qp_type, qp, true);
2446304d
EC		 783 if (err)
784 goto err;
785
0a1405da 786 if (qp_has_rq(init_attr)) {
40f2287b 787 err = mlx4_db_alloc(dev->dev, &qp->db, 0, gfp);
02d89b87
RD		 788 if (err)
789 goto err;
225c7b1f 790
02d89b87
RD		 791 *qp->db.db = 0;
792 }
225c7b1f 793
73898db0
HA		 794 if (mlx4_buf_alloc(dev->dev, qp->buf_size, qp->buf_size,
795 &qp->buf, gfp)) {
796 memcpy(&init_attr->cap, &backup_cap,
797 sizeof(backup_cap));
798 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type,
799 qp, false);
800 if (err)
801 goto err_db;
802
803 if (mlx4_buf_alloc(dev->dev, qp->buf_size,
804 PAGE_SIZE * 2, &qp->buf, gfp)) {
805 err = -ENOMEM;
806 goto err_db;
807 }
225c7b1f
RD		 808 }
809
810 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
811 &qp->mtt);
812 if (err)
813 goto err_buf;
814
40f2287b 815 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf, gfp);
225c7b1f
RD		 816 if (err)
817 goto err_mtt;
818
ee370950 819 qp->sq.wrid = kmalloc_array(qp->sq.wqe_cnt, sizeof(u64),
9afc60dc 820 gfp | __GFP_NOWARN);
0ef2f05c
WW		 821 if (!qp->sq.wrid)
822 qp->sq.wrid = __vmalloc(qp->sq.wqe_cnt * sizeof(u64),
823 gfp, PAGE_KERNEL);
ee370950 824 qp->rq.wrid = kmalloc_array(qp->rq.wqe_cnt, sizeof(u64),
9afc60dc 825 gfp | __GFP_NOWARN);
0ef2f05c
WW		 826 if (!qp->rq.wrid)
827 qp->rq.wrid = __vmalloc(qp->rq.wqe_cnt * sizeof(u64),
828 gfp, PAGE_KERNEL);
225c7b1f
RD		 829 if (!qp->sq.wrid || !qp->rq.wrid) {
830 err = -ENOMEM;
831 goto err_wrid;
832 }
225c7b1f
RD		 833 }
834
a3cdcbfa 835 if (sqpn) {
1ffeb2eb
JM		 836 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
837 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
838 if (alloc_proxy_bufs(pd->device, qp)) {
839 err = -ENOMEM;
840 goto err_wrid;
841 }
842 }
a3cdcbfa 843 } else {
ddae0349
EE		 844 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
845 * otherwise, the WQE BlueFlame setup flow wrongly causes
846 * VLAN insertion. */
3987a2d3 847 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
ddae0349 848 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
d57febe1
MB		 849 (init_attr->cap.max_send_wr ?
850 MLX4_RESERVE_ETH_BF_QP : 0) |
851 (init_attr->cap.max_recv_wr ?
852 MLX4_RESERVE_A0_QP : 0));
3987a2d3 853 else
c1c98501
MB		 854 if (qp->flags & MLX4_IB_QP_NETIF)
855 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
856 else
857 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
ddae0349 858 &qpn, 0);
a3cdcbfa 859 if (err)
1ffeb2eb 860 goto err_proxy;
a3cdcbfa
YP		 861 }
862
fbfb6625
EBE		 863 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
864 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
865
40f2287b 866 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp, gfp);
225c7b1f 867 if (err)
a3cdcbfa 868 goto err_qpn;
225c7b1f 869
0a1405da
SH		 870 if (init_attr->qp_type == IB_QPT_XRC_TGT)
871 qp->mqp.qpn |= (1 << 23);
872
225c7b1f
RD		 873 /*
874 * Hardware wants QPN written in big-endian order (after
875 * shifting) for send doorbell. Precompute this value to save
876 * a little bit when posting sends.
877 */
878 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
879
225c7b1f 880 qp->mqp.event = mlx4_ib_qp_event;
1ffeb2eb
JM		 881 if (!*caller_qp)
882 *caller_qp = qp;
35f05dab
YH		 883
884 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
885 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
886 to_mcq(init_attr->recv_cq));
887 /* Maintain device to QPs access, needed for further handling
888 * via reset flow
889 */
890 list_add_tail(&qp->qps_list, &dev->qp_list);
891 /* Maintain CQ to QPs access, needed for further handling
892 * via reset flow
893 */
894 mcq = to_mcq(init_attr->send_cq);
895 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
896 mcq = to_mcq(init_attr->recv_cq);
897 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
898 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
899 to_mcq(init_attr->recv_cq));
900 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 901 return 0;
902
a3cdcbfa 903err_qpn:
c1c98501
MB		 904 if (!sqpn) {
905 if (qp->flags & MLX4_IB_QP_NETIF)
906 mlx4_ib_steer_qp_free(dev, qpn, 1);
907 else
908 mlx4_qp_release_range(dev->dev, qpn, 1);
909 }
1ffeb2eb
JM		 910err_proxy:
911 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
912 free_proxy_bufs(pd->device, qp);
225c7b1f 913err_wrid:
23f1b384 914 if (pd->uobject) {
0a1405da
SH		 915 if (qp_has_rq(init_attr))
916 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
23f1b384 917 } else {
0ef2f05c
WW		 918 kvfree(qp->sq.wrid);
919 kvfree(qp->rq.wrid);
225c7b1f
RD		 920 }
921
922err_mtt:
923 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
924
925err_buf:
926 if (pd->uobject)
927 ib_umem_release(qp->umem);
928 else
929 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
930
931err_db:
0a1405da 932 if (!pd->uobject && qp_has_rq(init_attr))
6296883c 933 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 934
935err:
1ffeb2eb
JM		 936 if (!*caller_qp)
937 kfree(qp);
225c7b1f
RD		 938 return err;
939}
940
941static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
942{
943 switch (state) {
944 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
945 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
946 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
947 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
948 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
949 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
950 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
951 default: return -1;
952 }
953}
954
955static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 956 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
225c7b1f 957{
338a8fad 958 if (send_cq == recv_cq) {
35f05dab 959 spin_lock(&send_cq->lock);
338a8fad
RD		 960 __acquire(&recv_cq->lock);
961 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
35f05dab 962 spin_lock(&send_cq->lock);
225c7b1f
RD		 963 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
964 } else {
35f05dab 965 spin_lock(&recv_cq->lock);
225c7b1f
RD		 966 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
967 }
968}
969
970static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 971 __releases(&send_cq->lock) __releases(&recv_cq->lock)
225c7b1f 972{
338a8fad
RD		 973 if (send_cq == recv_cq) {
974 __release(&recv_cq->lock);
35f05dab 975 spin_unlock(&send_cq->lock);
338a8fad 976 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
225c7b1f 977 spin_unlock(&recv_cq->lock);
35f05dab 978 spin_unlock(&send_cq->lock);
225c7b1f
RD		 979 } else {
980 spin_unlock(&send_cq->lock);
35f05dab 981 spin_unlock(&recv_cq->lock);
225c7b1f
RD		 982 }
983}
984
fa417f7b
EC		 985static void del_gid_entries(struct mlx4_ib_qp *qp)
986{
987 struct mlx4_ib_gid_entry *ge, *tmp;
988
989 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
990 list_del(&ge->list);
991 kfree(ge);
992 }
993}
994
0a1405da
SH		 995static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
996{
997 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
998 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
999 else
1000 return to_mpd(qp->ibqp.pd);
1001}
1002
1003static void get_cqs(struct mlx4_ib_qp *qp,
1004 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
1005{
1006 switch (qp->ibqp.qp_type) {
1007 case IB_QPT_XRC_TGT:
1008 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
1009 *recv_cq = *send_cq;
1010 break;
1011 case IB_QPT_XRC_INI:
1012 *send_cq = to_mcq(qp->ibqp.send_cq);
1013 *recv_cq = *send_cq;
1014 break;
1015 default:
1016 *send_cq = to_mcq(qp->ibqp.send_cq);
1017 *recv_cq = to_mcq(qp->ibqp.recv_cq);
1018 break;
1019 }
1020}
1021
225c7b1f
RD		 1022static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
1023 int is_user)
1024{
1025 struct mlx4_ib_cq *send_cq, *recv_cq;
35f05dab 1026 unsigned long flags;
225c7b1f 1027
2f5bb473 1028 if (qp->state != IB_QPS_RESET) {
225c7b1f
RD		 1029 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1030 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
987c8f8f 1031 pr_warn("modify QP %06x to RESET failed.\n",
225c7b1f 1032 qp->mqp.qpn);
25476b02 1033 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 1034 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1035 qp->pri.smac = 0;
25476b02 1036 qp->pri.smac_port = 0;
2f5bb473
JM		 1037 }
1038 if (qp->alt.smac) {
1039 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1040 qp->alt.smac = 0;
1041 }
1042 if (qp->pri.vid < 0x1000) {
1043 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1044 qp->pri.vid = 0xFFFF;
1045 qp->pri.candidate_vid = 0xFFFF;
1046 qp->pri.update_vid = 0;
1047 }
1048 if (qp->alt.vid < 0x1000) {
1049 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1050 qp->alt.vid = 0xFFFF;
1051 qp->alt.candidate_vid = 0xFFFF;
1052 qp->alt.update_vid = 0;
1053 }
1054 }
225c7b1f 1055
0a1405da 1056 get_cqs(qp, &send_cq, &recv_cq);
225c7b1f 1057
35f05dab 1058 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1059 mlx4_ib_lock_cqs(send_cq, recv_cq);
1060
35f05dab
YH		 1061 /* del from lists under both locks above to protect reset flow paths */
1062 list_del(&qp->qps_list);
1063 list_del(&qp->cq_send_list);
1064 list_del(&qp->cq_recv_list);
225c7b1f
RD		 1065 if (!is_user) {
1066 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1067 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1068 if (send_cq != recv_cq)
1069 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1070 }
1071
1072 mlx4_qp_remove(dev->dev, &qp->mqp);
1073
1074 mlx4_ib_unlock_cqs(send_cq, recv_cq);
35f05dab 1075 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1076
1077 mlx4_qp_free(dev->dev, &qp->mqp);
a3cdcbfa 1078
c1c98501
MB		 1079 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1080 if (qp->flags & MLX4_IB_QP_NETIF)
1081 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1082 else
1083 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1084 }
a3cdcbfa 1085
225c7b1f
RD		 1086 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1087
1088 if (is_user) {
0a1405da 1089 if (qp->rq.wqe_cnt)
02d89b87
RD		 1090 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
1091 &qp->db);
225c7b1f
RD		 1092 ib_umem_release(qp->umem);
1093 } else {
0ef2f05c
WW		 1094 kvfree(qp->sq.wrid);
1095 kvfree(qp->rq.wrid);
1ffeb2eb
JM		 1096 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1097 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1098 free_proxy_bufs(&dev->ib_dev, qp);
225c7b1f 1099 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
0a1405da 1100 if (qp->rq.wqe_cnt)
6296883c 1101 mlx4_db_free(dev->dev, &qp->db);
225c7b1f 1102 }
fa417f7b
EC		 1103
1104 del_gid_entries(qp);
225c7b1f
RD		 1105}
1106
47605df9
JM		 1107static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1108{
1109 /* Native or PPF */
1110 if (!mlx4_is_mfunc(dev->dev) ||
1111 (mlx4_is_master(dev->dev) &&
1112 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1113 return dev->dev->phys_caps.base_sqpn +
1114 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1115 attr->port_num - 1;
1116 }
1117 /* PF or VF -- creating proxies */
1118 if (attr->qp_type == IB_QPT_SMI)
1119 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1120 else
1121 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1122}
1123
e1b866c6
MS		 1124static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd,
1125 struct ib_qp_init_attr *init_attr,
1126 struct ib_udata *udata)
225c7b1f 1127{
1ffeb2eb 1128 struct mlx4_ib_qp *qp = NULL;
225c7b1f 1129 int err;
fbfb6625 1130 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
0a1405da 1131 u16 xrcdn = 0;
40f2287b 1132 gfp_t gfp;
225c7b1f 1133
40f2287b
JK		 1134 gfp = (init_attr->create_flags & MLX4_IB_QP_CREATE_USE_GFP_NOIO) ?
1135 GFP_NOIO : GFP_KERNEL;
521e575b 1136 /*
1ffeb2eb
JM		 1137 * We only support LSO, vendor flag1, and multicast loopback blocking,
1138 * and only for kernel UD QPs.
521e575b 1139 */
1ffeb2eb
JM		 1140 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1141 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
c1c98501
MB		 1142 MLX4_IB_SRIOV_TUNNEL_QP |
1143 MLX4_IB_SRIOV_SQP |
40f2287b 1144 MLX4_IB_QP_NETIF |
e1b866c6 1145 MLX4_IB_QP_CREATE_ROCE_V2_GSI |
40f2287b 1146 MLX4_IB_QP_CREATE_USE_GFP_NOIO))
b832be1e 1147 return ERR_PTR(-EINVAL);
521e575b 1148
c1c98501
MB		 1149 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1150 if (init_attr->qp_type != IB_QPT_UD)
1151 return ERR_PTR(-EINVAL);
1152 }
1153
e1b866c6
MS		 1154 if (init_attr->create_flags) {
1155 if (udata && init_attr->create_flags & ~(sup_u_create_flags))
1156 return ERR_PTR(-EINVAL);
1157
1158 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
1159 MLX4_IB_QP_CREATE_USE_GFP_NOIO |
1160 MLX4_IB_QP_CREATE_ROCE_V2_GSI |
1161 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) &&
1162 init_attr->qp_type != IB_QPT_UD) ||
1163 (init_attr->create_flags & MLX4_IB_SRIOV_SQP &&
1164 init_attr->qp_type > IB_QPT_GSI) ||
1165 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI &&
1166 init_attr->qp_type != IB_QPT_GSI))
1167 return ERR_PTR(-EINVAL);
1168 }
b846f25a 1169
225c7b1f 1170 switch (init_attr->qp_type) {
0a1405da
SH		 1171 case IB_QPT_XRC_TGT:
1172 pd = to_mxrcd(init_attr->xrcd)->pd;
1173 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1174 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1175 /* fall through */
1176 case IB_QPT_XRC_INI:
1177 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1178 return ERR_PTR(-ENOSYS);
1179 init_attr->recv_cq = init_attr->send_cq;
1180 /* fall through */
225c7b1f
RD		 1181 case IB_QPT_RC:
1182 case IB_QPT_UC:
3987a2d3 1183 case IB_QPT_RAW_PACKET:
40f2287b 1184 qp = kzalloc(sizeof *qp, gfp);
225c7b1f
RD		 1185 if (!qp)
1186 return ERR_PTR(-ENOMEM);
2f5bb473
JM		 1187 qp->pri.vid = 0xFFFF;
1188 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 1189 /* fall through */
1190 case IB_QPT_UD:
1191 {
1192 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
40f2287b 1193 udata, 0, &qp, gfp);
1ffeb2eb 1194 if (err)
225c7b1f 1195 return ERR_PTR(err);
225c7b1f
RD		 1196
1197 qp->ibqp.qp_num = qp->mqp.qpn;
0a1405da 1198 qp->xrcdn = xrcdn;
225c7b1f
RD		 1199
1200 break;
1201 }
1202 case IB_QPT_SMI:
1203 case IB_QPT_GSI:
1204 {
e1b866c6
MS		 1205 int sqpn;
1206
225c7b1f 1207 /* Userspace is not allowed to create special QPs: */
0a1405da 1208 if (udata)
225c7b1f 1209 return ERR_PTR(-EINVAL);
e1b866c6
MS		 1210 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) {
1211 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev, 1, 1, &sqpn, 0);
1212
1213 if (res)
1214 return ERR_PTR(res);
1215 } else {
1216 sqpn = get_sqp_num(to_mdev(pd->device), init_attr);
1217 }
225c7b1f 1218
0a1405da 1219 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
e1b866c6 1220 sqpn,
40f2287b 1221 &qp, gfp);
1ffeb2eb 1222 if (err)
225c7b1f 1223 return ERR_PTR(err);
225c7b1f
RD		 1224
1225 qp->port = init_attr->port_num;
e1b866c6
MS		 1226 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 :
1227 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1;
225c7b1f
RD		 1228 break;
1229 }
1230 default:
1231 /* Don't support raw QPs */
1232 return ERR_PTR(-EINVAL);
1233 }
1234
1235 return &qp->ibqp;
1236}
1237
e1b866c6
MS		 1238struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1239 struct ib_qp_init_attr *init_attr,
1240 struct ib_udata *udata) {
1241 struct ib_device *device = pd ? pd->device : init_attr->xrcd->device;
1242 struct ib_qp *ibqp;
1243 struct mlx4_ib_dev *dev = to_mdev(device);
1244
1245 ibqp = _mlx4_ib_create_qp(pd, init_attr, udata);
1246
1247 if (!IS_ERR(ibqp) &&
1248 (init_attr->qp_type == IB_QPT_GSI) &&
1249 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) {
1250 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp)));
1251 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num);
1252
1253 if (is_eth &&
1254 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
1255 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1256 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr);
1257
1258 if (IS_ERR(sqp->roce_v2_gsi)) {
1259 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi));
1260 sqp->roce_v2_gsi = NULL;
1261 } else {
1262 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi));
1263 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP;
1264 }
1265
1266 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1267 }
1268 }
1269 return ibqp;
1270}
1271
1272static int _mlx4_ib_destroy_qp(struct ib_qp *qp)
225c7b1f
RD		 1273{
1274 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1275 struct mlx4_ib_qp *mqp = to_mqp(qp);
0a1405da 1276 struct mlx4_ib_pd *pd;
225c7b1f
RD		 1277
1278 if (is_qp0(dev, mqp))
1279 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1280
9433c188
MB		 1281 if (dev->qp1_proxy[mqp->port - 1] == mqp) {
1282 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1283 dev->qp1_proxy[mqp->port - 1] = NULL;
1284 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1285 }
1286
7b59f0f9
EBE		 1287 if (mqp->counter_index)
1288 mlx4_ib_free_qp_counter(dev, mqp);
1289
0a1405da
SH		 1290 pd = get_pd(mqp);
1291 destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
225c7b1f
RD		 1292
1293 if (is_sqp(dev, mqp))
1294 kfree(to_msqp(mqp));
1295 else
1296 kfree(mqp);
1297
1298 return 0;
1299}
1300
e1b866c6
MS		 1301int mlx4_ib_destroy_qp(struct ib_qp *qp)
1302{
1303 struct mlx4_ib_qp *mqp = to_mqp(qp);
1304
1305 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
1306 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
1307
1308 if (sqp->roce_v2_gsi)
1309 ib_destroy_qp(sqp->roce_v2_gsi);
1310 }
1311
1312 return _mlx4_ib_destroy_qp(qp);
1313}
1314
1ffeb2eb 1315static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
225c7b1f
RD		 1316{
1317 switch (type) {
1ffeb2eb
JM		 1318 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1319 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1320 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1321 case MLX4_IB_QPT_XRC_INI:
1322 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1323 case MLX4_IB_QPT_SMI:
1324 case MLX4_IB_QPT_GSI:
1325 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1326
1327 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1328 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1329 MLX4_QP_ST_MLX : -1);
1330 case MLX4_IB_QPT_PROXY_SMI:
1331 case MLX4_IB_QPT_TUN_SMI:
1332 case MLX4_IB_QPT_PROXY_GSI:
1333 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1334 MLX4_QP_ST_UD : -1);
1335 default: return -1;
225c7b1f
RD		 1336 }
1337}
1338
65adfa91 1339static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1340 int attr_mask)
1341{
1342 u8 dest_rd_atomic;
1343 u32 access_flags;
1344 u32 hw_access_flags = 0;
1345
1346 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1347 dest_rd_atomic = attr->max_dest_rd_atomic;
1348 else
1349 dest_rd_atomic = qp->resp_depth;
1350
1351 if (attr_mask & IB_QP_ACCESS_FLAGS)
1352 access_flags = attr->qp_access_flags;
1353 else
1354 access_flags = qp->atomic_rd_en;
1355
1356 if (!dest_rd_atomic)
1357 access_flags &= IB_ACCESS_REMOTE_WRITE;
1358
1359 if (access_flags & IB_ACCESS_REMOTE_READ)
1360 hw_access_flags |= MLX4_QP_BIT_RRE;
1361 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1362 hw_access_flags |= MLX4_QP_BIT_RAE;
1363 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1364 hw_access_flags |= MLX4_QP_BIT_RWE;
1365
1366 return cpu_to_be32(hw_access_flags);
1367}
1368
65adfa91 1369static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1370 int attr_mask)
1371{
1372 if (attr_mask & IB_QP_PKEY_INDEX)
1373 sqp->pkey_index = attr->pkey_index;
1374 if (attr_mask & IB_QP_QKEY)
1375 sqp->qkey = attr->qkey;
1376 if (attr_mask & IB_QP_SQ_PSN)
1377 sqp->send_psn = attr->sq_psn;
1378}
1379
1380static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1381{
1382 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1383}
1384
297e0dad
MS		 1385static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1386 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
2f5bb473 1387 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
225c7b1f 1388{
fa417f7b
EC		 1389 int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1390 IB_LINK_LAYER_ETHERNET;
4c3eb3ca 1391 int vidx;
297e0dad 1392 int smac_index;
2f5bb473 1393 int err;
297e0dad 1394
fa417f7b 1395
225c7b1f
RD		 1396 path->grh_mylmc = ah->src_path_bits & 0x7f;
1397 path->rlid = cpu_to_be16(ah->dlid);
1398 if (ah->static_rate) {
1399 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1400 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1401 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1402 --path->static_rate;
1403 } else
1404 path->static_rate = 0;
225c7b1f
RD		 1405
1406 if (ah->ah_flags & IB_AH_GRH) {
5070cd22
MS		 1407 int real_sgid_index = mlx4_ib_gid_index_to_real_index(dev,
1408 port,
1409 ah->grh.sgid_index);
1410
1411 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
987c8f8f 1412 pr_err("sgid_index (%u) too large. max is %d\n",
5070cd22 1413 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
225c7b1f
RD		 1414 return -1;
1415 }
1416
1417 path->grh_mylmc |= 1 << 7;
5070cd22 1418 path->mgid_index = real_sgid_index;
225c7b1f
RD		 1419 path->hop_limit = ah->grh.hop_limit;
1420 path->tclass_flowlabel =
1421 cpu_to_be32((ah->grh.traffic_class << 20) |
1422 (ah->grh.flow_label));
1423 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1424 }
1425
fa417f7b
EC		 1426 if (is_eth) {
1427 if (!(ah->ah_flags & IB_AH_GRH))
1428 return -1;
1429
2f5bb473
JM		 1430 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1431 ((port - 1) << 6) | ((ah->sl & 7) << 3);
4c3eb3ca 1432
297e0dad 1433 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
4c3eb3ca 1434 if (vlan_tag < 0x1000) {
2f5bb473
JM		 1435 if (smac_info->vid < 0x1000) {
1436 /* both valid vlan ids */
1437 if (smac_info->vid != vlan_tag) {
1438 /* different VIDs. unreg old and reg new */
1439 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1440 if (err)
1441 return err;
1442 smac_info->candidate_vid = vlan_tag;
1443 smac_info->candidate_vlan_index = vidx;
1444 smac_info->candidate_vlan_port = port;
1445 smac_info->update_vid = 1;
1446 path->vlan_index = vidx;
1447 } else {
1448 path->vlan_index = smac_info->vlan_index;
1449 }
1450 } else {
1451 /* no current vlan tag in qp */
1452 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1453 if (err)
1454 return err;
1455 smac_info->candidate_vid = vlan_tag;
1456 smac_info->candidate_vlan_index = vidx;
1457 smac_info->candidate_vlan_port = port;
1458 smac_info->update_vid = 1;
1459 path->vlan_index = vidx;
1460 }
297e0dad 1461 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
2f5bb473
JM		 1462 path->fl = 1 << 6;
1463 } else {
1464 /* have current vlan tag. unregister it at modify-qp success */
1465 if (smac_info->vid < 0x1000) {
1466 smac_info->candidate_vid = 0xFFFF;
1467 smac_info->update_vid = 1;
1468 }
4c3eb3ca 1469 }
2f5bb473
JM		 1470
1471 /* get smac_index for RoCE use.
1472 * If no smac was yet assigned, register one.
1473 * If one was already assigned, but the new mac differs,
1474 * unregister the old one and register the new one.
1475 */
25476b02
JM		 1476 if ((!smac_info->smac && !smac_info->smac_port) ||
1477 smac_info->smac != smac) {
2f5bb473
JM		 1478 /* register candidate now, unreg if needed, after success */
1479 smac_index = mlx4_register_mac(dev->dev, port, smac);
1480 if (smac_index >= 0) {
1481 smac_info->candidate_smac_index = smac_index;
1482 smac_info->candidate_smac = smac;
1483 smac_info->candidate_smac_port = port;
1484 } else {
1485 return -EINVAL;
1486 }
1487 } else {
1488 smac_index = smac_info->smac_index;
1489 }
1490
1491 memcpy(path->dmac, ah->dmac, 6);
1492 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1493 /* put MAC table smac index for IBoE */
1494 path->grh_mylmc = (u8) (smac_index) | 0x80;
1495 } else {
4c3eb3ca
EC		 1496 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1497 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
2f5bb473 1498 }
fa417f7b 1499
225c7b1f
RD		 1500 return 0;
1501}
1502
297e0dad
MS		 1503static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1504 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1505 struct mlx4_ib_qp *mqp,
dbf727de
MB		 1506 struct mlx4_qp_path *path, u8 port,
1507 u16 vlan_id, u8 *smac)
297e0dad
MS		 1508{
1509 return _mlx4_set_path(dev, &qp->ah_attr,
dbf727de
MB		 1510 mlx4_mac_to_u64(smac),
1511 vlan_id,
2f5bb473 1512 path, &mqp->pri, port);
297e0dad
MS		 1513}
1514
1515static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1516 const struct ib_qp_attr *qp,
1517 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1518 struct mlx4_ib_qp *mqp,
297e0dad
MS		 1519 struct mlx4_qp_path *path, u8 port)
1520{
1521 return _mlx4_set_path(dev, &qp->alt_ah_attr,
dbf727de
MB		 1522 0,
1523 0xffff,
2f5bb473 1524 path, &mqp->alt, port);
297e0dad
MS		 1525}
1526
fa417f7b
EC		 1527static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1528{
1529 struct mlx4_ib_gid_entry *ge, *tmp;
1530
1531 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1532 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1533 ge->added = 1;
1534 ge->port = qp->port;
1535 }
1536 }
1537}
1538
dbf727de
MB		 1539static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1540 struct mlx4_ib_qp *qp,
2f5bb473
JM		 1541 struct mlx4_qp_context *context)
1542{
2f5bb473
JM		 1543 u64 u64_mac;
1544 int smac_index;
1545
3e0629cb 1546 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
2f5bb473
JM		 1547
1548 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
25476b02 1549 if (!qp->pri.smac && !qp->pri.smac_port) {
2f5bb473
JM		 1550 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1551 if (smac_index >= 0) {
1552 qp->pri.candidate_smac_index = smac_index;
1553 qp->pri.candidate_smac = u64_mac;
1554 qp->pri.candidate_smac_port = qp->port;
1555 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1556 } else {
1557 return -ENOENT;
1558 }
1559 }
1560 return 0;
1561}
1562
7b59f0f9
EBE		 1563static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1564{
1565 struct counter_index *new_counter_index;
1566 int err;
1567 u32 tmp_idx;
1568
1569 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1570 IB_LINK_LAYER_ETHERNET ||
1571 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1572 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1573 return 0;
1574
1575 err = mlx4_counter_alloc(dev->dev, &tmp_idx);
1576 if (err)
1577 return err;
1578
1579 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1580 if (!new_counter_index) {
1581 mlx4_counter_free(dev->dev, tmp_idx);
1582 return -ENOMEM;
1583 }
1584
1585 new_counter_index->index = tmp_idx;
1586 new_counter_index->allocated = 1;
1587 qp->counter_index = new_counter_index;
1588
1589 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1590 list_add_tail(&new_counter_index->list,
1591 &dev->counters_table[qp->port - 1].counters_list);
1592 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
1593
1594 return 0;
1595}
1596
3b5daf28
MS		 1597enum {
1598 MLX4_QPC_ROCE_MODE_1 = 0,
1599 MLX4_QPC_ROCE_MODE_2 = 2,
1600 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff
1601};
1602
1603static u8 gid_type_to_qpc(enum ib_gid_type gid_type)
1604{
1605 switch (gid_type) {
1606 case IB_GID_TYPE_ROCE:
1607 return MLX4_QPC_ROCE_MODE_1;
1608 case IB_GID_TYPE_ROCE_UDP_ENCAP:
1609 return MLX4_QPC_ROCE_MODE_2;
1610 default:
1611 return MLX4_QPC_ROCE_MODE_UNDEFINED;
1612 }
1613}
1614
65adfa91
MT		 1615static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1616 const struct ib_qp_attr *attr, int attr_mask,
1617 enum ib_qp_state cur_state, enum ib_qp_state new_state)
225c7b1f
RD		 1618{
1619 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1620 struct mlx4_ib_qp *qp = to_mqp(ibqp);
0a1405da
SH		 1621 struct mlx4_ib_pd *pd;
1622 struct mlx4_ib_cq *send_cq, *recv_cq;
225c7b1f
RD		 1623 struct mlx4_qp_context *context;
1624 enum mlx4_qp_optpar optpar = 0;
225c7b1f 1625 int sqd_event;
c1c98501 1626 int steer_qp = 0;
225c7b1f 1627 int err = -EINVAL;
3ba8e31d 1628 int counter_index;
225c7b1f 1629
3dec4878
JM		 1630 /* APM is not supported under RoCE */
1631 if (attr_mask & IB_QP_ALT_PATH &&
1632 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1633 IB_LINK_LAYER_ETHERNET)
1634 return -ENOTSUPP;
1635
225c7b1f
RD		 1636 context = kzalloc(sizeof *context, GFP_KERNEL);
1637 if (!context)
1638 return -ENOMEM;
1639
225c7b1f 1640 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1ffeb2eb 1641 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
225c7b1f
RD		 1642
1643 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1644 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1645 else {
1646 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1647 switch (attr->path_mig_state) {
1648 case IB_MIG_MIGRATED:
1649 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1650 break;
1651 case IB_MIG_REARM:
1652 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1653 break;
1654 case IB_MIG_ARMED:
1655 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1656 break;
1657 }
1658 }
1659
b832be1e 1660 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
225c7b1f 1661 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
3987a2d3
OG		 1662 else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1663 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
b832be1e
EC		 1664 else if (ibqp->qp_type == IB_QPT_UD) {
1665 if (qp->flags & MLX4_IB_QP_LSO)
1666 context->mtu_msgmax = (IB_MTU_4096 << 5) |
1667 ilog2(dev->dev->caps.max_gso_sz);
1668 else
6e0d733d 1669 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
b832be1e 1670 } else if (attr_mask & IB_QP_PATH_MTU) {
225c7b1f 1671 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
987c8f8f 1672 pr_err("path MTU (%u) is invalid\n",
225c7b1f 1673 attr->path_mtu);
f5b40431 1674 goto out;
225c7b1f 1675 }
d1f2cd89
EC		 1676 context->mtu_msgmax = (attr->path_mtu << 5) |
1677 ilog2(dev->dev->caps.max_msg_sz);
225c7b1f
RD		 1678 }
1679
0e6e7416
RD		 1680 if (qp->rq.wqe_cnt)
1681 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
225c7b1f
RD		 1682 context->rq_size_stride |= qp->rq.wqe_shift - 4;
1683
0e6e7416
RD		 1684 if (qp->sq.wqe_cnt)
1685 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
225c7b1f
RD		 1686 context->sq_size_stride |= qp->sq.wqe_shift - 4;
1687
7b59f0f9
EBE		 1688 if (new_state == IB_QPS_RESET && qp->counter_index)
1689 mlx4_ib_free_qp_counter(dev, qp);
1690
0a1405da 1691 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0e6e7416 1692 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
0a1405da 1693 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
02d7ef6f
DB		 1694 if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1695 context->param3 |= cpu_to_be32(1 << 30);
0a1405da 1696 }
0e6e7416 1697
225c7b1f 1698 if (qp->ibqp.uobject)
85743f1e
HN		 1699 context->usr_page = cpu_to_be32(
1700 mlx4_to_hw_uar_index(dev->dev,
1701 to_mucontext(ibqp->uobject->context)->uar.index));
225c7b1f 1702 else
85743f1e
HN		 1703 context->usr_page = cpu_to_be32(
1704 mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index));
225c7b1f
RD		 1705
1706 if (attr_mask & IB_QP_DEST_QPN)
1707 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1708
1709 if (attr_mask & IB_QP_PORT) {
1710 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1711 !(attr_mask & IB_QP_AV)) {
1712 mlx4_set_sched(&context->pri_path, attr->port_num);
1713 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1714 }
1715 }
1716
cfcde11c 1717 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
7b59f0f9
EBE		 1718 err = create_qp_lb_counter(dev, qp);
1719 if (err)
1720 goto out;
1721
3ba8e31d
EBE		 1722 counter_index =
1723 dev->counters_table[qp->port - 1].default_counter;
7b59f0f9
EBE		 1724 if (qp->counter_index)
1725 counter_index = qp->counter_index->index;
1726
3ba8e31d
EBE		 1727 if (counter_index != -1) {
1728 context->pri_path.counter_index = counter_index;
cfcde11c 1729 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
7b59f0f9
EBE		 1730 if (qp->counter_index) {
1731 context->pri_path.fl |=
1732 MLX4_FL_ETH_SRC_CHECK_MC_LB;
1733 context->pri_path.vlan_control |=
1734 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
1735 }
cfcde11c 1736 } else
47d8417f
EBE		 1737 context->pri_path.counter_index =
1738 MLX4_SINK_COUNTER_INDEX(dev->dev);
c1c98501
MB		 1739
1740 if (qp->flags & MLX4_IB_QP_NETIF) {
1741 mlx4_ib_steer_qp_reg(dev, qp, 1);
1742 steer_qp = 1;
1743 }
e1b866c6
MS		 1744
1745 if (ibqp->qp_type == IB_QPT_GSI) {
1746 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ?
1747 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE;
1748 u8 qpc_roce_mode = gid_type_to_qpc(gid_type);
1749
1750 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
1751 }
cfcde11c
OG		 1752 }
1753
225c7b1f 1754 if (attr_mask & IB_QP_PKEY_INDEX) {
1ffeb2eb
JM		 1755 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1756 context->pri_path.disable_pkey_check = 0x40;
225c7b1f
RD		 1757 context->pri_path.pkey_index = attr->pkey_index;
1758 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1759 }
1760
225c7b1f 1761 if (attr_mask & IB_QP_AV) {
dbf727de
MB		 1762 u8 port_num = mlx4_is_bonded(to_mdev(ibqp->device)->dev) ? 1 :
1763 attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1764 union ib_gid gid;
1765 struct ib_gid_attr gid_attr;
1766 u16 vlan = 0xffff;
1767 u8 smac[ETH_ALEN];
1768 int status = 0;
3b5daf28
MS		 1769 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
1770 attr->ah_attr.ah_flags & IB_AH_GRH;
dbf727de 1771
3b5daf28 1772 if (is_eth) {
dbf727de
MB		 1773 int index = attr->ah_attr.grh.sgid_index;
1774
1775 status = ib_get_cached_gid(ibqp->device, port_num,
1776 index, &gid, &gid_attr);
1777 if (!status && !memcmp(&gid, &zgid, sizeof(gid)))
1778 status = -ENOENT;
1779 if (!status && gid_attr.ndev) {
1780 vlan = rdma_vlan_dev_vlan_id(gid_attr.ndev);
1781 memcpy(smac, gid_attr.ndev->dev_addr, ETH_ALEN);
1782 dev_put(gid_attr.ndev);
1783 }
1784 }
1785 if (status)
1786 goto out;
1787
2f5bb473 1788 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
dbf727de 1789 port_num, vlan, smac))
225c7b1f 1790 goto out;
225c7b1f
RD		 1791
1792 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1793 MLX4_QP_OPTPAR_SCHED_QUEUE);
3b5daf28
MS		 1794
1795 if (is_eth &&
1796 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) {
1797 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr.gid_type);
1798
1799 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) {
1800 err = -EINVAL;
1801 goto out;
1802 }
1803 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
1804 }
1805
225c7b1f
RD		 1806 }
1807
1808 if (attr_mask & IB_QP_TIMEOUT) {
fa417f7b 1809 context->pri_path.ackto |= attr->timeout << 3;
225c7b1f
RD		 1810 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1811 }
1812
1813 if (attr_mask & IB_QP_ALT_PATH) {
225c7b1f
RD		 1814 if (attr->alt_port_num == 0 ||
1815 attr->alt_port_num > dev->dev->caps.num_ports)
f5b40431 1816 goto out;
225c7b1f 1817
5ae2a7a8
RD		 1818 if (attr->alt_pkey_index >=
1819 dev->dev->caps.pkey_table_len[attr->alt_port_num])
f5b40431 1820 goto out;
5ae2a7a8 1821
2f5bb473
JM		 1822 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
1823 &context->alt_path,
297e0dad 1824 attr->alt_port_num))
f5b40431 1825 goto out;
225c7b1f
RD		 1826
1827 context->alt_path.pkey_index = attr->alt_pkey_index;
1828 context->alt_path.ackto = attr->alt_timeout << 3;
1829 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1830 }
1831
0a1405da
SH		 1832 pd = get_pd(qp);
1833 get_cqs(qp, &send_cq, &recv_cq);
1834 context->pd = cpu_to_be32(pd->pdn);
1835 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1836 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1837 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
57f01b53 1838
95d04f07
RD		 1839 /* Set "fast registration enabled" for all kernel QPs */
1840 if (!qp->ibqp.uobject)
1841 context->params1 |= cpu_to_be32(1 << 11);
1842
57f01b53
JM		 1843 if (attr_mask & IB_QP_RNR_RETRY) {
1844 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1845 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1846 }
1847
225c7b1f
RD		 1848 if (attr_mask & IB_QP_RETRY_CNT) {
1849 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1850 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1851 }
1852
1853 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1854 if (attr->max_rd_atomic)
1855 context->params1 |=
1856 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1857 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1858 }
1859
1860 if (attr_mask & IB_QP_SQ_PSN)
1861 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1862
225c7b1f
RD		 1863 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1864 if (attr->max_dest_rd_atomic)
1865 context->params2 |=
1866 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1867 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1868 }
1869
1870 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1871 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1872 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1873 }
1874
1875 if (ibqp->srq)
1876 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1877
1878 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1879 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1880 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1881 }
1882 if (attr_mask & IB_QP_RQ_PSN)
1883 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1884
1ffeb2eb 1885 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
225c7b1f 1886 if (attr_mask & IB_QP_QKEY) {
1ffeb2eb
JM		 1887 if (qp->mlx4_ib_qp_type &
1888 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1889 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1890 else {
1891 if (mlx4_is_mfunc(dev->dev) &&
1892 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1893 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1894 MLX4_RESERVED_QKEY_BASE) {
1895 pr_err("Cannot use reserved QKEY"
1896 " 0x%x (range 0xffff0000..0xffffffff"
1897 " is reserved)\n", attr->qkey);
1898 err = -EINVAL;
1899 goto out;
1900 }
1901 context->qkey = cpu_to_be32(attr->qkey);
1902 }
225c7b1f
RD		 1903 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1904 }
1905
1906 if (ibqp->srq)
1907 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1908
0a1405da 1909 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
225c7b1f
RD		 1910 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1911
1912 if (cur_state == IB_QPS_INIT &&
1913 new_state == IB_QPS_RTR &&
1914 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
3987a2d3
OG		 1915 ibqp->qp_type == IB_QPT_UD ||
1916 ibqp->qp_type == IB_QPT_RAW_PACKET)) {
225c7b1f 1917 context->pri_path.sched_queue = (qp->port - 1) << 6;
1ffeb2eb
JM		 1918 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1919 qp->mlx4_ib_qp_type &
1920 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
225c7b1f 1921 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1ffeb2eb
JM		 1922 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1923 context->pri_path.fl = 0x80;
1924 } else {
1925 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1926 context->pri_path.fl = 0x80;
225c7b1f 1927 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1ffeb2eb 1928 }
2f5bb473
JM		 1929 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1930 IB_LINK_LAYER_ETHERNET) {
1931 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
1932 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
1933 context->pri_path.feup = 1 << 7; /* don't fsm */
1934 /* handle smac_index */
1935 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
1936 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
1937 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
dbf727de 1938 err = handle_eth_ud_smac_index(dev, qp, context);
bede98e7
MD		 1939 if (err) {
1940 err = -EINVAL;
1941 goto out;
1942 }
9433c188
MB		 1943 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1944 dev->qp1_proxy[qp->port - 1] = qp;
2f5bb473
JM		 1945 }
1946 }
225c7b1f
RD		 1947 }
1948
d2fce8a9 1949 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
3528f696
EC		 1950 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1951 MLX4_IB_LINK_TYPE_ETH;
d2fce8a9
OG		 1952 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1953 /* set QP to receive both tunneled & non-tunneled packets */
8e1a03b6 1954 if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET)))
d2fce8a9
OG		 1955 context->srqn = cpu_to_be32(7 << 28);
1956 }
1957 }
3528f696 1958
297e0dad
MS		 1959 if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1960 int is_eth = rdma_port_get_link_layer(
1961 &dev->ib_dev, qp->port) ==
1962 IB_LINK_LAYER_ETHERNET;
1963 if (is_eth) {
1964 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1965 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1966 }
1967 }
1968
1969
225c7b1f
RD		 1970 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
1971 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1972 sqd_event = 1;
1973 else
1974 sqd_event = 0;
1975
d57f5f72 1976 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3b5daf28 1977 context->rlkey_roce_mode |= (1 << 4);
d57f5f72 1978
c0be5fb5
EC		 1979 /*
1980 * Before passing a kernel QP to the HW, make sure that the
0e6e7416
RD		 1981 * ownership bits of the send queue are set and the SQ
1982 * headroom is stamped so that the hardware doesn't start
1983 * processing stale work requests.
c0be5fb5
EC		 1984 */
1985 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1986 struct mlx4_wqe_ctrl_seg *ctrl;
1987 int i;
1988
0e6e7416 1989 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
c0be5fb5
EC		 1990 ctrl = get_send_wqe(qp, i);
1991 ctrl->owner_opcode = cpu_to_be32(1 << 31);
9670e553
EC		 1992 if (qp->sq_max_wqes_per_wr == 1)
1993 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
0e6e7416 1994
ea54b10c 1995 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
c0be5fb5
EC		 1996 }
1997 }
1998
225c7b1f
RD		 1999 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
2000 to_mlx4_state(new_state), context, optpar,
2001 sqd_event, &qp->mqp);
2002 if (err)
2003 goto out;
2004
2005 qp->state = new_state;
2006
2007 if (attr_mask & IB_QP_ACCESS_FLAGS)
2008 qp->atomic_rd_en = attr->qp_access_flags;
2009 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2010 qp->resp_depth = attr->max_dest_rd_atomic;
fa417f7b 2011 if (attr_mask & IB_QP_PORT) {
225c7b1f 2012 qp->port = attr->port_num;
fa417f7b
EC		 2013 update_mcg_macs(dev, qp);
2014 }
225c7b1f
RD		 2015 if (attr_mask & IB_QP_ALT_PATH)
2016 qp->alt_port = attr->alt_port_num;
2017
2018 if (is_sqp(dev, qp))
2019 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
2020
2021 /*
2022 * If we moved QP0 to RTR, bring the IB link up; if we moved
2023 * QP0 to RESET or ERROR, bring the link back down.
2024 */
2025 if (is_qp0(dev, qp)) {
2026 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
5ae2a7a8 2027 if (mlx4_INIT_PORT(dev->dev, qp->port))
987c8f8f 2028 pr_warn("INIT_PORT failed for port %d\n",
5ae2a7a8 2029 qp->port);
225c7b1f
RD		 2030
2031 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2032 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
2033 mlx4_CLOSE_PORT(dev->dev, qp->port);
2034 }
2035
2036 /*
2037 * If we moved a kernel QP to RESET, clean up all old CQ
2038 * entries and reinitialize the QP.
2039 */
2f5bb473
JM		 2040 if (new_state == IB_QPS_RESET) {
2041 if (!ibqp->uobject) {
2042 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
2043 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2044 if (send_cq != recv_cq)
2045 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
2046
2047 qp->rq.head = 0;
2048 qp->rq.tail = 0;
2049 qp->sq.head = 0;
2050 qp->sq.tail = 0;
2051 qp->sq_next_wqe = 0;
2052 if (qp->rq.wqe_cnt)
2053 *qp->db.db = 0;
225c7b1f 2054
2f5bb473
JM		 2055 if (qp->flags & MLX4_IB_QP_NETIF)
2056 mlx4_ib_steer_qp_reg(dev, qp, 0);
2057 }
25476b02 2058 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 2059 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2060 qp->pri.smac = 0;
25476b02 2061 qp->pri.smac_port = 0;
2f5bb473
JM		 2062 }
2063 if (qp->alt.smac) {
2064 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2065 qp->alt.smac = 0;
2066 }
2067 if (qp->pri.vid < 0x1000) {
2068 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
2069 qp->pri.vid = 0xFFFF;
2070 qp->pri.candidate_vid = 0xFFFF;
2071 qp->pri.update_vid = 0;
2072 }
c1c98501 2073
2f5bb473
JM		 2074 if (qp->alt.vid < 0x1000) {
2075 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
2076 qp->alt.vid = 0xFFFF;
2077 qp->alt.candidate_vid = 0xFFFF;
2078 qp->alt.update_vid = 0;
2079 }
225c7b1f 2080 }
225c7b1f 2081out:
7b59f0f9
EBE		 2082 if (err && qp->counter_index)
2083 mlx4_ib_free_qp_counter(dev, qp);
c1c98501
MB		 2084 if (err && steer_qp)
2085 mlx4_ib_steer_qp_reg(dev, qp, 0);
225c7b1f 2086 kfree(context);
25476b02
JM		 2087 if (qp->pri.candidate_smac ||
2088 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2f5bb473
JM		 2089 if (err) {
2090 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
2091 } else {
25476b02 2092 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2f5bb473
JM		 2093 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2094 qp->pri.smac = qp->pri.candidate_smac;
2095 qp->pri.smac_index = qp->pri.candidate_smac_index;
2096 qp->pri.smac_port = qp->pri.candidate_smac_port;
2097 }
2098 qp->pri.candidate_smac = 0;
2099 qp->pri.candidate_smac_index = 0;
2100 qp->pri.candidate_smac_port = 0;
2101 }
2102 if (qp->alt.candidate_smac) {
2103 if (err) {
2104 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
2105 } else {
2106 if (qp->alt.smac)
2107 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2108 qp->alt.smac = qp->alt.candidate_smac;
2109 qp->alt.smac_index = qp->alt.candidate_smac_index;
2110 qp->alt.smac_port = qp->alt.candidate_smac_port;
2111 }
2112 qp->alt.candidate_smac = 0;
2113 qp->alt.candidate_smac_index = 0;
2114 qp->alt.candidate_smac_port = 0;
2115 }
2116
2117 if (qp->pri.update_vid) {
2118 if (err) {
2119 if (qp->pri.candidate_vid < 0x1000)
2120 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
2121 qp->pri.candidate_vid);
2122 } else {
2123 if (qp->pri.vid < 0x1000)
2124 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2125 qp->pri.vid);
2126 qp->pri.vid = qp->pri.candidate_vid;
2127 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2128 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
2129 }
2130 qp->pri.candidate_vid = 0xFFFF;
2131 qp->pri.update_vid = 0;
2132 }
2133
2134 if (qp->alt.update_vid) {
2135 if (err) {
2136 if (qp->alt.candidate_vid < 0x1000)
2137 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2138 qp->alt.candidate_vid);
2139 } else {
2140 if (qp->alt.vid < 0x1000)
2141 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2142 qp->alt.vid);
2143 qp->alt.vid = qp->alt.candidate_vid;
2144 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2145 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
2146 }
2147 qp->alt.candidate_vid = 0xFFFF;
2148 qp->alt.update_vid = 0;
2149 }
2150
225c7b1f
RD		 2151 return err;
2152}
2153
e1b866c6
MS		 2154static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2155 int attr_mask, struct ib_udata *udata)
65adfa91
MT		 2156{
2157 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2158 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2159 enum ib_qp_state cur_state, new_state;
2160 int err = -EINVAL;
297e0dad 2161 int ll;
65adfa91
MT		 2162 mutex_lock(&qp->mutex);
2163
2164 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2165 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2166
297e0dad
MS		 2167 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2168 ll = IB_LINK_LAYER_UNSPECIFIED;
2169 } else {
2170 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2171 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2172 }
dd5f03be
MB		 2173
2174 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
297e0dad 2175 attr_mask, ll)) {
b1d8eb5a
JM		 2176 pr_debug("qpn 0x%x: invalid attribute mask specified "
2177 "for transition %d to %d. qp_type %d,"
2178 " attr_mask 0x%x\n",
2179 ibqp->qp_num, cur_state, new_state,
2180 ibqp->qp_type, attr_mask);
65adfa91 2181 goto out;
b1d8eb5a 2182 }
65adfa91 2183
c6215745
MS		 2184 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2185 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2186 if ((ibqp->qp_type == IB_QPT_RC) ||
2187 (ibqp->qp_type == IB_QPT_UD) ||
2188 (ibqp->qp_type == IB_QPT_UC) ||
2189 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2190 (ibqp->qp_type == IB_QPT_XRC_INI)) {
2191 attr->port_num = mlx4_ib_bond_next_port(dev);
2192 }
2193 } else {
2194 /* no sense in changing port_num
2195 * when ports are bonded */
2196 attr_mask &= ~IB_QP_PORT;
2197 }
2198 }
2199
65adfa91 2200 if ((attr_mask & IB_QP_PORT) &&
1ffeb2eb 2201 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
b1d8eb5a
JM		 2202 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2203 "for transition %d to %d. qp_type %d\n",
2204 ibqp->qp_num, attr->port_num, cur_state,
2205 new_state, ibqp->qp_type);
65adfa91
MT		 2206 goto out;
2207 }
2208
3987a2d3
OG		 2209 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2210 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2211 IB_LINK_LAYER_ETHERNET))
2212 goto out;
2213
5ae2a7a8
RD		 2214 if (attr_mask & IB_QP_PKEY_INDEX) {
2215 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
b1d8eb5a
JM		 2216 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2217 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2218 "for transition %d to %d. qp_type %d\n",
2219 ibqp->qp_num, attr->pkey_index, cur_state,
2220 new_state, ibqp->qp_type);
5ae2a7a8 2221 goto out;
b1d8eb5a 2222 }
5ae2a7a8
RD		 2223 }
2224
65adfa91
MT		 2225 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2226 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
b1d8eb5a
JM		 2227 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2228 "Transition %d to %d. qp_type %d\n",
2229 ibqp->qp_num, attr->max_rd_atomic, cur_state,
2230 new_state, ibqp->qp_type);
65adfa91
MT		 2231 goto out;
2232 }
2233
2234 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2235 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
b1d8eb5a
JM		 2236 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2237 "Transition %d to %d. qp_type %d\n",
2238 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2239 new_state, ibqp->qp_type);
65adfa91
MT		 2240 goto out;
2241 }
2242
2243 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2244 err = 0;
2245 goto out;
2246 }
2247
65adfa91
MT		 2248 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2249
c6215745
MS		 2250 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2251 attr->port_num = 1;
2252
65adfa91
MT		 2253out:
2254 mutex_unlock(&qp->mutex);
2255 return err;
2256}
2257
e1b866c6
MS		 2258int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2259 int attr_mask, struct ib_udata *udata)
2260{
2261 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2262 int ret;
2263
2264 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata);
2265
2266 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2267 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
2268 int err = 0;
2269
2270 if (sqp->roce_v2_gsi)
2271 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask);
2272 if (err)
2273 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n",
2274 err);
2275 }
2276 return ret;
2277}
2278
99ec41d0
JM		 2279static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2280{
2281 int i;
2282 for (i = 0; i < dev->caps.num_ports; i++) {
2283 if (qpn == dev->caps.qp0_proxy[i] ||
2284 qpn == dev->caps.qp0_tunnel[i]) {
2285 *qkey = dev->caps.qp0_qkey[i];
2286 return 0;
2287 }
2288 }
2289 return -EINVAL;
2290}
2291
1ffeb2eb 2292static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
e622f2f4 2293 struct ib_ud_wr *wr,
1ffeb2eb
JM		 2294 void *wqe, unsigned *mlx_seg_len)
2295{
2296 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2297 struct ib_device *ib_dev = &mdev->ib_dev;
2298 struct mlx4_wqe_mlx_seg *mlx = wqe;
2299 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2300 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 2301 u16 pkey;
2302 u32 qkey;
2303 int send_size;
2304 int header_size;
2305 int spc;
2306 int i;
2307
e622f2f4 2308 if (wr->wr.opcode != IB_WR_SEND)
1ffeb2eb
JM		 2309 return -EINVAL;
2310
2311 send_size = 0;
2312
e622f2f4
CH		 2313 for (i = 0; i < wr->wr.num_sge; ++i)
2314 send_size += wr->wr.sg_list[i].length;
1ffeb2eb
JM		 2315
2316 /* for proxy-qp0 sends, need to add in size of tunnel header */
2317 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2318 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2319 send_size += sizeof (struct mlx4_ib_tunnel_header);
2320
25f40220 2321 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
1ffeb2eb
JM		 2322
2323 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2324 sqp->ud_header.lrh.service_level =
2325 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2326 sqp->ud_header.lrh.destination_lid =
2327 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2328 sqp->ud_header.lrh.source_lid =
2329 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2330 }
2331
2332 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2333
2334 /* force loopback */
2335 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2336 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2337
2338 sqp->ud_header.lrh.virtual_lane = 0;
e622f2f4 2339 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
1ffeb2eb
JM		 2340 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2341 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2342 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
e622f2f4 2343 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
1ffeb2eb
JM		 2344 else
2345 sqp->ud_header.bth.destination_qpn =
47605df9 2346 cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
1ffeb2eb
JM		 2347
2348 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
99ec41d0
JM		 2349 if (mlx4_is_master(mdev->dev)) {
2350 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2351 return -EINVAL;
2352 } else {
2353 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2354 return -EINVAL;
2355 }
1ffeb2eb
JM		 2356 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2357 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2358
2359 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2360 sqp->ud_header.immediate_present = 0;
2361
2362 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2363
2364 /*
2365 * Inline data segments may not cross a 64 byte boundary. If
2366 * our UD header is bigger than the space available up to the
2367 * next 64 byte boundary in the WQE, use two inline data
2368 * segments to hold the UD header.
2369 */
2370 spc = MLX4_INLINE_ALIGN -
2371 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2372 if (header_size <= spc) {
2373 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2374 memcpy(inl + 1, sqp->header_buf, header_size);
2375 i = 1;
2376 } else {
2377 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2378 memcpy(inl + 1, sqp->header_buf, spc);
2379
2380 inl = (void *) (inl + 1) + spc;
2381 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2382 /*
2383 * Need a barrier here to make sure all the data is
2384 * visible before the byte_count field is set.
2385 * Otherwise the HCA prefetcher could grab the 64-byte
2386 * chunk with this inline segment and get a valid (!=
2387 * 0xffffffff) byte count but stale data, and end up
2388 * generating a packet with bad headers.
2389 *
2390 * The first inline segment's byte_count field doesn't
2391 * need a barrier, because it comes after a
2392 * control/MLX segment and therefore is at an offset
2393 * of 16 mod 64.
2394 */
2395 wmb();
2396 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2397 i = 2;
2398 }
2399
2400 *mlx_seg_len =
2401 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2402 return 0;
2403}
2404
3ef967a4 2405#define MLX4_ROCEV2_QP1_SPORT 0xC000
e622f2f4 2406static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_ud_wr *wr,
f438000f 2407 void *wqe, unsigned *mlx_seg_len)
225c7b1f 2408{
a478868a 2409 struct ib_device *ib_dev = sqp->qp.ibqp.device;
225c7b1f 2410 struct mlx4_wqe_mlx_seg *mlx = wqe;
6ee51a4e 2411 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
225c7b1f 2412 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2413 struct mlx4_ib_ah *ah = to_mah(wr->ah);
4c3eb3ca 2414 union ib_gid sgid;
225c7b1f
RD		 2415 u16 pkey;
2416 int send_size;
2417 int header_size;
e61ef241 2418 int spc;
225c7b1f 2419 int i;
1ffeb2eb 2420 int err = 0;
57d88cff 2421 u16 vlan = 0xffff;
a29bec12
RD		 2422 bool is_eth;
2423 bool is_vlan = false;
2424 bool is_grh;
3ef967a4
MS		 2425 bool is_udp = false;
2426 int ip_version = 0;
225c7b1f
RD		 2427
2428 send_size = 0;
e622f2f4
CH		 2429 for (i = 0; i < wr->wr.num_sge; ++i)
2430 send_size += wr->wr.sg_list[i].length;
225c7b1f 2431
fa417f7b
EC		 2432 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2433 is_grh = mlx4_ib_ah_grh_present(ah);
4c3eb3ca 2434 if (is_eth) {
3ef967a4
MS		 2435 struct ib_gid_attr gid_attr;
2436
1ffeb2eb
JM		 2437 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2438 /* When multi-function is enabled, the ib_core gid
2439 * indexes don't necessarily match the hw ones, so
2440 * we must use our own cache */
6ee51a4e
JM		 2441 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2442 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2443 ah->av.ib.gid_index, &sgid.raw[0]);
2444 if (err)
2445 return err;
1ffeb2eb
JM		 2446 } else {
2447 err = ib_get_cached_gid(ib_dev,
2448 be32_to_cpu(ah->av.ib.port_pd) >> 24,
55ee3ab2 2449 ah->av.ib.gid_index, &sgid,
3ef967a4
MS		 2450 &gid_attr);
2451 if (!err) {
2452 if (gid_attr.ndev)
2453 dev_put(gid_attr.ndev);
2454 if (!memcmp(&sgid, &zgid, sizeof(sgid)))
2455 err = -ENOENT;
2456 }
2457 if (!err) {
2458 is_udp = gid_attr.gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
2459 if (is_udp) {
2460 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid))
2461 ip_version = 4;
2462 else
2463 ip_version = 6;
2464 is_grh = false;
2465 }
2466 } else {
1ffeb2eb 2467 return err;
3ef967a4 2468 }
1ffeb2eb 2469 }
0e9855db 2470 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
297e0dad
MS		 2471 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2472 is_vlan = 1;
2473 }
4c3eb3ca 2474 }
25f40220 2475 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
3ef967a4 2476 ip_version, is_udp, 0, &sqp->ud_header);
25f40220
MS		 2477 if (err)
2478 return err;
fa417f7b
EC		 2479
2480 if (!is_eth) {
2481 sqp->ud_header.lrh.service_level =
2482 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2483 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
2484 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2485 }
225c7b1f 2486
3ef967a4 2487 if (is_grh || (ip_version == 6)) {
225c7b1f 2488 sqp->ud_header.grh.traffic_class =
fa417f7b 2489 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
225c7b1f 2490 sqp->ud_header.grh.flow_label =
fa417f7b
EC		 2491 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
2492 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
6ee51a4e
JM		 2493 if (is_eth)
2494 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
2495 else {
1ffeb2eb
JM		 2496 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2497 /* When multi-function is enabled, the ib_core gid
2498 * indexes don't necessarily match the hw ones, so
2499 * we must use our own cache */
2500 sqp->ud_header.grh.source_gid.global.subnet_prefix =
2501 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2502 subnet_prefix;
2503 sqp->ud_header.grh.source_gid.global.interface_id =
2504 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2505 guid_cache[ah->av.ib.gid_index];
2506 } else
2507 ib_get_cached_gid(ib_dev,
2508 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2509 ah->av.ib.gid_index,
55ee3ab2 2510 &sqp->ud_header.grh.source_gid, NULL);
6ee51a4e 2511 }
225c7b1f 2512 memcpy(sqp->ud_header.grh.destination_gid.raw,
fa417f7b 2513 ah->av.ib.dgid, 16);
225c7b1f
RD		 2514 }
2515
3ef967a4
MS		 2516 if (ip_version == 4) {
2517 sqp->ud_header.ip4.tos =
2518 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
2519 sqp->ud_header.ip4.id = 0;
2520 sqp->ud_header.ip4.frag_off = htons(IP_DF);
2521 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit;
2522
2523 memcpy(&sqp->ud_header.ip4.saddr,
2524 sgid.raw + 12, 4);
2525 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4);
2526 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header);
2527 }
2528
2529 if (is_udp) {
2530 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT);
2531 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT);
2532 sqp->ud_header.udp.csum = 0;
2533 }
2534
225c7b1f 2535 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
fa417f7b
EC		 2536
2537 if (!is_eth) {
2538 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
2539 (sqp->ud_header.lrh.destination_lid ==
2540 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
2541 (sqp->ud_header.lrh.service_level << 8));
1ffeb2eb
JM		 2542 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
2543 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
fa417f7b
EC		 2544 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2545 }
225c7b1f 2546
e622f2f4 2547 switch (wr->wr.opcode) {
225c7b1f
RD		 2548 case IB_WR_SEND:
2549 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2550 sqp->ud_header.immediate_present = 0;
2551 break;
2552 case IB_WR_SEND_WITH_IMM:
2553 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2554 sqp->ud_header.immediate_present = 1;
e622f2f4 2555 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
225c7b1f
RD		 2556 break;
2557 default:
2558 return -EINVAL;
2559 }
2560
fa417f7b 2561 if (is_eth) {
6ee51a4e 2562 struct in6_addr in6;
3ef967a4 2563 u16 ether_type;
c0c1d3d7
OD		 2564 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
2565
3ef967a4
MS		 2566 ether_type = (!is_udp) ? MLX4_IB_IBOE_ETHERTYPE :
2567 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6);
2568
c0c1d3d7 2569 mlx->sched_prio = cpu_to_be16(pcp);
fa417f7b 2570
1049f138 2571 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);
fa417f7b 2572 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
6ee51a4e
JM		 2573 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
2574 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
2575 memcpy(&in6, sgid.raw, sizeof(in6));
5ea8bbfc 2576
3e0629cb 2577
fa417f7b
EC		 2578 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
2579 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
4c3eb3ca 2580 if (!is_vlan) {
3ef967a4 2581 sqp->ud_header.eth.type = cpu_to_be16(ether_type);
4c3eb3ca 2582 } else {
3ef967a4 2583 sqp->ud_header.vlan.type = cpu_to_be16(ether_type);
4c3eb3ca
EC		 2584 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
2585 }
fa417f7b
EC		 2586 } else {
2587 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
2588 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
2589 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
2590 }
e622f2f4 2591 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
225c7b1f
RD		 2592 if (!sqp->qp.ibqp.qp_num)
2593 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
2594 else
e622f2f4 2595 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index, &pkey);
225c7b1f 2596 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
e622f2f4 2597 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
225c7b1f 2598 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
e622f2f4
CH		 2599 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
2600 sqp->qkey : wr->remote_qkey);
225c7b1f
RD		 2601 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
2602
2603 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2604
2605 if (0) {
987c8f8f 2606 pr_err("built UD header of size %d:\n", header_size);
225c7b1f
RD		 2607 for (i = 0; i < header_size / 4; ++i) {
2608 if (i % 8 == 0)
987c8f8f
SP		 2609 pr_err(" [%02x] ", i * 4);
2610 pr_cont(" %08x",
2611 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
225c7b1f 2612 if ((i + 1) % 8 == 0)
987c8f8f 2613 pr_cont("\n");
225c7b1f 2614 }
987c8f8f 2615 pr_err("\n");
225c7b1f
RD		 2616 }
2617
e61ef241
RD		 2618 /*
2619 * Inline data segments may not cross a 64 byte boundary. If
2620 * our UD header is bigger than the space available up to the
2621 * next 64 byte boundary in the WQE, use two inline data
2622 * segments to hold the UD header.
2623 */
2624 spc = MLX4_INLINE_ALIGN -
2625 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2626 if (header_size <= spc) {
2627 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2628 memcpy(inl + 1, sqp->header_buf, header_size);
2629 i = 1;
2630 } else {
2631 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2632 memcpy(inl + 1, sqp->header_buf, spc);
2633
2634 inl = (void *) (inl + 1) + spc;
2635 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2636 /*
2637 * Need a barrier here to make sure all the data is
2638 * visible before the byte_count field is set.
2639 * Otherwise the HCA prefetcher could grab the 64-byte
2640 * chunk with this inline segment and get a valid (!=
2641 * 0xffffffff) byte count but stale data, and end up
2642 * generating a packet with bad headers.
2643 *
2644 * The first inline segment's byte_count field doesn't
2645 * need a barrier, because it comes after a
2646 * control/MLX segment and therefore is at an offset
2647 * of 16 mod 64.
2648 */
2649 wmb();
2650 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2651 i = 2;
2652 }
225c7b1f 2653
f438000f
RD		 2654 *mlx_seg_len =
2655 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2656 return 0;
225c7b1f
RD		 2657}
2658
2659static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2660{
2661 unsigned cur;
2662 struct mlx4_ib_cq *cq;
2663
2664 cur = wq->head - wq->tail;
0e6e7416 2665 if (likely(cur + nreq < wq->max_post))
225c7b1f
RD		 2666 return 0;
2667
2668 cq = to_mcq(ib_cq);
2669 spin_lock(&cq->lock);
2670 cur = wq->head - wq->tail;
2671 spin_unlock(&cq->lock);
2672
0e6e7416 2673 return cur + nreq >= wq->max_post;
225c7b1f
RD		 2674}
2675
95d04f07
RD		 2676static __be32 convert_access(int acc)
2677{
6ff63e19
SM		 2678 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2679 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
2680 (acc & IB_ACCESS_REMOTE_WRITE ?
2681 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2682 (acc & IB_ACCESS_REMOTE_READ ?
2683 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
95d04f07
RD		 2684 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
2685 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2686}
2687
1b2cd0fc
SG		 2688static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
2689 struct ib_reg_wr *wr)
2690{
2691 struct mlx4_ib_mr *mr = to_mmr(wr->mr);
2692
2693 fseg->flags = convert_access(wr->access);
2694 fseg->mem_key = cpu_to_be32(wr->key);
2695 fseg->buf_list = cpu_to_be64(mr->page_map);
2696 fseg->start_addr = cpu_to_be64(mr->ibmr.iova);
2697 fseg->reg_len = cpu_to_be64(mr->ibmr.length);
2698 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
2699 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size));
2700 fseg->reserved[0] = 0;
2701 fseg->reserved[1] = 0;
2702}
2703
95d04f07
RD		 2704static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2705{
aee38fad
SM		 2706 memset(iseg, 0, sizeof(*iseg));
2707 iseg->mem_key = cpu_to_be32(rkey);
95d04f07
RD		 2708}
2709
0fbfa6a9
RD		 2710static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2711 u64 remote_addr, u32 rkey)
2712{
2713 rseg->raddr = cpu_to_be64(remote_addr);
2714 rseg->rkey = cpu_to_be32(rkey);
2715 rseg->reserved = 0;
2716}
2717
e622f2f4
CH		 2718static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
2719 struct ib_atomic_wr *wr)
0fbfa6a9 2720{
e622f2f4
CH		 2721 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2722 aseg->swap_add = cpu_to_be64(wr->swap);
2723 aseg->compare = cpu_to_be64(wr->compare_add);
2724 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2725 aseg->swap_add = cpu_to_be64(wr->compare_add);
2726 aseg->compare = cpu_to_be64(wr->compare_add_mask);
0fbfa6a9 2727 } else {
e622f2f4 2728 aseg->swap_add = cpu_to_be64(wr->compare_add);
0fbfa6a9
RD		 2729 aseg->compare = 0;
2730 }
2731
2732}
2733
6fa8f719 2734static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
e622f2f4 2735 struct ib_atomic_wr *wr)
6fa8f719 2736{
e622f2f4
CH		 2737 aseg->swap_add = cpu_to_be64(wr->swap);
2738 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask);
2739 aseg->compare = cpu_to_be64(wr->compare_add);
2740 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask);
6fa8f719
VS		 2741}
2742
0fbfa6a9 2743static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
e622f2f4 2744 struct ib_ud_wr *wr)
0fbfa6a9 2745{
e622f2f4
CH		 2746 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
2747 dseg->dqpn = cpu_to_be32(wr->remote_qpn);
2748 dseg->qkey = cpu_to_be32(wr->remote_qkey);
2749 dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
2750 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
0fbfa6a9
RD		 2751}
2752
1ffeb2eb
JM		 2753static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2754 struct mlx4_wqe_datagram_seg *dseg,
e622f2f4 2755 struct ib_ud_wr *wr,
97982f5a 2756 enum mlx4_ib_qp_type qpt)
1ffeb2eb 2757{
e622f2f4 2758 union mlx4_ext_av *av = &to_mah(wr->ah)->av;
1ffeb2eb
JM		 2759 struct mlx4_av sqp_av = {0};
2760 int port = *((u8 *) &av->ib.port_pd) & 0x3;
2761
2762 /* force loopback */
2763 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2764 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2765 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2766 cpu_to_be32(0xf0000000);
2767
2768 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
97982f5a
JM		 2769 if (qpt == MLX4_IB_QPT_PROXY_GSI)
2770 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2771 else
2772 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]);
47605df9
JM		 2773 /* Use QKEY from the QP context, which is set by master */
2774 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1ffeb2eb
JM		 2775}
2776
e622f2f4 2777static void build_tunnel_header(struct ib_ud_wr *wr, void *wqe, unsigned *mlx_seg_len)
1ffeb2eb
JM		 2778{
2779 struct mlx4_wqe_inline_seg *inl = wqe;
2780 struct mlx4_ib_tunnel_header hdr;
e622f2f4 2781 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 2782 int spc;
2783 int i;
2784
2785 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
e622f2f4
CH		 2786 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
2787 hdr.pkey_index = cpu_to_be16(wr->pkey_index);
2788 hdr.qkey = cpu_to_be32(wr->remote_qkey);
5ea8bbfc
JM		 2789 memcpy(hdr.mac, ah->av.eth.mac, 6);
2790 hdr.vlan = ah->av.eth.vlan;
1ffeb2eb
JM		 2791
2792 spc = MLX4_INLINE_ALIGN -
2793 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2794 if (sizeof (hdr) <= spc) {
2795 memcpy(inl + 1, &hdr, sizeof (hdr));
2796 wmb();
2797 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2798 i = 1;
2799 } else {
2800 memcpy(inl + 1, &hdr, spc);
2801 wmb();
2802 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2803
2804 inl = (void *) (inl + 1) + spc;
2805 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2806 wmb();
2807 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2808 i = 2;
2809 }
2810
2811 *mlx_seg_len =
2812 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2813}
2814
6e694ea3
JM		 2815static void set_mlx_icrc_seg(void *dseg)
2816{
2817 u32 *t = dseg;
2818 struct mlx4_wqe_inline_seg *iseg = dseg;
2819
2820 t[1] = 0;
2821
2822 /*
2823 * Need a barrier here before writing the byte_count field to
2824 * make sure that all the data is visible before the
2825 * byte_count field is set. Otherwise, if the segment begins
2826 * a new cacheline, the HCA prefetcher could grab the 64-byte
2827 * chunk and get a valid (!= * 0xffffffff) byte count but
2828 * stale data, and end up sending the wrong data.
2829 */
2830 wmb();
2831
2832 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2833}
2834
2835static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
d420d9e3 2836{
d420d9e3
RD		 2837 dseg->lkey = cpu_to_be32(sg->lkey);
2838 dseg->addr = cpu_to_be64(sg->addr);
6e694ea3
JM		 2839
2840 /*
2841 * Need a barrier here before writing the byte_count field to
2842 * make sure that all the data is visible before the
2843 * byte_count field is set. Otherwise, if the segment begins
2844 * a new cacheline, the HCA prefetcher could grab the 64-byte
2845 * chunk and get a valid (!= * 0xffffffff) byte count but
2846 * stale data, and end up sending the wrong data.
2847 */
2848 wmb();
2849
2850 dseg->byte_count = cpu_to_be32(sg->length);
d420d9e3
RD		 2851}
2852
2242fa4f
RD		 2853static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2854{
2855 dseg->byte_count = cpu_to_be32(sg->length);
2856 dseg->lkey = cpu_to_be32(sg->lkey);
2857 dseg->addr = cpu_to_be64(sg->addr);
2858}
2859
e622f2f4 2860static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_ud_wr *wr,
0fd7e1d8 2861 struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
417608c2 2862 __be32 *lso_hdr_sz, __be32 *blh)
b832be1e 2863{
e622f2f4 2864 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
b832be1e 2865
417608c2
EC		 2866 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2867 *blh = cpu_to_be32(1 << 6);
b832be1e
EC		 2868
2869 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
e622f2f4 2870 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
b832be1e
EC		 2871 return -EINVAL;
2872
e622f2f4 2873 memcpy(wqe->header, wr->header, wr->hlen);
b832be1e 2874
e622f2f4 2875 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen);
b832be1e
EC		 2876 *lso_seg_len = halign;
2877 return 0;
2878}
2879
95d04f07
RD		 2880static __be32 send_ieth(struct ib_send_wr *wr)
2881{
2882 switch (wr->opcode) {
2883 case IB_WR_SEND_WITH_IMM:
2884 case IB_WR_RDMA_WRITE_WITH_IMM:
2885 return wr->ex.imm_data;
2886
2887 case IB_WR_SEND_WITH_INV:
2888 return cpu_to_be32(wr->ex.invalidate_rkey);
2889
2890 default:
2891 return 0;
2892 }
2893}
2894
1ffeb2eb
JM		 2895static void add_zero_len_inline(void *wqe)
2896{
2897 struct mlx4_wqe_inline_seg *inl = wqe;
2898 memset(wqe, 0, 16);
2899 inl->byte_count = cpu_to_be32(1 << 31);
2900}
2901
225c7b1f
RD		 2902int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2903 struct ib_send_wr **bad_wr)
2904{
2905 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2906 void *wqe;
2907 struct mlx4_wqe_ctrl_seg *ctrl;
6e694ea3 2908 struct mlx4_wqe_data_seg *dseg;
225c7b1f
RD		 2909 unsigned long flags;
2910 int nreq;
2911 int err = 0;
ea54b10c
JM		 2912 unsigned ind;
2913 int uninitialized_var(stamp);
2914 int uninitialized_var(size);
a3d8e159 2915 unsigned uninitialized_var(seglen);
0fd7e1d8
RD		 2916 __be32 dummy;
2917 __be32 *lso_wqe;
2918 __be32 uninitialized_var(lso_hdr_sz);
417608c2 2919 __be32 blh;
225c7b1f 2920 int i;
35f05dab 2921 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 2922
e1b866c6
MS		 2923 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2924 struct mlx4_ib_sqp *sqp = to_msqp(qp);
2925
2926 if (sqp->roce_v2_gsi) {
2927 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah);
2928 struct ib_gid_attr gid_attr;
2929 union ib_gid gid;
2930
2931 if (!ib_get_cached_gid(ibqp->device,
2932 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2933 ah->av.ib.gid_index, &gid,
2934 &gid_attr)) {
2935 if (gid_attr.ndev)
2936 dev_put(gid_attr.ndev);
2937 qp = (gid_attr.gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ?
2938 to_mqp(sqp->roce_v2_gsi) : qp;
2939 } else {
2940 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n",
2941 ah->av.ib.gid_index);
2942 }
2943 }
2944 }
2945
96db0e03 2946 spin_lock_irqsave(&qp->sq.lock, flags);
35f05dab
YH		 2947 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
2948 err = -EIO;
2949 *bad_wr = wr;
2950 nreq = 0;
2951 goto out;
2952 }
225c7b1f 2953
ea54b10c 2954 ind = qp->sq_next_wqe;
225c7b1f
RD		 2955
2956 for (nreq = 0; wr; ++nreq, wr = wr->next) {
0fd7e1d8 2957 lso_wqe = &dummy;
417608c2 2958 blh = 0;
0fd7e1d8 2959
225c7b1f
RD		 2960 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2961 err = -ENOMEM;
2962 *bad_wr = wr;
2963 goto out;
2964 }
2965
2966 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
2967 err = -EINVAL;
2968 *bad_wr = wr;
2969 goto out;
2970 }
2971
0e6e7416 2972 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
ea54b10c 2973 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
225c7b1f
RD		 2974
2975 ctrl->srcrb_flags =
2976 (wr->send_flags & IB_SEND_SIGNALED ?
2977 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
2978 (wr->send_flags & IB_SEND_SOLICITED ?
2979 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
8ff095ec
EC		 2980 ((wr->send_flags & IB_SEND_IP_CSUM) ?
2981 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
2982 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
225c7b1f
RD		 2983 qp->sq_signal_bits;
2984
95d04f07 2985 ctrl->imm = send_ieth(wr);
225c7b1f
RD		 2986
2987 wqe += sizeof *ctrl;
2988 size = sizeof *ctrl / 16;
2989
1ffeb2eb
JM		 2990 switch (qp->mlx4_ib_qp_type) {
2991 case MLX4_IB_QPT_RC:
2992 case MLX4_IB_QPT_UC:
225c7b1f
RD		 2993 switch (wr->opcode) {
2994 case IB_WR_ATOMIC_CMP_AND_SWP:
2995 case IB_WR_ATOMIC_FETCH_AND_ADD:
6fa8f719 2996 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
e622f2f4
CH		 2997 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
2998 atomic_wr(wr)->rkey);
225c7b1f
RD		 2999 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3000
e622f2f4 3001 set_atomic_seg(wqe, atomic_wr(wr));
225c7b1f 3002 wqe += sizeof (struct mlx4_wqe_atomic_seg);
0fbfa6a9 3003
225c7b1f
RD		 3004 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3005 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
6fa8f719
VS		 3006
3007 break;
3008
3009 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
e622f2f4
CH		 3010 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3011 atomic_wr(wr)->rkey);
6fa8f719
VS		 3012 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3013
e622f2f4 3014 set_masked_atomic_seg(wqe, atomic_wr(wr));
6fa8f719
VS		 3015 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
3016
3017 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3018 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
225c7b1f
RD		 3019
3020 break;
3021
3022 case IB_WR_RDMA_READ:
3023 case IB_WR_RDMA_WRITE:
3024 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3025 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
3026 rdma_wr(wr)->rkey);
225c7b1f
RD		 3027 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3028 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
225c7b1f 3029 break;
95d04f07
RD		 3030
3031 case IB_WR_LOCAL_INV:
2ac6bf4d
JM		 3032 ctrl->srcrb_flags |=
3033 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 3034 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
3035 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
3036 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
3037 break;
3038
1b2cd0fc
SG		 3039 case IB_WR_REG_MR:
3040 ctrl->srcrb_flags |=
3041 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3042 set_reg_seg(wqe, reg_wr(wr));
3043 wqe += sizeof(struct mlx4_wqe_fmr_seg);
3044 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
3045 break;
3046
225c7b1f
RD		 3047 default:
3048 /* No extra segments required for sends */
3049 break;
3050 }
3051 break;
3052
1ffeb2eb 3053 case MLX4_IB_QPT_TUN_SMI_OWNER:
e622f2f4
CH		 3054 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3055 ctrl, &seglen);
1ffeb2eb
JM		 3056 if (unlikely(err)) {
3057 *bad_wr = wr;
3058 goto out;
3059 }
3060 wqe += seglen;
3061 size += seglen / 16;
3062 break;
3063 case MLX4_IB_QPT_TUN_SMI:
3064 case MLX4_IB_QPT_TUN_GSI:
3065 /* this is a UD qp used in MAD responses to slaves. */
e622f2f4 3066 set_datagram_seg(wqe, ud_wr(wr));
1ffeb2eb
JM		 3067 /* set the forced-loopback bit in the data seg av */
3068 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
3069 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3070 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3071 break;
3072 case MLX4_IB_QPT_UD:
e622f2f4 3073 set_datagram_seg(wqe, ud_wr(wr));
225c7b1f
RD		 3074 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3075 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
b832be1e
EC		 3076
3077 if (wr->opcode == IB_WR_LSO) {
e622f2f4
CH		 3078 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
3079 &lso_hdr_sz, &blh);
b832be1e
EC		 3080 if (unlikely(err)) {
3081 *bad_wr = wr;
3082 goto out;
3083 }
0fd7e1d8 3084 lso_wqe = (__be32 *) wqe;
b832be1e
EC		 3085 wqe += seglen;
3086 size += seglen / 16;
3087 }
225c7b1f
RD		 3088 break;
3089
1ffeb2eb 3090 case MLX4_IB_QPT_PROXY_SMI_OWNER:
e622f2f4
CH		 3091 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3092 ctrl, &seglen);
1ffeb2eb
JM		 3093 if (unlikely(err)) {
3094 *bad_wr = wr;
3095 goto out;
3096 }
3097 wqe += seglen;
3098 size += seglen / 16;
3099 /* to start tunnel header on a cache-line boundary */
3100 add_zero_len_inline(wqe);
3101 wqe += 16;
3102 size++;
e622f2f4 3103 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 3104 wqe += seglen;
3105 size += seglen / 16;
3106 break;
3107 case MLX4_IB_QPT_PROXY_SMI:
1ffeb2eb
JM		 3108 case MLX4_IB_QPT_PROXY_GSI:
3109 /* If we are tunneling special qps, this is a UD qp.
3110 * In this case we first add a UD segment targeting
3111 * the tunnel qp, and then add a header with address
3112 * information */
e622f2f4
CH		 3113 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
3114 ud_wr(wr),
97982f5a 3115 qp->mlx4_ib_qp_type);
1ffeb2eb
JM		 3116 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3117 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
e622f2f4 3118 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 3119 wqe += seglen;
3120 size += seglen / 16;
3121 break;
3122
3123 case MLX4_IB_QPT_SMI:
3124 case MLX4_IB_QPT_GSI:
e622f2f4
CH		 3125 err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
3126 &seglen);
f438000f 3127 if (unlikely(err)) {
225c7b1f
RD		 3128 *bad_wr = wr;
3129 goto out;
3130 }
f438000f
RD		 3131 wqe += seglen;
3132 size += seglen / 16;
225c7b1f
RD		 3133 break;
3134
3135 default:
3136 break;
3137 }
3138
6e694ea3
JM		 3139 /*
3140 * Write data segments in reverse order, so as to
3141 * overwrite cacheline stamp last within each
3142 * cacheline. This avoids issues with WQE
3143 * prefetching.
3144 */
225c7b1f 3145
6e694ea3
JM		 3146 dseg = wqe;
3147 dseg += wr->num_sge - 1;
3148 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
225c7b1f
RD		 3149
3150 /* Add one more inline data segment for ICRC for MLX sends */
1ffeb2eb
JM		 3151 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
3152 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
3153 qp->mlx4_ib_qp_type &
3154 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6e694ea3 3155 set_mlx_icrc_seg(dseg + 1);
225c7b1f
RD		 3156 size += sizeof (struct mlx4_wqe_data_seg) / 16;
3157 }
3158
6e694ea3
JM		 3159 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3160 set_data_seg(dseg, wr->sg_list + i);
3161
0fd7e1d8
RD		 3162 /*
3163 * Possibly overwrite stamping in cacheline with LSO
3164 * segment only after making sure all data segments
3165 * are written.
3166 */
3167 wmb();
3168 *lso_wqe = lso_hdr_sz;
3169
225c7b1f
RD		 3170 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
3171 MLX4_WQE_CTRL_FENCE : 0) | size;
3172
3173 /*
3174 * Make sure descriptor is fully written before
3175 * setting ownership bit (because HW can start
3176 * executing as soon as we do).
3177 */
3178 wmb();
3179
59b0ed12 3180 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
4ba6b8ea 3181 *bad_wr = wr;
225c7b1f
RD		 3182 err = -EINVAL;
3183 goto out;
3184 }
3185
3186 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
417608c2 3187 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
0e6e7416 3188
ea54b10c
JM		 3189 stamp = ind + qp->sq_spare_wqes;
3190 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
3191
0e6e7416
RD		 3192 /*
3193 * We can improve latency by not stamping the last
3194 * send queue WQE until after ringing the doorbell, so
3195 * only stamp here if there are still more WQEs to post.
ea54b10c
JM		 3196 *
3197 * Same optimization applies to padding with NOP wqe
3198 * in case of WQE shrinking (used to prevent wrap-around
3199 * in the middle of WR).
0e6e7416 3200 */
ea54b10c
JM		 3201 if (wr->next) {
3202 stamp_send_wqe(qp, stamp, size * 16);
3203 ind = pad_wraparound(qp, ind);
3204 }
225c7b1f
RD		 3205 }
3206
3207out:
3208 if (likely(nreq)) {
3209 qp->sq.head += nreq;
3210
3211 /*
3212 * Make sure that descriptors are written before
3213 * doorbell record.
3214 */
3215 wmb();
3216
3217 writel(qp->doorbell_qpn,
3218 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3219
3220 /*
3221 * Make sure doorbells don't leak out of SQ spinlock
3222 * and reach the HCA out of order.
3223 */
3224 mmiowb();
0e6e7416 3225
ea54b10c
JM		 3226 stamp_send_wqe(qp, stamp, size * 16);
3227
3228 ind = pad_wraparound(qp, ind);
3229 qp->sq_next_wqe = ind;
225c7b1f
RD		 3230 }
3231
96db0e03 3232 spin_unlock_irqrestore(&qp->sq.lock, flags);
225c7b1f
RD		 3233
3234 return err;
3235}
3236
3237int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3238 struct ib_recv_wr **bad_wr)
3239{
3240 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3241 struct mlx4_wqe_data_seg *scat;
3242 unsigned long flags;
3243 int err = 0;
3244 int nreq;
3245 int ind;
1ffeb2eb 3246 int max_gs;
225c7b1f 3247 int i;
35f05dab 3248 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3249
1ffeb2eb 3250 max_gs = qp->rq.max_gs;
225c7b1f
RD		 3251 spin_lock_irqsave(&qp->rq.lock, flags);
3252
35f05dab
YH		 3253 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3254 err = -EIO;
3255 *bad_wr = wr;
3256 nreq = 0;
3257 goto out;
3258 }
3259
0e6e7416 3260 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3261
3262 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2b946077 3263 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
225c7b1f
RD		 3264 err = -ENOMEM;
3265 *bad_wr = wr;
3266 goto out;
3267 }
3268
3269 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3270 err = -EINVAL;
3271 *bad_wr = wr;
3272 goto out;
3273 }
3274
3275 scat = get_recv_wqe(qp, ind);
3276
1ffeb2eb
JM		 3277 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3278 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3279 ib_dma_sync_single_for_device(ibqp->device,
3280 qp->sqp_proxy_rcv[ind].map,
3281 sizeof (struct mlx4_ib_proxy_sqp_hdr),
3282 DMA_FROM_DEVICE);
3283 scat->byte_count =
3284 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3285 /* use dma lkey from upper layer entry */
3286 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3287 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3288 scat++;
3289 max_gs--;
3290 }
3291
2242fa4f
RD		 3292 for (i = 0; i < wr->num_sge; ++i)
3293 __set_data_seg(scat + i, wr->sg_list + i);
225c7b1f 3294
1ffeb2eb 3295 if (i < max_gs) {
225c7b1f
RD		 3296 scat[i].byte_count = 0;
3297 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
3298 scat[i].addr = 0;
3299 }
3300
3301 qp->rq.wrid[ind] = wr->wr_id;
3302
0e6e7416 3303 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3304 }
3305
3306out:
3307 if (likely(nreq)) {
3308 qp->rq.head += nreq;
3309
3310 /*
3311 * Make sure that descriptors are written before
3312 * doorbell record.
3313 */
3314 wmb();
3315
3316 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3317 }
3318
3319 spin_unlock_irqrestore(&qp->rq.lock, flags);
3320
3321 return err;
3322}
6a775e2b
JM		 3323
3324static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3325{
3326 switch (mlx4_state) {
3327 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
3328 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
3329 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
3330 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
3331 case MLX4_QP_STATE_SQ_DRAINING:
3332 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
3333 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
3334 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
3335 default: return -1;
3336 }
3337}
3338
3339static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3340{
3341 switch (mlx4_mig_state) {
3342 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
3343 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
3344 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3345 default: return -1;
3346 }
3347}
3348
3349static int to_ib_qp_access_flags(int mlx4_flags)
3350{
3351 int ib_flags = 0;
3352
3353 if (mlx4_flags & MLX4_QP_BIT_RRE)
3354 ib_flags |= IB_ACCESS_REMOTE_READ;
3355 if (mlx4_flags & MLX4_QP_BIT_RWE)
3356 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3357 if (mlx4_flags & MLX4_QP_BIT_RAE)
3358 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3359
3360 return ib_flags;
3361}
3362
4c3eb3ca 3363static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
6a775e2b
JM		 3364 struct mlx4_qp_path *path)
3365{
4c3eb3ca
EC		 3366 struct mlx4_dev *dev = ibdev->dev;
3367 int is_eth;
3368
8fcea95a 3369 memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
6a775e2b
JM		 3370 ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1;
3371
3372 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
3373 return;
3374
4c3eb3ca
EC		 3375 is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
3376 IB_LINK_LAYER_ETHERNET;
3377 if (is_eth)
3378 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
3379 ((path->sched_queue & 4) << 1);
3380 else
3381 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
3382
6a775e2b 3383 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
6a775e2b
JM		 3384 ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
3385 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
3386 ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
3387 if (ib_ah_attr->ah_flags) {
3388 ib_ah_attr->grh.sgid_index = path->mgid_index;
3389 ib_ah_attr->grh.hop_limit = path->hop_limit;
3390 ib_ah_attr->grh.traffic_class =
3391 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3392 ib_ah_attr->grh.flow_label =
586bb586 3393 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
6a775e2b
JM		 3394 memcpy(ib_ah_attr->grh.dgid.raw,
3395 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
3396 }
3397}
3398
3399int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3400 struct ib_qp_init_attr *qp_init_attr)
3401{
3402 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3403 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3404 struct mlx4_qp_context context;
3405 int mlx4_state;
0df67030
DB		 3406 int err = 0;
3407
3408 mutex_lock(&qp->mutex);
6a775e2b
JM		 3409
3410 if (qp->state == IB_QPS_RESET) {
3411 qp_attr->qp_state = IB_QPS_RESET;
3412 goto done;
3413 }
3414
3415 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
0df67030
DB		 3416 if (err) {
3417 err = -EINVAL;
3418 goto out;
3419 }
6a775e2b
JM		 3420
3421 mlx4_state = be32_to_cpu(context.flags) >> 28;
3422
0df67030
DB		 3423 qp->state = to_ib_qp_state(mlx4_state);
3424 qp_attr->qp_state = qp->state;
6a775e2b
JM		 3425 qp_attr->path_mtu = context.mtu_msgmax >> 5;
3426 qp_attr->path_mig_state =
3427 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3428 qp_attr->qkey = be32_to_cpu(context.qkey);
3429 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3430 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
3431 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
3432 qp_attr->qp_access_flags =
3433 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3434
3435 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4c3eb3ca
EC		 3436 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3437 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
6a775e2b
JM		 3438 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
3439 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
3440 }
3441
3442 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1c27cb71
JM		 3443 if (qp_attr->qp_state == IB_QPS_INIT)
3444 qp_attr->port_num = qp->port;
3445 else
3446 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
6a775e2b
JM		 3447
3448 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3449 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3450
3451 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3452
3453 qp_attr->max_dest_rd_atomic =
3454 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3455 qp_attr->min_rnr_timer =
3456 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3457 qp_attr->timeout = context.pri_path.ackto >> 3;
3458 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
3459 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
3460 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
3461
3462done:
3463 qp_attr->cur_qp_state = qp_attr->qp_state;
7f5eb9bb
RD		 3464 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
3465 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
3466
6a775e2b 3467 if (!ibqp->uobject) {
7f5eb9bb
RD		 3468 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
3469 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3470 } else {
3471 qp_attr->cap.max_send_wr = 0;
3472 qp_attr->cap.max_send_sge = 0;
6a775e2b
JM		 3473 }
3474
7f5eb9bb
RD		 3475 /*
3476 * We don't support inline sends for kernel QPs (yet), and we
3477 * don't know what userspace's value should be.
3478 */
3479 qp_attr->cap.max_inline_data = 0;
3480
3481 qp_init_attr->cap = qp_attr->cap;
3482
521e575b
RL		 3483 qp_init_attr->create_flags = 0;
3484 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3485 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3486
3487 if (qp->flags & MLX4_IB_QP_LSO)
3488 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
3489
c1c98501
MB		 3490 if (qp->flags & MLX4_IB_QP_NETIF)
3491 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
3492
46db567d
DB		 3493 qp_init_attr->sq_sig_type =
3494 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
3495 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3496
0df67030
DB		 3497out:
3498 mutex_unlock(&qp->mutex);
3499 return err;
6a775e2b
JM		 3500}
3501
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