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IB/mlx4: Enable send of RoCE QP1 packets with IP/UDP headers
[mirror_ubuntu-jammy-kernel.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
ea54b10c 34#include <linux/log2.h>
1049f138 35#include <linux/etherdevice.h>
3ef967a4 36#include <net/ip.h>
5a0e3ad6 37#include <linux/slab.h>
fa417f7b 38#include <linux/netdevice.h>
0ef2f05c 39#include <linux/vmalloc.h>
ea54b10c 40
225c7b1f
RD		 41#include <rdma/ib_cache.h>
42#include <rdma/ib_pack.h>
4c3eb3ca 43#include <rdma/ib_addr.h>
1ffeb2eb 44#include <rdma/ib_mad.h>
225c7b1f 45
2f48485d 46#include <linux/mlx4/driver.h>
225c7b1f
RD		 47#include <linux/mlx4/qp.h>
48
49#include "mlx4_ib.h"
50#include "user.h"
51
35f05dab
YH		 52static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
53 struct mlx4_ib_cq *recv_cq);
54static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
55 struct mlx4_ib_cq *recv_cq);
56
225c7b1f
RD		 57enum {
58 MLX4_IB_ACK_REQ_FREQ = 8,
59};
60
61enum {
62 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
fa417f7b
EC		 63 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
64 MLX4_IB_LINK_TYPE_IB = 0,
65 MLX4_IB_LINK_TYPE_ETH = 1
225c7b1f
RD		 66};
67
68enum {
69 /*
fa417f7b 70 * Largest possible UD header: send with GRH and immediate
4c3eb3ca
EC		 71 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
72 * tag. (LRH would only use 8 bytes, so Ethernet is the
73 * biggest case)
225c7b1f 74 */
4c3eb3ca 75 MLX4_IB_UD_HEADER_SIZE = 82,
417608c2 76 MLX4_IB_LSO_HEADER_SPARE = 128,
225c7b1f
RD		 77};
78
fa417f7b
EC		 79enum {
80 MLX4_IB_IBOE_ETHERTYPE = 0x8915
81};
82
225c7b1f
RD		 83struct mlx4_ib_sqp {
84 struct mlx4_ib_qp qp;
85 int pkey_index;
86 u32 qkey;
87 u32 send_psn;
88 struct ib_ud_header ud_header;
89 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
90};
91
83904132 92enum {
417608c2
EC		 93 MLX4_IB_MIN_SQ_STRIDE = 6,
94 MLX4_IB_CACHE_LINE_SIZE = 64,
83904132
JM		 95};
96
3987a2d3
OG		 97enum {
98 MLX4_RAW_QP_MTU = 7,
99 MLX4_RAW_QP_MSGMAX = 31,
100};
101
297e0dad
MS		 102#ifndef ETH_ALEN
103#define ETH_ALEN 6
104#endif
297e0dad 105
225c7b1f 106static const __be32 mlx4_ib_opcode[] = {
6fa8f719
VS		 107 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
108 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
109 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
110 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
111 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
112 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
113 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
114 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
115 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
116 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
1b2cd0fc 117 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
6fa8f719
VS		 118 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
119 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
225c7b1f
RD		 120};
121
122static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
123{
124 return container_of(mqp, struct mlx4_ib_sqp, qp);
125}
126
1ffeb2eb
JM		 127static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
128{
129 if (!mlx4_is_master(dev->dev))
130 return 0;
131
47605df9
JM		 132 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
133 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
134 8 * MLX4_MFUNC_MAX;
1ffeb2eb
JM		 135}
136
225c7b1f
RD		 137static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
138{
47605df9
JM		 139 int proxy_sqp = 0;
140 int real_sqp = 0;
141 int i;
142 /* PPF or Native -- real SQP */
143 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
144 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
145 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
146 if (real_sqp)
147 return 1;
148 /* VF or PF -- proxy SQP */
149 if (mlx4_is_mfunc(dev->dev)) {
150 for (i = 0; i < dev->dev->caps.num_ports; i++) {
151 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
152 qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
153 proxy_sqp = 1;
154 break;
155 }
156 }
157 }
158 return proxy_sqp;
225c7b1f
RD		 159}
160
1ffeb2eb 161/* used for INIT/CLOSE port logic */
225c7b1f
RD		 162static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
163{
47605df9
JM		 164 int proxy_qp0 = 0;
165 int real_qp0 = 0;
166 int i;
167 /* PPF or Native -- real QP0 */
168 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
169 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
170 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
171 if (real_qp0)
172 return 1;
173 /* VF or PF -- proxy QP0 */
174 if (mlx4_is_mfunc(dev->dev)) {
175 for (i = 0; i < dev->dev->caps.num_ports; i++) {
176 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
177 proxy_qp0 = 1;
178 break;
179 }
180 }
181 }
182 return proxy_qp0;
225c7b1f
RD		 183}
184
185static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
186{
1c69fc2a 187 return mlx4_buf_offset(&qp->buf, offset);
225c7b1f
RD		 188}
189
190static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
191{
192 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
193}
194
195static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
196{
197 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
198}
199
0e6e7416
RD		 200/*
201 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
ea54b10c
JM		 202 * first four bytes of every 64 byte chunk with
203 * 0x7FFFFFF | (invalid_ownership_value << 31).
204 *
205 * When the max work request size is less than or equal to the WQE
206 * basic block size, as an optimization, we can stamp all WQEs with
207 * 0xffffffff, and skip the very first chunk of each WQE.
0e6e7416 208 */
ea54b10c 209static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
0e6e7416 210{
d2ae16d5 211 __be32 *wqe;
0e6e7416 212 int i;
ea54b10c
JM		 213 int s;
214 int ind;
215 void *buf;
216 __be32 stamp;
9670e553 217 struct mlx4_wqe_ctrl_seg *ctrl;
ea54b10c 218
ea54b10c 219 if (qp->sq_max_wqes_per_wr > 1) {
9670e553 220 s = roundup(size, 1U << qp->sq.wqe_shift);
ea54b10c
JM		 221 for (i = 0; i < s; i += 64) {
222 ind = (i >> qp->sq.wqe_shift) + n;
223 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
224 cpu_to_be32(0xffffffff);
225 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
226 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
227 *wqe = stamp;
228 }
229 } else {
9670e553
EC		 230 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
231 s = (ctrl->fence_size & 0x3f) << 4;
ea54b10c
JM		 232 for (i = 64; i < s; i += 64) {
233 wqe = buf + i;
d2ae16d5 234 *wqe = cpu_to_be32(0xffffffff);
ea54b10c
JM		 235 }
236 }
237}
238
239static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
240{
241 struct mlx4_wqe_ctrl_seg *ctrl;
242 struct mlx4_wqe_inline_seg *inl;
243 void *wqe;
244 int s;
245
246 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
247 s = sizeof(struct mlx4_wqe_ctrl_seg);
248
249 if (qp->ibqp.qp_type == IB_QPT_UD) {
250 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
251 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
252 memset(dgram, 0, sizeof *dgram);
253 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
254 s += sizeof(struct mlx4_wqe_datagram_seg);
255 }
256
257 /* Pad the remainder of the WQE with an inline data segment. */
258 if (size > s) {
259 inl = wqe + s;
260 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
261 }
262 ctrl->srcrb_flags = 0;
263 ctrl->fence_size = size / 16;
264 /*
265 * Make sure descriptor is fully written before setting ownership bit
266 * (because HW can start executing as soon as we do).
267 */
268 wmb();
269
270 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
271 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
0e6e7416 272
ea54b10c
JM		 273 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
274}
275
276/* Post NOP WQE to prevent wrap-around in the middle of WR */
277static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
278{
279 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
280 if (unlikely(s < qp->sq_max_wqes_per_wr)) {
281 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
282 ind += s;
283 }
284 return ind;
0e6e7416
RD		 285}
286
225c7b1f
RD		 287static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
288{
289 struct ib_event event;
290 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
291
292 if (type == MLX4_EVENT_TYPE_PATH_MIG)
293 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
294
295 if (ibqp->event_handler) {
296 event.device = ibqp->device;
297 event.element.qp = ibqp;
298 switch (type) {
299 case MLX4_EVENT_TYPE_PATH_MIG:
300 event.event = IB_EVENT_PATH_MIG;
301 break;
302 case MLX4_EVENT_TYPE_COMM_EST:
303 event.event = IB_EVENT_COMM_EST;
304 break;
305 case MLX4_EVENT_TYPE_SQ_DRAINED:
306 event.event = IB_EVENT_SQ_DRAINED;
307 break;
308 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
309 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
310 break;
311 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
312 event.event = IB_EVENT_QP_FATAL;
313 break;
314 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
315 event.event = IB_EVENT_PATH_MIG_ERR;
316 break;
317 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
318 event.event = IB_EVENT_QP_REQ_ERR;
319 break;
320 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
321 event.event = IB_EVENT_QP_ACCESS_ERR;
322 break;
323 default:
987c8f8f 324 pr_warn("Unexpected event type %d "
225c7b1f
RD		 325 "on QP %06x\n", type, qp->qpn);
326 return;
327 }
328
329 ibqp->event_handler(&event, ibqp->qp_context);
330 }
331}
332
1ffeb2eb 333static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
225c7b1f
RD		 334{
335 /*
336 * UD WQEs must have a datagram segment.
337 * RC and UC WQEs might have a remote address segment.
338 * MLX WQEs need two extra inline data segments (for the UD
339 * header and space for the ICRC).
340 */
341 switch (type) {
1ffeb2eb 342 case MLX4_IB_QPT_UD:
225c7b1f 343 return sizeof (struct mlx4_wqe_ctrl_seg) +
b832be1e 344 sizeof (struct mlx4_wqe_datagram_seg) +
417608c2 345 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
1ffeb2eb
JM		 346 case MLX4_IB_QPT_PROXY_SMI_OWNER:
347 case MLX4_IB_QPT_PROXY_SMI:
348 case MLX4_IB_QPT_PROXY_GSI:
349 return sizeof (struct mlx4_wqe_ctrl_seg) +
350 sizeof (struct mlx4_wqe_datagram_seg) + 64;
351 case MLX4_IB_QPT_TUN_SMI_OWNER:
352 case MLX4_IB_QPT_TUN_GSI:
353 return sizeof (struct mlx4_wqe_ctrl_seg) +
354 sizeof (struct mlx4_wqe_datagram_seg);
355
356 case MLX4_IB_QPT_UC:
225c7b1f
RD		 357 return sizeof (struct mlx4_wqe_ctrl_seg) +
358 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb 359 case MLX4_IB_QPT_RC:
225c7b1f
RD		 360 return sizeof (struct mlx4_wqe_ctrl_seg) +
361 sizeof (struct mlx4_wqe_atomic_seg) +
362 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb
JM		 363 case MLX4_IB_QPT_SMI:
364 case MLX4_IB_QPT_GSI:
225c7b1f
RD		 365 return sizeof (struct mlx4_wqe_ctrl_seg) +
366 ALIGN(MLX4_IB_UD_HEADER_SIZE +
e61ef241
RD		 367 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
368 MLX4_INLINE_ALIGN) *
225c7b1f
RD		 369 sizeof (struct mlx4_wqe_inline_seg),
370 sizeof (struct mlx4_wqe_data_seg)) +
371 ALIGN(4 +
372 sizeof (struct mlx4_wqe_inline_seg),
373 sizeof (struct mlx4_wqe_data_seg));
374 default:
375 return sizeof (struct mlx4_wqe_ctrl_seg);
376 }
377}
378
2446304d 379static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
0a1405da 380 int is_user, int has_rq, struct mlx4_ib_qp *qp)
225c7b1f 381{
2446304d 382 /* Sanity check RQ size before proceeding */
fc2d0044
SG		 383 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
384 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
2446304d
EC		 385 return -EINVAL;
386
0a1405da 387 if (!has_rq) {
a4cd7ed8
RD		 388 if (cap->max_recv_wr)
389 return -EINVAL;
2446304d 390
0e6e7416 391 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
a4cd7ed8
RD		 392 } else {
393 /* HW requires >= 1 RQ entry with >= 1 gather entry */
394 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
395 return -EINVAL;
396
0e6e7416 397 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
42c059ea 398 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
a4cd7ed8
RD		 399 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
400 }
2446304d 401
fc2d0044
SG		 402 /* leave userspace return values as they were, so as not to break ABI */
403 if (is_user) {
404 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
405 cap->max_recv_sge = qp->rq.max_gs;
406 } else {
407 cap->max_recv_wr = qp->rq.max_post =
408 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
409 cap->max_recv_sge = min(qp->rq.max_gs,
410 min(dev->dev->caps.max_sq_sg,
411 dev->dev->caps.max_rq_sg));
412 }
2446304d
EC		 413
414 return 0;
415}
416
417static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
1ffeb2eb 418 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
2446304d 419{
ea54b10c
JM		 420 int s;
421
2446304d 422 /* Sanity check SQ size before proceeding */
fc2d0044
SG		 423 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
424 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
b832be1e 425 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
225c7b1f
RD		 426 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
427 return -EINVAL;
428
429 /*
430 * For MLX transport we need 2 extra S/G entries:
431 * one for the header and one for the checksum at the end
432 */
1ffeb2eb
JM		 433 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
434 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
225c7b1f
RD		 435 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
436 return -EINVAL;
437
ea54b10c
JM		 438 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
439 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
b832be1e 440 send_wqe_overhead(type, qp->flags);
225c7b1f 441
cd155c1c
RD		 442 if (s > dev->dev->caps.max_sq_desc_sz)
443 return -EINVAL;
444
0e6e7416 445 /*
ea54b10c
JM		 446 * Hermon supports shrinking WQEs, such that a single work
447 * request can include multiple units of 1 << wqe_shift. This
448 * way, work requests can differ in size, and do not have to
449 * be a power of 2 in size, saving memory and speeding up send
450 * WR posting. Unfortunately, if we do this then the
451 * wqe_index field in CQEs can't be used to look up the WR ID
452 * anymore, so we do this only if selective signaling is off.
453 *
454 * Further, on 32-bit platforms, we can't use vmap() to make
af901ca1 455 * the QP buffer virtually contiguous. Thus we have to use
ea54b10c
JM		 456 * constant-sized WRs to make sure a WR is always fully within
457 * a single page-sized chunk.
458 *
459 * Finally, we use NOP work requests to pad the end of the
460 * work queue, to avoid wrap-around in the middle of WR. We
461 * set NEC bit to avoid getting completions with error for
462 * these NOP WRs, but since NEC is only supported starting
463 * with firmware 2.2.232, we use constant-sized WRs for older
464 * firmware.
465 *
466 * And, since MLX QPs only support SEND, we use constant-sized
467 * WRs in this case.
468 *
469 * We look for the smallest value of wqe_shift such that the
470 * resulting number of wqes does not exceed device
471 * capabilities.
472 *
473 * We set WQE size to at least 64 bytes, this way stamping
474 * invalidates each WQE.
0e6e7416 475 */
ea54b10c
JM		 476 if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
477 qp->sq_signal_bits && BITS_PER_LONG == 64 &&
1ffeb2eb
JM		 478 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
479 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
480 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
ea54b10c
JM		 481 qp->sq.wqe_shift = ilog2(64);
482 else
483 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
484
485 for (;;) {
ea54b10c
JM		 486 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
487
488 /*
489 * We need to leave 2 KB + 1 WR of headroom in the SQ to
490 * allow HW to prefetch.
491 */
492 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
493 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
494 qp->sq_max_wqes_per_wr +
495 qp->sq_spare_wqes);
496
497 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
498 break;
499
500 if (qp->sq_max_wqes_per_wr <= 1)
501 return -EINVAL;
502
503 ++qp->sq.wqe_shift;
504 }
505
cd155c1c
RD		 506 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
507 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
b832be1e
EC		 508 send_wqe_overhead(type, qp->flags)) /
509 sizeof (struct mlx4_wqe_data_seg);
0e6e7416
RD		 510
511 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
512 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
225c7b1f
RD		 513 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
514 qp->rq.offset = 0;
0e6e7416 515 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
225c7b1f 516 } else {
0e6e7416 517 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
225c7b1f
RD		 518 qp->sq.offset = 0;
519 }
520
ea54b10c
JM		 521 cap->max_send_wr = qp->sq.max_post =
522 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
cd155c1c
RD		 523 cap->max_send_sge = min(qp->sq.max_gs,
524 min(dev->dev->caps.max_sq_sg,
525 dev->dev->caps.max_rq_sg));
54e95f8d
RD		 526 /* We don't support inline sends for kernel QPs (yet) */
527 cap->max_inline_data = 0;
225c7b1f
RD		 528
529 return 0;
530}
531
83904132
JM		 532static int set_user_sq_size(struct mlx4_ib_dev *dev,
533 struct mlx4_ib_qp *qp,
2446304d
EC		 534 struct mlx4_ib_create_qp *ucmd)
535{
83904132
JM		 536 /* Sanity check SQ size before proceeding */
537 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
538 ucmd->log_sq_stride >
539 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
540 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
541 return -EINVAL;
542
0e6e7416 543 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
2446304d
EC		 544 qp->sq.wqe_shift = ucmd->log_sq_stride;
545
0e6e7416
RD		 546 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
547 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
2446304d
EC		 548
549 return 0;
550}
551
1ffeb2eb
JM		 552static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
553{
554 int i;
555
556 qp->sqp_proxy_rcv =
557 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
558 GFP_KERNEL);
559 if (!qp->sqp_proxy_rcv)
560 return -ENOMEM;
561 for (i = 0; i < qp->rq.wqe_cnt; i++) {
562 qp->sqp_proxy_rcv[i].addr =
563 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
564 GFP_KERNEL);
565 if (!qp->sqp_proxy_rcv[i].addr)
566 goto err;
567 qp->sqp_proxy_rcv[i].map =
568 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
569 sizeof (struct mlx4_ib_proxy_sqp_hdr),
570 DMA_FROM_DEVICE);
cc47d369
SO		 571 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
572 kfree(qp->sqp_proxy_rcv[i].addr);
573 goto err;
574 }
1ffeb2eb
JM		 575 }
576 return 0;
577
578err:
579 while (i > 0) {
580 --i;
581 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
582 sizeof (struct mlx4_ib_proxy_sqp_hdr),
583 DMA_FROM_DEVICE);
584 kfree(qp->sqp_proxy_rcv[i].addr);
585 }
586 kfree(qp->sqp_proxy_rcv);
587 qp->sqp_proxy_rcv = NULL;
588 return -ENOMEM;
589}
590
591static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
592{
593 int i;
594
595 for (i = 0; i < qp->rq.wqe_cnt; i++) {
596 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
597 sizeof (struct mlx4_ib_proxy_sqp_hdr),
598 DMA_FROM_DEVICE);
599 kfree(qp->sqp_proxy_rcv[i].addr);
600 }
601 kfree(qp->sqp_proxy_rcv);
602}
603
0a1405da
SH		 604static int qp_has_rq(struct ib_qp_init_attr *attr)
605{
606 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
607 return 0;
608
609 return !attr->srq;
610}
611
99ec41d0
JM		 612static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
613{
614 int i;
615 for (i = 0; i < dev->caps.num_ports; i++) {
616 if (qpn == dev->caps.qp0_proxy[i])
617 return !!dev->caps.qp0_qkey[i];
618 }
619 return 0;
620}
621
7b59f0f9
EBE		 622static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
623 struct mlx4_ib_qp *qp)
624{
625 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
626 mlx4_counter_free(dev->dev, qp->counter_index->index);
627 list_del(&qp->counter_index->list);
628 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
629
630 kfree(qp->counter_index);
631 qp->counter_index = NULL;
632}
633
225c7b1f
RD		 634static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
635 struct ib_qp_init_attr *init_attr,
40f2287b
JK		 636 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp,
637 gfp_t gfp)
225c7b1f 638{
a3cdcbfa 639 int qpn;
225c7b1f 640 int err;
1ffeb2eb
JM		 641 struct mlx4_ib_sqp *sqp;
642 struct mlx4_ib_qp *qp;
643 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
35f05dab
YH		 644 struct mlx4_ib_cq *mcq;
645 unsigned long flags;
1ffeb2eb
JM		 646
647 /* When tunneling special qps, we use a plain UD qp */
648 if (sqpn) {
649 if (mlx4_is_mfunc(dev->dev) &&
650 (!mlx4_is_master(dev->dev) ||
651 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
652 if (init_attr->qp_type == IB_QPT_GSI)
653 qp_type = MLX4_IB_QPT_PROXY_GSI;
99ec41d0
JM		 654 else {
655 if (mlx4_is_master(dev->dev) ||
656 qp0_enabled_vf(dev->dev, sqpn))
657 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
658 else
659 qp_type = MLX4_IB_QPT_PROXY_SMI;
660 }
1ffeb2eb
JM		 661 }
662 qpn = sqpn;
663 /* add extra sg entry for tunneling */
664 init_attr->cap.max_recv_sge++;
665 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
666 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
667 container_of(init_attr,
668 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
669 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
670 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
671 !mlx4_is_master(dev->dev))
672 return -EINVAL;
673 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
674 qp_type = MLX4_IB_QPT_TUN_GSI;
99ec41d0
JM		 675 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
676 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
677 tnl_init->port))
1ffeb2eb
JM		 678 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
679 else
680 qp_type = MLX4_IB_QPT_TUN_SMI;
47605df9
JM		 681 /* we are definitely in the PPF here, since we are creating
682 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
683 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
684 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1ffeb2eb
JM		 685 sqpn = qpn;
686 }
687
688 if (!*caller_qp) {
689 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
690 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
691 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6fcd8d0d 692 sqp = kzalloc(sizeof (struct mlx4_ib_sqp), gfp);
1ffeb2eb
JM		 693 if (!sqp)
694 return -ENOMEM;
695 qp = &sqp->qp;
2f5bb473
JM		 696 qp->pri.vid = 0xFFFF;
697 qp->alt.vid = 0xFFFF;
1ffeb2eb 698 } else {
6fcd8d0d 699 qp = kzalloc(sizeof (struct mlx4_ib_qp), gfp);
1ffeb2eb
JM		 700 if (!qp)
701 return -ENOMEM;
2f5bb473
JM		 702 qp->pri.vid = 0xFFFF;
703 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 704 }
705 } else
706 qp = *caller_qp;
707
708 qp->mlx4_ib_qp_type = qp_type;
225c7b1f
RD		 709
710 mutex_init(&qp->mutex);
711 spin_lock_init(&qp->sq.lock);
712 spin_lock_init(&qp->rq.lock);
fa417f7b 713 INIT_LIST_HEAD(&qp->gid_list);
0ff1fb65 714 INIT_LIST_HEAD(&qp->steering_rules);
225c7b1f
RD		 715
716 qp->state = IB_QPS_RESET;
ea54b10c
JM		 717 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
718 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
225c7b1f 719
0a1405da 720 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
225c7b1f
RD		 721 if (err)
722 goto err;
723
724 if (pd->uobject) {
725 struct mlx4_ib_create_qp ucmd;
726
727 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
728 err = -EFAULT;
729 goto err;
730 }
731
0e6e7416
RD		 732 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
733
83904132 734 err = set_user_sq_size(dev, qp, &ucmd);
2446304d
EC		 735 if (err)
736 goto err;
737
225c7b1f 738 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
cb9fbc5c 739 qp->buf_size, 0, 0);
225c7b1f
RD		 740 if (IS_ERR(qp->umem)) {
741 err = PTR_ERR(qp->umem);
742 goto err;
743 }
744
745 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
746 ilog2(qp->umem->page_size), &qp->mtt);
747 if (err)
748 goto err_buf;
749
750 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
751 if (err)
752 goto err_mtt;
753
0a1405da 754 if (qp_has_rq(init_attr)) {
02d89b87
RD		 755 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
756 ucmd.db_addr, &qp->db);
757 if (err)
758 goto err_mtt;
759 }
225c7b1f 760 } else {
0e6e7416
RD		 761 qp->sq_no_prefetch = 0;
762
b832be1e
EC		 763 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
764 qp->flags |= MLX4_IB_QP_LSO;
765
c1c98501
MB		 766 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
767 if (dev->steering_support ==
768 MLX4_STEERING_MODE_DEVICE_MANAGED)
769 qp->flags |= MLX4_IB_QP_NETIF;
770 else
771 goto err;
772 }
773
1ffeb2eb 774 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
2446304d
EC		 775 if (err)
776 goto err;
777
0a1405da 778 if (qp_has_rq(init_attr)) {
40f2287b 779 err = mlx4_db_alloc(dev->dev, &qp->db, 0, gfp);
02d89b87
RD		 780 if (err)
781 goto err;
225c7b1f 782
02d89b87
RD		 783 *qp->db.db = 0;
784 }
225c7b1f 785
40f2287b 786 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf, gfp)) {
225c7b1f
RD		 787 err = -ENOMEM;
788 goto err_db;
789 }
790
791 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
792 &qp->mtt);
793 if (err)
794 goto err_buf;
795
40f2287b 796 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf, gfp);
225c7b1f
RD		 797 if (err)
798 goto err_mtt;
799
ee370950 800 qp->sq.wrid = kmalloc_array(qp->sq.wqe_cnt, sizeof(u64),
9afc60dc 801 gfp | __GFP_NOWARN);
0ef2f05c
WW		 802 if (!qp->sq.wrid)
803 qp->sq.wrid = __vmalloc(qp->sq.wqe_cnt * sizeof(u64),
804 gfp, PAGE_KERNEL);
ee370950 805 qp->rq.wrid = kmalloc_array(qp->rq.wqe_cnt, sizeof(u64),
9afc60dc 806 gfp | __GFP_NOWARN);
0ef2f05c
WW		 807 if (!qp->rq.wrid)
808 qp->rq.wrid = __vmalloc(qp->rq.wqe_cnt * sizeof(u64),
809 gfp, PAGE_KERNEL);
225c7b1f
RD		 810 if (!qp->sq.wrid || !qp->rq.wrid) {
811 err = -ENOMEM;
812 goto err_wrid;
813 }
225c7b1f
RD		 814 }
815
a3cdcbfa 816 if (sqpn) {
1ffeb2eb
JM		 817 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
818 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
819 if (alloc_proxy_bufs(pd->device, qp)) {
820 err = -ENOMEM;
821 goto err_wrid;
822 }
823 }
a3cdcbfa 824 } else {
ddae0349
EE		 825 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
826 * otherwise, the WQE BlueFlame setup flow wrongly causes
827 * VLAN insertion. */
3987a2d3 828 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
ddae0349 829 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
d57febe1
MB		 830 (init_attr->cap.max_send_wr ?
831 MLX4_RESERVE_ETH_BF_QP : 0) |
832 (init_attr->cap.max_recv_wr ?
833 MLX4_RESERVE_A0_QP : 0));
3987a2d3 834 else
c1c98501
MB		 835 if (qp->flags & MLX4_IB_QP_NETIF)
836 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
837 else
838 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
ddae0349 839 &qpn, 0);
a3cdcbfa 840 if (err)
1ffeb2eb 841 goto err_proxy;
a3cdcbfa
YP		 842 }
843
fbfb6625
EBE		 844 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
845 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
846
40f2287b 847 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp, gfp);
225c7b1f 848 if (err)
a3cdcbfa 849 goto err_qpn;
225c7b1f 850
0a1405da
SH		 851 if (init_attr->qp_type == IB_QPT_XRC_TGT)
852 qp->mqp.qpn |= (1 << 23);
853
225c7b1f
RD		 854 /*
855 * Hardware wants QPN written in big-endian order (after
856 * shifting) for send doorbell. Precompute this value to save
857 * a little bit when posting sends.
858 */
859 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
860
225c7b1f 861 qp->mqp.event = mlx4_ib_qp_event;
1ffeb2eb
JM		 862 if (!*caller_qp)
863 *caller_qp = qp;
35f05dab
YH		 864
865 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
866 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
867 to_mcq(init_attr->recv_cq));
868 /* Maintain device to QPs access, needed for further handling
869 * via reset flow
870 */
871 list_add_tail(&qp->qps_list, &dev->qp_list);
872 /* Maintain CQ to QPs access, needed for further handling
873 * via reset flow
874 */
875 mcq = to_mcq(init_attr->send_cq);
876 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
877 mcq = to_mcq(init_attr->recv_cq);
878 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
879 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
880 to_mcq(init_attr->recv_cq));
881 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 882 return 0;
883
a3cdcbfa 884err_qpn:
c1c98501
MB		 885 if (!sqpn) {
886 if (qp->flags & MLX4_IB_QP_NETIF)
887 mlx4_ib_steer_qp_free(dev, qpn, 1);
888 else
889 mlx4_qp_release_range(dev->dev, qpn, 1);
890 }
1ffeb2eb
JM		 891err_proxy:
892 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
893 free_proxy_bufs(pd->device, qp);
225c7b1f 894err_wrid:
23f1b384 895 if (pd->uobject) {
0a1405da
SH		 896 if (qp_has_rq(init_attr))
897 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
23f1b384 898 } else {
0ef2f05c
WW		 899 kvfree(qp->sq.wrid);
900 kvfree(qp->rq.wrid);
225c7b1f
RD		 901 }
902
903err_mtt:
904 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
905
906err_buf:
907 if (pd->uobject)
908 ib_umem_release(qp->umem);
909 else
910 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
911
912err_db:
0a1405da 913 if (!pd->uobject && qp_has_rq(init_attr))
6296883c 914 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 915
916err:
1ffeb2eb
JM		 917 if (!*caller_qp)
918 kfree(qp);
225c7b1f
RD		 919 return err;
920}
921
922static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
923{
924 switch (state) {
925 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
926 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
927 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
928 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
929 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
930 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
931 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
932 default: return -1;
933 }
934}
935
936static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 937 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
225c7b1f 938{
338a8fad 939 if (send_cq == recv_cq) {
35f05dab 940 spin_lock(&send_cq->lock);
338a8fad
RD		 941 __acquire(&recv_cq->lock);
942 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
35f05dab 943 spin_lock(&send_cq->lock);
225c7b1f
RD		 944 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
945 } else {
35f05dab 946 spin_lock(&recv_cq->lock);
225c7b1f
RD		 947 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
948 }
949}
950
951static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 952 __releases(&send_cq->lock) __releases(&recv_cq->lock)
225c7b1f 953{
338a8fad
RD		 954 if (send_cq == recv_cq) {
955 __release(&recv_cq->lock);
35f05dab 956 spin_unlock(&send_cq->lock);
338a8fad 957 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
225c7b1f 958 spin_unlock(&recv_cq->lock);
35f05dab 959 spin_unlock(&send_cq->lock);
225c7b1f
RD		 960 } else {
961 spin_unlock(&send_cq->lock);
35f05dab 962 spin_unlock(&recv_cq->lock);
225c7b1f
RD		 963 }
964}
965
fa417f7b
EC		 966static void del_gid_entries(struct mlx4_ib_qp *qp)
967{
968 struct mlx4_ib_gid_entry *ge, *tmp;
969
970 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
971 list_del(&ge->list);
972 kfree(ge);
973 }
974}
975
0a1405da
SH		 976static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
977{
978 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
979 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
980 else
981 return to_mpd(qp->ibqp.pd);
982}
983
984static void get_cqs(struct mlx4_ib_qp *qp,
985 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
986{
987 switch (qp->ibqp.qp_type) {
988 case IB_QPT_XRC_TGT:
989 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
990 *recv_cq = *send_cq;
991 break;
992 case IB_QPT_XRC_INI:
993 *send_cq = to_mcq(qp->ibqp.send_cq);
994 *recv_cq = *send_cq;
995 break;
996 default:
997 *send_cq = to_mcq(qp->ibqp.send_cq);
998 *recv_cq = to_mcq(qp->ibqp.recv_cq);
999 break;
1000 }
1001}
1002
225c7b1f
RD		 1003static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
1004 int is_user)
1005{
1006 struct mlx4_ib_cq *send_cq, *recv_cq;
35f05dab 1007 unsigned long flags;
225c7b1f 1008
2f5bb473 1009 if (qp->state != IB_QPS_RESET) {
225c7b1f
RD		 1010 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1011 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
987c8f8f 1012 pr_warn("modify QP %06x to RESET failed.\n",
225c7b1f 1013 qp->mqp.qpn);
25476b02 1014 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 1015 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1016 qp->pri.smac = 0;
25476b02 1017 qp->pri.smac_port = 0;
2f5bb473
JM		 1018 }
1019 if (qp->alt.smac) {
1020 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1021 qp->alt.smac = 0;
1022 }
1023 if (qp->pri.vid < 0x1000) {
1024 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1025 qp->pri.vid = 0xFFFF;
1026 qp->pri.candidate_vid = 0xFFFF;
1027 qp->pri.update_vid = 0;
1028 }
1029 if (qp->alt.vid < 0x1000) {
1030 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1031 qp->alt.vid = 0xFFFF;
1032 qp->alt.candidate_vid = 0xFFFF;
1033 qp->alt.update_vid = 0;
1034 }
1035 }
225c7b1f 1036
0a1405da 1037 get_cqs(qp, &send_cq, &recv_cq);
225c7b1f 1038
35f05dab 1039 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1040 mlx4_ib_lock_cqs(send_cq, recv_cq);
1041
35f05dab
YH		 1042 /* del from lists under both locks above to protect reset flow paths */
1043 list_del(&qp->qps_list);
1044 list_del(&qp->cq_send_list);
1045 list_del(&qp->cq_recv_list);
225c7b1f
RD		 1046 if (!is_user) {
1047 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1048 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1049 if (send_cq != recv_cq)
1050 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1051 }
1052
1053 mlx4_qp_remove(dev->dev, &qp->mqp);
1054
1055 mlx4_ib_unlock_cqs(send_cq, recv_cq);
35f05dab 1056 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1057
1058 mlx4_qp_free(dev->dev, &qp->mqp);
a3cdcbfa 1059
c1c98501
MB		 1060 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1061 if (qp->flags & MLX4_IB_QP_NETIF)
1062 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1063 else
1064 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1065 }
a3cdcbfa 1066
225c7b1f
RD		 1067 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1068
1069 if (is_user) {
0a1405da 1070 if (qp->rq.wqe_cnt)
02d89b87
RD		 1071 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
1072 &qp->db);
225c7b1f
RD		 1073 ib_umem_release(qp->umem);
1074 } else {
0ef2f05c
WW		 1075 kvfree(qp->sq.wrid);
1076 kvfree(qp->rq.wrid);
1ffeb2eb
JM		 1077 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1078 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1079 free_proxy_bufs(&dev->ib_dev, qp);
225c7b1f 1080 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
0a1405da 1081 if (qp->rq.wqe_cnt)
6296883c 1082 mlx4_db_free(dev->dev, &qp->db);
225c7b1f 1083 }
fa417f7b
EC		 1084
1085 del_gid_entries(qp);
225c7b1f
RD		 1086}
1087
47605df9
JM		 1088static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1089{
1090 /* Native or PPF */
1091 if (!mlx4_is_mfunc(dev->dev) ||
1092 (mlx4_is_master(dev->dev) &&
1093 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1094 return dev->dev->phys_caps.base_sqpn +
1095 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1096 attr->port_num - 1;
1097 }
1098 /* PF or VF -- creating proxies */
1099 if (attr->qp_type == IB_QPT_SMI)
1100 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1101 else
1102 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1103}
1104
225c7b1f
RD		 1105struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1106 struct ib_qp_init_attr *init_attr,
1107 struct ib_udata *udata)
1108{
1ffeb2eb 1109 struct mlx4_ib_qp *qp = NULL;
225c7b1f 1110 int err;
fbfb6625 1111 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
0a1405da 1112 u16 xrcdn = 0;
40f2287b 1113 gfp_t gfp;
225c7b1f 1114
40f2287b
JK		 1115 gfp = (init_attr->create_flags & MLX4_IB_QP_CREATE_USE_GFP_NOIO) ?
1116 GFP_NOIO : GFP_KERNEL;
521e575b 1117 /*
1ffeb2eb
JM		 1118 * We only support LSO, vendor flag1, and multicast loopback blocking,
1119 * and only for kernel UD QPs.
521e575b 1120 */
1ffeb2eb
JM		 1121 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1122 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
c1c98501
MB		 1123 MLX4_IB_SRIOV_TUNNEL_QP |
1124 MLX4_IB_SRIOV_SQP |
40f2287b
JK		 1125 MLX4_IB_QP_NETIF |
1126 MLX4_IB_QP_CREATE_USE_GFP_NOIO))
b832be1e 1127 return ERR_PTR(-EINVAL);
521e575b 1128
c1c98501
MB		 1129 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1130 if (init_attr->qp_type != IB_QPT_UD)
1131 return ERR_PTR(-EINVAL);
1132 }
1133
521e575b 1134 if (init_attr->create_flags &&
fbfb6625
EBE		 1135 ((udata && init_attr->create_flags & ~(sup_u_create_flags)) ||
1136 ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
1137 MLX4_IB_QP_CREATE_USE_GFP_NOIO |
1138 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)) &&
1ffeb2eb
JM		 1139 init_attr->qp_type != IB_QPT_UD) ||
1140 ((init_attr->create_flags & MLX4_IB_SRIOV_SQP) &&
1141 init_attr->qp_type > IB_QPT_GSI)))
b846f25a
EC		 1142 return ERR_PTR(-EINVAL);
1143
225c7b1f 1144 switch (init_attr->qp_type) {
0a1405da
SH		 1145 case IB_QPT_XRC_TGT:
1146 pd = to_mxrcd(init_attr->xrcd)->pd;
1147 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1148 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1149 /* fall through */
1150 case IB_QPT_XRC_INI:
1151 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1152 return ERR_PTR(-ENOSYS);
1153 init_attr->recv_cq = init_attr->send_cq;
1154 /* fall through */
225c7b1f
RD		 1155 case IB_QPT_RC:
1156 case IB_QPT_UC:
3987a2d3 1157 case IB_QPT_RAW_PACKET:
40f2287b 1158 qp = kzalloc(sizeof *qp, gfp);
225c7b1f
RD		 1159 if (!qp)
1160 return ERR_PTR(-ENOMEM);
2f5bb473
JM		 1161 qp->pri.vid = 0xFFFF;
1162 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 1163 /* fall through */
1164 case IB_QPT_UD:
1165 {
1166 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
40f2287b 1167 udata, 0, &qp, gfp);
1ffeb2eb 1168 if (err)
225c7b1f 1169 return ERR_PTR(err);
225c7b1f
RD		 1170
1171 qp->ibqp.qp_num = qp->mqp.qpn;
0a1405da 1172 qp->xrcdn = xrcdn;
225c7b1f
RD		 1173
1174 break;
1175 }
1176 case IB_QPT_SMI:
1177 case IB_QPT_GSI:
1178 {
1179 /* Userspace is not allowed to create special QPs: */
0a1405da 1180 if (udata)
225c7b1f
RD		 1181 return ERR_PTR(-EINVAL);
1182
0a1405da 1183 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
47605df9 1184 get_sqp_num(to_mdev(pd->device), init_attr),
40f2287b 1185 &qp, gfp);
1ffeb2eb 1186 if (err)
225c7b1f 1187 return ERR_PTR(err);
225c7b1f
RD		 1188
1189 qp->port = init_attr->port_num;
1190 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
1191
1192 break;
1193 }
1194 default:
1195 /* Don't support raw QPs */
1196 return ERR_PTR(-EINVAL);
1197 }
1198
1199 return &qp->ibqp;
1200}
1201
1202int mlx4_ib_destroy_qp(struct ib_qp *qp)
1203{
1204 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1205 struct mlx4_ib_qp *mqp = to_mqp(qp);
0a1405da 1206 struct mlx4_ib_pd *pd;
225c7b1f
RD		 1207
1208 if (is_qp0(dev, mqp))
1209 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1210
9433c188
MB		 1211 if (dev->qp1_proxy[mqp->port - 1] == mqp) {
1212 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1213 dev->qp1_proxy[mqp->port - 1] = NULL;
1214 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1215 }
1216
7b59f0f9
EBE		 1217 if (mqp->counter_index)
1218 mlx4_ib_free_qp_counter(dev, mqp);
1219
0a1405da
SH		 1220 pd = get_pd(mqp);
1221 destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
225c7b1f
RD		 1222
1223 if (is_sqp(dev, mqp))
1224 kfree(to_msqp(mqp));
1225 else
1226 kfree(mqp);
1227
1228 return 0;
1229}
1230
1ffeb2eb 1231static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
225c7b1f
RD		 1232{
1233 switch (type) {
1ffeb2eb
JM		 1234 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1235 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1236 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1237 case MLX4_IB_QPT_XRC_INI:
1238 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1239 case MLX4_IB_QPT_SMI:
1240 case MLX4_IB_QPT_GSI:
1241 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1242
1243 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1244 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1245 MLX4_QP_ST_MLX : -1);
1246 case MLX4_IB_QPT_PROXY_SMI:
1247 case MLX4_IB_QPT_TUN_SMI:
1248 case MLX4_IB_QPT_PROXY_GSI:
1249 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1250 MLX4_QP_ST_UD : -1);
1251 default: return -1;
225c7b1f
RD		 1252 }
1253}
1254
65adfa91 1255static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1256 int attr_mask)
1257{
1258 u8 dest_rd_atomic;
1259 u32 access_flags;
1260 u32 hw_access_flags = 0;
1261
1262 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1263 dest_rd_atomic = attr->max_dest_rd_atomic;
1264 else
1265 dest_rd_atomic = qp->resp_depth;
1266
1267 if (attr_mask & IB_QP_ACCESS_FLAGS)
1268 access_flags = attr->qp_access_flags;
1269 else
1270 access_flags = qp->atomic_rd_en;
1271
1272 if (!dest_rd_atomic)
1273 access_flags &= IB_ACCESS_REMOTE_WRITE;
1274
1275 if (access_flags & IB_ACCESS_REMOTE_READ)
1276 hw_access_flags |= MLX4_QP_BIT_RRE;
1277 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1278 hw_access_flags |= MLX4_QP_BIT_RAE;
1279 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1280 hw_access_flags |= MLX4_QP_BIT_RWE;
1281
1282 return cpu_to_be32(hw_access_flags);
1283}
1284
65adfa91 1285static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1286 int attr_mask)
1287{
1288 if (attr_mask & IB_QP_PKEY_INDEX)
1289 sqp->pkey_index = attr->pkey_index;
1290 if (attr_mask & IB_QP_QKEY)
1291 sqp->qkey = attr->qkey;
1292 if (attr_mask & IB_QP_SQ_PSN)
1293 sqp->send_psn = attr->sq_psn;
1294}
1295
1296static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1297{
1298 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1299}
1300
297e0dad
MS		 1301static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1302 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
2f5bb473 1303 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
225c7b1f 1304{
fa417f7b
EC		 1305 int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1306 IB_LINK_LAYER_ETHERNET;
4c3eb3ca 1307 int vidx;
297e0dad 1308 int smac_index;
2f5bb473 1309 int err;
297e0dad 1310
fa417f7b 1311
225c7b1f
RD		 1312 path->grh_mylmc = ah->src_path_bits & 0x7f;
1313 path->rlid = cpu_to_be16(ah->dlid);
1314 if (ah->static_rate) {
1315 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1316 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1317 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1318 --path->static_rate;
1319 } else
1320 path->static_rate = 0;
225c7b1f
RD		 1321
1322 if (ah->ah_flags & IB_AH_GRH) {
5070cd22
MS		 1323 int real_sgid_index = mlx4_ib_gid_index_to_real_index(dev,
1324 port,
1325 ah->grh.sgid_index);
1326
1327 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
987c8f8f 1328 pr_err("sgid_index (%u) too large. max is %d\n",
5070cd22 1329 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
225c7b1f
RD		 1330 return -1;
1331 }
1332
1333 path->grh_mylmc |= 1 << 7;
5070cd22 1334 path->mgid_index = real_sgid_index;
225c7b1f
RD		 1335 path->hop_limit = ah->grh.hop_limit;
1336 path->tclass_flowlabel =
1337 cpu_to_be32((ah->grh.traffic_class << 20) |
1338 (ah->grh.flow_label));
1339 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1340 }
1341
fa417f7b
EC		 1342 if (is_eth) {
1343 if (!(ah->ah_flags & IB_AH_GRH))
1344 return -1;
1345
2f5bb473
JM		 1346 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1347 ((port - 1) << 6) | ((ah->sl & 7) << 3);
4c3eb3ca 1348
297e0dad 1349 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
4c3eb3ca 1350 if (vlan_tag < 0x1000) {
2f5bb473
JM		 1351 if (smac_info->vid < 0x1000) {
1352 /* both valid vlan ids */
1353 if (smac_info->vid != vlan_tag) {
1354 /* different VIDs. unreg old and reg new */
1355 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1356 if (err)
1357 return err;
1358 smac_info->candidate_vid = vlan_tag;
1359 smac_info->candidate_vlan_index = vidx;
1360 smac_info->candidate_vlan_port = port;
1361 smac_info->update_vid = 1;
1362 path->vlan_index = vidx;
1363 } else {
1364 path->vlan_index = smac_info->vlan_index;
1365 }
1366 } else {
1367 /* no current vlan tag in qp */
1368 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1369 if (err)
1370 return err;
1371 smac_info->candidate_vid = vlan_tag;
1372 smac_info->candidate_vlan_index = vidx;
1373 smac_info->candidate_vlan_port = port;
1374 smac_info->update_vid = 1;
1375 path->vlan_index = vidx;
1376 }
297e0dad 1377 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
2f5bb473
JM		 1378 path->fl = 1 << 6;
1379 } else {
1380 /* have current vlan tag. unregister it at modify-qp success */
1381 if (smac_info->vid < 0x1000) {
1382 smac_info->candidate_vid = 0xFFFF;
1383 smac_info->update_vid = 1;
1384 }
4c3eb3ca 1385 }
2f5bb473
JM		 1386
1387 /* get smac_index for RoCE use.
1388 * If no smac was yet assigned, register one.
1389 * If one was already assigned, but the new mac differs,
1390 * unregister the old one and register the new one.
1391 */
25476b02
JM		 1392 if ((!smac_info->smac && !smac_info->smac_port) ||
1393 smac_info->smac != smac) {
2f5bb473
JM		 1394 /* register candidate now, unreg if needed, after success */
1395 smac_index = mlx4_register_mac(dev->dev, port, smac);
1396 if (smac_index >= 0) {
1397 smac_info->candidate_smac_index = smac_index;
1398 smac_info->candidate_smac = smac;
1399 smac_info->candidate_smac_port = port;
1400 } else {
1401 return -EINVAL;
1402 }
1403 } else {
1404 smac_index = smac_info->smac_index;
1405 }
1406
1407 memcpy(path->dmac, ah->dmac, 6);
1408 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1409 /* put MAC table smac index for IBoE */
1410 path->grh_mylmc = (u8) (smac_index) | 0x80;
1411 } else {
4c3eb3ca
EC		 1412 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1413 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
2f5bb473 1414 }
fa417f7b 1415
225c7b1f
RD		 1416 return 0;
1417}
1418
297e0dad
MS		 1419static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1420 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1421 struct mlx4_ib_qp *mqp,
dbf727de
MB		 1422 struct mlx4_qp_path *path, u8 port,
1423 u16 vlan_id, u8 *smac)
297e0dad
MS		 1424{
1425 return _mlx4_set_path(dev, &qp->ah_attr,
dbf727de
MB		 1426 mlx4_mac_to_u64(smac),
1427 vlan_id,
2f5bb473 1428 path, &mqp->pri, port);
297e0dad
MS		 1429}
1430
1431static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1432 const struct ib_qp_attr *qp,
1433 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1434 struct mlx4_ib_qp *mqp,
297e0dad
MS		 1435 struct mlx4_qp_path *path, u8 port)
1436{
1437 return _mlx4_set_path(dev, &qp->alt_ah_attr,
dbf727de
MB		 1438 0,
1439 0xffff,
2f5bb473 1440 path, &mqp->alt, port);
297e0dad
MS		 1441}
1442
fa417f7b
EC		 1443static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1444{
1445 struct mlx4_ib_gid_entry *ge, *tmp;
1446
1447 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1448 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1449 ge->added = 1;
1450 ge->port = qp->port;
1451 }
1452 }
1453}
1454
dbf727de
MB		 1455static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1456 struct mlx4_ib_qp *qp,
2f5bb473
JM		 1457 struct mlx4_qp_context *context)
1458{
2f5bb473
JM		 1459 u64 u64_mac;
1460 int smac_index;
1461
3e0629cb 1462 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
2f5bb473
JM		 1463
1464 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
25476b02 1465 if (!qp->pri.smac && !qp->pri.smac_port) {
2f5bb473
JM		 1466 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1467 if (smac_index >= 0) {
1468 qp->pri.candidate_smac_index = smac_index;
1469 qp->pri.candidate_smac = u64_mac;
1470 qp->pri.candidate_smac_port = qp->port;
1471 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1472 } else {
1473 return -ENOENT;
1474 }
1475 }
1476 return 0;
1477}
1478
7b59f0f9
EBE		 1479static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1480{
1481 struct counter_index *new_counter_index;
1482 int err;
1483 u32 tmp_idx;
1484
1485 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1486 IB_LINK_LAYER_ETHERNET ||
1487 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1488 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1489 return 0;
1490
1491 err = mlx4_counter_alloc(dev->dev, &tmp_idx);
1492 if (err)
1493 return err;
1494
1495 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1496 if (!new_counter_index) {
1497 mlx4_counter_free(dev->dev, tmp_idx);
1498 return -ENOMEM;
1499 }
1500
1501 new_counter_index->index = tmp_idx;
1502 new_counter_index->allocated = 1;
1503 qp->counter_index = new_counter_index;
1504
1505 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1506 list_add_tail(&new_counter_index->list,
1507 &dev->counters_table[qp->port - 1].counters_list);
1508 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
1509
1510 return 0;
1511}
1512
3b5daf28
MS		 1513enum {
1514 MLX4_QPC_ROCE_MODE_1 = 0,
1515 MLX4_QPC_ROCE_MODE_2 = 2,
1516 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff
1517};
1518
1519static u8 gid_type_to_qpc(enum ib_gid_type gid_type)
1520{
1521 switch (gid_type) {
1522 case IB_GID_TYPE_ROCE:
1523 return MLX4_QPC_ROCE_MODE_1;
1524 case IB_GID_TYPE_ROCE_UDP_ENCAP:
1525 return MLX4_QPC_ROCE_MODE_2;
1526 default:
1527 return MLX4_QPC_ROCE_MODE_UNDEFINED;
1528 }
1529}
1530
65adfa91
MT		 1531static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1532 const struct ib_qp_attr *attr, int attr_mask,
1533 enum ib_qp_state cur_state, enum ib_qp_state new_state)
225c7b1f
RD		 1534{
1535 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1536 struct mlx4_ib_qp *qp = to_mqp(ibqp);
0a1405da
SH		 1537 struct mlx4_ib_pd *pd;
1538 struct mlx4_ib_cq *send_cq, *recv_cq;
225c7b1f
RD		 1539 struct mlx4_qp_context *context;
1540 enum mlx4_qp_optpar optpar = 0;
225c7b1f 1541 int sqd_event;
c1c98501 1542 int steer_qp = 0;
225c7b1f 1543 int err = -EINVAL;
3ba8e31d 1544 int counter_index;
225c7b1f 1545
3dec4878
JM		 1546 /* APM is not supported under RoCE */
1547 if (attr_mask & IB_QP_ALT_PATH &&
1548 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1549 IB_LINK_LAYER_ETHERNET)
1550 return -ENOTSUPP;
1551
225c7b1f
RD		 1552 context = kzalloc(sizeof *context, GFP_KERNEL);
1553 if (!context)
1554 return -ENOMEM;
1555
225c7b1f 1556 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1ffeb2eb 1557 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
225c7b1f
RD		 1558
1559 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1560 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1561 else {
1562 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1563 switch (attr->path_mig_state) {
1564 case IB_MIG_MIGRATED:
1565 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1566 break;
1567 case IB_MIG_REARM:
1568 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1569 break;
1570 case IB_MIG_ARMED:
1571 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1572 break;
1573 }
1574 }
1575
b832be1e 1576 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
225c7b1f 1577 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
3987a2d3
OG		 1578 else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1579 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
b832be1e
EC		 1580 else if (ibqp->qp_type == IB_QPT_UD) {
1581 if (qp->flags & MLX4_IB_QP_LSO)
1582 context->mtu_msgmax = (IB_MTU_4096 << 5) |
1583 ilog2(dev->dev->caps.max_gso_sz);
1584 else
6e0d733d 1585 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
b832be1e 1586 } else if (attr_mask & IB_QP_PATH_MTU) {
225c7b1f 1587 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
987c8f8f 1588 pr_err("path MTU (%u) is invalid\n",
225c7b1f 1589 attr->path_mtu);
f5b40431 1590 goto out;
225c7b1f 1591 }
d1f2cd89
EC		 1592 context->mtu_msgmax = (attr->path_mtu << 5) |
1593 ilog2(dev->dev->caps.max_msg_sz);
225c7b1f
RD		 1594 }
1595
0e6e7416
RD		 1596 if (qp->rq.wqe_cnt)
1597 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
225c7b1f
RD		 1598 context->rq_size_stride |= qp->rq.wqe_shift - 4;
1599
0e6e7416
RD		 1600 if (qp->sq.wqe_cnt)
1601 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
225c7b1f
RD		 1602 context->sq_size_stride |= qp->sq.wqe_shift - 4;
1603
7b59f0f9
EBE		 1604 if (new_state == IB_QPS_RESET && qp->counter_index)
1605 mlx4_ib_free_qp_counter(dev, qp);
1606
0a1405da 1607 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0e6e7416 1608 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
0a1405da 1609 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
02d7ef6f
DB		 1610 if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1611 context->param3 |= cpu_to_be32(1 << 30);
0a1405da 1612 }
0e6e7416 1613
225c7b1f
RD		 1614 if (qp->ibqp.uobject)
1615 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1616 else
1617 context->usr_page = cpu_to_be32(dev->priv_uar.index);
1618
1619 if (attr_mask & IB_QP_DEST_QPN)
1620 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1621
1622 if (attr_mask & IB_QP_PORT) {
1623 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1624 !(attr_mask & IB_QP_AV)) {
1625 mlx4_set_sched(&context->pri_path, attr->port_num);
1626 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1627 }
1628 }
1629
cfcde11c 1630 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
7b59f0f9
EBE		 1631 err = create_qp_lb_counter(dev, qp);
1632 if (err)
1633 goto out;
1634
3ba8e31d
EBE		 1635 counter_index =
1636 dev->counters_table[qp->port - 1].default_counter;
7b59f0f9
EBE		 1637 if (qp->counter_index)
1638 counter_index = qp->counter_index->index;
1639
3ba8e31d
EBE		 1640 if (counter_index != -1) {
1641 context->pri_path.counter_index = counter_index;
cfcde11c 1642 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
7b59f0f9
EBE		 1643 if (qp->counter_index) {
1644 context->pri_path.fl |=
1645 MLX4_FL_ETH_SRC_CHECK_MC_LB;
1646 context->pri_path.vlan_control |=
1647 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
1648 }
cfcde11c 1649 } else
47d8417f
EBE		 1650 context->pri_path.counter_index =
1651 MLX4_SINK_COUNTER_INDEX(dev->dev);
c1c98501
MB		 1652
1653 if (qp->flags & MLX4_IB_QP_NETIF) {
1654 mlx4_ib_steer_qp_reg(dev, qp, 1);
1655 steer_qp = 1;
1656 }
cfcde11c
OG		 1657 }
1658
225c7b1f 1659 if (attr_mask & IB_QP_PKEY_INDEX) {
1ffeb2eb
JM		 1660 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1661 context->pri_path.disable_pkey_check = 0x40;
225c7b1f
RD		 1662 context->pri_path.pkey_index = attr->pkey_index;
1663 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1664 }
1665
225c7b1f 1666 if (attr_mask & IB_QP_AV) {
dbf727de
MB		 1667 u8 port_num = mlx4_is_bonded(to_mdev(ibqp->device)->dev) ? 1 :
1668 attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1669 union ib_gid gid;
1670 struct ib_gid_attr gid_attr;
1671 u16 vlan = 0xffff;
1672 u8 smac[ETH_ALEN];
1673 int status = 0;
3b5daf28
MS		 1674 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
1675 attr->ah_attr.ah_flags & IB_AH_GRH;
dbf727de 1676
3b5daf28 1677 if (is_eth) {
dbf727de
MB		 1678 int index = attr->ah_attr.grh.sgid_index;
1679
1680 status = ib_get_cached_gid(ibqp->device, port_num,
1681 index, &gid, &gid_attr);
1682 if (!status && !memcmp(&gid, &zgid, sizeof(gid)))
1683 status = -ENOENT;
1684 if (!status && gid_attr.ndev) {
1685 vlan = rdma_vlan_dev_vlan_id(gid_attr.ndev);
1686 memcpy(smac, gid_attr.ndev->dev_addr, ETH_ALEN);
1687 dev_put(gid_attr.ndev);
1688 }
1689 }
1690 if (status)
1691 goto out;
1692
2f5bb473 1693 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
dbf727de 1694 port_num, vlan, smac))
225c7b1f 1695 goto out;
225c7b1f
RD		 1696
1697 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1698 MLX4_QP_OPTPAR_SCHED_QUEUE);
3b5daf28
MS		 1699
1700 if (is_eth &&
1701 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) {
1702 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr.gid_type);
1703
1704 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) {
1705 err = -EINVAL;
1706 goto out;
1707 }
1708 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
1709 }
1710
225c7b1f
RD		 1711 }
1712
1713 if (attr_mask & IB_QP_TIMEOUT) {
fa417f7b 1714 context->pri_path.ackto |= attr->timeout << 3;
225c7b1f
RD		 1715 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1716 }
1717
1718 if (attr_mask & IB_QP_ALT_PATH) {
225c7b1f
RD		 1719 if (attr->alt_port_num == 0 ||
1720 attr->alt_port_num > dev->dev->caps.num_ports)
f5b40431 1721 goto out;
225c7b1f 1722
5ae2a7a8
RD		 1723 if (attr->alt_pkey_index >=
1724 dev->dev->caps.pkey_table_len[attr->alt_port_num])
f5b40431 1725 goto out;
5ae2a7a8 1726
2f5bb473
JM		 1727 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
1728 &context->alt_path,
297e0dad 1729 attr->alt_port_num))
f5b40431 1730 goto out;
225c7b1f
RD		 1731
1732 context->alt_path.pkey_index = attr->alt_pkey_index;
1733 context->alt_path.ackto = attr->alt_timeout << 3;
1734 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1735 }
1736
0a1405da
SH		 1737 pd = get_pd(qp);
1738 get_cqs(qp, &send_cq, &recv_cq);
1739 context->pd = cpu_to_be32(pd->pdn);
1740 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1741 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1742 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
57f01b53 1743
95d04f07
RD		 1744 /* Set "fast registration enabled" for all kernel QPs */
1745 if (!qp->ibqp.uobject)
1746 context->params1 |= cpu_to_be32(1 << 11);
1747
57f01b53
JM		 1748 if (attr_mask & IB_QP_RNR_RETRY) {
1749 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1750 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1751 }
1752
225c7b1f
RD		 1753 if (attr_mask & IB_QP_RETRY_CNT) {
1754 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1755 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1756 }
1757
1758 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1759 if (attr->max_rd_atomic)
1760 context->params1 |=
1761 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1762 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1763 }
1764
1765 if (attr_mask & IB_QP_SQ_PSN)
1766 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1767
225c7b1f
RD		 1768 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1769 if (attr->max_dest_rd_atomic)
1770 context->params2 |=
1771 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1772 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1773 }
1774
1775 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1776 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1777 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1778 }
1779
1780 if (ibqp->srq)
1781 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1782
1783 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1784 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1785 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1786 }
1787 if (attr_mask & IB_QP_RQ_PSN)
1788 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1789
1ffeb2eb 1790 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
225c7b1f 1791 if (attr_mask & IB_QP_QKEY) {
1ffeb2eb
JM		 1792 if (qp->mlx4_ib_qp_type &
1793 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1794 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1795 else {
1796 if (mlx4_is_mfunc(dev->dev) &&
1797 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1798 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1799 MLX4_RESERVED_QKEY_BASE) {
1800 pr_err("Cannot use reserved QKEY"
1801 " 0x%x (range 0xffff0000..0xffffffff"
1802 " is reserved)\n", attr->qkey);
1803 err = -EINVAL;
1804 goto out;
1805 }
1806 context->qkey = cpu_to_be32(attr->qkey);
1807 }
225c7b1f
RD		 1808 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1809 }
1810
1811 if (ibqp->srq)
1812 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1813
0a1405da 1814 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
225c7b1f
RD		 1815 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1816
1817 if (cur_state == IB_QPS_INIT &&
1818 new_state == IB_QPS_RTR &&
1819 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
3987a2d3
OG		 1820 ibqp->qp_type == IB_QPT_UD ||
1821 ibqp->qp_type == IB_QPT_RAW_PACKET)) {
225c7b1f 1822 context->pri_path.sched_queue = (qp->port - 1) << 6;
1ffeb2eb
JM		 1823 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1824 qp->mlx4_ib_qp_type &
1825 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
225c7b1f 1826 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1ffeb2eb
JM		 1827 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1828 context->pri_path.fl = 0x80;
1829 } else {
1830 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1831 context->pri_path.fl = 0x80;
225c7b1f 1832 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1ffeb2eb 1833 }
2f5bb473
JM		 1834 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1835 IB_LINK_LAYER_ETHERNET) {
1836 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
1837 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
1838 context->pri_path.feup = 1 << 7; /* don't fsm */
1839 /* handle smac_index */
1840 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
1841 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
1842 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
dbf727de 1843 err = handle_eth_ud_smac_index(dev, qp, context);
bede98e7
MD		 1844 if (err) {
1845 err = -EINVAL;
1846 goto out;
1847 }
9433c188
MB		 1848 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1849 dev->qp1_proxy[qp->port - 1] = qp;
2f5bb473
JM		 1850 }
1851 }
225c7b1f
RD		 1852 }
1853
d2fce8a9 1854 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
3528f696
EC		 1855 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1856 MLX4_IB_LINK_TYPE_ETH;
d2fce8a9
OG		 1857 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1858 /* set QP to receive both tunneled & non-tunneled packets */
8e1a03b6 1859 if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET)))
d2fce8a9
OG		 1860 context->srqn = cpu_to_be32(7 << 28);
1861 }
1862 }
3528f696 1863
297e0dad
MS		 1864 if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1865 int is_eth = rdma_port_get_link_layer(
1866 &dev->ib_dev, qp->port) ==
1867 IB_LINK_LAYER_ETHERNET;
1868 if (is_eth) {
1869 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1870 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1871 }
1872 }
1873
1874
225c7b1f
RD		 1875 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
1876 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1877 sqd_event = 1;
1878 else
1879 sqd_event = 0;
1880
d57f5f72 1881 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3b5daf28 1882 context->rlkey_roce_mode |= (1 << 4);
d57f5f72 1883
c0be5fb5
EC		 1884 /*
1885 * Before passing a kernel QP to the HW, make sure that the
0e6e7416
RD		 1886 * ownership bits of the send queue are set and the SQ
1887 * headroom is stamped so that the hardware doesn't start
1888 * processing stale work requests.
c0be5fb5
EC		 1889 */
1890 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1891 struct mlx4_wqe_ctrl_seg *ctrl;
1892 int i;
1893
0e6e7416 1894 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
c0be5fb5
EC		 1895 ctrl = get_send_wqe(qp, i);
1896 ctrl->owner_opcode = cpu_to_be32(1 << 31);
9670e553
EC		 1897 if (qp->sq_max_wqes_per_wr == 1)
1898 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
0e6e7416 1899
ea54b10c 1900 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
c0be5fb5
EC		 1901 }
1902 }
1903
225c7b1f
RD		 1904 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1905 to_mlx4_state(new_state), context, optpar,
1906 sqd_event, &qp->mqp);
1907 if (err)
1908 goto out;
1909
1910 qp->state = new_state;
1911
1912 if (attr_mask & IB_QP_ACCESS_FLAGS)
1913 qp->atomic_rd_en = attr->qp_access_flags;
1914 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1915 qp->resp_depth = attr->max_dest_rd_atomic;
fa417f7b 1916 if (attr_mask & IB_QP_PORT) {
225c7b1f 1917 qp->port = attr->port_num;
fa417f7b
EC		 1918 update_mcg_macs(dev, qp);
1919 }
225c7b1f
RD		 1920 if (attr_mask & IB_QP_ALT_PATH)
1921 qp->alt_port = attr->alt_port_num;
1922
1923 if (is_sqp(dev, qp))
1924 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1925
1926 /*
1927 * If we moved QP0 to RTR, bring the IB link up; if we moved
1928 * QP0 to RESET or ERROR, bring the link back down.
1929 */
1930 if (is_qp0(dev, qp)) {
1931 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
5ae2a7a8 1932 if (mlx4_INIT_PORT(dev->dev, qp->port))
987c8f8f 1933 pr_warn("INIT_PORT failed for port %d\n",
5ae2a7a8 1934 qp->port);
225c7b1f
RD		 1935
1936 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1937 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1938 mlx4_CLOSE_PORT(dev->dev, qp->port);
1939 }
1940
1941 /*
1942 * If we moved a kernel QP to RESET, clean up all old CQ
1943 * entries and reinitialize the QP.
1944 */
2f5bb473
JM		 1945 if (new_state == IB_QPS_RESET) {
1946 if (!ibqp->uobject) {
1947 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1948 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1949 if (send_cq != recv_cq)
1950 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1951
1952 qp->rq.head = 0;
1953 qp->rq.tail = 0;
1954 qp->sq.head = 0;
1955 qp->sq.tail = 0;
1956 qp->sq_next_wqe = 0;
1957 if (qp->rq.wqe_cnt)
1958 *qp->db.db = 0;
225c7b1f 1959
2f5bb473
JM		 1960 if (qp->flags & MLX4_IB_QP_NETIF)
1961 mlx4_ib_steer_qp_reg(dev, qp, 0);
1962 }
25476b02 1963 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 1964 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1965 qp->pri.smac = 0;
25476b02 1966 qp->pri.smac_port = 0;
2f5bb473
JM		 1967 }
1968 if (qp->alt.smac) {
1969 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1970 qp->alt.smac = 0;
1971 }
1972 if (qp->pri.vid < 0x1000) {
1973 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1974 qp->pri.vid = 0xFFFF;
1975 qp->pri.candidate_vid = 0xFFFF;
1976 qp->pri.update_vid = 0;
1977 }
c1c98501 1978
2f5bb473
JM		 1979 if (qp->alt.vid < 0x1000) {
1980 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1981 qp->alt.vid = 0xFFFF;
1982 qp->alt.candidate_vid = 0xFFFF;
1983 qp->alt.update_vid = 0;
1984 }
225c7b1f 1985 }
225c7b1f 1986out:
7b59f0f9
EBE		 1987 if (err && qp->counter_index)
1988 mlx4_ib_free_qp_counter(dev, qp);
c1c98501
MB		 1989 if (err && steer_qp)
1990 mlx4_ib_steer_qp_reg(dev, qp, 0);
225c7b1f 1991 kfree(context);
25476b02
JM		 1992 if (qp->pri.candidate_smac ||
1993 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2f5bb473
JM		 1994 if (err) {
1995 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
1996 } else {
25476b02 1997 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2f5bb473
JM		 1998 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1999 qp->pri.smac = qp->pri.candidate_smac;
2000 qp->pri.smac_index = qp->pri.candidate_smac_index;
2001 qp->pri.smac_port = qp->pri.candidate_smac_port;
2002 }
2003 qp->pri.candidate_smac = 0;
2004 qp->pri.candidate_smac_index = 0;
2005 qp->pri.candidate_smac_port = 0;
2006 }
2007 if (qp->alt.candidate_smac) {
2008 if (err) {
2009 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
2010 } else {
2011 if (qp->alt.smac)
2012 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2013 qp->alt.smac = qp->alt.candidate_smac;
2014 qp->alt.smac_index = qp->alt.candidate_smac_index;
2015 qp->alt.smac_port = qp->alt.candidate_smac_port;
2016 }
2017 qp->alt.candidate_smac = 0;
2018 qp->alt.candidate_smac_index = 0;
2019 qp->alt.candidate_smac_port = 0;
2020 }
2021
2022 if (qp->pri.update_vid) {
2023 if (err) {
2024 if (qp->pri.candidate_vid < 0x1000)
2025 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
2026 qp->pri.candidate_vid);
2027 } else {
2028 if (qp->pri.vid < 0x1000)
2029 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2030 qp->pri.vid);
2031 qp->pri.vid = qp->pri.candidate_vid;
2032 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2033 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
2034 }
2035 qp->pri.candidate_vid = 0xFFFF;
2036 qp->pri.update_vid = 0;
2037 }
2038
2039 if (qp->alt.update_vid) {
2040 if (err) {
2041 if (qp->alt.candidate_vid < 0x1000)
2042 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2043 qp->alt.candidate_vid);
2044 } else {
2045 if (qp->alt.vid < 0x1000)
2046 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2047 qp->alt.vid);
2048 qp->alt.vid = qp->alt.candidate_vid;
2049 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2050 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
2051 }
2052 qp->alt.candidate_vid = 0xFFFF;
2053 qp->alt.update_vid = 0;
2054 }
2055
225c7b1f
RD		 2056 return err;
2057}
2058
65adfa91
MT		 2059int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2060 int attr_mask, struct ib_udata *udata)
2061{
2062 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2063 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2064 enum ib_qp_state cur_state, new_state;
2065 int err = -EINVAL;
297e0dad 2066 int ll;
65adfa91
MT		 2067 mutex_lock(&qp->mutex);
2068
2069 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2070 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2071
297e0dad
MS		 2072 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2073 ll = IB_LINK_LAYER_UNSPECIFIED;
2074 } else {
2075 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2076 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2077 }
dd5f03be
MB		 2078
2079 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
297e0dad 2080 attr_mask, ll)) {
b1d8eb5a
JM		 2081 pr_debug("qpn 0x%x: invalid attribute mask specified "
2082 "for transition %d to %d. qp_type %d,"
2083 " attr_mask 0x%x\n",
2084 ibqp->qp_num, cur_state, new_state,
2085 ibqp->qp_type, attr_mask);
65adfa91 2086 goto out;
b1d8eb5a 2087 }
65adfa91 2088
c6215745
MS		 2089 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2090 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2091 if ((ibqp->qp_type == IB_QPT_RC) ||
2092 (ibqp->qp_type == IB_QPT_UD) ||
2093 (ibqp->qp_type == IB_QPT_UC) ||
2094 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2095 (ibqp->qp_type == IB_QPT_XRC_INI)) {
2096 attr->port_num = mlx4_ib_bond_next_port(dev);
2097 }
2098 } else {
2099 /* no sense in changing port_num
2100 * when ports are bonded */
2101 attr_mask &= ~IB_QP_PORT;
2102 }
2103 }
2104
65adfa91 2105 if ((attr_mask & IB_QP_PORT) &&
1ffeb2eb 2106 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
b1d8eb5a
JM		 2107 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2108 "for transition %d to %d. qp_type %d\n",
2109 ibqp->qp_num, attr->port_num, cur_state,
2110 new_state, ibqp->qp_type);
65adfa91
MT		 2111 goto out;
2112 }
2113
3987a2d3
OG		 2114 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2115 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2116 IB_LINK_LAYER_ETHERNET))
2117 goto out;
2118
5ae2a7a8
RD		 2119 if (attr_mask & IB_QP_PKEY_INDEX) {
2120 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
b1d8eb5a
JM		 2121 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2122 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2123 "for transition %d to %d. qp_type %d\n",
2124 ibqp->qp_num, attr->pkey_index, cur_state,
2125 new_state, ibqp->qp_type);
5ae2a7a8 2126 goto out;
b1d8eb5a 2127 }
5ae2a7a8
RD		 2128 }
2129
65adfa91
MT		 2130 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2131 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
b1d8eb5a
JM		 2132 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2133 "Transition %d to %d. qp_type %d\n",
2134 ibqp->qp_num, attr->max_rd_atomic, cur_state,
2135 new_state, ibqp->qp_type);
65adfa91
MT		 2136 goto out;
2137 }
2138
2139 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2140 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
b1d8eb5a
JM		 2141 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2142 "Transition %d to %d. qp_type %d\n",
2143 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2144 new_state, ibqp->qp_type);
65adfa91
MT		 2145 goto out;
2146 }
2147
2148 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2149 err = 0;
2150 goto out;
2151 }
2152
65adfa91
MT		 2153 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2154
c6215745
MS		 2155 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2156 attr->port_num = 1;
2157
65adfa91
MT		 2158out:
2159 mutex_unlock(&qp->mutex);
2160 return err;
2161}
2162
99ec41d0
JM		 2163static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2164{
2165 int i;
2166 for (i = 0; i < dev->caps.num_ports; i++) {
2167 if (qpn == dev->caps.qp0_proxy[i] ||
2168 qpn == dev->caps.qp0_tunnel[i]) {
2169 *qkey = dev->caps.qp0_qkey[i];
2170 return 0;
2171 }
2172 }
2173 return -EINVAL;
2174}
2175
1ffeb2eb 2176static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
e622f2f4 2177 struct ib_ud_wr *wr,
1ffeb2eb
JM		 2178 void *wqe, unsigned *mlx_seg_len)
2179{
2180 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2181 struct ib_device *ib_dev = &mdev->ib_dev;
2182 struct mlx4_wqe_mlx_seg *mlx = wqe;
2183 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2184 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 2185 u16 pkey;
2186 u32 qkey;
2187 int send_size;
2188 int header_size;
2189 int spc;
2190 int i;
2191
e622f2f4 2192 if (wr->wr.opcode != IB_WR_SEND)
1ffeb2eb
JM		 2193 return -EINVAL;
2194
2195 send_size = 0;
2196
e622f2f4
CH		 2197 for (i = 0; i < wr->wr.num_sge; ++i)
2198 send_size += wr->wr.sg_list[i].length;
1ffeb2eb
JM		 2199
2200 /* for proxy-qp0 sends, need to add in size of tunnel header */
2201 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2202 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2203 send_size += sizeof (struct mlx4_ib_tunnel_header);
2204
25f40220 2205 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
1ffeb2eb
JM		 2206
2207 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2208 sqp->ud_header.lrh.service_level =
2209 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2210 sqp->ud_header.lrh.destination_lid =
2211 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2212 sqp->ud_header.lrh.source_lid =
2213 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2214 }
2215
2216 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2217
2218 /* force loopback */
2219 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2220 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2221
2222 sqp->ud_header.lrh.virtual_lane = 0;
e622f2f4 2223 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
1ffeb2eb
JM		 2224 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2225 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2226 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
e622f2f4 2227 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
1ffeb2eb
JM		 2228 else
2229 sqp->ud_header.bth.destination_qpn =
47605df9 2230 cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
1ffeb2eb
JM		 2231
2232 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
99ec41d0
JM		 2233 if (mlx4_is_master(mdev->dev)) {
2234 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2235 return -EINVAL;
2236 } else {
2237 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2238 return -EINVAL;
2239 }
1ffeb2eb
JM		 2240 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2241 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2242
2243 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2244 sqp->ud_header.immediate_present = 0;
2245
2246 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2247
2248 /*
2249 * Inline data segments may not cross a 64 byte boundary. If
2250 * our UD header is bigger than the space available up to the
2251 * next 64 byte boundary in the WQE, use two inline data
2252 * segments to hold the UD header.
2253 */
2254 spc = MLX4_INLINE_ALIGN -
2255 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2256 if (header_size <= spc) {
2257 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2258 memcpy(inl + 1, sqp->header_buf, header_size);
2259 i = 1;
2260 } else {
2261 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2262 memcpy(inl + 1, sqp->header_buf, spc);
2263
2264 inl = (void *) (inl + 1) + spc;
2265 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2266 /*
2267 * Need a barrier here to make sure all the data is
2268 * visible before the byte_count field is set.
2269 * Otherwise the HCA prefetcher could grab the 64-byte
2270 * chunk with this inline segment and get a valid (!=
2271 * 0xffffffff) byte count but stale data, and end up
2272 * generating a packet with bad headers.
2273 *
2274 * The first inline segment's byte_count field doesn't
2275 * need a barrier, because it comes after a
2276 * control/MLX segment and therefore is at an offset
2277 * of 16 mod 64.
2278 */
2279 wmb();
2280 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2281 i = 2;
2282 }
2283
2284 *mlx_seg_len =
2285 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2286 return 0;
2287}
2288
3ef967a4 2289#define MLX4_ROCEV2_QP1_SPORT 0xC000
e622f2f4 2290static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_ud_wr *wr,
f438000f 2291 void *wqe, unsigned *mlx_seg_len)
225c7b1f 2292{
a478868a 2293 struct ib_device *ib_dev = sqp->qp.ibqp.device;
225c7b1f 2294 struct mlx4_wqe_mlx_seg *mlx = wqe;
6ee51a4e 2295 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
225c7b1f 2296 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2297 struct mlx4_ib_ah *ah = to_mah(wr->ah);
4c3eb3ca 2298 union ib_gid sgid;
225c7b1f
RD		 2299 u16 pkey;
2300 int send_size;
2301 int header_size;
e61ef241 2302 int spc;
225c7b1f 2303 int i;
1ffeb2eb 2304 int err = 0;
57d88cff 2305 u16 vlan = 0xffff;
a29bec12
RD		 2306 bool is_eth;
2307 bool is_vlan = false;
2308 bool is_grh;
3ef967a4
MS		 2309 bool is_udp = false;
2310 int ip_version = 0;
225c7b1f
RD		 2311
2312 send_size = 0;
e622f2f4
CH		 2313 for (i = 0; i < wr->wr.num_sge; ++i)
2314 send_size += wr->wr.sg_list[i].length;
225c7b1f 2315
fa417f7b
EC		 2316 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2317 is_grh = mlx4_ib_ah_grh_present(ah);
4c3eb3ca 2318 if (is_eth) {
3ef967a4
MS		 2319 struct ib_gid_attr gid_attr;
2320
1ffeb2eb
JM		 2321 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2322 /* When multi-function is enabled, the ib_core gid
2323 * indexes don't necessarily match the hw ones, so
2324 * we must use our own cache */
6ee51a4e
JM		 2325 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2326 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2327 ah->av.ib.gid_index, &sgid.raw[0]);
2328 if (err)
2329 return err;
1ffeb2eb
JM		 2330 } else {
2331 err = ib_get_cached_gid(ib_dev,
2332 be32_to_cpu(ah->av.ib.port_pd) >> 24,
55ee3ab2 2333 ah->av.ib.gid_index, &sgid,
3ef967a4
MS		 2334 &gid_attr);
2335 if (!err) {
2336 if (gid_attr.ndev)
2337 dev_put(gid_attr.ndev);
2338 if (!memcmp(&sgid, &zgid, sizeof(sgid)))
2339 err = -ENOENT;
2340 }
2341 if (!err) {
2342 is_udp = gid_attr.gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
2343 if (is_udp) {
2344 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid))
2345 ip_version = 4;
2346 else
2347 ip_version = 6;
2348 is_grh = false;
2349 }
2350 } else {
1ffeb2eb 2351 return err;
3ef967a4 2352 }
1ffeb2eb 2353 }
0e9855db 2354 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
297e0dad
MS		 2355 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2356 is_vlan = 1;
2357 }
4c3eb3ca 2358 }
25f40220 2359 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
3ef967a4 2360 ip_version, is_udp, 0, &sqp->ud_header);
25f40220
MS		 2361 if (err)
2362 return err;
fa417f7b
EC		 2363
2364 if (!is_eth) {
2365 sqp->ud_header.lrh.service_level =
2366 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2367 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
2368 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2369 }
225c7b1f 2370
3ef967a4 2371 if (is_grh || (ip_version == 6)) {
225c7b1f 2372 sqp->ud_header.grh.traffic_class =
fa417f7b 2373 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
225c7b1f 2374 sqp->ud_header.grh.flow_label =
fa417f7b
EC		 2375 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
2376 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
6ee51a4e
JM		 2377 if (is_eth)
2378 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
2379 else {
1ffeb2eb
JM		 2380 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2381 /* When multi-function is enabled, the ib_core gid
2382 * indexes don't necessarily match the hw ones, so
2383 * we must use our own cache */
2384 sqp->ud_header.grh.source_gid.global.subnet_prefix =
2385 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2386 subnet_prefix;
2387 sqp->ud_header.grh.source_gid.global.interface_id =
2388 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2389 guid_cache[ah->av.ib.gid_index];
2390 } else
2391 ib_get_cached_gid(ib_dev,
2392 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2393 ah->av.ib.gid_index,
55ee3ab2 2394 &sqp->ud_header.grh.source_gid, NULL);
6ee51a4e 2395 }
225c7b1f 2396 memcpy(sqp->ud_header.grh.destination_gid.raw,
fa417f7b 2397 ah->av.ib.dgid, 16);
225c7b1f
RD		 2398 }
2399
3ef967a4
MS		 2400 if (ip_version == 4) {
2401 sqp->ud_header.ip4.tos =
2402 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
2403 sqp->ud_header.ip4.id = 0;
2404 sqp->ud_header.ip4.frag_off = htons(IP_DF);
2405 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit;
2406
2407 memcpy(&sqp->ud_header.ip4.saddr,
2408 sgid.raw + 12, 4);
2409 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4);
2410 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header);
2411 }
2412
2413 if (is_udp) {
2414 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT);
2415 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT);
2416 sqp->ud_header.udp.csum = 0;
2417 }
2418
225c7b1f 2419 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
fa417f7b
EC		 2420
2421 if (!is_eth) {
2422 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
2423 (sqp->ud_header.lrh.destination_lid ==
2424 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
2425 (sqp->ud_header.lrh.service_level << 8));
1ffeb2eb
JM		 2426 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
2427 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
fa417f7b
EC		 2428 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2429 }
225c7b1f 2430
e622f2f4 2431 switch (wr->wr.opcode) {
225c7b1f
RD		 2432 case IB_WR_SEND:
2433 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2434 sqp->ud_header.immediate_present = 0;
2435 break;
2436 case IB_WR_SEND_WITH_IMM:
2437 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2438 sqp->ud_header.immediate_present = 1;
e622f2f4 2439 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
225c7b1f
RD		 2440 break;
2441 default:
2442 return -EINVAL;
2443 }
2444
fa417f7b 2445 if (is_eth) {
6ee51a4e 2446 struct in6_addr in6;
3ef967a4 2447 u16 ether_type;
c0c1d3d7
OD		 2448 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
2449
3ef967a4
MS		 2450 ether_type = (!is_udp) ? MLX4_IB_IBOE_ETHERTYPE :
2451 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6);
2452
c0c1d3d7 2453 mlx->sched_prio = cpu_to_be16(pcp);
fa417f7b 2454
1049f138 2455 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);
fa417f7b 2456 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
6ee51a4e
JM		 2457 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
2458 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
2459 memcpy(&in6, sgid.raw, sizeof(in6));
5ea8bbfc 2460
3e0629cb 2461
fa417f7b
EC		 2462 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
2463 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
4c3eb3ca 2464 if (!is_vlan) {
3ef967a4 2465 sqp->ud_header.eth.type = cpu_to_be16(ether_type);
4c3eb3ca 2466 } else {
3ef967a4 2467 sqp->ud_header.vlan.type = cpu_to_be16(ether_type);
4c3eb3ca
EC		 2468 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
2469 }
fa417f7b
EC		 2470 } else {
2471 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
2472 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
2473 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
2474 }
e622f2f4 2475 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
225c7b1f
RD		 2476 if (!sqp->qp.ibqp.qp_num)
2477 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
2478 else
e622f2f4 2479 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index, &pkey);
225c7b1f 2480 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
e622f2f4 2481 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
225c7b1f 2482 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
e622f2f4
CH		 2483 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
2484 sqp->qkey : wr->remote_qkey);
225c7b1f
RD		 2485 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
2486
2487 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2488
2489 if (0) {
987c8f8f 2490 pr_err("built UD header of size %d:\n", header_size);
225c7b1f
RD		 2491 for (i = 0; i < header_size / 4; ++i) {
2492 if (i % 8 == 0)
987c8f8f
SP		 2493 pr_err(" [%02x] ", i * 4);
2494 pr_cont(" %08x",
2495 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
225c7b1f 2496 if ((i + 1) % 8 == 0)
987c8f8f 2497 pr_cont("\n");
225c7b1f 2498 }
987c8f8f 2499 pr_err("\n");
225c7b1f
RD		 2500 }
2501
e61ef241
RD		 2502 /*
2503 * Inline data segments may not cross a 64 byte boundary. If
2504 * our UD header is bigger than the space available up to the
2505 * next 64 byte boundary in the WQE, use two inline data
2506 * segments to hold the UD header.
2507 */
2508 spc = MLX4_INLINE_ALIGN -
2509 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2510 if (header_size <= spc) {
2511 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2512 memcpy(inl + 1, sqp->header_buf, header_size);
2513 i = 1;
2514 } else {
2515 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2516 memcpy(inl + 1, sqp->header_buf, spc);
2517
2518 inl = (void *) (inl + 1) + spc;
2519 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2520 /*
2521 * Need a barrier here to make sure all the data is
2522 * visible before the byte_count field is set.
2523 * Otherwise the HCA prefetcher could grab the 64-byte
2524 * chunk with this inline segment and get a valid (!=
2525 * 0xffffffff) byte count but stale data, and end up
2526 * generating a packet with bad headers.
2527 *
2528 * The first inline segment's byte_count field doesn't
2529 * need a barrier, because it comes after a
2530 * control/MLX segment and therefore is at an offset
2531 * of 16 mod 64.
2532 */
2533 wmb();
2534 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2535 i = 2;
2536 }
225c7b1f 2537
f438000f
RD		 2538 *mlx_seg_len =
2539 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2540 return 0;
225c7b1f
RD		 2541}
2542
2543static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2544{
2545 unsigned cur;
2546 struct mlx4_ib_cq *cq;
2547
2548 cur = wq->head - wq->tail;
0e6e7416 2549 if (likely(cur + nreq < wq->max_post))
225c7b1f
RD		 2550 return 0;
2551
2552 cq = to_mcq(ib_cq);
2553 spin_lock(&cq->lock);
2554 cur = wq->head - wq->tail;
2555 spin_unlock(&cq->lock);
2556
0e6e7416 2557 return cur + nreq >= wq->max_post;
225c7b1f
RD		 2558}
2559
95d04f07
RD		 2560static __be32 convert_access(int acc)
2561{
6ff63e19
SM		 2562 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2563 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
2564 (acc & IB_ACCESS_REMOTE_WRITE ?
2565 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2566 (acc & IB_ACCESS_REMOTE_READ ?
2567 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
95d04f07
RD		 2568 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
2569 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2570}
2571
1b2cd0fc
SG		 2572static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
2573 struct ib_reg_wr *wr)
2574{
2575 struct mlx4_ib_mr *mr = to_mmr(wr->mr);
2576
2577 fseg->flags = convert_access(wr->access);
2578 fseg->mem_key = cpu_to_be32(wr->key);
2579 fseg->buf_list = cpu_to_be64(mr->page_map);
2580 fseg->start_addr = cpu_to_be64(mr->ibmr.iova);
2581 fseg->reg_len = cpu_to_be64(mr->ibmr.length);
2582 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
2583 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size));
2584 fseg->reserved[0] = 0;
2585 fseg->reserved[1] = 0;
2586}
2587
95d04f07
RD		 2588static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2589{
aee38fad
SM		 2590 memset(iseg, 0, sizeof(*iseg));
2591 iseg->mem_key = cpu_to_be32(rkey);
95d04f07
RD		 2592}
2593
0fbfa6a9
RD		 2594static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2595 u64 remote_addr, u32 rkey)
2596{
2597 rseg->raddr = cpu_to_be64(remote_addr);
2598 rseg->rkey = cpu_to_be32(rkey);
2599 rseg->reserved = 0;
2600}
2601
e622f2f4
CH		 2602static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
2603 struct ib_atomic_wr *wr)
0fbfa6a9 2604{
e622f2f4
CH		 2605 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2606 aseg->swap_add = cpu_to_be64(wr->swap);
2607 aseg->compare = cpu_to_be64(wr->compare_add);
2608 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2609 aseg->swap_add = cpu_to_be64(wr->compare_add);
2610 aseg->compare = cpu_to_be64(wr->compare_add_mask);
0fbfa6a9 2611 } else {
e622f2f4 2612 aseg->swap_add = cpu_to_be64(wr->compare_add);
0fbfa6a9
RD		 2613 aseg->compare = 0;
2614 }
2615
2616}
2617
6fa8f719 2618static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
e622f2f4 2619 struct ib_atomic_wr *wr)
6fa8f719 2620{
e622f2f4
CH		 2621 aseg->swap_add = cpu_to_be64(wr->swap);
2622 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask);
2623 aseg->compare = cpu_to_be64(wr->compare_add);
2624 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask);
6fa8f719
VS		 2625}
2626
0fbfa6a9 2627static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
e622f2f4 2628 struct ib_ud_wr *wr)
0fbfa6a9 2629{
e622f2f4
CH		 2630 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
2631 dseg->dqpn = cpu_to_be32(wr->remote_qpn);
2632 dseg->qkey = cpu_to_be32(wr->remote_qkey);
2633 dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
2634 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
0fbfa6a9
RD		 2635}
2636
1ffeb2eb
JM		 2637static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2638 struct mlx4_wqe_datagram_seg *dseg,
e622f2f4 2639 struct ib_ud_wr *wr,
97982f5a 2640 enum mlx4_ib_qp_type qpt)
1ffeb2eb 2641{
e622f2f4 2642 union mlx4_ext_av *av = &to_mah(wr->ah)->av;
1ffeb2eb
JM		 2643 struct mlx4_av sqp_av = {0};
2644 int port = *((u8 *) &av->ib.port_pd) & 0x3;
2645
2646 /* force loopback */
2647 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2648 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2649 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2650 cpu_to_be32(0xf0000000);
2651
2652 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
97982f5a
JM		 2653 if (qpt == MLX4_IB_QPT_PROXY_GSI)
2654 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2655 else
2656 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]);
47605df9
JM		 2657 /* Use QKEY from the QP context, which is set by master */
2658 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1ffeb2eb
JM		 2659}
2660
e622f2f4 2661static void build_tunnel_header(struct ib_ud_wr *wr, void *wqe, unsigned *mlx_seg_len)
1ffeb2eb
JM		 2662{
2663 struct mlx4_wqe_inline_seg *inl = wqe;
2664 struct mlx4_ib_tunnel_header hdr;
e622f2f4 2665 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 2666 int spc;
2667 int i;
2668
2669 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
e622f2f4
CH		 2670 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
2671 hdr.pkey_index = cpu_to_be16(wr->pkey_index);
2672 hdr.qkey = cpu_to_be32(wr->remote_qkey);
5ea8bbfc
JM		 2673 memcpy(hdr.mac, ah->av.eth.mac, 6);
2674 hdr.vlan = ah->av.eth.vlan;
1ffeb2eb
JM		 2675
2676 spc = MLX4_INLINE_ALIGN -
2677 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2678 if (sizeof (hdr) <= spc) {
2679 memcpy(inl + 1, &hdr, sizeof (hdr));
2680 wmb();
2681 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2682 i = 1;
2683 } else {
2684 memcpy(inl + 1, &hdr, spc);
2685 wmb();
2686 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2687
2688 inl = (void *) (inl + 1) + spc;
2689 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2690 wmb();
2691 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2692 i = 2;
2693 }
2694
2695 *mlx_seg_len =
2696 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2697}
2698
6e694ea3
JM		 2699static void set_mlx_icrc_seg(void *dseg)
2700{
2701 u32 *t = dseg;
2702 struct mlx4_wqe_inline_seg *iseg = dseg;
2703
2704 t[1] = 0;
2705
2706 /*
2707 * Need a barrier here before writing the byte_count field to
2708 * make sure that all the data is visible before the
2709 * byte_count field is set. Otherwise, if the segment begins
2710 * a new cacheline, the HCA prefetcher could grab the 64-byte
2711 * chunk and get a valid (!= * 0xffffffff) byte count but
2712 * stale data, and end up sending the wrong data.
2713 */
2714 wmb();
2715
2716 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2717}
2718
2719static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
d420d9e3 2720{
d420d9e3
RD		 2721 dseg->lkey = cpu_to_be32(sg->lkey);
2722 dseg->addr = cpu_to_be64(sg->addr);
6e694ea3
JM		 2723
2724 /*
2725 * Need a barrier here before writing the byte_count field to
2726 * make sure that all the data is visible before the
2727 * byte_count field is set. Otherwise, if the segment begins
2728 * a new cacheline, the HCA prefetcher could grab the 64-byte
2729 * chunk and get a valid (!= * 0xffffffff) byte count but
2730 * stale data, and end up sending the wrong data.
2731 */
2732 wmb();
2733
2734 dseg->byte_count = cpu_to_be32(sg->length);
d420d9e3
RD		 2735}
2736
2242fa4f
RD		 2737static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2738{
2739 dseg->byte_count = cpu_to_be32(sg->length);
2740 dseg->lkey = cpu_to_be32(sg->lkey);
2741 dseg->addr = cpu_to_be64(sg->addr);
2742}
2743
e622f2f4 2744static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_ud_wr *wr,
0fd7e1d8 2745 struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
417608c2 2746 __be32 *lso_hdr_sz, __be32 *blh)
b832be1e 2747{
e622f2f4 2748 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
b832be1e 2749
417608c2
EC		 2750 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2751 *blh = cpu_to_be32(1 << 6);
b832be1e
EC		 2752
2753 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
e622f2f4 2754 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
b832be1e
EC		 2755 return -EINVAL;
2756
e622f2f4 2757 memcpy(wqe->header, wr->header, wr->hlen);
b832be1e 2758
e622f2f4 2759 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen);
b832be1e
EC		 2760 *lso_seg_len = halign;
2761 return 0;
2762}
2763
95d04f07
RD		 2764static __be32 send_ieth(struct ib_send_wr *wr)
2765{
2766 switch (wr->opcode) {
2767 case IB_WR_SEND_WITH_IMM:
2768 case IB_WR_RDMA_WRITE_WITH_IMM:
2769 return wr->ex.imm_data;
2770
2771 case IB_WR_SEND_WITH_INV:
2772 return cpu_to_be32(wr->ex.invalidate_rkey);
2773
2774 default:
2775 return 0;
2776 }
2777}
2778
1ffeb2eb
JM		 2779static void add_zero_len_inline(void *wqe)
2780{
2781 struct mlx4_wqe_inline_seg *inl = wqe;
2782 memset(wqe, 0, 16);
2783 inl->byte_count = cpu_to_be32(1 << 31);
2784}
2785
225c7b1f
RD		 2786int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2787 struct ib_send_wr **bad_wr)
2788{
2789 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2790 void *wqe;
2791 struct mlx4_wqe_ctrl_seg *ctrl;
6e694ea3 2792 struct mlx4_wqe_data_seg *dseg;
225c7b1f
RD		 2793 unsigned long flags;
2794 int nreq;
2795 int err = 0;
ea54b10c
JM		 2796 unsigned ind;
2797 int uninitialized_var(stamp);
2798 int uninitialized_var(size);
a3d8e159 2799 unsigned uninitialized_var(seglen);
0fd7e1d8
RD		 2800 __be32 dummy;
2801 __be32 *lso_wqe;
2802 __be32 uninitialized_var(lso_hdr_sz);
417608c2 2803 __be32 blh;
225c7b1f 2804 int i;
35f05dab 2805 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 2806
96db0e03 2807 spin_lock_irqsave(&qp->sq.lock, flags);
35f05dab
YH		 2808 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
2809 err = -EIO;
2810 *bad_wr = wr;
2811 nreq = 0;
2812 goto out;
2813 }
225c7b1f 2814
ea54b10c 2815 ind = qp->sq_next_wqe;
225c7b1f
RD		 2816
2817 for (nreq = 0; wr; ++nreq, wr = wr->next) {
0fd7e1d8 2818 lso_wqe = &dummy;
417608c2 2819 blh = 0;
0fd7e1d8 2820
225c7b1f
RD		 2821 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2822 err = -ENOMEM;
2823 *bad_wr = wr;
2824 goto out;
2825 }
2826
2827 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
2828 err = -EINVAL;
2829 *bad_wr = wr;
2830 goto out;
2831 }
2832
0e6e7416 2833 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
ea54b10c 2834 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
225c7b1f
RD		 2835
2836 ctrl->srcrb_flags =
2837 (wr->send_flags & IB_SEND_SIGNALED ?
2838 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
2839 (wr->send_flags & IB_SEND_SOLICITED ?
2840 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
8ff095ec
EC		 2841 ((wr->send_flags & IB_SEND_IP_CSUM) ?
2842 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
2843 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
225c7b1f
RD		 2844 qp->sq_signal_bits;
2845
95d04f07 2846 ctrl->imm = send_ieth(wr);
225c7b1f
RD		 2847
2848 wqe += sizeof *ctrl;
2849 size = sizeof *ctrl / 16;
2850
1ffeb2eb
JM		 2851 switch (qp->mlx4_ib_qp_type) {
2852 case MLX4_IB_QPT_RC:
2853 case MLX4_IB_QPT_UC:
225c7b1f
RD		 2854 switch (wr->opcode) {
2855 case IB_WR_ATOMIC_CMP_AND_SWP:
2856 case IB_WR_ATOMIC_FETCH_AND_ADD:
6fa8f719 2857 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
e622f2f4
CH		 2858 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
2859 atomic_wr(wr)->rkey);
225c7b1f
RD		 2860 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2861
e622f2f4 2862 set_atomic_seg(wqe, atomic_wr(wr));
225c7b1f 2863 wqe += sizeof (struct mlx4_wqe_atomic_seg);
0fbfa6a9 2864
225c7b1f
RD		 2865 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2866 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
6fa8f719
VS		 2867
2868 break;
2869
2870 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
e622f2f4
CH		 2871 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
2872 atomic_wr(wr)->rkey);
6fa8f719
VS		 2873 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2874
e622f2f4 2875 set_masked_atomic_seg(wqe, atomic_wr(wr));
6fa8f719
VS		 2876 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
2877
2878 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2879 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
225c7b1f
RD		 2880
2881 break;
2882
2883 case IB_WR_RDMA_READ:
2884 case IB_WR_RDMA_WRITE:
2885 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 2886 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
2887 rdma_wr(wr)->rkey);
225c7b1f
RD		 2888 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2889 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
225c7b1f 2890 break;
95d04f07
RD		 2891
2892 case IB_WR_LOCAL_INV:
2ac6bf4d
JM		 2893 ctrl->srcrb_flags |=
2894 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 2895 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
2896 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
2897 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
2898 break;
2899
1b2cd0fc
SG		 2900 case IB_WR_REG_MR:
2901 ctrl->srcrb_flags |=
2902 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2903 set_reg_seg(wqe, reg_wr(wr));
2904 wqe += sizeof(struct mlx4_wqe_fmr_seg);
2905 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
2906 break;
2907
225c7b1f
RD		 2908 default:
2909 /* No extra segments required for sends */
2910 break;
2911 }
2912 break;
2913
1ffeb2eb 2914 case MLX4_IB_QPT_TUN_SMI_OWNER:
e622f2f4
CH		 2915 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
2916 ctrl, &seglen);
1ffeb2eb
JM		 2917 if (unlikely(err)) {
2918 *bad_wr = wr;
2919 goto out;
2920 }
2921 wqe += seglen;
2922 size += seglen / 16;
2923 break;
2924 case MLX4_IB_QPT_TUN_SMI:
2925 case MLX4_IB_QPT_TUN_GSI:
2926 /* this is a UD qp used in MAD responses to slaves. */
e622f2f4 2927 set_datagram_seg(wqe, ud_wr(wr));
1ffeb2eb
JM		 2928 /* set the forced-loopback bit in the data seg av */
2929 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
2930 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2931 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2932 break;
2933 case MLX4_IB_QPT_UD:
e622f2f4 2934 set_datagram_seg(wqe, ud_wr(wr));
225c7b1f
RD		 2935 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2936 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
b832be1e
EC		 2937
2938 if (wr->opcode == IB_WR_LSO) {
e622f2f4
CH		 2939 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
2940 &lso_hdr_sz, &blh);
b832be1e
EC		 2941 if (unlikely(err)) {
2942 *bad_wr = wr;
2943 goto out;
2944 }
0fd7e1d8 2945 lso_wqe = (__be32 *) wqe;
b832be1e
EC		 2946 wqe += seglen;
2947 size += seglen / 16;
2948 }
225c7b1f
RD		 2949 break;
2950
1ffeb2eb 2951 case MLX4_IB_QPT_PROXY_SMI_OWNER:
e622f2f4
CH		 2952 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
2953 ctrl, &seglen);
1ffeb2eb
JM		 2954 if (unlikely(err)) {
2955 *bad_wr = wr;
2956 goto out;
2957 }
2958 wqe += seglen;
2959 size += seglen / 16;
2960 /* to start tunnel header on a cache-line boundary */
2961 add_zero_len_inline(wqe);
2962 wqe += 16;
2963 size++;
e622f2f4 2964 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 2965 wqe += seglen;
2966 size += seglen / 16;
2967 break;
2968 case MLX4_IB_QPT_PROXY_SMI:
1ffeb2eb
JM		 2969 case MLX4_IB_QPT_PROXY_GSI:
2970 /* If we are tunneling special qps, this is a UD qp.
2971 * In this case we first add a UD segment targeting
2972 * the tunnel qp, and then add a header with address
2973 * information */
e622f2f4
CH		 2974 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
2975 ud_wr(wr),
97982f5a 2976 qp->mlx4_ib_qp_type);
1ffeb2eb
JM		 2977 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2978 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
e622f2f4 2979 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 2980 wqe += seglen;
2981 size += seglen / 16;
2982 break;
2983
2984 case MLX4_IB_QPT_SMI:
2985 case MLX4_IB_QPT_GSI:
e622f2f4
CH		 2986 err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
2987 &seglen);
f438000f 2988 if (unlikely(err)) {
225c7b1f
RD		 2989 *bad_wr = wr;
2990 goto out;
2991 }
f438000f
RD		 2992 wqe += seglen;
2993 size += seglen / 16;
225c7b1f
RD		 2994 break;
2995
2996 default:
2997 break;
2998 }
2999
6e694ea3
JM		 3000 /*
3001 * Write data segments in reverse order, so as to
3002 * overwrite cacheline stamp last within each
3003 * cacheline. This avoids issues with WQE
3004 * prefetching.
3005 */
225c7b1f 3006
6e694ea3
JM		 3007 dseg = wqe;
3008 dseg += wr->num_sge - 1;
3009 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
225c7b1f
RD		 3010
3011 /* Add one more inline data segment for ICRC for MLX sends */
1ffeb2eb
JM		 3012 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
3013 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
3014 qp->mlx4_ib_qp_type &
3015 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6e694ea3 3016 set_mlx_icrc_seg(dseg + 1);
225c7b1f
RD		 3017 size += sizeof (struct mlx4_wqe_data_seg) / 16;
3018 }
3019
6e694ea3
JM		 3020 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3021 set_data_seg(dseg, wr->sg_list + i);
3022
0fd7e1d8
RD		 3023 /*
3024 * Possibly overwrite stamping in cacheline with LSO
3025 * segment only after making sure all data segments
3026 * are written.
3027 */
3028 wmb();
3029 *lso_wqe = lso_hdr_sz;
3030
225c7b1f
RD		 3031 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
3032 MLX4_WQE_CTRL_FENCE : 0) | size;
3033
3034 /*
3035 * Make sure descriptor is fully written before
3036 * setting ownership bit (because HW can start
3037 * executing as soon as we do).
3038 */
3039 wmb();
3040
59b0ed12 3041 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
4ba6b8ea 3042 *bad_wr = wr;
225c7b1f
RD		 3043 err = -EINVAL;
3044 goto out;
3045 }
3046
3047 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
417608c2 3048 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
0e6e7416 3049
ea54b10c
JM		 3050 stamp = ind + qp->sq_spare_wqes;
3051 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
3052
0e6e7416
RD		 3053 /*
3054 * We can improve latency by not stamping the last
3055 * send queue WQE until after ringing the doorbell, so
3056 * only stamp here if there are still more WQEs to post.
ea54b10c
JM		 3057 *
3058 * Same optimization applies to padding with NOP wqe
3059 * in case of WQE shrinking (used to prevent wrap-around
3060 * in the middle of WR).
0e6e7416 3061 */
ea54b10c
JM		 3062 if (wr->next) {
3063 stamp_send_wqe(qp, stamp, size * 16);
3064 ind = pad_wraparound(qp, ind);
3065 }
225c7b1f
RD		 3066 }
3067
3068out:
3069 if (likely(nreq)) {
3070 qp->sq.head += nreq;
3071
3072 /*
3073 * Make sure that descriptors are written before
3074 * doorbell record.
3075 */
3076 wmb();
3077
3078 writel(qp->doorbell_qpn,
3079 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3080
3081 /*
3082 * Make sure doorbells don't leak out of SQ spinlock
3083 * and reach the HCA out of order.
3084 */
3085 mmiowb();
0e6e7416 3086
ea54b10c
JM		 3087 stamp_send_wqe(qp, stamp, size * 16);
3088
3089 ind = pad_wraparound(qp, ind);
3090 qp->sq_next_wqe = ind;
225c7b1f
RD		 3091 }
3092
96db0e03 3093 spin_unlock_irqrestore(&qp->sq.lock, flags);
225c7b1f
RD		 3094
3095 return err;
3096}
3097
3098int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3099 struct ib_recv_wr **bad_wr)
3100{
3101 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3102 struct mlx4_wqe_data_seg *scat;
3103 unsigned long flags;
3104 int err = 0;
3105 int nreq;
3106 int ind;
1ffeb2eb 3107 int max_gs;
225c7b1f 3108 int i;
35f05dab 3109 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3110
1ffeb2eb 3111 max_gs = qp->rq.max_gs;
225c7b1f
RD		 3112 spin_lock_irqsave(&qp->rq.lock, flags);
3113
35f05dab
YH		 3114 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3115 err = -EIO;
3116 *bad_wr = wr;
3117 nreq = 0;
3118 goto out;
3119 }
3120
0e6e7416 3121 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3122
3123 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2b946077 3124 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
225c7b1f
RD		 3125 err = -ENOMEM;
3126 *bad_wr = wr;
3127 goto out;
3128 }
3129
3130 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3131 err = -EINVAL;
3132 *bad_wr = wr;
3133 goto out;
3134 }
3135
3136 scat = get_recv_wqe(qp, ind);
3137
1ffeb2eb
JM		 3138 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3139 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3140 ib_dma_sync_single_for_device(ibqp->device,
3141 qp->sqp_proxy_rcv[ind].map,
3142 sizeof (struct mlx4_ib_proxy_sqp_hdr),
3143 DMA_FROM_DEVICE);
3144 scat->byte_count =
3145 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3146 /* use dma lkey from upper layer entry */
3147 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3148 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3149 scat++;
3150 max_gs--;
3151 }
3152
2242fa4f
RD		 3153 for (i = 0; i < wr->num_sge; ++i)
3154 __set_data_seg(scat + i, wr->sg_list + i);
225c7b1f 3155
1ffeb2eb 3156 if (i < max_gs) {
225c7b1f
RD		 3157 scat[i].byte_count = 0;
3158 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
3159 scat[i].addr = 0;
3160 }
3161
3162 qp->rq.wrid[ind] = wr->wr_id;
3163
0e6e7416 3164 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3165 }
3166
3167out:
3168 if (likely(nreq)) {
3169 qp->rq.head += nreq;
3170
3171 /*
3172 * Make sure that descriptors are written before
3173 * doorbell record.
3174 */
3175 wmb();
3176
3177 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3178 }
3179
3180 spin_unlock_irqrestore(&qp->rq.lock, flags);
3181
3182 return err;
3183}
6a775e2b
JM		 3184
3185static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3186{
3187 switch (mlx4_state) {
3188 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
3189 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
3190 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
3191 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
3192 case MLX4_QP_STATE_SQ_DRAINING:
3193 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
3194 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
3195 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
3196 default: return -1;
3197 }
3198}
3199
3200static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3201{
3202 switch (mlx4_mig_state) {
3203 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
3204 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
3205 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3206 default: return -1;
3207 }
3208}
3209
3210static int to_ib_qp_access_flags(int mlx4_flags)
3211{
3212 int ib_flags = 0;
3213
3214 if (mlx4_flags & MLX4_QP_BIT_RRE)
3215 ib_flags |= IB_ACCESS_REMOTE_READ;
3216 if (mlx4_flags & MLX4_QP_BIT_RWE)
3217 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3218 if (mlx4_flags & MLX4_QP_BIT_RAE)
3219 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3220
3221 return ib_flags;
3222}
3223
4c3eb3ca 3224static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
6a775e2b
JM		 3225 struct mlx4_qp_path *path)
3226{
4c3eb3ca
EC		 3227 struct mlx4_dev *dev = ibdev->dev;
3228 int is_eth;
3229
8fcea95a 3230 memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
6a775e2b
JM		 3231 ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1;
3232
3233 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
3234 return;
3235
4c3eb3ca
EC		 3236 is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
3237 IB_LINK_LAYER_ETHERNET;
3238 if (is_eth)
3239 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
3240 ((path->sched_queue & 4) << 1);
3241 else
3242 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
3243
6a775e2b 3244 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
6a775e2b
JM		 3245 ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
3246 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
3247 ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
3248 if (ib_ah_attr->ah_flags) {
3249 ib_ah_attr->grh.sgid_index = path->mgid_index;
3250 ib_ah_attr->grh.hop_limit = path->hop_limit;
3251 ib_ah_attr->grh.traffic_class =
3252 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3253 ib_ah_attr->grh.flow_label =
586bb586 3254 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
6a775e2b
JM		 3255 memcpy(ib_ah_attr->grh.dgid.raw,
3256 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
3257 }
3258}
3259
3260int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3261 struct ib_qp_init_attr *qp_init_attr)
3262{
3263 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3264 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3265 struct mlx4_qp_context context;
3266 int mlx4_state;
0df67030
DB		 3267 int err = 0;
3268
3269 mutex_lock(&qp->mutex);
6a775e2b
JM		 3270
3271 if (qp->state == IB_QPS_RESET) {
3272 qp_attr->qp_state = IB_QPS_RESET;
3273 goto done;
3274 }
3275
3276 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
0df67030
DB		 3277 if (err) {
3278 err = -EINVAL;
3279 goto out;
3280 }
6a775e2b
JM		 3281
3282 mlx4_state = be32_to_cpu(context.flags) >> 28;
3283
0df67030
DB		 3284 qp->state = to_ib_qp_state(mlx4_state);
3285 qp_attr->qp_state = qp->state;
6a775e2b
JM		 3286 qp_attr->path_mtu = context.mtu_msgmax >> 5;
3287 qp_attr->path_mig_state =
3288 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3289 qp_attr->qkey = be32_to_cpu(context.qkey);
3290 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3291 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
3292 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
3293 qp_attr->qp_access_flags =
3294 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3295
3296 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4c3eb3ca
EC		 3297 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3298 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
6a775e2b
JM		 3299 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
3300 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
3301 }
3302
3303 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1c27cb71
JM		 3304 if (qp_attr->qp_state == IB_QPS_INIT)
3305 qp_attr->port_num = qp->port;
3306 else
3307 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
6a775e2b
JM		 3308
3309 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3310 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3311
3312 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3313
3314 qp_attr->max_dest_rd_atomic =
3315 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3316 qp_attr->min_rnr_timer =
3317 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3318 qp_attr->timeout = context.pri_path.ackto >> 3;
3319 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
3320 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
3321 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
3322
3323done:
3324 qp_attr->cur_qp_state = qp_attr->qp_state;
7f5eb9bb
RD		 3325 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
3326 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
3327
6a775e2b 3328 if (!ibqp->uobject) {
7f5eb9bb
RD		 3329 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
3330 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3331 } else {
3332 qp_attr->cap.max_send_wr = 0;
3333 qp_attr->cap.max_send_sge = 0;
6a775e2b
JM		 3334 }
3335
7f5eb9bb
RD		 3336 /*
3337 * We don't support inline sends for kernel QPs (yet), and we
3338 * don't know what userspace's value should be.
3339 */
3340 qp_attr->cap.max_inline_data = 0;
3341
3342 qp_init_attr->cap = qp_attr->cap;
3343
521e575b
RL		 3344 qp_init_attr->create_flags = 0;
3345 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3346 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3347
3348 if (qp->flags & MLX4_IB_QP_LSO)
3349 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
3350
c1c98501
MB		 3351 if (qp->flags & MLX4_IB_QP_NETIF)
3352 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
3353
46db567d
DB		 3354 qp_init_attr->sq_sig_type =
3355 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
3356 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3357
0df67030
DB		 3358out:
3359 mutex_unlock(&qp->mutex);
3360 return err;
6a775e2b
JM		 3361}
3362
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