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[mirror_ubuntu-jammy-kernel.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
ea54b10c 34#include <linux/log2.h>
1049f138 35#include <linux/etherdevice.h>
3ef967a4 36#include <net/ip.h>
5a0e3ad6 37#include <linux/slab.h>
fa417f7b 38#include <linux/netdevice.h>
ea54b10c 39
225c7b1f
RD		 40#include <rdma/ib_cache.h>
41#include <rdma/ib_pack.h>
4c3eb3ca 42#include <rdma/ib_addr.h>
1ffeb2eb 43#include <rdma/ib_mad.h>
225c7b1f 44
2f48485d 45#include <linux/mlx4/driver.h>
225c7b1f
RD		 46#include <linux/mlx4/qp.h>
47
48#include "mlx4_ib.h"
9ce28a20 49#include <rdma/mlx4-abi.h>
225c7b1f 50
35f05dab
YH		 51static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
52 struct mlx4_ib_cq *recv_cq);
53static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
54 struct mlx4_ib_cq *recv_cq);
3078f5f1 55static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state);
35f05dab 56
225c7b1f
RD		 57enum {
58 MLX4_IB_ACK_REQ_FREQ = 8,
59};
60
61enum {
62 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
fa417f7b
EC		 63 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
64 MLX4_IB_LINK_TYPE_IB = 0,
65 MLX4_IB_LINK_TYPE_ETH = 1
225c7b1f
RD		 66};
67
68enum {
69 /*
fa417f7b 70 * Largest possible UD header: send with GRH and immediate
4c3eb3ca
EC		 71 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
72 * tag. (LRH would only use 8 bytes, so Ethernet is the
73 * biggest case)
225c7b1f 74 */
4c3eb3ca 75 MLX4_IB_UD_HEADER_SIZE = 82,
417608c2 76 MLX4_IB_LSO_HEADER_SPARE = 128,
225c7b1f
RD		 77};
78
79struct mlx4_ib_sqp {
80 struct mlx4_ib_qp qp;
81 int pkey_index;
82 u32 qkey;
83 u32 send_psn;
84 struct ib_ud_header ud_header;
85 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
e1b866c6 86 struct ib_qp *roce_v2_gsi;
225c7b1f
RD		 87};
88
83904132 89enum {
417608c2
EC		 90 MLX4_IB_MIN_SQ_STRIDE = 6,
91 MLX4_IB_CACHE_LINE_SIZE = 64,
83904132
JM		 92};
93
3987a2d3
OG		 94enum {
95 MLX4_RAW_QP_MTU = 7,
96 MLX4_RAW_QP_MSGMAX = 31,
97};
98
297e0dad
MS		 99#ifndef ETH_ALEN
100#define ETH_ALEN 6
101#endif
297e0dad 102
225c7b1f 103static const __be32 mlx4_ib_opcode[] = {
6fa8f719
VS		 104 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
105 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
106 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
107 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
108 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
109 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
110 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
111 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
112 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
113 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
1b2cd0fc 114 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
6fa8f719
VS		 115 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
116 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
225c7b1f
RD		 117};
118
400b1ebc
GL		 119enum mlx4_ib_source_type {
120 MLX4_IB_QP_SRC = 0,
121 MLX4_IB_RWQ_SRC = 1,
122};
123
225c7b1f
RD		 124static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
125{
126 return container_of(mqp, struct mlx4_ib_sqp, qp);
127}
128
1ffeb2eb
JM		 129static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
130{
131 if (!mlx4_is_master(dev->dev))
132 return 0;
133
47605df9
JM		 134 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
135 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
136 8 * MLX4_MFUNC_MAX;
1ffeb2eb
JM		 137}
138
225c7b1f
RD		 139static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
140{
47605df9
JM		 141 int proxy_sqp = 0;
142 int real_sqp = 0;
143 int i;
144 /* PPF or Native -- real SQP */
145 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
146 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
147 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
148 if (real_sqp)
149 return 1;
150 /* VF or PF -- proxy SQP */
151 if (mlx4_is_mfunc(dev->dev)) {
152 for (i = 0; i < dev->dev->caps.num_ports; i++) {
153 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
154 qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
155 proxy_sqp = 1;
156 break;
157 }
158 }
159 }
e1b866c6
MS		 160 if (proxy_sqp)
161 return 1;
162
163 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP);
225c7b1f
RD		 164}
165
1ffeb2eb 166/* used for INIT/CLOSE port logic */
225c7b1f
RD		 167static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
168{
47605df9
JM		 169 int proxy_qp0 = 0;
170 int real_qp0 = 0;
171 int i;
172 /* PPF or Native -- real QP0 */
173 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
174 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
175 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
176 if (real_qp0)
177 return 1;
178 /* VF or PF -- proxy QP0 */
179 if (mlx4_is_mfunc(dev->dev)) {
180 for (i = 0; i < dev->dev->caps.num_ports; i++) {
181 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
182 proxy_qp0 = 1;
183 break;
184 }
185 }
186 }
187 return proxy_qp0;
225c7b1f
RD		 188}
189
190static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
191{
1c69fc2a 192 return mlx4_buf_offset(&qp->buf, offset);
225c7b1f
RD		 193}
194
195static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
196{
197 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
198}
199
200static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
201{
202 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
203}
204
0e6e7416
RD		 205/*
206 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
ea54b10c
JM		 207 * first four bytes of every 64 byte chunk with
208 * 0x7FFFFFF | (invalid_ownership_value << 31).
209 *
210 * When the max work request size is less than or equal to the WQE
211 * basic block size, as an optimization, we can stamp all WQEs with
212 * 0xffffffff, and skip the very first chunk of each WQE.
0e6e7416 213 */
ea54b10c 214static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
0e6e7416 215{
d2ae16d5 216 __be32 *wqe;
0e6e7416 217 int i;
ea54b10c
JM		 218 int s;
219 int ind;
220 void *buf;
221 __be32 stamp;
9670e553 222 struct mlx4_wqe_ctrl_seg *ctrl;
ea54b10c 223
ea54b10c 224 if (qp->sq_max_wqes_per_wr > 1) {
9670e553 225 s = roundup(size, 1U << qp->sq.wqe_shift);
ea54b10c
JM		 226 for (i = 0; i < s; i += 64) {
227 ind = (i >> qp->sq.wqe_shift) + n;
228 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
229 cpu_to_be32(0xffffffff);
230 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
231 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
232 *wqe = stamp;
233 }
234 } else {
9670e553 235 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
224e92e0 236 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4;
ea54b10c
JM		 237 for (i = 64; i < s; i += 64) {
238 wqe = buf + i;
d2ae16d5 239 *wqe = cpu_to_be32(0xffffffff);
ea54b10c
JM		 240 }
241 }
242}
243
244static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
245{
246 struct mlx4_wqe_ctrl_seg *ctrl;
247 struct mlx4_wqe_inline_seg *inl;
248 void *wqe;
249 int s;
250
251 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
252 s = sizeof(struct mlx4_wqe_ctrl_seg);
253
254 if (qp->ibqp.qp_type == IB_QPT_UD) {
255 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
256 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
257 memset(dgram, 0, sizeof *dgram);
258 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
259 s += sizeof(struct mlx4_wqe_datagram_seg);
260 }
261
262 /* Pad the remainder of the WQE with an inline data segment. */
263 if (size > s) {
264 inl = wqe + s;
265 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
266 }
267 ctrl->srcrb_flags = 0;
224e92e0 268 ctrl->qpn_vlan.fence_size = size / 16;
ea54b10c
JM		 269 /*
270 * Make sure descriptor is fully written before setting ownership bit
271 * (because HW can start executing as soon as we do).
272 */
273 wmb();
274
275 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
276 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
0e6e7416 277
ea54b10c
JM		 278 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
279}
280
281/* Post NOP WQE to prevent wrap-around in the middle of WR */
282static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
283{
284 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
285 if (unlikely(s < qp->sq_max_wqes_per_wr)) {
286 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
287 ind += s;
288 }
289 return ind;
0e6e7416
RD		 290}
291
225c7b1f
RD		 292static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
293{
294 struct ib_event event;
295 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
296
297 if (type == MLX4_EVENT_TYPE_PATH_MIG)
298 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
299
300 if (ibqp->event_handler) {
301 event.device = ibqp->device;
302 event.element.qp = ibqp;
303 switch (type) {
304 case MLX4_EVENT_TYPE_PATH_MIG:
305 event.event = IB_EVENT_PATH_MIG;
306 break;
307 case MLX4_EVENT_TYPE_COMM_EST:
308 event.event = IB_EVENT_COMM_EST;
309 break;
310 case MLX4_EVENT_TYPE_SQ_DRAINED:
311 event.event = IB_EVENT_SQ_DRAINED;
312 break;
313 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
314 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
315 break;
316 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
317 event.event = IB_EVENT_QP_FATAL;
318 break;
319 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
320 event.event = IB_EVENT_PATH_MIG_ERR;
321 break;
322 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
323 event.event = IB_EVENT_QP_REQ_ERR;
324 break;
325 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
326 event.event = IB_EVENT_QP_ACCESS_ERR;
327 break;
328 default:
987c8f8f 329 pr_warn("Unexpected event type %d "
225c7b1f
RD		 330 "on QP %06x\n", type, qp->qpn);
331 return;
332 }
333
334 ibqp->event_handler(&event, ibqp->qp_context);
335 }
336}
337
400b1ebc
GL		 338static void mlx4_ib_wq_event(struct mlx4_qp *qp, enum mlx4_event type)
339{
340 pr_warn_ratelimited("Unexpected event type %d on WQ 0x%06x. Events are not supported for WQs\n",
341 type, qp->qpn);
342}
343
1ffeb2eb 344static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
225c7b1f
RD		 345{
346 /*
347 * UD WQEs must have a datagram segment.
348 * RC and UC WQEs might have a remote address segment.
349 * MLX WQEs need two extra inline data segments (for the UD
350 * header and space for the ICRC).
351 */
352 switch (type) {
1ffeb2eb 353 case MLX4_IB_QPT_UD:
225c7b1f 354 return sizeof (struct mlx4_wqe_ctrl_seg) +
b832be1e 355 sizeof (struct mlx4_wqe_datagram_seg) +
417608c2 356 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
1ffeb2eb
JM		 357 case MLX4_IB_QPT_PROXY_SMI_OWNER:
358 case MLX4_IB_QPT_PROXY_SMI:
359 case MLX4_IB_QPT_PROXY_GSI:
360 return sizeof (struct mlx4_wqe_ctrl_seg) +
361 sizeof (struct mlx4_wqe_datagram_seg) + 64;
362 case MLX4_IB_QPT_TUN_SMI_OWNER:
363 case MLX4_IB_QPT_TUN_GSI:
364 return sizeof (struct mlx4_wqe_ctrl_seg) +
365 sizeof (struct mlx4_wqe_datagram_seg);
366
367 case MLX4_IB_QPT_UC:
225c7b1f
RD		 368 return sizeof (struct mlx4_wqe_ctrl_seg) +
369 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb 370 case MLX4_IB_QPT_RC:
225c7b1f 371 return sizeof (struct mlx4_wqe_ctrl_seg) +
f2940e2c 372 sizeof (struct mlx4_wqe_masked_atomic_seg) +
225c7b1f 373 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb
JM		 374 case MLX4_IB_QPT_SMI:
375 case MLX4_IB_QPT_GSI:
225c7b1f
RD		 376 return sizeof (struct mlx4_wqe_ctrl_seg) +
377 ALIGN(MLX4_IB_UD_HEADER_SIZE +
e61ef241
RD		 378 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
379 MLX4_INLINE_ALIGN) *
225c7b1f
RD		 380 sizeof (struct mlx4_wqe_inline_seg),
381 sizeof (struct mlx4_wqe_data_seg)) +
382 ALIGN(4 +
383 sizeof (struct mlx4_wqe_inline_seg),
384 sizeof (struct mlx4_wqe_data_seg));
385 default:
386 return sizeof (struct mlx4_wqe_ctrl_seg);
387 }
388}
389
2446304d 390static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
ea30b966
MG		 391 int is_user, int has_rq, struct mlx4_ib_qp *qp,
392 u32 inl_recv_sz)
225c7b1f 393{
2446304d 394 /* Sanity check RQ size before proceeding */
fc2d0044
SG		 395 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
396 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
2446304d
EC		 397 return -EINVAL;
398
0a1405da 399 if (!has_rq) {
ea30b966 400 if (cap->max_recv_wr || inl_recv_sz)
a4cd7ed8 401 return -EINVAL;
2446304d 402
0e6e7416 403 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
a4cd7ed8 404 } else {
ea30b966
MG		 405 u32 max_inl_recv_sz = dev->dev->caps.max_rq_sg *
406 sizeof(struct mlx4_wqe_data_seg);
407 u32 wqe_size;
408
a4cd7ed8 409 /* HW requires >= 1 RQ entry with >= 1 gather entry */
ea30b966
MG		 410 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge ||
411 inl_recv_sz > max_inl_recv_sz))
a4cd7ed8
RD		 412 return -EINVAL;
413
0e6e7416 414 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
42c059ea 415 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
ea30b966
MG		 416 wqe_size = qp->rq.max_gs * sizeof(struct mlx4_wqe_data_seg);
417 qp->rq.wqe_shift = ilog2(max_t(u32, wqe_size, inl_recv_sz));
a4cd7ed8 418 }
2446304d 419
fc2d0044
SG		 420 /* leave userspace return values as they were, so as not to break ABI */
421 if (is_user) {
422 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
423 cap->max_recv_sge = qp->rq.max_gs;
424 } else {
425 cap->max_recv_wr = qp->rq.max_post =
426 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
427 cap->max_recv_sge = min(qp->rq.max_gs,
428 min(dev->dev->caps.max_sq_sg,
429 dev->dev->caps.max_rq_sg));
430 }
2446304d
EC		 431
432 return 0;
433}
434
435static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
73898db0
HA		 436 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp,
437 bool shrink_wqe)
2446304d 438{
ea54b10c
JM		 439 int s;
440
2446304d 441 /* Sanity check SQ size before proceeding */
fc2d0044
SG		 442 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
443 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
b832be1e 444 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
225c7b1f
RD		 445 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
446 return -EINVAL;
447
448 /*
449 * For MLX transport we need 2 extra S/G entries:
450 * one for the header and one for the checksum at the end
451 */
1ffeb2eb
JM		 452 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
453 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
225c7b1f
RD		 454 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
455 return -EINVAL;
456
ea54b10c
JM		 457 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
458 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
b832be1e 459 send_wqe_overhead(type, qp->flags);
225c7b1f 460
cd155c1c
RD		 461 if (s > dev->dev->caps.max_sq_desc_sz)
462 return -EINVAL;
463
0e6e7416 464 /*
ea54b10c
JM		 465 * Hermon supports shrinking WQEs, such that a single work
466 * request can include multiple units of 1 << wqe_shift. This
467 * way, work requests can differ in size, and do not have to
468 * be a power of 2 in size, saving memory and speeding up send
469 * WR posting. Unfortunately, if we do this then the
470 * wqe_index field in CQEs can't be used to look up the WR ID
471 * anymore, so we do this only if selective signaling is off.
472 *
473 * Further, on 32-bit platforms, we can't use vmap() to make
af901ca1 474 * the QP buffer virtually contiguous. Thus we have to use
ea54b10c
JM		 475 * constant-sized WRs to make sure a WR is always fully within
476 * a single page-sized chunk.
477 *
478 * Finally, we use NOP work requests to pad the end of the
479 * work queue, to avoid wrap-around in the middle of WR. We
480 * set NEC bit to avoid getting completions with error for
481 * these NOP WRs, but since NEC is only supported starting
482 * with firmware 2.2.232, we use constant-sized WRs for older
483 * firmware.
484 *
485 * And, since MLX QPs only support SEND, we use constant-sized
486 * WRs in this case.
487 *
488 * We look for the smallest value of wqe_shift such that the
489 * resulting number of wqes does not exceed device
490 * capabilities.
491 *
492 * We set WQE size to at least 64 bytes, this way stamping
493 * invalidates each WQE.
0e6e7416 494 */
73898db0 495 if (shrink_wqe && dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
ea54b10c 496 qp->sq_signal_bits && BITS_PER_LONG == 64 &&
1ffeb2eb
JM		 497 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
498 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
499 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
ea54b10c
JM		 500 qp->sq.wqe_shift = ilog2(64);
501 else
502 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
503
504 for (;;) {
ea54b10c
JM		 505 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
506
507 /*
508 * We need to leave 2 KB + 1 WR of headroom in the SQ to
509 * allow HW to prefetch.
510 */
511 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
512 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
513 qp->sq_max_wqes_per_wr +
514 qp->sq_spare_wqes);
515
516 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
517 break;
518
519 if (qp->sq_max_wqes_per_wr <= 1)
520 return -EINVAL;
521
522 ++qp->sq.wqe_shift;
523 }
524
cd155c1c
RD		 525 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
526 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
b832be1e
EC		 527 send_wqe_overhead(type, qp->flags)) /
528 sizeof (struct mlx4_wqe_data_seg);
0e6e7416
RD		 529
530 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
531 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
225c7b1f
RD		 532 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
533 qp->rq.offset = 0;
0e6e7416 534 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
225c7b1f 535 } else {
0e6e7416 536 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
225c7b1f
RD		 537 qp->sq.offset = 0;
538 }
539
ea54b10c
JM		 540 cap->max_send_wr = qp->sq.max_post =
541 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
cd155c1c
RD		 542 cap->max_send_sge = min(qp->sq.max_gs,
543 min(dev->dev->caps.max_sq_sg,
544 dev->dev->caps.max_rq_sg));
54e95f8d
RD		 545 /* We don't support inline sends for kernel QPs (yet) */
546 cap->max_inline_data = 0;
225c7b1f
RD		 547
548 return 0;
549}
550
83904132
JM		 551static int set_user_sq_size(struct mlx4_ib_dev *dev,
552 struct mlx4_ib_qp *qp,
2446304d
EC		 553 struct mlx4_ib_create_qp *ucmd)
554{
83904132
JM		 555 /* Sanity check SQ size before proceeding */
556 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
557 ucmd->log_sq_stride >
558 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
559 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
560 return -EINVAL;
561
0e6e7416 562 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
2446304d
EC		 563 qp->sq.wqe_shift = ucmd->log_sq_stride;
564
0e6e7416
RD		 565 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
566 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
2446304d
EC		 567
568 return 0;
569}
570
1ffeb2eb
JM		 571static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
572{
573 int i;
574
575 qp->sqp_proxy_rcv =
576 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
577 GFP_KERNEL);
578 if (!qp->sqp_proxy_rcv)
579 return -ENOMEM;
580 for (i = 0; i < qp->rq.wqe_cnt; i++) {
581 qp->sqp_proxy_rcv[i].addr =
582 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
583 GFP_KERNEL);
584 if (!qp->sqp_proxy_rcv[i].addr)
585 goto err;
586 qp->sqp_proxy_rcv[i].map =
587 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
588 sizeof (struct mlx4_ib_proxy_sqp_hdr),
589 DMA_FROM_DEVICE);
cc47d369
SO		 590 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
591 kfree(qp->sqp_proxy_rcv[i].addr);
592 goto err;
593 }
1ffeb2eb
JM		 594 }
595 return 0;
596
597err:
598 while (i > 0) {
599 --i;
600 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
601 sizeof (struct mlx4_ib_proxy_sqp_hdr),
602 DMA_FROM_DEVICE);
603 kfree(qp->sqp_proxy_rcv[i].addr);
604 }
605 kfree(qp->sqp_proxy_rcv);
606 qp->sqp_proxy_rcv = NULL;
607 return -ENOMEM;
608}
609
610static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
611{
612 int i;
613
614 for (i = 0; i < qp->rq.wqe_cnt; i++) {
615 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
616 sizeof (struct mlx4_ib_proxy_sqp_hdr),
617 DMA_FROM_DEVICE);
618 kfree(qp->sqp_proxy_rcv[i].addr);
619 }
620 kfree(qp->sqp_proxy_rcv);
621}
622
0a1405da
SH		 623static int qp_has_rq(struct ib_qp_init_attr *attr)
624{
625 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
626 return 0;
627
628 return !attr->srq;
629}
630
99ec41d0
JM		 631static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
632{
633 int i;
634 for (i = 0; i < dev->caps.num_ports; i++) {
635 if (qpn == dev->caps.qp0_proxy[i])
636 return !!dev->caps.qp0_qkey[i];
637 }
638 return 0;
639}
640
7b59f0f9
EBE		 641static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
642 struct mlx4_ib_qp *qp)
643{
644 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
645 mlx4_counter_free(dev->dev, qp->counter_index->index);
646 list_del(&qp->counter_index->list);
647 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
648
649 kfree(qp->counter_index);
650 qp->counter_index = NULL;
651}
652
3078f5f1
GL		 653static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx,
654 struct ib_qp_init_attr *init_attr,
655 struct mlx4_ib_create_qp_rss *ucmd)
656{
657 rss_ctx->base_qpn_tbl_sz = init_attr->rwq_ind_tbl->ind_tbl[0]->wq_num |
658 (init_attr->rwq_ind_tbl->log_ind_tbl_size << 24);
659
660 if ((ucmd->rx_hash_function == MLX4_IB_RX_HASH_FUNC_TOEPLITZ) &&
661 (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) {
662 memcpy(rss_ctx->rss_key, ucmd->rx_hash_key,
663 MLX4_EN_RSS_KEY_SIZE);
664 } else {
665 pr_debug("RX Hash function is not supported\n");
666 return (-EOPNOTSUPP);
667 }
668
669 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) &&
670 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
671 rss_ctx->flags = MLX4_RSS_IPV4;
672 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) ||
673 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
674 pr_debug("RX Hash fields_mask is not supported - both IPv4 SRC and DST must be set\n");
675 return (-EOPNOTSUPP);
676 }
677
678 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) &&
679 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
680 rss_ctx->flags |= MLX4_RSS_IPV6;
681 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) ||
682 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
683 pr_debug("RX Hash fields_mask is not supported - both IPv6 SRC and DST must be set\n");
684 return (-EOPNOTSUPP);
685 }
686
687 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) &&
688 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
689 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS)) {
690 pr_debug("RX Hash fields_mask for UDP is not supported\n");
691 return (-EOPNOTSUPP);
692 }
693
694 if (rss_ctx->flags & MLX4_RSS_IPV4) {
695 rss_ctx->flags |= MLX4_RSS_UDP_IPV4;
696 } else if (rss_ctx->flags & MLX4_RSS_IPV6) {
697 rss_ctx->flags |= MLX4_RSS_UDP_IPV6;
698 } else {
699 pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n");
700 return (-EOPNOTSUPP);
701 }
702 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) ||
703 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
704 pr_debug("RX Hash fields_mask is not supported - both UDP SRC and DST must be set\n");
705 return (-EOPNOTSUPP);
706 }
707
708 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) &&
709 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
710 if (rss_ctx->flags & MLX4_RSS_IPV4) {
711 rss_ctx->flags |= MLX4_RSS_TCP_IPV4;
712 } else if (rss_ctx->flags & MLX4_RSS_IPV6) {
713 rss_ctx->flags |= MLX4_RSS_TCP_IPV6;
714 } else {
715 pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n");
716 return (-EOPNOTSUPP);
717 }
718
719 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) ||
720 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
721 pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n");
722 return (-EOPNOTSUPP);
723 }
724
725 return 0;
726}
727
728static int create_qp_rss(struct mlx4_ib_dev *dev, struct ib_pd *ibpd,
729 struct ib_qp_init_attr *init_attr,
730 struct mlx4_ib_create_qp_rss *ucmd,
731 struct mlx4_ib_qp *qp)
732{
733 int qpn;
734 int err;
735
736 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
737
738 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 0, qp->mqp.usage);
739 if (err)
740 return err;
741
742 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
743 if (err)
744 goto err_qpn;
745
746 mutex_init(&qp->mutex);
747
748 INIT_LIST_HEAD(&qp->gid_list);
749 INIT_LIST_HEAD(&qp->steering_rules);
750
751 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_ETHERTYPE;
752 qp->state = IB_QPS_RESET;
753
754 /* Set dummy send resources to be compatible with HV and PRM */
755 qp->sq_no_prefetch = 1;
756 qp->sq.wqe_cnt = 1;
757 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
758 qp->buf_size = qp->sq.wqe_cnt << MLX4_IB_MIN_SQ_STRIDE;
759 qp->mtt = (to_mqp(
760 (struct ib_qp *)init_attr->rwq_ind_tbl->ind_tbl[0]))->mtt;
761
762 qp->rss_ctx = kzalloc(sizeof(*qp->rss_ctx), GFP_KERNEL);
763 if (!qp->rss_ctx) {
764 err = -ENOMEM;
765 goto err_qp_alloc;
766 }
767
768 err = set_qp_rss(dev, qp->rss_ctx, init_attr, ucmd);
769 if (err)
770 goto err;
771
772 return 0;
773
774err:
775 kfree(qp->rss_ctx);
776
777err_qp_alloc:
778 mlx4_qp_remove(dev->dev, &qp->mqp);
779 mlx4_qp_free(dev->dev, &qp->mqp);
780
781err_qpn:
782 mlx4_qp_release_range(dev->dev, qpn, 1);
783 return err;
784}
785
786static struct ib_qp *_mlx4_ib_create_qp_rss(struct ib_pd *pd,
787 struct ib_qp_init_attr *init_attr,
788 struct ib_udata *udata)
789{
790 struct mlx4_ib_qp *qp;
791 struct mlx4_ib_create_qp_rss ucmd = {};
792 size_t required_cmd_sz;
793 int err;
794
795 if (!udata) {
796 pr_debug("RSS QP with NULL udata\n");
797 return ERR_PTR(-EINVAL);
798 }
799
800 if (udata->outlen)
801 return ERR_PTR(-EOPNOTSUPP);
802
803 required_cmd_sz = offsetof(typeof(ucmd), reserved1) +
804 sizeof(ucmd.reserved1);
805 if (udata->inlen < required_cmd_sz) {
806 pr_debug("invalid inlen\n");
807 return ERR_PTR(-EINVAL);
808 }
809
810 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
811 pr_debug("copy failed\n");
812 return ERR_PTR(-EFAULT);
813 }
814
815 if (ucmd.comp_mask || ucmd.reserved1)
816 return ERR_PTR(-EOPNOTSUPP);
817
818 if (udata->inlen > sizeof(ucmd) &&
819 !ib_is_udata_cleared(udata, sizeof(ucmd),
820 udata->inlen - sizeof(ucmd))) {
821 pr_debug("inlen is not supported\n");
822 return ERR_PTR(-EOPNOTSUPP);
823 }
824
825 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
826 pr_debug("RSS QP with unsupported QP type %d\n",
827 init_attr->qp_type);
828 return ERR_PTR(-EOPNOTSUPP);
829 }
830
831 if (init_attr->create_flags) {
832 pr_debug("RSS QP doesn't support create flags\n");
833 return ERR_PTR(-EOPNOTSUPP);
834 }
835
836 if (init_attr->send_cq || init_attr->cap.max_send_wr) {
837 pr_debug("RSS QP with unsupported send attributes\n");
838 return ERR_PTR(-EOPNOTSUPP);
839 }
840
841 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
842 if (!qp)
843 return ERR_PTR(-ENOMEM);
844
845 qp->pri.vid = 0xFFFF;
846 qp->alt.vid = 0xFFFF;
847
848 err = create_qp_rss(to_mdev(pd->device), pd, init_attr, &ucmd, qp);
849 if (err) {
850 kfree(qp);
851 return ERR_PTR(err);
852 }
853
854 qp->ibqp.qp_num = qp->mqp.qpn;
855
856 return &qp->ibqp;
857}
858
400b1ebc
GL		 859/*
860 * This function allocates a WQN from a range which is consecutive and aligned
861 * to its size. In case the range is full, then it creates a new range and
862 * allocates WQN from it. The new range will be used for following allocations.
863 */
864static int mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext *context,
865 struct mlx4_ib_qp *qp, int range_size, int *wqn)
866{
867 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
868 struct mlx4_wqn_range *range;
869 int err = 0;
870
871 mutex_lock(&context->wqn_ranges_mutex);
872
873 range = list_first_entry_or_null(&context->wqn_ranges_list,
874 struct mlx4_wqn_range, list);
875
876 if (!range || (range->refcount == range->size) || range->dirty) {
877 range = kzalloc(sizeof(*range), GFP_KERNEL);
878 if (!range) {
879 err = -ENOMEM;
880 goto out;
881 }
882
883 err = mlx4_qp_reserve_range(dev->dev, range_size,
884 range_size, &range->base_wqn, 0,
885 qp->mqp.usage);
886 if (err) {
887 kfree(range);
888 goto out;
889 }
890
891 range->size = range_size;
892 list_add(&range->list, &context->wqn_ranges_list);
893 } else if (range_size != 1) {
894 /*
895 * Requesting a new range (>1) when last range is still open, is
896 * not valid.
897 */
898 err = -EINVAL;
899 goto out;
900 }
901
902 qp->wqn_range = range;
903
904 *wqn = range->base_wqn + range->refcount;
905
906 range->refcount++;
907
908out:
909 mutex_unlock(&context->wqn_ranges_mutex);
910
911 return err;
912}
913
914static void mlx4_ib_release_wqn(struct mlx4_ib_ucontext *context,
915 struct mlx4_ib_qp *qp, bool dirty_release)
916{
917 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
918 struct mlx4_wqn_range *range;
919
920 mutex_lock(&context->wqn_ranges_mutex);
921
922 range = qp->wqn_range;
923
924 range->refcount--;
925 if (!range->refcount) {
926 mlx4_qp_release_range(dev->dev, range->base_wqn,
927 range->size);
928 list_del(&range->list);
929 kfree(range);
930 } else if (dirty_release) {
931 /*
932 * A range which one of its WQNs is destroyed, won't be able to be
933 * reused for further WQN allocations.
934 * The next created WQ will allocate a new range.
935 */
936 range->dirty = 1;
937 }
938
939 mutex_unlock(&context->wqn_ranges_mutex);
940}
941
225c7b1f 942static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
400b1ebc 943 enum mlx4_ib_source_type src,
225c7b1f 944 struct ib_qp_init_attr *init_attr,
8900b894
LR		 945 struct ib_udata *udata, int sqpn,
946 struct mlx4_ib_qp **caller_qp)
225c7b1f 947{
a3cdcbfa 948 int qpn;
225c7b1f 949 int err;
73898db0 950 struct ib_qp_cap backup_cap;
b42dde47 951 struct mlx4_ib_sqp *sqp = NULL;
1ffeb2eb
JM		 952 struct mlx4_ib_qp *qp;
953 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
35f05dab
YH		 954 struct mlx4_ib_cq *mcq;
955 unsigned long flags;
400b1ebc 956 int range_size = 0;
1ffeb2eb
JM		 957
958 /* When tunneling special qps, we use a plain UD qp */
959 if (sqpn) {
960 if (mlx4_is_mfunc(dev->dev) &&
961 (!mlx4_is_master(dev->dev) ||
962 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
963 if (init_attr->qp_type == IB_QPT_GSI)
964 qp_type = MLX4_IB_QPT_PROXY_GSI;
99ec41d0
JM		 965 else {
966 if (mlx4_is_master(dev->dev) ||
967 qp0_enabled_vf(dev->dev, sqpn))
968 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
969 else
970 qp_type = MLX4_IB_QPT_PROXY_SMI;
971 }
1ffeb2eb
JM		 972 }
973 qpn = sqpn;
974 /* add extra sg entry for tunneling */
975 init_attr->cap.max_recv_sge++;
976 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
977 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
978 container_of(init_attr,
979 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
980 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
981 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
982 !mlx4_is_master(dev->dev))
983 return -EINVAL;
984 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
985 qp_type = MLX4_IB_QPT_TUN_GSI;
99ec41d0
JM		 986 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
987 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
988 tnl_init->port))
1ffeb2eb
JM		 989 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
990 else
991 qp_type = MLX4_IB_QPT_TUN_SMI;
47605df9
JM		 992 /* we are definitely in the PPF here, since we are creating
993 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
994 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
995 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1ffeb2eb
JM		 996 sqpn = qpn;
997 }
998
999 if (!*caller_qp) {
1000 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
1001 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
1002 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
8900b894 1003 sqp = kzalloc(sizeof(struct mlx4_ib_sqp), GFP_KERNEL);
1ffeb2eb
JM		 1004 if (!sqp)
1005 return -ENOMEM;
1006 qp = &sqp->qp;
2f5bb473
JM		 1007 qp->pri.vid = 0xFFFF;
1008 qp->alt.vid = 0xFFFF;
1ffeb2eb 1009 } else {
8900b894 1010 qp = kzalloc(sizeof(struct mlx4_ib_qp), GFP_KERNEL);
1ffeb2eb
JM		 1011 if (!qp)
1012 return -ENOMEM;
2f5bb473
JM		 1013 qp->pri.vid = 0xFFFF;
1014 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 1015 }
1016 } else
1017 qp = *caller_qp;
1018
1019 qp->mlx4_ib_qp_type = qp_type;
225c7b1f
RD		 1020
1021 mutex_init(&qp->mutex);
1022 spin_lock_init(&qp->sq.lock);
1023 spin_lock_init(&qp->rq.lock);
fa417f7b 1024 INIT_LIST_HEAD(&qp->gid_list);
0ff1fb65 1025 INIT_LIST_HEAD(&qp->steering_rules);
225c7b1f
RD		 1026
1027 qp->state = IB_QPS_RESET;
ea54b10c
JM		 1028 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1029 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
225c7b1f 1030
225c7b1f
RD		 1031
1032 if (pd->uobject) {
400b1ebc
GL		 1033 union {
1034 struct mlx4_ib_create_qp qp;
1035 struct mlx4_ib_create_wq wq;
1036 } ucmd;
1037 size_t copy_len;
1038
1039 copy_len = (src == MLX4_IB_QP_SRC) ?
1040 sizeof(struct mlx4_ib_create_qp) :
1041 min(sizeof(struct mlx4_ib_create_wq), udata->inlen);
225c7b1f 1042
400b1ebc 1043 if (ib_copy_from_udata(&ucmd, udata, copy_len)) {
225c7b1f
RD		 1044 err = -EFAULT;
1045 goto err;
1046 }
1047
400b1ebc
GL		 1048 if (src == MLX4_IB_RWQ_SRC) {
1049 if (ucmd.wq.comp_mask || ucmd.wq.reserved1 ||
1050 ucmd.wq.reserved[0] || ucmd.wq.reserved[1] ||
1051 ucmd.wq.reserved[2]) {
1052 pr_debug("user command isn't supported\n");
1053 err = -EOPNOTSUPP;
1054 goto err;
1055 }
ea30b966 1056
400b1ebc
GL		 1057 if (ucmd.wq.log_range_size >
1058 ilog2(dev->dev->caps.max_rss_tbl_sz)) {
1059 pr_debug("WQN range size must be equal or smaller than %d\n",
1060 dev->dev->caps.max_rss_tbl_sz);
1061 err = -EOPNOTSUPP;
1062 goto err;
1063 }
1064 range_size = 1 << ucmd.wq.log_range_size;
1065 } else {
1066 qp->inl_recv_sz = ucmd.qp.inl_recv_sz;
1067 }
0e6e7416 1068
400b1ebc
GL		 1069 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject,
1070 qp_has_rq(init_attr), qp, qp->inl_recv_sz);
2446304d
EC		 1071 if (err)
1072 goto err;
1073
400b1ebc
GL		 1074 if (src == MLX4_IB_QP_SRC) {
1075 qp->sq_no_prefetch = ucmd.qp.sq_no_prefetch;
1076
1077 err = set_user_sq_size(dev, qp,
1078 (struct mlx4_ib_create_qp *)
1079 &ucmd);
1080 if (err)
1081 goto err;
1082 } else {
1083 qp->sq_no_prefetch = 1;
1084 qp->sq.wqe_cnt = 1;
1085 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
1086 /* Allocated buffer expects to have at least that SQ
1087 * size.
1088 */
1089 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
1090 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
1091 }
1092
1093 qp->umem = ib_umem_get(pd->uobject->context,
1094 (src == MLX4_IB_QP_SRC) ? ucmd.qp.buf_addr :
1095 ucmd.wq.buf_addr, qp->buf_size, 0, 0);
225c7b1f
RD		 1096 if (IS_ERR(qp->umem)) {
1097 err = PTR_ERR(qp->umem);
1098 goto err;
1099 }
1100
1101 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
3e7e1193 1102 qp->umem->page_shift, &qp->mtt);
225c7b1f
RD		 1103 if (err)
1104 goto err_buf;
1105
1106 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
1107 if (err)
1108 goto err_mtt;
1109
0a1405da 1110 if (qp_has_rq(init_attr)) {
02d89b87 1111 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
400b1ebc
GL		 1112 (src == MLX4_IB_QP_SRC) ? ucmd.qp.db_addr :
1113 ucmd.wq.db_addr, &qp->db);
02d89b87
RD		 1114 if (err)
1115 goto err_mtt;
1116 }
f3301870 1117 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
225c7b1f 1118 } else {
ea30b966
MG		 1119 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject,
1120 qp_has_rq(init_attr), qp, 0);
1121 if (err)
1122 goto err;
1123
0e6e7416
RD		 1124 qp->sq_no_prefetch = 0;
1125
b832be1e
EC		 1126 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
1127 qp->flags |= MLX4_IB_QP_LSO;
1128
c1c98501
MB		 1129 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1130 if (dev->steering_support ==
1131 MLX4_STEERING_MODE_DEVICE_MANAGED)
1132 qp->flags |= MLX4_IB_QP_NETIF;
1133 else
1134 goto err;
1135 }
1136
73898db0
HA		 1137 memcpy(&backup_cap, &init_attr->cap, sizeof(backup_cap));
1138 err = set_kernel_sq_size(dev, &init_attr->cap,
1139 qp_type, qp, true);
2446304d
EC		 1140 if (err)
1141 goto err;
1142
0a1405da 1143 if (qp_has_rq(init_attr)) {
8900b894 1144 err = mlx4_db_alloc(dev->dev, &qp->db, 0);
02d89b87
RD		 1145 if (err)
1146 goto err;
225c7b1f 1147
02d89b87
RD		 1148 *qp->db.db = 0;
1149 }
225c7b1f 1150
73898db0 1151 if (mlx4_buf_alloc(dev->dev, qp->buf_size, qp->buf_size,
8900b894 1152 &qp->buf)) {
73898db0
HA		 1153 memcpy(&init_attr->cap, &backup_cap,
1154 sizeof(backup_cap));
1155 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type,
1156 qp, false);
1157 if (err)
1158 goto err_db;
1159
1160 if (mlx4_buf_alloc(dev->dev, qp->buf_size,
8900b894 1161 PAGE_SIZE * 2, &qp->buf)) {
73898db0
HA		 1162 err = -ENOMEM;
1163 goto err_db;
1164 }
225c7b1f
RD		 1165 }
1166
1167 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
1168 &qp->mtt);
1169 if (err)
1170 goto err_buf;
1171
8900b894 1172 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
225c7b1f
RD		 1173 if (err)
1174 goto err_mtt;
1175
e9105cde
LD		 1176 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1177 sizeof(u64), GFP_KERNEL);
1178 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1179 sizeof(u64), GFP_KERNEL);
225c7b1f
RD		 1180 if (!qp->sq.wrid || !qp->rq.wrid) {
1181 err = -ENOMEM;
1182 goto err_wrid;
1183 }
f3301870 1184 qp->mqp.usage = MLX4_RES_USAGE_DRIVER;
225c7b1f
RD		 1185 }
1186
a3cdcbfa 1187 if (sqpn) {
1ffeb2eb
JM		 1188 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1189 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
1190 if (alloc_proxy_bufs(pd->device, qp)) {
1191 err = -ENOMEM;
1192 goto err_wrid;
1193 }
1194 }
400b1ebc
GL		 1195 } else if (src == MLX4_IB_RWQ_SRC) {
1196 err = mlx4_ib_alloc_wqn(to_mucontext(pd->uobject->context), qp,
1197 range_size, &qpn);
1198 if (err)
1199 goto err_wrid;
a3cdcbfa 1200 } else {
ddae0349
EE		 1201 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
1202 * otherwise, the WQE BlueFlame setup flow wrongly causes
1203 * VLAN insertion. */
3987a2d3 1204 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
ddae0349 1205 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
d57febe1
MB		 1206 (init_attr->cap.max_send_wr ?
1207 MLX4_RESERVE_ETH_BF_QP : 0) |
1208 (init_attr->cap.max_recv_wr ?
f3301870
MS		 1209 MLX4_RESERVE_A0_QP : 0),
1210 qp->mqp.usage);
3987a2d3 1211 else
c1c98501
MB		 1212 if (qp->flags & MLX4_IB_QP_NETIF)
1213 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
1214 else
1215 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
f3301870 1216 &qpn, 0, qp->mqp.usage);
a3cdcbfa 1217 if (err)
1ffeb2eb 1218 goto err_proxy;
a3cdcbfa
YP		 1219 }
1220
fbfb6625
EBE		 1221 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1222 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1223
8900b894 1224 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
225c7b1f 1225 if (err)
a3cdcbfa 1226 goto err_qpn;
225c7b1f 1227
0a1405da
SH		 1228 if (init_attr->qp_type == IB_QPT_XRC_TGT)
1229 qp->mqp.qpn |= (1 << 23);
1230
225c7b1f
RD		 1231 /*
1232 * Hardware wants QPN written in big-endian order (after
1233 * shifting) for send doorbell. Precompute this value to save
1234 * a little bit when posting sends.
1235 */
1236 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
1237
400b1ebc
GL		 1238 qp->mqp.event = (src == MLX4_IB_QP_SRC) ? mlx4_ib_qp_event :
1239 mlx4_ib_wq_event;
1240
1ffeb2eb
JM		 1241 if (!*caller_qp)
1242 *caller_qp = qp;
35f05dab
YH		 1243
1244 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1245 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
1246 to_mcq(init_attr->recv_cq));
1247 /* Maintain device to QPs access, needed for further handling
1248 * via reset flow
1249 */
1250 list_add_tail(&qp->qps_list, &dev->qp_list);
1251 /* Maintain CQ to QPs access, needed for further handling
1252 * via reset flow
1253 */
1254 mcq = to_mcq(init_attr->send_cq);
1255 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
1256 mcq = to_mcq(init_attr->recv_cq);
1257 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
1258 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
1259 to_mcq(init_attr->recv_cq));
1260 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1261 return 0;
1262
a3cdcbfa 1263err_qpn:
c1c98501
MB		 1264 if (!sqpn) {
1265 if (qp->flags & MLX4_IB_QP_NETIF)
1266 mlx4_ib_steer_qp_free(dev, qpn, 1);
400b1ebc
GL		 1267 else if (src == MLX4_IB_RWQ_SRC)
1268 mlx4_ib_release_wqn(to_mucontext(pd->uobject->context),
1269 qp, 0);
c1c98501
MB		 1270 else
1271 mlx4_qp_release_range(dev->dev, qpn, 1);
1272 }
1ffeb2eb
JM		 1273err_proxy:
1274 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1275 free_proxy_bufs(pd->device, qp);
225c7b1f 1276err_wrid:
23f1b384 1277 if (pd->uobject) {
0a1405da
SH		 1278 if (qp_has_rq(init_attr))
1279 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
23f1b384 1280 } else {
0ef2f05c
WW		 1281 kvfree(qp->sq.wrid);
1282 kvfree(qp->rq.wrid);
225c7b1f
RD		 1283 }
1284
1285err_mtt:
1286 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1287
1288err_buf:
1289 if (pd->uobject)
1290 ib_umem_release(qp->umem);
1291 else
1292 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1293
1294err_db:
0a1405da 1295 if (!pd->uobject && qp_has_rq(init_attr))
6296883c 1296 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 1297
1298err:
b42dde47
BVA		 1299 if (sqp)
1300 kfree(sqp);
1301 else if (!*caller_qp)
1ffeb2eb 1302 kfree(qp);
225c7b1f
RD		 1303 return err;
1304}
1305
1306static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
1307{
1308 switch (state) {
1309 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
1310 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
1311 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
1312 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
1313 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
1314 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
1315 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
1316 default: return -1;
1317 }
1318}
1319
1320static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 1321 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
225c7b1f 1322{
338a8fad 1323 if (send_cq == recv_cq) {
35f05dab 1324 spin_lock(&send_cq->lock);
338a8fad
RD		 1325 __acquire(&recv_cq->lock);
1326 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
35f05dab 1327 spin_lock(&send_cq->lock);
225c7b1f
RD		 1328 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1329 } else {
35f05dab 1330 spin_lock(&recv_cq->lock);
225c7b1f
RD		 1331 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1332 }
1333}
1334
1335static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 1336 __releases(&send_cq->lock) __releases(&recv_cq->lock)
225c7b1f 1337{
338a8fad
RD		 1338 if (send_cq == recv_cq) {
1339 __release(&recv_cq->lock);
35f05dab 1340 spin_unlock(&send_cq->lock);
338a8fad 1341 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
225c7b1f 1342 spin_unlock(&recv_cq->lock);
35f05dab 1343 spin_unlock(&send_cq->lock);
225c7b1f
RD		 1344 } else {
1345 spin_unlock(&send_cq->lock);
35f05dab 1346 spin_unlock(&recv_cq->lock);
225c7b1f
RD		 1347 }
1348}
1349
fa417f7b
EC		 1350static void del_gid_entries(struct mlx4_ib_qp *qp)
1351{
1352 struct mlx4_ib_gid_entry *ge, *tmp;
1353
1354 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1355 list_del(&ge->list);
1356 kfree(ge);
1357 }
1358}
1359
0a1405da
SH		 1360static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
1361{
1362 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
1363 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
1364 else
1365 return to_mpd(qp->ibqp.pd);
1366}
1367
400b1ebc 1368static void get_cqs(struct mlx4_ib_qp *qp, enum mlx4_ib_source_type src,
0a1405da
SH		 1369 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
1370{
1371 switch (qp->ibqp.qp_type) {
1372 case IB_QPT_XRC_TGT:
1373 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
1374 *recv_cq = *send_cq;
1375 break;
1376 case IB_QPT_XRC_INI:
1377 *send_cq = to_mcq(qp->ibqp.send_cq);
1378 *recv_cq = *send_cq;
1379 break;
1380 default:
400b1ebc
GL		 1381 *recv_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.recv_cq) :
1382 to_mcq(qp->ibwq.cq);
1383 *send_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.send_cq) :
1384 *recv_cq;
0a1405da
SH		 1385 break;
1386 }
1387}
1388
3078f5f1
GL		 1389static void destroy_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1390{
1391 if (qp->state != IB_QPS_RESET) {
1392 int i;
1393
1394 for (i = 0; i < (1 << qp->ibqp.rwq_ind_tbl->log_ind_tbl_size);
1395 i++) {
1396 struct ib_wq *ibwq = qp->ibqp.rwq_ind_tbl->ind_tbl[i];
1397 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1398
1399 mutex_lock(&wq->mutex);
1400
1401 wq->rss_usecnt--;
1402
1403 mutex_unlock(&wq->mutex);
1404 }
1405
1406 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1407 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1408 pr_warn("modify QP %06x to RESET failed.\n",
1409 qp->mqp.qpn);
1410 }
1411
1412 mlx4_qp_remove(dev->dev, &qp->mqp);
1413 mlx4_qp_free(dev->dev, &qp->mqp);
1414 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1415 del_gid_entries(qp);
1416 kfree(qp->rss_ctx);
1417}
1418
225c7b1f 1419static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
400b1ebc 1420 enum mlx4_ib_source_type src, int is_user)
225c7b1f
RD		 1421{
1422 struct mlx4_ib_cq *send_cq, *recv_cq;
35f05dab 1423 unsigned long flags;
225c7b1f 1424
2f5bb473 1425 if (qp->state != IB_QPS_RESET) {
225c7b1f
RD		 1426 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1427 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
987c8f8f 1428 pr_warn("modify QP %06x to RESET failed.\n",
225c7b1f 1429 qp->mqp.qpn);
25476b02 1430 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 1431 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1432 qp->pri.smac = 0;
25476b02 1433 qp->pri.smac_port = 0;
2f5bb473
JM		 1434 }
1435 if (qp->alt.smac) {
1436 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1437 qp->alt.smac = 0;
1438 }
1439 if (qp->pri.vid < 0x1000) {
1440 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1441 qp->pri.vid = 0xFFFF;
1442 qp->pri.candidate_vid = 0xFFFF;
1443 qp->pri.update_vid = 0;
1444 }
1445 if (qp->alt.vid < 0x1000) {
1446 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1447 qp->alt.vid = 0xFFFF;
1448 qp->alt.candidate_vid = 0xFFFF;
1449 qp->alt.update_vid = 0;
1450 }
1451 }
225c7b1f 1452
400b1ebc 1453 get_cqs(qp, src, &send_cq, &recv_cq);
225c7b1f 1454
35f05dab 1455 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1456 mlx4_ib_lock_cqs(send_cq, recv_cq);
1457
35f05dab
YH		 1458 /* del from lists under both locks above to protect reset flow paths */
1459 list_del(&qp->qps_list);
1460 list_del(&qp->cq_send_list);
1461 list_del(&qp->cq_recv_list);
225c7b1f
RD		 1462 if (!is_user) {
1463 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1464 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1465 if (send_cq != recv_cq)
1466 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1467 }
1468
1469 mlx4_qp_remove(dev->dev, &qp->mqp);
1470
1471 mlx4_ib_unlock_cqs(send_cq, recv_cq);
35f05dab 1472 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1473
1474 mlx4_qp_free(dev->dev, &qp->mqp);
a3cdcbfa 1475
c1c98501
MB		 1476 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1477 if (qp->flags & MLX4_IB_QP_NETIF)
1478 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
400b1ebc
GL		 1479 else if (src == MLX4_IB_RWQ_SRC)
1480 mlx4_ib_release_wqn(to_mucontext(
1481 qp->ibwq.uobject->context), qp, 1);
c1c98501
MB		 1482 else
1483 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1484 }
a3cdcbfa 1485
225c7b1f
RD		 1486 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1487
1488 if (is_user) {
400b1ebc
GL		 1489 if (qp->rq.wqe_cnt) {
1490 struct mlx4_ib_ucontext *mcontext = !src ?
1491 to_mucontext(qp->ibqp.uobject->context) :
1492 to_mucontext(qp->ibwq.uobject->context);
1493 mlx4_ib_db_unmap_user(mcontext, &qp->db);
1494 }
225c7b1f
RD		 1495 ib_umem_release(qp->umem);
1496 } else {
0ef2f05c
WW		 1497 kvfree(qp->sq.wrid);
1498 kvfree(qp->rq.wrid);
1ffeb2eb
JM		 1499 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1500 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1501 free_proxy_bufs(&dev->ib_dev, qp);
225c7b1f 1502 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
0a1405da 1503 if (qp->rq.wqe_cnt)
6296883c 1504 mlx4_db_free(dev->dev, &qp->db);
225c7b1f 1505 }
fa417f7b
EC		 1506
1507 del_gid_entries(qp);
225c7b1f
RD		 1508}
1509
47605df9
JM		 1510static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1511{
1512 /* Native or PPF */
1513 if (!mlx4_is_mfunc(dev->dev) ||
1514 (mlx4_is_master(dev->dev) &&
1515 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1516 return dev->dev->phys_caps.base_sqpn +
1517 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1518 attr->port_num - 1;
1519 }
1520 /* PF or VF -- creating proxies */
1521 if (attr->qp_type == IB_QPT_SMI)
1522 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1523 else
1524 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1525}
1526
e1b866c6
MS		 1527static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd,
1528 struct ib_qp_init_attr *init_attr,
1529 struct ib_udata *udata)
225c7b1f 1530{
1ffeb2eb 1531 struct mlx4_ib_qp *qp = NULL;
225c7b1f 1532 int err;
fbfb6625 1533 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
0a1405da 1534 u16 xrcdn = 0;
225c7b1f 1535
3078f5f1
GL		 1536 if (init_attr->rwq_ind_tbl)
1537 return _mlx4_ib_create_qp_rss(pd, init_attr, udata);
1538
521e575b 1539 /*
1ffeb2eb
JM		 1540 * We only support LSO, vendor flag1, and multicast loopback blocking,
1541 * and only for kernel UD QPs.
521e575b 1542 */
1ffeb2eb
JM		 1543 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1544 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
c1c98501
MB		 1545 MLX4_IB_SRIOV_TUNNEL_QP |
1546 MLX4_IB_SRIOV_SQP |
40f2287b 1547 MLX4_IB_QP_NETIF |
8900b894 1548 MLX4_IB_QP_CREATE_ROCE_V2_GSI))
b832be1e 1549 return ERR_PTR(-EINVAL);
521e575b 1550
c1c98501
MB		 1551 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1552 if (init_attr->qp_type != IB_QPT_UD)
1553 return ERR_PTR(-EINVAL);
1554 }
1555
e1b866c6
MS		 1556 if (init_attr->create_flags) {
1557 if (udata && init_attr->create_flags & ~(sup_u_create_flags))
1558 return ERR_PTR(-EINVAL);
1559
1560 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
e1b866c6
MS		 1561 MLX4_IB_QP_CREATE_ROCE_V2_GSI |
1562 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) &&
1563 init_attr->qp_type != IB_QPT_UD) ||
1564 (init_attr->create_flags & MLX4_IB_SRIOV_SQP &&
1565 init_attr->qp_type > IB_QPT_GSI) ||
1566 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI &&
1567 init_attr->qp_type != IB_QPT_GSI))
1568 return ERR_PTR(-EINVAL);
1569 }
b846f25a 1570
225c7b1f 1571 switch (init_attr->qp_type) {
0a1405da
SH		 1572 case IB_QPT_XRC_TGT:
1573 pd = to_mxrcd(init_attr->xrcd)->pd;
1574 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1575 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1576 /* fall through */
1577 case IB_QPT_XRC_INI:
1578 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1579 return ERR_PTR(-ENOSYS);
1580 init_attr->recv_cq = init_attr->send_cq;
1581 /* fall through */
225c7b1f
RD		 1582 case IB_QPT_RC:
1583 case IB_QPT_UC:
3987a2d3 1584 case IB_QPT_RAW_PACKET:
8900b894 1585 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
225c7b1f
RD		 1586 if (!qp)
1587 return ERR_PTR(-ENOMEM);
2f5bb473
JM		 1588 qp->pri.vid = 0xFFFF;
1589 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 1590 /* fall through */
1591 case IB_QPT_UD:
1592 {
400b1ebc
GL		 1593 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC,
1594 init_attr, udata, 0, &qp);
5b420d9c
DB		 1595 if (err) {
1596 kfree(qp);
225c7b1f 1597 return ERR_PTR(err);
5b420d9c 1598 }
225c7b1f
RD		 1599
1600 qp->ibqp.qp_num = qp->mqp.qpn;
0a1405da 1601 qp->xrcdn = xrcdn;
225c7b1f
RD		 1602
1603 break;
1604 }
1605 case IB_QPT_SMI:
1606 case IB_QPT_GSI:
1607 {
e1b866c6
MS		 1608 int sqpn;
1609
225c7b1f 1610 /* Userspace is not allowed to create special QPs: */
0a1405da 1611 if (udata)
225c7b1f 1612 return ERR_PTR(-EINVAL);
e1b866c6 1613 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) {
f3301870
MS		 1614 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev,
1615 1, 1, &sqpn, 0,
1616 MLX4_RES_USAGE_DRIVER);
e1b866c6
MS		 1617
1618 if (res)
1619 return ERR_PTR(res);
1620 } else {
1621 sqpn = get_sqp_num(to_mdev(pd->device), init_attr);
1622 }
225c7b1f 1623
400b1ebc
GL		 1624 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC,
1625 init_attr, udata, sqpn, &qp);
1ffeb2eb 1626 if (err)
225c7b1f 1627 return ERR_PTR(err);
225c7b1f
RD		 1628
1629 qp->port = init_attr->port_num;
e1b866c6
MS		 1630 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 :
1631 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1;
225c7b1f
RD		 1632 break;
1633 }
1634 default:
1635 /* Don't support raw QPs */
1636 return ERR_PTR(-EINVAL);
1637 }
1638
1639 return &qp->ibqp;
1640}
1641
e1b866c6
MS		 1642struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1643 struct ib_qp_init_attr *init_attr,
1644 struct ib_udata *udata) {
1645 struct ib_device *device = pd ? pd->device : init_attr->xrcd->device;
1646 struct ib_qp *ibqp;
1647 struct mlx4_ib_dev *dev = to_mdev(device);
1648
1649 ibqp = _mlx4_ib_create_qp(pd, init_attr, udata);
1650
1651 if (!IS_ERR(ibqp) &&
1652 (init_attr->qp_type == IB_QPT_GSI) &&
1653 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) {
1654 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp)));
1655 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num);
1656
1657 if (is_eth &&
1658 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
1659 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1660 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr);
1661
1662 if (IS_ERR(sqp->roce_v2_gsi)) {
1663 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi));
1664 sqp->roce_v2_gsi = NULL;
1665 } else {
1666 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi));
1667 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP;
1668 }
1669
1670 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1671 }
1672 }
1673 return ibqp;
1674}
1675
1676static int _mlx4_ib_destroy_qp(struct ib_qp *qp)
225c7b1f
RD		 1677{
1678 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1679 struct mlx4_ib_qp *mqp = to_mqp(qp);
1680
1681 if (is_qp0(dev, mqp))
1682 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1683
c482af64
JM		 1684 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI &&
1685 dev->qp1_proxy[mqp->port - 1] == mqp) {
9433c188
MB		 1686 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1687 dev->qp1_proxy[mqp->port - 1] = NULL;
1688 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1689 }
1690
7b59f0f9
EBE		 1691 if (mqp->counter_index)
1692 mlx4_ib_free_qp_counter(dev, mqp);
1693
3078f5f1
GL		 1694 if (qp->rwq_ind_tbl) {
1695 destroy_qp_rss(dev, mqp);
1696 } else {
1697 struct mlx4_ib_pd *pd;
1698
1699 pd = get_pd(mqp);
1700 destroy_qp_common(dev, mqp, MLX4_IB_QP_SRC, !!pd->ibpd.uobject);
1701 }
225c7b1f
RD		 1702
1703 if (is_sqp(dev, mqp))
1704 kfree(to_msqp(mqp));
1705 else
1706 kfree(mqp);
1707
1708 return 0;
1709}
1710
e1b866c6
MS		 1711int mlx4_ib_destroy_qp(struct ib_qp *qp)
1712{
1713 struct mlx4_ib_qp *mqp = to_mqp(qp);
1714
1715 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
1716 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
1717
1718 if (sqp->roce_v2_gsi)
1719 ib_destroy_qp(sqp->roce_v2_gsi);
1720 }
1721
1722 return _mlx4_ib_destroy_qp(qp);
1723}
1724
1ffeb2eb 1725static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
225c7b1f
RD		 1726{
1727 switch (type) {
1ffeb2eb
JM		 1728 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1729 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1730 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1731 case MLX4_IB_QPT_XRC_INI:
1732 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1733 case MLX4_IB_QPT_SMI:
1734 case MLX4_IB_QPT_GSI:
1735 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1736
1737 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1738 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1739 MLX4_QP_ST_MLX : -1);
1740 case MLX4_IB_QPT_PROXY_SMI:
1741 case MLX4_IB_QPT_TUN_SMI:
1742 case MLX4_IB_QPT_PROXY_GSI:
1743 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1744 MLX4_QP_ST_UD : -1);
1745 default: return -1;
225c7b1f
RD		 1746 }
1747}
1748
65adfa91 1749static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1750 int attr_mask)
1751{
1752 u8 dest_rd_atomic;
1753 u32 access_flags;
1754 u32 hw_access_flags = 0;
1755
1756 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1757 dest_rd_atomic = attr->max_dest_rd_atomic;
1758 else
1759 dest_rd_atomic = qp->resp_depth;
1760
1761 if (attr_mask & IB_QP_ACCESS_FLAGS)
1762 access_flags = attr->qp_access_flags;
1763 else
1764 access_flags = qp->atomic_rd_en;
1765
1766 if (!dest_rd_atomic)
1767 access_flags &= IB_ACCESS_REMOTE_WRITE;
1768
1769 if (access_flags & IB_ACCESS_REMOTE_READ)
1770 hw_access_flags |= MLX4_QP_BIT_RRE;
1771 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1772 hw_access_flags |= MLX4_QP_BIT_RAE;
1773 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1774 hw_access_flags |= MLX4_QP_BIT_RWE;
1775
1776 return cpu_to_be32(hw_access_flags);
1777}
1778
65adfa91 1779static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1780 int attr_mask)
1781{
1782 if (attr_mask & IB_QP_PKEY_INDEX)
1783 sqp->pkey_index = attr->pkey_index;
1784 if (attr_mask & IB_QP_QKEY)
1785 sqp->qkey = attr->qkey;
1786 if (attr_mask & IB_QP_SQ_PSN)
1787 sqp->send_psn = attr->sq_psn;
1788}
1789
1790static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1791{
1792 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1793}
1794
90898850
DC		 1795static int _mlx4_set_path(struct mlx4_ib_dev *dev,
1796 const struct rdma_ah_attr *ah,
297e0dad 1797 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
2f5bb473 1798 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
225c7b1f 1799{
4c3eb3ca 1800 int vidx;
297e0dad 1801 int smac_index;
2f5bb473 1802 int err;
297e0dad 1803
d8966fcd
DC		 1804 path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f;
1805 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
1806 if (rdma_ah_get_static_rate(ah)) {
1807 path->static_rate = rdma_ah_get_static_rate(ah) +
1808 MLX4_STAT_RATE_OFFSET;
225c7b1f
RD		 1809 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1810 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1811 --path->static_rate;
1812 } else
1813 path->static_rate = 0;
225c7b1f 1814
d8966fcd
DC		 1815 if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) {
1816 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
1817 int real_sgid_index =
1818 mlx4_ib_gid_index_to_real_index(dev, port,
1819 grh->sgid_index);
5070cd22
MS		 1820
1821 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
987c8f8f 1822 pr_err("sgid_index (%u) too large. max is %d\n",
5070cd22 1823 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
225c7b1f
RD		 1824 return -1;
1825 }
1826
1827 path->grh_mylmc |= 1 << 7;
5070cd22 1828 path->mgid_index = real_sgid_index;
d8966fcd 1829 path->hop_limit = grh->hop_limit;
225c7b1f 1830 path->tclass_flowlabel =
d8966fcd
DC		 1831 cpu_to_be32((grh->traffic_class << 20) |
1832 (grh->flow_label));
1833 memcpy(path->rgid, grh->dgid.raw, 16);
225c7b1f
RD		 1834 }
1835
44c58487 1836 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
d8966fcd 1837 if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH))
fa417f7b
EC		 1838 return -1;
1839
2f5bb473 1840 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
d8966fcd 1841 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3);
4c3eb3ca 1842
297e0dad 1843 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
4c3eb3ca 1844 if (vlan_tag < 0x1000) {
2f5bb473
JM		 1845 if (smac_info->vid < 0x1000) {
1846 /* both valid vlan ids */
1847 if (smac_info->vid != vlan_tag) {
1848 /* different VIDs. unreg old and reg new */
1849 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1850 if (err)
1851 return err;
1852 smac_info->candidate_vid = vlan_tag;
1853 smac_info->candidate_vlan_index = vidx;
1854 smac_info->candidate_vlan_port = port;
1855 smac_info->update_vid = 1;
1856 path->vlan_index = vidx;
1857 } else {
1858 path->vlan_index = smac_info->vlan_index;
1859 }
1860 } else {
1861 /* no current vlan tag in qp */
1862 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1863 if (err)
1864 return err;
1865 smac_info->candidate_vid = vlan_tag;
1866 smac_info->candidate_vlan_index = vidx;
1867 smac_info->candidate_vlan_port = port;
1868 smac_info->update_vid = 1;
1869 path->vlan_index = vidx;
1870 }
297e0dad 1871 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
2f5bb473
JM		 1872 path->fl = 1 << 6;
1873 } else {
1874 /* have current vlan tag. unregister it at modify-qp success */
1875 if (smac_info->vid < 0x1000) {
1876 smac_info->candidate_vid = 0xFFFF;
1877 smac_info->update_vid = 1;
1878 }
4c3eb3ca 1879 }
2f5bb473
JM		 1880
1881 /* get smac_index for RoCE use.
1882 * If no smac was yet assigned, register one.
1883 * If one was already assigned, but the new mac differs,
1884 * unregister the old one and register the new one.
1885 */
25476b02
JM		 1886 if ((!smac_info->smac && !smac_info->smac_port) ||
1887 smac_info->smac != smac) {
2f5bb473
JM		 1888 /* register candidate now, unreg if needed, after success */
1889 smac_index = mlx4_register_mac(dev->dev, port, smac);
1890 if (smac_index >= 0) {
1891 smac_info->candidate_smac_index = smac_index;
1892 smac_info->candidate_smac = smac;
1893 smac_info->candidate_smac_port = port;
1894 } else {
1895 return -EINVAL;
1896 }
1897 } else {
1898 smac_index = smac_info->smac_index;
1899 }
44c58487 1900 memcpy(path->dmac, ah->roce.dmac, 6);
2f5bb473
JM		 1901 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1902 /* put MAC table smac index for IBoE */
1903 path->grh_mylmc = (u8) (smac_index) | 0x80;
1904 } else {
4c3eb3ca 1905 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
d8966fcd 1906 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2);
2f5bb473 1907 }
fa417f7b 1908
225c7b1f
RD		 1909 return 0;
1910}
1911
297e0dad
MS		 1912static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1913 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1914 struct mlx4_ib_qp *mqp,
dbf727de
MB		 1915 struct mlx4_qp_path *path, u8 port,
1916 u16 vlan_id, u8 *smac)
297e0dad
MS		 1917{
1918 return _mlx4_set_path(dev, &qp->ah_attr,
dbf727de
MB		 1919 mlx4_mac_to_u64(smac),
1920 vlan_id,
2f5bb473 1921 path, &mqp->pri, port);
297e0dad
MS		 1922}
1923
1924static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1925 const struct ib_qp_attr *qp,
1926 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1927 struct mlx4_ib_qp *mqp,
297e0dad
MS		 1928 struct mlx4_qp_path *path, u8 port)
1929{
1930 return _mlx4_set_path(dev, &qp->alt_ah_attr,
dbf727de
MB		 1931 0,
1932 0xffff,
2f5bb473 1933 path, &mqp->alt, port);
297e0dad
MS		 1934}
1935
fa417f7b
EC		 1936static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1937{
1938 struct mlx4_ib_gid_entry *ge, *tmp;
1939
1940 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1941 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1942 ge->added = 1;
1943 ge->port = qp->port;
1944 }
1945 }
1946}
1947
dbf727de
MB		 1948static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1949 struct mlx4_ib_qp *qp,
2f5bb473
JM		 1950 struct mlx4_qp_context *context)
1951{
2f5bb473
JM		 1952 u64 u64_mac;
1953 int smac_index;
1954
3e0629cb 1955 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
2f5bb473
JM		 1956
1957 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
25476b02 1958 if (!qp->pri.smac && !qp->pri.smac_port) {
2f5bb473
JM		 1959 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1960 if (smac_index >= 0) {
1961 qp->pri.candidate_smac_index = smac_index;
1962 qp->pri.candidate_smac = u64_mac;
1963 qp->pri.candidate_smac_port = qp->port;
1964 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1965 } else {
1966 return -ENOENT;
1967 }
1968 }
1969 return 0;
1970}
1971
7b59f0f9
EBE		 1972static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1973{
1974 struct counter_index *new_counter_index;
1975 int err;
1976 u32 tmp_idx;
1977
1978 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1979 IB_LINK_LAYER_ETHERNET ||
1980 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1981 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1982 return 0;
1983
f3301870 1984 err = mlx4_counter_alloc(dev->dev, &tmp_idx, MLX4_RES_USAGE_DRIVER);
7b59f0f9
EBE		 1985 if (err)
1986 return err;
1987
1988 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1989 if (!new_counter_index) {
1990 mlx4_counter_free(dev->dev, tmp_idx);
1991 return -ENOMEM;
1992 }
1993
1994 new_counter_index->index = tmp_idx;
1995 new_counter_index->allocated = 1;
1996 qp->counter_index = new_counter_index;
1997
1998 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1999 list_add_tail(&new_counter_index->list,
2000 &dev->counters_table[qp->port - 1].counters_list);
2001 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
2002
2003 return 0;
2004}
2005
3b5daf28
MS		 2006enum {
2007 MLX4_QPC_ROCE_MODE_1 = 0,
2008 MLX4_QPC_ROCE_MODE_2 = 2,
2009 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff
2010};
2011
2012static u8 gid_type_to_qpc(enum ib_gid_type gid_type)
2013{
2014 switch (gid_type) {
2015 case IB_GID_TYPE_ROCE:
2016 return MLX4_QPC_ROCE_MODE_1;
2017 case IB_GID_TYPE_ROCE_UDP_ENCAP:
2018 return MLX4_QPC_ROCE_MODE_2;
2019 default:
2020 return MLX4_QPC_ROCE_MODE_UNDEFINED;
2021 }
2022}
2023
3078f5f1
GL		 2024/*
2025 * Go over all RSS QP's childes (WQs) and apply their HW state according to
2026 * their logic state if the RSS QP is the first RSS QP associated for the WQ.
2027 */
2028static int bringup_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, u8 port_num)
2029{
2030 int i;
2031 int err;
2032
2033 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2034 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2035 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2036
2037 mutex_lock(&wq->mutex);
2038
2039 /* Mlx4_ib restrictions:
2040 * WQ's is associated to a port according to the RSS QP it is
2041 * associates to.
2042 * In case the WQ is associated to a different port by another
2043 * RSS QP, return a failure.
2044 */
2045 if ((wq->rss_usecnt > 0) && (wq->port != port_num)) {
2046 err = -EINVAL;
2047 mutex_unlock(&wq->mutex);
2048 break;
2049 }
2050 wq->port = port_num;
2051 if ((wq->rss_usecnt == 0) && (ibwq->state == IB_WQS_RDY)) {
2052 err = _mlx4_ib_modify_wq(ibwq, IB_WQS_RDY);
2053 if (err) {
2054 mutex_unlock(&wq->mutex);
2055 break;
2056 }
2057 }
2058 wq->rss_usecnt++;
2059
2060 mutex_unlock(&wq->mutex);
2061 }
2062
2063 if (i && err) {
2064 int j;
2065
2066 for (j = (i - 1); j >= 0; j--) {
2067 struct ib_wq *ibwq = ind_tbl->ind_tbl[j];
2068 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2069
2070 mutex_lock(&wq->mutex);
2071
2072 if ((wq->rss_usecnt == 1) &&
2073 (ibwq->state == IB_WQS_RDY))
2074 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET))
2075 pr_warn("failed to reverse WQN=0x%06x\n",
2076 ibwq->wq_num);
2077 wq->rss_usecnt--;
2078
2079 mutex_unlock(&wq->mutex);
2080 }
2081 }
2082
2083 return err;
2084}
2085
2086static void bring_down_rss_rwqs(struct ib_rwq_ind_table *ind_tbl)
2087{
2088 int i;
2089
2090 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2091 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2092 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2093
2094 mutex_lock(&wq->mutex);
2095
2096 if ((wq->rss_usecnt == 1) && (ibwq->state == IB_WQS_RDY))
2097 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET))
2098 pr_warn("failed to reverse WQN=%x\n",
2099 ibwq->wq_num);
2100 wq->rss_usecnt--;
2101
2102 mutex_unlock(&wq->mutex);
2103 }
2104}
2105
2106static void fill_qp_rss_context(struct mlx4_qp_context *context,
2107 struct mlx4_ib_qp *qp)
2108{
2109 struct mlx4_rss_context *rss_context;
2110
2111 rss_context = (void *)context + offsetof(struct mlx4_qp_context,
2112 pri_path) + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
2113
2114 rss_context->base_qpn = cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz);
2115 rss_context->default_qpn =
2116 cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz & 0xffffff);
2117 if (qp->rss_ctx->flags & (MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6))
2118 rss_context->base_qpn_udp = rss_context->default_qpn;
2119 rss_context->flags = qp->rss_ctx->flags;
2120 /* Currently support just toeplitz */
2121 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
2122
2123 memcpy(rss_context->rss_key, qp->rss_ctx->rss_key,
2124 MLX4_EN_RSS_KEY_SIZE);
2125}
2126
400b1ebc 2127static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type,
65adfa91
MT		 2128 const struct ib_qp_attr *attr, int attr_mask,
2129 enum ib_qp_state cur_state, enum ib_qp_state new_state)
225c7b1f 2130{
400b1ebc
GL		 2131 struct ib_uobject *ibuobject;
2132 struct ib_srq *ibsrq;
3078f5f1 2133 struct ib_rwq_ind_table *rwq_ind_tbl;
400b1ebc
GL		 2134 enum ib_qp_type qp_type;
2135 struct mlx4_ib_dev *dev;
2136 struct mlx4_ib_qp *qp;
0a1405da
SH		 2137 struct mlx4_ib_pd *pd;
2138 struct mlx4_ib_cq *send_cq, *recv_cq;
225c7b1f
RD		 2139 struct mlx4_qp_context *context;
2140 enum mlx4_qp_optpar optpar = 0;
225c7b1f 2141 int sqd_event;
c1c98501 2142 int steer_qp = 0;
225c7b1f 2143 int err = -EINVAL;
3ba8e31d 2144 int counter_index;
225c7b1f 2145
400b1ebc
GL		 2146 if (src_type == MLX4_IB_RWQ_SRC) {
2147 struct ib_wq *ibwq;
2148
3078f5f1
GL		 2149 ibwq = (struct ib_wq *)src;
2150 ibuobject = ibwq->uobject;
2151 ibsrq = NULL;
2152 rwq_ind_tbl = NULL;
2153 qp_type = IB_QPT_RAW_PACKET;
2154 qp = to_mqp((struct ib_qp *)ibwq);
2155 dev = to_mdev(ibwq->device);
2156 pd = to_mpd(ibwq->pd);
400b1ebc
GL		 2157 } else {
2158 struct ib_qp *ibqp;
2159
3078f5f1
GL		 2160 ibqp = (struct ib_qp *)src;
2161 ibuobject = ibqp->uobject;
2162 ibsrq = ibqp->srq;
2163 rwq_ind_tbl = ibqp->rwq_ind_tbl;
2164 qp_type = ibqp->qp_type;
2165 qp = to_mqp(ibqp);
2166 dev = to_mdev(ibqp->device);
2167 pd = get_pd(qp);
400b1ebc
GL		 2168 }
2169
3dec4878
JM		 2170 /* APM is not supported under RoCE */
2171 if (attr_mask & IB_QP_ALT_PATH &&
2172 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2173 IB_LINK_LAYER_ETHERNET)
2174 return -ENOTSUPP;
2175
225c7b1f
RD		 2176 context = kzalloc(sizeof *context, GFP_KERNEL);
2177 if (!context)
2178 return -ENOMEM;
2179
225c7b1f 2180 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1ffeb2eb 2181 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
225c7b1f 2182
3078f5f1
GL		 2183 if (rwq_ind_tbl) {
2184 fill_qp_rss_context(context, qp);
2185 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET);
2186 }
2187
225c7b1f
RD		 2188 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
2189 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2190 else {
2191 optpar |= MLX4_QP_OPTPAR_PM_STATE;
2192 switch (attr->path_mig_state) {
2193 case IB_MIG_MIGRATED:
2194 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2195 break;
2196 case IB_MIG_REARM:
2197 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
2198 break;
2199 case IB_MIG_ARMED:
2200 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
2201 break;
2202 }
2203 }
2204
ea30b966
MG		 2205 if (qp->inl_recv_sz)
2206 context->param3 |= cpu_to_be32(1 << 25);
2207
400b1ebc 2208 if (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI)
225c7b1f 2209 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
400b1ebc 2210 else if (qp_type == IB_QPT_RAW_PACKET)
3987a2d3 2211 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
400b1ebc 2212 else if (qp_type == IB_QPT_UD) {
b832be1e
EC		 2213 if (qp->flags & MLX4_IB_QP_LSO)
2214 context->mtu_msgmax = (IB_MTU_4096 << 5) |
2215 ilog2(dev->dev->caps.max_gso_sz);
2216 else
6e0d733d 2217 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
b832be1e 2218 } else if (attr_mask & IB_QP_PATH_MTU) {
225c7b1f 2219 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
987c8f8f 2220 pr_err("path MTU (%u) is invalid\n",
225c7b1f 2221 attr->path_mtu);
f5b40431 2222 goto out;
225c7b1f 2223 }
d1f2cd89
EC		 2224 context->mtu_msgmax = (attr->path_mtu << 5) |
2225 ilog2(dev->dev->caps.max_msg_sz);
225c7b1f
RD		 2226 }
2227
3078f5f1
GL		 2228 if (!rwq_ind_tbl) { /* PRM RSS receive side should be left zeros */
2229 if (qp->rq.wqe_cnt)
2230 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
2231 context->rq_size_stride |= qp->rq.wqe_shift - 4;
2232 }
225c7b1f 2233
0e6e7416
RD		 2234 if (qp->sq.wqe_cnt)
2235 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
225c7b1f
RD		 2236 context->sq_size_stride |= qp->sq.wqe_shift - 4;
2237
7b59f0f9
EBE		 2238 if (new_state == IB_QPS_RESET && qp->counter_index)
2239 mlx4_ib_free_qp_counter(dev, qp);
2240
0a1405da 2241 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0e6e7416 2242 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
0a1405da 2243 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
400b1ebc 2244 if (qp_type == IB_QPT_RAW_PACKET)
02d7ef6f 2245 context->param3 |= cpu_to_be32(1 << 30);
0a1405da 2246 }
0e6e7416 2247
400b1ebc 2248 if (ibuobject)
85743f1e
HN		 2249 context->usr_page = cpu_to_be32(
2250 mlx4_to_hw_uar_index(dev->dev,
400b1ebc
GL		 2251 to_mucontext(ibuobject->context)
2252 ->uar.index));
225c7b1f 2253 else
85743f1e
HN		 2254 context->usr_page = cpu_to_be32(
2255 mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index));
225c7b1f
RD		 2256
2257 if (attr_mask & IB_QP_DEST_QPN)
2258 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
2259
2260 if (attr_mask & IB_QP_PORT) {
2261 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
2262 !(attr_mask & IB_QP_AV)) {
2263 mlx4_set_sched(&context->pri_path, attr->port_num);
2264 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
2265 }
2266 }
2267
cfcde11c 2268 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
7b59f0f9
EBE		 2269 err = create_qp_lb_counter(dev, qp);
2270 if (err)
2271 goto out;
2272
3ba8e31d
EBE		 2273 counter_index =
2274 dev->counters_table[qp->port - 1].default_counter;
7b59f0f9
EBE		 2275 if (qp->counter_index)
2276 counter_index = qp->counter_index->index;
2277
3ba8e31d
EBE		 2278 if (counter_index != -1) {
2279 context->pri_path.counter_index = counter_index;
cfcde11c 2280 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
7b59f0f9
EBE		 2281 if (qp->counter_index) {
2282 context->pri_path.fl |=
2283 MLX4_FL_ETH_SRC_CHECK_MC_LB;
2284 context->pri_path.vlan_control |=
2285 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
2286 }
cfcde11c 2287 } else
47d8417f
EBE		 2288 context->pri_path.counter_index =
2289 MLX4_SINK_COUNTER_INDEX(dev->dev);
c1c98501
MB		 2290
2291 if (qp->flags & MLX4_IB_QP_NETIF) {
2292 mlx4_ib_steer_qp_reg(dev, qp, 1);
2293 steer_qp = 1;
2294 }
e1b866c6 2295
400b1ebc 2296 if (qp_type == IB_QPT_GSI) {
e1b866c6
MS		 2297 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ?
2298 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE;
2299 u8 qpc_roce_mode = gid_type_to_qpc(gid_type);
2300
2301 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2302 }
cfcde11c
OG		 2303 }
2304
225c7b1f 2305 if (attr_mask & IB_QP_PKEY_INDEX) {
1ffeb2eb
JM		 2306 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2307 context->pri_path.disable_pkey_check = 0x40;
225c7b1f
RD		 2308 context->pri_path.pkey_index = attr->pkey_index;
2309 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
2310 }
2311
225c7b1f 2312 if (attr_mask & IB_QP_AV) {
400b1ebc 2313 u8 port_num = mlx4_is_bonded(dev->dev) ? 1 :
dbf727de
MB		 2314 attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2315 union ib_gid gid;
bf08e884 2316 struct ib_gid_attr gid_attr = {.gid_type = IB_GID_TYPE_IB};
dbf727de
MB		 2317 u16 vlan = 0xffff;
2318 u8 smac[ETH_ALEN];
2319 int status = 0;
d8966fcd
DC		 2320 int is_eth =
2321 rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
2322 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
dbf727de 2323
d8966fcd
DC		 2324 if (is_eth) {
2325 int index =
2326 rdma_ah_read_grh(&attr->ah_attr)->sgid_index;
dbf727de 2327
400b1ebc 2328 status = ib_get_cached_gid(&dev->ib_dev, port_num,
dbf727de
MB		 2329 index, &gid, &gid_attr);
2330 if (!status && !memcmp(&gid, &zgid, sizeof(gid)))
2331 status = -ENOENT;
2332 if (!status && gid_attr.ndev) {
2333 vlan = rdma_vlan_dev_vlan_id(gid_attr.ndev);
2334 memcpy(smac, gid_attr.ndev->dev_addr, ETH_ALEN);
2335 dev_put(gid_attr.ndev);
2336 }
2337 }
2338 if (status)
2339 goto out;
2340
2f5bb473 2341 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
dbf727de 2342 port_num, vlan, smac))
225c7b1f 2343 goto out;
225c7b1f
RD		 2344
2345 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
2346 MLX4_QP_OPTPAR_SCHED_QUEUE);
3b5daf28
MS		 2347
2348 if (is_eth &&
2349 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) {
2350 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr.gid_type);
2351
2352 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) {
2353 err = -EINVAL;
2354 goto out;
2355 }
2356 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2357 }
2358
225c7b1f
RD		 2359 }
2360
2361 if (attr_mask & IB_QP_TIMEOUT) {
fa417f7b 2362 context->pri_path.ackto |= attr->timeout << 3;
225c7b1f
RD		 2363 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
2364 }
2365
2366 if (attr_mask & IB_QP_ALT_PATH) {
225c7b1f
RD		 2367 if (attr->alt_port_num == 0 ||
2368 attr->alt_port_num > dev->dev->caps.num_ports)
f5b40431 2369 goto out;
225c7b1f 2370
5ae2a7a8
RD		 2371 if (attr->alt_pkey_index >=
2372 dev->dev->caps.pkey_table_len[attr->alt_port_num])
f5b40431 2373 goto out;
5ae2a7a8 2374
2f5bb473
JM		 2375 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
2376 &context->alt_path,
297e0dad 2377 attr->alt_port_num))
f5b40431 2378 goto out;
225c7b1f
RD		 2379
2380 context->alt_path.pkey_index = attr->alt_pkey_index;
2381 context->alt_path.ackto = attr->alt_timeout << 3;
2382 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
2383 }
2384
3078f5f1
GL		 2385 context->pd = cpu_to_be32(pd->pdn);
2386
2387 if (!rwq_ind_tbl) {
2388 get_cqs(qp, src_type, &send_cq, &recv_cq);
2389 } else { /* Set dummy CQs to be compatible with HV and PRM */
2390 send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq);
2391 recv_cq = send_cq;
2392 }
0a1405da
SH		 2393 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
2394 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
2395 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
57f01b53 2396
95d04f07 2397 /* Set "fast registration enabled" for all kernel QPs */
400b1ebc 2398 if (!ibuobject)
95d04f07
RD		 2399 context->params1 |= cpu_to_be32(1 << 11);
2400
57f01b53
JM		 2401 if (attr_mask & IB_QP_RNR_RETRY) {
2402 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2403 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
2404 }
2405
225c7b1f
RD		 2406 if (attr_mask & IB_QP_RETRY_CNT) {
2407 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2408 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
2409 }
2410
2411 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2412 if (attr->max_rd_atomic)
2413 context->params1 |=
2414 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2415 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
2416 }
2417
2418 if (attr_mask & IB_QP_SQ_PSN)
2419 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2420
225c7b1f
RD		 2421 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2422 if (attr->max_dest_rd_atomic)
2423 context->params2 |=
2424 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2425 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
2426 }
2427
2428 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
2429 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
2430 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
2431 }
2432
400b1ebc 2433 if (ibsrq)
225c7b1f
RD		 2434 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
2435
2436 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2437 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2438 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
2439 }
2440 if (attr_mask & IB_QP_RQ_PSN)
2441 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2442
1ffeb2eb 2443 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
225c7b1f 2444 if (attr_mask & IB_QP_QKEY) {
1ffeb2eb
JM		 2445 if (qp->mlx4_ib_qp_type &
2446 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
2447 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2448 else {
2449 if (mlx4_is_mfunc(dev->dev) &&
2450 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
2451 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
2452 MLX4_RESERVED_QKEY_BASE) {
2453 pr_err("Cannot use reserved QKEY"
2454 " 0x%x (range 0xffff0000..0xffffffff"
2455 " is reserved)\n", attr->qkey);
2456 err = -EINVAL;
2457 goto out;
2458 }
2459 context->qkey = cpu_to_be32(attr->qkey);
2460 }
225c7b1f
RD		 2461 optpar |= MLX4_QP_OPTPAR_Q_KEY;
2462 }
2463
400b1ebc
GL		 2464 if (ibsrq)
2465 context->srqn = cpu_to_be32(1 << 24 |
2466 to_msrq(ibsrq)->msrq.srqn);
225c7b1f 2467
400b1ebc
GL		 2468 if (qp->rq.wqe_cnt &&
2469 cur_state == IB_QPS_RESET &&
2470 new_state == IB_QPS_INIT)
225c7b1f
RD		 2471 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2472
2473 if (cur_state == IB_QPS_INIT &&
2474 new_state == IB_QPS_RTR &&
400b1ebc
GL		 2475 (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI ||
2476 qp_type == IB_QPT_UD || qp_type == IB_QPT_RAW_PACKET)) {
225c7b1f 2477 context->pri_path.sched_queue = (qp->port - 1) << 6;
1ffeb2eb
JM		 2478 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2479 qp->mlx4_ib_qp_type &
2480 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
225c7b1f 2481 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1ffeb2eb
JM		 2482 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
2483 context->pri_path.fl = 0x80;
2484 } else {
2485 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2486 context->pri_path.fl = 0x80;
225c7b1f 2487 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1ffeb2eb 2488 }
2f5bb473
JM		 2489 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2490 IB_LINK_LAYER_ETHERNET) {
2491 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
2492 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
2493 context->pri_path.feup = 1 << 7; /* don't fsm */
2494 /* handle smac_index */
2495 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
2496 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
2497 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
dbf727de 2498 err = handle_eth_ud_smac_index(dev, qp, context);
bede98e7
MD		 2499 if (err) {
2500 err = -EINVAL;
2501 goto out;
2502 }
9433c188
MB		 2503 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
2504 dev->qp1_proxy[qp->port - 1] = qp;
2f5bb473
JM		 2505 }
2506 }
225c7b1f
RD		 2507 }
2508
400b1ebc 2509 if (qp_type == IB_QPT_RAW_PACKET) {
3528f696
EC		 2510 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
2511 MLX4_IB_LINK_TYPE_ETH;
d2fce8a9
OG		 2512 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
2513 /* set QP to receive both tunneled & non-tunneled packets */
8e1a03b6 2514 if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET)))
d2fce8a9
OG		 2515 context->srqn = cpu_to_be32(7 << 28);
2516 }
2517 }
3528f696 2518
400b1ebc 2519 if (qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
297e0dad
MS		 2520 int is_eth = rdma_port_get_link_layer(
2521 &dev->ib_dev, qp->port) ==
2522 IB_LINK_LAYER_ETHERNET;
2523 if (is_eth) {
2524 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
2525 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
2526 }
2527 }
2528
225c7b1f
RD		 2529 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
2530 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2531 sqd_event = 1;
2532 else
2533 sqd_event = 0;
2534
400b1ebc
GL		 2535 if (!ibuobject &&
2536 cur_state == IB_QPS_RESET &&
2537 new_state == IB_QPS_INIT)
3b5daf28 2538 context->rlkey_roce_mode |= (1 << 4);
d57f5f72 2539
c0be5fb5
EC		 2540 /*
2541 * Before passing a kernel QP to the HW, make sure that the
0e6e7416
RD		 2542 * ownership bits of the send queue are set and the SQ
2543 * headroom is stamped so that the hardware doesn't start
2544 * processing stale work requests.
c0be5fb5 2545 */
400b1ebc
GL		 2546 if (!ibuobject &&
2547 cur_state == IB_QPS_RESET &&
2548 new_state == IB_QPS_INIT) {
c0be5fb5
EC		 2549 struct mlx4_wqe_ctrl_seg *ctrl;
2550 int i;
2551
0e6e7416 2552 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
c0be5fb5
EC		 2553 ctrl = get_send_wqe(qp, i);
2554 ctrl->owner_opcode = cpu_to_be32(1 << 31);
9670e553 2555 if (qp->sq_max_wqes_per_wr == 1)
224e92e0
BB		 2556 ctrl->qpn_vlan.fence_size =
2557 1 << (qp->sq.wqe_shift - 4);
0e6e7416 2558
ea54b10c 2559 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
c0be5fb5
EC		 2560 }
2561 }
2562
225c7b1f
RD		 2563 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
2564 to_mlx4_state(new_state), context, optpar,
2565 sqd_event, &qp->mqp);
2566 if (err)
2567 goto out;
2568
2569 qp->state = new_state;
2570
2571 if (attr_mask & IB_QP_ACCESS_FLAGS)
2572 qp->atomic_rd_en = attr->qp_access_flags;
2573 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2574 qp->resp_depth = attr->max_dest_rd_atomic;
fa417f7b 2575 if (attr_mask & IB_QP_PORT) {
225c7b1f 2576 qp->port = attr->port_num;
fa417f7b
EC		 2577 update_mcg_macs(dev, qp);
2578 }
225c7b1f
RD		 2579 if (attr_mask & IB_QP_ALT_PATH)
2580 qp->alt_port = attr->alt_port_num;
2581
2582 if (is_sqp(dev, qp))
2583 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
2584
2585 /*
2586 * If we moved QP0 to RTR, bring the IB link up; if we moved
2587 * QP0 to RESET or ERROR, bring the link back down.
2588 */
2589 if (is_qp0(dev, qp)) {
2590 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
5ae2a7a8 2591 if (mlx4_INIT_PORT(dev->dev, qp->port))
987c8f8f 2592 pr_warn("INIT_PORT failed for port %d\n",
5ae2a7a8 2593 qp->port);
225c7b1f
RD		 2594
2595 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2596 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
2597 mlx4_CLOSE_PORT(dev->dev, qp->port);
2598 }
2599
2600 /*
2601 * If we moved a kernel QP to RESET, clean up all old CQ
2602 * entries and reinitialize the QP.
2603 */
2f5bb473 2604 if (new_state == IB_QPS_RESET) {
400b1ebc 2605 if (!ibuobject) {
2f5bb473 2606 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
400b1ebc 2607 ibsrq ? to_msrq(ibsrq) : NULL);
2f5bb473
JM		 2608 if (send_cq != recv_cq)
2609 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
2610
2611 qp->rq.head = 0;
2612 qp->rq.tail = 0;
2613 qp->sq.head = 0;
2614 qp->sq.tail = 0;
2615 qp->sq_next_wqe = 0;
2616 if (qp->rq.wqe_cnt)
2617 *qp->db.db = 0;
225c7b1f 2618
2f5bb473
JM		 2619 if (qp->flags & MLX4_IB_QP_NETIF)
2620 mlx4_ib_steer_qp_reg(dev, qp, 0);
2621 }
25476b02 2622 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 2623 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2624 qp->pri.smac = 0;
25476b02 2625 qp->pri.smac_port = 0;
2f5bb473
JM		 2626 }
2627 if (qp->alt.smac) {
2628 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2629 qp->alt.smac = 0;
2630 }
2631 if (qp->pri.vid < 0x1000) {
2632 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
2633 qp->pri.vid = 0xFFFF;
2634 qp->pri.candidate_vid = 0xFFFF;
2635 qp->pri.update_vid = 0;
2636 }
c1c98501 2637
2f5bb473
JM		 2638 if (qp->alt.vid < 0x1000) {
2639 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
2640 qp->alt.vid = 0xFFFF;
2641 qp->alt.candidate_vid = 0xFFFF;
2642 qp->alt.update_vid = 0;
2643 }
225c7b1f 2644 }
225c7b1f 2645out:
7b59f0f9
EBE		 2646 if (err && qp->counter_index)
2647 mlx4_ib_free_qp_counter(dev, qp);
c1c98501
MB		 2648 if (err && steer_qp)
2649 mlx4_ib_steer_qp_reg(dev, qp, 0);
225c7b1f 2650 kfree(context);
25476b02
JM		 2651 if (qp->pri.candidate_smac ||
2652 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2f5bb473
JM		 2653 if (err) {
2654 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
2655 } else {
25476b02 2656 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2f5bb473
JM		 2657 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2658 qp->pri.smac = qp->pri.candidate_smac;
2659 qp->pri.smac_index = qp->pri.candidate_smac_index;
2660 qp->pri.smac_port = qp->pri.candidate_smac_port;
2661 }
2662 qp->pri.candidate_smac = 0;
2663 qp->pri.candidate_smac_index = 0;
2664 qp->pri.candidate_smac_port = 0;
2665 }
2666 if (qp->alt.candidate_smac) {
2667 if (err) {
2668 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
2669 } else {
2670 if (qp->alt.smac)
2671 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2672 qp->alt.smac = qp->alt.candidate_smac;
2673 qp->alt.smac_index = qp->alt.candidate_smac_index;
2674 qp->alt.smac_port = qp->alt.candidate_smac_port;
2675 }
2676 qp->alt.candidate_smac = 0;
2677 qp->alt.candidate_smac_index = 0;
2678 qp->alt.candidate_smac_port = 0;
2679 }
2680
2681 if (qp->pri.update_vid) {
2682 if (err) {
2683 if (qp->pri.candidate_vid < 0x1000)
2684 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
2685 qp->pri.candidate_vid);
2686 } else {
2687 if (qp->pri.vid < 0x1000)
2688 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2689 qp->pri.vid);
2690 qp->pri.vid = qp->pri.candidate_vid;
2691 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2692 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
2693 }
2694 qp->pri.candidate_vid = 0xFFFF;
2695 qp->pri.update_vid = 0;
2696 }
2697
2698 if (qp->alt.update_vid) {
2699 if (err) {
2700 if (qp->alt.candidate_vid < 0x1000)
2701 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2702 qp->alt.candidate_vid);
2703 } else {
2704 if (qp->alt.vid < 0x1000)
2705 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2706 qp->alt.vid);
2707 qp->alt.vid = qp->alt.candidate_vid;
2708 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2709 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
2710 }
2711 qp->alt.candidate_vid = 0xFFFF;
2712 qp->alt.update_vid = 0;
2713 }
2714
225c7b1f
RD		 2715 return err;
2716}
2717
3078f5f1
GL		 2718enum {
2719 MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK = (IB_QP_STATE |
2720 IB_QP_PORT),
2721};
2722
e1b866c6
MS		 2723static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2724 int attr_mask, struct ib_udata *udata)
65adfa91
MT		 2725{
2726 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2727 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2728 enum ib_qp_state cur_state, new_state;
2729 int err = -EINVAL;
297e0dad 2730 int ll;
65adfa91
MT		 2731 mutex_lock(&qp->mutex);
2732
2733 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2734 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2735
297e0dad
MS		 2736 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2737 ll = IB_LINK_LAYER_UNSPECIFIED;
2738 } else {
2739 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2740 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2741 }
dd5f03be
MB		 2742
2743 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
297e0dad 2744 attr_mask, ll)) {
b1d8eb5a
JM		 2745 pr_debug("qpn 0x%x: invalid attribute mask specified "
2746 "for transition %d to %d. qp_type %d,"
2747 " attr_mask 0x%x\n",
2748 ibqp->qp_num, cur_state, new_state,
2749 ibqp->qp_type, attr_mask);
65adfa91 2750 goto out;
b1d8eb5a 2751 }
65adfa91 2752
3078f5f1
GL		 2753 if (ibqp->rwq_ind_tbl) {
2754 if (!(((cur_state == IB_QPS_RESET) &&
2755 (new_state == IB_QPS_INIT)) ||
2756 ((cur_state == IB_QPS_INIT) &&
2757 (new_state == IB_QPS_RTR)))) {
2758 pr_debug("qpn 0x%x: RSS QP unsupported transition %d to %d\n",
2759 ibqp->qp_num, cur_state, new_state);
2760
2761 err = -EOPNOTSUPP;
2762 goto out;
2763 }
2764
2765 if (attr_mask & ~MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK) {
2766 pr_debug("qpn 0x%x: RSS QP unsupported attribute mask 0x%x for transition %d to %d\n",
2767 ibqp->qp_num, attr_mask, cur_state, new_state);
2768
2769 err = -EOPNOTSUPP;
2770 goto out;
2771 }
2772 }
2773
c6215745
MS		 2774 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2775 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2776 if ((ibqp->qp_type == IB_QPT_RC) ||
2777 (ibqp->qp_type == IB_QPT_UD) ||
2778 (ibqp->qp_type == IB_QPT_UC) ||
2779 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2780 (ibqp->qp_type == IB_QPT_XRC_INI)) {
2781 attr->port_num = mlx4_ib_bond_next_port(dev);
2782 }
2783 } else {
2784 /* no sense in changing port_num
2785 * when ports are bonded */
2786 attr_mask &= ~IB_QP_PORT;
2787 }
2788 }
2789
65adfa91 2790 if ((attr_mask & IB_QP_PORT) &&
1ffeb2eb 2791 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
b1d8eb5a
JM		 2792 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2793 "for transition %d to %d. qp_type %d\n",
2794 ibqp->qp_num, attr->port_num, cur_state,
2795 new_state, ibqp->qp_type);
65adfa91
MT		 2796 goto out;
2797 }
2798
3987a2d3
OG		 2799 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2800 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2801 IB_LINK_LAYER_ETHERNET))
2802 goto out;
2803
5ae2a7a8
RD		 2804 if (attr_mask & IB_QP_PKEY_INDEX) {
2805 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
b1d8eb5a
JM		 2806 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2807 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2808 "for transition %d to %d. qp_type %d\n",
2809 ibqp->qp_num, attr->pkey_index, cur_state,
2810 new_state, ibqp->qp_type);
5ae2a7a8 2811 goto out;
b1d8eb5a 2812 }
5ae2a7a8
RD		 2813 }
2814
65adfa91
MT		 2815 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2816 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
b1d8eb5a
JM		 2817 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2818 "Transition %d to %d. qp_type %d\n",
2819 ibqp->qp_num, attr->max_rd_atomic, cur_state,
2820 new_state, ibqp->qp_type);
65adfa91
MT		 2821 goto out;
2822 }
2823
2824 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2825 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
b1d8eb5a
JM		 2826 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2827 "Transition %d to %d. qp_type %d\n",
2828 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2829 new_state, ibqp->qp_type);
65adfa91
MT		 2830 goto out;
2831 }
2832
2833 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2834 err = 0;
2835 goto out;
2836 }
2837
3078f5f1
GL		 2838 if (ibqp->rwq_ind_tbl && (new_state == IB_QPS_INIT)) {
2839 err = bringup_rss_rwqs(ibqp->rwq_ind_tbl, attr->port_num);
2840 if (err)
2841 goto out;
2842 }
2843
400b1ebc
GL		 2844 err = __mlx4_ib_modify_qp(ibqp, MLX4_IB_QP_SRC, attr, attr_mask,
2845 cur_state, new_state);
65adfa91 2846
3078f5f1
GL		 2847 if (ibqp->rwq_ind_tbl && err)
2848 bring_down_rss_rwqs(ibqp->rwq_ind_tbl);
2849
c6215745
MS		 2850 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2851 attr->port_num = 1;
2852
65adfa91
MT		 2853out:
2854 mutex_unlock(&qp->mutex);
2855 return err;
2856}
2857
e1b866c6
MS		 2858int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2859 int attr_mask, struct ib_udata *udata)
2860{
2861 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2862 int ret;
2863
2864 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata);
2865
2866 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2867 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
2868 int err = 0;
2869
2870 if (sqp->roce_v2_gsi)
2871 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask);
2872 if (err)
2873 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n",
2874 err);
2875 }
2876 return ret;
2877}
2878
99ec41d0
JM		 2879static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2880{
2881 int i;
2882 for (i = 0; i < dev->caps.num_ports; i++) {
2883 if (qpn == dev->caps.qp0_proxy[i] ||
2884 qpn == dev->caps.qp0_tunnel[i]) {
2885 *qkey = dev->caps.qp0_qkey[i];
2886 return 0;
2887 }
2888 }
2889 return -EINVAL;
2890}
2891
1ffeb2eb 2892static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
e622f2f4 2893 struct ib_ud_wr *wr,
1ffeb2eb
JM		 2894 void *wqe, unsigned *mlx_seg_len)
2895{
2896 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2897 struct ib_device *ib_dev = &mdev->ib_dev;
2898 struct mlx4_wqe_mlx_seg *mlx = wqe;
2899 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2900 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 2901 u16 pkey;
2902 u32 qkey;
2903 int send_size;
2904 int header_size;
2905 int spc;
2906 int i;
2907
e622f2f4 2908 if (wr->wr.opcode != IB_WR_SEND)
1ffeb2eb
JM		 2909 return -EINVAL;
2910
2911 send_size = 0;
2912
e622f2f4
CH		 2913 for (i = 0; i < wr->wr.num_sge; ++i)
2914 send_size += wr->wr.sg_list[i].length;
1ffeb2eb
JM		 2915
2916 /* for proxy-qp0 sends, need to add in size of tunnel header */
2917 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2918 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2919 send_size += sizeof (struct mlx4_ib_tunnel_header);
2920
25f40220 2921 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
1ffeb2eb
JM		 2922
2923 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2924 sqp->ud_header.lrh.service_level =
2925 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2926 sqp->ud_header.lrh.destination_lid =
2927 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2928 sqp->ud_header.lrh.source_lid =
2929 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2930 }
2931
2932 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2933
2934 /* force loopback */
2935 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2936 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2937
2938 sqp->ud_header.lrh.virtual_lane = 0;
e622f2f4 2939 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
1ffeb2eb
JM		 2940 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2941 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2942 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
e622f2f4 2943 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
1ffeb2eb
JM		 2944 else
2945 sqp->ud_header.bth.destination_qpn =
47605df9 2946 cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
1ffeb2eb
JM		 2947
2948 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
99ec41d0
JM		 2949 if (mlx4_is_master(mdev->dev)) {
2950 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2951 return -EINVAL;
2952 } else {
2953 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2954 return -EINVAL;
2955 }
1ffeb2eb
JM		 2956 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2957 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2958
2959 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2960 sqp->ud_header.immediate_present = 0;
2961
2962 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2963
2964 /*
2965 * Inline data segments may not cross a 64 byte boundary. If
2966 * our UD header is bigger than the space available up to the
2967 * next 64 byte boundary in the WQE, use two inline data
2968 * segments to hold the UD header.
2969 */
2970 spc = MLX4_INLINE_ALIGN -
2971 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2972 if (header_size <= spc) {
2973 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2974 memcpy(inl + 1, sqp->header_buf, header_size);
2975 i = 1;
2976 } else {
2977 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2978 memcpy(inl + 1, sqp->header_buf, spc);
2979
2980 inl = (void *) (inl + 1) + spc;
2981 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2982 /*
2983 * Need a barrier here to make sure all the data is
2984 * visible before the byte_count field is set.
2985 * Otherwise the HCA prefetcher could grab the 64-byte
2986 * chunk with this inline segment and get a valid (!=
2987 * 0xffffffff) byte count but stale data, and end up
2988 * generating a packet with bad headers.
2989 *
2990 * The first inline segment's byte_count field doesn't
2991 * need a barrier, because it comes after a
2992 * control/MLX segment and therefore is at an offset
2993 * of 16 mod 64.
2994 */
2995 wmb();
2996 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2997 i = 2;
2998 }
2999
3000 *mlx_seg_len =
3001 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
3002 return 0;
3003}
3004
fd10ed8e
JM		 3005static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num)
3006{
3007 union sl2vl_tbl_to_u64 tmp_vltab;
3008 u8 vl;
3009
3010 if (sl > 15)
3011 return 0xf;
3012 tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]);
3013 vl = tmp_vltab.sl8[sl >> 1];
3014 if (sl & 1)
3015 vl &= 0x0f;
3016 else
3017 vl >>= 4;
3018 return vl;
3019}
3020
a748d60d
TB		 3021static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num,
3022 int index, union ib_gid *gid,
3023 enum ib_gid_type *gid_type)
3024{
3025 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
3026 struct mlx4_port_gid_table *port_gid_table;
3027 unsigned long flags;
3028
3029 port_gid_table = &iboe->gids[port_num - 1];
3030 spin_lock_irqsave(&iboe->lock, flags);
3031 memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid));
3032 *gid_type = port_gid_table->gids[index].gid_type;
3033 spin_unlock_irqrestore(&iboe->lock, flags);
3034 if (!memcmp(gid, &zgid, sizeof(*gid)))
3035 return -ENOENT;
3036
3037 return 0;
3038}
3039
3ef967a4 3040#define MLX4_ROCEV2_QP1_SPORT 0xC000
e622f2f4 3041static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_ud_wr *wr,
f438000f 3042 void *wqe, unsigned *mlx_seg_len)
225c7b1f 3043{
a478868a 3044 struct ib_device *ib_dev = sqp->qp.ibqp.device;
a748d60d 3045 struct mlx4_ib_dev *ibdev = to_mdev(ib_dev);
225c7b1f 3046 struct mlx4_wqe_mlx_seg *mlx = wqe;
6ee51a4e 3047 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
225c7b1f 3048 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 3049 struct mlx4_ib_ah *ah = to_mah(wr->ah);
4c3eb3ca 3050 union ib_gid sgid;
225c7b1f
RD		 3051 u16 pkey;
3052 int send_size;
3053 int header_size;
e61ef241 3054 int spc;
225c7b1f 3055 int i;
1ffeb2eb 3056 int err = 0;
57d88cff 3057 u16 vlan = 0xffff;
a29bec12
RD		 3058 bool is_eth;
3059 bool is_vlan = false;
3060 bool is_grh;
3ef967a4
MS		 3061 bool is_udp = false;
3062 int ip_version = 0;
225c7b1f
RD		 3063
3064 send_size = 0;
e622f2f4
CH		 3065 for (i = 0; i < wr->wr.num_sge; ++i)
3066 send_size += wr->wr.sg_list[i].length;
225c7b1f 3067
fa417f7b
EC		 3068 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
3069 is_grh = mlx4_ib_ah_grh_present(ah);
4c3eb3ca 3070 if (is_eth) {
a748d60d 3071 enum ib_gid_type gid_type;
1ffeb2eb
JM		 3072 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3073 /* When multi-function is enabled, the ib_core gid
3074 * indexes don't necessarily match the hw ones, so
3075 * we must use our own cache */
6ee51a4e
JM		 3076 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
3077 be32_to_cpu(ah->av.ib.port_pd) >> 24,
3078 ah->av.ib.gid_index, &sgid.raw[0]);
3079 if (err)
3080 return err;
1ffeb2eb 3081 } else {
a748d60d
TB		 3082 err = fill_gid_by_hw_index(ibdev, sqp->qp.port,
3083 ah->av.ib.gid_index,
3084 &sgid, &gid_type);
3ef967a4 3085 if (!err) {
a748d60d 3086 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
3ef967a4
MS		 3087 if (is_udp) {
3088 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid))
3089 ip_version = 4;
3090 else
3091 ip_version = 6;
3092 is_grh = false;
3093 }
3094 } else {
1ffeb2eb 3095 return err;
3ef967a4 3096 }
1ffeb2eb 3097 }
0e9855db 3098 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
297e0dad
MS		 3099 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
3100 is_vlan = 1;
3101 }
4c3eb3ca 3102 }
25f40220 3103 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
3ef967a4 3104 ip_version, is_udp, 0, &sqp->ud_header);
25f40220
MS		 3105 if (err)
3106 return err;
fa417f7b
EC		 3107
3108 if (!is_eth) {
3109 sqp->ud_header.lrh.service_level =
3110 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
3111 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
3112 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
3113 }
225c7b1f 3114
3ef967a4 3115 if (is_grh || (ip_version == 6)) {
225c7b1f 3116 sqp->ud_header.grh.traffic_class =
fa417f7b 3117 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
225c7b1f 3118 sqp->ud_header.grh.flow_label =
fa417f7b
EC		 3119 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
3120 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
baa0be70 3121 if (is_eth) {
6ee51a4e 3122 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
baa0be70
JM		 3123 } else {
3124 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3125 /* When multi-function is enabled, the ib_core gid
3126 * indexes don't necessarily match the hw ones, so
3127 * we must use our own cache
3128 */
3129 sqp->ud_header.grh.source_gid.global.subnet_prefix =
8ec07bf8
JM		 3130 cpu_to_be64(atomic64_read(&(to_mdev(ib_dev)->sriov.
3131 demux[sqp->qp.port - 1].
3132 subnet_prefix)));
baa0be70
JM		 3133 sqp->ud_header.grh.source_gid.global.interface_id =
3134 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
3135 guid_cache[ah->av.ib.gid_index];
3136 } else {
3137 ib_get_cached_gid(ib_dev,
3138 be32_to_cpu(ah->av.ib.port_pd) >> 24,
3139 ah->av.ib.gid_index,
3140 &sqp->ud_header.grh.source_gid, NULL);
3141 }
6ee51a4e 3142 }
225c7b1f 3143 memcpy(sqp->ud_header.grh.destination_gid.raw,
fa417f7b 3144 ah->av.ib.dgid, 16);
225c7b1f
RD		 3145 }
3146
3ef967a4
MS		 3147 if (ip_version == 4) {
3148 sqp->ud_header.ip4.tos =
3149 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
3150 sqp->ud_header.ip4.id = 0;
3151 sqp->ud_header.ip4.frag_off = htons(IP_DF);
3152 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit;
3153
3154 memcpy(&sqp->ud_header.ip4.saddr,
3155 sgid.raw + 12, 4);
3156 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4);
3157 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header);
3158 }
3159
3160 if (is_udp) {
3161 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT);
3162 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT);
3163 sqp->ud_header.udp.csum = 0;
3164 }
3165
225c7b1f 3166 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
fa417f7b
EC		 3167
3168 if (!is_eth) {
3169 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
3170 (sqp->ud_header.lrh.destination_lid ==
3171 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
3172 (sqp->ud_header.lrh.service_level << 8));
1ffeb2eb
JM		 3173 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
3174 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
fa417f7b
EC		 3175 mlx->rlid = sqp->ud_header.lrh.destination_lid;
3176 }
225c7b1f 3177
e622f2f4 3178 switch (wr->wr.opcode) {
225c7b1f
RD		 3179 case IB_WR_SEND:
3180 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
3181 sqp->ud_header.immediate_present = 0;
3182 break;
3183 case IB_WR_SEND_WITH_IMM:
3184 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
3185 sqp->ud_header.immediate_present = 1;
e622f2f4 3186 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
225c7b1f
RD		 3187 break;
3188 default:
3189 return -EINVAL;
3190 }
3191
fa417f7b 3192 if (is_eth) {
6ee51a4e 3193 struct in6_addr in6;
3ef967a4 3194 u16 ether_type;
c0c1d3d7
OD		 3195 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
3196
69ae5439 3197 ether_type = (!is_udp) ? ETH_P_IBOE:
3ef967a4
MS		 3198 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6);
3199
c0c1d3d7 3200 mlx->sched_prio = cpu_to_be16(pcp);
fa417f7b 3201
1049f138 3202 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);
fa417f7b 3203 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
6ee51a4e
JM		 3204 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
3205 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
3206 memcpy(&in6, sgid.raw, sizeof(in6));
5ea8bbfc 3207
3e0629cb 3208
fa417f7b
EC		 3209 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
3210 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
4c3eb3ca 3211 if (!is_vlan) {
3ef967a4 3212 sqp->ud_header.eth.type = cpu_to_be16(ether_type);
4c3eb3ca 3213 } else {
3ef967a4 3214 sqp->ud_header.vlan.type = cpu_to_be16(ether_type);
4c3eb3ca
EC		 3215 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
3216 }
fa417f7b 3217 } else {
fd10ed8e
JM		 3218 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 :
3219 sl_to_vl(to_mdev(ib_dev),
3220 sqp->ud_header.lrh.service_level,
3221 sqp->qp.port);
3222 if (sqp->qp.ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15)
3223 return -EINVAL;
fa417f7b
EC		 3224 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
3225 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
3226 }
e622f2f4 3227 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
225c7b1f
RD		 3228 if (!sqp->qp.ibqp.qp_num)
3229 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
3230 else
e622f2f4 3231 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index, &pkey);
225c7b1f 3232 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
e622f2f4 3233 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
225c7b1f 3234 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
e622f2f4
CH		 3235 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
3236 sqp->qkey : wr->remote_qkey);
225c7b1f
RD		 3237 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
3238
3239 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
3240
3241 if (0) {
987c8f8f 3242 pr_err("built UD header of size %d:\n", header_size);
225c7b1f
RD		 3243 for (i = 0; i < header_size / 4; ++i) {
3244 if (i % 8 == 0)
987c8f8f
SP		 3245 pr_err(" [%02x] ", i * 4);
3246 pr_cont(" %08x",
3247 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
225c7b1f 3248 if ((i + 1) % 8 == 0)
987c8f8f 3249 pr_cont("\n");
225c7b1f 3250 }
987c8f8f 3251 pr_err("\n");
225c7b1f
RD		 3252 }
3253
e61ef241
RD		 3254 /*
3255 * Inline data segments may not cross a 64 byte boundary. If
3256 * our UD header is bigger than the space available up to the
3257 * next 64 byte boundary in the WQE, use two inline data
3258 * segments to hold the UD header.
3259 */
3260 spc = MLX4_INLINE_ALIGN -
3261 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3262 if (header_size <= spc) {
3263 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
3264 memcpy(inl + 1, sqp->header_buf, header_size);
3265 i = 1;
3266 } else {
3267 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3268 memcpy(inl + 1, sqp->header_buf, spc);
3269
3270 inl = (void *) (inl + 1) + spc;
3271 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
3272 /*
3273 * Need a barrier here to make sure all the data is
3274 * visible before the byte_count field is set.
3275 * Otherwise the HCA prefetcher could grab the 64-byte
3276 * chunk with this inline segment and get a valid (!=
3277 * 0xffffffff) byte count but stale data, and end up
3278 * generating a packet with bad headers.
3279 *
3280 * The first inline segment's byte_count field doesn't
3281 * need a barrier, because it comes after a
3282 * control/MLX segment and therefore is at an offset
3283 * of 16 mod 64.
3284 */
3285 wmb();
3286 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
3287 i = 2;
3288 }
225c7b1f 3289
f438000f
RD		 3290 *mlx_seg_len =
3291 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
3292 return 0;
225c7b1f
RD		 3293}
3294
3295static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3296{
3297 unsigned cur;
3298 struct mlx4_ib_cq *cq;
3299
3300 cur = wq->head - wq->tail;
0e6e7416 3301 if (likely(cur + nreq < wq->max_post))
225c7b1f
RD		 3302 return 0;
3303
3304 cq = to_mcq(ib_cq);
3305 spin_lock(&cq->lock);
3306 cur = wq->head - wq->tail;
3307 spin_unlock(&cq->lock);
3308
0e6e7416 3309 return cur + nreq >= wq->max_post;
225c7b1f
RD		 3310}
3311
95d04f07
RD		 3312static __be32 convert_access(int acc)
3313{
6ff63e19
SM		 3314 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
3315 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
3316 (acc & IB_ACCESS_REMOTE_WRITE ?
3317 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
3318 (acc & IB_ACCESS_REMOTE_READ ?
3319 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
95d04f07
RD		 3320 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
3321 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
3322}
3323
1b2cd0fc
SG		 3324static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
3325 struct ib_reg_wr *wr)
3326{
3327 struct mlx4_ib_mr *mr = to_mmr(wr->mr);
3328
3329 fseg->flags = convert_access(wr->access);
3330 fseg->mem_key = cpu_to_be32(wr->key);
3331 fseg->buf_list = cpu_to_be64(mr->page_map);
3332 fseg->start_addr = cpu_to_be64(mr->ibmr.iova);
3333 fseg->reg_len = cpu_to_be64(mr->ibmr.length);
3334 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
3335 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size));
3336 fseg->reserved[0] = 0;
3337 fseg->reserved[1] = 0;
3338}
3339
95d04f07
RD		 3340static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
3341{
aee38fad
SM		 3342 memset(iseg, 0, sizeof(*iseg));
3343 iseg->mem_key = cpu_to_be32(rkey);
95d04f07
RD		 3344}
3345
0fbfa6a9
RD		 3346static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
3347 u64 remote_addr, u32 rkey)
3348{
3349 rseg->raddr = cpu_to_be64(remote_addr);
3350 rseg->rkey = cpu_to_be32(rkey);
3351 rseg->reserved = 0;
3352}
3353
e622f2f4
CH		 3354static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
3355 struct ib_atomic_wr *wr)
0fbfa6a9 3356{
e622f2f4
CH		 3357 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
3358 aseg->swap_add = cpu_to_be64(wr->swap);
3359 aseg->compare = cpu_to_be64(wr->compare_add);
3360 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
3361 aseg->swap_add = cpu_to_be64(wr->compare_add);
3362 aseg->compare = cpu_to_be64(wr->compare_add_mask);
0fbfa6a9 3363 } else {
e622f2f4 3364 aseg->swap_add = cpu_to_be64(wr->compare_add);
0fbfa6a9
RD		 3365 aseg->compare = 0;
3366 }
3367
3368}
3369
6fa8f719 3370static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
e622f2f4 3371 struct ib_atomic_wr *wr)
6fa8f719 3372{
e622f2f4
CH		 3373 aseg->swap_add = cpu_to_be64(wr->swap);
3374 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask);
3375 aseg->compare = cpu_to_be64(wr->compare_add);
3376 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask);
6fa8f719
VS		 3377}
3378
0fbfa6a9 3379static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
e622f2f4 3380 struct ib_ud_wr *wr)
0fbfa6a9 3381{
e622f2f4
CH		 3382 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
3383 dseg->dqpn = cpu_to_be32(wr->remote_qpn);
3384 dseg->qkey = cpu_to_be32(wr->remote_qkey);
3385 dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
3386 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
0fbfa6a9
RD		 3387}
3388
1ffeb2eb
JM		 3389static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
3390 struct mlx4_wqe_datagram_seg *dseg,
e622f2f4 3391 struct ib_ud_wr *wr,
97982f5a 3392 enum mlx4_ib_qp_type qpt)
1ffeb2eb 3393{
e622f2f4 3394 union mlx4_ext_av *av = &to_mah(wr->ah)->av;
1ffeb2eb
JM		 3395 struct mlx4_av sqp_av = {0};
3396 int port = *((u8 *) &av->ib.port_pd) & 0x3;
3397
3398 /* force loopback */
3399 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
3400 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
3401 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
3402 cpu_to_be32(0xf0000000);
3403
3404 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
97982f5a
JM		 3405 if (qpt == MLX4_IB_QPT_PROXY_GSI)
3406 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
3407 else
3408 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]);
47605df9
JM		 3409 /* Use QKEY from the QP context, which is set by master */
3410 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1ffeb2eb
JM		 3411}
3412
e622f2f4 3413static void build_tunnel_header(struct ib_ud_wr *wr, void *wqe, unsigned *mlx_seg_len)
1ffeb2eb
JM		 3414{
3415 struct mlx4_wqe_inline_seg *inl = wqe;
3416 struct mlx4_ib_tunnel_header hdr;
e622f2f4 3417 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 3418 int spc;
3419 int i;
3420
3421 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
e622f2f4
CH		 3422 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
3423 hdr.pkey_index = cpu_to_be16(wr->pkey_index);
3424 hdr.qkey = cpu_to_be32(wr->remote_qkey);
5ea8bbfc
JM		 3425 memcpy(hdr.mac, ah->av.eth.mac, 6);
3426 hdr.vlan = ah->av.eth.vlan;
1ffeb2eb
JM		 3427
3428 spc = MLX4_INLINE_ALIGN -
3429 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3430 if (sizeof (hdr) <= spc) {
3431 memcpy(inl + 1, &hdr, sizeof (hdr));
3432 wmb();
3433 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
3434 i = 1;
3435 } else {
3436 memcpy(inl + 1, &hdr, spc);
3437 wmb();
3438 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3439
3440 inl = (void *) (inl + 1) + spc;
3441 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
3442 wmb();
3443 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
3444 i = 2;
3445 }
3446
3447 *mlx_seg_len =
3448 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
3449}
3450
6e694ea3
JM		 3451static void set_mlx_icrc_seg(void *dseg)
3452{
3453 u32 *t = dseg;
3454 struct mlx4_wqe_inline_seg *iseg = dseg;
3455
3456 t[1] = 0;
3457
3458 /*
3459 * Need a barrier here before writing the byte_count field to
3460 * make sure that all the data is visible before the
3461 * byte_count field is set. Otherwise, if the segment begins
3462 * a new cacheline, the HCA prefetcher could grab the 64-byte
3463 * chunk and get a valid (!= * 0xffffffff) byte count but
3464 * stale data, and end up sending the wrong data.
3465 */
3466 wmb();
3467
3468 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
3469}
3470
3471static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
d420d9e3 3472{
d420d9e3
RD		 3473 dseg->lkey = cpu_to_be32(sg->lkey);
3474 dseg->addr = cpu_to_be64(sg->addr);
6e694ea3
JM		 3475
3476 /*
3477 * Need a barrier here before writing the byte_count field to
3478 * make sure that all the data is visible before the
3479 * byte_count field is set. Otherwise, if the segment begins
3480 * a new cacheline, the HCA prefetcher could grab the 64-byte
3481 * chunk and get a valid (!= * 0xffffffff) byte count but
3482 * stale data, and end up sending the wrong data.
3483 */
3484 wmb();
3485
3486 dseg->byte_count = cpu_to_be32(sg->length);
d420d9e3
RD		 3487}
3488
2242fa4f
RD		 3489static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
3490{
3491 dseg->byte_count = cpu_to_be32(sg->length);
3492 dseg->lkey = cpu_to_be32(sg->lkey);
3493 dseg->addr = cpu_to_be64(sg->addr);
3494}
3495
e622f2f4 3496static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_ud_wr *wr,
0fd7e1d8 3497 struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
417608c2 3498 __be32 *lso_hdr_sz, __be32 *blh)
b832be1e 3499{
e622f2f4 3500 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
b832be1e 3501
417608c2
EC		 3502 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
3503 *blh = cpu_to_be32(1 << 6);
b832be1e
EC		 3504
3505 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
e622f2f4 3506 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
b832be1e
EC		 3507 return -EINVAL;
3508
e622f2f4 3509 memcpy(wqe->header, wr->header, wr->hlen);
b832be1e 3510
e622f2f4 3511 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen);
b832be1e
EC		 3512 *lso_seg_len = halign;
3513 return 0;
3514}
3515
95d04f07
RD		 3516static __be32 send_ieth(struct ib_send_wr *wr)
3517{
3518 switch (wr->opcode) {
3519 case IB_WR_SEND_WITH_IMM:
3520 case IB_WR_RDMA_WRITE_WITH_IMM:
3521 return wr->ex.imm_data;
3522
3523 case IB_WR_SEND_WITH_INV:
3524 return cpu_to_be32(wr->ex.invalidate_rkey);
3525
3526 default:
3527 return 0;
3528 }
3529}
3530
1ffeb2eb
JM		 3531static void add_zero_len_inline(void *wqe)
3532{
3533 struct mlx4_wqe_inline_seg *inl = wqe;
3534 memset(wqe, 0, 16);
3535 inl->byte_count = cpu_to_be32(1 << 31);
3536}
3537
225c7b1f
RD		 3538int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3539 struct ib_send_wr **bad_wr)
3540{
3541 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3542 void *wqe;
3543 struct mlx4_wqe_ctrl_seg *ctrl;
6e694ea3 3544 struct mlx4_wqe_data_seg *dseg;
225c7b1f
RD		 3545 unsigned long flags;
3546 int nreq;
3547 int err = 0;
ea54b10c
JM		 3548 unsigned ind;
3549 int uninitialized_var(stamp);
3550 int uninitialized_var(size);
a3d8e159 3551 unsigned uninitialized_var(seglen);
0fd7e1d8
RD		 3552 __be32 dummy;
3553 __be32 *lso_wqe;
3554 __be32 uninitialized_var(lso_hdr_sz);
417608c2 3555 __be32 blh;
225c7b1f 3556 int i;
35f05dab 3557 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3558
e1b866c6
MS		 3559 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
3560 struct mlx4_ib_sqp *sqp = to_msqp(qp);
3561
3562 if (sqp->roce_v2_gsi) {
3563 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah);
a748d60d 3564 enum ib_gid_type gid_type;
e1b866c6
MS		 3565 union ib_gid gid;
3566
a748d60d
TB		 3567 if (!fill_gid_by_hw_index(mdev, sqp->qp.port,
3568 ah->av.ib.gid_index,
3569 &gid, &gid_type))
3570 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ?
3571 to_mqp(sqp->roce_v2_gsi) : qp;
3572 else
e1b866c6
MS		 3573 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n",
3574 ah->av.ib.gid_index);
e1b866c6
MS		 3575 }
3576 }
3577
96db0e03 3578 spin_lock_irqsave(&qp->sq.lock, flags);
35f05dab
YH		 3579 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3580 err = -EIO;
3581 *bad_wr = wr;
3582 nreq = 0;
3583 goto out;
3584 }
225c7b1f 3585
ea54b10c 3586 ind = qp->sq_next_wqe;
225c7b1f
RD		 3587
3588 for (nreq = 0; wr; ++nreq, wr = wr->next) {
0fd7e1d8 3589 lso_wqe = &dummy;
417608c2 3590 blh = 0;
0fd7e1d8 3591
225c7b1f
RD		 3592 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
3593 err = -ENOMEM;
3594 *bad_wr = wr;
3595 goto out;
3596 }
3597
3598 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
3599 err = -EINVAL;
3600 *bad_wr = wr;
3601 goto out;
3602 }
3603
0e6e7416 3604 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
ea54b10c 3605 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
225c7b1f
RD		 3606
3607 ctrl->srcrb_flags =
3608 (wr->send_flags & IB_SEND_SIGNALED ?
3609 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
3610 (wr->send_flags & IB_SEND_SOLICITED ?
3611 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
8ff095ec
EC		 3612 ((wr->send_flags & IB_SEND_IP_CSUM) ?
3613 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
3614 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
225c7b1f
RD		 3615 qp->sq_signal_bits;
3616
95d04f07 3617 ctrl->imm = send_ieth(wr);
225c7b1f
RD		 3618
3619 wqe += sizeof *ctrl;
3620 size = sizeof *ctrl / 16;
3621
1ffeb2eb
JM		 3622 switch (qp->mlx4_ib_qp_type) {
3623 case MLX4_IB_QPT_RC:
3624 case MLX4_IB_QPT_UC:
225c7b1f
RD		 3625 switch (wr->opcode) {
3626 case IB_WR_ATOMIC_CMP_AND_SWP:
3627 case IB_WR_ATOMIC_FETCH_AND_ADD:
6fa8f719 3628 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
e622f2f4
CH		 3629 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3630 atomic_wr(wr)->rkey);
225c7b1f
RD		 3631 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3632
e622f2f4 3633 set_atomic_seg(wqe, atomic_wr(wr));
225c7b1f 3634 wqe += sizeof (struct mlx4_wqe_atomic_seg);
0fbfa6a9 3635
225c7b1f
RD		 3636 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3637 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
6fa8f719
VS		 3638
3639 break;
3640
3641 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
e622f2f4
CH		 3642 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3643 atomic_wr(wr)->rkey);
6fa8f719
VS		 3644 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3645
e622f2f4 3646 set_masked_atomic_seg(wqe, atomic_wr(wr));
6fa8f719
VS		 3647 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
3648
3649 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3650 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
225c7b1f
RD		 3651
3652 break;
3653
3654 case IB_WR_RDMA_READ:
3655 case IB_WR_RDMA_WRITE:
3656 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3657 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
3658 rdma_wr(wr)->rkey);
225c7b1f
RD		 3659 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3660 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
225c7b1f 3661 break;
95d04f07
RD		 3662
3663 case IB_WR_LOCAL_INV:
2ac6bf4d
JM		 3664 ctrl->srcrb_flags |=
3665 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 3666 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
3667 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
3668 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
3669 break;
3670
1b2cd0fc
SG		 3671 case IB_WR_REG_MR:
3672 ctrl->srcrb_flags |=
3673 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3674 set_reg_seg(wqe, reg_wr(wr));
3675 wqe += sizeof(struct mlx4_wqe_fmr_seg);
3676 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
3677 break;
3678
225c7b1f
RD		 3679 default:
3680 /* No extra segments required for sends */
3681 break;
3682 }
3683 break;
3684
1ffeb2eb 3685 case MLX4_IB_QPT_TUN_SMI_OWNER:
e622f2f4
CH		 3686 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3687 ctrl, &seglen);
1ffeb2eb
JM		 3688 if (unlikely(err)) {
3689 *bad_wr = wr;
3690 goto out;
3691 }
3692 wqe += seglen;
3693 size += seglen / 16;
3694 break;
3695 case MLX4_IB_QPT_TUN_SMI:
3696 case MLX4_IB_QPT_TUN_GSI:
3697 /* this is a UD qp used in MAD responses to slaves. */
e622f2f4 3698 set_datagram_seg(wqe, ud_wr(wr));
1ffeb2eb
JM		 3699 /* set the forced-loopback bit in the data seg av */
3700 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
3701 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3702 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3703 break;
3704 case MLX4_IB_QPT_UD:
e622f2f4 3705 set_datagram_seg(wqe, ud_wr(wr));
225c7b1f
RD		 3706 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3707 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
b832be1e
EC		 3708
3709 if (wr->opcode == IB_WR_LSO) {
e622f2f4
CH		 3710 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
3711 &lso_hdr_sz, &blh);
b832be1e
EC		 3712 if (unlikely(err)) {
3713 *bad_wr = wr;
3714 goto out;
3715 }
0fd7e1d8 3716 lso_wqe = (__be32 *) wqe;
b832be1e
EC		 3717 wqe += seglen;
3718 size += seglen / 16;
3719 }
225c7b1f
RD		 3720 break;
3721
1ffeb2eb 3722 case MLX4_IB_QPT_PROXY_SMI_OWNER:
e622f2f4
CH		 3723 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3724 ctrl, &seglen);
1ffeb2eb
JM		 3725 if (unlikely(err)) {
3726 *bad_wr = wr;
3727 goto out;
3728 }
3729 wqe += seglen;
3730 size += seglen / 16;
3731 /* to start tunnel header on a cache-line boundary */
3732 add_zero_len_inline(wqe);
3733 wqe += 16;
3734 size++;
e622f2f4 3735 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 3736 wqe += seglen;
3737 size += seglen / 16;
3738 break;
3739 case MLX4_IB_QPT_PROXY_SMI:
1ffeb2eb
JM		 3740 case MLX4_IB_QPT_PROXY_GSI:
3741 /* If we are tunneling special qps, this is a UD qp.
3742 * In this case we first add a UD segment targeting
3743 * the tunnel qp, and then add a header with address
3744 * information */
e622f2f4
CH		 3745 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
3746 ud_wr(wr),
97982f5a 3747 qp->mlx4_ib_qp_type);
1ffeb2eb
JM		 3748 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3749 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
e622f2f4 3750 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 3751 wqe += seglen;
3752 size += seglen / 16;
3753 break;
3754
3755 case MLX4_IB_QPT_SMI:
3756 case MLX4_IB_QPT_GSI:
e622f2f4
CH		 3757 err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
3758 &seglen);
f438000f 3759 if (unlikely(err)) {
225c7b1f
RD		 3760 *bad_wr = wr;
3761 goto out;
3762 }
f438000f
RD		 3763 wqe += seglen;
3764 size += seglen / 16;
225c7b1f
RD		 3765 break;
3766
3767 default:
3768 break;
3769 }
3770
6e694ea3
JM		 3771 /*
3772 * Write data segments in reverse order, so as to
3773 * overwrite cacheline stamp last within each
3774 * cacheline. This avoids issues with WQE
3775 * prefetching.
3776 */
225c7b1f 3777
6e694ea3
JM		 3778 dseg = wqe;
3779 dseg += wr->num_sge - 1;
3780 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
225c7b1f
RD		 3781
3782 /* Add one more inline data segment for ICRC for MLX sends */
1ffeb2eb
JM		 3783 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
3784 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
3785 qp->mlx4_ib_qp_type &
3786 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6e694ea3 3787 set_mlx_icrc_seg(dseg + 1);
225c7b1f
RD		 3788 size += sizeof (struct mlx4_wqe_data_seg) / 16;
3789 }
3790
6e694ea3
JM		 3791 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3792 set_data_seg(dseg, wr->sg_list + i);
3793
0fd7e1d8
RD		 3794 /*
3795 * Possibly overwrite stamping in cacheline with LSO
3796 * segment only after making sure all data segments
3797 * are written.
3798 */
3799 wmb();
3800 *lso_wqe = lso_hdr_sz;
3801
224e92e0
BB		 3802 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ?
3803 MLX4_WQE_CTRL_FENCE : 0) | size;
225c7b1f
RD		 3804
3805 /*
3806 * Make sure descriptor is fully written before
3807 * setting ownership bit (because HW can start
3808 * executing as soon as we do).
3809 */
3810 wmb();
3811
59b0ed12 3812 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
4ba6b8ea 3813 *bad_wr = wr;
225c7b1f
RD		 3814 err = -EINVAL;
3815 goto out;
3816 }
3817
3818 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
417608c2 3819 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
0e6e7416 3820
ea54b10c
JM		 3821 stamp = ind + qp->sq_spare_wqes;
3822 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
3823
0e6e7416
RD		 3824 /*
3825 * We can improve latency by not stamping the last
3826 * send queue WQE until after ringing the doorbell, so
3827 * only stamp here if there are still more WQEs to post.
ea54b10c
JM		 3828 *
3829 * Same optimization applies to padding with NOP wqe
3830 * in case of WQE shrinking (used to prevent wrap-around
3831 * in the middle of WR).
0e6e7416 3832 */
ea54b10c
JM		 3833 if (wr->next) {
3834 stamp_send_wqe(qp, stamp, size * 16);
3835 ind = pad_wraparound(qp, ind);
3836 }
225c7b1f
RD		 3837 }
3838
3839out:
3840 if (likely(nreq)) {
3841 qp->sq.head += nreq;
3842
3843 /*
3844 * Make sure that descriptors are written before
3845 * doorbell record.
3846 */
3847 wmb();
3848
3849 writel(qp->doorbell_qpn,
3850 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3851
3852 /*
3853 * Make sure doorbells don't leak out of SQ spinlock
3854 * and reach the HCA out of order.
3855 */
3856 mmiowb();
0e6e7416 3857
ea54b10c
JM		 3858 stamp_send_wqe(qp, stamp, size * 16);
3859
3860 ind = pad_wraparound(qp, ind);
3861 qp->sq_next_wqe = ind;
225c7b1f
RD		 3862 }
3863
96db0e03 3864 spin_unlock_irqrestore(&qp->sq.lock, flags);
225c7b1f
RD		 3865
3866 return err;
3867}
3868
3869int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3870 struct ib_recv_wr **bad_wr)
3871{
3872 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3873 struct mlx4_wqe_data_seg *scat;
3874 unsigned long flags;
3875 int err = 0;
3876 int nreq;
3877 int ind;
1ffeb2eb 3878 int max_gs;
225c7b1f 3879 int i;
35f05dab 3880 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3881
1ffeb2eb 3882 max_gs = qp->rq.max_gs;
225c7b1f
RD		 3883 spin_lock_irqsave(&qp->rq.lock, flags);
3884
35f05dab
YH		 3885 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3886 err = -EIO;
3887 *bad_wr = wr;
3888 nreq = 0;
3889 goto out;
3890 }
3891
0e6e7416 3892 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3893
3894 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2b946077 3895 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
225c7b1f
RD		 3896 err = -ENOMEM;
3897 *bad_wr = wr;
3898 goto out;
3899 }
3900
3901 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3902 err = -EINVAL;
3903 *bad_wr = wr;
3904 goto out;
3905 }
3906
3907 scat = get_recv_wqe(qp, ind);
3908
1ffeb2eb
JM		 3909 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3910 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3911 ib_dma_sync_single_for_device(ibqp->device,
3912 qp->sqp_proxy_rcv[ind].map,
3913 sizeof (struct mlx4_ib_proxy_sqp_hdr),
3914 DMA_FROM_DEVICE);
3915 scat->byte_count =
3916 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3917 /* use dma lkey from upper layer entry */
3918 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3919 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3920 scat++;
3921 max_gs--;
3922 }
3923
2242fa4f
RD		 3924 for (i = 0; i < wr->num_sge; ++i)
3925 __set_data_seg(scat + i, wr->sg_list + i);
225c7b1f 3926
1ffeb2eb 3927 if (i < max_gs) {
225c7b1f
RD		 3928 scat[i].byte_count = 0;
3929 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
3930 scat[i].addr = 0;
3931 }
3932
3933 qp->rq.wrid[ind] = wr->wr_id;
3934
0e6e7416 3935 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3936 }
3937
3938out:
3939 if (likely(nreq)) {
3940 qp->rq.head += nreq;
3941
3942 /*
3943 * Make sure that descriptors are written before
3944 * doorbell record.
3945 */
3946 wmb();
3947
3948 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3949 }
3950
3951 spin_unlock_irqrestore(&qp->rq.lock, flags);
3952
3953 return err;
3954}
6a775e2b
JM		 3955
3956static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3957{
3958 switch (mlx4_state) {
3959 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
3960 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
3961 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
3962 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
3963 case MLX4_QP_STATE_SQ_DRAINING:
3964 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
3965 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
3966 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
3967 default: return -1;
3968 }
3969}
3970
3971static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3972{
3973 switch (mlx4_mig_state) {
3974 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
3975 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
3976 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3977 default: return -1;
3978 }
3979}
3980
3981static int to_ib_qp_access_flags(int mlx4_flags)
3982{
3983 int ib_flags = 0;
3984
3985 if (mlx4_flags & MLX4_QP_BIT_RRE)
3986 ib_flags |= IB_ACCESS_REMOTE_READ;
3987 if (mlx4_flags & MLX4_QP_BIT_RWE)
3988 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3989 if (mlx4_flags & MLX4_QP_BIT_RAE)
3990 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3991
3992 return ib_flags;
3993}
3994
71d53ab4 3995static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev,
d8966fcd 3996 struct rdma_ah_attr *ah_attr,
71d53ab4 3997 struct mlx4_qp_path *path)
6a775e2b 3998{
4c3eb3ca 3999 struct mlx4_dev *dev = ibdev->dev;
d8966fcd 4000 u8 port_num = path->sched_queue & 0x40 ? 2 : 1;
4c3eb3ca 4001
d8966fcd 4002 memset(ah_attr, 0, sizeof(*ah_attr));
44c58487 4003 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num);
d8966fcd 4004 if (port_num == 0 || port_num > dev->caps.num_ports)
6a775e2b
JM		 4005 return;
4006
44c58487 4007 if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE)
d8966fcd
DC		 4008 rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) |
4009 ((path->sched_queue & 4) << 1));
4c3eb3ca 4010 else
d8966fcd 4011 rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf);
44c58487 4012 rdma_ah_set_port_num(ah_attr, port_num);
4c3eb3ca 4013
d8966fcd
DC		 4014 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4015 rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f);
4016 rdma_ah_set_static_rate(ah_attr,
4017 path->static_rate ? path->static_rate - 5 : 0);
4018 if (path->grh_mylmc & (1 << 7)) {
4019 rdma_ah_set_grh(ah_attr, NULL,
4020 be32_to_cpu(path->tclass_flowlabel) & 0xfffff,
4021 path->mgid_index,
4022 path->hop_limit,
4023 (be32_to_cpu(path->tclass_flowlabel)
4024 >> 20) & 0xff);
4025 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
6a775e2b
JM		 4026 }
4027}
4028
4029int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
4030 struct ib_qp_init_attr *qp_init_attr)
4031{
4032 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
4033 struct mlx4_ib_qp *qp = to_mqp(ibqp);
4034 struct mlx4_qp_context context;
4035 int mlx4_state;
0df67030
DB		 4036 int err = 0;
4037
3078f5f1
GL		 4038 if (ibqp->rwq_ind_tbl)
4039 return -EOPNOTSUPP;
4040
0df67030 4041 mutex_lock(&qp->mutex);
6a775e2b
JM		 4042
4043 if (qp->state == IB_QPS_RESET) {
4044 qp_attr->qp_state = IB_QPS_RESET;
4045 goto done;
4046 }
4047
4048 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
0df67030
DB		 4049 if (err) {
4050 err = -EINVAL;
4051 goto out;
4052 }
6a775e2b
JM		 4053
4054 mlx4_state = be32_to_cpu(context.flags) >> 28;
4055
0df67030
DB		 4056 qp->state = to_ib_qp_state(mlx4_state);
4057 qp_attr->qp_state = qp->state;
6a775e2b
JM		 4058 qp_attr->path_mtu = context.mtu_msgmax >> 5;
4059 qp_attr->path_mig_state =
4060 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
4061 qp_attr->qkey = be32_to_cpu(context.qkey);
4062 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
4063 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
4064 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
4065 qp_attr->qp_access_flags =
4066 to_ib_qp_access_flags(be32_to_cpu(context.params2));
4067
4068 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
71d53ab4
DC		 4069 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
4070 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
6a775e2b 4071 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
d8966fcd
DC		 4072 qp_attr->alt_port_num =
4073 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
6a775e2b
JM		 4074 }
4075
4076 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1c27cb71
JM		 4077 if (qp_attr->qp_state == IB_QPS_INIT)
4078 qp_attr->port_num = qp->port;
4079 else
4080 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
6a775e2b
JM		 4081
4082 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4083 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
4084
4085 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
4086
4087 qp_attr->max_dest_rd_atomic =
4088 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
4089 qp_attr->min_rnr_timer =
4090 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
4091 qp_attr->timeout = context.pri_path.ackto >> 3;
4092 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
4093 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
4094 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
4095
4096done:
4097 qp_attr->cur_qp_state = qp_attr->qp_state;
7f5eb9bb
RD		 4098 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4099 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4100
6a775e2b 4101 if (!ibqp->uobject) {
7f5eb9bb
RD		 4102 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
4103 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4104 } else {
4105 qp_attr->cap.max_send_wr = 0;
4106 qp_attr->cap.max_send_sge = 0;
6a775e2b
JM		 4107 }
4108
7f5eb9bb
RD		 4109 /*
4110 * We don't support inline sends for kernel QPs (yet), and we
4111 * don't know what userspace's value should be.
4112 */
4113 qp_attr->cap.max_inline_data = 0;
4114
4115 qp_init_attr->cap = qp_attr->cap;
4116
521e575b
RL		 4117 qp_init_attr->create_flags = 0;
4118 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4119 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4120
4121 if (qp->flags & MLX4_IB_QP_LSO)
4122 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
4123
c1c98501
MB		 4124 if (qp->flags & MLX4_IB_QP_NETIF)
4125 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
4126
46db567d
DB		 4127 qp_init_attr->sq_sig_type =
4128 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
4129 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4130
0df67030
DB		 4131out:
4132 mutex_unlock(&qp->mutex);
4133 return err;
6a775e2b
JM		 4134}
4135
400b1ebc
GL		 4136struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd,
4137 struct ib_wq_init_attr *init_attr,
4138 struct ib_udata *udata)
4139{
4140 struct mlx4_ib_dev *dev;
4141 struct ib_qp_init_attr ib_qp_init_attr;
4142 struct mlx4_ib_qp *qp;
4143 struct mlx4_ib_create_wq ucmd;
4144 int err, required_cmd_sz;
4145
4146 if (!(udata && pd->uobject))
4147 return ERR_PTR(-EINVAL);
4148
4149 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
4150 sizeof(ucmd.reserved);
4151 if (udata->inlen < required_cmd_sz) {
4152 pr_debug("invalid inlen\n");
4153 return ERR_PTR(-EINVAL);
4154 }
4155
4156 if (udata->inlen > sizeof(ucmd) &&
4157 !ib_is_udata_cleared(udata, sizeof(ucmd),
4158 udata->inlen - sizeof(ucmd))) {
4159 pr_debug("inlen is not supported\n");
4160 return ERR_PTR(-EOPNOTSUPP);
4161 }
4162
4163 if (udata->outlen)
4164 return ERR_PTR(-EOPNOTSUPP);
4165
4166 dev = to_mdev(pd->device);
4167
4168 if (init_attr->wq_type != IB_WQT_RQ) {
4169 pr_debug("unsupported wq type %d\n", init_attr->wq_type);
4170 return ERR_PTR(-EOPNOTSUPP);
4171 }
4172
4173 if (init_attr->create_flags) {
4174 pr_debug("unsupported create_flags %u\n",
4175 init_attr->create_flags);
4176 return ERR_PTR(-EOPNOTSUPP);
4177 }
4178
4179 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
4180 if (!qp)
4181 return ERR_PTR(-ENOMEM);
4182
4183 qp->pri.vid = 0xFFFF;
4184 qp->alt.vid = 0xFFFF;
4185
4186 memset(&ib_qp_init_attr, 0, sizeof(ib_qp_init_attr));
4187 ib_qp_init_attr.qp_context = init_attr->wq_context;
4188 ib_qp_init_attr.qp_type = IB_QPT_RAW_PACKET;
4189 ib_qp_init_attr.cap.max_recv_wr = init_attr->max_wr;
4190 ib_qp_init_attr.cap.max_recv_sge = init_attr->max_sge;
4191 ib_qp_init_attr.recv_cq = init_attr->cq;
4192 ib_qp_init_attr.send_cq = ib_qp_init_attr.recv_cq; /* Dummy CQ */
4193
4194 err = create_qp_common(dev, pd, MLX4_IB_RWQ_SRC, &ib_qp_init_attr,
4195 udata, 0, &qp);
4196 if (err) {
4197 kfree(qp);
4198 return ERR_PTR(err);
4199 }
4200
4201 qp->ibwq.event_handler = init_attr->event_handler;
4202 qp->ibwq.wq_num = qp->mqp.qpn;
4203 qp->ibwq.state = IB_WQS_RESET;
4204
4205 return &qp->ibwq;
4206}
4207
4208static int ib_wq2qp_state(enum ib_wq_state state)
4209{
4210 switch (state) {
4211 case IB_WQS_RESET:
4212 return IB_QPS_RESET;
4213 case IB_WQS_RDY:
4214 return IB_QPS_RTR;
4215 default:
4216 return IB_QPS_ERR;
4217 }
4218}
4219
4220static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state)
4221{
4222 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4223 enum ib_qp_state qp_cur_state;
4224 enum ib_qp_state qp_new_state;
4225 int attr_mask;
4226 int err;
4227
4228 /* ib_qp.state represents the WQ HW state while ib_wq.state represents
4229 * the WQ logic state.
4230 */
4231 qp_cur_state = qp->state;
4232 qp_new_state = ib_wq2qp_state(new_state);
4233
4234 if (ib_wq2qp_state(new_state) == qp_cur_state)
4235 return 0;
4236
4237 if (new_state == IB_WQS_RDY) {
4238 struct ib_qp_attr attr = {};
4239
4240 attr.port_num = qp->port;
4241 attr_mask = IB_QP_PORT;
4242
4243 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, &attr,
4244 attr_mask, IB_QPS_RESET, IB_QPS_INIT);
4245 if (err) {
4246 pr_debug("WQN=0x%06x failed to apply RST->INIT on the HW QP\n",
4247 ibwq->wq_num);
4248 return err;
4249 }
4250
4251 qp_cur_state = IB_QPS_INIT;
4252 }
4253
4254 attr_mask = 0;
4255 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, attr_mask,
4256 qp_cur_state, qp_new_state);
4257
4258 if (err && (qp_cur_state == IB_QPS_INIT)) {
4259 qp_new_state = IB_QPS_RESET;
4260 if (__mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL,
4261 attr_mask, IB_QPS_INIT, IB_QPS_RESET)) {
4262 pr_warn("WQN=0x%06x failed with reverting HW's resources failure\n",
4263 ibwq->wq_num);
4264 qp_new_state = IB_QPS_INIT;
4265 }
4266 }
4267
4268 qp->state = qp_new_state;
4269
4270 return err;
4271}
4272
4273int mlx4_ib_modify_wq(struct ib_wq *ibwq, struct ib_wq_attr *wq_attr,
4274 u32 wq_attr_mask, struct ib_udata *udata)
4275{
4276 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4277 struct mlx4_ib_modify_wq ucmd = {};
4278 size_t required_cmd_sz;
4279 enum ib_wq_state cur_state, new_state;
4280 int err = 0;
4281
4282 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
4283 sizeof(ucmd.reserved);
4284 if (udata->inlen < required_cmd_sz)
4285 return -EINVAL;
4286
4287 if (udata->inlen > sizeof(ucmd) &&
4288 !ib_is_udata_cleared(udata, sizeof(ucmd),
4289 udata->inlen - sizeof(ucmd)))
4290 return -EOPNOTSUPP;
4291
4292 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4293 return -EFAULT;
4294
4295 if (ucmd.comp_mask || ucmd.reserved)
4296 return -EOPNOTSUPP;
4297
4298 if (wq_attr_mask & IB_WQ_FLAGS)
4299 return -EOPNOTSUPP;
4300
4301 cur_state = wq_attr_mask & IB_WQ_CUR_STATE ? wq_attr->curr_wq_state :
4302 ibwq->state;
4303 new_state = wq_attr_mask & IB_WQ_STATE ? wq_attr->wq_state : cur_state;
4304
4305 if (cur_state < IB_WQS_RESET || cur_state > IB_WQS_ERR ||
4306 new_state < IB_WQS_RESET || new_state > IB_WQS_ERR)
4307 return -EINVAL;
4308
4309 if ((new_state == IB_WQS_RDY) && (cur_state == IB_WQS_ERR))
4310 return -EINVAL;
4311
4312 if ((new_state == IB_WQS_ERR) && (cur_state == IB_WQS_RESET))
4313 return -EINVAL;
4314
3078f5f1
GL		 4315 /* Need to protect against the parent RSS which also may modify WQ
4316 * state.
4317 */
4318 mutex_lock(&qp->mutex);
4319
400b1ebc
GL		 4320 /* Can update HW state only if a RSS QP has already associated to this
4321 * WQ, so we can apply its port on the WQ.
4322 */
4323 if (qp->rss_usecnt)
4324 err = _mlx4_ib_modify_wq(ibwq, new_state);
4325
4326 if (!err)
4327 ibwq->state = new_state;
4328
3078f5f1
GL		 4329 mutex_unlock(&qp->mutex);
4330
400b1ebc
GL		 4331 return err;
4332}
4333
4334int mlx4_ib_destroy_wq(struct ib_wq *ibwq)
4335{
4336 struct mlx4_ib_dev *dev = to_mdev(ibwq->device);
4337 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4338
4339 if (qp->counter_index)
4340 mlx4_ib_free_qp_counter(dev, qp);
4341
4342 destroy_qp_common(dev, qp, MLX4_IB_RWQ_SRC, 1);
4343
4344 kfree(qp);
4345
4346 return 0;
4347}
b8d46ca0
GL		 4348
4349struct ib_rwq_ind_table
4350*mlx4_ib_create_rwq_ind_table(struct ib_device *device,
4351 struct ib_rwq_ind_table_init_attr *init_attr,
4352 struct ib_udata *udata)
4353{
4354 struct ib_rwq_ind_table *rwq_ind_table;
4355 struct mlx4_ib_create_rwq_ind_tbl_resp resp = {};
4356 unsigned int ind_tbl_size = 1 << init_attr->log_ind_tbl_size;
4357 unsigned int base_wqn;
4358 size_t min_resp_len;
4359 int i;
4360 int err;
4361
4362 if (udata->inlen > 0 &&
4363 !ib_is_udata_cleared(udata, 0,
4364 udata->inlen))
4365 return ERR_PTR(-EOPNOTSUPP);
4366
4367 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4368 if (udata->outlen && udata->outlen < min_resp_len)
4369 return ERR_PTR(-EINVAL);
4370
4371 if (ind_tbl_size >
4372 device->attrs.rss_caps.max_rwq_indirection_table_size) {
4373 pr_debug("log_ind_tbl_size = %d is bigger than supported = %d\n",
4374 ind_tbl_size,
4375 device->attrs.rss_caps.max_rwq_indirection_table_size);
4376 return ERR_PTR(-EINVAL);
4377 }
4378
4379 base_wqn = init_attr->ind_tbl[0]->wq_num;
4380
4381 if (base_wqn % ind_tbl_size) {
4382 pr_debug("WQN=0x%x isn't aligned with indirection table size\n",
4383 base_wqn);
4384 return ERR_PTR(-EINVAL);
4385 }
4386
4387 for (i = 1; i < ind_tbl_size; i++) {
4388 if (++base_wqn != init_attr->ind_tbl[i]->wq_num) {
4389 pr_debug("indirection table's WQNs aren't consecutive\n");
4390 return ERR_PTR(-EINVAL);
4391 }
4392 }
4393
4394 rwq_ind_table = kzalloc(sizeof(*rwq_ind_table), GFP_KERNEL);
4395 if (!rwq_ind_table)
4396 return ERR_PTR(-ENOMEM);
4397
4398 if (udata->outlen) {
4399 resp.response_length = offsetof(typeof(resp), response_length) +
4400 sizeof(resp.response_length);
4401 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4402 if (err)
4403 goto err;
4404 }
4405
4406 return rwq_ind_table;
4407
4408err:
4409 kfree(rwq_ind_table);
4410 return ERR_PTR(err);
4411}
4412
4413int mlx4_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4414{
4415 kfree(ib_rwq_ind_tbl);
4416 return 0;
4417}
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