]> git.proxmox.com Git - mirror_ubuntu-focal-kernel.git/blame - drivers/infiniband/hw/mlx4/qp.c
projects / mirror_ubuntu-focal-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
UBUNTU: Ubuntu-5.4.0-117.132
[mirror_ubuntu-focal-kernel.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
ea54b10c 34#include <linux/log2.h>
1049f138 35#include <linux/etherdevice.h>
3ef967a4 36#include <net/ip.h>
5a0e3ad6 37#include <linux/slab.h>
fa417f7b 38#include <linux/netdevice.h>
ea54b10c 39
225c7b1f
RD		 40#include <rdma/ib_cache.h>
41#include <rdma/ib_pack.h>
4c3eb3ca 42#include <rdma/ib_addr.h>
1ffeb2eb 43#include <rdma/ib_mad.h>
89944450 44#include <rdma/uverbs_ioctl.h>
225c7b1f 45
2f48485d 46#include <linux/mlx4/driver.h>
225c7b1f
RD		 47#include <linux/mlx4/qp.h>
48
49#include "mlx4_ib.h"
9ce28a20 50#include <rdma/mlx4-abi.h>
225c7b1f 51
35f05dab
YH		 52static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
53 struct mlx4_ib_cq *recv_cq);
54static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
55 struct mlx4_ib_cq *recv_cq);
89944450
SR		 56static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state,
57 struct ib_udata *udata);
35f05dab 58
225c7b1f
RD		 59enum {
60 MLX4_IB_ACK_REQ_FREQ = 8,
61};
62
63enum {
64 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
fa417f7b
EC		 65 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
66 MLX4_IB_LINK_TYPE_IB = 0,
67 MLX4_IB_LINK_TYPE_ETH = 1
225c7b1f
RD		 68};
69
70enum {
71 /*
fa417f7b 72 * Largest possible UD header: send with GRH and immediate
4c3eb3ca
EC		 73 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
74 * tag. (LRH would only use 8 bytes, so Ethernet is the
75 * biggest case)
225c7b1f 76 */
4c3eb3ca 77 MLX4_IB_UD_HEADER_SIZE = 82,
417608c2 78 MLX4_IB_LSO_HEADER_SPARE = 128,
225c7b1f
RD		 79};
80
81struct mlx4_ib_sqp {
82 struct mlx4_ib_qp qp;
83 int pkey_index;
84 u32 qkey;
85 u32 send_psn;
86 struct ib_ud_header ud_header;
87 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
e1b866c6 88 struct ib_qp *roce_v2_gsi;
225c7b1f
RD		 89};
90
83904132 91enum {
417608c2
EC		 92 MLX4_IB_MIN_SQ_STRIDE = 6,
93 MLX4_IB_CACHE_LINE_SIZE = 64,
83904132
JM		 94};
95
3987a2d3
OG		 96enum {
97 MLX4_RAW_QP_MTU = 7,
98 MLX4_RAW_QP_MSGMAX = 31,
99};
100
297e0dad
MS		 101#ifndef ETH_ALEN
102#define ETH_ALEN 6
103#endif
297e0dad 104
225c7b1f 105static const __be32 mlx4_ib_opcode[] = {
6fa8f719
VS		 106 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
107 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
108 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
109 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
110 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
111 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
112 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
113 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
114 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
115 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
1b2cd0fc 116 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
6fa8f719
VS		 117 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
118 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
225c7b1f
RD		 119};
120
400b1ebc
GL		 121enum mlx4_ib_source_type {
122 MLX4_IB_QP_SRC = 0,
123 MLX4_IB_RWQ_SRC = 1,
124};
125
225c7b1f
RD		 126static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
127{
128 return container_of(mqp, struct mlx4_ib_sqp, qp);
129}
130
1ffeb2eb
JM		 131static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
132{
133 if (!mlx4_is_master(dev->dev))
134 return 0;
135
47605df9
JM		 136 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
137 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
138 8 * MLX4_MFUNC_MAX;
1ffeb2eb
JM		 139}
140
225c7b1f
RD		 141static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
142{
47605df9
JM		 143 int proxy_sqp = 0;
144 int real_sqp = 0;
145 int i;
146 /* PPF or Native -- real SQP */
147 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
148 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
149 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
150 if (real_sqp)
151 return 1;
152 /* VF or PF -- proxy SQP */
153 if (mlx4_is_mfunc(dev->dev)) {
154 for (i = 0; i < dev->dev->caps.num_ports; i++) {
c73c8b1e
EBE		 155 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy ||
156 qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp1_proxy) {
47605df9
JM		 157 proxy_sqp = 1;
158 break;
159 }
160 }
161 }
e1b866c6
MS		 162 if (proxy_sqp)
163 return 1;
164
165 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP);
225c7b1f
RD		 166}
167
1ffeb2eb 168/* used for INIT/CLOSE port logic */
225c7b1f
RD		 169static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
170{
47605df9
JM		 171 int proxy_qp0 = 0;
172 int real_qp0 = 0;
173 int i;
174 /* PPF or Native -- real QP0 */
175 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
176 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
177 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
178 if (real_qp0)
179 return 1;
180 /* VF or PF -- proxy QP0 */
181 if (mlx4_is_mfunc(dev->dev)) {
182 for (i = 0; i < dev->dev->caps.num_ports; i++) {
c73c8b1e 183 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy) {
47605df9
JM		 184 proxy_qp0 = 1;
185 break;
186 }
187 }
188 }
189 return proxy_qp0;
225c7b1f
RD		 190}
191
192static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
193{
1c69fc2a 194 return mlx4_buf_offset(&qp->buf, offset);
225c7b1f
RD		 195}
196
197static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
198{
199 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
200}
201
202static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
203{
204 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
205}
206
0e6e7416
RD		 207/*
208 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
f95ccffc
JM		 209 * first four bytes of every 64 byte chunk with 0xffffffff, except for
210 * the very first chunk of the WQE.
0e6e7416 211 */
f95ccffc 212static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n)
0e6e7416 213{
d2ae16d5 214 __be32 *wqe;
0e6e7416 215 int i;
ea54b10c 216 int s;
ea54b10c 217 void *buf;
ea54b10c 218 struct mlx4_wqe_ctrl_seg *ctrl;
ea54b10c 219
f95ccffc
JM		 220 buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
221 ctrl = (struct mlx4_wqe_ctrl_seg *)buf;
222 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4;
223 for (i = 64; i < s; i += 64) {
224 wqe = buf + i;
225 *wqe = cpu_to_be32(0xffffffff);
ea54b10c 226 }
0e6e7416
RD		 227}
228
225c7b1f
RD		 229static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
230{
231 struct ib_event event;
232 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
233
234 if (type == MLX4_EVENT_TYPE_PATH_MIG)
235 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
236
237 if (ibqp->event_handler) {
238 event.device = ibqp->device;
239 event.element.qp = ibqp;
240 switch (type) {
241 case MLX4_EVENT_TYPE_PATH_MIG:
242 event.event = IB_EVENT_PATH_MIG;
243 break;
244 case MLX4_EVENT_TYPE_COMM_EST:
245 event.event = IB_EVENT_COMM_EST;
246 break;
247 case MLX4_EVENT_TYPE_SQ_DRAINED:
248 event.event = IB_EVENT_SQ_DRAINED;
249 break;
250 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
251 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
252 break;
253 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
254 event.event = IB_EVENT_QP_FATAL;
255 break;
256 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
257 event.event = IB_EVENT_PATH_MIG_ERR;
258 break;
259 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
260 event.event = IB_EVENT_QP_REQ_ERR;
261 break;
262 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
263 event.event = IB_EVENT_QP_ACCESS_ERR;
264 break;
265 default:
987c8f8f 266 pr_warn("Unexpected event type %d "
225c7b1f
RD		 267 "on QP %06x\n", type, qp->qpn);
268 return;
269 }
270
271 ibqp->event_handler(&event, ibqp->qp_context);
272 }
273}
274
400b1ebc
GL		 275static void mlx4_ib_wq_event(struct mlx4_qp *qp, enum mlx4_event type)
276{
277 pr_warn_ratelimited("Unexpected event type %d on WQ 0x%06x. Events are not supported for WQs\n",
278 type, qp->qpn);
279}
280
1ffeb2eb 281static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
225c7b1f
RD		 282{
283 /*
284 * UD WQEs must have a datagram segment.
285 * RC and UC WQEs might have a remote address segment.
286 * MLX WQEs need two extra inline data segments (for the UD
287 * header and space for the ICRC).
288 */
289 switch (type) {
1ffeb2eb 290 case MLX4_IB_QPT_UD:
225c7b1f 291 return sizeof (struct mlx4_wqe_ctrl_seg) +
b832be1e 292 sizeof (struct mlx4_wqe_datagram_seg) +
417608c2 293 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
1ffeb2eb
JM		 294 case MLX4_IB_QPT_PROXY_SMI_OWNER:
295 case MLX4_IB_QPT_PROXY_SMI:
296 case MLX4_IB_QPT_PROXY_GSI:
297 return sizeof (struct mlx4_wqe_ctrl_seg) +
298 sizeof (struct mlx4_wqe_datagram_seg) + 64;
299 case MLX4_IB_QPT_TUN_SMI_OWNER:
300 case MLX4_IB_QPT_TUN_GSI:
301 return sizeof (struct mlx4_wqe_ctrl_seg) +
302 sizeof (struct mlx4_wqe_datagram_seg);
303
304 case MLX4_IB_QPT_UC:
225c7b1f
RD		 305 return sizeof (struct mlx4_wqe_ctrl_seg) +
306 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb 307 case MLX4_IB_QPT_RC:
225c7b1f 308 return sizeof (struct mlx4_wqe_ctrl_seg) +
f2940e2c 309 sizeof (struct mlx4_wqe_masked_atomic_seg) +
225c7b1f 310 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb
JM		 311 case MLX4_IB_QPT_SMI:
312 case MLX4_IB_QPT_GSI:
225c7b1f
RD		 313 return sizeof (struct mlx4_wqe_ctrl_seg) +
314 ALIGN(MLX4_IB_UD_HEADER_SIZE +
e61ef241
RD		 315 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
316 MLX4_INLINE_ALIGN) *
225c7b1f
RD		 317 sizeof (struct mlx4_wqe_inline_seg),
318 sizeof (struct mlx4_wqe_data_seg)) +
319 ALIGN(4 +
320 sizeof (struct mlx4_wqe_inline_seg),
321 sizeof (struct mlx4_wqe_data_seg));
322 default:
323 return sizeof (struct mlx4_wqe_ctrl_seg);
324 }
325}
326
2446304d 327static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
913df8c3 328 bool is_user, bool has_rq, struct mlx4_ib_qp *qp,
ea30b966 329 u32 inl_recv_sz)
225c7b1f 330{
2446304d 331 /* Sanity check RQ size before proceeding */
fc2d0044
SG		 332 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
333 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
2446304d
EC		 334 return -EINVAL;
335
0a1405da 336 if (!has_rq) {
ea30b966 337 if (cap->max_recv_wr || inl_recv_sz)
a4cd7ed8 338 return -EINVAL;
2446304d 339
0e6e7416 340 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
a4cd7ed8 341 } else {
ea30b966
MG		 342 u32 max_inl_recv_sz = dev->dev->caps.max_rq_sg *
343 sizeof(struct mlx4_wqe_data_seg);
344 u32 wqe_size;
345
a4cd7ed8 346 /* HW requires >= 1 RQ entry with >= 1 gather entry */
ea30b966
MG		 347 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge ||
348 inl_recv_sz > max_inl_recv_sz))
a4cd7ed8
RD		 349 return -EINVAL;
350
0e6e7416 351 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
42c059ea 352 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
ea30b966
MG		 353 wqe_size = qp->rq.max_gs * sizeof(struct mlx4_wqe_data_seg);
354 qp->rq.wqe_shift = ilog2(max_t(u32, wqe_size, inl_recv_sz));
a4cd7ed8 355 }
2446304d 356
fc2d0044
SG		 357 /* leave userspace return values as they were, so as not to break ABI */
358 if (is_user) {
359 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
360 cap->max_recv_sge = qp->rq.max_gs;
361 } else {
362 cap->max_recv_wr = qp->rq.max_post =
363 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
364 cap->max_recv_sge = min(qp->rq.max_gs,
365 min(dev->dev->caps.max_sq_sg,
366 dev->dev->caps.max_rq_sg));
367 }
2446304d
EC		 368
369 return 0;
370}
371
372static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
f95ccffc 373 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
2446304d 374{
ea54b10c
JM		 375 int s;
376
2446304d 377 /* Sanity check SQ size before proceeding */
fc2d0044
SG		 378 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
379 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
b832be1e 380 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
225c7b1f
RD		 381 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
382 return -EINVAL;
383
384 /*
385 * For MLX transport we need 2 extra S/G entries:
386 * one for the header and one for the checksum at the end
387 */
1ffeb2eb
JM		 388 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
389 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
225c7b1f
RD		 390 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
391 return -EINVAL;
392
ea54b10c
JM		 393 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
394 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
b832be1e 395 send_wqe_overhead(type, qp->flags);
225c7b1f 396
cd155c1c
RD		 397 if (s > dev->dev->caps.max_sq_desc_sz)
398 return -EINVAL;
399
f95ccffc
JM		 400 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
401
0e6e7416 402 /*
f95ccffc
JM		 403 * We need to leave 2 KB + 1 WR of headroom in the SQ to
404 * allow HW to prefetch.
0e6e7416 405 */
350b4c8a 406 qp->sq_spare_wqes = MLX4_IB_SQ_HEADROOM(qp->sq.wqe_shift);
f95ccffc
JM		 407 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr +
408 qp->sq_spare_wqes);
409
410 qp->sq.max_gs =
411 (min(dev->dev->caps.max_sq_desc_sz,
412 (1 << qp->sq.wqe_shift)) -
413 send_wqe_overhead(type, qp->flags)) /
b832be1e 414 sizeof (struct mlx4_wqe_data_seg);
0e6e7416
RD		 415
416 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
417 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
225c7b1f
RD		 418 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
419 qp->rq.offset = 0;
0e6e7416 420 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
225c7b1f 421 } else {
0e6e7416 422 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
225c7b1f
RD		 423 qp->sq.offset = 0;
424 }
425
ea54b10c 426 cap->max_send_wr = qp->sq.max_post =
f95ccffc 427 qp->sq.wqe_cnt - qp->sq_spare_wqes;
cd155c1c
RD		 428 cap->max_send_sge = min(qp->sq.max_gs,
429 min(dev->dev->caps.max_sq_sg,
430 dev->dev->caps.max_rq_sg));
54e95f8d
RD		 431 /* We don't support inline sends for kernel QPs (yet) */
432 cap->max_inline_data = 0;
225c7b1f
RD		 433
434 return 0;
435}
436
83904132
JM		 437static int set_user_sq_size(struct mlx4_ib_dev *dev,
438 struct mlx4_ib_qp *qp,
2446304d
EC		 439 struct mlx4_ib_create_qp *ucmd)
440{
83904132
JM		 441 /* Sanity check SQ size before proceeding */
442 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
443 ucmd->log_sq_stride >
444 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
445 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
446 return -EINVAL;
447
0e6e7416 448 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
2446304d
EC		 449 qp->sq.wqe_shift = ucmd->log_sq_stride;
450
0e6e7416
RD		 451 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
452 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
2446304d
EC		 453
454 return 0;
455}
456
1ffeb2eb
JM		 457static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
458{
459 int i;
460
461 qp->sqp_proxy_rcv =
6da2ec56
KC		 462 kmalloc_array(qp->rq.wqe_cnt, sizeof(struct mlx4_ib_buf),
463 GFP_KERNEL);
1ffeb2eb
JM		 464 if (!qp->sqp_proxy_rcv)
465 return -ENOMEM;
466 for (i = 0; i < qp->rq.wqe_cnt; i++) {
467 qp->sqp_proxy_rcv[i].addr =
468 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
469 GFP_KERNEL);
470 if (!qp->sqp_proxy_rcv[i].addr)
471 goto err;
472 qp->sqp_proxy_rcv[i].map =
473 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
474 sizeof (struct mlx4_ib_proxy_sqp_hdr),
475 DMA_FROM_DEVICE);
cc47d369
SO		 476 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
477 kfree(qp->sqp_proxy_rcv[i].addr);
478 goto err;
479 }
1ffeb2eb
JM		 480 }
481 return 0;
482
483err:
484 while (i > 0) {
485 --i;
486 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
487 sizeof (struct mlx4_ib_proxy_sqp_hdr),
488 DMA_FROM_DEVICE);
489 kfree(qp->sqp_proxy_rcv[i].addr);
490 }
491 kfree(qp->sqp_proxy_rcv);
492 qp->sqp_proxy_rcv = NULL;
493 return -ENOMEM;
494}
495
496static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
497{
498 int i;
499
500 for (i = 0; i < qp->rq.wqe_cnt; i++) {
501 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
502 sizeof (struct mlx4_ib_proxy_sqp_hdr),
503 DMA_FROM_DEVICE);
504 kfree(qp->sqp_proxy_rcv[i].addr);
505 }
506 kfree(qp->sqp_proxy_rcv);
507}
508
913df8c3 509static bool qp_has_rq(struct ib_qp_init_attr *attr)
0a1405da
SH		 510{
511 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
913df8c3 512 return false;
0a1405da
SH		 513
514 return !attr->srq;
515}
516
99ec41d0
JM		 517static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
518{
519 int i;
520 for (i = 0; i < dev->caps.num_ports; i++) {
c73c8b1e
EBE		 521 if (qpn == dev->caps.spec_qps[i].qp0_proxy)
522 return !!dev->caps.spec_qps[i].qp0_qkey;
99ec41d0
JM		 523 }
524 return 0;
525}
526
7b59f0f9
EBE		 527static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
528 struct mlx4_ib_qp *qp)
529{
530 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
531 mlx4_counter_free(dev->dev, qp->counter_index->index);
532 list_del(&qp->counter_index->list);
533 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
534
535 kfree(qp->counter_index);
536 qp->counter_index = NULL;
537}
538
3078f5f1
GL		 539static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx,
540 struct ib_qp_init_attr *init_attr,
541 struct mlx4_ib_create_qp_rss *ucmd)
542{
543 rss_ctx->base_qpn_tbl_sz = init_attr->rwq_ind_tbl->ind_tbl[0]->wq_num |
544 (init_attr->rwq_ind_tbl->log_ind_tbl_size << 24);
545
546 if ((ucmd->rx_hash_function == MLX4_IB_RX_HASH_FUNC_TOEPLITZ) &&
547 (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) {
548 memcpy(rss_ctx->rss_key, ucmd->rx_hash_key,
549 MLX4_EN_RSS_KEY_SIZE);
550 } else {
551 pr_debug("RX Hash function is not supported\n");
552 return (-EOPNOTSUPP);
553 }
554
4d02ebd9
GL		 555 if (ucmd->rx_hash_fields_mask & ~(MLX4_IB_RX_HASH_SRC_IPV4 |
556 MLX4_IB_RX_HASH_DST_IPV4 |
557 MLX4_IB_RX_HASH_SRC_IPV6 |
558 MLX4_IB_RX_HASH_DST_IPV6 |
559 MLX4_IB_RX_HASH_SRC_PORT_TCP |
560 MLX4_IB_RX_HASH_DST_PORT_TCP |
561 MLX4_IB_RX_HASH_SRC_PORT_UDP |
4f9ca2d8
LR		 562 MLX4_IB_RX_HASH_DST_PORT_UDP |
563 MLX4_IB_RX_HASH_INNER)) {
4d02ebd9
GL		 564 pr_debug("RX Hash fields_mask has unsupported mask (0x%llx)\n",
565 ucmd->rx_hash_fields_mask);
566 return (-EOPNOTSUPP);
567 }
568
3078f5f1
GL		 569 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) &&
570 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
571 rss_ctx->flags = MLX4_RSS_IPV4;
572 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) ||
573 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
574 pr_debug("RX Hash fields_mask is not supported - both IPv4 SRC and DST must be set\n");
575 return (-EOPNOTSUPP);
576 }
577
578 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) &&
579 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
580 rss_ctx->flags |= MLX4_RSS_IPV6;
581 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) ||
582 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
583 pr_debug("RX Hash fields_mask is not supported - both IPv6 SRC and DST must be set\n");
584 return (-EOPNOTSUPP);
585 }
586
587 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) &&
588 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
589 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS)) {
590 pr_debug("RX Hash fields_mask for UDP is not supported\n");
591 return (-EOPNOTSUPP);
592 }
593
4d02ebd9 594 if (rss_ctx->flags & MLX4_RSS_IPV4)
3078f5f1 595 rss_ctx->flags |= MLX4_RSS_UDP_IPV4;
4d02ebd9 596 if (rss_ctx->flags & MLX4_RSS_IPV6)
3078f5f1 597 rss_ctx->flags |= MLX4_RSS_UDP_IPV6;
4d02ebd9 598 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
3078f5f1
GL		 599 pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n");
600 return (-EOPNOTSUPP);
601 }
602 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) ||
603 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
604 pr_debug("RX Hash fields_mask is not supported - both UDP SRC and DST must be set\n");
605 return (-EOPNOTSUPP);
606 }
607
608 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) &&
609 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
4d02ebd9 610 if (rss_ctx->flags & MLX4_RSS_IPV4)
3078f5f1 611 rss_ctx->flags |= MLX4_RSS_TCP_IPV4;
4d02ebd9 612 if (rss_ctx->flags & MLX4_RSS_IPV6)
3078f5f1 613 rss_ctx->flags |= MLX4_RSS_TCP_IPV6;
4d02ebd9 614 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
3078f5f1
GL		 615 pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n");
616 return (-EOPNOTSUPP);
617 }
3078f5f1
GL		 618 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) ||
619 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
620 pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n");
621 return (-EOPNOTSUPP);
622 }
623
07d84f7b
GL		 624 if (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_INNER) {
625 if (dev->dev->caps.tunnel_offload_mode ==
626 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
627 /*
628 * Hash according to inner headers if exist, otherwise
629 * according to outer headers.
630 */
631 rss_ctx->flags |= MLX4_RSS_BY_INNER_HEADERS_IPONLY;
632 } else {
633 pr_debug("RSS Hash for inner headers isn't supported\n");
634 return (-EOPNOTSUPP);
635 }
636 }
637
3078f5f1
GL		 638 return 0;
639}
640
d7c0557a 641static int create_qp_rss(struct mlx4_ib_dev *dev,
3078f5f1
GL		 642 struct ib_qp_init_attr *init_attr,
643 struct mlx4_ib_create_qp_rss *ucmd,
644 struct mlx4_ib_qp *qp)
645{
646 int qpn;
647 int err;
648
649 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
650
651 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 0, qp->mqp.usage);
652 if (err)
653 return err;
654
655 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
656 if (err)
657 goto err_qpn;
658
659 mutex_init(&qp->mutex);
660
661 INIT_LIST_HEAD(&qp->gid_list);
662 INIT_LIST_HEAD(&qp->steering_rules);
663
c3f1ee29 664 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET;
3078f5f1
GL		 665 qp->state = IB_QPS_RESET;
666
667 /* Set dummy send resources to be compatible with HV and PRM */
668 qp->sq_no_prefetch = 1;
669 qp->sq.wqe_cnt = 1;
670 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
671 qp->buf_size = qp->sq.wqe_cnt << MLX4_IB_MIN_SQ_STRIDE;
672 qp->mtt = (to_mqp(
673 (struct ib_qp *)init_attr->rwq_ind_tbl->ind_tbl[0]))->mtt;
674
675 qp->rss_ctx = kzalloc(sizeof(*qp->rss_ctx), GFP_KERNEL);
676 if (!qp->rss_ctx) {
677 err = -ENOMEM;
678 goto err_qp_alloc;
679 }
680
681 err = set_qp_rss(dev, qp->rss_ctx, init_attr, ucmd);
682 if (err)
683 goto err;
684
685 return 0;
686
687err:
688 kfree(qp->rss_ctx);
689
690err_qp_alloc:
691 mlx4_qp_remove(dev->dev, &qp->mqp);
692 mlx4_qp_free(dev->dev, &qp->mqp);
693
694err_qpn:
695 mlx4_qp_release_range(dev->dev, qpn, 1);
696 return err;
697}
698
699static struct ib_qp *_mlx4_ib_create_qp_rss(struct ib_pd *pd,
700 struct ib_qp_init_attr *init_attr,
701 struct ib_udata *udata)
702{
703 struct mlx4_ib_qp *qp;
704 struct mlx4_ib_create_qp_rss ucmd = {};
705 size_t required_cmd_sz;
706 int err;
707
708 if (!udata) {
709 pr_debug("RSS QP with NULL udata\n");
710 return ERR_PTR(-EINVAL);
711 }
712
713 if (udata->outlen)
714 return ERR_PTR(-EOPNOTSUPP);
715
716 required_cmd_sz = offsetof(typeof(ucmd), reserved1) +
717 sizeof(ucmd.reserved1);
718 if (udata->inlen < required_cmd_sz) {
719 pr_debug("invalid inlen\n");
720 return ERR_PTR(-EINVAL);
721 }
722
723 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
724 pr_debug("copy failed\n");
725 return ERR_PTR(-EFAULT);
726 }
727
f9bfea99
GL		 728 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)))
729 return ERR_PTR(-EOPNOTSUPP);
730
3078f5f1
GL		 731 if (ucmd.comp_mask || ucmd.reserved1)
732 return ERR_PTR(-EOPNOTSUPP);
733
734 if (udata->inlen > sizeof(ucmd) &&
735 !ib_is_udata_cleared(udata, sizeof(ucmd),
736 udata->inlen - sizeof(ucmd))) {
737 pr_debug("inlen is not supported\n");
738 return ERR_PTR(-EOPNOTSUPP);
739 }
740
741 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
742 pr_debug("RSS QP with unsupported QP type %d\n",
743 init_attr->qp_type);
744 return ERR_PTR(-EOPNOTSUPP);
745 }
746
747 if (init_attr->create_flags) {
748 pr_debug("RSS QP doesn't support create flags\n");
749 return ERR_PTR(-EOPNOTSUPP);
750 }
751
752 if (init_attr->send_cq || init_attr->cap.max_send_wr) {
753 pr_debug("RSS QP with unsupported send attributes\n");
754 return ERR_PTR(-EOPNOTSUPP);
755 }
756
757 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
758 if (!qp)
759 return ERR_PTR(-ENOMEM);
760
761 qp->pri.vid = 0xFFFF;
762 qp->alt.vid = 0xFFFF;
763
d7c0557a 764 err = create_qp_rss(to_mdev(pd->device), init_attr, &ucmd, qp);
3078f5f1
GL		 765 if (err) {
766 kfree(qp);
767 return ERR_PTR(err);
768 }
769
770 qp->ibqp.qp_num = qp->mqp.qpn;
771
772 return &qp->ibqp;
773}
774
400b1ebc
GL		 775/*
776 * This function allocates a WQN from a range which is consecutive and aligned
777 * to its size. In case the range is full, then it creates a new range and
778 * allocates WQN from it. The new range will be used for following allocations.
779 */
780static int mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext *context,
781 struct mlx4_ib_qp *qp, int range_size, int *wqn)
782{
783 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
784 struct mlx4_wqn_range *range;
785 int err = 0;
786
787 mutex_lock(&context->wqn_ranges_mutex);
788
789 range = list_first_entry_or_null(&context->wqn_ranges_list,
790 struct mlx4_wqn_range, list);
791
792 if (!range || (range->refcount == range->size) || range->dirty) {
793 range = kzalloc(sizeof(*range), GFP_KERNEL);
794 if (!range) {
795 err = -ENOMEM;
796 goto out;
797 }
798
799 err = mlx4_qp_reserve_range(dev->dev, range_size,
800 range_size, &range->base_wqn, 0,
801 qp->mqp.usage);
802 if (err) {
803 kfree(range);
804 goto out;
805 }
806
807 range->size = range_size;
808 list_add(&range->list, &context->wqn_ranges_list);
809 } else if (range_size != 1) {
810 /*
811 * Requesting a new range (>1) when last range is still open, is
812 * not valid.
813 */
814 err = -EINVAL;
815 goto out;
816 }
817
818 qp->wqn_range = range;
819
820 *wqn = range->base_wqn + range->refcount;
821
822 range->refcount++;
823
824out:
825 mutex_unlock(&context->wqn_ranges_mutex);
826
827 return err;
828}
829
830static void mlx4_ib_release_wqn(struct mlx4_ib_ucontext *context,
831 struct mlx4_ib_qp *qp, bool dirty_release)
832{
833 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
834 struct mlx4_wqn_range *range;
835
836 mutex_lock(&context->wqn_ranges_mutex);
837
838 range = qp->wqn_range;
839
840 range->refcount--;
841 if (!range->refcount) {
842 mlx4_qp_release_range(dev->dev, range->base_wqn,
843 range->size);
844 list_del(&range->list);
845 kfree(range);
846 } else if (dirty_release) {
847 /*
848 * A range which one of its WQNs is destroyed, won't be able to be
849 * reused for further WQN allocations.
850 * The next created WQ will allocate a new range.
851 */
852 range->dirty = 1;
853 }
854
855 mutex_unlock(&context->wqn_ranges_mutex);
856}
857
089b645d
LR		 858static int create_rq(struct ib_pd *pd, struct ib_qp_init_attr *init_attr,
859 struct ib_udata *udata, struct mlx4_ib_qp *qp)
860{
861 struct mlx4_ib_dev *dev = to_mdev(pd->device);
862 int qpn;
863 int err;
864 struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context(
865 udata, struct mlx4_ib_ucontext, ibucontext);
866 struct mlx4_ib_cq *mcq;
867 unsigned long flags;
868 int range_size;
869 struct mlx4_ib_create_wq wq;
870 size_t copy_len;
871 int shift;
872 int n;
873
874 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET;
875
876 mutex_init(&qp->mutex);
877 spin_lock_init(&qp->sq.lock);
878 spin_lock_init(&qp->rq.lock);
879 INIT_LIST_HEAD(&qp->gid_list);
880 INIT_LIST_HEAD(&qp->steering_rules);
881
882 qp->state = IB_QPS_RESET;
883
884 copy_len = min(sizeof(struct mlx4_ib_create_wq), udata->inlen);
885
886 if (ib_copy_from_udata(&wq, udata, copy_len)) {
887 err = -EFAULT;
888 goto err;
889 }
890
891 if (wq.comp_mask || wq.reserved[0] || wq.reserved[1] ||
892 wq.reserved[2]) {
893 pr_debug("user command isn't supported\n");
894 err = -EOPNOTSUPP;
895 goto err;
896 }
897
898 if (wq.log_range_size > ilog2(dev->dev->caps.max_rss_tbl_sz)) {
899 pr_debug("WQN range size must be equal or smaller than %d\n",
900 dev->dev->caps.max_rss_tbl_sz);
901 err = -EOPNOTSUPP;
902 goto err;
903 }
904 range_size = 1 << wq.log_range_size;
905
906 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS)
907 qp->flags |= MLX4_IB_QP_SCATTER_FCS;
908
913df8c3 909 err = set_rq_size(dev, &init_attr->cap, true, true, qp, qp->inl_recv_sz);
089b645d
LR		 910 if (err)
911 goto err;
912
913 qp->sq_no_prefetch = 1;
914 qp->sq.wqe_cnt = 1;
915 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
916 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
917 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
918
9bbf00b0 919 qp->umem = ib_umem_get(pd->device, wq.buf_addr, qp->buf_size, 0);
089b645d
LR		 920 if (IS_ERR(qp->umem)) {
921 err = PTR_ERR(qp->umem);
922 goto err;
923 }
924
925 n = ib_umem_page_count(qp->umem);
926 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n);
927 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt);
928
929 if (err)
930 goto err_buf;
931
932 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
933 if (err)
934 goto err_mtt;
935
936 err = mlx4_ib_db_map_user(udata, wq.db_addr, &qp->db);
937 if (err)
938 goto err_mtt;
939 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
940
941 err = mlx4_ib_alloc_wqn(context, qp, range_size, &qpn);
942 if (err)
943 goto err_wrid;
944
945 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
946 if (err)
947 goto err_qpn;
948
949 /*
950 * Hardware wants QPN written in big-endian order (after
951 * shifting) for send doorbell. Precompute this value to save
952 * a little bit when posting sends.
953 */
954 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
955
956 qp->mqp.event = mlx4_ib_wq_event;
957
958 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
959 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
960 to_mcq(init_attr->recv_cq));
961 /* Maintain device to QPs access, needed for further handling
962 * via reset flow
963 */
964 list_add_tail(&qp->qps_list, &dev->qp_list);
965 /* Maintain CQ to QPs access, needed for further handling
966 * via reset flow
967 */
968 mcq = to_mcq(init_attr->send_cq);
969 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
970 mcq = to_mcq(init_attr->recv_cq);
971 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
972 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
973 to_mcq(init_attr->recv_cq));
974 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
975 return 0;
976
977err_qpn:
978 mlx4_ib_release_wqn(context, qp, 0);
979err_wrid:
980 mlx4_ib_db_unmap_user(context, &qp->db);
981
982err_mtt:
983 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
984err_buf:
985 ib_umem_release(qp->umem);
986err:
987 return err;
988}
989
990static int create_qp_common(struct ib_pd *pd, struct ib_qp_init_attr *init_attr,
8900b894
LR		 991 struct ib_udata *udata, int sqpn,
992 struct mlx4_ib_qp **caller_qp)
225c7b1f 993{
089b645d 994 struct mlx4_ib_dev *dev = to_mdev(pd->device);
a3cdcbfa 995 int qpn;
225c7b1f 996 int err;
b42dde47 997 struct mlx4_ib_sqp *sqp = NULL;
1ffeb2eb 998 struct mlx4_ib_qp *qp;
89944450
SR		 999 struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context(
1000 udata, struct mlx4_ib_ucontext, ibucontext);
1ffeb2eb 1001 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
35f05dab
YH		 1002 struct mlx4_ib_cq *mcq;
1003 unsigned long flags;
1ffeb2eb
JM		 1004
1005 /* When tunneling special qps, we use a plain UD qp */
1006 if (sqpn) {
1007 if (mlx4_is_mfunc(dev->dev) &&
1008 (!mlx4_is_master(dev->dev) ||
1009 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
1010 if (init_attr->qp_type == IB_QPT_GSI)
1011 qp_type = MLX4_IB_QPT_PROXY_GSI;
99ec41d0
JM		 1012 else {
1013 if (mlx4_is_master(dev->dev) ||
1014 qp0_enabled_vf(dev->dev, sqpn))
1015 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
1016 else
1017 qp_type = MLX4_IB_QPT_PROXY_SMI;
1018 }
1ffeb2eb
JM		 1019 }
1020 qpn = sqpn;
1021 /* add extra sg entry for tunneling */
1022 init_attr->cap.max_recv_sge++;
1023 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
1024 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
1025 container_of(init_attr,
1026 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
1027 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
1028 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
1029 !mlx4_is_master(dev->dev))
1030 return -EINVAL;
1031 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
1032 qp_type = MLX4_IB_QPT_TUN_GSI;
99ec41d0
JM		 1033 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
1034 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
1035 tnl_init->port))
1ffeb2eb
JM		 1036 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
1037 else
1038 qp_type = MLX4_IB_QPT_TUN_SMI;
47605df9
JM		 1039 /* we are definitely in the PPF here, since we are creating
1040 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
1041 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
1042 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1ffeb2eb
JM		 1043 sqpn = qpn;
1044 }
1045
1046 if (!*caller_qp) {
1047 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
1048 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
1049 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
8900b894 1050 sqp = kzalloc(sizeof(struct mlx4_ib_sqp), GFP_KERNEL);
1ffeb2eb
JM		 1051 if (!sqp)
1052 return -ENOMEM;
1053 qp = &sqp->qp;
1054 } else {
8900b894 1055 qp = kzalloc(sizeof(struct mlx4_ib_qp), GFP_KERNEL);
1ffeb2eb
JM		 1056 if (!qp)
1057 return -ENOMEM;
1058 }
089b645d
LR		 1059 qp->pri.vid = 0xFFFF;
1060 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 1061 } else
1062 qp = *caller_qp;
1063
1064 qp->mlx4_ib_qp_type = qp_type;
225c7b1f
RD		 1065
1066 mutex_init(&qp->mutex);
1067 spin_lock_init(&qp->sq.lock);
1068 spin_lock_init(&qp->rq.lock);
fa417f7b 1069 INIT_LIST_HEAD(&qp->gid_list);
0ff1fb65 1070 INIT_LIST_HEAD(&qp->steering_rules);
225c7b1f 1071
089b645d 1072 qp->state = IB_QPS_RESET;
ea54b10c
JM		 1073 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1074 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
225c7b1f 1075
e00b64f7 1076 if (udata) {
089b645d 1077 struct mlx4_ib_create_qp ucmd;
400b1ebc 1078 size_t copy_len;
ed8637d3
GL		 1079 int shift;
1080 int n;
400b1ebc 1081
089b645d 1082 copy_len = sizeof(struct mlx4_ib_create_qp);
225c7b1f 1083
400b1ebc 1084 if (ib_copy_from_udata(&ucmd, udata, copy_len)) {
225c7b1f
RD		 1085 err = -EFAULT;
1086 goto err;
1087 }
1088
089b645d 1089 qp->inl_recv_sz = ucmd.inl_recv_sz;
0e6e7416 1090
6d06c9aa
GL		 1091 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1092 if (!(dev->dev->caps.flags &
1093 MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
1094 pr_debug("scatter FCS is unsupported\n");
1095 err = -EOPNOTSUPP;
1096 goto err;
1097 }
1098
1099 qp->flags |= MLX4_IB_QP_SCATTER_FCS;
1100 }
1101
e00b64f7 1102 err = set_rq_size(dev, &init_attr->cap, udata,
400b1ebc 1103 qp_has_rq(init_attr), qp, qp->inl_recv_sz);
2446304d
EC		 1104 if (err)
1105 goto err;
1106
089b645d 1107 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
400b1ebc 1108
089b645d
LR		 1109 err = set_user_sq_size(dev, qp, &ucmd);
1110 if (err)
1111 goto err;
400b1ebc 1112
9bbf00b0
MS		 1113 qp->umem =
1114 ib_umem_get(pd->device, ucmd.buf_addr, qp->buf_size, 0);
225c7b1f
RD		 1115 if (IS_ERR(qp->umem)) {
1116 err = PTR_ERR(qp->umem);
1117 goto err;
1118 }
1119
ed8637d3
GL		 1120 n = ib_umem_page_count(qp->umem);
1121 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n);
1122 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt);
1123
225c7b1f
RD		 1124 if (err)
1125 goto err_buf;
1126
1127 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
1128 if (err)
1129 goto err_mtt;
1130
0a1405da 1131 if (qp_has_rq(init_attr)) {
089b645d 1132 err = mlx4_ib_db_map_user(udata, ucmd.db_addr, &qp->db);
02d89b87
RD		 1133 if (err)
1134 goto err_mtt;
1135 }
f3301870 1136 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
225c7b1f 1137 } else {
e00b64f7 1138 err = set_rq_size(dev, &init_attr->cap, udata,
ea30b966
MG		 1139 qp_has_rq(init_attr), qp, 0);
1140 if (err)
1141 goto err;
1142
0e6e7416
RD		 1143 qp->sq_no_prefetch = 0;
1144
b832be1e
EC		 1145 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
1146 qp->flags |= MLX4_IB_QP_LSO;
1147
c1c98501
MB		 1148 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1149 if (dev->steering_support ==
1150 MLX4_STEERING_MODE_DEVICE_MANAGED)
1151 qp->flags |= MLX4_IB_QP_NETIF;
0641f236
LR		 1152 else {
1153 err = -EINVAL;
c1c98501 1154 goto err;
0641f236 1155 }
c1c98501
MB		 1156 }
1157
f95ccffc 1158 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
2446304d
EC		 1159 if (err)
1160 goto err;
1161
0a1405da 1162 if (qp_has_rq(init_attr)) {
8900b894 1163 err = mlx4_db_alloc(dev->dev, &qp->db, 0);
02d89b87
RD		 1164 if (err)
1165 goto err;
225c7b1f 1166
02d89b87
RD		 1167 *qp->db.db = 0;
1168 }
225c7b1f 1169
f95ccffc 1170 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2,
8900b894 1171 &qp->buf)) {
f95ccffc
JM		 1172 err = -ENOMEM;
1173 goto err_db;
225c7b1f
RD		 1174 }
1175
1176 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
1177 &qp->mtt);
1178 if (err)
1179 goto err_buf;
1180
8900b894 1181 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
225c7b1f
RD		 1182 if (err)
1183 goto err_mtt;
1184
e9105cde
LD		 1185 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1186 sizeof(u64), GFP_KERNEL);
1187 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1188 sizeof(u64), GFP_KERNEL);
225c7b1f
RD		 1189 if (!qp->sq.wrid || !qp->rq.wrid) {
1190 err = -ENOMEM;
1191 goto err_wrid;
1192 }
f3301870 1193 qp->mqp.usage = MLX4_RES_USAGE_DRIVER;
225c7b1f
RD		 1194 }
1195
a3cdcbfa 1196 if (sqpn) {
1ffeb2eb
JM		 1197 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1198 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
1199 if (alloc_proxy_bufs(pd->device, qp)) {
1200 err = -ENOMEM;
1201 goto err_wrid;
1202 }
1203 }
a3cdcbfa 1204 } else {
ddae0349
EE		 1205 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
1206 * otherwise, the WQE BlueFlame setup flow wrongly causes
1207 * VLAN insertion. */
3987a2d3 1208 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
ddae0349 1209 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
d57febe1
MB		 1210 (init_attr->cap.max_send_wr ?
1211 MLX4_RESERVE_ETH_BF_QP : 0) |
1212 (init_attr->cap.max_recv_wr ?
f3301870
MS		 1213 MLX4_RESERVE_A0_QP : 0),
1214 qp->mqp.usage);
3987a2d3 1215 else
c1c98501
MB		 1216 if (qp->flags & MLX4_IB_QP_NETIF)
1217 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
1218 else
1219 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
f3301870 1220 &qpn, 0, qp->mqp.usage);
a3cdcbfa 1221 if (err)
1ffeb2eb 1222 goto err_proxy;
a3cdcbfa
YP		 1223 }
1224
fbfb6625
EBE		 1225 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1226 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1227
8900b894 1228 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
225c7b1f 1229 if (err)
a3cdcbfa 1230 goto err_qpn;
225c7b1f 1231
0a1405da
SH		 1232 if (init_attr->qp_type == IB_QPT_XRC_TGT)
1233 qp->mqp.qpn |= (1 << 23);
1234
225c7b1f
RD		 1235 /*
1236 * Hardware wants QPN written in big-endian order (after
1237 * shifting) for send doorbell. Precompute this value to save
1238 * a little bit when posting sends.
1239 */
1240 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
1241
089b645d 1242 qp->mqp.event = mlx4_ib_qp_event;
400b1ebc 1243
1ffeb2eb
JM		 1244 if (!*caller_qp)
1245 *caller_qp = qp;
35f05dab
YH		 1246
1247 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1248 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
1249 to_mcq(init_attr->recv_cq));
1250 /* Maintain device to QPs access, needed for further handling
1251 * via reset flow
1252 */
1253 list_add_tail(&qp->qps_list, &dev->qp_list);
1254 /* Maintain CQ to QPs access, needed for further handling
1255 * via reset flow
1256 */
1257 mcq = to_mcq(init_attr->send_cq);
1258 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
1259 mcq = to_mcq(init_attr->recv_cq);
1260 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
1261 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
1262 to_mcq(init_attr->recv_cq));
1263 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1264 return 0;
1265
a3cdcbfa 1266err_qpn:
c1c98501
MB		 1267 if (!sqpn) {
1268 if (qp->flags & MLX4_IB_QP_NETIF)
1269 mlx4_ib_steer_qp_free(dev, qpn, 1);
1270 else
1271 mlx4_qp_release_range(dev->dev, qpn, 1);
1272 }
1ffeb2eb
JM		 1273err_proxy:
1274 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1275 free_proxy_bufs(pd->device, qp);
225c7b1f 1276err_wrid:
e00b64f7 1277 if (udata) {
0a1405da 1278 if (qp_has_rq(init_attr))
89944450 1279 mlx4_ib_db_unmap_user(context, &qp->db);
23f1b384 1280 } else {
0ef2f05c
WW		 1281 kvfree(qp->sq.wrid);
1282 kvfree(qp->rq.wrid);
225c7b1f
RD		 1283 }
1284
1285err_mtt:
1286 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1287
1288err_buf:
836a0fbb 1289 if (!qp->umem)
225c7b1f 1290 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
836a0fbb 1291 ib_umem_release(qp->umem);
225c7b1f
RD		 1292
1293err_db:
e00b64f7 1294 if (!udata && qp_has_rq(init_attr))
6296883c 1295 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 1296
1297err:
2dd8e44c 1298 if (!sqp && !*caller_qp)
1ffeb2eb 1299 kfree(qp);
2dd8e44c
YS		 1300 kfree(sqp);
1301
225c7b1f
RD		 1302 return err;
1303}
1304
1305static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
1306{
1307 switch (state) {
1308 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
1309 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
1310 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
1311 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
1312 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
1313 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
1314 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
1315 default: return -1;
1316 }
1317}
1318
1319static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 1320 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
225c7b1f 1321{
338a8fad 1322 if (send_cq == recv_cq) {
35f05dab 1323 spin_lock(&send_cq->lock);
338a8fad
RD		 1324 __acquire(&recv_cq->lock);
1325 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
35f05dab 1326 spin_lock(&send_cq->lock);
225c7b1f
RD		 1327 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1328 } else {
35f05dab 1329 spin_lock(&recv_cq->lock);
225c7b1f
RD		 1330 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1331 }
1332}
1333
1334static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 1335 __releases(&send_cq->lock) __releases(&recv_cq->lock)
225c7b1f 1336{
338a8fad
RD		 1337 if (send_cq == recv_cq) {
1338 __release(&recv_cq->lock);
35f05dab 1339 spin_unlock(&send_cq->lock);
338a8fad 1340 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
225c7b1f 1341 spin_unlock(&recv_cq->lock);
35f05dab 1342 spin_unlock(&send_cq->lock);
225c7b1f
RD		 1343 } else {
1344 spin_unlock(&send_cq->lock);
35f05dab 1345 spin_unlock(&recv_cq->lock);
225c7b1f
RD		 1346 }
1347}
1348
fa417f7b
EC		 1349static void del_gid_entries(struct mlx4_ib_qp *qp)
1350{
1351 struct mlx4_ib_gid_entry *ge, *tmp;
1352
1353 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1354 list_del(&ge->list);
1355 kfree(ge);
1356 }
1357}
1358
0a1405da
SH		 1359static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
1360{
1361 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
1362 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
1363 else
1364 return to_mpd(qp->ibqp.pd);
1365}
1366
400b1ebc 1367static void get_cqs(struct mlx4_ib_qp *qp, enum mlx4_ib_source_type src,
0a1405da
SH		 1368 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
1369{
1370 switch (qp->ibqp.qp_type) {
1371 case IB_QPT_XRC_TGT:
1372 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
1373 *recv_cq = *send_cq;
1374 break;
1375 case IB_QPT_XRC_INI:
1376 *send_cq = to_mcq(qp->ibqp.send_cq);
1377 *recv_cq = *send_cq;
1378 break;
1379 default:
400b1ebc
GL		 1380 *recv_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.recv_cq) :
1381 to_mcq(qp->ibwq.cq);
1382 *send_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.send_cq) :
1383 *recv_cq;
0a1405da
SH		 1384 break;
1385 }
1386}
1387
3078f5f1
GL		 1388static void destroy_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1389{
1390 if (qp->state != IB_QPS_RESET) {
1391 int i;
1392
1393 for (i = 0; i < (1 << qp->ibqp.rwq_ind_tbl->log_ind_tbl_size);
1394 i++) {
1395 struct ib_wq *ibwq = qp->ibqp.rwq_ind_tbl->ind_tbl[i];
1396 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1397
1398 mutex_lock(&wq->mutex);
1399
1400 wq->rss_usecnt--;
1401
1402 mutex_unlock(&wq->mutex);
1403 }
1404
1405 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1406 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1407 pr_warn("modify QP %06x to RESET failed.\n",
1408 qp->mqp.qpn);
1409 }
1410
1411 mlx4_qp_remove(dev->dev, &qp->mqp);
1412 mlx4_qp_free(dev->dev, &qp->mqp);
1413 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1414 del_gid_entries(qp);
1415 kfree(qp->rss_ctx);
1416}
1417
225c7b1f 1418static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
bdeacabd
SR		 1419 enum mlx4_ib_source_type src,
1420 struct ib_udata *udata)
225c7b1f
RD		 1421{
1422 struct mlx4_ib_cq *send_cq, *recv_cq;
35f05dab 1423 unsigned long flags;
225c7b1f 1424
2f5bb473 1425 if (qp->state != IB_QPS_RESET) {
225c7b1f
RD		 1426 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1427 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
987c8f8f 1428 pr_warn("modify QP %06x to RESET failed.\n",
225c7b1f 1429 qp->mqp.qpn);
25476b02 1430 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 1431 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1432 qp->pri.smac = 0;
25476b02 1433 qp->pri.smac_port = 0;
2f5bb473
JM		 1434 }
1435 if (qp->alt.smac) {
1436 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1437 qp->alt.smac = 0;
1438 }
1439 if (qp->pri.vid < 0x1000) {
1440 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1441 qp->pri.vid = 0xFFFF;
1442 qp->pri.candidate_vid = 0xFFFF;
1443 qp->pri.update_vid = 0;
1444 }
1445 if (qp->alt.vid < 0x1000) {
1446 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1447 qp->alt.vid = 0xFFFF;
1448 qp->alt.candidate_vid = 0xFFFF;
1449 qp->alt.update_vid = 0;
1450 }
1451 }
225c7b1f 1452
400b1ebc 1453 get_cqs(qp, src, &send_cq, &recv_cq);
225c7b1f 1454
35f05dab 1455 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1456 mlx4_ib_lock_cqs(send_cq, recv_cq);
1457
35f05dab
YH		 1458 /* del from lists under both locks above to protect reset flow paths */
1459 list_del(&qp->qps_list);
1460 list_del(&qp->cq_send_list);
1461 list_del(&qp->cq_recv_list);
bdeacabd 1462 if (!udata) {
225c7b1f
RD		 1463 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1464 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1465 if (send_cq != recv_cq)
1466 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1467 }
1468
1469 mlx4_qp_remove(dev->dev, &qp->mqp);
1470
1471 mlx4_ib_unlock_cqs(send_cq, recv_cq);
35f05dab 1472 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1473
1474 mlx4_qp_free(dev->dev, &qp->mqp);
a3cdcbfa 1475
c1c98501
MB		 1476 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1477 if (qp->flags & MLX4_IB_QP_NETIF)
1478 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
400b1ebc 1479 else if (src == MLX4_IB_RWQ_SRC)
bdeacabd
SR		 1480 mlx4_ib_release_wqn(
1481 rdma_udata_to_drv_context(
1482 udata,
1483 struct mlx4_ib_ucontext,
1484 ibucontext),
1485 qp, 1);
c1c98501
MB		 1486 else
1487 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1488 }
a3cdcbfa 1489
225c7b1f
RD		 1490 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1491
bdeacabd 1492 if (udata) {
400b1ebc 1493 if (qp->rq.wqe_cnt) {
bdeacabd
SR		 1494 struct mlx4_ib_ucontext *mcontext =
1495 rdma_udata_to_drv_context(
1496 udata,
1497 struct mlx4_ib_ucontext,
1498 ibucontext);
1499
400b1ebc
GL		 1500 mlx4_ib_db_unmap_user(mcontext, &qp->db);
1501 }
225c7b1f 1502 } else {
0ef2f05c
WW		 1503 kvfree(qp->sq.wrid);
1504 kvfree(qp->rq.wrid);
1ffeb2eb
JM		 1505 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1506 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1507 free_proxy_bufs(&dev->ib_dev, qp);
225c7b1f 1508 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
0a1405da 1509 if (qp->rq.wqe_cnt)
6296883c 1510 mlx4_db_free(dev->dev, &qp->db);
225c7b1f 1511 }
836a0fbb 1512 ib_umem_release(qp->umem);
fa417f7b
EC		 1513
1514 del_gid_entries(qp);
225c7b1f
RD		 1515}
1516
47605df9
JM		 1517static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1518{
1519 /* Native or PPF */
1520 if (!mlx4_is_mfunc(dev->dev) ||
1521 (mlx4_is_master(dev->dev) &&
1522 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1523 return dev->dev->phys_caps.base_sqpn +
1524 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1525 attr->port_num - 1;
1526 }
1527 /* PF or VF -- creating proxies */
1528 if (attr->qp_type == IB_QPT_SMI)
c73c8b1e 1529 return dev->dev->caps.spec_qps[attr->port_num - 1].qp0_proxy;
47605df9 1530 else
c73c8b1e 1531 return dev->dev->caps.spec_qps[attr->port_num - 1].qp1_proxy;
47605df9
JM		 1532}
1533
e1b866c6
MS		 1534static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd,
1535 struct ib_qp_init_attr *init_attr,
1536 struct ib_udata *udata)
225c7b1f 1537{
1ffeb2eb 1538 struct mlx4_ib_qp *qp = NULL;
225c7b1f 1539 int err;
fbfb6625 1540 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
0a1405da 1541 u16 xrcdn = 0;
225c7b1f 1542
3078f5f1
GL		 1543 if (init_attr->rwq_ind_tbl)
1544 return _mlx4_ib_create_qp_rss(pd, init_attr, udata);
1545
521e575b 1546 /*
1ffeb2eb
JM		 1547 * We only support LSO, vendor flag1, and multicast loopback blocking,
1548 * and only for kernel UD QPs.
521e575b 1549 */
1ffeb2eb
JM		 1550 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1551 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
c1c98501
MB		 1552 MLX4_IB_SRIOV_TUNNEL_QP |
1553 MLX4_IB_SRIOV_SQP |
40f2287b 1554 MLX4_IB_QP_NETIF |
8900b894 1555 MLX4_IB_QP_CREATE_ROCE_V2_GSI))
b832be1e 1556 return ERR_PTR(-EINVAL);
521e575b 1557
c1c98501
MB		 1558 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1559 if (init_attr->qp_type != IB_QPT_UD)
1560 return ERR_PTR(-EINVAL);
1561 }
1562
e1b866c6
MS		 1563 if (init_attr->create_flags) {
1564 if (udata && init_attr->create_flags & ~(sup_u_create_flags))
1565 return ERR_PTR(-EINVAL);
1566
1567 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
e1b866c6
MS		 1568 MLX4_IB_QP_CREATE_ROCE_V2_GSI |
1569 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) &&
1570 init_attr->qp_type != IB_QPT_UD) ||
1571 (init_attr->create_flags & MLX4_IB_SRIOV_SQP &&
1572 init_attr->qp_type > IB_QPT_GSI) ||
1573 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI &&
1574 init_attr->qp_type != IB_QPT_GSI))
1575 return ERR_PTR(-EINVAL);
1576 }
b846f25a 1577
225c7b1f 1578 switch (init_attr->qp_type) {
0a1405da
SH		 1579 case IB_QPT_XRC_TGT:
1580 pd = to_mxrcd(init_attr->xrcd)->pd;
1581 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1582 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1583 /* fall through */
1584 case IB_QPT_XRC_INI:
1585 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1586 return ERR_PTR(-ENOSYS);
1587 init_attr->recv_cq = init_attr->send_cq;
1588 /* fall through */
225c7b1f
RD		 1589 case IB_QPT_RC:
1590 case IB_QPT_UC:
3987a2d3 1591 case IB_QPT_RAW_PACKET:
8900b894 1592 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
225c7b1f
RD		 1593 if (!qp)
1594 return ERR_PTR(-ENOMEM);
2f5bb473
JM		 1595 qp->pri.vid = 0xFFFF;
1596 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 1597 /* fall through */
1598 case IB_QPT_UD:
1599 {
089b645d 1600 err = create_qp_common(pd, init_attr, udata, 0, &qp);
5b420d9c
DB		 1601 if (err) {
1602 kfree(qp);
225c7b1f 1603 return ERR_PTR(err);
5b420d9c 1604 }
225c7b1f
RD		 1605
1606 qp->ibqp.qp_num = qp->mqp.qpn;
0a1405da 1607 qp->xrcdn = xrcdn;
225c7b1f
RD		 1608
1609 break;
1610 }
1611 case IB_QPT_SMI:
1612 case IB_QPT_GSI:
1613 {
e1b866c6
MS		 1614 int sqpn;
1615
225c7b1f 1616 /* Userspace is not allowed to create special QPs: */
0a1405da 1617 if (udata)
225c7b1f 1618 return ERR_PTR(-EINVAL);
e1b866c6 1619 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) {
f3301870
MS		 1620 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev,
1621 1, 1, &sqpn, 0,
1622 MLX4_RES_USAGE_DRIVER);
e1b866c6
MS		 1623
1624 if (res)
1625 return ERR_PTR(res);
1626 } else {
1627 sqpn = get_sqp_num(to_mdev(pd->device), init_attr);
1628 }
225c7b1f 1629
089b645d 1630 err = create_qp_common(pd, init_attr, udata, sqpn, &qp);
1ffeb2eb 1631 if (err)
225c7b1f 1632 return ERR_PTR(err);
225c7b1f
RD		 1633
1634 qp->port = init_attr->port_num;
e1b866c6
MS		 1635 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 :
1636 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1;
225c7b1f
RD		 1637 break;
1638 }
1639 default:
1640 /* Don't support raw QPs */
1641 return ERR_PTR(-EINVAL);
1642 }
1643
1644 return &qp->ibqp;
1645}
1646
e1b866c6
MS		 1647struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1648 struct ib_qp_init_attr *init_attr,
1649 struct ib_udata *udata) {
1650 struct ib_device *device = pd ? pd->device : init_attr->xrcd->device;
1651 struct ib_qp *ibqp;
1652 struct mlx4_ib_dev *dev = to_mdev(device);
1653
1654 ibqp = _mlx4_ib_create_qp(pd, init_attr, udata);
1655
1656 if (!IS_ERR(ibqp) &&
1657 (init_attr->qp_type == IB_QPT_GSI) &&
1658 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) {
1659 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp)));
1660 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num);
1661
1662 if (is_eth &&
1663 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
1664 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1665 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr);
1666
1667 if (IS_ERR(sqp->roce_v2_gsi)) {
1668 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi));
1669 sqp->roce_v2_gsi = NULL;
1670 } else {
1671 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi));
1672 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP;
1673 }
1674
1675 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1676 }
1677 }
1678 return ibqp;
1679}
1680
bdeacabd 1681static int _mlx4_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
225c7b1f
RD		 1682{
1683 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1684 struct mlx4_ib_qp *mqp = to_mqp(qp);
1685
1686 if (is_qp0(dev, mqp))
1687 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1688
c482af64
JM		 1689 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI &&
1690 dev->qp1_proxy[mqp->port - 1] == mqp) {
9433c188
MB		 1691 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1692 dev->qp1_proxy[mqp->port - 1] = NULL;
1693 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1694 }
1695
7b59f0f9
EBE		 1696 if (mqp->counter_index)
1697 mlx4_ib_free_qp_counter(dev, mqp);
1698
3078f5f1
GL		 1699 if (qp->rwq_ind_tbl) {
1700 destroy_qp_rss(dev, mqp);
1701 } else {
bdeacabd 1702 destroy_qp_common(dev, mqp, MLX4_IB_QP_SRC, udata);
3078f5f1 1703 }
225c7b1f
RD		 1704
1705 if (is_sqp(dev, mqp))
1706 kfree(to_msqp(mqp));
1707 else
1708 kfree(mqp);
1709
1710 return 0;
1711}
1712
c4367a26 1713int mlx4_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
e1b866c6
MS		 1714{
1715 struct mlx4_ib_qp *mqp = to_mqp(qp);
1716
1717 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
1718 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
1719
1720 if (sqp->roce_v2_gsi)
1721 ib_destroy_qp(sqp->roce_v2_gsi);
1722 }
1723
bdeacabd 1724 return _mlx4_ib_destroy_qp(qp, udata);
e1b866c6
MS		 1725}
1726
1ffeb2eb 1727static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
225c7b1f
RD		 1728{
1729 switch (type) {
1ffeb2eb
JM		 1730 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1731 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1732 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1733 case MLX4_IB_QPT_XRC_INI:
1734 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1735 case MLX4_IB_QPT_SMI:
1736 case MLX4_IB_QPT_GSI:
1737 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1738
1739 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1740 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1741 MLX4_QP_ST_MLX : -1);
1742 case MLX4_IB_QPT_PROXY_SMI:
1743 case MLX4_IB_QPT_TUN_SMI:
1744 case MLX4_IB_QPT_PROXY_GSI:
1745 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1746 MLX4_QP_ST_UD : -1);
1747 default: return -1;
225c7b1f
RD		 1748 }
1749}
1750
65adfa91 1751static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1752 int attr_mask)
1753{
1754 u8 dest_rd_atomic;
1755 u32 access_flags;
1756 u32 hw_access_flags = 0;
1757
1758 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1759 dest_rd_atomic = attr->max_dest_rd_atomic;
1760 else
1761 dest_rd_atomic = qp->resp_depth;
1762
1763 if (attr_mask & IB_QP_ACCESS_FLAGS)
1764 access_flags = attr->qp_access_flags;
1765 else
1766 access_flags = qp->atomic_rd_en;
1767
1768 if (!dest_rd_atomic)
1769 access_flags &= IB_ACCESS_REMOTE_WRITE;
1770
1771 if (access_flags & IB_ACCESS_REMOTE_READ)
1772 hw_access_flags |= MLX4_QP_BIT_RRE;
1773 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1774 hw_access_flags |= MLX4_QP_BIT_RAE;
1775 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1776 hw_access_flags |= MLX4_QP_BIT_RWE;
1777
1778 return cpu_to_be32(hw_access_flags);
1779}
1780
65adfa91 1781static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1782 int attr_mask)
1783{
1784 if (attr_mask & IB_QP_PKEY_INDEX)
1785 sqp->pkey_index = attr->pkey_index;
1786 if (attr_mask & IB_QP_QKEY)
1787 sqp->qkey = attr->qkey;
1788 if (attr_mask & IB_QP_SQ_PSN)
1789 sqp->send_psn = attr->sq_psn;
1790}
1791
1792static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1793{
1794 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1795}
1796
90898850
DC		 1797static int _mlx4_set_path(struct mlx4_ib_dev *dev,
1798 const struct rdma_ah_attr *ah,
297e0dad 1799 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
2f5bb473 1800 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
225c7b1f 1801{
4c3eb3ca 1802 int vidx;
297e0dad 1803 int smac_index;
2f5bb473 1804 int err;
297e0dad 1805
d8966fcd
DC		 1806 path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f;
1807 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
1808 if (rdma_ah_get_static_rate(ah)) {
1809 path->static_rate = rdma_ah_get_static_rate(ah) +
1810 MLX4_STAT_RATE_OFFSET;
225c7b1f
RD		 1811 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1812 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1813 --path->static_rate;
1814 } else
1815 path->static_rate = 0;
225c7b1f 1816
d8966fcd
DC		 1817 if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) {
1818 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
1819 int real_sgid_index =
7492052a 1820 mlx4_ib_gid_index_to_real_index(dev, grh->sgid_attr);
5070cd22 1821
54a6d63f
DC		 1822 if (real_sgid_index < 0)
1823 return real_sgid_index;
5070cd22 1824 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
987c8f8f 1825 pr_err("sgid_index (%u) too large. max is %d\n",
5070cd22 1826 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
225c7b1f
RD		 1827 return -1;
1828 }
1829
1830 path->grh_mylmc |= 1 << 7;
5070cd22 1831 path->mgid_index = real_sgid_index;
d8966fcd 1832 path->hop_limit = grh->hop_limit;
225c7b1f 1833 path->tclass_flowlabel =
d8966fcd
DC		 1834 cpu_to_be32((grh->traffic_class << 20) |
1835 (grh->flow_label));
1836 memcpy(path->rgid, grh->dgid.raw, 16);
225c7b1f
RD		 1837 }
1838
44c58487 1839 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
d8966fcd 1840 if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH))
fa417f7b
EC		 1841 return -1;
1842
2f5bb473 1843 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
d8966fcd 1844 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3);
4c3eb3ca 1845
297e0dad 1846 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
4c3eb3ca 1847 if (vlan_tag < 0x1000) {
2f5bb473
JM		 1848 if (smac_info->vid < 0x1000) {
1849 /* both valid vlan ids */
1850 if (smac_info->vid != vlan_tag) {
1851 /* different VIDs. unreg old and reg new */
1852 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1853 if (err)
1854 return err;
1855 smac_info->candidate_vid = vlan_tag;
1856 smac_info->candidate_vlan_index = vidx;
1857 smac_info->candidate_vlan_port = port;
1858 smac_info->update_vid = 1;
1859 path->vlan_index = vidx;
1860 } else {
1861 path->vlan_index = smac_info->vlan_index;
1862 }
1863 } else {
1864 /* no current vlan tag in qp */
1865 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1866 if (err)
1867 return err;
1868 smac_info->candidate_vid = vlan_tag;
1869 smac_info->candidate_vlan_index = vidx;
1870 smac_info->candidate_vlan_port = port;
1871 smac_info->update_vid = 1;
1872 path->vlan_index = vidx;
1873 }
297e0dad 1874 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
2f5bb473
JM		 1875 path->fl = 1 << 6;
1876 } else {
1877 /* have current vlan tag. unregister it at modify-qp success */
1878 if (smac_info->vid < 0x1000) {
1879 smac_info->candidate_vid = 0xFFFF;
1880 smac_info->update_vid = 1;
1881 }
4c3eb3ca 1882 }
2f5bb473
JM		 1883
1884 /* get smac_index for RoCE use.
1885 * If no smac was yet assigned, register one.
1886 * If one was already assigned, but the new mac differs,
1887 * unregister the old one and register the new one.
1888 */
25476b02
JM		 1889 if ((!smac_info->smac && !smac_info->smac_port) ||
1890 smac_info->smac != smac) {
2f5bb473
JM		 1891 /* register candidate now, unreg if needed, after success */
1892 smac_index = mlx4_register_mac(dev->dev, port, smac);
1893 if (smac_index >= 0) {
1894 smac_info->candidate_smac_index = smac_index;
1895 smac_info->candidate_smac = smac;
1896 smac_info->candidate_smac_port = port;
1897 } else {
1898 return -EINVAL;
1899 }
1900 } else {
1901 smac_index = smac_info->smac_index;
1902 }
44c58487 1903 memcpy(path->dmac, ah->roce.dmac, 6);
2f5bb473
JM		 1904 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1905 /* put MAC table smac index for IBoE */
1906 path->grh_mylmc = (u8) (smac_index) | 0x80;
1907 } else {
4c3eb3ca 1908 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
d8966fcd 1909 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2);
2f5bb473 1910 }
fa417f7b 1911
225c7b1f
RD		 1912 return 0;
1913}
1914
297e0dad
MS		 1915static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1916 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1917 struct mlx4_ib_qp *mqp,
dbf727de
MB		 1918 struct mlx4_qp_path *path, u8 port,
1919 u16 vlan_id, u8 *smac)
297e0dad
MS		 1920{
1921 return _mlx4_set_path(dev, &qp->ah_attr,
dbf727de
MB		 1922 mlx4_mac_to_u64(smac),
1923 vlan_id,
2f5bb473 1924 path, &mqp->pri, port);
297e0dad
MS		 1925}
1926
1927static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1928 const struct ib_qp_attr *qp,
1929 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1930 struct mlx4_ib_qp *mqp,
297e0dad
MS		 1931 struct mlx4_qp_path *path, u8 port)
1932{
1933 return _mlx4_set_path(dev, &qp->alt_ah_attr,
dbf727de
MB		 1934 0,
1935 0xffff,
2f5bb473 1936 path, &mqp->alt, port);
297e0dad
MS		 1937}
1938
fa417f7b
EC		 1939static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1940{
1941 struct mlx4_ib_gid_entry *ge, *tmp;
1942
1943 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1944 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1945 ge->added = 1;
1946 ge->port = qp->port;
1947 }
1948 }
1949}
1950
dbf727de
MB		 1951static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1952 struct mlx4_ib_qp *qp,
2f5bb473
JM		 1953 struct mlx4_qp_context *context)
1954{
2f5bb473
JM		 1955 u64 u64_mac;
1956 int smac_index;
1957
3e0629cb 1958 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
2f5bb473
JM		 1959
1960 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
25476b02 1961 if (!qp->pri.smac && !qp->pri.smac_port) {
2f5bb473
JM		 1962 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1963 if (smac_index >= 0) {
1964 qp->pri.candidate_smac_index = smac_index;
1965 qp->pri.candidate_smac = u64_mac;
1966 qp->pri.candidate_smac_port = qp->port;
1967 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1968 } else {
1969 return -ENOENT;
1970 }
1971 }
1972 return 0;
1973}
1974
7b59f0f9
EBE		 1975static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1976{
1977 struct counter_index *new_counter_index;
1978 int err;
1979 u32 tmp_idx;
1980
1981 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1982 IB_LINK_LAYER_ETHERNET ||
1983 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1984 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1985 return 0;
1986
f3301870 1987 err = mlx4_counter_alloc(dev->dev, &tmp_idx, MLX4_RES_USAGE_DRIVER);
7b59f0f9
EBE		 1988 if (err)
1989 return err;
1990
1991 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1992 if (!new_counter_index) {
1993 mlx4_counter_free(dev->dev, tmp_idx);
1994 return -ENOMEM;
1995 }
1996
1997 new_counter_index->index = tmp_idx;
1998 new_counter_index->allocated = 1;
1999 qp->counter_index = new_counter_index;
2000
2001 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
2002 list_add_tail(&new_counter_index->list,
2003 &dev->counters_table[qp->port - 1].counters_list);
2004 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
2005
2006 return 0;
2007}
2008
3b5daf28
MS		 2009enum {
2010 MLX4_QPC_ROCE_MODE_1 = 0,
2011 MLX4_QPC_ROCE_MODE_2 = 2,
2012 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff
2013};
2014
2015static u8 gid_type_to_qpc(enum ib_gid_type gid_type)
2016{
2017 switch (gid_type) {
2018 case IB_GID_TYPE_ROCE:
2019 return MLX4_QPC_ROCE_MODE_1;
2020 case IB_GID_TYPE_ROCE_UDP_ENCAP:
2021 return MLX4_QPC_ROCE_MODE_2;
2022 default:
2023 return MLX4_QPC_ROCE_MODE_UNDEFINED;
2024 }
2025}
2026
3078f5f1
GL		 2027/*
2028 * Go over all RSS QP's childes (WQs) and apply their HW state according to
2029 * their logic state if the RSS QP is the first RSS QP associated for the WQ.
2030 */
89944450
SR		 2031static int bringup_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, u8 port_num,
2032 struct ib_udata *udata)
3078f5f1 2033{
fba02e6c 2034 int err = 0;
3078f5f1 2035 int i;
3078f5f1
GL		 2036
2037 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2038 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2039 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2040
2041 mutex_lock(&wq->mutex);
2042
2043 /* Mlx4_ib restrictions:
2044 * WQ's is associated to a port according to the RSS QP it is
2045 * associates to.
2046 * In case the WQ is associated to a different port by another
2047 * RSS QP, return a failure.
2048 */
2049 if ((wq->rss_usecnt > 0) && (wq->port != port_num)) {
2050 err = -EINVAL;
2051 mutex_unlock(&wq->mutex);
2052 break;
2053 }
2054 wq->port = port_num;
2055 if ((wq->rss_usecnt == 0) && (ibwq->state == IB_WQS_RDY)) {
89944450 2056 err = _mlx4_ib_modify_wq(ibwq, IB_WQS_RDY, udata);
3078f5f1
GL		 2057 if (err) {
2058 mutex_unlock(&wq->mutex);
2059 break;
2060 }
2061 }
2062 wq->rss_usecnt++;
2063
2064 mutex_unlock(&wq->mutex);
2065 }
2066
2067 if (i && err) {
2068 int j;
2069
2070 for (j = (i - 1); j >= 0; j--) {
2071 struct ib_wq *ibwq = ind_tbl->ind_tbl[j];
2072 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2073
2074 mutex_lock(&wq->mutex);
2075
2076 if ((wq->rss_usecnt == 1) &&
2077 (ibwq->state == IB_WQS_RDY))
89944450
SR		 2078 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET,
2079 udata))
3078f5f1
GL		 2080 pr_warn("failed to reverse WQN=0x%06x\n",
2081 ibwq->wq_num);
2082 wq->rss_usecnt--;
2083
2084 mutex_unlock(&wq->mutex);
2085 }
2086 }
2087
2088 return err;
2089}
2090
89944450
SR		 2091static void bring_down_rss_rwqs(struct ib_rwq_ind_table *ind_tbl,
2092 struct ib_udata *udata)
3078f5f1
GL		 2093{
2094 int i;
2095
2096 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2097 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2098 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2099
2100 mutex_lock(&wq->mutex);
2101
2102 if ((wq->rss_usecnt == 1) && (ibwq->state == IB_WQS_RDY))
89944450 2103 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET, udata))
3078f5f1
GL		 2104 pr_warn("failed to reverse WQN=%x\n",
2105 ibwq->wq_num);
2106 wq->rss_usecnt--;
2107
2108 mutex_unlock(&wq->mutex);
2109 }
2110}
2111
2112static void fill_qp_rss_context(struct mlx4_qp_context *context,
2113 struct mlx4_ib_qp *qp)
2114{
2115 struct mlx4_rss_context *rss_context;
2116
2117 rss_context = (void *)context + offsetof(struct mlx4_qp_context,
2118 pri_path) + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
2119
2120 rss_context->base_qpn = cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz);
2121 rss_context->default_qpn =
2122 cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz & 0xffffff);
2123 if (qp->rss_ctx->flags & (MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6))
2124 rss_context->base_qpn_udp = rss_context->default_qpn;
2125 rss_context->flags = qp->rss_ctx->flags;
2126 /* Currently support just toeplitz */
2127 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
2128
2129 memcpy(rss_context->rss_key, qp->rss_ctx->rss_key,
2130 MLX4_EN_RSS_KEY_SIZE);
2131}
2132
400b1ebc 2133static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type,
65adfa91 2134 const struct ib_qp_attr *attr, int attr_mask,
89944450
SR		 2135 enum ib_qp_state cur_state,
2136 enum ib_qp_state new_state,
2137 struct ib_udata *udata)
225c7b1f 2138{
400b1ebc 2139 struct ib_srq *ibsrq;
47ec3866 2140 const struct ib_gid_attr *gid_attr = NULL;
3078f5f1 2141 struct ib_rwq_ind_table *rwq_ind_tbl;
400b1ebc
GL		 2142 enum ib_qp_type qp_type;
2143 struct mlx4_ib_dev *dev;
2144 struct mlx4_ib_qp *qp;
0a1405da
SH		 2145 struct mlx4_ib_pd *pd;
2146 struct mlx4_ib_cq *send_cq, *recv_cq;
89944450
SR		 2147 struct mlx4_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2148 udata, struct mlx4_ib_ucontext, ibucontext);
225c7b1f
RD		 2149 struct mlx4_qp_context *context;
2150 enum mlx4_qp_optpar optpar = 0;
225c7b1f 2151 int sqd_event;
c1c98501 2152 int steer_qp = 0;
225c7b1f 2153 int err = -EINVAL;
3ba8e31d 2154 int counter_index;
225c7b1f 2155
400b1ebc
GL		 2156 if (src_type == MLX4_IB_RWQ_SRC) {
2157 struct ib_wq *ibwq;
2158
3078f5f1 2159 ibwq = (struct ib_wq *)src;
3078f5f1
GL		 2160 ibsrq = NULL;
2161 rwq_ind_tbl = NULL;
2162 qp_type = IB_QPT_RAW_PACKET;
2163 qp = to_mqp((struct ib_qp *)ibwq);
2164 dev = to_mdev(ibwq->device);
2165 pd = to_mpd(ibwq->pd);
400b1ebc
GL		 2166 } else {
2167 struct ib_qp *ibqp;
2168
3078f5f1 2169 ibqp = (struct ib_qp *)src;
3078f5f1
GL		 2170 ibsrq = ibqp->srq;
2171 rwq_ind_tbl = ibqp->rwq_ind_tbl;
2172 qp_type = ibqp->qp_type;
2173 qp = to_mqp(ibqp);
2174 dev = to_mdev(ibqp->device);
2175 pd = get_pd(qp);
400b1ebc
GL		 2176 }
2177
3dec4878
JM		 2178 /* APM is not supported under RoCE */
2179 if (attr_mask & IB_QP_ALT_PATH &&
2180 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2181 IB_LINK_LAYER_ETHERNET)
2182 return -ENOTSUPP;
2183
225c7b1f
RD		 2184 context = kzalloc(sizeof *context, GFP_KERNEL);
2185 if (!context)
2186 return -ENOMEM;
2187
225c7b1f 2188 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1ffeb2eb 2189 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
225c7b1f
RD		 2190
2191 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
2192 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2193 else {
2194 optpar |= MLX4_QP_OPTPAR_PM_STATE;
2195 switch (attr->path_mig_state) {
2196 case IB_MIG_MIGRATED:
2197 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2198 break;
2199 case IB_MIG_REARM:
2200 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
2201 break;
2202 case IB_MIG_ARMED:
2203 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
2204 break;
2205 }
2206 }
2207
ea30b966
MG		 2208 if (qp->inl_recv_sz)
2209 context->param3 |= cpu_to_be32(1 << 25);
2210
6d06c9aa
GL		 2211 if (qp->flags & MLX4_IB_QP_SCATTER_FCS)
2212 context->param3 |= cpu_to_be32(1 << 29);
2213
400b1ebc 2214 if (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI)
225c7b1f 2215 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
400b1ebc 2216 else if (qp_type == IB_QPT_RAW_PACKET)
3987a2d3 2217 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
400b1ebc 2218 else if (qp_type == IB_QPT_UD) {
b832be1e
EC		 2219 if (qp->flags & MLX4_IB_QP_LSO)
2220 context->mtu_msgmax = (IB_MTU_4096 << 5) |
2221 ilog2(dev->dev->caps.max_gso_sz);
2222 else
5f22a1d8 2223 context->mtu_msgmax = (IB_MTU_4096 << 5) | 13;
b832be1e 2224 } else if (attr_mask & IB_QP_PATH_MTU) {
225c7b1f 2225 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
987c8f8f 2226 pr_err("path MTU (%u) is invalid\n",
225c7b1f 2227 attr->path_mtu);
f5b40431 2228 goto out;
225c7b1f 2229 }
d1f2cd89
EC		 2230 context->mtu_msgmax = (attr->path_mtu << 5) |
2231 ilog2(dev->dev->caps.max_msg_sz);
225c7b1f
RD		 2232 }
2233
3078f5f1
GL		 2234 if (!rwq_ind_tbl) { /* PRM RSS receive side should be left zeros */
2235 if (qp->rq.wqe_cnt)
2236 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
2237 context->rq_size_stride |= qp->rq.wqe_shift - 4;
2238 }
225c7b1f 2239
0e6e7416
RD		 2240 if (qp->sq.wqe_cnt)
2241 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
225c7b1f
RD		 2242 context->sq_size_stride |= qp->sq.wqe_shift - 4;
2243
7b59f0f9
EBE		 2244 if (new_state == IB_QPS_RESET && qp->counter_index)
2245 mlx4_ib_free_qp_counter(dev, qp);
2246
0a1405da 2247 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0e6e7416 2248 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
0a1405da 2249 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
400b1ebc 2250 if (qp_type == IB_QPT_RAW_PACKET)
02d7ef6f 2251 context->param3 |= cpu_to_be32(1 << 30);
0a1405da 2252 }
0e6e7416 2253
89944450 2254 if (ucontext)
85743f1e 2255 context->usr_page = cpu_to_be32(
89944450 2256 mlx4_to_hw_uar_index(dev->dev, ucontext->uar.index));
225c7b1f 2257 else
85743f1e
HN		 2258 context->usr_page = cpu_to_be32(
2259 mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index));
225c7b1f
RD		 2260
2261 if (attr_mask & IB_QP_DEST_QPN)
2262 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
2263
2264 if (attr_mask & IB_QP_PORT) {
2265 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
2266 !(attr_mask & IB_QP_AV)) {
2267 mlx4_set_sched(&context->pri_path, attr->port_num);
2268 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
2269 }
2270 }
2271
cfcde11c 2272 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
7b59f0f9
EBE		 2273 err = create_qp_lb_counter(dev, qp);
2274 if (err)
2275 goto out;
2276
3ba8e31d
EBE		 2277 counter_index =
2278 dev->counters_table[qp->port - 1].default_counter;
7b59f0f9
EBE		 2279 if (qp->counter_index)
2280 counter_index = qp->counter_index->index;
2281
3ba8e31d
EBE		 2282 if (counter_index != -1) {
2283 context->pri_path.counter_index = counter_index;
cfcde11c 2284 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
7b59f0f9
EBE		 2285 if (qp->counter_index) {
2286 context->pri_path.fl |=
2287 MLX4_FL_ETH_SRC_CHECK_MC_LB;
2288 context->pri_path.vlan_control |=
2289 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
2290 }
cfcde11c 2291 } else
47d8417f
EBE		 2292 context->pri_path.counter_index =
2293 MLX4_SINK_COUNTER_INDEX(dev->dev);
c1c98501
MB		 2294
2295 if (qp->flags & MLX4_IB_QP_NETIF) {
2296 mlx4_ib_steer_qp_reg(dev, qp, 1);
2297 steer_qp = 1;
2298 }
e1b866c6 2299
400b1ebc 2300 if (qp_type == IB_QPT_GSI) {
e1b866c6
MS		 2301 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ?
2302 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE;
2303 u8 qpc_roce_mode = gid_type_to_qpc(gid_type);
2304
2305 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2306 }
cfcde11c
OG		 2307 }
2308
225c7b1f 2309 if (attr_mask & IB_QP_PKEY_INDEX) {
1ffeb2eb
JM		 2310 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2311 context->pri_path.disable_pkey_check = 0x40;
225c7b1f
RD		 2312 context->pri_path.pkey_index = attr->pkey_index;
2313 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
2314 }
2315
225c7b1f 2316 if (attr_mask & IB_QP_AV) {
400b1ebc 2317 u8 port_num = mlx4_is_bonded(dev->dev) ? 1 :
dbf727de 2318 attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
dbf727de
MB		 2319 u16 vlan = 0xffff;
2320 u8 smac[ETH_ALEN];
d8966fcd
DC		 2321 int is_eth =
2322 rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
2323 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
dbf727de 2324
d8966fcd 2325 if (is_eth) {
47ec3866 2326 gid_attr = attr->ah_attr.grh.sgid_attr;
a70c0739
PP		 2327 err = rdma_read_gid_l2_fields(gid_attr, &vlan,
2328 &smac[0]);
2329 if (err)
2330 goto out;
dbf727de 2331 }
dbf727de 2332
2f5bb473 2333 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
dbf727de 2334 port_num, vlan, smac))
225c7b1f 2335 goto out;
225c7b1f
RD		 2336
2337 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
2338 MLX4_QP_OPTPAR_SCHED_QUEUE);
3b5daf28
MS		 2339
2340 if (is_eth &&
2341 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) {
47ec3866 2342 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr->gid_type);
3b5daf28
MS		 2343
2344 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) {
2345 err = -EINVAL;
2346 goto out;
2347 }
2348 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2349 }
2350
225c7b1f
RD		 2351 }
2352
2353 if (attr_mask & IB_QP_TIMEOUT) {
fa417f7b 2354 context->pri_path.ackto |= attr->timeout << 3;
225c7b1f
RD		 2355 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
2356 }
2357
2358 if (attr_mask & IB_QP_ALT_PATH) {
225c7b1f
RD		 2359 if (attr->alt_port_num == 0 ||
2360 attr->alt_port_num > dev->dev->caps.num_ports)
f5b40431 2361 goto out;
225c7b1f 2362
5ae2a7a8
RD		 2363 if (attr->alt_pkey_index >=
2364 dev->dev->caps.pkey_table_len[attr->alt_port_num])
f5b40431 2365 goto out;
5ae2a7a8 2366
2f5bb473
JM		 2367 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
2368 &context->alt_path,
297e0dad 2369 attr->alt_port_num))
f5b40431 2370 goto out;
225c7b1f
RD		 2371
2372 context->alt_path.pkey_index = attr->alt_pkey_index;
2373 context->alt_path.ackto = attr->alt_timeout << 3;
2374 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
2375 }
2376
3078f5f1
GL		 2377 context->pd = cpu_to_be32(pd->pdn);
2378
2379 if (!rwq_ind_tbl) {
108809a0 2380 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
3078f5f1
GL		 2381 get_cqs(qp, src_type, &send_cq, &recv_cq);
2382 } else { /* Set dummy CQs to be compatible with HV and PRM */
2383 send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq);
2384 recv_cq = send_cq;
2385 }
0a1405da
SH		 2386 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
2387 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
57f01b53 2388
95d04f07 2389 /* Set "fast registration enabled" for all kernel QPs */
89944450 2390 if (!ucontext)
95d04f07
RD		 2391 context->params1 |= cpu_to_be32(1 << 11);
2392
57f01b53
JM		 2393 if (attr_mask & IB_QP_RNR_RETRY) {
2394 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2395 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
2396 }
2397
225c7b1f
RD		 2398 if (attr_mask & IB_QP_RETRY_CNT) {
2399 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2400 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
2401 }
2402
2403 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2404 if (attr->max_rd_atomic)
2405 context->params1 |=
2406 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2407 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
2408 }
2409
2410 if (attr_mask & IB_QP_SQ_PSN)
2411 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2412
225c7b1f
RD		 2413 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2414 if (attr->max_dest_rd_atomic)
2415 context->params2 |=
2416 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2417 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
2418 }
2419
2420 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
2421 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
2422 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
2423 }
2424
400b1ebc 2425 if (ibsrq)
225c7b1f
RD		 2426 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
2427
2428 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2429 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2430 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
2431 }
2432 if (attr_mask & IB_QP_RQ_PSN)
2433 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2434
1ffeb2eb 2435 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
225c7b1f 2436 if (attr_mask & IB_QP_QKEY) {
1ffeb2eb
JM		 2437 if (qp->mlx4_ib_qp_type &
2438 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
2439 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2440 else {
2441 if (mlx4_is_mfunc(dev->dev) &&
2442 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
2443 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
2444 MLX4_RESERVED_QKEY_BASE) {
2445 pr_err("Cannot use reserved QKEY"
2446 " 0x%x (range 0xffff0000..0xffffffff"
2447 " is reserved)\n", attr->qkey);
2448 err = -EINVAL;
2449 goto out;
2450 }
2451 context->qkey = cpu_to_be32(attr->qkey);
2452 }
225c7b1f
RD		 2453 optpar |= MLX4_QP_OPTPAR_Q_KEY;
2454 }
2455
400b1ebc
GL		 2456 if (ibsrq)
2457 context->srqn = cpu_to_be32(1 << 24 |
2458 to_msrq(ibsrq)->msrq.srqn);
225c7b1f 2459
400b1ebc
GL		 2460 if (qp->rq.wqe_cnt &&
2461 cur_state == IB_QPS_RESET &&
2462 new_state == IB_QPS_INIT)
225c7b1f
RD		 2463 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2464
2465 if (cur_state == IB_QPS_INIT &&
2466 new_state == IB_QPS_RTR &&
400b1ebc
GL		 2467 (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI ||
2468 qp_type == IB_QPT_UD || qp_type == IB_QPT_RAW_PACKET)) {
225c7b1f 2469 context->pri_path.sched_queue = (qp->port - 1) << 6;
1ffeb2eb
JM		 2470 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2471 qp->mlx4_ib_qp_type &
2472 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
225c7b1f 2473 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1ffeb2eb
JM		 2474 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
2475 context->pri_path.fl = 0x80;
2476 } else {
2477 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2478 context->pri_path.fl = 0x80;
225c7b1f 2479 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1ffeb2eb 2480 }
2f5bb473
JM		 2481 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2482 IB_LINK_LAYER_ETHERNET) {
2483 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
2484 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
2485 context->pri_path.feup = 1 << 7; /* don't fsm */
2486 /* handle smac_index */
2487 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
2488 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
2489 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
dbf727de 2490 err = handle_eth_ud_smac_index(dev, qp, context);
bede98e7
MD		 2491 if (err) {
2492 err = -EINVAL;
2493 goto out;
2494 }
9433c188
MB		 2495 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
2496 dev->qp1_proxy[qp->port - 1] = qp;
2f5bb473
JM		 2497 }
2498 }
225c7b1f
RD		 2499 }
2500
400b1ebc 2501 if (qp_type == IB_QPT_RAW_PACKET) {
3528f696
EC		 2502 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
2503 MLX4_IB_LINK_TYPE_ETH;
d2fce8a9
OG		 2504 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
2505 /* set QP to receive both tunneled & non-tunneled packets */
108809a0 2506 if (!rwq_ind_tbl)
d2fce8a9
OG		 2507 context->srqn = cpu_to_be32(7 << 28);
2508 }
2509 }
3528f696 2510
400b1ebc 2511 if (qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
297e0dad
MS		 2512 int is_eth = rdma_port_get_link_layer(
2513 &dev->ib_dev, qp->port) ==
2514 IB_LINK_LAYER_ETHERNET;
2515 if (is_eth) {
2516 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
2517 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
2518 }
2519 }
2520
225c7b1f
RD		 2521 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
2522 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2523 sqd_event = 1;
2524 else
2525 sqd_event = 0;
2526
89944450 2527 if (!ucontext &&
400b1ebc
GL		 2528 cur_state == IB_QPS_RESET &&
2529 new_state == IB_QPS_INIT)
3b5daf28 2530 context->rlkey_roce_mode |= (1 << 4);
d57f5f72 2531
c0be5fb5
EC		 2532 /*
2533 * Before passing a kernel QP to the HW, make sure that the
0e6e7416
RD		 2534 * ownership bits of the send queue are set and the SQ
2535 * headroom is stamped so that the hardware doesn't start
2536 * processing stale work requests.
c0be5fb5 2537 */
89944450 2538 if (!ucontext &&
400b1ebc
GL		 2539 cur_state == IB_QPS_RESET &&
2540 new_state == IB_QPS_INIT) {
c0be5fb5
EC		 2541 struct mlx4_wqe_ctrl_seg *ctrl;
2542 int i;
2543
0e6e7416 2544 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
c0be5fb5
EC		 2545 ctrl = get_send_wqe(qp, i);
2546 ctrl->owner_opcode = cpu_to_be32(1 << 31);
f95ccffc
JM		 2547 ctrl->qpn_vlan.fence_size =
2548 1 << (qp->sq.wqe_shift - 4);
2549 stamp_send_wqe(qp, i);
c0be5fb5
EC		 2550 }
2551 }
2552
108809a0
GL		 2553 if (rwq_ind_tbl &&
2554 cur_state == IB_QPS_RESET &&
2555 new_state == IB_QPS_INIT) {
2556 fill_qp_rss_context(context, qp);
2557 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET);
2558 }
2559
225c7b1f
RD		 2560 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
2561 to_mlx4_state(new_state), context, optpar,
2562 sqd_event, &qp->mqp);
2563 if (err)
2564 goto out;
2565
2566 qp->state = new_state;
2567
2568 if (attr_mask & IB_QP_ACCESS_FLAGS)
2569 qp->atomic_rd_en = attr->qp_access_flags;
2570 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2571 qp->resp_depth = attr->max_dest_rd_atomic;
fa417f7b 2572 if (attr_mask & IB_QP_PORT) {
225c7b1f 2573 qp->port = attr->port_num;
fa417f7b
EC		 2574 update_mcg_macs(dev, qp);
2575 }
225c7b1f
RD		 2576 if (attr_mask & IB_QP_ALT_PATH)
2577 qp->alt_port = attr->alt_port_num;
2578
2579 if (is_sqp(dev, qp))
2580 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
2581
2582 /*
2583 * If we moved QP0 to RTR, bring the IB link up; if we moved
2584 * QP0 to RESET or ERROR, bring the link back down.
2585 */
2586 if (is_qp0(dev, qp)) {
2587 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
5ae2a7a8 2588 if (mlx4_INIT_PORT(dev->dev, qp->port))
987c8f8f 2589 pr_warn("INIT_PORT failed for port %d\n",
5ae2a7a8 2590 qp->port);
225c7b1f
RD		 2591
2592 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2593 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
2594 mlx4_CLOSE_PORT(dev->dev, qp->port);
2595 }
2596
2597 /*
2598 * If we moved a kernel QP to RESET, clean up all old CQ
2599 * entries and reinitialize the QP.
2600 */
2f5bb473 2601 if (new_state == IB_QPS_RESET) {
89944450 2602 if (!ucontext) {
2f5bb473 2603 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
400b1ebc 2604 ibsrq ? to_msrq(ibsrq) : NULL);
2f5bb473
JM		 2605 if (send_cq != recv_cq)
2606 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
2607
2608 qp->rq.head = 0;
2609 qp->rq.tail = 0;
2610 qp->sq.head = 0;
2611 qp->sq.tail = 0;
2612 qp->sq_next_wqe = 0;
2613 if (qp->rq.wqe_cnt)
2614 *qp->db.db = 0;
225c7b1f 2615
2f5bb473
JM		 2616 if (qp->flags & MLX4_IB_QP_NETIF)
2617 mlx4_ib_steer_qp_reg(dev, qp, 0);
2618 }
25476b02 2619 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 2620 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2621 qp->pri.smac = 0;
25476b02 2622 qp->pri.smac_port = 0;
2f5bb473
JM		 2623 }
2624 if (qp->alt.smac) {
2625 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2626 qp->alt.smac = 0;
2627 }
2628 if (qp->pri.vid < 0x1000) {
2629 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
2630 qp->pri.vid = 0xFFFF;
2631 qp->pri.candidate_vid = 0xFFFF;
2632 qp->pri.update_vid = 0;
2633 }
c1c98501 2634
2f5bb473
JM		 2635 if (qp->alt.vid < 0x1000) {
2636 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
2637 qp->alt.vid = 0xFFFF;
2638 qp->alt.candidate_vid = 0xFFFF;
2639 qp->alt.update_vid = 0;
2640 }
225c7b1f 2641 }
225c7b1f 2642out:
7b59f0f9
EBE		 2643 if (err && qp->counter_index)
2644 mlx4_ib_free_qp_counter(dev, qp);
c1c98501
MB		 2645 if (err && steer_qp)
2646 mlx4_ib_steer_qp_reg(dev, qp, 0);
225c7b1f 2647 kfree(context);
25476b02
JM		 2648 if (qp->pri.candidate_smac ||
2649 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2f5bb473
JM		 2650 if (err) {
2651 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
2652 } else {
25476b02 2653 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2f5bb473
JM		 2654 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2655 qp->pri.smac = qp->pri.candidate_smac;
2656 qp->pri.smac_index = qp->pri.candidate_smac_index;
2657 qp->pri.smac_port = qp->pri.candidate_smac_port;
2658 }
2659 qp->pri.candidate_smac = 0;
2660 qp->pri.candidate_smac_index = 0;
2661 qp->pri.candidate_smac_port = 0;
2662 }
2663 if (qp->alt.candidate_smac) {
2664 if (err) {
2665 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
2666 } else {
2667 if (qp->alt.smac)
2668 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2669 qp->alt.smac = qp->alt.candidate_smac;
2670 qp->alt.smac_index = qp->alt.candidate_smac_index;
2671 qp->alt.smac_port = qp->alt.candidate_smac_port;
2672 }
2673 qp->alt.candidate_smac = 0;
2674 qp->alt.candidate_smac_index = 0;
2675 qp->alt.candidate_smac_port = 0;
2676 }
2677
2678 if (qp->pri.update_vid) {
2679 if (err) {
2680 if (qp->pri.candidate_vid < 0x1000)
2681 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
2682 qp->pri.candidate_vid);
2683 } else {
2684 if (qp->pri.vid < 0x1000)
2685 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2686 qp->pri.vid);
2687 qp->pri.vid = qp->pri.candidate_vid;
2688 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2689 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
2690 }
2691 qp->pri.candidate_vid = 0xFFFF;
2692 qp->pri.update_vid = 0;
2693 }
2694
2695 if (qp->alt.update_vid) {
2696 if (err) {
2697 if (qp->alt.candidate_vid < 0x1000)
2698 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2699 qp->alt.candidate_vid);
2700 } else {
2701 if (qp->alt.vid < 0x1000)
2702 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2703 qp->alt.vid);
2704 qp->alt.vid = qp->alt.candidate_vid;
2705 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2706 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
2707 }
2708 qp->alt.candidate_vid = 0xFFFF;
2709 qp->alt.update_vid = 0;
2710 }
2711
225c7b1f
RD		 2712 return err;
2713}
2714
3078f5f1
GL		 2715enum {
2716 MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK = (IB_QP_STATE |
2717 IB_QP_PORT),
2718};
2719
e1b866c6
MS		 2720static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2721 int attr_mask, struct ib_udata *udata)
65adfa91
MT		 2722{
2723 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2724 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2725 enum ib_qp_state cur_state, new_state;
2726 int err = -EINVAL;
65adfa91
MT		 2727 mutex_lock(&qp->mutex);
2728
2729 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2730 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2731
dd5f03be 2732 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
d31131bb 2733 attr_mask)) {
b1d8eb5a
JM		 2734 pr_debug("qpn 0x%x: invalid attribute mask specified "
2735 "for transition %d to %d. qp_type %d,"
2736 " attr_mask 0x%x\n",
2737 ibqp->qp_num, cur_state, new_state,
2738 ibqp->qp_type, attr_mask);
65adfa91 2739 goto out;
b1d8eb5a 2740 }
65adfa91 2741
3078f5f1
GL		 2742 if (ibqp->rwq_ind_tbl) {
2743 if (!(((cur_state == IB_QPS_RESET) &&
2744 (new_state == IB_QPS_INIT)) ||
2745 ((cur_state == IB_QPS_INIT) &&
2746 (new_state == IB_QPS_RTR)))) {
2747 pr_debug("qpn 0x%x: RSS QP unsupported transition %d to %d\n",
2748 ibqp->qp_num, cur_state, new_state);
2749
2750 err = -EOPNOTSUPP;
2751 goto out;
2752 }
2753
2754 if (attr_mask & ~MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK) {
2755 pr_debug("qpn 0x%x: RSS QP unsupported attribute mask 0x%x for transition %d to %d\n",
2756 ibqp->qp_num, attr_mask, cur_state, new_state);
2757
2758 err = -EOPNOTSUPP;
2759 goto out;
2760 }
2761 }
2762
c6215745
MS		 2763 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2764 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2765 if ((ibqp->qp_type == IB_QPT_RC) ||
2766 (ibqp->qp_type == IB_QPT_UD) ||
2767 (ibqp->qp_type == IB_QPT_UC) ||
2768 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2769 (ibqp->qp_type == IB_QPT_XRC_INI)) {
2770 attr->port_num = mlx4_ib_bond_next_port(dev);
2771 }
2772 } else {
2773 /* no sense in changing port_num
2774 * when ports are bonded */
2775 attr_mask &= ~IB_QP_PORT;
2776 }
2777 }
2778
65adfa91 2779 if ((attr_mask & IB_QP_PORT) &&
1ffeb2eb 2780 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
b1d8eb5a
JM		 2781 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2782 "for transition %d to %d. qp_type %d\n",
2783 ibqp->qp_num, attr->port_num, cur_state,
2784 new_state, ibqp->qp_type);
65adfa91
MT		 2785 goto out;
2786 }
2787
3987a2d3
OG		 2788 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2789 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2790 IB_LINK_LAYER_ETHERNET))
2791 goto out;
2792
5ae2a7a8
RD		 2793 if (attr_mask & IB_QP_PKEY_INDEX) {
2794 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
b1d8eb5a
JM		 2795 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2796 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2797 "for transition %d to %d. qp_type %d\n",
2798 ibqp->qp_num, attr->pkey_index, cur_state,
2799 new_state, ibqp->qp_type);
5ae2a7a8 2800 goto out;
b1d8eb5a 2801 }
5ae2a7a8
RD		 2802 }
2803
65adfa91
MT		 2804 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2805 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
b1d8eb5a
JM		 2806 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2807 "Transition %d to %d. qp_type %d\n",
2808 ibqp->qp_num, attr->max_rd_atomic, cur_state,
2809 new_state, ibqp->qp_type);
65adfa91
MT		 2810 goto out;
2811 }
2812
2813 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2814 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
b1d8eb5a
JM		 2815 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2816 "Transition %d to %d. qp_type %d\n",
2817 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2818 new_state, ibqp->qp_type);
65adfa91
MT		 2819 goto out;
2820 }
2821
2822 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2823 err = 0;
2824 goto out;
2825 }
2826
3078f5f1 2827 if (ibqp->rwq_ind_tbl && (new_state == IB_QPS_INIT)) {
89944450
SR		 2828 err = bringup_rss_rwqs(ibqp->rwq_ind_tbl, attr->port_num,
2829 udata);
3078f5f1
GL		 2830 if (err)
2831 goto out;
2832 }
2833
400b1ebc 2834 err = __mlx4_ib_modify_qp(ibqp, MLX4_IB_QP_SRC, attr, attr_mask,
89944450 2835 cur_state, new_state, udata);
65adfa91 2836
3078f5f1 2837 if (ibqp->rwq_ind_tbl && err)
89944450 2838 bring_down_rss_rwqs(ibqp->rwq_ind_tbl, udata);
3078f5f1 2839
c6215745
MS		 2840 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2841 attr->port_num = 1;
2842
65adfa91
MT		 2843out:
2844 mutex_unlock(&qp->mutex);
2845 return err;
2846}
2847
e1b866c6
MS		 2848int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2849 int attr_mask, struct ib_udata *udata)
2850{
2851 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2852 int ret;
2853
2854 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata);
2855
2856 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2857 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
2858 int err = 0;
2859
2860 if (sqp->roce_v2_gsi)
2861 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask);
2862 if (err)
2863 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n",
2864 err);
2865 }
2866 return ret;
2867}
2868
99ec41d0
JM		 2869static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2870{
2871 int i;
2872 for (i = 0; i < dev->caps.num_ports; i++) {
c73c8b1e
EBE		 2873 if (qpn == dev->caps.spec_qps[i].qp0_proxy ||
2874 qpn == dev->caps.spec_qps[i].qp0_tunnel) {
2875 *qkey = dev->caps.spec_qps[i].qp0_qkey;
99ec41d0
JM		 2876 return 0;
2877 }
2878 }
2879 return -EINVAL;
2880}
2881
1ffeb2eb 2882static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
f696bf6d 2883 const struct ib_ud_wr *wr,
1ffeb2eb
JM		 2884 void *wqe, unsigned *mlx_seg_len)
2885{
2886 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2887 struct ib_device *ib_dev = &mdev->ib_dev;
2888 struct mlx4_wqe_mlx_seg *mlx = wqe;
2889 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2890 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 2891 u16 pkey;
2892 u32 qkey;
2893 int send_size;
2894 int header_size;
2895 int spc;
074fdd59 2896 int err;
1ffeb2eb
JM		 2897 int i;
2898
e622f2f4 2899 if (wr->wr.opcode != IB_WR_SEND)
1ffeb2eb
JM		 2900 return -EINVAL;
2901
2902 send_size = 0;
2903
e622f2f4
CH		 2904 for (i = 0; i < wr->wr.num_sge; ++i)
2905 send_size += wr->wr.sg_list[i].length;
1ffeb2eb
JM		 2906
2907 /* for proxy-qp0 sends, need to add in size of tunnel header */
2908 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2909 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2910 send_size += sizeof (struct mlx4_ib_tunnel_header);
2911
25f40220 2912 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
1ffeb2eb
JM		 2913
2914 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2915 sqp->ud_header.lrh.service_level =
2916 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2917 sqp->ud_header.lrh.destination_lid =
2918 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2919 sqp->ud_header.lrh.source_lid =
2920 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2921 }
2922
2923 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2924
2925 /* force loopback */
2926 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2927 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2928
2929 sqp->ud_header.lrh.virtual_lane = 0;
e622f2f4 2930 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
074fdd59
JM		 2931 err = ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2932 if (err)
2933 return err;
1ffeb2eb
JM		 2934 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2935 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
e622f2f4 2936 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
1ffeb2eb
JM		 2937 else
2938 sqp->ud_header.bth.destination_qpn =
c73c8b1e 2939 cpu_to_be32(mdev->dev->caps.spec_qps[sqp->qp.port - 1].qp0_tunnel);
1ffeb2eb
JM		 2940
2941 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
99ec41d0
JM		 2942 if (mlx4_is_master(mdev->dev)) {
2943 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2944 return -EINVAL;
2945 } else {
2946 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2947 return -EINVAL;
2948 }
1ffeb2eb
JM		 2949 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2950 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2951
2952 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2953 sqp->ud_header.immediate_present = 0;
2954
2955 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2956
2957 /*
2958 * Inline data segments may not cross a 64 byte boundary. If
2959 * our UD header is bigger than the space available up to the
2960 * next 64 byte boundary in the WQE, use two inline data
2961 * segments to hold the UD header.
2962 */
2963 spc = MLX4_INLINE_ALIGN -
2964 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2965 if (header_size <= spc) {
2966 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2967 memcpy(inl + 1, sqp->header_buf, header_size);
2968 i = 1;
2969 } else {
2970 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2971 memcpy(inl + 1, sqp->header_buf, spc);
2972
2973 inl = (void *) (inl + 1) + spc;
2974 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2975 /*
2976 * Need a barrier here to make sure all the data is
2977 * visible before the byte_count field is set.
2978 * Otherwise the HCA prefetcher could grab the 64-byte
2979 * chunk with this inline segment and get a valid (!=
2980 * 0xffffffff) byte count but stale data, and end up
2981 * generating a packet with bad headers.
2982 *
2983 * The first inline segment's byte_count field doesn't
2984 * need a barrier, because it comes after a
2985 * control/MLX segment and therefore is at an offset
2986 * of 16 mod 64.
2987 */
2988 wmb();
2989 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2990 i = 2;
2991 }
2992
2993 *mlx_seg_len =
2994 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2995 return 0;
2996}
2997
fd10ed8e
JM		 2998static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num)
2999{
3000 union sl2vl_tbl_to_u64 tmp_vltab;
3001 u8 vl;
3002
3003 if (sl > 15)
3004 return 0xf;
3005 tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]);
3006 vl = tmp_vltab.sl8[sl >> 1];
3007 if (sl & 1)
3008 vl &= 0x0f;
3009 else
3010 vl >>= 4;
3011 return vl;
3012}
3013
a748d60d
TB		 3014static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num,
3015 int index, union ib_gid *gid,
3016 enum ib_gid_type *gid_type)
3017{
3018 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
3019 struct mlx4_port_gid_table *port_gid_table;
3020 unsigned long flags;
3021
3022 port_gid_table = &iboe->gids[port_num - 1];
3023 spin_lock_irqsave(&iboe->lock, flags);
3024 memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid));
3025 *gid_type = port_gid_table->gids[index].gid_type;
3026 spin_unlock_irqrestore(&iboe->lock, flags);
25e62655 3027 if (rdma_is_zero_gid(gid))
a748d60d
TB		 3028 return -ENOENT;
3029
3030 return 0;
3031}
3032
3ef967a4 3033#define MLX4_ROCEV2_QP1_SPORT 0xC000
f696bf6d 3034static int build_mlx_header(struct mlx4_ib_sqp *sqp, const struct ib_ud_wr *wr,
f438000f 3035 void *wqe, unsigned *mlx_seg_len)
225c7b1f 3036{
a478868a 3037 struct ib_device *ib_dev = sqp->qp.ibqp.device;
a748d60d 3038 struct mlx4_ib_dev *ibdev = to_mdev(ib_dev);
225c7b1f 3039 struct mlx4_wqe_mlx_seg *mlx = wqe;
6ee51a4e 3040 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
225c7b1f 3041 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 3042 struct mlx4_ib_ah *ah = to_mah(wr->ah);
4c3eb3ca 3043 union ib_gid sgid;
225c7b1f
RD		 3044 u16 pkey;
3045 int send_size;
3046 int header_size;
e61ef241 3047 int spc;
225c7b1f 3048 int i;
1ffeb2eb 3049 int err = 0;
57d88cff 3050 u16 vlan = 0xffff;
a29bec12
RD		 3051 bool is_eth;
3052 bool is_vlan = false;
3053 bool is_grh;
3ef967a4
MS		 3054 bool is_udp = false;
3055 int ip_version = 0;
225c7b1f
RD		 3056
3057 send_size = 0;
e622f2f4
CH		 3058 for (i = 0; i < wr->wr.num_sge; ++i)
3059 send_size += wr->wr.sg_list[i].length;
225c7b1f 3060
fa417f7b
EC		 3061 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
3062 is_grh = mlx4_ib_ah_grh_present(ah);
4c3eb3ca 3063 if (is_eth) {
a748d60d 3064 enum ib_gid_type gid_type;
1ffeb2eb
JM		 3065 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3066 /* When multi-function is enabled, the ib_core gid
3067 * indexes don't necessarily match the hw ones, so
3068 * we must use our own cache */
6ee51a4e
JM		 3069 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
3070 be32_to_cpu(ah->av.ib.port_pd) >> 24,
3071 ah->av.ib.gid_index, &sgid.raw[0]);
3072 if (err)
3073 return err;
1ffeb2eb 3074 } else {
a748d60d
TB		 3075 err = fill_gid_by_hw_index(ibdev, sqp->qp.port,
3076 ah->av.ib.gid_index,
3077 &sgid, &gid_type);
3ef967a4 3078 if (!err) {
a748d60d 3079 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
3ef967a4
MS		 3080 if (is_udp) {
3081 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid))
3082 ip_version = 4;
3083 else
3084 ip_version = 6;
3085 is_grh = false;
3086 }
3087 } else {
1ffeb2eb 3088 return err;
3ef967a4 3089 }
1ffeb2eb 3090 }
0e9855db 3091 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
297e0dad
MS		 3092 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
3093 is_vlan = 1;
3094 }
4c3eb3ca 3095 }
25f40220 3096 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
3ef967a4 3097 ip_version, is_udp, 0, &sqp->ud_header);
25f40220
MS		 3098 if (err)
3099 return err;
fa417f7b
EC		 3100
3101 if (!is_eth) {
3102 sqp->ud_header.lrh.service_level =
3103 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
3104 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
3105 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
3106 }
225c7b1f 3107
3ef967a4 3108 if (is_grh || (ip_version == 6)) {
225c7b1f 3109 sqp->ud_header.grh.traffic_class =
fa417f7b 3110 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
225c7b1f 3111 sqp->ud_header.grh.flow_label =
fa417f7b
EC		 3112 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
3113 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
baa0be70 3114 if (is_eth) {
6ee51a4e 3115 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
baa0be70
JM		 3116 } else {
3117 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3118 /* When multi-function is enabled, the ib_core gid
3119 * indexes don't necessarily match the hw ones, so
3120 * we must use our own cache
3121 */
3122 sqp->ud_header.grh.source_gid.global.subnet_prefix =
8ec07bf8
JM		 3123 cpu_to_be64(atomic64_read(&(to_mdev(ib_dev)->sriov.
3124 demux[sqp->qp.port - 1].
3125 subnet_prefix)));
baa0be70
JM		 3126 sqp->ud_header.grh.source_gid.global.interface_id =
3127 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
3128 guid_cache[ah->av.ib.gid_index];
3129 } else {
89af969a
PP		 3130 sqp->ud_header.grh.source_gid =
3131 ah->ibah.sgid_attr->gid;
baa0be70 3132 }
6ee51a4e 3133 }
225c7b1f 3134 memcpy(sqp->ud_header.grh.destination_gid.raw,
fa417f7b 3135 ah->av.ib.dgid, 16);
225c7b1f
RD		 3136 }
3137
3ef967a4
MS		 3138 if (ip_version == 4) {
3139 sqp->ud_header.ip4.tos =
3140 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
3141 sqp->ud_header.ip4.id = 0;
3142 sqp->ud_header.ip4.frag_off = htons(IP_DF);
3143 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit;
3144
3145 memcpy(&sqp->ud_header.ip4.saddr,
3146 sgid.raw + 12, 4);
3147 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4);
3148 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header);
3149 }
3150
3151 if (is_udp) {
3152 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT);
3153 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT);
3154 sqp->ud_header.udp.csum = 0;
3155 }
3156
225c7b1f 3157 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
fa417f7b
EC		 3158
3159 if (!is_eth) {
3160 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
3161 (sqp->ud_header.lrh.destination_lid ==
3162 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
3163 (sqp->ud_header.lrh.service_level << 8));
1ffeb2eb
JM		 3164 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
3165 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
fa417f7b
EC		 3166 mlx->rlid = sqp->ud_header.lrh.destination_lid;
3167 }
225c7b1f 3168
e622f2f4 3169 switch (wr->wr.opcode) {
225c7b1f
RD		 3170 case IB_WR_SEND:
3171 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
3172 sqp->ud_header.immediate_present = 0;
3173 break;
3174 case IB_WR_SEND_WITH_IMM:
3175 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
3176 sqp->ud_header.immediate_present = 1;
e622f2f4 3177 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
225c7b1f
RD		 3178 break;
3179 default:
3180 return -EINVAL;
3181 }
3182
fa417f7b 3183 if (is_eth) {
6ee51a4e 3184 struct in6_addr in6;
3ef967a4 3185 u16 ether_type;
c0c1d3d7
OD		 3186 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
3187
69ae5439 3188 ether_type = (!is_udp) ? ETH_P_IBOE:
3ef967a4
MS		 3189 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6);
3190
c0c1d3d7 3191 mlx->sched_prio = cpu_to_be16(pcp);
fa417f7b 3192
1049f138 3193 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);
fa417f7b 3194 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
6ee51a4e
JM		 3195 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
3196 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
3197 memcpy(&in6, sgid.raw, sizeof(in6));
5ea8bbfc 3198
3e0629cb 3199
fa417f7b
EC		 3200 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
3201 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
4c3eb3ca 3202 if (!is_vlan) {
3ef967a4 3203 sqp->ud_header.eth.type = cpu_to_be16(ether_type);
4c3eb3ca 3204 } else {
3ef967a4 3205 sqp->ud_header.vlan.type = cpu_to_be16(ether_type);
4c3eb3ca
EC		 3206 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
3207 }
fa417f7b 3208 } else {
fd10ed8e
JM		 3209 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 :
3210 sl_to_vl(to_mdev(ib_dev),
3211 sqp->ud_header.lrh.service_level,
3212 sqp->qp.port);
3213 if (sqp->qp.ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15)
3214 return -EINVAL;
fa417f7b
EC		 3215 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
3216 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
3217 }
e622f2f4 3218 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
225c7b1f 3219 if (!sqp->qp.ibqp.qp_num)
074fdd59
JM		 3220 err = ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index,
3221 &pkey);
225c7b1f 3222 else
074fdd59
JM		 3223 err = ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index,
3224 &pkey);
3225 if (err)
3226 return err;
3227
225c7b1f 3228 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
e622f2f4 3229 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
225c7b1f 3230 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
e622f2f4
CH		 3231 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
3232 sqp->qkey : wr->remote_qkey);
225c7b1f
RD		 3233 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
3234
3235 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
3236
3237 if (0) {
987c8f8f 3238 pr_err("built UD header of size %d:\n", header_size);
225c7b1f
RD		 3239 for (i = 0; i < header_size / 4; ++i) {
3240 if (i % 8 == 0)
987c8f8f
SP		 3241 pr_err(" [%02x] ", i * 4);
3242 pr_cont(" %08x",
3243 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
225c7b1f 3244 if ((i + 1) % 8 == 0)
987c8f8f 3245 pr_cont("\n");
225c7b1f 3246 }
987c8f8f 3247 pr_err("\n");
225c7b1f
RD		 3248 }
3249
e61ef241
RD		 3250 /*
3251 * Inline data segments may not cross a 64 byte boundary. If
3252 * our UD header is bigger than the space available up to the
3253 * next 64 byte boundary in the WQE, use two inline data
3254 * segments to hold the UD header.
3255 */
3256 spc = MLX4_INLINE_ALIGN -
3257 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3258 if (header_size <= spc) {
3259 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
3260 memcpy(inl + 1, sqp->header_buf, header_size);
3261 i = 1;
3262 } else {
3263 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3264 memcpy(inl + 1, sqp->header_buf, spc);
3265
3266 inl = (void *) (inl + 1) + spc;
3267 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
3268 /*
3269 * Need a barrier here to make sure all the data is
3270 * visible before the byte_count field is set.
3271 * Otherwise the HCA prefetcher could grab the 64-byte
3272 * chunk with this inline segment and get a valid (!=
3273 * 0xffffffff) byte count but stale data, and end up
3274 * generating a packet with bad headers.
3275 *
3276 * The first inline segment's byte_count field doesn't
3277 * need a barrier, because it comes after a
3278 * control/MLX segment and therefore is at an offset
3279 * of 16 mod 64.
3280 */
3281 wmb();
3282 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
3283 i = 2;
3284 }
225c7b1f 3285
f438000f
RD		 3286 *mlx_seg_len =
3287 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
3288 return 0;
225c7b1f
RD		 3289}
3290
3291static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3292{
3293 unsigned cur;
3294 struct mlx4_ib_cq *cq;
3295
3296 cur = wq->head - wq->tail;
0e6e7416 3297 if (likely(cur + nreq < wq->max_post))
225c7b1f
RD		 3298 return 0;
3299
3300 cq = to_mcq(ib_cq);
3301 spin_lock(&cq->lock);
3302 cur = wq->head - wq->tail;
3303 spin_unlock(&cq->lock);
3304
0e6e7416 3305 return cur + nreq >= wq->max_post;
225c7b1f
RD		 3306}
3307
95d04f07
RD		 3308static __be32 convert_access(int acc)
3309{
6ff63e19
SM		 3310 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
3311 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
3312 (acc & IB_ACCESS_REMOTE_WRITE ?
3313 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
3314 (acc & IB_ACCESS_REMOTE_READ ?
3315 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
95d04f07
RD		 3316 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
3317 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
3318}
3319
1b2cd0fc 3320static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
f696bf6d 3321 const struct ib_reg_wr *wr)
1b2cd0fc
SG		 3322{
3323 struct mlx4_ib_mr *mr = to_mmr(wr->mr);
3324
3325 fseg->flags = convert_access(wr->access);
3326 fseg->mem_key = cpu_to_be32(wr->key);
3327 fseg->buf_list = cpu_to_be64(mr->page_map);
3328 fseg->start_addr = cpu_to_be64(mr->ibmr.iova);
3329 fseg->reg_len = cpu_to_be64(mr->ibmr.length);
3330 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
3331 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size));
3332 fseg->reserved[0] = 0;
3333 fseg->reserved[1] = 0;
3334}
3335
95d04f07
RD		 3336static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
3337{
aee38fad
SM		 3338 memset(iseg, 0, sizeof(*iseg));
3339 iseg->mem_key = cpu_to_be32(rkey);
95d04f07
RD		 3340}
3341
0fbfa6a9
RD		 3342static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
3343 u64 remote_addr, u32 rkey)
3344{
3345 rseg->raddr = cpu_to_be64(remote_addr);
3346 rseg->rkey = cpu_to_be32(rkey);
3347 rseg->reserved = 0;
3348}
3349
e622f2f4 3350static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
f696bf6d 3351 const struct ib_atomic_wr *wr)
0fbfa6a9 3352{
e622f2f4
CH		 3353 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
3354 aseg->swap_add = cpu_to_be64(wr->swap);
3355 aseg->compare = cpu_to_be64(wr->compare_add);
3356 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
3357 aseg->swap_add = cpu_to_be64(wr->compare_add);
3358 aseg->compare = cpu_to_be64(wr->compare_add_mask);
0fbfa6a9 3359 } else {
e622f2f4 3360 aseg->swap_add = cpu_to_be64(wr->compare_add);
0fbfa6a9
RD		 3361 aseg->compare = 0;
3362 }
3363
3364}
3365
6fa8f719 3366static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
f696bf6d 3367 const struct ib_atomic_wr *wr)
6fa8f719 3368{
e622f2f4
CH		 3369 aseg->swap_add = cpu_to_be64(wr->swap);
3370 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask);
3371 aseg->compare = cpu_to_be64(wr->compare_add);
3372 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask);
6fa8f719
VS		 3373}
3374
0fbfa6a9 3375static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
f696bf6d 3376 const struct ib_ud_wr *wr)
0fbfa6a9 3377{
e622f2f4
CH		 3378 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
3379 dseg->dqpn = cpu_to_be32(wr->remote_qpn);
3380 dseg->qkey = cpu_to_be32(wr->remote_qkey);
3381 dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
3382 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
0fbfa6a9
RD		 3383}
3384
1ffeb2eb
JM		 3385static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
3386 struct mlx4_wqe_datagram_seg *dseg,
f696bf6d 3387 const struct ib_ud_wr *wr,
97982f5a 3388 enum mlx4_ib_qp_type qpt)
1ffeb2eb 3389{
e622f2f4 3390 union mlx4_ext_av *av = &to_mah(wr->ah)->av;
1ffeb2eb
JM		 3391 struct mlx4_av sqp_av = {0};
3392 int port = *((u8 *) &av->ib.port_pd) & 0x3;
3393
3394 /* force loopback */
3395 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
3396 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
3397 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
3398 cpu_to_be32(0xf0000000);
3399
3400 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
97982f5a 3401 if (qpt == MLX4_IB_QPT_PROXY_GSI)
c73c8b1e 3402 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp1_tunnel);
97982f5a 3403 else
c73c8b1e 3404 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp0_tunnel);
47605df9
JM		 3405 /* Use QKEY from the QP context, which is set by master */
3406 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1ffeb2eb
JM		 3407}
3408
f696bf6d
BVA		 3409static void build_tunnel_header(const struct ib_ud_wr *wr, void *wqe,
3410 unsigned *mlx_seg_len)
1ffeb2eb
JM		 3411{
3412 struct mlx4_wqe_inline_seg *inl = wqe;
3413 struct mlx4_ib_tunnel_header hdr;
e622f2f4 3414 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 3415 int spc;
3416 int i;
3417
3418 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
e622f2f4
CH		 3419 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
3420 hdr.pkey_index = cpu_to_be16(wr->pkey_index);
3421 hdr.qkey = cpu_to_be32(wr->remote_qkey);
5ea8bbfc
JM		 3422 memcpy(hdr.mac, ah->av.eth.mac, 6);
3423 hdr.vlan = ah->av.eth.vlan;
1ffeb2eb
JM		 3424
3425 spc = MLX4_INLINE_ALIGN -
3426 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3427 if (sizeof (hdr) <= spc) {
3428 memcpy(inl + 1, &hdr, sizeof (hdr));
3429 wmb();
3430 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
3431 i = 1;
3432 } else {
3433 memcpy(inl + 1, &hdr, spc);
3434 wmb();
3435 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3436
3437 inl = (void *) (inl + 1) + spc;
3438 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
3439 wmb();
3440 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
3441 i = 2;
3442 }
3443
3444 *mlx_seg_len =
3445 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
3446}
3447
6e694ea3
JM		 3448static void set_mlx_icrc_seg(void *dseg)
3449{
3450 u32 *t = dseg;
3451 struct mlx4_wqe_inline_seg *iseg = dseg;
3452
3453 t[1] = 0;
3454
3455 /*
3456 * Need a barrier here before writing the byte_count field to
3457 * make sure that all the data is visible before the
3458 * byte_count field is set. Otherwise, if the segment begins
3459 * a new cacheline, the HCA prefetcher could grab the 64-byte
3460 * chunk and get a valid (!= * 0xffffffff) byte count but
3461 * stale data, and end up sending the wrong data.
3462 */
3463 wmb();
3464
3465 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
3466}
3467
3468static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
d420d9e3 3469{
d420d9e3
RD		 3470 dseg->lkey = cpu_to_be32(sg->lkey);
3471 dseg->addr = cpu_to_be64(sg->addr);
6e694ea3
JM		 3472
3473 /*
3474 * Need a barrier here before writing the byte_count field to
3475 * make sure that all the data is visible before the
3476 * byte_count field is set. Otherwise, if the segment begins
3477 * a new cacheline, the HCA prefetcher could grab the 64-byte
3478 * chunk and get a valid (!= * 0xffffffff) byte count but
3479 * stale data, and end up sending the wrong data.
3480 */
3481 wmb();
3482
3483 dseg->byte_count = cpu_to_be32(sg->length);
d420d9e3
RD		 3484}
3485
2242fa4f
RD		 3486static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
3487{
3488 dseg->byte_count = cpu_to_be32(sg->length);
3489 dseg->lkey = cpu_to_be32(sg->lkey);
3490 dseg->addr = cpu_to_be64(sg->addr);
3491}
3492
f696bf6d
BVA		 3493static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe,
3494 const struct ib_ud_wr *wr, struct mlx4_ib_qp *qp,
3495 unsigned *lso_seg_len, __be32 *lso_hdr_sz, __be32 *blh)
b832be1e 3496{
e622f2f4 3497 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
b832be1e 3498
417608c2
EC		 3499 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
3500 *blh = cpu_to_be32(1 << 6);
b832be1e
EC		 3501
3502 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
e622f2f4 3503 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
b832be1e
EC		 3504 return -EINVAL;
3505
e622f2f4 3506 memcpy(wqe->header, wr->header, wr->hlen);
b832be1e 3507
e622f2f4 3508 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen);
b832be1e
EC		 3509 *lso_seg_len = halign;
3510 return 0;
3511}
3512
f696bf6d 3513static __be32 send_ieth(const struct ib_send_wr *wr)
95d04f07
RD		 3514{
3515 switch (wr->opcode) {
3516 case IB_WR_SEND_WITH_IMM:
3517 case IB_WR_RDMA_WRITE_WITH_IMM:
3518 return wr->ex.imm_data;
3519
3520 case IB_WR_SEND_WITH_INV:
3521 return cpu_to_be32(wr->ex.invalidate_rkey);
3522
3523 default:
3524 return 0;
3525 }
3526}
3527
1ffeb2eb
JM		 3528static void add_zero_len_inline(void *wqe)
3529{
3530 struct mlx4_wqe_inline_seg *inl = wqe;
3531 memset(wqe, 0, 16);
3532 inl->byte_count = cpu_to_be32(1 << 31);
3533}
3534
d34ac5cd
BVA		 3535static int _mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
3536 const struct ib_send_wr **bad_wr, bool drain)
225c7b1f
RD		 3537{
3538 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3539 void *wqe;
3540 struct mlx4_wqe_ctrl_seg *ctrl;
6e694ea3 3541 struct mlx4_wqe_data_seg *dseg;
225c7b1f
RD		 3542 unsigned long flags;
3543 int nreq;
3544 int err = 0;
ea54b10c 3545 unsigned ind;
ea54b10c 3546 int uninitialized_var(size);
a3d8e159 3547 unsigned uninitialized_var(seglen);
0fd7e1d8
RD		 3548 __be32 dummy;
3549 __be32 *lso_wqe;
3550 __be32 uninitialized_var(lso_hdr_sz);
417608c2 3551 __be32 blh;
225c7b1f 3552 int i;
35f05dab 3553 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3554
e1b866c6
MS		 3555 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
3556 struct mlx4_ib_sqp *sqp = to_msqp(qp);
3557
3558 if (sqp->roce_v2_gsi) {
3559 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah);
a748d60d 3560 enum ib_gid_type gid_type;
e1b866c6
MS		 3561 union ib_gid gid;
3562
a748d60d
TB		 3563 if (!fill_gid_by_hw_index(mdev, sqp->qp.port,
3564 ah->av.ib.gid_index,
3565 &gid, &gid_type))
3566 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ?
3567 to_mqp(sqp->roce_v2_gsi) : qp;
3568 else
e1b866c6
MS		 3569 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n",
3570 ah->av.ib.gid_index);
e1b866c6
MS		 3571 }
3572 }
3573
96db0e03 3574 spin_lock_irqsave(&qp->sq.lock, flags);
1975acd9
YH		 3575 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR &&
3576 !drain) {
35f05dab
YH		 3577 err = -EIO;
3578 *bad_wr = wr;
3579 nreq = 0;
3580 goto out;
3581 }
225c7b1f 3582
ea54b10c 3583 ind = qp->sq_next_wqe;
225c7b1f
RD		 3584
3585 for (nreq = 0; wr; ++nreq, wr = wr->next) {
0fd7e1d8 3586 lso_wqe = &dummy;
417608c2 3587 blh = 0;
0fd7e1d8 3588
225c7b1f
RD		 3589 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
3590 err = -ENOMEM;
3591 *bad_wr = wr;
3592 goto out;
3593 }
3594
3595 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
3596 err = -EINVAL;
3597 *bad_wr = wr;
3598 goto out;
3599 }
3600
0e6e7416 3601 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
ea54b10c 3602 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
225c7b1f
RD		 3603
3604 ctrl->srcrb_flags =
3605 (wr->send_flags & IB_SEND_SIGNALED ?
3606 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
3607 (wr->send_flags & IB_SEND_SOLICITED ?
3608 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
8ff095ec
EC		 3609 ((wr->send_flags & IB_SEND_IP_CSUM) ?
3610 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
3611 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
225c7b1f
RD		 3612 qp->sq_signal_bits;
3613
95d04f07 3614 ctrl->imm = send_ieth(wr);
225c7b1f
RD		 3615
3616 wqe += sizeof *ctrl;
3617 size = sizeof *ctrl / 16;
3618
1ffeb2eb
JM		 3619 switch (qp->mlx4_ib_qp_type) {
3620 case MLX4_IB_QPT_RC:
3621 case MLX4_IB_QPT_UC:
225c7b1f
RD		 3622 switch (wr->opcode) {
3623 case IB_WR_ATOMIC_CMP_AND_SWP:
3624 case IB_WR_ATOMIC_FETCH_AND_ADD:
6fa8f719 3625 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
e622f2f4
CH		 3626 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3627 atomic_wr(wr)->rkey);
225c7b1f
RD		 3628 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3629
e622f2f4 3630 set_atomic_seg(wqe, atomic_wr(wr));
225c7b1f 3631 wqe += sizeof (struct mlx4_wqe_atomic_seg);
0fbfa6a9 3632
225c7b1f
RD		 3633 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3634 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
6fa8f719
VS		 3635
3636 break;
3637
3638 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
e622f2f4
CH		 3639 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3640 atomic_wr(wr)->rkey);
6fa8f719
VS		 3641 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3642
e622f2f4 3643 set_masked_atomic_seg(wqe, atomic_wr(wr));
6fa8f719
VS		 3644 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
3645
3646 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3647 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
225c7b1f
RD		 3648
3649 break;
3650
3651 case IB_WR_RDMA_READ:
3652 case IB_WR_RDMA_WRITE:
3653 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3654 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
3655 rdma_wr(wr)->rkey);
225c7b1f
RD		 3656 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3657 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
225c7b1f 3658 break;
95d04f07
RD		 3659
3660 case IB_WR_LOCAL_INV:
2ac6bf4d
JM		 3661 ctrl->srcrb_flags |=
3662 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 3663 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
3664 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
3665 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
3666 break;
3667
1b2cd0fc
SG		 3668 case IB_WR_REG_MR:
3669 ctrl->srcrb_flags |=
3670 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3671 set_reg_seg(wqe, reg_wr(wr));
3672 wqe += sizeof(struct mlx4_wqe_fmr_seg);
3673 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
3674 break;
3675
225c7b1f
RD		 3676 default:
3677 /* No extra segments required for sends */
3678 break;
3679 }
3680 break;
3681
1ffeb2eb 3682 case MLX4_IB_QPT_TUN_SMI_OWNER:
e622f2f4
CH		 3683 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3684 ctrl, &seglen);
1ffeb2eb
JM		 3685 if (unlikely(err)) {
3686 *bad_wr = wr;
3687 goto out;
3688 }
3689 wqe += seglen;
3690 size += seglen / 16;
3691 break;
3692 case MLX4_IB_QPT_TUN_SMI:
3693 case MLX4_IB_QPT_TUN_GSI:
3694 /* this is a UD qp used in MAD responses to slaves. */
e622f2f4 3695 set_datagram_seg(wqe, ud_wr(wr));
1ffeb2eb
JM		 3696 /* set the forced-loopback bit in the data seg av */
3697 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
3698 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3699 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3700 break;
3701 case MLX4_IB_QPT_UD:
e622f2f4 3702 set_datagram_seg(wqe, ud_wr(wr));
225c7b1f
RD		 3703 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3704 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
b832be1e
EC		 3705
3706 if (wr->opcode == IB_WR_LSO) {
e622f2f4
CH		 3707 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
3708 &lso_hdr_sz, &blh);
b832be1e
EC		 3709 if (unlikely(err)) {
3710 *bad_wr = wr;
3711 goto out;
3712 }
0fd7e1d8 3713 lso_wqe = (__be32 *) wqe;
b832be1e
EC		 3714 wqe += seglen;
3715 size += seglen / 16;
3716 }
225c7b1f
RD		 3717 break;
3718
1ffeb2eb 3719 case MLX4_IB_QPT_PROXY_SMI_OWNER:
e622f2f4
CH		 3720 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3721 ctrl, &seglen);
1ffeb2eb
JM		 3722 if (unlikely(err)) {
3723 *bad_wr = wr;
3724 goto out;
3725 }
3726 wqe += seglen;
3727 size += seglen / 16;
3728 /* to start tunnel header on a cache-line boundary */
3729 add_zero_len_inline(wqe);
3730 wqe += 16;
3731 size++;
e622f2f4 3732 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 3733 wqe += seglen;
3734 size += seglen / 16;
3735 break;
3736 case MLX4_IB_QPT_PROXY_SMI:
1ffeb2eb
JM		 3737 case MLX4_IB_QPT_PROXY_GSI:
3738 /* If we are tunneling special qps, this is a UD qp.
3739 * In this case we first add a UD segment targeting
3740 * the tunnel qp, and then add a header with address
3741 * information */
e622f2f4
CH		 3742 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
3743 ud_wr(wr),
97982f5a 3744 qp->mlx4_ib_qp_type);
1ffeb2eb
JM		 3745 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3746 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
e622f2f4 3747 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 3748 wqe += seglen;
3749 size += seglen / 16;
3750 break;
3751
3752 case MLX4_IB_QPT_SMI:
3753 case MLX4_IB_QPT_GSI:
e622f2f4
CH		 3754 err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
3755 &seglen);
f438000f 3756 if (unlikely(err)) {
225c7b1f
RD		 3757 *bad_wr = wr;
3758 goto out;
3759 }
f438000f
RD		 3760 wqe += seglen;
3761 size += seglen / 16;
225c7b1f
RD		 3762 break;
3763
3764 default:
3765 break;
3766 }
3767
6e694ea3
JM		 3768 /*
3769 * Write data segments in reverse order, so as to
3770 * overwrite cacheline stamp last within each
3771 * cacheline. This avoids issues with WQE
3772 * prefetching.
3773 */
225c7b1f 3774
6e694ea3
JM		 3775 dseg = wqe;
3776 dseg += wr->num_sge - 1;
3777 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
225c7b1f
RD		 3778
3779 /* Add one more inline data segment for ICRC for MLX sends */
1ffeb2eb
JM		 3780 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
3781 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
3782 qp->mlx4_ib_qp_type &
3783 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6e694ea3 3784 set_mlx_icrc_seg(dseg + 1);
225c7b1f
RD		 3785 size += sizeof (struct mlx4_wqe_data_seg) / 16;
3786 }
3787
6e694ea3
JM		 3788 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3789 set_data_seg(dseg, wr->sg_list + i);
3790
0fd7e1d8
RD		 3791 /*
3792 * Possibly overwrite stamping in cacheline with LSO
3793 * segment only after making sure all data segments
3794 * are written.
3795 */
3796 wmb();
3797 *lso_wqe = lso_hdr_sz;
3798
224e92e0
BB		 3799 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ?
3800 MLX4_WQE_CTRL_FENCE : 0) | size;
225c7b1f
RD		 3801
3802 /*
3803 * Make sure descriptor is fully written before
3804 * setting ownership bit (because HW can start
3805 * executing as soon as we do).
3806 */
3807 wmb();
3808
59b0ed12 3809 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
4ba6b8ea 3810 *bad_wr = wr;
225c7b1f
RD		 3811 err = -EINVAL;
3812 goto out;
3813 }
3814
3815 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
417608c2 3816 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
0e6e7416
RD		 3817
3818 /*
3819 * We can improve latency by not stamping the last
3820 * send queue WQE until after ringing the doorbell, so
3821 * only stamp here if there are still more WQEs to post.
3822 */
f95ccffc
JM		 3823 if (wr->next)
3824 stamp_send_wqe(qp, ind + qp->sq_spare_wqes);
3825 ind++;
225c7b1f
RD		 3826 }
3827
3828out:
3829 if (likely(nreq)) {
3830 qp->sq.head += nreq;
3831
3832 /*
3833 * Make sure that descriptors are written before
3834 * doorbell record.
3835 */
3836 wmb();
3837
97d82a48
SK		 3838 writel_relaxed(qp->doorbell_qpn,
3839 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
225c7b1f 3840
f95ccffc 3841 stamp_send_wqe(qp, ind + qp->sq_spare_wqes - 1);
ea54b10c 3842
ea54b10c 3843 qp->sq_next_wqe = ind;
225c7b1f
RD		 3844 }
3845
96db0e03 3846 spin_unlock_irqrestore(&qp->sq.lock, flags);
225c7b1f
RD		 3847
3848 return err;
3849}
3850
d34ac5cd
BVA		 3851int mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
3852 const struct ib_send_wr **bad_wr)
1975acd9
YH		 3853{
3854 return _mlx4_ib_post_send(ibqp, wr, bad_wr, false);
3855}
3856
d34ac5cd
BVA		 3857static int _mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
3858 const struct ib_recv_wr **bad_wr, bool drain)
225c7b1f
RD		 3859{
3860 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3861 struct mlx4_wqe_data_seg *scat;
3862 unsigned long flags;
3863 int err = 0;
3864 int nreq;
3865 int ind;
1ffeb2eb 3866 int max_gs;
225c7b1f 3867 int i;
35f05dab 3868 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3869
1ffeb2eb 3870 max_gs = qp->rq.max_gs;
225c7b1f
RD		 3871 spin_lock_irqsave(&qp->rq.lock, flags);
3872
1975acd9
YH		 3873 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR &&
3874 !drain) {
35f05dab
YH		 3875 err = -EIO;
3876 *bad_wr = wr;
3877 nreq = 0;
3878 goto out;
3879 }
3880
0e6e7416 3881 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3882
3883 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2b946077 3884 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
225c7b1f
RD		 3885 err = -ENOMEM;
3886 *bad_wr = wr;
3887 goto out;
3888 }
3889
3890 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3891 err = -EINVAL;
3892 *bad_wr = wr;
3893 goto out;
3894 }
3895
3896 scat = get_recv_wqe(qp, ind);
3897
1ffeb2eb
JM		 3898 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3899 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3900 ib_dma_sync_single_for_device(ibqp->device,
3901 qp->sqp_proxy_rcv[ind].map,
3902 sizeof (struct mlx4_ib_proxy_sqp_hdr),
3903 DMA_FROM_DEVICE);
3904 scat->byte_count =
3905 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3906 /* use dma lkey from upper layer entry */
3907 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3908 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3909 scat++;
3910 max_gs--;
3911 }
3912
2242fa4f
RD		 3913 for (i = 0; i < wr->num_sge; ++i)
3914 __set_data_seg(scat + i, wr->sg_list + i);
225c7b1f 3915
1ffeb2eb 3916 if (i < max_gs) {
225c7b1f
RD		 3917 scat[i].byte_count = 0;
3918 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
3919 scat[i].addr = 0;
3920 }
3921
3922 qp->rq.wrid[ind] = wr->wr_id;
3923
0e6e7416 3924 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3925 }
3926
3927out:
3928 if (likely(nreq)) {
3929 qp->rq.head += nreq;
3930
3931 /*
3932 * Make sure that descriptors are written before
3933 * doorbell record.
3934 */
3935 wmb();
3936
3937 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3938 }
3939
3940 spin_unlock_irqrestore(&qp->rq.lock, flags);
3941
3942 return err;
3943}
6a775e2b 3944
d34ac5cd
BVA		 3945int mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
3946 const struct ib_recv_wr **bad_wr)
1975acd9
YH		 3947{
3948 return _mlx4_ib_post_recv(ibqp, wr, bad_wr, false);
3949}
3950
6a775e2b
JM		 3951static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3952{
3953 switch (mlx4_state) {
3954 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
3955 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
3956 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
3957 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
3958 case MLX4_QP_STATE_SQ_DRAINING:
3959 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
3960 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
3961 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
3962 default: return -1;
3963 }
3964}
3965
3966static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3967{
3968 switch (mlx4_mig_state) {
3969 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
3970 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
3971 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3972 default: return -1;
3973 }
3974}
3975
3976static int to_ib_qp_access_flags(int mlx4_flags)
3977{
3978 int ib_flags = 0;
3979
3980 if (mlx4_flags & MLX4_QP_BIT_RRE)
3981 ib_flags |= IB_ACCESS_REMOTE_READ;
3982 if (mlx4_flags & MLX4_QP_BIT_RWE)
3983 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3984 if (mlx4_flags & MLX4_QP_BIT_RAE)
3985 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3986
3987 return ib_flags;
3988}
3989
71d53ab4 3990static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev,
d8966fcd 3991 struct rdma_ah_attr *ah_attr,
71d53ab4 3992 struct mlx4_qp_path *path)
6a775e2b 3993{
4c3eb3ca 3994 struct mlx4_dev *dev = ibdev->dev;
d8966fcd 3995 u8 port_num = path->sched_queue & 0x40 ? 2 : 1;
4c3eb3ca 3996
d8966fcd 3997 memset(ah_attr, 0, sizeof(*ah_attr));
d8966fcd 3998 if (port_num == 0 || port_num > dev->caps.num_ports)
6a775e2b 3999 return;
f1228867 4000 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num);
6a775e2b 4001
44c58487 4002 if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE)
d8966fcd
DC		 4003 rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) |
4004 ((path->sched_queue & 4) << 1));
4c3eb3ca 4005 else
d8966fcd 4006 rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf);
44c58487 4007 rdma_ah_set_port_num(ah_attr, port_num);
4c3eb3ca 4008
d8966fcd
DC		 4009 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4010 rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f);
4011 rdma_ah_set_static_rate(ah_attr,
4012 path->static_rate ? path->static_rate - 5 : 0);
4013 if (path->grh_mylmc & (1 << 7)) {
4014 rdma_ah_set_grh(ah_attr, NULL,
4015 be32_to_cpu(path->tclass_flowlabel) & 0xfffff,
4016 path->mgid_index,
4017 path->hop_limit,
4018 (be32_to_cpu(path->tclass_flowlabel)
4019 >> 20) & 0xff);
4020 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
6a775e2b
JM		 4021 }
4022}
4023
4024int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
4025 struct ib_qp_init_attr *qp_init_attr)
4026{
4027 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
4028 struct mlx4_ib_qp *qp = to_mqp(ibqp);
4029 struct mlx4_qp_context context;
4030 int mlx4_state;
0df67030
DB		 4031 int err = 0;
4032
3078f5f1
GL		 4033 if (ibqp->rwq_ind_tbl)
4034 return -EOPNOTSUPP;
4035
0df67030 4036 mutex_lock(&qp->mutex);
6a775e2b
JM		 4037
4038 if (qp->state == IB_QPS_RESET) {
4039 qp_attr->qp_state = IB_QPS_RESET;
4040 goto done;
4041 }
4042
4043 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
0df67030
DB		 4044 if (err) {
4045 err = -EINVAL;
4046 goto out;
4047 }
6a775e2b
JM		 4048
4049 mlx4_state = be32_to_cpu(context.flags) >> 28;
4050
0df67030
DB		 4051 qp->state = to_ib_qp_state(mlx4_state);
4052 qp_attr->qp_state = qp->state;
6a775e2b
JM		 4053 qp_attr->path_mtu = context.mtu_msgmax >> 5;
4054 qp_attr->path_mig_state =
4055 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
4056 qp_attr->qkey = be32_to_cpu(context.qkey);
4057 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
4058 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
4059 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
4060 qp_attr->qp_access_flags =
4061 to_ib_qp_access_flags(be32_to_cpu(context.params2));
4062
4063 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
71d53ab4
DC		 4064 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
4065 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
6a775e2b 4066 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
d8966fcd
DC		 4067 qp_attr->alt_port_num =
4068 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
6a775e2b
JM		 4069 }
4070
4071 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1c27cb71
JM		 4072 if (qp_attr->qp_state == IB_QPS_INIT)
4073 qp_attr->port_num = qp->port;
4074 else
4075 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
6a775e2b
JM		 4076
4077 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4078 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
4079
4080 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
4081
4082 qp_attr->max_dest_rd_atomic =
4083 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
4084 qp_attr->min_rnr_timer =
4085 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
4086 qp_attr->timeout = context.pri_path.ackto >> 3;
4087 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
4088 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
4089 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
4090
4091done:
4092 qp_attr->cur_qp_state = qp_attr->qp_state;
7f5eb9bb
RD		 4093 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4094 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4095
6a775e2b 4096 if (!ibqp->uobject) {
7f5eb9bb
RD		 4097 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
4098 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4099 } else {
4100 qp_attr->cap.max_send_wr = 0;
4101 qp_attr->cap.max_send_sge = 0;
6a775e2b
JM		 4102 }
4103
7f5eb9bb
RD		 4104 /*
4105 * We don't support inline sends for kernel QPs (yet), and we
4106 * don't know what userspace's value should be.
4107 */
4108 qp_attr->cap.max_inline_data = 0;
4109
4110 qp_init_attr->cap = qp_attr->cap;
4111
521e575b
RL		 4112 qp_init_attr->create_flags = 0;
4113 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4114 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4115
4116 if (qp->flags & MLX4_IB_QP_LSO)
4117 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
4118
c1c98501
MB		 4119 if (qp->flags & MLX4_IB_QP_NETIF)
4120 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
4121
46db567d
DB		 4122 qp_init_attr->sq_sig_type =
4123 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
4124 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4125
0df67030
DB		 4126out:
4127 mutex_unlock(&qp->mutex);
4128 return err;
6a775e2b
JM		 4129}
4130
400b1ebc
GL		 4131struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd,
4132 struct ib_wq_init_attr *init_attr,
4133 struct ib_udata *udata)
4134{
089b645d
LR		 4135 struct mlx4_dev *dev = to_mdev(pd->device)->dev;
4136 struct ib_qp_init_attr ib_qp_init_attr = {};
400b1ebc
GL		 4137 struct mlx4_ib_qp *qp;
4138 struct mlx4_ib_create_wq ucmd;
4139 int err, required_cmd_sz;
4140
e00b64f7 4141 if (!udata)
400b1ebc
GL		 4142 return ERR_PTR(-EINVAL);
4143
078b3573
GL		 4144 required_cmd_sz = offsetof(typeof(ucmd), comp_mask) +
4145 sizeof(ucmd.comp_mask);
400b1ebc
GL		 4146 if (udata->inlen < required_cmd_sz) {
4147 pr_debug("invalid inlen\n");
4148 return ERR_PTR(-EINVAL);
4149 }
4150
4151 if (udata->inlen > sizeof(ucmd) &&
4152 !ib_is_udata_cleared(udata, sizeof(ucmd),
4153 udata->inlen - sizeof(ucmd))) {
4154 pr_debug("inlen is not supported\n");
4155 return ERR_PTR(-EOPNOTSUPP);
4156 }
4157
4158 if (udata->outlen)
4159 return ERR_PTR(-EOPNOTSUPP);
4160
400b1ebc
GL		 4161 if (init_attr->wq_type != IB_WQT_RQ) {
4162 pr_debug("unsupported wq type %d\n", init_attr->wq_type);
4163 return ERR_PTR(-EOPNOTSUPP);
4164 }
4165
089b645d
LR		 4166 if (init_attr->create_flags & ~IB_WQ_FLAGS_SCATTER_FCS ||
4167 !(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
400b1ebc
GL		 4168 pr_debug("unsupported create_flags %u\n",
4169 init_attr->create_flags);
4170 return ERR_PTR(-EOPNOTSUPP);
4171 }
4172
4173 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
4174 if (!qp)
4175 return ERR_PTR(-ENOMEM);
4176
4177 qp->pri.vid = 0xFFFF;
4178 qp->alt.vid = 0xFFFF;
4179
400b1ebc
GL		 4180 ib_qp_init_attr.qp_context = init_attr->wq_context;
4181 ib_qp_init_attr.qp_type = IB_QPT_RAW_PACKET;
4182 ib_qp_init_attr.cap.max_recv_wr = init_attr->max_wr;
4183 ib_qp_init_attr.cap.max_recv_sge = init_attr->max_sge;
4184 ib_qp_init_attr.recv_cq = init_attr->cq;
4185 ib_qp_init_attr.send_cq = ib_qp_init_attr.recv_cq; /* Dummy CQ */
4186
6d06c9aa
GL		 4187 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS)
4188 ib_qp_init_attr.create_flags |= IB_QP_CREATE_SCATTER_FCS;
4189
089b645d 4190 err = create_rq(pd, &ib_qp_init_attr, udata, qp);
400b1ebc
GL		 4191 if (err) {
4192 kfree(qp);
4193 return ERR_PTR(err);
4194 }
4195
4196 qp->ibwq.event_handler = init_attr->event_handler;
4197 qp->ibwq.wq_num = qp->mqp.qpn;
4198 qp->ibwq.state = IB_WQS_RESET;
4199
4200 return &qp->ibwq;
4201}
4202
4203static int ib_wq2qp_state(enum ib_wq_state state)
4204{
4205 switch (state) {
4206 case IB_WQS_RESET:
4207 return IB_QPS_RESET;
4208 case IB_WQS_RDY:
4209 return IB_QPS_RTR;
4210 default:
4211 return IB_QPS_ERR;
4212 }
4213}
4214
89944450
SR		 4215static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state,
4216 struct ib_udata *udata)
400b1ebc
GL		 4217{
4218 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4219 enum ib_qp_state qp_cur_state;
4220 enum ib_qp_state qp_new_state;
4221 int attr_mask;
4222 int err;
4223
4224 /* ib_qp.state represents the WQ HW state while ib_wq.state represents
4225 * the WQ logic state.
4226 */
4227 qp_cur_state = qp->state;
4228 qp_new_state = ib_wq2qp_state(new_state);
4229
4230 if (ib_wq2qp_state(new_state) == qp_cur_state)
4231 return 0;
4232
4233 if (new_state == IB_WQS_RDY) {
4234 struct ib_qp_attr attr = {};
4235
4236 attr.port_num = qp->port;
4237 attr_mask = IB_QP_PORT;
4238
4239 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, &attr,
89944450
SR		 4240 attr_mask, IB_QPS_RESET, IB_QPS_INIT,
4241 udata);
400b1ebc
GL		 4242 if (err) {
4243 pr_debug("WQN=0x%06x failed to apply RST->INIT on the HW QP\n",
4244 ibwq->wq_num);
4245 return err;
4246 }
4247
4248 qp_cur_state = IB_QPS_INIT;
4249 }
4250
4251 attr_mask = 0;
4252 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, attr_mask,
89944450 4253 qp_cur_state, qp_new_state, udata);
400b1ebc
GL		 4254
4255 if (err && (qp_cur_state == IB_QPS_INIT)) {
4256 qp_new_state = IB_QPS_RESET;
4257 if (__mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL,
89944450
SR		 4258 attr_mask, IB_QPS_INIT, IB_QPS_RESET,
4259 udata)) {
400b1ebc
GL		 4260 pr_warn("WQN=0x%06x failed with reverting HW's resources failure\n",
4261 ibwq->wq_num);
4262 qp_new_state = IB_QPS_INIT;
4263 }
4264 }
4265
4266 qp->state = qp_new_state;
4267
4268 return err;
4269}
4270
4271int mlx4_ib_modify_wq(struct ib_wq *ibwq, struct ib_wq_attr *wq_attr,
4272 u32 wq_attr_mask, struct ib_udata *udata)
4273{
4274 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4275 struct mlx4_ib_modify_wq ucmd = {};
4276 size_t required_cmd_sz;
4277 enum ib_wq_state cur_state, new_state;
4278 int err = 0;
4279
4280 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
4281 sizeof(ucmd.reserved);
4282 if (udata->inlen < required_cmd_sz)
4283 return -EINVAL;
4284
4285 if (udata->inlen > sizeof(ucmd) &&
4286 !ib_is_udata_cleared(udata, sizeof(ucmd),
4287 udata->inlen - sizeof(ucmd)))
4288 return -EOPNOTSUPP;
4289
4290 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4291 return -EFAULT;
4292
4293 if (ucmd.comp_mask || ucmd.reserved)
4294 return -EOPNOTSUPP;
4295
4296 if (wq_attr_mask & IB_WQ_FLAGS)
4297 return -EOPNOTSUPP;
4298
af3a2ecc
LR		 4299 cur_state = wq_attr->curr_wq_state;
4300 new_state = wq_attr->wq_state;
400b1ebc
GL		 4301
4302 if ((new_state == IB_WQS_RDY) && (cur_state == IB_WQS_ERR))
4303 return -EINVAL;
4304
4305 if ((new_state == IB_WQS_ERR) && (cur_state == IB_WQS_RESET))
4306 return -EINVAL;
4307
3078f5f1
GL		 4308 /* Need to protect against the parent RSS which also may modify WQ
4309 * state.
4310 */
4311 mutex_lock(&qp->mutex);
4312
400b1ebc
GL		 4313 /* Can update HW state only if a RSS QP has already associated to this
4314 * WQ, so we can apply its port on the WQ.
4315 */
4316 if (qp->rss_usecnt)
89944450 4317 err = _mlx4_ib_modify_wq(ibwq, new_state, udata);
400b1ebc
GL		 4318
4319 if (!err)
4320 ibwq->state = new_state;
4321
3078f5f1
GL		 4322 mutex_unlock(&qp->mutex);
4323
400b1ebc
GL		 4324 return err;
4325}
4326
a49b1dc7 4327void mlx4_ib_destroy_wq(struct ib_wq *ibwq, struct ib_udata *udata)
400b1ebc
GL		 4328{
4329 struct mlx4_ib_dev *dev = to_mdev(ibwq->device);
4330 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4331
4332 if (qp->counter_index)
4333 mlx4_ib_free_qp_counter(dev, qp);
4334
bdeacabd 4335 destroy_qp_common(dev, qp, MLX4_IB_RWQ_SRC, udata);
400b1ebc
GL		 4336
4337 kfree(qp);
400b1ebc 4338}
b8d46ca0
GL		 4339
4340struct ib_rwq_ind_table
4341*mlx4_ib_create_rwq_ind_table(struct ib_device *device,
4342 struct ib_rwq_ind_table_init_attr *init_attr,
4343 struct ib_udata *udata)
4344{
4345 struct ib_rwq_ind_table *rwq_ind_table;
4346 struct mlx4_ib_create_rwq_ind_tbl_resp resp = {};
4347 unsigned int ind_tbl_size = 1 << init_attr->log_ind_tbl_size;
4348 unsigned int base_wqn;
4349 size_t min_resp_len;
4350 int i;
4351 int err;
4352
4353 if (udata->inlen > 0 &&
4354 !ib_is_udata_cleared(udata, 0,
4355 udata->inlen))
4356 return ERR_PTR(-EOPNOTSUPP);
4357
4358 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4359 if (udata->outlen && udata->outlen < min_resp_len)
4360 return ERR_PTR(-EINVAL);
4361
4362 if (ind_tbl_size >
4363 device->attrs.rss_caps.max_rwq_indirection_table_size) {
4364 pr_debug("log_ind_tbl_size = %d is bigger than supported = %d\n",
4365 ind_tbl_size,
4366 device->attrs.rss_caps.max_rwq_indirection_table_size);
4367 return ERR_PTR(-EINVAL);
4368 }
4369
4370 base_wqn = init_attr->ind_tbl[0]->wq_num;
4371
4372 if (base_wqn % ind_tbl_size) {
4373 pr_debug("WQN=0x%x isn't aligned with indirection table size\n",
4374 base_wqn);
4375 return ERR_PTR(-EINVAL);
4376 }
4377
4378 for (i = 1; i < ind_tbl_size; i++) {
4379 if (++base_wqn != init_attr->ind_tbl[i]->wq_num) {
4380 pr_debug("indirection table's WQNs aren't consecutive\n");
4381 return ERR_PTR(-EINVAL);
4382 }
4383 }
4384
4385 rwq_ind_table = kzalloc(sizeof(*rwq_ind_table), GFP_KERNEL);
4386 if (!rwq_ind_table)
4387 return ERR_PTR(-ENOMEM);
4388
4389 if (udata->outlen) {
4390 resp.response_length = offsetof(typeof(resp), response_length) +
4391 sizeof(resp.response_length);
4392 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4393 if (err)
4394 goto err;
4395 }
4396
4397 return rwq_ind_table;
4398
4399err:
4400 kfree(rwq_ind_table);
4401 return ERR_PTR(err);
4402}
4403
4404int mlx4_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4405{
4406 kfree(ib_rwq_ind_tbl);
4407 return 0;
4408}
1975acd9
YH		 4409
4410struct mlx4_ib_drain_cqe {
4411 struct ib_cqe cqe;
4412 struct completion done;
4413};
4414
4415static void mlx4_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
4416{
4417 struct mlx4_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
4418 struct mlx4_ib_drain_cqe,
4419 cqe);
4420
4421 complete(&cqe->done);
4422}
4423
4424/* This function returns only once the drained WR was completed */
4425static void handle_drain_completion(struct ib_cq *cq,
4426 struct mlx4_ib_drain_cqe *sdrain,
4427 struct mlx4_ib_dev *dev)
4428{
4429 struct mlx4_dev *mdev = dev->dev;
4430
4431 if (cq->poll_ctx == IB_POLL_DIRECT) {
4432 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
4433 ib_process_cq_direct(cq, -1);
4434 return;
4435 }
4436
4437 if (mdev->persist->state == MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4438 struct mlx4_ib_cq *mcq = to_mcq(cq);
4439 bool triggered = false;
4440 unsigned long flags;
4441
4442 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
4443 /* Make sure that the CQ handler won't run if wasn't run yet */
4444 if (!mcq->mcq.reset_notify_added)
4445 mcq->mcq.reset_notify_added = 1;
4446 else
4447 triggered = true;
4448 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
4449
4450 if (triggered) {
4451 /* Wait for any scheduled/running task to be ended */
4452 switch (cq->poll_ctx) {
4453 case IB_POLL_SOFTIRQ:
4454 irq_poll_disable(&cq->iop);
4455 irq_poll_enable(&cq->iop);
4456 break;
4457 case IB_POLL_WORKQUEUE:
4458 cancel_work_sync(&cq->work);
4459 break;
4460 default:
4461 WARN_ON_ONCE(1);
4462 }
4463 }
4464
4465 /* Run the CQ handler - this makes sure that the drain WR will
4466 * be processed if wasn't processed yet.
4467 */
4468 mcq->mcq.comp(&mcq->mcq);
4469 }
4470
4471 wait_for_completion(&sdrain->done);
4472}
4473
4474void mlx4_ib_drain_sq(struct ib_qp *qp)
4475{
4476 struct ib_cq *cq = qp->send_cq;
4477 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
4478 struct mlx4_ib_drain_cqe sdrain;
d34ac5cd 4479 const struct ib_send_wr *bad_swr;
1975acd9
YH		 4480 struct ib_rdma_wr swr = {
4481 .wr = {
4482 .next = NULL,
4483 { .wr_cqe = &sdrain.cqe, },
4484 .opcode = IB_WR_RDMA_WRITE,
4485 },
4486 };
4487 int ret;
4488 struct mlx4_ib_dev *dev = to_mdev(qp->device);
4489 struct mlx4_dev *mdev = dev->dev;
4490
4491 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
4492 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4493 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
4494 return;
4495 }
4496
4497 sdrain.cqe.done = mlx4_ib_drain_qp_done;
4498 init_completion(&sdrain.done);
4499
4500 ret = _mlx4_ib_post_send(qp, &swr.wr, &bad_swr, true);
4501 if (ret) {
4502 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
4503 return;
4504 }
4505
4506 handle_drain_completion(cq, &sdrain, dev);
4507}
4508
4509void mlx4_ib_drain_rq(struct ib_qp *qp)
4510{
4511 struct ib_cq *cq = qp->recv_cq;
4512 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
4513 struct mlx4_ib_drain_cqe rdrain;
d34ac5cd
BVA		 4514 struct ib_recv_wr rwr = {};
4515 const struct ib_recv_wr *bad_rwr;
1975acd9
YH		 4516 int ret;
4517 struct mlx4_ib_dev *dev = to_mdev(qp->device);
4518 struct mlx4_dev *mdev = dev->dev;
4519
4520 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
4521 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4522 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
4523 return;
4524 }
4525
4526 rwr.wr_cqe = &rdrain.cqe;
4527 rdrain.cqe.done = mlx4_ib_drain_qp_done;
4528 init_completion(&rdrain.done);
4529
4530 ret = _mlx4_ib_post_recv(qp, &rwr, &bad_rwr, true);
4531 if (ret) {
4532 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
4533 return;
4534 }
4535
4536 handle_drain_completion(cq, &rdrain, dev);
4537}
Ubuntu Focal Linux kernel mirror