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Merge remote-tracking branches 'asoc/topic/sgtl5000', 'asoc/topic/simple', 'asoc...
[mirror_ubuntu-bionic-kernel.git] / drivers / infiniband / hw / mlx5 / cq.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/kref.h>
34#include <rdma/ib_umem.h>
a8237b32 35#include <rdma/ib_user_verbs.h>
b636401f 36#include <rdma/ib_cache.h>
e126ba97
EC		 37#include "mlx5_ib.h"
38#include "user.h"
39
40static void mlx5_ib_cq_comp(struct mlx5_core_cq *cq)
41{
42 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
43
44 ibcq->comp_handler(ibcq, ibcq->cq_context);
45}
46
47static void mlx5_ib_cq_event(struct mlx5_core_cq *mcq, enum mlx5_event type)
48{
49 struct mlx5_ib_cq *cq = container_of(mcq, struct mlx5_ib_cq, mcq);
50 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
51 struct ib_cq *ibcq = &cq->ibcq;
52 struct ib_event event;
53
54 if (type != MLX5_EVENT_TYPE_CQ_ERROR) {
55 mlx5_ib_warn(dev, "Unexpected event type %d on CQ %06x\n",
56 type, mcq->cqn);
57 return;
58 }
59
60 if (ibcq->event_handler) {
61 event.device = &dev->ib_dev;
62 event.event = IB_EVENT_CQ_ERR;
63 event.element.cq = ibcq;
64 ibcq->event_handler(&event, ibcq->cq_context);
65 }
66}
67
68static void *get_cqe_from_buf(struct mlx5_ib_cq_buf *buf, int n, int size)
69{
70 return mlx5_buf_offset(&buf->buf, n * size);
71}
72
73static void *get_cqe(struct mlx5_ib_cq *cq, int n)
74{
75 return get_cqe_from_buf(&cq->buf, n, cq->mcq.cqe_sz);
76}
77
bde51583
EC		 78static u8 sw_ownership_bit(int n, int nent)
79{
80 return (n & nent) ? 1 : 0;
81}
82
e126ba97
EC		 83static void *get_sw_cqe(struct mlx5_ib_cq *cq, int n)
84{
85 void *cqe = get_cqe(cq, n & cq->ibcq.cqe);
86 struct mlx5_cqe64 *cqe64;
87
88 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
bde51583
EC		 89
90 if (likely((cqe64->op_own) >> 4 != MLX5_CQE_INVALID) &&
91 !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ibcq.cqe + 1)))) {
92 return cqe;
93 } else {
94 return NULL;
95 }
e126ba97
EC		 96}
97
98static void *next_cqe_sw(struct mlx5_ib_cq *cq)
99{
100 return get_sw_cqe(cq, cq->mcq.cons_index);
101}
102
103static enum ib_wc_opcode get_umr_comp(struct mlx5_ib_wq *wq, int idx)
104{
105 switch (wq->wr_data[idx]) {
106 case MLX5_IB_WR_UMR:
107 return 0;
108
109 case IB_WR_LOCAL_INV:
110 return IB_WC_LOCAL_INV;
111
8a187ee5
SG		 112 case IB_WR_REG_MR:
113 return IB_WC_REG_MR;
114
e126ba97
EC		 115 default:
116 pr_warn("unknown completion status\n");
117 return 0;
118 }
119}
120
121static void handle_good_req(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
122 struct mlx5_ib_wq *wq, int idx)
123{
124 wc->wc_flags = 0;
125 switch (be32_to_cpu(cqe->sop_drop_qpn) >> 24) {
126 case MLX5_OPCODE_RDMA_WRITE_IMM:
127 wc->wc_flags |= IB_WC_WITH_IMM;
128 case MLX5_OPCODE_RDMA_WRITE:
129 wc->opcode = IB_WC_RDMA_WRITE;
130 break;
131 case MLX5_OPCODE_SEND_IMM:
132 wc->wc_flags |= IB_WC_WITH_IMM;
133 case MLX5_OPCODE_SEND:
134 case MLX5_OPCODE_SEND_INVAL:
135 wc->opcode = IB_WC_SEND;
136 break;
137 case MLX5_OPCODE_RDMA_READ:
138 wc->opcode = IB_WC_RDMA_READ;
139 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
140 break;
141 case MLX5_OPCODE_ATOMIC_CS:
142 wc->opcode = IB_WC_COMP_SWAP;
143 wc->byte_len = 8;
144 break;
145 case MLX5_OPCODE_ATOMIC_FA:
146 wc->opcode = IB_WC_FETCH_ADD;
147 wc->byte_len = 8;
148 break;
149 case MLX5_OPCODE_ATOMIC_MASKED_CS:
150 wc->opcode = IB_WC_MASKED_COMP_SWAP;
151 wc->byte_len = 8;
152 break;
153 case MLX5_OPCODE_ATOMIC_MASKED_FA:
154 wc->opcode = IB_WC_MASKED_FETCH_ADD;
155 wc->byte_len = 8;
156 break;
e126ba97
EC		 157 case MLX5_OPCODE_UMR:
158 wc->opcode = get_umr_comp(wq, idx);
159 break;
160 }
161}
162
163enum {
164 MLX5_GRH_IN_BUFFER = 1,
165 MLX5_GRH_IN_CQE = 2,
166};
167
168static void handle_responder(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
169 struct mlx5_ib_qp *qp)
170{
cb34be6d 171 enum rdma_link_layer ll = rdma_port_get_link_layer(qp->ibqp.device, 1);
e126ba97
EC		 172 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
173 struct mlx5_ib_srq *srq;
174 struct mlx5_ib_wq *wq;
175 u16 wqe_ctr;
176 u8 g;
177
178 if (qp->ibqp.srq || qp->ibqp.xrcd) {
179 struct mlx5_core_srq *msrq = NULL;
180
181 if (qp->ibqp.xrcd) {
9603b61d 182 msrq = mlx5_core_get_srq(dev->mdev,
e126ba97
EC		 183 be32_to_cpu(cqe->srqn));
184 srq = to_mibsrq(msrq);
185 } else {
186 srq = to_msrq(qp->ibqp.srq);
187 }
188 if (srq) {
189 wqe_ctr = be16_to_cpu(cqe->wqe_counter);
190 wc->wr_id = srq->wrid[wqe_ctr];
191 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
192 if (msrq && atomic_dec_and_test(&msrq->refcount))
193 complete(&msrq->free);
194 }
195 } else {
196 wq = &qp->rq;
197 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
198 ++wq->tail;
199 }
200 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
201
202 switch (cqe->op_own >> 4) {
203 case MLX5_CQE_RESP_WR_IMM:
204 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
205 wc->wc_flags = IB_WC_WITH_IMM;
206 wc->ex.imm_data = cqe->imm_inval_pkey;
207 break;
208 case MLX5_CQE_RESP_SEND:
209 wc->opcode = IB_WC_RECV;
c7ce833b
ES		 210 wc->wc_flags = IB_WC_IP_CSUM_OK;
211 if (unlikely(!((cqe->hds_ip_ext & CQE_L3_OK) &&
212 (cqe->hds_ip_ext & CQE_L4_OK))))
213 wc->wc_flags = 0;
e126ba97
EC		 214 break;
215 case MLX5_CQE_RESP_SEND_IMM:
216 wc->opcode = IB_WC_RECV;
217 wc->wc_flags = IB_WC_WITH_IMM;
218 wc->ex.imm_data = cqe->imm_inval_pkey;
219 break;
220 case MLX5_CQE_RESP_SEND_INV:
221 wc->opcode = IB_WC_RECV;
222 wc->wc_flags = IB_WC_WITH_INVALIDATE;
223 wc->ex.invalidate_rkey = be32_to_cpu(cqe->imm_inval_pkey);
224 break;
225 }
226 wc->slid = be16_to_cpu(cqe->slid);
227 wc->sl = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0xf;
228 wc->src_qp = be32_to_cpu(cqe->flags_rqpn) & 0xffffff;
229 wc->dlid_path_bits = cqe->ml_path;
230 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
231 wc->wc_flags |= g ? IB_WC_GRH : 0;
b636401f
SG		 232 if (unlikely(is_qp1(qp->ibqp.qp_type))) {
233 u16 pkey = be32_to_cpu(cqe->imm_inval_pkey) & 0xffff;
234
235 ib_find_cached_pkey(&dev->ib_dev, qp->port, pkey,
236 &wc->pkey_index);
237 } else {
238 wc->pkey_index = 0;
239 }
cb34be6d
AS		 240
241 if (ll != IB_LINK_LAYER_ETHERNET)
242 return;
243
244 switch (wc->sl & 0x3) {
245 case MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH:
246 wc->network_hdr_type = RDMA_NETWORK_IB;
247 break;
248 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6:
249 wc->network_hdr_type = RDMA_NETWORK_IPV6;
250 break;
251 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4:
252 wc->network_hdr_type = RDMA_NETWORK_IPV4;
253 break;
254 }
255 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
e126ba97
EC		 256}
257
258static void dump_cqe(struct mlx5_ib_dev *dev, struct mlx5_err_cqe *cqe)
259{
260 __be32 *p = (__be32 *)cqe;
261 int i;
262
263 mlx5_ib_warn(dev, "dump error cqe\n");
264 for (i = 0; i < sizeof(*cqe) / 16; i++, p += 4)
265 pr_info("%08x %08x %08x %08x\n", be32_to_cpu(p[0]),
266 be32_to_cpu(p[1]), be32_to_cpu(p[2]),
267 be32_to_cpu(p[3]));
268}
269
270static void mlx5_handle_error_cqe(struct mlx5_ib_dev *dev,
271 struct mlx5_err_cqe *cqe,
272 struct ib_wc *wc)
273{
274 int dump = 1;
275
276 switch (cqe->syndrome) {
277 case MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR:
278 wc->status = IB_WC_LOC_LEN_ERR;
279 break;
280 case MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR:
281 wc->status = IB_WC_LOC_QP_OP_ERR;
282 break;
283 case MLX5_CQE_SYNDROME_LOCAL_PROT_ERR:
284 wc->status = IB_WC_LOC_PROT_ERR;
285 break;
286 case MLX5_CQE_SYNDROME_WR_FLUSH_ERR:
287 dump = 0;
288 wc->status = IB_WC_WR_FLUSH_ERR;
289 break;
290 case MLX5_CQE_SYNDROME_MW_BIND_ERR:
291 wc->status = IB_WC_MW_BIND_ERR;
292 break;
293 case MLX5_CQE_SYNDROME_BAD_RESP_ERR:
294 wc->status = IB_WC_BAD_RESP_ERR;
295 break;
296 case MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR:
297 wc->status = IB_WC_LOC_ACCESS_ERR;
298 break;
299 case MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
300 wc->status = IB_WC_REM_INV_REQ_ERR;
301 break;
302 case MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR:
303 wc->status = IB_WC_REM_ACCESS_ERR;
304 break;
305 case MLX5_CQE_SYNDROME_REMOTE_OP_ERR:
306 wc->status = IB_WC_REM_OP_ERR;
307 break;
308 case MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
309 wc->status = IB_WC_RETRY_EXC_ERR;
310 dump = 0;
311 break;
312 case MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
313 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
314 dump = 0;
315 break;
316 case MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR:
317 wc->status = IB_WC_REM_ABORT_ERR;
318 break;
319 default:
320 wc->status = IB_WC_GENERAL_ERR;
321 break;
322 }
323
324 wc->vendor_err = cqe->vendor_err_synd;
325 if (dump)
326 dump_cqe(dev, cqe);
327}
328
329static int is_atomic_response(struct mlx5_ib_qp *qp, uint16_t idx)
330{
331 /* TBD: waiting decision
332 */
333 return 0;
334}
335
336static void *mlx5_get_atomic_laddr(struct mlx5_ib_qp *qp, uint16_t idx)
337{
338 struct mlx5_wqe_data_seg *dpseg;
339 void *addr;
340
341 dpseg = mlx5_get_send_wqe(qp, idx) + sizeof(struct mlx5_wqe_ctrl_seg) +
342 sizeof(struct mlx5_wqe_raddr_seg) +
343 sizeof(struct mlx5_wqe_atomic_seg);
344 addr = (void *)(unsigned long)be64_to_cpu(dpseg->addr);
345 return addr;
346}
347
348static void handle_atomic(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
349 uint16_t idx)
350{
351 void *addr;
352 int byte_count;
353 int i;
354
355 if (!is_atomic_response(qp, idx))
356 return;
357
358 byte_count = be32_to_cpu(cqe64->byte_cnt);
359 addr = mlx5_get_atomic_laddr(qp, idx);
360
361 if (byte_count == 4) {
362 *(uint32_t *)addr = be32_to_cpu(*((__be32 *)addr));
363 } else {
364 for (i = 0; i < byte_count; i += 8) {
365 *(uint64_t *)addr = be64_to_cpu(*((__be64 *)addr));
366 addr += 8;
367 }
368 }
369
370 return;
371}
372
373static void handle_atomics(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
374 u16 tail, u16 head)
375{
f241e749 376 u16 idx;
e126ba97
EC		 377
378 do {
379 idx = tail & (qp->sq.wqe_cnt - 1);
380 handle_atomic(qp, cqe64, idx);
381 if (idx == head)
382 break;
383
384 tail = qp->sq.w_list[idx].next;
385 } while (1);
386 tail = qp->sq.w_list[idx].next;
387 qp->sq.last_poll = tail;
388}
389
bde51583
EC		 390static void free_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf)
391{
9603b61d 392 mlx5_buf_free(dev->mdev, &buf->buf);
bde51583
EC		 393}
394
d5436ba0
SG		 395static void get_sig_err_item(struct mlx5_sig_err_cqe *cqe,
396 struct ib_sig_err *item)
397{
398 u16 syndrome = be16_to_cpu(cqe->syndrome);
399
400#define GUARD_ERR (1 << 13)
401#define APPTAG_ERR (1 << 12)
402#define REFTAG_ERR (1 << 11)
403
404 if (syndrome & GUARD_ERR) {
405 item->err_type = IB_SIG_BAD_GUARD;
406 item->expected = be32_to_cpu(cqe->expected_trans_sig) >> 16;
407 item->actual = be32_to_cpu(cqe->actual_trans_sig) >> 16;
408 } else
409 if (syndrome & REFTAG_ERR) {
410 item->err_type = IB_SIG_BAD_REFTAG;
411 item->expected = be32_to_cpu(cqe->expected_reftag);
412 item->actual = be32_to_cpu(cqe->actual_reftag);
413 } else
414 if (syndrome & APPTAG_ERR) {
415 item->err_type = IB_SIG_BAD_APPTAG;
416 item->expected = be32_to_cpu(cqe->expected_trans_sig) & 0xffff;
417 item->actual = be32_to_cpu(cqe->actual_trans_sig) & 0xffff;
418 } else {
419 pr_err("Got signature completion error with bad syndrome %04x\n",
420 syndrome);
421 }
422
423 item->sig_err_offset = be64_to_cpu(cqe->err_offset);
424 item->key = be32_to_cpu(cqe->mkey);
425}
426
89ea94a7
MG		 427static void sw_send_comp(struct mlx5_ib_qp *qp, int num_entries,
428 struct ib_wc *wc, int *npolled)
429{
430 struct mlx5_ib_wq *wq;
431 unsigned int cur;
432 unsigned int idx;
433 int np;
434 int i;
435
436 wq = &qp->sq;
437 cur = wq->head - wq->tail;
438 np = *npolled;
439
440 if (cur == 0)
441 return;
442
443 for (i = 0; i < cur && np < num_entries; i++) {
444 idx = wq->last_poll & (wq->wqe_cnt - 1);
445 wc->wr_id = wq->wrid[idx];
446 wc->status = IB_WC_WR_FLUSH_ERR;
447 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
448 wq->tail++;
449 np++;
450 wc->qp = &qp->ibqp;
451 wc++;
452 wq->last_poll = wq->w_list[idx].next;
453 }
454 *npolled = np;
455}
456
457static void sw_recv_comp(struct mlx5_ib_qp *qp, int num_entries,
458 struct ib_wc *wc, int *npolled)
459{
460 struct mlx5_ib_wq *wq;
461 unsigned int cur;
462 int np;
463 int i;
464
465 wq = &qp->rq;
466 cur = wq->head - wq->tail;
467 np = *npolled;
468
469 if (cur == 0)
470 return;
471
472 for (i = 0; i < cur && np < num_entries; i++) {
473 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
474 wc->status = IB_WC_WR_FLUSH_ERR;
475 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
476 wq->tail++;
477 np++;
478 wc->qp = &qp->ibqp;
479 wc++;
480 }
481 *npolled = np;
482}
483
484static void mlx5_ib_poll_sw_comp(struct mlx5_ib_cq *cq, int num_entries,
485 struct ib_wc *wc, int *npolled)
486{
487 struct mlx5_ib_qp *qp;
488
489 *npolled = 0;
490 /* Find uncompleted WQEs belonging to that cq and retrun mmics ones */
491 list_for_each_entry(qp, &cq->list_send_qp, cq_send_list) {
492 sw_send_comp(qp, num_entries, wc + *npolled, npolled);
493 if (*npolled >= num_entries)
494 return;
495 }
496
497 list_for_each_entry(qp, &cq->list_recv_qp, cq_recv_list) {
498 sw_recv_comp(qp, num_entries, wc + *npolled, npolled);
499 if (*npolled >= num_entries)
500 return;
501 }
502}
503
e126ba97
EC		 504static int mlx5_poll_one(struct mlx5_ib_cq *cq,
505 struct mlx5_ib_qp **cur_qp,
506 struct ib_wc *wc)
507{
508 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
509 struct mlx5_err_cqe *err_cqe;
510 struct mlx5_cqe64 *cqe64;
511 struct mlx5_core_qp *mqp;
512 struct mlx5_ib_wq *wq;
d5436ba0 513 struct mlx5_sig_err_cqe *sig_err_cqe;
a606b0f6 514 struct mlx5_core_mkey *mmkey;
d5436ba0 515 struct mlx5_ib_mr *mr;
e126ba97
EC		 516 uint8_t opcode;
517 uint32_t qpn;
518 u16 wqe_ctr;
519 void *cqe;
520 int idx;
521
bde51583 522repoll:
e126ba97
EC		 523 cqe = next_cqe_sw(cq);
524 if (!cqe)
525 return -EAGAIN;
526
527 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
528
529 ++cq->mcq.cons_index;
530
531 /* Make sure we read CQ entry contents after we've checked the
532 * ownership bit.
533 */
534 rmb();
535
bde51583
EC		 536 opcode = cqe64->op_own >> 4;
537 if (unlikely(opcode == MLX5_CQE_RESIZE_CQ)) {
538 if (likely(cq->resize_buf)) {
539 free_cq_buf(dev, &cq->buf);
540 cq->buf = *cq->resize_buf;
541 kfree(cq->resize_buf);
542 cq->resize_buf = NULL;
543 goto repoll;
544 } else {
545 mlx5_ib_warn(dev, "unexpected resize cqe\n");
546 }
547 }
e126ba97
EC		 548
549 qpn = ntohl(cqe64->sop_drop_qpn) & 0xffffff;
550 if (!*cur_qp || (qpn != (*cur_qp)->ibqp.qp_num)) {
551 /* We do not have to take the QP table lock here,
552 * because CQs will be locked while QPs are removed
553 * from the table.
554 */
9603b61d 555 mqp = __mlx5_qp_lookup(dev->mdev, qpn);
e126ba97
EC		 556 *cur_qp = to_mibqp(mqp);
557 }
558
559 wc->qp = &(*cur_qp)->ibqp;
e126ba97
EC		 560 switch (opcode) {
561 case MLX5_CQE_REQ:
562 wq = &(*cur_qp)->sq;
563 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
564 idx = wqe_ctr & (wq->wqe_cnt - 1);
565 handle_good_req(wc, cqe64, wq, idx);
566 handle_atomics(*cur_qp, cqe64, wq->last_poll, idx);
567 wc->wr_id = wq->wrid[idx];
568 wq->tail = wq->wqe_head[idx] + 1;
569 wc->status = IB_WC_SUCCESS;
570 break;
571 case MLX5_CQE_RESP_WR_IMM:
572 case MLX5_CQE_RESP_SEND:
573 case MLX5_CQE_RESP_SEND_IMM:
574 case MLX5_CQE_RESP_SEND_INV:
575 handle_responder(wc, cqe64, *cur_qp);
576 wc->status = IB_WC_SUCCESS;
577 break;
578 case MLX5_CQE_RESIZE_CQ:
579 break;
580 case MLX5_CQE_REQ_ERR:
581 case MLX5_CQE_RESP_ERR:
582 err_cqe = (struct mlx5_err_cqe *)cqe64;
583 mlx5_handle_error_cqe(dev, err_cqe, wc);
584 mlx5_ib_dbg(dev, "%s error cqe on cqn 0x%x:\n",
585 opcode == MLX5_CQE_REQ_ERR ?
586 "Requestor" : "Responder", cq->mcq.cqn);
587 mlx5_ib_dbg(dev, "syndrome 0x%x, vendor syndrome 0x%x\n",
588 err_cqe->syndrome, err_cqe->vendor_err_synd);
589 if (opcode == MLX5_CQE_REQ_ERR) {
590 wq = &(*cur_qp)->sq;
591 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
592 idx = wqe_ctr & (wq->wqe_cnt - 1);
593 wc->wr_id = wq->wrid[idx];
594 wq->tail = wq->wqe_head[idx] + 1;
595 } else {
596 struct mlx5_ib_srq *srq;
597
598 if ((*cur_qp)->ibqp.srq) {
599 srq = to_msrq((*cur_qp)->ibqp.srq);
600 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
601 wc->wr_id = srq->wrid[wqe_ctr];
602 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
603 } else {
604 wq = &(*cur_qp)->rq;
605 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
606 ++wq->tail;
607 }
608 }
609 break;
d5436ba0
SG		 610 case MLX5_CQE_SIG_ERR:
611 sig_err_cqe = (struct mlx5_sig_err_cqe *)cqe64;
612
a606b0f6
MB		 613 read_lock(&dev->mdev->priv.mkey_table.lock);
614 mmkey = __mlx5_mr_lookup(dev->mdev,
615 mlx5_base_mkey(be32_to_cpu(sig_err_cqe->mkey)));
a606b0f6 616 mr = to_mibmr(mmkey);
d5436ba0
SG		 617 get_sig_err_item(sig_err_cqe, &mr->sig->err_item);
618 mr->sig->sig_err_exists = true;
619 mr->sig->sigerr_count++;
620
621 mlx5_ib_warn(dev, "CQN: 0x%x Got SIGERR on key: 0x%x err_type %x err_offset %llx expected %x actual %x\n",
622 cq->mcq.cqn, mr->sig->err_item.key,
623 mr->sig->err_item.err_type,
624 mr->sig->err_item.sig_err_offset,
625 mr->sig->err_item.expected,
626 mr->sig->err_item.actual);
627
a606b0f6 628 read_unlock(&dev->mdev->priv.mkey_table.lock);
d5436ba0 629 goto repoll;
e126ba97
EC		 630 }
631
632 return 0;
633}
634
25361e02
HE		 635static int poll_soft_wc(struct mlx5_ib_cq *cq, int num_entries,
636 struct ib_wc *wc)
637{
638 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
639 struct mlx5_ib_wc *soft_wc, *next;
640 int npolled = 0;
641
642 list_for_each_entry_safe(soft_wc, next, &cq->wc_list, list) {
643 if (npolled >= num_entries)
644 break;
645
646 mlx5_ib_dbg(dev, "polled software generated completion on CQ 0x%x\n",
647 cq->mcq.cqn);
648
649 wc[npolled++] = soft_wc->wc;
650 list_del(&soft_wc->list);
651 kfree(soft_wc);
652 }
653
654 return npolled;
655}
656
e126ba97
EC		 657int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
658{
659 struct mlx5_ib_cq *cq = to_mcq(ibcq);
660 struct mlx5_ib_qp *cur_qp = NULL;
89ea94a7
MG		 661 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
662 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 663 unsigned long flags;
25361e02 664 int soft_polled = 0;
e126ba97 665 int npolled;
e126ba97
EC		 666
667 spin_lock_irqsave(&cq->lock, flags);
89ea94a7
MG		 668 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
669 mlx5_ib_poll_sw_comp(cq, num_entries, wc, &npolled);
670 goto out;
671 }
e126ba97 672
25361e02
HE		 673 if (unlikely(!list_empty(&cq->wc_list)))
674 soft_polled = poll_soft_wc(cq, num_entries, wc);
675
676 for (npolled = 0; npolled < num_entries - soft_polled; npolled++) {
dbdf7d4e 677 if (mlx5_poll_one(cq, &cur_qp, wc + soft_polled + npolled))
e126ba97
EC		 678 break;
679 }
680
681 if (npolled)
682 mlx5_cq_set_ci(&cq->mcq);
89ea94a7 683out:
e126ba97
EC		 684 spin_unlock_irqrestore(&cq->lock, flags);
685
dbdf7d4e 686 return soft_polled + npolled;
e126ba97
EC		 687}
688
689int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
690{
ce0f7509 691 struct mlx5_core_dev *mdev = to_mdev(ibcq->device)->mdev;
25361e02 692 struct mlx5_ib_cq *cq = to_mcq(ibcq);
ce0f7509 693 void __iomem *uar_page = mdev->priv.uuari.uars[0].map;
25361e02
HE		 694 unsigned long irq_flags;
695 int ret = 0;
696
697 spin_lock_irqsave(&cq->lock, irq_flags);
698 if (cq->notify_flags != IB_CQ_NEXT_COMP)
699 cq->notify_flags = flags & IB_CQ_SOLICITED_MASK;
ce0f7509 700
25361e02
HE		 701 if ((flags & IB_CQ_REPORT_MISSED_EVENTS) && !list_empty(&cq->wc_list))
702 ret = 1;
703 spin_unlock_irqrestore(&cq->lock, irq_flags);
704
705 mlx5_cq_arm(&cq->mcq,
e126ba97
EC		 706 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
707 MLX5_CQ_DB_REQ_NOT_SOL : MLX5_CQ_DB_REQ_NOT,
ce0f7509
SM		 708 uar_page,
709 MLX5_GET_DOORBELL_LOCK(&mdev->priv.cq_uar_lock),
710 to_mcq(ibcq)->mcq.cons_index);
e126ba97 711
25361e02 712 return ret;
e126ba97
EC		 713}
714
715static int alloc_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf,
716 int nent, int cqe_size)
717{
718 int err;
719
64ffaa21 720 err = mlx5_buf_alloc(dev->mdev, nent * cqe_size, &buf->buf);
e126ba97
EC		 721 if (err)
722 return err;
723
724 buf->cqe_size = cqe_size;
bde51583 725 buf->nent = nent;
e126ba97
EC		 726
727 return 0;
728}
729
e126ba97
EC		 730static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata,
731 struct ib_ucontext *context, struct mlx5_ib_cq *cq,
732 int entries, struct mlx5_create_cq_mbox_in **cqb,
733 int *cqe_size, int *index, int *inlen)
734{
735 struct mlx5_ib_create_cq ucmd;
a8237b32 736 size_t ucmdlen;
e126ba97
EC		 737 int page_shift;
738 int npages;
739 int ncont;
740 int err;
741
a8237b32
YD		 742 ucmdlen =
743 (udata->inlen - sizeof(struct ib_uverbs_cmd_hdr) <
744 sizeof(ucmd)) ? (sizeof(ucmd) -
745 sizeof(ucmd.reserved)) : sizeof(ucmd);
746
747 if (ib_copy_from_udata(&ucmd, udata, ucmdlen))
e126ba97
EC		 748 return -EFAULT;
749
a8237b32
YD		 750 if (ucmdlen == sizeof(ucmd) &&
751 ucmd.reserved != 0)
752 return -EINVAL;
753
e126ba97
EC		 754 if (ucmd.cqe_size != 64 && ucmd.cqe_size != 128)
755 return -EINVAL;
756
757 *cqe_size = ucmd.cqe_size;
758
759 cq->buf.umem = ib_umem_get(context, ucmd.buf_addr,
760 entries * ucmd.cqe_size,
761 IB_ACCESS_LOCAL_WRITE, 1);
762 if (IS_ERR(cq->buf.umem)) {
763 err = PTR_ERR(cq->buf.umem);
764 return err;
765 }
766
767 err = mlx5_ib_db_map_user(to_mucontext(context), ucmd.db_addr,
768 &cq->db);
769 if (err)
770 goto err_umem;
771
772 mlx5_ib_cont_pages(cq->buf.umem, ucmd.buf_addr, &npages, &page_shift,
773 &ncont, NULL);
774 mlx5_ib_dbg(dev, "addr 0x%llx, size %u, npages %d, page_shift %d, ncont %d\n",
775 ucmd.buf_addr, entries * ucmd.cqe_size, npages, page_shift, ncont);
776
777 *inlen = sizeof(**cqb) + sizeof(*(*cqb)->pas) * ncont;
778 *cqb = mlx5_vzalloc(*inlen);
779 if (!*cqb) {
780 err = -ENOMEM;
781 goto err_db;
782 }
783 mlx5_ib_populate_pas(dev, cq->buf.umem, page_shift, (*cqb)->pas, 0);
cf1c5e1f 784 (*cqb)->ctx.log_pg_sz = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
e126ba97
EC		 785
786 *index = to_mucontext(context)->uuari.uars[0].index;
787
788 return 0;
789
790err_db:
791 mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db);
792
793err_umem:
794 ib_umem_release(cq->buf.umem);
795 return err;
796}
797
798static void destroy_cq_user(struct mlx5_ib_cq *cq, struct ib_ucontext *context)
799{
800 mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db);
801 ib_umem_release(cq->buf.umem);
802}
803
bde51583 804static void init_cq_buf(struct mlx5_ib_cq *cq, struct mlx5_ib_cq_buf *buf)
e126ba97
EC		 805{
806 int i;
807 void *cqe;
808 struct mlx5_cqe64 *cqe64;
809
bde51583
EC		 810 for (i = 0; i < buf->nent; i++) {
811 cqe = get_cqe_from_buf(buf, i, buf->cqe_size);
812 cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64;
813 cqe64->op_own = MLX5_CQE_INVALID << 4;
e126ba97
EC		 814 }
815}
816
817static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
818 int entries, int cqe_size,
819 struct mlx5_create_cq_mbox_in **cqb,
820 int *index, int *inlen)
821{
822 int err;
823
9603b61d 824 err = mlx5_db_alloc(dev->mdev, &cq->db);
e126ba97
EC		 825 if (err)
826 return err;
827
828 cq->mcq.set_ci_db = cq->db.db;
829 cq->mcq.arm_db = cq->db.db + 1;
e126ba97
EC		 830 cq->mcq.cqe_sz = cqe_size;
831
832 err = alloc_cq_buf(dev, &cq->buf, entries, cqe_size);
833 if (err)
834 goto err_db;
835
bde51583 836 init_cq_buf(cq, &cq->buf);
e126ba97
EC		 837
838 *inlen = sizeof(**cqb) + sizeof(*(*cqb)->pas) * cq->buf.buf.npages;
839 *cqb = mlx5_vzalloc(*inlen);
840 if (!*cqb) {
841 err = -ENOMEM;
842 goto err_buf;
843 }
844 mlx5_fill_page_array(&cq->buf.buf, (*cqb)->pas);
845
1b77d2bd 846 (*cqb)->ctx.log_pg_sz = cq->buf.buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT;
9603b61d 847 *index = dev->mdev->priv.uuari.uars[0].index;
e126ba97
EC		 848
849 return 0;
850
851err_buf:
852 free_cq_buf(dev, &cq->buf);
853
854err_db:
9603b61d 855 mlx5_db_free(dev->mdev, &cq->db);
e126ba97
EC		 856 return err;
857}
858
859static void destroy_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
860{
861 free_cq_buf(dev, &cq->buf);
9603b61d 862 mlx5_db_free(dev->mdev, &cq->db);
e126ba97
EC		 863}
864
25361e02
HE		 865static void notify_soft_wc_handler(struct work_struct *work)
866{
867 struct mlx5_ib_cq *cq = container_of(work, struct mlx5_ib_cq,
868 notify_work);
869
870 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
871}
872
bcf4c1ea
MB		 873struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev,
874 const struct ib_cq_init_attr *attr,
875 struct ib_ucontext *context,
e126ba97
EC		 876 struct ib_udata *udata)
877{
bcf4c1ea
MB		 878 int entries = attr->cqe;
879 int vector = attr->comp_vector;
e126ba97
EC		 880 struct mlx5_create_cq_mbox_in *cqb = NULL;
881 struct mlx5_ib_dev *dev = to_mdev(ibdev);
882 struct mlx5_ib_cq *cq;
883 int uninitialized_var(index);
884 int uninitialized_var(inlen);
885 int cqe_size;
0b6e26ce 886 unsigned int irqn;
e126ba97
EC		 887 int eqn;
888 int err;
889
9ea57852
NO		 890 if (entries < 0 ||
891 (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))))
51ee86a4
EC		 892 return ERR_PTR(-EINVAL);
893
34356f64 894 if (check_cq_create_flags(attr->flags))
972ecb82
MB		 895 return ERR_PTR(-EOPNOTSUPP);
896
e126ba97 897 entries = roundup_pow_of_two(entries + 1);
938fe83c 898 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)))
e126ba97
EC		 899 return ERR_PTR(-EINVAL);
900
901 cq = kzalloc(sizeof(*cq), GFP_KERNEL);
902 if (!cq)
903 return ERR_PTR(-ENOMEM);
904
905 cq->ibcq.cqe = entries - 1;
906 mutex_init(&cq->resize_mutex);
907 spin_lock_init(&cq->lock);
908 cq->resize_buf = NULL;
909 cq->resize_umem = NULL;
051f2630 910 cq->create_flags = attr->flags;
89ea94a7
MG		 911 INIT_LIST_HEAD(&cq->list_send_qp);
912 INIT_LIST_HEAD(&cq->list_recv_qp);
e126ba97
EC		 913
914 if (context) {
915 err = create_cq_user(dev, udata, context, cq, entries,
916 &cqb, &cqe_size, &index, &inlen);
917 if (err)
918 goto err_create;
919 } else {
920 /* for now choose 64 bytes till we have a proper interface */
921 cqe_size = 64;
922 err = create_cq_kernel(dev, cq, entries, cqe_size, &cqb,
923 &index, &inlen);
924 if (err)
925 goto err_create;
25361e02
HE		 926
927 INIT_WORK(&cq->notify_work, notify_soft_wc_handler);
e126ba97
EC		 928 }
929
930 cq->cqe_size = cqe_size;
931 cqb->ctx.cqe_sz_flags = cqe_sz_to_mlx_sz(cqe_size) << 5;
051f2630
LR		 932
933 if (cq->create_flags & IB_CQ_FLAGS_IGNORE_OVERRUN)
934 cqb->ctx.cqe_sz_flags |= (1 << 1);
935
e126ba97 936 cqb->ctx.log_sz_usr_page = cpu_to_be32((ilog2(entries) << 24) | index);
233d05d2 937 err = mlx5_vector2eqn(dev->mdev, vector, &eqn, &irqn);
e126ba97
EC		 938 if (err)
939 goto err_cqb;
940
941 cqb->ctx.c_eqn = cpu_to_be16(eqn);
942 cqb->ctx.db_record_addr = cpu_to_be64(cq->db.dma);
943
9603b61d 944 err = mlx5_core_create_cq(dev->mdev, &cq->mcq, cqb, inlen);
e126ba97
EC		 945 if (err)
946 goto err_cqb;
947
948 mlx5_ib_dbg(dev, "cqn 0x%x\n", cq->mcq.cqn);
949 cq->mcq.irqn = irqn;
c16d2750
MB		 950 if (context)
951 cq->mcq.tasklet_ctx.comp = mlx5_ib_cq_comp;
952 else
953 cq->mcq.comp = mlx5_ib_cq_comp;
e126ba97
EC		 954 cq->mcq.event = mlx5_ib_cq_event;
955
25361e02
HE		 956 INIT_LIST_HEAD(&cq->wc_list);
957
e126ba97
EC		 958 if (context)
959 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof(__u32))) {
960 err = -EFAULT;
961 goto err_cmd;
962 }
963
964
479163f4 965 kvfree(cqb);
e126ba97
EC		 966 return &cq->ibcq;
967
968err_cmd:
9603b61d 969 mlx5_core_destroy_cq(dev->mdev, &cq->mcq);
e126ba97
EC		 970
971err_cqb:
479163f4 972 kvfree(cqb);
e126ba97
EC		 973 if (context)
974 destroy_cq_user(cq, context);
975 else
976 destroy_cq_kernel(dev, cq);
977
978err_create:
979 kfree(cq);
980
981 return ERR_PTR(err);
982}
983
984
985int mlx5_ib_destroy_cq(struct ib_cq *cq)
986{
987 struct mlx5_ib_dev *dev = to_mdev(cq->device);
988 struct mlx5_ib_cq *mcq = to_mcq(cq);
989 struct ib_ucontext *context = NULL;
990
991 if (cq->uobject)
992 context = cq->uobject->context;
993
9603b61d 994 mlx5_core_destroy_cq(dev->mdev, &mcq->mcq);
e126ba97
EC		 995 if (context)
996 destroy_cq_user(mcq, context);
997 else
998 destroy_cq_kernel(dev, mcq);
999
1000 kfree(mcq);
1001
1002 return 0;
1003}
1004
cfd8f1d4 1005static int is_equal_rsn(struct mlx5_cqe64 *cqe64, u32 rsn)
e126ba97 1006{
cfd8f1d4 1007 return rsn == (ntohl(cqe64->sop_drop_qpn) & 0xffffff);
e126ba97
EC		 1008}
1009
1010void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 rsn, struct mlx5_ib_srq *srq)
1011{
1012 struct mlx5_cqe64 *cqe64, *dest64;
1013 void *cqe, *dest;
1014 u32 prod_index;
1015 int nfreed = 0;
1016 u8 owner_bit;
1017
1018 if (!cq)
1019 return;
1020
1021 /* First we need to find the current producer index, so we
1022 * know where to start cleaning from. It doesn't matter if HW
1023 * adds new entries after this loop -- the QP we're worried
1024 * about is already in RESET, so the new entries won't come
1025 * from our QP and therefore don't need to be checked.
1026 */
1027 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); prod_index++)
1028 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
1029 break;
1030
1031 /* Now sweep backwards through the CQ, removing CQ entries
1032 * that match our QP by copying older entries on top of them.
1033 */
1034 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
1035 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
1036 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
cfd8f1d4
ML		 1037 if (is_equal_rsn(cqe64, rsn)) {
1038 if (srq && (ntohl(cqe64->srqn) & 0xffffff))
e126ba97
EC		 1039 mlx5_ib_free_srq_wqe(srq, be16_to_cpu(cqe64->wqe_counter));
1040 ++nfreed;
1041 } else if (nfreed) {
1042 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
1043 dest64 = (cq->mcq.cqe_sz == 64) ? dest : dest + 64;
1044 owner_bit = dest64->op_own & MLX5_CQE_OWNER_MASK;
1045 memcpy(dest, cqe, cq->mcq.cqe_sz);
1046 dest64->op_own = owner_bit |
1047 (dest64->op_own & ~MLX5_CQE_OWNER_MASK);
1048 }
1049 }
1050
1051 if (nfreed) {
1052 cq->mcq.cons_index += nfreed;
1053 /* Make sure update of buffer contents is done before
1054 * updating consumer index.
1055 */
1056 wmb();
1057 mlx5_cq_set_ci(&cq->mcq);
1058 }
1059}
1060
1061void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq)
1062{
1063 if (!cq)
1064 return;
1065
1066 spin_lock_irq(&cq->lock);
1067 __mlx5_ib_cq_clean(cq, qpn, srq);
1068 spin_unlock_irq(&cq->lock);
1069}
1070
1071int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
1072{
3bdb31f6
EC		 1073 struct mlx5_modify_cq_mbox_in *in;
1074 struct mlx5_ib_dev *dev = to_mdev(cq->device);
1075 struct mlx5_ib_cq *mcq = to_mcq(cq);
1076 int err;
1077 u32 fsel;
1078
938fe83c 1079 if (!MLX5_CAP_GEN(dev->mdev, cq_moderation))
3bdb31f6
EC		 1080 return -ENOSYS;
1081
1082 in = kzalloc(sizeof(*in), GFP_KERNEL);
1083 if (!in)
1084 return -ENOMEM;
1085
1086 in->cqn = cpu_to_be32(mcq->mcq.cqn);
1087 fsel = (MLX5_CQ_MODIFY_PERIOD | MLX5_CQ_MODIFY_COUNT);
1088 in->ctx.cq_period = cpu_to_be16(cq_period);
1089 in->ctx.cq_max_count = cpu_to_be16(cq_count);
1090 in->field_select = cpu_to_be32(fsel);
9603b61d 1091 err = mlx5_core_modify_cq(dev->mdev, &mcq->mcq, in, sizeof(*in));
3bdb31f6
EC		 1092 kfree(in);
1093
1094 if (err)
1095 mlx5_ib_warn(dev, "modify cq 0x%x failed\n", mcq->mcq.cqn);
1096
1097 return err;
e126ba97
EC		 1098}
1099
bde51583
EC		 1100static int resize_user(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1101 int entries, struct ib_udata *udata, int *npas,
1102 int *page_shift, int *cqe_size)
1103{
1104 struct mlx5_ib_resize_cq ucmd;
1105 struct ib_umem *umem;
1106 int err;
1107 int npages;
1108 struct ib_ucontext *context = cq->buf.umem->context;
1109
57761d8d
EC		 1110 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
1111 if (err)
1112 return err;
1113
1114 if (ucmd.reserved0 || ucmd.reserved1)
1115 return -EINVAL;
bde51583
EC		 1116
1117 umem = ib_umem_get(context, ucmd.buf_addr, entries * ucmd.cqe_size,
1118 IB_ACCESS_LOCAL_WRITE, 1);
1119 if (IS_ERR(umem)) {
1120 err = PTR_ERR(umem);
1121 return err;
1122 }
1123
1124 mlx5_ib_cont_pages(umem, ucmd.buf_addr, &npages, page_shift,
1125 npas, NULL);
1126
1127 cq->resize_umem = umem;
1128 *cqe_size = ucmd.cqe_size;
1129
1130 return 0;
1131}
1132
1133static void un_resize_user(struct mlx5_ib_cq *cq)
1134{
1135 ib_umem_release(cq->resize_umem);
1136}
1137
1138static int resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1139 int entries, int cqe_size)
1140{
1141 int err;
1142
1143 cq->resize_buf = kzalloc(sizeof(*cq->resize_buf), GFP_KERNEL);
1144 if (!cq->resize_buf)
1145 return -ENOMEM;
1146
1147 err = alloc_cq_buf(dev, cq->resize_buf, entries, cqe_size);
1148 if (err)
1149 goto ex;
1150
1151 init_cq_buf(cq, cq->resize_buf);
1152
1153 return 0;
1154
1155ex:
1156 kfree(cq->resize_buf);
1157 return err;
1158}
1159
1160static void un_resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
1161{
1162 free_cq_buf(dev, cq->resize_buf);
1163 cq->resize_buf = NULL;
1164}
1165
1166static int copy_resize_cqes(struct mlx5_ib_cq *cq)
1167{
1168 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
1169 struct mlx5_cqe64 *scqe64;
1170 struct mlx5_cqe64 *dcqe64;
1171 void *start_cqe;
1172 void *scqe;
1173 void *dcqe;
1174 int ssize;
1175 int dsize;
1176 int i;
1177 u8 sw_own;
1178
1179 ssize = cq->buf.cqe_size;
1180 dsize = cq->resize_buf->cqe_size;
1181 if (ssize != dsize) {
1182 mlx5_ib_warn(dev, "resize from different cqe size is not supported\n");
1183 return -EINVAL;
1184 }
1185
1186 i = cq->mcq.cons_index;
1187 scqe = get_sw_cqe(cq, i);
1188 scqe64 = ssize == 64 ? scqe : scqe + 64;
1189 start_cqe = scqe;
1190 if (!scqe) {
1191 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1192 return -EINVAL;
1193 }
1194
1195 while ((scqe64->op_own >> 4) != MLX5_CQE_RESIZE_CQ) {
1196 dcqe = get_cqe_from_buf(cq->resize_buf,
1197 (i + 1) & (cq->resize_buf->nent),
1198 dsize);
1199 dcqe64 = dsize == 64 ? dcqe : dcqe + 64;
1200 sw_own = sw_ownership_bit(i + 1, cq->resize_buf->nent);
1201 memcpy(dcqe, scqe, dsize);
1202 dcqe64->op_own = (dcqe64->op_own & ~MLX5_CQE_OWNER_MASK) | sw_own;
1203
1204 ++i;
1205 scqe = get_sw_cqe(cq, i);
1206 scqe64 = ssize == 64 ? scqe : scqe + 64;
1207 if (!scqe) {
1208 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1209 return -EINVAL;
1210 }
1211
1212 if (scqe == start_cqe) {
1213 pr_warn("resize CQ failed to get resize CQE, CQN 0x%x\n",
1214 cq->mcq.cqn);
1215 return -ENOMEM;
1216 }
1217 }
1218 ++cq->mcq.cons_index;
1219 return 0;
1220}
1221
e126ba97
EC		 1222int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
1223{
bde51583
EC		 1224 struct mlx5_ib_dev *dev = to_mdev(ibcq->device);
1225 struct mlx5_ib_cq *cq = to_mcq(ibcq);
1226 struct mlx5_modify_cq_mbox_in *in;
1227 int err;
1228 int npas;
1229 int page_shift;
1230 int inlen;
1231 int uninitialized_var(cqe_size);
1232 unsigned long flags;
1233
938fe83c 1234 if (!MLX5_CAP_GEN(dev->mdev, cq_resize)) {
bde51583
EC		 1235 pr_info("Firmware does not support resize CQ\n");
1236 return -ENOSYS;
1237 }
1238
3c4c3774
NO		 1239 if (entries < 1 ||
1240 entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) {
1241 mlx5_ib_warn(dev, "wrong entries number %d, max %d\n",
1242 entries,
1243 1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz));
bde51583 1244 return -EINVAL;
3c4c3774 1245 }
bde51583
EC		 1246
1247 entries = roundup_pow_of_two(entries + 1);
3c4c3774 1248 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)) + 1)
bde51583
EC		 1249 return -EINVAL;
1250
1251 if (entries == ibcq->cqe + 1)
1252 return 0;
1253
1254 mutex_lock(&cq->resize_mutex);
1255 if (udata) {
1256 err = resize_user(dev, cq, entries, udata, &npas, &page_shift,
1257 &cqe_size);
1258 } else {
1259 cqe_size = 64;
1260 err = resize_kernel(dev, cq, entries, cqe_size);
1261 if (!err) {
1262 npas = cq->resize_buf->buf.npages;
1263 page_shift = cq->resize_buf->buf.page_shift;
1264 }
1265 }
1266
1267 if (err)
1268 goto ex;
1269
1270 inlen = sizeof(*in) + npas * sizeof(in->pas[0]);
1271 in = mlx5_vzalloc(inlen);
1272 if (!in) {
1273 err = -ENOMEM;
1274 goto ex_resize;
1275 }
1276
1277 if (udata)
1278 mlx5_ib_populate_pas(dev, cq->resize_umem, page_shift,
1279 in->pas, 0);
1280 else
1281 mlx5_fill_page_array(&cq->resize_buf->buf, in->pas);
1282
1283 in->field_select = cpu_to_be32(MLX5_MODIFY_CQ_MASK_LOG_SIZE |
1284 MLX5_MODIFY_CQ_MASK_PG_OFFSET |
1285 MLX5_MODIFY_CQ_MASK_PG_SIZE);
1286 in->ctx.log_pg_sz = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
1287 in->ctx.cqe_sz_flags = cqe_sz_to_mlx_sz(cqe_size) << 5;
1288 in->ctx.page_offset = 0;
1289 in->ctx.log_sz_usr_page = cpu_to_be32(ilog2(entries) << 24);
1290 in->hdr.opmod = cpu_to_be16(MLX5_CQ_OPMOD_RESIZE);
1291 in->cqn = cpu_to_be32(cq->mcq.cqn);
1292
9603b61d 1293 err = mlx5_core_modify_cq(dev->mdev, &cq->mcq, in, inlen);
bde51583
EC		 1294 if (err)
1295 goto ex_alloc;
1296
1297 if (udata) {
1298 cq->ibcq.cqe = entries - 1;
1299 ib_umem_release(cq->buf.umem);
1300 cq->buf.umem = cq->resize_umem;
1301 cq->resize_umem = NULL;
1302 } else {
1303 struct mlx5_ib_cq_buf tbuf;
1304 int resized = 0;
1305
1306 spin_lock_irqsave(&cq->lock, flags);
1307 if (cq->resize_buf) {
1308 err = copy_resize_cqes(cq);
1309 if (!err) {
1310 tbuf = cq->buf;
1311 cq->buf = *cq->resize_buf;
1312 kfree(cq->resize_buf);
1313 cq->resize_buf = NULL;
1314 resized = 1;
1315 }
1316 }
1317 cq->ibcq.cqe = entries - 1;
1318 spin_unlock_irqrestore(&cq->lock, flags);
1319 if (resized)
1320 free_cq_buf(dev, &tbuf);
1321 }
1322 mutex_unlock(&cq->resize_mutex);
1323
479163f4 1324 kvfree(in);
bde51583
EC		 1325 return 0;
1326
1327ex_alloc:
479163f4 1328 kvfree(in);
bde51583
EC		 1329
1330ex_resize:
1331 if (udata)
1332 un_resize_user(cq);
1333 else
1334 un_resize_kernel(dev, cq);
1335ex:
1336 mutex_unlock(&cq->resize_mutex);
1337 return err;
e126ba97
EC		 1338}
1339
1340int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq)
1341{
1342 struct mlx5_ib_cq *cq;
1343
1344 if (!ibcq)
1345 return 128;
1346
1347 cq = to_mcq(ibcq);
1348 return cq->cqe_size;
1349}
25361e02
HE		 1350
1351/* Called from atomic context */
1352int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc)
1353{
1354 struct mlx5_ib_wc *soft_wc;
1355 struct mlx5_ib_cq *cq = to_mcq(ibcq);
1356 unsigned long flags;
1357
1358 soft_wc = kmalloc(sizeof(*soft_wc), GFP_ATOMIC);
1359 if (!soft_wc)
1360 return -ENOMEM;
1361
1362 soft_wc->wc = *wc;
1363 spin_lock_irqsave(&cq->lock, flags);
1364 list_add_tail(&soft_wc->list, &cq->wc_list);
1365 if (cq->notify_flags == IB_CQ_NEXT_COMP ||
1366 wc->status != IB_WC_SUCCESS) {
1367 cq->notify_flags = 0;
1368 schedule_work(&cq->notify_work);
1369 }
1370 spin_unlock_irqrestore(&cq->lock, flags);
1371
1372 return 0;
1373}
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