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RDMA/srp: Increase max_segment_size
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
24da0016 41#include <linux/bitmap.h>
37aa5c36
GL		 42#if defined(CONFIG_X86)
43#include <asm/pat.h>
44#endif
e126ba97 45#include <linux/sched.h>
6e84f315 46#include <linux/sched/mm.h>
0881e7bd 47#include <linux/sched/task.h>
7c2344c3 48#include <linux/delay.h>
e126ba97 49#include <rdma/ib_user_verbs.h>
3f89a643 50#include <rdma/ib_addr.h>
2811ba51 51#include <rdma/ib_cache.h>
ada68c31 52#include <linux/mlx5/port.h>
1b5daf11 53#include <linux/mlx5/vport.h>
72c7fe90 54#include <linux/mlx5/fs.h>
7c2344c3 55#include <linux/list.h>
e126ba97
EC		 56#include <rdma/ib_smi.h>
57#include <rdma/ib_umem.h>
038d2ef8
MG		 58#include <linux/in.h>
59#include <linux/etherdevice.h>
e126ba97 60#include "mlx5_ib.h"
fc385b7a 61#include "ib_rep.h"
e1f24a79 62#include "cmd.h"
f3da6577 63#include "srq.h"
3346c487 64#include <linux/mlx5/fs_helpers.h>
c6475a0b 65#include <linux/mlx5/accel.h>
8c84660b 66#include <rdma/uverbs_std_types.h>
c6475a0b
AY		 67#include <rdma/mlx5_user_ioctl_verbs.h>
68#include <rdma/mlx5_user_ioctl_cmds.h>
8c84660b
MB		 69
70#define UVERBS_MODULE_NAME mlx5_ib
71#include <rdma/uverbs_named_ioctl.h>
e126ba97
EC		 72
73#define DRIVER_NAME "mlx5_ib"
b359911d 74#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 75
76MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
77MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
78MODULE_LICENSE("Dual BSD/GPL");
e126ba97 79
e126ba97
EC		 80static char mlx5_version[] =
81 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 82 DRIVER_VERSION "\n";
e126ba97 83
d69a24e0
DJ		 84struct mlx5_ib_event_work {
85 struct work_struct work;
df097a27
SM		 86 union {
87 struct mlx5_ib_dev *dev;
88 struct mlx5_ib_multiport_info *mpi;
89 };
90 bool is_slave;
134e9349 91 unsigned int event;
df097a27 92 void *param;
d69a24e0
DJ		 93};
94
da7525d2
EBE		 95enum {
96 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
97};
98
d69a24e0 99static struct workqueue_struct *mlx5_ib_event_wq;
32f69e4b
DJ		 100static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
101static LIST_HEAD(mlx5_ib_dev_list);
102/*
103 * This mutex should be held when accessing either of the above lists
104 */
105static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
106
c44ef998
IL		 107/* We can't use an array for xlt_emergency_page because dma_map_single
108 * doesn't work on kernel modules memory
109 */
110static unsigned long xlt_emergency_page;
111static struct mutex xlt_emergency_page_mutex;
112
32f69e4b
DJ		 113struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
114{
115 struct mlx5_ib_dev *dev;
116
117 mutex_lock(&mlx5_ib_multiport_mutex);
118 dev = mpi->ibdev;
119 mutex_unlock(&mlx5_ib_multiport_mutex);
120 return dev;
121}
122
1b5daf11 123static enum rdma_link_layer
ebd61f68 124mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 125{
ebd61f68 126 switch (port_type_cap) {
1b5daf11
MD		 127 case MLX5_CAP_PORT_TYPE_IB:
128 return IB_LINK_LAYER_INFINIBAND;
129 case MLX5_CAP_PORT_TYPE_ETH:
130 return IB_LINK_LAYER_ETHERNET;
131 default:
132 return IB_LINK_LAYER_UNSPECIFIED;
133 }
134}
135
ebd61f68
AS		 136static enum rdma_link_layer
137mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
138{
139 struct mlx5_ib_dev *dev = to_mdev(device);
140 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
141
142 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
143}
144
fd65f1b8
MS		 145static int get_port_state(struct ib_device *ibdev,
146 u8 port_num,
147 enum ib_port_state *state)
148{
149 struct ib_port_attr attr;
150 int ret;
151
152 memset(&attr, 0, sizeof(attr));
3023a1e9 153 ret = ibdev->ops.query_port(ibdev, port_num, &attr);
fd65f1b8
MS		 154 if (!ret)
155 *state = attr.state;
156 return ret;
157}
158
fc24fc5e
AS		 159static int mlx5_netdev_event(struct notifier_block *this,
160 unsigned long event, void *ptr)
161{
7fd8aefb 162 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
fc24fc5e 163 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
7fd8aefb
DJ		 164 u8 port_num = roce->native_port_num;
165 struct mlx5_core_dev *mdev;
166 struct mlx5_ib_dev *ibdev;
167
168 ibdev = roce->dev;
32f69e4b
DJ		 169 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
170 if (!mdev)
171 return NOTIFY_DONE;
fc24fc5e 172
5ec8c83e
AH		 173 switch (event) {
174 case NETDEV_REGISTER:
7fd8aefb 175 write_lock(&roce->netdev_lock);
bcf87f1d
MB		 176 if (ibdev->rep) {
177 struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch;
178 struct net_device *rep_ndev;
179
180 rep_ndev = mlx5_ib_get_rep_netdev(esw,
181 ibdev->rep->vport);
182 if (rep_ndev == ndev)
842a9c83 183 roce->netdev = ndev;
84a6a7a9 184 } else if (ndev->dev.parent == &mdev->pdev->dev) {
842a9c83 185 roce->netdev = ndev;
bcf87f1d 186 }
7fd8aefb 187 write_unlock(&roce->netdev_lock);
5ec8c83e 188 break;
fc24fc5e 189
842a9c83
OG		 190 case NETDEV_UNREGISTER:
191 write_lock(&roce->netdev_lock);
192 if (roce->netdev == ndev)
193 roce->netdev = NULL;
194 write_unlock(&roce->netdev_lock);
195 break;
196
fd65f1b8 197 case NETDEV_CHANGE:
5ec8c83e 198 case NETDEV_UP:
88621dfe 199 case NETDEV_DOWN: {
7fd8aefb 200 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe
AH		 201 struct net_device *upper = NULL;
202
203 if (lag_ndev) {
204 upper = netdev_master_upper_dev_get(lag_ndev);
205 dev_put(lag_ndev);
206 }
207
7fd8aefb 208 if ((upper == ndev || (!upper && ndev == roce->netdev))
88621dfe 209 && ibdev->ib_active) {
626bc02d 210 struct ib_event ibev = { };
fd65f1b8 211 enum ib_port_state port_state;
5ec8c83e 212
7fd8aefb
DJ		 213 if (get_port_state(&ibdev->ib_dev, port_num,
214 &port_state))
215 goto done;
fd65f1b8 216
7fd8aefb
DJ		 217 if (roce->last_port_state == port_state)
218 goto done;
fd65f1b8 219
7fd8aefb 220 roce->last_port_state = port_state;
5ec8c83e 221 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 222 if (port_state == IB_PORT_DOWN)
223 ibev.event = IB_EVENT_PORT_ERR;
224 else if (port_state == IB_PORT_ACTIVE)
225 ibev.event = IB_EVENT_PORT_ACTIVE;
226 else
7fd8aefb 227 goto done;
fd65f1b8 228
7fd8aefb 229 ibev.element.port_num = port_num;
5ec8c83e
AH		 230 ib_dispatch_event(&ibev);
231 }
232 break;
88621dfe 233 }
fc24fc5e 234
5ec8c83e
AH		 235 default:
236 break;
237 }
7fd8aefb 238done:
32f69e4b 239 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 240 return NOTIFY_DONE;
241}
242
243static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
244 u8 port_num)
245{
246 struct mlx5_ib_dev *ibdev = to_mdev(device);
247 struct net_device *ndev;
32f69e4b
DJ		 248 struct mlx5_core_dev *mdev;
249
250 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
251 if (!mdev)
252 return NULL;
fc24fc5e 253
32f69e4b 254 ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe 255 if (ndev)
32f69e4b 256 goto out;
88621dfe 257
fc24fc5e
AS		 258 /* Ensure ndev does not disappear before we invoke dev_hold()
259 */
7fd8aefb
DJ		 260 read_lock(&ibdev->roce[port_num - 1].netdev_lock);
261 ndev = ibdev->roce[port_num - 1].netdev;
fc24fc5e
AS		 262 if (ndev)
263 dev_hold(ndev);
7fd8aefb 264 read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
fc24fc5e 265
32f69e4b
DJ		 266out:
267 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 268 return ndev;
269}
270
32f69e4b
DJ		 271struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
272 u8 ib_port_num,
273 u8 *native_port_num)
274{
275 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
276 ib_port_num);
277 struct mlx5_core_dev *mdev = NULL;
278 struct mlx5_ib_multiport_info *mpi;
279 struct mlx5_ib_port *port;
280
210b1f78
MB		 281 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
282 ll != IB_LINK_LAYER_ETHERNET) {
283 if (native_port_num)
284 *native_port_num = ib_port_num;
285 return ibdev->mdev;
286 }
287
32f69e4b
DJ		 288 if (native_port_num)
289 *native_port_num = 1;
290
32f69e4b
DJ		 291 port = &ibdev->port[ib_port_num - 1];
292 if (!port)
293 return NULL;
294
295 spin_lock(&port->mp.mpi_lock);
296 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
297 if (mpi && !mpi->unaffiliate) {
298 mdev = mpi->mdev;
299 /* If it's the master no need to refcount, it'll exist
300 * as long as the ib_dev exists.
301 */
302 if (!mpi->is_master)
303 mpi->mdev_refcnt++;
304 }
305 spin_unlock(&port->mp.mpi_lock);
306
307 return mdev;
308}
309
310void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
311{
312 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
313 port_num);
314 struct mlx5_ib_multiport_info *mpi;
315 struct mlx5_ib_port *port;
316
317 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
318 return;
319
320 port = &ibdev->port[port_num - 1];
321
322 spin_lock(&port->mp.mpi_lock);
323 mpi = ibdev->port[port_num - 1].mp.mpi;
324 if (mpi->is_master)
325 goto out;
326
327 mpi->mdev_refcnt--;
328 if (mpi->unaffiliate)
329 complete(&mpi->unref_comp);
330out:
331 spin_unlock(&port->mp.mpi_lock);
332}
333
f1b65df5
NO		 334static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
335 u8 *active_width)
336{
337 switch (eth_proto_oper) {
338 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
339 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
340 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
341 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
342 *active_width = IB_WIDTH_1X;
343 *active_speed = IB_SPEED_SDR;
344 break;
345 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
346 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
347 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
348 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
349 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
350 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
351 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
352 *active_width = IB_WIDTH_1X;
353 *active_speed = IB_SPEED_QDR;
354 break;
355 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
356 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
357 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
358 *active_width = IB_WIDTH_1X;
359 *active_speed = IB_SPEED_EDR;
360 break;
361 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
362 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
363 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
364 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
365 *active_width = IB_WIDTH_4X;
366 *active_speed = IB_SPEED_QDR;
367 break;
368 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
369 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
370 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
371 *active_width = IB_WIDTH_1X;
372 *active_speed = IB_SPEED_HDR;
373 break;
374 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
375 *active_width = IB_WIDTH_4X;
376 *active_speed = IB_SPEED_FDR;
377 break;
378 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
379 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
380 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
381 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
382 *active_width = IB_WIDTH_4X;
383 *active_speed = IB_SPEED_EDR;
384 break;
385 default:
386 return -EINVAL;
387 }
388
389 return 0;
390}
391
095b0927
IT		 392static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
393 struct ib_port_attr *props)
3f89a643
AS		 394{
395 struct mlx5_ib_dev *dev = to_mdev(device);
da005f9f 396 struct mlx5_core_dev *mdev;
88621dfe 397 struct net_device *ndev, *upper;
3f89a643 398 enum ib_mtu ndev_ib_mtu;
b3cbd6f0 399 bool put_mdev = true;
c876a1b7 400 u16 qkey_viol_cntr;
f1b65df5 401 u32 eth_prot_oper;
b3cbd6f0 402 u8 mdev_port_num;
095b0927 403 int err;
3f89a643 404
b3cbd6f0
DJ		 405 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
406 if (!mdev) {
407 /* This means the port isn't affiliated yet. Get the
408 * info for the master port instead.
409 */
410 put_mdev = false;
411 mdev = dev->mdev;
412 mdev_port_num = 1;
413 port_num = 1;
414 }
415
f1b65df5
NO		 416 /* Possible bad flows are checked before filling out props so in case
417 * of an error it will still be zeroed out.
50f22fd8 418 */
b3cbd6f0
DJ		 419 err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper,
420 mdev_port_num);
095b0927 421 if (err)
b3cbd6f0 422 goto out;
f1b65df5 423
7672ed33
HL		 424 props->active_width = IB_WIDTH_4X;
425 props->active_speed = IB_SPEED_QDR;
426
f1b65df5
NO		 427 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
428 &props->active_width);
3f89a643 429
2f944c0f
JG		 430 props->port_cap_flags |= IB_PORT_CM_SUP;
431 props->ip_gids = true;
3f89a643
AS		 432
433 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
434 roce_address_table_size);
435 props->max_mtu = IB_MTU_4096;
436 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
437 props->pkey_tbl_len = 1;
438 props->state = IB_PORT_DOWN;
439 props->phys_state = 3;
440
b3cbd6f0 441 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
c876a1b7 442 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643 443
b3cbd6f0
DJ		 444 /* If this is a stub query for an unaffiliated port stop here */
445 if (!put_mdev)
446 goto out;
447
3f89a643
AS		 448 ndev = mlx5_ib_get_netdev(device, port_num);
449 if (!ndev)
b3cbd6f0 450 goto out;
3f89a643 451
7c34ec19 452 if (dev->lag_active) {
88621dfe
AH		 453 rcu_read_lock();
454 upper = netdev_master_upper_dev_get_rcu(ndev);
455 if (upper) {
456 dev_put(ndev);
457 ndev = upper;
458 dev_hold(ndev);
459 }
460 rcu_read_unlock();
461 }
462
3f89a643
AS		 463 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
464 props->state = IB_PORT_ACTIVE;
465 props->phys_state = 5;
466 }
467
468 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
469
470 dev_put(ndev);
471
472 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
b3cbd6f0
DJ		 473out:
474 if (put_mdev)
475 mlx5_ib_put_native_port_mdev(dev, port_num);
476 return err;
3f89a643
AS		 477}
478
095b0927
IT		 479static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
480 unsigned int index, const union ib_gid *gid,
481 const struct ib_gid_attr *attr)
3cca2606 482{
095b0927
IT		 483 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
484 u8 roce_version = 0;
485 u8 roce_l3_type = 0;
486 bool vlan = false;
487 u8 mac[ETH_ALEN];
488 u16 vlan_id = 0;
489
490 if (gid) {
491 gid_type = attr->gid_type;
492 ether_addr_copy(mac, attr->ndev->dev_addr);
493
494 if (is_vlan_dev(attr->ndev)) {
495 vlan = true;
496 vlan_id = vlan_dev_vlan_id(attr->ndev);
497 }
3cca2606
AS		 498 }
499
095b0927 500 switch (gid_type) {
3cca2606 501 case IB_GID_TYPE_IB:
095b0927 502 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 503 break;
504 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 505 roce_version = MLX5_ROCE_VERSION_2;
506 if (ipv6_addr_v4mapped((void *)gid))
507 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
508 else
509 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 510 break;
511
512 default:
095b0927 513 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 514 }
515
095b0927
IT		 516 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
517 roce_l3_type, gid->raw, mac, vlan,
cfe4e37f 518 vlan_id, port_num);
3cca2606
AS		 519}
520
f4df9a7c 521static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
3cca2606
AS		 522 __always_unused void **context)
523{
414448d2 524 return set_roce_addr(to_mdev(attr->device), attr->port_num,
f4df9a7c 525 attr->index, &attr->gid, attr);
3cca2606
AS		 526}
527
414448d2
PP		 528static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
529 __always_unused void **context)
3cca2606 530{
414448d2
PP		 531 return set_roce_addr(to_mdev(attr->device), attr->port_num,
532 attr->index, NULL, NULL);
3cca2606
AS		 533}
534
47ec3866
PP		 535__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
536 const struct ib_gid_attr *attr)
2811ba51 537{
47ec3866 538 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
2811ba51
AS		 539 return 0;
540
541 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
542}
543
1b5daf11
MD		 544static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
545{
7fae6655
NO		 546 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
547 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
548 return 0;
1b5daf11
MD		 549}
550
551enum {
552 MLX5_VPORT_ACCESS_METHOD_MAD,
553 MLX5_VPORT_ACCESS_METHOD_HCA,
554 MLX5_VPORT_ACCESS_METHOD_NIC,
555};
556
557static int mlx5_get_vport_access_method(struct ib_device *ibdev)
558{
559 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
560 return MLX5_VPORT_ACCESS_METHOD_MAD;
561
ebd61f68 562 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 563 IB_LINK_LAYER_ETHERNET)
564 return MLX5_VPORT_ACCESS_METHOD_NIC;
565
566 return MLX5_VPORT_ACCESS_METHOD_HCA;
567}
568
da7525d2 569static void get_atomic_caps(struct mlx5_ib_dev *dev,
776a3906 570 u8 atomic_size_qp,
da7525d2
EBE		 571 struct ib_device_attr *props)
572{
573 u8 tmp;
574 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
da7525d2 575 u8 atomic_req_8B_endianness_mode =
bd10838a 576 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 577
578 /* Check if HW supports 8 bytes standard atomic operations and capable
579 * of host endianness respond
580 */
581 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
582 if (((atomic_operations & tmp) == tmp) &&
583 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
584 (atomic_req_8B_endianness_mode)) {
585 props->atomic_cap = IB_ATOMIC_HCA;
586 } else {
587 props->atomic_cap = IB_ATOMIC_NONE;
588 }
589}
590
776a3906
MS		 591static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
592 struct ib_device_attr *props)
593{
594 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
595
596 get_atomic_caps(dev, atomic_size_qp, props);
597}
598
599static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
600 struct ib_device_attr *props)
601{
602 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
603
604 get_atomic_caps(dev, atomic_size_qp, props);
605}
606
607bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
608{
609 struct ib_device_attr props = {};
610
611 get_atomic_caps_dc(dev, &props);
612 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
613}
1b5daf11
MD		 614static int mlx5_query_system_image_guid(struct ib_device *ibdev,
615 __be64 *sys_image_guid)
616{
617 struct mlx5_ib_dev *dev = to_mdev(ibdev);
618 struct mlx5_core_dev *mdev = dev->mdev;
619 u64 tmp;
620 int err;
621
622 switch (mlx5_get_vport_access_method(ibdev)) {
623 case MLX5_VPORT_ACCESS_METHOD_MAD:
624 return mlx5_query_mad_ifc_system_image_guid(ibdev,
625 sys_image_guid);
626
627 case MLX5_VPORT_ACCESS_METHOD_HCA:
628 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 629 break;
630
631 case MLX5_VPORT_ACCESS_METHOD_NIC:
632 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
633 break;
1b5daf11
MD		 634
635 default:
636 return -EINVAL;
637 }
3f89a643
AS		 638
639 if (!err)
640 *sys_image_guid = cpu_to_be64(tmp);
641
642 return err;
643
1b5daf11
MD		 644}
645
646static int mlx5_query_max_pkeys(struct ib_device *ibdev,
647 u16 *max_pkeys)
648{
649 struct mlx5_ib_dev *dev = to_mdev(ibdev);
650 struct mlx5_core_dev *mdev = dev->mdev;
651
652 switch (mlx5_get_vport_access_method(ibdev)) {
653 case MLX5_VPORT_ACCESS_METHOD_MAD:
654 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
655
656 case MLX5_VPORT_ACCESS_METHOD_HCA:
657 case MLX5_VPORT_ACCESS_METHOD_NIC:
658 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
659 pkey_table_size));
660 return 0;
661
662 default:
663 return -EINVAL;
664 }
665}
666
667static int mlx5_query_vendor_id(struct ib_device *ibdev,
668 u32 *vendor_id)
669{
670 struct mlx5_ib_dev *dev = to_mdev(ibdev);
671
672 switch (mlx5_get_vport_access_method(ibdev)) {
673 case MLX5_VPORT_ACCESS_METHOD_MAD:
674 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
675
676 case MLX5_VPORT_ACCESS_METHOD_HCA:
677 case MLX5_VPORT_ACCESS_METHOD_NIC:
678 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
679
680 default:
681 return -EINVAL;
682 }
683}
684
685static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
686 __be64 *node_guid)
687{
688 u64 tmp;
689 int err;
690
691 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
692 case MLX5_VPORT_ACCESS_METHOD_MAD:
693 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
694
695 case MLX5_VPORT_ACCESS_METHOD_HCA:
696 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 697 break;
698
699 case MLX5_VPORT_ACCESS_METHOD_NIC:
700 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
701 break;
1b5daf11
MD		 702
703 default:
704 return -EINVAL;
705 }
3f89a643
AS		 706
707 if (!err)
708 *node_guid = cpu_to_be64(tmp);
709
710 return err;
1b5daf11
MD		 711}
712
713struct mlx5_reg_node_desc {
bd99fdea 714 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 715};
716
717static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
718{
719 struct mlx5_reg_node_desc in;
720
721 if (mlx5_use_mad_ifc(dev))
722 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
723
724 memset(&in, 0, sizeof(in));
725
726 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
727 sizeof(struct mlx5_reg_node_desc),
728 MLX5_REG_NODE_DESC, 0, 0);
729}
730
e126ba97 731static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 732 struct ib_device_attr *props,
733 struct ib_udata *uhw)
e126ba97
EC		 734{
735 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 736 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 737 int err = -ENOMEM;
288c01b7 738 int max_sq_desc;
e126ba97
EC		 739 int max_rq_sg;
740 int max_sq_sg;
e0238a6a 741 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
85c7c014 742 bool raw_support = !mlx5_core_mp_enabled(mdev);
402ca536
BW		 743 struct mlx5_ib_query_device_resp resp = {};
744 size_t resp_len;
745 u64 max_tso;
e126ba97 746
402ca536
BW		 747 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
748 if (uhw->outlen && uhw->outlen < resp_len)
749 return -EINVAL;
750 else
751 resp.response_length = resp_len;
752
753 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 754 return -EINVAL;
755
1b5daf11
MD		 756 memset(props, 0, sizeof(*props));
757 err = mlx5_query_system_image_guid(ibdev,
758 &props->sys_image_guid);
759 if (err)
760 return err;
e126ba97 761
1b5daf11 762 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 763 if (err)
1b5daf11 764 return err;
e126ba97 765
1b5daf11
MD		 766 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
767 if (err)
768 return err;
e126ba97 769
9603b61d
JM		 770 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
771 (fw_rev_min(dev->mdev) << 16) |
772 fw_rev_sub(dev->mdev);
e126ba97
EC		 773 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
774 IB_DEVICE_PORT_ACTIVE_EVENT |
775 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 776 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 777
778 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 779 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 780 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 781 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 782 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 783 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 784 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 785 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 786 if (MLX5_CAP_GEN(mdev, imaicl)) {
787 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
788 IB_DEVICE_MEM_WINDOW_TYPE_2B;
789 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 790 /* We support 'Gappy' memory registration too */
791 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 792 }
e126ba97 793 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 794 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 795 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
796 /* At this stage no support for signature handover */
797 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
798 IB_PROT_T10DIF_TYPE_2 |
799 IB_PROT_T10DIF_TYPE_3;
800 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
801 IB_GUARD_T10DIF_CSUM;
802 }
938fe83c 803 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 804 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 805
85c7c014 806 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
e8161334
NO		 807 if (MLX5_CAP_ETH(mdev, csum_cap)) {
808 /* Legacy bit to support old userspace libraries */
88115fe7 809 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 810 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
811 }
812
813 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
814 props->raw_packet_caps |=
815 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 816
402ca536
BW		 817 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
818 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
819 if (max_tso) {
820 resp.tso_caps.max_tso = 1 << max_tso;
821 resp.tso_caps.supported_qpts |=
822 1 << IB_QPT_RAW_PACKET;
823 resp.response_length += sizeof(resp.tso_caps);
824 }
825 }
31f69a82
YH		 826
827 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
828 resp.rss_caps.rx_hash_function =
829 MLX5_RX_HASH_FUNC_TOEPLITZ;
830 resp.rss_caps.rx_hash_fields_mask =
831 MLX5_RX_HASH_SRC_IPV4 |
832 MLX5_RX_HASH_DST_IPV4 |
833 MLX5_RX_HASH_SRC_IPV6 |
834 MLX5_RX_HASH_DST_IPV6 |
835 MLX5_RX_HASH_SRC_PORT_TCP |
836 MLX5_RX_HASH_DST_PORT_TCP |
837 MLX5_RX_HASH_SRC_PORT_UDP |
4e2b53a5
MG		 838 MLX5_RX_HASH_DST_PORT_UDP |
839 MLX5_RX_HASH_INNER;
2d93fc85
MB		 840 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
841 MLX5_ACCEL_IPSEC_CAP_DEVICE)
842 resp.rss_caps.rx_hash_fields_mask |=
843 MLX5_RX_HASH_IPSEC_SPI;
31f69a82
YH		 844 resp.response_length += sizeof(resp.rss_caps);
845 }
846 } else {
847 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
848 resp.response_length += sizeof(resp.tso_caps);
849 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
850 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 851 }
852
f0313965
ES		 853 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
854 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
855 props->device_cap_flags |= IB_DEVICE_UD_TSO;
856 }
857
03404e8a 858 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
85c7c014
DJ		 859 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
860 raw_support)
03404e8a
MG		 861 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
862
1d54f890
YH		 863 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
864 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
865 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
866
cff5a0f3 867 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
85c7c014
DJ		 868 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
869 raw_support) {
e8161334 870 /* Legacy bit to support old userspace libraries */
cff5a0f3 871 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 872 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
873 }
cff5a0f3 874
24da0016
AL		 875 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
876 props->max_dm_size =
877 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
878 }
879
da6d6ba3
MG		 880 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
881 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
882
b1383aa6
NO		 883 if (MLX5_CAP_GEN(mdev, end_pad))
884 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
885
1b5daf11
MD		 886 props->vendor_part_id = mdev->pdev->device;
887 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 888
889 props->max_mr_size = ~0ull;
e0238a6a 890 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 891 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
892 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
893 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
894 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 895 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
896 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
897 sizeof(struct mlx5_wqe_raddr_seg)) /
898 sizeof(struct mlx5_wqe_data_seg);
33023fb8
SW		 899 props->max_send_sge = max_sq_sg;
900 props->max_recv_sge = max_rq_sg;
986ef95e 901 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 902 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 903 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 904 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
905 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
906 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
907 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
908 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
909 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
910 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 911 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 912 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 913 props->max_fast_reg_page_list_len =
914 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
776a3906 915 get_atomic_caps_qp(dev, props);
81bea28f 916 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 917 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
918 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 919 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
920 props->max_mcast_grp;
921 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 922 props->max_ah = INT_MAX;
7c60bcbb
MB		 923 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
924 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 925
e502b8b0
LR		 926 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
927 if (MLX5_CAP_GEN(mdev, pg))
928 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
929 props->odp_caps = dev->odp_caps;
930 }
8cdd312c 931
051f2630
LR		 932 if (MLX5_CAP_GEN(mdev, cd))
933 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
934
eff901d3
EC		 935 if (!mlx5_core_is_pf(mdev))
936 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
937
31f69a82 938 if (mlx5_ib_port_link_layer(ibdev, 1) ==
85c7c014 939 IB_LINK_LAYER_ETHERNET && raw_support) {
31f69a82
YH		 940 props->rss_caps.max_rwq_indirection_tables =
941 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
942 props->rss_caps.max_rwq_indirection_table_size =
943 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
944 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
945 props->max_wq_type_rq =
946 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
947 }
948
eb761894 949 if (MLX5_CAP_GEN(mdev, tag_matching)) {
78b1beb0
LR		 950 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
951 props->tm_caps.max_num_tags =
eb761894 952 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
78b1beb0
LR		 953 props->tm_caps.flags = IB_TM_CAP_RC;
954 props->tm_caps.max_ops =
eb761894 955 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
78b1beb0 956 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
eb761894
AK		 957 }
958
87ab3f52
YC		 959 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
960 props->cq_caps.max_cq_moderation_count =
961 MLX5_MAX_CQ_COUNT;
962 props->cq_caps.max_cq_moderation_period =
963 MLX5_MAX_CQ_PERIOD;
964 }
965
7e43a2a5 966 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
7e43a2a5 967 resp.response_length += sizeof(resp.cqe_comp_caps);
572f46bf
YC		 968
969 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
970 resp.cqe_comp_caps.max_num =
971 MLX5_CAP_GEN(dev->mdev,
972 cqe_compression_max_num);
973
974 resp.cqe_comp_caps.supported_format =
975 MLX5_IB_CQE_RES_FORMAT_HASH |
976 MLX5_IB_CQE_RES_FORMAT_CSUM;
6f1006a4
YC		 977
978 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
979 resp.cqe_comp_caps.supported_format |=
980 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
572f46bf 981 }
7e43a2a5
BW		 982 }
983
85c7c014
DJ		 984 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
985 raw_support) {
d949167d
BW		 986 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
987 MLX5_CAP_GEN(mdev, qos)) {
988 resp.packet_pacing_caps.qp_rate_limit_max =
989 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
990 resp.packet_pacing_caps.qp_rate_limit_min =
991 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
992 resp.packet_pacing_caps.supported_qpts |=
993 1 << IB_QPT_RAW_PACKET;
61147f39
BW		 994 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
995 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
996 resp.packet_pacing_caps.cap_flags |=
997 MLX5_IB_PP_SUPPORT_BURST;
d949167d
BW		 998 }
999 resp.response_length += sizeof(resp.packet_pacing_caps);
1000 }
1001
9f885201
LR		 1002 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
1003 uhw->outlen)) {
795b609c
BW		 1004 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1005 resp.mlx5_ib_support_multi_pkt_send_wqes =
1006 MLX5_IB_ALLOW_MPW;
050da902
BW		 1007
1008 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1009 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1010 MLX5_IB_SUPPORT_EMPW;
1011
9f885201
LR		 1012 resp.response_length +=
1013 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1014 }
1015
de57f2ad
GL		 1016 if (field_avail(typeof(resp), flags, uhw->outlen)) {
1017 resp.response_length += sizeof(resp.flags);
7a0c8f42 1018
de57f2ad
GL		 1019 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1020 resp.flags |=
1021 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
7a0c8f42
GL		 1022
1023 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1024 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
7e11b911
DG		 1025 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1026 resp.flags |=
1027 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
de57f2ad 1028 }
9f885201 1029
96dc3fc5
NO		 1030 if (field_avail(typeof(resp), sw_parsing_caps,
1031 uhw->outlen)) {
1032 resp.response_length += sizeof(resp.sw_parsing_caps);
1033 if (MLX5_CAP_ETH(mdev, swp)) {
1034 resp.sw_parsing_caps.sw_parsing_offloads |=
1035 MLX5_IB_SW_PARSING;
1036
1037 if (MLX5_CAP_ETH(mdev, swp_csum))
1038 resp.sw_parsing_caps.sw_parsing_offloads |=
1039 MLX5_IB_SW_PARSING_CSUM;
1040
1041 if (MLX5_CAP_ETH(mdev, swp_lso))
1042 resp.sw_parsing_caps.sw_parsing_offloads |=
1043 MLX5_IB_SW_PARSING_LSO;
1044
1045 if (resp.sw_parsing_caps.sw_parsing_offloads)
1046 resp.sw_parsing_caps.supported_qpts =
1047 BIT(IB_QPT_RAW_PACKET);
1048 }
1049 }
1050
85c7c014
DJ		 1051 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1052 raw_support) {
b4f34597
NO		 1053 resp.response_length += sizeof(resp.striding_rq_caps);
1054 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1055 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1056 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1057 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1058 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1059 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1060 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1061 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1062 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1063 resp.striding_rq_caps.supported_qpts =
1064 BIT(IB_QPT_RAW_PACKET);
1065 }
1066 }
1067
f95ef6cb
MG		 1068 if (field_avail(typeof(resp), tunnel_offloads_caps,
1069 uhw->outlen)) {
1070 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1071 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1072 resp.tunnel_offloads_caps |=
1073 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1074 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1075 resp.tunnel_offloads_caps |=
1076 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1077 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1078 resp.tunnel_offloads_caps |=
1079 MLX5_IB_TUNNELED_OFFLOADS_GRE;
e818e255
AL		 1080 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1081 MLX5_FLEX_PROTO_CW_MPLS_GRE)
1082 resp.tunnel_offloads_caps |=
1083 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1084 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1085 MLX5_FLEX_PROTO_CW_MPLS_UDP)
1086 resp.tunnel_offloads_caps |=
1087 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
f95ef6cb
MG		 1088 }
1089
402ca536
BW		 1090 if (uhw->outlen) {
1091 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1092
1093 if (err)
1094 return err;
1095 }
1096
1b5daf11 1097 return 0;
e126ba97
EC		 1098}
1099
1b5daf11
MD		 1100enum mlx5_ib_width {
1101 MLX5_IB_WIDTH_1X = 1 << 0,
1102 MLX5_IB_WIDTH_2X = 1 << 1,
1103 MLX5_IB_WIDTH_4X = 1 << 2,
1104 MLX5_IB_WIDTH_8X = 1 << 3,
1105 MLX5_IB_WIDTH_12X = 1 << 4
1106};
1107
db7a691a 1108static void translate_active_width(struct ib_device *ibdev, u8 active_width,
1b5daf11 1109 u8 *ib_width)
e126ba97
EC		 1110{
1111 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11 1112
db7a691a 1113 if (active_width & MLX5_IB_WIDTH_1X)
1b5daf11 1114 *ib_width = IB_WIDTH_1X;
d764970b
MG		 1115 else if (active_width & MLX5_IB_WIDTH_2X)
1116 *ib_width = IB_WIDTH_2X;
db7a691a 1117 else if (active_width & MLX5_IB_WIDTH_4X)
1b5daf11 1118 *ib_width = IB_WIDTH_4X;
db7a691a 1119 else if (active_width & MLX5_IB_WIDTH_8X)
1b5daf11 1120 *ib_width = IB_WIDTH_8X;
db7a691a 1121 else if (active_width & MLX5_IB_WIDTH_12X)
1b5daf11 1122 *ib_width = IB_WIDTH_12X;
db7a691a
MG		 1123 else {
1124 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1b5daf11 1125 (int)active_width);
db7a691a 1126 *ib_width = IB_WIDTH_4X;
e126ba97
EC		 1127 }
1128
db7a691a 1129 return;
1b5daf11 1130}
e126ba97 1131
1b5daf11
MD		 1132static int mlx5_mtu_to_ib_mtu(int mtu)
1133{
1134 switch (mtu) {
1135 case 256: return 1;
1136 case 512: return 2;
1137 case 1024: return 3;
1138 case 2048: return 4;
1139 case 4096: return 5;
1140 default:
1141 pr_warn("invalid mtu\n");
1142 return -1;
e126ba97 1143 }
1b5daf11 1144}
e126ba97 1145
1b5daf11
MD		 1146enum ib_max_vl_num {
1147 __IB_MAX_VL_0 = 1,
1148 __IB_MAX_VL_0_1 = 2,
1149 __IB_MAX_VL_0_3 = 3,
1150 __IB_MAX_VL_0_7 = 4,
1151 __IB_MAX_VL_0_14 = 5,
1152};
e126ba97 1153
1b5daf11
MD		 1154enum mlx5_vl_hw_cap {
1155 MLX5_VL_HW_0 = 1,
1156 MLX5_VL_HW_0_1 = 2,
1157 MLX5_VL_HW_0_2 = 3,
1158 MLX5_VL_HW_0_3 = 4,
1159 MLX5_VL_HW_0_4 = 5,
1160 MLX5_VL_HW_0_5 = 6,
1161 MLX5_VL_HW_0_6 = 7,
1162 MLX5_VL_HW_0_7 = 8,
1163 MLX5_VL_HW_0_14 = 15
1164};
e126ba97 1165
1b5daf11
MD		 1166static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1167 u8 *max_vl_num)
1168{
1169 switch (vl_hw_cap) {
1170 case MLX5_VL_HW_0:
1171 *max_vl_num = __IB_MAX_VL_0;
1172 break;
1173 case MLX5_VL_HW_0_1:
1174 *max_vl_num = __IB_MAX_VL_0_1;
1175 break;
1176 case MLX5_VL_HW_0_3:
1177 *max_vl_num = __IB_MAX_VL_0_3;
1178 break;
1179 case MLX5_VL_HW_0_7:
1180 *max_vl_num = __IB_MAX_VL_0_7;
1181 break;
1182 case MLX5_VL_HW_0_14:
1183 *max_vl_num = __IB_MAX_VL_0_14;
1184 break;
e126ba97 1185
1b5daf11
MD		 1186 default:
1187 return -EINVAL;
e126ba97 1188 }
e126ba97 1189
1b5daf11 1190 return 0;
e126ba97
EC		 1191}
1192
1b5daf11
MD		 1193static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1194 struct ib_port_attr *props)
e126ba97 1195{
1b5daf11
MD		 1196 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1197 struct mlx5_core_dev *mdev = dev->mdev;
1198 struct mlx5_hca_vport_context *rep;
046339ea
SM		 1199 u16 max_mtu;
1200 u16 oper_mtu;
1b5daf11
MD		 1201 int err;
1202 u8 ib_link_width_oper;
1203 u8 vl_hw_cap;
e126ba97 1204
1b5daf11
MD		 1205 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1206 if (!rep) {
1207 err = -ENOMEM;
e126ba97 1208 goto out;
e126ba97 1209 }
e126ba97 1210
c4550c63 1211 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 1212
1b5daf11 1213 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 1214 if (err)
1215 goto out;
1216
1b5daf11
MD		 1217 props->lid = rep->lid;
1218 props->lmc = rep->lmc;
1219 props->sm_lid = rep->sm_lid;
1220 props->sm_sl = rep->sm_sl;
1221 props->state = rep->vport_state;
1222 props->phys_state = rep->port_physical_state;
1223 props->port_cap_flags = rep->cap_mask1;
1224 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1225 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1226 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1227 props->bad_pkey_cntr = rep->pkey_violation_counter;
1228 props->qkey_viol_cntr = rep->qkey_violation_counter;
1229 props->subnet_timeout = rep->subnet_timeout;
1230 props->init_type_reply = rep->init_type_reply;
e126ba97 1231
4106a758
MG		 1232 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1233 props->port_cap_flags2 = rep->cap_mask2;
1234
1b5daf11
MD		 1235 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1236 if (err)
e126ba97 1237 goto out;
e126ba97 1238
db7a691a
MG		 1239 translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1240
d5beb7f2 1241 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 1242 if (err)
1243 goto out;
1244
facc9699 1245 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 1246
1b5daf11 1247 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 1248
facc9699 1249 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 1250
1b5daf11 1251 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1252
1b5daf11
MD		 1253 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1254 if (err)
1255 goto out;
e126ba97 1256
1b5daf11
MD		 1257 err = translate_max_vl_num(ibdev, vl_hw_cap,
1258 &props->max_vl_num);
e126ba97 1259out:
1b5daf11 1260 kfree(rep);
e126ba97
EC		 1261 return err;
1262}
1263
1b5daf11
MD		 1264int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1265 struct ib_port_attr *props)
e126ba97 1266{
095b0927
IT		 1267 unsigned int count;
1268 int ret;
1269
1b5daf11
MD		 1270 switch (mlx5_get_vport_access_method(ibdev)) {
1271 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1272 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1273 break;
e126ba97 1274
1b5daf11 1275 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1276 ret = mlx5_query_hca_port(ibdev, port, props);
1277 break;
e126ba97 1278
3f89a643 1279 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1280 ret = mlx5_query_port_roce(ibdev, port, props);
1281 break;
3f89a643 1282
1b5daf11 1283 default:
095b0927
IT		 1284 ret = -EINVAL;
1285 }
1286
1287 if (!ret && props) {
b3cbd6f0
DJ		 1288 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1289 struct mlx5_core_dev *mdev;
1290 bool put_mdev = true;
1291
1292 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1293 if (!mdev) {
1294 /* If the port isn't affiliated yet query the master.
1295 * The master and slave will have the same values.
1296 */
1297 mdev = dev->mdev;
1298 port = 1;
1299 put_mdev = false;
1300 }
1301 count = mlx5_core_reserved_gids_count(mdev);
1302 if (put_mdev)
1303 mlx5_ib_put_native_port_mdev(dev, port);
095b0927 1304 props->gid_tbl_len -= count;
1b5daf11 1305 }
095b0927 1306 return ret;
1b5daf11 1307}
e126ba97 1308
8e6efa3a
MB		 1309static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1310 struct ib_port_attr *props)
1311{
1312 int ret;
1313
1314 /* Only link layer == ethernet is valid for representors */
1315 ret = mlx5_query_port_roce(ibdev, port, props);
1316 if (ret || !props)
1317 return ret;
1318
1319 /* We don't support GIDS */
1320 props->gid_tbl_len = 0;
1321
1322 return ret;
1323}
1324
1b5daf11
MD		 1325static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1326 union ib_gid *gid)
1327{
1328 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1329 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1330
1b5daf11
MD		 1331 switch (mlx5_get_vport_access_method(ibdev)) {
1332 case MLX5_VPORT_ACCESS_METHOD_MAD:
1333 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1334
1b5daf11
MD		 1335 case MLX5_VPORT_ACCESS_METHOD_HCA:
1336 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1337
1338 default:
1339 return -EINVAL;
1340 }
e126ba97 1341
e126ba97
EC		 1342}
1343
b3cbd6f0
DJ		 1344static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1345 u16 index, u16 *pkey)
1b5daf11
MD		 1346{
1347 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b3cbd6f0
DJ		 1348 struct mlx5_core_dev *mdev;
1349 bool put_mdev = true;
1350 u8 mdev_port_num;
1351 int err;
1b5daf11 1352
b3cbd6f0
DJ		 1353 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1354 if (!mdev) {
1355 /* The port isn't affiliated yet, get the PKey from the master
1356 * port. For RoCE the PKey tables will be the same.
1357 */
1358 put_mdev = false;
1359 mdev = dev->mdev;
1360 mdev_port_num = 1;
1361 }
1362
1363 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1364 index, pkey);
1365 if (put_mdev)
1366 mlx5_ib_put_native_port_mdev(dev, port);
1367
1368 return err;
1369}
1370
1371static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1372 u16 *pkey)
1373{
1b5daf11
MD		 1374 switch (mlx5_get_vport_access_method(ibdev)) {
1375 case MLX5_VPORT_ACCESS_METHOD_MAD:
1376 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1377
1378 case MLX5_VPORT_ACCESS_METHOD_HCA:
1379 case MLX5_VPORT_ACCESS_METHOD_NIC:
b3cbd6f0 1380 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1b5daf11
MD		 1381 default:
1382 return -EINVAL;
1383 }
1384}
e126ba97
EC		 1385
1386static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1387 struct ib_device_modify *props)
1388{
1389 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1390 struct mlx5_reg_node_desc in;
1391 struct mlx5_reg_node_desc out;
1392 int err;
1393
1394 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1395 return -EOPNOTSUPP;
1396
1397 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1398 return 0;
1399
1400 /*
1401 * If possible, pass node desc to FW, so it can generate
1402 * a 144 trap. If cmd fails, just ignore.
1403 */
bd99fdea 1404 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1405 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1406 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1407 if (err)
1408 return err;
1409
bd99fdea 1410 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1411
1412 return err;
1413}
1414
cdbe33d0
EC		 1415static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1416 u32 value)
1417{
1418 struct mlx5_hca_vport_context ctx = {};
b3cbd6f0
DJ		 1419 struct mlx5_core_dev *mdev;
1420 u8 mdev_port_num;
cdbe33d0
EC		 1421 int err;
1422
b3cbd6f0
DJ		 1423 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1424 if (!mdev)
1425 return -ENODEV;
1426
1427 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
cdbe33d0 1428 if (err)
b3cbd6f0 1429 goto out;
cdbe33d0
EC		 1430
1431 if (~ctx.cap_mask1_perm & mask) {
1432 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1433 mask, ctx.cap_mask1_perm);
b3cbd6f0
DJ		 1434 err = -EINVAL;
1435 goto out;
cdbe33d0
EC		 1436 }
1437
1438 ctx.cap_mask1 = value;
1439 ctx.cap_mask1_perm = mask;
b3cbd6f0
DJ		 1440 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1441 0, &ctx);
1442
1443out:
1444 mlx5_ib_put_native_port_mdev(dev, port_num);
cdbe33d0
EC		 1445
1446 return err;
1447}
1448
e126ba97
EC		 1449static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1450 struct ib_port_modify *props)
1451{
1452 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1453 struct ib_port_attr attr;
1454 u32 tmp;
1455 int err;
cdbe33d0
EC		 1456 u32 change_mask;
1457 u32 value;
1458 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1459 IB_LINK_LAYER_INFINIBAND);
1460
ec255879
MD		 1461 /* CM layer calls ib_modify_port() regardless of the link layer. For
1462 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1463 */
1464 if (!is_ib)
1465 return 0;
1466
cdbe33d0
EC		 1467 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1468 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1469 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1470 return set_port_caps_atomic(dev, port, change_mask, value);
1471 }
e126ba97
EC		 1472
1473 mutex_lock(&dev->cap_mask_mutex);
1474
c4550c63 1475 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1476 if (err)
1477 goto out;
1478
1479 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1480 ~props->clr_port_cap_mask;
1481
9603b61d 1482 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1483
1484out:
1485 mutex_unlock(&dev->cap_mask_mutex);
1486 return err;
1487}
1488
30aa60b3
EC		 1489static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1490{
1491 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1492 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1493}
1494
31a78a5a
YH		 1495static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1496{
1497 /* Large page with non 4k uar support might limit the dynamic size */
1498 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1499 return MLX5_MIN_DYN_BFREGS;
1500
1501 return MLX5_MAX_DYN_BFREGS;
1502}
1503
b037c29a
EC		 1504static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1505 struct mlx5_ib_alloc_ucontext_req_v2 *req,
31a78a5a 1506 struct mlx5_bfreg_info *bfregi)
b037c29a
EC		 1507{
1508 int uars_per_sys_page;
1509 int bfregs_per_sys_page;
1510 int ref_bfregs = req->total_num_bfregs;
1511
1512 if (req->total_num_bfregs == 0)
1513 return -EINVAL;
1514
1515 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1516 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1517
1518 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1519 return -ENOMEM;
1520
1521 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1522 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
31a78a5a 1523 /* This holds the required static allocation asked by the user */
b037c29a 1524 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
b037c29a
EC		 1525 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1526 return -EINVAL;
1527
31a78a5a
YH		 1528 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1529 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1530 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1531 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1532
1533 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
b037c29a
EC		 1534 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1535 lib_uar_4k ? "yes" : "no", ref_bfregs,
31a78a5a
YH		 1536 req->total_num_bfregs, bfregi->total_num_bfregs,
1537 bfregi->num_sys_pages);
b037c29a
EC		 1538
1539 return 0;
1540}
1541
1542static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1543{
1544 struct mlx5_bfreg_info *bfregi;
1545 int err;
1546 int i;
1547
1548 bfregi = &context->bfregi;
31a78a5a 1549 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
b037c29a
EC		 1550 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1551 if (err)
1552 goto error;
1553
1554 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1555 }
4ed131d0
YH		 1556
1557 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1558 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1559
b037c29a
EC		 1560 return 0;
1561
1562error:
1563 for (--i; i >= 0; i--)
1564 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1565 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1566
1567 return err;
1568}
1569
15177999
LR		 1570static void deallocate_uars(struct mlx5_ib_dev *dev,
1571 struct mlx5_ib_ucontext *context)
b037c29a
EC		 1572{
1573 struct mlx5_bfreg_info *bfregi;
b037c29a
EC		 1574 int i;
1575
1576 bfregi = &context->bfregi;
15177999 1577 for (i = 0; i < bfregi->num_sys_pages; i++)
4ed131d0 1578 if (i < bfregi->num_static_sys_pages ||
15177999
LR		 1579 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1580 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
b037c29a
EC		 1581}
1582
0042f9e4 1583int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
a560f1d9
MB		 1584{
1585 int err = 0;
1586
1587 mutex_lock(&dev->lb.mutex);
0042f9e4
MB		 1588 if (td)
1589 dev->lb.user_td++;
1590 if (qp)
1591 dev->lb.qps++;
1592
1593 if (dev->lb.user_td == 2 ||
1594 dev->lb.qps == 1) {
1595 if (!dev->lb.enabled) {
1596 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1597 dev->lb.enabled = true;
1598 }
1599 }
a560f1d9
MB		 1600
1601 mutex_unlock(&dev->lb.mutex);
1602
1603 return err;
1604}
1605
0042f9e4 1606void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
a560f1d9
MB		 1607{
1608 mutex_lock(&dev->lb.mutex);
0042f9e4
MB		 1609 if (td)
1610 dev->lb.user_td--;
1611 if (qp)
1612 dev->lb.qps--;
1613
1614 if (dev->lb.user_td == 1 &&
1615 dev->lb.qps == 0) {
1616 if (dev->lb.enabled) {
1617 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1618 dev->lb.enabled = false;
1619 }
1620 }
a560f1d9
MB		 1621
1622 mutex_unlock(&dev->lb.mutex);
1623}
1624
d2d19121
YH		 1625static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1626 u16 uid)
c85023e1
HN		 1627{
1628 int err;
1629
cfdeb893
LR		 1630 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1631 return 0;
1632
d2d19121 1633 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
c85023e1
HN		 1634 if (err)
1635 return err;
1636
1637 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1638 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1639 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1640 return err;
1641
0042f9e4 1642 return mlx5_ib_enable_lb(dev, true, false);
c85023e1
HN		 1643}
1644
d2d19121
YH		 1645static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1646 u16 uid)
c85023e1 1647{
cfdeb893
LR		 1648 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1649 return;
1650
d2d19121 1651 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
c85023e1
HN		 1652
1653 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1654 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1655 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1656 return;
1657
0042f9e4 1658 mlx5_ib_disable_lb(dev, true, false);
c85023e1
HN		 1659}
1660
e126ba97
EC		 1661static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1662 struct ib_udata *udata)
1663{
1664 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1665 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1666 struct mlx5_ib_alloc_ucontext_resp resp = {};
5c99eaec 1667 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1668 struct mlx5_ib_ucontext *context;
2f5ff264 1669 struct mlx5_bfreg_info *bfregi;
78c0f98c 1670 int ver;
e126ba97 1671 int err;
a168a41c
MD		 1672 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1673 max_cqe_version);
25bb36e7 1674 u32 dump_fill_mkey;
b037c29a 1675 bool lib_uar_4k;
e126ba97
EC		 1676
1677 if (!dev->ib_active)
1678 return ERR_PTR(-EAGAIN);
1679
e093111d 1680 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1681 ver = 0;
e093111d 1682 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1683 ver = 2;
1684 else
1685 return ERR_PTR(-EINVAL);
1686
e093111d 1687 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97
EC		 1688 if (err)
1689 return ERR_PTR(err);
1690
a8b92ca1
YH		 1691 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1692 return ERR_PTR(-EOPNOTSUPP);
78c0f98c 1693
f72300c5 1694 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 1695 return ERR_PTR(-EOPNOTSUPP);
1696
2f5ff264
EC		 1697 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1698 MLX5_NON_FP_BFREGS_PER_UAR);
1699 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
e126ba97
EC		 1700 return ERR_PTR(-EINVAL);
1701
938fe83c 1702 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1703 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1704 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1705 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1706 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1707 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1708 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1709 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1710 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1711 resp.cqe_version = min_t(__u8,
1712 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1713 req.max_cqe_version);
30aa60b3
EC		 1714 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1715 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1716 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1717 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1718 resp.response_length = min(offsetof(typeof(resp), response_length) +
1719 sizeof(resp.response_length), udata->outlen);
e126ba97 1720
c03faa56
MB		 1721 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1722 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1723 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1724 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1725 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1726 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1727 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1728 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1729 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1730 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1731 }
1732
e126ba97
EC		 1733 context = kzalloc(sizeof(*context), GFP_KERNEL);
1734 if (!context)
1735 return ERR_PTR(-ENOMEM);
1736
30aa60b3 1737 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1738 bfregi = &context->bfregi;
b037c29a
EC		 1739
1740 /* updates req->total_num_bfregs */
31a78a5a 1741 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
b037c29a 1742 if (err)
e126ba97 1743 goto out_ctx;
e126ba97 1744
b037c29a
EC		 1745 mutex_init(&bfregi->lock);
1746 bfregi->lib_uar_4k = lib_uar_4k;
31a78a5a 1747 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1748 GFP_KERNEL);
b037c29a 1749 if (!bfregi->count) {
e126ba97 1750 err = -ENOMEM;
b037c29a 1751 goto out_ctx;
e126ba97
EC		 1752 }
1753
b037c29a
EC		 1754 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1755 sizeof(*bfregi->sys_pages),
1756 GFP_KERNEL);
1757 if (!bfregi->sys_pages) {
e126ba97 1758 err = -ENOMEM;
b037c29a 1759 goto out_count;
e126ba97
EC		 1760 }
1761
b037c29a
EC		 1762 err = allocate_uars(dev, context);
1763 if (err)
1764 goto out_sys_pages;
e126ba97 1765
13859d5d
LR		 1766 if (ibdev->attrs.device_cap_flags & IB_DEVICE_ON_DEMAND_PAGING)
1767 context->ibucontext.invalidate_range =
1768 &mlx5_ib_invalidate_range;
b4cfe447 1769
a8b92ca1 1770 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
fb98153b 1771 err = mlx5_ib_devx_create(dev, true);
76dc5a84 1772 if (err < 0)
d2d19121 1773 goto out_uars;
76dc5a84 1774 context->devx_uid = err;
a8b92ca1
YH		 1775 }
1776
d2d19121
YH		 1777 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1778 context->devx_uid);
1779 if (err)
1780 goto out_devx;
1781
25bb36e7
YC		 1782 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1783 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1784 if (err)
8193abb6 1785 goto out_mdev;
25bb36e7
YC		 1786 }
1787
e126ba97
EC		 1788 INIT_LIST_HEAD(&context->db_page_list);
1789 mutex_init(&context->db_page_mutex);
1790
2f5ff264 1791 resp.tot_bfregs = req.total_num_bfregs;
508562d6 1792 resp.num_ports = dev->num_ports;
b368d7cb 1793
f72300c5
HA		 1794 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1795 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1796
402ca536 1797 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1798 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1799 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1800 resp.response_length += sizeof(resp.cmds_supp_uhw);
1801 }
1802
78984898
OG		 1803 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1804 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1805 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1806 resp.eth_min_inline++;
1807 }
1808 resp.response_length += sizeof(resp.eth_min_inline);
1809 }
1810
5c99eaec
FD		 1811 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1812 if (mdev->clock_info)
1813 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1814 resp.response_length += sizeof(resp.clock_info_versions);
1815 }
1816
bc5c6eed
NO		 1817 /*
1818 * We don't want to expose information from the PCI bar that is located
1819 * after 4096 bytes, so if the arch only supports larger pages, let's
1820 * pretend we don't support reading the HCA's core clock. This is also
1821 * forced by mmap function.
1822 */
de8d6e02
EC		 1823 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1824 if (PAGE_SIZE <= 4096) {
1825 resp.comp_mask |=
1826 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1827 resp.hca_core_clock_offset =
1828 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1829 }
5c99eaec 1830 resp.response_length += sizeof(resp.hca_core_clock_offset);
b368d7cb
MB		 1831 }
1832
30aa60b3
EC		 1833 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1834 resp.response_length += sizeof(resp.log_uar_size);
1835
1836 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1837 resp.response_length += sizeof(resp.num_uars_per_page);
1838
31a78a5a
YH		 1839 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1840 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1841 resp.response_length += sizeof(resp.num_dyn_bfregs);
1842 }
1843
25bb36e7
YC		 1844 if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) {
1845 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1846 resp.dump_fill_mkey = dump_fill_mkey;
1847 resp.comp_mask |=
1848 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1849 }
1850 resp.response_length += sizeof(resp.dump_fill_mkey);
1851 }
1852
b368d7cb 1853 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1854 if (err)
a8b92ca1 1855 goto out_mdev;
e126ba97 1856
2f5ff264
EC		 1857 bfregi->ver = ver;
1858 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1859 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1860 context->lib_caps = req.lib_caps;
1861 print_lib_caps(dev, context->lib_caps);
f72300c5 1862
7c34ec19 1863 if (dev->lag_active) {
c6a21c38
MD		 1864 u8 port = mlx5_core_native_port_num(dev->mdev);
1865
1866 atomic_set(&context->tx_port_affinity,
1867 atomic_add_return(
1868 1, &dev->roce[port].tx_port_affinity));
1869 }
1870
e126ba97
EC		 1871 return &context->ibucontext;
1872
a8b92ca1 1873out_mdev:
d2d19121
YH		 1874 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1875out_devx:
a8b92ca1 1876 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
76dc5a84 1877 mlx5_ib_devx_destroy(dev, context->devx_uid);
146d2f1a 1878
e126ba97 1879out_uars:
b037c29a 1880 deallocate_uars(dev, context);
e126ba97 1881
b037c29a
EC		 1882out_sys_pages:
1883 kfree(bfregi->sys_pages);
e126ba97 1884
b037c29a
EC		 1885out_count:
1886 kfree(bfregi->count);
e126ba97
EC		 1887
1888out_ctx:
1889 kfree(context);
b037c29a 1890
e126ba97
EC		 1891 return ERR_PTR(err);
1892}
1893
1894static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1895{
1896 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1897 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 1898 struct mlx5_bfreg_info *bfregi;
e126ba97 1899
f27a0d50
JG		 1900 /* All umem's must be destroyed before destroying the ucontext. */
1901 mutex_lock(&ibcontext->per_mm_list_lock);
1902 WARN_ON(!list_empty(&ibcontext->per_mm_list));
1903 mutex_unlock(&ibcontext->per_mm_list_lock);
a8b92ca1 1904
b037c29a 1905 bfregi = &context->bfregi;
d2d19121
YH		 1906 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1907
a8b92ca1 1908 if (context->devx_uid)
76dc5a84 1909 mlx5_ib_devx_destroy(dev, context->devx_uid);
146d2f1a 1910
b037c29a
EC		 1911 deallocate_uars(dev, context);
1912 kfree(bfregi->sys_pages);
2f5ff264 1913 kfree(bfregi->count);
e126ba97
EC		 1914 kfree(context);
1915
1916 return 0;
1917}
1918
b037c29a 1919static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
4ed131d0 1920 int uar_idx)
e126ba97 1921{
b037c29a
EC		 1922 int fw_uars_per_page;
1923
1924 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1925
4ed131d0 1926 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
e126ba97
EC		 1927}
1928
1929static int get_command(unsigned long offset)
1930{
1931 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1932}
1933
1934static int get_arg(unsigned long offset)
1935{
1936 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1937}
1938
1939static int get_index(unsigned long offset)
1940{
1941 return get_arg(offset);
1942}
1943
4ed131d0
YH		 1944/* Index resides in an extra byte to enable larger values than 255 */
1945static int get_extended_index(unsigned long offset)
1946{
1947 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1948}
1949
7c2344c3
MG		 1950
1951static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1952{
7c2344c3
MG		 1953}
1954
37aa5c36
GL		 1955static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1956{
1957 switch (cmd) {
1958 case MLX5_IB_MMAP_WC_PAGE:
1959 return "WC";
1960 case MLX5_IB_MMAP_REGULAR_PAGE:
1961 return "best effort WC";
1962 case MLX5_IB_MMAP_NC_PAGE:
1963 return "NC";
24da0016
AL		 1964 case MLX5_IB_MMAP_DEVICE_MEM:
1965 return "Device Memory";
37aa5c36
GL		 1966 default:
1967 return NULL;
1968 }
1969}
1970
5c99eaec
FD		 1971static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
1972 struct vm_area_struct *vma,
1973 struct mlx5_ib_ucontext *context)
1974{
5c99eaec
FD		 1975 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1976 return -EINVAL;
1977
1978 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
1979 return -EOPNOTSUPP;
1980
1981 if (vma->vm_flags & VM_WRITE)
1982 return -EPERM;
1983
1984 if (!dev->mdev->clock_info_page)
1985 return -EOPNOTSUPP;
1986
e2cd1d1a
JG		 1987 return rdma_user_mmap_page(&context->ibucontext, vma,
1988 dev->mdev->clock_info_page, PAGE_SIZE);
5c99eaec
FD		 1989}
1990
37aa5c36 1991static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 1992 struct vm_area_struct *vma,
1993 struct mlx5_ib_ucontext *context)
37aa5c36 1994{
2f5ff264 1995 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 1996 int err;
1997 unsigned long idx;
aa09ea6e 1998 phys_addr_t pfn;
37aa5c36 1999 pgprot_t prot;
4ed131d0
YH		 2000 u32 bfreg_dyn_idx = 0;
2001 u32 uar_index;
2002 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2003 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2004 bfregi->num_static_sys_pages;
b037c29a
EC		 2005
2006 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2007 return -EINVAL;
2008
4ed131d0
YH		 2009 if (dyn_uar)
2010 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2011 else
2012 idx = get_index(vma->vm_pgoff);
2013
2014 if (idx >= max_valid_idx) {
2015 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2016 idx, max_valid_idx);
b037c29a
EC		 2017 return -EINVAL;
2018 }
37aa5c36
GL		 2019
2020 switch (cmd) {
2021 case MLX5_IB_MMAP_WC_PAGE:
4ed131d0 2022 case MLX5_IB_MMAP_ALLOC_WC:
37aa5c36
GL		 2023/* Some architectures don't support WC memory */
2024#if defined(CONFIG_X86)
2025 if (!pat_enabled())
2026 return -EPERM;
2027#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2028 return -EPERM;
2029#endif
2030 /* fall through */
2031 case MLX5_IB_MMAP_REGULAR_PAGE:
2032 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2033 prot = pgprot_writecombine(vma->vm_page_prot);
2034 break;
2035 case MLX5_IB_MMAP_NC_PAGE:
2036 prot = pgprot_noncached(vma->vm_page_prot);
2037 break;
2038 default:
2039 return -EINVAL;
2040 }
2041
4ed131d0
YH		 2042 if (dyn_uar) {
2043 int uars_per_page;
2044
2045 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2046 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2047 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2048 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2049 bfreg_dyn_idx, bfregi->total_num_bfregs);
2050 return -EINVAL;
2051 }
2052
2053 mutex_lock(&bfregi->lock);
2054 /* Fail if uar already allocated, first bfreg index of each
2055 * page holds its count.
2056 */
2057 if (bfregi->count[bfreg_dyn_idx]) {
2058 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2059 mutex_unlock(&bfregi->lock);
2060 return -EINVAL;
2061 }
2062
2063 bfregi->count[bfreg_dyn_idx]++;
2064 mutex_unlock(&bfregi->lock);
2065
2066 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2067 if (err) {
2068 mlx5_ib_warn(dev, "UAR alloc failed\n");
2069 goto free_bfreg;
2070 }
2071 } else {
2072 uar_index = bfregi->sys_pages[idx];
2073 }
2074
2075 pfn = uar_index2pfn(dev, uar_index);
37aa5c36
GL		 2076 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2077
e2cd1d1a
JG		 2078 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2079 prot);
37aa5c36 2080 if (err) {
8f062287 2081 mlx5_ib_err(dev,
e2cd1d1a 2082 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
8f062287 2083 err, mmap_cmd2str(cmd));
4ed131d0 2084 goto err;
37aa5c36
GL		 2085 }
2086
4ed131d0
YH		 2087 if (dyn_uar)
2088 bfregi->sys_pages[idx] = uar_index;
2089 return 0;
2090
2091err:
2092 if (!dyn_uar)
2093 return err;
2094
2095 mlx5_cmd_free_uar(dev->mdev, idx);
2096
2097free_bfreg:
2098 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2099
2100 return err;
37aa5c36
GL		 2101}
2102
24da0016
AL		 2103static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2104{
2105 struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2106 struct mlx5_ib_dev *dev = to_mdev(context->device);
2107 u16 page_idx = get_extended_index(vma->vm_pgoff);
2108 size_t map_size = vma->vm_end - vma->vm_start;
2109 u32 npages = map_size >> PAGE_SHIFT;
2110 phys_addr_t pfn;
24da0016
AL		 2111
2112 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2113 page_idx + npages)
2114 return -EINVAL;
2115
2116 pfn = ((pci_resource_start(dev->mdev->pdev, 0) +
2117 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2118 PAGE_SHIFT) +
2119 page_idx;
e2cd1d1a
JG		 2120 return rdma_user_mmap_io(context, vma, pfn, map_size,
2121 pgprot_writecombine(vma->vm_page_prot));
24da0016
AL		 2122}
2123
e126ba97
EC		 2124static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2125{
2126 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2127 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 2128 unsigned long command;
e126ba97
EC		 2129 phys_addr_t pfn;
2130
2131 command = get_command(vma->vm_pgoff);
2132 switch (command) {
37aa5c36
GL		 2133 case MLX5_IB_MMAP_WC_PAGE:
2134 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 2135 case MLX5_IB_MMAP_REGULAR_PAGE:
4ed131d0 2136 case MLX5_IB_MMAP_ALLOC_WC:
7c2344c3 2137 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 2138
2139 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2140 return -ENOSYS;
2141
d69e3bcf 2142 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 2143 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2144 return -EINVAL;
2145
6cbac1e4 2146 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 2147 return -EPERM;
2148
2149 /* Don't expose to user-space information it shouldn't have */
2150 if (PAGE_SIZE > 4096)
2151 return -EOPNOTSUPP;
2152
2153 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2154 pfn = (dev->mdev->iseg_base +
2155 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2156 PAGE_SHIFT;
2157 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2158 PAGE_SIZE, vma->vm_page_prot))
2159 return -EAGAIN;
d69e3bcf 2160 break;
5c99eaec
FD		 2161 case MLX5_IB_MMAP_CLOCK_INFO:
2162 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
d69e3bcf 2163
24da0016
AL		 2164 case MLX5_IB_MMAP_DEVICE_MEM:
2165 return dm_mmap(ibcontext, vma);
2166
e126ba97
EC		 2167 default:
2168 return -EINVAL;
2169 }
2170
2171 return 0;
2172}
2173
24da0016
AL		 2174struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2175 struct ib_ucontext *context,
2176 struct ib_dm_alloc_attr *attr,
2177 struct uverbs_attr_bundle *attrs)
2178{
2179 u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2180 struct mlx5_memic *memic = &to_mdev(ibdev)->memic;
2181 phys_addr_t memic_addr;
2182 struct mlx5_ib_dm *dm;
2183 u64 start_offset;
2184 u32 page_idx;
2185 int err;
2186
2187 dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2188 if (!dm)
2189 return ERR_PTR(-ENOMEM);
2190
2191 mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n",
2192 attr->length, act_size, attr->alignment);
2193
2194 err = mlx5_cmd_alloc_memic(memic, &memic_addr,
2195 act_size, attr->alignment);
2196 if (err)
2197 goto err_free;
2198
2199 start_offset = memic_addr & ~PAGE_MASK;
2200 page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) -
2201 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2202 PAGE_SHIFT;
2203
2204 err = uverbs_copy_to(attrs,
2205 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2206 &start_offset, sizeof(start_offset));
2207 if (err)
2208 goto err_dealloc;
2209
2210 err = uverbs_copy_to(attrs,
2211 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2212 &page_idx, sizeof(page_idx));
2213 if (err)
2214 goto err_dealloc;
2215
2216 bitmap_set(to_mucontext(context)->dm_pages, page_idx,
2217 DIV_ROUND_UP(act_size, PAGE_SIZE));
2218
2219 dm->dev_addr = memic_addr;
2220
2221 return &dm->ibdm;
2222
2223err_dealloc:
2224 mlx5_cmd_dealloc_memic(memic, memic_addr,
2225 act_size);
2226err_free:
2227 kfree(dm);
2228 return ERR_PTR(err);
2229}
2230
2231int mlx5_ib_dealloc_dm(struct ib_dm *ibdm)
2232{
2233 struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic;
2234 struct mlx5_ib_dm *dm = to_mdm(ibdm);
2235 u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE);
2236 u32 page_idx;
2237 int ret;
2238
2239 ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size);
2240 if (ret)
2241 return ret;
2242
2243 page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) -
2244 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2245 PAGE_SHIFT;
2246 bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages,
2247 page_idx,
2248 DIV_ROUND_UP(act_size, PAGE_SIZE));
2249
2250 kfree(dm);
2251
2252 return 0;
2253}
2254
e126ba97
EC		 2255static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2256 struct ib_ucontext *context,
2257 struct ib_udata *udata)
2258{
2259 struct mlx5_ib_alloc_pd_resp resp;
2260 struct mlx5_ib_pd *pd;
2261 int err;
a1069c1c
YH		 2262 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2263 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
2264 u16 uid = 0;
e126ba97 2265
8cbfaac3 2266 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
e126ba97
EC		 2267 if (!pd)
2268 return ERR_PTR(-ENOMEM);
2269
58895f0d 2270 uid = context ? to_mucontext(context)->devx_uid : 0;
a1069c1c
YH		 2271 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2272 MLX5_SET(alloc_pd_in, in, uid, uid);
2273 err = mlx5_cmd_exec(to_mdev(ibdev)->mdev, in, sizeof(in),
2274 out, sizeof(out));
e126ba97
EC		 2275 if (err) {
2276 kfree(pd);
2277 return ERR_PTR(err);
2278 }
2279
a1069c1c
YH		 2280 pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2281 pd->uid = uid;
e126ba97
EC		 2282 if (context) {
2283 resp.pdn = pd->pdn;
2284 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
a1069c1c 2285 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
e126ba97
EC		 2286 kfree(pd);
2287 return ERR_PTR(-EFAULT);
2288 }
e126ba97
EC		 2289 }
2290
2291 return &pd->ibpd;
2292}
2293
2294static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2295{
2296 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2297 struct mlx5_ib_pd *mpd = to_mpd(pd);
2298
a1069c1c 2299 mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
e126ba97
EC		 2300 kfree(mpd);
2301
2302 return 0;
2303}
2304
466fa6d2
MG		 2305enum {
2306 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2307 MATCH_CRITERIA_ENABLE_MISC_BIT,
71c6e863
AL		 2308 MATCH_CRITERIA_ENABLE_INNER_BIT,
2309 MATCH_CRITERIA_ENABLE_MISC2_BIT
466fa6d2
MG		 2310};
2311
2312#define HEADER_IS_ZERO(match_criteria, headers) \
2313 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2314 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 2315
466fa6d2 2316static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 2317{
466fa6d2 2318 u8 match_criteria_enable;
038d2ef8 2319
466fa6d2
MG		 2320 match_criteria_enable =
2321 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2322 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2323 match_criteria_enable |=
2324 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2325 MATCH_CRITERIA_ENABLE_MISC_BIT;
2326 match_criteria_enable |=
2327 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2328 MATCH_CRITERIA_ENABLE_INNER_BIT;
71c6e863
AL		 2329 match_criteria_enable |=
2330 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2331 MATCH_CRITERIA_ENABLE_MISC2_BIT;
466fa6d2
MG		 2332
2333 return match_criteria_enable;
038d2ef8
MG		 2334}
2335
6113cc44 2336static int set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
ca0d4753 2337{
6113cc44
MG		 2338 u8 entry_mask;
2339 u8 entry_val;
2340 int err = 0;
2341
2342 if (!mask)
2343 goto out;
2344
2345 entry_mask = MLX5_GET(fte_match_set_lyr_2_4, outer_c,
2346 ip_protocol);
2347 entry_val = MLX5_GET(fte_match_set_lyr_2_4, outer_v,
2348 ip_protocol);
2349 if (!entry_mask) {
2350 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2351 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2352 goto out;
2353 }
2354 /* Don't override existing ip protocol */
2355 if (mask != entry_mask || val != entry_val)
2356 err = -EINVAL;
2357out:
2358 return err;
038d2ef8
MG		 2359}
2360
37da2a03 2361static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2d1e697e
MR		 2362 bool inner)
2363{
2364 if (inner) {
2365 MLX5_SET(fte_match_set_misc,
2366 misc_c, inner_ipv6_flow_label, mask);
2367 MLX5_SET(fte_match_set_misc,
2368 misc_v, inner_ipv6_flow_label, val);
2369 } else {
2370 MLX5_SET(fte_match_set_misc,
2371 misc_c, outer_ipv6_flow_label, mask);
2372 MLX5_SET(fte_match_set_misc,
2373 misc_v, outer_ipv6_flow_label, val);
2374 }
2375}
2376
ca0d4753
MG		 2377static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2378{
2379 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2380 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2381 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2382 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2383}
2384
71c6e863
AL		 2385static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2386{
2387 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2388 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2389 return -EOPNOTSUPP;
2390
2391 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2392 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2393 return -EOPNOTSUPP;
2394
2395 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2396 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2397 return -EOPNOTSUPP;
2398
2399 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2400 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2401 return -EOPNOTSUPP;
2402
2403 return 0;
2404}
2405
c47ac6ae
MG		 2406#define LAST_ETH_FIELD vlan_tag
2407#define LAST_IB_FIELD sl
ca0d4753 2408#define LAST_IPV4_FIELD tos
466fa6d2 2409#define LAST_IPV6_FIELD traffic_class
c47ac6ae 2410#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 2411#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 2412#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 2413#define LAST_DROP_FIELD size
3b3233fb 2414#define LAST_COUNTERS_FIELD counters
c47ac6ae
MG		 2415
2416/* Field is the last supported field */
2417#define FIELDS_NOT_SUPPORTED(filter, field)\
2418 memchr_inv((void *)&filter.field +\
2419 sizeof(filter.field), 0,\
2420 sizeof(filter) -\
2421 offsetof(typeof(filter), field) -\
2422 sizeof(filter.field))
2423
2ea26203
MB		 2424int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
2425 bool is_egress,
2426 struct mlx5_flow_act *action)
802c2125 2427{
802c2125
AY		 2428
2429 switch (maction->ib_action.type) {
2430 case IB_FLOW_ACTION_ESP:
501f14e3
MB		 2431 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2432 MLX5_FLOW_CONTEXT_ACTION_DECRYPT))
2433 return -EINVAL;
802c2125
AY		 2434 /* Currently only AES_GCM keymat is supported by the driver */
2435 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2ea26203 2436 action->action |= is_egress ?
802c2125
AY		 2437 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2438 MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2439 return 0;
b1085be3
MB		 2440 case IB_FLOW_ACTION_UNSPECIFIED:
2441 if (maction->flow_action_raw.sub_type ==
2442 MLX5_IB_FLOW_ACTION_MODIFY_HEADER) {
501f14e3
MB		 2443 if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2444 return -EINVAL;
b1085be3
MB		 2445 action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2446 action->modify_id = maction->flow_action_raw.action_id;
2447 return 0;
2448 }
10a30896
MB		 2449 if (maction->flow_action_raw.sub_type ==
2450 MLX5_IB_FLOW_ACTION_DECAP) {
501f14e3
MB		 2451 if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP)
2452 return -EINVAL;
10a30896
MB		 2453 action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2454 return 0;
2455 }
e806f932
MB		 2456 if (maction->flow_action_raw.sub_type ==
2457 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) {
501f14e3
MB		 2458 if (action->action &
2459 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT)
2460 return -EINVAL;
e806f932
MB		 2461 action->action |=
2462 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
2463 action->reformat_id =
2464 maction->flow_action_raw.action_id;
2465 return 0;
2466 }
b1085be3 2467 /* fall through */
802c2125
AY		 2468 default:
2469 return -EOPNOTSUPP;
2470 }
2471}
2472
19cc7524
AL		 2473static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2474 u32 *match_v, const union ib_flow_spec *ib_spec,
802c2125 2475 const struct ib_flow_attr *flow_attr,
71c6e863 2476 struct mlx5_flow_act *action, u32 prev_type)
038d2ef8 2477{
466fa6d2
MG		 2478 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2479 misc_parameters);
2480 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2481 misc_parameters);
71c6e863
AL		 2482 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2483 misc_parameters_2);
2484 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2485 misc_parameters_2);
2d1e697e
MR		 2486 void *headers_c;
2487 void *headers_v;
19cc7524 2488 int match_ipv;
802c2125 2489 int ret;
2d1e697e
MR		 2490
2491 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2492 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2493 inner_headers);
2494 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2495 inner_headers);
19cc7524
AL		 2496 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2497 ft_field_support.inner_ip_version);
2d1e697e
MR		 2498 } else {
2499 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2500 outer_headers);
2501 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2502 outer_headers);
19cc7524
AL		 2503 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2504 ft_field_support.outer_ip_version);
2d1e697e 2505 }
466fa6d2 2506
2d1e697e 2507 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 2508 case IB_FLOW_SPEC_ETH:
c47ac6ae 2509 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 2510 return -EOPNOTSUPP;
038d2ef8 2511
2d1e697e 2512 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2513 dmac_47_16),
2514 ib_spec->eth.mask.dst_mac);
2d1e697e 2515 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2516 dmac_47_16),
2517 ib_spec->eth.val.dst_mac);
2518
2d1e697e 2519 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 2520 smac_47_16),
2521 ib_spec->eth.mask.src_mac);
2d1e697e 2522 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 2523 smac_47_16),
2524 ib_spec->eth.val.src_mac);
2525
038d2ef8 2526 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 2527 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 2528 cvlan_tag, 1);
2d1e697e 2529 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 2530 cvlan_tag, 1);
038d2ef8 2531
2d1e697e 2532 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2533 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 2534 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2535 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2536
2d1e697e 2537 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2538 first_cfi,
2539 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 2540 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2541 first_cfi,
2542 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2543
2d1e697e 2544 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2545 first_prio,
2546 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 2547 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2548 first_prio,
2549 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2550 }
2d1e697e 2551 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2552 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 2553 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2554 ethertype, ntohs(ib_spec->eth.val.ether_type));
2555 break;
2556 case IB_FLOW_SPEC_IPV4:
c47ac6ae 2557 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 2558 return -EOPNOTSUPP;
038d2ef8 2559
19cc7524
AL		 2560 if (match_ipv) {
2561 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2562 ip_version, 0xf);
2563 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2564 ip_version, MLX5_FS_IPV4_VERSION);
19cc7524
AL		 2565 } else {
2566 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2567 ethertype, 0xffff);
2568 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2569 ethertype, ETH_P_IP);
2570 }
038d2ef8 2571
2d1e697e 2572 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2573 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2574 &ib_spec->ipv4.mask.src_ip,
2575 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 2576 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2577 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2578 &ib_spec->ipv4.val.src_ip,
2579 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 2580 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2581 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2582 &ib_spec->ipv4.mask.dst_ip,
2583 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 2584 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2585 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2586 &ib_spec->ipv4.val.dst_ip,
2587 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 2588
2d1e697e 2589 set_tos(headers_c, headers_v,
ca0d4753
MG		 2590 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2591
6113cc44
MG		 2592 if (set_proto(headers_c, headers_v,
2593 ib_spec->ipv4.mask.proto,
2594 ib_spec->ipv4.val.proto))
2595 return -EINVAL;
038d2ef8 2596 break;
026bae0c 2597 case IB_FLOW_SPEC_IPV6:
c47ac6ae 2598 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 2599 return -EOPNOTSUPP;
026bae0c 2600
19cc7524
AL		 2601 if (match_ipv) {
2602 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2603 ip_version, 0xf);
2604 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2605 ip_version, MLX5_FS_IPV6_VERSION);
19cc7524
AL		 2606 } else {
2607 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2608 ethertype, 0xffff);
2609 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2610 ethertype, ETH_P_IPV6);
2611 }
026bae0c 2612
2d1e697e 2613 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2614 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2615 &ib_spec->ipv6.mask.src_ip,
2616 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2617 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2618 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2619 &ib_spec->ipv6.val.src_ip,
2620 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2621 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2622 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2623 &ib_spec->ipv6.mask.dst_ip,
2624 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2625 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2626 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2627 &ib_spec->ipv6.val.dst_ip,
2628 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2629
2d1e697e 2630 set_tos(headers_c, headers_v,
466fa6d2
MG		 2631 ib_spec->ipv6.mask.traffic_class,
2632 ib_spec->ipv6.val.traffic_class);
2633
6113cc44
MG		 2634 if (set_proto(headers_c, headers_v,
2635 ib_spec->ipv6.mask.next_hdr,
2636 ib_spec->ipv6.val.next_hdr))
2637 return -EINVAL;
466fa6d2 2638
2d1e697e
MR		 2639 set_flow_label(misc_params_c, misc_params_v,
2640 ntohl(ib_spec->ipv6.mask.flow_label),
2641 ntohl(ib_spec->ipv6.val.flow_label),
2642 ib_spec->type & IB_FLOW_SPEC_INNER);
802c2125
AY		 2643 break;
2644 case IB_FLOW_SPEC_ESP:
2645 if (ib_spec->esp.mask.seq)
2646 return -EOPNOTSUPP;
2d1e697e 2647
802c2125
AY		 2648 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2649 ntohl(ib_spec->esp.mask.spi));
2650 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2651 ntohl(ib_spec->esp.val.spi));
026bae0c 2652 break;
038d2ef8 2653 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2654 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2655 LAST_TCP_UDP_FIELD))
1ffd3a26 2656 return -EOPNOTSUPP;
038d2ef8 2657
6113cc44
MG		 2658 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_TCP))
2659 return -EINVAL;
038d2ef8 2660
2d1e697e 2661 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2662 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2663 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2664 ntohs(ib_spec->tcp_udp.val.src_port));
2665
2d1e697e 2666 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2667 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2668 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2669 ntohs(ib_spec->tcp_udp.val.dst_port));
2670 break;
2671 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2672 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2673 LAST_TCP_UDP_FIELD))
1ffd3a26 2674 return -EOPNOTSUPP;
038d2ef8 2675
6113cc44
MG		 2676 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_UDP))
2677 return -EINVAL;
038d2ef8 2678
2d1e697e 2679 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2680 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2681 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2682 ntohs(ib_spec->tcp_udp.val.src_port));
2683
2d1e697e 2684 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2685 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2686 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2687 ntohs(ib_spec->tcp_udp.val.dst_port));
2688 break;
da2f22ae
AL		 2689 case IB_FLOW_SPEC_GRE:
2690 if (ib_spec->gre.mask.c_ks_res0_ver)
2691 return -EOPNOTSUPP;
2692
6113cc44
MG		 2693 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_GRE))
2694 return -EINVAL;
2695
da2f22ae
AL		 2696 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2697 0xff);
2698 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2699 IPPROTO_GRE);
2700
2701 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
a93b632c 2702 ntohs(ib_spec->gre.mask.protocol));
da2f22ae
AL		 2703 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2704 ntohs(ib_spec->gre.val.protocol));
2705
2706 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
5886a96a 2707 gre_key.nvgre.hi),
da2f22ae
AL		 2708 &ib_spec->gre.mask.key,
2709 sizeof(ib_spec->gre.mask.key));
2710 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
5886a96a 2711 gre_key.nvgre.hi),
da2f22ae
AL		 2712 &ib_spec->gre.val.key,
2713 sizeof(ib_spec->gre.val.key));
2714 break;
71c6e863
AL		 2715 case IB_FLOW_SPEC_MPLS:
2716 switch (prev_type) {
2717 case IB_FLOW_SPEC_UDP:
2718 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2719 ft_field_support.outer_first_mpls_over_udp),
2720 &ib_spec->mpls.mask.tag))
2721 return -EOPNOTSUPP;
2722
2723 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2724 outer_first_mpls_over_udp),
2725 &ib_spec->mpls.val.tag,
2726 sizeof(ib_spec->mpls.val.tag));
2727 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2728 outer_first_mpls_over_udp),
2729 &ib_spec->mpls.mask.tag,
2730 sizeof(ib_spec->mpls.mask.tag));
2731 break;
2732 case IB_FLOW_SPEC_GRE:
2733 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2734 ft_field_support.outer_first_mpls_over_gre),
2735 &ib_spec->mpls.mask.tag))
2736 return -EOPNOTSUPP;
2737
2738 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2739 outer_first_mpls_over_gre),
2740 &ib_spec->mpls.val.tag,
2741 sizeof(ib_spec->mpls.val.tag));
2742 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2743 outer_first_mpls_over_gre),
2744 &ib_spec->mpls.mask.tag,
2745 sizeof(ib_spec->mpls.mask.tag));
2746 break;
2747 default:
2748 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2749 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2750 ft_field_support.inner_first_mpls),
2751 &ib_spec->mpls.mask.tag))
2752 return -EOPNOTSUPP;
2753
2754 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2755 inner_first_mpls),
2756 &ib_spec->mpls.val.tag,
2757 sizeof(ib_spec->mpls.val.tag));
2758 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2759 inner_first_mpls),
2760 &ib_spec->mpls.mask.tag,
2761 sizeof(ib_spec->mpls.mask.tag));
2762 } else {
2763 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2764 ft_field_support.outer_first_mpls),
2765 &ib_spec->mpls.mask.tag))
2766 return -EOPNOTSUPP;
2767
2768 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2769 outer_first_mpls),
2770 &ib_spec->mpls.val.tag,
2771 sizeof(ib_spec->mpls.val.tag));
2772 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2773 outer_first_mpls),
2774 &ib_spec->mpls.mask.tag,
2775 sizeof(ib_spec->mpls.mask.tag));
2776 }
2777 }
2778 break;
ffb30d8f
MR		 2779 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2780 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2781 LAST_TUNNEL_FIELD))
1ffd3a26 2782 return -EOPNOTSUPP;
ffb30d8f
MR		 2783
2784 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2785 ntohl(ib_spec->tunnel.mask.tunnel_id));
2786 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2787 ntohl(ib_spec->tunnel.val.tunnel_id));
2788 break;
2ac693f9
MR		 2789 case IB_FLOW_SPEC_ACTION_TAG:
2790 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2791 LAST_FLOW_TAG_FIELD))
2792 return -EOPNOTSUPP;
2793 if (ib_spec->flow_tag.tag_id >= BIT(24))
2794 return -EINVAL;
2795
075572d4 2796 action->flow_tag = ib_spec->flow_tag.tag_id;
d5634fee 2797 action->flags |= FLOW_ACT_HAS_TAG;
2ac693f9 2798 break;
a22ed86c
SS		 2799 case IB_FLOW_SPEC_ACTION_DROP:
2800 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2801 LAST_DROP_FIELD))
2802 return -EOPNOTSUPP;
075572d4 2803 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
a22ed86c 2804 break;
802c2125 2805 case IB_FLOW_SPEC_ACTION_HANDLE:
2ea26203
MB		 2806 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act),
2807 flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action);
802c2125
AY		 2808 if (ret)
2809 return ret;
2810 break;
3b3233fb
RS		 2811 case IB_FLOW_SPEC_ACTION_COUNT:
2812 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
2813 LAST_COUNTERS_FIELD))
2814 return -EOPNOTSUPP;
2815
2816 /* for now support only one counters spec per flow */
2817 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
2818 return -EINVAL;
2819
2820 action->counters = ib_spec->flow_count.counters;
2821 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2822 break;
038d2ef8
MG		 2823 default:
2824 return -EINVAL;
2825 }
2826
2827 return 0;
2828}
2829
2830/* If a flow could catch both multicast and unicast packets,
2831 * it won't fall into the multicast flow steering table and this rule
2832 * could steal other multicast packets.
2833 */
a550ddfc 2834static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
038d2ef8 2835{
81e30880 2836 union ib_flow_spec *flow_spec;
038d2ef8
MG		 2837
2838 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 2839 ib_attr->num_of_specs < 1)
2840 return false;
2841
81e30880
YH		 2842 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2843 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2844 struct ib_flow_spec_ipv4 *ipv4_spec;
2845
2846 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2847 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2848 return true;
2849
038d2ef8 2850 return false;
81e30880
YH		 2851 }
2852
2853 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2854 struct ib_flow_spec_eth *eth_spec;
2855
2856 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2857 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2858 is_multicast_ether_addr(eth_spec->val.dst_mac);
2859 }
038d2ef8 2860
81e30880 2861 return false;
038d2ef8
MG		 2862}
2863
802c2125
AY		 2864enum valid_spec {
2865 VALID_SPEC_INVALID,
2866 VALID_SPEC_VALID,
2867 VALID_SPEC_NA,
2868};
2869
2870static enum valid_spec
2871is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
2872 const struct mlx5_flow_spec *spec,
2873 const struct mlx5_flow_act *flow_act,
2874 bool egress)
2875{
2876 const u32 *match_c = spec->match_criteria;
2877 bool is_crypto =
2878 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2879 MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
2880 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
2881 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
2882
2883 /*
2884 * Currently only crypto is supported in egress, when regular egress
2885 * rules would be supported, always return VALID_SPEC_NA.
2886 */
2887 if (!is_crypto)
78dd0c43 2888 return VALID_SPEC_NA;
802c2125
AY		 2889
2890 return is_crypto && is_ipsec &&
d5634fee 2891 (!egress || (!is_drop && !(flow_act->flags & FLOW_ACT_HAS_TAG))) ?
802c2125
AY		 2892 VALID_SPEC_VALID : VALID_SPEC_INVALID;
2893}
2894
2895static bool is_valid_spec(struct mlx5_core_dev *mdev,
2896 const struct mlx5_flow_spec *spec,
2897 const struct mlx5_flow_act *flow_act,
2898 bool egress)
2899{
2900 /* We curretly only support ipsec egress flow */
2901 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
2902}
2903
19cc7524
AL		 2904static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2905 const struct ib_flow_attr *flow_attr,
0f750966 2906 bool check_inner)
038d2ef8
MG		 2907{
2908 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 2909 int match_ipv = check_inner ?
2910 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2911 ft_field_support.inner_ip_version) :
2912 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2913 ft_field_support.outer_ip_version);
0f750966
AL		 2914 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2915 bool ipv4_spec_valid, ipv6_spec_valid;
2916 unsigned int ip_spec_type = 0;
2917 bool has_ethertype = false;
038d2ef8 2918 unsigned int spec_index;
0f750966
AL		 2919 bool mask_valid = true;
2920 u16 eth_type = 0;
2921 bool type_valid;
038d2ef8
MG		 2922
2923 /* Validate that ethertype is correct */
2924 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 2925 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 2926 ib_spec->eth.mask.ether_type) {
0f750966
AL		 2927 mask_valid = (ib_spec->eth.mask.ether_type ==
2928 htons(0xffff));
2929 has_ethertype = true;
2930 eth_type = ntohs(ib_spec->eth.val.ether_type);
2931 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2932 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2933 ip_spec_type = ib_spec->type;
038d2ef8
MG		 2934 }
2935 ib_spec = (void *)ib_spec + ib_spec->size;
2936 }
0f750966
AL		 2937
2938 type_valid = (!has_ethertype) || (!ip_spec_type);
2939 if (!type_valid && mask_valid) {
2940 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2941 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2942 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2943 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 2944
2945 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2946 (((eth_type == ETH_P_MPLS_UC) ||
2947 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 2948 }
2949
2950 return type_valid;
2951}
2952
19cc7524
AL		 2953static bool is_valid_attr(struct mlx5_core_dev *mdev,
2954 const struct ib_flow_attr *flow_attr)
0f750966 2955{
19cc7524
AL		 2956 return is_valid_ethertype(mdev, flow_attr, false) &&
2957 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 2958}
2959
2960static void put_flow_table(struct mlx5_ib_dev *dev,
2961 struct mlx5_ib_flow_prio *prio, bool ft_added)
2962{
2963 prio->refcount -= !!ft_added;
2964 if (!prio->refcount) {
2965 mlx5_destroy_flow_table(prio->flow_table);
2966 prio->flow_table = NULL;
2967 }
2968}
2969
3b3233fb
RS		 2970static void counters_clear_description(struct ib_counters *counters)
2971{
2972 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
2973
2974 mutex_lock(&mcounters->mcntrs_mutex);
2975 kfree(mcounters->counters_data);
2976 mcounters->counters_data = NULL;
2977 mcounters->cntrs_max_index = 0;
2978 mutex_unlock(&mcounters->mcntrs_mutex);
2979}
2980
038d2ef8
MG		 2981static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2982{
038d2ef8
MG		 2983 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2984 struct mlx5_ib_flow_handler,
2985 ibflow);
2986 struct mlx5_ib_flow_handler *iter, *tmp;
d4be3f44 2987 struct mlx5_ib_dev *dev = handler->dev;
038d2ef8 2988
9a4ca38d 2989 mutex_lock(&dev->flow_db->lock);
038d2ef8
MG		 2990
2991 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 2992 mlx5_del_flow_rules(iter->rule);
cc0e5d42 2993 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 2994 list_del(&iter->list);
2995 kfree(iter);
2996 }
2997
74491de9 2998 mlx5_del_flow_rules(handler->rule);
5497adc6 2999 put_flow_table(dev, handler->prio, true);
3b3233fb
RS		 3000 if (handler->ibcounters &&
3001 atomic_read(&handler->ibcounters->usecnt) == 1)
3002 counters_clear_description(handler->ibcounters);
038d2ef8 3003
3b3233fb 3004 mutex_unlock(&dev->flow_db->lock);
d4be3f44
YH		 3005 if (handler->flow_matcher)
3006 atomic_dec(&handler->flow_matcher->usecnt);
038d2ef8
MG		 3007 kfree(handler);
3008
3009 return 0;
3010}
3011
35d19011
MG		 3012static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
3013{
3014 priority *= 2;
3015 if (!dont_trap)
3016 priority++;
3017 return priority;
3018}
3019
cc0e5d42
MG		 3020enum flow_table_type {
3021 MLX5_IB_FT_RX,
3022 MLX5_IB_FT_TX
3023};
3024
00b7c2ab
MG		 3025#define MLX5_FS_MAX_TYPES 6
3026#define MLX5_FS_MAX_ENTRIES BIT(16)
d4be3f44
YH		 3027
3028static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns,
3029 struct mlx5_ib_flow_prio *prio,
3030 int priority,
4adda112
MB		 3031 int num_entries, int num_groups,
3032 u32 flags)
d4be3f44
YH		 3033{
3034 struct mlx5_flow_table *ft;
3035
3036 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3037 num_entries,
3038 num_groups,
4adda112 3039 0, flags);
d4be3f44
YH		 3040 if (IS_ERR(ft))
3041 return ERR_CAST(ft);
3042
3043 prio->flow_table = ft;
3044 prio->refcount = 0;
3045 return prio;
3046}
3047
038d2ef8 3048static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 3049 struct ib_flow_attr *flow_attr,
3050 enum flow_table_type ft_type)
038d2ef8 3051{
35d19011 3052 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 3053 struct mlx5_flow_namespace *ns = NULL;
3054 struct mlx5_ib_flow_prio *prio;
3055 struct mlx5_flow_table *ft;
dac388ef 3056 int max_table_size;
038d2ef8
MG		 3057 int num_entries;
3058 int num_groups;
4adda112 3059 u32 flags = 0;
038d2ef8 3060 int priority;
038d2ef8 3061
dac388ef
MG		 3062 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3063 log_max_ft_size));
038d2ef8 3064 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
78dd0c43
MB		 3065 enum mlx5_flow_namespace_type fn_type;
3066
3067 if (flow_is_multicast_only(flow_attr) &&
3068 !dont_trap)
038d2ef8
MG		 3069 priority = MLX5_IB_FLOW_MCAST_PRIO;
3070 else
35d19011
MG		 3071 priority = ib_prio_to_core_prio(flow_attr->priority,
3072 dont_trap);
78dd0c43
MB		 3073 if (ft_type == MLX5_IB_FT_RX) {
3074 fn_type = MLX5_FLOW_NAMESPACE_BYPASS;
3075 prio = &dev->flow_db->prios[priority];
4adda112
MB		 3076 if (!dev->rep &&
3077 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3078 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
5c2db53f
MB		 3079 if (!dev->rep &&
3080 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3081 reformat_l3_tunnel_to_l2))
3082 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
78dd0c43
MB		 3083 } else {
3084 max_table_size =
3085 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3086 log_max_ft_size));
3087 fn_type = MLX5_FLOW_NAMESPACE_EGRESS;
3088 prio = &dev->flow_db->egress_prios[priority];
4adda112
MB		 3089 if (!dev->rep &&
3090 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3091 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
78dd0c43
MB		 3092 }
3093 ns = mlx5_get_flow_namespace(dev->mdev, fn_type);
038d2ef8
MG		 3094 num_entries = MLX5_FS_MAX_ENTRIES;
3095 num_groups = MLX5_FS_MAX_TYPES;
038d2ef8
MG		 3096 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3097 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3098 ns = mlx5_get_flow_namespace(dev->mdev,
3099 MLX5_FLOW_NAMESPACE_LEFTOVERS);
3100 build_leftovers_ft_param(&priority,
3101 &num_entries,
3102 &num_groups);
9a4ca38d 3103 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 3104 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3105 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3106 allow_sniffer_and_nic_rx_shared_tir))
3107 return ERR_PTR(-ENOTSUPP);
3108
3109 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3110 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3111 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3112
9a4ca38d 3113 prio = &dev->flow_db->sniffer[ft_type];
cc0e5d42
MG		 3114 priority = 0;
3115 num_entries = 1;
3116 num_groups = 1;
038d2ef8
MG		 3117 }
3118
3119 if (!ns)
3120 return ERR_PTR(-ENOTSUPP);
3121
dac388ef
MG		 3122 if (num_entries > max_table_size)
3123 return ERR_PTR(-ENOMEM);
3124
038d2ef8 3125 ft = prio->flow_table;
d4be3f44 3126 if (!ft)
4adda112
MB		 3127 return _get_prio(ns, prio, priority, num_entries, num_groups,
3128 flags);
038d2ef8 3129
d4be3f44 3130 return prio;
038d2ef8
MG		 3131}
3132
a550ddfc
YH		 3133static void set_underlay_qp(struct mlx5_ib_dev *dev,
3134 struct mlx5_flow_spec *spec,
3135 u32 underlay_qpn)
3136{
3137 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3138 spec->match_criteria,
3139 misc_parameters);
3140 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3141 misc_parameters);
3142
3143 if (underlay_qpn &&
3144 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3145 ft_field_support.bth_dst_qp)) {
3146 MLX5_SET(fte_match_set_misc,
3147 misc_params_v, bth_dst_qp, underlay_qpn);
3148 MLX5_SET(fte_match_set_misc,
3149 misc_params_c, bth_dst_qp, 0xffffff);
3150 }
3151}
3152
5e95af5f
RS		 3153static int read_flow_counters(struct ib_device *ibdev,
3154 struct mlx5_read_counters_attr *read_attr)
3155{
3156 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3157 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3158
3159 return mlx5_fc_query(dev->mdev, fc,
3160 &read_attr->out[IB_COUNTER_PACKETS],
3161 &read_attr->out[IB_COUNTER_BYTES]);
3162}
3163
3164/* flow counters currently expose two counters packets and bytes */
3165#define FLOW_COUNTERS_NUM 2
3b3233fb
RS		 3166static int counters_set_description(struct ib_counters *counters,
3167 enum mlx5_ib_counters_type counters_type,
3168 struct mlx5_ib_flow_counters_desc *desc_data,
3169 u32 ncounters)
3170{
3171 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3172 u32 cntrs_max_index = 0;
3173 int i;
3174
3175 if (counters_type != MLX5_IB_COUNTERS_FLOW)
3176 return -EINVAL;
3177
3178 /* init the fields for the object */
3179 mcounters->type = counters_type;
5e95af5f
RS		 3180 mcounters->read_counters = read_flow_counters;
3181 mcounters->counters_num = FLOW_COUNTERS_NUM;
3b3233fb
RS		 3182 mcounters->ncounters = ncounters;
3183 /* each counter entry have both description and index pair */
3184 for (i = 0; i < ncounters; i++) {
3185 if (desc_data[i].description > IB_COUNTER_BYTES)
3186 return -EINVAL;
3187
3188 if (cntrs_max_index <= desc_data[i].index)
3189 cntrs_max_index = desc_data[i].index + 1;
3190 }
3191
3192 mutex_lock(&mcounters->mcntrs_mutex);
3193 mcounters->counters_data = desc_data;
3194 mcounters->cntrs_max_index = cntrs_max_index;
3195 mutex_unlock(&mcounters->mcntrs_mutex);
3196
3197 return 0;
3198}
3199
3200#define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3201static int flow_counters_set_data(struct ib_counters *ibcounters,
3202 struct mlx5_ib_create_flow *ucmd)
3203{
3204 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3205 struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3206 struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3207 bool hw_hndl = false;
3208 int ret = 0;
3209
3210 if (ucmd && ucmd->ncounters_data != 0) {
3211 cntrs_data = ucmd->data;
3212 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3213 return -EINVAL;
3214
3215 desc_data = kcalloc(cntrs_data->ncounters,
3216 sizeof(*desc_data),
3217 GFP_KERNEL);
3218 if (!desc_data)
3219 return -ENOMEM;
3220
3221 if (copy_from_user(desc_data,
3222 u64_to_user_ptr(cntrs_data->counters_data),
3223 sizeof(*desc_data) * cntrs_data->ncounters)) {
3224 ret = -EFAULT;
3225 goto free;
3226 }
3227 }
3228
3229 if (!mcounters->hw_cntrs_hndl) {
3230 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3231 to_mdev(ibcounters->device)->mdev, false);
e31abf76 3232 if (IS_ERR(mcounters->hw_cntrs_hndl)) {
3233 ret = PTR_ERR(mcounters->hw_cntrs_hndl);
3b3233fb
RS		 3234 goto free;
3235 }
3236 hw_hndl = true;
3237 }
3238
3239 if (desc_data) {
3240 /* counters already bound to at least one flow */
3241 if (mcounters->cntrs_max_index) {
3242 ret = -EINVAL;
3243 goto free_hndl;
3244 }
3245
3246 ret = counters_set_description(ibcounters,
3247 MLX5_IB_COUNTERS_FLOW,
3248 desc_data,
3249 cntrs_data->ncounters);
3250 if (ret)
3251 goto free_hndl;
3252
3253 } else if (!mcounters->cntrs_max_index) {
3254 /* counters not bound yet, must have udata passed */
3255 ret = -EINVAL;
3256 goto free_hndl;
3257 }
3258
3259 return 0;
3260
3261free_hndl:
3262 if (hw_hndl) {
3263 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3264 mcounters->hw_cntrs_hndl);
3265 mcounters->hw_cntrs_hndl = NULL;
3266 }
3267free:
3268 kfree(desc_data);
3269 return ret;
3270}
3271
a550ddfc
YH		 3272static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3273 struct mlx5_ib_flow_prio *ft_prio,
3274 const struct ib_flow_attr *flow_attr,
3275 struct mlx5_flow_destination *dst,
3b3233fb
RS		 3276 u32 underlay_qpn,
3277 struct mlx5_ib_create_flow *ucmd)
038d2ef8
MG		 3278{
3279 struct mlx5_flow_table *ft = ft_prio->flow_table;
3280 struct mlx5_ib_flow_handler *handler;
075572d4 3281 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
c5bb1730 3282 struct mlx5_flow_spec *spec;
3b3233fb
RS		 3283 struct mlx5_flow_destination dest_arr[2] = {};
3284 struct mlx5_flow_destination *rule_dst = dest_arr;
dd063d0e 3285 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 3286 unsigned int spec_index;
71c6e863 3287 u32 prev_type = 0;
038d2ef8 3288 int err = 0;
3b3233fb 3289 int dest_num = 0;
802c2125 3290 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
038d2ef8 3291
19cc7524 3292 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 3293 return ERR_PTR(-EINVAL);
3294
78dd0c43
MB		 3295 if (dev->rep && is_egress)
3296 return ERR_PTR(-EINVAL);
3297
1b9a07ee 3298 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 3299 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 3300 if (!handler || !spec) {
038d2ef8
MG		 3301 err = -ENOMEM;
3302 goto free;
3303 }
3304
3305 INIT_LIST_HEAD(&handler->list);
3b3233fb
RS		 3306 if (dst) {
3307 memcpy(&dest_arr[0], dst, sizeof(*dst));
3308 dest_num++;
3309 }
038d2ef8
MG		 3310
3311 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
19cc7524 3312 err = parse_flow_attr(dev->mdev, spec->match_criteria,
a22ed86c 3313 spec->match_value,
71c6e863
AL		 3314 ib_flow, flow_attr, &flow_act,
3315 prev_type);
038d2ef8
MG		 3316 if (err < 0)
3317 goto free;
3318
71c6e863 3319 prev_type = ((union ib_flow_spec *)ib_flow)->type;
038d2ef8
MG		 3320 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3321 }
3322
a550ddfc
YH		 3323 if (!flow_is_multicast_only(flow_attr))
3324 set_underlay_qp(dev, spec, underlay_qpn);
3325
018a94ee
MB		 3326 if (dev->rep) {
3327 void *misc;
3328
3329 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3330 misc_parameters);
3331 MLX5_SET(fte_match_set_misc, misc, source_port,
3332 dev->rep->vport);
3333 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3334 misc_parameters);
3335 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3336 }
3337
466fa6d2 3338 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
802c2125
AY		 3339
3340 if (is_egress &&
3341 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3342 err = -EINVAL;
3343 goto free;
3344 }
3345
3b3233fb 3346 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
171c7625
MB		 3347 struct mlx5_ib_mcounters *mcounters;
3348
3b3233fb
RS		 3349 err = flow_counters_set_data(flow_act.counters, ucmd);
3350 if (err)
3351 goto free;
3352
171c7625 3353 mcounters = to_mcounters(flow_act.counters);
3b3233fb
RS		 3354 handler->ibcounters = flow_act.counters;
3355 dest_arr[dest_num].type =
3356 MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625
MB		 3357 dest_arr[dest_num].counter_id =
3358 mlx5_fc_id(mcounters->hw_cntrs_hndl);
3b3233fb
RS		 3359 dest_num++;
3360 }
3361
075572d4 3362 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3b3233fb
RS		 3363 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) {
3364 rule_dst = NULL;
3365 dest_num = 0;
3366 }
a22ed86c 3367 } else {
802c2125
AY		 3368 if (is_egress)
3369 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3370 else
3371 flow_act.action |=
3b3233fb 3372 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
802c2125 3373 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
a22ed86c 3374 }
2ac693f9 3375
d5634fee 3376 if ((flow_act.flags & FLOW_ACT_HAS_TAG) &&
2ac693f9
MR		 3377 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3378 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3379 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
075572d4 3380 flow_act.flow_tag, flow_attr->type);
2ac693f9
MR		 3381 err = -EINVAL;
3382 goto free;
3383 }
74491de9 3384 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 3385 &flow_act,
a22ed86c 3386 rule_dst, dest_num);
038d2ef8
MG		 3387
3388 if (IS_ERR(handler->rule)) {
3389 err = PTR_ERR(handler->rule);
3390 goto free;
3391 }
3392
d9d4980a 3393 ft_prio->refcount++;
5497adc6 3394 handler->prio = ft_prio;
d4be3f44 3395 handler->dev = dev;
038d2ef8
MG		 3396
3397 ft_prio->flow_table = ft;
3398free:
3b3233fb
RS		 3399 if (err && handler) {
3400 if (handler->ibcounters &&
3401 atomic_read(&handler->ibcounters->usecnt) == 1)
3402 counters_clear_description(handler->ibcounters);
038d2ef8 3403 kfree(handler);
3b3233fb 3404 }
c5bb1730 3405 kvfree(spec);
038d2ef8
MG		 3406 return err ? ERR_PTR(err) : handler;
3407}
3408
a550ddfc
YH		 3409static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3410 struct mlx5_ib_flow_prio *ft_prio,
3411 const struct ib_flow_attr *flow_attr,
3412 struct mlx5_flow_destination *dst)
3413{
3b3233fb 3414 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
a550ddfc
YH		 3415}
3416
35d19011
MG		 3417static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3418 struct mlx5_ib_flow_prio *ft_prio,
3419 struct ib_flow_attr *flow_attr,
3420 struct mlx5_flow_destination *dst)
3421{
3422 struct mlx5_ib_flow_handler *handler_dst = NULL;
3423 struct mlx5_ib_flow_handler *handler = NULL;
3424
3425 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3426 if (!IS_ERR(handler)) {
3427 handler_dst = create_flow_rule(dev, ft_prio,
3428 flow_attr, dst);
3429 if (IS_ERR(handler_dst)) {
74491de9 3430 mlx5_del_flow_rules(handler->rule);
d9d4980a 3431 ft_prio->refcount--;
35d19011
MG		 3432 kfree(handler);
3433 handler = handler_dst;
3434 } else {
3435 list_add(&handler_dst->list, &handler->list);
3436 }
3437 }
3438
3439 return handler;
3440}
038d2ef8
MG		 3441enum {
3442 LEFTOVERS_MC,
3443 LEFTOVERS_UC,
3444};
3445
3446static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3447 struct mlx5_ib_flow_prio *ft_prio,
3448 struct ib_flow_attr *flow_attr,
3449 struct mlx5_flow_destination *dst)
3450{
3451 struct mlx5_ib_flow_handler *handler_ucast = NULL;
3452 struct mlx5_ib_flow_handler *handler = NULL;
3453
3454 static struct {
3455 struct ib_flow_attr flow_attr;
3456 struct ib_flow_spec_eth eth_flow;
3457 } leftovers_specs[] = {
3458 [LEFTOVERS_MC] = {
3459 .flow_attr = {
3460 .num_of_specs = 1,
3461 .size = sizeof(leftovers_specs[0])
3462 },
3463 .eth_flow = {
3464 .type = IB_FLOW_SPEC_ETH,
3465 .size = sizeof(struct ib_flow_spec_eth),
3466 .mask = {.dst_mac = {0x1} },
3467 .val = {.dst_mac = {0x1} }
3468 }
3469 },
3470 [LEFTOVERS_UC] = {
3471 .flow_attr = {
3472 .num_of_specs = 1,
3473 .size = sizeof(leftovers_specs[0])
3474 },
3475 .eth_flow = {
3476 .type = IB_FLOW_SPEC_ETH,
3477 .size = sizeof(struct ib_flow_spec_eth),
3478 .mask = {.dst_mac = {0x1} },
3479 .val = {.dst_mac = {} }
3480 }
3481 }
3482 };
3483
3484 handler = create_flow_rule(dev, ft_prio,
3485 &leftovers_specs[LEFTOVERS_MC].flow_attr,
3486 dst);
3487 if (!IS_ERR(handler) &&
3488 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3489 handler_ucast = create_flow_rule(dev, ft_prio,
3490 &leftovers_specs[LEFTOVERS_UC].flow_attr,
3491 dst);
3492 if (IS_ERR(handler_ucast)) {
74491de9 3493 mlx5_del_flow_rules(handler->rule);
d9d4980a 3494 ft_prio->refcount--;
038d2ef8
MG		 3495 kfree(handler);
3496 handler = handler_ucast;
3497 } else {
3498 list_add(&handler_ucast->list, &handler->list);
3499 }
3500 }
3501
3502 return handler;
3503}
3504
cc0e5d42
MG		 3505static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3506 struct mlx5_ib_flow_prio *ft_rx,
3507 struct mlx5_ib_flow_prio *ft_tx,
3508 struct mlx5_flow_destination *dst)
3509{
3510 struct mlx5_ib_flow_handler *handler_rx;
3511 struct mlx5_ib_flow_handler *handler_tx;
3512 int err;
3513 static const struct ib_flow_attr flow_attr = {
3514 .num_of_specs = 0,
3515 .size = sizeof(flow_attr)
3516 };
3517
3518 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3519 if (IS_ERR(handler_rx)) {
3520 err = PTR_ERR(handler_rx);
3521 goto err;
3522 }
3523
3524 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3525 if (IS_ERR(handler_tx)) {
3526 err = PTR_ERR(handler_tx);
3527 goto err_tx;
3528 }
3529
3530 list_add(&handler_tx->list, &handler_rx->list);
3531
3532 return handler_rx;
3533
3534err_tx:
74491de9 3535 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 3536 ft_rx->refcount--;
3537 kfree(handler_rx);
3538err:
3539 return ERR_PTR(err);
3540}
3541
038d2ef8
MG		 3542static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3543 struct ib_flow_attr *flow_attr,
59082a32
MB		 3544 int domain,
3545 struct ib_udata *udata)
038d2ef8
MG		 3546{
3547 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 3548 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 3549 struct mlx5_ib_flow_handler *handler = NULL;
3550 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 3551 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8 3552 struct mlx5_ib_flow_prio *ft_prio;
802c2125 3553 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3b3233fb
RS		 3554 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3555 size_t min_ucmd_sz, required_ucmd_sz;
038d2ef8 3556 int err;
a550ddfc 3557 int underlay_qpn;
038d2ef8 3558
3b3233fb
RS		 3559 if (udata && udata->inlen) {
3560 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3561 sizeof(ucmd_hdr.reserved);
3562 if (udata->inlen < min_ucmd_sz)
3563 return ERR_PTR(-EOPNOTSUPP);
3564
3565 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3566 if (err)
3567 return ERR_PTR(err);
3568
3569 /* currently supports only one counters data */
3570 if (ucmd_hdr.ncounters_data > 1)
3571 return ERR_PTR(-EINVAL);
3572
3573 required_ucmd_sz = min_ucmd_sz +
3574 sizeof(struct mlx5_ib_flow_counters_data) *
3575 ucmd_hdr.ncounters_data;
3576 if (udata->inlen > required_ucmd_sz &&
3577 !ib_is_udata_cleared(udata, required_ucmd_sz,
3578 udata->inlen - required_ucmd_sz))
3579 return ERR_PTR(-EOPNOTSUPP);
3580
3581 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3582 if (!ucmd)
3583 return ERR_PTR(-ENOMEM);
3584
3585 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
299eafee
GS		 3586 if (err)
3587 goto free_ucmd;
3b3233fb 3588 }
59082a32 3589
299eafee
GS		 3590 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) {
3591 err = -ENOMEM;
3592 goto free_ucmd;
3593 }
038d2ef8
MG		 3594
3595 if (domain != IB_FLOW_DOMAIN_USER ||
508562d6 3596 flow_attr->port > dev->num_ports ||
802c2125 3597 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
299eafee
GS		 3598 IB_FLOW_ATTR_FLAGS_EGRESS))) {
3599 err = -EINVAL;
3600 goto free_ucmd;
3601 }
802c2125
AY		 3602
3603 if (is_egress &&
3604 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
299eafee
GS		 3605 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3606 err = -EINVAL;
3607 goto free_ucmd;
3608 }
038d2ef8
MG		 3609
3610 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
299eafee
GS		 3611 if (!dst) {
3612 err = -ENOMEM;
3613 goto free_ucmd;
3614 }
038d2ef8 3615
9a4ca38d 3616 mutex_lock(&dev->flow_db->lock);
038d2ef8 3617
802c2125
AY		 3618 ft_prio = get_flow_table(dev, flow_attr,
3619 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
038d2ef8
MG		 3620 if (IS_ERR(ft_prio)) {
3621 err = PTR_ERR(ft_prio);
3622 goto unlock;
3623 }
cc0e5d42
MG		 3624 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3625 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3626 if (IS_ERR(ft_prio_tx)) {
3627 err = PTR_ERR(ft_prio_tx);
3628 ft_prio_tx = NULL;
3629 goto destroy_ft;
3630 }
3631 }
038d2ef8 3632
802c2125
AY		 3633 if (is_egress) {
3634 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3635 } else {
3636 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3637 if (mqp->flags & MLX5_IB_QP_RSS)
3638 dst->tir_num = mqp->rss_qp.tirn;
3639 else
3640 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3641 }
038d2ef8
MG		 3642
3643 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 3644 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3645 handler = create_dont_trap_rule(dev, ft_prio,
3646 flow_attr, dst);
3647 } else {
a550ddfc
YH		 3648 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3649 mqp->underlay_qpn : 0;
3650 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3b3233fb 3651 dst, underlay_qpn, ucmd);
35d19011 3652 }
038d2ef8
MG		 3653 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3654 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3655 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3656 dst);
cc0e5d42
MG		 3657 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3658 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 3659 } else {
3660 err = -EINVAL;
3661 goto destroy_ft;
3662 }
3663
3664 if (IS_ERR(handler)) {
3665 err = PTR_ERR(handler);
3666 handler = NULL;
3667 goto destroy_ft;
3668 }
3669
9a4ca38d 3670 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3671 kfree(dst);
3b3233fb 3672 kfree(ucmd);
038d2ef8
MG		 3673
3674 return &handler->ibflow;
3675
3676destroy_ft:
3677 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 3678 if (ft_prio_tx)
3679 put_flow_table(dev, ft_prio_tx, false);
038d2ef8 3680unlock:
9a4ca38d 3681 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3682 kfree(dst);
299eafee 3683free_ucmd:
3b3233fb 3684 kfree(ucmd);
038d2ef8
MG		 3685 return ERR_PTR(err);
3686}
3687
b47fd4ff
MB		 3688static struct mlx5_ib_flow_prio *
3689_get_flow_table(struct mlx5_ib_dev *dev,
3690 struct mlx5_ib_flow_matcher *fs_matcher,
3691 bool mcast)
d4be3f44 3692{
d4be3f44
YH		 3693 struct mlx5_flow_namespace *ns = NULL;
3694 struct mlx5_ib_flow_prio *prio;
b47fd4ff
MB		 3695 int max_table_size;
3696 u32 flags = 0;
3697 int priority;
3698
3699 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) {
3700 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3701 log_max_ft_size));
3702 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3703 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3704 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3705 reformat_l3_tunnel_to_l2))
3706 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3707 } else { /* Can only be MLX5_FLOW_NAMESPACE_EGRESS */
3708 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3709 log_max_ft_size));
3710 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3711 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3712 }
d4be3f44 3713
d4be3f44
YH		 3714 if (max_table_size < MLX5_FS_MAX_ENTRIES)
3715 return ERR_PTR(-ENOMEM);
3716
3717 if (mcast)
3718 priority = MLX5_IB_FLOW_MCAST_PRIO;
3719 else
b47fd4ff 3720 priority = ib_prio_to_core_prio(fs_matcher->priority, false);
d4be3f44 3721
b47fd4ff 3722 ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type);
d4be3f44
YH		 3723 if (!ns)
3724 return ERR_PTR(-ENOTSUPP);
3725
b47fd4ff
MB		 3726 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS)
3727 prio = &dev->flow_db->prios[priority];
3728 else
3729 prio = &dev->flow_db->egress_prios[priority];
d4be3f44
YH		 3730
3731 if (prio->flow_table)
3732 return prio;
3733
3734 return _get_prio(ns, prio, priority, MLX5_FS_MAX_ENTRIES,
b47fd4ff 3735 MLX5_FS_MAX_TYPES, flags);
d4be3f44
YH		 3736}
3737
3738static struct mlx5_ib_flow_handler *
3739_create_raw_flow_rule(struct mlx5_ib_dev *dev,
3740 struct mlx5_ib_flow_prio *ft_prio,
3741 struct mlx5_flow_destination *dst,
3742 struct mlx5_ib_flow_matcher *fs_matcher,
b823dd6d 3743 struct mlx5_flow_act *flow_act,
bfc5d839
MB		 3744 void *cmd_in, int inlen,
3745 int dst_num)
d4be3f44
YH		 3746{
3747 struct mlx5_ib_flow_handler *handler;
d4be3f44
YH		 3748 struct mlx5_flow_spec *spec;
3749 struct mlx5_flow_table *ft = ft_prio->flow_table;
3750 int err = 0;
3751
3752 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3753 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3754 if (!handler || !spec) {
3755 err = -ENOMEM;
3756 goto free;
3757 }
3758
3759 INIT_LIST_HEAD(&handler->list);
3760
3761 memcpy(spec->match_value, cmd_in, inlen);
3762 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params,
3763 fs_matcher->mask_len);
3764 spec->match_criteria_enable = fs_matcher->match_criteria_enable;
3765
d4be3f44 3766 handler->rule = mlx5_add_flow_rules(ft, spec,
bfc5d839 3767 flow_act, dst, dst_num);
d4be3f44
YH		 3768
3769 if (IS_ERR(handler->rule)) {
3770 err = PTR_ERR(handler->rule);
3771 goto free;
3772 }
3773
3774 ft_prio->refcount++;
3775 handler->prio = ft_prio;
3776 handler->dev = dev;
3777 ft_prio->flow_table = ft;
3778
3779free:
3780 if (err)
3781 kfree(handler);
3782 kvfree(spec);
3783 return err ? ERR_PTR(err) : handler;
3784}
3785
3786static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher,
3787 void *match_v)
3788{
3789 void *match_c;
3790 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4;
3791 void *dmac, *dmac_mask;
3792 void *ipv4, *ipv4_mask;
3793
3794 if (!(fs_matcher->match_criteria_enable &
3795 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT)))
3796 return false;
3797
3798 match_c = fs_matcher->matcher_mask.match_params;
3799 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v,
3800 outer_headers);
3801 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c,
3802 outer_headers);
3803
3804 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
3805 dmac_47_16);
3806 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
3807 dmac_47_16);
3808
3809 if (is_multicast_ether_addr(dmac) &&
3810 is_multicast_ether_addr(dmac_mask))
3811 return true;
3812
3813 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
3814 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3815
3816 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
3817 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3818
3819 if (ipv4_is_multicast(*(__be32 *)(ipv4)) &&
3820 ipv4_is_multicast(*(__be32 *)(ipv4_mask)))
3821 return true;
3822
3823 return false;
3824}
3825
32269441
YH		 3826struct mlx5_ib_flow_handler *
3827mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
3828 struct mlx5_ib_flow_matcher *fs_matcher,
b823dd6d 3829 struct mlx5_flow_act *flow_act,
bfc5d839 3830 u32 counter_id,
32269441
YH		 3831 void *cmd_in, int inlen, int dest_id,
3832 int dest_type)
3833{
d4be3f44
YH		 3834 struct mlx5_flow_destination *dst;
3835 struct mlx5_ib_flow_prio *ft_prio;
d4be3f44 3836 struct mlx5_ib_flow_handler *handler;
bfc5d839 3837 int dst_num = 0;
d4be3f44
YH		 3838 bool mcast;
3839 int err;
3840
3841 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL)
3842 return ERR_PTR(-EOPNOTSUPP);
3843
3844 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO)
3845 return ERR_PTR(-ENOMEM);
3846
8e8aa145 3847 dst = kcalloc(2, sizeof(*dst), GFP_KERNEL);
d4be3f44
YH		 3848 if (!dst)
3849 return ERR_PTR(-ENOMEM);
3850
3851 mcast = raw_fs_is_multicast(fs_matcher, cmd_in);
3852 mutex_lock(&dev->flow_db->lock);
3853
b47fd4ff 3854 ft_prio = _get_flow_table(dev, fs_matcher, mcast);
d4be3f44
YH		 3855 if (IS_ERR(ft_prio)) {
3856 err = PTR_ERR(ft_prio);
3857 goto unlock;
3858 }
3859
6346f0bf 3860 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
bfc5d839
MB		 3861 dst[dst_num].type = dest_type;
3862 dst[dst_num].tir_num = dest_id;
b823dd6d 3863 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
a7ee18bd 3864 } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) {
bfc5d839
MB		 3865 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
3866 dst[dst_num].ft_num = dest_id;
b823dd6d 3867 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
a7ee18bd 3868 } else {
bfc5d839 3869 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_PORT;
a7ee18bd 3870 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
6346f0bf
YH		 3871 }
3872
bfc5d839
MB		 3873 dst_num++;
3874
3875 if (flow_act->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
3876 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
3877 dst[dst_num].counter_id = counter_id;
3878 dst_num++;
3879 }
3880
b823dd6d 3881 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher, flow_act,
bfc5d839 3882 cmd_in, inlen, dst_num);
d4be3f44
YH		 3883
3884 if (IS_ERR(handler)) {
3885 err = PTR_ERR(handler);
3886 goto destroy_ft;
3887 }
3888
3889 mutex_unlock(&dev->flow_db->lock);
3890 atomic_inc(&fs_matcher->usecnt);
3891 handler->flow_matcher = fs_matcher;
3892
3893 kfree(dst);
3894
3895 return handler;
3896
3897destroy_ft:
3898 put_flow_table(dev, ft_prio, false);
3899unlock:
3900 mutex_unlock(&dev->flow_db->lock);
3901 kfree(dst);
3902
3903 return ERR_PTR(err);
32269441
YH		 3904}
3905
c6475a0b
AY		 3906static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
3907{
3908 u32 flags = 0;
3909
3910 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
3911 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
3912
3913 return flags;
3914}
3915
3916#define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
3917static struct ib_flow_action *
3918mlx5_ib_create_flow_action_esp(struct ib_device *device,
3919 const struct ib_flow_action_attrs_esp *attr,
3920 struct uverbs_attr_bundle *attrs)
3921{
3922 struct mlx5_ib_dev *mdev = to_mdev(device);
3923 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
3924 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
3925 struct mlx5_ib_flow_action *action;
3926 u64 action_flags;
3927 u64 flags;
3928 int err = 0;
3929
bccd0622
JG		 3930 err = uverbs_get_flags64(
3931 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
3932 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1));
3933 if (err)
3934 return ERR_PTR(err);
c6475a0b
AY		 3935
3936 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
3937
3938 /* We current only support a subset of the standard features. Only a
3939 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
3940 * (with overlap). Full offload mode isn't supported.
3941 */
3942 if (!attr->keymat || attr->replay || attr->encap ||
3943 attr->spi || attr->seq || attr->tfc_pad ||
3944 attr->hard_limit_pkts ||
3945 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3946 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
3947 return ERR_PTR(-EOPNOTSUPP);
3948
3949 if (attr->keymat->protocol !=
3950 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
3951 return ERR_PTR(-EOPNOTSUPP);
3952
3953 aes_gcm = &attr->keymat->keymat.aes_gcm;
3954
3955 if (aes_gcm->icv_len != 16 ||
3956 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
3957 return ERR_PTR(-EOPNOTSUPP);
3958
3959 action = kmalloc(sizeof(*action), GFP_KERNEL);
3960 if (!action)
3961 return ERR_PTR(-ENOMEM);
3962
3963 action->esp_aes_gcm.ib_flags = attr->flags;
3964 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
3965 sizeof(accel_attrs.keymat.aes_gcm.aes_key));
3966 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
3967 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
3968 sizeof(accel_attrs.keymat.aes_gcm.salt));
3969 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
3970 sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
3971 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
3972 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
3973 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
3974
3975 accel_attrs.esn = attr->esn;
3976 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
3977 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
3978 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3979 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3980
3981 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
3982 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
3983
3984 action->esp_aes_gcm.ctx =
3985 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
3986 if (IS_ERR(action->esp_aes_gcm.ctx)) {
3987 err = PTR_ERR(action->esp_aes_gcm.ctx);
3988 goto err_parse;
3989 }
3990
3991 action->esp_aes_gcm.ib_flags = attr->flags;
3992
3993 return &action->ib_action;
3994
3995err_parse:
3996 kfree(action);
3997 return ERR_PTR(err);
3998}
3999
349705c1
MB		 4000static int
4001mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
4002 const struct ib_flow_action_attrs_esp *attr,
4003 struct uverbs_attr_bundle *attrs)
4004{
4005 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4006 struct mlx5_accel_esp_xfrm_attrs accel_attrs;
4007 int err = 0;
4008
4009 if (attr->keymat || attr->replay || attr->encap ||
4010 attr->spi || attr->seq || attr->tfc_pad ||
4011 attr->hard_limit_pkts ||
4012 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4013 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
4014 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
4015 return -EOPNOTSUPP;
4016
4017 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
4018 * be modified.
4019 */
4020 if (!(maction->esp_aes_gcm.ib_flags &
4021 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
4022 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4023 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
4024 return -EINVAL;
4025
4026 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
4027 sizeof(accel_attrs));
4028
4029 accel_attrs.esn = attr->esn;
4030 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4031 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4032 else
4033 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4034
4035 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
4036 &accel_attrs);
4037 if (err)
4038 return err;
4039
4040 maction->esp_aes_gcm.ib_flags &=
4041 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4042 maction->esp_aes_gcm.ib_flags |=
4043 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4044
4045 return 0;
4046}
4047
c6475a0b
AY		 4048static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
4049{
4050 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4051
4052 switch (action->type) {
4053 case IB_FLOW_ACTION_ESP:
4054 /*
4055 * We only support aes_gcm by now, so we implicitly know this is
4056 * the underline crypto.
4057 */
4058 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
4059 break;
b4749bf2
MB		 4060 case IB_FLOW_ACTION_UNSPECIFIED:
4061 mlx5_ib_destroy_flow_action_raw(maction);
4062 break;
c6475a0b
AY		 4063 default:
4064 WARN_ON(true);
4065 break;
4066 }
4067
4068 kfree(maction);
4069 return 0;
4070}
4071
e126ba97
EC		 4072static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4073{
4074 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 4075 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97 4076 int err;
539ec982
YH		 4077 u16 uid;
4078
4079 uid = ibqp->pd ?
4080 to_mpd(ibqp->pd)->uid : 0;
e126ba97 4081
81e30880
YH		 4082 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
4083 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
4084 return -EOPNOTSUPP;
4085 }
4086
539ec982 4087 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
e126ba97
EC		 4088 if (err)
4089 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
4090 ibqp->qp_num, gid->raw);
4091
4092 return err;
4093}
4094
4095static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4096{
4097 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4098 int err;
539ec982 4099 u16 uid;
e126ba97 4100
539ec982
YH		 4101 uid = ibqp->pd ?
4102 to_mpd(ibqp->pd)->uid : 0;
4103 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
e126ba97
EC		 4104 if (err)
4105 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
4106 ibqp->qp_num, gid->raw);
4107
4108 return err;
4109}
4110
4111static int init_node_data(struct mlx5_ib_dev *dev)
4112{
1b5daf11 4113 int err;
e126ba97 4114
1b5daf11 4115 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 4116 if (err)
1b5daf11 4117 return err;
e126ba97 4118
1b5daf11 4119 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 4120
1b5daf11 4121 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 4122}
4123
508a523f
PP		 4124static ssize_t fw_pages_show(struct device *device,
4125 struct device_attribute *attr, char *buf)
e126ba97
EC		 4126{
4127 struct mlx5_ib_dev *dev =
54747231 4128 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
e126ba97 4129
9603b61d 4130 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97 4131}
508a523f 4132static DEVICE_ATTR_RO(fw_pages);
e126ba97 4133
508a523f 4134static ssize_t reg_pages_show(struct device *device,
e126ba97
EC		 4135 struct device_attribute *attr, char *buf)
4136{
4137 struct mlx5_ib_dev *dev =
54747231 4138 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
e126ba97 4139
6aec21f6 4140 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97 4141}
508a523f 4142static DEVICE_ATTR_RO(reg_pages);
e126ba97 4143
508a523f
PP		 4144static ssize_t hca_type_show(struct device *device,
4145 struct device_attribute *attr, char *buf)
e126ba97
EC		 4146{
4147 struct mlx5_ib_dev *dev =
54747231
PP		 4148 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4149
9603b61d 4150 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97 4151}
508a523f 4152static DEVICE_ATTR_RO(hca_type);
e126ba97 4153
508a523f
PP		 4154static ssize_t hw_rev_show(struct device *device,
4155 struct device_attribute *attr, char *buf)
e126ba97
EC		 4156{
4157 struct mlx5_ib_dev *dev =
54747231
PP		 4158 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4159
9603b61d 4160 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97 4161}
508a523f 4162static DEVICE_ATTR_RO(hw_rev);
e126ba97 4163
508a523f
PP		 4164static ssize_t board_id_show(struct device *device,
4165 struct device_attribute *attr, char *buf)
e126ba97
EC		 4166{
4167 struct mlx5_ib_dev *dev =
54747231
PP		 4168 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4169
e126ba97 4170 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 4171 dev->mdev->board_id);
e126ba97 4172}
508a523f 4173static DEVICE_ATTR_RO(board_id);
e126ba97 4174
508a523f
PP		 4175static struct attribute *mlx5_class_attributes[] = {
4176 &dev_attr_hw_rev.attr,
4177 &dev_attr_hca_type.attr,
4178 &dev_attr_board_id.attr,
4179 &dev_attr_fw_pages.attr,
4180 &dev_attr_reg_pages.attr,
4181 NULL,
4182};
e126ba97 4183
508a523f
PP		 4184static const struct attribute_group mlx5_attr_group = {
4185 .attrs = mlx5_class_attributes,
e126ba97
EC		 4186};
4187
7722f47e
HE		 4188static void pkey_change_handler(struct work_struct *work)
4189{
4190 struct mlx5_ib_port_resources *ports =
4191 container_of(work, struct mlx5_ib_port_resources,
4192 pkey_change_work);
4193
4194 mutex_lock(&ports->devr->mutex);
4195 mlx5_ib_gsi_pkey_change(ports->gsi);
4196 mutex_unlock(&ports->devr->mutex);
4197}
4198
89ea94a7
MG		 4199static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
4200{
4201 struct mlx5_ib_qp *mqp;
4202 struct mlx5_ib_cq *send_mcq, *recv_mcq;
4203 struct mlx5_core_cq *mcq;
4204 struct list_head cq_armed_list;
4205 unsigned long flags_qp;
4206 unsigned long flags_cq;
4207 unsigned long flags;
4208
4209 INIT_LIST_HEAD(&cq_armed_list);
4210
4211 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
4212 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
4213 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
4214 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
4215 if (mqp->sq.tail != mqp->sq.head) {
4216 send_mcq = to_mcq(mqp->ibqp.send_cq);
4217 spin_lock_irqsave(&send_mcq->lock, flags_cq);
4218 if (send_mcq->mcq.comp &&
4219 mqp->ibqp.send_cq->comp_handler) {
4220 if (!send_mcq->mcq.reset_notify_added) {
4221 send_mcq->mcq.reset_notify_added = 1;
4222 list_add_tail(&send_mcq->mcq.reset_notify,
4223 &cq_armed_list);
4224 }
4225 }
4226 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
4227 }
4228 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
4229 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
4230 /* no handling is needed for SRQ */
4231 if (!mqp->ibqp.srq) {
4232 if (mqp->rq.tail != mqp->rq.head) {
4233 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
4234 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
4235 if (recv_mcq->mcq.comp &&
4236 mqp->ibqp.recv_cq->comp_handler) {
4237 if (!recv_mcq->mcq.reset_notify_added) {
4238 recv_mcq->mcq.reset_notify_added = 1;
4239 list_add_tail(&recv_mcq->mcq.reset_notify,
4240 &cq_armed_list);
4241 }
4242 }
4243 spin_unlock_irqrestore(&recv_mcq->lock,
4244 flags_cq);
4245 }
4246 }
4247 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
4248 }
4249 /*At that point all inflight post send were put to be executed as of we
4250 * lock/unlock above locks Now need to arm all involved CQs.
4251 */
4252 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4253 mcq->comp(mcq);
4254 }
4255 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
4256}
4257
03404e8a
MG		 4258static void delay_drop_handler(struct work_struct *work)
4259{
4260 int err;
4261 struct mlx5_ib_delay_drop *delay_drop =
4262 container_of(work, struct mlx5_ib_delay_drop,
4263 delay_drop_work);
4264
fe248c3a
MG		 4265 atomic_inc(&delay_drop->events_cnt);
4266
03404e8a
MG		 4267 mutex_lock(&delay_drop->lock);
4268 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
4269 delay_drop->timeout);
4270 if (err) {
4271 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4272 delay_drop->timeout);
4273 delay_drop->activate = false;
4274 }
4275 mutex_unlock(&delay_drop->lock);
4276}
4277
09e574fa
SM		 4278static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4279 struct ib_event *ibev)
4280{
4281 switch (eqe->sub_type) {
4282 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
4283 schedule_work(&ibdev->delay_drop.delay_drop_work);
4284 break;
4285 default: /* do nothing */
4286 return;
4287 }
4288}
4289
134e9349
SM		 4290static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4291 struct ib_event *ibev)
4292{
4293 u8 port = (eqe->data.port.port >> 4) & 0xf;
4294
4295 ibev->element.port_num = port;
4296
4297 switch (eqe->sub_type) {
4298 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
4299 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
4300 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
4301 /* In RoCE, port up/down events are handled in
4302 * mlx5_netdev_event().
4303 */
4304 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4305 IB_LINK_LAYER_ETHERNET)
4306 return -EINVAL;
4307
4308 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
4309 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
4310 break;
4311
4312 case MLX5_PORT_CHANGE_SUBTYPE_LID:
4313 ibev->event = IB_EVENT_LID_CHANGE;
4314 break;
4315
4316 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
4317 ibev->event = IB_EVENT_PKEY_CHANGE;
4318 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
4319 break;
4320
4321 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
4322 ibev->event = IB_EVENT_GID_CHANGE;
4323 break;
4324
4325 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
4326 ibev->event = IB_EVENT_CLIENT_REREGISTER;
4327 break;
4328 default:
4329 return -EINVAL;
4330 }
4331
4332 return 0;
4333}
4334
d69a24e0 4335static void mlx5_ib_handle_event(struct work_struct *_work)
e126ba97 4336{
d69a24e0
DJ		 4337 struct mlx5_ib_event_work *work =
4338 container_of(_work, struct mlx5_ib_event_work, work);
4339 struct mlx5_ib_dev *ibdev;
e126ba97 4340 struct ib_event ibev;
dbaaff2a 4341 bool fatal = false;
e126ba97 4342
df097a27
SM		 4343 if (work->is_slave) {
4344 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
d69a24e0
DJ		 4345 if (!ibdev)
4346 goto out;
4347 } else {
df097a27 4348 ibdev = work->dev;
d69a24e0
DJ		 4349 }
4350
4351 switch (work->event) {
e126ba97 4352 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 4353 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 4354 mlx5_ib_handle_internal_error(ibdev);
134e9349 4355 ibev.element.port_num = (u8)(unsigned long)work->param;
dbaaff2a 4356 fatal = true;
e126ba97 4357 break;
134e9349
SM		 4358 case MLX5_EVENT_TYPE_PORT_CHANGE:
4359 if (handle_port_change(ibdev, work->param, &ibev))
d69a24e0 4360 goto out;
e126ba97 4361 break;
09e574fa
SM		 4362 case MLX5_EVENT_TYPE_GENERAL_EVENT:
4363 handle_general_event(ibdev, work->param, &ibev);
4364 /* fall through */
bdc37924 4365 default:
03404e8a 4366 goto out;
e126ba97
EC		 4367 }
4368
134e9349 4369 ibev.device = &ibdev->ib_dev;
e126ba97 4370
134e9349
SM		 4371 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
4372 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num);
03404e8a 4373 goto out;
a0c84c32
EC		 4374 }
4375
e126ba97
EC		 4376 if (ibdev->ib_active)
4377 ib_dispatch_event(&ibev);
dbaaff2a
EC		 4378
4379 if (fatal)
4380 ibdev->ib_active = false;
03404e8a 4381out:
d69a24e0
DJ		 4382 kfree(work);
4383}
4384
df097a27
SM		 4385static int mlx5_ib_event(struct notifier_block *nb,
4386 unsigned long event, void *param)
d69a24e0
DJ		 4387{
4388 struct mlx5_ib_event_work *work;
4389
4390 work = kmalloc(sizeof(*work), GFP_ATOMIC);
10bea9c8 4391 if (!work)
df097a27 4392 return NOTIFY_DONE;
d69a24e0 4393
10bea9c8 4394 INIT_WORK(&work->work, mlx5_ib_handle_event);
df097a27
SM		 4395 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
4396 work->is_slave = false;
10bea9c8 4397 work->param = param;
10bea9c8
LR		 4398 work->event = event;
4399
4400 queue_work(mlx5_ib_event_wq, &work->work);
df097a27
SM		 4401
4402 return NOTIFY_OK;
4403}
4404
4405static int mlx5_ib_event_slave_port(struct notifier_block *nb,
4406 unsigned long event, void *param)
4407{
4408 struct mlx5_ib_event_work *work;
4409
4410 work = kmalloc(sizeof(*work), GFP_ATOMIC);
4411 if (!work)
4412 return NOTIFY_DONE;
4413
4414 INIT_WORK(&work->work, mlx5_ib_handle_event);
4415 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
4416 work->is_slave = true;
4417 work->param = param;
4418 work->event = event;
4419 queue_work(mlx5_ib_event_wq, &work->work);
4420
4421 return NOTIFY_OK;
e126ba97
EC		 4422}
4423
c43f1112
MG		 4424static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4425{
4426 struct mlx5_hca_vport_context vport_ctx;
4427 int err;
4428 int port;
4429
508562d6 4430 for (port = 1; port <= dev->num_ports; port++) {
c43f1112
MG		 4431 dev->mdev->port_caps[port - 1].has_smi = false;
4432 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4433 MLX5_CAP_PORT_TYPE_IB) {
4434 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4435 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4436 port, 0,
4437 &vport_ctx);
4438 if (err) {
4439 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4440 port, err);
4441 return err;
4442 }
4443 dev->mdev->port_caps[port - 1].has_smi =
4444 vport_ctx.has_smi;
4445 } else {
4446 dev->mdev->port_caps[port - 1].has_smi = true;
4447 }
4448 }
4449 }
4450 return 0;
4451}
4452
e126ba97
EC		 4453static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4454{
4455 int port;
4456
508562d6 4457 for (port = 1; port <= dev->num_ports; port++)
e126ba97
EC		 4458 mlx5_query_ext_port_caps(dev, port);
4459}
4460
32f69e4b 4461static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
e126ba97
EC		 4462{
4463 struct ib_device_attr *dprops = NULL;
4464 struct ib_port_attr *pprops = NULL;
f614fc15 4465 int err = -ENOMEM;
2528e33e 4466 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 4467
4468 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
4469 if (!pprops)
4470 goto out;
4471
4472 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4473 if (!dprops)
4474 goto out;
4475
c43f1112
MG		 4476 err = set_has_smi_cap(dev);
4477 if (err)
4478 goto out;
4479
2528e33e 4480 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 4481 if (err) {
4482 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4483 goto out;
4484 }
4485
32f69e4b
DJ		 4486 memset(pprops, 0, sizeof(*pprops));
4487 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4488 if (err) {
4489 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4490 port, err);
4491 goto out;
e126ba97
EC		 4492 }
4493
32f69e4b
DJ		 4494 dev->mdev->port_caps[port - 1].pkey_table_len =
4495 dprops->max_pkeys;
4496 dev->mdev->port_caps[port - 1].gid_table_len =
4497 pprops->gid_tbl_len;
4498 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4499 port, dprops->max_pkeys, pprops->gid_tbl_len);
4500
e126ba97
EC		 4501out:
4502 kfree(pprops);
4503 kfree(dprops);
4504
4505 return err;
4506}
4507
4508static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4509{
4510 int err;
4511
4512 err = mlx5_mr_cache_cleanup(dev);
4513 if (err)
4514 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4515
32927e28
MB		 4516 if (dev->umrc.qp)
4517 mlx5_ib_destroy_qp(dev->umrc.qp);
4518 if (dev->umrc.cq)
4519 ib_free_cq(dev->umrc.cq);
4520 if (dev->umrc.pd)
4521 ib_dealloc_pd(dev->umrc.pd);
e126ba97
EC		 4522}
4523
4524enum {
4525 MAX_UMR_WR = 128,
4526};
4527
4528static int create_umr_res(struct mlx5_ib_dev *dev)
4529{
4530 struct ib_qp_init_attr *init_attr = NULL;
4531 struct ib_qp_attr *attr = NULL;
4532 struct ib_pd *pd;
4533 struct ib_cq *cq;
4534 struct ib_qp *qp;
e126ba97
EC		 4535 int ret;
4536
4537 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4538 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4539 if (!attr || !init_attr) {
4540 ret = -ENOMEM;
4541 goto error_0;
4542 }
4543
ed082d36 4544 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 4545 if (IS_ERR(pd)) {
4546 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4547 ret = PTR_ERR(pd);
4548 goto error_0;
4549 }
4550
add08d76 4551 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 4552 if (IS_ERR(cq)) {
4553 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4554 ret = PTR_ERR(cq);
4555 goto error_2;
4556 }
e126ba97
EC		 4557
4558 init_attr->send_cq = cq;
4559 init_attr->recv_cq = cq;
4560 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4561 init_attr->cap.max_send_wr = MAX_UMR_WR;
4562 init_attr->cap.max_send_sge = 1;
4563 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4564 init_attr->port_num = 1;
4565 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4566 if (IS_ERR(qp)) {
4567 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4568 ret = PTR_ERR(qp);
4569 goto error_3;
4570 }
4571 qp->device = &dev->ib_dev;
4572 qp->real_qp = qp;
4573 qp->uobject = NULL;
4574 qp->qp_type = MLX5_IB_QPT_REG_UMR;
31fde034
MD		 4575 qp->send_cq = init_attr->send_cq;
4576 qp->recv_cq = init_attr->recv_cq;
e126ba97
EC		 4577
4578 attr->qp_state = IB_QPS_INIT;
4579 attr->port_num = 1;
4580 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4581 IB_QP_PORT, NULL);
4582 if (ret) {
4583 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4584 goto error_4;
4585 }
4586
4587 memset(attr, 0, sizeof(*attr));
4588 attr->qp_state = IB_QPS_RTR;
4589 attr->path_mtu = IB_MTU_256;
4590
4591 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4592 if (ret) {
4593 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4594 goto error_4;
4595 }
4596
4597 memset(attr, 0, sizeof(*attr));
4598 attr->qp_state = IB_QPS_RTS;
4599 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4600 if (ret) {
4601 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4602 goto error_4;
4603 }
4604
4605 dev->umrc.qp = qp;
4606 dev->umrc.cq = cq;
e126ba97
EC		 4607 dev->umrc.pd = pd;
4608
4609 sema_init(&dev->umrc.sem, MAX_UMR_WR);
4610 ret = mlx5_mr_cache_init(dev);
4611 if (ret) {
4612 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4613 goto error_4;
4614 }
4615
4616 kfree(attr);
4617 kfree(init_attr);
4618
4619 return 0;
4620
4621error_4:
4622 mlx5_ib_destroy_qp(qp);
32927e28 4623 dev->umrc.qp = NULL;
e126ba97
EC		 4624
4625error_3:
add08d76 4626 ib_free_cq(cq);
32927e28 4627 dev->umrc.cq = NULL;
e126ba97
EC		 4628
4629error_2:
e126ba97 4630 ib_dealloc_pd(pd);
32927e28 4631 dev->umrc.pd = NULL;
e126ba97
EC		 4632
4633error_0:
4634 kfree(attr);
4635 kfree(init_attr);
4636 return ret;
4637}
4638
6e8484c5
MG		 4639static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4640{
4641 switch (umr_fence_cap) {
4642 case MLX5_CAP_UMR_FENCE_NONE:
4643 return MLX5_FENCE_MODE_NONE;
4644 case MLX5_CAP_UMR_FENCE_SMALL:
4645 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4646 default:
4647 return MLX5_FENCE_MODE_STRONG_ORDERING;
4648 }
4649}
4650
e126ba97
EC		 4651static int create_dev_resources(struct mlx5_ib_resources *devr)
4652{
4653 struct ib_srq_init_attr attr;
4654 struct mlx5_ib_dev *dev;
bcf4c1ea 4655 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 4656 int port;
e126ba97
EC		 4657 int ret = 0;
4658
4659 dev = container_of(devr, struct mlx5_ib_dev, devr);
4660
d16e91da
HE		 4661 mutex_init(&devr->mutex);
4662
e126ba97
EC		 4663 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
4664 if (IS_ERR(devr->p0)) {
4665 ret = PTR_ERR(devr->p0);
4666 goto error0;
4667 }
4668 devr->p0->device = &dev->ib_dev;
4669 devr->p0->uobject = NULL;
4670 atomic_set(&devr->p0->usecnt, 0);
4671
bcf4c1ea 4672 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 4673 if (IS_ERR(devr->c0)) {
4674 ret = PTR_ERR(devr->c0);
4675 goto error1;
4676 }
4677 devr->c0->device = &dev->ib_dev;
4678 devr->c0->uobject = NULL;
4679 devr->c0->comp_handler = NULL;
4680 devr->c0->event_handler = NULL;
4681 devr->c0->cq_context = NULL;
4682 atomic_set(&devr->c0->usecnt, 0);
4683
4684 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4685 if (IS_ERR(devr->x0)) {
4686 ret = PTR_ERR(devr->x0);
4687 goto error2;
4688 }
4689 devr->x0->device = &dev->ib_dev;
4690 devr->x0->inode = NULL;
4691 atomic_set(&devr->x0->usecnt, 0);
4692 mutex_init(&devr->x0->tgt_qp_mutex);
4693 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4694
4695 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4696 if (IS_ERR(devr->x1)) {
4697 ret = PTR_ERR(devr->x1);
4698 goto error3;
4699 }
4700 devr->x1->device = &dev->ib_dev;
4701 devr->x1->inode = NULL;
4702 atomic_set(&devr->x1->usecnt, 0);
4703 mutex_init(&devr->x1->tgt_qp_mutex);
4704 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4705
4706 memset(&attr, 0, sizeof(attr));
4707 attr.attr.max_sge = 1;
4708 attr.attr.max_wr = 1;
4709 attr.srq_type = IB_SRQT_XRC;
1a56ff6d 4710 attr.ext.cq = devr->c0;
e126ba97
EC		 4711 attr.ext.xrc.xrcd = devr->x0;
4712
4713 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4714 if (IS_ERR(devr->s0)) {
4715 ret = PTR_ERR(devr->s0);
4716 goto error4;
4717 }
4718 devr->s0->device = &dev->ib_dev;
4719 devr->s0->pd = devr->p0;
4720 devr->s0->uobject = NULL;
4721 devr->s0->event_handler = NULL;
4722 devr->s0->srq_context = NULL;
4723 devr->s0->srq_type = IB_SRQT_XRC;
4724 devr->s0->ext.xrc.xrcd = devr->x0;
1a56ff6d 4725 devr->s0->ext.cq = devr->c0;
e126ba97 4726 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1a56ff6d 4727 atomic_inc(&devr->s0->ext.cq->usecnt);
e126ba97
EC		 4728 atomic_inc(&devr->p0->usecnt);
4729 atomic_set(&devr->s0->usecnt, 0);
4730
4aa17b28
HA		 4731 memset(&attr, 0, sizeof(attr));
4732 attr.attr.max_sge = 1;
4733 attr.attr.max_wr = 1;
4734 attr.srq_type = IB_SRQT_BASIC;
4735 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4736 if (IS_ERR(devr->s1)) {
4737 ret = PTR_ERR(devr->s1);
4738 goto error5;
4739 }
4740 devr->s1->device = &dev->ib_dev;
4741 devr->s1->pd = devr->p0;
4742 devr->s1->uobject = NULL;
4743 devr->s1->event_handler = NULL;
4744 devr->s1->srq_context = NULL;
4745 devr->s1->srq_type = IB_SRQT_BASIC;
1a56ff6d 4746 devr->s1->ext.cq = devr->c0;
4aa17b28 4747 atomic_inc(&devr->p0->usecnt);
1a56ff6d 4748 atomic_set(&devr->s1->usecnt, 0);
4aa17b28 4749
7722f47e
HE		 4750 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
4751 INIT_WORK(&devr->ports[port].pkey_change_work,
4752 pkey_change_handler);
4753 devr->ports[port].devr = devr;
4754 }
4755
e126ba97
EC		 4756 return 0;
4757
4aa17b28
HA		 4758error5:
4759 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 4760error4:
4761 mlx5_ib_dealloc_xrcd(devr->x1);
4762error3:
4763 mlx5_ib_dealloc_xrcd(devr->x0);
4764error2:
4765 mlx5_ib_destroy_cq(devr->c0);
4766error1:
4767 mlx5_ib_dealloc_pd(devr->p0);
4768error0:
4769 return ret;
4770}
4771
4772static void destroy_dev_resources(struct mlx5_ib_resources *devr)
4773{
7722f47e
HE		 4774 struct mlx5_ib_dev *dev =
4775 container_of(devr, struct mlx5_ib_dev, devr);
4776 int port;
4777
4aa17b28 4778 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 4779 mlx5_ib_destroy_srq(devr->s0);
4780 mlx5_ib_dealloc_xrcd(devr->x0);
4781 mlx5_ib_dealloc_xrcd(devr->x1);
4782 mlx5_ib_destroy_cq(devr->c0);
4783 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 4784
4785 /* Make sure no change P_Key work items are still executing */
4786 for (port = 0; port < dev->num_ports; ++port)
4787 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 4788}
4789
b02289b3
AK		 4790static u32 get_core_cap_flags(struct ib_device *ibdev,
4791 struct mlx5_hca_vport_context *rep)
e53505a8
AS		 4792{
4793 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4794 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
4795 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
4796 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
85c7c014 4797 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
e53505a8
AS		 4798 u32 ret = 0;
4799
b02289b3
AK		 4800 if (rep->grh_required)
4801 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
4802
e53505a8 4803 if (ll == IB_LINK_LAYER_INFINIBAND)
b02289b3 4804 return ret | RDMA_CORE_PORT_IBA_IB;
e53505a8 4805
85c7c014 4806 if (raw_support)
b02289b3 4807 ret |= RDMA_CORE_PORT_RAW_PACKET;
72cd5717 4808
e53505a8 4809 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 4810 return ret;
e53505a8
AS		 4811
4812 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 4813 return ret;
e53505a8
AS		 4814
4815 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
4816 ret |= RDMA_CORE_PORT_IBA_ROCE;
4817
4818 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
4819 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
4820
4821 return ret;
4822}
4823
7738613e
IW		 4824static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
4825 struct ib_port_immutable *immutable)
4826{
4827 struct ib_port_attr attr;
ca5b91d6
OG		 4828 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4829 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
b02289b3 4830 struct mlx5_hca_vport_context rep = {0};
7738613e
IW		 4831 int err;
4832
c4550c63 4833 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 4834 if (err)
4835 return err;
4836
b02289b3
AK		 4837 if (ll == IB_LINK_LAYER_INFINIBAND) {
4838 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
4839 &rep);
4840 if (err)
4841 return err;
4842 }
4843
7738613e
IW		 4844 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4845 immutable->gid_tbl_len = attr.gid_tbl_len;
b02289b3 4846 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
ca5b91d6
OG		 4847 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
4848 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 4849
4850 return 0;
4851}
4852
8e6efa3a
MB		 4853static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
4854 struct ib_port_immutable *immutable)
4855{
4856 struct ib_port_attr attr;
4857 int err;
4858
4859 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4860
4861 err = ib_query_port(ibdev, port_num, &attr);
4862 if (err)
4863 return err;
4864
4865 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4866 immutable->gid_tbl_len = attr.gid_tbl_len;
4867 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4868
4869 return 0;
4870}
4871
9abb0d1b 4872static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 4873{
4874 struct mlx5_ib_dev *dev =
4875 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 4876 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
4877 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
4878 fw_rev_sub(dev->mdev));
c7342823
IW		 4879}
4880
45f95acd 4881static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 4882{
4883 struct mlx5_core_dev *mdev = dev->mdev;
4884 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
4885 MLX5_FLOW_NAMESPACE_LAG);
4886 struct mlx5_flow_table *ft;
4887 int err;
4888
7c34ec19 4889 if (!ns || !mlx5_lag_is_roce(mdev))
9ef9c640
AH		 4890 return 0;
4891
4892 err = mlx5_cmd_create_vport_lag(mdev);
4893 if (err)
4894 return err;
4895
4896 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
4897 if (IS_ERR(ft)) {
4898 err = PTR_ERR(ft);
4899 goto err_destroy_vport_lag;
4900 }
4901
9a4ca38d 4902 dev->flow_db->lag_demux_ft = ft;
7c34ec19 4903 dev->lag_active = true;
9ef9c640
AH		 4904 return 0;
4905
4906err_destroy_vport_lag:
4907 mlx5_cmd_destroy_vport_lag(mdev);
4908 return err;
4909}
4910
45f95acd 4911static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 4912{
4913 struct mlx5_core_dev *mdev = dev->mdev;
4914
7c34ec19
AH		 4915 if (dev->lag_active) {
4916 dev->lag_active = false;
4917
9a4ca38d
MB		 4918 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
4919 dev->flow_db->lag_demux_ft = NULL;
9ef9c640
AH		 4920
4921 mlx5_cmd_destroy_vport_lag(mdev);
4922 }
4923}
4924
7fd8aefb 4925static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
d012f5d6
OG		 4926{
4927 int err;
4928
7fd8aefb
DJ		 4929 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
4930 err = register_netdevice_notifier(&dev->roce[port_num].nb);
d012f5d6 4931 if (err) {
7fd8aefb 4932 dev->roce[port_num].nb.notifier_call = NULL;
d012f5d6
OG		 4933 return err;
4934 }
4935
4936 return 0;
4937}
4938
7fd8aefb 4939static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5ec8c83e 4940{
7fd8aefb
DJ		 4941 if (dev->roce[port_num].nb.notifier_call) {
4942 unregister_netdevice_notifier(&dev->roce[port_num].nb);
4943 dev->roce[port_num].nb.notifier_call = NULL;
5ec8c83e
AH		 4944 }
4945}
4946
e3f1ed1f 4947static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 4948{
e53505a8
AS		 4949 int err;
4950
ca5b91d6
OG		 4951 if (MLX5_CAP_GEN(dev->mdev, roce)) {
4952 err = mlx5_nic_vport_enable_roce(dev->mdev);
4953 if (err)
8e6efa3a 4954 return err;
ca5b91d6 4955 }
e53505a8 4956
45f95acd 4957 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 4958 if (err)
4959 goto err_disable_roce;
4960
e53505a8
AS		 4961 return 0;
4962
9ef9c640 4963err_disable_roce:
ca5b91d6
OG		 4964 if (MLX5_CAP_GEN(dev->mdev, roce))
4965 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 4966
e53505a8 4967 return err;
fc24fc5e
AS		 4968}
4969
45f95acd 4970static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 4971{
45f95acd 4972 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 4973 if (MLX5_CAP_GEN(dev->mdev, roce))
4974 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 4975}
4976
e1f24a79 4977struct mlx5_ib_counter {
7c16f477
KH		 4978 const char *name;
4979 size_t offset;
4980};
4981
4982#define INIT_Q_COUNTER(_name) \
4983 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
4984
e1f24a79 4985static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 4986 INIT_Q_COUNTER(rx_write_requests),
4987 INIT_Q_COUNTER(rx_read_requests),
4988 INIT_Q_COUNTER(rx_atomic_requests),
4989 INIT_Q_COUNTER(out_of_buffer),
4990};
4991
e1f24a79 4992static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 4993 INIT_Q_COUNTER(out_of_sequence),
4994};
4995
e1f24a79 4996static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 4997 INIT_Q_COUNTER(duplicate_request),
4998 INIT_Q_COUNTER(rnr_nak_retry_err),
4999 INIT_Q_COUNTER(packet_seq_err),
5000 INIT_Q_COUNTER(implied_nak_seq_err),
5001 INIT_Q_COUNTER(local_ack_timeout_err),
5002};
5003
e1f24a79
PP		 5004#define INIT_CONG_COUNTER(_name) \
5005 { .name = #_name, .offset = \
5006 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
5007
5008static const struct mlx5_ib_counter cong_cnts[] = {
5009 INIT_CONG_COUNTER(rp_cnp_ignored),
5010 INIT_CONG_COUNTER(rp_cnp_handled),
5011 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
5012 INIT_CONG_COUNTER(np_cnp_sent),
5013};
5014
58dcb60a
PP		 5015static const struct mlx5_ib_counter extended_err_cnts[] = {
5016 INIT_Q_COUNTER(resp_local_length_error),
5017 INIT_Q_COUNTER(resp_cqe_error),
5018 INIT_Q_COUNTER(req_cqe_error),
5019 INIT_Q_COUNTER(req_remote_invalid_request),
5020 INIT_Q_COUNTER(req_remote_access_errors),
5021 INIT_Q_COUNTER(resp_remote_access_errors),
5022 INIT_Q_COUNTER(resp_cqe_flush_error),
5023 INIT_Q_COUNTER(req_cqe_flush_error),
5024};
5025
9f876f3d
TB		 5026#define INIT_EXT_PPCNT_COUNTER(_name) \
5027 { .name = #_name, .offset = \
5028 MLX5_BYTE_OFF(ppcnt_reg, \
5029 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
5030
5031static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
5032 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
5033};
5034
e1f24a79 5035static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a 5036{
aac4492e 5037 int i;
0837e86a 5038
7c16f477 5039 for (i = 0; i < dev->num_ports; i++) {
921c0f5b 5040 if (dev->port[i].cnts.set_id_valid)
aac4492e
DJ		 5041 mlx5_core_dealloc_q_counter(dev->mdev,
5042 dev->port[i].cnts.set_id);
e1f24a79
PP		 5043 kfree(dev->port[i].cnts.names);
5044 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 5045 }
5046}
5047
e1f24a79
PP		 5048static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
5049 struct mlx5_ib_counters *cnts)
7c16f477
KH		 5050{
5051 u32 num_counters;
5052
5053 num_counters = ARRAY_SIZE(basic_q_cnts);
5054
5055 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
5056 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
5057
5058 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
5059 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 5060
5061 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
5062 num_counters += ARRAY_SIZE(extended_err_cnts);
5063
e1f24a79 5064 cnts->num_q_counters = num_counters;
7c16f477 5065
e1f24a79
PP		 5066 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5067 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
5068 num_counters += ARRAY_SIZE(cong_cnts);
5069 }
9f876f3d
TB		 5070 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5071 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
5072 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
5073 }
e1f24a79
PP		 5074 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
5075 if (!cnts->names)
7c16f477
KH		 5076 return -ENOMEM;
5077
e1f24a79
PP		 5078 cnts->offsets = kcalloc(num_counters,
5079 sizeof(cnts->offsets), GFP_KERNEL);
5080 if (!cnts->offsets)
7c16f477
KH		 5081 goto err_names;
5082
7c16f477
KH		 5083 return 0;
5084
5085err_names:
e1f24a79 5086 kfree(cnts->names);
aac4492e 5087 cnts->names = NULL;
7c16f477
KH		 5088 return -ENOMEM;
5089}
5090
e1f24a79
PP		 5091static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
5092 const char **names,
5093 size_t *offsets)
7c16f477
KH		 5094{
5095 int i;
5096 int j = 0;
5097
5098 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
5099 names[j] = basic_q_cnts[i].name;
5100 offsets[j] = basic_q_cnts[i].offset;
5101 }
5102
5103 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
5104 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
5105 names[j] = out_of_seq_q_cnts[i].name;
5106 offsets[j] = out_of_seq_q_cnts[i].offset;
5107 }
5108 }
5109
5110 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
5111 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
5112 names[j] = retrans_q_cnts[i].name;
5113 offsets[j] = retrans_q_cnts[i].offset;
5114 }
5115 }
e1f24a79 5116
58dcb60a
PP		 5117 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
5118 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
5119 names[j] = extended_err_cnts[i].name;
5120 offsets[j] = extended_err_cnts[i].offset;
5121 }
5122 }
5123
e1f24a79
PP		 5124 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5125 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
5126 names[j] = cong_cnts[i].name;
5127 offsets[j] = cong_cnts[i].offset;
5128 }
5129 }
9f876f3d
TB		 5130
5131 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5132 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
5133 names[j] = ext_ppcnt_cnts[i].name;
5134 offsets[j] = ext_ppcnt_cnts[i].offset;
5135 }
5136 }
0837e86a
MB		 5137}
5138
e1f24a79 5139static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a 5140{
aac4492e 5141 int err = 0;
0837e86a 5142 int i;
aa74be6e
YH		 5143 bool is_shared;
5144
5145 is_shared = MLX5_CAP_GEN(dev->mdev, log_max_uctx) != 0;
0837e86a
MB		 5146
5147 for (i = 0; i < dev->num_ports; i++) {
aac4492e
DJ		 5148 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
5149 if (err)
5150 goto err_alloc;
5151
5152 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
5153 dev->port[i].cnts.offsets);
7c16f477 5154
aa74be6e
YH		 5155 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5156 &dev->port[i].cnts.set_id,
5157 is_shared ?
5158 MLX5_SHARED_RESOURCE_UID : 0);
aac4492e 5159 if (err) {
0837e86a
MB		 5160 mlx5_ib_warn(dev,
5161 "couldn't allocate queue counter for port %d, err %d\n",
aac4492e
DJ		 5162 i + 1, err);
5163 goto err_alloc;
0837e86a 5164 }
aac4492e 5165 dev->port[i].cnts.set_id_valid = true;
0837e86a
MB		 5166 }
5167
5168 return 0;
5169
aac4492e
DJ		 5170err_alloc:
5171 mlx5_ib_dealloc_counters(dev);
5172 return err;
0837e86a
MB		 5173}
5174
0ad17a8f
MB		 5175static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
5176 u8 port_num)
5177{
7c16f477
KH		 5178 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5179 struct mlx5_ib_port *port = &dev->port[port_num - 1];
0ad17a8f
MB		 5180
5181 /* We support only per port stats */
5182 if (port_num == 0)
5183 return NULL;
5184
e1f24a79
PP		 5185 return rdma_alloc_hw_stats_struct(port->cnts.names,
5186 port->cnts.num_q_counters +
9f876f3d
TB		 5187 port->cnts.num_cong_counters +
5188 port->cnts.num_ext_ppcnt_counters,
0ad17a8f
MB		 5189 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5190}
5191
aac4492e 5192static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
e1f24a79
PP		 5193 struct mlx5_ib_port *port,
5194 struct rdma_hw_stats *stats)
0ad17a8f 5195{
0ad17a8f
MB		 5196 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
5197 void *out;
5198 __be32 val;
e1f24a79 5199 int ret, i;
0ad17a8f 5200
1b9a07ee 5201 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 5202 if (!out)
5203 return -ENOMEM;
5204
aac4492e 5205 ret = mlx5_core_query_q_counter(mdev,
e1f24a79 5206 port->cnts.set_id, 0,
0ad17a8f
MB		 5207 out, outlen);
5208 if (ret)
5209 goto free;
5210
e1f24a79
PP		 5211 for (i = 0; i < port->cnts.num_q_counters; i++) {
5212 val = *(__be32 *)(out + port->cnts.offsets[i]);
0ad17a8f
MB		 5213 stats->value[i] = (u64)be32_to_cpu(val);
5214 }
7c16f477 5215
0ad17a8f
MB		 5216free:
5217 kvfree(out);
e1f24a79
PP		 5218 return ret;
5219}
5220
9f876f3d
TB		 5221static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
5222 struct mlx5_ib_port *port,
5223 struct rdma_hw_stats *stats)
5224{
5225 int offset = port->cnts.num_q_counters + port->cnts.num_cong_counters;
5226 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
5227 int ret, i;
5228 void *out;
5229
5230 out = kvzalloc(sz, GFP_KERNEL);
5231 if (!out)
5232 return -ENOMEM;
5233
5234 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
5235 if (ret)
5236 goto free;
5237
5238 for (i = 0; i < port->cnts.num_ext_ppcnt_counters; i++) {
5239 stats->value[i + offset] =
5240 be64_to_cpup((__be64 *)(out +
5241 port->cnts.offsets[i + offset]));
5242 }
5243
5244free:
5245 kvfree(out);
5246 return ret;
5247}
5248
e1f24a79
PP		 5249static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
5250 struct rdma_hw_stats *stats,
5251 u8 port_num, int index)
5252{
5253 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5254 struct mlx5_ib_port *port = &dev->port[port_num - 1];
aac4492e 5255 struct mlx5_core_dev *mdev;
e1f24a79 5256 int ret, num_counters;
aac4492e 5257 u8 mdev_port_num;
e1f24a79
PP		 5258
5259 if (!stats)
5260 return -EINVAL;
5261
9f876f3d
TB		 5262 num_counters = port->cnts.num_q_counters +
5263 port->cnts.num_cong_counters +
5264 port->cnts.num_ext_ppcnt_counters;
aac4492e
DJ		 5265
5266 /* q_counters are per IB device, query the master mdev */
5267 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
e1f24a79
PP		 5268 if (ret)
5269 return ret;
e1f24a79 5270
9f876f3d
TB		 5271 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5272 ret = mlx5_ib_query_ext_ppcnt_counters(dev, port, stats);
5273 if (ret)
5274 return ret;
5275 }
5276
e1f24a79 5277 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
aac4492e
DJ		 5278 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
5279 &mdev_port_num);
5280 if (!mdev) {
5281 /* If port is not affiliated yet, its in down state
5282 * which doesn't have any counters yet, so it would be
5283 * zero. So no need to read from the HCA.
5284 */
5285 goto done;
5286 }
71a0ff65
MD		 5287 ret = mlx5_lag_query_cong_counters(dev->mdev,
5288 stats->value +
5289 port->cnts.num_q_counters,
5290 port->cnts.num_cong_counters,
5291 port->cnts.offsets +
5292 port->cnts.num_q_counters);
aac4492e
DJ		 5293
5294 mlx5_ib_put_native_port_mdev(dev, port_num);
e1f24a79
PP		 5295 if (ret)
5296 return ret;
e1f24a79
PP		 5297 }
5298
aac4492e 5299done:
e1f24a79 5300 return num_counters;
0ad17a8f
MB		 5301}
5302
f6a8a19b
DD		 5303static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num,
5304 enum rdma_netdev_t type,
5305 struct rdma_netdev_alloc_params *params)
693dfd5a
ES		 5306{
5307 if (type != RDMA_NETDEV_IPOIB)
f6a8a19b 5308 return -EOPNOTSUPP;
693dfd5a 5309
f6a8a19b 5310 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
693dfd5a
ES		 5311}
5312
fe248c3a
MG		 5313static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
5314{
5315 if (!dev->delay_drop.dbg)
5316 return;
5317 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
5318 kfree(dev->delay_drop.dbg);
5319 dev->delay_drop.dbg = NULL;
5320}
5321
03404e8a
MG		 5322static void cancel_delay_drop(struct mlx5_ib_dev *dev)
5323{
5324 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5325 return;
5326
5327 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 5328 delay_drop_debugfs_cleanup(dev);
5329}
5330
5331static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5332 size_t count, loff_t *pos)
5333{
5334 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5335 char lbuf[20];
5336 int len;
5337
5338 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5339 return simple_read_from_buffer(buf, count, pos, lbuf, len);
5340}
5341
5342static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5343 size_t count, loff_t *pos)
5344{
5345 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5346 u32 timeout;
5347 u32 var;
5348
5349 if (kstrtouint_from_user(buf, count, 0, &var))
5350 return -EFAULT;
5351
5352 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5353 1000);
5354 if (timeout != var)
5355 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5356 timeout);
5357
5358 delay_drop->timeout = timeout;
5359
5360 return count;
5361}
5362
5363static const struct file_operations fops_delay_drop_timeout = {
5364 .owner = THIS_MODULE,
5365 .open = simple_open,
5366 .write = delay_drop_timeout_write,
5367 .read = delay_drop_timeout_read,
5368};
5369
5370static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5371{
5372 struct mlx5_ib_dbg_delay_drop *dbg;
5373
5374 if (!mlx5_debugfs_root)
5375 return 0;
5376
5377 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
5378 if (!dbg)
5379 return -ENOMEM;
5380
cbafad87
SM		 5381 dev->delay_drop.dbg = dbg;
5382
fe248c3a
MG		 5383 dbg->dir_debugfs =
5384 debugfs_create_dir("delay_drop",
5385 dev->mdev->priv.dbg_root);
5386 if (!dbg->dir_debugfs)
cbafad87 5387 goto out_debugfs;
fe248c3a
MG		 5388
5389 dbg->events_cnt_debugfs =
5390 debugfs_create_atomic_t("num_timeout_events", 0400,
5391 dbg->dir_debugfs,
5392 &dev->delay_drop.events_cnt);
5393 if (!dbg->events_cnt_debugfs)
5394 goto out_debugfs;
5395
5396 dbg->rqs_cnt_debugfs =
5397 debugfs_create_atomic_t("num_rqs", 0400,
5398 dbg->dir_debugfs,
5399 &dev->delay_drop.rqs_cnt);
5400 if (!dbg->rqs_cnt_debugfs)
5401 goto out_debugfs;
5402
5403 dbg->timeout_debugfs =
5404 debugfs_create_file("timeout", 0600,
5405 dbg->dir_debugfs,
5406 &dev->delay_drop,
5407 &fops_delay_drop_timeout);
5408 if (!dbg->timeout_debugfs)
5409 goto out_debugfs;
5410
5411 return 0;
5412
5413out_debugfs:
5414 delay_drop_debugfs_cleanup(dev);
5415 return -ENOMEM;
03404e8a
MG		 5416}
5417
5418static void init_delay_drop(struct mlx5_ib_dev *dev)
5419{
5420 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5421 return;
5422
5423 mutex_init(&dev->delay_drop.lock);
5424 dev->delay_drop.dev = dev;
5425 dev->delay_drop.activate = false;
5426 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5427 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 5428 atomic_set(&dev->delay_drop.rqs_cnt, 0);
5429 atomic_set(&dev->delay_drop.events_cnt, 0);
5430
5431 if (delay_drop_debugfs_init(dev))
5432 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
03404e8a
MG		 5433}
5434
32f69e4b
DJ		 5435/* The mlx5_ib_multiport_mutex should be held when calling this function */
5436static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5437 struct mlx5_ib_multiport_info *mpi)
5438{
5439 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5440 struct mlx5_ib_port *port = &ibdev->port[port_num];
5441 int comps;
5442 int err;
5443 int i;
5444
a9e546e7
PP		 5445 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5446
32f69e4b
DJ		 5447 spin_lock(&port->mp.mpi_lock);
5448 if (!mpi->ibdev) {
5449 spin_unlock(&port->mp.mpi_lock);
5450 return;
5451 }
df097a27
SM		 5452
5453 if (mpi->mdev_events.notifier_call)
5454 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
5455 mpi->mdev_events.notifier_call = NULL;
5456
32f69e4b
DJ		 5457 mpi->ibdev = NULL;
5458
5459 spin_unlock(&port->mp.mpi_lock);
5460 mlx5_remove_netdev_notifier(ibdev, port_num);
5461 spin_lock(&port->mp.mpi_lock);
5462
5463 comps = mpi->mdev_refcnt;
5464 if (comps) {
5465 mpi->unaffiliate = true;
5466 init_completion(&mpi->unref_comp);
5467 spin_unlock(&port->mp.mpi_lock);
5468
5469 for (i = 0; i < comps; i++)
5470 wait_for_completion(&mpi->unref_comp);
5471
5472 spin_lock(&port->mp.mpi_lock);
5473 mpi->unaffiliate = false;
5474 }
5475
5476 port->mp.mpi = NULL;
5477
5478 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5479
5480 spin_unlock(&port->mp.mpi_lock);
5481
5482 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5483
5484 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5485 /* Log an error, still needed to cleanup the pointers and add
5486 * it back to the list.
5487 */
5488 if (err)
5489 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5490 port_num + 1);
5491
5492 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
5493}
5494
5495/* The mlx5_ib_multiport_mutex should be held when calling this function */
5496static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5497 struct mlx5_ib_multiport_info *mpi)
5498{
5499 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5500 int err;
5501
5502 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5503 if (ibdev->port[port_num].mp.mpi) {
2577188e
QH		 5504 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
5505 port_num + 1);
32f69e4b
DJ		 5506 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5507 return false;
5508 }
5509
5510 ibdev->port[port_num].mp.mpi = mpi;
5511 mpi->ibdev = ibdev;
df097a27 5512 mpi->mdev_events.notifier_call = NULL;
32f69e4b
DJ		 5513 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5514
5515 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5516 if (err)
5517 goto unbind;
5518
5519 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5520 if (err)
5521 goto unbind;
5522
5523 err = mlx5_add_netdev_notifier(ibdev, port_num);
5524 if (err) {
5525 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5526 port_num + 1);
5527 goto unbind;
5528 }
5529
df097a27
SM		 5530 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
5531 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
5532
73eb8f03 5533 mlx5_ib_init_cong_debugfs(ibdev, port_num);
a9e546e7 5534
32f69e4b
DJ		 5535 return true;
5536
5537unbind:
5538 mlx5_ib_unbind_slave_port(ibdev, mpi);
5539 return false;
5540}
5541
5542static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5543{
5544 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5545 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5546 port_num + 1);
5547 struct mlx5_ib_multiport_info *mpi;
5548 int err;
5549 int i;
5550
5551 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5552 return 0;
5553
5554 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5555 &dev->sys_image_guid);
5556 if (err)
5557 return err;
5558
5559 err = mlx5_nic_vport_enable_roce(dev->mdev);
5560 if (err)
5561 return err;
5562
5563 mutex_lock(&mlx5_ib_multiport_mutex);
5564 for (i = 0; i < dev->num_ports; i++) {
5565 bool bound = false;
5566
5567 /* build a stub multiport info struct for the native port. */
5568 if (i == port_num) {
5569 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5570 if (!mpi) {
5571 mutex_unlock(&mlx5_ib_multiport_mutex);
5572 mlx5_nic_vport_disable_roce(dev->mdev);
5573 return -ENOMEM;
5574 }
5575
5576 mpi->is_master = true;
5577 mpi->mdev = dev->mdev;
5578 mpi->sys_image_guid = dev->sys_image_guid;
5579 dev->port[i].mp.mpi = mpi;
5580 mpi->ibdev = dev;
5581 mpi = NULL;
5582 continue;
5583 }
5584
5585 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5586 list) {
5587 if (dev->sys_image_guid == mpi->sys_image_guid &&
5588 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5589 bound = mlx5_ib_bind_slave_port(dev, mpi);
5590 }
5591
5592 if (bound) {
5593 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
5594 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5595 list_del(&mpi->list);
5596 break;
5597 }
5598 }
5599 if (!bound) {
5600 get_port_caps(dev, i + 1);
5601 mlx5_ib_dbg(dev, "no free port found for port %d\n",
5602 i + 1);
5603 }
5604 }
5605
5606 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
5607 mutex_unlock(&mlx5_ib_multiport_mutex);
5608 return err;
5609}
5610
5611static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
5612{
5613 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5614 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5615 port_num + 1);
5616 int i;
5617
5618 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5619 return;
5620
5621 mutex_lock(&mlx5_ib_multiport_mutex);
5622 for (i = 0; i < dev->num_ports; i++) {
5623 if (dev->port[i].mp.mpi) {
5624 /* Destroy the native port stub */
5625 if (i == port_num) {
5626 kfree(dev->port[i].mp.mpi);
5627 dev->port[i].mp.mpi = NULL;
5628 } else {
5629 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
5630 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
5631 }
5632 }
5633 }
5634
5635 mlx5_ib_dbg(dev, "removing from devlist\n");
5636 list_del(&dev->ib_dev_list);
5637 mutex_unlock(&mlx5_ib_multiport_mutex);
5638
5639 mlx5_nic_vport_disable_roce(dev->mdev);
5640}
5641
9a119cd5
JG		 5642ADD_UVERBS_ATTRIBUTES_SIMPLE(
5643 mlx5_ib_dm,
5644 UVERBS_OBJECT_DM,
5645 UVERBS_METHOD_DM_ALLOC,
5646 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
5647 UVERBS_ATTR_TYPE(u64),
83bb4442 5648 UA_MANDATORY),
9a119cd5
JG		 5649 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
5650 UVERBS_ATTR_TYPE(u16),
83bb4442 5651 UA_MANDATORY));
9a119cd5
JG		 5652
5653ADD_UVERBS_ATTRIBUTES_SIMPLE(
5654 mlx5_ib_flow_action,
5655 UVERBS_OBJECT_FLOW_ACTION,
5656 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
bccd0622
JG		 5657 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
5658 enum mlx5_ib_uapi_flow_action_flags));
c6475a0b 5659
0cbf432d
JG		 5660static const struct uapi_definition mlx5_ib_defs[] = {
5661#if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)
36e235c8 5662 UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
0cbf432d
JG		 5663 UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
5664#endif
8c84660b 5665
0cbf432d
JG		 5666 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION,
5667 &mlx5_ib_flow_action),
5668 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm),
5669 {}
5670};
8c84660b 5671
1a1e03dc
RS		 5672static int mlx5_ib_read_counters(struct ib_counters *counters,
5673 struct ib_counters_read_attr *read_attr,
5674 struct uverbs_attr_bundle *attrs)
5675{
5676 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5677 struct mlx5_read_counters_attr mread_attr = {};
5678 struct mlx5_ib_flow_counters_desc *desc;
5679 int ret, i;
5680
5681 mutex_lock(&mcounters->mcntrs_mutex);
5682 if (mcounters->cntrs_max_index > read_attr->ncounters) {
5683 ret = -EINVAL;
5684 goto err_bound;
5685 }
5686
5687 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
5688 GFP_KERNEL);
5689 if (!mread_attr.out) {
5690 ret = -ENOMEM;
5691 goto err_bound;
5692 }
5693
5694 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
5695 mread_attr.flags = read_attr->flags;
5696 ret = mcounters->read_counters(counters->device, &mread_attr);
5697 if (ret)
5698 goto err_read;
5699
5700 /* do the pass over the counters data array to assign according to the
5701 * descriptions and indexing pairs
5702 */
5703 desc = mcounters->counters_data;
5704 for (i = 0; i < mcounters->ncounters; i++)
5705 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
5706
5707err_read:
5708 kfree(mread_attr.out);
5709err_bound:
5710 mutex_unlock(&mcounters->mcntrs_mutex);
5711 return ret;
5712}
5713
b29e2a13
RS		 5714static int mlx5_ib_destroy_counters(struct ib_counters *counters)
5715{
5716 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5717
3b3233fb
RS		 5718 counters_clear_description(counters);
5719 if (mcounters->hw_cntrs_hndl)
5720 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
5721 mcounters->hw_cntrs_hndl);
5722
b29e2a13
RS		 5723 kfree(mcounters);
5724
5725 return 0;
5726}
5727
5728static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
5729 struct uverbs_attr_bundle *attrs)
5730{
5731 struct mlx5_ib_mcounters *mcounters;
5732
5733 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
5734 if (!mcounters)
5735 return ERR_PTR(-ENOMEM);
5736
3b3233fb
RS		 5737 mutex_init(&mcounters->mcntrs_mutex);
5738
b29e2a13
RS		 5739 return &mcounters->ibcntrs;
5740}
5741
b5ca15ad 5742void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
e126ba97 5743{
32f69e4b 5744 mlx5_ib_cleanup_multiport_master(dev);
13859d5d 5745 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
534fd7aa 5746 srcu_barrier(&dev->mr_srcu);
13859d5d
LR		 5747 cleanup_srcu_struct(&dev->mr_srcu);
5748 drain_workqueue(dev->advise_mr_wq);
5749 destroy_workqueue(dev->advise_mr_wq);
5750 }
16c1975f
MB		 5751 kfree(dev->port);
5752}
5753
b5ca15ad 5754int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5755{
5756 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 5757 int err;
32f69e4b 5758 int i;
e126ba97 5759
508562d6 5760 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
0837e86a
MB		 5761 GFP_KERNEL);
5762 if (!dev->port)
16c1975f 5763 return -ENOMEM;
0837e86a 5764
32f69e4b
DJ		 5765 for (i = 0; i < dev->num_ports; i++) {
5766 spin_lock_init(&dev->port[i].mp.mpi_lock);
5767 rwlock_init(&dev->roce[i].netdev_lock);
5768 }
5769
5770 err = mlx5_ib_init_multiport_master(dev);
e126ba97 5771 if (err)
0837e86a 5772 goto err_free_port;
e126ba97 5773
32f69e4b 5774 if (!mlx5_core_mp_enabled(mdev)) {
32f69e4b
DJ		 5775 for (i = 1; i <= dev->num_ports; i++) {
5776 err = get_port_caps(dev, i);
5777 if (err)
5778 break;
5779 }
5780 } else {
5781 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
5782 }
5783 if (err)
5784 goto err_mp;
5785
1b5daf11
MD		 5786 if (mlx5_use_mad_ifc(dev))
5787 get_ext_port_caps(dev);
e126ba97 5788
e126ba97
EC		 5789 dev->ib_dev.owner = THIS_MODULE;
5790 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 5791 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
508562d6 5792 dev->ib_dev.phys_port_cnt = dev->num_ports;
f2f3df55 5793 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev);
9b0c289e 5794 dev->ib_dev.dev.parent = &mdev->pdev->dev;
e126ba97 5795
3cc297db
MB		 5796 mutex_init(&dev->cap_mask_mutex);
5797 INIT_LIST_HEAD(&dev->qp_list);
5798 spin_lock_init(&dev->reset_flow_resource_lock);
5799
24da0016
AL		 5800 spin_lock_init(&dev->memic.memic_lock);
5801 dev->memic.dev = mdev;
5802
13859d5d
LR		 5803 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
5804 dev->advise_mr_wq =
5805 alloc_ordered_workqueue("mlx5_ib_advise_mr_wq", 0);
5806 if (!dev->advise_mr_wq) {
5807 err = -ENOMEM;
5808 goto err_mp;
5809 }
813e90b1 5810
13859d5d
LR		 5811 err = init_srcu_struct(&dev->mr_srcu);
5812 if (err) {
5813 destroy_workqueue(dev->advise_mr_wq);
5814 goto err_mp;
5815 }
623d1543 5816 }
3cc297db 5817
16c1975f 5818 return 0;
32f69e4b
DJ		 5819err_mp:
5820 mlx5_ib_cleanup_multiport_master(dev);
16c1975f
MB		 5821
5822err_free_port:
5823 kfree(dev->port);
5824
5825 return -ENOMEM;
5826}
5827
9a4ca38d
MB		 5828static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
5829{
5830 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
5831
5832 if (!dev->flow_db)
5833 return -ENOMEM;
5834
5835 mutex_init(&dev->flow_db->lock);
5836
5837 return 0;
5838}
5839
b5ca15ad
MB		 5840int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev)
5841{
5842 struct mlx5_ib_dev *nic_dev;
5843
5844 nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch);
5845
5846 if (!nic_dev)
5847 return -EINVAL;
5848
5849 dev->flow_db = nic_dev->flow_db;
5850
5851 return 0;
5852}
5853
9a4ca38d
MB		 5854static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
5855{
5856 kfree(dev->flow_db);
5857}
5858
96458233
KH		 5859static const struct ib_device_ops mlx5_ib_dev_ops = {
5860 .add_gid = mlx5_ib_add_gid,
5861 .alloc_mr = mlx5_ib_alloc_mr,
5862 .alloc_pd = mlx5_ib_alloc_pd,
5863 .alloc_ucontext = mlx5_ib_alloc_ucontext,
5864 .attach_mcast = mlx5_ib_mcg_attach,
5865 .check_mr_status = mlx5_ib_check_mr_status,
5866 .create_ah = mlx5_ib_create_ah,
5867 .create_counters = mlx5_ib_create_counters,
5868 .create_cq = mlx5_ib_create_cq,
5869 .create_flow = mlx5_ib_create_flow,
5870 .create_qp = mlx5_ib_create_qp,
5871 .create_srq = mlx5_ib_create_srq,
5872 .dealloc_pd = mlx5_ib_dealloc_pd,
5873 .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
5874 .del_gid = mlx5_ib_del_gid,
5875 .dereg_mr = mlx5_ib_dereg_mr,
5876 .destroy_ah = mlx5_ib_destroy_ah,
5877 .destroy_counters = mlx5_ib_destroy_counters,
5878 .destroy_cq = mlx5_ib_destroy_cq,
5879 .destroy_flow = mlx5_ib_destroy_flow,
5880 .destroy_flow_action = mlx5_ib_destroy_flow_action,
5881 .destroy_qp = mlx5_ib_destroy_qp,
5882 .destroy_srq = mlx5_ib_destroy_srq,
5883 .detach_mcast = mlx5_ib_mcg_detach,
5884 .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
5885 .drain_rq = mlx5_ib_drain_rq,
5886 .drain_sq = mlx5_ib_drain_sq,
5887 .get_dev_fw_str = get_dev_fw_str,
5888 .get_dma_mr = mlx5_ib_get_dma_mr,
5889 .get_link_layer = mlx5_ib_port_link_layer,
5890 .map_mr_sg = mlx5_ib_map_mr_sg,
5891 .mmap = mlx5_ib_mmap,
5892 .modify_cq = mlx5_ib_modify_cq,
5893 .modify_device = mlx5_ib_modify_device,
5894 .modify_port = mlx5_ib_modify_port,
5895 .modify_qp = mlx5_ib_modify_qp,
5896 .modify_srq = mlx5_ib_modify_srq,
5897 .poll_cq = mlx5_ib_poll_cq,
5898 .post_recv = mlx5_ib_post_recv,
5899 .post_send = mlx5_ib_post_send,
5900 .post_srq_recv = mlx5_ib_post_srq_recv,
5901 .process_mad = mlx5_ib_process_mad,
5902 .query_ah = mlx5_ib_query_ah,
5903 .query_device = mlx5_ib_query_device,
5904 .query_gid = mlx5_ib_query_gid,
5905 .query_pkey = mlx5_ib_query_pkey,
5906 .query_qp = mlx5_ib_query_qp,
5907 .query_srq = mlx5_ib_query_srq,
5908 .read_counters = mlx5_ib_read_counters,
5909 .reg_user_mr = mlx5_ib_reg_user_mr,
5910 .req_notify_cq = mlx5_ib_arm_cq,
5911 .rereg_user_mr = mlx5_ib_rereg_user_mr,
5912 .resize_cq = mlx5_ib_resize_cq,
5913};
5914
5915static const struct ib_device_ops mlx5_ib_dev_flow_ipsec_ops = {
5916 .create_flow_action_esp = mlx5_ib_create_flow_action_esp,
5917 .modify_flow_action_esp = mlx5_ib_modify_flow_action_esp,
5918};
5919
5920static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
5921 .rdma_netdev_get_params = mlx5_ib_rn_get_params,
5922};
5923
5924static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
5925 .get_vf_config = mlx5_ib_get_vf_config,
5926 .get_vf_stats = mlx5_ib_get_vf_stats,
5927 .set_vf_guid = mlx5_ib_set_vf_guid,
5928 .set_vf_link_state = mlx5_ib_set_vf_link_state,
5929};
5930
5931static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
5932 .alloc_mw = mlx5_ib_alloc_mw,
5933 .dealloc_mw = mlx5_ib_dealloc_mw,
5934};
5935
5936static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
5937 .alloc_xrcd = mlx5_ib_alloc_xrcd,
5938 .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
5939};
5940
5941static const struct ib_device_ops mlx5_ib_dev_dm_ops = {
5942 .alloc_dm = mlx5_ib_alloc_dm,
5943 .dealloc_dm = mlx5_ib_dealloc_dm,
5944 .reg_dm_mr = mlx5_ib_reg_dm_mr,
5945};
5946
b5ca15ad 5947int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5948{
5949 struct mlx5_core_dev *mdev = dev->mdev;
16c1975f
MB		 5950 int err;
5951
e126ba97
EC		 5952 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
5953 dev->ib_dev.uverbs_cmd_mask =
5954 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
5955 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
5956 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
5957 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
5958 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 5959 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
5960 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 5961 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 5962 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 5963 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
5964 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
5965 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
5966 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
5967 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
5968 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
5969 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
5970 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
5971 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
5972 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
5973 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
5974 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
5975 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
5976 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
5977 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
5978 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
5979 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 5980 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 5981 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
5982 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349 5983 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
b0e9df6d 5984 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
96458233
KH		 5985 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ) |
5986 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
5987 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
5988
f6a8a19b
DD		 5989 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
5990 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
96458233
KH		 5991 ib_set_device_ops(&dev->ib_dev,
5992 &mlx5_ib_dev_ipoib_enhanced_ops);
8e959601 5993
96458233
KH		 5994 if (mlx5_core_is_pf(mdev))
5995 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
7c2344c3 5996
6e8484c5
MG		 5997 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
5998
d2370e0a 5999 if (MLX5_CAP_GEN(mdev, imaicl)) {
d2370e0a
MB		 6000 dev->ib_dev.uverbs_cmd_mask |=
6001 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
6002 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
96458233 6003 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
d2370e0a
MB		 6004 }
6005
938fe83c 6006 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 6007 dev->ib_dev.uverbs_cmd_mask |=
6008 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
6009 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
96458233 6010 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
e126ba97
EC		 6011 }
6012
96458233
KH		 6013 if (MLX5_CAP_DEV_MEM(mdev, memic))
6014 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
24da0016 6015
dfb631a1 6016 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
96458233
KH		 6017 MLX5_ACCEL_IPSEC_CAP_DEVICE)
6018 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_flow_ipsec_ops);
0ede73bc 6019 dev->ib_dev.driver_id = RDMA_DRIVER_MLX5;
96458233 6020 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
81e30880 6021
36e235c8
JG		 6022 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
6023 dev->ib_dev.driver_def = mlx5_ib_defs;
81e30880 6024
e126ba97
EC		 6025 err = init_node_data(dev);
6026 if (err)
16c1975f 6027 return err;
e126ba97 6028
c8b89924 6029 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
e7996a9a
JG		 6030 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
6031 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
a560f1d9 6032 mutex_init(&dev->lb.mutex);
c8b89924 6033
16c1975f
MB		 6034 return 0;
6035}
6036
96458233
KH		 6037static const struct ib_device_ops mlx5_ib_dev_port_ops = {
6038 .get_port_immutable = mlx5_port_immutable,
6039 .query_port = mlx5_ib_query_port,
6040};
6041
8e6efa3a
MB		 6042static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
6043{
96458233 6044 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
8e6efa3a
MB		 6045 return 0;
6046}
6047
96458233
KH		 6048static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
6049 .get_port_immutable = mlx5_port_rep_immutable,
6050 .query_port = mlx5_ib_rep_query_port,
6051};
6052
b5ca15ad 6053int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
8e6efa3a 6054{
96458233 6055 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
8e6efa3a
MB		 6056 return 0;
6057}
6058
96458233
KH		 6059static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
6060 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
6061 .create_wq = mlx5_ib_create_wq,
6062 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
6063 .destroy_wq = mlx5_ib_destroy_wq,
6064 .get_netdev = mlx5_ib_get_netdev,
6065 .modify_wq = mlx5_ib_modify_wq,
6066};
6067
e3f1ed1f 6068static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
8e6efa3a 6069{
e3f1ed1f 6070 u8 port_num;
8e6efa3a
MB		 6071 int i;
6072
6073 for (i = 0; i < dev->num_ports; i++) {
6074 dev->roce[i].dev = dev;
6075 dev->roce[i].native_port_num = i + 1;
6076 dev->roce[i].last_port_state = IB_PORT_DOWN;
6077 }
6078
8e6efa3a
MB		 6079 dev->ib_dev.uverbs_ex_cmd_mask |=
6080 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
6081 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
6082 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
6083 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
6084 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
96458233 6085 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
8e6efa3a 6086
e3f1ed1f
LR		 6087 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6088
8e6efa3a
MB		 6089 return mlx5_add_netdev_notifier(dev, port_num);
6090}
6091
6092static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
6093{
6094 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6095
6096 mlx5_remove_netdev_notifier(dev, port_num);
6097}
6098
6099int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
6100{
6101 struct mlx5_core_dev *mdev = dev->mdev;
6102 enum rdma_link_layer ll;
6103 int port_type_cap;
6104 int err = 0;
8e6efa3a 6105
8e6efa3a
MB		 6106 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6107 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6108
6109 if (ll == IB_LINK_LAYER_ETHERNET)
e3f1ed1f 6110 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 6111
6112 return err;
6113}
6114
6115void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
6116{
6117 mlx5_ib_stage_common_roce_cleanup(dev);
6118}
6119
16c1975f
MB		 6120static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
6121{
6122 struct mlx5_core_dev *mdev = dev->mdev;
6123 enum rdma_link_layer ll;
6124 int port_type_cap;
6125 int err;
6126
6127 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6128 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6129
fc24fc5e 6130 if (ll == IB_LINK_LAYER_ETHERNET) {
e3f1ed1f 6131 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 6132 if (err)
6133 return err;
7fd8aefb 6134
e3f1ed1f 6135 err = mlx5_enable_eth(dev);
fc24fc5e 6136 if (err)
8e6efa3a 6137 goto cleanup;
fc24fc5e
AS		 6138 }
6139
16c1975f 6140 return 0;
8e6efa3a
MB		 6141cleanup:
6142 mlx5_ib_stage_common_roce_cleanup(dev);
6143
6144 return err;
16c1975f 6145}
e126ba97 6146
16c1975f
MB		 6147static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
6148{
6149 struct mlx5_core_dev *mdev = dev->mdev;
6150 enum rdma_link_layer ll;
6151 int port_type_cap;
e126ba97 6152
16c1975f
MB		 6153 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6154 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6155
6156 if (ll == IB_LINK_LAYER_ETHERNET) {
6157 mlx5_disable_eth(dev);
8e6efa3a 6158 mlx5_ib_stage_common_roce_cleanup(dev);
45bded2c 6159 }
16c1975f 6160}
6aec21f6 6161
b5ca15ad 6162int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6163{
6164 return create_dev_resources(&dev->devr);
6165}
6166
b5ca15ad 6167void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6168{
6169 destroy_dev_resources(&dev->devr);
6170}
6171
6172static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
6173{
07321b3c
MB		 6174 mlx5_ib_internal_fill_odp_caps(dev);
6175
16c1975f
MB		 6176 return mlx5_ib_odp_init_one(dev);
6177}
4a2da0b8 6178
d5d284b8
SM		 6179void mlx5_ib_stage_odp_cleanup(struct mlx5_ib_dev *dev)
6180{
6181 mlx5_ib_odp_cleanup_one(dev);
6182}
6183
96458233
KH		 6184static const struct ib_device_ops mlx5_ib_dev_hw_stats_ops = {
6185 .alloc_hw_stats = mlx5_ib_alloc_hw_stats,
6186 .get_hw_stats = mlx5_ib_get_hw_stats,
6187};
6188
b5ca15ad 6189int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
16c1975f 6190{
5e1e7612 6191 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
96458233 6192 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_hw_stats_ops);
5e1e7612
MB		 6193
6194 return mlx5_ib_alloc_counters(dev);
6195 }
16c1975f
MB		 6196
6197 return 0;
6198}
6199
b5ca15ad 6200void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6201{
6202 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
6203 mlx5_ib_dealloc_counters(dev);
6204}
6205
6206static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
6207{
73eb8f03
GKH		 6208 mlx5_ib_init_cong_debugfs(dev,
6209 mlx5_core_native_port_num(dev->mdev) - 1);
6210 return 0;
16c1975f
MB		 6211}
6212
6213static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
6214{
a9e546e7
PP		 6215 mlx5_ib_cleanup_cong_debugfs(dev,
6216 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 6217}
6218
6219static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
6220{
5fe9dec0 6221 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
444261ca 6222 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
16c1975f
MB		 6223}
6224
6225static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
6226{
6227 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
6228}
6229
b5ca15ad 6230int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6231{
6232 int err;
5fe9dec0
EC		 6233
6234 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
6235 if (err)
16c1975f 6236 return err;
5fe9dec0
EC		 6237
6238 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
6239 if (err)
16c1975f 6240 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5fe9dec0 6241
16c1975f
MB		 6242 return err;
6243}
0837e86a 6244
b5ca15ad 6245void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6246{
6247 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6248 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
6249}
e126ba97 6250
b5ca15ad 6251int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
16c1975f 6252{
e349f858
JG		 6253 const char *name;
6254
508a523f 6255 rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group);
7c34ec19 6256 if (!mlx5_lag_is_roce(dev->mdev))
e349f858
JG		 6257 name = "mlx5_%d";
6258 else
6259 name = "mlx5_bond_%d";
ea4baf7f 6260 return ib_register_device(&dev->ib_dev, name);
16c1975f
MB		 6261}
6262
03fe2deb 6263void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
16c1975f 6264{
42cea83f 6265 destroy_umrc_res(dev);
16c1975f
MB		 6266}
6267
03fe2deb 6268void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
16c1975f 6269{
42cea83f 6270 ib_unregister_device(&dev->ib_dev);
16c1975f
MB		 6271}
6272
03fe2deb 6273int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
16c1975f 6274{
42cea83f 6275 return create_umr_res(dev);
16c1975f
MB		 6276}
6277
6278static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
6279{
03404e8a
MG		 6280 init_delay_drop(dev);
6281
16c1975f
MB		 6282 return 0;
6283}
6284
6285static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
6286{
6287 cancel_delay_drop(dev);
6288}
6289
df097a27
SM		 6290static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
6291{
6292 dev->mdev_events.notifier_call = mlx5_ib_event;
6293 mlx5_notifier_register(dev->mdev, &dev->mdev_events);
6294 return 0;
6295}
6296
6297static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
6298{
6299 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
6300}
6301
81773ce5
LR		 6302static int mlx5_ib_stage_devx_init(struct mlx5_ib_dev *dev)
6303{
6304 int uid;
6305
fb98153b 6306 uid = mlx5_ib_devx_create(dev, false);
81773ce5
LR		 6307 if (uid > 0)
6308 dev->devx_whitelist_uid = uid;
6309
6310 return 0;
6311}
6312static void mlx5_ib_stage_devx_cleanup(struct mlx5_ib_dev *dev)
6313{
6314 if (dev->devx_whitelist_uid)
6315 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid);
6316}
6317
b5ca15ad
MB		 6318void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
6319 const struct mlx5_ib_profile *profile,
6320 int stage)
16c1975f
MB		 6321{
6322 /* Number of stages to cleanup */
6323 while (stage) {
6324 stage--;
6325 if (profile->stage[stage].cleanup)
6326 profile->stage[stage].cleanup(dev);
6327 }
16c1975f 6328}
e126ba97 6329
b5ca15ad
MB		 6330void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
6331 const struct mlx5_ib_profile *profile)
16c1975f 6332{
16c1975f
MB		 6333 int err;
6334 int i;
5fe9dec0 6335
16c1975f
MB		 6336 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
6337 if (profile->stage[i].init) {
6338 err = profile->stage[i].init(dev);
6339 if (err)
6340 goto err_out;
6341 }
6342 }
0837e86a 6343
16c1975f
MB		 6344 dev->profile = profile;
6345 dev->ib_active = true;
6aec21f6 6346
16c1975f 6347 return dev;
e126ba97 6348
16c1975f
MB		 6349err_out:
6350 __mlx5_ib_remove(dev, profile, i);
fc24fc5e 6351
16c1975f
MB		 6352 return NULL;
6353}
0837e86a 6354
16c1975f
MB		 6355static const struct mlx5_ib_profile pf_profile = {
6356 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6357 mlx5_ib_stage_init_init,
6358 mlx5_ib_stage_init_cleanup),
9a4ca38d
MB		 6359 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6360 mlx5_ib_stage_flow_db_init,
6361 mlx5_ib_stage_flow_db_cleanup),
16c1975f
MB		 6362 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6363 mlx5_ib_stage_caps_init,
6364 NULL),
8e6efa3a
MB		 6365 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6366 mlx5_ib_stage_non_default_cb,
6367 NULL),
16c1975f
MB		 6368 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6369 mlx5_ib_stage_roce_init,
6370 mlx5_ib_stage_roce_cleanup),
f3da6577
LR		 6371 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6372 mlx5_init_srq_table,
6373 mlx5_cleanup_srq_table),
16c1975f
MB		 6374 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6375 mlx5_ib_stage_dev_res_init,
6376 mlx5_ib_stage_dev_res_cleanup),
df097a27
SM		 6377 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6378 mlx5_ib_stage_dev_notifier_init,
6379 mlx5_ib_stage_dev_notifier_cleanup),
16c1975f
MB		 6380 STAGE_CREATE(MLX5_IB_STAGE_ODP,
6381 mlx5_ib_stage_odp_init,
d5d284b8 6382 mlx5_ib_stage_odp_cleanup),
16c1975f
MB		 6383 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6384 mlx5_ib_stage_counters_init,
6385 mlx5_ib_stage_counters_cleanup),
6386 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
6387 mlx5_ib_stage_cong_debugfs_init,
6388 mlx5_ib_stage_cong_debugfs_cleanup),
6389 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6390 mlx5_ib_stage_uar_init,
6391 mlx5_ib_stage_uar_cleanup),
6392 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6393 mlx5_ib_stage_bfrag_init,
6394 mlx5_ib_stage_bfrag_cleanup),
42cea83f
MB		 6395 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6396 NULL,
6397 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
81773ce5
LR		 6398 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
6399 mlx5_ib_stage_devx_init,
6400 mlx5_ib_stage_devx_cleanup),
16c1975f
MB		 6401 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6402 mlx5_ib_stage_ib_reg_init,
6403 mlx5_ib_stage_ib_reg_cleanup),
42cea83f
MB		 6404 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6405 mlx5_ib_stage_post_ib_reg_umr_init,
6406 NULL),
16c1975f
MB		 6407 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
6408 mlx5_ib_stage_delay_drop_init,
6409 mlx5_ib_stage_delay_drop_cleanup),
16c1975f 6410};
e126ba97 6411
b5ca15ad
MB		 6412static const struct mlx5_ib_profile nic_rep_profile = {
6413 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6414 mlx5_ib_stage_init_init,
6415 mlx5_ib_stage_init_cleanup),
6416 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6417 mlx5_ib_stage_flow_db_init,
6418 mlx5_ib_stage_flow_db_cleanup),
6419 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6420 mlx5_ib_stage_caps_init,
6421 NULL),
6422 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6423 mlx5_ib_stage_rep_non_default_cb,
6424 NULL),
6425 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6426 mlx5_ib_stage_rep_roce_init,
6427 mlx5_ib_stage_rep_roce_cleanup),
f3da6577
LR		 6428 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6429 mlx5_init_srq_table,
6430 mlx5_cleanup_srq_table),
b5ca15ad
MB		 6431 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6432 mlx5_ib_stage_dev_res_init,
6433 mlx5_ib_stage_dev_res_cleanup),
df097a27
SM		 6434 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6435 mlx5_ib_stage_dev_notifier_init,
6436 mlx5_ib_stage_dev_notifier_cleanup),
b5ca15ad
MB		 6437 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6438 mlx5_ib_stage_counters_init,
6439 mlx5_ib_stage_counters_cleanup),
6440 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6441 mlx5_ib_stage_uar_init,
6442 mlx5_ib_stage_uar_cleanup),
6443 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6444 mlx5_ib_stage_bfrag_init,
6445 mlx5_ib_stage_bfrag_cleanup),
03fe2deb
DM		 6446 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6447 NULL,
6448 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
b5ca15ad
MB		 6449 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6450 mlx5_ib_stage_ib_reg_init,
6451 mlx5_ib_stage_ib_reg_cleanup),
03fe2deb
DM		 6452 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6453 mlx5_ib_stage_post_ib_reg_umr_init,
6454 NULL),
b5ca15ad
MB		 6455};
6456
e3f1ed1f 6457static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
32f69e4b
DJ		 6458{
6459 struct mlx5_ib_multiport_info *mpi;
6460 struct mlx5_ib_dev *dev;
6461 bool bound = false;
6462 int err;
6463
6464 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6465 if (!mpi)
6466 return NULL;
6467
6468 mpi->mdev = mdev;
6469
6470 err = mlx5_query_nic_vport_system_image_guid(mdev,
6471 &mpi->sys_image_guid);
6472 if (err) {
6473 kfree(mpi);
6474 return NULL;
6475 }
6476
6477 mutex_lock(&mlx5_ib_multiport_mutex);
6478 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
6479 if (dev->sys_image_guid == mpi->sys_image_guid)
6480 bound = mlx5_ib_bind_slave_port(dev, mpi);
6481
6482 if (bound) {
6483 rdma_roce_rescan_device(&dev->ib_dev);
6484 break;
6485 }
6486 }
6487
6488 if (!bound) {
6489 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
6490 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
32f69e4b
DJ		 6491 }
6492 mutex_unlock(&mlx5_ib_multiport_mutex);
6493
6494 return mpi;
6495}
6496
16c1975f
MB		 6497static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
6498{
32f69e4b 6499 enum rdma_link_layer ll;
b5ca15ad 6500 struct mlx5_ib_dev *dev;
32f69e4b
DJ		 6501 int port_type_cap;
6502
b5ca15ad
MB		 6503 printk_once(KERN_INFO "%s", mlx5_version);
6504
32f69e4b
DJ		 6505 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6506 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6507
e3f1ed1f
LR		 6508 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
6509 return mlx5_ib_add_slave_port(mdev);
32f69e4b 6510
b5ca15ad
MB		 6511 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
6512 if (!dev)
6513 return NULL;
6514
6515 dev->mdev = mdev;
6516 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
6517 MLX5_CAP_GEN(mdev, num_vhca_ports));
6518
aff2252a 6519 if (MLX5_ESWITCH_MANAGER(mdev) &&
b5ca15ad
MB		 6520 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
6521 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0);
06cc74af
MB		 6522 dev->profile = &nic_rep_profile;
6523 mlx5_ib_register_vport_reps(dev);
6524 return dev;
b5ca15ad
MB		 6525 }
6526
6527 return __mlx5_ib_add(dev, &pf_profile);
e126ba97
EC		 6528}
6529
9603b61d 6530static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 6531{
32f69e4b
DJ		 6532 struct mlx5_ib_multiport_info *mpi;
6533 struct mlx5_ib_dev *dev;
6534
6535 if (mlx5_core_is_mp_slave(mdev)) {
6536 mpi = context;
6537 mutex_lock(&mlx5_ib_multiport_mutex);
6538 if (mpi->ibdev)
6539 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
6540 list_del(&mpi->list);
6541 mutex_unlock(&mlx5_ib_multiport_mutex);
6542 return;
6543 }
6aec21f6 6544
32f69e4b 6545 dev = context;
06cc74af
MB		 6546 if (dev->profile == &nic_rep_profile)
6547 mlx5_ib_unregister_vport_reps(dev);
6548 else
6549 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
6550
6551 ib_dealloc_device((struct ib_device *)dev);
e126ba97
EC		 6552}
6553
9603b61d
JM		 6554static struct mlx5_interface mlx5_ib_interface = {
6555 .add = mlx5_ib_add,
6556 .remove = mlx5_ib_remove,
64613d94 6557 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 6558};
6559
c44ef998
IL		 6560unsigned long mlx5_ib_get_xlt_emergency_page(void)
6561{
6562 mutex_lock(&xlt_emergency_page_mutex);
6563 return xlt_emergency_page;
6564}
6565
6566void mlx5_ib_put_xlt_emergency_page(void)
6567{
6568 mutex_unlock(&xlt_emergency_page_mutex);
6569}
6570
e126ba97
EC		 6571static int __init mlx5_ib_init(void)
6572{
6aec21f6
HE		 6573 int err;
6574
c44ef998
IL		 6575 xlt_emergency_page = __get_free_page(GFP_KERNEL);
6576 if (!xlt_emergency_page)
6577 return -ENOMEM;
6578
6579 mutex_init(&xlt_emergency_page_mutex);
6580
d69a24e0 6581 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
c44ef998
IL		 6582 if (!mlx5_ib_event_wq) {
6583 free_page(xlt_emergency_page);
d69a24e0 6584 return -ENOMEM;
c44ef998 6585 }
d69a24e0 6586
81713d37 6587 mlx5_ib_odp_init();
9603b61d 6588
6aec21f6 6589 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 6590
6aec21f6 6591 return err;
e126ba97
EC		 6592}
6593
6594static void __exit mlx5_ib_cleanup(void)
6595{
9603b61d 6596 mlx5_unregister_interface(&mlx5_ib_interface);
d69a24e0 6597 destroy_workqueue(mlx5_ib_event_wq);
c44ef998
IL		 6598 mutex_destroy(&xlt_emergency_page_mutex);
6599 free_page(xlt_emergency_page);
e126ba97
EC		 6600}
6601
6602module_init(mlx5_ib_init);
6603module_exit(mlx5_ib_cleanup);
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