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IB/mlx5: Add inner spec and IPv6 validation in user's flow attribute list
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97
EC		 34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
37aa5c36
GL		 40#if defined(CONFIG_X86)
41#include <asm/pat.h>
42#endif
e126ba97 43#include <linux/sched.h>
6e84f315 44#include <linux/sched/mm.h>
0881e7bd 45#include <linux/sched/task.h>
7c2344c3 46#include <linux/delay.h>
e126ba97 47#include <rdma/ib_user_verbs.h>
3f89a643 48#include <rdma/ib_addr.h>
2811ba51 49#include <rdma/ib_cache.h>
ada68c31 50#include <linux/mlx5/port.h>
1b5daf11 51#include <linux/mlx5/vport.h>
7c2344c3 52#include <linux/list.h>
e126ba97
EC		 53#include <rdma/ib_smi.h>
54#include <rdma/ib_umem.h>
038d2ef8
MG		 55#include <linux/in.h>
56#include <linux/etherdevice.h>
57#include <linux/mlx5/fs.h>
78984898 58#include <linux/mlx5/vport.h>
e126ba97
EC		 59#include "mlx5_ib.h"
60
61#define DRIVER_NAME "mlx5_ib"
169a1d85
AV		 62#define DRIVER_VERSION "2.2-1"
63#define DRIVER_RELDATE "Feb 2014"
e126ba97
EC		 64
65MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
66MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
67MODULE_LICENSE("Dual BSD/GPL");
68MODULE_VERSION(DRIVER_VERSION);
69
e126ba97
EC		 70static char mlx5_version[] =
71 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
72 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
73
da7525d2
EBE		 74enum {
75 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
76};
77
1b5daf11 78static enum rdma_link_layer
ebd61f68 79mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 80{
ebd61f68 81 switch (port_type_cap) {
1b5daf11
MD		 82 case MLX5_CAP_PORT_TYPE_IB:
83 return IB_LINK_LAYER_INFINIBAND;
84 case MLX5_CAP_PORT_TYPE_ETH:
85 return IB_LINK_LAYER_ETHERNET;
86 default:
87 return IB_LINK_LAYER_UNSPECIFIED;
88 }
89}
90
ebd61f68
AS		 91static enum rdma_link_layer
92mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
93{
94 struct mlx5_ib_dev *dev = to_mdev(device);
95 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
96
97 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
98}
99
fc24fc5e
AS		 100static int mlx5_netdev_event(struct notifier_block *this,
101 unsigned long event, void *ptr)
102{
103 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
104 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
105 roce.nb);
106
5ec8c83e
AH		 107 switch (event) {
108 case NETDEV_REGISTER:
109 case NETDEV_UNREGISTER:
110 write_lock(&ibdev->roce.netdev_lock);
111 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
112 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
113 NULL : ndev;
114 write_unlock(&ibdev->roce.netdev_lock);
115 break;
fc24fc5e 116
5ec8c83e 117 case NETDEV_UP:
88621dfe
AH		 118 case NETDEV_DOWN: {
119 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
120 struct net_device *upper = NULL;
121
122 if (lag_ndev) {
123 upper = netdev_master_upper_dev_get(lag_ndev);
124 dev_put(lag_ndev);
125 }
126
127 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
128 && ibdev->ib_active) {
626bc02d 129 struct ib_event ibev = { };
5ec8c83e
AH		 130
131 ibev.device = &ibdev->ib_dev;
132 ibev.event = (event == NETDEV_UP) ?
133 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
134 ibev.element.port_num = 1;
135 ib_dispatch_event(&ibev);
136 }
137 break;
88621dfe 138 }
fc24fc5e 139
5ec8c83e
AH		 140 default:
141 break;
142 }
fc24fc5e
AS		 143
144 return NOTIFY_DONE;
145}
146
147static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
148 u8 port_num)
149{
150 struct mlx5_ib_dev *ibdev = to_mdev(device);
151 struct net_device *ndev;
152
88621dfe
AH		 153 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
154 if (ndev)
155 return ndev;
156
fc24fc5e
AS		 157 /* Ensure ndev does not disappear before we invoke dev_hold()
158 */
159 read_lock(&ibdev->roce.netdev_lock);
160 ndev = ibdev->roce.netdev;
161 if (ndev)
162 dev_hold(ndev);
163 read_unlock(&ibdev->roce.netdev_lock);
164
165 return ndev;
166}
167
3f89a643
AS		 168static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
169 struct ib_port_attr *props)
170{
171 struct mlx5_ib_dev *dev = to_mdev(device);
88621dfe 172 struct net_device *ndev, *upper;
3f89a643 173 enum ib_mtu ndev_ib_mtu;
c876a1b7 174 u16 qkey_viol_cntr;
3f89a643 175
c4550c63 176 /* props being zeroed by the caller, avoid zeroing it here */
3f89a643
AS		 177
178 props->port_cap_flags |= IB_PORT_CM_SUP;
179 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
180
181 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
182 roce_address_table_size);
183 props->max_mtu = IB_MTU_4096;
184 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
185 props->pkey_tbl_len = 1;
186 props->state = IB_PORT_DOWN;
187 props->phys_state = 3;
188
c876a1b7
LR		 189 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
190 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643
AS		 191
192 ndev = mlx5_ib_get_netdev(device, port_num);
193 if (!ndev)
194 return 0;
195
88621dfe
AH		 196 if (mlx5_lag_is_active(dev->mdev)) {
197 rcu_read_lock();
198 upper = netdev_master_upper_dev_get_rcu(ndev);
199 if (upper) {
200 dev_put(ndev);
201 ndev = upper;
202 dev_hold(ndev);
203 }
204 rcu_read_unlock();
205 }
206
3f89a643
AS		 207 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
208 props->state = IB_PORT_ACTIVE;
209 props->phys_state = 5;
210 }
211
212 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
213
214 dev_put(ndev);
215
216 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
217
218 props->active_width = IB_WIDTH_4X; /* TODO */
219 props->active_speed = IB_SPEED_QDR; /* TODO */
220
221 return 0;
222}
223
3cca2606
AS		 224static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
225 const struct ib_gid_attr *attr,
226 void *mlx5_addr)
227{
228#define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
229 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
230 source_l3_address);
231 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
232 source_mac_47_32);
233
234 if (!gid)
235 return;
236
237 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
238
239 if (is_vlan_dev(attr->ndev)) {
240 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
241 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
242 }
243
244 switch (attr->gid_type) {
245 case IB_GID_TYPE_IB:
246 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
247 break;
248 case IB_GID_TYPE_ROCE_UDP_ENCAP:
249 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
250 break;
251
252 default:
253 WARN_ON(true);
254 }
255
256 if (attr->gid_type != IB_GID_TYPE_IB) {
257 if (ipv6_addr_v4mapped((void *)gid))
258 MLX5_SET_RA(mlx5_addr, roce_l3_type,
259 MLX5_ROCE_L3_TYPE_IPV4);
260 else
261 MLX5_SET_RA(mlx5_addr, roce_l3_type,
262 MLX5_ROCE_L3_TYPE_IPV6);
263 }
264
265 if ((attr->gid_type == IB_GID_TYPE_IB) ||
266 !ipv6_addr_v4mapped((void *)gid))
267 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
268 else
269 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
270}
271
272static int set_roce_addr(struct ib_device *device, u8 port_num,
273 unsigned int index,
274 const union ib_gid *gid,
275 const struct ib_gid_attr *attr)
276{
c4f287c4
SM		 277 struct mlx5_ib_dev *dev = to_mdev(device);
278 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0};
279 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
3cca2606
AS		 280 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
281 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
282
283 if (ll != IB_LINK_LAYER_ETHERNET)
284 return -EINVAL;
285
3cca2606
AS		 286 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
287
288 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
289 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
3cca2606
AS		 290 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
291}
292
293static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
294 unsigned int index, const union ib_gid *gid,
295 const struct ib_gid_attr *attr,
296 __always_unused void **context)
297{
298 return set_roce_addr(device, port_num, index, gid, attr);
299}
300
301static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
302 unsigned int index, __always_unused void **context)
303{
304 return set_roce_addr(device, port_num, index, NULL, NULL);
305}
306
2811ba51
AS		 307__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
308 int index)
309{
310 struct ib_gid_attr attr;
311 union ib_gid gid;
312
313 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
314 return 0;
315
316 if (!attr.ndev)
317 return 0;
318
319 dev_put(attr.ndev);
320
321 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
322 return 0;
323
324 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
325}
326
ed88451e
MD		 327int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
328 int index, enum ib_gid_type *gid_type)
329{
330 struct ib_gid_attr attr;
331 union ib_gid gid;
332 int ret;
333
334 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
335 if (ret)
336 return ret;
337
338 if (!attr.ndev)
339 return -ENODEV;
340
341 dev_put(attr.ndev);
342
343 *gid_type = attr.gid_type;
344
345 return 0;
346}
347
1b5daf11
MD		 348static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
349{
7fae6655
NO		 350 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
351 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
352 return 0;
1b5daf11
MD		 353}
354
355enum {
356 MLX5_VPORT_ACCESS_METHOD_MAD,
357 MLX5_VPORT_ACCESS_METHOD_HCA,
358 MLX5_VPORT_ACCESS_METHOD_NIC,
359};
360
361static int mlx5_get_vport_access_method(struct ib_device *ibdev)
362{
363 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
364 return MLX5_VPORT_ACCESS_METHOD_MAD;
365
ebd61f68 366 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 367 IB_LINK_LAYER_ETHERNET)
368 return MLX5_VPORT_ACCESS_METHOD_NIC;
369
370 return MLX5_VPORT_ACCESS_METHOD_HCA;
371}
372
da7525d2
EBE		 373static void get_atomic_caps(struct mlx5_ib_dev *dev,
374 struct ib_device_attr *props)
375{
376 u8 tmp;
377 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
378 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
379 u8 atomic_req_8B_endianness_mode =
380 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
381
382 /* Check if HW supports 8 bytes standard atomic operations and capable
383 * of host endianness respond
384 */
385 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
386 if (((atomic_operations & tmp) == tmp) &&
387 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
388 (atomic_req_8B_endianness_mode)) {
389 props->atomic_cap = IB_ATOMIC_HCA;
390 } else {
391 props->atomic_cap = IB_ATOMIC_NONE;
392 }
393}
394
1b5daf11
MD		 395static int mlx5_query_system_image_guid(struct ib_device *ibdev,
396 __be64 *sys_image_guid)
397{
398 struct mlx5_ib_dev *dev = to_mdev(ibdev);
399 struct mlx5_core_dev *mdev = dev->mdev;
400 u64 tmp;
401 int err;
402
403 switch (mlx5_get_vport_access_method(ibdev)) {
404 case MLX5_VPORT_ACCESS_METHOD_MAD:
405 return mlx5_query_mad_ifc_system_image_guid(ibdev,
406 sys_image_guid);
407
408 case MLX5_VPORT_ACCESS_METHOD_HCA:
409 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 410 break;
411
412 case MLX5_VPORT_ACCESS_METHOD_NIC:
413 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
414 break;
1b5daf11
MD		 415
416 default:
417 return -EINVAL;
418 }
3f89a643
AS		 419
420 if (!err)
421 *sys_image_guid = cpu_to_be64(tmp);
422
423 return err;
424
1b5daf11
MD		 425}
426
427static int mlx5_query_max_pkeys(struct ib_device *ibdev,
428 u16 *max_pkeys)
429{
430 struct mlx5_ib_dev *dev = to_mdev(ibdev);
431 struct mlx5_core_dev *mdev = dev->mdev;
432
433 switch (mlx5_get_vport_access_method(ibdev)) {
434 case MLX5_VPORT_ACCESS_METHOD_MAD:
435 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
436
437 case MLX5_VPORT_ACCESS_METHOD_HCA:
438 case MLX5_VPORT_ACCESS_METHOD_NIC:
439 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
440 pkey_table_size));
441 return 0;
442
443 default:
444 return -EINVAL;
445 }
446}
447
448static int mlx5_query_vendor_id(struct ib_device *ibdev,
449 u32 *vendor_id)
450{
451 struct mlx5_ib_dev *dev = to_mdev(ibdev);
452
453 switch (mlx5_get_vport_access_method(ibdev)) {
454 case MLX5_VPORT_ACCESS_METHOD_MAD:
455 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
456
457 case MLX5_VPORT_ACCESS_METHOD_HCA:
458 case MLX5_VPORT_ACCESS_METHOD_NIC:
459 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
460
461 default:
462 return -EINVAL;
463 }
464}
465
466static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
467 __be64 *node_guid)
468{
469 u64 tmp;
470 int err;
471
472 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
473 case MLX5_VPORT_ACCESS_METHOD_MAD:
474 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
475
476 case MLX5_VPORT_ACCESS_METHOD_HCA:
477 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 478 break;
479
480 case MLX5_VPORT_ACCESS_METHOD_NIC:
481 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
482 break;
1b5daf11
MD		 483
484 default:
485 return -EINVAL;
486 }
3f89a643
AS		 487
488 if (!err)
489 *node_guid = cpu_to_be64(tmp);
490
491 return err;
1b5daf11
MD		 492}
493
494struct mlx5_reg_node_desc {
bd99fdea 495 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 496};
497
498static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
499{
500 struct mlx5_reg_node_desc in;
501
502 if (mlx5_use_mad_ifc(dev))
503 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
504
505 memset(&in, 0, sizeof(in));
506
507 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
508 sizeof(struct mlx5_reg_node_desc),
509 MLX5_REG_NODE_DESC, 0, 0);
510}
511
e126ba97 512static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 513 struct ib_device_attr *props,
514 struct ib_udata *uhw)
e126ba97
EC		 515{
516 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 517 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 518 int err = -ENOMEM;
288c01b7 519 int max_sq_desc;
e126ba97
EC		 520 int max_rq_sg;
521 int max_sq_sg;
e0238a6a 522 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
402ca536
BW		 523 struct mlx5_ib_query_device_resp resp = {};
524 size_t resp_len;
525 u64 max_tso;
e126ba97 526
402ca536
BW		 527 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
528 if (uhw->outlen && uhw->outlen < resp_len)
529 return -EINVAL;
530 else
531 resp.response_length = resp_len;
532
533 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 534 return -EINVAL;
535
1b5daf11
MD		 536 memset(props, 0, sizeof(*props));
537 err = mlx5_query_system_image_guid(ibdev,
538 &props->sys_image_guid);
539 if (err)
540 return err;
e126ba97 541
1b5daf11 542 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 543 if (err)
1b5daf11 544 return err;
e126ba97 545
1b5daf11
MD		 546 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
547 if (err)
548 return err;
e126ba97 549
9603b61d
JM		 550 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
551 (fw_rev_min(dev->mdev) << 16) |
552 fw_rev_sub(dev->mdev);
e126ba97
EC		 553 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
554 IB_DEVICE_PORT_ACTIVE_EVENT |
555 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 556 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 557
558 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 559 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 560 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 561 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 562 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 563 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 564 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 565 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 566 if (MLX5_CAP_GEN(mdev, imaicl)) {
567 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
568 IB_DEVICE_MEM_WINDOW_TYPE_2B;
569 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 570 /* We support 'Gappy' memory registration too */
571 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 572 }
e126ba97 573 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 574 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 575 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
576 /* At this stage no support for signature handover */
577 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
578 IB_PROT_T10DIF_TYPE_2 |
579 IB_PROT_T10DIF_TYPE_3;
580 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
581 IB_GUARD_T10DIF_CSUM;
582 }
938fe83c 583 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 584 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 585
402ca536 586 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
e8161334
NO		 587 if (MLX5_CAP_ETH(mdev, csum_cap)) {
588 /* Legacy bit to support old userspace libraries */
88115fe7 589 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 590 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
591 }
592
593 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
594 props->raw_packet_caps |=
595 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 596
402ca536
BW		 597 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
598 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
599 if (max_tso) {
600 resp.tso_caps.max_tso = 1 << max_tso;
601 resp.tso_caps.supported_qpts |=
602 1 << IB_QPT_RAW_PACKET;
603 resp.response_length += sizeof(resp.tso_caps);
604 }
605 }
31f69a82
YH		 606
607 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
608 resp.rss_caps.rx_hash_function =
609 MLX5_RX_HASH_FUNC_TOEPLITZ;
610 resp.rss_caps.rx_hash_fields_mask =
611 MLX5_RX_HASH_SRC_IPV4 |
612 MLX5_RX_HASH_DST_IPV4 |
613 MLX5_RX_HASH_SRC_IPV6 |
614 MLX5_RX_HASH_DST_IPV6 |
615 MLX5_RX_HASH_SRC_PORT_TCP |
616 MLX5_RX_HASH_DST_PORT_TCP |
617 MLX5_RX_HASH_SRC_PORT_UDP |
618 MLX5_RX_HASH_DST_PORT_UDP;
619 resp.response_length += sizeof(resp.rss_caps);
620 }
621 } else {
622 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
623 resp.response_length += sizeof(resp.tso_caps);
624 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
625 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 626 }
627
f0313965
ES		 628 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
629 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
630 props->device_cap_flags |= IB_DEVICE_UD_TSO;
631 }
632
cff5a0f3 633 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
e8161334
NO		 634 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
635 /* Legacy bit to support old userspace libraries */
cff5a0f3 636 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 637 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
638 }
cff5a0f3 639
da6d6ba3
MG		 640 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
641 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
642
1b5daf11
MD		 643 props->vendor_part_id = mdev->pdev->device;
644 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 645
646 props->max_mr_size = ~0ull;
e0238a6a 647 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 648 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
649 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
650 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
651 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 652 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
653 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
654 sizeof(struct mlx5_wqe_raddr_seg)) /
655 sizeof(struct mlx5_wqe_data_seg);
e126ba97 656 props->max_sge = min(max_rq_sg, max_sq_sg);
986ef95e 657 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 658 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 659 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 660 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
661 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
662 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
663 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
664 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
665 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
666 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 667 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 668 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 669 props->max_fast_reg_page_list_len =
670 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
da7525d2 671 get_atomic_caps(dev, props);
81bea28f 672 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 673 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
674 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 675 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
676 props->max_mcast_grp;
677 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 678 props->max_ah = INT_MAX;
7c60bcbb
MB		 679 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
680 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 681
8cdd312c 682#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 683 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 684 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
685 props->odp_caps = dev->odp_caps;
686#endif
687
051f2630
LR		 688 if (MLX5_CAP_GEN(mdev, cd))
689 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
690
eff901d3
EC		 691 if (!mlx5_core_is_pf(mdev))
692 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
693
31f69a82
YH		 694 if (mlx5_ib_port_link_layer(ibdev, 1) ==
695 IB_LINK_LAYER_ETHERNET) {
696 props->rss_caps.max_rwq_indirection_tables =
697 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
698 props->rss_caps.max_rwq_indirection_table_size =
699 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
700 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
701 props->max_wq_type_rq =
702 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
703 }
704
7e43a2a5
BW		 705 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
706 resp.cqe_comp_caps.max_num =
707 MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
708 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
709 resp.cqe_comp_caps.supported_format =
710 MLX5_IB_CQE_RES_FORMAT_HASH |
711 MLX5_IB_CQE_RES_FORMAT_CSUM;
712 resp.response_length += sizeof(resp.cqe_comp_caps);
713 }
714
d949167d
BW		 715 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) {
716 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
717 MLX5_CAP_GEN(mdev, qos)) {
718 resp.packet_pacing_caps.qp_rate_limit_max =
719 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
720 resp.packet_pacing_caps.qp_rate_limit_min =
721 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
722 resp.packet_pacing_caps.supported_qpts |=
723 1 << IB_QPT_RAW_PACKET;
724 }
725 resp.response_length += sizeof(resp.packet_pacing_caps);
726 }
727
9f885201
LR		 728 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
729 uhw->outlen)) {
730 resp.mlx5_ib_support_multi_pkt_send_wqes =
731 MLX5_CAP_ETH(mdev, multi_pkt_send_wqe);
732 resp.response_length +=
733 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
734 }
735
736 if (field_avail(typeof(resp), reserved, uhw->outlen))
737 resp.response_length += sizeof(resp.reserved);
738
402ca536
BW		 739 if (uhw->outlen) {
740 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
741
742 if (err)
743 return err;
744 }
745
1b5daf11 746 return 0;
e126ba97
EC		 747}
748
1b5daf11
MD		 749enum mlx5_ib_width {
750 MLX5_IB_WIDTH_1X = 1 << 0,
751 MLX5_IB_WIDTH_2X = 1 << 1,
752 MLX5_IB_WIDTH_4X = 1 << 2,
753 MLX5_IB_WIDTH_8X = 1 << 3,
754 MLX5_IB_WIDTH_12X = 1 << 4
755};
756
757static int translate_active_width(struct ib_device *ibdev, u8 active_width,
758 u8 *ib_width)
e126ba97
EC		 759{
760 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 761 int err = 0;
762
763 if (active_width & MLX5_IB_WIDTH_1X) {
764 *ib_width = IB_WIDTH_1X;
765 } else if (active_width & MLX5_IB_WIDTH_2X) {
766 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
767 (int)active_width);
768 err = -EINVAL;
769 } else if (active_width & MLX5_IB_WIDTH_4X) {
770 *ib_width = IB_WIDTH_4X;
771 } else if (active_width & MLX5_IB_WIDTH_8X) {
772 *ib_width = IB_WIDTH_8X;
773 } else if (active_width & MLX5_IB_WIDTH_12X) {
774 *ib_width = IB_WIDTH_12X;
775 } else {
776 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
777 (int)active_width);
778 err = -EINVAL;
e126ba97
EC		 779 }
780
1b5daf11
MD		 781 return err;
782}
e126ba97 783
1b5daf11
MD		 784static int mlx5_mtu_to_ib_mtu(int mtu)
785{
786 switch (mtu) {
787 case 256: return 1;
788 case 512: return 2;
789 case 1024: return 3;
790 case 2048: return 4;
791 case 4096: return 5;
792 default:
793 pr_warn("invalid mtu\n");
794 return -1;
e126ba97 795 }
1b5daf11 796}
e126ba97 797
1b5daf11
MD		 798enum ib_max_vl_num {
799 __IB_MAX_VL_0 = 1,
800 __IB_MAX_VL_0_1 = 2,
801 __IB_MAX_VL_0_3 = 3,
802 __IB_MAX_VL_0_7 = 4,
803 __IB_MAX_VL_0_14 = 5,
804};
e126ba97 805
1b5daf11
MD		 806enum mlx5_vl_hw_cap {
807 MLX5_VL_HW_0 = 1,
808 MLX5_VL_HW_0_1 = 2,
809 MLX5_VL_HW_0_2 = 3,
810 MLX5_VL_HW_0_3 = 4,
811 MLX5_VL_HW_0_4 = 5,
812 MLX5_VL_HW_0_5 = 6,
813 MLX5_VL_HW_0_6 = 7,
814 MLX5_VL_HW_0_7 = 8,
815 MLX5_VL_HW_0_14 = 15
816};
e126ba97 817
1b5daf11
MD		 818static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
819 u8 *max_vl_num)
820{
821 switch (vl_hw_cap) {
822 case MLX5_VL_HW_0:
823 *max_vl_num = __IB_MAX_VL_0;
824 break;
825 case MLX5_VL_HW_0_1:
826 *max_vl_num = __IB_MAX_VL_0_1;
827 break;
828 case MLX5_VL_HW_0_3:
829 *max_vl_num = __IB_MAX_VL_0_3;
830 break;
831 case MLX5_VL_HW_0_7:
832 *max_vl_num = __IB_MAX_VL_0_7;
833 break;
834 case MLX5_VL_HW_0_14:
835 *max_vl_num = __IB_MAX_VL_0_14;
836 break;
e126ba97 837
1b5daf11
MD		 838 default:
839 return -EINVAL;
e126ba97 840 }
e126ba97 841
1b5daf11 842 return 0;
e126ba97
EC		 843}
844
1b5daf11
MD		 845static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
846 struct ib_port_attr *props)
e126ba97 847{
1b5daf11
MD		 848 struct mlx5_ib_dev *dev = to_mdev(ibdev);
849 struct mlx5_core_dev *mdev = dev->mdev;
850 struct mlx5_hca_vport_context *rep;
046339ea
SM		 851 u16 max_mtu;
852 u16 oper_mtu;
1b5daf11
MD		 853 int err;
854 u8 ib_link_width_oper;
855 u8 vl_hw_cap;
e126ba97 856
1b5daf11
MD		 857 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
858 if (!rep) {
859 err = -ENOMEM;
e126ba97 860 goto out;
e126ba97 861 }
e126ba97 862
c4550c63 863 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 864
1b5daf11 865 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 866 if (err)
867 goto out;
868
1b5daf11
MD		 869 props->lid = rep->lid;
870 props->lmc = rep->lmc;
871 props->sm_lid = rep->sm_lid;
872 props->sm_sl = rep->sm_sl;
873 props->state = rep->vport_state;
874 props->phys_state = rep->port_physical_state;
875 props->port_cap_flags = rep->cap_mask1;
876 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
877 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
878 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
879 props->bad_pkey_cntr = rep->pkey_violation_counter;
880 props->qkey_viol_cntr = rep->qkey_violation_counter;
881 props->subnet_timeout = rep->subnet_timeout;
882 props->init_type_reply = rep->init_type_reply;
eff901d3 883 props->grh_required = rep->grh_required;
e126ba97 884
1b5daf11
MD		 885 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
886 if (err)
e126ba97 887 goto out;
e126ba97 888
1b5daf11
MD		 889 err = translate_active_width(ibdev, ib_link_width_oper,
890 &props->active_width);
891 if (err)
892 goto out;
d5beb7f2 893 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 894 if (err)
895 goto out;
896
facc9699 897 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 898
1b5daf11 899 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 900
facc9699 901 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 902
1b5daf11 903 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 904
1b5daf11
MD		 905 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
906 if (err)
907 goto out;
e126ba97 908
1b5daf11
MD		 909 err = translate_max_vl_num(ibdev, vl_hw_cap,
910 &props->max_vl_num);
e126ba97 911out:
1b5daf11 912 kfree(rep);
e126ba97
EC		 913 return err;
914}
915
1b5daf11
MD		 916int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
917 struct ib_port_attr *props)
e126ba97 918{
1b5daf11
MD		 919 switch (mlx5_get_vport_access_method(ibdev)) {
920 case MLX5_VPORT_ACCESS_METHOD_MAD:
921 return mlx5_query_mad_ifc_port(ibdev, port, props);
e126ba97 922
1b5daf11
MD		 923 case MLX5_VPORT_ACCESS_METHOD_HCA:
924 return mlx5_query_hca_port(ibdev, port, props);
e126ba97 925
3f89a643
AS		 926 case MLX5_VPORT_ACCESS_METHOD_NIC:
927 return mlx5_query_port_roce(ibdev, port, props);
928
1b5daf11
MD		 929 default:
930 return -EINVAL;
931 }
932}
e126ba97 933
1b5daf11
MD		 934static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
935 union ib_gid *gid)
936{
937 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 939
1b5daf11
MD		 940 switch (mlx5_get_vport_access_method(ibdev)) {
941 case MLX5_VPORT_ACCESS_METHOD_MAD:
942 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 943
1b5daf11
MD		 944 case MLX5_VPORT_ACCESS_METHOD_HCA:
945 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
946
947 default:
948 return -EINVAL;
949 }
e126ba97 950
e126ba97
EC		 951}
952
1b5daf11
MD		 953static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
954 u16 *pkey)
955{
956 struct mlx5_ib_dev *dev = to_mdev(ibdev);
957 struct mlx5_core_dev *mdev = dev->mdev;
958
959 switch (mlx5_get_vport_access_method(ibdev)) {
960 case MLX5_VPORT_ACCESS_METHOD_MAD:
961 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
962
963 case MLX5_VPORT_ACCESS_METHOD_HCA:
964 case MLX5_VPORT_ACCESS_METHOD_NIC:
965 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
966 pkey);
967 default:
968 return -EINVAL;
969 }
970}
e126ba97
EC		 971
972static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
973 struct ib_device_modify *props)
974{
975 struct mlx5_ib_dev *dev = to_mdev(ibdev);
976 struct mlx5_reg_node_desc in;
977 struct mlx5_reg_node_desc out;
978 int err;
979
980 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
981 return -EOPNOTSUPP;
982
983 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
984 return 0;
985
986 /*
987 * If possible, pass node desc to FW, so it can generate
988 * a 144 trap. If cmd fails, just ignore.
989 */
bd99fdea 990 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 991 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 992 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
993 if (err)
994 return err;
995
bd99fdea 996 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 997
998 return err;
999}
1000
cdbe33d0
EC		 1001static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1002 u32 value)
1003{
1004 struct mlx5_hca_vport_context ctx = {};
1005 int err;
1006
1007 err = mlx5_query_hca_vport_context(dev->mdev, 0,
1008 port_num, 0, &ctx);
1009 if (err)
1010 return err;
1011
1012 if (~ctx.cap_mask1_perm & mask) {
1013 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1014 mask, ctx.cap_mask1_perm);
1015 return -EINVAL;
1016 }
1017
1018 ctx.cap_mask1 = value;
1019 ctx.cap_mask1_perm = mask;
1020 err = mlx5_core_modify_hca_vport_context(dev->mdev, 0,
1021 port_num, 0, &ctx);
1022
1023 return err;
1024}
1025
e126ba97
EC		 1026static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1027 struct ib_port_modify *props)
1028{
1029 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1030 struct ib_port_attr attr;
1031 u32 tmp;
1032 int err;
cdbe33d0
EC		 1033 u32 change_mask;
1034 u32 value;
1035 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1036 IB_LINK_LAYER_INFINIBAND);
1037
1038 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1039 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1040 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1041 return set_port_caps_atomic(dev, port, change_mask, value);
1042 }
e126ba97
EC		 1043
1044 mutex_lock(&dev->cap_mask_mutex);
1045
c4550c63 1046 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1047 if (err)
1048 goto out;
1049
1050 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1051 ~props->clr_port_cap_mask;
1052
9603b61d 1053 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1054
1055out:
1056 mutex_unlock(&dev->cap_mask_mutex);
1057 return err;
1058}
1059
30aa60b3
EC		 1060static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1061{
1062 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1063 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1064}
1065
b037c29a
EC		 1066static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1067 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1068 u32 *num_sys_pages)
1069{
1070 int uars_per_sys_page;
1071 int bfregs_per_sys_page;
1072 int ref_bfregs = req->total_num_bfregs;
1073
1074 if (req->total_num_bfregs == 0)
1075 return -EINVAL;
1076
1077 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1078 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1079
1080 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1081 return -ENOMEM;
1082
1083 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1084 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1085 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1086 *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1087
1088 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1089 return -EINVAL;
1090
1091 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, alloated %d, using %d sys pages\n",
1092 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1093 lib_uar_4k ? "yes" : "no", ref_bfregs,
1094 req->total_num_bfregs, *num_sys_pages);
1095
1096 return 0;
1097}
1098
1099static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1100{
1101 struct mlx5_bfreg_info *bfregi;
1102 int err;
1103 int i;
1104
1105 bfregi = &context->bfregi;
1106 for (i = 0; i < bfregi->num_sys_pages; i++) {
1107 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1108 if (err)
1109 goto error;
1110
1111 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1112 }
1113 return 0;
1114
1115error:
1116 for (--i; i >= 0; i--)
1117 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1118 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1119
1120 return err;
1121}
1122
1123static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1124{
1125 struct mlx5_bfreg_info *bfregi;
1126 int err;
1127 int i;
1128
1129 bfregi = &context->bfregi;
1130 for (i = 0; i < bfregi->num_sys_pages; i++) {
1131 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1132 if (err) {
1133 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1134 return err;
1135 }
1136 }
1137 return 0;
1138}
1139
e126ba97
EC		 1140static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1141 struct ib_udata *udata)
1142{
1143 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1144 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1145 struct mlx5_ib_alloc_ucontext_resp resp = {};
e126ba97 1146 struct mlx5_ib_ucontext *context;
2f5ff264 1147 struct mlx5_bfreg_info *bfregi;
78c0f98c 1148 int ver;
e126ba97 1149 int err;
f241e749 1150 size_t reqlen;
a168a41c
MD		 1151 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1152 max_cqe_version);
b037c29a 1153 bool lib_uar_4k;
e126ba97
EC		 1154
1155 if (!dev->ib_active)
1156 return ERR_PTR(-EAGAIN);
1157
dfbee859
HA		 1158 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
1159 return ERR_PTR(-EINVAL);
1160
78c0f98c
EC		 1161 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
1162 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1163 ver = 0;
a168a41c 1164 else if (reqlen >= min_req_v2)
78c0f98c
EC		 1165 ver = 2;
1166 else
1167 return ERR_PTR(-EINVAL);
1168
b368d7cb 1169 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
e126ba97
EC		 1170 if (err)
1171 return ERR_PTR(err);
1172
b368d7cb 1173 if (req.flags)
78c0f98c
EC		 1174 return ERR_PTR(-EINVAL);
1175
f72300c5 1176 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 1177 return ERR_PTR(-EOPNOTSUPP);
1178
2f5ff264
EC		 1179 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1180 MLX5_NON_FP_BFREGS_PER_UAR);
1181 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
e126ba97
EC		 1182 return ERR_PTR(-EINVAL);
1183
938fe83c 1184 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1185 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1186 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1187 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1188 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1189 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1190 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1191 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1192 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1193 resp.cqe_version = min_t(__u8,
1194 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1195 req.max_cqe_version);
30aa60b3
EC		 1196 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1197 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1198 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1199 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1200 resp.response_length = min(offsetof(typeof(resp), response_length) +
1201 sizeof(resp.response_length), udata->outlen);
e126ba97
EC		 1202
1203 context = kzalloc(sizeof(*context), GFP_KERNEL);
1204 if (!context)
1205 return ERR_PTR(-ENOMEM);
1206
30aa60b3 1207 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1208 bfregi = &context->bfregi;
b037c29a
EC		 1209
1210 /* updates req->total_num_bfregs */
1211 err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages);
1212 if (err)
e126ba97 1213 goto out_ctx;
e126ba97 1214
b037c29a
EC		 1215 mutex_init(&bfregi->lock);
1216 bfregi->lib_uar_4k = lib_uar_4k;
1217 bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1218 GFP_KERNEL);
b037c29a 1219 if (!bfregi->count) {
e126ba97 1220 err = -ENOMEM;
b037c29a 1221 goto out_ctx;
e126ba97
EC		 1222 }
1223
b037c29a
EC		 1224 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1225 sizeof(*bfregi->sys_pages),
1226 GFP_KERNEL);
1227 if (!bfregi->sys_pages) {
e126ba97 1228 err = -ENOMEM;
b037c29a 1229 goto out_count;
e126ba97
EC		 1230 }
1231
b037c29a
EC		 1232 err = allocate_uars(dev, context);
1233 if (err)
1234 goto out_sys_pages;
e126ba97 1235
b4cfe447
HE		 1236#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1237 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1238#endif
1239
7d0cc6ed
AK		 1240 context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1241 if (!context->upd_xlt_page) {
1242 err = -ENOMEM;
1243 goto out_uars;
1244 }
1245 mutex_init(&context->upd_xlt_page_mutex);
1246
146d2f1a 1247 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1248 err = mlx5_core_alloc_transport_domain(dev->mdev,
1249 &context->tdn);
1250 if (err)
7d0cc6ed 1251 goto out_page;
146d2f1a 1252 }
1253
7c2344c3 1254 INIT_LIST_HEAD(&context->vma_private_list);
e126ba97
EC		 1255 INIT_LIST_HEAD(&context->db_page_list);
1256 mutex_init(&context->db_page_mutex);
1257
2f5ff264 1258 resp.tot_bfregs = req.total_num_bfregs;
938fe83c 1259 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
b368d7cb 1260
f72300c5
HA		 1261 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1262 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1263
402ca536 1264 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1265 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1266 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1267 resp.response_length += sizeof(resp.cmds_supp_uhw);
1268 }
1269
78984898
OG		 1270 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1271 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1272 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1273 resp.eth_min_inline++;
1274 }
1275 resp.response_length += sizeof(resp.eth_min_inline);
1276 }
1277
bc5c6eed
NO		 1278 /*
1279 * We don't want to expose information from the PCI bar that is located
1280 * after 4096 bytes, so if the arch only supports larger pages, let's
1281 * pretend we don't support reading the HCA's core clock. This is also
1282 * forced by mmap function.
1283 */
de8d6e02
EC		 1284 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1285 if (PAGE_SIZE <= 4096) {
1286 resp.comp_mask |=
1287 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1288 resp.hca_core_clock_offset =
1289 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1290 }
f72300c5 1291 resp.response_length += sizeof(resp.hca_core_clock_offset) +
402ca536 1292 sizeof(resp.reserved2);
b368d7cb
MB		 1293 }
1294
30aa60b3
EC		 1295 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1296 resp.response_length += sizeof(resp.log_uar_size);
1297
1298 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1299 resp.response_length += sizeof(resp.num_uars_per_page);
1300
b368d7cb 1301 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1302 if (err)
146d2f1a 1303 goto out_td;
e126ba97 1304
2f5ff264
EC		 1305 bfregi->ver = ver;
1306 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1307 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1308 context->lib_caps = req.lib_caps;
1309 print_lib_caps(dev, context->lib_caps);
f72300c5 1310
e126ba97
EC		 1311 return &context->ibucontext;
1312
146d2f1a 1313out_td:
1314 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1315 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1316
7d0cc6ed
AK		 1317out_page:
1318 free_page(context->upd_xlt_page);
1319
e126ba97 1320out_uars:
b037c29a 1321 deallocate_uars(dev, context);
e126ba97 1322
b037c29a
EC		 1323out_sys_pages:
1324 kfree(bfregi->sys_pages);
e126ba97 1325
b037c29a
EC		 1326out_count:
1327 kfree(bfregi->count);
e126ba97
EC		 1328
1329out_ctx:
1330 kfree(context);
b037c29a 1331
e126ba97
EC		 1332 return ERR_PTR(err);
1333}
1334
1335static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1336{
1337 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1338 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 1339 struct mlx5_bfreg_info *bfregi;
e126ba97 1340
b037c29a 1341 bfregi = &context->bfregi;
146d2f1a 1342 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1343 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1344
7d0cc6ed 1345 free_page(context->upd_xlt_page);
b037c29a
EC		 1346 deallocate_uars(dev, context);
1347 kfree(bfregi->sys_pages);
2f5ff264 1348 kfree(bfregi->count);
e126ba97
EC		 1349 kfree(context);
1350
1351 return 0;
1352}
1353
b037c29a
EC		 1354static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1355 struct mlx5_bfreg_info *bfregi,
1356 int idx)
e126ba97 1357{
b037c29a
EC		 1358 int fw_uars_per_page;
1359
1360 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1361
1362 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) +
1363 bfregi->sys_pages[idx] / fw_uars_per_page;
e126ba97
EC		 1364}
1365
1366static int get_command(unsigned long offset)
1367{
1368 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1369}
1370
1371static int get_arg(unsigned long offset)
1372{
1373 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1374}
1375
1376static int get_index(unsigned long offset)
1377{
1378 return get_arg(offset);
1379}
1380
7c2344c3
MG		 1381static void mlx5_ib_vma_open(struct vm_area_struct *area)
1382{
1383 /* vma_open is called when a new VMA is created on top of our VMA. This
1384 * is done through either mremap flow or split_vma (usually due to
1385 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1386 * as this VMA is strongly hardware related. Therefore we set the
1387 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1388 * calling us again and trying to do incorrect actions. We assume that
1389 * the original VMA size is exactly a single page, and therefore all
1390 * "splitting" operation will not happen to it.
1391 */
1392 area->vm_ops = NULL;
1393}
1394
1395static void mlx5_ib_vma_close(struct vm_area_struct *area)
1396{
1397 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1398
1399 /* It's guaranteed that all VMAs opened on a FD are closed before the
1400 * file itself is closed, therefore no sync is needed with the regular
1401 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1402 * However need a sync with accessing the vma as part of
1403 * mlx5_ib_disassociate_ucontext.
1404 * The close operation is usually called under mm->mmap_sem except when
1405 * process is exiting.
1406 * The exiting case is handled explicitly as part of
1407 * mlx5_ib_disassociate_ucontext.
1408 */
1409 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1410
1411 /* setting the vma context pointer to null in the mlx5_ib driver's
1412 * private data, to protect a race condition in
1413 * mlx5_ib_disassociate_ucontext().
1414 */
1415 mlx5_ib_vma_priv_data->vma = NULL;
1416 list_del(&mlx5_ib_vma_priv_data->list);
1417 kfree(mlx5_ib_vma_priv_data);
1418}
1419
1420static const struct vm_operations_struct mlx5_ib_vm_ops = {
1421 .open = mlx5_ib_vma_open,
1422 .close = mlx5_ib_vma_close
1423};
1424
1425static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1426 struct mlx5_ib_ucontext *ctx)
1427{
1428 struct mlx5_ib_vma_private_data *vma_prv;
1429 struct list_head *vma_head = &ctx->vma_private_list;
1430
1431 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1432 if (!vma_prv)
1433 return -ENOMEM;
1434
1435 vma_prv->vma = vma;
1436 vma->vm_private_data = vma_prv;
1437 vma->vm_ops = &mlx5_ib_vm_ops;
1438
1439 list_add(&vma_prv->list, vma_head);
1440
1441 return 0;
1442}
1443
1444static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1445{
1446 int ret;
1447 struct vm_area_struct *vma;
1448 struct mlx5_ib_vma_private_data *vma_private, *n;
1449 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1450 struct task_struct *owning_process = NULL;
1451 struct mm_struct *owning_mm = NULL;
1452
1453 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1454 if (!owning_process)
1455 return;
1456
1457 owning_mm = get_task_mm(owning_process);
1458 if (!owning_mm) {
1459 pr_info("no mm, disassociate ucontext is pending task termination\n");
1460 while (1) {
1461 put_task_struct(owning_process);
1462 usleep_range(1000, 2000);
1463 owning_process = get_pid_task(ibcontext->tgid,
1464 PIDTYPE_PID);
1465 if (!owning_process ||
1466 owning_process->state == TASK_DEAD) {
1467 pr_info("disassociate ucontext done, task was terminated\n");
1468 /* in case task was dead need to release the
1469 * task struct.
1470 */
1471 if (owning_process)
1472 put_task_struct(owning_process);
1473 return;
1474 }
1475 }
1476 }
1477
1478 /* need to protect from a race on closing the vma as part of
1479 * mlx5_ib_vma_close.
1480 */
ecc7d83b 1481 down_write(&owning_mm->mmap_sem);
7c2344c3
MG		 1482 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1483 list) {
1484 vma = vma_private->vma;
1485 ret = zap_vma_ptes(vma, vma->vm_start,
1486 PAGE_SIZE);
1487 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1488 /* context going to be destroyed, should
1489 * not access ops any more.
1490 */
13776612 1491 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
7c2344c3
MG		 1492 vma->vm_ops = NULL;
1493 list_del(&vma_private->list);
1494 kfree(vma_private);
1495 }
ecc7d83b 1496 up_write(&owning_mm->mmap_sem);
7c2344c3
MG		 1497 mmput(owning_mm);
1498 put_task_struct(owning_process);
1499}
1500
37aa5c36
GL		 1501static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1502{
1503 switch (cmd) {
1504 case MLX5_IB_MMAP_WC_PAGE:
1505 return "WC";
1506 case MLX5_IB_MMAP_REGULAR_PAGE:
1507 return "best effort WC";
1508 case MLX5_IB_MMAP_NC_PAGE:
1509 return "NC";
1510 default:
1511 return NULL;
1512 }
1513}
1514
1515static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 1516 struct vm_area_struct *vma,
1517 struct mlx5_ib_ucontext *context)
37aa5c36 1518{
2f5ff264 1519 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 1520 int err;
1521 unsigned long idx;
1522 phys_addr_t pfn, pa;
1523 pgprot_t prot;
b037c29a
EC		 1524 int uars_per_page;
1525
1526 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1527 return -EINVAL;
1528
1529 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
1530 idx = get_index(vma->vm_pgoff);
1531 if (idx % uars_per_page ||
1532 idx * uars_per_page >= bfregi->num_sys_pages) {
1533 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx);
1534 return -EINVAL;
1535 }
37aa5c36
GL		 1536
1537 switch (cmd) {
1538 case MLX5_IB_MMAP_WC_PAGE:
1539/* Some architectures don't support WC memory */
1540#if defined(CONFIG_X86)
1541 if (!pat_enabled())
1542 return -EPERM;
1543#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1544 return -EPERM;
1545#endif
1546 /* fall through */
1547 case MLX5_IB_MMAP_REGULAR_PAGE:
1548 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1549 prot = pgprot_writecombine(vma->vm_page_prot);
1550 break;
1551 case MLX5_IB_MMAP_NC_PAGE:
1552 prot = pgprot_noncached(vma->vm_page_prot);
1553 break;
1554 default:
1555 return -EINVAL;
1556 }
1557
b037c29a 1558 pfn = uar_index2pfn(dev, bfregi, idx);
37aa5c36
GL		 1559 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1560
1561 vma->vm_page_prot = prot;
1562 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1563 PAGE_SIZE, vma->vm_page_prot);
1564 if (err) {
1565 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1566 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1567 return -EAGAIN;
1568 }
1569
1570 pa = pfn << PAGE_SHIFT;
1571 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1572 vma->vm_start, &pa);
1573
7c2344c3 1574 return mlx5_ib_set_vma_data(vma, context);
37aa5c36
GL		 1575}
1576
e126ba97
EC		 1577static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1578{
1579 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1580 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 1581 unsigned long command;
e126ba97
EC		 1582 phys_addr_t pfn;
1583
1584 command = get_command(vma->vm_pgoff);
1585 switch (command) {
37aa5c36
GL		 1586 case MLX5_IB_MMAP_WC_PAGE:
1587 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 1588 case MLX5_IB_MMAP_REGULAR_PAGE:
7c2344c3 1589 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 1590
1591 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1592 return -ENOSYS;
1593
d69e3bcf 1594 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 1595 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1596 return -EINVAL;
1597
6cbac1e4 1598 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 1599 return -EPERM;
1600
1601 /* Don't expose to user-space information it shouldn't have */
1602 if (PAGE_SIZE > 4096)
1603 return -EOPNOTSUPP;
1604
1605 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1606 pfn = (dev->mdev->iseg_base +
1607 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1608 PAGE_SHIFT;
1609 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1610 PAGE_SIZE, vma->vm_page_prot))
1611 return -EAGAIN;
1612
1613 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1614 vma->vm_start,
1615 (unsigned long long)pfn << PAGE_SHIFT);
1616 break;
d69e3bcf 1617
e126ba97
EC		 1618 default:
1619 return -EINVAL;
1620 }
1621
1622 return 0;
1623}
1624
e126ba97
EC		 1625static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1626 struct ib_ucontext *context,
1627 struct ib_udata *udata)
1628{
1629 struct mlx5_ib_alloc_pd_resp resp;
1630 struct mlx5_ib_pd *pd;
1631 int err;
1632
1633 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1634 if (!pd)
1635 return ERR_PTR(-ENOMEM);
1636
9603b61d 1637 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 1638 if (err) {
1639 kfree(pd);
1640 return ERR_PTR(err);
1641 }
1642
1643 if (context) {
1644 resp.pdn = pd->pdn;
1645 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 1646 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 1647 kfree(pd);
1648 return ERR_PTR(-EFAULT);
1649 }
e126ba97
EC		 1650 }
1651
1652 return &pd->ibpd;
1653}
1654
1655static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1656{
1657 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1658 struct mlx5_ib_pd *mpd = to_mpd(pd);
1659
9603b61d 1660 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 1661 kfree(mpd);
1662
1663 return 0;
1664}
1665
466fa6d2
MG		 1666enum {
1667 MATCH_CRITERIA_ENABLE_OUTER_BIT,
1668 MATCH_CRITERIA_ENABLE_MISC_BIT,
1669 MATCH_CRITERIA_ENABLE_INNER_BIT
1670};
1671
1672#define HEADER_IS_ZERO(match_criteria, headers) \
1673 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1674 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 1675
466fa6d2 1676static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 1677{
466fa6d2 1678 u8 match_criteria_enable;
038d2ef8 1679
466fa6d2
MG		 1680 match_criteria_enable =
1681 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1682 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1683 match_criteria_enable |=
1684 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1685 MATCH_CRITERIA_ENABLE_MISC_BIT;
1686 match_criteria_enable |=
1687 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1688 MATCH_CRITERIA_ENABLE_INNER_BIT;
1689
1690 return match_criteria_enable;
038d2ef8
MG		 1691}
1692
ca0d4753
MG		 1693static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1694{
1695 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1696 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
038d2ef8
MG		 1697}
1698
2d1e697e
MR		 1699static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
1700 bool inner)
1701{
1702 if (inner) {
1703 MLX5_SET(fte_match_set_misc,
1704 misc_c, inner_ipv6_flow_label, mask);
1705 MLX5_SET(fte_match_set_misc,
1706 misc_v, inner_ipv6_flow_label, val);
1707 } else {
1708 MLX5_SET(fte_match_set_misc,
1709 misc_c, outer_ipv6_flow_label, mask);
1710 MLX5_SET(fte_match_set_misc,
1711 misc_v, outer_ipv6_flow_label, val);
1712 }
1713}
1714
ca0d4753
MG		 1715static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1716{
1717 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1718 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1719 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1720 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1721}
1722
c47ac6ae
MG		 1723#define LAST_ETH_FIELD vlan_tag
1724#define LAST_IB_FIELD sl
ca0d4753 1725#define LAST_IPV4_FIELD tos
466fa6d2 1726#define LAST_IPV6_FIELD traffic_class
c47ac6ae 1727#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 1728#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 1729#define LAST_FLOW_TAG_FIELD tag_id
c47ac6ae
MG		 1730
1731/* Field is the last supported field */
1732#define FIELDS_NOT_SUPPORTED(filter, field)\
1733 memchr_inv((void *)&filter.field +\
1734 sizeof(filter.field), 0,\
1735 sizeof(filter) -\
1736 offsetof(typeof(filter), field) -\
1737 sizeof(filter.field))
1738
038d2ef8 1739static int parse_flow_attr(u32 *match_c, u32 *match_v,
2ac693f9 1740 const union ib_flow_spec *ib_spec, u32 *tag_id)
038d2ef8 1741{
466fa6d2
MG		 1742 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1743 misc_parameters);
1744 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1745 misc_parameters);
2d1e697e
MR		 1746 void *headers_c;
1747 void *headers_v;
1748
1749 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
1750 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1751 inner_headers);
1752 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1753 inner_headers);
1754 } else {
1755 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1756 outer_headers);
1757 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1758 outer_headers);
1759 }
466fa6d2 1760
2d1e697e 1761 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 1762 case IB_FLOW_SPEC_ETH:
c47ac6ae 1763 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 1764 return -EOPNOTSUPP;
038d2ef8 1765
2d1e697e 1766 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1767 dmac_47_16),
1768 ib_spec->eth.mask.dst_mac);
2d1e697e 1769 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1770 dmac_47_16),
1771 ib_spec->eth.val.dst_mac);
1772
2d1e697e 1773 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 1774 smac_47_16),
1775 ib_spec->eth.mask.src_mac);
2d1e697e 1776 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 1777 smac_47_16),
1778 ib_spec->eth.val.src_mac);
1779
038d2ef8 1780 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 1781 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 1782 cvlan_tag, 1);
2d1e697e 1783 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 1784 cvlan_tag, 1);
038d2ef8 1785
2d1e697e 1786 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 1787 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 1788 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1789 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1790
2d1e697e 1791 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1792 first_cfi,
1793 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 1794 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1795 first_cfi,
1796 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1797
2d1e697e 1798 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1799 first_prio,
1800 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 1801 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1802 first_prio,
1803 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1804 }
2d1e697e 1805 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 1806 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 1807 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1808 ethertype, ntohs(ib_spec->eth.val.ether_type));
1809 break;
1810 case IB_FLOW_SPEC_IPV4:
c47ac6ae 1811 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 1812 return -EOPNOTSUPP;
038d2ef8 1813
2d1e697e 1814 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 1815 ethertype, 0xffff);
2d1e697e 1816 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1817 ethertype, ETH_P_IP);
1818
2d1e697e 1819 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1820 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1821 &ib_spec->ipv4.mask.src_ip,
1822 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 1823 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1824 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1825 &ib_spec->ipv4.val.src_ip,
1826 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 1827 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1828 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1829 &ib_spec->ipv4.mask.dst_ip,
1830 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 1831 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1832 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1833 &ib_spec->ipv4.val.dst_ip,
1834 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 1835
2d1e697e 1836 set_tos(headers_c, headers_v,
ca0d4753
MG		 1837 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1838
2d1e697e 1839 set_proto(headers_c, headers_v,
ca0d4753 1840 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
038d2ef8 1841 break;
026bae0c 1842 case IB_FLOW_SPEC_IPV6:
c47ac6ae 1843 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 1844 return -EOPNOTSUPP;
026bae0c 1845
2d1e697e 1846 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
026bae0c 1847 ethertype, 0xffff);
2d1e697e 1848 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 1849 ethertype, ETH_P_IPV6);
1850
2d1e697e 1851 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 1852 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1853 &ib_spec->ipv6.mask.src_ip,
1854 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 1855 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 1856 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1857 &ib_spec->ipv6.val.src_ip,
1858 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 1859 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 1860 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1861 &ib_spec->ipv6.mask.dst_ip,
1862 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 1863 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 1864 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1865 &ib_spec->ipv6.val.dst_ip,
1866 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 1867
2d1e697e 1868 set_tos(headers_c, headers_v,
466fa6d2
MG		 1869 ib_spec->ipv6.mask.traffic_class,
1870 ib_spec->ipv6.val.traffic_class);
1871
2d1e697e 1872 set_proto(headers_c, headers_v,
466fa6d2
MG		 1873 ib_spec->ipv6.mask.next_hdr,
1874 ib_spec->ipv6.val.next_hdr);
1875
2d1e697e
MR		 1876 set_flow_label(misc_params_c, misc_params_v,
1877 ntohl(ib_spec->ipv6.mask.flow_label),
1878 ntohl(ib_spec->ipv6.val.flow_label),
1879 ib_spec->type & IB_FLOW_SPEC_INNER);
1880
026bae0c 1881 break;
038d2ef8 1882 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 1883 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1884 LAST_TCP_UDP_FIELD))
1ffd3a26 1885 return -EOPNOTSUPP;
038d2ef8 1886
2d1e697e 1887 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 1888 0xff);
2d1e697e 1889 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 1890 IPPROTO_TCP);
1891
2d1e697e 1892 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 1893 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 1894 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 1895 ntohs(ib_spec->tcp_udp.val.src_port));
1896
2d1e697e 1897 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 1898 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 1899 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 1900 ntohs(ib_spec->tcp_udp.val.dst_port));
1901 break;
1902 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 1903 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1904 LAST_TCP_UDP_FIELD))
1ffd3a26 1905 return -EOPNOTSUPP;
038d2ef8 1906
2d1e697e 1907 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 1908 0xff);
2d1e697e 1909 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 1910 IPPROTO_UDP);
1911
2d1e697e 1912 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 1913 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 1914 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 1915 ntohs(ib_spec->tcp_udp.val.src_port));
1916
2d1e697e 1917 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 1918 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 1919 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 1920 ntohs(ib_spec->tcp_udp.val.dst_port));
1921 break;
ffb30d8f
MR		 1922 case IB_FLOW_SPEC_VXLAN_TUNNEL:
1923 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
1924 LAST_TUNNEL_FIELD))
1ffd3a26 1925 return -EOPNOTSUPP;
ffb30d8f
MR		 1926
1927 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
1928 ntohl(ib_spec->tunnel.mask.tunnel_id));
1929 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
1930 ntohl(ib_spec->tunnel.val.tunnel_id));
1931 break;
2ac693f9
MR		 1932 case IB_FLOW_SPEC_ACTION_TAG:
1933 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
1934 LAST_FLOW_TAG_FIELD))
1935 return -EOPNOTSUPP;
1936 if (ib_spec->flow_tag.tag_id >= BIT(24))
1937 return -EINVAL;
1938
1939 *tag_id = ib_spec->flow_tag.tag_id;
1940 break;
038d2ef8
MG		 1941 default:
1942 return -EINVAL;
1943 }
1944
1945 return 0;
1946}
1947
1948/* If a flow could catch both multicast and unicast packets,
1949 * it won't fall into the multicast flow steering table and this rule
1950 * could steal other multicast packets.
1951 */
1952static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1953{
1954 struct ib_flow_spec_eth *eth_spec;
1955
1956 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1957 ib_attr->size < sizeof(struct ib_flow_attr) +
1958 sizeof(struct ib_flow_spec_eth) ||
1959 ib_attr->num_of_specs < 1)
1960 return false;
1961
1962 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1963 if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1964 eth_spec->size != sizeof(*eth_spec))
1965 return false;
1966
1967 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1968 is_multicast_ether_addr(eth_spec->val.dst_mac);
1969}
1970
0f750966
AL		 1971static bool is_valid_ethertype(const struct ib_flow_attr *flow_attr,
1972 bool check_inner)
038d2ef8
MG		 1973{
1974 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
0f750966
AL		 1975 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
1976 bool ipv4_spec_valid, ipv6_spec_valid;
1977 unsigned int ip_spec_type = 0;
1978 bool has_ethertype = false;
038d2ef8 1979 unsigned int spec_index;
0f750966
AL		 1980 bool mask_valid = true;
1981 u16 eth_type = 0;
1982 bool type_valid;
038d2ef8
MG		 1983
1984 /* Validate that ethertype is correct */
1985 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 1986 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 1987 ib_spec->eth.mask.ether_type) {
0f750966
AL		 1988 mask_valid = (ib_spec->eth.mask.ether_type ==
1989 htons(0xffff));
1990 has_ethertype = true;
1991 eth_type = ntohs(ib_spec->eth.val.ether_type);
1992 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
1993 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
1994 ip_spec_type = ib_spec->type;
038d2ef8
MG		 1995 }
1996 ib_spec = (void *)ib_spec + ib_spec->size;
1997 }
0f750966
AL		 1998
1999 type_valid = (!has_ethertype) || (!ip_spec_type);
2000 if (!type_valid && mask_valid) {
2001 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2002 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2003 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2004 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
2005 type_valid = ipv4_spec_valid || ipv6_spec_valid;
2006 }
2007
2008 return type_valid;
2009}
2010
2011static bool is_valid_attr(const struct ib_flow_attr *flow_attr)
2012{
2013 return is_valid_ethertype(flow_attr, false) &&
2014 is_valid_ethertype(flow_attr, true);
038d2ef8
MG		 2015}
2016
2017static void put_flow_table(struct mlx5_ib_dev *dev,
2018 struct mlx5_ib_flow_prio *prio, bool ft_added)
2019{
2020 prio->refcount -= !!ft_added;
2021 if (!prio->refcount) {
2022 mlx5_destroy_flow_table(prio->flow_table);
2023 prio->flow_table = NULL;
2024 }
2025}
2026
2027static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2028{
2029 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2030 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2031 struct mlx5_ib_flow_handler,
2032 ibflow);
2033 struct mlx5_ib_flow_handler *iter, *tmp;
2034
2035 mutex_lock(&dev->flow_db.lock);
2036
2037 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 2038 mlx5_del_flow_rules(iter->rule);
cc0e5d42 2039 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 2040 list_del(&iter->list);
2041 kfree(iter);
2042 }
2043
74491de9 2044 mlx5_del_flow_rules(handler->rule);
5497adc6 2045 put_flow_table(dev, handler->prio, true);
038d2ef8
MG		 2046 mutex_unlock(&dev->flow_db.lock);
2047
2048 kfree(handler);
2049
2050 return 0;
2051}
2052
35d19011
MG		 2053static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2054{
2055 priority *= 2;
2056 if (!dont_trap)
2057 priority++;
2058 return priority;
2059}
2060
cc0e5d42
MG		 2061enum flow_table_type {
2062 MLX5_IB_FT_RX,
2063 MLX5_IB_FT_TX
2064};
2065
00b7c2ab
MG		 2066#define MLX5_FS_MAX_TYPES 6
2067#define MLX5_FS_MAX_ENTRIES BIT(16)
038d2ef8 2068static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 2069 struct ib_flow_attr *flow_attr,
2070 enum flow_table_type ft_type)
038d2ef8 2071{
35d19011 2072 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 2073 struct mlx5_flow_namespace *ns = NULL;
2074 struct mlx5_ib_flow_prio *prio;
2075 struct mlx5_flow_table *ft;
dac388ef 2076 int max_table_size;
038d2ef8
MG		 2077 int num_entries;
2078 int num_groups;
2079 int priority;
2080 int err = 0;
2081
dac388ef
MG		 2082 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2083 log_max_ft_size));
038d2ef8 2084 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2085 if (flow_is_multicast_only(flow_attr) &&
2086 !dont_trap)
038d2ef8
MG		 2087 priority = MLX5_IB_FLOW_MCAST_PRIO;
2088 else
35d19011
MG		 2089 priority = ib_prio_to_core_prio(flow_attr->priority,
2090 dont_trap);
038d2ef8
MG		 2091 ns = mlx5_get_flow_namespace(dev->mdev,
2092 MLX5_FLOW_NAMESPACE_BYPASS);
2093 num_entries = MLX5_FS_MAX_ENTRIES;
2094 num_groups = MLX5_FS_MAX_TYPES;
2095 prio = &dev->flow_db.prios[priority];
2096 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2097 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2098 ns = mlx5_get_flow_namespace(dev->mdev,
2099 MLX5_FLOW_NAMESPACE_LEFTOVERS);
2100 build_leftovers_ft_param(&priority,
2101 &num_entries,
2102 &num_groups);
2103 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 2104 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2105 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2106 allow_sniffer_and_nic_rx_shared_tir))
2107 return ERR_PTR(-ENOTSUPP);
2108
2109 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2110 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2111 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2112
2113 prio = &dev->flow_db.sniffer[ft_type];
2114 priority = 0;
2115 num_entries = 1;
2116 num_groups = 1;
038d2ef8
MG		 2117 }
2118
2119 if (!ns)
2120 return ERR_PTR(-ENOTSUPP);
2121
dac388ef
MG		 2122 if (num_entries > max_table_size)
2123 return ERR_PTR(-ENOMEM);
2124
038d2ef8
MG		 2125 ft = prio->flow_table;
2126 if (!ft) {
2127 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2128 num_entries,
d63cd286 2129 num_groups,
c9f1b073 2130 0, 0);
038d2ef8
MG		 2131
2132 if (!IS_ERR(ft)) {
2133 prio->refcount = 0;
2134 prio->flow_table = ft;
2135 } else {
2136 err = PTR_ERR(ft);
2137 }
2138 }
2139
2140 return err ? ERR_PTR(err) : prio;
2141}
2142
2143static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2144 struct mlx5_ib_flow_prio *ft_prio,
dd063d0e 2145 const struct ib_flow_attr *flow_attr,
038d2ef8
MG		 2146 struct mlx5_flow_destination *dst)
2147{
2148 struct mlx5_flow_table *ft = ft_prio->flow_table;
2149 struct mlx5_ib_flow_handler *handler;
66958ed9 2150 struct mlx5_flow_act flow_act = {0};
c5bb1730 2151 struct mlx5_flow_spec *spec;
dd063d0e 2152 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 2153 unsigned int spec_index;
2ac693f9 2154 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
038d2ef8
MG		 2155 int err = 0;
2156
2157 if (!is_valid_attr(flow_attr))
2158 return ERR_PTR(-EINVAL);
2159
c5bb1730 2160 spec = mlx5_vzalloc(sizeof(*spec));
038d2ef8 2161 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 2162 if (!handler || !spec) {
038d2ef8
MG		 2163 err = -ENOMEM;
2164 goto free;
2165 }
2166
2167 INIT_LIST_HEAD(&handler->list);
2168
2169 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
c5bb1730 2170 err = parse_flow_attr(spec->match_criteria,
2ac693f9 2171 spec->match_value, ib_flow, &flow_tag);
038d2ef8
MG		 2172 if (err < 0)
2173 goto free;
2174
2175 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2176 }
2177
466fa6d2 2178 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
66958ed9 2179 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
35d19011 2180 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2ac693f9
MR		 2181
2182 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG &&
2183 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2184 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
2185 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
2186 flow_tag, flow_attr->type);
2187 err = -EINVAL;
2188 goto free;
2189 }
2190 flow_act.flow_tag = flow_tag;
74491de9 2191 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9
HHZ		 2192 &flow_act,
2193 dst, 1);
038d2ef8
MG		 2194
2195 if (IS_ERR(handler->rule)) {
2196 err = PTR_ERR(handler->rule);
2197 goto free;
2198 }
2199
d9d4980a 2200 ft_prio->refcount++;
5497adc6 2201 handler->prio = ft_prio;
038d2ef8
MG		 2202
2203 ft_prio->flow_table = ft;
2204free:
2205 if (err)
2206 kfree(handler);
c5bb1730 2207 kvfree(spec);
038d2ef8
MG		 2208 return err ? ERR_PTR(err) : handler;
2209}
2210
35d19011
MG		 2211static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2212 struct mlx5_ib_flow_prio *ft_prio,
2213 struct ib_flow_attr *flow_attr,
2214 struct mlx5_flow_destination *dst)
2215{
2216 struct mlx5_ib_flow_handler *handler_dst = NULL;
2217 struct mlx5_ib_flow_handler *handler = NULL;
2218
2219 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2220 if (!IS_ERR(handler)) {
2221 handler_dst = create_flow_rule(dev, ft_prio,
2222 flow_attr, dst);
2223 if (IS_ERR(handler_dst)) {
74491de9 2224 mlx5_del_flow_rules(handler->rule);
d9d4980a 2225 ft_prio->refcount--;
35d19011
MG		 2226 kfree(handler);
2227 handler = handler_dst;
2228 } else {
2229 list_add(&handler_dst->list, &handler->list);
2230 }
2231 }
2232
2233 return handler;
2234}
038d2ef8
MG		 2235enum {
2236 LEFTOVERS_MC,
2237 LEFTOVERS_UC,
2238};
2239
2240static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2241 struct mlx5_ib_flow_prio *ft_prio,
2242 struct ib_flow_attr *flow_attr,
2243 struct mlx5_flow_destination *dst)
2244{
2245 struct mlx5_ib_flow_handler *handler_ucast = NULL;
2246 struct mlx5_ib_flow_handler *handler = NULL;
2247
2248 static struct {
2249 struct ib_flow_attr flow_attr;
2250 struct ib_flow_spec_eth eth_flow;
2251 } leftovers_specs[] = {
2252 [LEFTOVERS_MC] = {
2253 .flow_attr = {
2254 .num_of_specs = 1,
2255 .size = sizeof(leftovers_specs[0])
2256 },
2257 .eth_flow = {
2258 .type = IB_FLOW_SPEC_ETH,
2259 .size = sizeof(struct ib_flow_spec_eth),
2260 .mask = {.dst_mac = {0x1} },
2261 .val = {.dst_mac = {0x1} }
2262 }
2263 },
2264 [LEFTOVERS_UC] = {
2265 .flow_attr = {
2266 .num_of_specs = 1,
2267 .size = sizeof(leftovers_specs[0])
2268 },
2269 .eth_flow = {
2270 .type = IB_FLOW_SPEC_ETH,
2271 .size = sizeof(struct ib_flow_spec_eth),
2272 .mask = {.dst_mac = {0x1} },
2273 .val = {.dst_mac = {} }
2274 }
2275 }
2276 };
2277
2278 handler = create_flow_rule(dev, ft_prio,
2279 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2280 dst);
2281 if (!IS_ERR(handler) &&
2282 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2283 handler_ucast = create_flow_rule(dev, ft_prio,
2284 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2285 dst);
2286 if (IS_ERR(handler_ucast)) {
74491de9 2287 mlx5_del_flow_rules(handler->rule);
d9d4980a 2288 ft_prio->refcount--;
038d2ef8
MG		 2289 kfree(handler);
2290 handler = handler_ucast;
2291 } else {
2292 list_add(&handler_ucast->list, &handler->list);
2293 }
2294 }
2295
2296 return handler;
2297}
2298
cc0e5d42
MG		 2299static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2300 struct mlx5_ib_flow_prio *ft_rx,
2301 struct mlx5_ib_flow_prio *ft_tx,
2302 struct mlx5_flow_destination *dst)
2303{
2304 struct mlx5_ib_flow_handler *handler_rx;
2305 struct mlx5_ib_flow_handler *handler_tx;
2306 int err;
2307 static const struct ib_flow_attr flow_attr = {
2308 .num_of_specs = 0,
2309 .size = sizeof(flow_attr)
2310 };
2311
2312 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2313 if (IS_ERR(handler_rx)) {
2314 err = PTR_ERR(handler_rx);
2315 goto err;
2316 }
2317
2318 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2319 if (IS_ERR(handler_tx)) {
2320 err = PTR_ERR(handler_tx);
2321 goto err_tx;
2322 }
2323
2324 list_add(&handler_tx->list, &handler_rx->list);
2325
2326 return handler_rx;
2327
2328err_tx:
74491de9 2329 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 2330 ft_rx->refcount--;
2331 kfree(handler_rx);
2332err:
2333 return ERR_PTR(err);
2334}
2335
038d2ef8
MG		 2336static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2337 struct ib_flow_attr *flow_attr,
2338 int domain)
2339{
2340 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 2341 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 2342 struct mlx5_ib_flow_handler *handler = NULL;
2343 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 2344 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8
MG		 2345 struct mlx5_ib_flow_prio *ft_prio;
2346 int err;
2347
2348 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
dac388ef 2349 return ERR_PTR(-ENOMEM);
038d2ef8
MG		 2350
2351 if (domain != IB_FLOW_DOMAIN_USER ||
2352 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
35d19011 2353 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
038d2ef8
MG		 2354 return ERR_PTR(-EINVAL);
2355
2356 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2357 if (!dst)
2358 return ERR_PTR(-ENOMEM);
2359
2360 mutex_lock(&dev->flow_db.lock);
2361
cc0e5d42 2362 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
038d2ef8
MG		 2363 if (IS_ERR(ft_prio)) {
2364 err = PTR_ERR(ft_prio);
2365 goto unlock;
2366 }
cc0e5d42
MG		 2367 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2368 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2369 if (IS_ERR(ft_prio_tx)) {
2370 err = PTR_ERR(ft_prio_tx);
2371 ft_prio_tx = NULL;
2372 goto destroy_ft;
2373 }
2374 }
038d2ef8
MG		 2375
2376 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
d9f88e5a
YH		 2377 if (mqp->flags & MLX5_IB_QP_RSS)
2378 dst->tir_num = mqp->rss_qp.tirn;
2379 else
2380 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
038d2ef8
MG		 2381
2382 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2383 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2384 handler = create_dont_trap_rule(dev, ft_prio,
2385 flow_attr, dst);
2386 } else {
2387 handler = create_flow_rule(dev, ft_prio, flow_attr,
2388 dst);
2389 }
038d2ef8
MG		 2390 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2391 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2392 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2393 dst);
cc0e5d42
MG		 2394 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2395 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 2396 } else {
2397 err = -EINVAL;
2398 goto destroy_ft;
2399 }
2400
2401 if (IS_ERR(handler)) {
2402 err = PTR_ERR(handler);
2403 handler = NULL;
2404 goto destroy_ft;
2405 }
2406
038d2ef8
MG		 2407 mutex_unlock(&dev->flow_db.lock);
2408 kfree(dst);
2409
2410 return &handler->ibflow;
2411
2412destroy_ft:
2413 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 2414 if (ft_prio_tx)
2415 put_flow_table(dev, ft_prio_tx, false);
038d2ef8
MG		 2416unlock:
2417 mutex_unlock(&dev->flow_db.lock);
2418 kfree(dst);
2419 kfree(handler);
2420 return ERR_PTR(err);
2421}
2422
e126ba97
EC		 2423static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2424{
2425 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2426 int err;
2427
9603b61d 2428 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2429 if (err)
2430 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2431 ibqp->qp_num, gid->raw);
2432
2433 return err;
2434}
2435
2436static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2437{
2438 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2439 int err;
2440
9603b61d 2441 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2442 if (err)
2443 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2444 ibqp->qp_num, gid->raw);
2445
2446 return err;
2447}
2448
2449static int init_node_data(struct mlx5_ib_dev *dev)
2450{
1b5daf11 2451 int err;
e126ba97 2452
1b5daf11 2453 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 2454 if (err)
1b5daf11 2455 return err;
e126ba97 2456
1b5daf11 2457 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 2458
1b5daf11 2459 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 2460}
2461
2462static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2463 char *buf)
2464{
2465 struct mlx5_ib_dev *dev =
2466 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2467
9603b61d 2468 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 2469}
2470
2471static ssize_t show_reg_pages(struct device *device,
2472 struct device_attribute *attr, char *buf)
2473{
2474 struct mlx5_ib_dev *dev =
2475 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2476
6aec21f6 2477 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 2478}
2479
2480static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2481 char *buf)
2482{
2483 struct mlx5_ib_dev *dev =
2484 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 2485 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 2486}
2487
e126ba97
EC		 2488static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2489 char *buf)
2490{
2491 struct mlx5_ib_dev *dev =
2492 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 2493 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 2494}
2495
2496static ssize_t show_board(struct device *device, struct device_attribute *attr,
2497 char *buf)
2498{
2499 struct mlx5_ib_dev *dev =
2500 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2501 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 2502 dev->mdev->board_id);
e126ba97
EC		 2503}
2504
2505static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
e126ba97
EC		 2506static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2507static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2508static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2509static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2510
2511static struct device_attribute *mlx5_class_attributes[] = {
2512 &dev_attr_hw_rev,
e126ba97
EC		 2513 &dev_attr_hca_type,
2514 &dev_attr_board_id,
2515 &dev_attr_fw_pages,
2516 &dev_attr_reg_pages,
2517};
2518
7722f47e
HE		 2519static void pkey_change_handler(struct work_struct *work)
2520{
2521 struct mlx5_ib_port_resources *ports =
2522 container_of(work, struct mlx5_ib_port_resources,
2523 pkey_change_work);
2524
2525 mutex_lock(&ports->devr->mutex);
2526 mlx5_ib_gsi_pkey_change(ports->gsi);
2527 mutex_unlock(&ports->devr->mutex);
2528}
2529
89ea94a7
MG		 2530static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2531{
2532 struct mlx5_ib_qp *mqp;
2533 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2534 struct mlx5_core_cq *mcq;
2535 struct list_head cq_armed_list;
2536 unsigned long flags_qp;
2537 unsigned long flags_cq;
2538 unsigned long flags;
2539
2540 INIT_LIST_HEAD(&cq_armed_list);
2541
2542 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2543 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2544 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2545 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2546 if (mqp->sq.tail != mqp->sq.head) {
2547 send_mcq = to_mcq(mqp->ibqp.send_cq);
2548 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2549 if (send_mcq->mcq.comp &&
2550 mqp->ibqp.send_cq->comp_handler) {
2551 if (!send_mcq->mcq.reset_notify_added) {
2552 send_mcq->mcq.reset_notify_added = 1;
2553 list_add_tail(&send_mcq->mcq.reset_notify,
2554 &cq_armed_list);
2555 }
2556 }
2557 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2558 }
2559 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2560 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2561 /* no handling is needed for SRQ */
2562 if (!mqp->ibqp.srq) {
2563 if (mqp->rq.tail != mqp->rq.head) {
2564 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2565 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2566 if (recv_mcq->mcq.comp &&
2567 mqp->ibqp.recv_cq->comp_handler) {
2568 if (!recv_mcq->mcq.reset_notify_added) {
2569 recv_mcq->mcq.reset_notify_added = 1;
2570 list_add_tail(&recv_mcq->mcq.reset_notify,
2571 &cq_armed_list);
2572 }
2573 }
2574 spin_unlock_irqrestore(&recv_mcq->lock,
2575 flags_cq);
2576 }
2577 }
2578 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2579 }
2580 /*At that point all inflight post send were put to be executed as of we
2581 * lock/unlock above locks Now need to arm all involved CQs.
2582 */
2583 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2584 mcq->comp(mcq);
2585 }
2586 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2587}
2588
9603b61d 2589static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 2590 enum mlx5_dev_event event, unsigned long param)
e126ba97 2591{
9603b61d 2592 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
e126ba97 2593 struct ib_event ibev;
dbaaff2a 2594 bool fatal = false;
e126ba97
EC		 2595 u8 port = 0;
2596
2597 switch (event) {
2598 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 2599 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 2600 mlx5_ib_handle_internal_error(ibdev);
dbaaff2a 2601 fatal = true;
e126ba97
EC		 2602 break;
2603
2604 case MLX5_DEV_EVENT_PORT_UP:
e126ba97 2605 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 2606 case MLX5_DEV_EVENT_PORT_INITIALIZED:
4d2f9bbb 2607 port = (u8)param;
5ec8c83e
AH		 2608
2609 /* In RoCE, port up/down events are handled in
2610 * mlx5_netdev_event().
2611 */
2612 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2613 IB_LINK_LAYER_ETHERNET)
2614 return;
2615
2616 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2617 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
e126ba97
EC		 2618 break;
2619
e126ba97
EC		 2620 case MLX5_DEV_EVENT_LID_CHANGE:
2621 ibev.event = IB_EVENT_LID_CHANGE;
4d2f9bbb 2622 port = (u8)param;
e126ba97
EC		 2623 break;
2624
2625 case MLX5_DEV_EVENT_PKEY_CHANGE:
2626 ibev.event = IB_EVENT_PKEY_CHANGE;
4d2f9bbb 2627 port = (u8)param;
7722f47e
HE		 2628
2629 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 2630 break;
2631
2632 case MLX5_DEV_EVENT_GUID_CHANGE:
2633 ibev.event = IB_EVENT_GID_CHANGE;
4d2f9bbb 2634 port = (u8)param;
e126ba97
EC		 2635 break;
2636
2637 case MLX5_DEV_EVENT_CLIENT_REREG:
2638 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4d2f9bbb 2639 port = (u8)param;
e126ba97 2640 break;
bdc37924
SM		 2641 default:
2642 return;
e126ba97
EC		 2643 }
2644
2645 ibev.device = &ibdev->ib_dev;
2646 ibev.element.port_num = port;
2647
a0c84c32
EC		 2648 if (port < 1 || port > ibdev->num_ports) {
2649 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2650 return;
2651 }
2652
e126ba97
EC		 2653 if (ibdev->ib_active)
2654 ib_dispatch_event(&ibev);
dbaaff2a
EC		 2655
2656 if (fatal)
2657 ibdev->ib_active = false;
e126ba97
EC		 2658}
2659
c43f1112
MG		 2660static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2661{
2662 struct mlx5_hca_vport_context vport_ctx;
2663 int err;
2664 int port;
2665
2666 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2667 dev->mdev->port_caps[port - 1].has_smi = false;
2668 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
2669 MLX5_CAP_PORT_TYPE_IB) {
2670 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2671 err = mlx5_query_hca_vport_context(dev->mdev, 0,
2672 port, 0,
2673 &vport_ctx);
2674 if (err) {
2675 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2676 port, err);
2677 return err;
2678 }
2679 dev->mdev->port_caps[port - 1].has_smi =
2680 vport_ctx.has_smi;
2681 } else {
2682 dev->mdev->port_caps[port - 1].has_smi = true;
2683 }
2684 }
2685 }
2686 return 0;
2687}
2688
e126ba97
EC		 2689static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2690{
2691 int port;
2692
938fe83c 2693 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
e126ba97
EC		 2694 mlx5_query_ext_port_caps(dev, port);
2695}
2696
2697static int get_port_caps(struct mlx5_ib_dev *dev)
2698{
2699 struct ib_device_attr *dprops = NULL;
2700 struct ib_port_attr *pprops = NULL;
f614fc15 2701 int err = -ENOMEM;
e126ba97 2702 int port;
2528e33e 2703 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 2704
2705 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2706 if (!pprops)
2707 goto out;
2708
2709 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2710 if (!dprops)
2711 goto out;
2712
c43f1112
MG		 2713 err = set_has_smi_cap(dev);
2714 if (err)
2715 goto out;
2716
2528e33e 2717 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 2718 if (err) {
2719 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2720 goto out;
2721 }
2722
938fe83c 2723 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
c4550c63 2724 memset(pprops, 0, sizeof(*pprops));
e126ba97
EC		 2725 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2726 if (err) {
938fe83c
SM		 2727 mlx5_ib_warn(dev, "query_port %d failed %d\n",
2728 port, err);
e126ba97
EC		 2729 break;
2730 }
938fe83c
SM		 2731 dev->mdev->port_caps[port - 1].pkey_table_len =
2732 dprops->max_pkeys;
2733 dev->mdev->port_caps[port - 1].gid_table_len =
2734 pprops->gid_tbl_len;
e126ba97
EC		 2735 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2736 dprops->max_pkeys, pprops->gid_tbl_len);
2737 }
2738
2739out:
2740 kfree(pprops);
2741 kfree(dprops);
2742
2743 return err;
2744}
2745
2746static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2747{
2748 int err;
2749
2750 err = mlx5_mr_cache_cleanup(dev);
2751 if (err)
2752 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2753
2754 mlx5_ib_destroy_qp(dev->umrc.qp);
add08d76 2755 ib_free_cq(dev->umrc.cq);
e126ba97
EC		 2756 ib_dealloc_pd(dev->umrc.pd);
2757}
2758
2759enum {
2760 MAX_UMR_WR = 128,
2761};
2762
2763static int create_umr_res(struct mlx5_ib_dev *dev)
2764{
2765 struct ib_qp_init_attr *init_attr = NULL;
2766 struct ib_qp_attr *attr = NULL;
2767 struct ib_pd *pd;
2768 struct ib_cq *cq;
2769 struct ib_qp *qp;
e126ba97
EC		 2770 int ret;
2771
2772 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2773 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2774 if (!attr || !init_attr) {
2775 ret = -ENOMEM;
2776 goto error_0;
2777 }
2778
ed082d36 2779 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 2780 if (IS_ERR(pd)) {
2781 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2782 ret = PTR_ERR(pd);
2783 goto error_0;
2784 }
2785
add08d76 2786 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 2787 if (IS_ERR(cq)) {
2788 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2789 ret = PTR_ERR(cq);
2790 goto error_2;
2791 }
e126ba97
EC		 2792
2793 init_attr->send_cq = cq;
2794 init_attr->recv_cq = cq;
2795 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2796 init_attr->cap.max_send_wr = MAX_UMR_WR;
2797 init_attr->cap.max_send_sge = 1;
2798 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2799 init_attr->port_num = 1;
2800 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2801 if (IS_ERR(qp)) {
2802 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2803 ret = PTR_ERR(qp);
2804 goto error_3;
2805 }
2806 qp->device = &dev->ib_dev;
2807 qp->real_qp = qp;
2808 qp->uobject = NULL;
2809 qp->qp_type = MLX5_IB_QPT_REG_UMR;
2810
2811 attr->qp_state = IB_QPS_INIT;
2812 attr->port_num = 1;
2813 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2814 IB_QP_PORT, NULL);
2815 if (ret) {
2816 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2817 goto error_4;
2818 }
2819
2820 memset(attr, 0, sizeof(*attr));
2821 attr->qp_state = IB_QPS_RTR;
2822 attr->path_mtu = IB_MTU_256;
2823
2824 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2825 if (ret) {
2826 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2827 goto error_4;
2828 }
2829
2830 memset(attr, 0, sizeof(*attr));
2831 attr->qp_state = IB_QPS_RTS;
2832 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2833 if (ret) {
2834 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2835 goto error_4;
2836 }
2837
2838 dev->umrc.qp = qp;
2839 dev->umrc.cq = cq;
e126ba97
EC		 2840 dev->umrc.pd = pd;
2841
2842 sema_init(&dev->umrc.sem, MAX_UMR_WR);
2843 ret = mlx5_mr_cache_init(dev);
2844 if (ret) {
2845 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2846 goto error_4;
2847 }
2848
2849 kfree(attr);
2850 kfree(init_attr);
2851
2852 return 0;
2853
2854error_4:
2855 mlx5_ib_destroy_qp(qp);
2856
2857error_3:
add08d76 2858 ib_free_cq(cq);
e126ba97
EC		 2859
2860error_2:
e126ba97
EC		 2861 ib_dealloc_pd(pd);
2862
2863error_0:
2864 kfree(attr);
2865 kfree(init_attr);
2866 return ret;
2867}
2868
2869static int create_dev_resources(struct mlx5_ib_resources *devr)
2870{
2871 struct ib_srq_init_attr attr;
2872 struct mlx5_ib_dev *dev;
bcf4c1ea 2873 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 2874 int port;
e126ba97
EC		 2875 int ret = 0;
2876
2877 dev = container_of(devr, struct mlx5_ib_dev, devr);
2878
d16e91da
HE		 2879 mutex_init(&devr->mutex);
2880
e126ba97
EC		 2881 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2882 if (IS_ERR(devr->p0)) {
2883 ret = PTR_ERR(devr->p0);
2884 goto error0;
2885 }
2886 devr->p0->device = &dev->ib_dev;
2887 devr->p0->uobject = NULL;
2888 atomic_set(&devr->p0->usecnt, 0);
2889
bcf4c1ea 2890 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 2891 if (IS_ERR(devr->c0)) {
2892 ret = PTR_ERR(devr->c0);
2893 goto error1;
2894 }
2895 devr->c0->device = &dev->ib_dev;
2896 devr->c0->uobject = NULL;
2897 devr->c0->comp_handler = NULL;
2898 devr->c0->event_handler = NULL;
2899 devr->c0->cq_context = NULL;
2900 atomic_set(&devr->c0->usecnt, 0);
2901
2902 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2903 if (IS_ERR(devr->x0)) {
2904 ret = PTR_ERR(devr->x0);
2905 goto error2;
2906 }
2907 devr->x0->device = &dev->ib_dev;
2908 devr->x0->inode = NULL;
2909 atomic_set(&devr->x0->usecnt, 0);
2910 mutex_init(&devr->x0->tgt_qp_mutex);
2911 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2912
2913 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2914 if (IS_ERR(devr->x1)) {
2915 ret = PTR_ERR(devr->x1);
2916 goto error3;
2917 }
2918 devr->x1->device = &dev->ib_dev;
2919 devr->x1->inode = NULL;
2920 atomic_set(&devr->x1->usecnt, 0);
2921 mutex_init(&devr->x1->tgt_qp_mutex);
2922 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2923
2924 memset(&attr, 0, sizeof(attr));
2925 attr.attr.max_sge = 1;
2926 attr.attr.max_wr = 1;
2927 attr.srq_type = IB_SRQT_XRC;
2928 attr.ext.xrc.cq = devr->c0;
2929 attr.ext.xrc.xrcd = devr->x0;
2930
2931 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2932 if (IS_ERR(devr->s0)) {
2933 ret = PTR_ERR(devr->s0);
2934 goto error4;
2935 }
2936 devr->s0->device = &dev->ib_dev;
2937 devr->s0->pd = devr->p0;
2938 devr->s0->uobject = NULL;
2939 devr->s0->event_handler = NULL;
2940 devr->s0->srq_context = NULL;
2941 devr->s0->srq_type = IB_SRQT_XRC;
2942 devr->s0->ext.xrc.xrcd = devr->x0;
2943 devr->s0->ext.xrc.cq = devr->c0;
2944 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2945 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2946 atomic_inc(&devr->p0->usecnt);
2947 atomic_set(&devr->s0->usecnt, 0);
2948
4aa17b28
HA		 2949 memset(&attr, 0, sizeof(attr));
2950 attr.attr.max_sge = 1;
2951 attr.attr.max_wr = 1;
2952 attr.srq_type = IB_SRQT_BASIC;
2953 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2954 if (IS_ERR(devr->s1)) {
2955 ret = PTR_ERR(devr->s1);
2956 goto error5;
2957 }
2958 devr->s1->device = &dev->ib_dev;
2959 devr->s1->pd = devr->p0;
2960 devr->s1->uobject = NULL;
2961 devr->s1->event_handler = NULL;
2962 devr->s1->srq_context = NULL;
2963 devr->s1->srq_type = IB_SRQT_BASIC;
2964 devr->s1->ext.xrc.cq = devr->c0;
2965 atomic_inc(&devr->p0->usecnt);
2966 atomic_set(&devr->s0->usecnt, 0);
2967
7722f47e
HE		 2968 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2969 INIT_WORK(&devr->ports[port].pkey_change_work,
2970 pkey_change_handler);
2971 devr->ports[port].devr = devr;
2972 }
2973
e126ba97
EC		 2974 return 0;
2975
4aa17b28
HA		 2976error5:
2977 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 2978error4:
2979 mlx5_ib_dealloc_xrcd(devr->x1);
2980error3:
2981 mlx5_ib_dealloc_xrcd(devr->x0);
2982error2:
2983 mlx5_ib_destroy_cq(devr->c0);
2984error1:
2985 mlx5_ib_dealloc_pd(devr->p0);
2986error0:
2987 return ret;
2988}
2989
2990static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2991{
7722f47e
HE		 2992 struct mlx5_ib_dev *dev =
2993 container_of(devr, struct mlx5_ib_dev, devr);
2994 int port;
2995
4aa17b28 2996 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 2997 mlx5_ib_destroy_srq(devr->s0);
2998 mlx5_ib_dealloc_xrcd(devr->x0);
2999 mlx5_ib_dealloc_xrcd(devr->x1);
3000 mlx5_ib_destroy_cq(devr->c0);
3001 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 3002
3003 /* Make sure no change P_Key work items are still executing */
3004 for (port = 0; port < dev->num_ports; ++port)
3005 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 3006}
3007
e53505a8
AS		 3008static u32 get_core_cap_flags(struct ib_device *ibdev)
3009{
3010 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3011 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3012 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3013 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3014 u32 ret = 0;
3015
3016 if (ll == IB_LINK_LAYER_INFINIBAND)
3017 return RDMA_CORE_PORT_IBA_IB;
3018
72cd5717
OG		 3019 ret = RDMA_CORE_PORT_RAW_PACKET;
3020
e53505a8 3021 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 3022 return ret;
e53505a8
AS		 3023
3024 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 3025 return ret;
e53505a8
AS		 3026
3027 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3028 ret |= RDMA_CORE_PORT_IBA_ROCE;
3029
3030 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3031 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3032
3033 return ret;
3034}
3035
7738613e
IW		 3036static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3037 struct ib_port_immutable *immutable)
3038{
3039 struct ib_port_attr attr;
ca5b91d6
OG		 3040 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3041 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
7738613e
IW		 3042 int err;
3043
c4550c63
OG		 3044 immutable->core_cap_flags = get_core_cap_flags(ibdev);
3045
3046 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 3047 if (err)
3048 return err;
3049
3050 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3051 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 3052 immutable->core_cap_flags = get_core_cap_flags(ibdev);
ca5b91d6
OG		 3053 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3054 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 3055
3056 return 0;
3057}
3058
c7342823
IW		 3059static void get_dev_fw_str(struct ib_device *ibdev, char *str,
3060 size_t str_len)
3061{
3062 struct mlx5_ib_dev *dev =
3063 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
3064 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
3065 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
3066}
3067
45f95acd 3068static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 3069{
3070 struct mlx5_core_dev *mdev = dev->mdev;
3071 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3072 MLX5_FLOW_NAMESPACE_LAG);
3073 struct mlx5_flow_table *ft;
3074 int err;
3075
3076 if (!ns || !mlx5_lag_is_active(mdev))
3077 return 0;
3078
3079 err = mlx5_cmd_create_vport_lag(mdev);
3080 if (err)
3081 return err;
3082
3083 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3084 if (IS_ERR(ft)) {
3085 err = PTR_ERR(ft);
3086 goto err_destroy_vport_lag;
3087 }
3088
3089 dev->flow_db.lag_demux_ft = ft;
3090 return 0;
3091
3092err_destroy_vport_lag:
3093 mlx5_cmd_destroy_vport_lag(mdev);
3094 return err;
3095}
3096
45f95acd 3097static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 3098{
3099 struct mlx5_core_dev *mdev = dev->mdev;
3100
3101 if (dev->flow_db.lag_demux_ft) {
3102 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
3103 dev->flow_db.lag_demux_ft = NULL;
3104
3105 mlx5_cmd_destroy_vport_lag(mdev);
3106 }
3107}
3108
d012f5d6
OG		 3109static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev)
3110{
3111 int err;
3112
3113 dev->roce.nb.notifier_call = mlx5_netdev_event;
3114 err = register_netdevice_notifier(&dev->roce.nb);
3115 if (err) {
3116 dev->roce.nb.notifier_call = NULL;
3117 return err;
3118 }
3119
3120 return 0;
3121}
3122
3123static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev)
5ec8c83e
AH		 3124{
3125 if (dev->roce.nb.notifier_call) {
3126 unregister_netdevice_notifier(&dev->roce.nb);
3127 dev->roce.nb.notifier_call = NULL;
3128 }
3129}
3130
45f95acd 3131static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 3132{
e53505a8
AS		 3133 int err;
3134
d012f5d6
OG		 3135 err = mlx5_add_netdev_notifier(dev);
3136 if (err)
e53505a8
AS		 3137 return err;
3138
ca5b91d6
OG		 3139 if (MLX5_CAP_GEN(dev->mdev, roce)) {
3140 err = mlx5_nic_vport_enable_roce(dev->mdev);
3141 if (err)
3142 goto err_unregister_netdevice_notifier;
3143 }
e53505a8 3144
45f95acd 3145 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 3146 if (err)
3147 goto err_disable_roce;
3148
e53505a8
AS		 3149 return 0;
3150
9ef9c640 3151err_disable_roce:
ca5b91d6
OG		 3152 if (MLX5_CAP_GEN(dev->mdev, roce))
3153 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 3154
e53505a8 3155err_unregister_netdevice_notifier:
d012f5d6 3156 mlx5_remove_netdev_notifier(dev);
e53505a8 3157 return err;
fc24fc5e
AS		 3158}
3159
45f95acd 3160static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 3161{
45f95acd 3162 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 3163 if (MLX5_CAP_GEN(dev->mdev, roce))
3164 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 3165}
3166
7c16f477
KH		 3167struct mlx5_ib_q_counter {
3168 const char *name;
3169 size_t offset;
3170};
3171
3172#define INIT_Q_COUNTER(_name) \
3173 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3174
3175static const struct mlx5_ib_q_counter basic_q_cnts[] = {
3176 INIT_Q_COUNTER(rx_write_requests),
3177 INIT_Q_COUNTER(rx_read_requests),
3178 INIT_Q_COUNTER(rx_atomic_requests),
3179 INIT_Q_COUNTER(out_of_buffer),
3180};
3181
3182static const struct mlx5_ib_q_counter out_of_seq_q_cnts[] = {
3183 INIT_Q_COUNTER(out_of_sequence),
3184};
3185
3186static const struct mlx5_ib_q_counter retrans_q_cnts[] = {
3187 INIT_Q_COUNTER(duplicate_request),
3188 INIT_Q_COUNTER(rnr_nak_retry_err),
3189 INIT_Q_COUNTER(packet_seq_err),
3190 INIT_Q_COUNTER(implied_nak_seq_err),
3191 INIT_Q_COUNTER(local_ack_timeout_err),
3192};
3193
0837e86a
MB		 3194static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
3195{
3196 unsigned int i;
3197
7c16f477 3198 for (i = 0; i < dev->num_ports; i++) {
0837e86a 3199 mlx5_core_dealloc_q_counter(dev->mdev,
7c16f477
KH		 3200 dev->port[i].q_cnts.set_id);
3201 kfree(dev->port[i].q_cnts.names);
3202 kfree(dev->port[i].q_cnts.offsets);
3203 }
3204}
3205
3206static int __mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev,
3207 const char ***names,
3208 size_t **offsets,
3209 u32 *num)
3210{
3211 u32 num_counters;
3212
3213 num_counters = ARRAY_SIZE(basic_q_cnts);
3214
3215 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
3216 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
3217
3218 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
3219 num_counters += ARRAY_SIZE(retrans_q_cnts);
3220
3221 *names = kcalloc(num_counters, sizeof(**names), GFP_KERNEL);
3222 if (!*names)
3223 return -ENOMEM;
3224
3225 *offsets = kcalloc(num_counters, sizeof(**offsets), GFP_KERNEL);
3226 if (!*offsets)
3227 goto err_names;
3228
3229 *num = num_counters;
3230
3231 return 0;
3232
3233err_names:
3234 kfree(*names);
3235 return -ENOMEM;
3236}
3237
3238static void mlx5_ib_fill_q_counters(struct mlx5_ib_dev *dev,
3239 const char **names,
3240 size_t *offsets)
3241{
3242 int i;
3243 int j = 0;
3244
3245 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
3246 names[j] = basic_q_cnts[i].name;
3247 offsets[j] = basic_q_cnts[i].offset;
3248 }
3249
3250 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
3251 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
3252 names[j] = out_of_seq_q_cnts[i].name;
3253 offsets[j] = out_of_seq_q_cnts[i].offset;
3254 }
3255 }
3256
3257 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3258 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
3259 names[j] = retrans_q_cnts[i].name;
3260 offsets[j] = retrans_q_cnts[i].offset;
3261 }
3262 }
0837e86a
MB		 3263}
3264
3265static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
3266{
3267 int i;
3268 int ret;
3269
3270 for (i = 0; i < dev->num_ports; i++) {
7c16f477
KH		 3271 struct mlx5_ib_port *port = &dev->port[i];
3272
0837e86a 3273 ret = mlx5_core_alloc_q_counter(dev->mdev,
7c16f477 3274 &port->q_cnts.set_id);
0837e86a
MB		 3275 if (ret) {
3276 mlx5_ib_warn(dev,
3277 "couldn't allocate queue counter for port %d, err %d\n",
3278 i + 1, ret);
3279 goto dealloc_counters;
3280 }
7c16f477
KH		 3281
3282 ret = __mlx5_ib_alloc_q_counters(dev,
3283 &port->q_cnts.names,
3284 &port->q_cnts.offsets,
3285 &port->q_cnts.num_counters);
3286 if (ret)
3287 goto dealloc_counters;
3288
3289 mlx5_ib_fill_q_counters(dev, port->q_cnts.names,
3290 port->q_cnts.offsets);
0837e86a
MB		 3291 }
3292
3293 return 0;
3294
3295dealloc_counters:
3296 while (--i >= 0)
3297 mlx5_core_dealloc_q_counter(dev->mdev,
7c16f477 3298 dev->port[i].q_cnts.set_id);
0837e86a
MB		 3299
3300 return ret;
3301}
3302
0ad17a8f
MB		 3303static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
3304 u8 port_num)
3305{
7c16f477
KH		 3306 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3307 struct mlx5_ib_port *port = &dev->port[port_num - 1];
0ad17a8f
MB		 3308
3309 /* We support only per port stats */
3310 if (port_num == 0)
3311 return NULL;
3312
7c16f477
KH		 3313 return rdma_alloc_hw_stats_struct(port->q_cnts.names,
3314 port->q_cnts.num_counters,
0ad17a8f
MB		 3315 RDMA_HW_STATS_DEFAULT_LIFESPAN);
3316}
3317
3318static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
3319 struct rdma_hw_stats *stats,
7c16f477 3320 u8 port_num, int index)
0ad17a8f
MB		 3321{
3322 struct mlx5_ib_dev *dev = to_mdev(ibdev);
7c16f477 3323 struct mlx5_ib_port *port = &dev->port[port_num - 1];
0ad17a8f
MB		 3324 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3325 void *out;
3326 __be32 val;
3327 int ret;
3328 int i;
3329
7c16f477 3330 if (!stats)
0ad17a8f
MB		 3331 return -ENOSYS;
3332
3333 out = mlx5_vzalloc(outlen);
3334 if (!out)
3335 return -ENOMEM;
3336
3337 ret = mlx5_core_query_q_counter(dev->mdev,
7c16f477 3338 port->q_cnts.set_id, 0,
0ad17a8f
MB		 3339 out, outlen);
3340 if (ret)
3341 goto free;
3342
7c16f477
KH		 3343 for (i = 0; i < port->q_cnts.num_counters; i++) {
3344 val = *(__be32 *)(out + port->q_cnts.offsets[i]);
0ad17a8f
MB		 3345 stats->value[i] = (u64)be32_to_cpu(val);
3346 }
7c16f477 3347
0ad17a8f
MB		 3348free:
3349 kvfree(out);
7c16f477 3350 return port->q_cnts.num_counters;
0ad17a8f
MB		 3351}
3352
9603b61d 3353static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
e126ba97 3354{
e126ba97 3355 struct mlx5_ib_dev *dev;
ebd61f68
AS		 3356 enum rdma_link_layer ll;
3357 int port_type_cap;
4babcf97 3358 const char *name;
e126ba97
EC		 3359 int err;
3360 int i;
3361
ebd61f68
AS		 3362 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3363 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3364
e126ba97
EC		 3365 printk_once(KERN_INFO "%s", mlx5_version);
3366
3367 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
3368 if (!dev)
9603b61d 3369 return NULL;
e126ba97 3370
9603b61d 3371 dev->mdev = mdev;
e126ba97 3372
0837e86a
MB		 3373 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
3374 GFP_KERNEL);
3375 if (!dev->port)
3376 goto err_dealloc;
3377
fc24fc5e 3378 rwlock_init(&dev->roce.netdev_lock);
e126ba97
EC		 3379 err = get_port_caps(dev);
3380 if (err)
0837e86a 3381 goto err_free_port;
e126ba97 3382
1b5daf11
MD		 3383 if (mlx5_use_mad_ifc(dev))
3384 get_ext_port_caps(dev);
e126ba97 3385
4babcf97
AH		 3386 if (!mlx5_lag_is_active(mdev))
3387 name = "mlx5_%d";
3388 else
3389 name = "mlx5_bond_%d";
3390
3391 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
e126ba97
EC		 3392 dev->ib_dev.owner = THIS_MODULE;
3393 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 3394 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
938fe83c 3395 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
e126ba97 3396 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 3397 dev->ib_dev.num_comp_vectors =
3398 dev->mdev->priv.eq_table.num_comp_vectors;
9b0c289e 3399 dev->ib_dev.dev.parent = &mdev->pdev->dev;
e126ba97
EC		 3400
3401 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
3402 dev->ib_dev.uverbs_cmd_mask =
3403 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
3404 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
3405 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
3406 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
3407 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 3408 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
3409 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 3410 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 3411 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 3412 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
3413 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
3414 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
3415 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
3416 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
3417 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
3418 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
3419 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
3420 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
3421 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
3422 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
3423 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
3424 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
3425 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
3426 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
3427 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
3428 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 3429 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 3430 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
3431 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349
BW		 3432 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
3433 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP);
e126ba97
EC		 3434
3435 dev->ib_dev.query_device = mlx5_ib_query_device;
3436 dev->ib_dev.query_port = mlx5_ib_query_port;
ebd61f68 3437 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
fc24fc5e
AS		 3438 if (ll == IB_LINK_LAYER_ETHERNET)
3439 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
e126ba97 3440 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 3441 dev->ib_dev.add_gid = mlx5_ib_add_gid;
3442 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 3443 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
3444 dev->ib_dev.modify_device = mlx5_ib_modify_device;
3445 dev->ib_dev.modify_port = mlx5_ib_modify_port;
3446 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
3447 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
3448 dev->ib_dev.mmap = mlx5_ib_mmap;
3449 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
3450 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
3451 dev->ib_dev.create_ah = mlx5_ib_create_ah;
3452 dev->ib_dev.query_ah = mlx5_ib_query_ah;
3453 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
3454 dev->ib_dev.create_srq = mlx5_ib_create_srq;
3455 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
3456 dev->ib_dev.query_srq = mlx5_ib_query_srq;
3457 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
3458 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
3459 dev->ib_dev.create_qp = mlx5_ib_create_qp;
3460 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
3461 dev->ib_dev.query_qp = mlx5_ib_query_qp;
3462 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
3463 dev->ib_dev.post_send = mlx5_ib_post_send;
3464 dev->ib_dev.post_recv = mlx5_ib_post_recv;
3465 dev->ib_dev.create_cq = mlx5_ib_create_cq;
3466 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
3467 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
3468 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
3469 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
3470 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
3471 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
3472 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 3473 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 3474 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
3475 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
3476 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
3477 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 3478 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 3479 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 3480 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
7738613e 3481 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
c7342823 3482 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
eff901d3
EC		 3483 if (mlx5_core_is_pf(mdev)) {
3484 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
3485 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
3486 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
3487 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
3488 }
e126ba97 3489
7c2344c3
MG		 3490 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3491
938fe83c 3492 mlx5_ib_internal_fill_odp_caps(dev);
8cdd312c 3493
d2370e0a
MB		 3494 if (MLX5_CAP_GEN(mdev, imaicl)) {
3495 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
3496 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
3497 dev->ib_dev.uverbs_cmd_mask |=
3498 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
3499 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3500 }
3501
7c16f477 3502 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
0ad17a8f
MB		 3503 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
3504 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
3505 }
3506
938fe83c 3507 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 3508 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3509 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3510 dev->ib_dev.uverbs_cmd_mask |=
3511 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3512 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3513 }
3514
048ccca8 3515 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
038d2ef8
MG		 3516 IB_LINK_LAYER_ETHERNET) {
3517 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3518 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
79b20a6c
YH		 3519 dev->ib_dev.create_wq = mlx5_ib_create_wq;
3520 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
3521 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
c5f90929
YH		 3522 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
3523 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
038d2ef8
MG		 3524 dev->ib_dev.uverbs_ex_cmd_mask |=
3525 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
79b20a6c
YH		 3526 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
3527 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
3528 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
c5f90929
YH		 3529 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
3530 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
3531 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
038d2ef8 3532 }
e126ba97
EC		 3533 err = init_node_data(dev);
3534 if (err)
90be7c8a 3535 goto err_free_port;
e126ba97 3536
038d2ef8 3537 mutex_init(&dev->flow_db.lock);
e126ba97 3538 mutex_init(&dev->cap_mask_mutex);
89ea94a7
MG		 3539 INIT_LIST_HEAD(&dev->qp_list);
3540 spin_lock_init(&dev->reset_flow_resource_lock);
e126ba97 3541
fc24fc5e 3542 if (ll == IB_LINK_LAYER_ETHERNET) {
45f95acd 3543 err = mlx5_enable_eth(dev);
fc24fc5e 3544 if (err)
90be7c8a 3545 goto err_free_port;
fc24fc5e
AS		 3546 }
3547
e126ba97
EC		 3548 err = create_dev_resources(&dev->devr);
3549 if (err)
45f95acd 3550 goto err_disable_eth;
e126ba97 3551
6aec21f6 3552 err = mlx5_ib_odp_init_one(dev);
281d1a92 3553 if (err)
e126ba97
EC		 3554 goto err_rsrc;
3555
45bded2c
KH		 3556 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
3557 err = mlx5_ib_alloc_q_counters(dev);
3558 if (err)
3559 goto err_odp;
3560 }
6aec21f6 3561
5fe9dec0
EC		 3562 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
3563 if (!dev->mdev->priv.uar)
3564 goto err_q_cnt;
3565
3566 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
3567 if (err)
3568 goto err_uar_page;
3569
3570 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
3571 if (err)
3572 goto err_bfreg;
3573
0837e86a
MB		 3574 err = ib_register_device(&dev->ib_dev, NULL);
3575 if (err)
5fe9dec0 3576 goto err_fp_bfreg;
0837e86a 3577
e126ba97
EC		 3578 err = create_umr_res(dev);
3579 if (err)
3580 goto err_dev;
3581
3582 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 3583 err = device_create_file(&dev->ib_dev.dev,
3584 mlx5_class_attributes[i]);
3585 if (err)
e126ba97
EC		 3586 goto err_umrc;
3587 }
3588
3589 dev->ib_active = true;
3590
9603b61d 3591 return dev;
e126ba97
EC		 3592
3593err_umrc:
3594 destroy_umrc_res(dev);
3595
3596err_dev:
3597 ib_unregister_device(&dev->ib_dev);
3598
5fe9dec0
EC		 3599err_fp_bfreg:
3600 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3601
3602err_bfreg:
3603 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3604
3605err_uar_page:
3606 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
3607
0837e86a 3608err_q_cnt:
45bded2c
KH		 3609 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
3610 mlx5_ib_dealloc_q_counters(dev);
0837e86a 3611
6aec21f6
HE		 3612err_odp:
3613 mlx5_ib_odp_remove_one(dev);
3614
e126ba97
EC		 3615err_rsrc:
3616 destroy_dev_resources(&dev->devr);
3617
45f95acd 3618err_disable_eth:
5ec8c83e 3619 if (ll == IB_LINK_LAYER_ETHERNET) {
45f95acd 3620 mlx5_disable_eth(dev);
d012f5d6 3621 mlx5_remove_netdev_notifier(dev);
5ec8c83e 3622 }
fc24fc5e 3623
0837e86a
MB		 3624err_free_port:
3625 kfree(dev->port);
3626
9603b61d 3627err_dealloc:
e126ba97
EC		 3628 ib_dealloc_device((struct ib_device *)dev);
3629
9603b61d 3630 return NULL;
e126ba97
EC		 3631}
3632
9603b61d 3633static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 3634{
9603b61d 3635 struct mlx5_ib_dev *dev = context;
fc24fc5e 3636 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
6aec21f6 3637
d012f5d6 3638 mlx5_remove_netdev_notifier(dev);
e126ba97 3639 ib_unregister_device(&dev->ib_dev);
5fe9dec0
EC		 3640 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3641 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3642 mlx5_put_uars_page(dev->mdev, mdev->priv.uar);
45bded2c
KH		 3643 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
3644 mlx5_ib_dealloc_q_counters(dev);
eefd56e5 3645 destroy_umrc_res(dev);
6aec21f6 3646 mlx5_ib_odp_remove_one(dev);
e126ba97 3647 destroy_dev_resources(&dev->devr);
fc24fc5e 3648 if (ll == IB_LINK_LAYER_ETHERNET)
45f95acd 3649 mlx5_disable_eth(dev);
0837e86a 3650 kfree(dev->port);
e126ba97
EC		 3651 ib_dealloc_device(&dev->ib_dev);
3652}
3653
9603b61d
JM		 3654static struct mlx5_interface mlx5_ib_interface = {
3655 .add = mlx5_ib_add,
3656 .remove = mlx5_ib_remove,
3657 .event = mlx5_ib_event,
d9aaed83
AK		 3658#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
3659 .pfault = mlx5_ib_pfault,
3660#endif
64613d94 3661 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 3662};
3663
3664static int __init mlx5_ib_init(void)
3665{
6aec21f6
HE		 3666 int err;
3667
81713d37 3668 mlx5_ib_odp_init();
9603b61d 3669
6aec21f6 3670 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 3671
6aec21f6 3672 return err;
e126ba97
EC		 3673}
3674
3675static void __exit mlx5_ib_cleanup(void)
3676{
9603b61d 3677 mlx5_unregister_interface(&mlx5_ib_interface);
e126ba97
EC		 3678}
3679
3680module_init(mlx5_ib_init);
3681module_exit(mlx5_ib_cleanup);
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