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e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
24da0016 41#include <linux/bitmap.h>
37aa5c36
GL		 42#if defined(CONFIG_X86)
43#include <asm/pat.h>
44#endif
e126ba97 45#include <linux/sched.h>
6e84f315 46#include <linux/sched/mm.h>
0881e7bd 47#include <linux/sched/task.h>
7c2344c3 48#include <linux/delay.h>
e126ba97 49#include <rdma/ib_user_verbs.h>
3f89a643 50#include <rdma/ib_addr.h>
2811ba51 51#include <rdma/ib_cache.h>
ada68c31 52#include <linux/mlx5/port.h>
1b5daf11 53#include <linux/mlx5/vport.h>
72c7fe90 54#include <linux/mlx5/fs.h>
cecae747 55#include <linux/mlx5/eswitch.h>
7c2344c3 56#include <linux/list.h>
e126ba97
EC		 57#include <rdma/ib_smi.h>
58#include <rdma/ib_umem.h>
038d2ef8
MG		 59#include <linux/in.h>
60#include <linux/etherdevice.h>
e126ba97 61#include "mlx5_ib.h"
fc385b7a 62#include "ib_rep.h"
e1f24a79 63#include "cmd.h"
f3da6577 64#include "srq.h"
3346c487 65#include <linux/mlx5/fs_helpers.h>
c6475a0b 66#include <linux/mlx5/accel.h>
8c84660b 67#include <rdma/uverbs_std_types.h>
c6475a0b
AY		 68#include <rdma/mlx5_user_ioctl_verbs.h>
69#include <rdma/mlx5_user_ioctl_cmds.h>
8c84660b
MB		 70
71#define UVERBS_MODULE_NAME mlx5_ib
72#include <rdma/uverbs_named_ioctl.h>
e126ba97
EC		 73
74#define DRIVER_NAME "mlx5_ib"
b359911d 75#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 76
77MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
78MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
79MODULE_LICENSE("Dual BSD/GPL");
e126ba97 80
e126ba97
EC		 81static char mlx5_version[] =
82 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 83 DRIVER_VERSION "\n";
e126ba97 84
d69a24e0
DJ		 85struct mlx5_ib_event_work {
86 struct work_struct work;
df097a27
SM		 87 union {
88 struct mlx5_ib_dev *dev;
89 struct mlx5_ib_multiport_info *mpi;
90 };
91 bool is_slave;
134e9349 92 unsigned int event;
df097a27 93 void *param;
d69a24e0
DJ		 94};
95
da7525d2
EBE		 96enum {
97 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
98};
99
d69a24e0 100static struct workqueue_struct *mlx5_ib_event_wq;
32f69e4b
DJ		 101static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
102static LIST_HEAD(mlx5_ib_dev_list);
103/*
104 * This mutex should be held when accessing either of the above lists
105 */
106static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
107
c44ef998
IL		 108/* We can't use an array for xlt_emergency_page because dma_map_single
109 * doesn't work on kernel modules memory
110 */
111static unsigned long xlt_emergency_page;
112static struct mutex xlt_emergency_page_mutex;
113
32f69e4b
DJ		 114struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
115{
116 struct mlx5_ib_dev *dev;
117
118 mutex_lock(&mlx5_ib_multiport_mutex);
119 dev = mpi->ibdev;
120 mutex_unlock(&mlx5_ib_multiport_mutex);
121 return dev;
122}
123
1b5daf11 124static enum rdma_link_layer
ebd61f68 125mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 126{
ebd61f68 127 switch (port_type_cap) {
1b5daf11
MD		 128 case MLX5_CAP_PORT_TYPE_IB:
129 return IB_LINK_LAYER_INFINIBAND;
130 case MLX5_CAP_PORT_TYPE_ETH:
131 return IB_LINK_LAYER_ETHERNET;
132 default:
133 return IB_LINK_LAYER_UNSPECIFIED;
134 }
135}
136
ebd61f68
AS		 137static enum rdma_link_layer
138mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
139{
140 struct mlx5_ib_dev *dev = to_mdev(device);
141 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
142
143 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
144}
145
fd65f1b8
MS		 146static int get_port_state(struct ib_device *ibdev,
147 u8 port_num,
148 enum ib_port_state *state)
149{
150 struct ib_port_attr attr;
151 int ret;
152
153 memset(&attr, 0, sizeof(attr));
3023a1e9 154 ret = ibdev->ops.query_port(ibdev, port_num, &attr);
fd65f1b8
MS		 155 if (!ret)
156 *state = attr.state;
157 return ret;
158}
159
35b0aa67
MB		 160static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
161 struct net_device *ndev,
162 u8 *port_num)
163{
164 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
165 struct net_device *rep_ndev;
166 struct mlx5_ib_port *port;
167 int i;
168
169 for (i = 0; i < dev->num_ports; i++) {
170 port = &dev->port[i];
171 if (!port->rep)
172 continue;
173
174 read_lock(&port->roce.netdev_lock);
175 rep_ndev = mlx5_ib_get_rep_netdev(esw,
176 port->rep->vport);
177 if (rep_ndev == ndev) {
178 read_unlock(&port->roce.netdev_lock);
179 *port_num = i + 1;
180 return &port->roce;
181 }
182 read_unlock(&port->roce.netdev_lock);
183 }
184
185 return NULL;
186}
187
fc24fc5e
AS		 188static int mlx5_netdev_event(struct notifier_block *this,
189 unsigned long event, void *ptr)
190{
7fd8aefb 191 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
fc24fc5e 192 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
7fd8aefb
DJ		 193 u8 port_num = roce->native_port_num;
194 struct mlx5_core_dev *mdev;
195 struct mlx5_ib_dev *ibdev;
196
197 ibdev = roce->dev;
32f69e4b
DJ		 198 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
199 if (!mdev)
200 return NOTIFY_DONE;
fc24fc5e 201
5ec8c83e
AH		 202 switch (event) {
203 case NETDEV_REGISTER:
35b0aa67
MB		 204 /* Should already be registered during the load */
205 if (ibdev->is_rep)
206 break;
7fd8aefb 207 write_lock(&roce->netdev_lock);
dce45af5 208 if (ndev->dev.parent == mdev->device)
842a9c83 209 roce->netdev = ndev;
7fd8aefb 210 write_unlock(&roce->netdev_lock);
5ec8c83e 211 break;
fc24fc5e 212
842a9c83 213 case NETDEV_UNREGISTER:
35b0aa67 214 /* In case of reps, ib device goes away before the netdevs */
842a9c83
OG		 215 write_lock(&roce->netdev_lock);
216 if (roce->netdev == ndev)
217 roce->netdev = NULL;
218 write_unlock(&roce->netdev_lock);
219 break;
220
fd65f1b8 221 case NETDEV_CHANGE:
5ec8c83e 222 case NETDEV_UP:
88621dfe 223 case NETDEV_DOWN: {
7fd8aefb 224 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe
AH		 225 struct net_device *upper = NULL;
226
227 if (lag_ndev) {
228 upper = netdev_master_upper_dev_get(lag_ndev);
229 dev_put(lag_ndev);
230 }
231
35b0aa67
MB		 232 if (ibdev->is_rep)
233 roce = mlx5_get_rep_roce(ibdev, ndev, &port_num);
234 if (!roce)
235 return NOTIFY_DONE;
7fd8aefb 236 if ((upper == ndev || (!upper && ndev == roce->netdev))
88621dfe 237 && ibdev->ib_active) {
626bc02d 238 struct ib_event ibev = { };
fd65f1b8 239 enum ib_port_state port_state;
5ec8c83e 240
7fd8aefb
DJ		 241 if (get_port_state(&ibdev->ib_dev, port_num,
242 &port_state))
243 goto done;
fd65f1b8 244
7fd8aefb
DJ		 245 if (roce->last_port_state == port_state)
246 goto done;
fd65f1b8 247
7fd8aefb 248 roce->last_port_state = port_state;
5ec8c83e 249 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 250 if (port_state == IB_PORT_DOWN)
251 ibev.event = IB_EVENT_PORT_ERR;
252 else if (port_state == IB_PORT_ACTIVE)
253 ibev.event = IB_EVENT_PORT_ACTIVE;
254 else
7fd8aefb 255 goto done;
fd65f1b8 256
7fd8aefb 257 ibev.element.port_num = port_num;
5ec8c83e
AH		 258 ib_dispatch_event(&ibev);
259 }
260 break;
88621dfe 261 }
fc24fc5e 262
5ec8c83e
AH		 263 default:
264 break;
265 }
7fd8aefb 266done:
32f69e4b 267 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 268 return NOTIFY_DONE;
269}
270
271static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
272 u8 port_num)
273{
274 struct mlx5_ib_dev *ibdev = to_mdev(device);
275 struct net_device *ndev;
32f69e4b
DJ		 276 struct mlx5_core_dev *mdev;
277
278 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
279 if (!mdev)
280 return NULL;
fc24fc5e 281
32f69e4b 282 ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe 283 if (ndev)
32f69e4b 284 goto out;
88621dfe 285
fc24fc5e
AS		 286 /* Ensure ndev does not disappear before we invoke dev_hold()
287 */
95579e78
MB		 288 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock);
289 ndev = ibdev->port[port_num - 1].roce.netdev;
fc24fc5e
AS		 290 if (ndev)
291 dev_hold(ndev);
95579e78 292 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock);
fc24fc5e 293
32f69e4b
DJ		 294out:
295 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 296 return ndev;
297}
298
32f69e4b
DJ		 299struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
300 u8 ib_port_num,
301 u8 *native_port_num)
302{
303 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
304 ib_port_num);
305 struct mlx5_core_dev *mdev = NULL;
306 struct mlx5_ib_multiport_info *mpi;
307 struct mlx5_ib_port *port;
308
210b1f78
MB		 309 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
310 ll != IB_LINK_LAYER_ETHERNET) {
311 if (native_port_num)
312 *native_port_num = ib_port_num;
313 return ibdev->mdev;
314 }
315
32f69e4b
DJ		 316 if (native_port_num)
317 *native_port_num = 1;
318
32f69e4b
DJ		 319 port = &ibdev->port[ib_port_num - 1];
320 if (!port)
321 return NULL;
322
323 spin_lock(&port->mp.mpi_lock);
324 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
325 if (mpi && !mpi->unaffiliate) {
326 mdev = mpi->mdev;
327 /* If it's the master no need to refcount, it'll exist
328 * as long as the ib_dev exists.
329 */
330 if (!mpi->is_master)
331 mpi->mdev_refcnt++;
332 }
333 spin_unlock(&port->mp.mpi_lock);
334
335 return mdev;
336}
337
338void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
339{
340 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
341 port_num);
342 struct mlx5_ib_multiport_info *mpi;
343 struct mlx5_ib_port *port;
344
345 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
346 return;
347
348 port = &ibdev->port[port_num - 1];
349
350 spin_lock(&port->mp.mpi_lock);
351 mpi = ibdev->port[port_num - 1].mp.mpi;
352 if (mpi->is_master)
353 goto out;
354
355 mpi->mdev_refcnt--;
356 if (mpi->unaffiliate)
357 complete(&mpi->unref_comp);
358out:
359 spin_unlock(&port->mp.mpi_lock);
360}
361
08e8676f
AL		 362static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, u8 *active_speed,
363 u8 *active_width)
f1b65df5
NO		 364{
365 switch (eth_proto_oper) {
366 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
367 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
368 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
369 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
370 *active_width = IB_WIDTH_1X;
371 *active_speed = IB_SPEED_SDR;
372 break;
373 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
374 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
375 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
376 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
377 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
378 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
379 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
380 *active_width = IB_WIDTH_1X;
381 *active_speed = IB_SPEED_QDR;
382 break;
383 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
384 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
385 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
386 *active_width = IB_WIDTH_1X;
387 *active_speed = IB_SPEED_EDR;
388 break;
389 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
390 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
391 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
392 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
393 *active_width = IB_WIDTH_4X;
394 *active_speed = IB_SPEED_QDR;
395 break;
396 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
397 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
398 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
399 *active_width = IB_WIDTH_1X;
400 *active_speed = IB_SPEED_HDR;
401 break;
402 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
403 *active_width = IB_WIDTH_4X;
404 *active_speed = IB_SPEED_FDR;
405 break;
406 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
407 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
408 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
409 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
410 *active_width = IB_WIDTH_4X;
411 *active_speed = IB_SPEED_EDR;
412 break;
413 default:
414 return -EINVAL;
415 }
416
417 return 0;
418}
419
08e8676f
AL		 420static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed,
421 u8 *active_width)
422{
423 switch (eth_proto_oper) {
424 case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
425 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
426 *active_width = IB_WIDTH_1X;
427 *active_speed = IB_SPEED_SDR;
428 break;
429 case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
430 *active_width = IB_WIDTH_1X;
431 *active_speed = IB_SPEED_DDR;
432 break;
433 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
434 *active_width = IB_WIDTH_1X;
435 *active_speed = IB_SPEED_QDR;
436 break;
437 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
438 *active_width = IB_WIDTH_4X;
439 *active_speed = IB_SPEED_QDR;
440 break;
441 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
442 *active_width = IB_WIDTH_1X;
443 *active_speed = IB_SPEED_EDR;
444 break;
445 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
cd272875
AL		 446 *active_width = IB_WIDTH_2X;
447 *active_speed = IB_SPEED_EDR;
448 break;
08e8676f
AL		 449 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
450 *active_width = IB_WIDTH_1X;
451 *active_speed = IB_SPEED_HDR;
452 break;
cd272875
AL		 453 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
454 *active_width = IB_WIDTH_4X;
455 *active_speed = IB_SPEED_EDR;
456 break;
08e8676f
AL		 457 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
458 *active_width = IB_WIDTH_2X;
459 *active_speed = IB_SPEED_HDR;
460 break;
461 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
462 *active_width = IB_WIDTH_4X;
463 *active_speed = IB_SPEED_HDR;
464 break;
465 default:
466 return -EINVAL;
467 }
468
469 return 0;
470}
471
472static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
473 u8 *active_width, bool ext)
474{
475 return ext ?
476 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
477 active_width) :
478 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
479 active_width);
480}
481
095b0927
IT		 482static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
483 struct ib_port_attr *props)
3f89a643
AS		 484{
485 struct mlx5_ib_dev *dev = to_mdev(device);
bc4e12ff 486 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
da005f9f 487 struct mlx5_core_dev *mdev;
88621dfe 488 struct net_device *ndev, *upper;
3f89a643 489 enum ib_mtu ndev_ib_mtu;
b3cbd6f0 490 bool put_mdev = true;
c876a1b7 491 u16 qkey_viol_cntr;
f1b65df5 492 u32 eth_prot_oper;
b3cbd6f0 493 u8 mdev_port_num;
08e8676f 494 bool ext;
095b0927 495 int err;
3f89a643 496
b3cbd6f0
DJ		 497 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
498 if (!mdev) {
499 /* This means the port isn't affiliated yet. Get the
500 * info for the master port instead.
501 */
502 put_mdev = false;
503 mdev = dev->mdev;
504 mdev_port_num = 1;
505 port_num = 1;
506 }
507
f1b65df5
NO		 508 /* Possible bad flows are checked before filling out props so in case
509 * of an error it will still be zeroed out.
26628e2d 510 * Use native port in case of reps
50f22fd8 511 */
26628e2d
MB		 512 if (dev->is_rep)
513 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
514 1);
515 else
516 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
517 mdev_port_num);
095b0927 518 if (err)
b3cbd6f0 519 goto out;
08e8676f
AL		 520 ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet);
521 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
f1b65df5 522
7672ed33
HL		 523 props->active_width = IB_WIDTH_4X;
524 props->active_speed = IB_SPEED_QDR;
525
f1b65df5 526 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
08e8676f 527 &props->active_width, ext);
3f89a643 528
2f944c0f
JG		 529 props->port_cap_flags |= IB_PORT_CM_SUP;
530 props->ip_gids = true;
3f89a643
AS		 531
532 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
533 roce_address_table_size);
534 props->max_mtu = IB_MTU_4096;
535 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
536 props->pkey_tbl_len = 1;
537 props->state = IB_PORT_DOWN;
72a7720f 538 props->phys_state = IB_PORT_PHYS_STATE_DISABLED;
3f89a643 539
b3cbd6f0 540 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
c876a1b7 541 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643 542
b3cbd6f0
DJ		 543 /* If this is a stub query for an unaffiliated port stop here */
544 if (!put_mdev)
545 goto out;
546
3f89a643
AS		 547 ndev = mlx5_ib_get_netdev(device, port_num);
548 if (!ndev)
b3cbd6f0 549 goto out;
3f89a643 550
7c34ec19 551 if (dev->lag_active) {
88621dfe
AH		 552 rcu_read_lock();
553 upper = netdev_master_upper_dev_get_rcu(ndev);
554 if (upper) {
555 dev_put(ndev);
556 ndev = upper;
557 dev_hold(ndev);
558 }
559 rcu_read_unlock();
560 }
561
3f89a643
AS		 562 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
563 props->state = IB_PORT_ACTIVE;
72a7720f 564 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
3f89a643
AS		 565 }
566
567 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
568
569 dev_put(ndev);
570
571 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
b3cbd6f0
DJ		 572out:
573 if (put_mdev)
574 mlx5_ib_put_native_port_mdev(dev, port_num);
575 return err;
3f89a643
AS		 576}
577
095b0927
IT		 578static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
579 unsigned int index, const union ib_gid *gid,
580 const struct ib_gid_attr *attr)
3cca2606 581{
095b0927 582 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
a70c0739 583 u16 vlan_id = 0xffff;
095b0927
IT		 584 u8 roce_version = 0;
585 u8 roce_l3_type = 0;
095b0927 586 u8 mac[ETH_ALEN];
a70c0739 587 int ret;
095b0927
IT		 588
589 if (gid) {
590 gid_type = attr->gid_type;
a70c0739
PP		 591 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
592 if (ret)
593 return ret;
3cca2606
AS		 594 }
595
095b0927 596 switch (gid_type) {
3cca2606 597 case IB_GID_TYPE_IB:
095b0927 598 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 599 break;
600 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 601 roce_version = MLX5_ROCE_VERSION_2;
602 if (ipv6_addr_v4mapped((void *)gid))
603 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
604 else
605 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 606 break;
607
608 default:
095b0927 609 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 610 }
611
095b0927 612 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
cf34e1fe 613 roce_l3_type, gid->raw, mac,
a70c0739 614 vlan_id < VLAN_CFI_MASK, vlan_id,
cf34e1fe 615 port_num);
3cca2606
AS		 616}
617
f4df9a7c 618static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
3cca2606
AS		 619 __always_unused void **context)
620{
414448d2 621 return set_roce_addr(to_mdev(attr->device), attr->port_num,
f4df9a7c 622 attr->index, &attr->gid, attr);
3cca2606
AS		 623}
624
414448d2
PP		 625static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
626 __always_unused void **context)
3cca2606 627{
414448d2
PP		 628 return set_roce_addr(to_mdev(attr->device), attr->port_num,
629 attr->index, NULL, NULL);
3cca2606
AS		 630}
631
47ec3866
PP		 632__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
633 const struct ib_gid_attr *attr)
2811ba51 634{
47ec3866 635 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
2811ba51
AS		 636 return 0;
637
638 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
639}
640
1b5daf11
MD		 641static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
642{
7fae6655
NO		 643 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
644 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
645 return 0;
1b5daf11
MD		 646}
647
648enum {
649 MLX5_VPORT_ACCESS_METHOD_MAD,
650 MLX5_VPORT_ACCESS_METHOD_HCA,
651 MLX5_VPORT_ACCESS_METHOD_NIC,
652};
653
654static int mlx5_get_vport_access_method(struct ib_device *ibdev)
655{
656 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
657 return MLX5_VPORT_ACCESS_METHOD_MAD;
658
ebd61f68 659 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 660 IB_LINK_LAYER_ETHERNET)
661 return MLX5_VPORT_ACCESS_METHOD_NIC;
662
663 return MLX5_VPORT_ACCESS_METHOD_HCA;
664}
665
da7525d2 666static void get_atomic_caps(struct mlx5_ib_dev *dev,
776a3906 667 u8 atomic_size_qp,
da7525d2
EBE		 668 struct ib_device_attr *props)
669{
670 u8 tmp;
671 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
da7525d2 672 u8 atomic_req_8B_endianness_mode =
bd10838a 673 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 674
675 /* Check if HW supports 8 bytes standard atomic operations and capable
676 * of host endianness respond
677 */
678 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
679 if (((atomic_operations & tmp) == tmp) &&
680 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
681 (atomic_req_8B_endianness_mode)) {
682 props->atomic_cap = IB_ATOMIC_HCA;
683 } else {
684 props->atomic_cap = IB_ATOMIC_NONE;
685 }
686}
687
776a3906
MS		 688static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
689 struct ib_device_attr *props)
690{
691 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
692
693 get_atomic_caps(dev, atomic_size_qp, props);
694}
695
696static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
697 struct ib_device_attr *props)
698{
699 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
700
701 get_atomic_caps(dev, atomic_size_qp, props);
702}
703
704bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
705{
706 struct ib_device_attr props = {};
707
708 get_atomic_caps_dc(dev, &props);
709 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
710}
1b5daf11
MD		 711static int mlx5_query_system_image_guid(struct ib_device *ibdev,
712 __be64 *sys_image_guid)
713{
714 struct mlx5_ib_dev *dev = to_mdev(ibdev);
715 struct mlx5_core_dev *mdev = dev->mdev;
716 u64 tmp;
717 int err;
718
719 switch (mlx5_get_vport_access_method(ibdev)) {
720 case MLX5_VPORT_ACCESS_METHOD_MAD:
721 return mlx5_query_mad_ifc_system_image_guid(ibdev,
722 sys_image_guid);
723
724 case MLX5_VPORT_ACCESS_METHOD_HCA:
725 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 726 break;
727
728 case MLX5_VPORT_ACCESS_METHOD_NIC:
729 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
730 break;
1b5daf11
MD		 731
732 default:
733 return -EINVAL;
734 }
3f89a643
AS		 735
736 if (!err)
737 *sys_image_guid = cpu_to_be64(tmp);
738
739 return err;
740
1b5daf11
MD		 741}
742
743static int mlx5_query_max_pkeys(struct ib_device *ibdev,
744 u16 *max_pkeys)
745{
746 struct mlx5_ib_dev *dev = to_mdev(ibdev);
747 struct mlx5_core_dev *mdev = dev->mdev;
748
749 switch (mlx5_get_vport_access_method(ibdev)) {
750 case MLX5_VPORT_ACCESS_METHOD_MAD:
751 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
752
753 case MLX5_VPORT_ACCESS_METHOD_HCA:
754 case MLX5_VPORT_ACCESS_METHOD_NIC:
755 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
756 pkey_table_size));
757 return 0;
758
759 default:
760 return -EINVAL;
761 }
762}
763
764static int mlx5_query_vendor_id(struct ib_device *ibdev,
765 u32 *vendor_id)
766{
767 struct mlx5_ib_dev *dev = to_mdev(ibdev);
768
769 switch (mlx5_get_vport_access_method(ibdev)) {
770 case MLX5_VPORT_ACCESS_METHOD_MAD:
771 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
772
773 case MLX5_VPORT_ACCESS_METHOD_HCA:
774 case MLX5_VPORT_ACCESS_METHOD_NIC:
775 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
776
777 default:
778 return -EINVAL;
779 }
780}
781
782static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
783 __be64 *node_guid)
784{
785 u64 tmp;
786 int err;
787
788 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
789 case MLX5_VPORT_ACCESS_METHOD_MAD:
790 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
791
792 case MLX5_VPORT_ACCESS_METHOD_HCA:
793 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 794 break;
795
796 case MLX5_VPORT_ACCESS_METHOD_NIC:
797 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
798 break;
1b5daf11
MD		 799
800 default:
801 return -EINVAL;
802 }
3f89a643
AS		 803
804 if (!err)
805 *node_guid = cpu_to_be64(tmp);
806
807 return err;
1b5daf11
MD		 808}
809
810struct mlx5_reg_node_desc {
bd99fdea 811 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 812};
813
814static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
815{
816 struct mlx5_reg_node_desc in;
817
818 if (mlx5_use_mad_ifc(dev))
819 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
820
821 memset(&in, 0, sizeof(in));
822
823 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
824 sizeof(struct mlx5_reg_node_desc),
825 MLX5_REG_NODE_DESC, 0, 0);
826}
827
e126ba97 828static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 829 struct ib_device_attr *props,
830 struct ib_udata *uhw)
e126ba97
EC		 831{
832 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 833 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 834 int err = -ENOMEM;
288c01b7 835 int max_sq_desc;
e126ba97
EC		 836 int max_rq_sg;
837 int max_sq_sg;
e0238a6a 838 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
85c7c014 839 bool raw_support = !mlx5_core_mp_enabled(mdev);
402ca536
BW		 840 struct mlx5_ib_query_device_resp resp = {};
841 size_t resp_len;
842 u64 max_tso;
e126ba97 843
402ca536
BW		 844 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
845 if (uhw->outlen && uhw->outlen < resp_len)
846 return -EINVAL;
847 else
848 resp.response_length = resp_len;
849
850 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 851 return -EINVAL;
852
1b5daf11
MD		 853 memset(props, 0, sizeof(*props));
854 err = mlx5_query_system_image_guid(ibdev,
855 &props->sys_image_guid);
856 if (err)
857 return err;
e126ba97 858
1b5daf11 859 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 860 if (err)
1b5daf11 861 return err;
e126ba97 862
1b5daf11
MD		 863 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
864 if (err)
865 return err;
e126ba97 866
9603b61d
JM		 867 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
868 (fw_rev_min(dev->mdev) << 16) |
869 fw_rev_sub(dev->mdev);
e126ba97
EC		 870 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
871 IB_DEVICE_PORT_ACTIVE_EVENT |
872 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 873 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 874
875 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 876 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 877 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 878 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 879 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 880 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 881 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 882 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 883 if (MLX5_CAP_GEN(mdev, imaicl)) {
884 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
885 IB_DEVICE_MEM_WINDOW_TYPE_2B;
886 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 887 /* We support 'Gappy' memory registration too */
888 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 889 }
e126ba97 890 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 891 if (MLX5_CAP_GEN(mdev, sho)) {
c0a6cbb9 892 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER;
2dea9094
SG		 893 /* At this stage no support for signature handover */
894 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
895 IB_PROT_T10DIF_TYPE_2 |
896 IB_PROT_T10DIF_TYPE_3;
897 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
898 IB_GUARD_T10DIF_CSUM;
899 }
938fe83c 900 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 901 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 902
85c7c014 903 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
e8161334
NO		 904 if (MLX5_CAP_ETH(mdev, csum_cap)) {
905 /* Legacy bit to support old userspace libraries */
88115fe7 906 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 907 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
908 }
909
910 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
911 props->raw_packet_caps |=
912 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 913
402ca536
BW		 914 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
915 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
916 if (max_tso) {
917 resp.tso_caps.max_tso = 1 << max_tso;
918 resp.tso_caps.supported_qpts |=
919 1 << IB_QPT_RAW_PACKET;
920 resp.response_length += sizeof(resp.tso_caps);
921 }
922 }
31f69a82
YH		 923
924 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
925 resp.rss_caps.rx_hash_function =
926 MLX5_RX_HASH_FUNC_TOEPLITZ;
927 resp.rss_caps.rx_hash_fields_mask =
928 MLX5_RX_HASH_SRC_IPV4 |
929 MLX5_RX_HASH_DST_IPV4 |
930 MLX5_RX_HASH_SRC_IPV6 |
931 MLX5_RX_HASH_DST_IPV6 |
932 MLX5_RX_HASH_SRC_PORT_TCP |
933 MLX5_RX_HASH_DST_PORT_TCP |
934 MLX5_RX_HASH_SRC_PORT_UDP |
4e2b53a5
MG		 935 MLX5_RX_HASH_DST_PORT_UDP |
936 MLX5_RX_HASH_INNER;
2d93fc85
MB		 937 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
938 MLX5_ACCEL_IPSEC_CAP_DEVICE)
939 resp.rss_caps.rx_hash_fields_mask |=
940 MLX5_RX_HASH_IPSEC_SPI;
31f69a82
YH		 941 resp.response_length += sizeof(resp.rss_caps);
942 }
943 } else {
944 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
945 resp.response_length += sizeof(resp.tso_caps);
946 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
947 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 948 }
949
f0313965
ES		 950 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
951 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
952 props->device_cap_flags |= IB_DEVICE_UD_TSO;
953 }
954
03404e8a 955 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
85c7c014
DJ		 956 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
957 raw_support)
03404e8a
MG		 958 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
959
1d54f890
YH		 960 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
961 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
962 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
963
cff5a0f3 964 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
85c7c014
DJ		 965 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
966 raw_support) {
e8161334 967 /* Legacy bit to support old userspace libraries */
cff5a0f3 968 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 969 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
970 }
cff5a0f3 971
24da0016
AL		 972 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
973 props->max_dm_size =
974 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
975 }
976
da6d6ba3
MG		 977 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
978 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
979
b1383aa6
NO		 980 if (MLX5_CAP_GEN(mdev, end_pad))
981 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
982
1b5daf11
MD		 983 props->vendor_part_id = mdev->pdev->device;
984 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 985
986 props->max_mr_size = ~0ull;
e0238a6a 987 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 988 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
989 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
990 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
991 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 992 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
993 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
994 sizeof(struct mlx5_wqe_raddr_seg)) /
995 sizeof(struct mlx5_wqe_data_seg);
33023fb8
SW		 996 props->max_send_sge = max_sq_sg;
997 props->max_recv_sge = max_rq_sg;
986ef95e 998 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 999 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 1000 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 1001 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
1002 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
1003 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
1004 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
1005 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
1006 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
1007 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 1008 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 1009 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 1010 props->max_fast_reg_page_list_len =
1011 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
62e3c379
MG		 1012 props->max_pi_fast_reg_page_list_len =
1013 props->max_fast_reg_page_list_len / 2;
776a3906 1014 get_atomic_caps_qp(dev, props);
81bea28f 1015 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 1016 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
1017 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 1018 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1019 props->max_mcast_grp;
1020 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 1021 props->max_ah = INT_MAX;
7c60bcbb
MB		 1022 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
1023 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 1024
e502b8b0 1025 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
00815752 1026 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT)
e502b8b0
LR		 1027 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
1028 props->odp_caps = dev->odp_caps;
1029 }
8cdd312c 1030
051f2630
LR		 1031 if (MLX5_CAP_GEN(mdev, cd))
1032 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
1033
eff901d3
EC		 1034 if (!mlx5_core_is_pf(mdev))
1035 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
1036
31f69a82 1037 if (mlx5_ib_port_link_layer(ibdev, 1) ==
85c7c014 1038 IB_LINK_LAYER_ETHERNET && raw_support) {
31f69a82
YH		 1039 props->rss_caps.max_rwq_indirection_tables =
1040 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1041 props->rss_caps.max_rwq_indirection_table_size =
1042 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1043 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1044 props->max_wq_type_rq =
1045 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1046 }
1047
eb761894 1048 if (MLX5_CAP_GEN(mdev, tag_matching)) {
78b1beb0 1049 props->tm_caps.max_num_tags =
eb761894 1050 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
78b1beb0 1051 props->tm_caps.max_ops =
eb761894 1052 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
78b1beb0 1053 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
eb761894
AK		 1054 }
1055
89705e92
DG		 1056 if (MLX5_CAP_GEN(mdev, tag_matching) &&
1057 MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
1058 props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
1059 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1060 }
1061
87ab3f52
YC		 1062 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1063 props->cq_caps.max_cq_moderation_count =
1064 MLX5_MAX_CQ_COUNT;
1065 props->cq_caps.max_cq_moderation_period =
1066 MLX5_MAX_CQ_PERIOD;
1067 }
1068
7e43a2a5 1069 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
7e43a2a5 1070 resp.response_length += sizeof(resp.cqe_comp_caps);
572f46bf
YC		 1071
1072 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1073 resp.cqe_comp_caps.max_num =
1074 MLX5_CAP_GEN(dev->mdev,
1075 cqe_compression_max_num);
1076
1077 resp.cqe_comp_caps.supported_format =
1078 MLX5_IB_CQE_RES_FORMAT_HASH |
1079 MLX5_IB_CQE_RES_FORMAT_CSUM;
6f1006a4
YC		 1080
1081 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1082 resp.cqe_comp_caps.supported_format |=
1083 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
572f46bf 1084 }
7e43a2a5
BW		 1085 }
1086
85c7c014
DJ		 1087 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
1088 raw_support) {
d949167d
BW		 1089 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1090 MLX5_CAP_GEN(mdev, qos)) {
1091 resp.packet_pacing_caps.qp_rate_limit_max =
1092 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1093 resp.packet_pacing_caps.qp_rate_limit_min =
1094 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1095 resp.packet_pacing_caps.supported_qpts |=
1096 1 << IB_QPT_RAW_PACKET;
61147f39
BW		 1097 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1098 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1099 resp.packet_pacing_caps.cap_flags |=
1100 MLX5_IB_PP_SUPPORT_BURST;
d949167d
BW		 1101 }
1102 resp.response_length += sizeof(resp.packet_pacing_caps);
1103 }
1104
9f885201
LR		 1105 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
1106 uhw->outlen)) {
795b609c
BW		 1107 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1108 resp.mlx5_ib_support_multi_pkt_send_wqes =
1109 MLX5_IB_ALLOW_MPW;
050da902
BW		 1110
1111 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1112 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1113 MLX5_IB_SUPPORT_EMPW;
1114
9f885201
LR		 1115 resp.response_length +=
1116 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1117 }
1118
de57f2ad
GL		 1119 if (field_avail(typeof(resp), flags, uhw->outlen)) {
1120 resp.response_length += sizeof(resp.flags);
7a0c8f42 1121
de57f2ad
GL		 1122 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1123 resp.flags |=
1124 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
7a0c8f42
GL		 1125
1126 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1127 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
7e11b911
DG		 1128 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1129 resp.flags |=
1130 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
7249c8ea
GL		 1131
1132 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
de57f2ad 1133 }
9f885201 1134
96dc3fc5
NO		 1135 if (field_avail(typeof(resp), sw_parsing_caps,
1136 uhw->outlen)) {
1137 resp.response_length += sizeof(resp.sw_parsing_caps);
1138 if (MLX5_CAP_ETH(mdev, swp)) {
1139 resp.sw_parsing_caps.sw_parsing_offloads |=
1140 MLX5_IB_SW_PARSING;
1141
1142 if (MLX5_CAP_ETH(mdev, swp_csum))
1143 resp.sw_parsing_caps.sw_parsing_offloads |=
1144 MLX5_IB_SW_PARSING_CSUM;
1145
1146 if (MLX5_CAP_ETH(mdev, swp_lso))
1147 resp.sw_parsing_caps.sw_parsing_offloads |=
1148 MLX5_IB_SW_PARSING_LSO;
1149
1150 if (resp.sw_parsing_caps.sw_parsing_offloads)
1151 resp.sw_parsing_caps.supported_qpts =
1152 BIT(IB_QPT_RAW_PACKET);
1153 }
1154 }
1155
85c7c014
DJ		 1156 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1157 raw_support) {
b4f34597
NO		 1158 resp.response_length += sizeof(resp.striding_rq_caps);
1159 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1160 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1161 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1162 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1163 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1164 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1165 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1166 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1167 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1168 resp.striding_rq_caps.supported_qpts =
1169 BIT(IB_QPT_RAW_PACKET);
1170 }
1171 }
1172
f95ef6cb
MG		 1173 if (field_avail(typeof(resp), tunnel_offloads_caps,
1174 uhw->outlen)) {
1175 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1176 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1177 resp.tunnel_offloads_caps |=
1178 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1179 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1180 resp.tunnel_offloads_caps |=
1181 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1182 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1183 resp.tunnel_offloads_caps |=
1184 MLX5_IB_TUNNELED_OFFLOADS_GRE;
e818e255
AL		 1185 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1186 MLX5_FLEX_PROTO_CW_MPLS_GRE)
1187 resp.tunnel_offloads_caps |=
1188 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1189 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1190 MLX5_FLEX_PROTO_CW_MPLS_UDP)
1191 resp.tunnel_offloads_caps |=
1192 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
f95ef6cb
MG		 1193 }
1194
402ca536
BW		 1195 if (uhw->outlen) {
1196 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1197
1198 if (err)
1199 return err;
1200 }
1201
1b5daf11 1202 return 0;
e126ba97
EC		 1203}
1204
1b5daf11
MD		 1205enum mlx5_ib_width {
1206 MLX5_IB_WIDTH_1X = 1 << 0,
1207 MLX5_IB_WIDTH_2X = 1 << 1,
1208 MLX5_IB_WIDTH_4X = 1 << 2,
1209 MLX5_IB_WIDTH_8X = 1 << 3,
1210 MLX5_IB_WIDTH_12X = 1 << 4
1211};
1212
db7a691a 1213static void translate_active_width(struct ib_device *ibdev, u8 active_width,
1b5daf11 1214 u8 *ib_width)
e126ba97
EC		 1215{
1216 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11 1217
db7a691a 1218 if (active_width & MLX5_IB_WIDTH_1X)
1b5daf11 1219 *ib_width = IB_WIDTH_1X;
d764970b
MG		 1220 else if (active_width & MLX5_IB_WIDTH_2X)
1221 *ib_width = IB_WIDTH_2X;
db7a691a 1222 else if (active_width & MLX5_IB_WIDTH_4X)
1b5daf11 1223 *ib_width = IB_WIDTH_4X;
db7a691a 1224 else if (active_width & MLX5_IB_WIDTH_8X)
1b5daf11 1225 *ib_width = IB_WIDTH_8X;
db7a691a 1226 else if (active_width & MLX5_IB_WIDTH_12X)
1b5daf11 1227 *ib_width = IB_WIDTH_12X;
db7a691a
MG		 1228 else {
1229 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1b5daf11 1230 (int)active_width);
db7a691a 1231 *ib_width = IB_WIDTH_4X;
e126ba97
EC		 1232 }
1233
db7a691a 1234 return;
1b5daf11 1235}
e126ba97 1236
1b5daf11
MD		 1237static int mlx5_mtu_to_ib_mtu(int mtu)
1238{
1239 switch (mtu) {
1240 case 256: return 1;
1241 case 512: return 2;
1242 case 1024: return 3;
1243 case 2048: return 4;
1244 case 4096: return 5;
1245 default:
1246 pr_warn("invalid mtu\n");
1247 return -1;
e126ba97 1248 }
1b5daf11 1249}
e126ba97 1250
1b5daf11
MD		 1251enum ib_max_vl_num {
1252 __IB_MAX_VL_0 = 1,
1253 __IB_MAX_VL_0_1 = 2,
1254 __IB_MAX_VL_0_3 = 3,
1255 __IB_MAX_VL_0_7 = 4,
1256 __IB_MAX_VL_0_14 = 5,
1257};
e126ba97 1258
1b5daf11
MD		 1259enum mlx5_vl_hw_cap {
1260 MLX5_VL_HW_0 = 1,
1261 MLX5_VL_HW_0_1 = 2,
1262 MLX5_VL_HW_0_2 = 3,
1263 MLX5_VL_HW_0_3 = 4,
1264 MLX5_VL_HW_0_4 = 5,
1265 MLX5_VL_HW_0_5 = 6,
1266 MLX5_VL_HW_0_6 = 7,
1267 MLX5_VL_HW_0_7 = 8,
1268 MLX5_VL_HW_0_14 = 15
1269};
e126ba97 1270
1b5daf11
MD		 1271static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1272 u8 *max_vl_num)
1273{
1274 switch (vl_hw_cap) {
1275 case MLX5_VL_HW_0:
1276 *max_vl_num = __IB_MAX_VL_0;
1277 break;
1278 case MLX5_VL_HW_0_1:
1279 *max_vl_num = __IB_MAX_VL_0_1;
1280 break;
1281 case MLX5_VL_HW_0_3:
1282 *max_vl_num = __IB_MAX_VL_0_3;
1283 break;
1284 case MLX5_VL_HW_0_7:
1285 *max_vl_num = __IB_MAX_VL_0_7;
1286 break;
1287 case MLX5_VL_HW_0_14:
1288 *max_vl_num = __IB_MAX_VL_0_14;
1289 break;
e126ba97 1290
1b5daf11
MD		 1291 default:
1292 return -EINVAL;
e126ba97 1293 }
e126ba97 1294
1b5daf11 1295 return 0;
e126ba97
EC		 1296}
1297
1b5daf11
MD		 1298static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1299 struct ib_port_attr *props)
e126ba97 1300{
1b5daf11
MD		 1301 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1302 struct mlx5_core_dev *mdev = dev->mdev;
1303 struct mlx5_hca_vport_context *rep;
046339ea
SM		 1304 u16 max_mtu;
1305 u16 oper_mtu;
1b5daf11
MD		 1306 int err;
1307 u8 ib_link_width_oper;
1308 u8 vl_hw_cap;
e126ba97 1309
1b5daf11
MD		 1310 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1311 if (!rep) {
1312 err = -ENOMEM;
e126ba97 1313 goto out;
e126ba97 1314 }
e126ba97 1315
c4550c63 1316 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 1317
1b5daf11 1318 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 1319 if (err)
1320 goto out;
1321
1b5daf11
MD		 1322 props->lid = rep->lid;
1323 props->lmc = rep->lmc;
1324 props->sm_lid = rep->sm_lid;
1325 props->sm_sl = rep->sm_sl;
1326 props->state = rep->vport_state;
1327 props->phys_state = rep->port_physical_state;
1328 props->port_cap_flags = rep->cap_mask1;
1329 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1330 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1331 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1332 props->bad_pkey_cntr = rep->pkey_violation_counter;
1333 props->qkey_viol_cntr = rep->qkey_violation_counter;
1334 props->subnet_timeout = rep->subnet_timeout;
1335 props->init_type_reply = rep->init_type_reply;
e126ba97 1336
4106a758
MG		 1337 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1338 props->port_cap_flags2 = rep->cap_mask2;
1339
1b5daf11
MD		 1340 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1341 if (err)
e126ba97 1342 goto out;
e126ba97 1343
db7a691a
MG		 1344 translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1345
d5beb7f2 1346 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 1347 if (err)
1348 goto out;
1349
facc9699 1350 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 1351
1b5daf11 1352 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 1353
facc9699 1354 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 1355
1b5daf11 1356 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1357
1b5daf11
MD		 1358 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1359 if (err)
1360 goto out;
e126ba97 1361
1b5daf11
MD		 1362 err = translate_max_vl_num(ibdev, vl_hw_cap,
1363 &props->max_vl_num);
e126ba97 1364out:
1b5daf11 1365 kfree(rep);
e126ba97
EC		 1366 return err;
1367}
1368
1b5daf11
MD		 1369int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1370 struct ib_port_attr *props)
e126ba97 1371{
095b0927
IT		 1372 unsigned int count;
1373 int ret;
1374
1b5daf11
MD		 1375 switch (mlx5_get_vport_access_method(ibdev)) {
1376 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1377 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1378 break;
e126ba97 1379
1b5daf11 1380 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1381 ret = mlx5_query_hca_port(ibdev, port, props);
1382 break;
e126ba97 1383
3f89a643 1384 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1385 ret = mlx5_query_port_roce(ibdev, port, props);
1386 break;
3f89a643 1387
1b5daf11 1388 default:
095b0927
IT		 1389 ret = -EINVAL;
1390 }
1391
1392 if (!ret && props) {
b3cbd6f0
DJ		 1393 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1394 struct mlx5_core_dev *mdev;
1395 bool put_mdev = true;
1396
1397 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1398 if (!mdev) {
1399 /* If the port isn't affiliated yet query the master.
1400 * The master and slave will have the same values.
1401 */
1402 mdev = dev->mdev;
1403 port = 1;
1404 put_mdev = false;
1405 }
1406 count = mlx5_core_reserved_gids_count(mdev);
1407 if (put_mdev)
1408 mlx5_ib_put_native_port_mdev(dev, port);
095b0927 1409 props->gid_tbl_len -= count;
1b5daf11 1410 }
095b0927 1411 return ret;
1b5daf11 1412}
e126ba97 1413
8e6efa3a
MB		 1414static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1415 struct ib_port_attr *props)
1416{
1417 int ret;
1418
26628e2d
MB		 1419 /* Only link layer == ethernet is valid for representors
1420 * and we always use port 1
1421 */
8e6efa3a
MB		 1422 ret = mlx5_query_port_roce(ibdev, port, props);
1423 if (ret || !props)
1424 return ret;
1425
1426 /* We don't support GIDS */
1427 props->gid_tbl_len = 0;
1428
1429 return ret;
1430}
1431
1b5daf11
MD		 1432static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1433 union ib_gid *gid)
1434{
1435 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1436 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1437
1b5daf11
MD		 1438 switch (mlx5_get_vport_access_method(ibdev)) {
1439 case MLX5_VPORT_ACCESS_METHOD_MAD:
1440 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1441
1b5daf11
MD		 1442 case MLX5_VPORT_ACCESS_METHOD_HCA:
1443 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1444
1445 default:
1446 return -EINVAL;
1447 }
e126ba97 1448
e126ba97
EC		 1449}
1450
b3cbd6f0
DJ		 1451static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1452 u16 index, u16 *pkey)
1b5daf11
MD		 1453{
1454 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b3cbd6f0
DJ		 1455 struct mlx5_core_dev *mdev;
1456 bool put_mdev = true;
1457 u8 mdev_port_num;
1458 int err;
1b5daf11 1459
b3cbd6f0
DJ		 1460 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1461 if (!mdev) {
1462 /* The port isn't affiliated yet, get the PKey from the master
1463 * port. For RoCE the PKey tables will be the same.
1464 */
1465 put_mdev = false;
1466 mdev = dev->mdev;
1467 mdev_port_num = 1;
1468 }
1469
1470 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1471 index, pkey);
1472 if (put_mdev)
1473 mlx5_ib_put_native_port_mdev(dev, port);
1474
1475 return err;
1476}
1477
1478static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1479 u16 *pkey)
1480{
1b5daf11
MD		 1481 switch (mlx5_get_vport_access_method(ibdev)) {
1482 case MLX5_VPORT_ACCESS_METHOD_MAD:
1483 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1484
1485 case MLX5_VPORT_ACCESS_METHOD_HCA:
1486 case MLX5_VPORT_ACCESS_METHOD_NIC:
b3cbd6f0 1487 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1b5daf11
MD		 1488 default:
1489 return -EINVAL;
1490 }
1491}
e126ba97
EC		 1492
1493static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1494 struct ib_device_modify *props)
1495{
1496 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1497 struct mlx5_reg_node_desc in;
1498 struct mlx5_reg_node_desc out;
1499 int err;
1500
1501 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1502 return -EOPNOTSUPP;
1503
1504 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1505 return 0;
1506
1507 /*
1508 * If possible, pass node desc to FW, so it can generate
1509 * a 144 trap. If cmd fails, just ignore.
1510 */
bd99fdea 1511 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1512 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1513 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1514 if (err)
1515 return err;
1516
bd99fdea 1517 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1518
1519 return err;
1520}
1521
cdbe33d0
EC		 1522static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1523 u32 value)
1524{
1525 struct mlx5_hca_vport_context ctx = {};
b3cbd6f0
DJ		 1526 struct mlx5_core_dev *mdev;
1527 u8 mdev_port_num;
cdbe33d0
EC		 1528 int err;
1529
b3cbd6f0
DJ		 1530 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1531 if (!mdev)
1532 return -ENODEV;
1533
1534 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
cdbe33d0 1535 if (err)
b3cbd6f0 1536 goto out;
cdbe33d0
EC		 1537
1538 if (~ctx.cap_mask1_perm & mask) {
1539 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1540 mask, ctx.cap_mask1_perm);
b3cbd6f0
DJ		 1541 err = -EINVAL;
1542 goto out;
cdbe33d0
EC		 1543 }
1544
1545 ctx.cap_mask1 = value;
1546 ctx.cap_mask1_perm = mask;
b3cbd6f0
DJ		 1547 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1548 0, &ctx);
1549
1550out:
1551 mlx5_ib_put_native_port_mdev(dev, port_num);
cdbe33d0
EC		 1552
1553 return err;
1554}
1555
e126ba97
EC		 1556static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1557 struct ib_port_modify *props)
1558{
1559 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1560 struct ib_port_attr attr;
1561 u32 tmp;
1562 int err;
cdbe33d0
EC		 1563 u32 change_mask;
1564 u32 value;
1565 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1566 IB_LINK_LAYER_INFINIBAND);
1567
ec255879
MD		 1568 /* CM layer calls ib_modify_port() regardless of the link layer. For
1569 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1570 */
1571 if (!is_ib)
1572 return 0;
1573
cdbe33d0
EC		 1574 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1575 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1576 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1577 return set_port_caps_atomic(dev, port, change_mask, value);
1578 }
e126ba97
EC		 1579
1580 mutex_lock(&dev->cap_mask_mutex);
1581
c4550c63 1582 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1583 if (err)
1584 goto out;
1585
1586 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1587 ~props->clr_port_cap_mask;
1588
9603b61d 1589 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1590
1591out:
1592 mutex_unlock(&dev->cap_mask_mutex);
1593 return err;
1594}
1595
30aa60b3
EC		 1596static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1597{
1598 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1599 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1600}
1601
31a78a5a
YH		 1602static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1603{
1604 /* Large page with non 4k uar support might limit the dynamic size */
1605 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1606 return MLX5_MIN_DYN_BFREGS;
1607
1608 return MLX5_MAX_DYN_BFREGS;
1609}
1610
b037c29a
EC		 1611static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1612 struct mlx5_ib_alloc_ucontext_req_v2 *req,
31a78a5a 1613 struct mlx5_bfreg_info *bfregi)
b037c29a
EC		 1614{
1615 int uars_per_sys_page;
1616 int bfregs_per_sys_page;
1617 int ref_bfregs = req->total_num_bfregs;
1618
1619 if (req->total_num_bfregs == 0)
1620 return -EINVAL;
1621
1622 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1623 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1624
1625 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1626 return -ENOMEM;
1627
1628 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1629 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
31a78a5a 1630 /* This holds the required static allocation asked by the user */
b037c29a 1631 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
b037c29a
EC		 1632 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1633 return -EINVAL;
1634
31a78a5a
YH		 1635 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1636 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1637 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1638 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1639
1640 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
b037c29a
EC		 1641 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1642 lib_uar_4k ? "yes" : "no", ref_bfregs,
31a78a5a
YH		 1643 req->total_num_bfregs, bfregi->total_num_bfregs,
1644 bfregi->num_sys_pages);
b037c29a
EC		 1645
1646 return 0;
1647}
1648
1649static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1650{
1651 struct mlx5_bfreg_info *bfregi;
1652 int err;
1653 int i;
1654
1655 bfregi = &context->bfregi;
31a78a5a 1656 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
b037c29a
EC		 1657 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1658 if (err)
1659 goto error;
1660
1661 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1662 }
4ed131d0
YH		 1663
1664 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1665 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1666
b037c29a
EC		 1667 return 0;
1668
1669error:
1670 for (--i; i >= 0; i--)
1671 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1672 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1673
1674 return err;
1675}
1676
15177999
LR		 1677static void deallocate_uars(struct mlx5_ib_dev *dev,
1678 struct mlx5_ib_ucontext *context)
b037c29a
EC		 1679{
1680 struct mlx5_bfreg_info *bfregi;
b037c29a
EC		 1681 int i;
1682
1683 bfregi = &context->bfregi;
15177999 1684 for (i = 0; i < bfregi->num_sys_pages; i++)
4ed131d0 1685 if (i < bfregi->num_static_sys_pages ||
15177999
LR		 1686 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1687 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
b037c29a
EC		 1688}
1689
0042f9e4 1690int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
a560f1d9
MB		 1691{
1692 int err = 0;
1693
1694 mutex_lock(&dev->lb.mutex);
0042f9e4
MB		 1695 if (td)
1696 dev->lb.user_td++;
1697 if (qp)
1698 dev->lb.qps++;
1699
1700 if (dev->lb.user_td == 2 ||
1701 dev->lb.qps == 1) {
1702 if (!dev->lb.enabled) {
1703 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1704 dev->lb.enabled = true;
1705 }
1706 }
a560f1d9
MB		 1707
1708 mutex_unlock(&dev->lb.mutex);
1709
1710 return err;
1711}
1712
0042f9e4 1713void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
a560f1d9
MB		 1714{
1715 mutex_lock(&dev->lb.mutex);
0042f9e4
MB		 1716 if (td)
1717 dev->lb.user_td--;
1718 if (qp)
1719 dev->lb.qps--;
1720
1721 if (dev->lb.user_td == 1 &&
1722 dev->lb.qps == 0) {
1723 if (dev->lb.enabled) {
1724 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1725 dev->lb.enabled = false;
1726 }
1727 }
a560f1d9
MB		 1728
1729 mutex_unlock(&dev->lb.mutex);
1730}
1731
d2d19121
YH		 1732static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1733 u16 uid)
c85023e1
HN		 1734{
1735 int err;
1736
cfdeb893
LR		 1737 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1738 return 0;
1739
d2d19121 1740 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
c85023e1
HN		 1741 if (err)
1742 return err;
1743
1744 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1745 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1746 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1747 return err;
1748
0042f9e4 1749 return mlx5_ib_enable_lb(dev, true, false);
c85023e1
HN		 1750}
1751
d2d19121
YH		 1752static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1753 u16 uid)
c85023e1 1754{
cfdeb893
LR		 1755 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1756 return;
1757
d2d19121 1758 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
c85023e1
HN		 1759
1760 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1761 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1762 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1763 return;
1764
0042f9e4 1765 mlx5_ib_disable_lb(dev, true, false);
c85023e1
HN		 1766}
1767
a2a074ef
LR		 1768static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1769 struct ib_udata *udata)
e126ba97 1770{
a2a074ef 1771 struct ib_device *ibdev = uctx->device;
e126ba97 1772 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1773 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1774 struct mlx5_ib_alloc_ucontext_resp resp = {};
5c99eaec 1775 struct mlx5_core_dev *mdev = dev->mdev;
a2a074ef 1776 struct mlx5_ib_ucontext *context = to_mucontext(uctx);
2f5ff264 1777 struct mlx5_bfreg_info *bfregi;
78c0f98c 1778 int ver;
e126ba97 1779 int err;
a168a41c
MD		 1780 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1781 max_cqe_version);
25bb36e7 1782 u32 dump_fill_mkey;
b037c29a 1783 bool lib_uar_4k;
e126ba97
EC		 1784
1785 if (!dev->ib_active)
a2a074ef 1786 return -EAGAIN;
e126ba97 1787
e093111d 1788 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1789 ver = 0;
e093111d 1790 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1791 ver = 2;
1792 else
a2a074ef 1793 return -EINVAL;
78c0f98c 1794
e093111d 1795 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97 1796 if (err)
a2a074ef 1797 return err;
e126ba97 1798
a8b92ca1 1799 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
a2a074ef 1800 return -EOPNOTSUPP;
78c0f98c 1801
f72300c5 1802 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
a2a074ef 1803 return -EOPNOTSUPP;
b368d7cb 1804
2f5ff264
EC		 1805 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1806 MLX5_NON_FP_BFREGS_PER_UAR);
1807 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
a2a074ef 1808 return -EINVAL;
e126ba97 1809
938fe83c 1810 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1811 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1812 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1813 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1814 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1815 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1816 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1817 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1818 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1819 resp.cqe_version = min_t(__u8,
1820 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1821 req.max_cqe_version);
30aa60b3
EC		 1822 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1823 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1824 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1825 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1826 resp.response_length = min(offsetof(typeof(resp), response_length) +
1827 sizeof(resp.response_length), udata->outlen);
e126ba97 1828
c03faa56
MB		 1829 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1830 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1831 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1832 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1833 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1834 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1835 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1836 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1837 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1838 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1839 }
1840
30aa60b3 1841 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1842 bfregi = &context->bfregi;
b037c29a
EC		 1843
1844 /* updates req->total_num_bfregs */
31a78a5a 1845 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
b037c29a 1846 if (err)
e126ba97 1847 goto out_ctx;
e126ba97 1848
b037c29a
EC		 1849 mutex_init(&bfregi->lock);
1850 bfregi->lib_uar_4k = lib_uar_4k;
31a78a5a 1851 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1852 GFP_KERNEL);
b037c29a 1853 if (!bfregi->count) {
e126ba97 1854 err = -ENOMEM;
b037c29a 1855 goto out_ctx;
e126ba97
EC		 1856 }
1857
b037c29a
EC		 1858 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1859 sizeof(*bfregi->sys_pages),
1860 GFP_KERNEL);
1861 if (!bfregi->sys_pages) {
e126ba97 1862 err = -ENOMEM;
b037c29a 1863 goto out_count;
e126ba97
EC		 1864 }
1865
b037c29a
EC		 1866 err = allocate_uars(dev, context);
1867 if (err)
1868 goto out_sys_pages;
e126ba97 1869
a8b92ca1 1870 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
fb98153b 1871 err = mlx5_ib_devx_create(dev, true);
76dc5a84 1872 if (err < 0)
d2d19121 1873 goto out_uars;
76dc5a84 1874 context->devx_uid = err;
a8b92ca1
YH		 1875 }
1876
d2d19121
YH		 1877 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1878 context->devx_uid);
1879 if (err)
1880 goto out_devx;
1881
25bb36e7
YC		 1882 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1883 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1884 if (err)
8193abb6 1885 goto out_mdev;
25bb36e7
YC		 1886 }
1887
e126ba97
EC		 1888 INIT_LIST_HEAD(&context->db_page_list);
1889 mutex_init(&context->db_page_mutex);
1890
2f5ff264 1891 resp.tot_bfregs = req.total_num_bfregs;
508562d6 1892 resp.num_ports = dev->num_ports;
b368d7cb 1893
f72300c5
HA		 1894 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1895 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1896
402ca536 1897 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1898 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1899 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1900 resp.response_length += sizeof(resp.cmds_supp_uhw);
1901 }
1902
78984898
OG		 1903 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1904 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1905 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1906 resp.eth_min_inline++;
1907 }
1908 resp.response_length += sizeof(resp.eth_min_inline);
1909 }
1910
5c99eaec
FD		 1911 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1912 if (mdev->clock_info)
1913 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1914 resp.response_length += sizeof(resp.clock_info_versions);
1915 }
1916
bc5c6eed
NO		 1917 /*
1918 * We don't want to expose information from the PCI bar that is located
1919 * after 4096 bytes, so if the arch only supports larger pages, let's
1920 * pretend we don't support reading the HCA's core clock. This is also
1921 * forced by mmap function.
1922 */
de8d6e02
EC		 1923 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1924 if (PAGE_SIZE <= 4096) {
1925 resp.comp_mask |=
1926 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1927 resp.hca_core_clock_offset =
1928 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1929 }
5c99eaec 1930 resp.response_length += sizeof(resp.hca_core_clock_offset);
b368d7cb
MB		 1931 }
1932
30aa60b3
EC		 1933 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1934 resp.response_length += sizeof(resp.log_uar_size);
1935
1936 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1937 resp.response_length += sizeof(resp.num_uars_per_page);
1938
31a78a5a
YH		 1939 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1940 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1941 resp.response_length += sizeof(resp.num_dyn_bfregs);
1942 }
1943
25bb36e7
YC		 1944 if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) {
1945 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1946 resp.dump_fill_mkey = dump_fill_mkey;
1947 resp.comp_mask |=
1948 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1949 }
1950 resp.response_length += sizeof(resp.dump_fill_mkey);
1951 }
1952
b368d7cb 1953 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1954 if (err)
a8b92ca1 1955 goto out_mdev;
e126ba97 1956
2f5ff264
EC		 1957 bfregi->ver = ver;
1958 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1959 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1960 context->lib_caps = req.lib_caps;
1961 print_lib_caps(dev, context->lib_caps);
f72300c5 1962
7c34ec19 1963 if (dev->lag_active) {
95579e78 1964 u8 port = mlx5_core_native_port_num(dev->mdev) - 1;
c6a21c38
MD		 1965
1966 atomic_set(&context->tx_port_affinity,
1967 atomic_add_return(
95579e78 1968 1, &dev->port[port].roce.tx_port_affinity));
c6a21c38
MD		 1969 }
1970
a2a074ef 1971 return 0;
e126ba97 1972
a8b92ca1 1973out_mdev:
d2d19121
YH		 1974 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1975out_devx:
a8b92ca1 1976 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
76dc5a84 1977 mlx5_ib_devx_destroy(dev, context->devx_uid);
146d2f1a 1978
e126ba97 1979out_uars:
b037c29a 1980 deallocate_uars(dev, context);
e126ba97 1981
b037c29a
EC		 1982out_sys_pages:
1983 kfree(bfregi->sys_pages);
e126ba97 1984
b037c29a
EC		 1985out_count:
1986 kfree(bfregi->count);
e126ba97
EC		 1987
1988out_ctx:
a2a074ef 1989 return err;
e126ba97
EC		 1990}
1991
a2a074ef 1992static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
e126ba97
EC		 1993{
1994 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1995 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 1996 struct mlx5_bfreg_info *bfregi;
e126ba97 1997
f27a0d50
JG		 1998 /* All umem's must be destroyed before destroying the ucontext. */
1999 mutex_lock(&ibcontext->per_mm_list_lock);
2000 WARN_ON(!list_empty(&ibcontext->per_mm_list));
2001 mutex_unlock(&ibcontext->per_mm_list_lock);
a8b92ca1 2002
b037c29a 2003 bfregi = &context->bfregi;
d2d19121
YH		 2004 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
2005
a8b92ca1 2006 if (context->devx_uid)
76dc5a84 2007 mlx5_ib_devx_destroy(dev, context->devx_uid);
146d2f1a 2008
b037c29a
EC		 2009 deallocate_uars(dev, context);
2010 kfree(bfregi->sys_pages);
2f5ff264 2011 kfree(bfregi->count);
e126ba97
EC		 2012}
2013
b037c29a 2014static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
4ed131d0 2015 int uar_idx)
e126ba97 2016{
b037c29a
EC		 2017 int fw_uars_per_page;
2018
2019 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2020
aa8106f1 2021 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
e126ba97
EC		 2022}
2023
2024static int get_command(unsigned long offset)
2025{
2026 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2027}
2028
2029static int get_arg(unsigned long offset)
2030{
2031 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2032}
2033
2034static int get_index(unsigned long offset)
2035{
2036 return get_arg(offset);
2037}
2038
4ed131d0
YH		 2039/* Index resides in an extra byte to enable larger values than 255 */
2040static int get_extended_index(unsigned long offset)
2041{
2042 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2043}
2044
7c2344c3
MG		 2045
2046static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2047{
7c2344c3
MG		 2048}
2049
37aa5c36
GL		 2050static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2051{
2052 switch (cmd) {
2053 case MLX5_IB_MMAP_WC_PAGE:
2054 return "WC";
2055 case MLX5_IB_MMAP_REGULAR_PAGE:
2056 return "best effort WC";
2057 case MLX5_IB_MMAP_NC_PAGE:
2058 return "NC";
24da0016
AL		 2059 case MLX5_IB_MMAP_DEVICE_MEM:
2060 return "Device Memory";
37aa5c36
GL		 2061 default:
2062 return NULL;
2063 }
2064}
2065
5c99eaec
FD		 2066static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2067 struct vm_area_struct *vma,
2068 struct mlx5_ib_ucontext *context)
2069{
4eb6ab13
JG		 2070 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2071 !(vma->vm_flags & VM_SHARED))
5c99eaec
FD		 2072 return -EINVAL;
2073
2074 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2075 return -EOPNOTSUPP;
2076
4eb6ab13 2077 if (vma->vm_flags & (VM_WRITE | VM_EXEC))
5c99eaec 2078 return -EPERM;
c660133c 2079 vma->vm_flags &= ~VM_MAYWRITE;
5c99eaec 2080
ddcdc368 2081 if (!dev->mdev->clock_info)
5c99eaec
FD		 2082 return -EOPNOTSUPP;
2083
4eb6ab13
JG		 2084 return vm_insert_page(vma, vma->vm_start,
2085 virt_to_page(dev->mdev->clock_info));
5c99eaec
FD		 2086}
2087
37aa5c36 2088static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 2089 struct vm_area_struct *vma,
2090 struct mlx5_ib_ucontext *context)
37aa5c36 2091{
2f5ff264 2092 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 2093 int err;
2094 unsigned long idx;
aa09ea6e 2095 phys_addr_t pfn;
37aa5c36 2096 pgprot_t prot;
4ed131d0
YH		 2097 u32 bfreg_dyn_idx = 0;
2098 u32 uar_index;
2099 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2100 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2101 bfregi->num_static_sys_pages;
b037c29a
EC		 2102
2103 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2104 return -EINVAL;
2105
4ed131d0
YH		 2106 if (dyn_uar)
2107 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2108 else
2109 idx = get_index(vma->vm_pgoff);
2110
2111 if (idx >= max_valid_idx) {
2112 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2113 idx, max_valid_idx);
b037c29a
EC		 2114 return -EINVAL;
2115 }
37aa5c36
GL		 2116
2117 switch (cmd) {
2118 case MLX5_IB_MMAP_WC_PAGE:
4ed131d0 2119 case MLX5_IB_MMAP_ALLOC_WC:
37aa5c36
GL		 2120/* Some architectures don't support WC memory */
2121#if defined(CONFIG_X86)
2122 if (!pat_enabled())
2123 return -EPERM;
2124#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2125 return -EPERM;
2126#endif
2127 /* fall through */
2128 case MLX5_IB_MMAP_REGULAR_PAGE:
2129 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2130 prot = pgprot_writecombine(vma->vm_page_prot);
2131 break;
2132 case MLX5_IB_MMAP_NC_PAGE:
2133 prot = pgprot_noncached(vma->vm_page_prot);
2134 break;
2135 default:
2136 return -EINVAL;
2137 }
2138
4ed131d0
YH		 2139 if (dyn_uar) {
2140 int uars_per_page;
2141
2142 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2143 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2144 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2145 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2146 bfreg_dyn_idx, bfregi->total_num_bfregs);
2147 return -EINVAL;
2148 }
2149
2150 mutex_lock(&bfregi->lock);
2151 /* Fail if uar already allocated, first bfreg index of each
2152 * page holds its count.
2153 */
2154 if (bfregi->count[bfreg_dyn_idx]) {
2155 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2156 mutex_unlock(&bfregi->lock);
2157 return -EINVAL;
2158 }
2159
2160 bfregi->count[bfreg_dyn_idx]++;
2161 mutex_unlock(&bfregi->lock);
2162
2163 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2164 if (err) {
2165 mlx5_ib_warn(dev, "UAR alloc failed\n");
2166 goto free_bfreg;
2167 }
2168 } else {
2169 uar_index = bfregi->sys_pages[idx];
2170 }
2171
2172 pfn = uar_index2pfn(dev, uar_index);
37aa5c36
GL		 2173 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2174
e2cd1d1a
JG		 2175 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2176 prot);
37aa5c36 2177 if (err) {
8f062287 2178 mlx5_ib_err(dev,
e2cd1d1a 2179 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
8f062287 2180 err, mmap_cmd2str(cmd));
4ed131d0 2181 goto err;
37aa5c36
GL		 2182 }
2183
4ed131d0
YH		 2184 if (dyn_uar)
2185 bfregi->sys_pages[idx] = uar_index;
2186 return 0;
2187
2188err:
2189 if (!dyn_uar)
2190 return err;
2191
2192 mlx5_cmd_free_uar(dev->mdev, idx);
2193
2194free_bfreg:
2195 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2196
2197 return err;
37aa5c36
GL		 2198}
2199
24da0016
AL		 2200static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2201{
2202 struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2203 struct mlx5_ib_dev *dev = to_mdev(context->device);
2204 u16 page_idx = get_extended_index(vma->vm_pgoff);
2205 size_t map_size = vma->vm_end - vma->vm_start;
2206 u32 npages = map_size >> PAGE_SHIFT;
2207 phys_addr_t pfn;
24da0016
AL		 2208
2209 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2210 page_idx + npages)
2211 return -EINVAL;
2212
aa8106f1 2213 pfn = ((dev->mdev->bar_addr +
24da0016
AL		 2214 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2215 PAGE_SHIFT) +
2216 page_idx;
e2cd1d1a
JG		 2217 return rdma_user_mmap_io(context, vma, pfn, map_size,
2218 pgprot_writecombine(vma->vm_page_prot));
24da0016
AL		 2219}
2220
e126ba97
EC		 2221static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2222{
2223 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2224 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 2225 unsigned long command;
e126ba97
EC		 2226 phys_addr_t pfn;
2227
2228 command = get_command(vma->vm_pgoff);
2229 switch (command) {
37aa5c36
GL		 2230 case MLX5_IB_MMAP_WC_PAGE:
2231 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 2232 case MLX5_IB_MMAP_REGULAR_PAGE:
4ed131d0 2233 case MLX5_IB_MMAP_ALLOC_WC:
7c2344c3 2234 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 2235
2236 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2237 return -ENOSYS;
2238
d69e3bcf 2239 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 2240 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2241 return -EINVAL;
2242
6cbac1e4 2243 if (vma->vm_flags & VM_WRITE)
d69e3bcf 2244 return -EPERM;
c660133c 2245 vma->vm_flags &= ~VM_MAYWRITE;
d69e3bcf
MB		 2246
2247 /* Don't expose to user-space information it shouldn't have */
2248 if (PAGE_SIZE > 4096)
2249 return -EOPNOTSUPP;
2250
d69e3bcf
MB		 2251 pfn = (dev->mdev->iseg_base +
2252 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2253 PAGE_SHIFT;
d5e560d3
JG		 2254 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2255 PAGE_SIZE,
2256 pgprot_noncached(vma->vm_page_prot));
5c99eaec
FD		 2257 case MLX5_IB_MMAP_CLOCK_INFO:
2258 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
d69e3bcf 2259
24da0016
AL		 2260 case MLX5_IB_MMAP_DEVICE_MEM:
2261 return dm_mmap(ibcontext, vma);
2262
e126ba97
EC		 2263 default:
2264 return -EINVAL;
2265 }
2266
2267 return 0;
2268}
2269
25c13324
AL		 2270static inline int check_dm_type_support(struct mlx5_ib_dev *dev,
2271 u32 type)
24da0016 2272{
25c13324
AL		 2273 switch (type) {
2274 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2275 if (!MLX5_CAP_DEV_MEM(dev->mdev, memic))
2276 return -EOPNOTSUPP;
2277 break;
2278 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2279 if (!capable(CAP_SYS_RAWIO) ||
2280 !capable(CAP_NET_RAW))
2281 return -EPERM;
2282
2283 if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
2284 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner)))
2285 return -EOPNOTSUPP;
2286 break;
2287 }
2288
2289 return 0;
2290}
2291
3b113a1e
AL		 2292static int handle_alloc_dm_memic(struct ib_ucontext *ctx,
2293 struct mlx5_ib_dm *dm,
2294 struct ib_dm_alloc_attr *attr,
2295 struct uverbs_attr_bundle *attrs)
24da0016 2296{
3b113a1e 2297 struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm;
24da0016
AL		 2298 u64 start_offset;
2299 u32 page_idx;
2300 int err;
2301
3b113a1e 2302 dm->size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
24da0016 2303
3b113a1e
AL		 2304 err = mlx5_cmd_alloc_memic(dm_db, &dm->dev_addr,
2305 dm->size, attr->alignment);
24da0016 2306 if (err)
3b113a1e 2307 return err;
24da0016 2308
3b113a1e
AL		 2309 page_idx = (dm->dev_addr - pci_resource_start(dm_db->dev->pdev, 0) -
2310 MLX5_CAP64_DEV_MEM(dm_db->dev, memic_bar_start_addr)) >>
24da0016
AL		 2311 PAGE_SHIFT;
2312
2313 err = uverbs_copy_to(attrs,
3b113a1e
AL		 2314 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2315 &page_idx, sizeof(page_idx));
24da0016
AL		 2316 if (err)
2317 goto err_dealloc;
2318
3b113a1e 2319 start_offset = dm->dev_addr & ~PAGE_MASK;
24da0016
AL		 2320 err = uverbs_copy_to(attrs,
2321 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2322 &start_offset, sizeof(start_offset));
2323 if (err)
2324 goto err_dealloc;
2325
3b113a1e
AL		 2326 bitmap_set(to_mucontext(ctx)->dm_pages, page_idx,
2327 DIV_ROUND_UP(dm->size, PAGE_SIZE));
2328
2329 return 0;
2330
2331err_dealloc:
2332 mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2333
2334 return err;
2335}
2336
25c13324
AL		 2337static int handle_alloc_dm_sw_icm(struct ib_ucontext *ctx,
2338 struct mlx5_ib_dm *dm,
2339 struct ib_dm_alloc_attr *attr,
2340 struct uverbs_attr_bundle *attrs,
2341 int type)
2342{
2343 struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm;
2344 u64 act_size;
2345 int err;
2346
2347 /* Allocation size must a multiple of the basic block size
2348 * and a power of 2.
2349 */
37eb86c4 2350 act_size = round_up(attr->length, MLX5_SW_ICM_BLOCK_SIZE(dm_db->dev));
25c13324
AL		 2351 act_size = roundup_pow_of_two(act_size);
2352
2353 dm->size = act_size;
2354 err = mlx5_cmd_alloc_sw_icm(dm_db, type, act_size,
2355 to_mucontext(ctx)->devx_uid, &dm->dev_addr,
2356 &dm->icm_dm.obj_id);
2357 if (err)
2358 return err;
2359
24da0016 2360 err = uverbs_copy_to(attrs,
25c13324
AL		 2361 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2362 &dm->dev_addr, sizeof(dm->dev_addr));
24da0016 2363 if (err)
25c13324
AL		 2364 mlx5_cmd_dealloc_sw_icm(dm_db, type, dm->size,
2365 to_mucontext(ctx)->devx_uid,
2366 dm->dev_addr, dm->icm_dm.obj_id);
2367
2368 return err;
2369}
2370
3b113a1e
AL		 2371struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2372 struct ib_ucontext *context,
2373 struct ib_dm_alloc_attr *attr,
2374 struct uverbs_attr_bundle *attrs)
2375{
2376 struct mlx5_ib_dm *dm;
2377 enum mlx5_ib_uapi_dm_type type;
2378 int err;
24da0016 2379
3b113a1e
AL		 2380 err = uverbs_get_const_default(&type, attrs,
2381 MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
2382 MLX5_IB_UAPI_DM_TYPE_MEMIC);
2383 if (err)
2384 return ERR_PTR(err);
24da0016 2385
3b113a1e
AL		 2386 mlx5_ib_dbg(to_mdev(ibdev), "alloc_dm req: dm_type=%d user_length=0x%llx log_alignment=%d\n",
2387 type, attr->length, attr->alignment);
2388
25c13324
AL		 2389 err = check_dm_type_support(to_mdev(ibdev), type);
2390 if (err)
2391 return ERR_PTR(err);
2392
3b113a1e
AL		 2393 dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2394 if (!dm)
2395 return ERR_PTR(-ENOMEM);
2396
2397 dm->type = type;
2398
2399 switch (type) {
2400 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2401 err = handle_alloc_dm_memic(context, dm,
2402 attr,
2403 attrs);
2404 break;
25c13324
AL		 2405 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2406 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2407 err = handle_alloc_dm_sw_icm(context, dm, attr, attrs, type);
2408 break;
3b113a1e
AL		 2409 default:
2410 err = -EOPNOTSUPP;
2411 }
24da0016 2412
3b113a1e
AL		 2413 if (err)
2414 goto err_free;
24da0016
AL		 2415
2416 return &dm->ibdm;
2417
24da0016
AL		 2418err_free:
2419 kfree(dm);
2420 return ERR_PTR(err);
2421}
2422
c4367a26 2423int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs)
24da0016 2424{
25c13324
AL		 2425 struct mlx5_ib_ucontext *ctx = rdma_udata_to_drv_context(
2426 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
3b113a1e 2427 struct mlx5_dm *dm_db = &to_mdev(ibdm->device)->dm;
24da0016 2428 struct mlx5_ib_dm *dm = to_mdm(ibdm);
24da0016
AL		 2429 u32 page_idx;
2430 int ret;
2431
3b113a1e
AL		 2432 switch (dm->type) {
2433 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2434 ret = mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2435 if (ret)
2436 return ret;
24da0016 2437
3b113a1e
AL		 2438 page_idx = (dm->dev_addr -
2439 pci_resource_start(dm_db->dev->pdev, 0) -
2440 MLX5_CAP64_DEV_MEM(dm_db->dev,
2441 memic_bar_start_addr)) >>
2442 PAGE_SHIFT;
25c13324
AL		 2443 bitmap_clear(ctx->dm_pages, page_idx,
2444 DIV_ROUND_UP(dm->size, PAGE_SIZE));
2445 break;
2446 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2447 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2448 ret = mlx5_cmd_dealloc_sw_icm(dm_db, dm->type, dm->size,
2449 ctx->devx_uid, dm->dev_addr,
2450 dm->icm_dm.obj_id);
2451 if (ret)
2452 return ret;
3b113a1e
AL		 2453 break;
2454 default:
2455 return -EOPNOTSUPP;
2456 }
24da0016
AL		 2457
2458 kfree(dm);
2459
2460 return 0;
2461}
2462
ff23dfa1 2463static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
e126ba97 2464{
21a428a0
LR		 2465 struct mlx5_ib_pd *pd = to_mpd(ibpd);
2466 struct ib_device *ibdev = ibpd->device;
e126ba97 2467 struct mlx5_ib_alloc_pd_resp resp;
e126ba97 2468 int err;
a1069c1c
YH		 2469 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2470 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
2471 u16 uid = 0;
ff23dfa1
SR		 2472 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2473 udata, struct mlx5_ib_ucontext, ibucontext);
e126ba97 2474
ff23dfa1 2475 uid = context ? context->devx_uid : 0;
a1069c1c
YH		 2476 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2477 MLX5_SET(alloc_pd_in, in, uid, uid);
2478 err = mlx5_cmd_exec(to_mdev(ibdev)->mdev, in, sizeof(in),
2479 out, sizeof(out));
21a428a0
LR		 2480 if (err)
2481 return err;
e126ba97 2482
a1069c1c
YH		 2483 pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2484 pd->uid = uid;
ff23dfa1 2485 if (udata) {
e126ba97
EC		 2486 resp.pdn = pd->pdn;
2487 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
a1069c1c 2488 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
21a428a0 2489 return -EFAULT;
e126ba97 2490 }
e126ba97
EC		 2491 }
2492
21a428a0 2493 return 0;
e126ba97
EC		 2494}
2495
c4367a26 2496static void mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
e126ba97
EC		 2497{
2498 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2499 struct mlx5_ib_pd *mpd = to_mpd(pd);
2500
a1069c1c 2501 mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
e126ba97
EC		 2502}
2503
466fa6d2
MG		 2504enum {
2505 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2506 MATCH_CRITERIA_ENABLE_MISC_BIT,
71c6e863
AL		 2507 MATCH_CRITERIA_ENABLE_INNER_BIT,
2508 MATCH_CRITERIA_ENABLE_MISC2_BIT
466fa6d2
MG		 2509};
2510
2511#define HEADER_IS_ZERO(match_criteria, headers) \
2512 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2513 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 2514
466fa6d2 2515static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 2516{
466fa6d2 2517 u8 match_criteria_enable;
038d2ef8 2518
466fa6d2
MG		 2519 match_criteria_enable =
2520 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2521 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2522 match_criteria_enable |=
2523 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2524 MATCH_CRITERIA_ENABLE_MISC_BIT;
2525 match_criteria_enable |=
2526 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2527 MATCH_CRITERIA_ENABLE_INNER_BIT;
71c6e863
AL		 2528 match_criteria_enable |=
2529 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2530 MATCH_CRITERIA_ENABLE_MISC2_BIT;
466fa6d2
MG		 2531
2532 return match_criteria_enable;
038d2ef8
MG		 2533}
2534
6113cc44 2535static int set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
ca0d4753 2536{
6113cc44
MG		 2537 u8 entry_mask;
2538 u8 entry_val;
2539 int err = 0;
2540
2541 if (!mask)
2542 goto out;
2543
2544 entry_mask = MLX5_GET(fte_match_set_lyr_2_4, outer_c,
2545 ip_protocol);
2546 entry_val = MLX5_GET(fte_match_set_lyr_2_4, outer_v,
2547 ip_protocol);
2548 if (!entry_mask) {
2549 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2550 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2551 goto out;
2552 }
2553 /* Don't override existing ip protocol */
2554 if (mask != entry_mask || val != entry_val)
2555 err = -EINVAL;
2556out:
2557 return err;
038d2ef8
MG		 2558}
2559
37da2a03 2560static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2d1e697e
MR		 2561 bool inner)
2562{
2563 if (inner) {
2564 MLX5_SET(fte_match_set_misc,
2565 misc_c, inner_ipv6_flow_label, mask);
2566 MLX5_SET(fte_match_set_misc,
2567 misc_v, inner_ipv6_flow_label, val);
2568 } else {
2569 MLX5_SET(fte_match_set_misc,
2570 misc_c, outer_ipv6_flow_label, mask);
2571 MLX5_SET(fte_match_set_misc,
2572 misc_v, outer_ipv6_flow_label, val);
2573 }
2574}
2575
ca0d4753
MG		 2576static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2577{
2578 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2579 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2580 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2581 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2582}
2583
71c6e863
AL		 2584static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2585{
2586 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2587 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2588 return -EOPNOTSUPP;
2589
2590 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2591 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2592 return -EOPNOTSUPP;
2593
2594 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2595 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2596 return -EOPNOTSUPP;
2597
2598 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2599 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2600 return -EOPNOTSUPP;
2601
2602 return 0;
2603}
2604
c47ac6ae
MG		 2605#define LAST_ETH_FIELD vlan_tag
2606#define LAST_IB_FIELD sl
ca0d4753 2607#define LAST_IPV4_FIELD tos
466fa6d2 2608#define LAST_IPV6_FIELD traffic_class
c47ac6ae 2609#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 2610#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 2611#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 2612#define LAST_DROP_FIELD size
3b3233fb 2613#define LAST_COUNTERS_FIELD counters
c47ac6ae
MG		 2614
2615/* Field is the last supported field */
2616#define FIELDS_NOT_SUPPORTED(filter, field)\
2617 memchr_inv((void *)&filter.field +\
2618 sizeof(filter.field), 0,\
2619 sizeof(filter) -\
2620 offsetof(typeof(filter), field) -\
2621 sizeof(filter.field))
2622
2ea26203
MB		 2623int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
2624 bool is_egress,
2625 struct mlx5_flow_act *action)
802c2125 2626{
802c2125
AY		 2627
2628 switch (maction->ib_action.type) {
2629 case IB_FLOW_ACTION_ESP:
501f14e3
MB		 2630 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2631 MLX5_FLOW_CONTEXT_ACTION_DECRYPT))
2632 return -EINVAL;
802c2125
AY		 2633 /* Currently only AES_GCM keymat is supported by the driver */
2634 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2ea26203 2635 action->action |= is_egress ?
802c2125
AY		 2636 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2637 MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2638 return 0;
b1085be3
MB		 2639 case IB_FLOW_ACTION_UNSPECIFIED:
2640 if (maction->flow_action_raw.sub_type ==
2641 MLX5_IB_FLOW_ACTION_MODIFY_HEADER) {
501f14e3
MB		 2642 if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2643 return -EINVAL;
b1085be3
MB		 2644 action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2645 action->modify_id = maction->flow_action_raw.action_id;
2646 return 0;
2647 }
10a30896
MB		 2648 if (maction->flow_action_raw.sub_type ==
2649 MLX5_IB_FLOW_ACTION_DECAP) {
501f14e3
MB		 2650 if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP)
2651 return -EINVAL;
10a30896
MB		 2652 action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2653 return 0;
2654 }
e806f932
MB		 2655 if (maction->flow_action_raw.sub_type ==
2656 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) {
501f14e3
MB		 2657 if (action->action &
2658 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT)
2659 return -EINVAL;
e806f932
MB		 2660 action->action |=
2661 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
2662 action->reformat_id =
2663 maction->flow_action_raw.action_id;
2664 return 0;
2665 }
b1085be3 2666 /* fall through */
802c2125
AY		 2667 default:
2668 return -EOPNOTSUPP;
2669 }
2670}
2671
bb0ee7dc
JL		 2672static int parse_flow_attr(struct mlx5_core_dev *mdev,
2673 struct mlx5_flow_spec *spec,
2674 const union ib_flow_spec *ib_spec,
802c2125 2675 const struct ib_flow_attr *flow_attr,
71c6e863 2676 struct mlx5_flow_act *action, u32 prev_type)
038d2ef8 2677{
bb0ee7dc
JL		 2678 struct mlx5_flow_context *flow_context = &spec->flow_context;
2679 u32 *match_c = spec->match_criteria;
2680 u32 *match_v = spec->match_value;
466fa6d2
MG		 2681 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2682 misc_parameters);
2683 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2684 misc_parameters);
71c6e863
AL		 2685 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2686 misc_parameters_2);
2687 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2688 misc_parameters_2);
2d1e697e
MR		 2689 void *headers_c;
2690 void *headers_v;
19cc7524 2691 int match_ipv;
802c2125 2692 int ret;
2d1e697e
MR		 2693
2694 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2695 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2696 inner_headers);
2697 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2698 inner_headers);
19cc7524
AL		 2699 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2700 ft_field_support.inner_ip_version);
2d1e697e
MR		 2701 } else {
2702 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2703 outer_headers);
2704 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2705 outer_headers);
19cc7524
AL		 2706 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2707 ft_field_support.outer_ip_version);
2d1e697e 2708 }
466fa6d2 2709
2d1e697e 2710 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 2711 case IB_FLOW_SPEC_ETH:
c47ac6ae 2712 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 2713 return -EOPNOTSUPP;
038d2ef8 2714
2d1e697e 2715 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2716 dmac_47_16),
2717 ib_spec->eth.mask.dst_mac);
2d1e697e 2718 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2719 dmac_47_16),
2720 ib_spec->eth.val.dst_mac);
2721
2d1e697e 2722 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 2723 smac_47_16),
2724 ib_spec->eth.mask.src_mac);
2d1e697e 2725 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 2726 smac_47_16),
2727 ib_spec->eth.val.src_mac);
2728
038d2ef8 2729 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 2730 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 2731 cvlan_tag, 1);
2d1e697e 2732 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 2733 cvlan_tag, 1);
038d2ef8 2734
2d1e697e 2735 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2736 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 2737 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2738 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2739
2d1e697e 2740 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2741 first_cfi,
2742 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 2743 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2744 first_cfi,
2745 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2746
2d1e697e 2747 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2748 first_prio,
2749 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 2750 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2751 first_prio,
2752 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2753 }
2d1e697e 2754 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2755 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 2756 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2757 ethertype, ntohs(ib_spec->eth.val.ether_type));
2758 break;
2759 case IB_FLOW_SPEC_IPV4:
c47ac6ae 2760 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 2761 return -EOPNOTSUPP;
038d2ef8 2762
19cc7524
AL		 2763 if (match_ipv) {
2764 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2765 ip_version, 0xf);
2766 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2767 ip_version, MLX5_FS_IPV4_VERSION);
19cc7524
AL		 2768 } else {
2769 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2770 ethertype, 0xffff);
2771 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2772 ethertype, ETH_P_IP);
2773 }
038d2ef8 2774
2d1e697e 2775 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2776 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2777 &ib_spec->ipv4.mask.src_ip,
2778 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 2779 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2780 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2781 &ib_spec->ipv4.val.src_ip,
2782 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 2783 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2784 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2785 &ib_spec->ipv4.mask.dst_ip,
2786 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 2787 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2788 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2789 &ib_spec->ipv4.val.dst_ip,
2790 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 2791
2d1e697e 2792 set_tos(headers_c, headers_v,
ca0d4753
MG		 2793 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2794
6113cc44
MG		 2795 if (set_proto(headers_c, headers_v,
2796 ib_spec->ipv4.mask.proto,
2797 ib_spec->ipv4.val.proto))
2798 return -EINVAL;
038d2ef8 2799 break;
026bae0c 2800 case IB_FLOW_SPEC_IPV6:
c47ac6ae 2801 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 2802 return -EOPNOTSUPP;
026bae0c 2803
19cc7524
AL		 2804 if (match_ipv) {
2805 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2806 ip_version, 0xf);
2807 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2808 ip_version, MLX5_FS_IPV6_VERSION);
19cc7524
AL		 2809 } else {
2810 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2811 ethertype, 0xffff);
2812 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2813 ethertype, ETH_P_IPV6);
2814 }
026bae0c 2815
2d1e697e 2816 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2817 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2818 &ib_spec->ipv6.mask.src_ip,
2819 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2820 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2821 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2822 &ib_spec->ipv6.val.src_ip,
2823 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2824 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2825 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2826 &ib_spec->ipv6.mask.dst_ip,
2827 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2828 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2829 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2830 &ib_spec->ipv6.val.dst_ip,
2831 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2832
2d1e697e 2833 set_tos(headers_c, headers_v,
466fa6d2
MG		 2834 ib_spec->ipv6.mask.traffic_class,
2835 ib_spec->ipv6.val.traffic_class);
2836
6113cc44
MG		 2837 if (set_proto(headers_c, headers_v,
2838 ib_spec->ipv6.mask.next_hdr,
2839 ib_spec->ipv6.val.next_hdr))
2840 return -EINVAL;
466fa6d2 2841
2d1e697e
MR		 2842 set_flow_label(misc_params_c, misc_params_v,
2843 ntohl(ib_spec->ipv6.mask.flow_label),
2844 ntohl(ib_spec->ipv6.val.flow_label),
2845 ib_spec->type & IB_FLOW_SPEC_INNER);
802c2125
AY		 2846 break;
2847 case IB_FLOW_SPEC_ESP:
2848 if (ib_spec->esp.mask.seq)
2849 return -EOPNOTSUPP;
2d1e697e 2850
802c2125
AY		 2851 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2852 ntohl(ib_spec->esp.mask.spi));
2853 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2854 ntohl(ib_spec->esp.val.spi));
026bae0c 2855 break;
038d2ef8 2856 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2857 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2858 LAST_TCP_UDP_FIELD))
1ffd3a26 2859 return -EOPNOTSUPP;
038d2ef8 2860
6113cc44
MG		 2861 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_TCP))
2862 return -EINVAL;
038d2ef8 2863
2d1e697e 2864 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2865 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2866 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2867 ntohs(ib_spec->tcp_udp.val.src_port));
2868
2d1e697e 2869 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2870 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2871 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2872 ntohs(ib_spec->tcp_udp.val.dst_port));
2873 break;
2874 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2875 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2876 LAST_TCP_UDP_FIELD))
1ffd3a26 2877 return -EOPNOTSUPP;
038d2ef8 2878
6113cc44
MG		 2879 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_UDP))
2880 return -EINVAL;
038d2ef8 2881
2d1e697e 2882 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2883 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2884 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2885 ntohs(ib_spec->tcp_udp.val.src_port));
2886
2d1e697e 2887 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2888 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2889 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2890 ntohs(ib_spec->tcp_udp.val.dst_port));
2891 break;
da2f22ae
AL		 2892 case IB_FLOW_SPEC_GRE:
2893 if (ib_spec->gre.mask.c_ks_res0_ver)
2894 return -EOPNOTSUPP;
2895
6113cc44
MG		 2896 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_GRE))
2897 return -EINVAL;
2898
da2f22ae
AL		 2899 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2900 0xff);
2901 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2902 IPPROTO_GRE);
2903
2904 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
a93b632c 2905 ntohs(ib_spec->gre.mask.protocol));
da2f22ae
AL		 2906 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2907 ntohs(ib_spec->gre.val.protocol));
2908
2909 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
5886a96a 2910 gre_key.nvgre.hi),
da2f22ae
AL		 2911 &ib_spec->gre.mask.key,
2912 sizeof(ib_spec->gre.mask.key));
2913 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
5886a96a 2914 gre_key.nvgre.hi),
da2f22ae
AL		 2915 &ib_spec->gre.val.key,
2916 sizeof(ib_spec->gre.val.key));
2917 break;
71c6e863
AL		 2918 case IB_FLOW_SPEC_MPLS:
2919 switch (prev_type) {
2920 case IB_FLOW_SPEC_UDP:
2921 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2922 ft_field_support.outer_first_mpls_over_udp),
2923 &ib_spec->mpls.mask.tag))
2924 return -EOPNOTSUPP;
2925
2926 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2927 outer_first_mpls_over_udp),
2928 &ib_spec->mpls.val.tag,
2929 sizeof(ib_spec->mpls.val.tag));
2930 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2931 outer_first_mpls_over_udp),
2932 &ib_spec->mpls.mask.tag,
2933 sizeof(ib_spec->mpls.mask.tag));
2934 break;
2935 case IB_FLOW_SPEC_GRE:
2936 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2937 ft_field_support.outer_first_mpls_over_gre),
2938 &ib_spec->mpls.mask.tag))
2939 return -EOPNOTSUPP;
2940
2941 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2942 outer_first_mpls_over_gre),
2943 &ib_spec->mpls.val.tag,
2944 sizeof(ib_spec->mpls.val.tag));
2945 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2946 outer_first_mpls_over_gre),
2947 &ib_spec->mpls.mask.tag,
2948 sizeof(ib_spec->mpls.mask.tag));
2949 break;
2950 default:
2951 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2952 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2953 ft_field_support.inner_first_mpls),
2954 &ib_spec->mpls.mask.tag))
2955 return -EOPNOTSUPP;
2956
2957 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2958 inner_first_mpls),
2959 &ib_spec->mpls.val.tag,
2960 sizeof(ib_spec->mpls.val.tag));
2961 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2962 inner_first_mpls),
2963 &ib_spec->mpls.mask.tag,
2964 sizeof(ib_spec->mpls.mask.tag));
2965 } else {
2966 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2967 ft_field_support.outer_first_mpls),
2968 &ib_spec->mpls.mask.tag))
2969 return -EOPNOTSUPP;
2970
2971 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2972 outer_first_mpls),
2973 &ib_spec->mpls.val.tag,
2974 sizeof(ib_spec->mpls.val.tag));
2975 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2976 outer_first_mpls),
2977 &ib_spec->mpls.mask.tag,
2978 sizeof(ib_spec->mpls.mask.tag));
2979 }
2980 }
2981 break;
ffb30d8f
MR		 2982 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2983 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2984 LAST_TUNNEL_FIELD))
1ffd3a26 2985 return -EOPNOTSUPP;
ffb30d8f
MR		 2986
2987 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2988 ntohl(ib_spec->tunnel.mask.tunnel_id));
2989 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2990 ntohl(ib_spec->tunnel.val.tunnel_id));
2991 break;
2ac693f9
MR		 2992 case IB_FLOW_SPEC_ACTION_TAG:
2993 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2994 LAST_FLOW_TAG_FIELD))
2995 return -EOPNOTSUPP;
2996 if (ib_spec->flow_tag.tag_id >= BIT(24))
2997 return -EINVAL;
2998
bb0ee7dc
JL		 2999 flow_context->flow_tag = ib_spec->flow_tag.tag_id;
3000 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
2ac693f9 3001 break;
a22ed86c
SS		 3002 case IB_FLOW_SPEC_ACTION_DROP:
3003 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
3004 LAST_DROP_FIELD))
3005 return -EOPNOTSUPP;
075572d4 3006 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
a22ed86c 3007 break;
802c2125 3008 case IB_FLOW_SPEC_ACTION_HANDLE:
2ea26203
MB		 3009 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act),
3010 flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action);
802c2125
AY		 3011 if (ret)
3012 return ret;
3013 break;
3b3233fb
RS		 3014 case IB_FLOW_SPEC_ACTION_COUNT:
3015 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
3016 LAST_COUNTERS_FIELD))
3017 return -EOPNOTSUPP;
3018
3019 /* for now support only one counters spec per flow */
3020 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
3021 return -EINVAL;
3022
3023 action->counters = ib_spec->flow_count.counters;
3024 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3025 break;
038d2ef8
MG		 3026 default:
3027 return -EINVAL;
3028 }
3029
3030 return 0;
3031}
3032
3033/* If a flow could catch both multicast and unicast packets,
3034 * it won't fall into the multicast flow steering table and this rule
3035 * could steal other multicast packets.
3036 */
a550ddfc 3037static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
038d2ef8 3038{
81e30880 3039 union ib_flow_spec *flow_spec;
038d2ef8
MG		 3040
3041 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 3042 ib_attr->num_of_specs < 1)
3043 return false;
3044
81e30880
YH		 3045 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
3046 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
3047 struct ib_flow_spec_ipv4 *ipv4_spec;
3048
3049 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
3050 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
3051 return true;
3052
038d2ef8 3053 return false;
81e30880
YH		 3054 }
3055
3056 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
3057 struct ib_flow_spec_eth *eth_spec;
3058
3059 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
3060 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
3061 is_multicast_ether_addr(eth_spec->val.dst_mac);
3062 }
038d2ef8 3063
81e30880 3064 return false;
038d2ef8
MG		 3065}
3066
802c2125
AY		 3067enum valid_spec {
3068 VALID_SPEC_INVALID,
3069 VALID_SPEC_VALID,
3070 VALID_SPEC_NA,
3071};
3072
3073static enum valid_spec
3074is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
3075 const struct mlx5_flow_spec *spec,
3076 const struct mlx5_flow_act *flow_act,
3077 bool egress)
3078{
3079 const u32 *match_c = spec->match_criteria;
3080 bool is_crypto =
3081 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
3082 MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
3083 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
3084 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
3085
3086 /*
3087 * Currently only crypto is supported in egress, when regular egress
3088 * rules would be supported, always return VALID_SPEC_NA.
3089 */
3090 if (!is_crypto)
78dd0c43 3091 return VALID_SPEC_NA;
802c2125
AY		 3092
3093 return is_crypto && is_ipsec &&
bb0ee7dc
JL		 3094 (!egress || (!is_drop &&
3095 !(spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG))) ?
802c2125
AY		 3096 VALID_SPEC_VALID : VALID_SPEC_INVALID;
3097}
3098
3099static bool is_valid_spec(struct mlx5_core_dev *mdev,
3100 const struct mlx5_flow_spec *spec,
3101 const struct mlx5_flow_act *flow_act,
3102 bool egress)
3103{
3104 /* We curretly only support ipsec egress flow */
3105 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
3106}
3107
19cc7524
AL		 3108static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
3109 const struct ib_flow_attr *flow_attr,
0f750966 3110 bool check_inner)
038d2ef8
MG		 3111{
3112 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 3113 int match_ipv = check_inner ?
3114 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3115 ft_field_support.inner_ip_version) :
3116 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3117 ft_field_support.outer_ip_version);
0f750966
AL		 3118 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
3119 bool ipv4_spec_valid, ipv6_spec_valid;
3120 unsigned int ip_spec_type = 0;
3121 bool has_ethertype = false;
038d2ef8 3122 unsigned int spec_index;
0f750966
AL		 3123 bool mask_valid = true;
3124 u16 eth_type = 0;
3125 bool type_valid;
038d2ef8
MG		 3126
3127 /* Validate that ethertype is correct */
3128 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 3129 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 3130 ib_spec->eth.mask.ether_type) {
0f750966
AL		 3131 mask_valid = (ib_spec->eth.mask.ether_type ==
3132 htons(0xffff));
3133 has_ethertype = true;
3134 eth_type = ntohs(ib_spec->eth.val.ether_type);
3135 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
3136 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
3137 ip_spec_type = ib_spec->type;
038d2ef8
MG		 3138 }
3139 ib_spec = (void *)ib_spec + ib_spec->size;
3140 }
0f750966
AL		 3141
3142 type_valid = (!has_ethertype) || (!ip_spec_type);
3143 if (!type_valid && mask_valid) {
3144 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
3145 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
3146 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
3147 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 3148
3149 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
3150 (((eth_type == ETH_P_MPLS_UC) ||
3151 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 3152 }
3153
3154 return type_valid;
3155}
3156
19cc7524
AL		 3157static bool is_valid_attr(struct mlx5_core_dev *mdev,
3158 const struct ib_flow_attr *flow_attr)
0f750966 3159{
19cc7524
AL		 3160 return is_valid_ethertype(mdev, flow_attr, false) &&
3161 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 3162}
3163
3164static void put_flow_table(struct mlx5_ib_dev *dev,
3165 struct mlx5_ib_flow_prio *prio, bool ft_added)
3166{
3167 prio->refcount -= !!ft_added;
3168 if (!prio->refcount) {
3169 mlx5_destroy_flow_table(prio->flow_table);
3170 prio->flow_table = NULL;
3171 }
3172}
3173
3b3233fb
RS		 3174static void counters_clear_description(struct ib_counters *counters)
3175{
3176 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3177
3178 mutex_lock(&mcounters->mcntrs_mutex);
3179 kfree(mcounters->counters_data);
3180 mcounters->counters_data = NULL;
3181 mcounters->cntrs_max_index = 0;
3182 mutex_unlock(&mcounters->mcntrs_mutex);
3183}
3184
038d2ef8
MG		 3185static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
3186{
038d2ef8
MG		 3187 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
3188 struct mlx5_ib_flow_handler,
3189 ibflow);
3190 struct mlx5_ib_flow_handler *iter, *tmp;
d4be3f44 3191 struct mlx5_ib_dev *dev = handler->dev;
038d2ef8 3192
9a4ca38d 3193 mutex_lock(&dev->flow_db->lock);
038d2ef8
MG		 3194
3195 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 3196 mlx5_del_flow_rules(iter->rule);
cc0e5d42 3197 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 3198 list_del(&iter->list);
3199 kfree(iter);
3200 }
3201
74491de9 3202 mlx5_del_flow_rules(handler->rule);
5497adc6 3203 put_flow_table(dev, handler->prio, true);
3b3233fb
RS		 3204 if (handler->ibcounters &&
3205 atomic_read(&handler->ibcounters->usecnt) == 1)
3206 counters_clear_description(handler->ibcounters);
038d2ef8 3207
3b3233fb 3208 mutex_unlock(&dev->flow_db->lock);
d4be3f44
YH		 3209 if (handler->flow_matcher)
3210 atomic_dec(&handler->flow_matcher->usecnt);
038d2ef8
MG		 3211 kfree(handler);
3212
3213 return 0;
3214}
3215
35d19011
MG		 3216static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
3217{
3218 priority *= 2;
3219 if (!dont_trap)
3220 priority++;
3221 return priority;
3222}
3223
cc0e5d42
MG		 3224enum flow_table_type {
3225 MLX5_IB_FT_RX,
3226 MLX5_IB_FT_TX
3227};
3228
00b7c2ab
MG		 3229#define MLX5_FS_MAX_TYPES 6
3230#define MLX5_FS_MAX_ENTRIES BIT(16)
d4be3f44
YH		 3231
3232static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns,
3233 struct mlx5_ib_flow_prio *prio,
3234 int priority,
4adda112
MB		 3235 int num_entries, int num_groups,
3236 u32 flags)
d4be3f44
YH		 3237{
3238 struct mlx5_flow_table *ft;
3239
3240 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3241 num_entries,
3242 num_groups,
4adda112 3243 0, flags);
d4be3f44
YH		 3244 if (IS_ERR(ft))
3245 return ERR_CAST(ft);
3246
3247 prio->flow_table = ft;
3248 prio->refcount = 0;
3249 return prio;
3250}
3251
038d2ef8 3252static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 3253 struct ib_flow_attr *flow_attr,
3254 enum flow_table_type ft_type)
038d2ef8 3255{
35d19011 3256 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 3257 struct mlx5_flow_namespace *ns = NULL;
3258 struct mlx5_ib_flow_prio *prio;
3259 struct mlx5_flow_table *ft;
dac388ef 3260 int max_table_size;
038d2ef8
MG		 3261 int num_entries;
3262 int num_groups;
cecae747 3263 bool esw_encap;
4adda112 3264 u32 flags = 0;
038d2ef8 3265 int priority;
038d2ef8 3266
dac388ef
MG		 3267 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3268 log_max_ft_size));
cecae747
MG		 3269 esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
3270 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
038d2ef8 3271 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
78dd0c43
MB		 3272 enum mlx5_flow_namespace_type fn_type;
3273
3274 if (flow_is_multicast_only(flow_attr) &&
3275 !dont_trap)
038d2ef8
MG		 3276 priority = MLX5_IB_FLOW_MCAST_PRIO;
3277 else
35d19011
MG		 3278 priority = ib_prio_to_core_prio(flow_attr->priority,
3279 dont_trap);
78dd0c43
MB		 3280 if (ft_type == MLX5_IB_FT_RX) {
3281 fn_type = MLX5_FLOW_NAMESPACE_BYPASS;
3282 prio = &dev->flow_db->prios[priority];
cecae747 3283 if (!dev->is_rep && !esw_encap &&
4adda112
MB		 3284 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3285 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
cecae747 3286 if (!dev->is_rep && !esw_encap &&
5c2db53f
MB		 3287 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3288 reformat_l3_tunnel_to_l2))
3289 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
78dd0c43
MB		 3290 } else {
3291 max_table_size =
3292 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3293 log_max_ft_size));
3294 fn_type = MLX5_FLOW_NAMESPACE_EGRESS;
3295 prio = &dev->flow_db->egress_prios[priority];
cecae747 3296 if (!dev->is_rep && !esw_encap &&
4adda112
MB		 3297 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3298 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
78dd0c43
MB		 3299 }
3300 ns = mlx5_get_flow_namespace(dev->mdev, fn_type);
038d2ef8
MG		 3301 num_entries = MLX5_FS_MAX_ENTRIES;
3302 num_groups = MLX5_FS_MAX_TYPES;
038d2ef8
MG		 3303 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3304 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3305 ns = mlx5_get_flow_namespace(dev->mdev,
3306 MLX5_FLOW_NAMESPACE_LEFTOVERS);
3307 build_leftovers_ft_param(&priority,
3308 &num_entries,
3309 &num_groups);
9a4ca38d 3310 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 3311 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3312 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3313 allow_sniffer_and_nic_rx_shared_tir))
3314 return ERR_PTR(-ENOTSUPP);
3315
3316 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3317 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3318 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3319
9a4ca38d 3320 prio = &dev->flow_db->sniffer[ft_type];
cc0e5d42
MG		 3321 priority = 0;
3322 num_entries = 1;
3323 num_groups = 1;
038d2ef8
MG		 3324 }
3325
3326 if (!ns)
3327 return ERR_PTR(-ENOTSUPP);
3328
3b70508a 3329 max_table_size = min_t(int, num_entries, max_table_size);
dac388ef 3330
038d2ef8 3331 ft = prio->flow_table;
d4be3f44 3332 if (!ft)
3b70508a 3333 return _get_prio(ns, prio, priority, max_table_size, num_groups,
4adda112 3334 flags);
038d2ef8 3335
d4be3f44 3336 return prio;
038d2ef8
MG		 3337}
3338
a550ddfc
YH		 3339static void set_underlay_qp(struct mlx5_ib_dev *dev,
3340 struct mlx5_flow_spec *spec,
3341 u32 underlay_qpn)
3342{
3343 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3344 spec->match_criteria,
3345 misc_parameters);
3346 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3347 misc_parameters);
3348
3349 if (underlay_qpn &&
3350 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3351 ft_field_support.bth_dst_qp)) {
3352 MLX5_SET(fte_match_set_misc,
3353 misc_params_v, bth_dst_qp, underlay_qpn);
3354 MLX5_SET(fte_match_set_misc,
3355 misc_params_c, bth_dst_qp, 0xffffff);
3356 }
3357}
3358
5e95af5f
RS		 3359static int read_flow_counters(struct ib_device *ibdev,
3360 struct mlx5_read_counters_attr *read_attr)
3361{
3362 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3363 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3364
3365 return mlx5_fc_query(dev->mdev, fc,
3366 &read_attr->out[IB_COUNTER_PACKETS],
3367 &read_attr->out[IB_COUNTER_BYTES]);
3368}
3369
3370/* flow counters currently expose two counters packets and bytes */
3371#define FLOW_COUNTERS_NUM 2
3b3233fb
RS		 3372static int counters_set_description(struct ib_counters *counters,
3373 enum mlx5_ib_counters_type counters_type,
3374 struct mlx5_ib_flow_counters_desc *desc_data,
3375 u32 ncounters)
3376{
3377 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3378 u32 cntrs_max_index = 0;
3379 int i;
3380
3381 if (counters_type != MLX5_IB_COUNTERS_FLOW)
3382 return -EINVAL;
3383
3384 /* init the fields for the object */
3385 mcounters->type = counters_type;
5e95af5f
RS		 3386 mcounters->read_counters = read_flow_counters;
3387 mcounters->counters_num = FLOW_COUNTERS_NUM;
3b3233fb
RS		 3388 mcounters->ncounters = ncounters;
3389 /* each counter entry have both description and index pair */
3390 for (i = 0; i < ncounters; i++) {
3391 if (desc_data[i].description > IB_COUNTER_BYTES)
3392 return -EINVAL;
3393
3394 if (cntrs_max_index <= desc_data[i].index)
3395 cntrs_max_index = desc_data[i].index + 1;
3396 }
3397
3398 mutex_lock(&mcounters->mcntrs_mutex);
3399 mcounters->counters_data = desc_data;
3400 mcounters->cntrs_max_index = cntrs_max_index;
3401 mutex_unlock(&mcounters->mcntrs_mutex);
3402
3403 return 0;
3404}
3405
3406#define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3407static int flow_counters_set_data(struct ib_counters *ibcounters,
3408 struct mlx5_ib_create_flow *ucmd)
3409{
3410 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3411 struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3412 struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3413 bool hw_hndl = false;
3414 int ret = 0;
3415
3416 if (ucmd && ucmd->ncounters_data != 0) {
3417 cntrs_data = ucmd->data;
3418 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3419 return -EINVAL;
3420
3421 desc_data = kcalloc(cntrs_data->ncounters,
3422 sizeof(*desc_data),
3423 GFP_KERNEL);
3424 if (!desc_data)
3425 return -ENOMEM;
3426
3427 if (copy_from_user(desc_data,
3428 u64_to_user_ptr(cntrs_data->counters_data),
3429 sizeof(*desc_data) * cntrs_data->ncounters)) {
3430 ret = -EFAULT;
3431 goto free;
3432 }
3433 }
3434
3435 if (!mcounters->hw_cntrs_hndl) {
3436 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3437 to_mdev(ibcounters->device)->mdev, false);
e31abf76 3438 if (IS_ERR(mcounters->hw_cntrs_hndl)) {
3439 ret = PTR_ERR(mcounters->hw_cntrs_hndl);
3b3233fb
RS		 3440 goto free;
3441 }
3442 hw_hndl = true;
3443 }
3444
3445 if (desc_data) {
3446 /* counters already bound to at least one flow */
3447 if (mcounters->cntrs_max_index) {
3448 ret = -EINVAL;
3449 goto free_hndl;
3450 }
3451
3452 ret = counters_set_description(ibcounters,
3453 MLX5_IB_COUNTERS_FLOW,
3454 desc_data,
3455 cntrs_data->ncounters);
3456 if (ret)
3457 goto free_hndl;
3458
3459 } else if (!mcounters->cntrs_max_index) {
3460 /* counters not bound yet, must have udata passed */
3461 ret = -EINVAL;
3462 goto free_hndl;
3463 }
3464
3465 return 0;
3466
3467free_hndl:
3468 if (hw_hndl) {
3469 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3470 mcounters->hw_cntrs_hndl);
3471 mcounters->hw_cntrs_hndl = NULL;
3472 }
3473free:
3474 kfree(desc_data);
3475 return ret;
3476}
3477
669ff1e3
JL		 3478static void mlx5_ib_set_rule_source_port(struct mlx5_ib_dev *dev,
3479 struct mlx5_flow_spec *spec,
3480 struct mlx5_eswitch_rep *rep)
3481{
3482 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
3483 void *misc;
3484
3485 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
3486 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3487 misc_parameters_2);
3488
3489 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
3490 mlx5_eswitch_get_vport_metadata_for_match(esw,
3491 rep->vport));
3492 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3493 misc_parameters_2);
3494
3495 MLX5_SET_TO_ONES(fte_match_set_misc2, misc, metadata_reg_c_0);
3496 } else {
3497 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3498 misc_parameters);
3499
3500 MLX5_SET(fte_match_set_misc, misc, source_port, rep->vport);
3501
3502 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3503 misc_parameters);
3504
3505 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3506 }
3507}
3508
a550ddfc
YH		 3509static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3510 struct mlx5_ib_flow_prio *ft_prio,
3511 const struct ib_flow_attr *flow_attr,
3512 struct mlx5_flow_destination *dst,
3b3233fb
RS		 3513 u32 underlay_qpn,
3514 struct mlx5_ib_create_flow *ucmd)
038d2ef8
MG		 3515{
3516 struct mlx5_flow_table *ft = ft_prio->flow_table;
3517 struct mlx5_ib_flow_handler *handler;
bb0ee7dc 3518 struct mlx5_flow_act flow_act = {};
c5bb1730 3519 struct mlx5_flow_spec *spec;
3b3233fb
RS		 3520 struct mlx5_flow_destination dest_arr[2] = {};
3521 struct mlx5_flow_destination *rule_dst = dest_arr;
dd063d0e 3522 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 3523 unsigned int spec_index;
71c6e863 3524 u32 prev_type = 0;
038d2ef8 3525 int err = 0;
3b3233fb 3526 int dest_num = 0;
802c2125 3527 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
038d2ef8 3528
19cc7524 3529 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 3530 return ERR_PTR(-EINVAL);
3531
6a4d00be 3532 if (dev->is_rep && is_egress)
78dd0c43
MB		 3533 return ERR_PTR(-EINVAL);
3534
1b9a07ee 3535 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 3536 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 3537 if (!handler || !spec) {
038d2ef8
MG		 3538 err = -ENOMEM;
3539 goto free;
3540 }
3541
3542 INIT_LIST_HEAD(&handler->list);
3b3233fb
RS		 3543 if (dst) {
3544 memcpy(&dest_arr[0], dst, sizeof(*dst));
3545 dest_num++;
3546 }
038d2ef8
MG		 3547
3548 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
bb0ee7dc 3549 err = parse_flow_attr(dev->mdev, spec,
71c6e863
AL		 3550 ib_flow, flow_attr, &flow_act,
3551 prev_type);
038d2ef8
MG		 3552 if (err < 0)
3553 goto free;
3554
71c6e863 3555 prev_type = ((union ib_flow_spec *)ib_flow)->type;
038d2ef8
MG		 3556 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3557 }
3558
a550ddfc
YH		 3559 if (!flow_is_multicast_only(flow_attr))
3560 set_underlay_qp(dev, spec, underlay_qpn);
3561
6a4d00be 3562 if (dev->is_rep) {
669ff1e3 3563 struct mlx5_eswitch_rep *rep;
018a94ee 3564
669ff1e3
JL		 3565 rep = dev->port[flow_attr->port - 1].rep;
3566 if (!rep) {
6a4d00be
MB		 3567 err = -EINVAL;
3568 goto free;
3569 }
669ff1e3
JL		 3570
3571 mlx5_ib_set_rule_source_port(dev, spec, rep);
018a94ee
MB		 3572 }
3573
466fa6d2 3574 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
802c2125
AY		 3575
3576 if (is_egress &&
3577 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3578 err = -EINVAL;
3579 goto free;
3580 }
3581
3b3233fb 3582 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
171c7625
MB		 3583 struct mlx5_ib_mcounters *mcounters;
3584
3b3233fb
RS		 3585 err = flow_counters_set_data(flow_act.counters, ucmd);
3586 if (err)
3587 goto free;
3588
171c7625 3589 mcounters = to_mcounters(flow_act.counters);
3b3233fb
RS		 3590 handler->ibcounters = flow_act.counters;
3591 dest_arr[dest_num].type =
3592 MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625
MB		 3593 dest_arr[dest_num].counter_id =
3594 mlx5_fc_id(mcounters->hw_cntrs_hndl);
3b3233fb
RS		 3595 dest_num++;
3596 }
3597
075572d4 3598 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3b3233fb
RS		 3599 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) {
3600 rule_dst = NULL;
3601 dest_num = 0;
3602 }
a22ed86c 3603 } else {
802c2125
AY		 3604 if (is_egress)
3605 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3606 else
3607 flow_act.action |=
3b3233fb 3608 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
802c2125 3609 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
a22ed86c 3610 }
2ac693f9 3611
bb0ee7dc 3612 if ((spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG) &&
2ac693f9
MR		 3613 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3614 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3615 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
bb0ee7dc 3616 spec->flow_context.flow_tag, flow_attr->type);
2ac693f9
MR		 3617 err = -EINVAL;
3618 goto free;
3619 }
74491de9 3620 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 3621 &flow_act,
a22ed86c 3622 rule_dst, dest_num);
038d2ef8
MG		 3623
3624 if (IS_ERR(handler->rule)) {
3625 err = PTR_ERR(handler->rule);
3626 goto free;
3627 }
3628
d9d4980a 3629 ft_prio->refcount++;
5497adc6 3630 handler->prio = ft_prio;
d4be3f44 3631 handler->dev = dev;
038d2ef8
MG		 3632
3633 ft_prio->flow_table = ft;
3634free:
3b3233fb
RS		 3635 if (err && handler) {
3636 if (handler->ibcounters &&
3637 atomic_read(&handler->ibcounters->usecnt) == 1)
3638 counters_clear_description(handler->ibcounters);
038d2ef8 3639 kfree(handler);
3b3233fb 3640 }
c5bb1730 3641 kvfree(spec);
038d2ef8
MG		 3642 return err ? ERR_PTR(err) : handler;
3643}
3644
a550ddfc
YH		 3645static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3646 struct mlx5_ib_flow_prio *ft_prio,
3647 const struct ib_flow_attr *flow_attr,
3648 struct mlx5_flow_destination *dst)
3649{
3b3233fb 3650 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
a550ddfc
YH		 3651}
3652
35d19011
MG		 3653static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3654 struct mlx5_ib_flow_prio *ft_prio,
3655 struct ib_flow_attr *flow_attr,
3656 struct mlx5_flow_destination *dst)
3657{
3658 struct mlx5_ib_flow_handler *handler_dst = NULL;
3659 struct mlx5_ib_flow_handler *handler = NULL;
3660
3661 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3662 if (!IS_ERR(handler)) {
3663 handler_dst = create_flow_rule(dev, ft_prio,
3664 flow_attr, dst);
3665 if (IS_ERR(handler_dst)) {
74491de9 3666 mlx5_del_flow_rules(handler->rule);
d9d4980a 3667 ft_prio->refcount--;
35d19011
MG		 3668 kfree(handler);
3669 handler = handler_dst;
3670 } else {
3671 list_add(&handler_dst->list, &handler->list);
3672 }
3673 }
3674
3675 return handler;
3676}
038d2ef8
MG		 3677enum {
3678 LEFTOVERS_MC,
3679 LEFTOVERS_UC,
3680};
3681
3682static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3683 struct mlx5_ib_flow_prio *ft_prio,
3684 struct ib_flow_attr *flow_attr,
3685 struct mlx5_flow_destination *dst)
3686{
3687 struct mlx5_ib_flow_handler *handler_ucast = NULL;
3688 struct mlx5_ib_flow_handler *handler = NULL;
3689
3690 static struct {
3691 struct ib_flow_attr flow_attr;
3692 struct ib_flow_spec_eth eth_flow;
3693 } leftovers_specs[] = {
3694 [LEFTOVERS_MC] = {
3695 .flow_attr = {
3696 .num_of_specs = 1,
3697 .size = sizeof(leftovers_specs[0])
3698 },
3699 .eth_flow = {
3700 .type = IB_FLOW_SPEC_ETH,
3701 .size = sizeof(struct ib_flow_spec_eth),
3702 .mask = {.dst_mac = {0x1} },
3703 .val = {.dst_mac = {0x1} }
3704 }
3705 },
3706 [LEFTOVERS_UC] = {
3707 .flow_attr = {
3708 .num_of_specs = 1,
3709 .size = sizeof(leftovers_specs[0])
3710 },
3711 .eth_flow = {
3712 .type = IB_FLOW_SPEC_ETH,
3713 .size = sizeof(struct ib_flow_spec_eth),
3714 .mask = {.dst_mac = {0x1} },
3715 .val = {.dst_mac = {} }
3716 }
3717 }
3718 };
3719
3720 handler = create_flow_rule(dev, ft_prio,
3721 &leftovers_specs[LEFTOVERS_MC].flow_attr,
3722 dst);
3723 if (!IS_ERR(handler) &&
3724 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3725 handler_ucast = create_flow_rule(dev, ft_prio,
3726 &leftovers_specs[LEFTOVERS_UC].flow_attr,
3727 dst);
3728 if (IS_ERR(handler_ucast)) {
74491de9 3729 mlx5_del_flow_rules(handler->rule);
d9d4980a 3730 ft_prio->refcount--;
038d2ef8
MG		 3731 kfree(handler);
3732 handler = handler_ucast;
3733 } else {
3734 list_add(&handler_ucast->list, &handler->list);
3735 }
3736 }
3737
3738 return handler;
3739}
3740
cc0e5d42
MG		 3741static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3742 struct mlx5_ib_flow_prio *ft_rx,
3743 struct mlx5_ib_flow_prio *ft_tx,
3744 struct mlx5_flow_destination *dst)
3745{
3746 struct mlx5_ib_flow_handler *handler_rx;
3747 struct mlx5_ib_flow_handler *handler_tx;
3748 int err;
3749 static const struct ib_flow_attr flow_attr = {
3750 .num_of_specs = 0,
3751 .size = sizeof(flow_attr)
3752 };
3753
3754 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3755 if (IS_ERR(handler_rx)) {
3756 err = PTR_ERR(handler_rx);
3757 goto err;
3758 }
3759
3760 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3761 if (IS_ERR(handler_tx)) {
3762 err = PTR_ERR(handler_tx);
3763 goto err_tx;
3764 }
3765
3766 list_add(&handler_tx->list, &handler_rx->list);
3767
3768 return handler_rx;
3769
3770err_tx:
74491de9 3771 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 3772 ft_rx->refcount--;
3773 kfree(handler_rx);
3774err:
3775 return ERR_PTR(err);
3776}
3777
038d2ef8
MG		 3778static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3779 struct ib_flow_attr *flow_attr,
59082a32
MB		 3780 int domain,
3781 struct ib_udata *udata)
038d2ef8
MG		 3782{
3783 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 3784 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 3785 struct mlx5_ib_flow_handler *handler = NULL;
3786 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 3787 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8 3788 struct mlx5_ib_flow_prio *ft_prio;
802c2125 3789 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3b3233fb
RS		 3790 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3791 size_t min_ucmd_sz, required_ucmd_sz;
038d2ef8 3792 int err;
a550ddfc 3793 int underlay_qpn;
038d2ef8 3794
3b3233fb
RS		 3795 if (udata && udata->inlen) {
3796 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3797 sizeof(ucmd_hdr.reserved);
3798 if (udata->inlen < min_ucmd_sz)
3799 return ERR_PTR(-EOPNOTSUPP);
3800
3801 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3802 if (err)
3803 return ERR_PTR(err);
3804
3805 /* currently supports only one counters data */
3806 if (ucmd_hdr.ncounters_data > 1)
3807 return ERR_PTR(-EINVAL);
3808
3809 required_ucmd_sz = min_ucmd_sz +
3810 sizeof(struct mlx5_ib_flow_counters_data) *
3811 ucmd_hdr.ncounters_data;
3812 if (udata->inlen > required_ucmd_sz &&
3813 !ib_is_udata_cleared(udata, required_ucmd_sz,
3814 udata->inlen - required_ucmd_sz))
3815 return ERR_PTR(-EOPNOTSUPP);
3816
3817 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3818 if (!ucmd)
3819 return ERR_PTR(-ENOMEM);
3820
3821 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
299eafee
GS		 3822 if (err)
3823 goto free_ucmd;
3b3233fb 3824 }
59082a32 3825
299eafee
GS		 3826 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) {
3827 err = -ENOMEM;
3828 goto free_ucmd;
3829 }
038d2ef8
MG		 3830
3831 if (domain != IB_FLOW_DOMAIN_USER ||
508562d6 3832 flow_attr->port > dev->num_ports ||
802c2125 3833 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
299eafee
GS		 3834 IB_FLOW_ATTR_FLAGS_EGRESS))) {
3835 err = -EINVAL;
3836 goto free_ucmd;
3837 }
802c2125
AY		 3838
3839 if (is_egress &&
3840 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
299eafee
GS		 3841 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3842 err = -EINVAL;
3843 goto free_ucmd;
3844 }
038d2ef8
MG		 3845
3846 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
299eafee
GS		 3847 if (!dst) {
3848 err = -ENOMEM;
3849 goto free_ucmd;
3850 }
038d2ef8 3851
9a4ca38d 3852 mutex_lock(&dev->flow_db->lock);
038d2ef8 3853
802c2125
AY		 3854 ft_prio = get_flow_table(dev, flow_attr,
3855 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
038d2ef8
MG		 3856 if (IS_ERR(ft_prio)) {
3857 err = PTR_ERR(ft_prio);
3858 goto unlock;
3859 }
cc0e5d42
MG		 3860 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3861 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3862 if (IS_ERR(ft_prio_tx)) {
3863 err = PTR_ERR(ft_prio_tx);
3864 ft_prio_tx = NULL;
3865 goto destroy_ft;
3866 }
3867 }
038d2ef8 3868
802c2125
AY		 3869 if (is_egress) {
3870 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3871 } else {
3872 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3873 if (mqp->flags & MLX5_IB_QP_RSS)
3874 dst->tir_num = mqp->rss_qp.tirn;
3875 else
3876 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3877 }
038d2ef8
MG		 3878
3879 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 3880 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3881 handler = create_dont_trap_rule(dev, ft_prio,
3882 flow_attr, dst);
3883 } else {
a550ddfc
YH		 3884 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3885 mqp->underlay_qpn : 0;
3886 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3b3233fb 3887 dst, underlay_qpn, ucmd);
35d19011 3888 }
038d2ef8
MG		 3889 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3890 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3891 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3892 dst);
cc0e5d42
MG		 3893 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3894 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 3895 } else {
3896 err = -EINVAL;
3897 goto destroy_ft;
3898 }
3899
3900 if (IS_ERR(handler)) {
3901 err = PTR_ERR(handler);
3902 handler = NULL;
3903 goto destroy_ft;
3904 }
3905
9a4ca38d 3906 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3907 kfree(dst);
3b3233fb 3908 kfree(ucmd);
038d2ef8
MG		 3909
3910 return &handler->ibflow;
3911
3912destroy_ft:
3913 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 3914 if (ft_prio_tx)
3915 put_flow_table(dev, ft_prio_tx, false);
038d2ef8 3916unlock:
9a4ca38d 3917 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3918 kfree(dst);
299eafee 3919free_ucmd:
3b3233fb 3920 kfree(ucmd);
038d2ef8
MG		 3921 return ERR_PTR(err);
3922}
3923
b47fd4ff
MB		 3924static struct mlx5_ib_flow_prio *
3925_get_flow_table(struct mlx5_ib_dev *dev,
3926 struct mlx5_ib_flow_matcher *fs_matcher,
3927 bool mcast)
d4be3f44 3928{
d4be3f44 3929 struct mlx5_flow_namespace *ns = NULL;
13a43765
MB		 3930 struct mlx5_ib_flow_prio *prio = NULL;
3931 int max_table_size = 0;
cecae747 3932 bool esw_encap;
b47fd4ff
MB		 3933 u32 flags = 0;
3934 int priority;
3935
13a43765
MB		 3936 if (mcast)
3937 priority = MLX5_IB_FLOW_MCAST_PRIO;
3938 else
3939 priority = ib_prio_to_core_prio(fs_matcher->priority, false);
3940
cecae747
MG		 3941 esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
3942 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
b47fd4ff
MB		 3943 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) {
3944 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3945 log_max_ft_size));
cecae747 3946 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap) && !esw_encap)
b47fd4ff
MB		 3947 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3948 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
cecae747
MG		 3949 reformat_l3_tunnel_to_l2) &&
3950 !esw_encap)
b47fd4ff 3951 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
13a43765
MB		 3952 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS) {
3953 max_table_size = BIT(
3954 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, log_max_ft_size));
cecae747 3955 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat) && !esw_encap)
b47fd4ff 3956 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
13a43765
MB		 3957 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB) {
3958 max_table_size = BIT(
3959 MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, log_max_ft_size));
09d985be
MG		 3960 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, decap) && esw_encap)
3961 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3962 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, reformat_l3_tunnel_to_l2) &&
3963 esw_encap)
3964 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
13a43765 3965 priority = FDB_BYPASS_PATH;
d8abe884
MZ		 3966 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_RDMA_RX) {
3967 max_table_size =
3968 BIT(MLX5_CAP_FLOWTABLE_RDMA_RX(dev->mdev,
3969 log_max_ft_size));
3970 priority = fs_matcher->priority;
b47fd4ff 3971 }
d4be3f44 3972
3b70508a 3973 max_table_size = min_t(int, max_table_size, MLX5_FS_MAX_ENTRIES);
d4be3f44 3974
b47fd4ff 3975 ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type);
d4be3f44
YH		 3976 if (!ns)
3977 return ERR_PTR(-ENOTSUPP);
3978
b47fd4ff
MB		 3979 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS)
3980 prio = &dev->flow_db->prios[priority];
13a43765 3981 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS)
b47fd4ff 3982 prio = &dev->flow_db->egress_prios[priority];
13a43765
MB		 3983 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB)
3984 prio = &dev->flow_db->fdb;
d8abe884
MZ		 3985 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_RDMA_RX)
3986 prio = &dev->flow_db->rdma_rx[priority];
13a43765
MB		 3987
3988 if (!prio)
3989 return ERR_PTR(-EINVAL);
d4be3f44
YH		 3990
3991 if (prio->flow_table)
3992 return prio;
3993
3b70508a 3994 return _get_prio(ns, prio, priority, max_table_size,
b47fd4ff 3995 MLX5_FS_MAX_TYPES, flags);
d4be3f44
YH		 3996}
3997
3998static struct mlx5_ib_flow_handler *
3999_create_raw_flow_rule(struct mlx5_ib_dev *dev,
4000 struct mlx5_ib_flow_prio *ft_prio,
4001 struct mlx5_flow_destination *dst,
4002 struct mlx5_ib_flow_matcher *fs_matcher,
bb0ee7dc 4003 struct mlx5_flow_context *flow_context,
b823dd6d 4004 struct mlx5_flow_act *flow_act,
bfc5d839
MB		 4005 void *cmd_in, int inlen,
4006 int dst_num)
d4be3f44
YH		 4007{
4008 struct mlx5_ib_flow_handler *handler;
d4be3f44
YH		 4009 struct mlx5_flow_spec *spec;
4010 struct mlx5_flow_table *ft = ft_prio->flow_table;
4011 int err = 0;
4012
4013 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
4014 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
4015 if (!handler || !spec) {
4016 err = -ENOMEM;
4017 goto free;
4018 }
4019
4020 INIT_LIST_HEAD(&handler->list);
4021
4022 memcpy(spec->match_value, cmd_in, inlen);
4023 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params,
4024 fs_matcher->mask_len);
4025 spec->match_criteria_enable = fs_matcher->match_criteria_enable;
bb0ee7dc 4026 spec->flow_context = *flow_context;
d4be3f44 4027
d4be3f44 4028 handler->rule = mlx5_add_flow_rules(ft, spec,
bfc5d839 4029 flow_act, dst, dst_num);
d4be3f44
YH		 4030
4031 if (IS_ERR(handler->rule)) {
4032 err = PTR_ERR(handler->rule);
4033 goto free;
4034 }
4035
4036 ft_prio->refcount++;
4037 handler->prio = ft_prio;
4038 handler->dev = dev;
4039 ft_prio->flow_table = ft;
4040
4041free:
4042 if (err)
4043 kfree(handler);
4044 kvfree(spec);
4045 return err ? ERR_PTR(err) : handler;
4046}
4047
4048static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher,
4049 void *match_v)
4050{
4051 void *match_c;
4052 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4;
4053 void *dmac, *dmac_mask;
4054 void *ipv4, *ipv4_mask;
4055
4056 if (!(fs_matcher->match_criteria_enable &
4057 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT)))
4058 return false;
4059
4060 match_c = fs_matcher->matcher_mask.match_params;
4061 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v,
4062 outer_headers);
4063 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c,
4064 outer_headers);
4065
4066 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4067 dmac_47_16);
4068 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4069 dmac_47_16);
4070
4071 if (is_multicast_ether_addr(dmac) &&
4072 is_multicast_ether_addr(dmac_mask))
4073 return true;
4074
4075 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4076 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4077
4078 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4079 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4080
4081 if (ipv4_is_multicast(*(__be32 *)(ipv4)) &&
4082 ipv4_is_multicast(*(__be32 *)(ipv4_mask)))
4083 return true;
4084
4085 return false;
4086}
4087
32269441
YH		 4088struct mlx5_ib_flow_handler *
4089mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
4090 struct mlx5_ib_flow_matcher *fs_matcher,
bb0ee7dc 4091 struct mlx5_flow_context *flow_context,
b823dd6d 4092 struct mlx5_flow_act *flow_act,
bfc5d839 4093 u32 counter_id,
32269441
YH		 4094 void *cmd_in, int inlen, int dest_id,
4095 int dest_type)
4096{
d4be3f44
YH		 4097 struct mlx5_flow_destination *dst;
4098 struct mlx5_ib_flow_prio *ft_prio;
d4be3f44 4099 struct mlx5_ib_flow_handler *handler;
bfc5d839 4100 int dst_num = 0;
d4be3f44
YH		 4101 bool mcast;
4102 int err;
4103
4104 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL)
4105 return ERR_PTR(-EOPNOTSUPP);
4106
4107 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO)
4108 return ERR_PTR(-ENOMEM);
4109
8e8aa145 4110 dst = kcalloc(2, sizeof(*dst), GFP_KERNEL);
d4be3f44
YH		 4111 if (!dst)
4112 return ERR_PTR(-ENOMEM);
4113
4114 mcast = raw_fs_is_multicast(fs_matcher, cmd_in);
4115 mutex_lock(&dev->flow_db->lock);
4116
b47fd4ff 4117 ft_prio = _get_flow_table(dev, fs_matcher, mcast);
d4be3f44
YH		 4118 if (IS_ERR(ft_prio)) {
4119 err = PTR_ERR(ft_prio);
4120 goto unlock;
4121 }
4122
6346f0bf 4123 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
bfc5d839
MB		 4124 dst[dst_num].type = dest_type;
4125 dst[dst_num].tir_num = dest_id;
b823dd6d 4126 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
a7ee18bd 4127 } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) {
bfc5d839
MB		 4128 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
4129 dst[dst_num].ft_num = dest_id;
b823dd6d 4130 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
a7ee18bd 4131 } else {
bfc5d839 4132 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_PORT;
a7ee18bd 4133 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
6346f0bf
YH		 4134 }
4135
bfc5d839
MB		 4136 dst_num++;
4137
4138 if (flow_act->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
4139 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
4140 dst[dst_num].counter_id = counter_id;
4141 dst_num++;
4142 }
4143
bb0ee7dc
JL		 4144 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher,
4145 flow_context, flow_act,
bfc5d839 4146 cmd_in, inlen, dst_num);
d4be3f44
YH		 4147
4148 if (IS_ERR(handler)) {
4149 err = PTR_ERR(handler);
4150 goto destroy_ft;
4151 }
4152
4153 mutex_unlock(&dev->flow_db->lock);
4154 atomic_inc(&fs_matcher->usecnt);
4155 handler->flow_matcher = fs_matcher;
4156
4157 kfree(dst);
4158
4159 return handler;
4160
4161destroy_ft:
4162 put_flow_table(dev, ft_prio, false);
4163unlock:
4164 mutex_unlock(&dev->flow_db->lock);
4165 kfree(dst);
4166
4167 return ERR_PTR(err);
32269441
YH		 4168}
4169
c6475a0b
AY		 4170static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
4171{
4172 u32 flags = 0;
4173
4174 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
4175 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
4176
4177 return flags;
4178}
4179
4180#define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
4181static struct ib_flow_action *
4182mlx5_ib_create_flow_action_esp(struct ib_device *device,
4183 const struct ib_flow_action_attrs_esp *attr,
4184 struct uverbs_attr_bundle *attrs)
4185{
4186 struct mlx5_ib_dev *mdev = to_mdev(device);
4187 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
4188 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
4189 struct mlx5_ib_flow_action *action;
4190 u64 action_flags;
4191 u64 flags;
4192 int err = 0;
4193
bccd0622
JG		 4194 err = uverbs_get_flags64(
4195 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
4196 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1));
4197 if (err)
4198 return ERR_PTR(err);
c6475a0b
AY		 4199
4200 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
4201
4202 /* We current only support a subset of the standard features. Only a
4203 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
4204 * (with overlap). Full offload mode isn't supported.
4205 */
4206 if (!attr->keymat || attr->replay || attr->encap ||
4207 attr->spi || attr->seq || attr->tfc_pad ||
4208 attr->hard_limit_pkts ||
4209 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4210 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
4211 return ERR_PTR(-EOPNOTSUPP);
4212
4213 if (attr->keymat->protocol !=
4214 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
4215 return ERR_PTR(-EOPNOTSUPP);
4216
4217 aes_gcm = &attr->keymat->keymat.aes_gcm;
4218
4219 if (aes_gcm->icv_len != 16 ||
4220 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
4221 return ERR_PTR(-EOPNOTSUPP);
4222
4223 action = kmalloc(sizeof(*action), GFP_KERNEL);
4224 if (!action)
4225 return ERR_PTR(-ENOMEM);
4226
4227 action->esp_aes_gcm.ib_flags = attr->flags;
4228 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
4229 sizeof(accel_attrs.keymat.aes_gcm.aes_key));
4230 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
4231 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
4232 sizeof(accel_attrs.keymat.aes_gcm.salt));
4233 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
4234 sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
4235 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
4236 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
4237 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
4238
4239 accel_attrs.esn = attr->esn;
4240 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
4241 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
4242 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4243 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4244
4245 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
4246 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
4247
4248 action->esp_aes_gcm.ctx =
4249 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
4250 if (IS_ERR(action->esp_aes_gcm.ctx)) {
4251 err = PTR_ERR(action->esp_aes_gcm.ctx);
4252 goto err_parse;
4253 }
4254
4255 action->esp_aes_gcm.ib_flags = attr->flags;
4256
4257 return &action->ib_action;
4258
4259err_parse:
4260 kfree(action);
4261 return ERR_PTR(err);
4262}
4263
349705c1
MB		 4264static int
4265mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
4266 const struct ib_flow_action_attrs_esp *attr,
4267 struct uverbs_attr_bundle *attrs)
4268{
4269 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4270 struct mlx5_accel_esp_xfrm_attrs accel_attrs;
4271 int err = 0;
4272
4273 if (attr->keymat || attr->replay || attr->encap ||
4274 attr->spi || attr->seq || attr->tfc_pad ||
4275 attr->hard_limit_pkts ||
4276 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4277 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
4278 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
4279 return -EOPNOTSUPP;
4280
4281 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
4282 * be modified.
4283 */
4284 if (!(maction->esp_aes_gcm.ib_flags &
4285 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
4286 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4287 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
4288 return -EINVAL;
4289
4290 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
4291 sizeof(accel_attrs));
4292
4293 accel_attrs.esn = attr->esn;
4294 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4295 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4296 else
4297 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4298
4299 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
4300 &accel_attrs);
4301 if (err)
4302 return err;
4303
4304 maction->esp_aes_gcm.ib_flags &=
4305 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4306 maction->esp_aes_gcm.ib_flags |=
4307 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4308
4309 return 0;
4310}
4311
c6475a0b
AY		 4312static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
4313{
4314 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4315
4316 switch (action->type) {
4317 case IB_FLOW_ACTION_ESP:
4318 /*
4319 * We only support aes_gcm by now, so we implicitly know this is
4320 * the underline crypto.
4321 */
4322 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
4323 break;
b4749bf2
MB		 4324 case IB_FLOW_ACTION_UNSPECIFIED:
4325 mlx5_ib_destroy_flow_action_raw(maction);
4326 break;
c6475a0b
AY		 4327 default:
4328 WARN_ON(true);
4329 break;
4330 }
4331
4332 kfree(maction);
4333 return 0;
4334}
4335
e126ba97
EC		 4336static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4337{
4338 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 4339 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97 4340 int err;
539ec982
YH		 4341 u16 uid;
4342
4343 uid = ibqp->pd ?
4344 to_mpd(ibqp->pd)->uid : 0;
e126ba97 4345
81e30880
YH		 4346 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
4347 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
4348 return -EOPNOTSUPP;
4349 }
4350
539ec982 4351 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
e126ba97
EC		 4352 if (err)
4353 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
4354 ibqp->qp_num, gid->raw);
4355
4356 return err;
4357}
4358
4359static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4360{
4361 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4362 int err;
539ec982 4363 u16 uid;
e126ba97 4364
539ec982
YH		 4365 uid = ibqp->pd ?
4366 to_mpd(ibqp->pd)->uid : 0;
4367 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
e126ba97
EC		 4368 if (err)
4369 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
4370 ibqp->qp_num, gid->raw);
4371
4372 return err;
4373}
4374
4375static int init_node_data(struct mlx5_ib_dev *dev)
4376{
1b5daf11 4377 int err;
e126ba97 4378
1b5daf11 4379 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 4380 if (err)
1b5daf11 4381 return err;
e126ba97 4382
1b5daf11 4383 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 4384
1b5daf11 4385 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 4386}
4387
508a523f
PP		 4388static ssize_t fw_pages_show(struct device *device,
4389 struct device_attribute *attr, char *buf)
e126ba97
EC		 4390{
4391 struct mlx5_ib_dev *dev =
54747231 4392 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
e126ba97 4393
9603b61d 4394 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97 4395}
508a523f 4396static DEVICE_ATTR_RO(fw_pages);
e126ba97 4397
508a523f 4398static ssize_t reg_pages_show(struct device *device,
e126ba97
EC		 4399 struct device_attribute *attr, char *buf)
4400{
4401 struct mlx5_ib_dev *dev =
54747231 4402 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
e126ba97 4403
6aec21f6 4404 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97 4405}
508a523f 4406static DEVICE_ATTR_RO(reg_pages);
e126ba97 4407
508a523f
PP		 4408static ssize_t hca_type_show(struct device *device,
4409 struct device_attribute *attr, char *buf)
e126ba97
EC		 4410{
4411 struct mlx5_ib_dev *dev =
54747231
PP		 4412 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4413
9603b61d 4414 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97 4415}
508a523f 4416static DEVICE_ATTR_RO(hca_type);
e126ba97 4417
508a523f
PP		 4418static ssize_t hw_rev_show(struct device *device,
4419 struct device_attribute *attr, char *buf)
e126ba97
EC		 4420{
4421 struct mlx5_ib_dev *dev =
54747231
PP		 4422 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4423
9603b61d 4424 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97 4425}
508a523f 4426static DEVICE_ATTR_RO(hw_rev);
e126ba97 4427
508a523f
PP		 4428static ssize_t board_id_show(struct device *device,
4429 struct device_attribute *attr, char *buf)
e126ba97
EC		 4430{
4431 struct mlx5_ib_dev *dev =
54747231
PP		 4432 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4433
e126ba97 4434 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 4435 dev->mdev->board_id);
e126ba97 4436}
508a523f 4437static DEVICE_ATTR_RO(board_id);
e126ba97 4438
508a523f
PP		 4439static struct attribute *mlx5_class_attributes[] = {
4440 &dev_attr_hw_rev.attr,
4441 &dev_attr_hca_type.attr,
4442 &dev_attr_board_id.attr,
4443 &dev_attr_fw_pages.attr,
4444 &dev_attr_reg_pages.attr,
4445 NULL,
4446};
e126ba97 4447
508a523f
PP		 4448static const struct attribute_group mlx5_attr_group = {
4449 .attrs = mlx5_class_attributes,
e126ba97
EC		 4450};
4451
7722f47e
HE		 4452static void pkey_change_handler(struct work_struct *work)
4453{
4454 struct mlx5_ib_port_resources *ports =
4455 container_of(work, struct mlx5_ib_port_resources,
4456 pkey_change_work);
4457
4458 mutex_lock(&ports->devr->mutex);
4459 mlx5_ib_gsi_pkey_change(ports->gsi);
4460 mutex_unlock(&ports->devr->mutex);
4461}
4462
89ea94a7
MG		 4463static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
4464{
4465 struct mlx5_ib_qp *mqp;
4466 struct mlx5_ib_cq *send_mcq, *recv_mcq;
4467 struct mlx5_core_cq *mcq;
4468 struct list_head cq_armed_list;
4469 unsigned long flags_qp;
4470 unsigned long flags_cq;
4471 unsigned long flags;
4472
4473 INIT_LIST_HEAD(&cq_armed_list);
4474
4475 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
4476 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
4477 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
4478 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
4479 if (mqp->sq.tail != mqp->sq.head) {
4480 send_mcq = to_mcq(mqp->ibqp.send_cq);
4481 spin_lock_irqsave(&send_mcq->lock, flags_cq);
4482 if (send_mcq->mcq.comp &&
4483 mqp->ibqp.send_cq->comp_handler) {
4484 if (!send_mcq->mcq.reset_notify_added) {
4485 send_mcq->mcq.reset_notify_added = 1;
4486 list_add_tail(&send_mcq->mcq.reset_notify,
4487 &cq_armed_list);
4488 }
4489 }
4490 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
4491 }
4492 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
4493 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
4494 /* no handling is needed for SRQ */
4495 if (!mqp->ibqp.srq) {
4496 if (mqp->rq.tail != mqp->rq.head) {
4497 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
4498 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
4499 if (recv_mcq->mcq.comp &&
4500 mqp->ibqp.recv_cq->comp_handler) {
4501 if (!recv_mcq->mcq.reset_notify_added) {
4502 recv_mcq->mcq.reset_notify_added = 1;
4503 list_add_tail(&recv_mcq->mcq.reset_notify,
4504 &cq_armed_list);
4505 }
4506 }
4507 spin_unlock_irqrestore(&recv_mcq->lock,
4508 flags_cq);
4509 }
4510 }
4511 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
4512 }
4513 /*At that point all inflight post send were put to be executed as of we
4514 * lock/unlock above locks Now need to arm all involved CQs.
4515 */
4516 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4e0e2ea1 4517 mcq->comp(mcq, NULL);
89ea94a7
MG		 4518 }
4519 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
4520}
4521
03404e8a
MG		 4522static void delay_drop_handler(struct work_struct *work)
4523{
4524 int err;
4525 struct mlx5_ib_delay_drop *delay_drop =
4526 container_of(work, struct mlx5_ib_delay_drop,
4527 delay_drop_work);
4528
fe248c3a
MG		 4529 atomic_inc(&delay_drop->events_cnt);
4530
03404e8a
MG		 4531 mutex_lock(&delay_drop->lock);
4532 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
4533 delay_drop->timeout);
4534 if (err) {
4535 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4536 delay_drop->timeout);
4537 delay_drop->activate = false;
4538 }
4539 mutex_unlock(&delay_drop->lock);
4540}
4541
09e574fa
SM		 4542static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4543 struct ib_event *ibev)
4544{
6cfdc7e4
AL		 4545 u8 port = (eqe->data.port.port >> 4) & 0xf;
4546
09e574fa
SM		 4547 switch (eqe->sub_type) {
4548 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
6cfdc7e4
AL		 4549 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4550 IB_LINK_LAYER_ETHERNET)
4551 schedule_work(&ibdev->delay_drop.delay_drop_work);
09e574fa
SM		 4552 break;
4553 default: /* do nothing */
4554 return;
4555 }
4556}
4557
134e9349
SM		 4558static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4559 struct ib_event *ibev)
4560{
4561 u8 port = (eqe->data.port.port >> 4) & 0xf;
4562
4563 ibev->element.port_num = port;
4564
4565 switch (eqe->sub_type) {
4566 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
4567 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
4568 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
4569 /* In RoCE, port up/down events are handled in
4570 * mlx5_netdev_event().
4571 */
4572 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4573 IB_LINK_LAYER_ETHERNET)
4574 return -EINVAL;
4575
4576 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
4577 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
4578 break;
4579
4580 case MLX5_PORT_CHANGE_SUBTYPE_LID:
4581 ibev->event = IB_EVENT_LID_CHANGE;
4582 break;
4583
4584 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
4585 ibev->event = IB_EVENT_PKEY_CHANGE;
4586 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
4587 break;
4588
4589 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
4590 ibev->event = IB_EVENT_GID_CHANGE;
4591 break;
4592
4593 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
4594 ibev->event = IB_EVENT_CLIENT_REREGISTER;
4595 break;
4596 default:
4597 return -EINVAL;
4598 }
4599
4600 return 0;
4601}
4602
d69a24e0 4603static void mlx5_ib_handle_event(struct work_struct *_work)
e126ba97 4604{
d69a24e0
DJ		 4605 struct mlx5_ib_event_work *work =
4606 container_of(_work, struct mlx5_ib_event_work, work);
4607 struct mlx5_ib_dev *ibdev;
e126ba97 4608 struct ib_event ibev;
dbaaff2a 4609 bool fatal = false;
e126ba97 4610
df097a27
SM		 4611 if (work->is_slave) {
4612 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
d69a24e0
DJ		 4613 if (!ibdev)
4614 goto out;
4615 } else {
df097a27 4616 ibdev = work->dev;
d69a24e0
DJ		 4617 }
4618
4619 switch (work->event) {
e126ba97 4620 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 4621 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 4622 mlx5_ib_handle_internal_error(ibdev);
134e9349 4623 ibev.element.port_num = (u8)(unsigned long)work->param;
dbaaff2a 4624 fatal = true;
e126ba97 4625 break;
134e9349
SM		 4626 case MLX5_EVENT_TYPE_PORT_CHANGE:
4627 if (handle_port_change(ibdev, work->param, &ibev))
d69a24e0 4628 goto out;
e126ba97 4629 break;
09e574fa
SM		 4630 case MLX5_EVENT_TYPE_GENERAL_EVENT:
4631 handle_general_event(ibdev, work->param, &ibev);
4632 /* fall through */
bdc37924 4633 default:
03404e8a 4634 goto out;
e126ba97
EC		 4635 }
4636
134e9349 4637 ibev.device = &ibdev->ib_dev;
e126ba97 4638
134e9349
SM		 4639 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
4640 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num);
03404e8a 4641 goto out;
a0c84c32
EC		 4642 }
4643
e126ba97
EC		 4644 if (ibdev->ib_active)
4645 ib_dispatch_event(&ibev);
dbaaff2a
EC		 4646
4647 if (fatal)
4648 ibdev->ib_active = false;
03404e8a 4649out:
d69a24e0
DJ		 4650 kfree(work);
4651}
4652
df097a27
SM		 4653static int mlx5_ib_event(struct notifier_block *nb,
4654 unsigned long event, void *param)
d69a24e0
DJ		 4655{
4656 struct mlx5_ib_event_work *work;
4657
4658 work = kmalloc(sizeof(*work), GFP_ATOMIC);
10bea9c8 4659 if (!work)
df097a27 4660 return NOTIFY_DONE;
d69a24e0 4661
10bea9c8 4662 INIT_WORK(&work->work, mlx5_ib_handle_event);
df097a27
SM		 4663 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
4664 work->is_slave = false;
10bea9c8 4665 work->param = param;
10bea9c8
LR		 4666 work->event = event;
4667
4668 queue_work(mlx5_ib_event_wq, &work->work);
df097a27
SM		 4669
4670 return NOTIFY_OK;
4671}
4672
4673static int mlx5_ib_event_slave_port(struct notifier_block *nb,
4674 unsigned long event, void *param)
4675{
4676 struct mlx5_ib_event_work *work;
4677
4678 work = kmalloc(sizeof(*work), GFP_ATOMIC);
4679 if (!work)
4680 return NOTIFY_DONE;
4681
4682 INIT_WORK(&work->work, mlx5_ib_handle_event);
4683 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
4684 work->is_slave = true;
4685 work->param = param;
4686 work->event = event;
4687 queue_work(mlx5_ib_event_wq, &work->work);
4688
4689 return NOTIFY_OK;
e126ba97
EC		 4690}
4691
c43f1112
MG		 4692static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4693{
4694 struct mlx5_hca_vport_context vport_ctx;
4695 int err;
4696 int port;
4697
a989ea01 4698 for (port = 1; port <= ARRAY_SIZE(dev->mdev->port_caps); port++) {
c43f1112
MG		 4699 dev->mdev->port_caps[port - 1].has_smi = false;
4700 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4701 MLX5_CAP_PORT_TYPE_IB) {
4702 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4703 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4704 port, 0,
4705 &vport_ctx);
4706 if (err) {
4707 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4708 port, err);
4709 return err;
4710 }
4711 dev->mdev->port_caps[port - 1].has_smi =
4712 vport_ctx.has_smi;
4713 } else {
4714 dev->mdev->port_caps[port - 1].has_smi = true;
4715 }
4716 }
4717 }
4718 return 0;
4719}
4720
e126ba97
EC		 4721static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4722{
4723 int port;
4724
508562d6 4725 for (port = 1; port <= dev->num_ports; port++)
e126ba97
EC		 4726 mlx5_query_ext_port_caps(dev, port);
4727}
4728
26628e2d 4729static int __get_port_caps(struct mlx5_ib_dev *dev, u8 port)
e126ba97
EC		 4730{
4731 struct ib_device_attr *dprops = NULL;
4732 struct ib_port_attr *pprops = NULL;
f614fc15 4733 int err = -ENOMEM;
2528e33e 4734 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97 4735
50ba3c18 4736 pprops = kzalloc(sizeof(*pprops), GFP_KERNEL);
e126ba97
EC		 4737 if (!pprops)
4738 goto out;
4739
4740 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4741 if (!dprops)
4742 goto out;
4743
2528e33e 4744 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 4745 if (err) {
4746 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4747 goto out;
4748 }
4749
32f69e4b
DJ		 4750 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4751 if (err) {
4752 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4753 port, err);
4754 goto out;
e126ba97
EC		 4755 }
4756
32f69e4b
DJ		 4757 dev->mdev->port_caps[port - 1].pkey_table_len =
4758 dprops->max_pkeys;
4759 dev->mdev->port_caps[port - 1].gid_table_len =
4760 pprops->gid_tbl_len;
4761 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4762 port, dprops->max_pkeys, pprops->gid_tbl_len);
4763
e126ba97
EC		 4764out:
4765 kfree(pprops);
4766 kfree(dprops);
4767
4768 return err;
4769}
4770
26628e2d
MB		 4771static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4772{
4773 /* For representors use port 1, is this is the only native
4774 * port
4775 */
4776 if (dev->is_rep)
4777 return __get_port_caps(dev, 1);
4778 return __get_port_caps(dev, port);
4779}
4780
e126ba97
EC		 4781static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4782{
4783 int err;
4784
4785 err = mlx5_mr_cache_cleanup(dev);
4786 if (err)
4787 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4788
32927e28 4789 if (dev->umrc.qp)
c4367a26 4790 mlx5_ib_destroy_qp(dev->umrc.qp, NULL);
32927e28
MB		 4791 if (dev->umrc.cq)
4792 ib_free_cq(dev->umrc.cq);
4793 if (dev->umrc.pd)
4794 ib_dealloc_pd(dev->umrc.pd);
e126ba97
EC		 4795}
4796
4797enum {
4798 MAX_UMR_WR = 128,
4799};
4800
4801static int create_umr_res(struct mlx5_ib_dev *dev)
4802{
4803 struct ib_qp_init_attr *init_attr = NULL;
4804 struct ib_qp_attr *attr = NULL;
4805 struct ib_pd *pd;
4806 struct ib_cq *cq;
4807 struct ib_qp *qp;
e126ba97
EC		 4808 int ret;
4809
4810 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4811 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4812 if (!attr || !init_attr) {
4813 ret = -ENOMEM;
4814 goto error_0;
4815 }
4816
ed082d36 4817 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 4818 if (IS_ERR(pd)) {
4819 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4820 ret = PTR_ERR(pd);
4821 goto error_0;
4822 }
4823
add08d76 4824 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 4825 if (IS_ERR(cq)) {
4826 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4827 ret = PTR_ERR(cq);
4828 goto error_2;
4829 }
e126ba97
EC		 4830
4831 init_attr->send_cq = cq;
4832 init_attr->recv_cq = cq;
4833 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4834 init_attr->cap.max_send_wr = MAX_UMR_WR;
4835 init_attr->cap.max_send_sge = 1;
4836 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4837 init_attr->port_num = 1;
4838 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4839 if (IS_ERR(qp)) {
4840 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4841 ret = PTR_ERR(qp);
4842 goto error_3;
4843 }
4844 qp->device = &dev->ib_dev;
4845 qp->real_qp = qp;
4846 qp->uobject = NULL;
4847 qp->qp_type = MLX5_IB_QPT_REG_UMR;
31fde034
MD		 4848 qp->send_cq = init_attr->send_cq;
4849 qp->recv_cq = init_attr->recv_cq;
e126ba97
EC		 4850
4851 attr->qp_state = IB_QPS_INIT;
4852 attr->port_num = 1;
4853 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4854 IB_QP_PORT, NULL);
4855 if (ret) {
4856 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4857 goto error_4;
4858 }
4859
4860 memset(attr, 0, sizeof(*attr));
4861 attr->qp_state = IB_QPS_RTR;
4862 attr->path_mtu = IB_MTU_256;
4863
4864 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4865 if (ret) {
4866 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4867 goto error_4;
4868 }
4869
4870 memset(attr, 0, sizeof(*attr));
4871 attr->qp_state = IB_QPS_RTS;
4872 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4873 if (ret) {
4874 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4875 goto error_4;
4876 }
4877
4878 dev->umrc.qp = qp;
4879 dev->umrc.cq = cq;
e126ba97
EC		 4880 dev->umrc.pd = pd;
4881
4882 sema_init(&dev->umrc.sem, MAX_UMR_WR);
4883 ret = mlx5_mr_cache_init(dev);
4884 if (ret) {
4885 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4886 goto error_4;
4887 }
4888
4889 kfree(attr);
4890 kfree(init_attr);
4891
4892 return 0;
4893
4894error_4:
c4367a26 4895 mlx5_ib_destroy_qp(qp, NULL);
32927e28 4896 dev->umrc.qp = NULL;
e126ba97
EC		 4897
4898error_3:
add08d76 4899 ib_free_cq(cq);
32927e28 4900 dev->umrc.cq = NULL;
e126ba97
EC		 4901
4902error_2:
e126ba97 4903 ib_dealloc_pd(pd);
32927e28 4904 dev->umrc.pd = NULL;
e126ba97
EC		 4905
4906error_0:
4907 kfree(attr);
4908 kfree(init_attr);
4909 return ret;
4910}
4911
6e8484c5
MG		 4912static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4913{
4914 switch (umr_fence_cap) {
4915 case MLX5_CAP_UMR_FENCE_NONE:
4916 return MLX5_FENCE_MODE_NONE;
4917 case MLX5_CAP_UMR_FENCE_SMALL:
4918 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4919 default:
4920 return MLX5_FENCE_MODE_STRONG_ORDERING;
4921 }
4922}
4923
e126ba97
EC		 4924static int create_dev_resources(struct mlx5_ib_resources *devr)
4925{
4926 struct ib_srq_init_attr attr;
4927 struct mlx5_ib_dev *dev;
21a428a0 4928 struct ib_device *ibdev;
bcf4c1ea 4929 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 4930 int port;
e126ba97
EC		 4931 int ret = 0;
4932
4933 dev = container_of(devr, struct mlx5_ib_dev, devr);
21a428a0 4934 ibdev = &dev->ib_dev;
e126ba97 4935
d16e91da
HE		 4936 mutex_init(&devr->mutex);
4937
21a428a0
LR		 4938 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd);
4939 if (!devr->p0)
4940 return -ENOMEM;
4941
4942 devr->p0->device = ibdev;
e126ba97
EC		 4943 devr->p0->uobject = NULL;
4944 atomic_set(&devr->p0->usecnt, 0);
4945
ff23dfa1 4946 ret = mlx5_ib_alloc_pd(devr->p0, NULL);
21a428a0
LR		 4947 if (ret)
4948 goto error0;
4949
e39afe3d
LR		 4950 devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq);
4951 if (!devr->c0) {
4952 ret = -ENOMEM;
e126ba97
EC		 4953 goto error1;
4954 }
e39afe3d
LR		 4955
4956 devr->c0->device = &dev->ib_dev;
e126ba97
EC		 4957 atomic_set(&devr->c0->usecnt, 0);
4958
e39afe3d
LR		 4959 ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL);
4960 if (ret)
4961 goto err_create_cq;
4962
ff23dfa1 4963 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
e126ba97
EC		 4964 if (IS_ERR(devr->x0)) {
4965 ret = PTR_ERR(devr->x0);
4966 goto error2;
4967 }
4968 devr->x0->device = &dev->ib_dev;
4969 devr->x0->inode = NULL;
4970 atomic_set(&devr->x0->usecnt, 0);
4971 mutex_init(&devr->x0->tgt_qp_mutex);
4972 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4973
ff23dfa1 4974 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
e126ba97
EC		 4975 if (IS_ERR(devr->x1)) {
4976 ret = PTR_ERR(devr->x1);
4977 goto error3;
4978 }
4979 devr->x1->device = &dev->ib_dev;
4980 devr->x1->inode = NULL;
4981 atomic_set(&devr->x1->usecnt, 0);
4982 mutex_init(&devr->x1->tgt_qp_mutex);
4983 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4984
4985 memset(&attr, 0, sizeof(attr));
4986 attr.attr.max_sge = 1;
4987 attr.attr.max_wr = 1;
4988 attr.srq_type = IB_SRQT_XRC;
1a56ff6d 4989 attr.ext.cq = devr->c0;
e126ba97
EC		 4990 attr.ext.xrc.xrcd = devr->x0;
4991
68e326de
LR		 4992 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq);
4993 if (!devr->s0) {
4994 ret = -ENOMEM;
e126ba97
EC		 4995 goto error4;
4996 }
68e326de 4997
e126ba97
EC		 4998 devr->s0->device = &dev->ib_dev;
4999 devr->s0->pd = devr->p0;
e126ba97
EC		 5000 devr->s0->srq_type = IB_SRQT_XRC;
5001 devr->s0->ext.xrc.xrcd = devr->x0;
1a56ff6d 5002 devr->s0->ext.cq = devr->c0;
68e326de
LR		 5003 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL);
5004 if (ret)
5005 goto err_create;
5006
e126ba97 5007 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1a56ff6d 5008 atomic_inc(&devr->s0->ext.cq->usecnt);
e126ba97
EC		 5009 atomic_inc(&devr->p0->usecnt);
5010 atomic_set(&devr->s0->usecnt, 0);
5011
4aa17b28
HA		 5012 memset(&attr, 0, sizeof(attr));
5013 attr.attr.max_sge = 1;
5014 attr.attr.max_wr = 1;
5015 attr.srq_type = IB_SRQT_BASIC;
68e326de
LR		 5016 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq);
5017 if (!devr->s1) {
5018 ret = -ENOMEM;
4aa17b28
HA		 5019 goto error5;
5020 }
68e326de 5021
4aa17b28
HA		 5022 devr->s1->device = &dev->ib_dev;
5023 devr->s1->pd = devr->p0;
4aa17b28 5024 devr->s1->srq_type = IB_SRQT_BASIC;
1a56ff6d 5025 devr->s1->ext.cq = devr->c0;
68e326de
LR		 5026
5027 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL);
5028 if (ret)
5029 goto error6;
5030
4aa17b28 5031 atomic_inc(&devr->p0->usecnt);
1a56ff6d 5032 atomic_set(&devr->s1->usecnt, 0);
4aa17b28 5033
7722f47e
HE		 5034 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
5035 INIT_WORK(&devr->ports[port].pkey_change_work,
5036 pkey_change_handler);
5037 devr->ports[port].devr = devr;
5038 }
5039
e126ba97
EC		 5040 return 0;
5041
68e326de
LR		 5042error6:
5043 kfree(devr->s1);
4aa17b28 5044error5:
c4367a26 5045 mlx5_ib_destroy_srq(devr->s0, NULL);
68e326de
LR		 5046err_create:
5047 kfree(devr->s0);
e126ba97 5048error4:
c4367a26 5049 mlx5_ib_dealloc_xrcd(devr->x1, NULL);
e126ba97 5050error3:
c4367a26 5051 mlx5_ib_dealloc_xrcd(devr->x0, NULL);
e126ba97 5052error2:
c4367a26 5053 mlx5_ib_destroy_cq(devr->c0, NULL);
e39afe3d
LR		 5054err_create_cq:
5055 kfree(devr->c0);
e126ba97 5056error1:
c4367a26 5057 mlx5_ib_dealloc_pd(devr->p0, NULL);
e126ba97 5058error0:
21a428a0 5059 kfree(devr->p0);
e126ba97
EC		 5060 return ret;
5061}
5062
5063static void destroy_dev_resources(struct mlx5_ib_resources *devr)
5064{
7722f47e
HE		 5065 int port;
5066
c4367a26 5067 mlx5_ib_destroy_srq(devr->s1, NULL);
68e326de 5068 kfree(devr->s1);
c4367a26 5069 mlx5_ib_destroy_srq(devr->s0, NULL);
68e326de 5070 kfree(devr->s0);
c4367a26
SR		 5071 mlx5_ib_dealloc_xrcd(devr->x0, NULL);
5072 mlx5_ib_dealloc_xrcd(devr->x1, NULL);
5073 mlx5_ib_destroy_cq(devr->c0, NULL);
e39afe3d 5074 kfree(devr->c0);
c4367a26 5075 mlx5_ib_dealloc_pd(devr->p0, NULL);
21a428a0 5076 kfree(devr->p0);
7722f47e
HE		 5077
5078 /* Make sure no change P_Key work items are still executing */
5d8f6a0e 5079 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
7722f47e 5080 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 5081}
5082
b02289b3
AK		 5083static u32 get_core_cap_flags(struct ib_device *ibdev,
5084 struct mlx5_hca_vport_context *rep)
e53505a8
AS		 5085{
5086 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5087 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
5088 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
5089 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
85c7c014 5090 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
e53505a8
AS		 5091 u32 ret = 0;
5092
b02289b3
AK		 5093 if (rep->grh_required)
5094 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
5095
e53505a8 5096 if (ll == IB_LINK_LAYER_INFINIBAND)
b02289b3 5097 return ret | RDMA_CORE_PORT_IBA_IB;
e53505a8 5098
85c7c014 5099 if (raw_support)
b02289b3 5100 ret |= RDMA_CORE_PORT_RAW_PACKET;
72cd5717 5101
e53505a8 5102 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 5103 return ret;
e53505a8
AS		 5104
5105 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 5106 return ret;
e53505a8
AS		 5107
5108 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
5109 ret |= RDMA_CORE_PORT_IBA_ROCE;
5110
5111 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
5112 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
5113
5114 return ret;
5115}
5116
7738613e
IW		 5117static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
5118 struct ib_port_immutable *immutable)
5119{
5120 struct ib_port_attr attr;
ca5b91d6
OG		 5121 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5122 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
b02289b3 5123 struct mlx5_hca_vport_context rep = {0};
7738613e
IW		 5124 int err;
5125
c4550c63 5126 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 5127 if (err)
5128 return err;
5129
b02289b3
AK		 5130 if (ll == IB_LINK_LAYER_INFINIBAND) {
5131 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
5132 &rep);
5133 if (err)
5134 return err;
5135 }
5136
7738613e
IW		 5137 immutable->pkey_tbl_len = attr.pkey_tbl_len;
5138 immutable->gid_tbl_len = attr.gid_tbl_len;
b02289b3 5139 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
ca5b91d6
OG		 5140 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
5141 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 5142
5143 return 0;
5144}
5145
8e6efa3a
MB		 5146static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
5147 struct ib_port_immutable *immutable)
5148{
5149 struct ib_port_attr attr;
5150 int err;
5151
5152 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5153
5154 err = ib_query_port(ibdev, port_num, &attr);
5155 if (err)
5156 return err;
5157
5158 immutable->pkey_tbl_len = attr.pkey_tbl_len;
5159 immutable->gid_tbl_len = attr.gid_tbl_len;
5160 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5161
5162 return 0;
5163}
5164
9abb0d1b 5165static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 5166{
5167 struct mlx5_ib_dev *dev =
5168 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 5169 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
5170 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
5171 fw_rev_sub(dev->mdev));
c7342823
IW		 5172}
5173
45f95acd 5174static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 5175{
5176 struct mlx5_core_dev *mdev = dev->mdev;
5177 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
5178 MLX5_FLOW_NAMESPACE_LAG);
5179 struct mlx5_flow_table *ft;
5180 int err;
5181
7c34ec19 5182 if (!ns || !mlx5_lag_is_roce(mdev))
9ef9c640
AH		 5183 return 0;
5184
5185 err = mlx5_cmd_create_vport_lag(mdev);
5186 if (err)
5187 return err;
5188
5189 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
5190 if (IS_ERR(ft)) {
5191 err = PTR_ERR(ft);
5192 goto err_destroy_vport_lag;
5193 }
5194
9a4ca38d 5195 dev->flow_db->lag_demux_ft = ft;
7c34ec19 5196 dev->lag_active = true;
9ef9c640
AH		 5197 return 0;
5198
5199err_destroy_vport_lag:
5200 mlx5_cmd_destroy_vport_lag(mdev);
5201 return err;
5202}
5203
45f95acd 5204static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 5205{
5206 struct mlx5_core_dev *mdev = dev->mdev;
5207
7c34ec19
AH		 5208 if (dev->lag_active) {
5209 dev->lag_active = false;
5210
9a4ca38d
MB		 5211 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
5212 dev->flow_db->lag_demux_ft = NULL;
9ef9c640
AH		 5213
5214 mlx5_cmd_destroy_vport_lag(mdev);
5215 }
5216}
5217
7fd8aefb 5218static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
d012f5d6
OG		 5219{
5220 int err;
5221
95579e78
MB		 5222 dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event;
5223 err = register_netdevice_notifier(&dev->port[port_num].roce.nb);
d012f5d6 5224 if (err) {
95579e78 5225 dev->port[port_num].roce.nb.notifier_call = NULL;
d012f5d6
OG		 5226 return err;
5227 }
5228
5229 return 0;
5230}
5231
7fd8aefb 5232static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5ec8c83e 5233{
95579e78
MB		 5234 if (dev->port[port_num].roce.nb.notifier_call) {
5235 unregister_netdevice_notifier(&dev->port[port_num].roce.nb);
5236 dev->port[port_num].roce.nb.notifier_call = NULL;
5ec8c83e
AH		 5237 }
5238}
5239
e3f1ed1f 5240static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 5241{
e53505a8
AS		 5242 int err;
5243
ca5b91d6
OG		 5244 if (MLX5_CAP_GEN(dev->mdev, roce)) {
5245 err = mlx5_nic_vport_enable_roce(dev->mdev);
5246 if (err)
8e6efa3a 5247 return err;
ca5b91d6 5248 }
e53505a8 5249
45f95acd 5250 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 5251 if (err)
5252 goto err_disable_roce;
5253
e53505a8
AS		 5254 return 0;
5255
9ef9c640 5256err_disable_roce:
ca5b91d6
OG		 5257 if (MLX5_CAP_GEN(dev->mdev, roce))
5258 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 5259
e53505a8 5260 return err;
fc24fc5e
AS		 5261}
5262
45f95acd 5263static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 5264{
45f95acd 5265 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 5266 if (MLX5_CAP_GEN(dev->mdev, roce))
5267 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 5268}
5269
e1f24a79 5270struct mlx5_ib_counter {
7c16f477
KH		 5271 const char *name;
5272 size_t offset;
5273};
5274
5275#define INIT_Q_COUNTER(_name) \
5276 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
5277
e1f24a79 5278static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 5279 INIT_Q_COUNTER(rx_write_requests),
5280 INIT_Q_COUNTER(rx_read_requests),
5281 INIT_Q_COUNTER(rx_atomic_requests),
5282 INIT_Q_COUNTER(out_of_buffer),
5283};
5284
e1f24a79 5285static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 5286 INIT_Q_COUNTER(out_of_sequence),
5287};
5288
e1f24a79 5289static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 5290 INIT_Q_COUNTER(duplicate_request),
5291 INIT_Q_COUNTER(rnr_nak_retry_err),
5292 INIT_Q_COUNTER(packet_seq_err),
5293 INIT_Q_COUNTER(implied_nak_seq_err),
5294 INIT_Q_COUNTER(local_ack_timeout_err),
5295};
5296
e1f24a79
PP		 5297#define INIT_CONG_COUNTER(_name) \
5298 { .name = #_name, .offset = \
5299 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
5300
5301static const struct mlx5_ib_counter cong_cnts[] = {
5302 INIT_CONG_COUNTER(rp_cnp_ignored),
5303 INIT_CONG_COUNTER(rp_cnp_handled),
5304 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
5305 INIT_CONG_COUNTER(np_cnp_sent),
5306};
5307
58dcb60a
PP		 5308static const struct mlx5_ib_counter extended_err_cnts[] = {
5309 INIT_Q_COUNTER(resp_local_length_error),
5310 INIT_Q_COUNTER(resp_cqe_error),
5311 INIT_Q_COUNTER(req_cqe_error),
5312 INIT_Q_COUNTER(req_remote_invalid_request),
5313 INIT_Q_COUNTER(req_remote_access_errors),
5314 INIT_Q_COUNTER(resp_remote_access_errors),
5315 INIT_Q_COUNTER(resp_cqe_flush_error),
5316 INIT_Q_COUNTER(req_cqe_flush_error),
5317};
5318
9f876f3d
TB		 5319#define INIT_EXT_PPCNT_COUNTER(_name) \
5320 { .name = #_name, .offset = \
5321 MLX5_BYTE_OFF(ppcnt_reg, \
5322 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
5323
5324static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
5325 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
5326};
5327
3e1f000f
PP		 5328static bool is_mdev_switchdev_mode(const struct mlx5_core_dev *mdev)
5329{
5330 return MLX5_ESWITCH_MANAGER(mdev) &&
5331 mlx5_ib_eswitch_mode(mdev->priv.eswitch) ==
5332 MLX5_ESWITCH_OFFLOADS;
5333}
5334
e1f24a79 5335static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a 5336{
3e1f000f 5337 int num_cnt_ports;
aac4492e 5338 int i;
0837e86a 5339
3e1f000f
PP		 5340 num_cnt_ports = is_mdev_switchdev_mode(dev->mdev) ? 1 : dev->num_ports;
5341
5342 for (i = 0; i < num_cnt_ports; i++) {
921c0f5b 5343 if (dev->port[i].cnts.set_id_valid)
aac4492e
DJ		 5344 mlx5_core_dealloc_q_counter(dev->mdev,
5345 dev->port[i].cnts.set_id);
e1f24a79
PP		 5346 kfree(dev->port[i].cnts.names);
5347 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 5348 }
5349}
5350
e1f24a79
PP		 5351static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
5352 struct mlx5_ib_counters *cnts)
7c16f477
KH		 5353{
5354 u32 num_counters;
5355
5356 num_counters = ARRAY_SIZE(basic_q_cnts);
5357
5358 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
5359 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
5360
5361 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
5362 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 5363
5364 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
5365 num_counters += ARRAY_SIZE(extended_err_cnts);
5366
e1f24a79 5367 cnts->num_q_counters = num_counters;
7c16f477 5368
e1f24a79
PP		 5369 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5370 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
5371 num_counters += ARRAY_SIZE(cong_cnts);
5372 }
9f876f3d
TB		 5373 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5374 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
5375 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
5376 }
e1f24a79
PP		 5377 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
5378 if (!cnts->names)
7c16f477
KH		 5379 return -ENOMEM;
5380
e1f24a79
PP		 5381 cnts->offsets = kcalloc(num_counters,
5382 sizeof(cnts->offsets), GFP_KERNEL);
5383 if (!cnts->offsets)
7c16f477
KH		 5384 goto err_names;
5385
7c16f477
KH		 5386 return 0;
5387
5388err_names:
e1f24a79 5389 kfree(cnts->names);
aac4492e 5390 cnts->names = NULL;
7c16f477
KH		 5391 return -ENOMEM;
5392}
5393
e1f24a79
PP		 5394static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
5395 const char **names,
5396 size_t *offsets)
7c16f477
KH		 5397{
5398 int i;
5399 int j = 0;
5400
5401 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
5402 names[j] = basic_q_cnts[i].name;
5403 offsets[j] = basic_q_cnts[i].offset;
5404 }
5405
5406 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
5407 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
5408 names[j] = out_of_seq_q_cnts[i].name;
5409 offsets[j] = out_of_seq_q_cnts[i].offset;
5410 }
5411 }
5412
5413 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
5414 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
5415 names[j] = retrans_q_cnts[i].name;
5416 offsets[j] = retrans_q_cnts[i].offset;
5417 }
5418 }
e1f24a79 5419
58dcb60a
PP		 5420 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
5421 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
5422 names[j] = extended_err_cnts[i].name;
5423 offsets[j] = extended_err_cnts[i].offset;
5424 }
5425 }
5426
e1f24a79
PP		 5427 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5428 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
5429 names[j] = cong_cnts[i].name;
5430 offsets[j] = cong_cnts[i].offset;
5431 }
5432 }
9f876f3d
TB		 5433
5434 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5435 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
5436 names[j] = ext_ppcnt_cnts[i].name;
5437 offsets[j] = ext_ppcnt_cnts[i].offset;
5438 }
5439 }
0837e86a
MB		 5440}
5441
e1f24a79 5442static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a 5443{
3e1f000f 5444 int num_cnt_ports;
aac4492e 5445 int err = 0;
0837e86a 5446 int i;
aa74be6e
YH		 5447 bool is_shared;
5448
5449 is_shared = MLX5_CAP_GEN(dev->mdev, log_max_uctx) != 0;
3e1f000f 5450 num_cnt_ports = is_mdev_switchdev_mode(dev->mdev) ? 1 : dev->num_ports;
0837e86a 5451
3e1f000f 5452 for (i = 0; i < num_cnt_ports; i++) {
aac4492e
DJ		 5453 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
5454 if (err)
5455 goto err_alloc;
5456
5457 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
5458 dev->port[i].cnts.offsets);
7c16f477 5459
aa74be6e
YH		 5460 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5461 &dev->port[i].cnts.set_id,
5462 is_shared ?
5463 MLX5_SHARED_RESOURCE_UID : 0);
aac4492e 5464 if (err) {
0837e86a
MB		 5465 mlx5_ib_warn(dev,
5466 "couldn't allocate queue counter for port %d, err %d\n",
aac4492e
DJ		 5467 i + 1, err);
5468 goto err_alloc;
0837e86a 5469 }
aac4492e 5470 dev->port[i].cnts.set_id_valid = true;
0837e86a 5471 }
0837e86a
MB		 5472 return 0;
5473
aac4492e
DJ		 5474err_alloc:
5475 mlx5_ib_dealloc_counters(dev);
5476 return err;
0837e86a
MB		 5477}
5478
3e1f000f
PP		 5479static const struct mlx5_ib_counters *get_counters(struct mlx5_ib_dev *dev,
5480 u8 port_num)
5481{
5482 return is_mdev_switchdev_mode(dev->mdev) ? &dev->port[0].cnts :
5483 &dev->port[port_num].cnts;
5484}
5485
5486/**
5487 * mlx5_ib_get_counters_id - Returns counters id to use for device+port
5488 * @dev: Pointer to mlx5 IB device
5489 * @port_num: Zero based port number
5490 *
5491 * mlx5_ib_get_counters_id() Returns counters set id to use for given
5492 * device port combination in switchdev and non switchdev mode of the
5493 * parent device.
5494 */
5495u16 mlx5_ib_get_counters_id(struct mlx5_ib_dev *dev, u8 port_num)
5496{
5497 const struct mlx5_ib_counters *cnts = get_counters(dev, port_num);
5498
5499 return cnts->set_id;
5500}
5501
0ad17a8f
MB		 5502static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
5503 u8 port_num)
5504{
7c16f477 5505 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3e1f000f
PP		 5506 const struct mlx5_ib_counters *cnts;
5507 bool is_switchdev = is_mdev_switchdev_mode(dev->mdev);
0ad17a8f 5508
3e1f000f 5509 if ((is_switchdev && port_num) || (!is_switchdev && !port_num))
0ad17a8f
MB		 5510 return NULL;
5511
3e1f000f
PP		 5512 cnts = get_counters(dev, port_num - 1);
5513
5dcecbc9
PP		 5514 return rdma_alloc_hw_stats_struct(cnts->names,
5515 cnts->num_q_counters +
5516 cnts->num_cong_counters +
5517 cnts->num_ext_ppcnt_counters,
0ad17a8f
MB		 5518 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5519}
5520
aac4492e 5521static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
5dcecbc9 5522 const struct mlx5_ib_counters *cnts,
318d535c
MZ		 5523 struct rdma_hw_stats *stats,
5524 u16 set_id)
0ad17a8f 5525{
0ad17a8f
MB		 5526 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
5527 void *out;
5528 __be32 val;
e1f24a79 5529 int ret, i;
0ad17a8f 5530
1b9a07ee 5531 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 5532 if (!out)
5533 return -ENOMEM;
5534
318d535c 5535 ret = mlx5_core_query_q_counter(mdev, set_id, 0, out, outlen);
0ad17a8f
MB		 5536 if (ret)
5537 goto free;
5538
5dcecbc9
PP		 5539 for (i = 0; i < cnts->num_q_counters; i++) {
5540 val = *(__be32 *)(out + cnts->offsets[i]);
0ad17a8f
MB		 5541 stats->value[i] = (u64)be32_to_cpu(val);
5542 }
7c16f477 5543
0ad17a8f
MB		 5544free:
5545 kvfree(out);
e1f24a79
PP		 5546 return ret;
5547}
5548
9f876f3d 5549static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
5dcecbc9
PP		 5550 const struct mlx5_ib_counters *cnts,
5551 struct rdma_hw_stats *stats)
9f876f3d 5552{
5dcecbc9 5553 int offset = cnts->num_q_counters + cnts->num_cong_counters;
9f876f3d
TB		 5554 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
5555 int ret, i;
5556 void *out;
5557
5558 out = kvzalloc(sz, GFP_KERNEL);
5559 if (!out)
5560 return -ENOMEM;
5561
5562 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
5563 if (ret)
5564 goto free;
5565
5dcecbc9 5566 for (i = 0; i < cnts->num_ext_ppcnt_counters; i++)
9f876f3d
TB		 5567 stats->value[i + offset] =
5568 be64_to_cpup((__be64 *)(out +
5dcecbc9 5569 cnts->offsets[i + offset]));
9f876f3d
TB		 5570free:
5571 kvfree(out);
5572 return ret;
5573}
5574
e1f24a79
PP		 5575static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
5576 struct rdma_hw_stats *stats,
5577 u8 port_num, int index)
5578{
5579 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3e1f000f 5580 const struct mlx5_ib_counters *cnts = get_counters(dev, port_num - 1);
aac4492e 5581 struct mlx5_core_dev *mdev;
e1f24a79 5582 int ret, num_counters;
aac4492e 5583 u8 mdev_port_num;
e1f24a79
PP		 5584
5585 if (!stats)
5586 return -EINVAL;
5587
5dcecbc9
PP		 5588 num_counters = cnts->num_q_counters +
5589 cnts->num_cong_counters +
5590 cnts->num_ext_ppcnt_counters;
aac4492e
DJ		 5591
5592 /* q_counters are per IB device, query the master mdev */
5dcecbc9 5593 ret = mlx5_ib_query_q_counters(dev->mdev, cnts, stats, cnts->set_id);
e1f24a79
PP		 5594 if (ret)
5595 return ret;
e1f24a79 5596
9f876f3d 5597 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5dcecbc9 5598 ret = mlx5_ib_query_ext_ppcnt_counters(dev, cnts, stats);
9f876f3d
TB		 5599 if (ret)
5600 return ret;
5601 }
5602
e1f24a79 5603 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
aac4492e
DJ		 5604 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
5605 &mdev_port_num);
5606 if (!mdev) {
5607 /* If port is not affiliated yet, its in down state
5608 * which doesn't have any counters yet, so it would be
5609 * zero. So no need to read from the HCA.
5610 */
5611 goto done;
5612 }
71a0ff65
MD		 5613 ret = mlx5_lag_query_cong_counters(dev->mdev,
5614 stats->value +
5dcecbc9
PP		 5615 cnts->num_q_counters,
5616 cnts->num_cong_counters,
5617 cnts->offsets +
5618 cnts->num_q_counters);
aac4492e
DJ		 5619
5620 mlx5_ib_put_native_port_mdev(dev, port_num);
e1f24a79
PP		 5621 if (ret)
5622 return ret;
e1f24a79
PP		 5623 }
5624
aac4492e 5625done:
e1f24a79 5626 return num_counters;
0ad17a8f
MB		 5627}
5628
18d422ce
MZ		 5629static struct rdma_hw_stats *
5630mlx5_ib_counter_alloc_stats(struct rdma_counter *counter)
5631{
5632 struct mlx5_ib_dev *dev = to_mdev(counter->device);
5dcecbc9 5633 const struct mlx5_ib_counters *cnts =
3e1f000f 5634 get_counters(dev, counter->port - 1);
18d422ce
MZ		 5635
5636 /* Q counters are in the beginning of all counters */
5dcecbc9
PP		 5637 return rdma_alloc_hw_stats_struct(cnts->names,
5638 cnts->num_q_counters,
18d422ce
MZ		 5639 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5640}
5641
5642static int mlx5_ib_counter_update_stats(struct rdma_counter *counter)
5643{
5644 struct mlx5_ib_dev *dev = to_mdev(counter->device);
3e1f000f
PP		 5645 const struct mlx5_ib_counters *cnts =
5646 get_counters(dev, counter->port - 1);
18d422ce 5647
5dcecbc9 5648 return mlx5_ib_query_q_counters(dev->mdev, cnts,
18d422ce
MZ		 5649 counter->stats, counter->id);
5650}
5651
45842fc6
MZ		 5652static int mlx5_ib_counter_bind_qp(struct rdma_counter *counter,
5653 struct ib_qp *qp)
5654{
5655 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5656 u16 cnt_set_id = 0;
5657 int err;
5658
5659 if (!counter->id) {
5660 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5661 &cnt_set_id,
5662 MLX5_SHARED_RESOURCE_UID);
5663 if (err)
5664 return err;
5665 counter->id = cnt_set_id;
5666 }
5667
5668 err = mlx5_ib_qp_set_counter(qp, counter);
5669 if (err)
5670 goto fail_set_counter;
5671
5672 return 0;
5673
5674fail_set_counter:
5675 mlx5_core_dealloc_q_counter(dev->mdev, cnt_set_id);
5676 counter->id = 0;
5677
5678 return err;
5679}
5680
5681static int mlx5_ib_counter_unbind_qp(struct ib_qp *qp)
5682{
5683 return mlx5_ib_qp_set_counter(qp, NULL);
5684}
5685
5686static int mlx5_ib_counter_dealloc(struct rdma_counter *counter)
5687{
5688 struct mlx5_ib_dev *dev = to_mdev(counter->device);
5689
5690 return mlx5_core_dealloc_q_counter(dev->mdev, counter->id);
5691}
5692
f6a8a19b
DD		 5693static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num,
5694 enum rdma_netdev_t type,
5695 struct rdma_netdev_alloc_params *params)
693dfd5a
ES		 5696{
5697 if (type != RDMA_NETDEV_IPOIB)
f6a8a19b 5698 return -EOPNOTSUPP;
693dfd5a 5699
f6a8a19b 5700 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
693dfd5a
ES		 5701}
5702
fe248c3a
MG		 5703static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
5704{
5705 if (!dev->delay_drop.dbg)
5706 return;
5707 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
5708 kfree(dev->delay_drop.dbg);
5709 dev->delay_drop.dbg = NULL;
5710}
5711
03404e8a
MG		 5712static void cancel_delay_drop(struct mlx5_ib_dev *dev)
5713{
5714 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5715 return;
5716
5717 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 5718 delay_drop_debugfs_cleanup(dev);
5719}
5720
5721static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5722 size_t count, loff_t *pos)
5723{
5724 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5725 char lbuf[20];
5726 int len;
5727
5728 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5729 return simple_read_from_buffer(buf, count, pos, lbuf, len);
5730}
5731
5732static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5733 size_t count, loff_t *pos)
5734{
5735 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5736 u32 timeout;
5737 u32 var;
5738
5739 if (kstrtouint_from_user(buf, count, 0, &var))
5740 return -EFAULT;
5741
5742 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5743 1000);
5744 if (timeout != var)
5745 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5746 timeout);
5747
5748 delay_drop->timeout = timeout;
5749
5750 return count;
5751}
5752
5753static const struct file_operations fops_delay_drop_timeout = {
5754 .owner = THIS_MODULE,
5755 .open = simple_open,
5756 .write = delay_drop_timeout_write,
5757 .read = delay_drop_timeout_read,
5758};
5759
5760static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5761{
5762 struct mlx5_ib_dbg_delay_drop *dbg;
5763
5764 if (!mlx5_debugfs_root)
5765 return 0;
5766
5767 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
5768 if (!dbg)
5769 return -ENOMEM;
5770
cbafad87
SM		 5771 dev->delay_drop.dbg = dbg;
5772
fe248c3a
MG		 5773 dbg->dir_debugfs =
5774 debugfs_create_dir("delay_drop",
5775 dev->mdev->priv.dbg_root);
5776 if (!dbg->dir_debugfs)
cbafad87 5777 goto out_debugfs;
fe248c3a
MG		 5778
5779 dbg->events_cnt_debugfs =
5780 debugfs_create_atomic_t("num_timeout_events", 0400,
5781 dbg->dir_debugfs,
5782 &dev->delay_drop.events_cnt);
5783 if (!dbg->events_cnt_debugfs)
5784 goto out_debugfs;
5785
5786 dbg->rqs_cnt_debugfs =
5787 debugfs_create_atomic_t("num_rqs", 0400,
5788 dbg->dir_debugfs,
5789 &dev->delay_drop.rqs_cnt);
5790 if (!dbg->rqs_cnt_debugfs)
5791 goto out_debugfs;
5792
5793 dbg->timeout_debugfs =
5794 debugfs_create_file("timeout", 0600,
5795 dbg->dir_debugfs,
5796 &dev->delay_drop,
5797 &fops_delay_drop_timeout);
5798 if (!dbg->timeout_debugfs)
5799 goto out_debugfs;
5800
5801 return 0;
5802
5803out_debugfs:
5804 delay_drop_debugfs_cleanup(dev);
5805 return -ENOMEM;
03404e8a
MG		 5806}
5807
5808static void init_delay_drop(struct mlx5_ib_dev *dev)
5809{
5810 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5811 return;
5812
5813 mutex_init(&dev->delay_drop.lock);
5814 dev->delay_drop.dev = dev;
5815 dev->delay_drop.activate = false;
5816 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5817 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 5818 atomic_set(&dev->delay_drop.rqs_cnt, 0);
5819 atomic_set(&dev->delay_drop.events_cnt, 0);
5820
5821 if (delay_drop_debugfs_init(dev))
5822 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
03404e8a
MG		 5823}
5824
32f69e4b
DJ		 5825static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5826 struct mlx5_ib_multiport_info *mpi)
5827{
5828 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5829 struct mlx5_ib_port *port = &ibdev->port[port_num];
5830 int comps;
5831 int err;
5832 int i;
5833
9dc4cfff
LR		 5834 lockdep_assert_held(&mlx5_ib_multiport_mutex);
5835
a9e546e7
PP		 5836 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5837
32f69e4b
DJ		 5838 spin_lock(&port->mp.mpi_lock);
5839 if (!mpi->ibdev) {
5840 spin_unlock(&port->mp.mpi_lock);
5841 return;
5842 }
df097a27 5843
32f69e4b
DJ		 5844 mpi->ibdev = NULL;
5845
5846 spin_unlock(&port->mp.mpi_lock);
23eaf3b5
LR		 5847 if (mpi->mdev_events.notifier_call)
5848 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
5849 mpi->mdev_events.notifier_call = NULL;
32f69e4b
DJ		 5850 mlx5_remove_netdev_notifier(ibdev, port_num);
5851 spin_lock(&port->mp.mpi_lock);
5852
5853 comps = mpi->mdev_refcnt;
5854 if (comps) {
5855 mpi->unaffiliate = true;
5856 init_completion(&mpi->unref_comp);
5857 spin_unlock(&port->mp.mpi_lock);
5858
5859 for (i = 0; i < comps; i++)
5860 wait_for_completion(&mpi->unref_comp);
5861
5862 spin_lock(&port->mp.mpi_lock);
5863 mpi->unaffiliate = false;
5864 }
5865
5866 port->mp.mpi = NULL;
5867
5868 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5869
5870 spin_unlock(&port->mp.mpi_lock);
5871
5872 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5873
5874 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5875 /* Log an error, still needed to cleanup the pointers and add
5876 * it back to the list.
5877 */
5878 if (err)
5879 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5880 port_num + 1);
5881
95579e78 5882 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
32f69e4b
DJ		 5883}
5884
32f69e4b
DJ		 5885static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5886 struct mlx5_ib_multiport_info *mpi)
5887{
5888 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5889 int err;
5890
9dc4cfff
LR		 5891 lockdep_assert_held(&mlx5_ib_multiport_mutex);
5892
32f69e4b
DJ		 5893 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5894 if (ibdev->port[port_num].mp.mpi) {
2577188e
QH		 5895 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
5896 port_num + 1);
32f69e4b
DJ		 5897 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5898 return false;
5899 }
5900
5901 ibdev->port[port_num].mp.mpi = mpi;
5902 mpi->ibdev = ibdev;
df097a27 5903 mpi->mdev_events.notifier_call = NULL;
32f69e4b
DJ		 5904 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5905
5906 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5907 if (err)
5908 goto unbind;
5909
5910 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5911 if (err)
5912 goto unbind;
5913
5914 err = mlx5_add_netdev_notifier(ibdev, port_num);
5915 if (err) {
5916 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5917 port_num + 1);
5918 goto unbind;
5919 }
5920
df097a27
SM		 5921 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
5922 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
5923
73eb8f03 5924 mlx5_ib_init_cong_debugfs(ibdev, port_num);
a9e546e7 5925
32f69e4b
DJ		 5926 return true;
5927
5928unbind:
5929 mlx5_ib_unbind_slave_port(ibdev, mpi);
5930 return false;
5931}
5932
5933static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5934{
5935 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5936 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5937 port_num + 1);
5938 struct mlx5_ib_multiport_info *mpi;
5939 int err;
5940 int i;
5941
5942 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5943 return 0;
5944
5945 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5946 &dev->sys_image_guid);
5947 if (err)
5948 return err;
5949
5950 err = mlx5_nic_vport_enable_roce(dev->mdev);
5951 if (err)
5952 return err;
5953
5954 mutex_lock(&mlx5_ib_multiport_mutex);
5955 for (i = 0; i < dev->num_ports; i++) {
5956 bool bound = false;
5957
5958 /* build a stub multiport info struct for the native port. */
5959 if (i == port_num) {
5960 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5961 if (!mpi) {
5962 mutex_unlock(&mlx5_ib_multiport_mutex);
5963 mlx5_nic_vport_disable_roce(dev->mdev);
5964 return -ENOMEM;
5965 }
5966
5967 mpi->is_master = true;
5968 mpi->mdev = dev->mdev;
5969 mpi->sys_image_guid = dev->sys_image_guid;
5970 dev->port[i].mp.mpi = mpi;
5971 mpi->ibdev = dev;
5972 mpi = NULL;
5973 continue;
5974 }
5975
5976 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5977 list) {
5978 if (dev->sys_image_guid == mpi->sys_image_guid &&
5979 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5980 bound = mlx5_ib_bind_slave_port(dev, mpi);
5981 }
5982
5983 if (bound) {
c42260f1
VP		 5984 dev_dbg(mpi->mdev->device,
5985 "removing port from unaffiliated list.\n");
32f69e4b
DJ		 5986 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5987 list_del(&mpi->list);
5988 break;
5989 }
5990 }
5991 if (!bound) {
5992 get_port_caps(dev, i + 1);
5993 mlx5_ib_dbg(dev, "no free port found for port %d\n",
5994 i + 1);
5995 }
5996 }
5997
5998 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
5999 mutex_unlock(&mlx5_ib_multiport_mutex);
6000 return err;
6001}
6002
6003static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
6004{
6005 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6006 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
6007 port_num + 1);
6008 int i;
6009
6010 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
6011 return;
6012
6013 mutex_lock(&mlx5_ib_multiport_mutex);
6014 for (i = 0; i < dev->num_ports; i++) {
6015 if (dev->port[i].mp.mpi) {
6016 /* Destroy the native port stub */
6017 if (i == port_num) {
6018 kfree(dev->port[i].mp.mpi);
6019 dev->port[i].mp.mpi = NULL;
6020 } else {
6021 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
6022 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
6023 }
6024 }
6025 }
6026
6027 mlx5_ib_dbg(dev, "removing from devlist\n");
6028 list_del(&dev->ib_dev_list);
6029 mutex_unlock(&mlx5_ib_multiport_mutex);
6030
6031 mlx5_nic_vport_disable_roce(dev->mdev);
6032}
6033
9a119cd5
JG		 6034ADD_UVERBS_ATTRIBUTES_SIMPLE(
6035 mlx5_ib_dm,
6036 UVERBS_OBJECT_DM,
6037 UVERBS_METHOD_DM_ALLOC,
6038 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
6039 UVERBS_ATTR_TYPE(u64),
83bb4442 6040 UA_MANDATORY),
9a119cd5
JG		 6041 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
6042 UVERBS_ATTR_TYPE(u16),
3b113a1e
AL		 6043 UA_OPTIONAL),
6044 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
6045 enum mlx5_ib_uapi_dm_type,
6046 UA_OPTIONAL));
9a119cd5
JG		 6047
6048ADD_UVERBS_ATTRIBUTES_SIMPLE(
6049 mlx5_ib_flow_action,
6050 UVERBS_OBJECT_FLOW_ACTION,
6051 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
bccd0622
JG		 6052 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
6053 enum mlx5_ib_uapi_flow_action_flags));
c6475a0b 6054
0cbf432d
JG		 6055static const struct uapi_definition mlx5_ib_defs[] = {
6056#if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)
36e235c8 6057 UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
0cbf432d
JG		 6058 UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
6059#endif
8c84660b 6060
0cbf432d
JG		 6061 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION,
6062 &mlx5_ib_flow_action),
6063 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm),
6064 {}
6065};
8c84660b 6066
1a1e03dc
RS		 6067static int mlx5_ib_read_counters(struct ib_counters *counters,
6068 struct ib_counters_read_attr *read_attr,
6069 struct uverbs_attr_bundle *attrs)
6070{
6071 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
6072 struct mlx5_read_counters_attr mread_attr = {};
6073 struct mlx5_ib_flow_counters_desc *desc;
6074 int ret, i;
6075
6076 mutex_lock(&mcounters->mcntrs_mutex);
6077 if (mcounters->cntrs_max_index > read_attr->ncounters) {
6078 ret = -EINVAL;
6079 goto err_bound;
6080 }
6081
6082 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
6083 GFP_KERNEL);
6084 if (!mread_attr.out) {
6085 ret = -ENOMEM;
6086 goto err_bound;
6087 }
6088
6089 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
6090 mread_attr.flags = read_attr->flags;
6091 ret = mcounters->read_counters(counters->device, &mread_attr);
6092 if (ret)
6093 goto err_read;
6094
6095 /* do the pass over the counters data array to assign according to the
6096 * descriptions and indexing pairs
6097 */
6098 desc = mcounters->counters_data;
6099 for (i = 0; i < mcounters->ncounters; i++)
6100 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
6101
6102err_read:
6103 kfree(mread_attr.out);
6104err_bound:
6105 mutex_unlock(&mcounters->mcntrs_mutex);
6106 return ret;
6107}
6108
b29e2a13
RS		 6109static int mlx5_ib_destroy_counters(struct ib_counters *counters)
6110{
6111 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
6112
3b3233fb
RS		 6113 counters_clear_description(counters);
6114 if (mcounters->hw_cntrs_hndl)
6115 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
6116 mcounters->hw_cntrs_hndl);
6117
b29e2a13
RS		 6118 kfree(mcounters);
6119
6120 return 0;
6121}
6122
6123static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
6124 struct uverbs_attr_bundle *attrs)
6125{
6126 struct mlx5_ib_mcounters *mcounters;
6127
6128 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
6129 if (!mcounters)
6130 return ERR_PTR(-ENOMEM);
6131
3b3233fb
RS		 6132 mutex_init(&mcounters->mcntrs_mutex);
6133
b29e2a13
RS		 6134 return &mcounters->ibcntrs;
6135}
6136
fb652d32 6137static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
e126ba97 6138{
25c13324
AL		 6139 struct mlx5_core_dev *mdev = dev->mdev;
6140
32f69e4b 6141 mlx5_ib_cleanup_multiport_master(dev);
13859d5d 6142 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
534fd7aa 6143 srcu_barrier(&dev->mr_srcu);
13859d5d 6144 cleanup_srcu_struct(&dev->mr_srcu);
13859d5d 6145 }
4056b12e
AL		 6146
6147 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
25c13324
AL		 6148
6149 WARN_ON(dev->dm.steering_sw_icm_alloc_blocks &&
6150 !bitmap_empty(
6151 dev->dm.steering_sw_icm_alloc_blocks,
6152 BIT(MLX5_CAP_DEV_MEM(mdev, log_steering_sw_icm_size) -
6153 MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev))));
6154
6155 kfree(dev->dm.steering_sw_icm_alloc_blocks);
6156
6157 WARN_ON(dev->dm.header_modify_sw_icm_alloc_blocks &&
6158 !bitmap_empty(dev->dm.header_modify_sw_icm_alloc_blocks,
6159 BIT(MLX5_CAP_DEV_MEM(
6160 mdev, log_header_modify_sw_icm_size) -
6161 MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev))));
6162
6163 kfree(dev->dm.header_modify_sw_icm_alloc_blocks);
16c1975f
MB		 6164}
6165
fb652d32 6166static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6167{
6168 struct mlx5_core_dev *mdev = dev->mdev;
25c13324
AL		 6169 u64 header_modify_icm_blocks = 0;
6170 u64 steering_icm_blocks = 0;
e126ba97 6171 int err;
32f69e4b 6172 int i;
e126ba97 6173
32f69e4b
DJ		 6174 for (i = 0; i < dev->num_ports; i++) {
6175 spin_lock_init(&dev->port[i].mp.mpi_lock);
95579e78 6176 rwlock_init(&dev->port[i].roce.netdev_lock);
d3b5cc1c
MB		 6177 dev->port[i].roce.dev = dev;
6178 dev->port[i].roce.native_port_num = i + 1;
6179 dev->port[i].roce.last_port_state = IB_PORT_DOWN;
32f69e4b
DJ		 6180 }
6181
00815752
MS		 6182 mlx5_ib_internal_fill_odp_caps(dev);
6183
32f69e4b 6184 err = mlx5_ib_init_multiport_master(dev);
e126ba97 6185 if (err)
da796ccb 6186 return err;
e126ba97 6187
a989ea01
MB		 6188 err = set_has_smi_cap(dev);
6189 if (err)
6190 return err;
e126ba97 6191
32f69e4b 6192 if (!mlx5_core_mp_enabled(mdev)) {
32f69e4b
DJ		 6193 for (i = 1; i <= dev->num_ports; i++) {
6194 err = get_port_caps(dev, i);
6195 if (err)
6196 break;
6197 }
6198 } else {
6199 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
6200 }
6201 if (err)
6202 goto err_mp;
6203
1b5daf11
MD		 6204 if (mlx5_use_mad_ifc(dev))
6205 get_ext_port_caps(dev);
e126ba97 6206
e126ba97 6207 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 6208 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
508562d6 6209 dev->ib_dev.phys_port_cnt = dev->num_ports;
f2f3df55 6210 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev);
c42260f1 6211 dev->ib_dev.dev.parent = mdev->device;
e126ba97 6212
3cc297db
MB		 6213 mutex_init(&dev->cap_mask_mutex);
6214 INIT_LIST_HEAD(&dev->qp_list);
6215 spin_lock_init(&dev->reset_flow_resource_lock);
6216
25c13324
AL		 6217 if (MLX5_CAP_GEN_64(mdev, general_obj_types) &
6218 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) {
6219 if (MLX5_CAP64_DEV_MEM(mdev, steering_sw_icm_start_address)) {
6220 steering_icm_blocks =
6221 BIT(MLX5_CAP_DEV_MEM(mdev,
6222 log_steering_sw_icm_size) -
6223 MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev));
6224
6225 dev->dm.steering_sw_icm_alloc_blocks =
6226 kcalloc(BITS_TO_LONGS(steering_icm_blocks),
6227 sizeof(unsigned long), GFP_KERNEL);
6228 if (!dev->dm.steering_sw_icm_alloc_blocks)
6229 goto err_mp;
6230 }
6231
6232 if (MLX5_CAP64_DEV_MEM(mdev,
6233 header_modify_sw_icm_start_address)) {
6234 header_modify_icm_blocks = BIT(
6235 MLX5_CAP_DEV_MEM(
6236 mdev, log_header_modify_sw_icm_size) -
6237 MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev));
6238
6239 dev->dm.header_modify_sw_icm_alloc_blocks =
6240 kcalloc(BITS_TO_LONGS(header_modify_icm_blocks),
6241 sizeof(unsigned long), GFP_KERNEL);
6242 if (!dev->dm.header_modify_sw_icm_alloc_blocks)
6243 goto err_dm;
6244 }
6245 }
6246
3b113a1e
AL		 6247 spin_lock_init(&dev->dm.lock);
6248 dev->dm.dev = mdev;
24da0016 6249
13859d5d 6250 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
13859d5d 6251 err = init_srcu_struct(&dev->mr_srcu);
a6bc3875 6252 if (err)
25c13324 6253 goto err_dm;
623d1543 6254 }
3cc297db 6255
16c1975f 6256 return 0;
25c13324
AL		 6257
6258err_dm:
6259 kfree(dev->dm.steering_sw_icm_alloc_blocks);
6260 kfree(dev->dm.header_modify_sw_icm_alloc_blocks);
6261
32f69e4b
DJ		 6262err_mp:
6263 mlx5_ib_cleanup_multiport_master(dev);
16c1975f 6264
16c1975f
MB		 6265 return -ENOMEM;
6266}
6267
9a4ca38d
MB		 6268static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
6269{
6270 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
6271
6272 if (!dev->flow_db)
6273 return -ENOMEM;
6274
6275 mutex_init(&dev->flow_db->lock);
6276
6277 return 0;
6278}
6279
6280static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
6281{
6282 kfree(dev->flow_db);
6283}
6284
96458233 6285static const struct ib_device_ops mlx5_ib_dev_ops = {
7a154142 6286 .owner = THIS_MODULE,
b9560a41 6287 .driver_id = RDMA_DRIVER_MLX5,
72c6ec18 6288 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
b9560a41 6289
96458233
KH		 6290 .add_gid = mlx5_ib_add_gid,
6291 .alloc_mr = mlx5_ib_alloc_mr,
6c984472 6292 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
96458233
KH		 6293 .alloc_pd = mlx5_ib_alloc_pd,
6294 .alloc_ucontext = mlx5_ib_alloc_ucontext,
6295 .attach_mcast = mlx5_ib_mcg_attach,
6296 .check_mr_status = mlx5_ib_check_mr_status,
6297 .create_ah = mlx5_ib_create_ah,
6298 .create_counters = mlx5_ib_create_counters,
6299 .create_cq = mlx5_ib_create_cq,
6300 .create_flow = mlx5_ib_create_flow,
6301 .create_qp = mlx5_ib_create_qp,
6302 .create_srq = mlx5_ib_create_srq,
6303 .dealloc_pd = mlx5_ib_dealloc_pd,
6304 .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
6305 .del_gid = mlx5_ib_del_gid,
6306 .dereg_mr = mlx5_ib_dereg_mr,
6307 .destroy_ah = mlx5_ib_destroy_ah,
6308 .destroy_counters = mlx5_ib_destroy_counters,
6309 .destroy_cq = mlx5_ib_destroy_cq,
6310 .destroy_flow = mlx5_ib_destroy_flow,
6311 .destroy_flow_action = mlx5_ib_destroy_flow_action,
6312 .destroy_qp = mlx5_ib_destroy_qp,
6313 .destroy_srq = mlx5_ib_destroy_srq,
6314 .detach_mcast = mlx5_ib_mcg_detach,
6315 .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
6316 .drain_rq = mlx5_ib_drain_rq,
6317 .drain_sq = mlx5_ib_drain_sq,
6318 .get_dev_fw_str = get_dev_fw_str,
6319 .get_dma_mr = mlx5_ib_get_dma_mr,
6320 .get_link_layer = mlx5_ib_port_link_layer,
6321 .map_mr_sg = mlx5_ib_map_mr_sg,
6c984472 6322 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi,
96458233
KH		 6323 .mmap = mlx5_ib_mmap,
6324 .modify_cq = mlx5_ib_modify_cq,
6325 .modify_device = mlx5_ib_modify_device,
6326 .modify_port = mlx5_ib_modify_port,
6327 .modify_qp = mlx5_ib_modify_qp,
6328 .modify_srq = mlx5_ib_modify_srq,
6329 .poll_cq = mlx5_ib_poll_cq,
6330 .post_recv = mlx5_ib_post_recv,
6331 .post_send = mlx5_ib_post_send,
6332 .post_srq_recv = mlx5_ib_post_srq_recv,
6333 .process_mad = mlx5_ib_process_mad,
6334 .query_ah = mlx5_ib_query_ah,
6335 .query_device = mlx5_ib_query_device,
6336 .query_gid = mlx5_ib_query_gid,
6337 .query_pkey = mlx5_ib_query_pkey,
6338 .query_qp = mlx5_ib_query_qp,
6339 .query_srq = mlx5_ib_query_srq,
6340 .read_counters = mlx5_ib_read_counters,
6341 .reg_user_mr = mlx5_ib_reg_user_mr,
6342 .req_notify_cq = mlx5_ib_arm_cq,
6343 .rereg_user_mr = mlx5_ib_rereg_user_mr,
6344 .resize_cq = mlx5_ib_resize_cq,
d3456914
LR		 6345
6346 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
e39afe3d 6347 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
21a428a0 6348 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
68e326de 6349 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
a2a074ef 6350 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
96458233
KH		 6351};
6352
6353static const struct ib_device_ops mlx5_ib_dev_flow_ipsec_ops = {
6354 .create_flow_action_esp = mlx5_ib_create_flow_action_esp,
6355 .modify_flow_action_esp = mlx5_ib_modify_flow_action_esp,
6356};
6357
6358static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
6359 .rdma_netdev_get_params = mlx5_ib_rn_get_params,
6360};
6361
6362static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
6363 .get_vf_config = mlx5_ib_get_vf_config,
6364 .get_vf_stats = mlx5_ib_get_vf_stats,
6365 .set_vf_guid = mlx5_ib_set_vf_guid,
6366 .set_vf_link_state = mlx5_ib_set_vf_link_state,
6367};
6368
6369static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
6370 .alloc_mw = mlx5_ib_alloc_mw,
6371 .dealloc_mw = mlx5_ib_dealloc_mw,
6372};
6373
6374static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
6375 .alloc_xrcd = mlx5_ib_alloc_xrcd,
6376 .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
6377};
6378
6379static const struct ib_device_ops mlx5_ib_dev_dm_ops = {
6380 .alloc_dm = mlx5_ib_alloc_dm,
6381 .dealloc_dm = mlx5_ib_dealloc_dm,
6382 .reg_dm_mr = mlx5_ib_reg_dm_mr,
6383};
6384
fb652d32 6385static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6386{
6387 struct mlx5_core_dev *mdev = dev->mdev;
16c1975f
MB		 6388 int err;
6389
e126ba97
EC		 6390 dev->ib_dev.uverbs_cmd_mask =
6391 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
6392 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
6393 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
6394 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
6395 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 6396 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
6397 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 6398 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 6399 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 6400 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
6401 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
6402 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
6403 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
6404 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
6405 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
6406 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
6407 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
6408 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
6409 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
6410 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
6411 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
6412 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
6413 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
6414 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
6415 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
6416 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 6417 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 6418 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
6419 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349 6420 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
b0e9df6d 6421 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
96458233
KH		 6422 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ) |
6423 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
6424 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
6425
f6a8a19b
DD		 6426 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
6427 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
96458233
KH		 6428 ib_set_device_ops(&dev->ib_dev,
6429 &mlx5_ib_dev_ipoib_enhanced_ops);
8e959601 6430
96458233
KH		 6431 if (mlx5_core_is_pf(mdev))
6432 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
7c2344c3 6433
6e8484c5
MG		 6434 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
6435
d2370e0a 6436 if (MLX5_CAP_GEN(mdev, imaicl)) {
d2370e0a
MB		 6437 dev->ib_dev.uverbs_cmd_mask |=
6438 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
6439 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
96458233 6440 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
d2370e0a
MB		 6441 }
6442
938fe83c 6443 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 6444 dev->ib_dev.uverbs_cmd_mask |=
6445 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
6446 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
96458233 6447 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
e126ba97
EC		 6448 }
6449
25c13324
AL		 6450 if (MLX5_CAP_DEV_MEM(mdev, memic) ||
6451 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
6452 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
96458233 6453 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
24da0016 6454
dfb631a1 6455 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
96458233
KH		 6456 MLX5_ACCEL_IPSEC_CAP_DEVICE)
6457 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_flow_ipsec_ops);
96458233 6458 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
81e30880 6459
36e235c8
JG		 6460 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
6461 dev->ib_dev.driver_def = mlx5_ib_defs;
81e30880 6462
e126ba97
EC		 6463 err = init_node_data(dev);
6464 if (err)
16c1975f 6465 return err;
e126ba97 6466
c8b89924 6467 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
e7996a9a
JG		 6468 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
6469 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
a560f1d9 6470 mutex_init(&dev->lb.mutex);
c8b89924 6471
96e2fd73
LR		 6472 dev->ib_dev.use_cq_dim = true;
6473
16c1975f
MB		 6474 return 0;
6475}
6476
96458233
KH		 6477static const struct ib_device_ops mlx5_ib_dev_port_ops = {
6478 .get_port_immutable = mlx5_port_immutable,
6479 .query_port = mlx5_ib_query_port,
6480};
6481
8e6efa3a
MB		 6482static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
6483{
96458233 6484 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
8e6efa3a
MB		 6485 return 0;
6486}
6487
96458233
KH		 6488static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
6489 .get_port_immutable = mlx5_port_rep_immutable,
6490 .query_port = mlx5_ib_rep_query_port,
6491};
6492
fb652d32 6493static int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
8e6efa3a 6494{
96458233 6495 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
8e6efa3a
MB		 6496 return 0;
6497}
6498
96458233
KH		 6499static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
6500 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
6501 .create_wq = mlx5_ib_create_wq,
6502 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
6503 .destroy_wq = mlx5_ib_destroy_wq,
6504 .get_netdev = mlx5_ib_get_netdev,
6505 .modify_wq = mlx5_ib_modify_wq,
6506};
6507
e3f1ed1f 6508static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
8e6efa3a 6509{
e3f1ed1f 6510 u8 port_num;
8e6efa3a 6511
8e6efa3a
MB		 6512 dev->ib_dev.uverbs_ex_cmd_mask |=
6513 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
6514 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
6515 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
6516 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
6517 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
96458233 6518 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
8e6efa3a 6519
e3f1ed1f
LR		 6520 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6521
26628e2d 6522 /* Register only for native ports */
8e6efa3a
MB		 6523 return mlx5_add_netdev_notifier(dev, port_num);
6524}
6525
6526static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
6527{
6528 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6529
6530 mlx5_remove_netdev_notifier(dev, port_num);
6531}
6532
fb652d32 6533static int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
8e6efa3a
MB		 6534{
6535 struct mlx5_core_dev *mdev = dev->mdev;
6536 enum rdma_link_layer ll;
6537 int port_type_cap;
6538 int err = 0;
8e6efa3a 6539
8e6efa3a
MB		 6540 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6541 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6542
6543 if (ll == IB_LINK_LAYER_ETHERNET)
e3f1ed1f 6544 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 6545
6546 return err;
6547}
6548
fb652d32 6549static void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
8e6efa3a
MB		 6550{
6551 mlx5_ib_stage_common_roce_cleanup(dev);
6552}
6553
16c1975f
MB		 6554static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
6555{
6556 struct mlx5_core_dev *mdev = dev->mdev;
6557 enum rdma_link_layer ll;
6558 int port_type_cap;
6559 int err;
6560
6561 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6562 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6563
fc24fc5e 6564 if (ll == IB_LINK_LAYER_ETHERNET) {
e3f1ed1f 6565 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 6566 if (err)
6567 return err;
7fd8aefb 6568
e3f1ed1f 6569 err = mlx5_enable_eth(dev);
fc24fc5e 6570 if (err)
8e6efa3a 6571 goto cleanup;
fc24fc5e
AS		 6572 }
6573
16c1975f 6574 return 0;
8e6efa3a
MB		 6575cleanup:
6576 mlx5_ib_stage_common_roce_cleanup(dev);
6577
6578 return err;
16c1975f 6579}
e126ba97 6580
16c1975f
MB		 6581static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
6582{
6583 struct mlx5_core_dev *mdev = dev->mdev;
6584 enum rdma_link_layer ll;
6585 int port_type_cap;
e126ba97 6586
16c1975f
MB		 6587 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6588 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6589
6590 if (ll == IB_LINK_LAYER_ETHERNET) {
6591 mlx5_disable_eth(dev);
8e6efa3a 6592 mlx5_ib_stage_common_roce_cleanup(dev);
45bded2c 6593 }
16c1975f 6594}
6aec21f6 6595
fb652d32 6596static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6597{
6598 return create_dev_resources(&dev->devr);
6599}
6600
fb652d32 6601static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6602{
6603 destroy_dev_resources(&dev->devr);
6604}
6605
6606static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
6607{
6608 return mlx5_ib_odp_init_one(dev);
6609}
4a2da0b8 6610
f3ffed0c 6611static void mlx5_ib_stage_odp_cleanup(struct mlx5_ib_dev *dev)
d5d284b8
SM		 6612{
6613 mlx5_ib_odp_cleanup_one(dev);
6614}
6615
96458233
KH		 6616static const struct ib_device_ops mlx5_ib_dev_hw_stats_ops = {
6617 .alloc_hw_stats = mlx5_ib_alloc_hw_stats,
6618 .get_hw_stats = mlx5_ib_get_hw_stats,
45842fc6
MZ		 6619 .counter_bind_qp = mlx5_ib_counter_bind_qp,
6620 .counter_unbind_qp = mlx5_ib_counter_unbind_qp,
6621 .counter_dealloc = mlx5_ib_counter_dealloc,
18d422ce
MZ		 6622 .counter_alloc_stats = mlx5_ib_counter_alloc_stats,
6623 .counter_update_stats = mlx5_ib_counter_update_stats,
96458233
KH		 6624};
6625
fb652d32 6626static int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
16c1975f 6627{
5e1e7612 6628 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
96458233 6629 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_hw_stats_ops);
5e1e7612
MB		 6630
6631 return mlx5_ib_alloc_counters(dev);
6632 }
16c1975f
MB		 6633
6634 return 0;
6635}
6636
fb652d32 6637static void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6638{
6639 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
6640 mlx5_ib_dealloc_counters(dev);
6641}
6642
6643static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
6644{
73eb8f03
GKH		 6645 mlx5_ib_init_cong_debugfs(dev,
6646 mlx5_core_native_port_num(dev->mdev) - 1);
6647 return 0;
16c1975f
MB		 6648}
6649
6650static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
6651{
a9e546e7
PP		 6652 mlx5_ib_cleanup_cong_debugfs(dev,
6653 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 6654}
6655
6656static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
6657{
5fe9dec0 6658 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
444261ca 6659 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
16c1975f
MB		 6660}
6661
6662static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
6663{
6664 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
6665}
6666
fb652d32 6667static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6668{
6669 int err;
5fe9dec0
EC		 6670
6671 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
6672 if (err)
16c1975f 6673 return err;
5fe9dec0
EC		 6674
6675 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
6676 if (err)
16c1975f 6677 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5fe9dec0 6678
16c1975f
MB		 6679 return err;
6680}
0837e86a 6681
fb652d32 6682static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6683{
6684 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6685 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
6686}
e126ba97 6687
fb652d32 6688static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
16c1975f 6689{
e349f858
JG		 6690 const char *name;
6691
508a523f 6692 rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group);
7c34ec19 6693 if (!mlx5_lag_is_roce(dev->mdev))
e349f858
JG		 6694 name = "mlx5_%d";
6695 else
6696 name = "mlx5_bond_%d";
ea4baf7f 6697 return ib_register_device(&dev->ib_dev, name);
16c1975f
MB		 6698}
6699
fb652d32 6700static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
16c1975f 6701{
42cea83f 6702 destroy_umrc_res(dev);
16c1975f
MB		 6703}
6704
fb652d32 6705static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
16c1975f 6706{
42cea83f 6707 ib_unregister_device(&dev->ib_dev);
16c1975f
MB		 6708}
6709
fb652d32 6710static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
16c1975f 6711{
42cea83f 6712 return create_umr_res(dev);
16c1975f
MB		 6713}
6714
6715static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
6716{
03404e8a
MG		 6717 init_delay_drop(dev);
6718
16c1975f
MB		 6719 return 0;
6720}
6721
6722static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
6723{
6724 cancel_delay_drop(dev);
6725}
6726
df097a27
SM		 6727static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
6728{
6729 dev->mdev_events.notifier_call = mlx5_ib_event;
6730 mlx5_notifier_register(dev->mdev, &dev->mdev_events);
6731 return 0;
6732}
6733
6734static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
6735{
6736 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
6737}
6738
81773ce5
LR		 6739static int mlx5_ib_stage_devx_init(struct mlx5_ib_dev *dev)
6740{
6741 int uid;
6742
fb98153b 6743 uid = mlx5_ib_devx_create(dev, false);
e337dd53 6744 if (uid > 0) {
81773ce5 6745 dev->devx_whitelist_uid = uid;
e337dd53
YH		 6746 mlx5_ib_devx_init_event_table(dev);
6747 }
81773ce5
LR		 6748
6749 return 0;
6750}
6751static void mlx5_ib_stage_devx_cleanup(struct mlx5_ib_dev *dev)
6752{
e337dd53
YH		 6753 if (dev->devx_whitelist_uid) {
6754 mlx5_ib_devx_cleanup_event_table(dev);
81773ce5 6755 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid);
e337dd53 6756 }
81773ce5
LR		 6757}
6758
b5ca15ad
MB		 6759void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
6760 const struct mlx5_ib_profile *profile,
6761 int stage)
16c1975f
MB		 6762{
6763 /* Number of stages to cleanup */
6764 while (stage) {
6765 stage--;
6766 if (profile->stage[stage].cleanup)
6767 profile->stage[stage].cleanup(dev);
6768 }
4a6dc855 6769
da796ccb 6770 kfree(dev->port);
4a6dc855 6771 ib_dealloc_device(&dev->ib_dev);
16c1975f 6772}
e126ba97 6773
b5ca15ad
MB		 6774void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
6775 const struct mlx5_ib_profile *profile)
16c1975f 6776{
16c1975f
MB		 6777 int err;
6778 int i;
5fe9dec0 6779
16c1975f
MB		 6780 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
6781 if (profile->stage[i].init) {
6782 err = profile->stage[i].init(dev);
6783 if (err)
6784 goto err_out;
6785 }
6786 }
0837e86a 6787
16c1975f
MB		 6788 dev->profile = profile;
6789 dev->ib_active = true;
6aec21f6 6790
16c1975f 6791 return dev;
e126ba97 6792
16c1975f
MB		 6793err_out:
6794 __mlx5_ib_remove(dev, profile, i);
fc24fc5e 6795
16c1975f
MB		 6796 return NULL;
6797}
0837e86a 6798
16c1975f
MB		 6799static const struct mlx5_ib_profile pf_profile = {
6800 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6801 mlx5_ib_stage_init_init,
6802 mlx5_ib_stage_init_cleanup),
9a4ca38d
MB		 6803 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6804 mlx5_ib_stage_flow_db_init,
6805 mlx5_ib_stage_flow_db_cleanup),
16c1975f
MB		 6806 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6807 mlx5_ib_stage_caps_init,
6808 NULL),
8e6efa3a
MB		 6809 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6810 mlx5_ib_stage_non_default_cb,
6811 NULL),
16c1975f
MB		 6812 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6813 mlx5_ib_stage_roce_init,
6814 mlx5_ib_stage_roce_cleanup),
f3da6577
LR		 6815 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6816 mlx5_init_srq_table,
6817 mlx5_cleanup_srq_table),
16c1975f
MB		 6818 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6819 mlx5_ib_stage_dev_res_init,
6820 mlx5_ib_stage_dev_res_cleanup),
df097a27
SM		 6821 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6822 mlx5_ib_stage_dev_notifier_init,
6823 mlx5_ib_stage_dev_notifier_cleanup),
16c1975f
MB		 6824 STAGE_CREATE(MLX5_IB_STAGE_ODP,
6825 mlx5_ib_stage_odp_init,
d5d284b8 6826 mlx5_ib_stage_odp_cleanup),
16c1975f
MB		 6827 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6828 mlx5_ib_stage_counters_init,
6829 mlx5_ib_stage_counters_cleanup),
6830 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
6831 mlx5_ib_stage_cong_debugfs_init,
6832 mlx5_ib_stage_cong_debugfs_cleanup),
6833 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6834 mlx5_ib_stage_uar_init,
6835 mlx5_ib_stage_uar_cleanup),
6836 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6837 mlx5_ib_stage_bfrag_init,
6838 mlx5_ib_stage_bfrag_cleanup),
42cea83f
MB		 6839 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6840 NULL,
6841 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
81773ce5
LR		 6842 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
6843 mlx5_ib_stage_devx_init,
6844 mlx5_ib_stage_devx_cleanup),
16c1975f
MB		 6845 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6846 mlx5_ib_stage_ib_reg_init,
6847 mlx5_ib_stage_ib_reg_cleanup),
42cea83f
MB		 6848 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6849 mlx5_ib_stage_post_ib_reg_umr_init,
6850 NULL),
16c1975f
MB		 6851 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
6852 mlx5_ib_stage_delay_drop_init,
6853 mlx5_ib_stage_delay_drop_cleanup),
16c1975f 6854};
e126ba97 6855
f0666f1f 6856const struct mlx5_ib_profile uplink_rep_profile = {
b5ca15ad
MB		 6857 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6858 mlx5_ib_stage_init_init,
6859 mlx5_ib_stage_init_cleanup),
6860 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6861 mlx5_ib_stage_flow_db_init,
6862 mlx5_ib_stage_flow_db_cleanup),
6863 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6864 mlx5_ib_stage_caps_init,
6865 NULL),
6866 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6867 mlx5_ib_stage_rep_non_default_cb,
6868 NULL),
6869 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6870 mlx5_ib_stage_rep_roce_init,
6871 mlx5_ib_stage_rep_roce_cleanup),
f3da6577
LR		 6872 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6873 mlx5_init_srq_table,
6874 mlx5_cleanup_srq_table),
b5ca15ad
MB		 6875 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6876 mlx5_ib_stage_dev_res_init,
6877 mlx5_ib_stage_dev_res_cleanup),
df097a27
SM		 6878 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6879 mlx5_ib_stage_dev_notifier_init,
6880 mlx5_ib_stage_dev_notifier_cleanup),
b5ca15ad
MB		 6881 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6882 mlx5_ib_stage_counters_init,
6883 mlx5_ib_stage_counters_cleanup),
6884 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6885 mlx5_ib_stage_uar_init,
6886 mlx5_ib_stage_uar_cleanup),
6887 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6888 mlx5_ib_stage_bfrag_init,
6889 mlx5_ib_stage_bfrag_cleanup),
03fe2deb
DM		 6890 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6891 NULL,
6892 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
7f575103
MB		 6893 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
6894 mlx5_ib_stage_devx_init,
6895 mlx5_ib_stage_devx_cleanup),
b5ca15ad
MB		 6896 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6897 mlx5_ib_stage_ib_reg_init,
6898 mlx5_ib_stage_ib_reg_cleanup),
03fe2deb
DM		 6899 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6900 mlx5_ib_stage_post_ib_reg_umr_init,
6901 NULL),
b5ca15ad
MB		 6902};
6903
e3f1ed1f 6904static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
32f69e4b
DJ		 6905{
6906 struct mlx5_ib_multiport_info *mpi;
6907 struct mlx5_ib_dev *dev;
6908 bool bound = false;
6909 int err;
6910
6911 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6912 if (!mpi)
6913 return NULL;
6914
6915 mpi->mdev = mdev;
6916
6917 err = mlx5_query_nic_vport_system_image_guid(mdev,
6918 &mpi->sys_image_guid);
6919 if (err) {
6920 kfree(mpi);
6921 return NULL;
6922 }
6923
6924 mutex_lock(&mlx5_ib_multiport_mutex);
6925 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
6926 if (dev->sys_image_guid == mpi->sys_image_guid)
6927 bound = mlx5_ib_bind_slave_port(dev, mpi);
6928
6929 if (bound) {
6930 rdma_roce_rescan_device(&dev->ib_dev);
6931 break;
6932 }
6933 }
6934
6935 if (!bound) {
6936 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
c42260f1
VP		 6937 dev_dbg(mdev->device,
6938 "no suitable IB device found to bind to, added to unaffiliated list.\n");
32f69e4b
DJ		 6939 }
6940 mutex_unlock(&mlx5_ib_multiport_mutex);
6941
6942 return mpi;
6943}
6944
16c1975f
MB		 6945static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
6946{
32f69e4b 6947 enum rdma_link_layer ll;
b5ca15ad 6948 struct mlx5_ib_dev *dev;
32f69e4b 6949 int port_type_cap;
da796ccb 6950 int num_ports;
32f69e4b 6951
b5ca15ad
MB		 6952 printk_once(KERN_INFO "%s", mlx5_version);
6953
f0666f1f 6954 if (MLX5_ESWITCH_MANAGER(mdev) &&
f6455de0 6955 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
5fb58c9e
MB		 6956 if (!mlx5_core_mp_enabled(mdev))
6957 mlx5_ib_register_vport_reps(mdev);
f0666f1f
BW		 6958 return mdev;
6959 }
6960
32f69e4b
DJ		 6961 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6962 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6963
e3f1ed1f
LR		 6964 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
6965 return mlx5_ib_add_slave_port(mdev);
32f69e4b 6966
da796ccb
MB		 6967 num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
6968 MLX5_CAP_GEN(mdev, num_vhca_ports));
459cc69f 6969 dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
b5ca15ad
MB		 6970 if (!dev)
6971 return NULL;
da796ccb
MB		 6972 dev->port = kcalloc(num_ports, sizeof(*dev->port),
6973 GFP_KERNEL);
6974 if (!dev->port) {
a5c9c299 6975 ib_dealloc_device(&dev->ib_dev);
da796ccb
MB		 6976 return NULL;
6977 }
b5ca15ad
MB		 6978
6979 dev->mdev = mdev;
da796ccb 6980 dev->num_ports = num_ports;
b5ca15ad 6981
b5ca15ad 6982 return __mlx5_ib_add(dev, &pf_profile);
e126ba97
EC		 6983}
6984
9603b61d 6985static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 6986{
32f69e4b
DJ		 6987 struct mlx5_ib_multiport_info *mpi;
6988 struct mlx5_ib_dev *dev;
6989
f0666f1f
BW		 6990 if (MLX5_ESWITCH_MANAGER(mdev) && context == mdev) {
6991 mlx5_ib_unregister_vport_reps(mdev);
6992 return;
6993 }
6994
32f69e4b
DJ		 6995 if (mlx5_core_is_mp_slave(mdev)) {
6996 mpi = context;
6997 mutex_lock(&mlx5_ib_multiport_mutex);
6998 if (mpi->ibdev)
6999 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
7000 list_del(&mpi->list);
7001 mutex_unlock(&mlx5_ib_multiport_mutex);
7002 return;
7003 }
6aec21f6 7004
32f69e4b 7005 dev = context;
f0666f1f 7006 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
e126ba97
EC		 7007}
7008
9603b61d
JM		 7009static struct mlx5_interface mlx5_ib_interface = {
7010 .add = mlx5_ib_add,
7011 .remove = mlx5_ib_remove,
64613d94 7012 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 7013};
7014
c44ef998
IL		 7015unsigned long mlx5_ib_get_xlt_emergency_page(void)
7016{
7017 mutex_lock(&xlt_emergency_page_mutex);
7018 return xlt_emergency_page;
7019}
7020
7021void mlx5_ib_put_xlt_emergency_page(void)
7022{
7023 mutex_unlock(&xlt_emergency_page_mutex);
7024}
7025
e126ba97
EC		 7026static int __init mlx5_ib_init(void)
7027{
6aec21f6
HE		 7028 int err;
7029
c44ef998
IL		 7030 xlt_emergency_page = __get_free_page(GFP_KERNEL);
7031 if (!xlt_emergency_page)
7032 return -ENOMEM;
7033
7034 mutex_init(&xlt_emergency_page_mutex);
7035
d69a24e0 7036 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
c44ef998
IL		 7037 if (!mlx5_ib_event_wq) {
7038 free_page(xlt_emergency_page);
d69a24e0 7039 return -ENOMEM;
c44ef998 7040 }
d69a24e0 7041
81713d37 7042 mlx5_ib_odp_init();
9603b61d 7043
6aec21f6 7044 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 7045
6aec21f6 7046 return err;
e126ba97
EC		 7047}
7048
7049static void __exit mlx5_ib_cleanup(void)
7050{
9603b61d 7051 mlx5_unregister_interface(&mlx5_ib_interface);
d69a24e0 7052 destroy_workqueue(mlx5_ib_event_wq);
c44ef998
IL		 7053 mutex_destroy(&xlt_emergency_page_mutex);
7054 free_page(xlt_emergency_page);
e126ba97
EC		 7055}
7056
7057module_init(mlx5_ib_init);
7058module_exit(mlx5_ib_cleanup);
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