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{net,IB}/mlx5: Modify QP commands via mlx5 ifc
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97
EC		 34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
37aa5c36
GL		 41#if defined(CONFIG_X86)
42#include <asm/pat.h>
43#endif
e126ba97 44#include <linux/sched.h>
7c2344c3 45#include <linux/delay.h>
e126ba97 46#include <rdma/ib_user_verbs.h>
3f89a643 47#include <rdma/ib_addr.h>
2811ba51 48#include <rdma/ib_cache.h>
ada68c31 49#include <linux/mlx5/port.h>
1b5daf11 50#include <linux/mlx5/vport.h>
7c2344c3 51#include <linux/list.h>
e126ba97
EC		 52#include <rdma/ib_smi.h>
53#include <rdma/ib_umem.h>
038d2ef8
MG		 54#include <linux/in.h>
55#include <linux/etherdevice.h>
56#include <linux/mlx5/fs.h>
e126ba97
EC		 57#include "user.h"
58#include "mlx5_ib.h"
59
60#define DRIVER_NAME "mlx5_ib"
169a1d85
AV		 61#define DRIVER_VERSION "2.2-1"
62#define DRIVER_RELDATE "Feb 2014"
e126ba97
EC		 63
64MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
65MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
66MODULE_LICENSE("Dual BSD/GPL");
67MODULE_VERSION(DRIVER_VERSION);
68
9603b61d
JM		 69static int deprecated_prof_sel = 2;
70module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
71MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
e126ba97
EC		 72
73static char mlx5_version[] =
74 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
75 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
76
da7525d2
EBE		 77enum {
78 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
79};
80
1b5daf11 81static enum rdma_link_layer
ebd61f68 82mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 83{
ebd61f68 84 switch (port_type_cap) {
1b5daf11
MD		 85 case MLX5_CAP_PORT_TYPE_IB:
86 return IB_LINK_LAYER_INFINIBAND;
87 case MLX5_CAP_PORT_TYPE_ETH:
88 return IB_LINK_LAYER_ETHERNET;
89 default:
90 return IB_LINK_LAYER_UNSPECIFIED;
91 }
92}
93
ebd61f68
AS		 94static enum rdma_link_layer
95mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
96{
97 struct mlx5_ib_dev *dev = to_mdev(device);
98 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
99
100 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
101}
102
fc24fc5e
AS		 103static int mlx5_netdev_event(struct notifier_block *this,
104 unsigned long event, void *ptr)
105{
106 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
107 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
108 roce.nb);
109
110 if ((event != NETDEV_UNREGISTER) && (event != NETDEV_REGISTER))
111 return NOTIFY_DONE;
112
113 write_lock(&ibdev->roce.netdev_lock);
114 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
115 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? NULL : ndev;
116 write_unlock(&ibdev->roce.netdev_lock);
117
118 return NOTIFY_DONE;
119}
120
121static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
122 u8 port_num)
123{
124 struct mlx5_ib_dev *ibdev = to_mdev(device);
125 struct net_device *ndev;
126
127 /* Ensure ndev does not disappear before we invoke dev_hold()
128 */
129 read_lock(&ibdev->roce.netdev_lock);
130 ndev = ibdev->roce.netdev;
131 if (ndev)
132 dev_hold(ndev);
133 read_unlock(&ibdev->roce.netdev_lock);
134
135 return ndev;
136}
137
3f89a643
AS		 138static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
139 struct ib_port_attr *props)
140{
141 struct mlx5_ib_dev *dev = to_mdev(device);
142 struct net_device *ndev;
143 enum ib_mtu ndev_ib_mtu;
c876a1b7 144 u16 qkey_viol_cntr;
3f89a643
AS		 145
146 memset(props, 0, sizeof(*props));
147
148 props->port_cap_flags |= IB_PORT_CM_SUP;
149 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
150
151 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
152 roce_address_table_size);
153 props->max_mtu = IB_MTU_4096;
154 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
155 props->pkey_tbl_len = 1;
156 props->state = IB_PORT_DOWN;
157 props->phys_state = 3;
158
c876a1b7
LR		 159 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
160 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643
AS		 161
162 ndev = mlx5_ib_get_netdev(device, port_num);
163 if (!ndev)
164 return 0;
165
166 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
167 props->state = IB_PORT_ACTIVE;
168 props->phys_state = 5;
169 }
170
171 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
172
173 dev_put(ndev);
174
175 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
176
177 props->active_width = IB_WIDTH_4X; /* TODO */
178 props->active_speed = IB_SPEED_QDR; /* TODO */
179
180 return 0;
181}
182
3cca2606
AS		 183static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
184 const struct ib_gid_attr *attr,
185 void *mlx5_addr)
186{
187#define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
188 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
189 source_l3_address);
190 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
191 source_mac_47_32);
192
193 if (!gid)
194 return;
195
196 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
197
198 if (is_vlan_dev(attr->ndev)) {
199 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
200 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
201 }
202
203 switch (attr->gid_type) {
204 case IB_GID_TYPE_IB:
205 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
206 break;
207 case IB_GID_TYPE_ROCE_UDP_ENCAP:
208 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
209 break;
210
211 default:
212 WARN_ON(true);
213 }
214
215 if (attr->gid_type != IB_GID_TYPE_IB) {
216 if (ipv6_addr_v4mapped((void *)gid))
217 MLX5_SET_RA(mlx5_addr, roce_l3_type,
218 MLX5_ROCE_L3_TYPE_IPV4);
219 else
220 MLX5_SET_RA(mlx5_addr, roce_l3_type,
221 MLX5_ROCE_L3_TYPE_IPV6);
222 }
223
224 if ((attr->gid_type == IB_GID_TYPE_IB) ||
225 !ipv6_addr_v4mapped((void *)gid))
226 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
227 else
228 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
229}
230
231static int set_roce_addr(struct ib_device *device, u8 port_num,
232 unsigned int index,
233 const union ib_gid *gid,
234 const struct ib_gid_attr *attr)
235{
236 struct mlx5_ib_dev *dev = to_mdev(device);
237 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)];
238 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)];
239 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
240 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
241
242 if (ll != IB_LINK_LAYER_ETHERNET)
243 return -EINVAL;
244
245 memset(in, 0, sizeof(in));
246
247 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
248
249 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
250 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
251
252 memset(out, 0, sizeof(out));
253 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
254}
255
256static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
257 unsigned int index, const union ib_gid *gid,
258 const struct ib_gid_attr *attr,
259 __always_unused void **context)
260{
261 return set_roce_addr(device, port_num, index, gid, attr);
262}
263
264static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
265 unsigned int index, __always_unused void **context)
266{
267 return set_roce_addr(device, port_num, index, NULL, NULL);
268}
269
2811ba51
AS		 270__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
271 int index)
272{
273 struct ib_gid_attr attr;
274 union ib_gid gid;
275
276 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
277 return 0;
278
279 if (!attr.ndev)
280 return 0;
281
282 dev_put(attr.ndev);
283
284 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
285 return 0;
286
287 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
288}
289
1b5daf11
MD		 290static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
291{
d603c809 292 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
1b5daf11
MD		 293}
294
295enum {
296 MLX5_VPORT_ACCESS_METHOD_MAD,
297 MLX5_VPORT_ACCESS_METHOD_HCA,
298 MLX5_VPORT_ACCESS_METHOD_NIC,
299};
300
301static int mlx5_get_vport_access_method(struct ib_device *ibdev)
302{
303 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
304 return MLX5_VPORT_ACCESS_METHOD_MAD;
305
ebd61f68 306 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 307 IB_LINK_LAYER_ETHERNET)
308 return MLX5_VPORT_ACCESS_METHOD_NIC;
309
310 return MLX5_VPORT_ACCESS_METHOD_HCA;
311}
312
da7525d2
EBE		 313static void get_atomic_caps(struct mlx5_ib_dev *dev,
314 struct ib_device_attr *props)
315{
316 u8 tmp;
317 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
318 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
319 u8 atomic_req_8B_endianness_mode =
320 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
321
322 /* Check if HW supports 8 bytes standard atomic operations and capable
323 * of host endianness respond
324 */
325 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
326 if (((atomic_operations & tmp) == tmp) &&
327 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
328 (atomic_req_8B_endianness_mode)) {
329 props->atomic_cap = IB_ATOMIC_HCA;
330 } else {
331 props->atomic_cap = IB_ATOMIC_NONE;
332 }
333}
334
1b5daf11
MD		 335static int mlx5_query_system_image_guid(struct ib_device *ibdev,
336 __be64 *sys_image_guid)
337{
338 struct mlx5_ib_dev *dev = to_mdev(ibdev);
339 struct mlx5_core_dev *mdev = dev->mdev;
340 u64 tmp;
341 int err;
342
343 switch (mlx5_get_vport_access_method(ibdev)) {
344 case MLX5_VPORT_ACCESS_METHOD_MAD:
345 return mlx5_query_mad_ifc_system_image_guid(ibdev,
346 sys_image_guid);
347
348 case MLX5_VPORT_ACCESS_METHOD_HCA:
349 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 350 break;
351
352 case MLX5_VPORT_ACCESS_METHOD_NIC:
353 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
354 break;
1b5daf11
MD		 355
356 default:
357 return -EINVAL;
358 }
3f89a643
AS		 359
360 if (!err)
361 *sys_image_guid = cpu_to_be64(tmp);
362
363 return err;
364
1b5daf11
MD		 365}
366
367static int mlx5_query_max_pkeys(struct ib_device *ibdev,
368 u16 *max_pkeys)
369{
370 struct mlx5_ib_dev *dev = to_mdev(ibdev);
371 struct mlx5_core_dev *mdev = dev->mdev;
372
373 switch (mlx5_get_vport_access_method(ibdev)) {
374 case MLX5_VPORT_ACCESS_METHOD_MAD:
375 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
376
377 case MLX5_VPORT_ACCESS_METHOD_HCA:
378 case MLX5_VPORT_ACCESS_METHOD_NIC:
379 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
380 pkey_table_size));
381 return 0;
382
383 default:
384 return -EINVAL;
385 }
386}
387
388static int mlx5_query_vendor_id(struct ib_device *ibdev,
389 u32 *vendor_id)
390{
391 struct mlx5_ib_dev *dev = to_mdev(ibdev);
392
393 switch (mlx5_get_vport_access_method(ibdev)) {
394 case MLX5_VPORT_ACCESS_METHOD_MAD:
395 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
396
397 case MLX5_VPORT_ACCESS_METHOD_HCA:
398 case MLX5_VPORT_ACCESS_METHOD_NIC:
399 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
400
401 default:
402 return -EINVAL;
403 }
404}
405
406static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
407 __be64 *node_guid)
408{
409 u64 tmp;
410 int err;
411
412 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
413 case MLX5_VPORT_ACCESS_METHOD_MAD:
414 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
415
416 case MLX5_VPORT_ACCESS_METHOD_HCA:
417 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 418 break;
419
420 case MLX5_VPORT_ACCESS_METHOD_NIC:
421 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
422 break;
1b5daf11
MD		 423
424 default:
425 return -EINVAL;
426 }
3f89a643
AS		 427
428 if (!err)
429 *node_guid = cpu_to_be64(tmp);
430
431 return err;
1b5daf11
MD		 432}
433
434struct mlx5_reg_node_desc {
435 u8 desc[64];
436};
437
438static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
439{
440 struct mlx5_reg_node_desc in;
441
442 if (mlx5_use_mad_ifc(dev))
443 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
444
445 memset(&in, 0, sizeof(in));
446
447 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
448 sizeof(struct mlx5_reg_node_desc),
449 MLX5_REG_NODE_DESC, 0, 0);
450}
451
e126ba97 452static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 453 struct ib_device_attr *props,
454 struct ib_udata *uhw)
e126ba97
EC		 455{
456 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 457 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 458 int err = -ENOMEM;
459 int max_rq_sg;
460 int max_sq_sg;
e0238a6a 461 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
402ca536
BW		 462 struct mlx5_ib_query_device_resp resp = {};
463 size_t resp_len;
464 u64 max_tso;
e126ba97 465
402ca536
BW		 466 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
467 if (uhw->outlen && uhw->outlen < resp_len)
468 return -EINVAL;
469 else
470 resp.response_length = resp_len;
471
472 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 473 return -EINVAL;
474
1b5daf11
MD		 475 memset(props, 0, sizeof(*props));
476 err = mlx5_query_system_image_guid(ibdev,
477 &props->sys_image_guid);
478 if (err)
479 return err;
e126ba97 480
1b5daf11 481 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 482 if (err)
1b5daf11 483 return err;
e126ba97 484
1b5daf11
MD		 485 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
486 if (err)
487 return err;
e126ba97 488
9603b61d
JM		 489 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
490 (fw_rev_min(dev->mdev) << 16) |
491 fw_rev_sub(dev->mdev);
e126ba97
EC		 492 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
493 IB_DEVICE_PORT_ACTIVE_EVENT |
494 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 495 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 496
497 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 498 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 499 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 500 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 501 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 502 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 503 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 504 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 505 if (MLX5_CAP_GEN(mdev, imaicl)) {
506 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
507 IB_DEVICE_MEM_WINDOW_TYPE_2B;
508 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 509 /* We support 'Gappy' memory registration too */
510 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 511 }
e126ba97 512 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 513 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 514 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
515 /* At this stage no support for signature handover */
516 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
517 IB_PROT_T10DIF_TYPE_2 |
518 IB_PROT_T10DIF_TYPE_3;
519 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
520 IB_GUARD_T10DIF_CSUM;
521 }
938fe83c 522 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 523 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 524
402ca536
BW		 525 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
526 if (MLX5_CAP_ETH(mdev, csum_cap))
88115fe7
BW		 527 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
528
402ca536
BW		 529 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
530 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
531 if (max_tso) {
532 resp.tso_caps.max_tso = 1 << max_tso;
533 resp.tso_caps.supported_qpts |=
534 1 << IB_QPT_RAW_PACKET;
535 resp.response_length += sizeof(resp.tso_caps);
536 }
537 }
538 }
539
f0313965
ES		 540 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
541 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
542 props->device_cap_flags |= IB_DEVICE_UD_TSO;
543 }
544
cff5a0f3
MD		 545 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
546 MLX5_CAP_ETH(dev->mdev, scatter_fcs))
547 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
548
da6d6ba3
MG		 549 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
550 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
551
1b5daf11
MD		 552 props->vendor_part_id = mdev->pdev->device;
553 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 554
555 props->max_mr_size = ~0ull;
e0238a6a 556 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 557 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
558 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
559 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
560 sizeof(struct mlx5_wqe_data_seg);
561 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
562 sizeof(struct mlx5_wqe_ctrl_seg)) /
563 sizeof(struct mlx5_wqe_data_seg);
e126ba97 564 props->max_sge = min(max_rq_sg, max_sq_sg);
986ef95e 565 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 566 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 567 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 568 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
569 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
570 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
571 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
572 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
573 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
574 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 575 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 576 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 577 props->max_fast_reg_page_list_len =
578 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
da7525d2 579 get_atomic_caps(dev, props);
81bea28f 580 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 581 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
582 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 583 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
584 props->max_mcast_grp;
585 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
7c60bcbb
MB		 586 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
587 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 588
8cdd312c 589#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 590 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 591 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
592 props->odp_caps = dev->odp_caps;
593#endif
594
051f2630
LR		 595 if (MLX5_CAP_GEN(mdev, cd))
596 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
597
eff901d3
EC		 598 if (!mlx5_core_is_pf(mdev))
599 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
600
402ca536
BW		 601 if (uhw->outlen) {
602 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
603
604 if (err)
605 return err;
606 }
607
1b5daf11 608 return 0;
e126ba97
EC		 609}
610
1b5daf11
MD		 611enum mlx5_ib_width {
612 MLX5_IB_WIDTH_1X = 1 << 0,
613 MLX5_IB_WIDTH_2X = 1 << 1,
614 MLX5_IB_WIDTH_4X = 1 << 2,
615 MLX5_IB_WIDTH_8X = 1 << 3,
616 MLX5_IB_WIDTH_12X = 1 << 4
617};
618
619static int translate_active_width(struct ib_device *ibdev, u8 active_width,
620 u8 *ib_width)
e126ba97
EC		 621{
622 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 623 int err = 0;
624
625 if (active_width & MLX5_IB_WIDTH_1X) {
626 *ib_width = IB_WIDTH_1X;
627 } else if (active_width & MLX5_IB_WIDTH_2X) {
628 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
629 (int)active_width);
630 err = -EINVAL;
631 } else if (active_width & MLX5_IB_WIDTH_4X) {
632 *ib_width = IB_WIDTH_4X;
633 } else if (active_width & MLX5_IB_WIDTH_8X) {
634 *ib_width = IB_WIDTH_8X;
635 } else if (active_width & MLX5_IB_WIDTH_12X) {
636 *ib_width = IB_WIDTH_12X;
637 } else {
638 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
639 (int)active_width);
640 err = -EINVAL;
e126ba97
EC		 641 }
642
1b5daf11
MD		 643 return err;
644}
e126ba97 645
1b5daf11
MD		 646static int mlx5_mtu_to_ib_mtu(int mtu)
647{
648 switch (mtu) {
649 case 256: return 1;
650 case 512: return 2;
651 case 1024: return 3;
652 case 2048: return 4;
653 case 4096: return 5;
654 default:
655 pr_warn("invalid mtu\n");
656 return -1;
e126ba97 657 }
1b5daf11 658}
e126ba97 659
1b5daf11
MD		 660enum ib_max_vl_num {
661 __IB_MAX_VL_0 = 1,
662 __IB_MAX_VL_0_1 = 2,
663 __IB_MAX_VL_0_3 = 3,
664 __IB_MAX_VL_0_7 = 4,
665 __IB_MAX_VL_0_14 = 5,
666};
e126ba97 667
1b5daf11
MD		 668enum mlx5_vl_hw_cap {
669 MLX5_VL_HW_0 = 1,
670 MLX5_VL_HW_0_1 = 2,
671 MLX5_VL_HW_0_2 = 3,
672 MLX5_VL_HW_0_3 = 4,
673 MLX5_VL_HW_0_4 = 5,
674 MLX5_VL_HW_0_5 = 6,
675 MLX5_VL_HW_0_6 = 7,
676 MLX5_VL_HW_0_7 = 8,
677 MLX5_VL_HW_0_14 = 15
678};
e126ba97 679
1b5daf11
MD		 680static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
681 u8 *max_vl_num)
682{
683 switch (vl_hw_cap) {
684 case MLX5_VL_HW_0:
685 *max_vl_num = __IB_MAX_VL_0;
686 break;
687 case MLX5_VL_HW_0_1:
688 *max_vl_num = __IB_MAX_VL_0_1;
689 break;
690 case MLX5_VL_HW_0_3:
691 *max_vl_num = __IB_MAX_VL_0_3;
692 break;
693 case MLX5_VL_HW_0_7:
694 *max_vl_num = __IB_MAX_VL_0_7;
695 break;
696 case MLX5_VL_HW_0_14:
697 *max_vl_num = __IB_MAX_VL_0_14;
698 break;
e126ba97 699
1b5daf11
MD		 700 default:
701 return -EINVAL;
e126ba97 702 }
e126ba97 703
1b5daf11 704 return 0;
e126ba97
EC		 705}
706
1b5daf11
MD		 707static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
708 struct ib_port_attr *props)
e126ba97 709{
1b5daf11
MD		 710 struct mlx5_ib_dev *dev = to_mdev(ibdev);
711 struct mlx5_core_dev *mdev = dev->mdev;
712 struct mlx5_hca_vport_context *rep;
046339ea
SM		 713 u16 max_mtu;
714 u16 oper_mtu;
1b5daf11
MD		 715 int err;
716 u8 ib_link_width_oper;
717 u8 vl_hw_cap;
e126ba97 718
1b5daf11
MD		 719 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
720 if (!rep) {
721 err = -ENOMEM;
e126ba97 722 goto out;
e126ba97 723 }
e126ba97 724
1b5daf11 725 memset(props, 0, sizeof(*props));
e126ba97 726
1b5daf11 727 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 728 if (err)
729 goto out;
730
1b5daf11
MD		 731 props->lid = rep->lid;
732 props->lmc = rep->lmc;
733 props->sm_lid = rep->sm_lid;
734 props->sm_sl = rep->sm_sl;
735 props->state = rep->vport_state;
736 props->phys_state = rep->port_physical_state;
737 props->port_cap_flags = rep->cap_mask1;
738 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
739 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
740 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
741 props->bad_pkey_cntr = rep->pkey_violation_counter;
742 props->qkey_viol_cntr = rep->qkey_violation_counter;
743 props->subnet_timeout = rep->subnet_timeout;
744 props->init_type_reply = rep->init_type_reply;
eff901d3 745 props->grh_required = rep->grh_required;
e126ba97 746
1b5daf11
MD		 747 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
748 if (err)
e126ba97 749 goto out;
e126ba97 750
1b5daf11
MD		 751 err = translate_active_width(ibdev, ib_link_width_oper,
752 &props->active_width);
753 if (err)
754 goto out;
755 err = mlx5_query_port_proto_oper(mdev, &props->active_speed, MLX5_PTYS_IB,
756 port);
e126ba97
EC		 757 if (err)
758 goto out;
759
facc9699 760 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 761
1b5daf11 762 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 763
facc9699 764 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 765
1b5daf11 766 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 767
1b5daf11
MD		 768 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
769 if (err)
770 goto out;
e126ba97 771
1b5daf11
MD		 772 err = translate_max_vl_num(ibdev, vl_hw_cap,
773 &props->max_vl_num);
e126ba97 774out:
1b5daf11 775 kfree(rep);
e126ba97
EC		 776 return err;
777}
778
1b5daf11
MD		 779int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
780 struct ib_port_attr *props)
e126ba97 781{
1b5daf11
MD		 782 switch (mlx5_get_vport_access_method(ibdev)) {
783 case MLX5_VPORT_ACCESS_METHOD_MAD:
784 return mlx5_query_mad_ifc_port(ibdev, port, props);
e126ba97 785
1b5daf11
MD		 786 case MLX5_VPORT_ACCESS_METHOD_HCA:
787 return mlx5_query_hca_port(ibdev, port, props);
e126ba97 788
3f89a643
AS		 789 case MLX5_VPORT_ACCESS_METHOD_NIC:
790 return mlx5_query_port_roce(ibdev, port, props);
791
1b5daf11
MD		 792 default:
793 return -EINVAL;
794 }
795}
e126ba97 796
1b5daf11
MD		 797static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
798 union ib_gid *gid)
799{
800 struct mlx5_ib_dev *dev = to_mdev(ibdev);
801 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 802
1b5daf11
MD		 803 switch (mlx5_get_vport_access_method(ibdev)) {
804 case MLX5_VPORT_ACCESS_METHOD_MAD:
805 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 806
1b5daf11
MD		 807 case MLX5_VPORT_ACCESS_METHOD_HCA:
808 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
809
810 default:
811 return -EINVAL;
812 }
e126ba97 813
e126ba97
EC		 814}
815
1b5daf11
MD		 816static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
817 u16 *pkey)
818{
819 struct mlx5_ib_dev *dev = to_mdev(ibdev);
820 struct mlx5_core_dev *mdev = dev->mdev;
821
822 switch (mlx5_get_vport_access_method(ibdev)) {
823 case MLX5_VPORT_ACCESS_METHOD_MAD:
824 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
825
826 case MLX5_VPORT_ACCESS_METHOD_HCA:
827 case MLX5_VPORT_ACCESS_METHOD_NIC:
828 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
829 pkey);
830 default:
831 return -EINVAL;
832 }
833}
e126ba97
EC		 834
835static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
836 struct ib_device_modify *props)
837{
838 struct mlx5_ib_dev *dev = to_mdev(ibdev);
839 struct mlx5_reg_node_desc in;
840 struct mlx5_reg_node_desc out;
841 int err;
842
843 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
844 return -EOPNOTSUPP;
845
846 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
847 return 0;
848
849 /*
850 * If possible, pass node desc to FW, so it can generate
851 * a 144 trap. If cmd fails, just ignore.
852 */
853 memcpy(&in, props->node_desc, 64);
9603b61d 854 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 855 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
856 if (err)
857 return err;
858
859 memcpy(ibdev->node_desc, props->node_desc, 64);
860
861 return err;
862}
863
864static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
865 struct ib_port_modify *props)
866{
867 struct mlx5_ib_dev *dev = to_mdev(ibdev);
868 struct ib_port_attr attr;
869 u32 tmp;
870 int err;
871
872 mutex_lock(&dev->cap_mask_mutex);
873
874 err = mlx5_ib_query_port(ibdev, port, &attr);
875 if (err)
876 goto out;
877
878 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
879 ~props->clr_port_cap_mask;
880
9603b61d 881 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 882
883out:
884 mutex_unlock(&dev->cap_mask_mutex);
885 return err;
886}
887
888static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
889 struct ib_udata *udata)
890{
891 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 892 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
893 struct mlx5_ib_alloc_ucontext_resp resp = {};
e126ba97
EC		 894 struct mlx5_ib_ucontext *context;
895 struct mlx5_uuar_info *uuari;
896 struct mlx5_uar *uars;
c1be5232 897 int gross_uuars;
e126ba97 898 int num_uars;
78c0f98c 899 int ver;
e126ba97
EC		 900 int uuarn;
901 int err;
902 int i;
f241e749 903 size_t reqlen;
a168a41c
MD		 904 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
905 max_cqe_version);
e126ba97
EC		 906
907 if (!dev->ib_active)
908 return ERR_PTR(-EAGAIN);
909
dfbee859
HA		 910 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
911 return ERR_PTR(-EINVAL);
912
78c0f98c
EC		 913 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
914 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
915 ver = 0;
a168a41c 916 else if (reqlen >= min_req_v2)
78c0f98c
EC		 917 ver = 2;
918 else
919 return ERR_PTR(-EINVAL);
920
b368d7cb 921 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
e126ba97
EC		 922 if (err)
923 return ERR_PTR(err);
924
b368d7cb 925 if (req.flags)
78c0f98c
EC		 926 return ERR_PTR(-EINVAL);
927
e126ba97
EC		 928 if (req.total_num_uuars > MLX5_MAX_UUARS)
929 return ERR_PTR(-ENOMEM);
930
931 if (req.total_num_uuars == 0)
932 return ERR_PTR(-EINVAL);
933
f72300c5 934 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 935 return ERR_PTR(-EOPNOTSUPP);
936
937 if (reqlen > sizeof(req) &&
938 !ib_is_udata_cleared(udata, sizeof(req),
dfbee859 939 reqlen - sizeof(req)))
b368d7cb
MB		 940 return ERR_PTR(-EOPNOTSUPP);
941
c1be5232
EC		 942 req.total_num_uuars = ALIGN(req.total_num_uuars,
943 MLX5_NON_FP_BF_REGS_PER_PAGE);
e126ba97
EC		 944 if (req.num_low_latency_uuars > req.total_num_uuars - 1)
945 return ERR_PTR(-EINVAL);
946
c1be5232
EC		 947 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
948 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
938fe83c 949 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 950 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
951 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
938fe83c
SM		 952 resp.cache_line_size = L1_CACHE_BYTES;
953 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
954 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
955 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
956 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
957 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 958 resp.cqe_version = min_t(__u8,
959 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
960 req.max_cqe_version);
b368d7cb
MB		 961 resp.response_length = min(offsetof(typeof(resp), response_length) +
962 sizeof(resp.response_length), udata->outlen);
e126ba97
EC		 963
964 context = kzalloc(sizeof(*context), GFP_KERNEL);
965 if (!context)
966 return ERR_PTR(-ENOMEM);
967
968 uuari = &context->uuari;
969 mutex_init(&uuari->lock);
970 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
971 if (!uars) {
972 err = -ENOMEM;
973 goto out_ctx;
974 }
975
c1be5232 976 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
e126ba97
EC		 977 sizeof(*uuari->bitmap),
978 GFP_KERNEL);
979 if (!uuari->bitmap) {
980 err = -ENOMEM;
981 goto out_uar_ctx;
982 }
983 /*
984 * clear all fast path uuars
985 */
c1be5232 986 for (i = 0; i < gross_uuars; i++) {
e126ba97
EC		 987 uuarn = i & 3;
988 if (uuarn == 2 || uuarn == 3)
989 set_bit(i, uuari->bitmap);
990 }
991
c1be5232 992 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
e126ba97
EC		 993 if (!uuari->count) {
994 err = -ENOMEM;
995 goto out_bitmap;
996 }
997
998 for (i = 0; i < num_uars; i++) {
9603b61d 999 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
e126ba97
EC		 1000 if (err)
1001 goto out_count;
1002 }
1003
b4cfe447
HE		 1004#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1005 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1006#endif
1007
146d2f1a 1008 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1009 err = mlx5_core_alloc_transport_domain(dev->mdev,
1010 &context->tdn);
1011 if (err)
1012 goto out_uars;
1013 }
1014
7c2344c3 1015 INIT_LIST_HEAD(&context->vma_private_list);
e126ba97
EC		 1016 INIT_LIST_HEAD(&context->db_page_list);
1017 mutex_init(&context->db_page_mutex);
1018
1019 resp.tot_uuars = req.total_num_uuars;
938fe83c 1020 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
b368d7cb 1021
f72300c5
HA		 1022 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1023 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1024
402ca536
BW		 1025 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1026 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE;
1027 resp.response_length += sizeof(resp.cmds_supp_uhw);
1028 }
1029
bc5c6eed
NO		 1030 /*
1031 * We don't want to expose information from the PCI bar that is located
1032 * after 4096 bytes, so if the arch only supports larger pages, let's
1033 * pretend we don't support reading the HCA's core clock. This is also
1034 * forced by mmap function.
1035 */
1036 if (PAGE_SIZE <= 4096 &&
1037 field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
b368d7cb
MB		 1038 resp.comp_mask |=
1039 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1040 resp.hca_core_clock_offset =
1041 offsetof(struct mlx5_init_seg, internal_timer_h) %
1042 PAGE_SIZE;
f72300c5 1043 resp.response_length += sizeof(resp.hca_core_clock_offset) +
402ca536 1044 sizeof(resp.reserved2);
b368d7cb
MB		 1045 }
1046
1047 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1048 if (err)
146d2f1a 1049 goto out_td;
e126ba97 1050
78c0f98c 1051 uuari->ver = ver;
e126ba97
EC		 1052 uuari->num_low_latency_uuars = req.num_low_latency_uuars;
1053 uuari->uars = uars;
1054 uuari->num_uars = num_uars;
f72300c5
HA		 1055 context->cqe_version = resp.cqe_version;
1056
e126ba97
EC		 1057 return &context->ibucontext;
1058
146d2f1a 1059out_td:
1060 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1061 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1062
e126ba97
EC		 1063out_uars:
1064 for (i--; i >= 0; i--)
9603b61d 1065 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
e126ba97
EC		 1066out_count:
1067 kfree(uuari->count);
1068
1069out_bitmap:
1070 kfree(uuari->bitmap);
1071
1072out_uar_ctx:
1073 kfree(uars);
1074
1075out_ctx:
1076 kfree(context);
1077 return ERR_PTR(err);
1078}
1079
1080static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1081{
1082 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1083 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1084 struct mlx5_uuar_info *uuari = &context->uuari;
1085 int i;
1086
146d2f1a 1087 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1088 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1089
e126ba97 1090 for (i = 0; i < uuari->num_uars; i++) {
9603b61d 1091 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
e126ba97
EC		 1092 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
1093 }
1094
1095 kfree(uuari->count);
1096 kfree(uuari->bitmap);
1097 kfree(uuari->uars);
1098 kfree(context);
1099
1100 return 0;
1101}
1102
1103static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1104{
9603b61d 1105 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
e126ba97
EC		 1106}
1107
1108static int get_command(unsigned long offset)
1109{
1110 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1111}
1112
1113static int get_arg(unsigned long offset)
1114{
1115 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1116}
1117
1118static int get_index(unsigned long offset)
1119{
1120 return get_arg(offset);
1121}
1122
7c2344c3
MG		 1123static void mlx5_ib_vma_open(struct vm_area_struct *area)
1124{
1125 /* vma_open is called when a new VMA is created on top of our VMA. This
1126 * is done through either mremap flow or split_vma (usually due to
1127 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1128 * as this VMA is strongly hardware related. Therefore we set the
1129 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1130 * calling us again and trying to do incorrect actions. We assume that
1131 * the original VMA size is exactly a single page, and therefore all
1132 * "splitting" operation will not happen to it.
1133 */
1134 area->vm_ops = NULL;
1135}
1136
1137static void mlx5_ib_vma_close(struct vm_area_struct *area)
1138{
1139 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1140
1141 /* It's guaranteed that all VMAs opened on a FD are closed before the
1142 * file itself is closed, therefore no sync is needed with the regular
1143 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1144 * However need a sync with accessing the vma as part of
1145 * mlx5_ib_disassociate_ucontext.
1146 * The close operation is usually called under mm->mmap_sem except when
1147 * process is exiting.
1148 * The exiting case is handled explicitly as part of
1149 * mlx5_ib_disassociate_ucontext.
1150 */
1151 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1152
1153 /* setting the vma context pointer to null in the mlx5_ib driver's
1154 * private data, to protect a race condition in
1155 * mlx5_ib_disassociate_ucontext().
1156 */
1157 mlx5_ib_vma_priv_data->vma = NULL;
1158 list_del(&mlx5_ib_vma_priv_data->list);
1159 kfree(mlx5_ib_vma_priv_data);
1160}
1161
1162static const struct vm_operations_struct mlx5_ib_vm_ops = {
1163 .open = mlx5_ib_vma_open,
1164 .close = mlx5_ib_vma_close
1165};
1166
1167static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1168 struct mlx5_ib_ucontext *ctx)
1169{
1170 struct mlx5_ib_vma_private_data *vma_prv;
1171 struct list_head *vma_head = &ctx->vma_private_list;
1172
1173 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1174 if (!vma_prv)
1175 return -ENOMEM;
1176
1177 vma_prv->vma = vma;
1178 vma->vm_private_data = vma_prv;
1179 vma->vm_ops = &mlx5_ib_vm_ops;
1180
1181 list_add(&vma_prv->list, vma_head);
1182
1183 return 0;
1184}
1185
1186static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1187{
1188 int ret;
1189 struct vm_area_struct *vma;
1190 struct mlx5_ib_vma_private_data *vma_private, *n;
1191 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1192 struct task_struct *owning_process = NULL;
1193 struct mm_struct *owning_mm = NULL;
1194
1195 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1196 if (!owning_process)
1197 return;
1198
1199 owning_mm = get_task_mm(owning_process);
1200 if (!owning_mm) {
1201 pr_info("no mm, disassociate ucontext is pending task termination\n");
1202 while (1) {
1203 put_task_struct(owning_process);
1204 usleep_range(1000, 2000);
1205 owning_process = get_pid_task(ibcontext->tgid,
1206 PIDTYPE_PID);
1207 if (!owning_process ||
1208 owning_process->state == TASK_DEAD) {
1209 pr_info("disassociate ucontext done, task was terminated\n");
1210 /* in case task was dead need to release the
1211 * task struct.
1212 */
1213 if (owning_process)
1214 put_task_struct(owning_process);
1215 return;
1216 }
1217 }
1218 }
1219
1220 /* need to protect from a race on closing the vma as part of
1221 * mlx5_ib_vma_close.
1222 */
1223 down_read(&owning_mm->mmap_sem);
1224 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1225 list) {
1226 vma = vma_private->vma;
1227 ret = zap_vma_ptes(vma, vma->vm_start,
1228 PAGE_SIZE);
1229 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1230 /* context going to be destroyed, should
1231 * not access ops any more.
1232 */
1233 vma->vm_ops = NULL;
1234 list_del(&vma_private->list);
1235 kfree(vma_private);
1236 }
1237 up_read(&owning_mm->mmap_sem);
1238 mmput(owning_mm);
1239 put_task_struct(owning_process);
1240}
1241
37aa5c36
GL		 1242static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1243{
1244 switch (cmd) {
1245 case MLX5_IB_MMAP_WC_PAGE:
1246 return "WC";
1247 case MLX5_IB_MMAP_REGULAR_PAGE:
1248 return "best effort WC";
1249 case MLX5_IB_MMAP_NC_PAGE:
1250 return "NC";
1251 default:
1252 return NULL;
1253 }
1254}
1255
1256static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 1257 struct vm_area_struct *vma,
1258 struct mlx5_ib_ucontext *context)
37aa5c36 1259{
7c2344c3 1260 struct mlx5_uuar_info *uuari = &context->uuari;
37aa5c36
GL		 1261 int err;
1262 unsigned long idx;
1263 phys_addr_t pfn, pa;
1264 pgprot_t prot;
1265
1266 switch (cmd) {
1267 case MLX5_IB_MMAP_WC_PAGE:
1268/* Some architectures don't support WC memory */
1269#if defined(CONFIG_X86)
1270 if (!pat_enabled())
1271 return -EPERM;
1272#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1273 return -EPERM;
1274#endif
1275 /* fall through */
1276 case MLX5_IB_MMAP_REGULAR_PAGE:
1277 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1278 prot = pgprot_writecombine(vma->vm_page_prot);
1279 break;
1280 case MLX5_IB_MMAP_NC_PAGE:
1281 prot = pgprot_noncached(vma->vm_page_prot);
1282 break;
1283 default:
1284 return -EINVAL;
1285 }
1286
1287 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1288 return -EINVAL;
1289
1290 idx = get_index(vma->vm_pgoff);
1291 if (idx >= uuari->num_uars)
1292 return -EINVAL;
1293
1294 pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1295 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1296
1297 vma->vm_page_prot = prot;
1298 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1299 PAGE_SIZE, vma->vm_page_prot);
1300 if (err) {
1301 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1302 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1303 return -EAGAIN;
1304 }
1305
1306 pa = pfn << PAGE_SHIFT;
1307 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1308 vma->vm_start, &pa);
1309
7c2344c3 1310 return mlx5_ib_set_vma_data(vma, context);
37aa5c36
GL		 1311}
1312
e126ba97
EC		 1313static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1314{
1315 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1316 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 1317 unsigned long command;
e126ba97
EC		 1318 phys_addr_t pfn;
1319
1320 command = get_command(vma->vm_pgoff);
1321 switch (command) {
37aa5c36
GL		 1322 case MLX5_IB_MMAP_WC_PAGE:
1323 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 1324 case MLX5_IB_MMAP_REGULAR_PAGE:
7c2344c3 1325 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 1326
1327 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1328 return -ENOSYS;
1329
d69e3bcf 1330 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 1331 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1332 return -EINVAL;
1333
6cbac1e4 1334 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 1335 return -EPERM;
1336
1337 /* Don't expose to user-space information it shouldn't have */
1338 if (PAGE_SIZE > 4096)
1339 return -EOPNOTSUPP;
1340
1341 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1342 pfn = (dev->mdev->iseg_base +
1343 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1344 PAGE_SHIFT;
1345 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1346 PAGE_SIZE, vma->vm_page_prot))
1347 return -EAGAIN;
1348
1349 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1350 vma->vm_start,
1351 (unsigned long long)pfn << PAGE_SHIFT);
1352 break;
d69e3bcf 1353
e126ba97
EC		 1354 default:
1355 return -EINVAL;
1356 }
1357
1358 return 0;
1359}
1360
e126ba97
EC		 1361static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1362 struct ib_ucontext *context,
1363 struct ib_udata *udata)
1364{
1365 struct mlx5_ib_alloc_pd_resp resp;
1366 struct mlx5_ib_pd *pd;
1367 int err;
1368
1369 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1370 if (!pd)
1371 return ERR_PTR(-ENOMEM);
1372
9603b61d 1373 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 1374 if (err) {
1375 kfree(pd);
1376 return ERR_PTR(err);
1377 }
1378
1379 if (context) {
1380 resp.pdn = pd->pdn;
1381 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 1382 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 1383 kfree(pd);
1384 return ERR_PTR(-EFAULT);
1385 }
e126ba97
EC		 1386 }
1387
1388 return &pd->ibpd;
1389}
1390
1391static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1392{
1393 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1394 struct mlx5_ib_pd *mpd = to_mpd(pd);
1395
9603b61d 1396 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 1397 kfree(mpd);
1398
1399 return 0;
1400}
1401
038d2ef8
MG		 1402static bool outer_header_zero(u32 *match_criteria)
1403{
1404 int size = MLX5_ST_SZ_BYTES(fte_match_param);
1405 char *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_criteria,
1406 outer_headers);
1407
1408 return outer_headers_c[0] == 0 && !memcmp(outer_headers_c,
1409 outer_headers_c + 1,
1410 size - 1);
1411}
1412
1413static int parse_flow_attr(u32 *match_c, u32 *match_v,
1414 union ib_flow_spec *ib_spec)
1415{
1416 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1417 outer_headers);
1418 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1419 outer_headers);
1420 switch (ib_spec->type) {
1421 case IB_FLOW_SPEC_ETH:
1422 if (ib_spec->size != sizeof(ib_spec->eth))
1423 return -EINVAL;
1424
1425 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1426 dmac_47_16),
1427 ib_spec->eth.mask.dst_mac);
1428 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1429 dmac_47_16),
1430 ib_spec->eth.val.dst_mac);
1431
1432 if (ib_spec->eth.mask.vlan_tag) {
1433 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1434 vlan_tag, 1);
1435 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1436 vlan_tag, 1);
1437
1438 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1439 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1440 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1441 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1442
1443 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1444 first_cfi,
1445 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1446 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1447 first_cfi,
1448 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1449
1450 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1451 first_prio,
1452 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1453 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1454 first_prio,
1455 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1456 }
1457 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1458 ethertype, ntohs(ib_spec->eth.mask.ether_type));
1459 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1460 ethertype, ntohs(ib_spec->eth.val.ether_type));
1461 break;
1462 case IB_FLOW_SPEC_IPV4:
1463 if (ib_spec->size != sizeof(ib_spec->ipv4))
1464 return -EINVAL;
1465
1466 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1467 ethertype, 0xffff);
1468 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1469 ethertype, ETH_P_IP);
1470
1471 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1472 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1473 &ib_spec->ipv4.mask.src_ip,
1474 sizeof(ib_spec->ipv4.mask.src_ip));
1475 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1476 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1477 &ib_spec->ipv4.val.src_ip,
1478 sizeof(ib_spec->ipv4.val.src_ip));
1479 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1480 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1481 &ib_spec->ipv4.mask.dst_ip,
1482 sizeof(ib_spec->ipv4.mask.dst_ip));
1483 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1484 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1485 &ib_spec->ipv4.val.dst_ip,
1486 sizeof(ib_spec->ipv4.val.dst_ip));
1487 break;
026bae0c
MG		 1488 case IB_FLOW_SPEC_IPV6:
1489 if (ib_spec->size != sizeof(ib_spec->ipv6))
1490 return -EINVAL;
1491
1492 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1493 ethertype, 0xffff);
1494 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1495 ethertype, ETH_P_IPV6);
1496
1497 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1498 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1499 &ib_spec->ipv6.mask.src_ip,
1500 sizeof(ib_spec->ipv6.mask.src_ip));
1501 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1502 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1503 &ib_spec->ipv6.val.src_ip,
1504 sizeof(ib_spec->ipv6.val.src_ip));
1505 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1506 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1507 &ib_spec->ipv6.mask.dst_ip,
1508 sizeof(ib_spec->ipv6.mask.dst_ip));
1509 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1510 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1511 &ib_spec->ipv6.val.dst_ip,
1512 sizeof(ib_spec->ipv6.val.dst_ip));
1513 break;
038d2ef8
MG		 1514 case IB_FLOW_SPEC_TCP:
1515 if (ib_spec->size != sizeof(ib_spec->tcp_udp))
1516 return -EINVAL;
1517
1518 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1519 0xff);
1520 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1521 IPPROTO_TCP);
1522
1523 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport,
1524 ntohs(ib_spec->tcp_udp.mask.src_port));
1525 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport,
1526 ntohs(ib_spec->tcp_udp.val.src_port));
1527
1528 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport,
1529 ntohs(ib_spec->tcp_udp.mask.dst_port));
1530 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport,
1531 ntohs(ib_spec->tcp_udp.val.dst_port));
1532 break;
1533 case IB_FLOW_SPEC_UDP:
1534 if (ib_spec->size != sizeof(ib_spec->tcp_udp))
1535 return -EINVAL;
1536
1537 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1538 0xff);
1539 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1540 IPPROTO_UDP);
1541
1542 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport,
1543 ntohs(ib_spec->tcp_udp.mask.src_port));
1544 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport,
1545 ntohs(ib_spec->tcp_udp.val.src_port));
1546
1547 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport,
1548 ntohs(ib_spec->tcp_udp.mask.dst_port));
1549 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport,
1550 ntohs(ib_spec->tcp_udp.val.dst_port));
1551 break;
1552 default:
1553 return -EINVAL;
1554 }
1555
1556 return 0;
1557}
1558
1559/* If a flow could catch both multicast and unicast packets,
1560 * it won't fall into the multicast flow steering table and this rule
1561 * could steal other multicast packets.
1562 */
1563static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1564{
1565 struct ib_flow_spec_eth *eth_spec;
1566
1567 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1568 ib_attr->size < sizeof(struct ib_flow_attr) +
1569 sizeof(struct ib_flow_spec_eth) ||
1570 ib_attr->num_of_specs < 1)
1571 return false;
1572
1573 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1574 if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1575 eth_spec->size != sizeof(*eth_spec))
1576 return false;
1577
1578 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1579 is_multicast_ether_addr(eth_spec->val.dst_mac);
1580}
1581
1582static bool is_valid_attr(struct ib_flow_attr *flow_attr)
1583{
1584 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1585 bool has_ipv4_spec = false;
1586 bool eth_type_ipv4 = true;
1587 unsigned int spec_index;
1588
1589 /* Validate that ethertype is correct */
1590 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1591 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1592 ib_spec->eth.mask.ether_type) {
1593 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1594 ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1595 eth_type_ipv4 = false;
1596 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1597 has_ipv4_spec = true;
1598 }
1599 ib_spec = (void *)ib_spec + ib_spec->size;
1600 }
1601 return !has_ipv4_spec || eth_type_ipv4;
1602}
1603
1604static void put_flow_table(struct mlx5_ib_dev *dev,
1605 struct mlx5_ib_flow_prio *prio, bool ft_added)
1606{
1607 prio->refcount -= !!ft_added;
1608 if (!prio->refcount) {
1609 mlx5_destroy_flow_table(prio->flow_table);
1610 prio->flow_table = NULL;
1611 }
1612}
1613
1614static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1615{
1616 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1617 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1618 struct mlx5_ib_flow_handler,
1619 ibflow);
1620 struct mlx5_ib_flow_handler *iter, *tmp;
1621
1622 mutex_lock(&dev->flow_db.lock);
1623
1624 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1625 mlx5_del_flow_rule(iter->rule);
1626 list_del(&iter->list);
1627 kfree(iter);
1628 }
1629
1630 mlx5_del_flow_rule(handler->rule);
1631 put_flow_table(dev, &dev->flow_db.prios[handler->prio], true);
1632 mutex_unlock(&dev->flow_db.lock);
1633
1634 kfree(handler);
1635
1636 return 0;
1637}
1638
35d19011
MG		 1639static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1640{
1641 priority *= 2;
1642 if (!dont_trap)
1643 priority++;
1644 return priority;
1645}
1646
038d2ef8
MG		 1647#define MLX5_FS_MAX_TYPES 10
1648#define MLX5_FS_MAX_ENTRIES 32000UL
1649static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
1650 struct ib_flow_attr *flow_attr)
1651{
35d19011 1652 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 1653 struct mlx5_flow_namespace *ns = NULL;
1654 struct mlx5_ib_flow_prio *prio;
1655 struct mlx5_flow_table *ft;
1656 int num_entries;
1657 int num_groups;
1658 int priority;
1659 int err = 0;
1660
1661 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 1662 if (flow_is_multicast_only(flow_attr) &&
1663 !dont_trap)
038d2ef8
MG		 1664 priority = MLX5_IB_FLOW_MCAST_PRIO;
1665 else
35d19011
MG		 1666 priority = ib_prio_to_core_prio(flow_attr->priority,
1667 dont_trap);
038d2ef8
MG		 1668 ns = mlx5_get_flow_namespace(dev->mdev,
1669 MLX5_FLOW_NAMESPACE_BYPASS);
1670 num_entries = MLX5_FS_MAX_ENTRIES;
1671 num_groups = MLX5_FS_MAX_TYPES;
1672 prio = &dev->flow_db.prios[priority];
1673 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1674 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1675 ns = mlx5_get_flow_namespace(dev->mdev,
1676 MLX5_FLOW_NAMESPACE_LEFTOVERS);
1677 build_leftovers_ft_param(&priority,
1678 &num_entries,
1679 &num_groups);
1680 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
1681 }
1682
1683 if (!ns)
1684 return ERR_PTR(-ENOTSUPP);
1685
1686 ft = prio->flow_table;
1687 if (!ft) {
1688 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
1689 num_entries,
d63cd286
MG		 1690 num_groups,
1691 0);
038d2ef8
MG		 1692
1693 if (!IS_ERR(ft)) {
1694 prio->refcount = 0;
1695 prio->flow_table = ft;
1696 } else {
1697 err = PTR_ERR(ft);
1698 }
1699 }
1700
1701 return err ? ERR_PTR(err) : prio;
1702}
1703
1704static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1705 struct mlx5_ib_flow_prio *ft_prio,
1706 struct ib_flow_attr *flow_attr,
1707 struct mlx5_flow_destination *dst)
1708{
1709 struct mlx5_flow_table *ft = ft_prio->flow_table;
1710 struct mlx5_ib_flow_handler *handler;
c5bb1730 1711 struct mlx5_flow_spec *spec;
038d2ef8 1712 void *ib_flow = flow_attr + 1;
038d2ef8 1713 unsigned int spec_index;
35d19011 1714 u32 action;
038d2ef8
MG		 1715 int err = 0;
1716
1717 if (!is_valid_attr(flow_attr))
1718 return ERR_PTR(-EINVAL);
1719
c5bb1730 1720 spec = mlx5_vzalloc(sizeof(*spec));
038d2ef8 1721 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 1722 if (!handler || !spec) {
038d2ef8
MG		 1723 err = -ENOMEM;
1724 goto free;
1725 }
1726
1727 INIT_LIST_HEAD(&handler->list);
1728
1729 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
c5bb1730
MG		 1730 err = parse_flow_attr(spec->match_criteria,
1731 spec->match_value, ib_flow);
038d2ef8
MG		 1732 if (err < 0)
1733 goto free;
1734
1735 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1736 }
1737
1738 /* Outer header support only */
c5bb1730
MG		 1739 spec->match_criteria_enable = (!outer_header_zero(spec->match_criteria))
1740 << 0;
35d19011
MG		 1741 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
1742 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
c5bb1730 1743 handler->rule = mlx5_add_flow_rule(ft, spec,
35d19011 1744 action,
038d2ef8
MG		 1745 MLX5_FS_DEFAULT_FLOW_TAG,
1746 dst);
1747
1748 if (IS_ERR(handler->rule)) {
1749 err = PTR_ERR(handler->rule);
1750 goto free;
1751 }
1752
1753 handler->prio = ft_prio - dev->flow_db.prios;
1754
1755 ft_prio->flow_table = ft;
1756free:
1757 if (err)
1758 kfree(handler);
c5bb1730 1759 kvfree(spec);
038d2ef8
MG		 1760 return err ? ERR_PTR(err) : handler;
1761}
1762
35d19011
MG		 1763static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
1764 struct mlx5_ib_flow_prio *ft_prio,
1765 struct ib_flow_attr *flow_attr,
1766 struct mlx5_flow_destination *dst)
1767{
1768 struct mlx5_ib_flow_handler *handler_dst = NULL;
1769 struct mlx5_ib_flow_handler *handler = NULL;
1770
1771 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
1772 if (!IS_ERR(handler)) {
1773 handler_dst = create_flow_rule(dev, ft_prio,
1774 flow_attr, dst);
1775 if (IS_ERR(handler_dst)) {
1776 mlx5_del_flow_rule(handler->rule);
1777 kfree(handler);
1778 handler = handler_dst;
1779 } else {
1780 list_add(&handler_dst->list, &handler->list);
1781 }
1782 }
1783
1784 return handler;
1785}
038d2ef8
MG		 1786enum {
1787 LEFTOVERS_MC,
1788 LEFTOVERS_UC,
1789};
1790
1791static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
1792 struct mlx5_ib_flow_prio *ft_prio,
1793 struct ib_flow_attr *flow_attr,
1794 struct mlx5_flow_destination *dst)
1795{
1796 struct mlx5_ib_flow_handler *handler_ucast = NULL;
1797 struct mlx5_ib_flow_handler *handler = NULL;
1798
1799 static struct {
1800 struct ib_flow_attr flow_attr;
1801 struct ib_flow_spec_eth eth_flow;
1802 } leftovers_specs[] = {
1803 [LEFTOVERS_MC] = {
1804 .flow_attr = {
1805 .num_of_specs = 1,
1806 .size = sizeof(leftovers_specs[0])
1807 },
1808 .eth_flow = {
1809 .type = IB_FLOW_SPEC_ETH,
1810 .size = sizeof(struct ib_flow_spec_eth),
1811 .mask = {.dst_mac = {0x1} },
1812 .val = {.dst_mac = {0x1} }
1813 }
1814 },
1815 [LEFTOVERS_UC] = {
1816 .flow_attr = {
1817 .num_of_specs = 1,
1818 .size = sizeof(leftovers_specs[0])
1819 },
1820 .eth_flow = {
1821 .type = IB_FLOW_SPEC_ETH,
1822 .size = sizeof(struct ib_flow_spec_eth),
1823 .mask = {.dst_mac = {0x1} },
1824 .val = {.dst_mac = {} }
1825 }
1826 }
1827 };
1828
1829 handler = create_flow_rule(dev, ft_prio,
1830 &leftovers_specs[LEFTOVERS_MC].flow_attr,
1831 dst);
1832 if (!IS_ERR(handler) &&
1833 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
1834 handler_ucast = create_flow_rule(dev, ft_prio,
1835 &leftovers_specs[LEFTOVERS_UC].flow_attr,
1836 dst);
1837 if (IS_ERR(handler_ucast)) {
1838 kfree(handler);
1839 handler = handler_ucast;
1840 } else {
1841 list_add(&handler_ucast->list, &handler->list);
1842 }
1843 }
1844
1845 return handler;
1846}
1847
1848static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
1849 struct ib_flow_attr *flow_attr,
1850 int domain)
1851{
1852 struct mlx5_ib_dev *dev = to_mdev(qp->device);
1853 struct mlx5_ib_flow_handler *handler = NULL;
1854 struct mlx5_flow_destination *dst = NULL;
1855 struct mlx5_ib_flow_prio *ft_prio;
1856 int err;
1857
1858 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
1859 return ERR_PTR(-ENOSPC);
1860
1861 if (domain != IB_FLOW_DOMAIN_USER ||
1862 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
35d19011 1863 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
038d2ef8
MG		 1864 return ERR_PTR(-EINVAL);
1865
1866 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
1867 if (!dst)
1868 return ERR_PTR(-ENOMEM);
1869
1870 mutex_lock(&dev->flow_db.lock);
1871
1872 ft_prio = get_flow_table(dev, flow_attr);
1873 if (IS_ERR(ft_prio)) {
1874 err = PTR_ERR(ft_prio);
1875 goto unlock;
1876 }
1877
1878 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
1879 dst->tir_num = to_mqp(qp)->raw_packet_qp.rq.tirn;
1880
1881 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 1882 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
1883 handler = create_dont_trap_rule(dev, ft_prio,
1884 flow_attr, dst);
1885 } else {
1886 handler = create_flow_rule(dev, ft_prio, flow_attr,
1887 dst);
1888 }
038d2ef8
MG		 1889 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1890 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1891 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
1892 dst);
1893 } else {
1894 err = -EINVAL;
1895 goto destroy_ft;
1896 }
1897
1898 if (IS_ERR(handler)) {
1899 err = PTR_ERR(handler);
1900 handler = NULL;
1901 goto destroy_ft;
1902 }
1903
1904 ft_prio->refcount++;
1905 mutex_unlock(&dev->flow_db.lock);
1906 kfree(dst);
1907
1908 return &handler->ibflow;
1909
1910destroy_ft:
1911 put_flow_table(dev, ft_prio, false);
1912unlock:
1913 mutex_unlock(&dev->flow_db.lock);
1914 kfree(dst);
1915 kfree(handler);
1916 return ERR_PTR(err);
1917}
1918
e126ba97
EC		 1919static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1920{
1921 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1922 int err;
1923
9603b61d 1924 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 1925 if (err)
1926 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
1927 ibqp->qp_num, gid->raw);
1928
1929 return err;
1930}
1931
1932static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1933{
1934 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1935 int err;
1936
9603b61d 1937 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 1938 if (err)
1939 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
1940 ibqp->qp_num, gid->raw);
1941
1942 return err;
1943}
1944
1945static int init_node_data(struct mlx5_ib_dev *dev)
1946{
1b5daf11 1947 int err;
e126ba97 1948
1b5daf11 1949 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 1950 if (err)
1b5daf11 1951 return err;
e126ba97 1952
1b5daf11 1953 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 1954
1b5daf11 1955 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 1956}
1957
1958static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
1959 char *buf)
1960{
1961 struct mlx5_ib_dev *dev =
1962 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1963
9603b61d 1964 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 1965}
1966
1967static ssize_t show_reg_pages(struct device *device,
1968 struct device_attribute *attr, char *buf)
1969{
1970 struct mlx5_ib_dev *dev =
1971 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1972
6aec21f6 1973 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 1974}
1975
1976static ssize_t show_hca(struct device *device, struct device_attribute *attr,
1977 char *buf)
1978{
1979 struct mlx5_ib_dev *dev =
1980 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 1981 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 1982}
1983
e126ba97
EC		 1984static ssize_t show_rev(struct device *device, struct device_attribute *attr,
1985 char *buf)
1986{
1987 struct mlx5_ib_dev *dev =
1988 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 1989 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 1990}
1991
1992static ssize_t show_board(struct device *device, struct device_attribute *attr,
1993 char *buf)
1994{
1995 struct mlx5_ib_dev *dev =
1996 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1997 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 1998 dev->mdev->board_id);
e126ba97
EC		 1999}
2000
2001static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
e126ba97
EC		 2002static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2003static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2004static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2005static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2006
2007static struct device_attribute *mlx5_class_attributes[] = {
2008 &dev_attr_hw_rev,
e126ba97
EC		 2009 &dev_attr_hca_type,
2010 &dev_attr_board_id,
2011 &dev_attr_fw_pages,
2012 &dev_attr_reg_pages,
2013};
2014
7722f47e
HE		 2015static void pkey_change_handler(struct work_struct *work)
2016{
2017 struct mlx5_ib_port_resources *ports =
2018 container_of(work, struct mlx5_ib_port_resources,
2019 pkey_change_work);
2020
2021 mutex_lock(&ports->devr->mutex);
2022 mlx5_ib_gsi_pkey_change(ports->gsi);
2023 mutex_unlock(&ports->devr->mutex);
2024}
2025
89ea94a7
MG		 2026static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2027{
2028 struct mlx5_ib_qp *mqp;
2029 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2030 struct mlx5_core_cq *mcq;
2031 struct list_head cq_armed_list;
2032 unsigned long flags_qp;
2033 unsigned long flags_cq;
2034 unsigned long flags;
2035
2036 INIT_LIST_HEAD(&cq_armed_list);
2037
2038 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2039 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2040 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2041 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2042 if (mqp->sq.tail != mqp->sq.head) {
2043 send_mcq = to_mcq(mqp->ibqp.send_cq);
2044 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2045 if (send_mcq->mcq.comp &&
2046 mqp->ibqp.send_cq->comp_handler) {
2047 if (!send_mcq->mcq.reset_notify_added) {
2048 send_mcq->mcq.reset_notify_added = 1;
2049 list_add_tail(&send_mcq->mcq.reset_notify,
2050 &cq_armed_list);
2051 }
2052 }
2053 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2054 }
2055 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2056 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2057 /* no handling is needed for SRQ */
2058 if (!mqp->ibqp.srq) {
2059 if (mqp->rq.tail != mqp->rq.head) {
2060 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2061 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2062 if (recv_mcq->mcq.comp &&
2063 mqp->ibqp.recv_cq->comp_handler) {
2064 if (!recv_mcq->mcq.reset_notify_added) {
2065 recv_mcq->mcq.reset_notify_added = 1;
2066 list_add_tail(&recv_mcq->mcq.reset_notify,
2067 &cq_armed_list);
2068 }
2069 }
2070 spin_unlock_irqrestore(&recv_mcq->lock,
2071 flags_cq);
2072 }
2073 }
2074 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2075 }
2076 /*At that point all inflight post send were put to be executed as of we
2077 * lock/unlock above locks Now need to arm all involved CQs.
2078 */
2079 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2080 mcq->comp(mcq);
2081 }
2082 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2083}
2084
9603b61d 2085static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 2086 enum mlx5_dev_event event, unsigned long param)
e126ba97 2087{
9603b61d 2088 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
e126ba97 2089 struct ib_event ibev;
9603b61d 2090
e126ba97
EC		 2091 u8 port = 0;
2092
2093 switch (event) {
2094 case MLX5_DEV_EVENT_SYS_ERROR:
2095 ibdev->ib_active = false;
2096 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 2097 mlx5_ib_handle_internal_error(ibdev);
e126ba97
EC		 2098 break;
2099
2100 case MLX5_DEV_EVENT_PORT_UP:
2101 ibev.event = IB_EVENT_PORT_ACTIVE;
4d2f9bbb 2102 port = (u8)param;
e126ba97
EC		 2103 break;
2104
2105 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 2106 case MLX5_DEV_EVENT_PORT_INITIALIZED:
e126ba97 2107 ibev.event = IB_EVENT_PORT_ERR;
4d2f9bbb 2108 port = (u8)param;
e126ba97
EC		 2109 break;
2110
e126ba97
EC		 2111 case MLX5_DEV_EVENT_LID_CHANGE:
2112 ibev.event = IB_EVENT_LID_CHANGE;
4d2f9bbb 2113 port = (u8)param;
e126ba97
EC		 2114 break;
2115
2116 case MLX5_DEV_EVENT_PKEY_CHANGE:
2117 ibev.event = IB_EVENT_PKEY_CHANGE;
4d2f9bbb 2118 port = (u8)param;
7722f47e
HE		 2119
2120 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 2121 break;
2122
2123 case MLX5_DEV_EVENT_GUID_CHANGE:
2124 ibev.event = IB_EVENT_GID_CHANGE;
4d2f9bbb 2125 port = (u8)param;
e126ba97
EC		 2126 break;
2127
2128 case MLX5_DEV_EVENT_CLIENT_REREG:
2129 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4d2f9bbb 2130 port = (u8)param;
e126ba97
EC		 2131 break;
2132 }
2133
2134 ibev.device = &ibdev->ib_dev;
2135 ibev.element.port_num = port;
2136
a0c84c32
EC		 2137 if (port < 1 || port > ibdev->num_ports) {
2138 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2139 return;
2140 }
2141
e126ba97
EC		 2142 if (ibdev->ib_active)
2143 ib_dispatch_event(&ibev);
2144}
2145
2146static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2147{
2148 int port;
2149
938fe83c 2150 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
e126ba97
EC		 2151 mlx5_query_ext_port_caps(dev, port);
2152}
2153
2154static int get_port_caps(struct mlx5_ib_dev *dev)
2155{
2156 struct ib_device_attr *dprops = NULL;
2157 struct ib_port_attr *pprops = NULL;
f614fc15 2158 int err = -ENOMEM;
e126ba97 2159 int port;
2528e33e 2160 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 2161
2162 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2163 if (!pprops)
2164 goto out;
2165
2166 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2167 if (!dprops)
2168 goto out;
2169
2528e33e 2170 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 2171 if (err) {
2172 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2173 goto out;
2174 }
2175
938fe83c 2176 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
e126ba97
EC		 2177 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2178 if (err) {
938fe83c
SM		 2179 mlx5_ib_warn(dev, "query_port %d failed %d\n",
2180 port, err);
e126ba97
EC		 2181 break;
2182 }
938fe83c
SM		 2183 dev->mdev->port_caps[port - 1].pkey_table_len =
2184 dprops->max_pkeys;
2185 dev->mdev->port_caps[port - 1].gid_table_len =
2186 pprops->gid_tbl_len;
e126ba97
EC		 2187 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2188 dprops->max_pkeys, pprops->gid_tbl_len);
2189 }
2190
2191out:
2192 kfree(pprops);
2193 kfree(dprops);
2194
2195 return err;
2196}
2197
2198static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2199{
2200 int err;
2201
2202 err = mlx5_mr_cache_cleanup(dev);
2203 if (err)
2204 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2205
2206 mlx5_ib_destroy_qp(dev->umrc.qp);
add08d76 2207 ib_free_cq(dev->umrc.cq);
e126ba97
EC		 2208 ib_dealloc_pd(dev->umrc.pd);
2209}
2210
2211enum {
2212 MAX_UMR_WR = 128,
2213};
2214
2215static int create_umr_res(struct mlx5_ib_dev *dev)
2216{
2217 struct ib_qp_init_attr *init_attr = NULL;
2218 struct ib_qp_attr *attr = NULL;
2219 struct ib_pd *pd;
2220 struct ib_cq *cq;
2221 struct ib_qp *qp;
e126ba97
EC		 2222 int ret;
2223
2224 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2225 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2226 if (!attr || !init_attr) {
2227 ret = -ENOMEM;
2228 goto error_0;
2229 }
2230
2231 pd = ib_alloc_pd(&dev->ib_dev);
2232 if (IS_ERR(pd)) {
2233 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2234 ret = PTR_ERR(pd);
2235 goto error_0;
2236 }
2237
add08d76 2238 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 2239 if (IS_ERR(cq)) {
2240 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2241 ret = PTR_ERR(cq);
2242 goto error_2;
2243 }
e126ba97
EC		 2244
2245 init_attr->send_cq = cq;
2246 init_attr->recv_cq = cq;
2247 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2248 init_attr->cap.max_send_wr = MAX_UMR_WR;
2249 init_attr->cap.max_send_sge = 1;
2250 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2251 init_attr->port_num = 1;
2252 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2253 if (IS_ERR(qp)) {
2254 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2255 ret = PTR_ERR(qp);
2256 goto error_3;
2257 }
2258 qp->device = &dev->ib_dev;
2259 qp->real_qp = qp;
2260 qp->uobject = NULL;
2261 qp->qp_type = MLX5_IB_QPT_REG_UMR;
2262
2263 attr->qp_state = IB_QPS_INIT;
2264 attr->port_num = 1;
2265 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2266 IB_QP_PORT, NULL);
2267 if (ret) {
2268 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2269 goto error_4;
2270 }
2271
2272 memset(attr, 0, sizeof(*attr));
2273 attr->qp_state = IB_QPS_RTR;
2274 attr->path_mtu = IB_MTU_256;
2275
2276 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2277 if (ret) {
2278 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2279 goto error_4;
2280 }
2281
2282 memset(attr, 0, sizeof(*attr));
2283 attr->qp_state = IB_QPS_RTS;
2284 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2285 if (ret) {
2286 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2287 goto error_4;
2288 }
2289
2290 dev->umrc.qp = qp;
2291 dev->umrc.cq = cq;
e126ba97
EC		 2292 dev->umrc.pd = pd;
2293
2294 sema_init(&dev->umrc.sem, MAX_UMR_WR);
2295 ret = mlx5_mr_cache_init(dev);
2296 if (ret) {
2297 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2298 goto error_4;
2299 }
2300
2301 kfree(attr);
2302 kfree(init_attr);
2303
2304 return 0;
2305
2306error_4:
2307 mlx5_ib_destroy_qp(qp);
2308
2309error_3:
add08d76 2310 ib_free_cq(cq);
e126ba97
EC		 2311
2312error_2:
e126ba97
EC		 2313 ib_dealloc_pd(pd);
2314
2315error_0:
2316 kfree(attr);
2317 kfree(init_attr);
2318 return ret;
2319}
2320
2321static int create_dev_resources(struct mlx5_ib_resources *devr)
2322{
2323 struct ib_srq_init_attr attr;
2324 struct mlx5_ib_dev *dev;
bcf4c1ea 2325 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 2326 int port;
e126ba97
EC		 2327 int ret = 0;
2328
2329 dev = container_of(devr, struct mlx5_ib_dev, devr);
2330
d16e91da
HE		 2331 mutex_init(&devr->mutex);
2332
e126ba97
EC		 2333 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2334 if (IS_ERR(devr->p0)) {
2335 ret = PTR_ERR(devr->p0);
2336 goto error0;
2337 }
2338 devr->p0->device = &dev->ib_dev;
2339 devr->p0->uobject = NULL;
2340 atomic_set(&devr->p0->usecnt, 0);
2341
bcf4c1ea 2342 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 2343 if (IS_ERR(devr->c0)) {
2344 ret = PTR_ERR(devr->c0);
2345 goto error1;
2346 }
2347 devr->c0->device = &dev->ib_dev;
2348 devr->c0->uobject = NULL;
2349 devr->c0->comp_handler = NULL;
2350 devr->c0->event_handler = NULL;
2351 devr->c0->cq_context = NULL;
2352 atomic_set(&devr->c0->usecnt, 0);
2353
2354 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2355 if (IS_ERR(devr->x0)) {
2356 ret = PTR_ERR(devr->x0);
2357 goto error2;
2358 }
2359 devr->x0->device = &dev->ib_dev;
2360 devr->x0->inode = NULL;
2361 atomic_set(&devr->x0->usecnt, 0);
2362 mutex_init(&devr->x0->tgt_qp_mutex);
2363 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2364
2365 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2366 if (IS_ERR(devr->x1)) {
2367 ret = PTR_ERR(devr->x1);
2368 goto error3;
2369 }
2370 devr->x1->device = &dev->ib_dev;
2371 devr->x1->inode = NULL;
2372 atomic_set(&devr->x1->usecnt, 0);
2373 mutex_init(&devr->x1->tgt_qp_mutex);
2374 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2375
2376 memset(&attr, 0, sizeof(attr));
2377 attr.attr.max_sge = 1;
2378 attr.attr.max_wr = 1;
2379 attr.srq_type = IB_SRQT_XRC;
2380 attr.ext.xrc.cq = devr->c0;
2381 attr.ext.xrc.xrcd = devr->x0;
2382
2383 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2384 if (IS_ERR(devr->s0)) {
2385 ret = PTR_ERR(devr->s0);
2386 goto error4;
2387 }
2388 devr->s0->device = &dev->ib_dev;
2389 devr->s0->pd = devr->p0;
2390 devr->s0->uobject = NULL;
2391 devr->s0->event_handler = NULL;
2392 devr->s0->srq_context = NULL;
2393 devr->s0->srq_type = IB_SRQT_XRC;
2394 devr->s0->ext.xrc.xrcd = devr->x0;
2395 devr->s0->ext.xrc.cq = devr->c0;
2396 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2397 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2398 atomic_inc(&devr->p0->usecnt);
2399 atomic_set(&devr->s0->usecnt, 0);
2400
4aa17b28
HA		 2401 memset(&attr, 0, sizeof(attr));
2402 attr.attr.max_sge = 1;
2403 attr.attr.max_wr = 1;
2404 attr.srq_type = IB_SRQT_BASIC;
2405 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2406 if (IS_ERR(devr->s1)) {
2407 ret = PTR_ERR(devr->s1);
2408 goto error5;
2409 }
2410 devr->s1->device = &dev->ib_dev;
2411 devr->s1->pd = devr->p0;
2412 devr->s1->uobject = NULL;
2413 devr->s1->event_handler = NULL;
2414 devr->s1->srq_context = NULL;
2415 devr->s1->srq_type = IB_SRQT_BASIC;
2416 devr->s1->ext.xrc.cq = devr->c0;
2417 atomic_inc(&devr->p0->usecnt);
2418 atomic_set(&devr->s0->usecnt, 0);
2419
7722f47e
HE		 2420 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2421 INIT_WORK(&devr->ports[port].pkey_change_work,
2422 pkey_change_handler);
2423 devr->ports[port].devr = devr;
2424 }
2425
e126ba97
EC		 2426 return 0;
2427
4aa17b28
HA		 2428error5:
2429 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 2430error4:
2431 mlx5_ib_dealloc_xrcd(devr->x1);
2432error3:
2433 mlx5_ib_dealloc_xrcd(devr->x0);
2434error2:
2435 mlx5_ib_destroy_cq(devr->c0);
2436error1:
2437 mlx5_ib_dealloc_pd(devr->p0);
2438error0:
2439 return ret;
2440}
2441
2442static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2443{
7722f47e
HE		 2444 struct mlx5_ib_dev *dev =
2445 container_of(devr, struct mlx5_ib_dev, devr);
2446 int port;
2447
4aa17b28 2448 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 2449 mlx5_ib_destroy_srq(devr->s0);
2450 mlx5_ib_dealloc_xrcd(devr->x0);
2451 mlx5_ib_dealloc_xrcd(devr->x1);
2452 mlx5_ib_destroy_cq(devr->c0);
2453 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 2454
2455 /* Make sure no change P_Key work items are still executing */
2456 for (port = 0; port < dev->num_ports; ++port)
2457 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 2458}
2459
e53505a8
AS		 2460static u32 get_core_cap_flags(struct ib_device *ibdev)
2461{
2462 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2463 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2464 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2465 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2466 u32 ret = 0;
2467
2468 if (ll == IB_LINK_LAYER_INFINIBAND)
2469 return RDMA_CORE_PORT_IBA_IB;
2470
2471 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2472 return 0;
2473
2474 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2475 return 0;
2476
2477 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2478 ret |= RDMA_CORE_PORT_IBA_ROCE;
2479
2480 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2481 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2482
2483 return ret;
2484}
2485
7738613e
IW		 2486static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2487 struct ib_port_immutable *immutable)
2488{
2489 struct ib_port_attr attr;
2490 int err;
2491
2492 err = mlx5_ib_query_port(ibdev, port_num, &attr);
2493 if (err)
2494 return err;
2495
2496 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2497 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 2498 immutable->core_cap_flags = get_core_cap_flags(ibdev);
337877a4 2499 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 2500
2501 return 0;
2502}
2503
c7342823
IW		 2504static void get_dev_fw_str(struct ib_device *ibdev, char *str,
2505 size_t str_len)
2506{
2507 struct mlx5_ib_dev *dev =
2508 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
2509 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
2510 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
2511}
2512
fc24fc5e
AS		 2513static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
2514{
e53505a8
AS		 2515 int err;
2516
fc24fc5e 2517 dev->roce.nb.notifier_call = mlx5_netdev_event;
e53505a8
AS		 2518 err = register_netdevice_notifier(&dev->roce.nb);
2519 if (err)
2520 return err;
2521
2522 err = mlx5_nic_vport_enable_roce(dev->mdev);
2523 if (err)
2524 goto err_unregister_netdevice_notifier;
2525
2526 return 0;
2527
2528err_unregister_netdevice_notifier:
2529 unregister_netdevice_notifier(&dev->roce.nb);
2530 return err;
fc24fc5e
AS		 2531}
2532
2533static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
2534{
e53505a8 2535 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 2536 unregister_netdevice_notifier(&dev->roce.nb);
2537}
2538
0837e86a
MB		 2539static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
2540{
2541 unsigned int i;
2542
2543 for (i = 0; i < dev->num_ports; i++)
2544 mlx5_core_dealloc_q_counter(dev->mdev,
2545 dev->port[i].q_cnt_id);
2546}
2547
2548static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
2549{
2550 int i;
2551 int ret;
2552
2553 for (i = 0; i < dev->num_ports; i++) {
2554 ret = mlx5_core_alloc_q_counter(dev->mdev,
2555 &dev->port[i].q_cnt_id);
2556 if (ret) {
2557 mlx5_ib_warn(dev,
2558 "couldn't allocate queue counter for port %d, err %d\n",
2559 i + 1, ret);
2560 goto dealloc_counters;
2561 }
2562 }
2563
2564 return 0;
2565
2566dealloc_counters:
2567 while (--i >= 0)
2568 mlx5_core_dealloc_q_counter(dev->mdev,
2569 dev->port[i].q_cnt_id);
2570
2571 return ret;
2572}
2573
61961500 2574static const char * const names[] = {
0ad17a8f
MB		 2575 "rx_write_requests",
2576 "rx_read_requests",
2577 "rx_atomic_requests",
2578 "out_of_buffer",
2579 "out_of_sequence",
2580 "duplicate_request",
2581 "rnr_nak_retry_err",
2582 "packet_seq_err",
2583 "implied_nak_seq_err",
2584 "local_ack_timeout_err",
2585};
2586
2587static const size_t stats_offsets[] = {
2588 MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests),
2589 MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests),
2590 MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests),
2591 MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer),
2592 MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence),
2593 MLX5_BYTE_OFF(query_q_counter_out, duplicate_request),
2594 MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err),
2595 MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err),
2596 MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err),
2597 MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err),
2598};
2599
2600static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
2601 u8 port_num)
2602{
2603 BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets));
2604
2605 /* We support only per port stats */
2606 if (port_num == 0)
2607 return NULL;
2608
2609 return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names),
2610 RDMA_HW_STATS_DEFAULT_LIFESPAN);
2611}
2612
2613static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
2614 struct rdma_hw_stats *stats,
2615 u8 port, int index)
2616{
2617 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2618 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
2619 void *out;
2620 __be32 val;
2621 int ret;
2622 int i;
2623
2624 if (!port || !stats)
2625 return -ENOSYS;
2626
2627 out = mlx5_vzalloc(outlen);
2628 if (!out)
2629 return -ENOMEM;
2630
2631 ret = mlx5_core_query_q_counter(dev->mdev,
2632 dev->port[port - 1].q_cnt_id, 0,
2633 out, outlen);
2634 if (ret)
2635 goto free;
2636
2637 for (i = 0; i < ARRAY_SIZE(names); i++) {
2638 val = *(__be32 *)(out + stats_offsets[i]);
2639 stats->value[i] = (u64)be32_to_cpu(val);
2640 }
2641free:
2642 kvfree(out);
2643 return ARRAY_SIZE(names);
2644}
2645
9603b61d 2646static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
e126ba97 2647{
e126ba97 2648 struct mlx5_ib_dev *dev;
ebd61f68
AS		 2649 enum rdma_link_layer ll;
2650 int port_type_cap;
e126ba97
EC		 2651 int err;
2652 int i;
2653
ebd61f68
AS		 2654 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
2655 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
2656
e53505a8 2657 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
647241ea
MD		 2658 return NULL;
2659
e126ba97
EC		 2660 printk_once(KERN_INFO "%s", mlx5_version);
2661
2662 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
2663 if (!dev)
9603b61d 2664 return NULL;
e126ba97 2665
9603b61d 2666 dev->mdev = mdev;
e126ba97 2667
0837e86a
MB		 2668 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
2669 GFP_KERNEL);
2670 if (!dev->port)
2671 goto err_dealloc;
2672
fc24fc5e 2673 rwlock_init(&dev->roce.netdev_lock);
e126ba97
EC		 2674 err = get_port_caps(dev);
2675 if (err)
0837e86a 2676 goto err_free_port;
e126ba97 2677
1b5daf11
MD		 2678 if (mlx5_use_mad_ifc(dev))
2679 get_ext_port_caps(dev);
e126ba97 2680
e126ba97
EC		 2681 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
2682
2683 strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX);
2684 dev->ib_dev.owner = THIS_MODULE;
2685 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 2686 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
938fe83c 2687 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
e126ba97 2688 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 2689 dev->ib_dev.num_comp_vectors =
2690 dev->mdev->priv.eq_table.num_comp_vectors;
e126ba97
EC		 2691 dev->ib_dev.dma_device = &mdev->pdev->dev;
2692
2693 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
2694 dev->ib_dev.uverbs_cmd_mask =
2695 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2696 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2697 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2698 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2699 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2700 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 2701 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 2702 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2703 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2704 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2705 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
2706 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2707 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2708 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2709 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2710 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2711 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2712 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2713 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2714 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
2715 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
2716 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
2717 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
2718 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 2719 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 2720 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
2721 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
2722 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
e126ba97
EC		 2723
2724 dev->ib_dev.query_device = mlx5_ib_query_device;
2725 dev->ib_dev.query_port = mlx5_ib_query_port;
ebd61f68 2726 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
fc24fc5e
AS		 2727 if (ll == IB_LINK_LAYER_ETHERNET)
2728 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
e126ba97 2729 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 2730 dev->ib_dev.add_gid = mlx5_ib_add_gid;
2731 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 2732 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
2733 dev->ib_dev.modify_device = mlx5_ib_modify_device;
2734 dev->ib_dev.modify_port = mlx5_ib_modify_port;
2735 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
2736 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
2737 dev->ib_dev.mmap = mlx5_ib_mmap;
2738 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
2739 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
2740 dev->ib_dev.create_ah = mlx5_ib_create_ah;
2741 dev->ib_dev.query_ah = mlx5_ib_query_ah;
2742 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
2743 dev->ib_dev.create_srq = mlx5_ib_create_srq;
2744 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
2745 dev->ib_dev.query_srq = mlx5_ib_query_srq;
2746 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
2747 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
2748 dev->ib_dev.create_qp = mlx5_ib_create_qp;
2749 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
2750 dev->ib_dev.query_qp = mlx5_ib_query_qp;
2751 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
2752 dev->ib_dev.post_send = mlx5_ib_post_send;
2753 dev->ib_dev.post_recv = mlx5_ib_post_recv;
2754 dev->ib_dev.create_cq = mlx5_ib_create_cq;
2755 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
2756 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
2757 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
2758 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
2759 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
2760 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
2761 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 2762 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 2763 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
2764 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
2765 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
2766 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 2767 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 2768 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 2769 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
7738613e 2770 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
c7342823 2771 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
eff901d3
EC		 2772 if (mlx5_core_is_pf(mdev)) {
2773 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
2774 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
2775 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
2776 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
2777 }
e126ba97 2778
7c2344c3
MG		 2779 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
2780
938fe83c 2781 mlx5_ib_internal_fill_odp_caps(dev);
8cdd312c 2782
d2370e0a
MB		 2783 if (MLX5_CAP_GEN(mdev, imaicl)) {
2784 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
2785 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
2786 dev->ib_dev.uverbs_cmd_mask |=
2787 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
2788 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
2789 }
2790
0ad17a8f
MB		 2791 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) &&
2792 MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
2793 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
2794 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
2795 }
2796
938fe83c 2797 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 2798 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
2799 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
2800 dev->ib_dev.uverbs_cmd_mask |=
2801 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
2802 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
2803 }
2804
048ccca8 2805 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
038d2ef8
MG		 2806 IB_LINK_LAYER_ETHERNET) {
2807 dev->ib_dev.create_flow = mlx5_ib_create_flow;
2808 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
79b20a6c
YH		 2809 dev->ib_dev.create_wq = mlx5_ib_create_wq;
2810 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
2811 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
c5f90929
YH		 2812 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
2813 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
038d2ef8
MG		 2814 dev->ib_dev.uverbs_ex_cmd_mask |=
2815 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
79b20a6c
YH		 2816 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
2817 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
2818 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
c5f90929
YH		 2819 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
2820 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
2821 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
038d2ef8 2822 }
e126ba97
EC		 2823 err = init_node_data(dev);
2824 if (err)
233d05d2 2825 goto err_dealloc;
e126ba97 2826
038d2ef8 2827 mutex_init(&dev->flow_db.lock);
e126ba97 2828 mutex_init(&dev->cap_mask_mutex);
89ea94a7
MG		 2829 INIT_LIST_HEAD(&dev->qp_list);
2830 spin_lock_init(&dev->reset_flow_resource_lock);
e126ba97 2831
fc24fc5e
AS		 2832 if (ll == IB_LINK_LAYER_ETHERNET) {
2833 err = mlx5_enable_roce(dev);
2834 if (err)
2835 goto err_dealloc;
2836 }
2837
e126ba97
EC		 2838 err = create_dev_resources(&dev->devr);
2839 if (err)
fc24fc5e 2840 goto err_disable_roce;
e126ba97 2841
6aec21f6 2842 err = mlx5_ib_odp_init_one(dev);
281d1a92 2843 if (err)
e126ba97
EC		 2844 goto err_rsrc;
2845
0837e86a 2846 err = mlx5_ib_alloc_q_counters(dev);
6aec21f6
HE		 2847 if (err)
2848 goto err_odp;
2849
0837e86a
MB		 2850 err = ib_register_device(&dev->ib_dev, NULL);
2851 if (err)
2852 goto err_q_cnt;
2853
e126ba97
EC		 2854 err = create_umr_res(dev);
2855 if (err)
2856 goto err_dev;
2857
2858 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 2859 err = device_create_file(&dev->ib_dev.dev,
2860 mlx5_class_attributes[i]);
2861 if (err)
e126ba97
EC		 2862 goto err_umrc;
2863 }
2864
2865 dev->ib_active = true;
2866
9603b61d 2867 return dev;
e126ba97
EC		 2868
2869err_umrc:
2870 destroy_umrc_res(dev);
2871
2872err_dev:
2873 ib_unregister_device(&dev->ib_dev);
2874
0837e86a
MB		 2875err_q_cnt:
2876 mlx5_ib_dealloc_q_counters(dev);
2877
6aec21f6
HE		 2878err_odp:
2879 mlx5_ib_odp_remove_one(dev);
2880
e126ba97
EC		 2881err_rsrc:
2882 destroy_dev_resources(&dev->devr);
2883
fc24fc5e
AS		 2884err_disable_roce:
2885 if (ll == IB_LINK_LAYER_ETHERNET)
2886 mlx5_disable_roce(dev);
2887
0837e86a
MB		 2888err_free_port:
2889 kfree(dev->port);
2890
9603b61d 2891err_dealloc:
e126ba97
EC		 2892 ib_dealloc_device((struct ib_device *)dev);
2893
9603b61d 2894 return NULL;
e126ba97
EC		 2895}
2896
9603b61d 2897static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 2898{
9603b61d 2899 struct mlx5_ib_dev *dev = context;
fc24fc5e 2900 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
6aec21f6 2901
e126ba97 2902 ib_unregister_device(&dev->ib_dev);
0837e86a 2903 mlx5_ib_dealloc_q_counters(dev);
eefd56e5 2904 destroy_umrc_res(dev);
6aec21f6 2905 mlx5_ib_odp_remove_one(dev);
e126ba97 2906 destroy_dev_resources(&dev->devr);
fc24fc5e
AS		 2907 if (ll == IB_LINK_LAYER_ETHERNET)
2908 mlx5_disable_roce(dev);
0837e86a 2909 kfree(dev->port);
e126ba97
EC		 2910 ib_dealloc_device(&dev->ib_dev);
2911}
2912
9603b61d
JM		 2913static struct mlx5_interface mlx5_ib_interface = {
2914 .add = mlx5_ib_add,
2915 .remove = mlx5_ib_remove,
2916 .event = mlx5_ib_event,
64613d94 2917 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 2918};
2919
2920static int __init mlx5_ib_init(void)
2921{
6aec21f6
HE		 2922 int err;
2923
9603b61d
JM		 2924 if (deprecated_prof_sel != 2)
2925 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
2926
6aec21f6
HE		 2927 err = mlx5_ib_odp_init();
2928 if (err)
2929 return err;
2930
2931 err = mlx5_register_interface(&mlx5_ib_interface);
2932 if (err)
2933 goto clean_odp;
2934
2935 return err;
2936
2937clean_odp:
2938 mlx5_ib_odp_cleanup();
2939 return err;
e126ba97
EC		 2940}
2941
2942static void __exit mlx5_ib_cleanup(void)
2943{
9603b61d 2944 mlx5_unregister_interface(&mlx5_ib_interface);
6aec21f6 2945 mlx5_ib_odp_cleanup();
e126ba97
EC		 2946}
2947
2948module_init(mlx5_ib_init);
2949module_exit(mlx5_ib_cleanup);
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