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RDMA/mlx5: Delete create QP flags obfuscation
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
24da0016 41#include <linux/bitmap.h>
e126ba97 42#include <linux/sched.h>
6e84f315 43#include <linux/sched/mm.h>
0881e7bd 44#include <linux/sched/task.h>
7c2344c3 45#include <linux/delay.h>
e126ba97 46#include <rdma/ib_user_verbs.h>
3f89a643 47#include <rdma/ib_addr.h>
2811ba51 48#include <rdma/ib_cache.h>
ada68c31 49#include <linux/mlx5/port.h>
1b5daf11 50#include <linux/mlx5/vport.h>
72c7fe90 51#include <linux/mlx5/fs.h>
cecae747 52#include <linux/mlx5/eswitch.h>
7c2344c3 53#include <linux/list.h>
e126ba97
EC		 54#include <rdma/ib_smi.h>
55#include <rdma/ib_umem.h>
038d2ef8
MG		 56#include <linux/in.h>
57#include <linux/etherdevice.h>
e126ba97 58#include "mlx5_ib.h"
fc385b7a 59#include "ib_rep.h"
e1f24a79 60#include "cmd.h"
f3da6577 61#include "srq.h"
333fbaa0 62#include "qp.h"
3346c487 63#include <linux/mlx5/fs_helpers.h>
c6475a0b 64#include <linux/mlx5/accel.h>
8c84660b 65#include <rdma/uverbs_std_types.h>
c6475a0b
AY		 66#include <rdma/mlx5_user_ioctl_verbs.h>
67#include <rdma/mlx5_user_ioctl_cmds.h>
4061ff7a 68#include <rdma/ib_umem_odp.h>
8c84660b
MB		 69
70#define UVERBS_MODULE_NAME mlx5_ib
71#include <rdma/uverbs_named_ioctl.h>
e126ba97
EC		 72
73#define DRIVER_NAME "mlx5_ib"
b359911d 74#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 75
76MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
77MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
78MODULE_LICENSE("Dual BSD/GPL");
e126ba97 79
e126ba97
EC		 80static char mlx5_version[] =
81 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 82 DRIVER_VERSION "\n";
e126ba97 83
d69a24e0
DJ		 84struct mlx5_ib_event_work {
85 struct work_struct work;
df097a27
SM		 86 union {
87 struct mlx5_ib_dev *dev;
88 struct mlx5_ib_multiport_info *mpi;
89 };
90 bool is_slave;
134e9349 91 unsigned int event;
df097a27 92 void *param;
d69a24e0
DJ		 93};
94
da7525d2
EBE		 95enum {
96 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
97};
98
d69a24e0 99static struct workqueue_struct *mlx5_ib_event_wq;
32f69e4b
DJ		 100static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
101static LIST_HEAD(mlx5_ib_dev_list);
102/*
103 * This mutex should be held when accessing either of the above lists
104 */
105static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
106
c44ef998
IL		 107/* We can't use an array for xlt_emergency_page because dma_map_single
108 * doesn't work on kernel modules memory
109 */
110static unsigned long xlt_emergency_page;
111static struct mutex xlt_emergency_page_mutex;
112
32f69e4b
DJ		 113struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
114{
115 struct mlx5_ib_dev *dev;
116
117 mutex_lock(&mlx5_ib_multiport_mutex);
118 dev = mpi->ibdev;
119 mutex_unlock(&mlx5_ib_multiport_mutex);
120 return dev;
121}
122
1b5daf11 123static enum rdma_link_layer
ebd61f68 124mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 125{
ebd61f68 126 switch (port_type_cap) {
1b5daf11
MD		 127 case MLX5_CAP_PORT_TYPE_IB:
128 return IB_LINK_LAYER_INFINIBAND;
129 case MLX5_CAP_PORT_TYPE_ETH:
130 return IB_LINK_LAYER_ETHERNET;
131 default:
132 return IB_LINK_LAYER_UNSPECIFIED;
133 }
134}
135
ebd61f68
AS		 136static enum rdma_link_layer
137mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
138{
139 struct mlx5_ib_dev *dev = to_mdev(device);
140 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
141
142 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
143}
144
fd65f1b8
MS		 145static int get_port_state(struct ib_device *ibdev,
146 u8 port_num,
147 enum ib_port_state *state)
148{
149 struct ib_port_attr attr;
150 int ret;
151
152 memset(&attr, 0, sizeof(attr));
3023a1e9 153 ret = ibdev->ops.query_port(ibdev, port_num, &attr);
fd65f1b8
MS		 154 if (!ret)
155 *state = attr.state;
156 return ret;
157}
158
35b0aa67
MB		 159static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
160 struct net_device *ndev,
161 u8 *port_num)
162{
163 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
164 struct net_device *rep_ndev;
165 struct mlx5_ib_port *port;
166 int i;
167
168 for (i = 0; i < dev->num_ports; i++) {
169 port = &dev->port[i];
170 if (!port->rep)
171 continue;
172
173 read_lock(&port->roce.netdev_lock);
174 rep_ndev = mlx5_ib_get_rep_netdev(esw,
175 port->rep->vport);
176 if (rep_ndev == ndev) {
177 read_unlock(&port->roce.netdev_lock);
178 *port_num = i + 1;
179 return &port->roce;
180 }
181 read_unlock(&port->roce.netdev_lock);
182 }
183
184 return NULL;
185}
186
fc24fc5e
AS		 187static int mlx5_netdev_event(struct notifier_block *this,
188 unsigned long event, void *ptr)
189{
7fd8aefb 190 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
fc24fc5e 191 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
7fd8aefb
DJ		 192 u8 port_num = roce->native_port_num;
193 struct mlx5_core_dev *mdev;
194 struct mlx5_ib_dev *ibdev;
195
196 ibdev = roce->dev;
32f69e4b
DJ		 197 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
198 if (!mdev)
199 return NOTIFY_DONE;
fc24fc5e 200
5ec8c83e
AH		 201 switch (event) {
202 case NETDEV_REGISTER:
35b0aa67
MB		 203 /* Should already be registered during the load */
204 if (ibdev->is_rep)
205 break;
7fd8aefb 206 write_lock(&roce->netdev_lock);
dce45af5 207 if (ndev->dev.parent == mdev->device)
842a9c83 208 roce->netdev = ndev;
7fd8aefb 209 write_unlock(&roce->netdev_lock);
5ec8c83e 210 break;
fc24fc5e 211
842a9c83 212 case NETDEV_UNREGISTER:
35b0aa67 213 /* In case of reps, ib device goes away before the netdevs */
842a9c83
OG		 214 write_lock(&roce->netdev_lock);
215 if (roce->netdev == ndev)
216 roce->netdev = NULL;
217 write_unlock(&roce->netdev_lock);
218 break;
219
fd65f1b8 220 case NETDEV_CHANGE:
5ec8c83e 221 case NETDEV_UP:
88621dfe 222 case NETDEV_DOWN: {
7fd8aefb 223 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe
AH		 224 struct net_device *upper = NULL;
225
226 if (lag_ndev) {
227 upper = netdev_master_upper_dev_get(lag_ndev);
228 dev_put(lag_ndev);
229 }
230
35b0aa67
MB		 231 if (ibdev->is_rep)
232 roce = mlx5_get_rep_roce(ibdev, ndev, &port_num);
233 if (!roce)
234 return NOTIFY_DONE;
7fd8aefb 235 if ((upper == ndev || (!upper && ndev == roce->netdev))
88621dfe 236 && ibdev->ib_active) {
626bc02d 237 struct ib_event ibev = { };
fd65f1b8 238 enum ib_port_state port_state;
5ec8c83e 239
7fd8aefb
DJ		 240 if (get_port_state(&ibdev->ib_dev, port_num,
241 &port_state))
242 goto done;
fd65f1b8 243
7fd8aefb
DJ		 244 if (roce->last_port_state == port_state)
245 goto done;
fd65f1b8 246
7fd8aefb 247 roce->last_port_state = port_state;
5ec8c83e 248 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 249 if (port_state == IB_PORT_DOWN)
250 ibev.event = IB_EVENT_PORT_ERR;
251 else if (port_state == IB_PORT_ACTIVE)
252 ibev.event = IB_EVENT_PORT_ACTIVE;
253 else
7fd8aefb 254 goto done;
fd65f1b8 255
7fd8aefb 256 ibev.element.port_num = port_num;
5ec8c83e
AH		 257 ib_dispatch_event(&ibev);
258 }
259 break;
88621dfe 260 }
fc24fc5e 261
5ec8c83e
AH		 262 default:
263 break;
264 }
7fd8aefb 265done:
32f69e4b 266 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 267 return NOTIFY_DONE;
268}
269
270static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
271 u8 port_num)
272{
273 struct mlx5_ib_dev *ibdev = to_mdev(device);
274 struct net_device *ndev;
32f69e4b
DJ		 275 struct mlx5_core_dev *mdev;
276
277 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
278 if (!mdev)
279 return NULL;
fc24fc5e 280
32f69e4b 281 ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe 282 if (ndev)
32f69e4b 283 goto out;
88621dfe 284
fc24fc5e
AS		 285 /* Ensure ndev does not disappear before we invoke dev_hold()
286 */
95579e78
MB		 287 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock);
288 ndev = ibdev->port[port_num - 1].roce.netdev;
fc24fc5e
AS		 289 if (ndev)
290 dev_hold(ndev);
95579e78 291 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock);
fc24fc5e 292
32f69e4b
DJ		 293out:
294 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 295 return ndev;
296}
297
32f69e4b
DJ		 298struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
299 u8 ib_port_num,
300 u8 *native_port_num)
301{
302 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
303 ib_port_num);
304 struct mlx5_core_dev *mdev = NULL;
305 struct mlx5_ib_multiport_info *mpi;
306 struct mlx5_ib_port *port;
307
210b1f78
MB		 308 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
309 ll != IB_LINK_LAYER_ETHERNET) {
310 if (native_port_num)
311 *native_port_num = ib_port_num;
312 return ibdev->mdev;
313 }
314
32f69e4b
DJ		 315 if (native_port_num)
316 *native_port_num = 1;
317
32f69e4b
DJ		 318 port = &ibdev->port[ib_port_num - 1];
319 if (!port)
320 return NULL;
321
322 spin_lock(&port->mp.mpi_lock);
323 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
324 if (mpi && !mpi->unaffiliate) {
325 mdev = mpi->mdev;
326 /* If it's the master no need to refcount, it'll exist
327 * as long as the ib_dev exists.
328 */
329 if (!mpi->is_master)
330 mpi->mdev_refcnt++;
331 }
332 spin_unlock(&port->mp.mpi_lock);
333
334 return mdev;
335}
336
337void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
338{
339 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
340 port_num);
341 struct mlx5_ib_multiport_info *mpi;
342 struct mlx5_ib_port *port;
343
344 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
345 return;
346
347 port = &ibdev->port[port_num - 1];
348
349 spin_lock(&port->mp.mpi_lock);
350 mpi = ibdev->port[port_num - 1].mp.mpi;
351 if (mpi->is_master)
352 goto out;
353
354 mpi->mdev_refcnt--;
355 if (mpi->unaffiliate)
356 complete(&mpi->unref_comp);
357out:
358 spin_unlock(&port->mp.mpi_lock);
359}
360
08e8676f
AL		 361static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, u8 *active_speed,
362 u8 *active_width)
f1b65df5
NO		 363{
364 switch (eth_proto_oper) {
365 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
366 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
367 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
368 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
369 *active_width = IB_WIDTH_1X;
370 *active_speed = IB_SPEED_SDR;
371 break;
372 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
373 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
374 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
375 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
376 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
377 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
378 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
379 *active_width = IB_WIDTH_1X;
380 *active_speed = IB_SPEED_QDR;
381 break;
382 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
383 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
384 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
385 *active_width = IB_WIDTH_1X;
386 *active_speed = IB_SPEED_EDR;
387 break;
388 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
389 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
390 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
391 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
392 *active_width = IB_WIDTH_4X;
393 *active_speed = IB_SPEED_QDR;
394 break;
395 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
396 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
397 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
398 *active_width = IB_WIDTH_1X;
399 *active_speed = IB_SPEED_HDR;
400 break;
401 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
402 *active_width = IB_WIDTH_4X;
403 *active_speed = IB_SPEED_FDR;
404 break;
405 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
406 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
407 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
408 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
409 *active_width = IB_WIDTH_4X;
410 *active_speed = IB_SPEED_EDR;
411 break;
412 default:
413 return -EINVAL;
414 }
415
416 return 0;
417}
418
08e8676f
AL		 419static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed,
420 u8 *active_width)
421{
422 switch (eth_proto_oper) {
423 case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
424 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
425 *active_width = IB_WIDTH_1X;
426 *active_speed = IB_SPEED_SDR;
427 break;
428 case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
429 *active_width = IB_WIDTH_1X;
430 *active_speed = IB_SPEED_DDR;
431 break;
432 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
433 *active_width = IB_WIDTH_1X;
434 *active_speed = IB_SPEED_QDR;
435 break;
436 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
437 *active_width = IB_WIDTH_4X;
438 *active_speed = IB_SPEED_QDR;
439 break;
440 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
441 *active_width = IB_WIDTH_1X;
442 *active_speed = IB_SPEED_EDR;
443 break;
444 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
cd272875
AL		 445 *active_width = IB_WIDTH_2X;
446 *active_speed = IB_SPEED_EDR;
447 break;
08e8676f
AL		 448 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
449 *active_width = IB_WIDTH_1X;
450 *active_speed = IB_SPEED_HDR;
451 break;
cd272875
AL		 452 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
453 *active_width = IB_WIDTH_4X;
454 *active_speed = IB_SPEED_EDR;
455 break;
08e8676f
AL		 456 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
457 *active_width = IB_WIDTH_2X;
458 *active_speed = IB_SPEED_HDR;
459 break;
460 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
461 *active_width = IB_WIDTH_4X;
462 *active_speed = IB_SPEED_HDR;
463 break;
464 default:
465 return -EINVAL;
466 }
467
468 return 0;
469}
470
471static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
472 u8 *active_width, bool ext)
473{
474 return ext ?
475 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
476 active_width) :
477 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
478 active_width);
479}
480
095b0927
IT		 481static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
482 struct ib_port_attr *props)
3f89a643
AS		 483{
484 struct mlx5_ib_dev *dev = to_mdev(device);
bc4e12ff 485 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
da005f9f 486 struct mlx5_core_dev *mdev;
88621dfe 487 struct net_device *ndev, *upper;
3f89a643 488 enum ib_mtu ndev_ib_mtu;
b3cbd6f0 489 bool put_mdev = true;
c876a1b7 490 u16 qkey_viol_cntr;
f1b65df5 491 u32 eth_prot_oper;
b3cbd6f0 492 u8 mdev_port_num;
08e8676f 493 bool ext;
095b0927 494 int err;
3f89a643 495
b3cbd6f0
DJ		 496 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
497 if (!mdev) {
498 /* This means the port isn't affiliated yet. Get the
499 * info for the master port instead.
500 */
501 put_mdev = false;
502 mdev = dev->mdev;
503 mdev_port_num = 1;
504 port_num = 1;
505 }
506
f1b65df5
NO		 507 /* Possible bad flows are checked before filling out props so in case
508 * of an error it will still be zeroed out.
26628e2d 509 * Use native port in case of reps
50f22fd8 510 */
26628e2d
MB		 511 if (dev->is_rep)
512 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
513 1);
514 else
515 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
516 mdev_port_num);
095b0927 517 if (err)
b3cbd6f0 518 goto out;
08e8676f
AL		 519 ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet);
520 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
f1b65df5 521
7672ed33
HL		 522 props->active_width = IB_WIDTH_4X;
523 props->active_speed = IB_SPEED_QDR;
524
f1b65df5 525 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
08e8676f 526 &props->active_width, ext);
3f89a643 527
2f944c0f
JG		 528 props->port_cap_flags |= IB_PORT_CM_SUP;
529 props->ip_gids = true;
3f89a643
AS		 530
531 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
532 roce_address_table_size);
533 props->max_mtu = IB_MTU_4096;
534 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
535 props->pkey_tbl_len = 1;
536 props->state = IB_PORT_DOWN;
72a7720f 537 props->phys_state = IB_PORT_PHYS_STATE_DISABLED;
3f89a643 538
b3cbd6f0 539 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
c876a1b7 540 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643 541
b3cbd6f0
DJ		 542 /* If this is a stub query for an unaffiliated port stop here */
543 if (!put_mdev)
544 goto out;
545
3f89a643
AS		 546 ndev = mlx5_ib_get_netdev(device, port_num);
547 if (!ndev)
b3cbd6f0 548 goto out;
3f89a643 549
7c34ec19 550 if (dev->lag_active) {
88621dfe
AH		 551 rcu_read_lock();
552 upper = netdev_master_upper_dev_get_rcu(ndev);
553 if (upper) {
554 dev_put(ndev);
555 ndev = upper;
556 dev_hold(ndev);
557 }
558 rcu_read_unlock();
559 }
560
3f89a643
AS		 561 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
562 props->state = IB_PORT_ACTIVE;
72a7720f 563 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
3f89a643
AS		 564 }
565
566 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
567
568 dev_put(ndev);
569
570 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
b3cbd6f0
DJ		 571out:
572 if (put_mdev)
573 mlx5_ib_put_native_port_mdev(dev, port_num);
574 return err;
3f89a643
AS		 575}
576
095b0927
IT		 577static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
578 unsigned int index, const union ib_gid *gid,
579 const struct ib_gid_attr *attr)
3cca2606 580{
095b0927 581 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
a70c0739 582 u16 vlan_id = 0xffff;
095b0927
IT		 583 u8 roce_version = 0;
584 u8 roce_l3_type = 0;
095b0927 585 u8 mac[ETH_ALEN];
a70c0739 586 int ret;
095b0927
IT		 587
588 if (gid) {
589 gid_type = attr->gid_type;
a70c0739
PP		 590 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
591 if (ret)
592 return ret;
3cca2606
AS		 593 }
594
095b0927 595 switch (gid_type) {
3cca2606 596 case IB_GID_TYPE_IB:
095b0927 597 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 598 break;
599 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 600 roce_version = MLX5_ROCE_VERSION_2;
601 if (ipv6_addr_v4mapped((void *)gid))
602 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
603 else
604 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 605 break;
606
607 default:
095b0927 608 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 609 }
610
095b0927 611 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
cf34e1fe 612 roce_l3_type, gid->raw, mac,
a70c0739 613 vlan_id < VLAN_CFI_MASK, vlan_id,
cf34e1fe 614 port_num);
3cca2606
AS		 615}
616
f4df9a7c 617static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
3cca2606
AS		 618 __always_unused void **context)
619{
414448d2 620 return set_roce_addr(to_mdev(attr->device), attr->port_num,
f4df9a7c 621 attr->index, &attr->gid, attr);
3cca2606
AS		 622}
623
414448d2
PP		 624static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
625 __always_unused void **context)
3cca2606 626{
414448d2
PP		 627 return set_roce_addr(to_mdev(attr->device), attr->port_num,
628 attr->index, NULL, NULL);
3cca2606
AS		 629}
630
47ec3866
PP		 631__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
632 const struct ib_gid_attr *attr)
2811ba51 633{
47ec3866 634 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
2811ba51
AS		 635 return 0;
636
637 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
638}
639
1b5daf11
MD		 640static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
641{
7fae6655
NO		 642 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
643 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
644 return 0;
1b5daf11
MD		 645}
646
647enum {
648 MLX5_VPORT_ACCESS_METHOD_MAD,
649 MLX5_VPORT_ACCESS_METHOD_HCA,
650 MLX5_VPORT_ACCESS_METHOD_NIC,
651};
652
653static int mlx5_get_vport_access_method(struct ib_device *ibdev)
654{
655 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
656 return MLX5_VPORT_ACCESS_METHOD_MAD;
657
ebd61f68 658 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 659 IB_LINK_LAYER_ETHERNET)
660 return MLX5_VPORT_ACCESS_METHOD_NIC;
661
662 return MLX5_VPORT_ACCESS_METHOD_HCA;
663}
664
da7525d2 665static void get_atomic_caps(struct mlx5_ib_dev *dev,
776a3906 666 u8 atomic_size_qp,
da7525d2
EBE		 667 struct ib_device_attr *props)
668{
669 u8 tmp;
670 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
da7525d2 671 u8 atomic_req_8B_endianness_mode =
bd10838a 672 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 673
674 /* Check if HW supports 8 bytes standard atomic operations and capable
675 * of host endianness respond
676 */
677 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
678 if (((atomic_operations & tmp) == tmp) &&
679 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
680 (atomic_req_8B_endianness_mode)) {
681 props->atomic_cap = IB_ATOMIC_HCA;
682 } else {
683 props->atomic_cap = IB_ATOMIC_NONE;
684 }
685}
686
776a3906
MS		 687static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
688 struct ib_device_attr *props)
689{
690 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
691
692 get_atomic_caps(dev, atomic_size_qp, props);
693}
694
1b5daf11
MD		 695static int mlx5_query_system_image_guid(struct ib_device *ibdev,
696 __be64 *sys_image_guid)
697{
698 struct mlx5_ib_dev *dev = to_mdev(ibdev);
699 struct mlx5_core_dev *mdev = dev->mdev;
700 u64 tmp;
701 int err;
702
703 switch (mlx5_get_vport_access_method(ibdev)) {
704 case MLX5_VPORT_ACCESS_METHOD_MAD:
705 return mlx5_query_mad_ifc_system_image_guid(ibdev,
706 sys_image_guid);
707
708 case MLX5_VPORT_ACCESS_METHOD_HCA:
709 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 710 break;
711
712 case MLX5_VPORT_ACCESS_METHOD_NIC:
713 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
714 break;
1b5daf11
MD		 715
716 default:
717 return -EINVAL;
718 }
3f89a643
AS		 719
720 if (!err)
721 *sys_image_guid = cpu_to_be64(tmp);
722
723 return err;
724
1b5daf11
MD		 725}
726
727static int mlx5_query_max_pkeys(struct ib_device *ibdev,
728 u16 *max_pkeys)
729{
730 struct mlx5_ib_dev *dev = to_mdev(ibdev);
731 struct mlx5_core_dev *mdev = dev->mdev;
732
733 switch (mlx5_get_vport_access_method(ibdev)) {
734 case MLX5_VPORT_ACCESS_METHOD_MAD:
735 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
736
737 case MLX5_VPORT_ACCESS_METHOD_HCA:
738 case MLX5_VPORT_ACCESS_METHOD_NIC:
739 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
740 pkey_table_size));
741 return 0;
742
743 default:
744 return -EINVAL;
745 }
746}
747
748static int mlx5_query_vendor_id(struct ib_device *ibdev,
749 u32 *vendor_id)
750{
751 struct mlx5_ib_dev *dev = to_mdev(ibdev);
752
753 switch (mlx5_get_vport_access_method(ibdev)) {
754 case MLX5_VPORT_ACCESS_METHOD_MAD:
755 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
756
757 case MLX5_VPORT_ACCESS_METHOD_HCA:
758 case MLX5_VPORT_ACCESS_METHOD_NIC:
759 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
760
761 default:
762 return -EINVAL;
763 }
764}
765
766static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
767 __be64 *node_guid)
768{
769 u64 tmp;
770 int err;
771
772 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
773 case MLX5_VPORT_ACCESS_METHOD_MAD:
774 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
775
776 case MLX5_VPORT_ACCESS_METHOD_HCA:
777 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 778 break;
779
780 case MLX5_VPORT_ACCESS_METHOD_NIC:
781 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
782 break;
1b5daf11
MD		 783
784 default:
785 return -EINVAL;
786 }
3f89a643
AS		 787
788 if (!err)
789 *node_guid = cpu_to_be64(tmp);
790
791 return err;
1b5daf11
MD		 792}
793
794struct mlx5_reg_node_desc {
bd99fdea 795 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 796};
797
798static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
799{
800 struct mlx5_reg_node_desc in;
801
802 if (mlx5_use_mad_ifc(dev))
803 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
804
805 memset(&in, 0, sizeof(in));
806
807 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
808 sizeof(struct mlx5_reg_node_desc),
809 MLX5_REG_NODE_DESC, 0, 0);
810}
811
e126ba97 812static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 813 struct ib_device_attr *props,
814 struct ib_udata *uhw)
e126ba97 815{
48357091 816 size_t uhw_outlen = (uhw) ? uhw->outlen : 0;
e126ba97 817 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 818 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 819 int err = -ENOMEM;
288c01b7 820 int max_sq_desc;
e126ba97
EC		 821 int max_rq_sg;
822 int max_sq_sg;
e0238a6a 823 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
85c7c014 824 bool raw_support = !mlx5_core_mp_enabled(mdev);
402ca536
BW		 825 struct mlx5_ib_query_device_resp resp = {};
826 size_t resp_len;
827 u64 max_tso;
e126ba97 828
402ca536 829 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
48357091 830 if (uhw_outlen && uhw_outlen < resp_len)
402ca536 831 return -EINVAL;
6f26b2ac
EA		 832
833 resp.response_length = resp_len;
402ca536 834
48357091 835 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 836 return -EINVAL;
837
1b5daf11
MD		 838 memset(props, 0, sizeof(*props));
839 err = mlx5_query_system_image_guid(ibdev,
840 &props->sys_image_guid);
841 if (err)
842 return err;
e126ba97 843
1b5daf11 844 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 845 if (err)
1b5daf11 846 return err;
e126ba97 847
1b5daf11
MD		 848 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
849 if (err)
850 return err;
e126ba97 851
9603b61d
JM		 852 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
853 (fw_rev_min(dev->mdev) << 16) |
854 fw_rev_sub(dev->mdev);
e126ba97
EC		 855 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
856 IB_DEVICE_PORT_ACTIVE_EVENT |
857 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 858 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 859
860 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 861 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 862 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 863 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 864 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 865 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 866 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 867 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 868 if (MLX5_CAP_GEN(mdev, imaicl)) {
869 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
870 IB_DEVICE_MEM_WINDOW_TYPE_2B;
871 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 872 /* We support 'Gappy' memory registration too */
873 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 874 }
e126ba97 875 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 876 if (MLX5_CAP_GEN(mdev, sho)) {
c0a6cbb9 877 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER;
2dea9094
SG		 878 /* At this stage no support for signature handover */
879 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
880 IB_PROT_T10DIF_TYPE_2 |
881 IB_PROT_T10DIF_TYPE_3;
882 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
883 IB_GUARD_T10DIF_CSUM;
884 }
938fe83c 885 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 886 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 887
85c7c014 888 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
e8161334
NO		 889 if (MLX5_CAP_ETH(mdev, csum_cap)) {
890 /* Legacy bit to support old userspace libraries */
88115fe7 891 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 892 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
893 }
894
895 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
896 props->raw_packet_caps |=
897 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 898
a762d460 899 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) {
402ca536
BW		 900 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
901 if (max_tso) {
902 resp.tso_caps.max_tso = 1 << max_tso;
903 resp.tso_caps.supported_qpts |=
904 1 << IB_QPT_RAW_PACKET;
905 resp.response_length += sizeof(resp.tso_caps);
906 }
907 }
31f69a82 908
a762d460 909 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) {
31f69a82
YH		 910 resp.rss_caps.rx_hash_function =
911 MLX5_RX_HASH_FUNC_TOEPLITZ;
912 resp.rss_caps.rx_hash_fields_mask =
913 MLX5_RX_HASH_SRC_IPV4 |
914 MLX5_RX_HASH_DST_IPV4 |
915 MLX5_RX_HASH_SRC_IPV6 |
916 MLX5_RX_HASH_DST_IPV6 |
917 MLX5_RX_HASH_SRC_PORT_TCP |
918 MLX5_RX_HASH_DST_PORT_TCP |
919 MLX5_RX_HASH_SRC_PORT_UDP |
4e2b53a5
MG		 920 MLX5_RX_HASH_DST_PORT_UDP |
921 MLX5_RX_HASH_INNER;
2d93fc85
MB		 922 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
923 MLX5_ACCEL_IPSEC_CAP_DEVICE)
924 resp.rss_caps.rx_hash_fields_mask |=
925 MLX5_RX_HASH_IPSEC_SPI;
31f69a82
YH		 926 resp.response_length += sizeof(resp.rss_caps);
927 }
928 } else {
a762d460 929 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen)
31f69a82 930 resp.response_length += sizeof(resp.tso_caps);
a762d460 931 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen)
31f69a82 932 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 933 }
934
f0313965
ES		 935 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
936 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
937 props->device_cap_flags |= IB_DEVICE_UD_TSO;
938 }
939
03404e8a 940 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
85c7c014
DJ		 941 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
942 raw_support)
03404e8a
MG		 943 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
944
1d54f890
YH		 945 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
946 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
947 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
948
cff5a0f3 949 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
85c7c014
DJ		 950 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
951 raw_support) {
e8161334 952 /* Legacy bit to support old userspace libraries */
cff5a0f3 953 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 954 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
955 }
cff5a0f3 956
24da0016
AL		 957 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
958 props->max_dm_size =
959 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
960 }
961
da6d6ba3
MG		 962 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
963 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
964
b1383aa6
NO		 965 if (MLX5_CAP_GEN(mdev, end_pad))
966 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
967
1b5daf11
MD		 968 props->vendor_part_id = mdev->pdev->device;
969 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 970
971 props->max_mr_size = ~0ull;
e0238a6a 972 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 973 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
974 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
975 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
976 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 977 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
978 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
979 sizeof(struct mlx5_wqe_raddr_seg)) /
980 sizeof(struct mlx5_wqe_data_seg);
33023fb8
SW		 981 props->max_send_sge = max_sq_sg;
982 props->max_recv_sge = max_rq_sg;
986ef95e 983 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 984 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 985 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 986 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
987 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
988 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
989 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
990 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
991 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
992 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 993 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 994 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 995 props->max_fast_reg_page_list_len =
996 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
62e3c379
MG		 997 props->max_pi_fast_reg_page_list_len =
998 props->max_fast_reg_page_list_len / 2;
36609056
YF		 999 props->max_sgl_rd =
1000 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance);
776a3906 1001 get_atomic_caps_qp(dev, props);
81bea28f 1002 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 1003 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
1004 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 1005 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1006 props->max_mcast_grp;
1007 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 1008 props->max_ah = INT_MAX;
7c60bcbb
MB		 1009 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
1010 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 1011
e502b8b0 1012 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
00815752 1013 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT)
e502b8b0
LR		 1014 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
1015 props->odp_caps = dev->odp_caps;
a73a8955
MS		 1016 if (!uhw) {
1017 /* ODP for kernel QPs is not implemented for receive
1018 * WQEs and SRQ WQEs
1019 */
1020 props->odp_caps.per_transport_caps.rc_odp_caps &=
1021 ~(IB_ODP_SUPPORT_READ |
1022 IB_ODP_SUPPORT_SRQ_RECV);
1023 props->odp_caps.per_transport_caps.uc_odp_caps &=
1024 ~(IB_ODP_SUPPORT_READ |
1025 IB_ODP_SUPPORT_SRQ_RECV);
1026 props->odp_caps.per_transport_caps.ud_odp_caps &=
1027 ~(IB_ODP_SUPPORT_READ |
1028 IB_ODP_SUPPORT_SRQ_RECV);
1029 props->odp_caps.per_transport_caps.xrc_odp_caps &=
1030 ~(IB_ODP_SUPPORT_READ |
1031 IB_ODP_SUPPORT_SRQ_RECV);
1032 }
e502b8b0 1033 }
8cdd312c 1034
051f2630
LR		 1035 if (MLX5_CAP_GEN(mdev, cd))
1036 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
1037
e53a9d26 1038 if (mlx5_core_is_vf(mdev))
eff901d3
EC		 1039 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
1040
31f69a82 1041 if (mlx5_ib_port_link_layer(ibdev, 1) ==
85c7c014 1042 IB_LINK_LAYER_ETHERNET && raw_support) {
31f69a82
YH		 1043 props->rss_caps.max_rwq_indirection_tables =
1044 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1045 props->rss_caps.max_rwq_indirection_table_size =
1046 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1047 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1048 props->max_wq_type_rq =
1049 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1050 }
1051
eb761894 1052 if (MLX5_CAP_GEN(mdev, tag_matching)) {
78b1beb0 1053 props->tm_caps.max_num_tags =
eb761894 1054 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
78b1beb0 1055 props->tm_caps.max_ops =
eb761894 1056 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
78b1beb0 1057 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
eb761894
AK		 1058 }
1059
89705e92
DG		 1060 if (MLX5_CAP_GEN(mdev, tag_matching) &&
1061 MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
1062 props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
1063 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1064 }
1065
87ab3f52
YC		 1066 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1067 props->cq_caps.max_cq_moderation_count =
1068 MLX5_MAX_CQ_COUNT;
1069 props->cq_caps.max_cq_moderation_period =
1070 MLX5_MAX_CQ_PERIOD;
1071 }
1072
a762d460 1073 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) {
7e43a2a5 1074 resp.response_length += sizeof(resp.cqe_comp_caps);
572f46bf
YC		 1075
1076 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1077 resp.cqe_comp_caps.max_num =
1078 MLX5_CAP_GEN(dev->mdev,
1079 cqe_compression_max_num);
1080
1081 resp.cqe_comp_caps.supported_format =
1082 MLX5_IB_CQE_RES_FORMAT_HASH |
1083 MLX5_IB_CQE_RES_FORMAT_CSUM;
6f1006a4
YC		 1084
1085 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1086 resp.cqe_comp_caps.supported_format |=
1087 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
572f46bf 1088 }
7e43a2a5
BW		 1089 }
1090
a762d460 1091 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen &&
85c7c014 1092 raw_support) {
d949167d
BW		 1093 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1094 MLX5_CAP_GEN(mdev, qos)) {
1095 resp.packet_pacing_caps.qp_rate_limit_max =
1096 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1097 resp.packet_pacing_caps.qp_rate_limit_min =
1098 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1099 resp.packet_pacing_caps.supported_qpts |=
1100 1 << IB_QPT_RAW_PACKET;
61147f39
BW		 1101 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1102 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1103 resp.packet_pacing_caps.cap_flags |=
1104 MLX5_IB_PP_SUPPORT_BURST;
d949167d
BW		 1105 }
1106 resp.response_length += sizeof(resp.packet_pacing_caps);
1107 }
1108
a762d460
LR		 1109 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <=
1110 uhw_outlen) {
795b609c
BW		 1111 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1112 resp.mlx5_ib_support_multi_pkt_send_wqes =
1113 MLX5_IB_ALLOW_MPW;
050da902
BW		 1114
1115 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1116 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1117 MLX5_IB_SUPPORT_EMPW;
1118
9f885201
LR		 1119 resp.response_length +=
1120 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1121 }
1122
a762d460 1123 if (offsetofend(typeof(resp), flags) <= uhw_outlen) {
de57f2ad 1124 resp.response_length += sizeof(resp.flags);
7a0c8f42 1125
de57f2ad
GL		 1126 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1127 resp.flags |=
1128 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
7a0c8f42
GL		 1129
1130 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1131 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
7e11b911
DG		 1132 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1133 resp.flags |=
1134 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
7249c8ea
GL		 1135
1136 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
de57f2ad 1137 }
9f885201 1138
a762d460 1139 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) {
96dc3fc5
NO		 1140 resp.response_length += sizeof(resp.sw_parsing_caps);
1141 if (MLX5_CAP_ETH(mdev, swp)) {
1142 resp.sw_parsing_caps.sw_parsing_offloads |=
1143 MLX5_IB_SW_PARSING;
1144
1145 if (MLX5_CAP_ETH(mdev, swp_csum))
1146 resp.sw_parsing_caps.sw_parsing_offloads |=
1147 MLX5_IB_SW_PARSING_CSUM;
1148
1149 if (MLX5_CAP_ETH(mdev, swp_lso))
1150 resp.sw_parsing_caps.sw_parsing_offloads |=
1151 MLX5_IB_SW_PARSING_LSO;
1152
1153 if (resp.sw_parsing_caps.sw_parsing_offloads)
1154 resp.sw_parsing_caps.supported_qpts =
1155 BIT(IB_QPT_RAW_PACKET);
1156 }
1157 }
1158
a762d460 1159 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen &&
85c7c014 1160 raw_support) {
b4f34597
NO		 1161 resp.response_length += sizeof(resp.striding_rq_caps);
1162 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1163 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1164 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1165 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1166 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
c16339b6
MZ		 1167 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range))
1168 resp.striding_rq_caps
1169 .min_single_wqe_log_num_of_strides =
1170 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1171 else
1172 resp.striding_rq_caps
1173 .min_single_wqe_log_num_of_strides =
1174 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
b4f34597
NO		 1175 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1176 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1177 resp.striding_rq_caps.supported_qpts =
1178 BIT(IB_QPT_RAW_PACKET);
1179 }
1180 }
1181
a762d460 1182 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) {
f95ef6cb
MG		 1183 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1184 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1185 resp.tunnel_offloads_caps |=
1186 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1187 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1188 resp.tunnel_offloads_caps |=
1189 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1190 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1191 resp.tunnel_offloads_caps |=
1192 MLX5_IB_TUNNELED_OFFLOADS_GRE;
41e684ef 1193 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre))
e818e255
AL		 1194 resp.tunnel_offloads_caps |=
1195 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
41e684ef 1196 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp))
e818e255
AL		 1197 resp.tunnel_offloads_caps |=
1198 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
f95ef6cb
MG		 1199 }
1200
48357091 1201 if (uhw_outlen) {
402ca536
BW		 1202 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1203
1204 if (err)
1205 return err;
1206 }
1207
1b5daf11 1208 return 0;
e126ba97
EC		 1209}
1210
1b5daf11
MD		 1211enum mlx5_ib_width {
1212 MLX5_IB_WIDTH_1X = 1 << 0,
1213 MLX5_IB_WIDTH_2X = 1 << 1,
1214 MLX5_IB_WIDTH_4X = 1 << 2,
1215 MLX5_IB_WIDTH_8X = 1 << 3,
1216 MLX5_IB_WIDTH_12X = 1 << 4
1217};
1218
db7a691a 1219static void translate_active_width(struct ib_device *ibdev, u8 active_width,
1b5daf11 1220 u8 *ib_width)
e126ba97
EC		 1221{
1222 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11 1223
db7a691a 1224 if (active_width & MLX5_IB_WIDTH_1X)
1b5daf11 1225 *ib_width = IB_WIDTH_1X;
d764970b
MG		 1226 else if (active_width & MLX5_IB_WIDTH_2X)
1227 *ib_width = IB_WIDTH_2X;
db7a691a 1228 else if (active_width & MLX5_IB_WIDTH_4X)
1b5daf11 1229 *ib_width = IB_WIDTH_4X;
db7a691a 1230 else if (active_width & MLX5_IB_WIDTH_8X)
1b5daf11 1231 *ib_width = IB_WIDTH_8X;
db7a691a 1232 else if (active_width & MLX5_IB_WIDTH_12X)
1b5daf11 1233 *ib_width = IB_WIDTH_12X;
db7a691a
MG		 1234 else {
1235 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1b5daf11 1236 (int)active_width);
db7a691a 1237 *ib_width = IB_WIDTH_4X;
e126ba97
EC		 1238 }
1239
db7a691a 1240 return;
1b5daf11 1241}
e126ba97 1242
1b5daf11
MD		 1243static int mlx5_mtu_to_ib_mtu(int mtu)
1244{
1245 switch (mtu) {
1246 case 256: return 1;
1247 case 512: return 2;
1248 case 1024: return 3;
1249 case 2048: return 4;
1250 case 4096: return 5;
1251 default:
1252 pr_warn("invalid mtu\n");
1253 return -1;
e126ba97 1254 }
1b5daf11 1255}
e126ba97 1256
1b5daf11
MD		 1257enum ib_max_vl_num {
1258 __IB_MAX_VL_0 = 1,
1259 __IB_MAX_VL_0_1 = 2,
1260 __IB_MAX_VL_0_3 = 3,
1261 __IB_MAX_VL_0_7 = 4,
1262 __IB_MAX_VL_0_14 = 5,
1263};
e126ba97 1264
1b5daf11
MD		 1265enum mlx5_vl_hw_cap {
1266 MLX5_VL_HW_0 = 1,
1267 MLX5_VL_HW_0_1 = 2,
1268 MLX5_VL_HW_0_2 = 3,
1269 MLX5_VL_HW_0_3 = 4,
1270 MLX5_VL_HW_0_4 = 5,
1271 MLX5_VL_HW_0_5 = 6,
1272 MLX5_VL_HW_0_6 = 7,
1273 MLX5_VL_HW_0_7 = 8,
1274 MLX5_VL_HW_0_14 = 15
1275};
e126ba97 1276
1b5daf11
MD		 1277static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1278 u8 *max_vl_num)
1279{
1280 switch (vl_hw_cap) {
1281 case MLX5_VL_HW_0:
1282 *max_vl_num = __IB_MAX_VL_0;
1283 break;
1284 case MLX5_VL_HW_0_1:
1285 *max_vl_num = __IB_MAX_VL_0_1;
1286 break;
1287 case MLX5_VL_HW_0_3:
1288 *max_vl_num = __IB_MAX_VL_0_3;
1289 break;
1290 case MLX5_VL_HW_0_7:
1291 *max_vl_num = __IB_MAX_VL_0_7;
1292 break;
1293 case MLX5_VL_HW_0_14:
1294 *max_vl_num = __IB_MAX_VL_0_14;
1295 break;
e126ba97 1296
1b5daf11
MD		 1297 default:
1298 return -EINVAL;
e126ba97 1299 }
e126ba97 1300
1b5daf11 1301 return 0;
e126ba97
EC		 1302}
1303
1b5daf11
MD		 1304static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1305 struct ib_port_attr *props)
e126ba97 1306{
1b5daf11
MD		 1307 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1308 struct mlx5_core_dev *mdev = dev->mdev;
1309 struct mlx5_hca_vport_context *rep;
046339ea
SM		 1310 u16 max_mtu;
1311 u16 oper_mtu;
1b5daf11
MD		 1312 int err;
1313 u8 ib_link_width_oper;
1314 u8 vl_hw_cap;
e126ba97 1315
1b5daf11
MD		 1316 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1317 if (!rep) {
1318 err = -ENOMEM;
e126ba97 1319 goto out;
e126ba97 1320 }
e126ba97 1321
c4550c63 1322 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 1323
1b5daf11 1324 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 1325 if (err)
1326 goto out;
1327
1b5daf11
MD		 1328 props->lid = rep->lid;
1329 props->lmc = rep->lmc;
1330 props->sm_lid = rep->sm_lid;
1331 props->sm_sl = rep->sm_sl;
1332 props->state = rep->vport_state;
1333 props->phys_state = rep->port_physical_state;
1334 props->port_cap_flags = rep->cap_mask1;
1335 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1336 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1337 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1338 props->bad_pkey_cntr = rep->pkey_violation_counter;
1339 props->qkey_viol_cntr = rep->qkey_violation_counter;
1340 props->subnet_timeout = rep->subnet_timeout;
1341 props->init_type_reply = rep->init_type_reply;
e126ba97 1342
4106a758
MG		 1343 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1344 props->port_cap_flags2 = rep->cap_mask2;
1345
1b5daf11
MD		 1346 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1347 if (err)
e126ba97 1348 goto out;
e126ba97 1349
db7a691a
MG		 1350 translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1351
d5beb7f2 1352 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 1353 if (err)
1354 goto out;
1355
facc9699 1356 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 1357
1b5daf11 1358 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 1359
facc9699 1360 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 1361
1b5daf11 1362 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1363
1b5daf11
MD		 1364 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1365 if (err)
1366 goto out;
e126ba97 1367
1b5daf11
MD		 1368 err = translate_max_vl_num(ibdev, vl_hw_cap,
1369 &props->max_vl_num);
e126ba97 1370out:
1b5daf11 1371 kfree(rep);
e126ba97
EC		 1372 return err;
1373}
1374
1b5daf11
MD		 1375int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1376 struct ib_port_attr *props)
e126ba97 1377{
095b0927
IT		 1378 unsigned int count;
1379 int ret;
1380
1b5daf11
MD		 1381 switch (mlx5_get_vport_access_method(ibdev)) {
1382 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1383 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1384 break;
e126ba97 1385
1b5daf11 1386 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1387 ret = mlx5_query_hca_port(ibdev, port, props);
1388 break;
e126ba97 1389
3f89a643 1390 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1391 ret = mlx5_query_port_roce(ibdev, port, props);
1392 break;
3f89a643 1393
1b5daf11 1394 default:
095b0927
IT		 1395 ret = -EINVAL;
1396 }
1397
1398 if (!ret && props) {
b3cbd6f0
DJ		 1399 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1400 struct mlx5_core_dev *mdev;
1401 bool put_mdev = true;
1402
1403 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1404 if (!mdev) {
1405 /* If the port isn't affiliated yet query the master.
1406 * The master and slave will have the same values.
1407 */
1408 mdev = dev->mdev;
1409 port = 1;
1410 put_mdev = false;
1411 }
1412 count = mlx5_core_reserved_gids_count(mdev);
1413 if (put_mdev)
1414 mlx5_ib_put_native_port_mdev(dev, port);
095b0927 1415 props->gid_tbl_len -= count;
1b5daf11 1416 }
095b0927 1417 return ret;
1b5daf11 1418}
e126ba97 1419
8e6efa3a
MB		 1420static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1421 struct ib_port_attr *props)
1422{
1423 int ret;
1424
26628e2d
MB		 1425 /* Only link layer == ethernet is valid for representors
1426 * and we always use port 1
1427 */
8e6efa3a
MB		 1428 ret = mlx5_query_port_roce(ibdev, port, props);
1429 if (ret || !props)
1430 return ret;
1431
1432 /* We don't support GIDS */
1433 props->gid_tbl_len = 0;
1434
1435 return ret;
1436}
1437
1b5daf11
MD		 1438static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1439 union ib_gid *gid)
1440{
1441 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1442 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1443
1b5daf11
MD		 1444 switch (mlx5_get_vport_access_method(ibdev)) {
1445 case MLX5_VPORT_ACCESS_METHOD_MAD:
1446 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1447
1b5daf11
MD		 1448 case MLX5_VPORT_ACCESS_METHOD_HCA:
1449 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1450
1451 default:
1452 return -EINVAL;
1453 }
e126ba97 1454
e126ba97
EC		 1455}
1456
b3cbd6f0
DJ		 1457static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1458 u16 index, u16 *pkey)
1b5daf11
MD		 1459{
1460 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b3cbd6f0
DJ		 1461 struct mlx5_core_dev *mdev;
1462 bool put_mdev = true;
1463 u8 mdev_port_num;
1464 int err;
1b5daf11 1465
b3cbd6f0
DJ		 1466 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1467 if (!mdev) {
1468 /* The port isn't affiliated yet, get the PKey from the master
1469 * port. For RoCE the PKey tables will be the same.
1470 */
1471 put_mdev = false;
1472 mdev = dev->mdev;
1473 mdev_port_num = 1;
1474 }
1475
1476 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1477 index, pkey);
1478 if (put_mdev)
1479 mlx5_ib_put_native_port_mdev(dev, port);
1480
1481 return err;
1482}
1483
1484static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1485 u16 *pkey)
1486{
1b5daf11
MD		 1487 switch (mlx5_get_vport_access_method(ibdev)) {
1488 case MLX5_VPORT_ACCESS_METHOD_MAD:
1489 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1490
1491 case MLX5_VPORT_ACCESS_METHOD_HCA:
1492 case MLX5_VPORT_ACCESS_METHOD_NIC:
b3cbd6f0 1493 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1b5daf11
MD		 1494 default:
1495 return -EINVAL;
1496 }
1497}
e126ba97
EC		 1498
1499static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1500 struct ib_device_modify *props)
1501{
1502 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1503 struct mlx5_reg_node_desc in;
1504 struct mlx5_reg_node_desc out;
1505 int err;
1506
1507 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1508 return -EOPNOTSUPP;
1509
1510 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1511 return 0;
1512
1513 /*
1514 * If possible, pass node desc to FW, so it can generate
1515 * a 144 trap. If cmd fails, just ignore.
1516 */
bd99fdea 1517 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1518 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1519 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1520 if (err)
1521 return err;
1522
bd99fdea 1523 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1524
1525 return err;
1526}
1527
cdbe33d0
EC		 1528static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1529 u32 value)
1530{
1531 struct mlx5_hca_vport_context ctx = {};
b3cbd6f0
DJ		 1532 struct mlx5_core_dev *mdev;
1533 u8 mdev_port_num;
cdbe33d0
EC		 1534 int err;
1535
b3cbd6f0
DJ		 1536 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1537 if (!mdev)
1538 return -ENODEV;
1539
1540 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
cdbe33d0 1541 if (err)
b3cbd6f0 1542 goto out;
cdbe33d0
EC		 1543
1544 if (~ctx.cap_mask1_perm & mask) {
1545 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1546 mask, ctx.cap_mask1_perm);
b3cbd6f0
DJ		 1547 err = -EINVAL;
1548 goto out;
cdbe33d0
EC		 1549 }
1550
1551 ctx.cap_mask1 = value;
1552 ctx.cap_mask1_perm = mask;
b3cbd6f0
DJ		 1553 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1554 0, &ctx);
1555
1556out:
1557 mlx5_ib_put_native_port_mdev(dev, port_num);
cdbe33d0
EC		 1558
1559 return err;
1560}
1561
e126ba97
EC		 1562static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1563 struct ib_port_modify *props)
1564{
1565 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1566 struct ib_port_attr attr;
1567 u32 tmp;
1568 int err;
cdbe33d0
EC		 1569 u32 change_mask;
1570 u32 value;
1571 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1572 IB_LINK_LAYER_INFINIBAND);
1573
ec255879
MD		 1574 /* CM layer calls ib_modify_port() regardless of the link layer. For
1575 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1576 */
1577 if (!is_ib)
1578 return 0;
1579
cdbe33d0
EC		 1580 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1581 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1582 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1583 return set_port_caps_atomic(dev, port, change_mask, value);
1584 }
e126ba97
EC		 1585
1586 mutex_lock(&dev->cap_mask_mutex);
1587
c4550c63 1588 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1589 if (err)
1590 goto out;
1591
1592 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1593 ~props->clr_port_cap_mask;
1594
9603b61d 1595 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1596
1597out:
1598 mutex_unlock(&dev->cap_mask_mutex);
1599 return err;
1600}
1601
30aa60b3
EC		 1602static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1603{
1604 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1605 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1606}
1607
31a78a5a
YH		 1608static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1609{
1610 /* Large page with non 4k uar support might limit the dynamic size */
1611 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1612 return MLX5_MIN_DYN_BFREGS;
1613
1614 return MLX5_MAX_DYN_BFREGS;
1615}
1616
b037c29a
EC		 1617static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1618 struct mlx5_ib_alloc_ucontext_req_v2 *req,
31a78a5a 1619 struct mlx5_bfreg_info *bfregi)
b037c29a
EC		 1620{
1621 int uars_per_sys_page;
1622 int bfregs_per_sys_page;
1623 int ref_bfregs = req->total_num_bfregs;
1624
1625 if (req->total_num_bfregs == 0)
1626 return -EINVAL;
1627
1628 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1629 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1630
1631 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1632 return -ENOMEM;
1633
1634 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1635 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
31a78a5a 1636 /* This holds the required static allocation asked by the user */
b037c29a 1637 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
b037c29a
EC		 1638 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1639 return -EINVAL;
1640
31a78a5a
YH		 1641 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1642 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1643 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1644 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1645
1646 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
b037c29a
EC		 1647 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1648 lib_uar_4k ? "yes" : "no", ref_bfregs,
31a78a5a
YH		 1649 req->total_num_bfregs, bfregi->total_num_bfregs,
1650 bfregi->num_sys_pages);
b037c29a
EC		 1651
1652 return 0;
1653}
1654
1655static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1656{
1657 struct mlx5_bfreg_info *bfregi;
1658 int err;
1659 int i;
1660
1661 bfregi = &context->bfregi;
31a78a5a 1662 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
b037c29a
EC		 1663 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1664 if (err)
1665 goto error;
1666
1667 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1668 }
4ed131d0
YH		 1669
1670 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1671 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1672
b037c29a
EC		 1673 return 0;
1674
1675error:
1676 for (--i; i >= 0; i--)
1677 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1678 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1679
1680 return err;
1681}
1682
15177999
LR		 1683static void deallocate_uars(struct mlx5_ib_dev *dev,
1684 struct mlx5_ib_ucontext *context)
b037c29a
EC		 1685{
1686 struct mlx5_bfreg_info *bfregi;
b037c29a
EC		 1687 int i;
1688
1689 bfregi = &context->bfregi;
15177999 1690 for (i = 0; i < bfregi->num_sys_pages; i++)
4ed131d0 1691 if (i < bfregi->num_static_sys_pages ||
15177999
LR		 1692 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1693 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
b037c29a
EC		 1694}
1695
0042f9e4 1696int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
a560f1d9
MB		 1697{
1698 int err = 0;
1699
1700 mutex_lock(&dev->lb.mutex);
0042f9e4
MB		 1701 if (td)
1702 dev->lb.user_td++;
1703 if (qp)
1704 dev->lb.qps++;
1705
1706 if (dev->lb.user_td == 2 ||
1707 dev->lb.qps == 1) {
1708 if (!dev->lb.enabled) {
1709 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1710 dev->lb.enabled = true;
1711 }
1712 }
a560f1d9
MB		 1713
1714 mutex_unlock(&dev->lb.mutex);
1715
1716 return err;
1717}
1718
0042f9e4 1719void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
a560f1d9
MB		 1720{
1721 mutex_lock(&dev->lb.mutex);
0042f9e4
MB		 1722 if (td)
1723 dev->lb.user_td--;
1724 if (qp)
1725 dev->lb.qps--;
1726
1727 if (dev->lb.user_td == 1 &&
1728 dev->lb.qps == 0) {
1729 if (dev->lb.enabled) {
1730 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1731 dev->lb.enabled = false;
1732 }
1733 }
a560f1d9
MB		 1734
1735 mutex_unlock(&dev->lb.mutex);
1736}
1737
d2d19121
YH		 1738static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1739 u16 uid)
c85023e1
HN		 1740{
1741 int err;
1742
cfdeb893
LR		 1743 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1744 return 0;
1745
d2d19121 1746 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
c85023e1
HN		 1747 if (err)
1748 return err;
1749
1750 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1751 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1752 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1753 return err;
1754
0042f9e4 1755 return mlx5_ib_enable_lb(dev, true, false);
c85023e1
HN		 1756}
1757
d2d19121
YH		 1758static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1759 u16 uid)
c85023e1 1760{
cfdeb893
LR		 1761 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1762 return;
1763
d2d19121 1764 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
c85023e1
HN		 1765
1766 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1767 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1768 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1769 return;
1770
0042f9e4 1771 mlx5_ib_disable_lb(dev, true, false);
c85023e1
HN		 1772}
1773
a2a074ef
LR		 1774static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1775 struct ib_udata *udata)
e126ba97 1776{
a2a074ef 1777 struct ib_device *ibdev = uctx->device;
e126ba97 1778 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1779 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1780 struct mlx5_ib_alloc_ucontext_resp resp = {};
5c99eaec 1781 struct mlx5_core_dev *mdev = dev->mdev;
a2a074ef 1782 struct mlx5_ib_ucontext *context = to_mucontext(uctx);
2f5ff264 1783 struct mlx5_bfreg_info *bfregi;
78c0f98c 1784 int ver;
e126ba97 1785 int err;
a168a41c
MD		 1786 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1787 max_cqe_version);
25bb36e7 1788 u32 dump_fill_mkey;
b037c29a 1789 bool lib_uar_4k;
0a2fd01c 1790 bool lib_uar_dyn;
e126ba97
EC		 1791
1792 if (!dev->ib_active)
a2a074ef 1793 return -EAGAIN;
e126ba97 1794
e093111d 1795 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1796 ver = 0;
e093111d 1797 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1798 ver = 2;
1799 else
a2a074ef 1800 return -EINVAL;
78c0f98c 1801
e093111d 1802 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97 1803 if (err)
a2a074ef 1804 return err;
e126ba97 1805
a8b92ca1 1806 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
a2a074ef 1807 return -EOPNOTSUPP;
78c0f98c 1808
f72300c5 1809 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
a2a074ef 1810 return -EOPNOTSUPP;
b368d7cb 1811
2f5ff264
EC		 1812 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1813 MLX5_NON_FP_BFREGS_PER_UAR);
1814 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
a2a074ef 1815 return -EINVAL;
e126ba97 1816
938fe83c 1817 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
11f552e2 1818 if (dev->wc_support)
2cc6ad5f 1819 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1820 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1821 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1822 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1823 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1824 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1825 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1826 resp.cqe_version = min_t(__u8,
1827 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1828 req.max_cqe_version);
30aa60b3
EC		 1829 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1830 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1831 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1832 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1833 resp.response_length = min(offsetof(typeof(resp), response_length) +
1834 sizeof(resp.response_length), udata->outlen);
e126ba97 1835
c03faa56
MB		 1836 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1837 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1838 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1839 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1840 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1841 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1842 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1843 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1844 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1845 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1846 }
1847
30aa60b3 1848 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
0a2fd01c 1849 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR;
2f5ff264 1850 bfregi = &context->bfregi;
b037c29a 1851
0a2fd01c
YH		 1852 if (lib_uar_dyn) {
1853 bfregi->lib_uar_dyn = lib_uar_dyn;
1854 goto uar_done;
1855 }
1856
b037c29a 1857 /* updates req->total_num_bfregs */
31a78a5a 1858 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
b037c29a 1859 if (err)
e126ba97 1860 goto out_ctx;
e126ba97 1861
b037c29a
EC		 1862 mutex_init(&bfregi->lock);
1863 bfregi->lib_uar_4k = lib_uar_4k;
31a78a5a 1864 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1865 GFP_KERNEL);
b037c29a 1866 if (!bfregi->count) {
e126ba97 1867 err = -ENOMEM;
b037c29a 1868 goto out_ctx;
e126ba97
EC		 1869 }
1870
b037c29a
EC		 1871 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1872 sizeof(*bfregi->sys_pages),
1873 GFP_KERNEL);
1874 if (!bfregi->sys_pages) {
e126ba97 1875 err = -ENOMEM;
b037c29a 1876 goto out_count;
e126ba97
EC		 1877 }
1878
b037c29a
EC		 1879 err = allocate_uars(dev, context);
1880 if (err)
1881 goto out_sys_pages;
e126ba97 1882
0a2fd01c 1883uar_done:
a8b92ca1 1884 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
fb98153b 1885 err = mlx5_ib_devx_create(dev, true);
76dc5a84 1886 if (err < 0)
d2d19121 1887 goto out_uars;
76dc5a84 1888 context->devx_uid = err;
a8b92ca1
YH		 1889 }
1890
d2d19121
YH		 1891 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1892 context->devx_uid);
1893 if (err)
1894 goto out_devx;
1895
25bb36e7
YC		 1896 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1897 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1898 if (err)
8193abb6 1899 goto out_mdev;
25bb36e7
YC		 1900 }
1901
e126ba97
EC		 1902 INIT_LIST_HEAD(&context->db_page_list);
1903 mutex_init(&context->db_page_mutex);
1904
0a2fd01c 1905 resp.tot_bfregs = lib_uar_dyn ? 0 : req.total_num_bfregs;
508562d6 1906 resp.num_ports = dev->num_ports;
b368d7cb 1907
a762d460 1908 if (offsetofend(typeof(resp), cqe_version) <= udata->outlen)
f72300c5 1909 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1910
a762d460 1911 if (offsetofend(typeof(resp), cmds_supp_uhw) <= udata->outlen) {
6ad279c5
MS		 1912 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1913 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1914 resp.response_length += sizeof(resp.cmds_supp_uhw);
1915 }
1916
a762d460 1917 if (offsetofend(typeof(resp), eth_min_inline) <= udata->outlen) {
78984898
OG		 1918 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1919 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1920 resp.eth_min_inline++;
1921 }
1922 resp.response_length += sizeof(resp.eth_min_inline);
1923 }
1924
a762d460 1925 if (offsetofend(typeof(resp), clock_info_versions) <= udata->outlen) {
5c99eaec
FD		 1926 if (mdev->clock_info)
1927 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1928 resp.response_length += sizeof(resp.clock_info_versions);
1929 }
1930
bc5c6eed
NO		 1931 /*
1932 * We don't want to expose information from the PCI bar that is located
1933 * after 4096 bytes, so if the arch only supports larger pages, let's
1934 * pretend we don't support reading the HCA's core clock. This is also
1935 * forced by mmap function.
1936 */
a762d460 1937 if (offsetofend(typeof(resp), hca_core_clock_offset) <= udata->outlen) {
de8d6e02
EC		 1938 if (PAGE_SIZE <= 4096) {
1939 resp.comp_mask |=
1940 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1941 resp.hca_core_clock_offset =
1942 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1943 }
5c99eaec 1944 resp.response_length += sizeof(resp.hca_core_clock_offset);
b368d7cb
MB		 1945 }
1946
a762d460 1947 if (offsetofend(typeof(resp), log_uar_size) <= udata->outlen)
30aa60b3
EC		 1948 resp.response_length += sizeof(resp.log_uar_size);
1949
a762d460 1950 if (offsetofend(typeof(resp), num_uars_per_page) <= udata->outlen)
30aa60b3
EC		 1951 resp.response_length += sizeof(resp.num_uars_per_page);
1952
a762d460 1953 if (offsetofend(typeof(resp), num_dyn_bfregs) <= udata->outlen) {
31a78a5a
YH		 1954 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1955 resp.response_length += sizeof(resp.num_dyn_bfregs);
1956 }
1957
a762d460 1958 if (offsetofend(typeof(resp), dump_fill_mkey) <= udata->outlen) {
25bb36e7
YC		 1959 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1960 resp.dump_fill_mkey = dump_fill_mkey;
1961 resp.comp_mask |=
1962 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1963 }
1964 resp.response_length += sizeof(resp.dump_fill_mkey);
1965 }
1966
b368d7cb 1967 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1968 if (err)
a8b92ca1 1969 goto out_mdev;
e126ba97 1970
2f5ff264
EC		 1971 bfregi->ver = ver;
1972 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1973 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1974 context->lib_caps = req.lib_caps;
1975 print_lib_caps(dev, context->lib_caps);
f72300c5 1976
7c34ec19 1977 if (dev->lag_active) {
95579e78 1978 u8 port = mlx5_core_native_port_num(dev->mdev) - 1;
c6a21c38
MD		 1979
1980 atomic_set(&context->tx_port_affinity,
1981 atomic_add_return(
95579e78 1982 1, &dev->port[port].roce.tx_port_affinity));
c6a21c38
MD		 1983 }
1984
a2a074ef 1985 return 0;
e126ba97 1986
a8b92ca1 1987out_mdev:
d2d19121
YH		 1988 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1989out_devx:
a8b92ca1 1990 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
76dc5a84 1991 mlx5_ib_devx_destroy(dev, context->devx_uid);
146d2f1a 1992
e126ba97 1993out_uars:
b037c29a 1994 deallocate_uars(dev, context);
e126ba97 1995
b037c29a
EC		 1996out_sys_pages:
1997 kfree(bfregi->sys_pages);
e126ba97 1998
b037c29a
EC		 1999out_count:
2000 kfree(bfregi->count);
e126ba97
EC		 2001
2002out_ctx:
a2a074ef 2003 return err;
e126ba97
EC		 2004}
2005
a2a074ef 2006static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
e126ba97
EC		 2007{
2008 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2009 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 2010 struct mlx5_bfreg_info *bfregi;
e126ba97 2011
b037c29a 2012 bfregi = &context->bfregi;
d2d19121
YH		 2013 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
2014
a8b92ca1 2015 if (context->devx_uid)
76dc5a84 2016 mlx5_ib_devx_destroy(dev, context->devx_uid);
146d2f1a 2017
b037c29a
EC		 2018 deallocate_uars(dev, context);
2019 kfree(bfregi->sys_pages);
2f5ff264 2020 kfree(bfregi->count);
e126ba97
EC		 2021}
2022
b037c29a 2023static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
4ed131d0 2024 int uar_idx)
e126ba97 2025{
b037c29a
EC		 2026 int fw_uars_per_page;
2027
2028 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2029
aa8106f1 2030 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
e126ba97
EC		 2031}
2032
342ee59d
YH		 2033static u64 uar_index2paddress(struct mlx5_ib_dev *dev,
2034 int uar_idx)
2035{
2036 unsigned int fw_uars_per_page;
2037
2038 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
2039 MLX5_UARS_IN_PAGE : 1;
2040
2041 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE);
2042}
2043
e126ba97
EC		 2044static int get_command(unsigned long offset)
2045{
2046 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2047}
2048
2049static int get_arg(unsigned long offset)
2050{
2051 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2052}
2053
2054static int get_index(unsigned long offset)
2055{
2056 return get_arg(offset);
2057}
2058
4ed131d0
YH		 2059/* Index resides in an extra byte to enable larger values than 255 */
2060static int get_extended_index(unsigned long offset)
2061{
2062 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2063}
2064
7c2344c3
MG		 2065
2066static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2067{
7c2344c3
MG		 2068}
2069
37aa5c36
GL		 2070static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2071{
2072 switch (cmd) {
2073 case MLX5_IB_MMAP_WC_PAGE:
2074 return "WC";
2075 case MLX5_IB_MMAP_REGULAR_PAGE:
2076 return "best effort WC";
2077 case MLX5_IB_MMAP_NC_PAGE:
2078 return "NC";
24da0016
AL		 2079 case MLX5_IB_MMAP_DEVICE_MEM:
2080 return "Device Memory";
37aa5c36
GL		 2081 default:
2082 return NULL;
2083 }
2084}
2085
5c99eaec
FD		 2086static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2087 struct vm_area_struct *vma,
2088 struct mlx5_ib_ucontext *context)
2089{
4eb6ab13
JG		 2090 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2091 !(vma->vm_flags & VM_SHARED))
5c99eaec
FD		 2092 return -EINVAL;
2093
2094 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2095 return -EOPNOTSUPP;
2096
4eb6ab13 2097 if (vma->vm_flags & (VM_WRITE | VM_EXEC))
5c99eaec 2098 return -EPERM;
c660133c 2099 vma->vm_flags &= ~VM_MAYWRITE;
5c99eaec 2100
ddcdc368 2101 if (!dev->mdev->clock_info)
5c99eaec
FD		 2102 return -EOPNOTSUPP;
2103
4eb6ab13
JG		 2104 return vm_insert_page(vma, vma->vm_start,
2105 virt_to_page(dev->mdev->clock_info));
5c99eaec
FD		 2106}
2107
dc2316eb
YH		 2108static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry)
2109{
2110 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry);
2111 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device);
7be76bef 2112 struct mlx5_var_table *var_table = &dev->var_table;
dc2316eb
YH		 2113 struct mlx5_ib_dm *mdm;
2114
2115 switch (mentry->mmap_flag) {
2116 case MLX5_IB_MMAP_TYPE_MEMIC:
2117 mdm = container_of(mentry, struct mlx5_ib_dm, mentry);
2118 mlx5_cmd_dealloc_memic(&dev->dm, mdm->dev_addr,
2119 mdm->size);
2120 kfree(mdm);
2121 break;
7be76bef
YH		 2122 case MLX5_IB_MMAP_TYPE_VAR:
2123 mutex_lock(&var_table->bitmap_lock);
2124 clear_bit(mentry->page_idx, var_table->bitmap);
2125 mutex_unlock(&var_table->bitmap_lock);
2126 kfree(mentry);
2127 break;
342ee59d
YH		 2128 case MLX5_IB_MMAP_TYPE_UAR_WC:
2129 case MLX5_IB_MMAP_TYPE_UAR_NC:
2130 mlx5_cmd_free_uar(dev->mdev, mentry->page_idx);
2131 kfree(mentry);
2132 break;
dc2316eb
YH		 2133 default:
2134 WARN_ON(true);
2135 }
2136}
2137
37aa5c36 2138static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 2139 struct vm_area_struct *vma,
2140 struct mlx5_ib_ucontext *context)
37aa5c36 2141{
2f5ff264 2142 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 2143 int err;
2144 unsigned long idx;
aa09ea6e 2145 phys_addr_t pfn;
37aa5c36 2146 pgprot_t prot;
4ed131d0
YH		 2147 u32 bfreg_dyn_idx = 0;
2148 u32 uar_index;
2149 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2150 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2151 bfregi->num_static_sys_pages;
b037c29a 2152
0a2fd01c
YH		 2153 if (bfregi->lib_uar_dyn)
2154 return -EINVAL;
2155
b037c29a
EC		 2156 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2157 return -EINVAL;
2158
4ed131d0
YH		 2159 if (dyn_uar)
2160 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2161 else
2162 idx = get_index(vma->vm_pgoff);
2163
2164 if (idx >= max_valid_idx) {
2165 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2166 idx, max_valid_idx);
b037c29a
EC		 2167 return -EINVAL;
2168 }
37aa5c36
GL		 2169
2170 switch (cmd) {
2171 case MLX5_IB_MMAP_WC_PAGE:
4ed131d0 2172 case MLX5_IB_MMAP_ALLOC_WC:
37aa5c36
GL		 2173 case MLX5_IB_MMAP_REGULAR_PAGE:
2174 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2175 prot = pgprot_writecombine(vma->vm_page_prot);
2176 break;
2177 case MLX5_IB_MMAP_NC_PAGE:
2178 prot = pgprot_noncached(vma->vm_page_prot);
2179 break;
2180 default:
2181 return -EINVAL;
2182 }
2183
4ed131d0
YH		 2184 if (dyn_uar) {
2185 int uars_per_page;
2186
2187 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2188 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2189 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2190 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2191 bfreg_dyn_idx, bfregi->total_num_bfregs);
2192 return -EINVAL;
2193 }
2194
2195 mutex_lock(&bfregi->lock);
2196 /* Fail if uar already allocated, first bfreg index of each
2197 * page holds its count.
2198 */
2199 if (bfregi->count[bfreg_dyn_idx]) {
2200 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2201 mutex_unlock(&bfregi->lock);
2202 return -EINVAL;
2203 }
2204
2205 bfregi->count[bfreg_dyn_idx]++;
2206 mutex_unlock(&bfregi->lock);
2207
2208 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2209 if (err) {
2210 mlx5_ib_warn(dev, "UAR alloc failed\n");
2211 goto free_bfreg;
2212 }
2213 } else {
2214 uar_index = bfregi->sys_pages[idx];
2215 }
2216
2217 pfn = uar_index2pfn(dev, uar_index);
37aa5c36
GL		 2218 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2219
e2cd1d1a 2220 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
c043ff2c 2221 prot, NULL);
37aa5c36 2222 if (err) {
8f062287 2223 mlx5_ib_err(dev,
e2cd1d1a 2224 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
8f062287 2225 err, mmap_cmd2str(cmd));
4ed131d0 2226 goto err;
37aa5c36
GL		 2227 }
2228
4ed131d0
YH		 2229 if (dyn_uar)
2230 bfregi->sys_pages[idx] = uar_index;
2231 return 0;
2232
2233err:
2234 if (!dyn_uar)
2235 return err;
2236
2237 mlx5_cmd_free_uar(dev->mdev, idx);
2238
2239free_bfreg:
2240 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2241
2242 return err;
37aa5c36
GL		 2243}
2244
dc2316eb
YH		 2245static int add_dm_mmap_entry(struct ib_ucontext *context,
2246 struct mlx5_ib_dm *mdm,
2247 u64 address)
2248{
2249 mdm->mentry.mmap_flag = MLX5_IB_MMAP_TYPE_MEMIC;
2250 mdm->mentry.address = address;
2251 return rdma_user_mmap_entry_insert_range(
2252 context, &mdm->mentry.rdma_entry,
2253 mdm->size,
2254 MLX5_IB_MMAP_DEVICE_MEM << 16,
2255 (MLX5_IB_MMAP_DEVICE_MEM << 16) + (1UL << 16) - 1);
2256}
2257
2258static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma)
2259{
2260 unsigned long idx;
2261 u8 command;
2262
2263 command = get_command(vma->vm_pgoff);
2264 idx = get_extended_index(vma->vm_pgoff);
2265
2266 return (command << 16 | idx);
2267}
2268
2269static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev,
2270 struct vm_area_struct *vma,
2271 struct ib_ucontext *ucontext)
24da0016 2272{
dc2316eb
YH		 2273 struct mlx5_user_mmap_entry *mentry;
2274 struct rdma_user_mmap_entry *entry;
2275 unsigned long pgoff;
2276 pgprot_t prot;
24da0016 2277 phys_addr_t pfn;
dc2316eb 2278 int ret;
24da0016 2279
dc2316eb
YH		 2280 pgoff = mlx5_vma_to_pgoff(vma);
2281 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff);
2282 if (!entry)
24da0016
AL		 2283 return -EINVAL;
2284
dc2316eb
YH		 2285 mentry = to_mmmap(entry);
2286 pfn = (mentry->address >> PAGE_SHIFT);
342ee59d
YH		 2287 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR ||
2288 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC)
3f59b6c3
YH		 2289 prot = pgprot_noncached(vma->vm_page_prot);
2290 else
2291 prot = pgprot_writecombine(vma->vm_page_prot);
dc2316eb
YH		 2292 ret = rdma_user_mmap_io(ucontext, vma, pfn,
2293 entry->npages * PAGE_SIZE,
2294 prot,
2295 entry);
2296 rdma_user_mmap_entry_put(&mentry->rdma_entry);
2297 return ret;
24da0016
AL		 2298}
2299
7be76bef
YH		 2300static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry)
2301{
9b6d3bbc
LR		 2302 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF;
2303 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF;
7be76bef
YH		 2304
2305 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) |
2306 (index & 0xFF)) << PAGE_SHIFT;
2307}
2308
e126ba97
EC		 2309static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2310{
2311 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2312 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 2313 unsigned long command;
e126ba97
EC		 2314 phys_addr_t pfn;
2315
2316 command = get_command(vma->vm_pgoff);
2317 switch (command) {
37aa5c36 2318 case MLX5_IB_MMAP_WC_PAGE:
1f3db161
YH		 2319 case MLX5_IB_MMAP_ALLOC_WC:
2320 if (!dev->wc_support)
2321 return -EPERM;
2322 fallthrough;
37aa5c36 2323 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 2324 case MLX5_IB_MMAP_REGULAR_PAGE:
7c2344c3 2325 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 2326
2327 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2328 return -ENOSYS;
2329
d69e3bcf 2330 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 2331 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2332 return -EINVAL;
2333
6cbac1e4 2334 if (vma->vm_flags & VM_WRITE)
d69e3bcf 2335 return -EPERM;
c660133c 2336 vma->vm_flags &= ~VM_MAYWRITE;
d69e3bcf
MB		 2337
2338 /* Don't expose to user-space information it shouldn't have */
2339 if (PAGE_SIZE > 4096)
2340 return -EOPNOTSUPP;
2341
d69e3bcf
MB		 2342 pfn = (dev->mdev->iseg_base +
2343 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2344 PAGE_SHIFT;
d5e560d3
JG		 2345 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2346 PAGE_SIZE,
c043ff2c
MK		 2347 pgprot_noncached(vma->vm_page_prot),
2348 NULL);
5c99eaec
FD		 2349 case MLX5_IB_MMAP_CLOCK_INFO:
2350 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
d69e3bcf 2351
e126ba97 2352 default:
dc2316eb 2353 return mlx5_ib_mmap_offset(dev, vma, ibcontext);
e126ba97
EC		 2354 }
2355
2356 return 0;
2357}
2358
25c13324
AL		 2359static inline int check_dm_type_support(struct mlx5_ib_dev *dev,
2360 u32 type)
24da0016 2361{
25c13324
AL		 2362 switch (type) {
2363 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2364 if (!MLX5_CAP_DEV_MEM(dev->mdev, memic))
2365 return -EOPNOTSUPP;
2366 break;
2367 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
c9b9dcb4 2368 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
25c13324
AL		 2369 if (!capable(CAP_SYS_RAWIO) ||
2370 !capable(CAP_NET_RAW))
2371 return -EPERM;
2372
2373 if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
2374 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner)))
2375 return -EOPNOTSUPP;
2376 break;
2377 }
2378
2379 return 0;
2380}
2381
3b113a1e
AL		 2382static int handle_alloc_dm_memic(struct ib_ucontext *ctx,
2383 struct mlx5_ib_dm *dm,
2384 struct ib_dm_alloc_attr *attr,
2385 struct uverbs_attr_bundle *attrs)
24da0016 2386{
3b113a1e 2387 struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm;
24da0016 2388 u64 start_offset;
dc2316eb 2389 u16 page_idx;
24da0016 2390 int err;
dc2316eb 2391 u64 address;
24da0016 2392
3b113a1e 2393 dm->size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
24da0016 2394
3b113a1e
AL		 2395 err = mlx5_cmd_alloc_memic(dm_db, &dm->dev_addr,
2396 dm->size, attr->alignment);
24da0016 2397 if (err)
3b113a1e 2398 return err;
24da0016 2399
dc2316eb
YH		 2400 address = dm->dev_addr & PAGE_MASK;
2401 err = add_dm_mmap_entry(ctx, dm, address);
2402 if (err)
2403 goto err_dealloc;
24da0016 2404
dc2316eb 2405 page_idx = dm->mentry.rdma_entry.start_pgoff & 0xFFFF;
24da0016 2406 err = uverbs_copy_to(attrs,
3b113a1e 2407 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
dc2316eb
YH		 2408 &page_idx,
2409 sizeof(page_idx));
24da0016 2410 if (err)
dc2316eb 2411 goto err_copy;
24da0016 2412
3b113a1e 2413 start_offset = dm->dev_addr & ~PAGE_MASK;
24da0016
AL		 2414 err = uverbs_copy_to(attrs,
2415 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2416 &start_offset, sizeof(start_offset));
2417 if (err)
dc2316eb 2418 goto err_copy;
3b113a1e
AL		 2419
2420 return 0;
2421
dc2316eb
YH		 2422err_copy:
2423 rdma_user_mmap_entry_remove(&dm->mentry.rdma_entry);
3b113a1e
AL		 2424err_dealloc:
2425 mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2426
2427 return err;
2428}
2429
25c13324
AL		 2430static int handle_alloc_dm_sw_icm(struct ib_ucontext *ctx,
2431 struct mlx5_ib_dm *dm,
2432 struct ib_dm_alloc_attr *attr,
2433 struct uverbs_attr_bundle *attrs,
2434 int type)
2435{
c9b9dcb4 2436 struct mlx5_core_dev *dev = to_mdev(ctx->device)->mdev;
25c13324
AL		 2437 u64 act_size;
2438 int err;
2439
2440 /* Allocation size must a multiple of the basic block size
2441 * and a power of 2.
2442 */
c9b9dcb4 2443 act_size = round_up(attr->length, MLX5_SW_ICM_BLOCK_SIZE(dev));
25c13324
AL		 2444 act_size = roundup_pow_of_two(act_size);
2445
2446 dm->size = act_size;
dff8e2d1 2447 err = mlx5_dm_sw_icm_alloc(dev, type, act_size, attr->alignment,
c9b9dcb4
AL		 2448 to_mucontext(ctx)->devx_uid, &dm->dev_addr,
2449 &dm->icm_dm.obj_id);
25c13324
AL		 2450 if (err)
2451 return err;
2452
24da0016 2453 err = uverbs_copy_to(attrs,
25c13324
AL		 2454 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2455 &dm->dev_addr, sizeof(dm->dev_addr));
24da0016 2456 if (err)
c9b9dcb4
AL		 2457 mlx5_dm_sw_icm_dealloc(dev, type, dm->size,
2458 to_mucontext(ctx)->devx_uid, dm->dev_addr,
2459 dm->icm_dm.obj_id);
25c13324
AL		 2460
2461 return err;
2462}
2463
3b113a1e
AL		 2464struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2465 struct ib_ucontext *context,
2466 struct ib_dm_alloc_attr *attr,
2467 struct uverbs_attr_bundle *attrs)
2468{
2469 struct mlx5_ib_dm *dm;
2470 enum mlx5_ib_uapi_dm_type type;
2471 int err;
24da0016 2472
3b113a1e
AL		 2473 err = uverbs_get_const_default(&type, attrs,
2474 MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
2475 MLX5_IB_UAPI_DM_TYPE_MEMIC);
2476 if (err)
2477 return ERR_PTR(err);
24da0016 2478
3b113a1e
AL		 2479 mlx5_ib_dbg(to_mdev(ibdev), "alloc_dm req: dm_type=%d user_length=0x%llx log_alignment=%d\n",
2480 type, attr->length, attr->alignment);
2481
25c13324
AL		 2482 err = check_dm_type_support(to_mdev(ibdev), type);
2483 if (err)
2484 return ERR_PTR(err);
2485
3b113a1e
AL		 2486 dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2487 if (!dm)
2488 return ERR_PTR(-ENOMEM);
2489
2490 dm->type = type;
2491
2492 switch (type) {
2493 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2494 err = handle_alloc_dm_memic(context, dm,
2495 attr,
2496 attrs);
2497 break;
25c13324 2498 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
c9b9dcb4
AL		 2499 err = handle_alloc_dm_sw_icm(context, dm,
2500 attr, attrs,
2501 MLX5_SW_ICM_TYPE_STEERING);
2502 break;
25c13324 2503 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
c9b9dcb4
AL		 2504 err = handle_alloc_dm_sw_icm(context, dm,
2505 attr, attrs,
2506 MLX5_SW_ICM_TYPE_HEADER_MODIFY);
25c13324 2507 break;
3b113a1e
AL		 2508 default:
2509 err = -EOPNOTSUPP;
2510 }
24da0016 2511
3b113a1e
AL		 2512 if (err)
2513 goto err_free;
24da0016
AL		 2514
2515 return &dm->ibdm;
2516
24da0016
AL		 2517err_free:
2518 kfree(dm);
2519 return ERR_PTR(err);
2520}
2521
c4367a26 2522int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs)
24da0016 2523{
25c13324
AL		 2524 struct mlx5_ib_ucontext *ctx = rdma_udata_to_drv_context(
2525 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
c9b9dcb4 2526 struct mlx5_core_dev *dev = to_mdev(ibdm->device)->mdev;
24da0016 2527 struct mlx5_ib_dm *dm = to_mdm(ibdm);
24da0016
AL		 2528 int ret;
2529
3b113a1e
AL		 2530 switch (dm->type) {
2531 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
dc2316eb
YH		 2532 rdma_user_mmap_entry_remove(&dm->mentry.rdma_entry);
2533 return 0;
25c13324 2534 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
c9b9dcb4
AL		 2535 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_STEERING,
2536 dm->size, ctx->devx_uid, dm->dev_addr,
2537 dm->icm_dm.obj_id);
2538 if (ret)
2539 return ret;
2540 break;
25c13324 2541 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
c9b9dcb4
AL		 2542 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_HEADER_MODIFY,
2543 dm->size, ctx->devx_uid, dm->dev_addr,
2544 dm->icm_dm.obj_id);
25c13324
AL		 2545 if (ret)
2546 return ret;
3b113a1e
AL		 2547 break;
2548 default:
2549 return -EOPNOTSUPP;
2550 }
24da0016
AL		 2551
2552 kfree(dm);
2553
2554 return 0;
2555}
2556
ff23dfa1 2557static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
e126ba97 2558{
21a428a0
LR		 2559 struct mlx5_ib_pd *pd = to_mpd(ibpd);
2560 struct ib_device *ibdev = ibpd->device;
e126ba97 2561 struct mlx5_ib_alloc_pd_resp resp;
e126ba97 2562 int err;
a1069c1c
YH		 2563 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2564 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
2565 u16 uid = 0;
ff23dfa1
SR		 2566 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2567 udata, struct mlx5_ib_ucontext, ibucontext);
e126ba97 2568
ff23dfa1 2569 uid = context ? context->devx_uid : 0;
a1069c1c
YH		 2570 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2571 MLX5_SET(alloc_pd_in, in, uid, uid);
2572 err = mlx5_cmd_exec(to_mdev(ibdev)->mdev, in, sizeof(in),
2573 out, sizeof(out));
21a428a0
LR		 2574 if (err)
2575 return err;
e126ba97 2576
a1069c1c
YH		 2577 pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2578 pd->uid = uid;
ff23dfa1 2579 if (udata) {
e126ba97
EC		 2580 resp.pdn = pd->pdn;
2581 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
a1069c1c 2582 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
21a428a0 2583 return -EFAULT;
e126ba97 2584 }
e126ba97
EC		 2585 }
2586
21a428a0 2587 return 0;
e126ba97
EC		 2588}
2589
c4367a26 2590static void mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
e126ba97
EC		 2591{
2592 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2593 struct mlx5_ib_pd *mpd = to_mpd(pd);
2594
a1069c1c 2595 mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
e126ba97
EC		 2596}
2597
466fa6d2
MG		 2598enum {
2599 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2600 MATCH_CRITERIA_ENABLE_MISC_BIT,
71c6e863
AL		 2601 MATCH_CRITERIA_ENABLE_INNER_BIT,
2602 MATCH_CRITERIA_ENABLE_MISC2_BIT
466fa6d2
MG		 2603};
2604
2605#define HEADER_IS_ZERO(match_criteria, headers) \
2606 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2607 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 2608
466fa6d2 2609static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 2610{
466fa6d2 2611 u8 match_criteria_enable;
038d2ef8 2612
466fa6d2
MG		 2613 match_criteria_enable =
2614 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2615 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2616 match_criteria_enable |=
2617 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2618 MATCH_CRITERIA_ENABLE_MISC_BIT;
2619 match_criteria_enable |=
2620 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2621 MATCH_CRITERIA_ENABLE_INNER_BIT;
71c6e863
AL		 2622 match_criteria_enable |=
2623 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2624 MATCH_CRITERIA_ENABLE_MISC2_BIT;
466fa6d2
MG		 2625
2626 return match_criteria_enable;
038d2ef8
MG		 2627}
2628
6113cc44 2629static int set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
ca0d4753 2630{
6113cc44
MG		 2631 u8 entry_mask;
2632 u8 entry_val;
2633 int err = 0;
2634
2635 if (!mask)
2636 goto out;
2637
2638 entry_mask = MLX5_GET(fte_match_set_lyr_2_4, outer_c,
2639 ip_protocol);
2640 entry_val = MLX5_GET(fte_match_set_lyr_2_4, outer_v,
2641 ip_protocol);
2642 if (!entry_mask) {
2643 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2644 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2645 goto out;
2646 }
2647 /* Don't override existing ip protocol */
2648 if (mask != entry_mask || val != entry_val)
2649 err = -EINVAL;
2650out:
2651 return err;
038d2ef8
MG		 2652}
2653
37da2a03 2654static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2d1e697e
MR		 2655 bool inner)
2656{
2657 if (inner) {
2658 MLX5_SET(fte_match_set_misc,
2659 misc_c, inner_ipv6_flow_label, mask);
2660 MLX5_SET(fte_match_set_misc,
2661 misc_v, inner_ipv6_flow_label, val);
2662 } else {
2663 MLX5_SET(fte_match_set_misc,
2664 misc_c, outer_ipv6_flow_label, mask);
2665 MLX5_SET(fte_match_set_misc,
2666 misc_v, outer_ipv6_flow_label, val);
2667 }
2668}
2669
ca0d4753
MG		 2670static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2671{
2672 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2673 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2674 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2675 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2676}
2677
71c6e863
AL		 2678static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2679{
2680 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2681 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2682 return -EOPNOTSUPP;
2683
2684 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2685 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2686 return -EOPNOTSUPP;
2687
2688 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2689 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2690 return -EOPNOTSUPP;
2691
2692 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2693 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2694 return -EOPNOTSUPP;
2695
2696 return 0;
2697}
2698
c47ac6ae
MG		 2699#define LAST_ETH_FIELD vlan_tag
2700#define LAST_IB_FIELD sl
ca0d4753 2701#define LAST_IPV4_FIELD tos
466fa6d2 2702#define LAST_IPV6_FIELD traffic_class
c47ac6ae 2703#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 2704#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 2705#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 2706#define LAST_DROP_FIELD size
3b3233fb 2707#define LAST_COUNTERS_FIELD counters
c47ac6ae
MG		 2708
2709/* Field is the last supported field */
2710#define FIELDS_NOT_SUPPORTED(filter, field)\
2711 memchr_inv((void *)&filter.field +\
2712 sizeof(filter.field), 0,\
2713 sizeof(filter) -\
2714 offsetof(typeof(filter), field) -\
2715 sizeof(filter.field))
2716
2ea26203
MB		 2717int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
2718 bool is_egress,
2719 struct mlx5_flow_act *action)
802c2125 2720{
802c2125
AY		 2721
2722 switch (maction->ib_action.type) {
2723 case IB_FLOW_ACTION_ESP:
501f14e3
MB		 2724 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2725 MLX5_FLOW_CONTEXT_ACTION_DECRYPT))
2726 return -EINVAL;
802c2125
AY		 2727 /* Currently only AES_GCM keymat is supported by the driver */
2728 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2ea26203 2729 action->action |= is_egress ?
802c2125
AY		 2730 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2731 MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2732 return 0;
b1085be3
MB		 2733 case IB_FLOW_ACTION_UNSPECIFIED:
2734 if (maction->flow_action_raw.sub_type ==
2735 MLX5_IB_FLOW_ACTION_MODIFY_HEADER) {
501f14e3
MB		 2736 if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2737 return -EINVAL;
b1085be3 2738 action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2b688ea5
MG		 2739 action->modify_hdr =
2740 maction->flow_action_raw.modify_hdr;
b1085be3
MB		 2741 return 0;
2742 }
10a30896
MB		 2743 if (maction->flow_action_raw.sub_type ==
2744 MLX5_IB_FLOW_ACTION_DECAP) {
501f14e3
MB		 2745 if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP)
2746 return -EINVAL;
10a30896
MB		 2747 action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2748 return 0;
2749 }
e806f932
MB		 2750 if (maction->flow_action_raw.sub_type ==
2751 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) {
501f14e3
MB		 2752 if (action->action &
2753 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT)
2754 return -EINVAL;
e806f932
MB		 2755 action->action |=
2756 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
2b688ea5
MG		 2757 action->pkt_reformat =
2758 maction->flow_action_raw.pkt_reformat;
e806f932
MB		 2759 return 0;
2760 }
b1085be3 2761 /* fall through */
802c2125
AY		 2762 default:
2763 return -EOPNOTSUPP;
2764 }
2765}
2766
bb0ee7dc
JL		 2767static int parse_flow_attr(struct mlx5_core_dev *mdev,
2768 struct mlx5_flow_spec *spec,
2769 const union ib_flow_spec *ib_spec,
802c2125 2770 const struct ib_flow_attr *flow_attr,
71c6e863 2771 struct mlx5_flow_act *action, u32 prev_type)
038d2ef8 2772{
bb0ee7dc
JL		 2773 struct mlx5_flow_context *flow_context = &spec->flow_context;
2774 u32 *match_c = spec->match_criteria;
2775 u32 *match_v = spec->match_value;
466fa6d2
MG		 2776 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2777 misc_parameters);
2778 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2779 misc_parameters);
71c6e863
AL		 2780 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2781 misc_parameters_2);
2782 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2783 misc_parameters_2);
2d1e697e
MR		 2784 void *headers_c;
2785 void *headers_v;
19cc7524 2786 int match_ipv;
802c2125 2787 int ret;
2d1e697e
MR		 2788
2789 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2790 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2791 inner_headers);
2792 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2793 inner_headers);
19cc7524
AL		 2794 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2795 ft_field_support.inner_ip_version);
2d1e697e
MR		 2796 } else {
2797 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2798 outer_headers);
2799 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2800 outer_headers);
19cc7524
AL		 2801 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2802 ft_field_support.outer_ip_version);
2d1e697e 2803 }
466fa6d2 2804
2d1e697e 2805 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 2806 case IB_FLOW_SPEC_ETH:
c47ac6ae 2807 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 2808 return -EOPNOTSUPP;
038d2ef8 2809
2d1e697e 2810 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2811 dmac_47_16),
2812 ib_spec->eth.mask.dst_mac);
2d1e697e 2813 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2814 dmac_47_16),
2815 ib_spec->eth.val.dst_mac);
2816
2d1e697e 2817 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 2818 smac_47_16),
2819 ib_spec->eth.mask.src_mac);
2d1e697e 2820 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 2821 smac_47_16),
2822 ib_spec->eth.val.src_mac);
2823
038d2ef8 2824 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 2825 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 2826 cvlan_tag, 1);
2d1e697e 2827 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 2828 cvlan_tag, 1);
038d2ef8 2829
2d1e697e 2830 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2831 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 2832 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2833 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2834
2d1e697e 2835 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2836 first_cfi,
2837 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 2838 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2839 first_cfi,
2840 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2841
2d1e697e 2842 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2843 first_prio,
2844 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 2845 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2846 first_prio,
2847 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2848 }
2d1e697e 2849 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2850 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 2851 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2852 ethertype, ntohs(ib_spec->eth.val.ether_type));
2853 break;
2854 case IB_FLOW_SPEC_IPV4:
c47ac6ae 2855 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 2856 return -EOPNOTSUPP;
038d2ef8 2857
19cc7524
AL		 2858 if (match_ipv) {
2859 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2860 ip_version, 0xf);
2861 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2862 ip_version, MLX5_FS_IPV4_VERSION);
19cc7524
AL		 2863 } else {
2864 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2865 ethertype, 0xffff);
2866 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2867 ethertype, ETH_P_IP);
2868 }
038d2ef8 2869
2d1e697e 2870 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2871 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2872 &ib_spec->ipv4.mask.src_ip,
2873 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 2874 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2875 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2876 &ib_spec->ipv4.val.src_ip,
2877 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 2878 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2879 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2880 &ib_spec->ipv4.mask.dst_ip,
2881 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 2882 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2883 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2884 &ib_spec->ipv4.val.dst_ip,
2885 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 2886
2d1e697e 2887 set_tos(headers_c, headers_v,
ca0d4753
MG		 2888 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2889
6113cc44
MG		 2890 if (set_proto(headers_c, headers_v,
2891 ib_spec->ipv4.mask.proto,
2892 ib_spec->ipv4.val.proto))
2893 return -EINVAL;
038d2ef8 2894 break;
026bae0c 2895 case IB_FLOW_SPEC_IPV6:
c47ac6ae 2896 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 2897 return -EOPNOTSUPP;
026bae0c 2898
19cc7524
AL		 2899 if (match_ipv) {
2900 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2901 ip_version, 0xf);
2902 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2903 ip_version, MLX5_FS_IPV6_VERSION);
19cc7524
AL		 2904 } else {
2905 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2906 ethertype, 0xffff);
2907 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2908 ethertype, ETH_P_IPV6);
2909 }
026bae0c 2910
2d1e697e 2911 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2912 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2913 &ib_spec->ipv6.mask.src_ip,
2914 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2915 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2916 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2917 &ib_spec->ipv6.val.src_ip,
2918 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2919 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2920 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2921 &ib_spec->ipv6.mask.dst_ip,
2922 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2923 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2924 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2925 &ib_spec->ipv6.val.dst_ip,
2926 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2927
2d1e697e 2928 set_tos(headers_c, headers_v,
466fa6d2
MG		 2929 ib_spec->ipv6.mask.traffic_class,
2930 ib_spec->ipv6.val.traffic_class);
2931
6113cc44
MG		 2932 if (set_proto(headers_c, headers_v,
2933 ib_spec->ipv6.mask.next_hdr,
2934 ib_spec->ipv6.val.next_hdr))
2935 return -EINVAL;
466fa6d2 2936
2d1e697e
MR		 2937 set_flow_label(misc_params_c, misc_params_v,
2938 ntohl(ib_spec->ipv6.mask.flow_label),
2939 ntohl(ib_spec->ipv6.val.flow_label),
2940 ib_spec->type & IB_FLOW_SPEC_INNER);
802c2125
AY		 2941 break;
2942 case IB_FLOW_SPEC_ESP:
2943 if (ib_spec->esp.mask.seq)
2944 return -EOPNOTSUPP;
2d1e697e 2945
802c2125
AY		 2946 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2947 ntohl(ib_spec->esp.mask.spi));
2948 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2949 ntohl(ib_spec->esp.val.spi));
026bae0c 2950 break;
038d2ef8 2951 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2952 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2953 LAST_TCP_UDP_FIELD))
1ffd3a26 2954 return -EOPNOTSUPP;
038d2ef8 2955
6113cc44
MG		 2956 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_TCP))
2957 return -EINVAL;
038d2ef8 2958
2d1e697e 2959 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2960 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2961 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2962 ntohs(ib_spec->tcp_udp.val.src_port));
2963
2d1e697e 2964 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2965 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2966 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2967 ntohs(ib_spec->tcp_udp.val.dst_port));
2968 break;
2969 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2970 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2971 LAST_TCP_UDP_FIELD))
1ffd3a26 2972 return -EOPNOTSUPP;
038d2ef8 2973
6113cc44
MG		 2974 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_UDP))
2975 return -EINVAL;
038d2ef8 2976
2d1e697e 2977 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2978 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2979 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2980 ntohs(ib_spec->tcp_udp.val.src_port));
2981
2d1e697e 2982 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2983 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2984 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2985 ntohs(ib_spec->tcp_udp.val.dst_port));
2986 break;
da2f22ae
AL		 2987 case IB_FLOW_SPEC_GRE:
2988 if (ib_spec->gre.mask.c_ks_res0_ver)
2989 return -EOPNOTSUPP;
2990
6113cc44
MG		 2991 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_GRE))
2992 return -EINVAL;
2993
da2f22ae
AL		 2994 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2995 0xff);
2996 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2997 IPPROTO_GRE);
2998
2999 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
a93b632c 3000 ntohs(ib_spec->gre.mask.protocol));
da2f22ae
AL		 3001 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
3002 ntohs(ib_spec->gre.val.protocol));
3003
3004 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
5886a96a 3005 gre_key.nvgre.hi),
da2f22ae
AL		 3006 &ib_spec->gre.mask.key,
3007 sizeof(ib_spec->gre.mask.key));
3008 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
5886a96a 3009 gre_key.nvgre.hi),
da2f22ae
AL		 3010 &ib_spec->gre.val.key,
3011 sizeof(ib_spec->gre.val.key));
3012 break;
71c6e863
AL		 3013 case IB_FLOW_SPEC_MPLS:
3014 switch (prev_type) {
3015 case IB_FLOW_SPEC_UDP:
3016 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3017 ft_field_support.outer_first_mpls_over_udp),
3018 &ib_spec->mpls.mask.tag))
3019 return -EOPNOTSUPP;
3020
3021 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
3022 outer_first_mpls_over_udp),
3023 &ib_spec->mpls.val.tag,
3024 sizeof(ib_spec->mpls.val.tag));
3025 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
3026 outer_first_mpls_over_udp),
3027 &ib_spec->mpls.mask.tag,
3028 sizeof(ib_spec->mpls.mask.tag));
3029 break;
3030 case IB_FLOW_SPEC_GRE:
3031 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3032 ft_field_support.outer_first_mpls_over_gre),
3033 &ib_spec->mpls.mask.tag))
3034 return -EOPNOTSUPP;
3035
3036 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
3037 outer_first_mpls_over_gre),
3038 &ib_spec->mpls.val.tag,
3039 sizeof(ib_spec->mpls.val.tag));
3040 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
3041 outer_first_mpls_over_gre),
3042 &ib_spec->mpls.mask.tag,
3043 sizeof(ib_spec->mpls.mask.tag));
3044 break;
3045 default:
3046 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
3047 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3048 ft_field_support.inner_first_mpls),
3049 &ib_spec->mpls.mask.tag))
3050 return -EOPNOTSUPP;
3051
3052 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
3053 inner_first_mpls),
3054 &ib_spec->mpls.val.tag,
3055 sizeof(ib_spec->mpls.val.tag));
3056 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
3057 inner_first_mpls),
3058 &ib_spec->mpls.mask.tag,
3059 sizeof(ib_spec->mpls.mask.tag));
3060 } else {
3061 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3062 ft_field_support.outer_first_mpls),
3063 &ib_spec->mpls.mask.tag))
3064 return -EOPNOTSUPP;
3065
3066 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
3067 outer_first_mpls),
3068 &ib_spec->mpls.val.tag,
3069 sizeof(ib_spec->mpls.val.tag));
3070 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
3071 outer_first_mpls),
3072 &ib_spec->mpls.mask.tag,
3073 sizeof(ib_spec->mpls.mask.tag));
3074 }
3075 }
3076 break;
ffb30d8f
MR		 3077 case IB_FLOW_SPEC_VXLAN_TUNNEL:
3078 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
3079 LAST_TUNNEL_FIELD))
1ffd3a26 3080 return -EOPNOTSUPP;
ffb30d8f
MR		 3081
3082 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
3083 ntohl(ib_spec->tunnel.mask.tunnel_id));
3084 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
3085 ntohl(ib_spec->tunnel.val.tunnel_id));
3086 break;
2ac693f9
MR		 3087 case IB_FLOW_SPEC_ACTION_TAG:
3088 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
3089 LAST_FLOW_TAG_FIELD))
3090 return -EOPNOTSUPP;
3091 if (ib_spec->flow_tag.tag_id >= BIT(24))
3092 return -EINVAL;
3093
bb0ee7dc
JL		 3094 flow_context->flow_tag = ib_spec->flow_tag.tag_id;
3095 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
2ac693f9 3096 break;
a22ed86c
SS		 3097 case IB_FLOW_SPEC_ACTION_DROP:
3098 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
3099 LAST_DROP_FIELD))
3100 return -EOPNOTSUPP;
075572d4 3101 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
a22ed86c 3102 break;
802c2125 3103 case IB_FLOW_SPEC_ACTION_HANDLE:
2ea26203
MB		 3104 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act),
3105 flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action);
802c2125
AY		 3106 if (ret)
3107 return ret;
3108 break;
3b3233fb
RS		 3109 case IB_FLOW_SPEC_ACTION_COUNT:
3110 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
3111 LAST_COUNTERS_FIELD))
3112 return -EOPNOTSUPP;
3113
3114 /* for now support only one counters spec per flow */
3115 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
3116 return -EINVAL;
3117
3118 action->counters = ib_spec->flow_count.counters;
3119 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3120 break;
038d2ef8
MG		 3121 default:
3122 return -EINVAL;
3123 }
3124
3125 return 0;
3126}
3127
3128/* If a flow could catch both multicast and unicast packets,
3129 * it won't fall into the multicast flow steering table and this rule
3130 * could steal other multicast packets.
3131 */
a550ddfc 3132static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
038d2ef8 3133{
81e30880 3134 union ib_flow_spec *flow_spec;
038d2ef8
MG		 3135
3136 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 3137 ib_attr->num_of_specs < 1)
3138 return false;
3139
81e30880
YH		 3140 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
3141 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
3142 struct ib_flow_spec_ipv4 *ipv4_spec;
3143
3144 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
3145 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
3146 return true;
3147
038d2ef8 3148 return false;
81e30880
YH		 3149 }
3150
3151 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
3152 struct ib_flow_spec_eth *eth_spec;
3153
3154 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
3155 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
3156 is_multicast_ether_addr(eth_spec->val.dst_mac);
3157 }
038d2ef8 3158
81e30880 3159 return false;
038d2ef8
MG		 3160}
3161
802c2125
AY		 3162enum valid_spec {
3163 VALID_SPEC_INVALID,
3164 VALID_SPEC_VALID,
3165 VALID_SPEC_NA,
3166};
3167
3168static enum valid_spec
3169is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
3170 const struct mlx5_flow_spec *spec,
3171 const struct mlx5_flow_act *flow_act,
3172 bool egress)
3173{
3174 const u32 *match_c = spec->match_criteria;
3175 bool is_crypto =
3176 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
3177 MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
3178 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
3179 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
3180
3181 /*
3182 * Currently only crypto is supported in egress, when regular egress
3183 * rules would be supported, always return VALID_SPEC_NA.
3184 */
3185 if (!is_crypto)
78dd0c43 3186 return VALID_SPEC_NA;
802c2125
AY		 3187
3188 return is_crypto && is_ipsec &&
bb0ee7dc
JL		 3189 (!egress || (!is_drop &&
3190 !(spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG))) ?
802c2125
AY		 3191 VALID_SPEC_VALID : VALID_SPEC_INVALID;
3192}
3193
3194static bool is_valid_spec(struct mlx5_core_dev *mdev,
3195 const struct mlx5_flow_spec *spec,
3196 const struct mlx5_flow_act *flow_act,
3197 bool egress)
3198{
3199 /* We curretly only support ipsec egress flow */
3200 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
3201}
3202
19cc7524
AL		 3203static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
3204 const struct ib_flow_attr *flow_attr,
0f750966 3205 bool check_inner)
038d2ef8
MG		 3206{
3207 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 3208 int match_ipv = check_inner ?
3209 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3210 ft_field_support.inner_ip_version) :
3211 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3212 ft_field_support.outer_ip_version);
0f750966
AL		 3213 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
3214 bool ipv4_spec_valid, ipv6_spec_valid;
3215 unsigned int ip_spec_type = 0;
3216 bool has_ethertype = false;
038d2ef8 3217 unsigned int spec_index;
0f750966
AL		 3218 bool mask_valid = true;
3219 u16 eth_type = 0;
3220 bool type_valid;
038d2ef8
MG		 3221
3222 /* Validate that ethertype is correct */
3223 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 3224 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 3225 ib_spec->eth.mask.ether_type) {
0f750966
AL		 3226 mask_valid = (ib_spec->eth.mask.ether_type ==
3227 htons(0xffff));
3228 has_ethertype = true;
3229 eth_type = ntohs(ib_spec->eth.val.ether_type);
3230 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
3231 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
3232 ip_spec_type = ib_spec->type;
038d2ef8
MG		 3233 }
3234 ib_spec = (void *)ib_spec + ib_spec->size;
3235 }
0f750966
AL		 3236
3237 type_valid = (!has_ethertype) || (!ip_spec_type);
3238 if (!type_valid && mask_valid) {
3239 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
3240 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
3241 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
3242 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 3243
3244 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
3245 (((eth_type == ETH_P_MPLS_UC) ||
3246 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 3247 }
3248
3249 return type_valid;
3250}
3251
19cc7524
AL		 3252static bool is_valid_attr(struct mlx5_core_dev *mdev,
3253 const struct ib_flow_attr *flow_attr)
0f750966 3254{
19cc7524
AL		 3255 return is_valid_ethertype(mdev, flow_attr, false) &&
3256 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 3257}
3258
3259static void put_flow_table(struct mlx5_ib_dev *dev,
3260 struct mlx5_ib_flow_prio *prio, bool ft_added)
3261{
3262 prio->refcount -= !!ft_added;
3263 if (!prio->refcount) {
3264 mlx5_destroy_flow_table(prio->flow_table);
3265 prio->flow_table = NULL;
3266 }
3267}
3268
3b3233fb
RS		 3269static void counters_clear_description(struct ib_counters *counters)
3270{
3271 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3272
3273 mutex_lock(&mcounters->mcntrs_mutex);
3274 kfree(mcounters->counters_data);
3275 mcounters->counters_data = NULL;
3276 mcounters->cntrs_max_index = 0;
3277 mutex_unlock(&mcounters->mcntrs_mutex);
3278}
3279
038d2ef8
MG		 3280static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
3281{
038d2ef8
MG		 3282 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
3283 struct mlx5_ib_flow_handler,
3284 ibflow);
3285 struct mlx5_ib_flow_handler *iter, *tmp;
d4be3f44 3286 struct mlx5_ib_dev *dev = handler->dev;
038d2ef8 3287
9a4ca38d 3288 mutex_lock(&dev->flow_db->lock);
038d2ef8
MG		 3289
3290 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 3291 mlx5_del_flow_rules(iter->rule);
cc0e5d42 3292 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 3293 list_del(&iter->list);
3294 kfree(iter);
3295 }
3296
74491de9 3297 mlx5_del_flow_rules(handler->rule);
5497adc6 3298 put_flow_table(dev, handler->prio, true);
3b3233fb
RS		 3299 if (handler->ibcounters &&
3300 atomic_read(&handler->ibcounters->usecnt) == 1)
3301 counters_clear_description(handler->ibcounters);
038d2ef8 3302
3b3233fb 3303 mutex_unlock(&dev->flow_db->lock);
d4be3f44
YH		 3304 if (handler->flow_matcher)
3305 atomic_dec(&handler->flow_matcher->usecnt);
038d2ef8
MG		 3306 kfree(handler);
3307
3308 return 0;
3309}
3310
35d19011
MG		 3311static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
3312{
3313 priority *= 2;
3314 if (!dont_trap)
3315 priority++;
3316 return priority;
3317}
3318
cc0e5d42
MG		 3319enum flow_table_type {
3320 MLX5_IB_FT_RX,
3321 MLX5_IB_FT_TX
3322};
3323
00b7c2ab
MG		 3324#define MLX5_FS_MAX_TYPES 6
3325#define MLX5_FS_MAX_ENTRIES BIT(16)
d4be3f44
YH		 3326
3327static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns,
3328 struct mlx5_ib_flow_prio *prio,
3329 int priority,
4adda112
MB		 3330 int num_entries, int num_groups,
3331 u32 flags)
d4be3f44 3332{
61dc7b01 3333 struct mlx5_flow_table_attr ft_attr = {};
d4be3f44
YH		 3334 struct mlx5_flow_table *ft;
3335
61dc7b01
PB		 3336 ft_attr.prio = priority;
3337 ft_attr.max_fte = num_entries;
3338 ft_attr.flags = flags;
3339 ft_attr.autogroup.max_num_groups = num_groups;
3340 ft = mlx5_create_auto_grouped_flow_table(ns, &ft_attr);
d4be3f44
YH		 3341 if (IS_ERR(ft))
3342 return ERR_CAST(ft);
3343
3344 prio->flow_table = ft;
3345 prio->refcount = 0;
3346 return prio;
3347}
3348
038d2ef8 3349static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 3350 struct ib_flow_attr *flow_attr,
3351 enum flow_table_type ft_type)
038d2ef8 3352{
35d19011 3353 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 3354 struct mlx5_flow_namespace *ns = NULL;
3355 struct mlx5_ib_flow_prio *prio;
3356 struct mlx5_flow_table *ft;
dac388ef 3357 int max_table_size;
038d2ef8
MG		 3358 int num_entries;
3359 int num_groups;
cecae747 3360 bool esw_encap;
4adda112 3361 u32 flags = 0;
038d2ef8 3362 int priority;
038d2ef8 3363
dac388ef
MG		 3364 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3365 log_max_ft_size));
cecae747
MG		 3366 esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
3367 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
038d2ef8 3368 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
78dd0c43
MB		 3369 enum mlx5_flow_namespace_type fn_type;
3370
3371 if (flow_is_multicast_only(flow_attr) &&
3372 !dont_trap)
038d2ef8
MG		 3373 priority = MLX5_IB_FLOW_MCAST_PRIO;
3374 else
35d19011
MG		 3375 priority = ib_prio_to_core_prio(flow_attr->priority,
3376 dont_trap);
78dd0c43
MB		 3377 if (ft_type == MLX5_IB_FT_RX) {
3378 fn_type = MLX5_FLOW_NAMESPACE_BYPASS;
3379 prio = &dev->flow_db->prios[priority];
cecae747 3380 if (!dev->is_rep && !esw_encap &&
4adda112
MB		 3381 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3382 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
cecae747 3383 if (!dev->is_rep && !esw_encap &&
5c2db53f
MB		 3384 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3385 reformat_l3_tunnel_to_l2))
3386 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
78dd0c43
MB		 3387 } else {
3388 max_table_size =
3389 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3390 log_max_ft_size));
3391 fn_type = MLX5_FLOW_NAMESPACE_EGRESS;
3392 prio = &dev->flow_db->egress_prios[priority];
cecae747 3393 if (!dev->is_rep && !esw_encap &&
4adda112
MB		 3394 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3395 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
78dd0c43
MB		 3396 }
3397 ns = mlx5_get_flow_namespace(dev->mdev, fn_type);
038d2ef8
MG		 3398 num_entries = MLX5_FS_MAX_ENTRIES;
3399 num_groups = MLX5_FS_MAX_TYPES;
038d2ef8
MG		 3400 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3401 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3402 ns = mlx5_get_flow_namespace(dev->mdev,
3403 MLX5_FLOW_NAMESPACE_LEFTOVERS);
3404 build_leftovers_ft_param(&priority,
3405 &num_entries,
3406 &num_groups);
9a4ca38d 3407 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 3408 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3409 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3410 allow_sniffer_and_nic_rx_shared_tir))
3411 return ERR_PTR(-ENOTSUPP);
3412
3413 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3414 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3415 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3416
9a4ca38d 3417 prio = &dev->flow_db->sniffer[ft_type];
cc0e5d42
MG		 3418 priority = 0;
3419 num_entries = 1;
3420 num_groups = 1;
038d2ef8
MG		 3421 }
3422
3423 if (!ns)
3424 return ERR_PTR(-ENOTSUPP);
3425
3b70508a 3426 max_table_size = min_t(int, num_entries, max_table_size);
dac388ef 3427
038d2ef8 3428 ft = prio->flow_table;
d4be3f44 3429 if (!ft)
3b70508a 3430 return _get_prio(ns, prio, priority, max_table_size, num_groups,
4adda112 3431 flags);
038d2ef8 3432
d4be3f44 3433 return prio;
038d2ef8
MG		 3434}
3435
a550ddfc
YH		 3436static void set_underlay_qp(struct mlx5_ib_dev *dev,
3437 struct mlx5_flow_spec *spec,
3438 u32 underlay_qpn)
3439{
3440 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3441 spec->match_criteria,
3442 misc_parameters);
3443 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3444 misc_parameters);
3445
3446 if (underlay_qpn &&
3447 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3448 ft_field_support.bth_dst_qp)) {
3449 MLX5_SET(fte_match_set_misc,
3450 misc_params_v, bth_dst_qp, underlay_qpn);
3451 MLX5_SET(fte_match_set_misc,
3452 misc_params_c, bth_dst_qp, 0xffffff);
3453 }
3454}
3455
5e95af5f
RS		 3456static int read_flow_counters(struct ib_device *ibdev,
3457 struct mlx5_read_counters_attr *read_attr)
3458{
3459 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3460 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3461
3462 return mlx5_fc_query(dev->mdev, fc,
3463 &read_attr->out[IB_COUNTER_PACKETS],
3464 &read_attr->out[IB_COUNTER_BYTES]);
3465}
3466
3467/* flow counters currently expose two counters packets and bytes */
3468#define FLOW_COUNTERS_NUM 2
3b3233fb
RS		 3469static int counters_set_description(struct ib_counters *counters,
3470 enum mlx5_ib_counters_type counters_type,
3471 struct mlx5_ib_flow_counters_desc *desc_data,
3472 u32 ncounters)
3473{
3474 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3475 u32 cntrs_max_index = 0;
3476 int i;
3477
3478 if (counters_type != MLX5_IB_COUNTERS_FLOW)
3479 return -EINVAL;
3480
3481 /* init the fields for the object */
3482 mcounters->type = counters_type;
5e95af5f
RS		 3483 mcounters->read_counters = read_flow_counters;
3484 mcounters->counters_num = FLOW_COUNTERS_NUM;
3b3233fb
RS		 3485 mcounters->ncounters = ncounters;
3486 /* each counter entry have both description and index pair */
3487 for (i = 0; i < ncounters; i++) {
3488 if (desc_data[i].description > IB_COUNTER_BYTES)
3489 return -EINVAL;
3490
3491 if (cntrs_max_index <= desc_data[i].index)
3492 cntrs_max_index = desc_data[i].index + 1;
3493 }
3494
3495 mutex_lock(&mcounters->mcntrs_mutex);
3496 mcounters->counters_data = desc_data;
3497 mcounters->cntrs_max_index = cntrs_max_index;
3498 mutex_unlock(&mcounters->mcntrs_mutex);
3499
3500 return 0;
3501}
3502
3503#define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3504static int flow_counters_set_data(struct ib_counters *ibcounters,
3505 struct mlx5_ib_create_flow *ucmd)
3506{
3507 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3508 struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3509 struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3510 bool hw_hndl = false;
3511 int ret = 0;
3512
3513 if (ucmd && ucmd->ncounters_data != 0) {
3514 cntrs_data = ucmd->data;
3515 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3516 return -EINVAL;
3517
3518 desc_data = kcalloc(cntrs_data->ncounters,
3519 sizeof(*desc_data),
3520 GFP_KERNEL);
3521 if (!desc_data)
3522 return -ENOMEM;
3523
3524 if (copy_from_user(desc_data,
3525 u64_to_user_ptr(cntrs_data->counters_data),
3526 sizeof(*desc_data) * cntrs_data->ncounters)) {
3527 ret = -EFAULT;
3528 goto free;
3529 }
3530 }
3531
3532 if (!mcounters->hw_cntrs_hndl) {
3533 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3534 to_mdev(ibcounters->device)->mdev, false);
e31abf76 3535 if (IS_ERR(mcounters->hw_cntrs_hndl)) {
3536 ret = PTR_ERR(mcounters->hw_cntrs_hndl);
3b3233fb
RS		 3537 goto free;
3538 }
3539 hw_hndl = true;
3540 }
3541
3542 if (desc_data) {
3543 /* counters already bound to at least one flow */
3544 if (mcounters->cntrs_max_index) {
3545 ret = -EINVAL;
3546 goto free_hndl;
3547 }
3548
3549 ret = counters_set_description(ibcounters,
3550 MLX5_IB_COUNTERS_FLOW,
3551 desc_data,
3552 cntrs_data->ncounters);
3553 if (ret)
3554 goto free_hndl;
3555
3556 } else if (!mcounters->cntrs_max_index) {
3557 /* counters not bound yet, must have udata passed */
3558 ret = -EINVAL;
3559 goto free_hndl;
3560 }
3561
3562 return 0;
3563
3564free_hndl:
3565 if (hw_hndl) {
3566 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3567 mcounters->hw_cntrs_hndl);
3568 mcounters->hw_cntrs_hndl = NULL;
3569 }
3570free:
3571 kfree(desc_data);
3572 return ret;
3573}
3574
669ff1e3
JL		 3575static void mlx5_ib_set_rule_source_port(struct mlx5_ib_dev *dev,
3576 struct mlx5_flow_spec *spec,
3577 struct mlx5_eswitch_rep *rep)
3578{
3579 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
3580 void *misc;
3581
3582 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
3583 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3584 misc_parameters_2);
3585
3586 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
3587 mlx5_eswitch_get_vport_metadata_for_match(esw,
3588 rep->vport));
3589 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3590 misc_parameters_2);
3591
0f0d3827
PB		 3592 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
3593 mlx5_eswitch_get_vport_metadata_mask());
669ff1e3
JL		 3594 } else {
3595 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3596 misc_parameters);
3597
3598 MLX5_SET(fte_match_set_misc, misc, source_port, rep->vport);
3599
3600 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3601 misc_parameters);
3602
3603 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3604 }
3605}
3606
a550ddfc
YH		 3607static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3608 struct mlx5_ib_flow_prio *ft_prio,
3609 const struct ib_flow_attr *flow_attr,
3610 struct mlx5_flow_destination *dst,
3b3233fb
RS		 3611 u32 underlay_qpn,
3612 struct mlx5_ib_create_flow *ucmd)
038d2ef8
MG		 3613{
3614 struct mlx5_flow_table *ft = ft_prio->flow_table;
3615 struct mlx5_ib_flow_handler *handler;
bb0ee7dc 3616 struct mlx5_flow_act flow_act = {};
c5bb1730 3617 struct mlx5_flow_spec *spec;
3b3233fb
RS		 3618 struct mlx5_flow_destination dest_arr[2] = {};
3619 struct mlx5_flow_destination *rule_dst = dest_arr;
dd063d0e 3620 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 3621 unsigned int spec_index;
71c6e863 3622 u32 prev_type = 0;
038d2ef8 3623 int err = 0;
3b3233fb 3624 int dest_num = 0;
802c2125 3625 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
038d2ef8 3626
19cc7524 3627 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 3628 return ERR_PTR(-EINVAL);
3629
6a4d00be 3630 if (dev->is_rep && is_egress)
78dd0c43
MB		 3631 return ERR_PTR(-EINVAL);
3632
1b9a07ee 3633 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 3634 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 3635 if (!handler || !spec) {
038d2ef8
MG		 3636 err = -ENOMEM;
3637 goto free;
3638 }
3639
3640 INIT_LIST_HEAD(&handler->list);
3641
3642 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
bb0ee7dc 3643 err = parse_flow_attr(dev->mdev, spec,
71c6e863
AL		 3644 ib_flow, flow_attr, &flow_act,
3645 prev_type);
038d2ef8
MG		 3646 if (err < 0)
3647 goto free;
3648
71c6e863 3649 prev_type = ((union ib_flow_spec *)ib_flow)->type;
038d2ef8
MG		 3650 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3651 }
3652
ed9085fe
MG		 3653 if (dst && !(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP)) {
3654 memcpy(&dest_arr[0], dst, sizeof(*dst));
3655 dest_num++;
3656 }
3657
a550ddfc
YH		 3658 if (!flow_is_multicast_only(flow_attr))
3659 set_underlay_qp(dev, spec, underlay_qpn);
3660
6a4d00be 3661 if (dev->is_rep) {
669ff1e3 3662 struct mlx5_eswitch_rep *rep;
018a94ee 3663
669ff1e3
JL		 3664 rep = dev->port[flow_attr->port - 1].rep;
3665 if (!rep) {
6a4d00be
MB		 3666 err = -EINVAL;
3667 goto free;
3668 }
669ff1e3
JL		 3669
3670 mlx5_ib_set_rule_source_port(dev, spec, rep);
018a94ee
MB		 3671 }
3672
466fa6d2 3673 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
802c2125
AY		 3674
3675 if (is_egress &&
3676 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3677 err = -EINVAL;
3678 goto free;
3679 }
3680
3b3233fb 3681 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
171c7625
MB		 3682 struct mlx5_ib_mcounters *mcounters;
3683
3b3233fb
RS		 3684 err = flow_counters_set_data(flow_act.counters, ucmd);
3685 if (err)
3686 goto free;
3687
171c7625 3688 mcounters = to_mcounters(flow_act.counters);
3b3233fb
RS		 3689 handler->ibcounters = flow_act.counters;
3690 dest_arr[dest_num].type =
3691 MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625
MB		 3692 dest_arr[dest_num].counter_id =
3693 mlx5_fc_id(mcounters->hw_cntrs_hndl);
3b3233fb
RS		 3694 dest_num++;
3695 }
3696
075572d4 3697 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
ed9085fe 3698 if (!dest_num)
3b3233fb 3699 rule_dst = NULL;
a22ed86c 3700 } else {
802c2125
AY		 3701 if (is_egress)
3702 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3703 else
3704 flow_act.action |=
3b3233fb 3705 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
802c2125 3706 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
a22ed86c 3707 }
2ac693f9 3708
bb0ee7dc 3709 if ((spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG) &&
2ac693f9
MR		 3710 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3711 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3712 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
bb0ee7dc 3713 spec->flow_context.flow_tag, flow_attr->type);
2ac693f9
MR		 3714 err = -EINVAL;
3715 goto free;
3716 }
74491de9 3717 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 3718 &flow_act,
a22ed86c 3719 rule_dst, dest_num);
038d2ef8
MG		 3720
3721 if (IS_ERR(handler->rule)) {
3722 err = PTR_ERR(handler->rule);
3723 goto free;
3724 }
3725
d9d4980a 3726 ft_prio->refcount++;
5497adc6 3727 handler->prio = ft_prio;
d4be3f44 3728 handler->dev = dev;
038d2ef8
MG		 3729
3730 ft_prio->flow_table = ft;
3731free:
3b3233fb
RS		 3732 if (err && handler) {
3733 if (handler->ibcounters &&
3734 atomic_read(&handler->ibcounters->usecnt) == 1)
3735 counters_clear_description(handler->ibcounters);
038d2ef8 3736 kfree(handler);
3b3233fb 3737 }
c5bb1730 3738 kvfree(spec);
038d2ef8
MG		 3739 return err ? ERR_PTR(err) : handler;
3740}
3741
a550ddfc
YH		 3742static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3743 struct mlx5_ib_flow_prio *ft_prio,
3744 const struct ib_flow_attr *flow_attr,
3745 struct mlx5_flow_destination *dst)
3746{
3b3233fb 3747 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
a550ddfc
YH		 3748}
3749
35d19011
MG		 3750static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3751 struct mlx5_ib_flow_prio *ft_prio,
3752 struct ib_flow_attr *flow_attr,
3753 struct mlx5_flow_destination *dst)
3754{
3755 struct mlx5_ib_flow_handler *handler_dst = NULL;
3756 struct mlx5_ib_flow_handler *handler = NULL;
3757
3758 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3759 if (!IS_ERR(handler)) {
3760 handler_dst = create_flow_rule(dev, ft_prio,
3761 flow_attr, dst);
3762 if (IS_ERR(handler_dst)) {
74491de9 3763 mlx5_del_flow_rules(handler->rule);
d9d4980a 3764 ft_prio->refcount--;
35d19011
MG		 3765 kfree(handler);
3766 handler = handler_dst;
3767 } else {
3768 list_add(&handler_dst->list, &handler->list);
3769 }
3770 }
3771
3772 return handler;
3773}
038d2ef8
MG		 3774enum {
3775 LEFTOVERS_MC,
3776 LEFTOVERS_UC,
3777};
3778
3779static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3780 struct mlx5_ib_flow_prio *ft_prio,
3781 struct ib_flow_attr *flow_attr,
3782 struct mlx5_flow_destination *dst)
3783{
3784 struct mlx5_ib_flow_handler *handler_ucast = NULL;
3785 struct mlx5_ib_flow_handler *handler = NULL;
3786
3787 static struct {
3788 struct ib_flow_attr flow_attr;
3789 struct ib_flow_spec_eth eth_flow;
3790 } leftovers_specs[] = {
3791 [LEFTOVERS_MC] = {
3792 .flow_attr = {
3793 .num_of_specs = 1,
3794 .size = sizeof(leftovers_specs[0])
3795 },
3796 .eth_flow = {
3797 .type = IB_FLOW_SPEC_ETH,
3798 .size = sizeof(struct ib_flow_spec_eth),
3799 .mask = {.dst_mac = {0x1} },
3800 .val = {.dst_mac = {0x1} }
3801 }
3802 },
3803 [LEFTOVERS_UC] = {
3804 .flow_attr = {
3805 .num_of_specs = 1,
3806 .size = sizeof(leftovers_specs[0])
3807 },
3808 .eth_flow = {
3809 .type = IB_FLOW_SPEC_ETH,
3810 .size = sizeof(struct ib_flow_spec_eth),
3811 .mask = {.dst_mac = {0x1} },
3812 .val = {.dst_mac = {} }
3813 }
3814 }
3815 };
3816
3817 handler = create_flow_rule(dev, ft_prio,
3818 &leftovers_specs[LEFTOVERS_MC].flow_attr,
3819 dst);
3820 if (!IS_ERR(handler) &&
3821 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3822 handler_ucast = create_flow_rule(dev, ft_prio,
3823 &leftovers_specs[LEFTOVERS_UC].flow_attr,
3824 dst);
3825 if (IS_ERR(handler_ucast)) {
74491de9 3826 mlx5_del_flow_rules(handler->rule);
d9d4980a 3827 ft_prio->refcount--;
038d2ef8
MG		 3828 kfree(handler);
3829 handler = handler_ucast;
3830 } else {
3831 list_add(&handler_ucast->list, &handler->list);
3832 }
3833 }
3834
3835 return handler;
3836}
3837
cc0e5d42
MG		 3838static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3839 struct mlx5_ib_flow_prio *ft_rx,
3840 struct mlx5_ib_flow_prio *ft_tx,
3841 struct mlx5_flow_destination *dst)
3842{
3843 struct mlx5_ib_flow_handler *handler_rx;
3844 struct mlx5_ib_flow_handler *handler_tx;
3845 int err;
3846 static const struct ib_flow_attr flow_attr = {
3847 .num_of_specs = 0,
3848 .size = sizeof(flow_attr)
3849 };
3850
3851 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3852 if (IS_ERR(handler_rx)) {
3853 err = PTR_ERR(handler_rx);
3854 goto err;
3855 }
3856
3857 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3858 if (IS_ERR(handler_tx)) {
3859 err = PTR_ERR(handler_tx);
3860 goto err_tx;
3861 }
3862
3863 list_add(&handler_tx->list, &handler_rx->list);
3864
3865 return handler_rx;
3866
3867err_tx:
74491de9 3868 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 3869 ft_rx->refcount--;
3870 kfree(handler_rx);
3871err:
3872 return ERR_PTR(err);
3873}
3874
038d2ef8
MG		 3875static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3876 struct ib_flow_attr *flow_attr,
59082a32
MB		 3877 int domain,
3878 struct ib_udata *udata)
038d2ef8
MG		 3879{
3880 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 3881 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 3882 struct mlx5_ib_flow_handler *handler = NULL;
3883 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 3884 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8 3885 struct mlx5_ib_flow_prio *ft_prio;
802c2125 3886 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3b3233fb
RS		 3887 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3888 size_t min_ucmd_sz, required_ucmd_sz;
038d2ef8 3889 int err;
a550ddfc 3890 int underlay_qpn;
038d2ef8 3891
3b3233fb
RS		 3892 if (udata && udata->inlen) {
3893 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3894 sizeof(ucmd_hdr.reserved);
3895 if (udata->inlen < min_ucmd_sz)
3896 return ERR_PTR(-EOPNOTSUPP);
3897
3898 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3899 if (err)
3900 return ERR_PTR(err);
3901
3902 /* currently supports only one counters data */
3903 if (ucmd_hdr.ncounters_data > 1)
3904 return ERR_PTR(-EINVAL);
3905
3906 required_ucmd_sz = min_ucmd_sz +
3907 sizeof(struct mlx5_ib_flow_counters_data) *
3908 ucmd_hdr.ncounters_data;
3909 if (udata->inlen > required_ucmd_sz &&
3910 !ib_is_udata_cleared(udata, required_ucmd_sz,
3911 udata->inlen - required_ucmd_sz))
3912 return ERR_PTR(-EOPNOTSUPP);
3913
3914 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3915 if (!ucmd)
3916 return ERR_PTR(-ENOMEM);
3917
3918 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
299eafee
GS		 3919 if (err)
3920 goto free_ucmd;
3b3233fb 3921 }
59082a32 3922
299eafee
GS		 3923 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) {
3924 err = -ENOMEM;
3925 goto free_ucmd;
3926 }
038d2ef8
MG		 3927
3928 if (domain != IB_FLOW_DOMAIN_USER ||
508562d6 3929 flow_attr->port > dev->num_ports ||
802c2125 3930 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
299eafee
GS		 3931 IB_FLOW_ATTR_FLAGS_EGRESS))) {
3932 err = -EINVAL;
3933 goto free_ucmd;
3934 }
802c2125
AY		 3935
3936 if (is_egress &&
3937 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
299eafee
GS		 3938 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3939 err = -EINVAL;
3940 goto free_ucmd;
3941 }
038d2ef8
MG		 3942
3943 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
299eafee
GS		 3944 if (!dst) {
3945 err = -ENOMEM;
3946 goto free_ucmd;
3947 }
038d2ef8 3948
9a4ca38d 3949 mutex_lock(&dev->flow_db->lock);
038d2ef8 3950
802c2125
AY		 3951 ft_prio = get_flow_table(dev, flow_attr,
3952 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
038d2ef8
MG		 3953 if (IS_ERR(ft_prio)) {
3954 err = PTR_ERR(ft_prio);
3955 goto unlock;
3956 }
cc0e5d42
MG		 3957 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3958 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3959 if (IS_ERR(ft_prio_tx)) {
3960 err = PTR_ERR(ft_prio_tx);
3961 ft_prio_tx = NULL;
3962 goto destroy_ft;
3963 }
3964 }
038d2ef8 3965
802c2125
AY		 3966 if (is_egress) {
3967 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3968 } else {
3969 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2be08c30 3970 if (mqp->is_rss)
802c2125
AY		 3971 dst->tir_num = mqp->rss_qp.tirn;
3972 else
3973 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3974 }
038d2ef8
MG		 3975
3976 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 3977 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3978 handler = create_dont_trap_rule(dev, ft_prio,
3979 flow_attr, dst);
3980 } else {
2be08c30 3981 underlay_qpn = (mqp->flags & IB_QP_CREATE_SOURCE_QPN) ?
a550ddfc
YH		 3982 mqp->underlay_qpn : 0;
3983 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3b3233fb 3984 dst, underlay_qpn, ucmd);
35d19011 3985 }
038d2ef8
MG		 3986 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3987 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3988 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3989 dst);
cc0e5d42
MG		 3990 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3991 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 3992 } else {
3993 err = -EINVAL;
3994 goto destroy_ft;
3995 }
3996
3997 if (IS_ERR(handler)) {
3998 err = PTR_ERR(handler);
3999 handler = NULL;
4000 goto destroy_ft;
4001 }
4002
9a4ca38d 4003 mutex_unlock(&dev->flow_db->lock);
038d2ef8 4004 kfree(dst);
3b3233fb 4005 kfree(ucmd);
038d2ef8
MG		 4006
4007 return &handler->ibflow;
4008
4009destroy_ft:
4010 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 4011 if (ft_prio_tx)
4012 put_flow_table(dev, ft_prio_tx, false);
038d2ef8 4013unlock:
9a4ca38d 4014 mutex_unlock(&dev->flow_db->lock);
038d2ef8 4015 kfree(dst);
299eafee 4016free_ucmd:
3b3233fb 4017 kfree(ucmd);
038d2ef8
MG		 4018 return ERR_PTR(err);
4019}
4020
b47fd4ff
MB		 4021static struct mlx5_ib_flow_prio *
4022_get_flow_table(struct mlx5_ib_dev *dev,
4023 struct mlx5_ib_flow_matcher *fs_matcher,
4024 bool mcast)
d4be3f44 4025{
d4be3f44 4026 struct mlx5_flow_namespace *ns = NULL;
13a43765
MB		 4027 struct mlx5_ib_flow_prio *prio = NULL;
4028 int max_table_size = 0;
cecae747 4029 bool esw_encap;
b47fd4ff
MB		 4030 u32 flags = 0;
4031 int priority;
4032
13a43765
MB		 4033 if (mcast)
4034 priority = MLX5_IB_FLOW_MCAST_PRIO;
4035 else
4036 priority = ib_prio_to_core_prio(fs_matcher->priority, false);
4037
cecae747
MG		 4038 esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
4039 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
b47fd4ff
MB		 4040 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) {
4041 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
4042 log_max_ft_size));
cecae747 4043 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap) && !esw_encap)
b47fd4ff
MB		 4044 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
4045 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
cecae747
MG		 4046 reformat_l3_tunnel_to_l2) &&
4047 !esw_encap)
b47fd4ff 4048 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
13a43765
MB		 4049 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS) {
4050 max_table_size = BIT(
4051 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, log_max_ft_size));
cecae747 4052 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat) && !esw_encap)
b47fd4ff 4053 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
13a43765
MB		 4054 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB) {
4055 max_table_size = BIT(
4056 MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, log_max_ft_size));
09d985be
MG		 4057 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, decap) && esw_encap)
4058 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
4059 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, reformat_l3_tunnel_to_l2) &&
4060 esw_encap)
4061 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
13a43765 4062 priority = FDB_BYPASS_PATH;
d8abe884
MZ		 4063 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_RDMA_RX) {
4064 max_table_size =
4065 BIT(MLX5_CAP_FLOWTABLE_RDMA_RX(dev->mdev,
4066 log_max_ft_size));
4067 priority = fs_matcher->priority;
af9c3841
MG		 4068 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_RDMA_TX) {
4069 max_table_size =
4070 BIT(MLX5_CAP_FLOWTABLE_RDMA_TX(dev->mdev,
4071 log_max_ft_size));
4072 priority = fs_matcher->priority;
b47fd4ff 4073 }
d4be3f44 4074
3b70508a 4075 max_table_size = min_t(int, max_table_size, MLX5_FS_MAX_ENTRIES);
d4be3f44 4076
b47fd4ff 4077 ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type);
d4be3f44
YH		 4078 if (!ns)
4079 return ERR_PTR(-ENOTSUPP);
4080
b47fd4ff
MB		 4081 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS)
4082 prio = &dev->flow_db->prios[priority];
13a43765 4083 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS)
b47fd4ff 4084 prio = &dev->flow_db->egress_prios[priority];
13a43765
MB		 4085 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB)
4086 prio = &dev->flow_db->fdb;
d8abe884
MZ		 4087 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_RDMA_RX)
4088 prio = &dev->flow_db->rdma_rx[priority];
af9c3841
MG		 4089 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_RDMA_TX)
4090 prio = &dev->flow_db->rdma_tx[priority];
13a43765
MB		 4091
4092 if (!prio)
4093 return ERR_PTR(-EINVAL);
d4be3f44
YH		 4094
4095 if (prio->flow_table)
4096 return prio;
4097
3b70508a 4098 return _get_prio(ns, prio, priority, max_table_size,
b47fd4ff 4099 MLX5_FS_MAX_TYPES, flags);
d4be3f44
YH		 4100}
4101
4102static struct mlx5_ib_flow_handler *
4103_create_raw_flow_rule(struct mlx5_ib_dev *dev,
4104 struct mlx5_ib_flow_prio *ft_prio,
4105 struct mlx5_flow_destination *dst,
4106 struct mlx5_ib_flow_matcher *fs_matcher,
bb0ee7dc 4107 struct mlx5_flow_context *flow_context,
b823dd6d 4108 struct mlx5_flow_act *flow_act,
bfc5d839
MB		 4109 void *cmd_in, int inlen,
4110 int dst_num)
d4be3f44
YH		 4111{
4112 struct mlx5_ib_flow_handler *handler;
d4be3f44
YH		 4113 struct mlx5_flow_spec *spec;
4114 struct mlx5_flow_table *ft = ft_prio->flow_table;
4115 int err = 0;
4116
4117 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
4118 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
4119 if (!handler || !spec) {
4120 err = -ENOMEM;
4121 goto free;
4122 }
4123
4124 INIT_LIST_HEAD(&handler->list);
4125
4126 memcpy(spec->match_value, cmd_in, inlen);
4127 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params,
4128 fs_matcher->mask_len);
4129 spec->match_criteria_enable = fs_matcher->match_criteria_enable;
bb0ee7dc 4130 spec->flow_context = *flow_context;
d4be3f44 4131
d4be3f44 4132 handler->rule = mlx5_add_flow_rules(ft, spec,
bfc5d839 4133 flow_act, dst, dst_num);
d4be3f44
YH		 4134
4135 if (IS_ERR(handler->rule)) {
4136 err = PTR_ERR(handler->rule);
4137 goto free;
4138 }
4139
4140 ft_prio->refcount++;
4141 handler->prio = ft_prio;
4142 handler->dev = dev;
4143 ft_prio->flow_table = ft;
4144
4145free:
4146 if (err)
4147 kfree(handler);
4148 kvfree(spec);
4149 return err ? ERR_PTR(err) : handler;
4150}
4151
4152static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher,
4153 void *match_v)
4154{
4155 void *match_c;
4156 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4;
4157 void *dmac, *dmac_mask;
4158 void *ipv4, *ipv4_mask;
4159
4160 if (!(fs_matcher->match_criteria_enable &
4161 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT)))
4162 return false;
4163
4164 match_c = fs_matcher->matcher_mask.match_params;
4165 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v,
4166 outer_headers);
4167 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c,
4168 outer_headers);
4169
4170 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4171 dmac_47_16);
4172 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4173 dmac_47_16);
4174
4175 if (is_multicast_ether_addr(dmac) &&
4176 is_multicast_ether_addr(dmac_mask))
4177 return true;
4178
4179 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4180 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4181
4182 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4183 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4184
4185 if (ipv4_is_multicast(*(__be32 *)(ipv4)) &&
4186 ipv4_is_multicast(*(__be32 *)(ipv4_mask)))
4187 return true;
4188
4189 return false;
4190}
4191
32269441
YH		 4192struct mlx5_ib_flow_handler *
4193mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
4194 struct mlx5_ib_flow_matcher *fs_matcher,
bb0ee7dc 4195 struct mlx5_flow_context *flow_context,
b823dd6d 4196 struct mlx5_flow_act *flow_act,
bfc5d839 4197 u32 counter_id,
32269441
YH		 4198 void *cmd_in, int inlen, int dest_id,
4199 int dest_type)
4200{
d4be3f44
YH		 4201 struct mlx5_flow_destination *dst;
4202 struct mlx5_ib_flow_prio *ft_prio;
d4be3f44 4203 struct mlx5_ib_flow_handler *handler;
bfc5d839 4204 int dst_num = 0;
d4be3f44
YH		 4205 bool mcast;
4206 int err;
4207
4208 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL)
4209 return ERR_PTR(-EOPNOTSUPP);
4210
4211 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO)
4212 return ERR_PTR(-ENOMEM);
4213
8e8aa145 4214 dst = kcalloc(2, sizeof(*dst), GFP_KERNEL);
d4be3f44
YH		 4215 if (!dst)
4216 return ERR_PTR(-ENOMEM);
4217
4218 mcast = raw_fs_is_multicast(fs_matcher, cmd_in);
4219 mutex_lock(&dev->flow_db->lock);
4220
b47fd4ff 4221 ft_prio = _get_flow_table(dev, fs_matcher, mcast);
d4be3f44
YH		 4222 if (IS_ERR(ft_prio)) {
4223 err = PTR_ERR(ft_prio);
4224 goto unlock;
4225 }
4226
6346f0bf 4227 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
bfc5d839
MB		 4228 dst[dst_num].type = dest_type;
4229 dst[dst_num].tir_num = dest_id;
b823dd6d 4230 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
a7ee18bd 4231 } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) {
bfc5d839
MB		 4232 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
4233 dst[dst_num].ft_num = dest_id;
b823dd6d 4234 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
a7ee18bd 4235 } else {
bfc5d839 4236 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_PORT;
a7ee18bd 4237 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
6346f0bf
YH		 4238 }
4239
bfc5d839
MB		 4240 dst_num++;
4241
4242 if (flow_act->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
4243 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
4244 dst[dst_num].counter_id = counter_id;
4245 dst_num++;
4246 }
4247
bb0ee7dc
JL		 4248 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher,
4249 flow_context, flow_act,
bfc5d839 4250 cmd_in, inlen, dst_num);
d4be3f44
YH		 4251
4252 if (IS_ERR(handler)) {
4253 err = PTR_ERR(handler);
4254 goto destroy_ft;
4255 }
4256
4257 mutex_unlock(&dev->flow_db->lock);
4258 atomic_inc(&fs_matcher->usecnt);
4259 handler->flow_matcher = fs_matcher;
4260
4261 kfree(dst);
4262
4263 return handler;
4264
4265destroy_ft:
4266 put_flow_table(dev, ft_prio, false);
4267unlock:
4268 mutex_unlock(&dev->flow_db->lock);
4269 kfree(dst);
4270
4271 return ERR_PTR(err);
32269441
YH		 4272}
4273
c6475a0b
AY		 4274static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
4275{
4276 u32 flags = 0;
4277
4278 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
4279 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
4280
4281 return flags;
4282}
4283
4284#define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
4285static struct ib_flow_action *
4286mlx5_ib_create_flow_action_esp(struct ib_device *device,
4287 const struct ib_flow_action_attrs_esp *attr,
4288 struct uverbs_attr_bundle *attrs)
4289{
4290 struct mlx5_ib_dev *mdev = to_mdev(device);
4291 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
4292 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
4293 struct mlx5_ib_flow_action *action;
4294 u64 action_flags;
4295 u64 flags;
4296 int err = 0;
4297
bccd0622
JG		 4298 err = uverbs_get_flags64(
4299 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
4300 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1));
4301 if (err)
4302 return ERR_PTR(err);
c6475a0b
AY		 4303
4304 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
4305
4306 /* We current only support a subset of the standard features. Only a
4307 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
4308 * (with overlap). Full offload mode isn't supported.
4309 */
4310 if (!attr->keymat || attr->replay || attr->encap ||
4311 attr->spi || attr->seq || attr->tfc_pad ||
4312 attr->hard_limit_pkts ||
4313 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4314 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
4315 return ERR_PTR(-EOPNOTSUPP);
4316
4317 if (attr->keymat->protocol !=
4318 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
4319 return ERR_PTR(-EOPNOTSUPP);
4320
4321 aes_gcm = &attr->keymat->keymat.aes_gcm;
4322
4323 if (aes_gcm->icv_len != 16 ||
4324 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
4325 return ERR_PTR(-EOPNOTSUPP);
4326
4327 action = kmalloc(sizeof(*action), GFP_KERNEL);
4328 if (!action)
4329 return ERR_PTR(-ENOMEM);
4330
4331 action->esp_aes_gcm.ib_flags = attr->flags;
4332 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
4333 sizeof(accel_attrs.keymat.aes_gcm.aes_key));
4334 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
4335 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
4336 sizeof(accel_attrs.keymat.aes_gcm.salt));
4337 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
4338 sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
4339 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
4340 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
4341 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
4342
4343 accel_attrs.esn = attr->esn;
4344 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
4345 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
4346 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4347 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4348
4349 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
4350 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
4351
4352 action->esp_aes_gcm.ctx =
4353 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
4354 if (IS_ERR(action->esp_aes_gcm.ctx)) {
4355 err = PTR_ERR(action->esp_aes_gcm.ctx);
4356 goto err_parse;
4357 }
4358
4359 action->esp_aes_gcm.ib_flags = attr->flags;
4360
4361 return &action->ib_action;
4362
4363err_parse:
4364 kfree(action);
4365 return ERR_PTR(err);
4366}
4367
349705c1
MB		 4368static int
4369mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
4370 const struct ib_flow_action_attrs_esp *attr,
4371 struct uverbs_attr_bundle *attrs)
4372{
4373 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4374 struct mlx5_accel_esp_xfrm_attrs accel_attrs;
4375 int err = 0;
4376
4377 if (attr->keymat || attr->replay || attr->encap ||
4378 attr->spi || attr->seq || attr->tfc_pad ||
4379 attr->hard_limit_pkts ||
4380 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4381 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
4382 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
4383 return -EOPNOTSUPP;
4384
4385 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
4386 * be modified.
4387 */
4388 if (!(maction->esp_aes_gcm.ib_flags &
4389 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
4390 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4391 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
4392 return -EINVAL;
4393
4394 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
4395 sizeof(accel_attrs));
4396
4397 accel_attrs.esn = attr->esn;
4398 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4399 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4400 else
4401 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4402
4403 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
4404 &accel_attrs);
4405 if (err)
4406 return err;
4407
4408 maction->esp_aes_gcm.ib_flags &=
4409 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4410 maction->esp_aes_gcm.ib_flags |=
4411 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4412
4413 return 0;
4414}
4415
c6475a0b
AY		 4416static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
4417{
4418 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4419
4420 switch (action->type) {
4421 case IB_FLOW_ACTION_ESP:
4422 /*
4423 * We only support aes_gcm by now, so we implicitly know this is
4424 * the underline crypto.
4425 */
4426 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
4427 break;
b4749bf2
MB		 4428 case IB_FLOW_ACTION_UNSPECIFIED:
4429 mlx5_ib_destroy_flow_action_raw(maction);
4430 break;
c6475a0b
AY		 4431 default:
4432 WARN_ON(true);
4433 break;
4434 }
4435
4436 kfree(maction);
4437 return 0;
4438}
4439
e126ba97
EC		 4440static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4441{
4442 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 4443 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97 4444 int err;
539ec982
YH		 4445 u16 uid;
4446
4447 uid = ibqp->pd ?
4448 to_mpd(ibqp->pd)->uid : 0;
e126ba97 4449
2be08c30 4450 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) {
81e30880
YH		 4451 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
4452 return -EOPNOTSUPP;
4453 }
4454
539ec982 4455 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
e126ba97
EC		 4456 if (err)
4457 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
4458 ibqp->qp_num, gid->raw);
4459
4460 return err;
4461}
4462
4463static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4464{
4465 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4466 int err;
539ec982 4467 u16 uid;
e126ba97 4468
539ec982
YH		 4469 uid = ibqp->pd ?
4470 to_mpd(ibqp->pd)->uid : 0;
4471 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
e126ba97
EC		 4472 if (err)
4473 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
4474 ibqp->qp_num, gid->raw);
4475
4476 return err;
4477}
4478
4479static int init_node_data(struct mlx5_ib_dev *dev)
4480{
1b5daf11 4481 int err;
e126ba97 4482
1b5daf11 4483 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 4484 if (err)
1b5daf11 4485 return err;
e126ba97 4486
1b5daf11 4487 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 4488
1b5daf11 4489 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 4490}
4491
508a523f
PP		 4492static ssize_t fw_pages_show(struct device *device,
4493 struct device_attribute *attr, char *buf)
e126ba97
EC		 4494{
4495 struct mlx5_ib_dev *dev =
54747231 4496 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
e126ba97 4497
9603b61d 4498 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97 4499}
508a523f 4500static DEVICE_ATTR_RO(fw_pages);
e126ba97 4501
508a523f 4502static ssize_t reg_pages_show(struct device *device,
e126ba97
EC		 4503 struct device_attribute *attr, char *buf)
4504{
4505 struct mlx5_ib_dev *dev =
54747231 4506 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
e126ba97 4507
6aec21f6 4508 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97 4509}
508a523f 4510static DEVICE_ATTR_RO(reg_pages);
e126ba97 4511
508a523f
PP		 4512static ssize_t hca_type_show(struct device *device,
4513 struct device_attribute *attr, char *buf)
e126ba97
EC		 4514{
4515 struct mlx5_ib_dev *dev =
54747231
PP		 4516 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4517
9603b61d 4518 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97 4519}
508a523f 4520static DEVICE_ATTR_RO(hca_type);
e126ba97 4521
508a523f
PP		 4522static ssize_t hw_rev_show(struct device *device,
4523 struct device_attribute *attr, char *buf)
e126ba97
EC		 4524{
4525 struct mlx5_ib_dev *dev =
54747231
PP		 4526 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4527
9603b61d 4528 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97 4529}
508a523f 4530static DEVICE_ATTR_RO(hw_rev);
e126ba97 4531
508a523f
PP		 4532static ssize_t board_id_show(struct device *device,
4533 struct device_attribute *attr, char *buf)
e126ba97
EC		 4534{
4535 struct mlx5_ib_dev *dev =
54747231
PP		 4536 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4537
e126ba97 4538 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 4539 dev->mdev->board_id);
e126ba97 4540}
508a523f 4541static DEVICE_ATTR_RO(board_id);
e126ba97 4542
508a523f
PP		 4543static struct attribute *mlx5_class_attributes[] = {
4544 &dev_attr_hw_rev.attr,
4545 &dev_attr_hca_type.attr,
4546 &dev_attr_board_id.attr,
4547 &dev_attr_fw_pages.attr,
4548 &dev_attr_reg_pages.attr,
4549 NULL,
4550};
e126ba97 4551
508a523f
PP		 4552static const struct attribute_group mlx5_attr_group = {
4553 .attrs = mlx5_class_attributes,
e126ba97
EC		 4554};
4555
7722f47e
HE		 4556static void pkey_change_handler(struct work_struct *work)
4557{
4558 struct mlx5_ib_port_resources *ports =
4559 container_of(work, struct mlx5_ib_port_resources,
4560 pkey_change_work);
4561
4562 mutex_lock(&ports->devr->mutex);
4563 mlx5_ib_gsi_pkey_change(ports->gsi);
4564 mutex_unlock(&ports->devr->mutex);
4565}
4566
89ea94a7
MG		 4567static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
4568{
4569 struct mlx5_ib_qp *mqp;
4570 struct mlx5_ib_cq *send_mcq, *recv_mcq;
4571 struct mlx5_core_cq *mcq;
4572 struct list_head cq_armed_list;
4573 unsigned long flags_qp;
4574 unsigned long flags_cq;
4575 unsigned long flags;
4576
4577 INIT_LIST_HEAD(&cq_armed_list);
4578
4579 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
4580 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
4581 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
4582 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
4583 if (mqp->sq.tail != mqp->sq.head) {
4584 send_mcq = to_mcq(mqp->ibqp.send_cq);
4585 spin_lock_irqsave(&send_mcq->lock, flags_cq);
4586 if (send_mcq->mcq.comp &&
4587 mqp->ibqp.send_cq->comp_handler) {
4588 if (!send_mcq->mcq.reset_notify_added) {
4589 send_mcq->mcq.reset_notify_added = 1;
4590 list_add_tail(&send_mcq->mcq.reset_notify,
4591 &cq_armed_list);
4592 }
4593 }
4594 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
4595 }
4596 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
4597 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
4598 /* no handling is needed for SRQ */
4599 if (!mqp->ibqp.srq) {
4600 if (mqp->rq.tail != mqp->rq.head) {
4601 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
4602 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
4603 if (recv_mcq->mcq.comp &&
4604 mqp->ibqp.recv_cq->comp_handler) {
4605 if (!recv_mcq->mcq.reset_notify_added) {
4606 recv_mcq->mcq.reset_notify_added = 1;
4607 list_add_tail(&recv_mcq->mcq.reset_notify,
4608 &cq_armed_list);
4609 }
4610 }
4611 spin_unlock_irqrestore(&recv_mcq->lock,
4612 flags_cq);
4613 }
4614 }
4615 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
4616 }
4617 /*At that point all inflight post send were put to be executed as of we
4618 * lock/unlock above locks Now need to arm all involved CQs.
4619 */
4620 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4e0e2ea1 4621 mcq->comp(mcq, NULL);
89ea94a7
MG		 4622 }
4623 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
4624}
4625
03404e8a
MG		 4626static void delay_drop_handler(struct work_struct *work)
4627{
4628 int err;
4629 struct mlx5_ib_delay_drop *delay_drop =
4630 container_of(work, struct mlx5_ib_delay_drop,
4631 delay_drop_work);
4632
fe248c3a
MG		 4633 atomic_inc(&delay_drop->events_cnt);
4634
03404e8a 4635 mutex_lock(&delay_drop->lock);
333fbaa0 4636 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout);
03404e8a
MG		 4637 if (err) {
4638 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4639 delay_drop->timeout);
4640 delay_drop->activate = false;
4641 }
4642 mutex_unlock(&delay_drop->lock);
4643}
4644
09e574fa
SM		 4645static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4646 struct ib_event *ibev)
4647{
6cfdc7e4
AL		 4648 u8 port = (eqe->data.port.port >> 4) & 0xf;
4649
09e574fa
SM		 4650 switch (eqe->sub_type) {
4651 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
6cfdc7e4
AL		 4652 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4653 IB_LINK_LAYER_ETHERNET)
4654 schedule_work(&ibdev->delay_drop.delay_drop_work);
09e574fa
SM		 4655 break;
4656 default: /* do nothing */
4657 return;
4658 }
4659}
4660
134e9349
SM		 4661static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4662 struct ib_event *ibev)
4663{
4664 u8 port = (eqe->data.port.port >> 4) & 0xf;
4665
4666 ibev->element.port_num = port;
4667
4668 switch (eqe->sub_type) {
4669 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
4670 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
4671 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
4672 /* In RoCE, port up/down events are handled in
4673 * mlx5_netdev_event().
4674 */
4675 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4676 IB_LINK_LAYER_ETHERNET)
4677 return -EINVAL;
4678
4679 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
4680 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
4681 break;
4682
4683 case MLX5_PORT_CHANGE_SUBTYPE_LID:
4684 ibev->event = IB_EVENT_LID_CHANGE;
4685 break;
4686
4687 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
4688 ibev->event = IB_EVENT_PKEY_CHANGE;
4689 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
4690 break;
4691
4692 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
4693 ibev->event = IB_EVENT_GID_CHANGE;
4694 break;
4695
4696 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
4697 ibev->event = IB_EVENT_CLIENT_REREGISTER;
4698 break;
4699 default:
4700 return -EINVAL;
4701 }
4702
4703 return 0;
4704}
4705
d69a24e0 4706static void mlx5_ib_handle_event(struct work_struct *_work)
e126ba97 4707{
d69a24e0
DJ		 4708 struct mlx5_ib_event_work *work =
4709 container_of(_work, struct mlx5_ib_event_work, work);
4710 struct mlx5_ib_dev *ibdev;
e126ba97 4711 struct ib_event ibev;
dbaaff2a 4712 bool fatal = false;
e126ba97 4713
df097a27
SM		 4714 if (work->is_slave) {
4715 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
d69a24e0
DJ		 4716 if (!ibdev)
4717 goto out;
4718 } else {
df097a27 4719 ibdev = work->dev;
d69a24e0
DJ		 4720 }
4721
4722 switch (work->event) {
e126ba97 4723 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 4724 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 4725 mlx5_ib_handle_internal_error(ibdev);
134e9349 4726 ibev.element.port_num = (u8)(unsigned long)work->param;
dbaaff2a 4727 fatal = true;
e126ba97 4728 break;
134e9349
SM		 4729 case MLX5_EVENT_TYPE_PORT_CHANGE:
4730 if (handle_port_change(ibdev, work->param, &ibev))
d69a24e0 4731 goto out;
e126ba97 4732 break;
09e574fa
SM		 4733 case MLX5_EVENT_TYPE_GENERAL_EVENT:
4734 handle_general_event(ibdev, work->param, &ibev);
4735 /* fall through */
bdc37924 4736 default:
03404e8a 4737 goto out;
e126ba97
EC		 4738 }
4739
134e9349 4740 ibev.device = &ibdev->ib_dev;
e126ba97 4741
134e9349
SM		 4742 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
4743 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num);
03404e8a 4744 goto out;
a0c84c32
EC		 4745 }
4746
e126ba97
EC		 4747 if (ibdev->ib_active)
4748 ib_dispatch_event(&ibev);
dbaaff2a
EC		 4749
4750 if (fatal)
4751 ibdev->ib_active = false;
03404e8a 4752out:
d69a24e0
DJ		 4753 kfree(work);
4754}
4755
df097a27
SM		 4756static int mlx5_ib_event(struct notifier_block *nb,
4757 unsigned long event, void *param)
d69a24e0
DJ		 4758{
4759 struct mlx5_ib_event_work *work;
4760
4761 work = kmalloc(sizeof(*work), GFP_ATOMIC);
10bea9c8 4762 if (!work)
df097a27 4763 return NOTIFY_DONE;
d69a24e0 4764
10bea9c8 4765 INIT_WORK(&work->work, mlx5_ib_handle_event);
df097a27
SM		 4766 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
4767 work->is_slave = false;
10bea9c8 4768 work->param = param;
10bea9c8
LR		 4769 work->event = event;
4770
4771 queue_work(mlx5_ib_event_wq, &work->work);
df097a27
SM		 4772
4773 return NOTIFY_OK;
4774}
4775
4776static int mlx5_ib_event_slave_port(struct notifier_block *nb,
4777 unsigned long event, void *param)
4778{
4779 struct mlx5_ib_event_work *work;
4780
4781 work = kmalloc(sizeof(*work), GFP_ATOMIC);
4782 if (!work)
4783 return NOTIFY_DONE;
4784
4785 INIT_WORK(&work->work, mlx5_ib_handle_event);
4786 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
4787 work->is_slave = true;
4788 work->param = param;
4789 work->event = event;
4790 queue_work(mlx5_ib_event_wq, &work->work);
4791
4792 return NOTIFY_OK;
e126ba97
EC		 4793}
4794
c43f1112
MG		 4795static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4796{
4797 struct mlx5_hca_vport_context vport_ctx;
4798 int err;
4799 int port;
4800
a989ea01 4801 for (port = 1; port <= ARRAY_SIZE(dev->mdev->port_caps); port++) {
c43f1112
MG		 4802 dev->mdev->port_caps[port - 1].has_smi = false;
4803 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4804 MLX5_CAP_PORT_TYPE_IB) {
4805 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4806 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4807 port, 0,
4808 &vport_ctx);
4809 if (err) {
4810 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4811 port, err);
4812 return err;
4813 }
4814 dev->mdev->port_caps[port - 1].has_smi =
4815 vport_ctx.has_smi;
4816 } else {
4817 dev->mdev->port_caps[port - 1].has_smi = true;
4818 }
4819 }
4820 }
4821 return 0;
4822}
4823
e126ba97
EC		 4824static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4825{
4826 int port;
4827
508562d6 4828 for (port = 1; port <= dev->num_ports; port++)
e126ba97
EC		 4829 mlx5_query_ext_port_caps(dev, port);
4830}
4831
26628e2d 4832static int __get_port_caps(struct mlx5_ib_dev *dev, u8 port)
e126ba97
EC		 4833{
4834 struct ib_device_attr *dprops = NULL;
4835 struct ib_port_attr *pprops = NULL;
f614fc15 4836 int err = -ENOMEM;
e126ba97 4837
50ba3c18 4838 pprops = kzalloc(sizeof(*pprops), GFP_KERNEL);
e126ba97
EC		 4839 if (!pprops)
4840 goto out;
4841
4842 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4843 if (!dprops)
4844 goto out;
4845
48357091 4846 err = mlx5_ib_query_device(&dev->ib_dev, dprops, NULL);
e126ba97
EC		 4847 if (err) {
4848 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4849 goto out;
4850 }
4851
32f69e4b
DJ		 4852 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4853 if (err) {
4854 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4855 port, err);
4856 goto out;
e126ba97
EC		 4857 }
4858
32f69e4b
DJ		 4859 dev->mdev->port_caps[port - 1].pkey_table_len =
4860 dprops->max_pkeys;
4861 dev->mdev->port_caps[port - 1].gid_table_len =
4862 pprops->gid_tbl_len;
4863 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4864 port, dprops->max_pkeys, pprops->gid_tbl_len);
4865
e126ba97
EC		 4866out:
4867 kfree(pprops);
4868 kfree(dprops);
4869
4870 return err;
4871}
4872
26628e2d
MB		 4873static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4874{
4875 /* For representors use port 1, is this is the only native
4876 * port
4877 */
4878 if (dev->is_rep)
4879 return __get_port_caps(dev, 1);
4880 return __get_port_caps(dev, port);
4881}
4882
e126ba97
EC		 4883static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4884{
4885 int err;
4886
4887 err = mlx5_mr_cache_cleanup(dev);
4888 if (err)
4889 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4890
32927e28 4891 if (dev->umrc.qp)
c4367a26 4892 mlx5_ib_destroy_qp(dev->umrc.qp, NULL);
32927e28
MB		 4893 if (dev->umrc.cq)
4894 ib_free_cq(dev->umrc.cq);
4895 if (dev->umrc.pd)
4896 ib_dealloc_pd(dev->umrc.pd);
e126ba97
EC		 4897}
4898
4899enum {
4900 MAX_UMR_WR = 128,
4901};
4902
4903static int create_umr_res(struct mlx5_ib_dev *dev)
4904{
4905 struct ib_qp_init_attr *init_attr = NULL;
4906 struct ib_qp_attr *attr = NULL;
4907 struct ib_pd *pd;
4908 struct ib_cq *cq;
4909 struct ib_qp *qp;
e126ba97
EC		 4910 int ret;
4911
4912 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4913 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4914 if (!attr || !init_attr) {
4915 ret = -ENOMEM;
4916 goto error_0;
4917 }
4918
ed082d36 4919 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 4920 if (IS_ERR(pd)) {
4921 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4922 ret = PTR_ERR(pd);
4923 goto error_0;
4924 }
4925
add08d76 4926 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 4927 if (IS_ERR(cq)) {
4928 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4929 ret = PTR_ERR(cq);
4930 goto error_2;
4931 }
e126ba97
EC		 4932
4933 init_attr->send_cq = cq;
4934 init_attr->recv_cq = cq;
4935 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4936 init_attr->cap.max_send_wr = MAX_UMR_WR;
4937 init_attr->cap.max_send_sge = 1;
4938 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4939 init_attr->port_num = 1;
4940 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4941 if (IS_ERR(qp)) {
4942 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4943 ret = PTR_ERR(qp);
4944 goto error_3;
4945 }
4946 qp->device = &dev->ib_dev;
4947 qp->real_qp = qp;
4948 qp->uobject = NULL;
4949 qp->qp_type = MLX5_IB_QPT_REG_UMR;
31fde034
MD		 4950 qp->send_cq = init_attr->send_cq;
4951 qp->recv_cq = init_attr->recv_cq;
e126ba97
EC		 4952
4953 attr->qp_state = IB_QPS_INIT;
4954 attr->port_num = 1;
4955 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4956 IB_QP_PORT, NULL);
4957 if (ret) {
4958 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4959 goto error_4;
4960 }
4961
4962 memset(attr, 0, sizeof(*attr));
4963 attr->qp_state = IB_QPS_RTR;
4964 attr->path_mtu = IB_MTU_256;
4965
4966 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4967 if (ret) {
4968 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4969 goto error_4;
4970 }
4971
4972 memset(attr, 0, sizeof(*attr));
4973 attr->qp_state = IB_QPS_RTS;
4974 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4975 if (ret) {
4976 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4977 goto error_4;
4978 }
4979
4980 dev->umrc.qp = qp;
4981 dev->umrc.cq = cq;
e126ba97
EC		 4982 dev->umrc.pd = pd;
4983
4984 sema_init(&dev->umrc.sem, MAX_UMR_WR);
4985 ret = mlx5_mr_cache_init(dev);
4986 if (ret) {
4987 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4988 goto error_4;
4989 }
4990
4991 kfree(attr);
4992 kfree(init_attr);
4993
4994 return 0;
4995
4996error_4:
c4367a26 4997 mlx5_ib_destroy_qp(qp, NULL);
32927e28 4998 dev->umrc.qp = NULL;
e126ba97
EC		 4999
5000error_3:
add08d76 5001 ib_free_cq(cq);
32927e28 5002 dev->umrc.cq = NULL;
e126ba97
EC		 5003
5004error_2:
e126ba97 5005 ib_dealloc_pd(pd);
32927e28 5006 dev->umrc.pd = NULL;
e126ba97
EC		 5007
5008error_0:
5009 kfree(attr);
5010 kfree(init_attr);
5011 return ret;
5012}
5013
6e8484c5
MG		 5014static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
5015{
5016 switch (umr_fence_cap) {
5017 case MLX5_CAP_UMR_FENCE_NONE:
5018 return MLX5_FENCE_MODE_NONE;
5019 case MLX5_CAP_UMR_FENCE_SMALL:
5020 return MLX5_FENCE_MODE_INITIATOR_SMALL;
5021 default:
5022 return MLX5_FENCE_MODE_STRONG_ORDERING;
5023 }
5024}
5025
e126ba97
EC		 5026static int create_dev_resources(struct mlx5_ib_resources *devr)
5027{
5028 struct ib_srq_init_attr attr;
5029 struct mlx5_ib_dev *dev;
21a428a0 5030 struct ib_device *ibdev;
bcf4c1ea 5031 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 5032 int port;
e126ba97
EC		 5033 int ret = 0;
5034
5035 dev = container_of(devr, struct mlx5_ib_dev, devr);
21a428a0 5036 ibdev = &dev->ib_dev;
e126ba97 5037
d16e91da
HE		 5038 mutex_init(&devr->mutex);
5039
21a428a0
LR		 5040 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd);
5041 if (!devr->p0)
5042 return -ENOMEM;
5043
5044 devr->p0->device = ibdev;
e126ba97
EC		 5045 devr->p0->uobject = NULL;
5046 atomic_set(&devr->p0->usecnt, 0);
5047
ff23dfa1 5048 ret = mlx5_ib_alloc_pd(devr->p0, NULL);
21a428a0
LR		 5049 if (ret)
5050 goto error0;
5051
e39afe3d
LR		 5052 devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq);
5053 if (!devr->c0) {
5054 ret = -ENOMEM;
e126ba97
EC		 5055 goto error1;
5056 }
e39afe3d
LR		 5057
5058 devr->c0->device = &dev->ib_dev;
e126ba97
EC		 5059 atomic_set(&devr->c0->usecnt, 0);
5060
e39afe3d
LR		 5061 ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL);
5062 if (ret)
5063 goto err_create_cq;
5064
ff23dfa1 5065 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
e126ba97
EC		 5066 if (IS_ERR(devr->x0)) {
5067 ret = PTR_ERR(devr->x0);
5068 goto error2;
5069 }
5070 devr->x0->device = &dev->ib_dev;
5071 devr->x0->inode = NULL;
5072 atomic_set(&devr->x0->usecnt, 0);
5073 mutex_init(&devr->x0->tgt_qp_mutex);
5074 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
5075
ff23dfa1 5076 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
e126ba97
EC		 5077 if (IS_ERR(devr->x1)) {
5078 ret = PTR_ERR(devr->x1);
5079 goto error3;
5080 }
5081 devr->x1->device = &dev->ib_dev;
5082 devr->x1->inode = NULL;
5083 atomic_set(&devr->x1->usecnt, 0);
5084 mutex_init(&devr->x1->tgt_qp_mutex);
5085 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
5086
5087 memset(&attr, 0, sizeof(attr));
5088 attr.attr.max_sge = 1;
5089 attr.attr.max_wr = 1;
5090 attr.srq_type = IB_SRQT_XRC;
1a56ff6d 5091 attr.ext.cq = devr->c0;
e126ba97
EC		 5092 attr.ext.xrc.xrcd = devr->x0;
5093
68e326de
LR		 5094 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq);
5095 if (!devr->s0) {
5096 ret = -ENOMEM;
e126ba97
EC		 5097 goto error4;
5098 }
68e326de 5099
e126ba97
EC		 5100 devr->s0->device = &dev->ib_dev;
5101 devr->s0->pd = devr->p0;
e126ba97
EC		 5102 devr->s0->srq_type = IB_SRQT_XRC;
5103 devr->s0->ext.xrc.xrcd = devr->x0;
1a56ff6d 5104 devr->s0->ext.cq = devr->c0;
68e326de
LR		 5105 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL);
5106 if (ret)
5107 goto err_create;
5108
e126ba97 5109 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1a56ff6d 5110 atomic_inc(&devr->s0->ext.cq->usecnt);
e126ba97
EC		 5111 atomic_inc(&devr->p0->usecnt);
5112 atomic_set(&devr->s0->usecnt, 0);
5113
4aa17b28
HA		 5114 memset(&attr, 0, sizeof(attr));
5115 attr.attr.max_sge = 1;
5116 attr.attr.max_wr = 1;
5117 attr.srq_type = IB_SRQT_BASIC;
68e326de
LR		 5118 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq);
5119 if (!devr->s1) {
5120 ret = -ENOMEM;
4aa17b28
HA		 5121 goto error5;
5122 }
68e326de 5123
4aa17b28
HA		 5124 devr->s1->device = &dev->ib_dev;
5125 devr->s1->pd = devr->p0;
4aa17b28 5126 devr->s1->srq_type = IB_SRQT_BASIC;
1a56ff6d 5127 devr->s1->ext.cq = devr->c0;
68e326de
LR		 5128
5129 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL);
5130 if (ret)
5131 goto error6;
5132
4aa17b28 5133 atomic_inc(&devr->p0->usecnt);
1a56ff6d 5134 atomic_set(&devr->s1->usecnt, 0);
4aa17b28 5135
7722f47e
HE		 5136 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
5137 INIT_WORK(&devr->ports[port].pkey_change_work,
5138 pkey_change_handler);
5139 devr->ports[port].devr = devr;
5140 }
5141
e126ba97
EC		 5142 return 0;
5143
68e326de
LR		 5144error6:
5145 kfree(devr->s1);
4aa17b28 5146error5:
c4367a26 5147 mlx5_ib_destroy_srq(devr->s0, NULL);
68e326de
LR		 5148err_create:
5149 kfree(devr->s0);
e126ba97 5150error4:
c4367a26 5151 mlx5_ib_dealloc_xrcd(devr->x1, NULL);
e126ba97 5152error3:
c4367a26 5153 mlx5_ib_dealloc_xrcd(devr->x0, NULL);
e126ba97 5154error2:
c4367a26 5155 mlx5_ib_destroy_cq(devr->c0, NULL);
e39afe3d
LR		 5156err_create_cq:
5157 kfree(devr->c0);
e126ba97 5158error1:
c4367a26 5159 mlx5_ib_dealloc_pd(devr->p0, NULL);
e126ba97 5160error0:
21a428a0 5161 kfree(devr->p0);
e126ba97
EC		 5162 return ret;
5163}
5164
5165static void destroy_dev_resources(struct mlx5_ib_resources *devr)
5166{
7722f47e
HE		 5167 int port;
5168
c4367a26 5169 mlx5_ib_destroy_srq(devr->s1, NULL);
68e326de 5170 kfree(devr->s1);
c4367a26 5171 mlx5_ib_destroy_srq(devr->s0, NULL);
68e326de 5172 kfree(devr->s0);
c4367a26
SR		 5173 mlx5_ib_dealloc_xrcd(devr->x0, NULL);
5174 mlx5_ib_dealloc_xrcd(devr->x1, NULL);
5175 mlx5_ib_destroy_cq(devr->c0, NULL);
e39afe3d 5176 kfree(devr->c0);
c4367a26 5177 mlx5_ib_dealloc_pd(devr->p0, NULL);
21a428a0 5178 kfree(devr->p0);
7722f47e
HE		 5179
5180 /* Make sure no change P_Key work items are still executing */
5d8f6a0e 5181 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
7722f47e 5182 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 5183}
5184
b02289b3
AK		 5185static u32 get_core_cap_flags(struct ib_device *ibdev,
5186 struct mlx5_hca_vport_context *rep)
e53505a8
AS		 5187{
5188 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5189 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
5190 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
5191 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
85c7c014 5192 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
e53505a8
AS		 5193 u32 ret = 0;
5194
b02289b3
AK		 5195 if (rep->grh_required)
5196 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
5197
e53505a8 5198 if (ll == IB_LINK_LAYER_INFINIBAND)
b02289b3 5199 return ret | RDMA_CORE_PORT_IBA_IB;
e53505a8 5200
85c7c014 5201 if (raw_support)
b02289b3 5202 ret |= RDMA_CORE_PORT_RAW_PACKET;
72cd5717 5203
e53505a8 5204 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 5205 return ret;
e53505a8
AS		 5206
5207 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 5208 return ret;
e53505a8
AS		 5209
5210 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
5211 ret |= RDMA_CORE_PORT_IBA_ROCE;
5212
5213 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
5214 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
5215
5216 return ret;
5217}
5218
7738613e
IW		 5219static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
5220 struct ib_port_immutable *immutable)
5221{
5222 struct ib_port_attr attr;
ca5b91d6
OG		 5223 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5224 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
b02289b3 5225 struct mlx5_hca_vport_context rep = {0};
7738613e
IW		 5226 int err;
5227
c4550c63 5228 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 5229 if (err)
5230 return err;
5231
b02289b3
AK		 5232 if (ll == IB_LINK_LAYER_INFINIBAND) {
5233 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
5234 &rep);
5235 if (err)
5236 return err;
5237 }
5238
7738613e
IW		 5239 immutable->pkey_tbl_len = attr.pkey_tbl_len;
5240 immutable->gid_tbl_len = attr.gid_tbl_len;
b02289b3 5241 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
94de879c 5242 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 5243
5244 return 0;
5245}
5246
8e6efa3a
MB		 5247static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
5248 struct ib_port_immutable *immutable)
5249{
5250 struct ib_port_attr attr;
5251 int err;
5252
5253 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5254
5255 err = ib_query_port(ibdev, port_num, &attr);
5256 if (err)
5257 return err;
5258
5259 immutable->pkey_tbl_len = attr.pkey_tbl_len;
5260 immutable->gid_tbl_len = attr.gid_tbl_len;
5261 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5262
5263 return 0;
5264}
5265
9abb0d1b 5266static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 5267{
5268 struct mlx5_ib_dev *dev =
5269 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 5270 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
5271 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
5272 fw_rev_sub(dev->mdev));
c7342823
IW		 5273}
5274
45f95acd 5275static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 5276{
5277 struct mlx5_core_dev *mdev = dev->mdev;
5278 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
5279 MLX5_FLOW_NAMESPACE_LAG);
5280 struct mlx5_flow_table *ft;
5281 int err;
5282
7c34ec19 5283 if (!ns || !mlx5_lag_is_roce(mdev))
9ef9c640
AH		 5284 return 0;
5285
5286 err = mlx5_cmd_create_vport_lag(mdev);
5287 if (err)
5288 return err;
5289
5290 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
5291 if (IS_ERR(ft)) {
5292 err = PTR_ERR(ft);
5293 goto err_destroy_vport_lag;
5294 }
5295
9a4ca38d 5296 dev->flow_db->lag_demux_ft = ft;
7c34ec19 5297 dev->lag_active = true;
9ef9c640
AH		 5298 return 0;
5299
5300err_destroy_vport_lag:
5301 mlx5_cmd_destroy_vport_lag(mdev);
5302 return err;
5303}
5304
45f95acd 5305static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 5306{
5307 struct mlx5_core_dev *mdev = dev->mdev;
5308
7c34ec19
AH		 5309 if (dev->lag_active) {
5310 dev->lag_active = false;
5311
9a4ca38d
MB		 5312 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
5313 dev->flow_db->lag_demux_ft = NULL;
9ef9c640
AH		 5314
5315 mlx5_cmd_destroy_vport_lag(mdev);
5316 }
5317}
5318
7fd8aefb 5319static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
d012f5d6
OG		 5320{
5321 int err;
5322
95579e78
MB		 5323 dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event;
5324 err = register_netdevice_notifier(&dev->port[port_num].roce.nb);
d012f5d6 5325 if (err) {
95579e78 5326 dev->port[port_num].roce.nb.notifier_call = NULL;
d012f5d6
OG		 5327 return err;
5328 }
5329
5330 return 0;
5331}
5332
7fd8aefb 5333static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5ec8c83e 5334{
95579e78
MB		 5335 if (dev->port[port_num].roce.nb.notifier_call) {
5336 unregister_netdevice_notifier(&dev->port[port_num].roce.nb);
5337 dev->port[port_num].roce.nb.notifier_call = NULL;
5ec8c83e
AH		 5338 }
5339}
5340
e3f1ed1f 5341static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 5342{
e53505a8
AS		 5343 int err;
5344
94de879c
MG		 5345 err = mlx5_nic_vport_enable_roce(dev->mdev);
5346 if (err)
5347 return err;
e53505a8 5348
45f95acd 5349 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 5350 if (err)
5351 goto err_disable_roce;
5352
e53505a8
AS		 5353 return 0;
5354
9ef9c640 5355err_disable_roce:
94de879c 5356 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 5357
e53505a8 5358 return err;
fc24fc5e
AS		 5359}
5360
45f95acd 5361static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 5362{
45f95acd 5363 mlx5_eth_lag_cleanup(dev);
94de879c 5364 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 5365}
5366
e1f24a79 5367struct mlx5_ib_counter {
7c16f477
KH		 5368 const char *name;
5369 size_t offset;
5370};
5371
5372#define INIT_Q_COUNTER(_name) \
5373 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
5374
e1f24a79 5375static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 5376 INIT_Q_COUNTER(rx_write_requests),
5377 INIT_Q_COUNTER(rx_read_requests),
5378 INIT_Q_COUNTER(rx_atomic_requests),
5379 INIT_Q_COUNTER(out_of_buffer),
5380};
5381
e1f24a79 5382static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 5383 INIT_Q_COUNTER(out_of_sequence),
5384};
5385
e1f24a79 5386static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 5387 INIT_Q_COUNTER(duplicate_request),
5388 INIT_Q_COUNTER(rnr_nak_retry_err),
5389 INIT_Q_COUNTER(packet_seq_err),
5390 INIT_Q_COUNTER(implied_nak_seq_err),
5391 INIT_Q_COUNTER(local_ack_timeout_err),
5392};
5393
e1f24a79
PP		 5394#define INIT_CONG_COUNTER(_name) \
5395 { .name = #_name, .offset = \
5396 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
5397
5398static const struct mlx5_ib_counter cong_cnts[] = {
5399 INIT_CONG_COUNTER(rp_cnp_ignored),
5400 INIT_CONG_COUNTER(rp_cnp_handled),
5401 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
5402 INIT_CONG_COUNTER(np_cnp_sent),
5403};
5404
58dcb60a
PP		 5405static const struct mlx5_ib_counter extended_err_cnts[] = {
5406 INIT_Q_COUNTER(resp_local_length_error),
5407 INIT_Q_COUNTER(resp_cqe_error),
5408 INIT_Q_COUNTER(req_cqe_error),
5409 INIT_Q_COUNTER(req_remote_invalid_request),
5410 INIT_Q_COUNTER(req_remote_access_errors),
5411 INIT_Q_COUNTER(resp_remote_access_errors),
5412 INIT_Q_COUNTER(resp_cqe_flush_error),
5413 INIT_Q_COUNTER(req_cqe_flush_error),
5414};
5415
d7fab916
AH		 5416static const struct mlx5_ib_counter roce_accl_cnts[] = {
5417 INIT_Q_COUNTER(roce_adp_retrans),
5418 INIT_Q_COUNTER(roce_adp_retrans_to),
5419 INIT_Q_COUNTER(roce_slow_restart),
5420 INIT_Q_COUNTER(roce_slow_restart_cnps),
5421 INIT_Q_COUNTER(roce_slow_restart_trans),
5422};
5423
9f876f3d
TB		 5424#define INIT_EXT_PPCNT_COUNTER(_name) \
5425 { .name = #_name, .offset = \
5426 MLX5_BYTE_OFF(ppcnt_reg, \
5427 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
5428
5429static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
5430 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
5431};
5432
3e1f000f
PP		 5433static bool is_mdev_switchdev_mode(const struct mlx5_core_dev *mdev)
5434{
5435 return MLX5_ESWITCH_MANAGER(mdev) &&
5436 mlx5_ib_eswitch_mode(mdev->priv.eswitch) ==
5437 MLX5_ESWITCH_OFFLOADS;
5438}
5439
e1f24a79 5440static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a 5441{
66247fbb 5442 u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
3e1f000f 5443 int num_cnt_ports;
aac4492e 5444 int i;
0837e86a 5445
3e1f000f
PP		 5446 num_cnt_ports = is_mdev_switchdev_mode(dev->mdev) ? 1 : dev->num_ports;
5447
66247fbb
LR		 5448 MLX5_SET(dealloc_q_counter_in, in, opcode,
5449 MLX5_CMD_OP_DEALLOC_Q_COUNTER);
5450
3e1f000f 5451 for (i = 0; i < num_cnt_ports; i++) {
bfd745f8 5452 if (dev->port[i].cnts.set_id) {
66247fbb
LR		 5453 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
5454 dev->port[i].cnts.set_id);
5455 mlx5_cmd_exec_in(dev->mdev, dealloc_q_counter, in);
5456 }
e1f24a79
PP		 5457 kfree(dev->port[i].cnts.names);
5458 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 5459 }
5460}
5461
e1f24a79
PP		 5462static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
5463 struct mlx5_ib_counters *cnts)
7c16f477
KH		 5464{
5465 u32 num_counters;
5466
5467 num_counters = ARRAY_SIZE(basic_q_cnts);
5468
5469 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
5470 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
5471
5472 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
5473 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 5474
5475 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
5476 num_counters += ARRAY_SIZE(extended_err_cnts);
5477
d7fab916
AH		 5478 if (MLX5_CAP_GEN(dev->mdev, roce_accl))
5479 num_counters += ARRAY_SIZE(roce_accl_cnts);
5480
e1f24a79 5481 cnts->num_q_counters = num_counters;
7c16f477 5482
e1f24a79
PP		 5483 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5484 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
5485 num_counters += ARRAY_SIZE(cong_cnts);
5486 }
9f876f3d
TB		 5487 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5488 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
5489 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
5490 }
e1f24a79
PP		 5491 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
5492 if (!cnts->names)
7c16f477
KH		 5493 return -ENOMEM;
5494
e1f24a79
PP		 5495 cnts->offsets = kcalloc(num_counters,
5496 sizeof(cnts->offsets), GFP_KERNEL);
5497 if (!cnts->offsets)
7c16f477
KH		 5498 goto err_names;
5499
7c16f477
KH		 5500 return 0;
5501
5502err_names:
e1f24a79 5503 kfree(cnts->names);
aac4492e 5504 cnts->names = NULL;
7c16f477
KH		 5505 return -ENOMEM;
5506}
5507
e1f24a79
PP		 5508static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
5509 const char **names,
5510 size_t *offsets)
7c16f477
KH		 5511{
5512 int i;
5513 int j = 0;
5514
5515 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
5516 names[j] = basic_q_cnts[i].name;
5517 offsets[j] = basic_q_cnts[i].offset;
5518 }
5519
5520 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
5521 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
5522 names[j] = out_of_seq_q_cnts[i].name;
5523 offsets[j] = out_of_seq_q_cnts[i].offset;
5524 }
5525 }
5526
5527 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
5528 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
5529 names[j] = retrans_q_cnts[i].name;
5530 offsets[j] = retrans_q_cnts[i].offset;
5531 }
5532 }
e1f24a79 5533
58dcb60a
PP		 5534 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
5535 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
5536 names[j] = extended_err_cnts[i].name;
5537 offsets[j] = extended_err_cnts[i].offset;
5538 }
5539 }
5540
d7fab916
AH		 5541 if (MLX5_CAP_GEN(dev->mdev, roce_accl)) {
5542 for (i = 0; i < ARRAY_SIZE(roce_accl_cnts); i++, j++) {
5543 names[j] = roce_accl_cnts[i].name;
5544 offsets[j] = roce_accl_cnts[i].offset;
5545 }
5546 }
5547
e1f24a79
PP		 5548 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5549 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
5550 names[j] = cong_cnts[i].name;
5551 offsets[j] = cong_cnts[i].offset;
5552 }
5553 }
9f876f3d
TB		 5554
5555 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5556 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
5557 names[j] = ext_ppcnt_cnts[i].name;
5558 offsets[j] = ext_ppcnt_cnts[i].offset;
5559 }
5560 }
0837e86a
MB		 5561}
5562
e1f24a79 5563static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a 5564{
bfd745f8
LR		 5565 u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
5566 u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
3e1f000f 5567 int num_cnt_ports;
aac4492e 5568 int err = 0;
0837e86a 5569 int i;
aa74be6e
YH		 5570 bool is_shared;
5571
bfd745f8 5572 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
aa74be6e 5573 is_shared = MLX5_CAP_GEN(dev->mdev, log_max_uctx) != 0;
3e1f000f 5574 num_cnt_ports = is_mdev_switchdev_mode(dev->mdev) ? 1 : dev->num_ports;
0837e86a 5575
3e1f000f 5576 for (i = 0; i < num_cnt_ports; i++) {
aac4492e
DJ		 5577 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
5578 if (err)
5579 goto err_alloc;
5580
5581 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
5582 dev->port[i].cnts.offsets);
7c16f477 5583
bfd745f8
LR		 5584 MLX5_SET(alloc_q_counter_in, in, uid,
5585 is_shared ? MLX5_SHARED_RESOURCE_UID : 0);
5586
5587 err = mlx5_cmd_exec_inout(dev->mdev, alloc_q_counter, in, out);
aac4492e 5588 if (err) {
0837e86a
MB		 5589 mlx5_ib_warn(dev,
5590 "couldn't allocate queue counter for port %d, err %d\n",
aac4492e
DJ		 5591 i + 1, err);
5592 goto err_alloc;
0837e86a 5593 }
bfd745f8
LR		 5594
5595 dev->port[i].cnts.set_id =
5596 MLX5_GET(alloc_q_counter_out, out, counter_set_id);
0837e86a 5597 }
0837e86a
MB		 5598 return 0;
5599
aac4492e
DJ		 5600err_alloc:
5601 mlx5_ib_dealloc_counters(dev);
5602 return err;
0837e86a
MB		 5603}
5604
3e1f000f
PP		 5605static const struct mlx5_ib_counters *get_counters(struct mlx5_ib_dev *dev,
5606 u8 port_num)
5607{
5608 return is_mdev_switchdev_mode(dev->mdev) ? &dev->port[0].cnts :
5609 &dev->port[port_num].cnts;
5610}
5611
5612/**
5613 * mlx5_ib_get_counters_id - Returns counters id to use for device+port
5614 * @dev: Pointer to mlx5 IB device
5615 * @port_num: Zero based port number
5616 *
5617 * mlx5_ib_get_counters_id() Returns counters set id to use for given
5618 * device port combination in switchdev and non switchdev mode of the
5619 * parent device.
5620 */
5621u16 mlx5_ib_get_counters_id(struct mlx5_ib_dev *dev, u8 port_num)
5622{
5623 const struct mlx5_ib_counters *cnts = get_counters(dev, port_num);
5624
5625 return cnts->set_id;
5626}
5627
0ad17a8f
MB		 5628static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
5629 u8 port_num)
5630{
7c16f477 5631 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3e1f000f
PP		 5632 const struct mlx5_ib_counters *cnts;
5633 bool is_switchdev = is_mdev_switchdev_mode(dev->mdev);
0ad17a8f 5634
3e1f000f 5635 if ((is_switchdev && port_num) || (!is_switchdev && !port_num))
0ad17a8f
MB		 5636 return NULL;
5637
3e1f000f
PP		 5638 cnts = get_counters(dev, port_num - 1);
5639
5dcecbc9
PP		 5640 return rdma_alloc_hw_stats_struct(cnts->names,
5641 cnts->num_q_counters +
5642 cnts->num_cong_counters +
5643 cnts->num_ext_ppcnt_counters,
0ad17a8f
MB		 5644 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5645}
5646
aac4492e 5647static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
5dcecbc9 5648 const struct mlx5_ib_counters *cnts,
318d535c
MZ		 5649 struct rdma_hw_stats *stats,
5650 u16 set_id)
0ad17a8f 5651{
66247fbb
LR		 5652 u32 out[MLX5_ST_SZ_DW(query_q_counter_out)] = {};
5653 u32 in[MLX5_ST_SZ_DW(query_q_counter_in)] = {};
0ad17a8f 5654 __be32 val;
e1f24a79 5655 int ret, i;
0ad17a8f 5656
66247fbb
LR		 5657 MLX5_SET(query_q_counter_in, in, opcode, MLX5_CMD_OP_QUERY_Q_COUNTER);
5658 MLX5_SET(query_q_counter_in, in, counter_set_id, set_id);
5659 ret = mlx5_cmd_exec_inout(mdev, query_q_counter, in, out);
0ad17a8f 5660 if (ret)
66247fbb 5661 return ret;
0ad17a8f 5662
5dcecbc9 5663 for (i = 0; i < cnts->num_q_counters; i++) {
66247fbb 5664 val = *(__be32 *)((void *)out + cnts->offsets[i]);
0ad17a8f
MB		 5665 stats->value[i] = (u64)be32_to_cpu(val);
5666 }
7c16f477 5667
66247fbb 5668 return 0;
e1f24a79
PP		 5669}
5670
9f876f3d 5671static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
5dcecbc9
PP		 5672 const struct mlx5_ib_counters *cnts,
5673 struct rdma_hw_stats *stats)
9f876f3d 5674{
5dcecbc9 5675 int offset = cnts->num_q_counters + cnts->num_cong_counters;
9f876f3d
TB		 5676 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
5677 int ret, i;
5678 void *out;
5679
5680 out = kvzalloc(sz, GFP_KERNEL);
5681 if (!out)
5682 return -ENOMEM;
5683
5684 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
5685 if (ret)
5686 goto free;
5687
5dcecbc9 5688 for (i = 0; i < cnts->num_ext_ppcnt_counters; i++)
9f876f3d
TB		 5689 stats->value[i + offset] =
5690 be64_to_cpup((__be64 *)(out +
5dcecbc9 5691 cnts->offsets[i + offset]));
9f876f3d
TB		 5692free:
5693 kvfree(out);
5694 return ret;
5695}
5696
e1f24a79
PP		 5697static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
5698 struct rdma_hw_stats *stats,
5699 u8 port_num, int index)
5700{
5701 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3e1f000f 5702 const struct mlx5_ib_counters *cnts = get_counters(dev, port_num - 1);
aac4492e 5703 struct mlx5_core_dev *mdev;
e1f24a79 5704 int ret, num_counters;
aac4492e 5705 u8 mdev_port_num;
e1f24a79
PP		 5706
5707 if (!stats)
5708 return -EINVAL;
5709
5dcecbc9
PP		 5710 num_counters = cnts->num_q_counters +
5711 cnts->num_cong_counters +
5712 cnts->num_ext_ppcnt_counters;
aac4492e
DJ		 5713
5714 /* q_counters are per IB device, query the master mdev */
5dcecbc9 5715 ret = mlx5_ib_query_q_counters(dev->mdev, cnts, stats, cnts->set_id);
e1f24a79
PP		 5716 if (ret)
5717 return ret;
e1f24a79 5718
9f876f3d 5719 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5dcecbc9 5720 ret = mlx5_ib_query_ext_ppcnt_counters(dev, cnts, stats);
9f876f3d
TB		 5721 if (ret)
5722 return ret;
5723 }
5724
e1f24a79 5725 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
aac4492e
DJ		 5726 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
5727 &mdev_port_num);
5728 if (!mdev) {
5729 /* If port is not affiliated yet, its in down state
5730 * which doesn't have any counters yet, so it would be
5731 * zero. So no need to read from the HCA.
5732 */
5733 goto done;
5734 }
71a0ff65
MD		 5735 ret = mlx5_lag_query_cong_counters(dev->mdev,
5736 stats->value +
5dcecbc9
PP		 5737 cnts->num_q_counters,
5738 cnts->num_cong_counters,
5739 cnts->offsets +
5740 cnts->num_q_counters);
aac4492e
DJ		 5741
5742 mlx5_ib_put_native_port_mdev(dev, port_num);
e1f24a79
PP		 5743 if (ret)
5744 return ret;
e1f24a79
PP		 5745 }
5746
aac4492e 5747done:
e1f24a79 5748 return num_counters;
0ad17a8f
MB		 5749}
5750
18d422ce
MZ		 5751static struct rdma_hw_stats *
5752mlx5_ib_counter_alloc_stats(struct rdma_counter *counter)
5753{
5754 struct mlx5_ib_dev *dev = to_mdev(counter->device);
5dcecbc9 5755 const struct mlx5_ib_counters *cnts =
3e1f000f 5756 get_counters(dev, counter->port - 1);
18d422ce 5757
5dcecbc9 5758 return rdma_alloc_hw_stats_struct(cnts->names,
ec16b6bb
MZ		 5759 cnts->num_q_counters +
5760 cnts->num_cong_counters +
5761 cnts->num_ext_ppcnt_counters,
18d422ce
MZ		 5762 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5763}
5764
5765static int mlx5_ib_counter_update_stats(struct rdma_counter *counter)
5766{
5767 struct mlx5_ib_dev *dev = to_mdev(counter->device);
3e1f000f
PP		 5768 const struct mlx5_ib_counters *cnts =
5769 get_counters(dev, counter->port - 1);
18d422ce 5770
5dcecbc9 5771 return mlx5_ib_query_q_counters(dev->mdev, cnts,
18d422ce
MZ		 5772 counter->stats, counter->id);
5773}
5774
66247fbb
LR		 5775static int mlx5_ib_counter_dealloc(struct rdma_counter *counter)
5776{
5777 struct mlx5_ib_dev *dev = to_mdev(counter->device);
5778 u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
5779
5780 if (!counter->id)
5781 return 0;
5782
5783 MLX5_SET(dealloc_q_counter_in, in, opcode,
5784 MLX5_CMD_OP_DEALLOC_Q_COUNTER);
5785 MLX5_SET(dealloc_q_counter_in, in, counter_set_id, counter->id);
5786 return mlx5_cmd_exec_in(dev->mdev, dealloc_q_counter, in);
5787}
5788
45842fc6
MZ		 5789static int mlx5_ib_counter_bind_qp(struct rdma_counter *counter,
5790 struct ib_qp *qp)
5791{
5792 struct mlx5_ib_dev *dev = to_mdev(qp->device);
45842fc6
MZ		 5793 int err;
5794
5795 if (!counter->id) {
bfd745f8
LR		 5796 u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
5797 u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
5798
5799 MLX5_SET(alloc_q_counter_in, in, opcode,
5800 MLX5_CMD_OP_ALLOC_Q_COUNTER);
5801 MLX5_SET(alloc_q_counter_in, in, uid, MLX5_SHARED_RESOURCE_UID);
5802 err = mlx5_cmd_exec_inout(dev->mdev, alloc_q_counter, in, out);
45842fc6
MZ		 5803 if (err)
5804 return err;
bfd745f8
LR		 5805 counter->id =
5806 MLX5_GET(alloc_q_counter_out, out, counter_set_id);
45842fc6
MZ		 5807 }
5808
5809 err = mlx5_ib_qp_set_counter(qp, counter);
5810 if (err)
5811 goto fail_set_counter;
5812
5813 return 0;
5814
5815fail_set_counter:
66247fbb 5816 mlx5_ib_counter_dealloc(counter);
45842fc6
MZ		 5817 counter->id = 0;
5818
5819 return err;
5820}
5821
5822static int mlx5_ib_counter_unbind_qp(struct ib_qp *qp)
5823{
5824 return mlx5_ib_qp_set_counter(qp, NULL);
5825}
5826
f6a8a19b
DD		 5827static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num,
5828 enum rdma_netdev_t type,
5829 struct rdma_netdev_alloc_params *params)
693dfd5a
ES		 5830{
5831 if (type != RDMA_NETDEV_IPOIB)
f6a8a19b 5832 return -EOPNOTSUPP;
693dfd5a 5833
f6a8a19b 5834 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
693dfd5a
ES		 5835}
5836
fe248c3a
MG		 5837static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
5838{
09b0965e 5839 if (!dev->delay_drop.dir_debugfs)
fe248c3a 5840 return;
09b0965e
GKH		 5841 debugfs_remove_recursive(dev->delay_drop.dir_debugfs);
5842 dev->delay_drop.dir_debugfs = NULL;
fe248c3a
MG		 5843}
5844
03404e8a
MG		 5845static void cancel_delay_drop(struct mlx5_ib_dev *dev)
5846{
5847 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5848 return;
5849
5850 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 5851 delay_drop_debugfs_cleanup(dev);
5852}
5853
5854static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5855 size_t count, loff_t *pos)
5856{
5857 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5858 char lbuf[20];
5859 int len;
5860
5861 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5862 return simple_read_from_buffer(buf, count, pos, lbuf, len);
5863}
5864
5865static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5866 size_t count, loff_t *pos)
5867{
5868 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5869 u32 timeout;
5870 u32 var;
5871
5872 if (kstrtouint_from_user(buf, count, 0, &var))
5873 return -EFAULT;
5874
5875 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5876 1000);
5877 if (timeout != var)
5878 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5879 timeout);
5880
5881 delay_drop->timeout = timeout;
5882
5883 return count;
5884}
5885
5886static const struct file_operations fops_delay_drop_timeout = {
5887 .owner = THIS_MODULE,
5888 .open = simple_open,
5889 .write = delay_drop_timeout_write,
5890 .read = delay_drop_timeout_read,
5891};
5892
09b0965e 5893static void delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
fe248c3a 5894{
09b0965e 5895 struct dentry *root;
fe248c3a
MG		 5896
5897 if (!mlx5_debugfs_root)
09b0965e 5898 return;
fe248c3a 5899
09b0965e
GKH		 5900 root = debugfs_create_dir("delay_drop", dev->mdev->priv.dbg_root);
5901 dev->delay_drop.dir_debugfs = root;
fe248c3a 5902
09b0965e
GKH		 5903 debugfs_create_atomic_t("num_timeout_events", 0400, root,
5904 &dev->delay_drop.events_cnt);
5905 debugfs_create_atomic_t("num_rqs", 0400, root,
5906 &dev->delay_drop.rqs_cnt);
5907 debugfs_create_file("timeout", 0600, root, &dev->delay_drop,
5908 &fops_delay_drop_timeout);
03404e8a
MG		 5909}
5910
5911static void init_delay_drop(struct mlx5_ib_dev *dev)
5912{
5913 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5914 return;
5915
5916 mutex_init(&dev->delay_drop.lock);
5917 dev->delay_drop.dev = dev;
5918 dev->delay_drop.activate = false;
5919 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5920 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 5921 atomic_set(&dev->delay_drop.rqs_cnt, 0);
5922 atomic_set(&dev->delay_drop.events_cnt, 0);
5923
09b0965e 5924 delay_drop_debugfs_init(dev);
03404e8a
MG		 5925}
5926
32f69e4b
DJ		 5927static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5928 struct mlx5_ib_multiport_info *mpi)
5929{
5930 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5931 struct mlx5_ib_port *port = &ibdev->port[port_num];
5932 int comps;
5933 int err;
5934 int i;
5935
9dc4cfff
LR		 5936 lockdep_assert_held(&mlx5_ib_multiport_mutex);
5937
a9e546e7
PP		 5938 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5939
32f69e4b
DJ		 5940 spin_lock(&port->mp.mpi_lock);
5941 if (!mpi->ibdev) {
5942 spin_unlock(&port->mp.mpi_lock);
5943 return;
5944 }
df097a27 5945
32f69e4b
DJ		 5946 mpi->ibdev = NULL;
5947
5948 spin_unlock(&port->mp.mpi_lock);
23eaf3b5
LR		 5949 if (mpi->mdev_events.notifier_call)
5950 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
5951 mpi->mdev_events.notifier_call = NULL;
32f69e4b
DJ		 5952 mlx5_remove_netdev_notifier(ibdev, port_num);
5953 spin_lock(&port->mp.mpi_lock);
5954
5955 comps = mpi->mdev_refcnt;
5956 if (comps) {
5957 mpi->unaffiliate = true;
5958 init_completion(&mpi->unref_comp);
5959 spin_unlock(&port->mp.mpi_lock);
5960
5961 for (i = 0; i < comps; i++)
5962 wait_for_completion(&mpi->unref_comp);
5963
5964 spin_lock(&port->mp.mpi_lock);
5965 mpi->unaffiliate = false;
5966 }
5967
5968 port->mp.mpi = NULL;
5969
5970 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5971
5972 spin_unlock(&port->mp.mpi_lock);
5973
5974 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5975
5976 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5977 /* Log an error, still needed to cleanup the pointers and add
5978 * it back to the list.
5979 */
5980 if (err)
5981 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5982 port_num + 1);
5983
95579e78 5984 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
32f69e4b
DJ		 5985}
5986
32f69e4b
DJ		 5987static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5988 struct mlx5_ib_multiport_info *mpi)
5989{
5990 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5991 int err;
5992
9dc4cfff
LR		 5993 lockdep_assert_held(&mlx5_ib_multiport_mutex);
5994
32f69e4b
DJ		 5995 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5996 if (ibdev->port[port_num].mp.mpi) {
2577188e
QH		 5997 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
5998 port_num + 1);
32f69e4b
DJ		 5999 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
6000 return false;
6001 }
6002
6003 ibdev->port[port_num].mp.mpi = mpi;
6004 mpi->ibdev = ibdev;
df097a27 6005 mpi->mdev_events.notifier_call = NULL;
32f69e4b
DJ		 6006 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
6007
6008 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
6009 if (err)
6010 goto unbind;
6011
6012 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
6013 if (err)
6014 goto unbind;
6015
6016 err = mlx5_add_netdev_notifier(ibdev, port_num);
6017 if (err) {
6018 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
6019 port_num + 1);
6020 goto unbind;
6021 }
6022
df097a27
SM		 6023 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
6024 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
6025
73eb8f03 6026 mlx5_ib_init_cong_debugfs(ibdev, port_num);
a9e546e7 6027
32f69e4b
DJ		 6028 return true;
6029
6030unbind:
6031 mlx5_ib_unbind_slave_port(ibdev, mpi);
6032 return false;
6033}
6034
6035static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
6036{
6037 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6038 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
6039 port_num + 1);
6040 struct mlx5_ib_multiport_info *mpi;
6041 int err;
6042 int i;
6043
6044 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
6045 return 0;
6046
6047 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
6048 &dev->sys_image_guid);
6049 if (err)
6050 return err;
6051
6052 err = mlx5_nic_vport_enable_roce(dev->mdev);
6053 if (err)
6054 return err;
6055
6056 mutex_lock(&mlx5_ib_multiport_mutex);
6057 for (i = 0; i < dev->num_ports; i++) {
6058 bool bound = false;
6059
6060 /* build a stub multiport info struct for the native port. */
6061 if (i == port_num) {
6062 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6063 if (!mpi) {
6064 mutex_unlock(&mlx5_ib_multiport_mutex);
6065 mlx5_nic_vport_disable_roce(dev->mdev);
6066 return -ENOMEM;
6067 }
6068
6069 mpi->is_master = true;
6070 mpi->mdev = dev->mdev;
6071 mpi->sys_image_guid = dev->sys_image_guid;
6072 dev->port[i].mp.mpi = mpi;
6073 mpi->ibdev = dev;
6074 mpi = NULL;
6075 continue;
6076 }
6077
6078 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
6079 list) {
6080 if (dev->sys_image_guid == mpi->sys_image_guid &&
6081 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
6082 bound = mlx5_ib_bind_slave_port(dev, mpi);
6083 }
6084
6085 if (bound) {
c42260f1
VP		 6086 dev_dbg(mpi->mdev->device,
6087 "removing port from unaffiliated list.\n");
32f69e4b
DJ		 6088 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
6089 list_del(&mpi->list);
6090 break;
6091 }
6092 }
6093 if (!bound) {
6094 get_port_caps(dev, i + 1);
6095 mlx5_ib_dbg(dev, "no free port found for port %d\n",
6096 i + 1);
6097 }
6098 }
6099
6100 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
6101 mutex_unlock(&mlx5_ib_multiport_mutex);
6102 return err;
6103}
6104
6105static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
6106{
6107 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6108 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
6109 port_num + 1);
6110 int i;
6111
6112 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
6113 return;
6114
6115 mutex_lock(&mlx5_ib_multiport_mutex);
6116 for (i = 0; i < dev->num_ports; i++) {
6117 if (dev->port[i].mp.mpi) {
6118 /* Destroy the native port stub */
6119 if (i == port_num) {
6120 kfree(dev->port[i].mp.mpi);
6121 dev->port[i].mp.mpi = NULL;
6122 } else {
6123 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
6124 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
6125 }
6126 }
6127 }
6128
6129 mlx5_ib_dbg(dev, "removing from devlist\n");
6130 list_del(&dev->ib_dev_list);
6131 mutex_unlock(&mlx5_ib_multiport_mutex);
6132
6133 mlx5_nic_vport_disable_roce(dev->mdev);
6134}
6135
342ee59d
YH		 6136static int mmap_obj_cleanup(struct ib_uobject *uobject,
6137 enum rdma_remove_reason why,
6138 struct uverbs_attr_bundle *attrs)
7be76bef
YH		 6139{
6140 struct mlx5_user_mmap_entry *obj = uobject->object;
6141
6142 rdma_user_mmap_entry_remove(&obj->rdma_entry);
6143 return 0;
6144}
6145
342ee59d
YH		 6146static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c,
6147 struct mlx5_user_mmap_entry *entry,
6148 size_t length)
6149{
6150 return rdma_user_mmap_entry_insert_range(
6151 &c->ibucontext, &entry->rdma_entry, length,
6152 (MLX5_IB_MMAP_OFFSET_START << 16),
6153 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1));
6154}
6155
7be76bef
YH		 6156static struct mlx5_user_mmap_entry *
6157alloc_var_entry(struct mlx5_ib_ucontext *c)
6158{
6159 struct mlx5_user_mmap_entry *entry;
6160 struct mlx5_var_table *var_table;
6161 u32 page_idx;
6162 int err;
6163
6164 var_table = &to_mdev(c->ibucontext.device)->var_table;
6165 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
6166 if (!entry)
6167 return ERR_PTR(-ENOMEM);
6168
6169 mutex_lock(&var_table->bitmap_lock);
6170 page_idx = find_first_zero_bit(var_table->bitmap,
6171 var_table->num_var_hw_entries);
6172 if (page_idx >= var_table->num_var_hw_entries) {
6173 err = -ENOSPC;
6174 mutex_unlock(&var_table->bitmap_lock);
6175 goto end;
6176 }
6177
6178 set_bit(page_idx, var_table->bitmap);
6179 mutex_unlock(&var_table->bitmap_lock);
6180
6181 entry->address = var_table->hw_start_addr +
6182 (page_idx * var_table->stride_size);
6183 entry->page_idx = page_idx;
6184 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR;
6185
342ee59d
YH		 6186 err = mlx5_rdma_user_mmap_entry_insert(c, entry,
6187 var_table->stride_size);
7be76bef
YH		 6188 if (err)
6189 goto err_insert;
6190
6191 return entry;
6192
6193err_insert:
6194 mutex_lock(&var_table->bitmap_lock);
6195 clear_bit(page_idx, var_table->bitmap);
6196 mutex_unlock(&var_table->bitmap_lock);
6197end:
6198 kfree(entry);
6199 return ERR_PTR(err);
6200}
6201
6202static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)(
6203 struct uverbs_attr_bundle *attrs)
6204{
6205 struct ib_uobject *uobj = uverbs_attr_get_uobject(
6206 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
6207 struct mlx5_ib_ucontext *c;
6208 struct mlx5_user_mmap_entry *entry;
6209 u64 mmap_offset;
6210 u32 length;
6211 int err;
6212
6213 c = to_mucontext(ib_uverbs_get_ucontext(attrs));
6214 if (IS_ERR(c))
6215 return PTR_ERR(c);
6216
6217 entry = alloc_var_entry(c);
6218 if (IS_ERR(entry))
6219 return PTR_ERR(entry);
6220
6221 mmap_offset = mlx5_entry_to_mmap_offset(entry);
6222 length = entry->rdma_entry.npages * PAGE_SIZE;
6223 uobj->object = entry;
6224
6225 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
6226 &mmap_offset, sizeof(mmap_offset));
6227 if (err)
6228 goto err;
6229
6230 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
6231 &entry->page_idx, sizeof(entry->page_idx));
6232 if (err)
6233 goto err;
6234
6235 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
6236 &length, sizeof(length));
6237 if (err)
6238 goto err;
6239
6240 return 0;
6241
6242err:
6243 rdma_user_mmap_entry_remove(&entry->rdma_entry);
6244 return err;
6245}
6246
6247DECLARE_UVERBS_NAMED_METHOD(
6248 MLX5_IB_METHOD_VAR_OBJ_ALLOC,
6249 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE,
6250 MLX5_IB_OBJECT_VAR,
6251 UVERBS_ACCESS_NEW,
6252 UA_MANDATORY),
6253 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
6254 UVERBS_ATTR_TYPE(u32),
6255 UA_MANDATORY),
6256 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
6257 UVERBS_ATTR_TYPE(u32),
6258 UA_MANDATORY),
6259 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
6260 UVERBS_ATTR_TYPE(u64),
6261 UA_MANDATORY));
6262
6263DECLARE_UVERBS_NAMED_METHOD_DESTROY(
6264 MLX5_IB_METHOD_VAR_OBJ_DESTROY,
6265 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE,
6266 MLX5_IB_OBJECT_VAR,
6267 UVERBS_ACCESS_DESTROY,
6268 UA_MANDATORY));
6269
6270DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR,
342ee59d 6271 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
7be76bef
YH		 6272 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC),
6273 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY));
6274
6275static bool var_is_supported(struct ib_device *device)
6276{
6277 struct mlx5_ib_dev *dev = to_mdev(device);
6278
6279 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
6280 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q);
6281}
6282
342ee59d
YH		 6283static struct mlx5_user_mmap_entry *
6284alloc_uar_entry(struct mlx5_ib_ucontext *c,
6285 enum mlx5_ib_uapi_uar_alloc_type alloc_type)
6286{
6287 struct mlx5_user_mmap_entry *entry;
6288 struct mlx5_ib_dev *dev;
6289 u32 uar_index;
6290 int err;
6291
6292 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
6293 if (!entry)
6294 return ERR_PTR(-ENOMEM);
6295
6296 dev = to_mdev(c->ibucontext.device);
6297 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
6298 if (err)
6299 goto end;
6300
6301 entry->page_idx = uar_index;
6302 entry->address = uar_index2paddress(dev, uar_index);
6303 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
6304 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC;
6305 else
6306 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC;
6307
6308 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE);
6309 if (err)
6310 goto err_insert;
6311
6312 return entry;
6313
6314err_insert:
6315 mlx5_cmd_free_uar(dev->mdev, uar_index);
6316end:
6317 kfree(entry);
6318 return ERR_PTR(err);
6319}
6320
6321static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)(
6322 struct uverbs_attr_bundle *attrs)
6323{
6324 struct ib_uobject *uobj = uverbs_attr_get_uobject(
6325 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
6326 enum mlx5_ib_uapi_uar_alloc_type alloc_type;
6327 struct mlx5_ib_ucontext *c;
6328 struct mlx5_user_mmap_entry *entry;
6329 u64 mmap_offset;
6330 u32 length;
6331 int err;
6332
6333 c = to_mucontext(ib_uverbs_get_ucontext(attrs));
6334 if (IS_ERR(c))
6335 return PTR_ERR(c);
6336
6337 err = uverbs_get_const(&alloc_type, attrs,
6338 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE);
6339 if (err)
6340 return err;
6341
6342 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF &&
6343 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC)
6344 return -EOPNOTSUPP;
6345
6346 if (!to_mdev(c->ibucontext.device)->wc_support &&
6347 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
6348 return -EOPNOTSUPP;
6349
6350 entry = alloc_uar_entry(c, alloc_type);
6351 if (IS_ERR(entry))
6352 return PTR_ERR(entry);
6353
6354 mmap_offset = mlx5_entry_to_mmap_offset(entry);
6355 length = entry->rdma_entry.npages * PAGE_SIZE;
6356 uobj->object = entry;
6357
6358 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
6359 &mmap_offset, sizeof(mmap_offset));
6360 if (err)
6361 goto err;
6362
6363 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
6364 &entry->page_idx, sizeof(entry->page_idx));
6365 if (err)
6366 goto err;
6367
6368 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
6369 &length, sizeof(length));
6370 if (err)
6371 goto err;
6372
6373 return 0;
6374
6375err:
6376 rdma_user_mmap_entry_remove(&entry->rdma_entry);
6377 return err;
6378}
6379
6380DECLARE_UVERBS_NAMED_METHOD(
6381 MLX5_IB_METHOD_UAR_OBJ_ALLOC,
6382 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE,
6383 MLX5_IB_OBJECT_UAR,
6384 UVERBS_ACCESS_NEW,
6385 UA_MANDATORY),
6386 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE,
6387 enum mlx5_ib_uapi_uar_alloc_type,
6388 UA_MANDATORY),
6389 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
6390 UVERBS_ATTR_TYPE(u32),
6391 UA_MANDATORY),
6392 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
6393 UVERBS_ATTR_TYPE(u32),
6394 UA_MANDATORY),
6395 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
6396 UVERBS_ATTR_TYPE(u64),
6397 UA_MANDATORY));
6398
6399DECLARE_UVERBS_NAMED_METHOD_DESTROY(
6400 MLX5_IB_METHOD_UAR_OBJ_DESTROY,
6401 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE,
6402 MLX5_IB_OBJECT_UAR,
6403 UVERBS_ACCESS_DESTROY,
6404 UA_MANDATORY));
6405
6406DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR,
6407 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
6408 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC),
6409 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY));
6410
9a119cd5
JG		 6411ADD_UVERBS_ATTRIBUTES_SIMPLE(
6412 mlx5_ib_dm,
6413 UVERBS_OBJECT_DM,
6414 UVERBS_METHOD_DM_ALLOC,
6415 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
6416 UVERBS_ATTR_TYPE(u64),
83bb4442 6417 UA_MANDATORY),
9a119cd5
JG		 6418 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
6419 UVERBS_ATTR_TYPE(u16),
3b113a1e
AL		 6420 UA_OPTIONAL),
6421 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
6422 enum mlx5_ib_uapi_dm_type,
6423 UA_OPTIONAL));
9a119cd5
JG		 6424
6425ADD_UVERBS_ATTRIBUTES_SIMPLE(
6426 mlx5_ib_flow_action,
6427 UVERBS_OBJECT_FLOW_ACTION,
6428 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
bccd0622
JG		 6429 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
6430 enum mlx5_ib_uapi_flow_action_flags));
c6475a0b 6431
0cbf432d 6432static const struct uapi_definition mlx5_ib_defs[] = {
36e235c8 6433 UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
0cbf432d 6434 UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
30f2fe40 6435 UAPI_DEF_CHAIN(mlx5_ib_qos_defs),
8c84660b 6436
0cbf432d
JG		 6437 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION,
6438 &mlx5_ib_flow_action),
6439 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm),
7be76bef
YH		 6440 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR,
6441 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)),
342ee59d 6442 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR),
0cbf432d
JG		 6443 {}
6444};
8c84660b 6445
1a1e03dc
RS		 6446static int mlx5_ib_read_counters(struct ib_counters *counters,
6447 struct ib_counters_read_attr *read_attr,
6448 struct uverbs_attr_bundle *attrs)
6449{
6450 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
6451 struct mlx5_read_counters_attr mread_attr = {};
6452 struct mlx5_ib_flow_counters_desc *desc;
6453 int ret, i;
6454
6455 mutex_lock(&mcounters->mcntrs_mutex);
6456 if (mcounters->cntrs_max_index > read_attr->ncounters) {
6457 ret = -EINVAL;
6458 goto err_bound;
6459 }
6460
6461 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
6462 GFP_KERNEL);
6463 if (!mread_attr.out) {
6464 ret = -ENOMEM;
6465 goto err_bound;
6466 }
6467
6468 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
6469 mread_attr.flags = read_attr->flags;
6470 ret = mcounters->read_counters(counters->device, &mread_attr);
6471 if (ret)
6472 goto err_read;
6473
6474 /* do the pass over the counters data array to assign according to the
6475 * descriptions and indexing pairs
6476 */
6477 desc = mcounters->counters_data;
6478 for (i = 0; i < mcounters->ncounters; i++)
6479 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
6480
6481err_read:
6482 kfree(mread_attr.out);
6483err_bound:
6484 mutex_unlock(&mcounters->mcntrs_mutex);
6485 return ret;
6486}
6487
b29e2a13
RS		 6488static int mlx5_ib_destroy_counters(struct ib_counters *counters)
6489{
6490 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
6491
3b3233fb
RS		 6492 counters_clear_description(counters);
6493 if (mcounters->hw_cntrs_hndl)
6494 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
6495 mcounters->hw_cntrs_hndl);
6496
b29e2a13
RS		 6497 kfree(mcounters);
6498
6499 return 0;
6500}
6501
6502static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
6503 struct uverbs_attr_bundle *attrs)
6504{
6505 struct mlx5_ib_mcounters *mcounters;
6506
6507 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
6508 if (!mcounters)
6509 return ERR_PTR(-ENOMEM);
6510
3b3233fb
RS		 6511 mutex_init(&mcounters->mcntrs_mutex);
6512
b29e2a13
RS		 6513 return &mcounters->ibcntrs;
6514}
6515
fb652d32 6516static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
e126ba97 6517{
32f69e4b 6518 mlx5_ib_cleanup_multiport_master(dev);
806b101b 6519 WARN_ON(!xa_empty(&dev->odp_mkeys));
806b101b 6520 cleanup_srcu_struct(&dev->odp_srcu);
4056b12e 6521
50211ec9 6522 WARN_ON(!xa_empty(&dev->sig_mrs));
4056b12e 6523 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
16c1975f
MB		 6524}
6525
fb652d32 6526static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6527{
6528 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 6529 int err;
32f69e4b 6530 int i;
e126ba97 6531
32f69e4b
DJ		 6532 for (i = 0; i < dev->num_ports; i++) {
6533 spin_lock_init(&dev->port[i].mp.mpi_lock);
95579e78 6534 rwlock_init(&dev->port[i].roce.netdev_lock);
d3b5cc1c
MB		 6535 dev->port[i].roce.dev = dev;
6536 dev->port[i].roce.native_port_num = i + 1;
6537 dev->port[i].roce.last_port_state = IB_PORT_DOWN;
32f69e4b
DJ		 6538 }
6539
00815752
MS		 6540 mlx5_ib_internal_fill_odp_caps(dev);
6541
32f69e4b 6542 err = mlx5_ib_init_multiport_master(dev);
e126ba97 6543 if (err)
da796ccb 6544 return err;
e126ba97 6545
a989ea01
MB		 6546 err = set_has_smi_cap(dev);
6547 if (err)
6548 return err;
e126ba97 6549
32f69e4b 6550 if (!mlx5_core_mp_enabled(mdev)) {
32f69e4b
DJ		 6551 for (i = 1; i <= dev->num_ports; i++) {
6552 err = get_port_caps(dev, i);
6553 if (err)
6554 break;
6555 }
6556 } else {
6557 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
6558 }
6559 if (err)
6560 goto err_mp;
6561
1b5daf11
MD		 6562 if (mlx5_use_mad_ifc(dev))
6563 get_ext_port_caps(dev);
e126ba97 6564
e126ba97 6565 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 6566 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
508562d6 6567 dev->ib_dev.phys_port_cnt = dev->num_ports;
f2f3df55 6568 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev);
c42260f1 6569 dev->ib_dev.dev.parent = mdev->device;
e126ba97 6570
3cc297db
MB		 6571 mutex_init(&dev->cap_mask_mutex);
6572 INIT_LIST_HEAD(&dev->qp_list);
6573 spin_lock_init(&dev->reset_flow_resource_lock);
806b101b 6574 xa_init(&dev->odp_mkeys);
50211ec9 6575 xa_init(&dev->sig_mrs);
f743ff3b 6576 atomic_set(&dev->mkey_var, 0);
3cc297db 6577
3b113a1e
AL		 6578 spin_lock_init(&dev->dm.lock);
6579 dev->dm.dev = mdev;
24da0016 6580
806b101b
JG		 6581 err = init_srcu_struct(&dev->odp_srcu);
6582 if (err)
6583 goto err_mp;
3cc297db 6584
16c1975f 6585 return 0;
25c13324 6586
32f69e4b
DJ		 6587err_mp:
6588 mlx5_ib_cleanup_multiport_master(dev);
16c1975f 6589
16c1975f
MB		 6590 return -ENOMEM;
6591}
6592
9a4ca38d
MB		 6593static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
6594{
6595 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
6596
6597 if (!dev->flow_db)
6598 return -ENOMEM;
6599
6600 mutex_init(&dev->flow_db->lock);
6601
6602 return 0;
6603}
6604
6605static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
6606{
6607 kfree(dev->flow_db);
6608}
6609
96458233 6610static const struct ib_device_ops mlx5_ib_dev_ops = {
7a154142 6611 .owner = THIS_MODULE,
b9560a41 6612 .driver_id = RDMA_DRIVER_MLX5,
72c6ec18 6613 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
b9560a41 6614
96458233
KH		 6615 .add_gid = mlx5_ib_add_gid,
6616 .alloc_mr = mlx5_ib_alloc_mr,
6c984472 6617 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
96458233
KH		 6618 .alloc_pd = mlx5_ib_alloc_pd,
6619 .alloc_ucontext = mlx5_ib_alloc_ucontext,
6620 .attach_mcast = mlx5_ib_mcg_attach,
6621 .check_mr_status = mlx5_ib_check_mr_status,
6622 .create_ah = mlx5_ib_create_ah,
6623 .create_counters = mlx5_ib_create_counters,
6624 .create_cq = mlx5_ib_create_cq,
6625 .create_flow = mlx5_ib_create_flow,
6626 .create_qp = mlx5_ib_create_qp,
6627 .create_srq = mlx5_ib_create_srq,
6628 .dealloc_pd = mlx5_ib_dealloc_pd,
6629 .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
6630 .del_gid = mlx5_ib_del_gid,
6631 .dereg_mr = mlx5_ib_dereg_mr,
6632 .destroy_ah = mlx5_ib_destroy_ah,
6633 .destroy_counters = mlx5_ib_destroy_counters,
6634 .destroy_cq = mlx5_ib_destroy_cq,
6635 .destroy_flow = mlx5_ib_destroy_flow,
6636 .destroy_flow_action = mlx5_ib_destroy_flow_action,
6637 .destroy_qp = mlx5_ib_destroy_qp,
6638 .destroy_srq = mlx5_ib_destroy_srq,
6639 .detach_mcast = mlx5_ib_mcg_detach,
6640 .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
6641 .drain_rq = mlx5_ib_drain_rq,
6642 .drain_sq = mlx5_ib_drain_sq,
11f552e2 6643 .enable_driver = mlx5_ib_enable_driver,
e1b95ae0 6644 .fill_res_entry = mlx5_ib_fill_res_entry,
4061ff7a 6645 .fill_stat_entry = mlx5_ib_fill_stat_entry,
96458233
KH		 6646 .get_dev_fw_str = get_dev_fw_str,
6647 .get_dma_mr = mlx5_ib_get_dma_mr,
6648 .get_link_layer = mlx5_ib_port_link_layer,
6649 .map_mr_sg = mlx5_ib_map_mr_sg,
6c984472 6650 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi,
96458233 6651 .mmap = mlx5_ib_mmap,
dc2316eb 6652 .mmap_free = mlx5_ib_mmap_free,
96458233
KH		 6653 .modify_cq = mlx5_ib_modify_cq,
6654 .modify_device = mlx5_ib_modify_device,
6655 .modify_port = mlx5_ib_modify_port,
6656 .modify_qp = mlx5_ib_modify_qp,
6657 .modify_srq = mlx5_ib_modify_srq,
6658 .poll_cq = mlx5_ib_poll_cq,
6659 .post_recv = mlx5_ib_post_recv,
6660 .post_send = mlx5_ib_post_send,
6661 .post_srq_recv = mlx5_ib_post_srq_recv,
6662 .process_mad = mlx5_ib_process_mad,
6663 .query_ah = mlx5_ib_query_ah,
6664 .query_device = mlx5_ib_query_device,
6665 .query_gid = mlx5_ib_query_gid,
6666 .query_pkey = mlx5_ib_query_pkey,
6667 .query_qp = mlx5_ib_query_qp,
6668 .query_srq = mlx5_ib_query_srq,
6669 .read_counters = mlx5_ib_read_counters,
6670 .reg_user_mr = mlx5_ib_reg_user_mr,
6671 .req_notify_cq = mlx5_ib_arm_cq,
6672 .rereg_user_mr = mlx5_ib_rereg_user_mr,
6673 .resize_cq = mlx5_ib_resize_cq,
d3456914
LR		 6674
6675 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
e39afe3d 6676 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
21a428a0 6677 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
68e326de 6678 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
a2a074ef 6679 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
96458233
KH		 6680};
6681
6682static const struct ib_device_ops mlx5_ib_dev_flow_ipsec_ops = {
6683 .create_flow_action_esp = mlx5_ib_create_flow_action_esp,
6684 .modify_flow_action_esp = mlx5_ib_modify_flow_action_esp,
6685};
6686
6687static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
6688 .rdma_netdev_get_params = mlx5_ib_rn_get_params,
6689};
6690
6691static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
6692 .get_vf_config = mlx5_ib_get_vf_config,
9c0015ef 6693 .get_vf_guid = mlx5_ib_get_vf_guid,
96458233
KH		 6694 .get_vf_stats = mlx5_ib_get_vf_stats,
6695 .set_vf_guid = mlx5_ib_set_vf_guid,
6696 .set_vf_link_state = mlx5_ib_set_vf_link_state,
6697};
6698
6699static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
6700 .alloc_mw = mlx5_ib_alloc_mw,
6701 .dealloc_mw = mlx5_ib_dealloc_mw,
6702};
6703
6704static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
6705 .alloc_xrcd = mlx5_ib_alloc_xrcd,
6706 .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
6707};
6708
6709static const struct ib_device_ops mlx5_ib_dev_dm_ops = {
6710 .alloc_dm = mlx5_ib_alloc_dm,
6711 .dealloc_dm = mlx5_ib_dealloc_dm,
6712 .reg_dm_mr = mlx5_ib_reg_dm_mr,
6713};
6714
f164be8c
YH		 6715static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev)
6716{
6717 struct mlx5_core_dev *mdev = dev->mdev;
6718 struct mlx5_var_table *var_table = &dev->var_table;
6719 u8 log_doorbell_bar_size;
6720 u8 log_doorbell_stride;
6721 u64 bar_size;
6722
6723 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
6724 log_doorbell_bar_size);
6725 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
6726 log_doorbell_stride);
6727 var_table->hw_start_addr = dev->mdev->bar_addr +
6728 MLX5_CAP64_DEV_VDPA_EMULATION(mdev,
6729 doorbell_bar_offset);
6730 bar_size = (1ULL << log_doorbell_bar_size) * 4096;
6731 var_table->stride_size = 1ULL << log_doorbell_stride;
91b74bf5
AL		 6732 var_table->num_var_hw_entries = div_u64(bar_size,
6733 var_table->stride_size);
f164be8c
YH		 6734 mutex_init(&var_table->bitmap_lock);
6735 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries,
6736 GFP_KERNEL);
6737 return (var_table->bitmap) ? 0 : -ENOMEM;
6738}
6739
6740static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev)
6741{
6742 bitmap_free(dev->var_table.bitmap);
6743}
6744
fb652d32 6745static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6746{
6747 struct mlx5_core_dev *mdev = dev->mdev;
16c1975f
MB		 6748 int err;
6749
e126ba97
EC		 6750 dev->ib_dev.uverbs_cmd_mask =
6751 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
6752 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
6753 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
6754 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
6755 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 6756 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
6757 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 6758 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 6759 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 6760 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
6761 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
6762 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
6763 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
6764 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
6765 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
6766 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
6767 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
6768 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
6769 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
6770 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
6771 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
6772 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
6773 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
6774 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
6775 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
6776 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 6777 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 6778 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
6779 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349 6780 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
b0e9df6d 6781 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
96458233
KH		 6782 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ) |
6783 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
6784 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
6785
f6a8a19b
DD		 6786 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
6787 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
96458233
KH		 6788 ib_set_device_ops(&dev->ib_dev,
6789 &mlx5_ib_dev_ipoib_enhanced_ops);
8e959601 6790
96458233
KH		 6791 if (mlx5_core_is_pf(mdev))
6792 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
7c2344c3 6793
6e8484c5
MG		 6794 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
6795
d2370e0a 6796 if (MLX5_CAP_GEN(mdev, imaicl)) {
d2370e0a
MB		 6797 dev->ib_dev.uverbs_cmd_mask |=
6798 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
6799 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
96458233 6800 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
d2370e0a
MB		 6801 }
6802
938fe83c 6803 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 6804 dev->ib_dev.uverbs_cmd_mask |=
6805 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
6806 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
96458233 6807 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
e126ba97
EC		 6808 }
6809
25c13324
AL		 6810 if (MLX5_CAP_DEV_MEM(mdev, memic) ||
6811 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
6812 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
96458233 6813 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
24da0016 6814
dfb631a1 6815 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
96458233
KH		 6816 MLX5_ACCEL_IPSEC_CAP_DEVICE)
6817 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_flow_ipsec_ops);
96458233 6818 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
81e30880 6819
36e235c8
JG		 6820 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
6821 dev->ib_dev.driver_def = mlx5_ib_defs;
81e30880 6822
e126ba97
EC		 6823 err = init_node_data(dev);
6824 if (err)
16c1975f 6825 return err;
e126ba97 6826
c8b89924 6827 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
e7996a9a
JG		 6828 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
6829 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
a560f1d9 6830 mutex_init(&dev->lb.mutex);
c8b89924 6831
f164be8c
YH		 6832 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
6833 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
6834 err = mlx5_ib_init_var_table(dev);
6835 if (err)
6836 return err;
6837 }
6838
96e2fd73
LR		 6839 dev->ib_dev.use_cq_dim = true;
6840
16c1975f
MB		 6841 return 0;
6842}
6843
96458233
KH		 6844static const struct ib_device_ops mlx5_ib_dev_port_ops = {
6845 .get_port_immutable = mlx5_port_immutable,
6846 .query_port = mlx5_ib_query_port,
6847};
6848
8e6efa3a
MB		 6849static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
6850{
96458233 6851 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
8e6efa3a
MB		 6852 return 0;
6853}
6854
96458233
KH		 6855static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
6856 .get_port_immutable = mlx5_port_rep_immutable,
6857 .query_port = mlx5_ib_rep_query_port,
6858};
6859
b5a498ba 6860static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev)
8e6efa3a 6861{
96458233 6862 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
8e6efa3a
MB		 6863 return 0;
6864}
6865
96458233
KH		 6866static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
6867 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
6868 .create_wq = mlx5_ib_create_wq,
6869 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
6870 .destroy_wq = mlx5_ib_destroy_wq,
6871 .get_netdev = mlx5_ib_get_netdev,
6872 .modify_wq = mlx5_ib_modify_wq,
6873};
6874
e3f1ed1f 6875static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
8e6efa3a 6876{
e3f1ed1f 6877 u8 port_num;
8e6efa3a 6878
8e6efa3a
MB		 6879 dev->ib_dev.uverbs_ex_cmd_mask |=
6880 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
6881 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
6882 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
6883 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
6884 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
96458233 6885 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
8e6efa3a 6886
e3f1ed1f
LR		 6887 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6888
26628e2d 6889 /* Register only for native ports */
8e6efa3a
MB		 6890 return mlx5_add_netdev_notifier(dev, port_num);
6891}
6892
6893static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
6894{
6895 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6896
6897 mlx5_remove_netdev_notifier(dev, port_num);
6898}
6899
b5a498ba 6900static int mlx5_ib_stage_raw_eth_roce_init(struct mlx5_ib_dev *dev)
8e6efa3a
MB		 6901{
6902 struct mlx5_core_dev *mdev = dev->mdev;
6903 enum rdma_link_layer ll;
6904 int port_type_cap;
6905 int err = 0;
8e6efa3a 6906
8e6efa3a
MB		 6907 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6908 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6909
6910 if (ll == IB_LINK_LAYER_ETHERNET)
e3f1ed1f 6911 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 6912
6913 return err;
6914}
6915
b5a498ba 6916static void mlx5_ib_stage_raw_eth_roce_cleanup(struct mlx5_ib_dev *dev)
8e6efa3a
MB		 6917{
6918 mlx5_ib_stage_common_roce_cleanup(dev);
6919}
6920
16c1975f
MB		 6921static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
6922{
6923 struct mlx5_core_dev *mdev = dev->mdev;
6924 enum rdma_link_layer ll;
6925 int port_type_cap;
6926 int err;
6927
6928 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6929 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6930
fc24fc5e 6931 if (ll == IB_LINK_LAYER_ETHERNET) {
e3f1ed1f 6932 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 6933 if (err)
6934 return err;
7fd8aefb 6935
e3f1ed1f 6936 err = mlx5_enable_eth(dev);
fc24fc5e 6937 if (err)
8e6efa3a 6938 goto cleanup;
fc24fc5e
AS		 6939 }
6940
16c1975f 6941 return 0;
8e6efa3a
MB		 6942cleanup:
6943 mlx5_ib_stage_common_roce_cleanup(dev);
6944
6945 return err;
16c1975f 6946}
e126ba97 6947
16c1975f
MB		 6948static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
6949{
6950 struct mlx5_core_dev *mdev = dev->mdev;
6951 enum rdma_link_layer ll;
6952 int port_type_cap;
e126ba97 6953
16c1975f
MB		 6954 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6955 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6956
6957 if (ll == IB_LINK_LAYER_ETHERNET) {
6958 mlx5_disable_eth(dev);
8e6efa3a 6959 mlx5_ib_stage_common_roce_cleanup(dev);
45bded2c 6960 }
16c1975f 6961}
6aec21f6 6962
fb652d32 6963static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6964{
6965 return create_dev_resources(&dev->devr);
6966}
6967
fb652d32 6968static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6969{
6970 destroy_dev_resources(&dev->devr);
6971}
6972
6973static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
6974{
6975 return mlx5_ib_odp_init_one(dev);
6976}
4a2da0b8 6977
f3ffed0c 6978static void mlx5_ib_stage_odp_cleanup(struct mlx5_ib_dev *dev)
d5d284b8
SM		 6979{
6980 mlx5_ib_odp_cleanup_one(dev);
6981}
6982
96458233
KH		 6983static const struct ib_device_ops mlx5_ib_dev_hw_stats_ops = {
6984 .alloc_hw_stats = mlx5_ib_alloc_hw_stats,
6985 .get_hw_stats = mlx5_ib_get_hw_stats,
45842fc6
MZ		 6986 .counter_bind_qp = mlx5_ib_counter_bind_qp,
6987 .counter_unbind_qp = mlx5_ib_counter_unbind_qp,
6988 .counter_dealloc = mlx5_ib_counter_dealloc,
18d422ce
MZ		 6989 .counter_alloc_stats = mlx5_ib_counter_alloc_stats,
6990 .counter_update_stats = mlx5_ib_counter_update_stats,
96458233
KH		 6991};
6992
fb652d32 6993static int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
16c1975f 6994{
5e1e7612 6995 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
96458233 6996 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_hw_stats_ops);
5e1e7612
MB		 6997
6998 return mlx5_ib_alloc_counters(dev);
6999 }
16c1975f
MB		 7000
7001 return 0;
7002}
7003
fb652d32 7004static void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 7005{
7006 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
7007 mlx5_ib_dealloc_counters(dev);
7008}
7009
7010static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
7011{
73eb8f03
GKH		 7012 mlx5_ib_init_cong_debugfs(dev,
7013 mlx5_core_native_port_num(dev->mdev) - 1);
7014 return 0;
16c1975f
MB		 7015}
7016
7017static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
7018{
a9e546e7
PP		 7019 mlx5_ib_cleanup_cong_debugfs(dev,
7020 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 7021}
7022
7023static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
7024{
5fe9dec0 7025 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
444261ca 7026 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
16c1975f
MB		 7027}
7028
7029static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
7030{
7031 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
7032}
7033
fb652d32 7034static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 7035{
7036 int err;
5fe9dec0
EC		 7037
7038 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
7039 if (err)
16c1975f 7040 return err;
5fe9dec0
EC		 7041
7042 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
7043 if (err)
16c1975f 7044 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5fe9dec0 7045
16c1975f
MB		 7046 return err;
7047}
0837e86a 7048
fb652d32 7049static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 7050{
7051 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
7052 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
7053}
e126ba97 7054
fb652d32 7055static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
16c1975f 7056{
e349f858
JG		 7057 const char *name;
7058
508a523f 7059 rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group);
7c34ec19 7060 if (!mlx5_lag_is_roce(dev->mdev))
e349f858
JG		 7061 name = "mlx5_%d";
7062 else
7063 name = "mlx5_bond_%d";
ea4baf7f 7064 return ib_register_device(&dev->ib_dev, name);
16c1975f
MB		 7065}
7066
fb652d32 7067static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
16c1975f 7068{
42cea83f 7069 destroy_umrc_res(dev);
16c1975f
MB		 7070}
7071
fb652d32 7072static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
16c1975f 7073{
42cea83f 7074 ib_unregister_device(&dev->ib_dev);
16c1975f
MB		 7075}
7076
fb652d32 7077static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
16c1975f 7078{
42cea83f 7079 return create_umr_res(dev);
16c1975f
MB		 7080}
7081
7082static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
7083{
03404e8a
MG		 7084 init_delay_drop(dev);
7085
16c1975f
MB		 7086 return 0;
7087}
7088
7089static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
7090{
7091 cancel_delay_drop(dev);
7092}
7093
df097a27
SM		 7094static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
7095{
7096 dev->mdev_events.notifier_call = mlx5_ib_event;
7097 mlx5_notifier_register(dev->mdev, &dev->mdev_events);
7098 return 0;
7099}
7100
7101static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
7102{
7103 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
7104}
7105
81773ce5
LR		 7106static int mlx5_ib_stage_devx_init(struct mlx5_ib_dev *dev)
7107{
7108 int uid;
7109
fb98153b 7110 uid = mlx5_ib_devx_create(dev, false);
e337dd53 7111 if (uid > 0) {
81773ce5 7112 dev->devx_whitelist_uid = uid;
e337dd53
YH		 7113 mlx5_ib_devx_init_event_table(dev);
7114 }
81773ce5
LR		 7115
7116 return 0;
7117}
7118static void mlx5_ib_stage_devx_cleanup(struct mlx5_ib_dev *dev)
7119{
e337dd53
YH		 7120 if (dev->devx_whitelist_uid) {
7121 mlx5_ib_devx_cleanup_event_table(dev);
81773ce5 7122 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid);
e337dd53 7123 }
81773ce5
LR		 7124}
7125
11f552e2
MG		 7126int mlx5_ib_enable_driver(struct ib_device *dev)
7127{
7128 struct mlx5_ib_dev *mdev = to_mdev(dev);
7129 int ret;
7130
7131 ret = mlx5_ib_test_wc(mdev);
7132 mlx5_ib_dbg(mdev, "Write-Combining %s",
7133 mdev->wc_support ? "supported" : "not supported");
7134
7135 return ret;
7136}
7137
b5ca15ad
MB		 7138void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
7139 const struct mlx5_ib_profile *profile,
7140 int stage)
16c1975f 7141{
4cca96a8
PP		 7142 dev->ib_active = false;
7143
16c1975f
MB		 7144 /* Number of stages to cleanup */
7145 while (stage) {
7146 stage--;
7147 if (profile->stage[stage].cleanup)
7148 profile->stage[stage].cleanup(dev);
7149 }
4a6dc855 7150
da796ccb 7151 kfree(dev->port);
4a6dc855 7152 ib_dealloc_device(&dev->ib_dev);
16c1975f 7153}
e126ba97 7154
b5ca15ad
MB		 7155void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
7156 const struct mlx5_ib_profile *profile)
16c1975f 7157{
16c1975f
MB		 7158 int err;
7159 int i;
5fe9dec0 7160
16c1975f
MB		 7161 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
7162 if (profile->stage[i].init) {
7163 err = profile->stage[i].init(dev);
7164 if (err)
7165 goto err_out;
7166 }
7167 }
0837e86a 7168
16c1975f
MB		 7169 dev->profile = profile;
7170 dev->ib_active = true;
6aec21f6 7171
16c1975f 7172 return dev;
e126ba97 7173
16c1975f
MB		 7174err_out:
7175 __mlx5_ib_remove(dev, profile, i);
fc24fc5e 7176
16c1975f
MB		 7177 return NULL;
7178}
0837e86a 7179
16c1975f
MB		 7180static const struct mlx5_ib_profile pf_profile = {
7181 STAGE_CREATE(MLX5_IB_STAGE_INIT,
7182 mlx5_ib_stage_init_init,
7183 mlx5_ib_stage_init_cleanup),
9a4ca38d
MB		 7184 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
7185 mlx5_ib_stage_flow_db_init,
7186 mlx5_ib_stage_flow_db_cleanup),
16c1975f
MB		 7187 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
7188 mlx5_ib_stage_caps_init,
f164be8c 7189 mlx5_ib_stage_caps_cleanup),
8e6efa3a
MB		 7190 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
7191 mlx5_ib_stage_non_default_cb,
7192 NULL),
16c1975f
MB		 7193 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
7194 mlx5_ib_stage_roce_init,
7195 mlx5_ib_stage_roce_cleanup),
333fbaa0
LR		 7196 STAGE_CREATE(MLX5_IB_STAGE_QP,
7197 mlx5_init_qp_table,
7198 mlx5_cleanup_qp_table),
f3da6577
LR		 7199 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
7200 mlx5_init_srq_table,
7201 mlx5_cleanup_srq_table),
16c1975f
MB		 7202 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
7203 mlx5_ib_stage_dev_res_init,
7204 mlx5_ib_stage_dev_res_cleanup),
df097a27
SM		 7205 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
7206 mlx5_ib_stage_dev_notifier_init,
7207 mlx5_ib_stage_dev_notifier_cleanup),
16c1975f
MB		 7208 STAGE_CREATE(MLX5_IB_STAGE_ODP,
7209 mlx5_ib_stage_odp_init,
d5d284b8 7210 mlx5_ib_stage_odp_cleanup),
16c1975f
MB		 7211 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
7212 mlx5_ib_stage_counters_init,
7213 mlx5_ib_stage_counters_cleanup),
7214 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
7215 mlx5_ib_stage_cong_debugfs_init,
7216 mlx5_ib_stage_cong_debugfs_cleanup),
7217 STAGE_CREATE(MLX5_IB_STAGE_UAR,
7218 mlx5_ib_stage_uar_init,
7219 mlx5_ib_stage_uar_cleanup),
7220 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
7221 mlx5_ib_stage_bfrag_init,
7222 mlx5_ib_stage_bfrag_cleanup),
42cea83f
MB		 7223 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
7224 NULL,
7225 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
81773ce5
LR		 7226 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
7227 mlx5_ib_stage_devx_init,
7228 mlx5_ib_stage_devx_cleanup),
16c1975f
MB		 7229 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
7230 mlx5_ib_stage_ib_reg_init,
7231 mlx5_ib_stage_ib_reg_cleanup),
42cea83f
MB		 7232 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
7233 mlx5_ib_stage_post_ib_reg_umr_init,
7234 NULL),
16c1975f
MB		 7235 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
7236 mlx5_ib_stage_delay_drop_init,
7237 mlx5_ib_stage_delay_drop_cleanup),
16c1975f 7238};
e126ba97 7239
b5a498ba 7240const struct mlx5_ib_profile raw_eth_profile = {
b5ca15ad
MB		 7241 STAGE_CREATE(MLX5_IB_STAGE_INIT,
7242 mlx5_ib_stage_init_init,
7243 mlx5_ib_stage_init_cleanup),
7244 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
7245 mlx5_ib_stage_flow_db_init,
7246 mlx5_ib_stage_flow_db_cleanup),
7247 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
7248 mlx5_ib_stage_caps_init,
f164be8c 7249 mlx5_ib_stage_caps_cleanup),
b5ca15ad 7250 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
b5a498ba 7251 mlx5_ib_stage_raw_eth_non_default_cb,
b5ca15ad
MB		 7252 NULL),
7253 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
b5a498ba
MG		 7254 mlx5_ib_stage_raw_eth_roce_init,
7255 mlx5_ib_stage_raw_eth_roce_cleanup),
333fbaa0
LR		 7256 STAGE_CREATE(MLX5_IB_STAGE_QP,
7257 mlx5_init_qp_table,
7258 mlx5_cleanup_qp_table),
f3da6577
LR		 7259 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
7260 mlx5_init_srq_table,
7261 mlx5_cleanup_srq_table),
b5ca15ad
MB		 7262 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
7263 mlx5_ib_stage_dev_res_init,
7264 mlx5_ib_stage_dev_res_cleanup),
df097a27
SM		 7265 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
7266 mlx5_ib_stage_dev_notifier_init,
7267 mlx5_ib_stage_dev_notifier_cleanup),
b5ca15ad
MB		 7268 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
7269 mlx5_ib_stage_counters_init,
7270 mlx5_ib_stage_counters_cleanup),
79db784e
PP		 7271 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
7272 mlx5_ib_stage_cong_debugfs_init,
7273 mlx5_ib_stage_cong_debugfs_cleanup),
b5ca15ad
MB		 7274 STAGE_CREATE(MLX5_IB_STAGE_UAR,
7275 mlx5_ib_stage_uar_init,
7276 mlx5_ib_stage_uar_cleanup),
7277 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
7278 mlx5_ib_stage_bfrag_init,
7279 mlx5_ib_stage_bfrag_cleanup),
03fe2deb
DM		 7280 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
7281 NULL,
7282 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
7f575103
MB		 7283 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
7284 mlx5_ib_stage_devx_init,
7285 mlx5_ib_stage_devx_cleanup),
b5ca15ad
MB		 7286 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
7287 mlx5_ib_stage_ib_reg_init,
7288 mlx5_ib_stage_ib_reg_cleanup),
03fe2deb
DM		 7289 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
7290 mlx5_ib_stage_post_ib_reg_umr_init,
7291 NULL),
b5ca15ad
MB		 7292};
7293
e3f1ed1f 7294static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
32f69e4b
DJ		 7295{
7296 struct mlx5_ib_multiport_info *mpi;
7297 struct mlx5_ib_dev *dev;
7298 bool bound = false;
7299 int err;
7300
7301 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
7302 if (!mpi)
7303 return NULL;
7304
7305 mpi->mdev = mdev;
7306
7307 err = mlx5_query_nic_vport_system_image_guid(mdev,
7308 &mpi->sys_image_guid);
7309 if (err) {
7310 kfree(mpi);
7311 return NULL;
7312 }
7313
7314 mutex_lock(&mlx5_ib_multiport_mutex);
7315 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
7316 if (dev->sys_image_guid == mpi->sys_image_guid)
7317 bound = mlx5_ib_bind_slave_port(dev, mpi);
7318
7319 if (bound) {
7320 rdma_roce_rescan_device(&dev->ib_dev);
7321 break;
7322 }
7323 }
7324
7325 if (!bound) {
7326 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
c42260f1
VP		 7327 dev_dbg(mdev->device,
7328 "no suitable IB device found to bind to, added to unaffiliated list.\n");
32f69e4b
DJ		 7329 }
7330 mutex_unlock(&mlx5_ib_multiport_mutex);
7331
7332 return mpi;
7333}
7334
16c1975f
MB		 7335static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
7336{
94de879c 7337 const struct mlx5_ib_profile *profile;
32f69e4b 7338 enum rdma_link_layer ll;
b5ca15ad 7339 struct mlx5_ib_dev *dev;
32f69e4b 7340 int port_type_cap;
da796ccb 7341 int num_ports;
32f69e4b 7342
b5ca15ad
MB		 7343 printk_once(KERN_INFO "%s", mlx5_version);
7344
f0666f1f 7345 if (MLX5_ESWITCH_MANAGER(mdev) &&
f6455de0 7346 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
5fb58c9e
MB		 7347 if (!mlx5_core_mp_enabled(mdev))
7348 mlx5_ib_register_vport_reps(mdev);
f0666f1f
BW		 7349 return mdev;
7350 }
7351
32f69e4b
DJ		 7352 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
7353 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
7354
e3f1ed1f
LR		 7355 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
7356 return mlx5_ib_add_slave_port(mdev);
32f69e4b 7357
da796ccb
MB		 7358 num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
7359 MLX5_CAP_GEN(mdev, num_vhca_ports));
459cc69f 7360 dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
b5ca15ad
MB		 7361 if (!dev)
7362 return NULL;
da796ccb
MB		 7363 dev->port = kcalloc(num_ports, sizeof(*dev->port),
7364 GFP_KERNEL);
7365 if (!dev->port) {
a5c9c299 7366 ib_dealloc_device(&dev->ib_dev);
da796ccb
MB		 7367 return NULL;
7368 }
b5ca15ad
MB		 7369
7370 dev->mdev = mdev;
da796ccb 7371 dev->num_ports = num_ports;
b5ca15ad 7372
94de879c
MG		 7373 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_is_roce_enabled(mdev))
7374 profile = &raw_eth_profile;
7375 else
7376 profile = &pf_profile;
7377
7378 return __mlx5_ib_add(dev, profile);
e126ba97
EC		 7379}
7380
9603b61d 7381static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 7382{
32f69e4b
DJ		 7383 struct mlx5_ib_multiport_info *mpi;
7384 struct mlx5_ib_dev *dev;
7385
f0666f1f
BW		 7386 if (MLX5_ESWITCH_MANAGER(mdev) && context == mdev) {
7387 mlx5_ib_unregister_vport_reps(mdev);
7388 return;
7389 }
7390
32f69e4b
DJ		 7391 if (mlx5_core_is_mp_slave(mdev)) {
7392 mpi = context;
7393 mutex_lock(&mlx5_ib_multiport_mutex);
7394 if (mpi->ibdev)
7395 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
7396 list_del(&mpi->list);
7397 mutex_unlock(&mlx5_ib_multiport_mutex);
5d44adeb 7398 kfree(mpi);
32f69e4b
DJ		 7399 return;
7400 }
6aec21f6 7401
32f69e4b 7402 dev = context;
f0666f1f 7403 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
e126ba97
EC		 7404}
7405
9603b61d
JM		 7406static struct mlx5_interface mlx5_ib_interface = {
7407 .add = mlx5_ib_add,
7408 .remove = mlx5_ib_remove,
64613d94 7409 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 7410};
7411
c44ef998
IL		 7412unsigned long mlx5_ib_get_xlt_emergency_page(void)
7413{
7414 mutex_lock(&xlt_emergency_page_mutex);
7415 return xlt_emergency_page;
7416}
7417
7418void mlx5_ib_put_xlt_emergency_page(void)
7419{
7420 mutex_unlock(&xlt_emergency_page_mutex);
7421}
7422
e126ba97
EC		 7423static int __init mlx5_ib_init(void)
7424{
6aec21f6
HE		 7425 int err;
7426
c44ef998
IL		 7427 xlt_emergency_page = __get_free_page(GFP_KERNEL);
7428 if (!xlt_emergency_page)
7429 return -ENOMEM;
7430
7431 mutex_init(&xlt_emergency_page_mutex);
7432
d69a24e0 7433 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
c44ef998
IL		 7434 if (!mlx5_ib_event_wq) {
7435 free_page(xlt_emergency_page);
d69a24e0 7436 return -ENOMEM;
c44ef998 7437 }
d69a24e0 7438
81713d37 7439 mlx5_ib_odp_init();
9603b61d 7440
6aec21f6 7441 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 7442
6aec21f6 7443 return err;
e126ba97
EC		 7444}
7445
7446static void __exit mlx5_ib_cleanup(void)
7447{
9603b61d 7448 mlx5_unregister_interface(&mlx5_ib_interface);
d69a24e0 7449 destroy_workqueue(mlx5_ib_event_wq);
c44ef998
IL		 7450 mutex_destroy(&xlt_emergency_page_mutex);
7451 free_page(xlt_emergency_page);
e126ba97
EC		 7452}
7453
7454module_init(mlx5_ib_init);
7455module_exit(mlx5_ib_cleanup);
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