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IB/core: Add ib_is_udata_cleared
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97
EC		 34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
41#include <linux/sched.h>
42#include <rdma/ib_user_verbs.h>
3f89a643 43#include <rdma/ib_addr.h>
2811ba51 44#include <rdma/ib_cache.h>
1b5daf11 45#include <linux/mlx5/vport.h>
e126ba97
EC		 46#include <rdma/ib_smi.h>
47#include <rdma/ib_umem.h>
48#include "user.h"
49#include "mlx5_ib.h"
50
51#define DRIVER_NAME "mlx5_ib"
169a1d85
AV		 52#define DRIVER_VERSION "2.2-1"
53#define DRIVER_RELDATE "Feb 2014"
e126ba97
EC		 54
55MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
56MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
57MODULE_LICENSE("Dual BSD/GPL");
58MODULE_VERSION(DRIVER_VERSION);
59
9603b61d
JM		 60static int deprecated_prof_sel = 2;
61module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
62MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
e126ba97
EC		 63
64static char mlx5_version[] =
65 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
66 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
67
1b5daf11 68static enum rdma_link_layer
ebd61f68 69mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 70{
ebd61f68 71 switch (port_type_cap) {
1b5daf11
MD		 72 case MLX5_CAP_PORT_TYPE_IB:
73 return IB_LINK_LAYER_INFINIBAND;
74 case MLX5_CAP_PORT_TYPE_ETH:
75 return IB_LINK_LAYER_ETHERNET;
76 default:
77 return IB_LINK_LAYER_UNSPECIFIED;
78 }
79}
80
ebd61f68
AS		 81static enum rdma_link_layer
82mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
83{
84 struct mlx5_ib_dev *dev = to_mdev(device);
85 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
86
87 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
88}
89
fc24fc5e
AS		 90static int mlx5_netdev_event(struct notifier_block *this,
91 unsigned long event, void *ptr)
92{
93 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
94 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
95 roce.nb);
96
97 if ((event != NETDEV_UNREGISTER) && (event != NETDEV_REGISTER))
98 return NOTIFY_DONE;
99
100 write_lock(&ibdev->roce.netdev_lock);
101 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
102 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? NULL : ndev;
103 write_unlock(&ibdev->roce.netdev_lock);
104
105 return NOTIFY_DONE;
106}
107
108static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
109 u8 port_num)
110{
111 struct mlx5_ib_dev *ibdev = to_mdev(device);
112 struct net_device *ndev;
113
114 /* Ensure ndev does not disappear before we invoke dev_hold()
115 */
116 read_lock(&ibdev->roce.netdev_lock);
117 ndev = ibdev->roce.netdev;
118 if (ndev)
119 dev_hold(ndev);
120 read_unlock(&ibdev->roce.netdev_lock);
121
122 return ndev;
123}
124
3f89a643
AS		 125static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
126 struct ib_port_attr *props)
127{
128 struct mlx5_ib_dev *dev = to_mdev(device);
129 struct net_device *ndev;
130 enum ib_mtu ndev_ib_mtu;
131
132 memset(props, 0, sizeof(*props));
133
134 props->port_cap_flags |= IB_PORT_CM_SUP;
135 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
136
137 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
138 roce_address_table_size);
139 props->max_mtu = IB_MTU_4096;
140 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
141 props->pkey_tbl_len = 1;
142 props->state = IB_PORT_DOWN;
143 props->phys_state = 3;
144
145 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev,
146 (u16 *)&props->qkey_viol_cntr);
147
148 ndev = mlx5_ib_get_netdev(device, port_num);
149 if (!ndev)
150 return 0;
151
152 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
153 props->state = IB_PORT_ACTIVE;
154 props->phys_state = 5;
155 }
156
157 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
158
159 dev_put(ndev);
160
161 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
162
163 props->active_width = IB_WIDTH_4X; /* TODO */
164 props->active_speed = IB_SPEED_QDR; /* TODO */
165
166 return 0;
167}
168
3cca2606
AS		 169static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
170 const struct ib_gid_attr *attr,
171 void *mlx5_addr)
172{
173#define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
174 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
175 source_l3_address);
176 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
177 source_mac_47_32);
178
179 if (!gid)
180 return;
181
182 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
183
184 if (is_vlan_dev(attr->ndev)) {
185 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
186 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
187 }
188
189 switch (attr->gid_type) {
190 case IB_GID_TYPE_IB:
191 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
192 break;
193 case IB_GID_TYPE_ROCE_UDP_ENCAP:
194 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
195 break;
196
197 default:
198 WARN_ON(true);
199 }
200
201 if (attr->gid_type != IB_GID_TYPE_IB) {
202 if (ipv6_addr_v4mapped((void *)gid))
203 MLX5_SET_RA(mlx5_addr, roce_l3_type,
204 MLX5_ROCE_L3_TYPE_IPV4);
205 else
206 MLX5_SET_RA(mlx5_addr, roce_l3_type,
207 MLX5_ROCE_L3_TYPE_IPV6);
208 }
209
210 if ((attr->gid_type == IB_GID_TYPE_IB) ||
211 !ipv6_addr_v4mapped((void *)gid))
212 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
213 else
214 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
215}
216
217static int set_roce_addr(struct ib_device *device, u8 port_num,
218 unsigned int index,
219 const union ib_gid *gid,
220 const struct ib_gid_attr *attr)
221{
222 struct mlx5_ib_dev *dev = to_mdev(device);
223 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)];
224 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)];
225 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
226 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
227
228 if (ll != IB_LINK_LAYER_ETHERNET)
229 return -EINVAL;
230
231 memset(in, 0, sizeof(in));
232
233 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
234
235 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
236 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
237
238 memset(out, 0, sizeof(out));
239 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
240}
241
242static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
243 unsigned int index, const union ib_gid *gid,
244 const struct ib_gid_attr *attr,
245 __always_unused void **context)
246{
247 return set_roce_addr(device, port_num, index, gid, attr);
248}
249
250static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
251 unsigned int index, __always_unused void **context)
252{
253 return set_roce_addr(device, port_num, index, NULL, NULL);
254}
255
2811ba51
AS		 256__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
257 int index)
258{
259 struct ib_gid_attr attr;
260 union ib_gid gid;
261
262 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
263 return 0;
264
265 if (!attr.ndev)
266 return 0;
267
268 dev_put(attr.ndev);
269
270 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
271 return 0;
272
273 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
274}
275
1b5daf11
MD		 276static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
277{
278 return !dev->mdev->issi;
279}
280
281enum {
282 MLX5_VPORT_ACCESS_METHOD_MAD,
283 MLX5_VPORT_ACCESS_METHOD_HCA,
284 MLX5_VPORT_ACCESS_METHOD_NIC,
285};
286
287static int mlx5_get_vport_access_method(struct ib_device *ibdev)
288{
289 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
290 return MLX5_VPORT_ACCESS_METHOD_MAD;
291
ebd61f68 292 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 293 IB_LINK_LAYER_ETHERNET)
294 return MLX5_VPORT_ACCESS_METHOD_NIC;
295
296 return MLX5_VPORT_ACCESS_METHOD_HCA;
297}
298
299static int mlx5_query_system_image_guid(struct ib_device *ibdev,
300 __be64 *sys_image_guid)
301{
302 struct mlx5_ib_dev *dev = to_mdev(ibdev);
303 struct mlx5_core_dev *mdev = dev->mdev;
304 u64 tmp;
305 int err;
306
307 switch (mlx5_get_vport_access_method(ibdev)) {
308 case MLX5_VPORT_ACCESS_METHOD_MAD:
309 return mlx5_query_mad_ifc_system_image_guid(ibdev,
310 sys_image_guid);
311
312 case MLX5_VPORT_ACCESS_METHOD_HCA:
313 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 314 break;
315
316 case MLX5_VPORT_ACCESS_METHOD_NIC:
317 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
318 break;
1b5daf11
MD		 319
320 default:
321 return -EINVAL;
322 }
3f89a643
AS		 323
324 if (!err)
325 *sys_image_guid = cpu_to_be64(tmp);
326
327 return err;
328
1b5daf11
MD		 329}
330
331static int mlx5_query_max_pkeys(struct ib_device *ibdev,
332 u16 *max_pkeys)
333{
334 struct mlx5_ib_dev *dev = to_mdev(ibdev);
335 struct mlx5_core_dev *mdev = dev->mdev;
336
337 switch (mlx5_get_vport_access_method(ibdev)) {
338 case MLX5_VPORT_ACCESS_METHOD_MAD:
339 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
340
341 case MLX5_VPORT_ACCESS_METHOD_HCA:
342 case MLX5_VPORT_ACCESS_METHOD_NIC:
343 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
344 pkey_table_size));
345 return 0;
346
347 default:
348 return -EINVAL;
349 }
350}
351
352static int mlx5_query_vendor_id(struct ib_device *ibdev,
353 u32 *vendor_id)
354{
355 struct mlx5_ib_dev *dev = to_mdev(ibdev);
356
357 switch (mlx5_get_vport_access_method(ibdev)) {
358 case MLX5_VPORT_ACCESS_METHOD_MAD:
359 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
360
361 case MLX5_VPORT_ACCESS_METHOD_HCA:
362 case MLX5_VPORT_ACCESS_METHOD_NIC:
363 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
364
365 default:
366 return -EINVAL;
367 }
368}
369
370static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
371 __be64 *node_guid)
372{
373 u64 tmp;
374 int err;
375
376 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
377 case MLX5_VPORT_ACCESS_METHOD_MAD:
378 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
379
380 case MLX5_VPORT_ACCESS_METHOD_HCA:
381 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 382 break;
383
384 case MLX5_VPORT_ACCESS_METHOD_NIC:
385 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
386 break;
1b5daf11
MD		 387
388 default:
389 return -EINVAL;
390 }
3f89a643
AS		 391
392 if (!err)
393 *node_guid = cpu_to_be64(tmp);
394
395 return err;
1b5daf11
MD		 396}
397
398struct mlx5_reg_node_desc {
399 u8 desc[64];
400};
401
402static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
403{
404 struct mlx5_reg_node_desc in;
405
406 if (mlx5_use_mad_ifc(dev))
407 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
408
409 memset(&in, 0, sizeof(in));
410
411 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
412 sizeof(struct mlx5_reg_node_desc),
413 MLX5_REG_NODE_DESC, 0, 0);
414}
415
e126ba97 416static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 417 struct ib_device_attr *props,
418 struct ib_udata *uhw)
e126ba97
EC		 419{
420 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 421 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 422 int err = -ENOMEM;
423 int max_rq_sg;
424 int max_sq_sg;
e0238a6a 425 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
e126ba97 426
2528e33e
MB		 427 if (uhw->inlen || uhw->outlen)
428 return -EINVAL;
429
1b5daf11
MD		 430 memset(props, 0, sizeof(*props));
431 err = mlx5_query_system_image_guid(ibdev,
432 &props->sys_image_guid);
433 if (err)
434 return err;
e126ba97 435
1b5daf11 436 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 437 if (err)
1b5daf11 438 return err;
e126ba97 439
1b5daf11
MD		 440 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
441 if (err)
442 return err;
e126ba97 443
9603b61d
JM		 444 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
445 (fw_rev_min(dev->mdev) << 16) |
446 fw_rev_sub(dev->mdev);
e126ba97
EC		 447 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
448 IB_DEVICE_PORT_ACTIVE_EVENT |
449 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 450 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 451
452 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 453 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 454 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 455 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 456 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 457 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 458 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97
EC		 459 props->device_cap_flags |= IB_DEVICE_XRC;
460 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 461 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 462 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
463 /* At this stage no support for signature handover */
464 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
465 IB_PROT_T10DIF_TYPE_2 |
466 IB_PROT_T10DIF_TYPE_3;
467 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
468 IB_GUARD_T10DIF_CSUM;
469 }
938fe83c 470 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 471 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 472
1b5daf11
MD		 473 props->vendor_part_id = mdev->pdev->device;
474 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 475
476 props->max_mr_size = ~0ull;
e0238a6a 477 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 478 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
479 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
480 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
481 sizeof(struct mlx5_wqe_data_seg);
482 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
483 sizeof(struct mlx5_wqe_ctrl_seg)) /
484 sizeof(struct mlx5_wqe_data_seg);
e126ba97 485 props->max_sge = min(max_rq_sg, max_sq_sg);
18ebd407 486 props->max_sge_rd = props->max_sge;
938fe83c
SM		 487 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
488 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_eq_sz)) - 1;
489 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
490 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
491 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
492 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
493 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
494 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
495 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 496 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97
EC		 497 props->max_srq_sge = max_rq_sg - 1;
498 props->max_fast_reg_page_list_len = (unsigned int)-1;
81bea28f
EC		 499 props->atomic_cap = IB_ATOMIC_NONE;
500 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 501 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
502 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 503 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
504 props->max_mcast_grp;
505 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
506
8cdd312c 507#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 508 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 509 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
510 props->odp_caps = dev->odp_caps;
511#endif
512
1b5daf11 513 return 0;
e126ba97
EC		 514}
515
1b5daf11
MD		 516enum mlx5_ib_width {
517 MLX5_IB_WIDTH_1X = 1 << 0,
518 MLX5_IB_WIDTH_2X = 1 << 1,
519 MLX5_IB_WIDTH_4X = 1 << 2,
520 MLX5_IB_WIDTH_8X = 1 << 3,
521 MLX5_IB_WIDTH_12X = 1 << 4
522};
523
524static int translate_active_width(struct ib_device *ibdev, u8 active_width,
525 u8 *ib_width)
e126ba97
EC		 526{
527 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 528 int err = 0;
529
530 if (active_width & MLX5_IB_WIDTH_1X) {
531 *ib_width = IB_WIDTH_1X;
532 } else if (active_width & MLX5_IB_WIDTH_2X) {
533 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
534 (int)active_width);
535 err = -EINVAL;
536 } else if (active_width & MLX5_IB_WIDTH_4X) {
537 *ib_width = IB_WIDTH_4X;
538 } else if (active_width & MLX5_IB_WIDTH_8X) {
539 *ib_width = IB_WIDTH_8X;
540 } else if (active_width & MLX5_IB_WIDTH_12X) {
541 *ib_width = IB_WIDTH_12X;
542 } else {
543 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
544 (int)active_width);
545 err = -EINVAL;
e126ba97
EC		 546 }
547
1b5daf11
MD		 548 return err;
549}
e126ba97 550
1b5daf11
MD		 551static int mlx5_mtu_to_ib_mtu(int mtu)
552{
553 switch (mtu) {
554 case 256: return 1;
555 case 512: return 2;
556 case 1024: return 3;
557 case 2048: return 4;
558 case 4096: return 5;
559 default:
560 pr_warn("invalid mtu\n");
561 return -1;
e126ba97 562 }
1b5daf11 563}
e126ba97 564
1b5daf11
MD		 565enum ib_max_vl_num {
566 __IB_MAX_VL_0 = 1,
567 __IB_MAX_VL_0_1 = 2,
568 __IB_MAX_VL_0_3 = 3,
569 __IB_MAX_VL_0_7 = 4,
570 __IB_MAX_VL_0_14 = 5,
571};
e126ba97 572
1b5daf11
MD		 573enum mlx5_vl_hw_cap {
574 MLX5_VL_HW_0 = 1,
575 MLX5_VL_HW_0_1 = 2,
576 MLX5_VL_HW_0_2 = 3,
577 MLX5_VL_HW_0_3 = 4,
578 MLX5_VL_HW_0_4 = 5,
579 MLX5_VL_HW_0_5 = 6,
580 MLX5_VL_HW_0_6 = 7,
581 MLX5_VL_HW_0_7 = 8,
582 MLX5_VL_HW_0_14 = 15
583};
e126ba97 584
1b5daf11
MD		 585static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
586 u8 *max_vl_num)
587{
588 switch (vl_hw_cap) {
589 case MLX5_VL_HW_0:
590 *max_vl_num = __IB_MAX_VL_0;
591 break;
592 case MLX5_VL_HW_0_1:
593 *max_vl_num = __IB_MAX_VL_0_1;
594 break;
595 case MLX5_VL_HW_0_3:
596 *max_vl_num = __IB_MAX_VL_0_3;
597 break;
598 case MLX5_VL_HW_0_7:
599 *max_vl_num = __IB_MAX_VL_0_7;
600 break;
601 case MLX5_VL_HW_0_14:
602 *max_vl_num = __IB_MAX_VL_0_14;
603 break;
e126ba97 604
1b5daf11
MD		 605 default:
606 return -EINVAL;
e126ba97 607 }
e126ba97 608
1b5daf11 609 return 0;
e126ba97
EC		 610}
611
1b5daf11
MD		 612static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
613 struct ib_port_attr *props)
e126ba97 614{
1b5daf11
MD		 615 struct mlx5_ib_dev *dev = to_mdev(ibdev);
616 struct mlx5_core_dev *mdev = dev->mdev;
617 struct mlx5_hca_vport_context *rep;
618 int max_mtu;
619 int oper_mtu;
620 int err;
621 u8 ib_link_width_oper;
622 u8 vl_hw_cap;
e126ba97 623
1b5daf11
MD		 624 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
625 if (!rep) {
626 err = -ENOMEM;
e126ba97 627 goto out;
e126ba97 628 }
e126ba97 629
1b5daf11 630 memset(props, 0, sizeof(*props));
e126ba97 631
1b5daf11 632 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 633 if (err)
634 goto out;
635
1b5daf11
MD		 636 props->lid = rep->lid;
637 props->lmc = rep->lmc;
638 props->sm_lid = rep->sm_lid;
639 props->sm_sl = rep->sm_sl;
640 props->state = rep->vport_state;
641 props->phys_state = rep->port_physical_state;
642 props->port_cap_flags = rep->cap_mask1;
643 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
644 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
645 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
646 props->bad_pkey_cntr = rep->pkey_violation_counter;
647 props->qkey_viol_cntr = rep->qkey_violation_counter;
648 props->subnet_timeout = rep->subnet_timeout;
649 props->init_type_reply = rep->init_type_reply;
e126ba97 650
1b5daf11
MD		 651 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
652 if (err)
e126ba97 653 goto out;
e126ba97 654
1b5daf11
MD		 655 err = translate_active_width(ibdev, ib_link_width_oper,
656 &props->active_width);
657 if (err)
658 goto out;
659 err = mlx5_query_port_proto_oper(mdev, &props->active_speed, MLX5_PTYS_IB,
660 port);
e126ba97
EC		 661 if (err)
662 goto out;
663
facc9699 664 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 665
1b5daf11 666 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 667
facc9699 668 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 669
1b5daf11 670 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 671
1b5daf11
MD		 672 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
673 if (err)
674 goto out;
e126ba97 675
1b5daf11
MD		 676 err = translate_max_vl_num(ibdev, vl_hw_cap,
677 &props->max_vl_num);
e126ba97 678out:
1b5daf11 679 kfree(rep);
e126ba97
EC		 680 return err;
681}
682
1b5daf11
MD		 683int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
684 struct ib_port_attr *props)
e126ba97 685{
1b5daf11
MD		 686 switch (mlx5_get_vport_access_method(ibdev)) {
687 case MLX5_VPORT_ACCESS_METHOD_MAD:
688 return mlx5_query_mad_ifc_port(ibdev, port, props);
e126ba97 689
1b5daf11
MD		 690 case MLX5_VPORT_ACCESS_METHOD_HCA:
691 return mlx5_query_hca_port(ibdev, port, props);
e126ba97 692
3f89a643
AS		 693 case MLX5_VPORT_ACCESS_METHOD_NIC:
694 return mlx5_query_port_roce(ibdev, port, props);
695
1b5daf11
MD		 696 default:
697 return -EINVAL;
698 }
699}
e126ba97 700
1b5daf11
MD		 701static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
702 union ib_gid *gid)
703{
704 struct mlx5_ib_dev *dev = to_mdev(ibdev);
705 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 706
1b5daf11
MD		 707 switch (mlx5_get_vport_access_method(ibdev)) {
708 case MLX5_VPORT_ACCESS_METHOD_MAD:
709 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 710
1b5daf11
MD		 711 case MLX5_VPORT_ACCESS_METHOD_HCA:
712 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
713
714 default:
715 return -EINVAL;
716 }
e126ba97 717
e126ba97
EC		 718}
719
1b5daf11
MD		 720static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
721 u16 *pkey)
722{
723 struct mlx5_ib_dev *dev = to_mdev(ibdev);
724 struct mlx5_core_dev *mdev = dev->mdev;
725
726 switch (mlx5_get_vport_access_method(ibdev)) {
727 case MLX5_VPORT_ACCESS_METHOD_MAD:
728 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
729
730 case MLX5_VPORT_ACCESS_METHOD_HCA:
731 case MLX5_VPORT_ACCESS_METHOD_NIC:
732 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
733 pkey);
734 default:
735 return -EINVAL;
736 }
737}
e126ba97
EC		 738
739static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
740 struct ib_device_modify *props)
741{
742 struct mlx5_ib_dev *dev = to_mdev(ibdev);
743 struct mlx5_reg_node_desc in;
744 struct mlx5_reg_node_desc out;
745 int err;
746
747 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
748 return -EOPNOTSUPP;
749
750 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
751 return 0;
752
753 /*
754 * If possible, pass node desc to FW, so it can generate
755 * a 144 trap. If cmd fails, just ignore.
756 */
757 memcpy(&in, props->node_desc, 64);
9603b61d 758 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 759 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
760 if (err)
761 return err;
762
763 memcpy(ibdev->node_desc, props->node_desc, 64);
764
765 return err;
766}
767
768static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
769 struct ib_port_modify *props)
770{
771 struct mlx5_ib_dev *dev = to_mdev(ibdev);
772 struct ib_port_attr attr;
773 u32 tmp;
774 int err;
775
776 mutex_lock(&dev->cap_mask_mutex);
777
778 err = mlx5_ib_query_port(ibdev, port, &attr);
779 if (err)
780 goto out;
781
782 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
783 ~props->clr_port_cap_mask;
784
9603b61d 785 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 786
787out:
788 mutex_unlock(&dev->cap_mask_mutex);
789 return err;
790}
791
792static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
793 struct ib_udata *udata)
794{
795 struct mlx5_ib_dev *dev = to_mdev(ibdev);
78c0f98c 796 struct mlx5_ib_alloc_ucontext_req_v2 req;
e126ba97
EC		 797 struct mlx5_ib_alloc_ucontext_resp resp;
798 struct mlx5_ib_ucontext *context;
799 struct mlx5_uuar_info *uuari;
800 struct mlx5_uar *uars;
c1be5232 801 int gross_uuars;
e126ba97 802 int num_uars;
78c0f98c 803 int ver;
e126ba97
EC		 804 int uuarn;
805 int err;
806 int i;
f241e749 807 size_t reqlen;
e126ba97
EC		 808
809 if (!dev->ib_active)
810 return ERR_PTR(-EAGAIN);
811
78c0f98c
EC		 812 memset(&req, 0, sizeof(req));
813 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
814 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
815 ver = 0;
816 else if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req_v2))
817 ver = 2;
818 else
819 return ERR_PTR(-EINVAL);
820
821 err = ib_copy_from_udata(&req, udata, reqlen);
e126ba97
EC		 822 if (err)
823 return ERR_PTR(err);
824
78c0f98c
EC		 825 if (req.flags || req.reserved)
826 return ERR_PTR(-EINVAL);
827
e126ba97
EC		 828 if (req.total_num_uuars > MLX5_MAX_UUARS)
829 return ERR_PTR(-ENOMEM);
830
831 if (req.total_num_uuars == 0)
832 return ERR_PTR(-EINVAL);
833
c1be5232
EC		 834 req.total_num_uuars = ALIGN(req.total_num_uuars,
835 MLX5_NON_FP_BF_REGS_PER_PAGE);
e126ba97
EC		 836 if (req.num_low_latency_uuars > req.total_num_uuars - 1)
837 return ERR_PTR(-EINVAL);
838
c1be5232
EC		 839 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
840 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
938fe83c
SM		 841 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
842 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
843 resp.cache_line_size = L1_CACHE_BYTES;
844 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
845 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
846 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
847 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
848 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
e126ba97
EC		 849
850 context = kzalloc(sizeof(*context), GFP_KERNEL);
851 if (!context)
852 return ERR_PTR(-ENOMEM);
853
854 uuari = &context->uuari;
855 mutex_init(&uuari->lock);
856 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
857 if (!uars) {
858 err = -ENOMEM;
859 goto out_ctx;
860 }
861
c1be5232 862 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
e126ba97
EC		 863 sizeof(*uuari->bitmap),
864 GFP_KERNEL);
865 if (!uuari->bitmap) {
866 err = -ENOMEM;
867 goto out_uar_ctx;
868 }
869 /*
870 * clear all fast path uuars
871 */
c1be5232 872 for (i = 0; i < gross_uuars; i++) {
e126ba97
EC		 873 uuarn = i & 3;
874 if (uuarn == 2 || uuarn == 3)
875 set_bit(i, uuari->bitmap);
876 }
877
c1be5232 878 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
e126ba97
EC		 879 if (!uuari->count) {
880 err = -ENOMEM;
881 goto out_bitmap;
882 }
883
884 for (i = 0; i < num_uars; i++) {
9603b61d 885 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
e126ba97
EC		 886 if (err)
887 goto out_count;
888 }
889
b4cfe447
HE		 890#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
891 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
892#endif
893
e126ba97
EC		 894 INIT_LIST_HEAD(&context->db_page_list);
895 mutex_init(&context->db_page_mutex);
896
897 resp.tot_uuars = req.total_num_uuars;
938fe83c 898 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
92b0ca7c
DC		 899 err = ib_copy_to_udata(udata, &resp,
900 sizeof(resp) - sizeof(resp.reserved));
e126ba97
EC		 901 if (err)
902 goto out_uars;
903
78c0f98c 904 uuari->ver = ver;
e126ba97
EC		 905 uuari->num_low_latency_uuars = req.num_low_latency_uuars;
906 uuari->uars = uars;
907 uuari->num_uars = num_uars;
908 return &context->ibucontext;
909
910out_uars:
911 for (i--; i >= 0; i--)
9603b61d 912 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
e126ba97
EC		 913out_count:
914 kfree(uuari->count);
915
916out_bitmap:
917 kfree(uuari->bitmap);
918
919out_uar_ctx:
920 kfree(uars);
921
922out_ctx:
923 kfree(context);
924 return ERR_PTR(err);
925}
926
927static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
928{
929 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
930 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
931 struct mlx5_uuar_info *uuari = &context->uuari;
932 int i;
933
934 for (i = 0; i < uuari->num_uars; i++) {
9603b61d 935 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
e126ba97
EC		 936 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
937 }
938
939 kfree(uuari->count);
940 kfree(uuari->bitmap);
941 kfree(uuari->uars);
942 kfree(context);
943
944 return 0;
945}
946
947static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
948{
9603b61d 949 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
e126ba97
EC		 950}
951
952static int get_command(unsigned long offset)
953{
954 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
955}
956
957static int get_arg(unsigned long offset)
958{
959 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
960}
961
962static int get_index(unsigned long offset)
963{
964 return get_arg(offset);
965}
966
967static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
968{
969 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
970 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
971 struct mlx5_uuar_info *uuari = &context->uuari;
972 unsigned long command;
973 unsigned long idx;
974 phys_addr_t pfn;
975
976 command = get_command(vma->vm_pgoff);
977 switch (command) {
978 case MLX5_IB_MMAP_REGULAR_PAGE:
979 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
980 return -EINVAL;
981
982 idx = get_index(vma->vm_pgoff);
1c3ce90d
EC		 983 if (idx >= uuari->num_uars)
984 return -EINVAL;
985
e126ba97
EC		 986 pfn = uar_index2pfn(dev, uuari->uars[idx].index);
987 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn 0x%llx\n", idx,
988 (unsigned long long)pfn);
989
e126ba97
EC		 990 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
991 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
992 PAGE_SIZE, vma->vm_page_prot))
993 return -EAGAIN;
994
995 mlx5_ib_dbg(dev, "mapped WC at 0x%lx, PA 0x%llx\n",
996 vma->vm_start,
997 (unsigned long long)pfn << PAGE_SHIFT);
998 break;
999
1000 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1001 return -ENOSYS;
1002
1003 default:
1004 return -EINVAL;
1005 }
1006
1007 return 0;
1008}
1009
e126ba97
EC		 1010static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1011 struct ib_ucontext *context,
1012 struct ib_udata *udata)
1013{
1014 struct mlx5_ib_alloc_pd_resp resp;
1015 struct mlx5_ib_pd *pd;
1016 int err;
1017
1018 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1019 if (!pd)
1020 return ERR_PTR(-ENOMEM);
1021
9603b61d 1022 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 1023 if (err) {
1024 kfree(pd);
1025 return ERR_PTR(err);
1026 }
1027
1028 if (context) {
1029 resp.pdn = pd->pdn;
1030 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 1031 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 1032 kfree(pd);
1033 return ERR_PTR(-EFAULT);
1034 }
e126ba97
EC		 1035 }
1036
1037 return &pd->ibpd;
1038}
1039
1040static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1041{
1042 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1043 struct mlx5_ib_pd *mpd = to_mpd(pd);
1044
9603b61d 1045 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 1046 kfree(mpd);
1047
1048 return 0;
1049}
1050
1051static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1052{
1053 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1054 int err;
1055
9603b61d 1056 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 1057 if (err)
1058 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
1059 ibqp->qp_num, gid->raw);
1060
1061 return err;
1062}
1063
1064static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1065{
1066 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1067 int err;
1068
9603b61d 1069 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 1070 if (err)
1071 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
1072 ibqp->qp_num, gid->raw);
1073
1074 return err;
1075}
1076
1077static int init_node_data(struct mlx5_ib_dev *dev)
1078{
1b5daf11 1079 int err;
e126ba97 1080
1b5daf11 1081 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 1082 if (err)
1b5daf11 1083 return err;
e126ba97 1084
1b5daf11 1085 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 1086
1b5daf11 1087 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 1088}
1089
1090static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
1091 char *buf)
1092{
1093 struct mlx5_ib_dev *dev =
1094 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1095
9603b61d 1096 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 1097}
1098
1099static ssize_t show_reg_pages(struct device *device,
1100 struct device_attribute *attr, char *buf)
1101{
1102 struct mlx5_ib_dev *dev =
1103 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1104
6aec21f6 1105 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 1106}
1107
1108static ssize_t show_hca(struct device *device, struct device_attribute *attr,
1109 char *buf)
1110{
1111 struct mlx5_ib_dev *dev =
1112 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 1113 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 1114}
1115
1116static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr,
1117 char *buf)
1118{
1119 struct mlx5_ib_dev *dev =
1120 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d
JM		 1121 return sprintf(buf, "%d.%d.%d\n", fw_rev_maj(dev->mdev),
1122 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
e126ba97
EC		 1123}
1124
1125static ssize_t show_rev(struct device *device, struct device_attribute *attr,
1126 char *buf)
1127{
1128 struct mlx5_ib_dev *dev =
1129 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 1130 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 1131}
1132
1133static ssize_t show_board(struct device *device, struct device_attribute *attr,
1134 char *buf)
1135{
1136 struct mlx5_ib_dev *dev =
1137 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1138 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 1139 dev->mdev->board_id);
e126ba97
EC		 1140}
1141
1142static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
1143static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
1144static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
1145static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
1146static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
1147static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
1148
1149static struct device_attribute *mlx5_class_attributes[] = {
1150 &dev_attr_hw_rev,
1151 &dev_attr_fw_ver,
1152 &dev_attr_hca_type,
1153 &dev_attr_board_id,
1154 &dev_attr_fw_pages,
1155 &dev_attr_reg_pages,
1156};
1157
9603b61d 1158static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 1159 enum mlx5_dev_event event, unsigned long param)
e126ba97 1160{
9603b61d 1161 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
e126ba97 1162 struct ib_event ibev;
9603b61d 1163
e126ba97
EC		 1164 u8 port = 0;
1165
1166 switch (event) {
1167 case MLX5_DEV_EVENT_SYS_ERROR:
1168 ibdev->ib_active = false;
1169 ibev.event = IB_EVENT_DEVICE_FATAL;
1170 break;
1171
1172 case MLX5_DEV_EVENT_PORT_UP:
1173 ibev.event = IB_EVENT_PORT_ACTIVE;
4d2f9bbb 1174 port = (u8)param;
e126ba97
EC		 1175 break;
1176
1177 case MLX5_DEV_EVENT_PORT_DOWN:
1178 ibev.event = IB_EVENT_PORT_ERR;
4d2f9bbb 1179 port = (u8)param;
e126ba97
EC		 1180 break;
1181
1182 case MLX5_DEV_EVENT_PORT_INITIALIZED:
1183 /* not used by ULPs */
1184 return;
1185
1186 case MLX5_DEV_EVENT_LID_CHANGE:
1187 ibev.event = IB_EVENT_LID_CHANGE;
4d2f9bbb 1188 port = (u8)param;
e126ba97
EC		 1189 break;
1190
1191 case MLX5_DEV_EVENT_PKEY_CHANGE:
1192 ibev.event = IB_EVENT_PKEY_CHANGE;
4d2f9bbb 1193 port = (u8)param;
e126ba97
EC		 1194 break;
1195
1196 case MLX5_DEV_EVENT_GUID_CHANGE:
1197 ibev.event = IB_EVENT_GID_CHANGE;
4d2f9bbb 1198 port = (u8)param;
e126ba97
EC		 1199 break;
1200
1201 case MLX5_DEV_EVENT_CLIENT_REREG:
1202 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4d2f9bbb 1203 port = (u8)param;
e126ba97
EC		 1204 break;
1205 }
1206
1207 ibev.device = &ibdev->ib_dev;
1208 ibev.element.port_num = port;
1209
a0c84c32
EC		 1210 if (port < 1 || port > ibdev->num_ports) {
1211 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
1212 return;
1213 }
1214
e126ba97
EC		 1215 if (ibdev->ib_active)
1216 ib_dispatch_event(&ibev);
1217}
1218
1219static void get_ext_port_caps(struct mlx5_ib_dev *dev)
1220{
1221 int port;
1222
938fe83c 1223 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
e126ba97
EC		 1224 mlx5_query_ext_port_caps(dev, port);
1225}
1226
1227static int get_port_caps(struct mlx5_ib_dev *dev)
1228{
1229 struct ib_device_attr *dprops = NULL;
1230 struct ib_port_attr *pprops = NULL;
f614fc15 1231 int err = -ENOMEM;
e126ba97 1232 int port;
2528e33e 1233 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 1234
1235 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
1236 if (!pprops)
1237 goto out;
1238
1239 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
1240 if (!dprops)
1241 goto out;
1242
2528e33e 1243 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 1244 if (err) {
1245 mlx5_ib_warn(dev, "query_device failed %d\n", err);
1246 goto out;
1247 }
1248
938fe83c 1249 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
e126ba97
EC		 1250 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
1251 if (err) {
938fe83c
SM		 1252 mlx5_ib_warn(dev, "query_port %d failed %d\n",
1253 port, err);
e126ba97
EC		 1254 break;
1255 }
938fe83c
SM		 1256 dev->mdev->port_caps[port - 1].pkey_table_len =
1257 dprops->max_pkeys;
1258 dev->mdev->port_caps[port - 1].gid_table_len =
1259 pprops->gid_tbl_len;
e126ba97
EC		 1260 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
1261 dprops->max_pkeys, pprops->gid_tbl_len);
1262 }
1263
1264out:
1265 kfree(pprops);
1266 kfree(dprops);
1267
1268 return err;
1269}
1270
1271static void destroy_umrc_res(struct mlx5_ib_dev *dev)
1272{
1273 int err;
1274
1275 err = mlx5_mr_cache_cleanup(dev);
1276 if (err)
1277 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
1278
1279 mlx5_ib_destroy_qp(dev->umrc.qp);
1280 ib_destroy_cq(dev->umrc.cq);
e126ba97
EC		 1281 ib_dealloc_pd(dev->umrc.pd);
1282}
1283
1284enum {
1285 MAX_UMR_WR = 128,
1286};
1287
1288static int create_umr_res(struct mlx5_ib_dev *dev)
1289{
1290 struct ib_qp_init_attr *init_attr = NULL;
1291 struct ib_qp_attr *attr = NULL;
1292 struct ib_pd *pd;
1293 struct ib_cq *cq;
1294 struct ib_qp *qp;
8e37210b 1295 struct ib_cq_init_attr cq_attr = {};
e126ba97
EC		 1296 int ret;
1297
1298 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
1299 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
1300 if (!attr || !init_attr) {
1301 ret = -ENOMEM;
1302 goto error_0;
1303 }
1304
1305 pd = ib_alloc_pd(&dev->ib_dev);
1306 if (IS_ERR(pd)) {
1307 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
1308 ret = PTR_ERR(pd);
1309 goto error_0;
1310 }
1311
8e37210b
MB		 1312 cq_attr.cqe = 128;
1313 cq = ib_create_cq(&dev->ib_dev, mlx5_umr_cq_handler, NULL, NULL,
1314 &cq_attr);
e126ba97
EC		 1315 if (IS_ERR(cq)) {
1316 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
1317 ret = PTR_ERR(cq);
1318 goto error_2;
1319 }
1320 ib_req_notify_cq(cq, IB_CQ_NEXT_COMP);
1321
1322 init_attr->send_cq = cq;
1323 init_attr->recv_cq = cq;
1324 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
1325 init_attr->cap.max_send_wr = MAX_UMR_WR;
1326 init_attr->cap.max_send_sge = 1;
1327 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
1328 init_attr->port_num = 1;
1329 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
1330 if (IS_ERR(qp)) {
1331 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
1332 ret = PTR_ERR(qp);
1333 goto error_3;
1334 }
1335 qp->device = &dev->ib_dev;
1336 qp->real_qp = qp;
1337 qp->uobject = NULL;
1338 qp->qp_type = MLX5_IB_QPT_REG_UMR;
1339
1340 attr->qp_state = IB_QPS_INIT;
1341 attr->port_num = 1;
1342 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
1343 IB_QP_PORT, NULL);
1344 if (ret) {
1345 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
1346 goto error_4;
1347 }
1348
1349 memset(attr, 0, sizeof(*attr));
1350 attr->qp_state = IB_QPS_RTR;
1351 attr->path_mtu = IB_MTU_256;
1352
1353 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
1354 if (ret) {
1355 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
1356 goto error_4;
1357 }
1358
1359 memset(attr, 0, sizeof(*attr));
1360 attr->qp_state = IB_QPS_RTS;
1361 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
1362 if (ret) {
1363 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
1364 goto error_4;
1365 }
1366
1367 dev->umrc.qp = qp;
1368 dev->umrc.cq = cq;
e126ba97
EC		 1369 dev->umrc.pd = pd;
1370
1371 sema_init(&dev->umrc.sem, MAX_UMR_WR);
1372 ret = mlx5_mr_cache_init(dev);
1373 if (ret) {
1374 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
1375 goto error_4;
1376 }
1377
1378 kfree(attr);
1379 kfree(init_attr);
1380
1381 return 0;
1382
1383error_4:
1384 mlx5_ib_destroy_qp(qp);
1385
1386error_3:
1387 ib_destroy_cq(cq);
1388
1389error_2:
e126ba97
EC		 1390 ib_dealloc_pd(pd);
1391
1392error_0:
1393 kfree(attr);
1394 kfree(init_attr);
1395 return ret;
1396}
1397
1398static int create_dev_resources(struct mlx5_ib_resources *devr)
1399{
1400 struct ib_srq_init_attr attr;
1401 struct mlx5_ib_dev *dev;
bcf4c1ea 1402 struct ib_cq_init_attr cq_attr = {.cqe = 1};
e126ba97
EC		 1403 int ret = 0;
1404
1405 dev = container_of(devr, struct mlx5_ib_dev, devr);
1406
1407 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
1408 if (IS_ERR(devr->p0)) {
1409 ret = PTR_ERR(devr->p0);
1410 goto error0;
1411 }
1412 devr->p0->device = &dev->ib_dev;
1413 devr->p0->uobject = NULL;
1414 atomic_set(&devr->p0->usecnt, 0);
1415
bcf4c1ea 1416 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 1417 if (IS_ERR(devr->c0)) {
1418 ret = PTR_ERR(devr->c0);
1419 goto error1;
1420 }
1421 devr->c0->device = &dev->ib_dev;
1422 devr->c0->uobject = NULL;
1423 devr->c0->comp_handler = NULL;
1424 devr->c0->event_handler = NULL;
1425 devr->c0->cq_context = NULL;
1426 atomic_set(&devr->c0->usecnt, 0);
1427
1428 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
1429 if (IS_ERR(devr->x0)) {
1430 ret = PTR_ERR(devr->x0);
1431 goto error2;
1432 }
1433 devr->x0->device = &dev->ib_dev;
1434 devr->x0->inode = NULL;
1435 atomic_set(&devr->x0->usecnt, 0);
1436 mutex_init(&devr->x0->tgt_qp_mutex);
1437 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
1438
1439 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
1440 if (IS_ERR(devr->x1)) {
1441 ret = PTR_ERR(devr->x1);
1442 goto error3;
1443 }
1444 devr->x1->device = &dev->ib_dev;
1445 devr->x1->inode = NULL;
1446 atomic_set(&devr->x1->usecnt, 0);
1447 mutex_init(&devr->x1->tgt_qp_mutex);
1448 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
1449
1450 memset(&attr, 0, sizeof(attr));
1451 attr.attr.max_sge = 1;
1452 attr.attr.max_wr = 1;
1453 attr.srq_type = IB_SRQT_XRC;
1454 attr.ext.xrc.cq = devr->c0;
1455 attr.ext.xrc.xrcd = devr->x0;
1456
1457 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
1458 if (IS_ERR(devr->s0)) {
1459 ret = PTR_ERR(devr->s0);
1460 goto error4;
1461 }
1462 devr->s0->device = &dev->ib_dev;
1463 devr->s0->pd = devr->p0;
1464 devr->s0->uobject = NULL;
1465 devr->s0->event_handler = NULL;
1466 devr->s0->srq_context = NULL;
1467 devr->s0->srq_type = IB_SRQT_XRC;
1468 devr->s0->ext.xrc.xrcd = devr->x0;
1469 devr->s0->ext.xrc.cq = devr->c0;
1470 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1471 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
1472 atomic_inc(&devr->p0->usecnt);
1473 atomic_set(&devr->s0->usecnt, 0);
1474
4aa17b28
HA		 1475 memset(&attr, 0, sizeof(attr));
1476 attr.attr.max_sge = 1;
1477 attr.attr.max_wr = 1;
1478 attr.srq_type = IB_SRQT_BASIC;
1479 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
1480 if (IS_ERR(devr->s1)) {
1481 ret = PTR_ERR(devr->s1);
1482 goto error5;
1483 }
1484 devr->s1->device = &dev->ib_dev;
1485 devr->s1->pd = devr->p0;
1486 devr->s1->uobject = NULL;
1487 devr->s1->event_handler = NULL;
1488 devr->s1->srq_context = NULL;
1489 devr->s1->srq_type = IB_SRQT_BASIC;
1490 devr->s1->ext.xrc.cq = devr->c0;
1491 atomic_inc(&devr->p0->usecnt);
1492 atomic_set(&devr->s0->usecnt, 0);
1493
e126ba97
EC		 1494 return 0;
1495
4aa17b28
HA		 1496error5:
1497 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 1498error4:
1499 mlx5_ib_dealloc_xrcd(devr->x1);
1500error3:
1501 mlx5_ib_dealloc_xrcd(devr->x0);
1502error2:
1503 mlx5_ib_destroy_cq(devr->c0);
1504error1:
1505 mlx5_ib_dealloc_pd(devr->p0);
1506error0:
1507 return ret;
1508}
1509
1510static void destroy_dev_resources(struct mlx5_ib_resources *devr)
1511{
4aa17b28 1512 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 1513 mlx5_ib_destroy_srq(devr->s0);
1514 mlx5_ib_dealloc_xrcd(devr->x0);
1515 mlx5_ib_dealloc_xrcd(devr->x1);
1516 mlx5_ib_destroy_cq(devr->c0);
1517 mlx5_ib_dealloc_pd(devr->p0);
1518}
1519
e53505a8
AS		 1520static u32 get_core_cap_flags(struct ib_device *ibdev)
1521{
1522 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1523 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
1524 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
1525 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
1526 u32 ret = 0;
1527
1528 if (ll == IB_LINK_LAYER_INFINIBAND)
1529 return RDMA_CORE_PORT_IBA_IB;
1530
1531 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
1532 return 0;
1533
1534 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
1535 return 0;
1536
1537 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
1538 ret |= RDMA_CORE_PORT_IBA_ROCE;
1539
1540 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
1541 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
1542
1543 return ret;
1544}
1545
7738613e
IW		 1546static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
1547 struct ib_port_immutable *immutable)
1548{
1549 struct ib_port_attr attr;
1550 int err;
1551
1552 err = mlx5_ib_query_port(ibdev, port_num, &attr);
1553 if (err)
1554 return err;
1555
1556 immutable->pkey_tbl_len = attr.pkey_tbl_len;
1557 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 1558 immutable->core_cap_flags = get_core_cap_flags(ibdev);
337877a4 1559 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 1560
1561 return 0;
1562}
1563
fc24fc5e
AS		 1564static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
1565{
e53505a8
AS		 1566 int err;
1567
fc24fc5e 1568 dev->roce.nb.notifier_call = mlx5_netdev_event;
e53505a8
AS		 1569 err = register_netdevice_notifier(&dev->roce.nb);
1570 if (err)
1571 return err;
1572
1573 err = mlx5_nic_vport_enable_roce(dev->mdev);
1574 if (err)
1575 goto err_unregister_netdevice_notifier;
1576
1577 return 0;
1578
1579err_unregister_netdevice_notifier:
1580 unregister_netdevice_notifier(&dev->roce.nb);
1581 return err;
fc24fc5e
AS		 1582}
1583
1584static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
1585{
e53505a8 1586 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 1587 unregister_netdevice_notifier(&dev->roce.nb);
1588}
1589
9603b61d 1590static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
e126ba97 1591{
e126ba97 1592 struct mlx5_ib_dev *dev;
ebd61f68
AS		 1593 enum rdma_link_layer ll;
1594 int port_type_cap;
e126ba97
EC		 1595 int err;
1596 int i;
1597
ebd61f68
AS		 1598 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
1599 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
1600
e53505a8 1601 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
647241ea
MD		 1602 return NULL;
1603
e126ba97
EC		 1604 printk_once(KERN_INFO "%s", mlx5_version);
1605
1606 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
1607 if (!dev)
9603b61d 1608 return NULL;
e126ba97 1609
9603b61d 1610 dev->mdev = mdev;
e126ba97 1611
fc24fc5e 1612 rwlock_init(&dev->roce.netdev_lock);
e126ba97
EC		 1613 err = get_port_caps(dev);
1614 if (err)
9603b61d 1615 goto err_dealloc;
e126ba97 1616
1b5daf11
MD		 1617 if (mlx5_use_mad_ifc(dev))
1618 get_ext_port_caps(dev);
e126ba97 1619
e126ba97
EC		 1620 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
1621
1622 strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX);
1623 dev->ib_dev.owner = THIS_MODULE;
1624 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 1625 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
938fe83c 1626 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
e126ba97 1627 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 1628 dev->ib_dev.num_comp_vectors =
1629 dev->mdev->priv.eq_table.num_comp_vectors;
e126ba97
EC		 1630 dev->ib_dev.dma_device = &mdev->pdev->dev;
1631
1632 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
1633 dev->ib_dev.uverbs_cmd_mask =
1634 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
1635 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
1636 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
1637 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
1638 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
1639 (1ull << IB_USER_VERBS_CMD_REG_MR) |
1640 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
1641 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
1642 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
1643 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
1644 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
1645 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
1646 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
1647 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
1648 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
1649 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
1650 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
1651 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
1652 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
1653 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
1654 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
1655 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
1656 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a
HE		 1657 dev->ib_dev.uverbs_ex_cmd_mask =
1658 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE);
e126ba97
EC		 1659
1660 dev->ib_dev.query_device = mlx5_ib_query_device;
1661 dev->ib_dev.query_port = mlx5_ib_query_port;
ebd61f68 1662 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
fc24fc5e
AS		 1663 if (ll == IB_LINK_LAYER_ETHERNET)
1664 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
e126ba97 1665 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 1666 dev->ib_dev.add_gid = mlx5_ib_add_gid;
1667 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 1668 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
1669 dev->ib_dev.modify_device = mlx5_ib_modify_device;
1670 dev->ib_dev.modify_port = mlx5_ib_modify_port;
1671 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
1672 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
1673 dev->ib_dev.mmap = mlx5_ib_mmap;
1674 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
1675 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
1676 dev->ib_dev.create_ah = mlx5_ib_create_ah;
1677 dev->ib_dev.query_ah = mlx5_ib_query_ah;
1678 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
1679 dev->ib_dev.create_srq = mlx5_ib_create_srq;
1680 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
1681 dev->ib_dev.query_srq = mlx5_ib_query_srq;
1682 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
1683 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
1684 dev->ib_dev.create_qp = mlx5_ib_create_qp;
1685 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
1686 dev->ib_dev.query_qp = mlx5_ib_query_qp;
1687 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
1688 dev->ib_dev.post_send = mlx5_ib_post_send;
1689 dev->ib_dev.post_recv = mlx5_ib_post_recv;
1690 dev->ib_dev.create_cq = mlx5_ib_create_cq;
1691 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
1692 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
1693 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
1694 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
1695 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
1696 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
1697 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
1698 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
1699 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
1700 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
1701 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 1702 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 1703 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 1704 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
7738613e 1705 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
e126ba97 1706
938fe83c 1707 mlx5_ib_internal_fill_odp_caps(dev);
8cdd312c 1708
938fe83c 1709 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 1710 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
1711 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
1712 dev->ib_dev.uverbs_cmd_mask |=
1713 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
1714 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
1715 }
1716
1717 err = init_node_data(dev);
1718 if (err)
233d05d2 1719 goto err_dealloc;
e126ba97
EC		 1720
1721 mutex_init(&dev->cap_mask_mutex);
e126ba97 1722
fc24fc5e
AS		 1723 if (ll == IB_LINK_LAYER_ETHERNET) {
1724 err = mlx5_enable_roce(dev);
1725 if (err)
1726 goto err_dealloc;
1727 }
1728
e126ba97
EC		 1729 err = create_dev_resources(&dev->devr);
1730 if (err)
fc24fc5e 1731 goto err_disable_roce;
e126ba97 1732
6aec21f6 1733 err = mlx5_ib_odp_init_one(dev);
281d1a92 1734 if (err)
e126ba97
EC		 1735 goto err_rsrc;
1736
6aec21f6
HE		 1737 err = ib_register_device(&dev->ib_dev, NULL);
1738 if (err)
1739 goto err_odp;
1740
e126ba97
EC		 1741 err = create_umr_res(dev);
1742 if (err)
1743 goto err_dev;
1744
1745 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 1746 err = device_create_file(&dev->ib_dev.dev,
1747 mlx5_class_attributes[i]);
1748 if (err)
e126ba97
EC		 1749 goto err_umrc;
1750 }
1751
1752 dev->ib_active = true;
1753
9603b61d 1754 return dev;
e126ba97
EC		 1755
1756err_umrc:
1757 destroy_umrc_res(dev);
1758
1759err_dev:
1760 ib_unregister_device(&dev->ib_dev);
1761
6aec21f6
HE		 1762err_odp:
1763 mlx5_ib_odp_remove_one(dev);
1764
e126ba97
EC		 1765err_rsrc:
1766 destroy_dev_resources(&dev->devr);
1767
fc24fc5e
AS		 1768err_disable_roce:
1769 if (ll == IB_LINK_LAYER_ETHERNET)
1770 mlx5_disable_roce(dev);
1771
9603b61d 1772err_dealloc:
e126ba97
EC		 1773 ib_dealloc_device((struct ib_device *)dev);
1774
9603b61d 1775 return NULL;
e126ba97
EC		 1776}
1777
9603b61d 1778static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 1779{
9603b61d 1780 struct mlx5_ib_dev *dev = context;
fc24fc5e 1781 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
6aec21f6 1782
e126ba97 1783 ib_unregister_device(&dev->ib_dev);
eefd56e5 1784 destroy_umrc_res(dev);
6aec21f6 1785 mlx5_ib_odp_remove_one(dev);
e126ba97 1786 destroy_dev_resources(&dev->devr);
fc24fc5e
AS		 1787 if (ll == IB_LINK_LAYER_ETHERNET)
1788 mlx5_disable_roce(dev);
e126ba97
EC		 1789 ib_dealloc_device(&dev->ib_dev);
1790}
1791
9603b61d
JM		 1792static struct mlx5_interface mlx5_ib_interface = {
1793 .add = mlx5_ib_add,
1794 .remove = mlx5_ib_remove,
1795 .event = mlx5_ib_event,
64613d94 1796 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 1797};
1798
1799static int __init mlx5_ib_init(void)
1800{
6aec21f6
HE		 1801 int err;
1802
9603b61d
JM		 1803 if (deprecated_prof_sel != 2)
1804 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
1805
6aec21f6
HE		 1806 err = mlx5_ib_odp_init();
1807 if (err)
1808 return err;
1809
1810 err = mlx5_register_interface(&mlx5_ib_interface);
1811 if (err)
1812 goto clean_odp;
1813
1814 return err;
1815
1816clean_odp:
1817 mlx5_ib_odp_cleanup();
1818 return err;
e126ba97
EC		 1819}
1820
1821static void __exit mlx5_ib_cleanup(void)
1822{
9603b61d 1823 mlx5_unregister_interface(&mlx5_ib_interface);
6aec21f6 1824 mlx5_ib_odp_cleanup();
e126ba97
EC		 1825}
1826
1827module_init(mlx5_ib_init);
1828module_exit(mlx5_ib_cleanup);
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