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IB/mlx5: Add support for ODP for DEVX indirection mkey
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
24da0016 41#include <linux/bitmap.h>
37aa5c36
GL		 42#if defined(CONFIG_X86)
43#include <asm/pat.h>
44#endif
e126ba97 45#include <linux/sched.h>
6e84f315 46#include <linux/sched/mm.h>
0881e7bd 47#include <linux/sched/task.h>
7c2344c3 48#include <linux/delay.h>
e126ba97 49#include <rdma/ib_user_verbs.h>
3f89a643 50#include <rdma/ib_addr.h>
2811ba51 51#include <rdma/ib_cache.h>
ada68c31 52#include <linux/mlx5/port.h>
1b5daf11 53#include <linux/mlx5/vport.h>
72c7fe90 54#include <linux/mlx5/fs.h>
7c2344c3 55#include <linux/list.h>
e126ba97
EC		 56#include <rdma/ib_smi.h>
57#include <rdma/ib_umem.h>
038d2ef8
MG		 58#include <linux/in.h>
59#include <linux/etherdevice.h>
e126ba97 60#include "mlx5_ib.h"
fc385b7a 61#include "ib_rep.h"
e1f24a79 62#include "cmd.h"
f3da6577 63#include "srq.h"
3346c487 64#include <linux/mlx5/fs_helpers.h>
c6475a0b 65#include <linux/mlx5/accel.h>
8c84660b 66#include <rdma/uverbs_std_types.h>
c6475a0b
AY		 67#include <rdma/mlx5_user_ioctl_verbs.h>
68#include <rdma/mlx5_user_ioctl_cmds.h>
8c84660b
MB		 69
70#define UVERBS_MODULE_NAME mlx5_ib
71#include <rdma/uverbs_named_ioctl.h>
e126ba97
EC		 72
73#define DRIVER_NAME "mlx5_ib"
b359911d 74#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 75
76MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
77MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
78MODULE_LICENSE("Dual BSD/GPL");
e126ba97 79
e126ba97
EC		 80static char mlx5_version[] =
81 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 82 DRIVER_VERSION "\n";
e126ba97 83
d69a24e0
DJ		 84struct mlx5_ib_event_work {
85 struct work_struct work;
df097a27
SM		 86 union {
87 struct mlx5_ib_dev *dev;
88 struct mlx5_ib_multiport_info *mpi;
89 };
90 bool is_slave;
134e9349 91 unsigned int event;
df097a27 92 void *param;
d69a24e0
DJ		 93};
94
da7525d2
EBE		 95enum {
96 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
97};
98
d69a24e0 99static struct workqueue_struct *mlx5_ib_event_wq;
32f69e4b
DJ		 100static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
101static LIST_HEAD(mlx5_ib_dev_list);
102/*
103 * This mutex should be held when accessing either of the above lists
104 */
105static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
106
c44ef998
IL		 107/* We can't use an array for xlt_emergency_page because dma_map_single
108 * doesn't work on kernel modules memory
109 */
110static unsigned long xlt_emergency_page;
111static struct mutex xlt_emergency_page_mutex;
112
32f69e4b
DJ		 113struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
114{
115 struct mlx5_ib_dev *dev;
116
117 mutex_lock(&mlx5_ib_multiport_mutex);
118 dev = mpi->ibdev;
119 mutex_unlock(&mlx5_ib_multiport_mutex);
120 return dev;
121}
122
1b5daf11 123static enum rdma_link_layer
ebd61f68 124mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 125{
ebd61f68 126 switch (port_type_cap) {
1b5daf11
MD		 127 case MLX5_CAP_PORT_TYPE_IB:
128 return IB_LINK_LAYER_INFINIBAND;
129 case MLX5_CAP_PORT_TYPE_ETH:
130 return IB_LINK_LAYER_ETHERNET;
131 default:
132 return IB_LINK_LAYER_UNSPECIFIED;
133 }
134}
135
ebd61f68
AS		 136static enum rdma_link_layer
137mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
138{
139 struct mlx5_ib_dev *dev = to_mdev(device);
140 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
141
142 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
143}
144
fd65f1b8
MS		 145static int get_port_state(struct ib_device *ibdev,
146 u8 port_num,
147 enum ib_port_state *state)
148{
149 struct ib_port_attr attr;
150 int ret;
151
152 memset(&attr, 0, sizeof(attr));
3023a1e9 153 ret = ibdev->ops.query_port(ibdev, port_num, &attr);
fd65f1b8
MS		 154 if (!ret)
155 *state = attr.state;
156 return ret;
157}
158
fc24fc5e
AS		 159static int mlx5_netdev_event(struct notifier_block *this,
160 unsigned long event, void *ptr)
161{
7fd8aefb 162 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
fc24fc5e 163 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
7fd8aefb
DJ		 164 u8 port_num = roce->native_port_num;
165 struct mlx5_core_dev *mdev;
166 struct mlx5_ib_dev *ibdev;
167
168 ibdev = roce->dev;
32f69e4b
DJ		 169 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
170 if (!mdev)
171 return NOTIFY_DONE;
fc24fc5e 172
5ec8c83e
AH		 173 switch (event) {
174 case NETDEV_REGISTER:
7fd8aefb 175 write_lock(&roce->netdev_lock);
bcf87f1d
MB		 176 if (ibdev->rep) {
177 struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch;
178 struct net_device *rep_ndev;
179
180 rep_ndev = mlx5_ib_get_rep_netdev(esw,
181 ibdev->rep->vport);
182 if (rep_ndev == ndev)
842a9c83 183 roce->netdev = ndev;
84a6a7a9 184 } else if (ndev->dev.parent == &mdev->pdev->dev) {
842a9c83 185 roce->netdev = ndev;
bcf87f1d 186 }
7fd8aefb 187 write_unlock(&roce->netdev_lock);
5ec8c83e 188 break;
fc24fc5e 189
842a9c83
OG		 190 case NETDEV_UNREGISTER:
191 write_lock(&roce->netdev_lock);
192 if (roce->netdev == ndev)
193 roce->netdev = NULL;
194 write_unlock(&roce->netdev_lock);
195 break;
196
fd65f1b8 197 case NETDEV_CHANGE:
5ec8c83e 198 case NETDEV_UP:
88621dfe 199 case NETDEV_DOWN: {
7fd8aefb 200 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe
AH		 201 struct net_device *upper = NULL;
202
203 if (lag_ndev) {
204 upper = netdev_master_upper_dev_get(lag_ndev);
205 dev_put(lag_ndev);
206 }
207
7fd8aefb 208 if ((upper == ndev || (!upper && ndev == roce->netdev))
88621dfe 209 && ibdev->ib_active) {
626bc02d 210 struct ib_event ibev = { };
fd65f1b8 211 enum ib_port_state port_state;
5ec8c83e 212
7fd8aefb
DJ		 213 if (get_port_state(&ibdev->ib_dev, port_num,
214 &port_state))
215 goto done;
fd65f1b8 216
7fd8aefb
DJ		 217 if (roce->last_port_state == port_state)
218 goto done;
fd65f1b8 219
7fd8aefb 220 roce->last_port_state = port_state;
5ec8c83e 221 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 222 if (port_state == IB_PORT_DOWN)
223 ibev.event = IB_EVENT_PORT_ERR;
224 else if (port_state == IB_PORT_ACTIVE)
225 ibev.event = IB_EVENT_PORT_ACTIVE;
226 else
7fd8aefb 227 goto done;
fd65f1b8 228
7fd8aefb 229 ibev.element.port_num = port_num;
5ec8c83e
AH		 230 ib_dispatch_event(&ibev);
231 }
232 break;
88621dfe 233 }
fc24fc5e 234
5ec8c83e
AH		 235 default:
236 break;
237 }
7fd8aefb 238done:
32f69e4b 239 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 240 return NOTIFY_DONE;
241}
242
243static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
244 u8 port_num)
245{
246 struct mlx5_ib_dev *ibdev = to_mdev(device);
247 struct net_device *ndev;
32f69e4b
DJ		 248 struct mlx5_core_dev *mdev;
249
250 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
251 if (!mdev)
252 return NULL;
fc24fc5e 253
32f69e4b 254 ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe 255 if (ndev)
32f69e4b 256 goto out;
88621dfe 257
fc24fc5e
AS		 258 /* Ensure ndev does not disappear before we invoke dev_hold()
259 */
7fd8aefb
DJ		 260 read_lock(&ibdev->roce[port_num - 1].netdev_lock);
261 ndev = ibdev->roce[port_num - 1].netdev;
fc24fc5e
AS		 262 if (ndev)
263 dev_hold(ndev);
7fd8aefb 264 read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
fc24fc5e 265
32f69e4b
DJ		 266out:
267 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 268 return ndev;
269}
270
32f69e4b
DJ		 271struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
272 u8 ib_port_num,
273 u8 *native_port_num)
274{
275 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
276 ib_port_num);
277 struct mlx5_core_dev *mdev = NULL;
278 struct mlx5_ib_multiport_info *mpi;
279 struct mlx5_ib_port *port;
280
210b1f78
MB		 281 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
282 ll != IB_LINK_LAYER_ETHERNET) {
283 if (native_port_num)
284 *native_port_num = ib_port_num;
285 return ibdev->mdev;
286 }
287
32f69e4b
DJ		 288 if (native_port_num)
289 *native_port_num = 1;
290
32f69e4b
DJ		 291 port = &ibdev->port[ib_port_num - 1];
292 if (!port)
293 return NULL;
294
295 spin_lock(&port->mp.mpi_lock);
296 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
297 if (mpi && !mpi->unaffiliate) {
298 mdev = mpi->mdev;
299 /* If it's the master no need to refcount, it'll exist
300 * as long as the ib_dev exists.
301 */
302 if (!mpi->is_master)
303 mpi->mdev_refcnt++;
304 }
305 spin_unlock(&port->mp.mpi_lock);
306
307 return mdev;
308}
309
310void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
311{
312 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
313 port_num);
314 struct mlx5_ib_multiport_info *mpi;
315 struct mlx5_ib_port *port;
316
317 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
318 return;
319
320 port = &ibdev->port[port_num - 1];
321
322 spin_lock(&port->mp.mpi_lock);
323 mpi = ibdev->port[port_num - 1].mp.mpi;
324 if (mpi->is_master)
325 goto out;
326
327 mpi->mdev_refcnt--;
328 if (mpi->unaffiliate)
329 complete(&mpi->unref_comp);
330out:
331 spin_unlock(&port->mp.mpi_lock);
332}
333
f1b65df5
NO		 334static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
335 u8 *active_width)
336{
337 switch (eth_proto_oper) {
338 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
339 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
340 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
341 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
342 *active_width = IB_WIDTH_1X;
343 *active_speed = IB_SPEED_SDR;
344 break;
345 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
346 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
347 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
348 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
349 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
350 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
351 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
352 *active_width = IB_WIDTH_1X;
353 *active_speed = IB_SPEED_QDR;
354 break;
355 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
356 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
357 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
358 *active_width = IB_WIDTH_1X;
359 *active_speed = IB_SPEED_EDR;
360 break;
361 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
362 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
363 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
364 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
365 *active_width = IB_WIDTH_4X;
366 *active_speed = IB_SPEED_QDR;
367 break;
368 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
369 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
370 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
371 *active_width = IB_WIDTH_1X;
372 *active_speed = IB_SPEED_HDR;
373 break;
374 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
375 *active_width = IB_WIDTH_4X;
376 *active_speed = IB_SPEED_FDR;
377 break;
378 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
379 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
380 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
381 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
382 *active_width = IB_WIDTH_4X;
383 *active_speed = IB_SPEED_EDR;
384 break;
385 default:
386 return -EINVAL;
387 }
388
389 return 0;
390}
391
095b0927
IT		 392static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
393 struct ib_port_attr *props)
3f89a643
AS		 394{
395 struct mlx5_ib_dev *dev = to_mdev(device);
da005f9f 396 struct mlx5_core_dev *mdev;
88621dfe 397 struct net_device *ndev, *upper;
3f89a643 398 enum ib_mtu ndev_ib_mtu;
b3cbd6f0 399 bool put_mdev = true;
c876a1b7 400 u16 qkey_viol_cntr;
f1b65df5 401 u32 eth_prot_oper;
b3cbd6f0 402 u8 mdev_port_num;
095b0927 403 int err;
3f89a643 404
b3cbd6f0
DJ		 405 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
406 if (!mdev) {
407 /* This means the port isn't affiliated yet. Get the
408 * info for the master port instead.
409 */
410 put_mdev = false;
411 mdev = dev->mdev;
412 mdev_port_num = 1;
413 port_num = 1;
414 }
415
f1b65df5
NO		 416 /* Possible bad flows are checked before filling out props so in case
417 * of an error it will still be zeroed out.
50f22fd8 418 */
b3cbd6f0
DJ		 419 err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper,
420 mdev_port_num);
095b0927 421 if (err)
b3cbd6f0 422 goto out;
f1b65df5 423
7672ed33
HL		 424 props->active_width = IB_WIDTH_4X;
425 props->active_speed = IB_SPEED_QDR;
426
f1b65df5
NO		 427 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
428 &props->active_width);
3f89a643 429
2f944c0f
JG		 430 props->port_cap_flags |= IB_PORT_CM_SUP;
431 props->ip_gids = true;
3f89a643
AS		 432
433 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
434 roce_address_table_size);
435 props->max_mtu = IB_MTU_4096;
436 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
437 props->pkey_tbl_len = 1;
438 props->state = IB_PORT_DOWN;
439 props->phys_state = 3;
440
b3cbd6f0 441 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
c876a1b7 442 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643 443
b3cbd6f0
DJ		 444 /* If this is a stub query for an unaffiliated port stop here */
445 if (!put_mdev)
446 goto out;
447
3f89a643
AS		 448 ndev = mlx5_ib_get_netdev(device, port_num);
449 if (!ndev)
b3cbd6f0 450 goto out;
3f89a643 451
7c34ec19 452 if (dev->lag_active) {
88621dfe
AH		 453 rcu_read_lock();
454 upper = netdev_master_upper_dev_get_rcu(ndev);
455 if (upper) {
456 dev_put(ndev);
457 ndev = upper;
458 dev_hold(ndev);
459 }
460 rcu_read_unlock();
461 }
462
3f89a643
AS		 463 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
464 props->state = IB_PORT_ACTIVE;
465 props->phys_state = 5;
466 }
467
468 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
469
470 dev_put(ndev);
471
472 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
b3cbd6f0
DJ		 473out:
474 if (put_mdev)
475 mlx5_ib_put_native_port_mdev(dev, port_num);
476 return err;
3f89a643
AS		 477}
478
095b0927
IT		 479static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
480 unsigned int index, const union ib_gid *gid,
481 const struct ib_gid_attr *attr)
3cca2606 482{
095b0927
IT		 483 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
484 u8 roce_version = 0;
485 u8 roce_l3_type = 0;
486 bool vlan = false;
487 u8 mac[ETH_ALEN];
488 u16 vlan_id = 0;
489
490 if (gid) {
491 gid_type = attr->gid_type;
492 ether_addr_copy(mac, attr->ndev->dev_addr);
493
494 if (is_vlan_dev(attr->ndev)) {
495 vlan = true;
496 vlan_id = vlan_dev_vlan_id(attr->ndev);
497 }
3cca2606
AS		 498 }
499
095b0927 500 switch (gid_type) {
3cca2606 501 case IB_GID_TYPE_IB:
095b0927 502 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 503 break;
504 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 505 roce_version = MLX5_ROCE_VERSION_2;
506 if (ipv6_addr_v4mapped((void *)gid))
507 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
508 else
509 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 510 break;
511
512 default:
095b0927 513 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 514 }
515
095b0927
IT		 516 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
517 roce_l3_type, gid->raw, mac, vlan,
cfe4e37f 518 vlan_id, port_num);
3cca2606
AS		 519}
520
f4df9a7c 521static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
3cca2606
AS		 522 __always_unused void **context)
523{
414448d2 524 return set_roce_addr(to_mdev(attr->device), attr->port_num,
f4df9a7c 525 attr->index, &attr->gid, attr);
3cca2606
AS		 526}
527
414448d2
PP		 528static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
529 __always_unused void **context)
3cca2606 530{
414448d2
PP		 531 return set_roce_addr(to_mdev(attr->device), attr->port_num,
532 attr->index, NULL, NULL);
3cca2606
AS		 533}
534
47ec3866
PP		 535__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
536 const struct ib_gid_attr *attr)
2811ba51 537{
47ec3866 538 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
2811ba51
AS		 539 return 0;
540
541 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
542}
543
1b5daf11
MD		 544static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
545{
7fae6655
NO		 546 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
547 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
548 return 0;
1b5daf11
MD		 549}
550
551enum {
552 MLX5_VPORT_ACCESS_METHOD_MAD,
553 MLX5_VPORT_ACCESS_METHOD_HCA,
554 MLX5_VPORT_ACCESS_METHOD_NIC,
555};
556
557static int mlx5_get_vport_access_method(struct ib_device *ibdev)
558{
559 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
560 return MLX5_VPORT_ACCESS_METHOD_MAD;
561
ebd61f68 562 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 563 IB_LINK_LAYER_ETHERNET)
564 return MLX5_VPORT_ACCESS_METHOD_NIC;
565
566 return MLX5_VPORT_ACCESS_METHOD_HCA;
567}
568
da7525d2 569static void get_atomic_caps(struct mlx5_ib_dev *dev,
776a3906 570 u8 atomic_size_qp,
da7525d2
EBE		 571 struct ib_device_attr *props)
572{
573 u8 tmp;
574 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
da7525d2 575 u8 atomic_req_8B_endianness_mode =
bd10838a 576 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 577
578 /* Check if HW supports 8 bytes standard atomic operations and capable
579 * of host endianness respond
580 */
581 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
582 if (((atomic_operations & tmp) == tmp) &&
583 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
584 (atomic_req_8B_endianness_mode)) {
585 props->atomic_cap = IB_ATOMIC_HCA;
586 } else {
587 props->atomic_cap = IB_ATOMIC_NONE;
588 }
589}
590
776a3906
MS		 591static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
592 struct ib_device_attr *props)
593{
594 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
595
596 get_atomic_caps(dev, atomic_size_qp, props);
597}
598
599static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
600 struct ib_device_attr *props)
601{
602 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
603
604 get_atomic_caps(dev, atomic_size_qp, props);
605}
606
607bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
608{
609 struct ib_device_attr props = {};
610
611 get_atomic_caps_dc(dev, &props);
612 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
613}
1b5daf11
MD		 614static int mlx5_query_system_image_guid(struct ib_device *ibdev,
615 __be64 *sys_image_guid)
616{
617 struct mlx5_ib_dev *dev = to_mdev(ibdev);
618 struct mlx5_core_dev *mdev = dev->mdev;
619 u64 tmp;
620 int err;
621
622 switch (mlx5_get_vport_access_method(ibdev)) {
623 case MLX5_VPORT_ACCESS_METHOD_MAD:
624 return mlx5_query_mad_ifc_system_image_guid(ibdev,
625 sys_image_guid);
626
627 case MLX5_VPORT_ACCESS_METHOD_HCA:
628 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 629 break;
630
631 case MLX5_VPORT_ACCESS_METHOD_NIC:
632 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
633 break;
1b5daf11
MD		 634
635 default:
636 return -EINVAL;
637 }
3f89a643
AS		 638
639 if (!err)
640 *sys_image_guid = cpu_to_be64(tmp);
641
642 return err;
643
1b5daf11
MD		 644}
645
646static int mlx5_query_max_pkeys(struct ib_device *ibdev,
647 u16 *max_pkeys)
648{
649 struct mlx5_ib_dev *dev = to_mdev(ibdev);
650 struct mlx5_core_dev *mdev = dev->mdev;
651
652 switch (mlx5_get_vport_access_method(ibdev)) {
653 case MLX5_VPORT_ACCESS_METHOD_MAD:
654 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
655
656 case MLX5_VPORT_ACCESS_METHOD_HCA:
657 case MLX5_VPORT_ACCESS_METHOD_NIC:
658 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
659 pkey_table_size));
660 return 0;
661
662 default:
663 return -EINVAL;
664 }
665}
666
667static int mlx5_query_vendor_id(struct ib_device *ibdev,
668 u32 *vendor_id)
669{
670 struct mlx5_ib_dev *dev = to_mdev(ibdev);
671
672 switch (mlx5_get_vport_access_method(ibdev)) {
673 case MLX5_VPORT_ACCESS_METHOD_MAD:
674 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
675
676 case MLX5_VPORT_ACCESS_METHOD_HCA:
677 case MLX5_VPORT_ACCESS_METHOD_NIC:
678 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
679
680 default:
681 return -EINVAL;
682 }
683}
684
685static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
686 __be64 *node_guid)
687{
688 u64 tmp;
689 int err;
690
691 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
692 case MLX5_VPORT_ACCESS_METHOD_MAD:
693 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
694
695 case MLX5_VPORT_ACCESS_METHOD_HCA:
696 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 697 break;
698
699 case MLX5_VPORT_ACCESS_METHOD_NIC:
700 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
701 break;
1b5daf11
MD		 702
703 default:
704 return -EINVAL;
705 }
3f89a643
AS		 706
707 if (!err)
708 *node_guid = cpu_to_be64(tmp);
709
710 return err;
1b5daf11
MD		 711}
712
713struct mlx5_reg_node_desc {
bd99fdea 714 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 715};
716
717static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
718{
719 struct mlx5_reg_node_desc in;
720
721 if (mlx5_use_mad_ifc(dev))
722 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
723
724 memset(&in, 0, sizeof(in));
725
726 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
727 sizeof(struct mlx5_reg_node_desc),
728 MLX5_REG_NODE_DESC, 0, 0);
729}
730
e126ba97 731static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 732 struct ib_device_attr *props,
733 struct ib_udata *uhw)
e126ba97
EC		 734{
735 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 736 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 737 int err = -ENOMEM;
288c01b7 738 int max_sq_desc;
e126ba97
EC		 739 int max_rq_sg;
740 int max_sq_sg;
e0238a6a 741 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
85c7c014 742 bool raw_support = !mlx5_core_mp_enabled(mdev);
402ca536
BW		 743 struct mlx5_ib_query_device_resp resp = {};
744 size_t resp_len;
745 u64 max_tso;
e126ba97 746
402ca536
BW		 747 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
748 if (uhw->outlen && uhw->outlen < resp_len)
749 return -EINVAL;
750 else
751 resp.response_length = resp_len;
752
753 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 754 return -EINVAL;
755
1b5daf11
MD		 756 memset(props, 0, sizeof(*props));
757 err = mlx5_query_system_image_guid(ibdev,
758 &props->sys_image_guid);
759 if (err)
760 return err;
e126ba97 761
1b5daf11 762 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 763 if (err)
1b5daf11 764 return err;
e126ba97 765
1b5daf11
MD		 766 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
767 if (err)
768 return err;
e126ba97 769
9603b61d
JM		 770 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
771 (fw_rev_min(dev->mdev) << 16) |
772 fw_rev_sub(dev->mdev);
e126ba97
EC		 773 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
774 IB_DEVICE_PORT_ACTIVE_EVENT |
775 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 776 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 777
778 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 779 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 780 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 781 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 782 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 783 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 784 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 785 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 786 if (MLX5_CAP_GEN(mdev, imaicl)) {
787 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
788 IB_DEVICE_MEM_WINDOW_TYPE_2B;
789 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 790 /* We support 'Gappy' memory registration too */
791 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 792 }
e126ba97 793 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 794 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 795 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
796 /* At this stage no support for signature handover */
797 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
798 IB_PROT_T10DIF_TYPE_2 |
799 IB_PROT_T10DIF_TYPE_3;
800 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
801 IB_GUARD_T10DIF_CSUM;
802 }
938fe83c 803 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 804 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 805
85c7c014 806 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
e8161334
NO		 807 if (MLX5_CAP_ETH(mdev, csum_cap)) {
808 /* Legacy bit to support old userspace libraries */
88115fe7 809 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 810 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
811 }
812
813 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
814 props->raw_packet_caps |=
815 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 816
402ca536
BW		 817 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
818 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
819 if (max_tso) {
820 resp.tso_caps.max_tso = 1 << max_tso;
821 resp.tso_caps.supported_qpts |=
822 1 << IB_QPT_RAW_PACKET;
823 resp.response_length += sizeof(resp.tso_caps);
824 }
825 }
31f69a82
YH		 826
827 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
828 resp.rss_caps.rx_hash_function =
829 MLX5_RX_HASH_FUNC_TOEPLITZ;
830 resp.rss_caps.rx_hash_fields_mask =
831 MLX5_RX_HASH_SRC_IPV4 |
832 MLX5_RX_HASH_DST_IPV4 |
833 MLX5_RX_HASH_SRC_IPV6 |
834 MLX5_RX_HASH_DST_IPV6 |
835 MLX5_RX_HASH_SRC_PORT_TCP |
836 MLX5_RX_HASH_DST_PORT_TCP |
837 MLX5_RX_HASH_SRC_PORT_UDP |
4e2b53a5
MG		 838 MLX5_RX_HASH_DST_PORT_UDP |
839 MLX5_RX_HASH_INNER;
2d93fc85
MB		 840 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
841 MLX5_ACCEL_IPSEC_CAP_DEVICE)
842 resp.rss_caps.rx_hash_fields_mask |=
843 MLX5_RX_HASH_IPSEC_SPI;
31f69a82
YH		 844 resp.response_length += sizeof(resp.rss_caps);
845 }
846 } else {
847 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
848 resp.response_length += sizeof(resp.tso_caps);
849 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
850 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 851 }
852
f0313965
ES		 853 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
854 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
855 props->device_cap_flags |= IB_DEVICE_UD_TSO;
856 }
857
03404e8a 858 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
85c7c014
DJ		 859 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
860 raw_support)
03404e8a
MG		 861 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
862
1d54f890
YH		 863 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
864 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
865 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
866
cff5a0f3 867 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
85c7c014
DJ		 868 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
869 raw_support) {
e8161334 870 /* Legacy bit to support old userspace libraries */
cff5a0f3 871 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 872 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
873 }
cff5a0f3 874
24da0016
AL		 875 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
876 props->max_dm_size =
877 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
878 }
879
da6d6ba3
MG		 880 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
881 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
882
b1383aa6
NO		 883 if (MLX5_CAP_GEN(mdev, end_pad))
884 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
885
1b5daf11
MD		 886 props->vendor_part_id = mdev->pdev->device;
887 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 888
889 props->max_mr_size = ~0ull;
e0238a6a 890 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 891 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
892 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
893 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
894 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 895 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
896 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
897 sizeof(struct mlx5_wqe_raddr_seg)) /
898 sizeof(struct mlx5_wqe_data_seg);
33023fb8
SW		 899 props->max_send_sge = max_sq_sg;
900 props->max_recv_sge = max_rq_sg;
986ef95e 901 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 902 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 903 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 904 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
905 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
906 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
907 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
908 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
909 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
910 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 911 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 912 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 913 props->max_fast_reg_page_list_len =
914 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
776a3906 915 get_atomic_caps_qp(dev, props);
81bea28f 916 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 917 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
918 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 919 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
920 props->max_mcast_grp;
921 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 922 props->max_ah = INT_MAX;
7c60bcbb
MB		 923 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
924 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 925
e502b8b0
LR		 926 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
927 if (MLX5_CAP_GEN(mdev, pg))
928 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
929 props->odp_caps = dev->odp_caps;
930 }
8cdd312c 931
051f2630
LR		 932 if (MLX5_CAP_GEN(mdev, cd))
933 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
934
eff901d3
EC		 935 if (!mlx5_core_is_pf(mdev))
936 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
937
31f69a82 938 if (mlx5_ib_port_link_layer(ibdev, 1) ==
85c7c014 939 IB_LINK_LAYER_ETHERNET && raw_support) {
31f69a82
YH		 940 props->rss_caps.max_rwq_indirection_tables =
941 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
942 props->rss_caps.max_rwq_indirection_table_size =
943 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
944 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
945 props->max_wq_type_rq =
946 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
947 }
948
eb761894 949 if (MLX5_CAP_GEN(mdev, tag_matching)) {
78b1beb0
LR		 950 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
951 props->tm_caps.max_num_tags =
eb761894 952 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
78b1beb0
LR		 953 props->tm_caps.flags = IB_TM_CAP_RC;
954 props->tm_caps.max_ops =
eb761894 955 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
78b1beb0 956 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
eb761894
AK		 957 }
958
87ab3f52
YC		 959 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
960 props->cq_caps.max_cq_moderation_count =
961 MLX5_MAX_CQ_COUNT;
962 props->cq_caps.max_cq_moderation_period =
963 MLX5_MAX_CQ_PERIOD;
964 }
965
7e43a2a5 966 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
7e43a2a5 967 resp.response_length += sizeof(resp.cqe_comp_caps);
572f46bf
YC		 968
969 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
970 resp.cqe_comp_caps.max_num =
971 MLX5_CAP_GEN(dev->mdev,
972 cqe_compression_max_num);
973
974 resp.cqe_comp_caps.supported_format =
975 MLX5_IB_CQE_RES_FORMAT_HASH |
976 MLX5_IB_CQE_RES_FORMAT_CSUM;
6f1006a4
YC		 977
978 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
979 resp.cqe_comp_caps.supported_format |=
980 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
572f46bf 981 }
7e43a2a5
BW		 982 }
983
85c7c014
DJ		 984 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
985 raw_support) {
d949167d
BW		 986 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
987 MLX5_CAP_GEN(mdev, qos)) {
988 resp.packet_pacing_caps.qp_rate_limit_max =
989 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
990 resp.packet_pacing_caps.qp_rate_limit_min =
991 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
992 resp.packet_pacing_caps.supported_qpts |=
993 1 << IB_QPT_RAW_PACKET;
61147f39
BW		 994 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
995 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
996 resp.packet_pacing_caps.cap_flags |=
997 MLX5_IB_PP_SUPPORT_BURST;
d949167d
BW		 998 }
999 resp.response_length += sizeof(resp.packet_pacing_caps);
1000 }
1001
9f885201
LR		 1002 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
1003 uhw->outlen)) {
795b609c
BW		 1004 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1005 resp.mlx5_ib_support_multi_pkt_send_wqes =
1006 MLX5_IB_ALLOW_MPW;
050da902
BW		 1007
1008 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1009 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1010 MLX5_IB_SUPPORT_EMPW;
1011
9f885201
LR		 1012 resp.response_length +=
1013 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1014 }
1015
de57f2ad
GL		 1016 if (field_avail(typeof(resp), flags, uhw->outlen)) {
1017 resp.response_length += sizeof(resp.flags);
7a0c8f42 1018
de57f2ad
GL		 1019 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1020 resp.flags |=
1021 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
7a0c8f42
GL		 1022
1023 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1024 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
7e11b911
DG		 1025 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1026 resp.flags |=
1027 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
de57f2ad 1028 }
9f885201 1029
96dc3fc5
NO		 1030 if (field_avail(typeof(resp), sw_parsing_caps,
1031 uhw->outlen)) {
1032 resp.response_length += sizeof(resp.sw_parsing_caps);
1033 if (MLX5_CAP_ETH(mdev, swp)) {
1034 resp.sw_parsing_caps.sw_parsing_offloads |=
1035 MLX5_IB_SW_PARSING;
1036
1037 if (MLX5_CAP_ETH(mdev, swp_csum))
1038 resp.sw_parsing_caps.sw_parsing_offloads |=
1039 MLX5_IB_SW_PARSING_CSUM;
1040
1041 if (MLX5_CAP_ETH(mdev, swp_lso))
1042 resp.sw_parsing_caps.sw_parsing_offloads |=
1043 MLX5_IB_SW_PARSING_LSO;
1044
1045 if (resp.sw_parsing_caps.sw_parsing_offloads)
1046 resp.sw_parsing_caps.supported_qpts =
1047 BIT(IB_QPT_RAW_PACKET);
1048 }
1049 }
1050
85c7c014
DJ		 1051 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1052 raw_support) {
b4f34597
NO		 1053 resp.response_length += sizeof(resp.striding_rq_caps);
1054 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1055 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1056 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1057 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1058 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1059 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1060 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1061 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1062 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1063 resp.striding_rq_caps.supported_qpts =
1064 BIT(IB_QPT_RAW_PACKET);
1065 }
1066 }
1067
f95ef6cb
MG		 1068 if (field_avail(typeof(resp), tunnel_offloads_caps,
1069 uhw->outlen)) {
1070 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1071 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1072 resp.tunnel_offloads_caps |=
1073 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1074 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1075 resp.tunnel_offloads_caps |=
1076 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1077 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1078 resp.tunnel_offloads_caps |=
1079 MLX5_IB_TUNNELED_OFFLOADS_GRE;
e818e255
AL		 1080 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1081 MLX5_FLEX_PROTO_CW_MPLS_GRE)
1082 resp.tunnel_offloads_caps |=
1083 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1084 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1085 MLX5_FLEX_PROTO_CW_MPLS_UDP)
1086 resp.tunnel_offloads_caps |=
1087 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
f95ef6cb
MG		 1088 }
1089
402ca536
BW		 1090 if (uhw->outlen) {
1091 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1092
1093 if (err)
1094 return err;
1095 }
1096
1b5daf11 1097 return 0;
e126ba97
EC		 1098}
1099
1b5daf11
MD		 1100enum mlx5_ib_width {
1101 MLX5_IB_WIDTH_1X = 1 << 0,
1102 MLX5_IB_WIDTH_2X = 1 << 1,
1103 MLX5_IB_WIDTH_4X = 1 << 2,
1104 MLX5_IB_WIDTH_8X = 1 << 3,
1105 MLX5_IB_WIDTH_12X = 1 << 4
1106};
1107
db7a691a 1108static void translate_active_width(struct ib_device *ibdev, u8 active_width,
1b5daf11 1109 u8 *ib_width)
e126ba97
EC		 1110{
1111 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11 1112
db7a691a 1113 if (active_width & MLX5_IB_WIDTH_1X)
1b5daf11 1114 *ib_width = IB_WIDTH_1X;
d764970b
MG		 1115 else if (active_width & MLX5_IB_WIDTH_2X)
1116 *ib_width = IB_WIDTH_2X;
db7a691a 1117 else if (active_width & MLX5_IB_WIDTH_4X)
1b5daf11 1118 *ib_width = IB_WIDTH_4X;
db7a691a 1119 else if (active_width & MLX5_IB_WIDTH_8X)
1b5daf11 1120 *ib_width = IB_WIDTH_8X;
db7a691a 1121 else if (active_width & MLX5_IB_WIDTH_12X)
1b5daf11 1122 *ib_width = IB_WIDTH_12X;
db7a691a
MG		 1123 else {
1124 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1b5daf11 1125 (int)active_width);
db7a691a 1126 *ib_width = IB_WIDTH_4X;
e126ba97
EC		 1127 }
1128
db7a691a 1129 return;
1b5daf11 1130}
e126ba97 1131
1b5daf11
MD		 1132static int mlx5_mtu_to_ib_mtu(int mtu)
1133{
1134 switch (mtu) {
1135 case 256: return 1;
1136 case 512: return 2;
1137 case 1024: return 3;
1138 case 2048: return 4;
1139 case 4096: return 5;
1140 default:
1141 pr_warn("invalid mtu\n");
1142 return -1;
e126ba97 1143 }
1b5daf11 1144}
e126ba97 1145
1b5daf11
MD		 1146enum ib_max_vl_num {
1147 __IB_MAX_VL_0 = 1,
1148 __IB_MAX_VL_0_1 = 2,
1149 __IB_MAX_VL_0_3 = 3,
1150 __IB_MAX_VL_0_7 = 4,
1151 __IB_MAX_VL_0_14 = 5,
1152};
e126ba97 1153
1b5daf11
MD		 1154enum mlx5_vl_hw_cap {
1155 MLX5_VL_HW_0 = 1,
1156 MLX5_VL_HW_0_1 = 2,
1157 MLX5_VL_HW_0_2 = 3,
1158 MLX5_VL_HW_0_3 = 4,
1159 MLX5_VL_HW_0_4 = 5,
1160 MLX5_VL_HW_0_5 = 6,
1161 MLX5_VL_HW_0_6 = 7,
1162 MLX5_VL_HW_0_7 = 8,
1163 MLX5_VL_HW_0_14 = 15
1164};
e126ba97 1165
1b5daf11
MD		 1166static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1167 u8 *max_vl_num)
1168{
1169 switch (vl_hw_cap) {
1170 case MLX5_VL_HW_0:
1171 *max_vl_num = __IB_MAX_VL_0;
1172 break;
1173 case MLX5_VL_HW_0_1:
1174 *max_vl_num = __IB_MAX_VL_0_1;
1175 break;
1176 case MLX5_VL_HW_0_3:
1177 *max_vl_num = __IB_MAX_VL_0_3;
1178 break;
1179 case MLX5_VL_HW_0_7:
1180 *max_vl_num = __IB_MAX_VL_0_7;
1181 break;
1182 case MLX5_VL_HW_0_14:
1183 *max_vl_num = __IB_MAX_VL_0_14;
1184 break;
e126ba97 1185
1b5daf11
MD		 1186 default:
1187 return -EINVAL;
e126ba97 1188 }
e126ba97 1189
1b5daf11 1190 return 0;
e126ba97
EC		 1191}
1192
1b5daf11
MD		 1193static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1194 struct ib_port_attr *props)
e126ba97 1195{
1b5daf11
MD		 1196 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1197 struct mlx5_core_dev *mdev = dev->mdev;
1198 struct mlx5_hca_vport_context *rep;
046339ea
SM		 1199 u16 max_mtu;
1200 u16 oper_mtu;
1b5daf11
MD		 1201 int err;
1202 u8 ib_link_width_oper;
1203 u8 vl_hw_cap;
e126ba97 1204
1b5daf11
MD		 1205 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1206 if (!rep) {
1207 err = -ENOMEM;
e126ba97 1208 goto out;
e126ba97 1209 }
e126ba97 1210
c4550c63 1211 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 1212
1b5daf11 1213 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 1214 if (err)
1215 goto out;
1216
1b5daf11
MD		 1217 props->lid = rep->lid;
1218 props->lmc = rep->lmc;
1219 props->sm_lid = rep->sm_lid;
1220 props->sm_sl = rep->sm_sl;
1221 props->state = rep->vport_state;
1222 props->phys_state = rep->port_physical_state;
1223 props->port_cap_flags = rep->cap_mask1;
1224 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1225 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1226 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1227 props->bad_pkey_cntr = rep->pkey_violation_counter;
1228 props->qkey_viol_cntr = rep->qkey_violation_counter;
1229 props->subnet_timeout = rep->subnet_timeout;
1230 props->init_type_reply = rep->init_type_reply;
e126ba97 1231
4106a758
MG		 1232 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1233 props->port_cap_flags2 = rep->cap_mask2;
1234
1b5daf11
MD		 1235 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1236 if (err)
e126ba97 1237 goto out;
e126ba97 1238
db7a691a
MG		 1239 translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1240
d5beb7f2 1241 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 1242 if (err)
1243 goto out;
1244
facc9699 1245 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 1246
1b5daf11 1247 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 1248
facc9699 1249 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 1250
1b5daf11 1251 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1252
1b5daf11
MD		 1253 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1254 if (err)
1255 goto out;
e126ba97 1256
1b5daf11
MD		 1257 err = translate_max_vl_num(ibdev, vl_hw_cap,
1258 &props->max_vl_num);
e126ba97 1259out:
1b5daf11 1260 kfree(rep);
e126ba97
EC		 1261 return err;
1262}
1263
1b5daf11
MD		 1264int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1265 struct ib_port_attr *props)
e126ba97 1266{
095b0927
IT		 1267 unsigned int count;
1268 int ret;
1269
1b5daf11
MD		 1270 switch (mlx5_get_vport_access_method(ibdev)) {
1271 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1272 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1273 break;
e126ba97 1274
1b5daf11 1275 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1276 ret = mlx5_query_hca_port(ibdev, port, props);
1277 break;
e126ba97 1278
3f89a643 1279 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1280 ret = mlx5_query_port_roce(ibdev, port, props);
1281 break;
3f89a643 1282
1b5daf11 1283 default:
095b0927
IT		 1284 ret = -EINVAL;
1285 }
1286
1287 if (!ret && props) {
b3cbd6f0
DJ		 1288 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1289 struct mlx5_core_dev *mdev;
1290 bool put_mdev = true;
1291
1292 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1293 if (!mdev) {
1294 /* If the port isn't affiliated yet query the master.
1295 * The master and slave will have the same values.
1296 */
1297 mdev = dev->mdev;
1298 port = 1;
1299 put_mdev = false;
1300 }
1301 count = mlx5_core_reserved_gids_count(mdev);
1302 if (put_mdev)
1303 mlx5_ib_put_native_port_mdev(dev, port);
095b0927 1304 props->gid_tbl_len -= count;
1b5daf11 1305 }
095b0927 1306 return ret;
1b5daf11 1307}
e126ba97 1308
8e6efa3a
MB		 1309static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1310 struct ib_port_attr *props)
1311{
1312 int ret;
1313
1314 /* Only link layer == ethernet is valid for representors */
1315 ret = mlx5_query_port_roce(ibdev, port, props);
1316 if (ret || !props)
1317 return ret;
1318
1319 /* We don't support GIDS */
1320 props->gid_tbl_len = 0;
1321
1322 return ret;
1323}
1324
1b5daf11
MD		 1325static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1326 union ib_gid *gid)
1327{
1328 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1329 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1330
1b5daf11
MD		 1331 switch (mlx5_get_vport_access_method(ibdev)) {
1332 case MLX5_VPORT_ACCESS_METHOD_MAD:
1333 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1334
1b5daf11
MD		 1335 case MLX5_VPORT_ACCESS_METHOD_HCA:
1336 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1337
1338 default:
1339 return -EINVAL;
1340 }
e126ba97 1341
e126ba97
EC		 1342}
1343
b3cbd6f0
DJ		 1344static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1345 u16 index, u16 *pkey)
1b5daf11
MD		 1346{
1347 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b3cbd6f0
DJ		 1348 struct mlx5_core_dev *mdev;
1349 bool put_mdev = true;
1350 u8 mdev_port_num;
1351 int err;
1b5daf11 1352
b3cbd6f0
DJ		 1353 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1354 if (!mdev) {
1355 /* The port isn't affiliated yet, get the PKey from the master
1356 * port. For RoCE the PKey tables will be the same.
1357 */
1358 put_mdev = false;
1359 mdev = dev->mdev;
1360 mdev_port_num = 1;
1361 }
1362
1363 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1364 index, pkey);
1365 if (put_mdev)
1366 mlx5_ib_put_native_port_mdev(dev, port);
1367
1368 return err;
1369}
1370
1371static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1372 u16 *pkey)
1373{
1b5daf11
MD		 1374 switch (mlx5_get_vport_access_method(ibdev)) {
1375 case MLX5_VPORT_ACCESS_METHOD_MAD:
1376 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1377
1378 case MLX5_VPORT_ACCESS_METHOD_HCA:
1379 case MLX5_VPORT_ACCESS_METHOD_NIC:
b3cbd6f0 1380 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1b5daf11
MD		 1381 default:
1382 return -EINVAL;
1383 }
1384}
e126ba97
EC		 1385
1386static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1387 struct ib_device_modify *props)
1388{
1389 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1390 struct mlx5_reg_node_desc in;
1391 struct mlx5_reg_node_desc out;
1392 int err;
1393
1394 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1395 return -EOPNOTSUPP;
1396
1397 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1398 return 0;
1399
1400 /*
1401 * If possible, pass node desc to FW, so it can generate
1402 * a 144 trap. If cmd fails, just ignore.
1403 */
bd99fdea 1404 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1405 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1406 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1407 if (err)
1408 return err;
1409
bd99fdea 1410 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1411
1412 return err;
1413}
1414
cdbe33d0
EC		 1415static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1416 u32 value)
1417{
1418 struct mlx5_hca_vport_context ctx = {};
b3cbd6f0
DJ		 1419 struct mlx5_core_dev *mdev;
1420 u8 mdev_port_num;
cdbe33d0
EC		 1421 int err;
1422
b3cbd6f0
DJ		 1423 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1424 if (!mdev)
1425 return -ENODEV;
1426
1427 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
cdbe33d0 1428 if (err)
b3cbd6f0 1429 goto out;
cdbe33d0
EC		 1430
1431 if (~ctx.cap_mask1_perm & mask) {
1432 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1433 mask, ctx.cap_mask1_perm);
b3cbd6f0
DJ		 1434 err = -EINVAL;
1435 goto out;
cdbe33d0
EC		 1436 }
1437
1438 ctx.cap_mask1 = value;
1439 ctx.cap_mask1_perm = mask;
b3cbd6f0
DJ		 1440 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1441 0, &ctx);
1442
1443out:
1444 mlx5_ib_put_native_port_mdev(dev, port_num);
cdbe33d0
EC		 1445
1446 return err;
1447}
1448
e126ba97
EC		 1449static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1450 struct ib_port_modify *props)
1451{
1452 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1453 struct ib_port_attr attr;
1454 u32 tmp;
1455 int err;
cdbe33d0
EC		 1456 u32 change_mask;
1457 u32 value;
1458 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1459 IB_LINK_LAYER_INFINIBAND);
1460
ec255879
MD		 1461 /* CM layer calls ib_modify_port() regardless of the link layer. For
1462 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1463 */
1464 if (!is_ib)
1465 return 0;
1466
cdbe33d0
EC		 1467 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1468 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1469 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1470 return set_port_caps_atomic(dev, port, change_mask, value);
1471 }
e126ba97
EC		 1472
1473 mutex_lock(&dev->cap_mask_mutex);
1474
c4550c63 1475 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1476 if (err)
1477 goto out;
1478
1479 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1480 ~props->clr_port_cap_mask;
1481
9603b61d 1482 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1483
1484out:
1485 mutex_unlock(&dev->cap_mask_mutex);
1486 return err;
1487}
1488
30aa60b3
EC		 1489static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1490{
1491 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1492 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1493}
1494
31a78a5a
YH		 1495static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1496{
1497 /* Large page with non 4k uar support might limit the dynamic size */
1498 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1499 return MLX5_MIN_DYN_BFREGS;
1500
1501 return MLX5_MAX_DYN_BFREGS;
1502}
1503
b037c29a
EC		 1504static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1505 struct mlx5_ib_alloc_ucontext_req_v2 *req,
31a78a5a 1506 struct mlx5_bfreg_info *bfregi)
b037c29a
EC		 1507{
1508 int uars_per_sys_page;
1509 int bfregs_per_sys_page;
1510 int ref_bfregs = req->total_num_bfregs;
1511
1512 if (req->total_num_bfregs == 0)
1513 return -EINVAL;
1514
1515 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1516 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1517
1518 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1519 return -ENOMEM;
1520
1521 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1522 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
31a78a5a 1523 /* This holds the required static allocation asked by the user */
b037c29a 1524 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
b037c29a
EC		 1525 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1526 return -EINVAL;
1527
31a78a5a
YH		 1528 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1529 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1530 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1531 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1532
1533 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
b037c29a
EC		 1534 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1535 lib_uar_4k ? "yes" : "no", ref_bfregs,
31a78a5a
YH		 1536 req->total_num_bfregs, bfregi->total_num_bfregs,
1537 bfregi->num_sys_pages);
b037c29a
EC		 1538
1539 return 0;
1540}
1541
1542static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1543{
1544 struct mlx5_bfreg_info *bfregi;
1545 int err;
1546 int i;
1547
1548 bfregi = &context->bfregi;
31a78a5a 1549 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
b037c29a
EC		 1550 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1551 if (err)
1552 goto error;
1553
1554 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1555 }
4ed131d0
YH		 1556
1557 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1558 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1559
b037c29a
EC		 1560 return 0;
1561
1562error:
1563 for (--i; i >= 0; i--)
1564 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1565 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1566
1567 return err;
1568}
1569
15177999
LR		 1570static void deallocate_uars(struct mlx5_ib_dev *dev,
1571 struct mlx5_ib_ucontext *context)
b037c29a
EC		 1572{
1573 struct mlx5_bfreg_info *bfregi;
b037c29a
EC		 1574 int i;
1575
1576 bfregi = &context->bfregi;
15177999 1577 for (i = 0; i < bfregi->num_sys_pages; i++)
4ed131d0 1578 if (i < bfregi->num_static_sys_pages ||
15177999
LR		 1579 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1580 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
b037c29a
EC		 1581}
1582
0042f9e4 1583int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
a560f1d9
MB		 1584{
1585 int err = 0;
1586
1587 mutex_lock(&dev->lb.mutex);
0042f9e4
MB		 1588 if (td)
1589 dev->lb.user_td++;
1590 if (qp)
1591 dev->lb.qps++;
1592
1593 if (dev->lb.user_td == 2 ||
1594 dev->lb.qps == 1) {
1595 if (!dev->lb.enabled) {
1596 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1597 dev->lb.enabled = true;
1598 }
1599 }
a560f1d9
MB		 1600
1601 mutex_unlock(&dev->lb.mutex);
1602
1603 return err;
1604}
1605
0042f9e4 1606void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
a560f1d9
MB		 1607{
1608 mutex_lock(&dev->lb.mutex);
0042f9e4
MB		 1609 if (td)
1610 dev->lb.user_td--;
1611 if (qp)
1612 dev->lb.qps--;
1613
1614 if (dev->lb.user_td == 1 &&
1615 dev->lb.qps == 0) {
1616 if (dev->lb.enabled) {
1617 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1618 dev->lb.enabled = false;
1619 }
1620 }
a560f1d9
MB		 1621
1622 mutex_unlock(&dev->lb.mutex);
1623}
1624
d2d19121
YH		 1625static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1626 u16 uid)
c85023e1
HN		 1627{
1628 int err;
1629
cfdeb893
LR		 1630 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1631 return 0;
1632
d2d19121 1633 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
c85023e1
HN		 1634 if (err)
1635 return err;
1636
1637 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1638 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1639 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1640 return err;
1641
0042f9e4 1642 return mlx5_ib_enable_lb(dev, true, false);
c85023e1
HN		 1643}
1644
d2d19121
YH		 1645static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1646 u16 uid)
c85023e1 1647{
cfdeb893
LR		 1648 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1649 return;
1650
d2d19121 1651 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
c85023e1
HN		 1652
1653 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1654 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1655 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1656 return;
1657
0042f9e4 1658 mlx5_ib_disable_lb(dev, true, false);
c85023e1
HN		 1659}
1660
e126ba97
EC		 1661static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1662 struct ib_udata *udata)
1663{
1664 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1665 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1666 struct mlx5_ib_alloc_ucontext_resp resp = {};
5c99eaec 1667 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1668 struct mlx5_ib_ucontext *context;
2f5ff264 1669 struct mlx5_bfreg_info *bfregi;
78c0f98c 1670 int ver;
e126ba97 1671 int err;
a168a41c
MD		 1672 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1673 max_cqe_version);
25bb36e7 1674 u32 dump_fill_mkey;
b037c29a 1675 bool lib_uar_4k;
e126ba97
EC		 1676
1677 if (!dev->ib_active)
1678 return ERR_PTR(-EAGAIN);
1679
e093111d 1680 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1681 ver = 0;
e093111d 1682 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1683 ver = 2;
1684 else
1685 return ERR_PTR(-EINVAL);
1686
e093111d 1687 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97
EC		 1688 if (err)
1689 return ERR_PTR(err);
1690
a8b92ca1
YH		 1691 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1692 return ERR_PTR(-EOPNOTSUPP);
78c0f98c 1693
f72300c5 1694 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 1695 return ERR_PTR(-EOPNOTSUPP);
1696
2f5ff264
EC		 1697 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1698 MLX5_NON_FP_BFREGS_PER_UAR);
1699 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
e126ba97
EC		 1700 return ERR_PTR(-EINVAL);
1701
938fe83c 1702 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1703 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1704 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1705 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1706 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1707 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1708 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1709 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1710 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1711 resp.cqe_version = min_t(__u8,
1712 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1713 req.max_cqe_version);
30aa60b3
EC		 1714 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1715 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1716 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1717 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1718 resp.response_length = min(offsetof(typeof(resp), response_length) +
1719 sizeof(resp.response_length), udata->outlen);
e126ba97 1720
c03faa56
MB		 1721 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1722 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1723 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1724 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1725 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1726 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1727 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1728 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1729 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1730 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1731 }
1732
e126ba97
EC		 1733 context = kzalloc(sizeof(*context), GFP_KERNEL);
1734 if (!context)
1735 return ERR_PTR(-ENOMEM);
1736
30aa60b3 1737 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1738 bfregi = &context->bfregi;
b037c29a
EC		 1739
1740 /* updates req->total_num_bfregs */
31a78a5a 1741 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
b037c29a 1742 if (err)
e126ba97 1743 goto out_ctx;
e126ba97 1744
b037c29a
EC		 1745 mutex_init(&bfregi->lock);
1746 bfregi->lib_uar_4k = lib_uar_4k;
31a78a5a 1747 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1748 GFP_KERNEL);
b037c29a 1749 if (!bfregi->count) {
e126ba97 1750 err = -ENOMEM;
b037c29a 1751 goto out_ctx;
e126ba97
EC		 1752 }
1753
b037c29a
EC		 1754 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1755 sizeof(*bfregi->sys_pages),
1756 GFP_KERNEL);
1757 if (!bfregi->sys_pages) {
e126ba97 1758 err = -ENOMEM;
b037c29a 1759 goto out_count;
e126ba97
EC		 1760 }
1761
b037c29a
EC		 1762 err = allocate_uars(dev, context);
1763 if (err)
1764 goto out_sys_pages;
e126ba97 1765
13859d5d
LR		 1766 if (ibdev->attrs.device_cap_flags & IB_DEVICE_ON_DEMAND_PAGING)
1767 context->ibucontext.invalidate_range =
1768 &mlx5_ib_invalidate_range;
b4cfe447 1769
a8b92ca1 1770 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
fb98153b 1771 err = mlx5_ib_devx_create(dev, true);
76dc5a84 1772 if (err < 0)
d2d19121 1773 goto out_uars;
76dc5a84 1774 context->devx_uid = err;
a8b92ca1
YH		 1775 }
1776
d2d19121
YH		 1777 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1778 context->devx_uid);
1779 if (err)
1780 goto out_devx;
1781
25bb36e7
YC		 1782 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1783 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1784 if (err)
8193abb6 1785 goto out_mdev;
25bb36e7
YC		 1786 }
1787
e126ba97
EC		 1788 INIT_LIST_HEAD(&context->db_page_list);
1789 mutex_init(&context->db_page_mutex);
1790
2f5ff264 1791 resp.tot_bfregs = req.total_num_bfregs;
508562d6 1792 resp.num_ports = dev->num_ports;
b368d7cb 1793
f72300c5
HA		 1794 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1795 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1796
402ca536 1797 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1798 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1799 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1800 resp.response_length += sizeof(resp.cmds_supp_uhw);
1801 }
1802
78984898
OG		 1803 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1804 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1805 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1806 resp.eth_min_inline++;
1807 }
1808 resp.response_length += sizeof(resp.eth_min_inline);
1809 }
1810
5c99eaec
FD		 1811 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1812 if (mdev->clock_info)
1813 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1814 resp.response_length += sizeof(resp.clock_info_versions);
1815 }
1816
bc5c6eed
NO		 1817 /*
1818 * We don't want to expose information from the PCI bar that is located
1819 * after 4096 bytes, so if the arch only supports larger pages, let's
1820 * pretend we don't support reading the HCA's core clock. This is also
1821 * forced by mmap function.
1822 */
de8d6e02
EC		 1823 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1824 if (PAGE_SIZE <= 4096) {
1825 resp.comp_mask |=
1826 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1827 resp.hca_core_clock_offset =
1828 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1829 }
5c99eaec 1830 resp.response_length += sizeof(resp.hca_core_clock_offset);
b368d7cb
MB		 1831 }
1832
30aa60b3
EC		 1833 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1834 resp.response_length += sizeof(resp.log_uar_size);
1835
1836 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1837 resp.response_length += sizeof(resp.num_uars_per_page);
1838
31a78a5a
YH		 1839 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1840 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1841 resp.response_length += sizeof(resp.num_dyn_bfregs);
1842 }
1843
25bb36e7
YC		 1844 if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) {
1845 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1846 resp.dump_fill_mkey = dump_fill_mkey;
1847 resp.comp_mask |=
1848 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1849 }
1850 resp.response_length += sizeof(resp.dump_fill_mkey);
1851 }
1852
b368d7cb 1853 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1854 if (err)
a8b92ca1 1855 goto out_mdev;
e126ba97 1856
2f5ff264
EC		 1857 bfregi->ver = ver;
1858 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1859 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1860 context->lib_caps = req.lib_caps;
1861 print_lib_caps(dev, context->lib_caps);
f72300c5 1862
7c34ec19 1863 if (dev->lag_active) {
c6a21c38
MD		 1864 u8 port = mlx5_core_native_port_num(dev->mdev);
1865
1866 atomic_set(&context->tx_port_affinity,
1867 atomic_add_return(
1868 1, &dev->roce[port].tx_port_affinity));
1869 }
1870
e126ba97
EC		 1871 return &context->ibucontext;
1872
a8b92ca1 1873out_mdev:
d2d19121
YH		 1874 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1875out_devx:
a8b92ca1 1876 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
76dc5a84 1877 mlx5_ib_devx_destroy(dev, context->devx_uid);
146d2f1a 1878
e126ba97 1879out_uars:
b037c29a 1880 deallocate_uars(dev, context);
e126ba97 1881
b037c29a
EC		 1882out_sys_pages:
1883 kfree(bfregi->sys_pages);
e126ba97 1884
b037c29a
EC		 1885out_count:
1886 kfree(bfregi->count);
e126ba97
EC		 1887
1888out_ctx:
1889 kfree(context);
b037c29a 1890
e126ba97
EC		 1891 return ERR_PTR(err);
1892}
1893
1894static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1895{
1896 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1897 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 1898 struct mlx5_bfreg_info *bfregi;
e126ba97 1899
f27a0d50
JG		 1900 /* All umem's must be destroyed before destroying the ucontext. */
1901 mutex_lock(&ibcontext->per_mm_list_lock);
1902 WARN_ON(!list_empty(&ibcontext->per_mm_list));
1903 mutex_unlock(&ibcontext->per_mm_list_lock);
a8b92ca1 1904
b037c29a 1905 bfregi = &context->bfregi;
d2d19121
YH		 1906 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1907
a8b92ca1 1908 if (context->devx_uid)
76dc5a84 1909 mlx5_ib_devx_destroy(dev, context->devx_uid);
146d2f1a 1910
b037c29a
EC		 1911 deallocate_uars(dev, context);
1912 kfree(bfregi->sys_pages);
2f5ff264 1913 kfree(bfregi->count);
e126ba97
EC		 1914 kfree(context);
1915
1916 return 0;
1917}
1918
b037c29a 1919static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
4ed131d0 1920 int uar_idx)
e126ba97 1921{
b037c29a
EC		 1922 int fw_uars_per_page;
1923
1924 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1925
4ed131d0 1926 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
e126ba97
EC		 1927}
1928
1929static int get_command(unsigned long offset)
1930{
1931 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1932}
1933
1934static int get_arg(unsigned long offset)
1935{
1936 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1937}
1938
1939static int get_index(unsigned long offset)
1940{
1941 return get_arg(offset);
1942}
1943
4ed131d0
YH		 1944/* Index resides in an extra byte to enable larger values than 255 */
1945static int get_extended_index(unsigned long offset)
1946{
1947 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1948}
1949
7c2344c3
MG		 1950
1951static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1952{
7c2344c3
MG		 1953}
1954
37aa5c36
GL		 1955static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1956{
1957 switch (cmd) {
1958 case MLX5_IB_MMAP_WC_PAGE:
1959 return "WC";
1960 case MLX5_IB_MMAP_REGULAR_PAGE:
1961 return "best effort WC";
1962 case MLX5_IB_MMAP_NC_PAGE:
1963 return "NC";
24da0016
AL		 1964 case MLX5_IB_MMAP_DEVICE_MEM:
1965 return "Device Memory";
37aa5c36
GL		 1966 default:
1967 return NULL;
1968 }
1969}
1970
5c99eaec
FD		 1971static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
1972 struct vm_area_struct *vma,
1973 struct mlx5_ib_ucontext *context)
1974{
5c99eaec
FD		 1975 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1976 return -EINVAL;
1977
1978 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
1979 return -EOPNOTSUPP;
1980
1981 if (vma->vm_flags & VM_WRITE)
1982 return -EPERM;
1983
1984 if (!dev->mdev->clock_info_page)
1985 return -EOPNOTSUPP;
1986
e2cd1d1a
JG		 1987 return rdma_user_mmap_page(&context->ibucontext, vma,
1988 dev->mdev->clock_info_page, PAGE_SIZE);
5c99eaec
FD		 1989}
1990
37aa5c36 1991static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 1992 struct vm_area_struct *vma,
1993 struct mlx5_ib_ucontext *context)
37aa5c36 1994{
2f5ff264 1995 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 1996 int err;
1997 unsigned long idx;
aa09ea6e 1998 phys_addr_t pfn;
37aa5c36 1999 pgprot_t prot;
4ed131d0
YH		 2000 u32 bfreg_dyn_idx = 0;
2001 u32 uar_index;
2002 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2003 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2004 bfregi->num_static_sys_pages;
b037c29a
EC		 2005
2006 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2007 return -EINVAL;
2008
4ed131d0
YH		 2009 if (dyn_uar)
2010 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2011 else
2012 idx = get_index(vma->vm_pgoff);
2013
2014 if (idx >= max_valid_idx) {
2015 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2016 idx, max_valid_idx);
b037c29a
EC		 2017 return -EINVAL;
2018 }
37aa5c36
GL		 2019
2020 switch (cmd) {
2021 case MLX5_IB_MMAP_WC_PAGE:
4ed131d0 2022 case MLX5_IB_MMAP_ALLOC_WC:
37aa5c36
GL		 2023/* Some architectures don't support WC memory */
2024#if defined(CONFIG_X86)
2025 if (!pat_enabled())
2026 return -EPERM;
2027#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2028 return -EPERM;
2029#endif
2030 /* fall through */
2031 case MLX5_IB_MMAP_REGULAR_PAGE:
2032 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2033 prot = pgprot_writecombine(vma->vm_page_prot);
2034 break;
2035 case MLX5_IB_MMAP_NC_PAGE:
2036 prot = pgprot_noncached(vma->vm_page_prot);
2037 break;
2038 default:
2039 return -EINVAL;
2040 }
2041
4ed131d0
YH		 2042 if (dyn_uar) {
2043 int uars_per_page;
2044
2045 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2046 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2047 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2048 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2049 bfreg_dyn_idx, bfregi->total_num_bfregs);
2050 return -EINVAL;
2051 }
2052
2053 mutex_lock(&bfregi->lock);
2054 /* Fail if uar already allocated, first bfreg index of each
2055 * page holds its count.
2056 */
2057 if (bfregi->count[bfreg_dyn_idx]) {
2058 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2059 mutex_unlock(&bfregi->lock);
2060 return -EINVAL;
2061 }
2062
2063 bfregi->count[bfreg_dyn_idx]++;
2064 mutex_unlock(&bfregi->lock);
2065
2066 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2067 if (err) {
2068 mlx5_ib_warn(dev, "UAR alloc failed\n");
2069 goto free_bfreg;
2070 }
2071 } else {
2072 uar_index = bfregi->sys_pages[idx];
2073 }
2074
2075 pfn = uar_index2pfn(dev, uar_index);
37aa5c36
GL		 2076 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2077
e2cd1d1a
JG		 2078 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2079 prot);
37aa5c36 2080 if (err) {
8f062287 2081 mlx5_ib_err(dev,
e2cd1d1a 2082 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
8f062287 2083 err, mmap_cmd2str(cmd));
4ed131d0 2084 goto err;
37aa5c36
GL		 2085 }
2086
4ed131d0
YH		 2087 if (dyn_uar)
2088 bfregi->sys_pages[idx] = uar_index;
2089 return 0;
2090
2091err:
2092 if (!dyn_uar)
2093 return err;
2094
2095 mlx5_cmd_free_uar(dev->mdev, idx);
2096
2097free_bfreg:
2098 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2099
2100 return err;
37aa5c36
GL		 2101}
2102
24da0016
AL		 2103static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2104{
2105 struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2106 struct mlx5_ib_dev *dev = to_mdev(context->device);
2107 u16 page_idx = get_extended_index(vma->vm_pgoff);
2108 size_t map_size = vma->vm_end - vma->vm_start;
2109 u32 npages = map_size >> PAGE_SHIFT;
2110 phys_addr_t pfn;
24da0016
AL		 2111
2112 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2113 page_idx + npages)
2114 return -EINVAL;
2115
2116 pfn = ((pci_resource_start(dev->mdev->pdev, 0) +
2117 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2118 PAGE_SHIFT) +
2119 page_idx;
e2cd1d1a
JG		 2120 return rdma_user_mmap_io(context, vma, pfn, map_size,
2121 pgprot_writecombine(vma->vm_page_prot));
24da0016
AL		 2122}
2123
e126ba97
EC		 2124static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2125{
2126 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2127 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 2128 unsigned long command;
e126ba97
EC		 2129 phys_addr_t pfn;
2130
2131 command = get_command(vma->vm_pgoff);
2132 switch (command) {
37aa5c36
GL		 2133 case MLX5_IB_MMAP_WC_PAGE:
2134 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 2135 case MLX5_IB_MMAP_REGULAR_PAGE:
4ed131d0 2136 case MLX5_IB_MMAP_ALLOC_WC:
7c2344c3 2137 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 2138
2139 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2140 return -ENOSYS;
2141
d69e3bcf 2142 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 2143 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2144 return -EINVAL;
2145
6cbac1e4 2146 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 2147 return -EPERM;
2148
2149 /* Don't expose to user-space information it shouldn't have */
2150 if (PAGE_SIZE > 4096)
2151 return -EOPNOTSUPP;
2152
2153 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2154 pfn = (dev->mdev->iseg_base +
2155 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2156 PAGE_SHIFT;
2157 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2158 PAGE_SIZE, vma->vm_page_prot))
2159 return -EAGAIN;
d69e3bcf 2160 break;
5c99eaec
FD		 2161 case MLX5_IB_MMAP_CLOCK_INFO:
2162 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
d69e3bcf 2163
24da0016
AL		 2164 case MLX5_IB_MMAP_DEVICE_MEM:
2165 return dm_mmap(ibcontext, vma);
2166
e126ba97
EC		 2167 default:
2168 return -EINVAL;
2169 }
2170
2171 return 0;
2172}
2173
24da0016
AL		 2174struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2175 struct ib_ucontext *context,
2176 struct ib_dm_alloc_attr *attr,
2177 struct uverbs_attr_bundle *attrs)
2178{
2179 u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2180 struct mlx5_memic *memic = &to_mdev(ibdev)->memic;
2181 phys_addr_t memic_addr;
2182 struct mlx5_ib_dm *dm;
2183 u64 start_offset;
2184 u32 page_idx;
2185 int err;
2186
2187 dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2188 if (!dm)
2189 return ERR_PTR(-ENOMEM);
2190
2191 mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n",
2192 attr->length, act_size, attr->alignment);
2193
2194 err = mlx5_cmd_alloc_memic(memic, &memic_addr,
2195 act_size, attr->alignment);
2196 if (err)
2197 goto err_free;
2198
2199 start_offset = memic_addr & ~PAGE_MASK;
2200 page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) -
2201 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2202 PAGE_SHIFT;
2203
2204 err = uverbs_copy_to(attrs,
2205 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2206 &start_offset, sizeof(start_offset));
2207 if (err)
2208 goto err_dealloc;
2209
2210 err = uverbs_copy_to(attrs,
2211 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2212 &page_idx, sizeof(page_idx));
2213 if (err)
2214 goto err_dealloc;
2215
2216 bitmap_set(to_mucontext(context)->dm_pages, page_idx,
2217 DIV_ROUND_UP(act_size, PAGE_SIZE));
2218
2219 dm->dev_addr = memic_addr;
2220
2221 return &dm->ibdm;
2222
2223err_dealloc:
2224 mlx5_cmd_dealloc_memic(memic, memic_addr,
2225 act_size);
2226err_free:
2227 kfree(dm);
2228 return ERR_PTR(err);
2229}
2230
2231int mlx5_ib_dealloc_dm(struct ib_dm *ibdm)
2232{
2233 struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic;
2234 struct mlx5_ib_dm *dm = to_mdm(ibdm);
2235 u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE);
2236 u32 page_idx;
2237 int ret;
2238
2239 ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size);
2240 if (ret)
2241 return ret;
2242
2243 page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) -
2244 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2245 PAGE_SHIFT;
2246 bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages,
2247 page_idx,
2248 DIV_ROUND_UP(act_size, PAGE_SIZE));
2249
2250 kfree(dm);
2251
2252 return 0;
2253}
2254
e126ba97
EC		 2255static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2256 struct ib_ucontext *context,
2257 struct ib_udata *udata)
2258{
2259 struct mlx5_ib_alloc_pd_resp resp;
2260 struct mlx5_ib_pd *pd;
2261 int err;
a1069c1c
YH		 2262 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2263 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
2264 u16 uid = 0;
e126ba97 2265
8cbfaac3 2266 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
e126ba97
EC		 2267 if (!pd)
2268 return ERR_PTR(-ENOMEM);
2269
58895f0d 2270 uid = context ? to_mucontext(context)->devx_uid : 0;
a1069c1c
YH		 2271 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2272 MLX5_SET(alloc_pd_in, in, uid, uid);
2273 err = mlx5_cmd_exec(to_mdev(ibdev)->mdev, in, sizeof(in),
2274 out, sizeof(out));
e126ba97
EC		 2275 if (err) {
2276 kfree(pd);
2277 return ERR_PTR(err);
2278 }
2279
a1069c1c
YH		 2280 pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2281 pd->uid = uid;
e126ba97
EC		 2282 if (context) {
2283 resp.pdn = pd->pdn;
2284 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
a1069c1c 2285 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
e126ba97
EC		 2286 kfree(pd);
2287 return ERR_PTR(-EFAULT);
2288 }
e126ba97
EC		 2289 }
2290
2291 return &pd->ibpd;
2292}
2293
2294static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2295{
2296 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2297 struct mlx5_ib_pd *mpd = to_mpd(pd);
2298
a1069c1c 2299 mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
e126ba97
EC		 2300 kfree(mpd);
2301
2302 return 0;
2303}
2304
466fa6d2
MG		 2305enum {
2306 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2307 MATCH_CRITERIA_ENABLE_MISC_BIT,
71c6e863
AL		 2308 MATCH_CRITERIA_ENABLE_INNER_BIT,
2309 MATCH_CRITERIA_ENABLE_MISC2_BIT
466fa6d2
MG		 2310};
2311
2312#define HEADER_IS_ZERO(match_criteria, headers) \
2313 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2314 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 2315
466fa6d2 2316static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 2317{
466fa6d2 2318 u8 match_criteria_enable;
038d2ef8 2319
466fa6d2
MG		 2320 match_criteria_enable =
2321 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2322 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2323 match_criteria_enable |=
2324 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2325 MATCH_CRITERIA_ENABLE_MISC_BIT;
2326 match_criteria_enable |=
2327 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2328 MATCH_CRITERIA_ENABLE_INNER_BIT;
71c6e863
AL		 2329 match_criteria_enable |=
2330 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2331 MATCH_CRITERIA_ENABLE_MISC2_BIT;
466fa6d2
MG		 2332
2333 return match_criteria_enable;
038d2ef8
MG		 2334}
2335
ca0d4753
MG		 2336static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2337{
2338 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2339 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
038d2ef8
MG		 2340}
2341
37da2a03 2342static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2d1e697e
MR		 2343 bool inner)
2344{
2345 if (inner) {
2346 MLX5_SET(fte_match_set_misc,
2347 misc_c, inner_ipv6_flow_label, mask);
2348 MLX5_SET(fte_match_set_misc,
2349 misc_v, inner_ipv6_flow_label, val);
2350 } else {
2351 MLX5_SET(fte_match_set_misc,
2352 misc_c, outer_ipv6_flow_label, mask);
2353 MLX5_SET(fte_match_set_misc,
2354 misc_v, outer_ipv6_flow_label, val);
2355 }
2356}
2357
ca0d4753
MG		 2358static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2359{
2360 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2361 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2362 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2363 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2364}
2365
71c6e863
AL		 2366static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2367{
2368 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2369 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2370 return -EOPNOTSUPP;
2371
2372 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2373 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2374 return -EOPNOTSUPP;
2375
2376 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2377 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2378 return -EOPNOTSUPP;
2379
2380 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2381 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2382 return -EOPNOTSUPP;
2383
2384 return 0;
2385}
2386
c47ac6ae
MG		 2387#define LAST_ETH_FIELD vlan_tag
2388#define LAST_IB_FIELD sl
ca0d4753 2389#define LAST_IPV4_FIELD tos
466fa6d2 2390#define LAST_IPV6_FIELD traffic_class
c47ac6ae 2391#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 2392#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 2393#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 2394#define LAST_DROP_FIELD size
3b3233fb 2395#define LAST_COUNTERS_FIELD counters
c47ac6ae
MG		 2396
2397/* Field is the last supported field */
2398#define FIELDS_NOT_SUPPORTED(filter, field)\
2399 memchr_inv((void *)&filter.field +\
2400 sizeof(filter.field), 0,\
2401 sizeof(filter) -\
2402 offsetof(typeof(filter), field) -\
2403 sizeof(filter.field))
2404
2ea26203
MB		 2405int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
2406 bool is_egress,
2407 struct mlx5_flow_act *action)
802c2125 2408{
802c2125
AY		 2409
2410 switch (maction->ib_action.type) {
2411 case IB_FLOW_ACTION_ESP:
501f14e3
MB		 2412 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2413 MLX5_FLOW_CONTEXT_ACTION_DECRYPT))
2414 return -EINVAL;
802c2125
AY		 2415 /* Currently only AES_GCM keymat is supported by the driver */
2416 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2ea26203 2417 action->action |= is_egress ?
802c2125
AY		 2418 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2419 MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2420 return 0;
b1085be3
MB		 2421 case IB_FLOW_ACTION_UNSPECIFIED:
2422 if (maction->flow_action_raw.sub_type ==
2423 MLX5_IB_FLOW_ACTION_MODIFY_HEADER) {
501f14e3
MB		 2424 if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2425 return -EINVAL;
b1085be3
MB		 2426 action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2427 action->modify_id = maction->flow_action_raw.action_id;
2428 return 0;
2429 }
10a30896
MB		 2430 if (maction->flow_action_raw.sub_type ==
2431 MLX5_IB_FLOW_ACTION_DECAP) {
501f14e3
MB		 2432 if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP)
2433 return -EINVAL;
10a30896
MB		 2434 action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2435 return 0;
2436 }
e806f932
MB		 2437 if (maction->flow_action_raw.sub_type ==
2438 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) {
501f14e3
MB		 2439 if (action->action &
2440 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT)
2441 return -EINVAL;
e806f932
MB		 2442 action->action |=
2443 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
2444 action->reformat_id =
2445 maction->flow_action_raw.action_id;
2446 return 0;
2447 }
b1085be3 2448 /* fall through */
802c2125
AY		 2449 default:
2450 return -EOPNOTSUPP;
2451 }
2452}
2453
19cc7524
AL		 2454static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2455 u32 *match_v, const union ib_flow_spec *ib_spec,
802c2125 2456 const struct ib_flow_attr *flow_attr,
71c6e863 2457 struct mlx5_flow_act *action, u32 prev_type)
038d2ef8 2458{
466fa6d2
MG		 2459 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2460 misc_parameters);
2461 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2462 misc_parameters);
71c6e863
AL		 2463 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2464 misc_parameters_2);
2465 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2466 misc_parameters_2);
2d1e697e
MR		 2467 void *headers_c;
2468 void *headers_v;
19cc7524 2469 int match_ipv;
802c2125 2470 int ret;
2d1e697e
MR		 2471
2472 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2473 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2474 inner_headers);
2475 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2476 inner_headers);
19cc7524
AL		 2477 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2478 ft_field_support.inner_ip_version);
2d1e697e
MR		 2479 } else {
2480 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2481 outer_headers);
2482 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2483 outer_headers);
19cc7524
AL		 2484 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2485 ft_field_support.outer_ip_version);
2d1e697e 2486 }
466fa6d2 2487
2d1e697e 2488 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 2489 case IB_FLOW_SPEC_ETH:
c47ac6ae 2490 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 2491 return -EOPNOTSUPP;
038d2ef8 2492
2d1e697e 2493 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2494 dmac_47_16),
2495 ib_spec->eth.mask.dst_mac);
2d1e697e 2496 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2497 dmac_47_16),
2498 ib_spec->eth.val.dst_mac);
2499
2d1e697e 2500 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 2501 smac_47_16),
2502 ib_spec->eth.mask.src_mac);
2d1e697e 2503 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 2504 smac_47_16),
2505 ib_spec->eth.val.src_mac);
2506
038d2ef8 2507 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 2508 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 2509 cvlan_tag, 1);
2d1e697e 2510 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 2511 cvlan_tag, 1);
038d2ef8 2512
2d1e697e 2513 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2514 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 2515 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2516 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2517
2d1e697e 2518 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2519 first_cfi,
2520 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 2521 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2522 first_cfi,
2523 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2524
2d1e697e 2525 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2526 first_prio,
2527 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 2528 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2529 first_prio,
2530 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2531 }
2d1e697e 2532 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2533 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 2534 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2535 ethertype, ntohs(ib_spec->eth.val.ether_type));
2536 break;
2537 case IB_FLOW_SPEC_IPV4:
c47ac6ae 2538 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 2539 return -EOPNOTSUPP;
038d2ef8 2540
19cc7524
AL		 2541 if (match_ipv) {
2542 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2543 ip_version, 0xf);
2544 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2545 ip_version, MLX5_FS_IPV4_VERSION);
19cc7524
AL		 2546 } else {
2547 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2548 ethertype, 0xffff);
2549 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2550 ethertype, ETH_P_IP);
2551 }
038d2ef8 2552
2d1e697e 2553 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2554 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2555 &ib_spec->ipv4.mask.src_ip,
2556 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 2557 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2558 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2559 &ib_spec->ipv4.val.src_ip,
2560 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 2561 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2562 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2563 &ib_spec->ipv4.mask.dst_ip,
2564 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 2565 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2566 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2567 &ib_spec->ipv4.val.dst_ip,
2568 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 2569
2d1e697e 2570 set_tos(headers_c, headers_v,
ca0d4753
MG		 2571 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2572
2d1e697e 2573 set_proto(headers_c, headers_v,
ca0d4753 2574 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
038d2ef8 2575 break;
026bae0c 2576 case IB_FLOW_SPEC_IPV6:
c47ac6ae 2577 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 2578 return -EOPNOTSUPP;
026bae0c 2579
19cc7524
AL		 2580 if (match_ipv) {
2581 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2582 ip_version, 0xf);
2583 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2584 ip_version, MLX5_FS_IPV6_VERSION);
19cc7524
AL		 2585 } else {
2586 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2587 ethertype, 0xffff);
2588 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2589 ethertype, ETH_P_IPV6);
2590 }
026bae0c 2591
2d1e697e 2592 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2593 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2594 &ib_spec->ipv6.mask.src_ip,
2595 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2596 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2597 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2598 &ib_spec->ipv6.val.src_ip,
2599 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2600 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2601 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2602 &ib_spec->ipv6.mask.dst_ip,
2603 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2604 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2605 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2606 &ib_spec->ipv6.val.dst_ip,
2607 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2608
2d1e697e 2609 set_tos(headers_c, headers_v,
466fa6d2
MG		 2610 ib_spec->ipv6.mask.traffic_class,
2611 ib_spec->ipv6.val.traffic_class);
2612
2d1e697e 2613 set_proto(headers_c, headers_v,
466fa6d2
MG		 2614 ib_spec->ipv6.mask.next_hdr,
2615 ib_spec->ipv6.val.next_hdr);
2616
2d1e697e
MR		 2617 set_flow_label(misc_params_c, misc_params_v,
2618 ntohl(ib_spec->ipv6.mask.flow_label),
2619 ntohl(ib_spec->ipv6.val.flow_label),
2620 ib_spec->type & IB_FLOW_SPEC_INNER);
802c2125
AY		 2621 break;
2622 case IB_FLOW_SPEC_ESP:
2623 if (ib_spec->esp.mask.seq)
2624 return -EOPNOTSUPP;
2d1e697e 2625
802c2125
AY		 2626 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2627 ntohl(ib_spec->esp.mask.spi));
2628 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2629 ntohl(ib_spec->esp.val.spi));
026bae0c 2630 break;
038d2ef8 2631 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2632 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2633 LAST_TCP_UDP_FIELD))
1ffd3a26 2634 return -EOPNOTSUPP;
038d2ef8 2635
2d1e697e 2636 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2637 0xff);
2d1e697e 2638 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2639 IPPROTO_TCP);
2640
2d1e697e 2641 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2642 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2643 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2644 ntohs(ib_spec->tcp_udp.val.src_port));
2645
2d1e697e 2646 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2647 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2648 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2649 ntohs(ib_spec->tcp_udp.val.dst_port));
2650 break;
2651 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2652 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2653 LAST_TCP_UDP_FIELD))
1ffd3a26 2654 return -EOPNOTSUPP;
038d2ef8 2655
2d1e697e 2656 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2657 0xff);
2d1e697e 2658 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2659 IPPROTO_UDP);
2660
2d1e697e 2661 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2662 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2663 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2664 ntohs(ib_spec->tcp_udp.val.src_port));
2665
2d1e697e 2666 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2667 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2668 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2669 ntohs(ib_spec->tcp_udp.val.dst_port));
2670 break;
da2f22ae
AL		 2671 case IB_FLOW_SPEC_GRE:
2672 if (ib_spec->gre.mask.c_ks_res0_ver)
2673 return -EOPNOTSUPP;
2674
2675 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2676 0xff);
2677 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2678 IPPROTO_GRE);
2679
2680 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
a93b632c 2681 ntohs(ib_spec->gre.mask.protocol));
da2f22ae
AL		 2682 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2683 ntohs(ib_spec->gre.val.protocol));
2684
2685 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
5886a96a 2686 gre_key.nvgre.hi),
da2f22ae
AL		 2687 &ib_spec->gre.mask.key,
2688 sizeof(ib_spec->gre.mask.key));
2689 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
5886a96a 2690 gre_key.nvgre.hi),
da2f22ae
AL		 2691 &ib_spec->gre.val.key,
2692 sizeof(ib_spec->gre.val.key));
2693 break;
71c6e863
AL		 2694 case IB_FLOW_SPEC_MPLS:
2695 switch (prev_type) {
2696 case IB_FLOW_SPEC_UDP:
2697 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2698 ft_field_support.outer_first_mpls_over_udp),
2699 &ib_spec->mpls.mask.tag))
2700 return -EOPNOTSUPP;
2701
2702 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2703 outer_first_mpls_over_udp),
2704 &ib_spec->mpls.val.tag,
2705 sizeof(ib_spec->mpls.val.tag));
2706 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2707 outer_first_mpls_over_udp),
2708 &ib_spec->mpls.mask.tag,
2709 sizeof(ib_spec->mpls.mask.tag));
2710 break;
2711 case IB_FLOW_SPEC_GRE:
2712 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2713 ft_field_support.outer_first_mpls_over_gre),
2714 &ib_spec->mpls.mask.tag))
2715 return -EOPNOTSUPP;
2716
2717 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2718 outer_first_mpls_over_gre),
2719 &ib_spec->mpls.val.tag,
2720 sizeof(ib_spec->mpls.val.tag));
2721 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2722 outer_first_mpls_over_gre),
2723 &ib_spec->mpls.mask.tag,
2724 sizeof(ib_spec->mpls.mask.tag));
2725 break;
2726 default:
2727 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2728 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2729 ft_field_support.inner_first_mpls),
2730 &ib_spec->mpls.mask.tag))
2731 return -EOPNOTSUPP;
2732
2733 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2734 inner_first_mpls),
2735 &ib_spec->mpls.val.tag,
2736 sizeof(ib_spec->mpls.val.tag));
2737 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2738 inner_first_mpls),
2739 &ib_spec->mpls.mask.tag,
2740 sizeof(ib_spec->mpls.mask.tag));
2741 } else {
2742 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2743 ft_field_support.outer_first_mpls),
2744 &ib_spec->mpls.mask.tag))
2745 return -EOPNOTSUPP;
2746
2747 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2748 outer_first_mpls),
2749 &ib_spec->mpls.val.tag,
2750 sizeof(ib_spec->mpls.val.tag));
2751 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2752 outer_first_mpls),
2753 &ib_spec->mpls.mask.tag,
2754 sizeof(ib_spec->mpls.mask.tag));
2755 }
2756 }
2757 break;
ffb30d8f
MR		 2758 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2759 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2760 LAST_TUNNEL_FIELD))
1ffd3a26 2761 return -EOPNOTSUPP;
ffb30d8f
MR		 2762
2763 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2764 ntohl(ib_spec->tunnel.mask.tunnel_id));
2765 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2766 ntohl(ib_spec->tunnel.val.tunnel_id));
2767 break;
2ac693f9
MR		 2768 case IB_FLOW_SPEC_ACTION_TAG:
2769 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2770 LAST_FLOW_TAG_FIELD))
2771 return -EOPNOTSUPP;
2772 if (ib_spec->flow_tag.tag_id >= BIT(24))
2773 return -EINVAL;
2774
075572d4 2775 action->flow_tag = ib_spec->flow_tag.tag_id;
d5634fee 2776 action->flags |= FLOW_ACT_HAS_TAG;
2ac693f9 2777 break;
a22ed86c
SS		 2778 case IB_FLOW_SPEC_ACTION_DROP:
2779 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2780 LAST_DROP_FIELD))
2781 return -EOPNOTSUPP;
075572d4 2782 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
a22ed86c 2783 break;
802c2125 2784 case IB_FLOW_SPEC_ACTION_HANDLE:
2ea26203
MB		 2785 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act),
2786 flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action);
802c2125
AY		 2787 if (ret)
2788 return ret;
2789 break;
3b3233fb
RS		 2790 case IB_FLOW_SPEC_ACTION_COUNT:
2791 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
2792 LAST_COUNTERS_FIELD))
2793 return -EOPNOTSUPP;
2794
2795 /* for now support only one counters spec per flow */
2796 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
2797 return -EINVAL;
2798
2799 action->counters = ib_spec->flow_count.counters;
2800 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2801 break;
038d2ef8
MG		 2802 default:
2803 return -EINVAL;
2804 }
2805
2806 return 0;
2807}
2808
2809/* If a flow could catch both multicast and unicast packets,
2810 * it won't fall into the multicast flow steering table and this rule
2811 * could steal other multicast packets.
2812 */
a550ddfc 2813static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
038d2ef8 2814{
81e30880 2815 union ib_flow_spec *flow_spec;
038d2ef8
MG		 2816
2817 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 2818 ib_attr->num_of_specs < 1)
2819 return false;
2820
81e30880
YH		 2821 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2822 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2823 struct ib_flow_spec_ipv4 *ipv4_spec;
2824
2825 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2826 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2827 return true;
2828
038d2ef8 2829 return false;
81e30880
YH		 2830 }
2831
2832 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2833 struct ib_flow_spec_eth *eth_spec;
2834
2835 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2836 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2837 is_multicast_ether_addr(eth_spec->val.dst_mac);
2838 }
038d2ef8 2839
81e30880 2840 return false;
038d2ef8
MG		 2841}
2842
802c2125
AY		 2843enum valid_spec {
2844 VALID_SPEC_INVALID,
2845 VALID_SPEC_VALID,
2846 VALID_SPEC_NA,
2847};
2848
2849static enum valid_spec
2850is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
2851 const struct mlx5_flow_spec *spec,
2852 const struct mlx5_flow_act *flow_act,
2853 bool egress)
2854{
2855 const u32 *match_c = spec->match_criteria;
2856 bool is_crypto =
2857 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2858 MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
2859 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
2860 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
2861
2862 /*
2863 * Currently only crypto is supported in egress, when regular egress
2864 * rules would be supported, always return VALID_SPEC_NA.
2865 */
2866 if (!is_crypto)
78dd0c43 2867 return VALID_SPEC_NA;
802c2125
AY		 2868
2869 return is_crypto && is_ipsec &&
d5634fee 2870 (!egress || (!is_drop && !(flow_act->flags & FLOW_ACT_HAS_TAG))) ?
802c2125
AY		 2871 VALID_SPEC_VALID : VALID_SPEC_INVALID;
2872}
2873
2874static bool is_valid_spec(struct mlx5_core_dev *mdev,
2875 const struct mlx5_flow_spec *spec,
2876 const struct mlx5_flow_act *flow_act,
2877 bool egress)
2878{
2879 /* We curretly only support ipsec egress flow */
2880 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
2881}
2882
19cc7524
AL		 2883static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2884 const struct ib_flow_attr *flow_attr,
0f750966 2885 bool check_inner)
038d2ef8
MG		 2886{
2887 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 2888 int match_ipv = check_inner ?
2889 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2890 ft_field_support.inner_ip_version) :
2891 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2892 ft_field_support.outer_ip_version);
0f750966
AL		 2893 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2894 bool ipv4_spec_valid, ipv6_spec_valid;
2895 unsigned int ip_spec_type = 0;
2896 bool has_ethertype = false;
038d2ef8 2897 unsigned int spec_index;
0f750966
AL		 2898 bool mask_valid = true;
2899 u16 eth_type = 0;
2900 bool type_valid;
038d2ef8
MG		 2901
2902 /* Validate that ethertype is correct */
2903 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 2904 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 2905 ib_spec->eth.mask.ether_type) {
0f750966
AL		 2906 mask_valid = (ib_spec->eth.mask.ether_type ==
2907 htons(0xffff));
2908 has_ethertype = true;
2909 eth_type = ntohs(ib_spec->eth.val.ether_type);
2910 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2911 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2912 ip_spec_type = ib_spec->type;
038d2ef8
MG		 2913 }
2914 ib_spec = (void *)ib_spec + ib_spec->size;
2915 }
0f750966
AL		 2916
2917 type_valid = (!has_ethertype) || (!ip_spec_type);
2918 if (!type_valid && mask_valid) {
2919 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2920 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2921 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2922 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 2923
2924 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2925 (((eth_type == ETH_P_MPLS_UC) ||
2926 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 2927 }
2928
2929 return type_valid;
2930}
2931
19cc7524
AL		 2932static bool is_valid_attr(struct mlx5_core_dev *mdev,
2933 const struct ib_flow_attr *flow_attr)
0f750966 2934{
19cc7524
AL		 2935 return is_valid_ethertype(mdev, flow_attr, false) &&
2936 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 2937}
2938
2939static void put_flow_table(struct mlx5_ib_dev *dev,
2940 struct mlx5_ib_flow_prio *prio, bool ft_added)
2941{
2942 prio->refcount -= !!ft_added;
2943 if (!prio->refcount) {
2944 mlx5_destroy_flow_table(prio->flow_table);
2945 prio->flow_table = NULL;
2946 }
2947}
2948
3b3233fb
RS		 2949static void counters_clear_description(struct ib_counters *counters)
2950{
2951 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
2952
2953 mutex_lock(&mcounters->mcntrs_mutex);
2954 kfree(mcounters->counters_data);
2955 mcounters->counters_data = NULL;
2956 mcounters->cntrs_max_index = 0;
2957 mutex_unlock(&mcounters->mcntrs_mutex);
2958}
2959
038d2ef8
MG		 2960static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2961{
038d2ef8
MG		 2962 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2963 struct mlx5_ib_flow_handler,
2964 ibflow);
2965 struct mlx5_ib_flow_handler *iter, *tmp;
d4be3f44 2966 struct mlx5_ib_dev *dev = handler->dev;
038d2ef8 2967
9a4ca38d 2968 mutex_lock(&dev->flow_db->lock);
038d2ef8
MG		 2969
2970 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 2971 mlx5_del_flow_rules(iter->rule);
cc0e5d42 2972 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 2973 list_del(&iter->list);
2974 kfree(iter);
2975 }
2976
74491de9 2977 mlx5_del_flow_rules(handler->rule);
5497adc6 2978 put_flow_table(dev, handler->prio, true);
3b3233fb
RS		 2979 if (handler->ibcounters &&
2980 atomic_read(&handler->ibcounters->usecnt) == 1)
2981 counters_clear_description(handler->ibcounters);
038d2ef8 2982
3b3233fb 2983 mutex_unlock(&dev->flow_db->lock);
d4be3f44
YH		 2984 if (handler->flow_matcher)
2985 atomic_dec(&handler->flow_matcher->usecnt);
038d2ef8
MG		 2986 kfree(handler);
2987
2988 return 0;
2989}
2990
35d19011
MG		 2991static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2992{
2993 priority *= 2;
2994 if (!dont_trap)
2995 priority++;
2996 return priority;
2997}
2998
cc0e5d42
MG		 2999enum flow_table_type {
3000 MLX5_IB_FT_RX,
3001 MLX5_IB_FT_TX
3002};
3003
00b7c2ab
MG		 3004#define MLX5_FS_MAX_TYPES 6
3005#define MLX5_FS_MAX_ENTRIES BIT(16)
d4be3f44
YH		 3006
3007static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns,
3008 struct mlx5_ib_flow_prio *prio,
3009 int priority,
4adda112
MB		 3010 int num_entries, int num_groups,
3011 u32 flags)
d4be3f44
YH		 3012{
3013 struct mlx5_flow_table *ft;
3014
3015 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3016 num_entries,
3017 num_groups,
4adda112 3018 0, flags);
d4be3f44
YH		 3019 if (IS_ERR(ft))
3020 return ERR_CAST(ft);
3021
3022 prio->flow_table = ft;
3023 prio->refcount = 0;
3024 return prio;
3025}
3026
038d2ef8 3027static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 3028 struct ib_flow_attr *flow_attr,
3029 enum flow_table_type ft_type)
038d2ef8 3030{
35d19011 3031 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 3032 struct mlx5_flow_namespace *ns = NULL;
3033 struct mlx5_ib_flow_prio *prio;
3034 struct mlx5_flow_table *ft;
dac388ef 3035 int max_table_size;
038d2ef8
MG		 3036 int num_entries;
3037 int num_groups;
4adda112 3038 u32 flags = 0;
038d2ef8 3039 int priority;
038d2ef8 3040
dac388ef
MG		 3041 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3042 log_max_ft_size));
038d2ef8 3043 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
78dd0c43
MB		 3044 enum mlx5_flow_namespace_type fn_type;
3045
3046 if (flow_is_multicast_only(flow_attr) &&
3047 !dont_trap)
038d2ef8
MG		 3048 priority = MLX5_IB_FLOW_MCAST_PRIO;
3049 else
35d19011
MG		 3050 priority = ib_prio_to_core_prio(flow_attr->priority,
3051 dont_trap);
78dd0c43
MB		 3052 if (ft_type == MLX5_IB_FT_RX) {
3053 fn_type = MLX5_FLOW_NAMESPACE_BYPASS;
3054 prio = &dev->flow_db->prios[priority];
4adda112
MB		 3055 if (!dev->rep &&
3056 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3057 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
5c2db53f
MB		 3058 if (!dev->rep &&
3059 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3060 reformat_l3_tunnel_to_l2))
3061 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
78dd0c43
MB		 3062 } else {
3063 max_table_size =
3064 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3065 log_max_ft_size));
3066 fn_type = MLX5_FLOW_NAMESPACE_EGRESS;
3067 prio = &dev->flow_db->egress_prios[priority];
4adda112
MB		 3068 if (!dev->rep &&
3069 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3070 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
78dd0c43
MB		 3071 }
3072 ns = mlx5_get_flow_namespace(dev->mdev, fn_type);
038d2ef8
MG		 3073 num_entries = MLX5_FS_MAX_ENTRIES;
3074 num_groups = MLX5_FS_MAX_TYPES;
038d2ef8
MG		 3075 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3076 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3077 ns = mlx5_get_flow_namespace(dev->mdev,
3078 MLX5_FLOW_NAMESPACE_LEFTOVERS);
3079 build_leftovers_ft_param(&priority,
3080 &num_entries,
3081 &num_groups);
9a4ca38d 3082 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 3083 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3084 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3085 allow_sniffer_and_nic_rx_shared_tir))
3086 return ERR_PTR(-ENOTSUPP);
3087
3088 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3089 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3090 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3091
9a4ca38d 3092 prio = &dev->flow_db->sniffer[ft_type];
cc0e5d42
MG		 3093 priority = 0;
3094 num_entries = 1;
3095 num_groups = 1;
038d2ef8
MG		 3096 }
3097
3098 if (!ns)
3099 return ERR_PTR(-ENOTSUPP);
3100
dac388ef
MG		 3101 if (num_entries > max_table_size)
3102 return ERR_PTR(-ENOMEM);
3103
038d2ef8 3104 ft = prio->flow_table;
d4be3f44 3105 if (!ft)
4adda112
MB		 3106 return _get_prio(ns, prio, priority, num_entries, num_groups,
3107 flags);
038d2ef8 3108
d4be3f44 3109 return prio;
038d2ef8
MG		 3110}
3111
a550ddfc
YH		 3112static void set_underlay_qp(struct mlx5_ib_dev *dev,
3113 struct mlx5_flow_spec *spec,
3114 u32 underlay_qpn)
3115{
3116 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3117 spec->match_criteria,
3118 misc_parameters);
3119 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3120 misc_parameters);
3121
3122 if (underlay_qpn &&
3123 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3124 ft_field_support.bth_dst_qp)) {
3125 MLX5_SET(fte_match_set_misc,
3126 misc_params_v, bth_dst_qp, underlay_qpn);
3127 MLX5_SET(fte_match_set_misc,
3128 misc_params_c, bth_dst_qp, 0xffffff);
3129 }
3130}
3131
5e95af5f
RS		 3132static int read_flow_counters(struct ib_device *ibdev,
3133 struct mlx5_read_counters_attr *read_attr)
3134{
3135 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3136 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3137
3138 return mlx5_fc_query(dev->mdev, fc,
3139 &read_attr->out[IB_COUNTER_PACKETS],
3140 &read_attr->out[IB_COUNTER_BYTES]);
3141}
3142
3143/* flow counters currently expose two counters packets and bytes */
3144#define FLOW_COUNTERS_NUM 2
3b3233fb
RS		 3145static int counters_set_description(struct ib_counters *counters,
3146 enum mlx5_ib_counters_type counters_type,
3147 struct mlx5_ib_flow_counters_desc *desc_data,
3148 u32 ncounters)
3149{
3150 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3151 u32 cntrs_max_index = 0;
3152 int i;
3153
3154 if (counters_type != MLX5_IB_COUNTERS_FLOW)
3155 return -EINVAL;
3156
3157 /* init the fields for the object */
3158 mcounters->type = counters_type;
5e95af5f
RS		 3159 mcounters->read_counters = read_flow_counters;
3160 mcounters->counters_num = FLOW_COUNTERS_NUM;
3b3233fb
RS		 3161 mcounters->ncounters = ncounters;
3162 /* each counter entry have both description and index pair */
3163 for (i = 0; i < ncounters; i++) {
3164 if (desc_data[i].description > IB_COUNTER_BYTES)
3165 return -EINVAL;
3166
3167 if (cntrs_max_index <= desc_data[i].index)
3168 cntrs_max_index = desc_data[i].index + 1;
3169 }
3170
3171 mutex_lock(&mcounters->mcntrs_mutex);
3172 mcounters->counters_data = desc_data;
3173 mcounters->cntrs_max_index = cntrs_max_index;
3174 mutex_unlock(&mcounters->mcntrs_mutex);
3175
3176 return 0;
3177}
3178
3179#define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3180static int flow_counters_set_data(struct ib_counters *ibcounters,
3181 struct mlx5_ib_create_flow *ucmd)
3182{
3183 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3184 struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3185 struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3186 bool hw_hndl = false;
3187 int ret = 0;
3188
3189 if (ucmd && ucmd->ncounters_data != 0) {
3190 cntrs_data = ucmd->data;
3191 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3192 return -EINVAL;
3193
3194 desc_data = kcalloc(cntrs_data->ncounters,
3195 sizeof(*desc_data),
3196 GFP_KERNEL);
3197 if (!desc_data)
3198 return -ENOMEM;
3199
3200 if (copy_from_user(desc_data,
3201 u64_to_user_ptr(cntrs_data->counters_data),
3202 sizeof(*desc_data) * cntrs_data->ncounters)) {
3203 ret = -EFAULT;
3204 goto free;
3205 }
3206 }
3207
3208 if (!mcounters->hw_cntrs_hndl) {
3209 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3210 to_mdev(ibcounters->device)->mdev, false);
e31abf76 3211 if (IS_ERR(mcounters->hw_cntrs_hndl)) {
3212 ret = PTR_ERR(mcounters->hw_cntrs_hndl);
3b3233fb
RS		 3213 goto free;
3214 }
3215 hw_hndl = true;
3216 }
3217
3218 if (desc_data) {
3219 /* counters already bound to at least one flow */
3220 if (mcounters->cntrs_max_index) {
3221 ret = -EINVAL;
3222 goto free_hndl;
3223 }
3224
3225 ret = counters_set_description(ibcounters,
3226 MLX5_IB_COUNTERS_FLOW,
3227 desc_data,
3228 cntrs_data->ncounters);
3229 if (ret)
3230 goto free_hndl;
3231
3232 } else if (!mcounters->cntrs_max_index) {
3233 /* counters not bound yet, must have udata passed */
3234 ret = -EINVAL;
3235 goto free_hndl;
3236 }
3237
3238 return 0;
3239
3240free_hndl:
3241 if (hw_hndl) {
3242 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3243 mcounters->hw_cntrs_hndl);
3244 mcounters->hw_cntrs_hndl = NULL;
3245 }
3246free:
3247 kfree(desc_data);
3248 return ret;
3249}
3250
a550ddfc
YH		 3251static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3252 struct mlx5_ib_flow_prio *ft_prio,
3253 const struct ib_flow_attr *flow_attr,
3254 struct mlx5_flow_destination *dst,
3b3233fb
RS		 3255 u32 underlay_qpn,
3256 struct mlx5_ib_create_flow *ucmd)
038d2ef8
MG		 3257{
3258 struct mlx5_flow_table *ft = ft_prio->flow_table;
3259 struct mlx5_ib_flow_handler *handler;
075572d4 3260 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
c5bb1730 3261 struct mlx5_flow_spec *spec;
3b3233fb
RS		 3262 struct mlx5_flow_destination dest_arr[2] = {};
3263 struct mlx5_flow_destination *rule_dst = dest_arr;
dd063d0e 3264 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 3265 unsigned int spec_index;
71c6e863 3266 u32 prev_type = 0;
038d2ef8 3267 int err = 0;
3b3233fb 3268 int dest_num = 0;
802c2125 3269 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
038d2ef8 3270
19cc7524 3271 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 3272 return ERR_PTR(-EINVAL);
3273
78dd0c43
MB		 3274 if (dev->rep && is_egress)
3275 return ERR_PTR(-EINVAL);
3276
1b9a07ee 3277 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 3278 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 3279 if (!handler || !spec) {
038d2ef8
MG		 3280 err = -ENOMEM;
3281 goto free;
3282 }
3283
3284 INIT_LIST_HEAD(&handler->list);
3b3233fb
RS		 3285 if (dst) {
3286 memcpy(&dest_arr[0], dst, sizeof(*dst));
3287 dest_num++;
3288 }
038d2ef8
MG		 3289
3290 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
19cc7524 3291 err = parse_flow_attr(dev->mdev, spec->match_criteria,
a22ed86c 3292 spec->match_value,
71c6e863
AL		 3293 ib_flow, flow_attr, &flow_act,
3294 prev_type);
038d2ef8
MG		 3295 if (err < 0)
3296 goto free;
3297
71c6e863 3298 prev_type = ((union ib_flow_spec *)ib_flow)->type;
038d2ef8
MG		 3299 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3300 }
3301
a550ddfc
YH		 3302 if (!flow_is_multicast_only(flow_attr))
3303 set_underlay_qp(dev, spec, underlay_qpn);
3304
018a94ee
MB		 3305 if (dev->rep) {
3306 void *misc;
3307
3308 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3309 misc_parameters);
3310 MLX5_SET(fte_match_set_misc, misc, source_port,
3311 dev->rep->vport);
3312 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3313 misc_parameters);
3314 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3315 }
3316
466fa6d2 3317 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
802c2125
AY		 3318
3319 if (is_egress &&
3320 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3321 err = -EINVAL;
3322 goto free;
3323 }
3324
3b3233fb 3325 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
171c7625
MB		 3326 struct mlx5_ib_mcounters *mcounters;
3327
3b3233fb
RS		 3328 err = flow_counters_set_data(flow_act.counters, ucmd);
3329 if (err)
3330 goto free;
3331
171c7625 3332 mcounters = to_mcounters(flow_act.counters);
3b3233fb
RS		 3333 handler->ibcounters = flow_act.counters;
3334 dest_arr[dest_num].type =
3335 MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625
MB		 3336 dest_arr[dest_num].counter_id =
3337 mlx5_fc_id(mcounters->hw_cntrs_hndl);
3b3233fb
RS		 3338 dest_num++;
3339 }
3340
075572d4 3341 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3b3233fb
RS		 3342 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) {
3343 rule_dst = NULL;
3344 dest_num = 0;
3345 }
a22ed86c 3346 } else {
802c2125
AY		 3347 if (is_egress)
3348 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3349 else
3350 flow_act.action |=
3b3233fb 3351 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
802c2125 3352 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
a22ed86c 3353 }
2ac693f9 3354
d5634fee 3355 if ((flow_act.flags & FLOW_ACT_HAS_TAG) &&
2ac693f9
MR		 3356 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3357 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3358 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
075572d4 3359 flow_act.flow_tag, flow_attr->type);
2ac693f9
MR		 3360 err = -EINVAL;
3361 goto free;
3362 }
74491de9 3363 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 3364 &flow_act,
a22ed86c 3365 rule_dst, dest_num);
038d2ef8
MG		 3366
3367 if (IS_ERR(handler->rule)) {
3368 err = PTR_ERR(handler->rule);
3369 goto free;
3370 }
3371
d9d4980a 3372 ft_prio->refcount++;
5497adc6 3373 handler->prio = ft_prio;
d4be3f44 3374 handler->dev = dev;
038d2ef8
MG		 3375
3376 ft_prio->flow_table = ft;
3377free:
3b3233fb
RS		 3378 if (err && handler) {
3379 if (handler->ibcounters &&
3380 atomic_read(&handler->ibcounters->usecnt) == 1)
3381 counters_clear_description(handler->ibcounters);
038d2ef8 3382 kfree(handler);
3b3233fb 3383 }
c5bb1730 3384 kvfree(spec);
038d2ef8
MG		 3385 return err ? ERR_PTR(err) : handler;
3386}
3387
a550ddfc
YH		 3388static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3389 struct mlx5_ib_flow_prio *ft_prio,
3390 const struct ib_flow_attr *flow_attr,
3391 struct mlx5_flow_destination *dst)
3392{
3b3233fb 3393 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
a550ddfc
YH		 3394}
3395
35d19011
MG		 3396static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3397 struct mlx5_ib_flow_prio *ft_prio,
3398 struct ib_flow_attr *flow_attr,
3399 struct mlx5_flow_destination *dst)
3400{
3401 struct mlx5_ib_flow_handler *handler_dst = NULL;
3402 struct mlx5_ib_flow_handler *handler = NULL;
3403
3404 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3405 if (!IS_ERR(handler)) {
3406 handler_dst = create_flow_rule(dev, ft_prio,
3407 flow_attr, dst);
3408 if (IS_ERR(handler_dst)) {
74491de9 3409 mlx5_del_flow_rules(handler->rule);
d9d4980a 3410 ft_prio->refcount--;
35d19011
MG		 3411 kfree(handler);
3412 handler = handler_dst;
3413 } else {
3414 list_add(&handler_dst->list, &handler->list);
3415 }
3416 }
3417
3418 return handler;
3419}
038d2ef8
MG		 3420enum {
3421 LEFTOVERS_MC,
3422 LEFTOVERS_UC,
3423};
3424
3425static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3426 struct mlx5_ib_flow_prio *ft_prio,
3427 struct ib_flow_attr *flow_attr,
3428 struct mlx5_flow_destination *dst)
3429{
3430 struct mlx5_ib_flow_handler *handler_ucast = NULL;
3431 struct mlx5_ib_flow_handler *handler = NULL;
3432
3433 static struct {
3434 struct ib_flow_attr flow_attr;
3435 struct ib_flow_spec_eth eth_flow;
3436 } leftovers_specs[] = {
3437 [LEFTOVERS_MC] = {
3438 .flow_attr = {
3439 .num_of_specs = 1,
3440 .size = sizeof(leftovers_specs[0])
3441 },
3442 .eth_flow = {
3443 .type = IB_FLOW_SPEC_ETH,
3444 .size = sizeof(struct ib_flow_spec_eth),
3445 .mask = {.dst_mac = {0x1} },
3446 .val = {.dst_mac = {0x1} }
3447 }
3448 },
3449 [LEFTOVERS_UC] = {
3450 .flow_attr = {
3451 .num_of_specs = 1,
3452 .size = sizeof(leftovers_specs[0])
3453 },
3454 .eth_flow = {
3455 .type = IB_FLOW_SPEC_ETH,
3456 .size = sizeof(struct ib_flow_spec_eth),
3457 .mask = {.dst_mac = {0x1} },
3458 .val = {.dst_mac = {} }
3459 }
3460 }
3461 };
3462
3463 handler = create_flow_rule(dev, ft_prio,
3464 &leftovers_specs[LEFTOVERS_MC].flow_attr,
3465 dst);
3466 if (!IS_ERR(handler) &&
3467 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3468 handler_ucast = create_flow_rule(dev, ft_prio,
3469 &leftovers_specs[LEFTOVERS_UC].flow_attr,
3470 dst);
3471 if (IS_ERR(handler_ucast)) {
74491de9 3472 mlx5_del_flow_rules(handler->rule);
d9d4980a 3473 ft_prio->refcount--;
038d2ef8
MG		 3474 kfree(handler);
3475 handler = handler_ucast;
3476 } else {
3477 list_add(&handler_ucast->list, &handler->list);
3478 }
3479 }
3480
3481 return handler;
3482}
3483
cc0e5d42
MG		 3484static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3485 struct mlx5_ib_flow_prio *ft_rx,
3486 struct mlx5_ib_flow_prio *ft_tx,
3487 struct mlx5_flow_destination *dst)
3488{
3489 struct mlx5_ib_flow_handler *handler_rx;
3490 struct mlx5_ib_flow_handler *handler_tx;
3491 int err;
3492 static const struct ib_flow_attr flow_attr = {
3493 .num_of_specs = 0,
3494 .size = sizeof(flow_attr)
3495 };
3496
3497 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3498 if (IS_ERR(handler_rx)) {
3499 err = PTR_ERR(handler_rx);
3500 goto err;
3501 }
3502
3503 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3504 if (IS_ERR(handler_tx)) {
3505 err = PTR_ERR(handler_tx);
3506 goto err_tx;
3507 }
3508
3509 list_add(&handler_tx->list, &handler_rx->list);
3510
3511 return handler_rx;
3512
3513err_tx:
74491de9 3514 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 3515 ft_rx->refcount--;
3516 kfree(handler_rx);
3517err:
3518 return ERR_PTR(err);
3519}
3520
038d2ef8
MG		 3521static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3522 struct ib_flow_attr *flow_attr,
59082a32
MB		 3523 int domain,
3524 struct ib_udata *udata)
038d2ef8
MG		 3525{
3526 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 3527 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 3528 struct mlx5_ib_flow_handler *handler = NULL;
3529 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 3530 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8 3531 struct mlx5_ib_flow_prio *ft_prio;
802c2125 3532 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3b3233fb
RS		 3533 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3534 size_t min_ucmd_sz, required_ucmd_sz;
038d2ef8 3535 int err;
a550ddfc 3536 int underlay_qpn;
038d2ef8 3537
3b3233fb
RS		 3538 if (udata && udata->inlen) {
3539 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3540 sizeof(ucmd_hdr.reserved);
3541 if (udata->inlen < min_ucmd_sz)
3542 return ERR_PTR(-EOPNOTSUPP);
3543
3544 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3545 if (err)
3546 return ERR_PTR(err);
3547
3548 /* currently supports only one counters data */
3549 if (ucmd_hdr.ncounters_data > 1)
3550 return ERR_PTR(-EINVAL);
3551
3552 required_ucmd_sz = min_ucmd_sz +
3553 sizeof(struct mlx5_ib_flow_counters_data) *
3554 ucmd_hdr.ncounters_data;
3555 if (udata->inlen > required_ucmd_sz &&
3556 !ib_is_udata_cleared(udata, required_ucmd_sz,
3557 udata->inlen - required_ucmd_sz))
3558 return ERR_PTR(-EOPNOTSUPP);
3559
3560 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3561 if (!ucmd)
3562 return ERR_PTR(-ENOMEM);
3563
3564 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
299eafee
GS		 3565 if (err)
3566 goto free_ucmd;
3b3233fb 3567 }
59082a32 3568
299eafee
GS		 3569 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) {
3570 err = -ENOMEM;
3571 goto free_ucmd;
3572 }
038d2ef8
MG		 3573
3574 if (domain != IB_FLOW_DOMAIN_USER ||
508562d6 3575 flow_attr->port > dev->num_ports ||
802c2125 3576 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
299eafee
GS		 3577 IB_FLOW_ATTR_FLAGS_EGRESS))) {
3578 err = -EINVAL;
3579 goto free_ucmd;
3580 }
802c2125
AY		 3581
3582 if (is_egress &&
3583 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
299eafee
GS		 3584 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3585 err = -EINVAL;
3586 goto free_ucmd;
3587 }
038d2ef8
MG		 3588
3589 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
299eafee
GS		 3590 if (!dst) {
3591 err = -ENOMEM;
3592 goto free_ucmd;
3593 }
038d2ef8 3594
9a4ca38d 3595 mutex_lock(&dev->flow_db->lock);
038d2ef8 3596
802c2125
AY		 3597 ft_prio = get_flow_table(dev, flow_attr,
3598 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
038d2ef8
MG		 3599 if (IS_ERR(ft_prio)) {
3600 err = PTR_ERR(ft_prio);
3601 goto unlock;
3602 }
cc0e5d42
MG		 3603 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3604 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3605 if (IS_ERR(ft_prio_tx)) {
3606 err = PTR_ERR(ft_prio_tx);
3607 ft_prio_tx = NULL;
3608 goto destroy_ft;
3609 }
3610 }
038d2ef8 3611
802c2125
AY		 3612 if (is_egress) {
3613 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3614 } else {
3615 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3616 if (mqp->flags & MLX5_IB_QP_RSS)
3617 dst->tir_num = mqp->rss_qp.tirn;
3618 else
3619 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3620 }
038d2ef8
MG		 3621
3622 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 3623 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3624 handler = create_dont_trap_rule(dev, ft_prio,
3625 flow_attr, dst);
3626 } else {
a550ddfc
YH		 3627 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3628 mqp->underlay_qpn : 0;
3629 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3b3233fb 3630 dst, underlay_qpn, ucmd);
35d19011 3631 }
038d2ef8
MG		 3632 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3633 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3634 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3635 dst);
cc0e5d42
MG		 3636 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3637 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 3638 } else {
3639 err = -EINVAL;
3640 goto destroy_ft;
3641 }
3642
3643 if (IS_ERR(handler)) {
3644 err = PTR_ERR(handler);
3645 handler = NULL;
3646 goto destroy_ft;
3647 }
3648
9a4ca38d 3649 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3650 kfree(dst);
3b3233fb 3651 kfree(ucmd);
038d2ef8
MG		 3652
3653 return &handler->ibflow;
3654
3655destroy_ft:
3656 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 3657 if (ft_prio_tx)
3658 put_flow_table(dev, ft_prio_tx, false);
038d2ef8 3659unlock:
9a4ca38d 3660 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3661 kfree(dst);
299eafee 3662free_ucmd:
3b3233fb 3663 kfree(ucmd);
038d2ef8
MG		 3664 return ERR_PTR(err);
3665}
3666
b47fd4ff
MB		 3667static struct mlx5_ib_flow_prio *
3668_get_flow_table(struct mlx5_ib_dev *dev,
3669 struct mlx5_ib_flow_matcher *fs_matcher,
3670 bool mcast)
d4be3f44 3671{
d4be3f44
YH		 3672 struct mlx5_flow_namespace *ns = NULL;
3673 struct mlx5_ib_flow_prio *prio;
b47fd4ff
MB		 3674 int max_table_size;
3675 u32 flags = 0;
3676 int priority;
3677
3678 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) {
3679 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3680 log_max_ft_size));
3681 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3682 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3683 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3684 reformat_l3_tunnel_to_l2))
3685 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3686 } else { /* Can only be MLX5_FLOW_NAMESPACE_EGRESS */
3687 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3688 log_max_ft_size));
3689 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3690 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3691 }
d4be3f44 3692
d4be3f44
YH		 3693 if (max_table_size < MLX5_FS_MAX_ENTRIES)
3694 return ERR_PTR(-ENOMEM);
3695
3696 if (mcast)
3697 priority = MLX5_IB_FLOW_MCAST_PRIO;
3698 else
b47fd4ff 3699 priority = ib_prio_to_core_prio(fs_matcher->priority, false);
d4be3f44 3700
b47fd4ff 3701 ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type);
d4be3f44
YH		 3702 if (!ns)
3703 return ERR_PTR(-ENOTSUPP);
3704
b47fd4ff
MB		 3705 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS)
3706 prio = &dev->flow_db->prios[priority];
3707 else
3708 prio = &dev->flow_db->egress_prios[priority];
d4be3f44
YH		 3709
3710 if (prio->flow_table)
3711 return prio;
3712
3713 return _get_prio(ns, prio, priority, MLX5_FS_MAX_ENTRIES,
b47fd4ff 3714 MLX5_FS_MAX_TYPES, flags);
d4be3f44
YH		 3715}
3716
3717static struct mlx5_ib_flow_handler *
3718_create_raw_flow_rule(struct mlx5_ib_dev *dev,
3719 struct mlx5_ib_flow_prio *ft_prio,
3720 struct mlx5_flow_destination *dst,
3721 struct mlx5_ib_flow_matcher *fs_matcher,
b823dd6d 3722 struct mlx5_flow_act *flow_act,
bfc5d839
MB		 3723 void *cmd_in, int inlen,
3724 int dst_num)
d4be3f44
YH		 3725{
3726 struct mlx5_ib_flow_handler *handler;
d4be3f44
YH		 3727 struct mlx5_flow_spec *spec;
3728 struct mlx5_flow_table *ft = ft_prio->flow_table;
3729 int err = 0;
3730
3731 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3732 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3733 if (!handler || !spec) {
3734 err = -ENOMEM;
3735 goto free;
3736 }
3737
3738 INIT_LIST_HEAD(&handler->list);
3739
3740 memcpy(spec->match_value, cmd_in, inlen);
3741 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params,
3742 fs_matcher->mask_len);
3743 spec->match_criteria_enable = fs_matcher->match_criteria_enable;
3744
d4be3f44 3745 handler->rule = mlx5_add_flow_rules(ft, spec,
bfc5d839 3746 flow_act, dst, dst_num);
d4be3f44
YH		 3747
3748 if (IS_ERR(handler->rule)) {
3749 err = PTR_ERR(handler->rule);
3750 goto free;
3751 }
3752
3753 ft_prio->refcount++;
3754 handler->prio = ft_prio;
3755 handler->dev = dev;
3756 ft_prio->flow_table = ft;
3757
3758free:
3759 if (err)
3760 kfree(handler);
3761 kvfree(spec);
3762 return err ? ERR_PTR(err) : handler;
3763}
3764
3765static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher,
3766 void *match_v)
3767{
3768 void *match_c;
3769 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4;
3770 void *dmac, *dmac_mask;
3771 void *ipv4, *ipv4_mask;
3772
3773 if (!(fs_matcher->match_criteria_enable &
3774 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT)))
3775 return false;
3776
3777 match_c = fs_matcher->matcher_mask.match_params;
3778 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v,
3779 outer_headers);
3780 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c,
3781 outer_headers);
3782
3783 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
3784 dmac_47_16);
3785 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
3786 dmac_47_16);
3787
3788 if (is_multicast_ether_addr(dmac) &&
3789 is_multicast_ether_addr(dmac_mask))
3790 return true;
3791
3792 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
3793 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3794
3795 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
3796 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3797
3798 if (ipv4_is_multicast(*(__be32 *)(ipv4)) &&
3799 ipv4_is_multicast(*(__be32 *)(ipv4_mask)))
3800 return true;
3801
3802 return false;
3803}
3804
32269441
YH		 3805struct mlx5_ib_flow_handler *
3806mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
3807 struct mlx5_ib_flow_matcher *fs_matcher,
b823dd6d 3808 struct mlx5_flow_act *flow_act,
bfc5d839 3809 u32 counter_id,
32269441
YH		 3810 void *cmd_in, int inlen, int dest_id,
3811 int dest_type)
3812{
d4be3f44
YH		 3813 struct mlx5_flow_destination *dst;
3814 struct mlx5_ib_flow_prio *ft_prio;
d4be3f44 3815 struct mlx5_ib_flow_handler *handler;
bfc5d839 3816 int dst_num = 0;
d4be3f44
YH		 3817 bool mcast;
3818 int err;
3819
3820 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL)
3821 return ERR_PTR(-EOPNOTSUPP);
3822
3823 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO)
3824 return ERR_PTR(-ENOMEM);
3825
8e8aa145 3826 dst = kcalloc(2, sizeof(*dst), GFP_KERNEL);
d4be3f44
YH		 3827 if (!dst)
3828 return ERR_PTR(-ENOMEM);
3829
3830 mcast = raw_fs_is_multicast(fs_matcher, cmd_in);
3831 mutex_lock(&dev->flow_db->lock);
3832
b47fd4ff 3833 ft_prio = _get_flow_table(dev, fs_matcher, mcast);
d4be3f44
YH		 3834 if (IS_ERR(ft_prio)) {
3835 err = PTR_ERR(ft_prio);
3836 goto unlock;
3837 }
3838
6346f0bf 3839 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
bfc5d839
MB		 3840 dst[dst_num].type = dest_type;
3841 dst[dst_num].tir_num = dest_id;
b823dd6d 3842 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
a7ee18bd 3843 } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) {
bfc5d839
MB		 3844 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
3845 dst[dst_num].ft_num = dest_id;
b823dd6d 3846 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
a7ee18bd 3847 } else {
bfc5d839 3848 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_PORT;
a7ee18bd 3849 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
6346f0bf
YH		 3850 }
3851
bfc5d839
MB		 3852 dst_num++;
3853
3854 if (flow_act->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
3855 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
3856 dst[dst_num].counter_id = counter_id;
3857 dst_num++;
3858 }
3859
b823dd6d 3860 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher, flow_act,
bfc5d839 3861 cmd_in, inlen, dst_num);
d4be3f44
YH		 3862
3863 if (IS_ERR(handler)) {
3864 err = PTR_ERR(handler);
3865 goto destroy_ft;
3866 }
3867
3868 mutex_unlock(&dev->flow_db->lock);
3869 atomic_inc(&fs_matcher->usecnt);
3870 handler->flow_matcher = fs_matcher;
3871
3872 kfree(dst);
3873
3874 return handler;
3875
3876destroy_ft:
3877 put_flow_table(dev, ft_prio, false);
3878unlock:
3879 mutex_unlock(&dev->flow_db->lock);
3880 kfree(dst);
3881
3882 return ERR_PTR(err);
32269441
YH		 3883}
3884
c6475a0b
AY		 3885static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
3886{
3887 u32 flags = 0;
3888
3889 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
3890 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
3891
3892 return flags;
3893}
3894
3895#define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
3896static struct ib_flow_action *
3897mlx5_ib_create_flow_action_esp(struct ib_device *device,
3898 const struct ib_flow_action_attrs_esp *attr,
3899 struct uverbs_attr_bundle *attrs)
3900{
3901 struct mlx5_ib_dev *mdev = to_mdev(device);
3902 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
3903 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
3904 struct mlx5_ib_flow_action *action;
3905 u64 action_flags;
3906 u64 flags;
3907 int err = 0;
3908
bccd0622
JG		 3909 err = uverbs_get_flags64(
3910 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
3911 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1));
3912 if (err)
3913 return ERR_PTR(err);
c6475a0b
AY		 3914
3915 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
3916
3917 /* We current only support a subset of the standard features. Only a
3918 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
3919 * (with overlap). Full offload mode isn't supported.
3920 */
3921 if (!attr->keymat || attr->replay || attr->encap ||
3922 attr->spi || attr->seq || attr->tfc_pad ||
3923 attr->hard_limit_pkts ||
3924 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3925 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
3926 return ERR_PTR(-EOPNOTSUPP);
3927
3928 if (attr->keymat->protocol !=
3929 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
3930 return ERR_PTR(-EOPNOTSUPP);
3931
3932 aes_gcm = &attr->keymat->keymat.aes_gcm;
3933
3934 if (aes_gcm->icv_len != 16 ||
3935 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
3936 return ERR_PTR(-EOPNOTSUPP);
3937
3938 action = kmalloc(sizeof(*action), GFP_KERNEL);
3939 if (!action)
3940 return ERR_PTR(-ENOMEM);
3941
3942 action->esp_aes_gcm.ib_flags = attr->flags;
3943 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
3944 sizeof(accel_attrs.keymat.aes_gcm.aes_key));
3945 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
3946 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
3947 sizeof(accel_attrs.keymat.aes_gcm.salt));
3948 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
3949 sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
3950 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
3951 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
3952 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
3953
3954 accel_attrs.esn = attr->esn;
3955 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
3956 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
3957 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3958 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3959
3960 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
3961 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
3962
3963 action->esp_aes_gcm.ctx =
3964 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
3965 if (IS_ERR(action->esp_aes_gcm.ctx)) {
3966 err = PTR_ERR(action->esp_aes_gcm.ctx);
3967 goto err_parse;
3968 }
3969
3970 action->esp_aes_gcm.ib_flags = attr->flags;
3971
3972 return &action->ib_action;
3973
3974err_parse:
3975 kfree(action);
3976 return ERR_PTR(err);
3977}
3978
349705c1
MB		 3979static int
3980mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
3981 const struct ib_flow_action_attrs_esp *attr,
3982 struct uverbs_attr_bundle *attrs)
3983{
3984 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3985 struct mlx5_accel_esp_xfrm_attrs accel_attrs;
3986 int err = 0;
3987
3988 if (attr->keymat || attr->replay || attr->encap ||
3989 attr->spi || attr->seq || attr->tfc_pad ||
3990 attr->hard_limit_pkts ||
3991 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3992 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
3993 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
3994 return -EOPNOTSUPP;
3995
3996 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
3997 * be modified.
3998 */
3999 if (!(maction->esp_aes_gcm.ib_flags &
4000 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
4001 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4002 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
4003 return -EINVAL;
4004
4005 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
4006 sizeof(accel_attrs));
4007
4008 accel_attrs.esn = attr->esn;
4009 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4010 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4011 else
4012 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4013
4014 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
4015 &accel_attrs);
4016 if (err)
4017 return err;
4018
4019 maction->esp_aes_gcm.ib_flags &=
4020 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4021 maction->esp_aes_gcm.ib_flags |=
4022 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4023
4024 return 0;
4025}
4026
c6475a0b
AY		 4027static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
4028{
4029 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4030
4031 switch (action->type) {
4032 case IB_FLOW_ACTION_ESP:
4033 /*
4034 * We only support aes_gcm by now, so we implicitly know this is
4035 * the underline crypto.
4036 */
4037 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
4038 break;
b4749bf2
MB		 4039 case IB_FLOW_ACTION_UNSPECIFIED:
4040 mlx5_ib_destroy_flow_action_raw(maction);
4041 break;
c6475a0b
AY		 4042 default:
4043 WARN_ON(true);
4044 break;
4045 }
4046
4047 kfree(maction);
4048 return 0;
4049}
4050
e126ba97
EC		 4051static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4052{
4053 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 4054 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97 4055 int err;
539ec982
YH		 4056 u16 uid;
4057
4058 uid = ibqp->pd ?
4059 to_mpd(ibqp->pd)->uid : 0;
e126ba97 4060
81e30880
YH		 4061 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
4062 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
4063 return -EOPNOTSUPP;
4064 }
4065
539ec982 4066 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
e126ba97
EC		 4067 if (err)
4068 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
4069 ibqp->qp_num, gid->raw);
4070
4071 return err;
4072}
4073
4074static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4075{
4076 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4077 int err;
539ec982 4078 u16 uid;
e126ba97 4079
539ec982
YH		 4080 uid = ibqp->pd ?
4081 to_mpd(ibqp->pd)->uid : 0;
4082 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
e126ba97
EC		 4083 if (err)
4084 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
4085 ibqp->qp_num, gid->raw);
4086
4087 return err;
4088}
4089
4090static int init_node_data(struct mlx5_ib_dev *dev)
4091{
1b5daf11 4092 int err;
e126ba97 4093
1b5daf11 4094 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 4095 if (err)
1b5daf11 4096 return err;
e126ba97 4097
1b5daf11 4098 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 4099
1b5daf11 4100 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 4101}
4102
508a523f
PP		 4103static ssize_t fw_pages_show(struct device *device,
4104 struct device_attribute *attr, char *buf)
e126ba97
EC		 4105{
4106 struct mlx5_ib_dev *dev =
54747231 4107 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
e126ba97 4108
9603b61d 4109 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97 4110}
508a523f 4111static DEVICE_ATTR_RO(fw_pages);
e126ba97 4112
508a523f 4113static ssize_t reg_pages_show(struct device *device,
e126ba97
EC		 4114 struct device_attribute *attr, char *buf)
4115{
4116 struct mlx5_ib_dev *dev =
54747231 4117 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
e126ba97 4118
6aec21f6 4119 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97 4120}
508a523f 4121static DEVICE_ATTR_RO(reg_pages);
e126ba97 4122
508a523f
PP		 4123static ssize_t hca_type_show(struct device *device,
4124 struct device_attribute *attr, char *buf)
e126ba97
EC		 4125{
4126 struct mlx5_ib_dev *dev =
54747231
PP		 4127 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4128
9603b61d 4129 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97 4130}
508a523f 4131static DEVICE_ATTR_RO(hca_type);
e126ba97 4132
508a523f
PP		 4133static ssize_t hw_rev_show(struct device *device,
4134 struct device_attribute *attr, char *buf)
e126ba97
EC		 4135{
4136 struct mlx5_ib_dev *dev =
54747231
PP		 4137 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4138
9603b61d 4139 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97 4140}
508a523f 4141static DEVICE_ATTR_RO(hw_rev);
e126ba97 4142
508a523f
PP		 4143static ssize_t board_id_show(struct device *device,
4144 struct device_attribute *attr, char *buf)
e126ba97
EC		 4145{
4146 struct mlx5_ib_dev *dev =
54747231
PP		 4147 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4148
e126ba97 4149 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 4150 dev->mdev->board_id);
e126ba97 4151}
508a523f 4152static DEVICE_ATTR_RO(board_id);
e126ba97 4153
508a523f
PP		 4154static struct attribute *mlx5_class_attributes[] = {
4155 &dev_attr_hw_rev.attr,
4156 &dev_attr_hca_type.attr,
4157 &dev_attr_board_id.attr,
4158 &dev_attr_fw_pages.attr,
4159 &dev_attr_reg_pages.attr,
4160 NULL,
4161};
e126ba97 4162
508a523f
PP		 4163static const struct attribute_group mlx5_attr_group = {
4164 .attrs = mlx5_class_attributes,
e126ba97
EC		 4165};
4166
7722f47e
HE		 4167static void pkey_change_handler(struct work_struct *work)
4168{
4169 struct mlx5_ib_port_resources *ports =
4170 container_of(work, struct mlx5_ib_port_resources,
4171 pkey_change_work);
4172
4173 mutex_lock(&ports->devr->mutex);
4174 mlx5_ib_gsi_pkey_change(ports->gsi);
4175 mutex_unlock(&ports->devr->mutex);
4176}
4177
89ea94a7
MG		 4178static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
4179{
4180 struct mlx5_ib_qp *mqp;
4181 struct mlx5_ib_cq *send_mcq, *recv_mcq;
4182 struct mlx5_core_cq *mcq;
4183 struct list_head cq_armed_list;
4184 unsigned long flags_qp;
4185 unsigned long flags_cq;
4186 unsigned long flags;
4187
4188 INIT_LIST_HEAD(&cq_armed_list);
4189
4190 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
4191 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
4192 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
4193 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
4194 if (mqp->sq.tail != mqp->sq.head) {
4195 send_mcq = to_mcq(mqp->ibqp.send_cq);
4196 spin_lock_irqsave(&send_mcq->lock, flags_cq);
4197 if (send_mcq->mcq.comp &&
4198 mqp->ibqp.send_cq->comp_handler) {
4199 if (!send_mcq->mcq.reset_notify_added) {
4200 send_mcq->mcq.reset_notify_added = 1;
4201 list_add_tail(&send_mcq->mcq.reset_notify,
4202 &cq_armed_list);
4203 }
4204 }
4205 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
4206 }
4207 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
4208 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
4209 /* no handling is needed for SRQ */
4210 if (!mqp->ibqp.srq) {
4211 if (mqp->rq.tail != mqp->rq.head) {
4212 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
4213 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
4214 if (recv_mcq->mcq.comp &&
4215 mqp->ibqp.recv_cq->comp_handler) {
4216 if (!recv_mcq->mcq.reset_notify_added) {
4217 recv_mcq->mcq.reset_notify_added = 1;
4218 list_add_tail(&recv_mcq->mcq.reset_notify,
4219 &cq_armed_list);
4220 }
4221 }
4222 spin_unlock_irqrestore(&recv_mcq->lock,
4223 flags_cq);
4224 }
4225 }
4226 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
4227 }
4228 /*At that point all inflight post send were put to be executed as of we
4229 * lock/unlock above locks Now need to arm all involved CQs.
4230 */
4231 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4232 mcq->comp(mcq);
4233 }
4234 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
4235}
4236
03404e8a
MG		 4237static void delay_drop_handler(struct work_struct *work)
4238{
4239 int err;
4240 struct mlx5_ib_delay_drop *delay_drop =
4241 container_of(work, struct mlx5_ib_delay_drop,
4242 delay_drop_work);
4243
fe248c3a
MG		 4244 atomic_inc(&delay_drop->events_cnt);
4245
03404e8a
MG		 4246 mutex_lock(&delay_drop->lock);
4247 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
4248 delay_drop->timeout);
4249 if (err) {
4250 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4251 delay_drop->timeout);
4252 delay_drop->activate = false;
4253 }
4254 mutex_unlock(&delay_drop->lock);
4255}
4256
09e574fa
SM		 4257static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4258 struct ib_event *ibev)
4259{
4260 switch (eqe->sub_type) {
4261 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
4262 schedule_work(&ibdev->delay_drop.delay_drop_work);
4263 break;
4264 default: /* do nothing */
4265 return;
4266 }
4267}
4268
134e9349
SM		 4269static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4270 struct ib_event *ibev)
4271{
4272 u8 port = (eqe->data.port.port >> 4) & 0xf;
4273
4274 ibev->element.port_num = port;
4275
4276 switch (eqe->sub_type) {
4277 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
4278 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
4279 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
4280 /* In RoCE, port up/down events are handled in
4281 * mlx5_netdev_event().
4282 */
4283 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4284 IB_LINK_LAYER_ETHERNET)
4285 return -EINVAL;
4286
4287 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
4288 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
4289 break;
4290
4291 case MLX5_PORT_CHANGE_SUBTYPE_LID:
4292 ibev->event = IB_EVENT_LID_CHANGE;
4293 break;
4294
4295 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
4296 ibev->event = IB_EVENT_PKEY_CHANGE;
4297 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
4298 break;
4299
4300 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
4301 ibev->event = IB_EVENT_GID_CHANGE;
4302 break;
4303
4304 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
4305 ibev->event = IB_EVENT_CLIENT_REREGISTER;
4306 break;
4307 default:
4308 return -EINVAL;
4309 }
4310
4311 return 0;
4312}
4313
d69a24e0 4314static void mlx5_ib_handle_event(struct work_struct *_work)
e126ba97 4315{
d69a24e0
DJ		 4316 struct mlx5_ib_event_work *work =
4317 container_of(_work, struct mlx5_ib_event_work, work);
4318 struct mlx5_ib_dev *ibdev;
e126ba97 4319 struct ib_event ibev;
dbaaff2a 4320 bool fatal = false;
e126ba97 4321
df097a27
SM		 4322 if (work->is_slave) {
4323 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
d69a24e0
DJ		 4324 if (!ibdev)
4325 goto out;
4326 } else {
df097a27 4327 ibdev = work->dev;
d69a24e0
DJ		 4328 }
4329
4330 switch (work->event) {
e126ba97 4331 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 4332 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 4333 mlx5_ib_handle_internal_error(ibdev);
134e9349 4334 ibev.element.port_num = (u8)(unsigned long)work->param;
dbaaff2a 4335 fatal = true;
e126ba97 4336 break;
134e9349
SM		 4337 case MLX5_EVENT_TYPE_PORT_CHANGE:
4338 if (handle_port_change(ibdev, work->param, &ibev))
d69a24e0 4339 goto out;
e126ba97 4340 break;
09e574fa
SM		 4341 case MLX5_EVENT_TYPE_GENERAL_EVENT:
4342 handle_general_event(ibdev, work->param, &ibev);
4343 /* fall through */
bdc37924 4344 default:
03404e8a 4345 goto out;
e126ba97
EC		 4346 }
4347
134e9349 4348 ibev.device = &ibdev->ib_dev;
e126ba97 4349
134e9349
SM		 4350 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
4351 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num);
03404e8a 4352 goto out;
a0c84c32
EC		 4353 }
4354
e126ba97
EC		 4355 if (ibdev->ib_active)
4356 ib_dispatch_event(&ibev);
dbaaff2a
EC		 4357
4358 if (fatal)
4359 ibdev->ib_active = false;
03404e8a 4360out:
d69a24e0
DJ		 4361 kfree(work);
4362}
4363
df097a27
SM		 4364static int mlx5_ib_event(struct notifier_block *nb,
4365 unsigned long event, void *param)
d69a24e0
DJ		 4366{
4367 struct mlx5_ib_event_work *work;
4368
4369 work = kmalloc(sizeof(*work), GFP_ATOMIC);
10bea9c8 4370 if (!work)
df097a27 4371 return NOTIFY_DONE;
d69a24e0 4372
10bea9c8 4373 INIT_WORK(&work->work, mlx5_ib_handle_event);
df097a27
SM		 4374 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
4375 work->is_slave = false;
10bea9c8 4376 work->param = param;
10bea9c8
LR		 4377 work->event = event;
4378
4379 queue_work(mlx5_ib_event_wq, &work->work);
df097a27
SM		 4380
4381 return NOTIFY_OK;
4382}
4383
4384static int mlx5_ib_event_slave_port(struct notifier_block *nb,
4385 unsigned long event, void *param)
4386{
4387 struct mlx5_ib_event_work *work;
4388
4389 work = kmalloc(sizeof(*work), GFP_ATOMIC);
4390 if (!work)
4391 return NOTIFY_DONE;
4392
4393 INIT_WORK(&work->work, mlx5_ib_handle_event);
4394 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
4395 work->is_slave = true;
4396 work->param = param;
4397 work->event = event;
4398 queue_work(mlx5_ib_event_wq, &work->work);
4399
4400 return NOTIFY_OK;
e126ba97
EC		 4401}
4402
c43f1112
MG		 4403static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4404{
4405 struct mlx5_hca_vport_context vport_ctx;
4406 int err;
4407 int port;
4408
508562d6 4409 for (port = 1; port <= dev->num_ports; port++) {
c43f1112
MG		 4410 dev->mdev->port_caps[port - 1].has_smi = false;
4411 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4412 MLX5_CAP_PORT_TYPE_IB) {
4413 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4414 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4415 port, 0,
4416 &vport_ctx);
4417 if (err) {
4418 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4419 port, err);
4420 return err;
4421 }
4422 dev->mdev->port_caps[port - 1].has_smi =
4423 vport_ctx.has_smi;
4424 } else {
4425 dev->mdev->port_caps[port - 1].has_smi = true;
4426 }
4427 }
4428 }
4429 return 0;
4430}
4431
e126ba97
EC		 4432static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4433{
4434 int port;
4435
508562d6 4436 for (port = 1; port <= dev->num_ports; port++)
e126ba97
EC		 4437 mlx5_query_ext_port_caps(dev, port);
4438}
4439
32f69e4b 4440static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
e126ba97
EC		 4441{
4442 struct ib_device_attr *dprops = NULL;
4443 struct ib_port_attr *pprops = NULL;
f614fc15 4444 int err = -ENOMEM;
2528e33e 4445 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 4446
4447 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
4448 if (!pprops)
4449 goto out;
4450
4451 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4452 if (!dprops)
4453 goto out;
4454
c43f1112
MG		 4455 err = set_has_smi_cap(dev);
4456 if (err)
4457 goto out;
4458
2528e33e 4459 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 4460 if (err) {
4461 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4462 goto out;
4463 }
4464
32f69e4b
DJ		 4465 memset(pprops, 0, sizeof(*pprops));
4466 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4467 if (err) {
4468 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4469 port, err);
4470 goto out;
e126ba97
EC		 4471 }
4472
32f69e4b
DJ		 4473 dev->mdev->port_caps[port - 1].pkey_table_len =
4474 dprops->max_pkeys;
4475 dev->mdev->port_caps[port - 1].gid_table_len =
4476 pprops->gid_tbl_len;
4477 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4478 port, dprops->max_pkeys, pprops->gid_tbl_len);
4479
e126ba97
EC		 4480out:
4481 kfree(pprops);
4482 kfree(dprops);
4483
4484 return err;
4485}
4486
4487static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4488{
4489 int err;
4490
4491 err = mlx5_mr_cache_cleanup(dev);
4492 if (err)
4493 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4494
32927e28
MB		 4495 if (dev->umrc.qp)
4496 mlx5_ib_destroy_qp(dev->umrc.qp);
4497 if (dev->umrc.cq)
4498 ib_free_cq(dev->umrc.cq);
4499 if (dev->umrc.pd)
4500 ib_dealloc_pd(dev->umrc.pd);
e126ba97
EC		 4501}
4502
4503enum {
4504 MAX_UMR_WR = 128,
4505};
4506
4507static int create_umr_res(struct mlx5_ib_dev *dev)
4508{
4509 struct ib_qp_init_attr *init_attr = NULL;
4510 struct ib_qp_attr *attr = NULL;
4511 struct ib_pd *pd;
4512 struct ib_cq *cq;
4513 struct ib_qp *qp;
e126ba97
EC		 4514 int ret;
4515
4516 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4517 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4518 if (!attr || !init_attr) {
4519 ret = -ENOMEM;
4520 goto error_0;
4521 }
4522
ed082d36 4523 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 4524 if (IS_ERR(pd)) {
4525 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4526 ret = PTR_ERR(pd);
4527 goto error_0;
4528 }
4529
add08d76 4530 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 4531 if (IS_ERR(cq)) {
4532 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4533 ret = PTR_ERR(cq);
4534 goto error_2;
4535 }
e126ba97
EC		 4536
4537 init_attr->send_cq = cq;
4538 init_attr->recv_cq = cq;
4539 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4540 init_attr->cap.max_send_wr = MAX_UMR_WR;
4541 init_attr->cap.max_send_sge = 1;
4542 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4543 init_attr->port_num = 1;
4544 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4545 if (IS_ERR(qp)) {
4546 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4547 ret = PTR_ERR(qp);
4548 goto error_3;
4549 }
4550 qp->device = &dev->ib_dev;
4551 qp->real_qp = qp;
4552 qp->uobject = NULL;
4553 qp->qp_type = MLX5_IB_QPT_REG_UMR;
31fde034
MD		 4554 qp->send_cq = init_attr->send_cq;
4555 qp->recv_cq = init_attr->recv_cq;
e126ba97
EC		 4556
4557 attr->qp_state = IB_QPS_INIT;
4558 attr->port_num = 1;
4559 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4560 IB_QP_PORT, NULL);
4561 if (ret) {
4562 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4563 goto error_4;
4564 }
4565
4566 memset(attr, 0, sizeof(*attr));
4567 attr->qp_state = IB_QPS_RTR;
4568 attr->path_mtu = IB_MTU_256;
4569
4570 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4571 if (ret) {
4572 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4573 goto error_4;
4574 }
4575
4576 memset(attr, 0, sizeof(*attr));
4577 attr->qp_state = IB_QPS_RTS;
4578 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4579 if (ret) {
4580 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4581 goto error_4;
4582 }
4583
4584 dev->umrc.qp = qp;
4585 dev->umrc.cq = cq;
e126ba97
EC		 4586 dev->umrc.pd = pd;
4587
4588 sema_init(&dev->umrc.sem, MAX_UMR_WR);
4589 ret = mlx5_mr_cache_init(dev);
4590 if (ret) {
4591 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4592 goto error_4;
4593 }
4594
4595 kfree(attr);
4596 kfree(init_attr);
4597
4598 return 0;
4599
4600error_4:
4601 mlx5_ib_destroy_qp(qp);
32927e28 4602 dev->umrc.qp = NULL;
e126ba97
EC		 4603
4604error_3:
add08d76 4605 ib_free_cq(cq);
32927e28 4606 dev->umrc.cq = NULL;
e126ba97
EC		 4607
4608error_2:
e126ba97 4609 ib_dealloc_pd(pd);
32927e28 4610 dev->umrc.pd = NULL;
e126ba97
EC		 4611
4612error_0:
4613 kfree(attr);
4614 kfree(init_attr);
4615 return ret;
4616}
4617
6e8484c5
MG		 4618static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4619{
4620 switch (umr_fence_cap) {
4621 case MLX5_CAP_UMR_FENCE_NONE:
4622 return MLX5_FENCE_MODE_NONE;
4623 case MLX5_CAP_UMR_FENCE_SMALL:
4624 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4625 default:
4626 return MLX5_FENCE_MODE_STRONG_ORDERING;
4627 }
4628}
4629
e126ba97
EC		 4630static int create_dev_resources(struct mlx5_ib_resources *devr)
4631{
4632 struct ib_srq_init_attr attr;
4633 struct mlx5_ib_dev *dev;
bcf4c1ea 4634 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 4635 int port;
e126ba97
EC		 4636 int ret = 0;
4637
4638 dev = container_of(devr, struct mlx5_ib_dev, devr);
4639
d16e91da
HE		 4640 mutex_init(&devr->mutex);
4641
e126ba97
EC		 4642 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
4643 if (IS_ERR(devr->p0)) {
4644 ret = PTR_ERR(devr->p0);
4645 goto error0;
4646 }
4647 devr->p0->device = &dev->ib_dev;
4648 devr->p0->uobject = NULL;
4649 atomic_set(&devr->p0->usecnt, 0);
4650
bcf4c1ea 4651 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 4652 if (IS_ERR(devr->c0)) {
4653 ret = PTR_ERR(devr->c0);
4654 goto error1;
4655 }
4656 devr->c0->device = &dev->ib_dev;
4657 devr->c0->uobject = NULL;
4658 devr->c0->comp_handler = NULL;
4659 devr->c0->event_handler = NULL;
4660 devr->c0->cq_context = NULL;
4661 atomic_set(&devr->c0->usecnt, 0);
4662
4663 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4664 if (IS_ERR(devr->x0)) {
4665 ret = PTR_ERR(devr->x0);
4666 goto error2;
4667 }
4668 devr->x0->device = &dev->ib_dev;
4669 devr->x0->inode = NULL;
4670 atomic_set(&devr->x0->usecnt, 0);
4671 mutex_init(&devr->x0->tgt_qp_mutex);
4672 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4673
4674 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4675 if (IS_ERR(devr->x1)) {
4676 ret = PTR_ERR(devr->x1);
4677 goto error3;
4678 }
4679 devr->x1->device = &dev->ib_dev;
4680 devr->x1->inode = NULL;
4681 atomic_set(&devr->x1->usecnt, 0);
4682 mutex_init(&devr->x1->tgt_qp_mutex);
4683 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4684
4685 memset(&attr, 0, sizeof(attr));
4686 attr.attr.max_sge = 1;
4687 attr.attr.max_wr = 1;
4688 attr.srq_type = IB_SRQT_XRC;
1a56ff6d 4689 attr.ext.cq = devr->c0;
e126ba97
EC		 4690 attr.ext.xrc.xrcd = devr->x0;
4691
4692 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4693 if (IS_ERR(devr->s0)) {
4694 ret = PTR_ERR(devr->s0);
4695 goto error4;
4696 }
4697 devr->s0->device = &dev->ib_dev;
4698 devr->s0->pd = devr->p0;
4699 devr->s0->uobject = NULL;
4700 devr->s0->event_handler = NULL;
4701 devr->s0->srq_context = NULL;
4702 devr->s0->srq_type = IB_SRQT_XRC;
4703 devr->s0->ext.xrc.xrcd = devr->x0;
1a56ff6d 4704 devr->s0->ext.cq = devr->c0;
e126ba97 4705 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1a56ff6d 4706 atomic_inc(&devr->s0->ext.cq->usecnt);
e126ba97
EC		 4707 atomic_inc(&devr->p0->usecnt);
4708 atomic_set(&devr->s0->usecnt, 0);
4709
4aa17b28
HA		 4710 memset(&attr, 0, sizeof(attr));
4711 attr.attr.max_sge = 1;
4712 attr.attr.max_wr = 1;
4713 attr.srq_type = IB_SRQT_BASIC;
4714 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4715 if (IS_ERR(devr->s1)) {
4716 ret = PTR_ERR(devr->s1);
4717 goto error5;
4718 }
4719 devr->s1->device = &dev->ib_dev;
4720 devr->s1->pd = devr->p0;
4721 devr->s1->uobject = NULL;
4722 devr->s1->event_handler = NULL;
4723 devr->s1->srq_context = NULL;
4724 devr->s1->srq_type = IB_SRQT_BASIC;
1a56ff6d 4725 devr->s1->ext.cq = devr->c0;
4aa17b28 4726 atomic_inc(&devr->p0->usecnt);
1a56ff6d 4727 atomic_set(&devr->s1->usecnt, 0);
4aa17b28 4728
7722f47e
HE		 4729 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
4730 INIT_WORK(&devr->ports[port].pkey_change_work,
4731 pkey_change_handler);
4732 devr->ports[port].devr = devr;
4733 }
4734
e126ba97
EC		 4735 return 0;
4736
4aa17b28
HA		 4737error5:
4738 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 4739error4:
4740 mlx5_ib_dealloc_xrcd(devr->x1);
4741error3:
4742 mlx5_ib_dealloc_xrcd(devr->x0);
4743error2:
4744 mlx5_ib_destroy_cq(devr->c0);
4745error1:
4746 mlx5_ib_dealloc_pd(devr->p0);
4747error0:
4748 return ret;
4749}
4750
4751static void destroy_dev_resources(struct mlx5_ib_resources *devr)
4752{
7722f47e
HE		 4753 struct mlx5_ib_dev *dev =
4754 container_of(devr, struct mlx5_ib_dev, devr);
4755 int port;
4756
4aa17b28 4757 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 4758 mlx5_ib_destroy_srq(devr->s0);
4759 mlx5_ib_dealloc_xrcd(devr->x0);
4760 mlx5_ib_dealloc_xrcd(devr->x1);
4761 mlx5_ib_destroy_cq(devr->c0);
4762 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 4763
4764 /* Make sure no change P_Key work items are still executing */
4765 for (port = 0; port < dev->num_ports; ++port)
4766 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 4767}
4768
b02289b3
AK		 4769static u32 get_core_cap_flags(struct ib_device *ibdev,
4770 struct mlx5_hca_vport_context *rep)
e53505a8
AS		 4771{
4772 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4773 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
4774 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
4775 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
85c7c014 4776 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
e53505a8
AS		 4777 u32 ret = 0;
4778
b02289b3
AK		 4779 if (rep->grh_required)
4780 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
4781
e53505a8 4782 if (ll == IB_LINK_LAYER_INFINIBAND)
b02289b3 4783 return ret | RDMA_CORE_PORT_IBA_IB;
e53505a8 4784
85c7c014 4785 if (raw_support)
b02289b3 4786 ret |= RDMA_CORE_PORT_RAW_PACKET;
72cd5717 4787
e53505a8 4788 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 4789 return ret;
e53505a8
AS		 4790
4791 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 4792 return ret;
e53505a8
AS		 4793
4794 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
4795 ret |= RDMA_CORE_PORT_IBA_ROCE;
4796
4797 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
4798 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
4799
4800 return ret;
4801}
4802
7738613e
IW		 4803static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
4804 struct ib_port_immutable *immutable)
4805{
4806 struct ib_port_attr attr;
ca5b91d6
OG		 4807 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4808 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
b02289b3 4809 struct mlx5_hca_vport_context rep = {0};
7738613e
IW		 4810 int err;
4811
c4550c63 4812 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 4813 if (err)
4814 return err;
4815
b02289b3
AK		 4816 if (ll == IB_LINK_LAYER_INFINIBAND) {
4817 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
4818 &rep);
4819 if (err)
4820 return err;
4821 }
4822
7738613e
IW		 4823 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4824 immutable->gid_tbl_len = attr.gid_tbl_len;
b02289b3 4825 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
ca5b91d6
OG		 4826 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
4827 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 4828
4829 return 0;
4830}
4831
8e6efa3a
MB		 4832static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
4833 struct ib_port_immutable *immutable)
4834{
4835 struct ib_port_attr attr;
4836 int err;
4837
4838 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4839
4840 err = ib_query_port(ibdev, port_num, &attr);
4841 if (err)
4842 return err;
4843
4844 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4845 immutable->gid_tbl_len = attr.gid_tbl_len;
4846 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4847
4848 return 0;
4849}
4850
9abb0d1b 4851static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 4852{
4853 struct mlx5_ib_dev *dev =
4854 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 4855 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
4856 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
4857 fw_rev_sub(dev->mdev));
c7342823
IW		 4858}
4859
45f95acd 4860static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 4861{
4862 struct mlx5_core_dev *mdev = dev->mdev;
4863 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
4864 MLX5_FLOW_NAMESPACE_LAG);
4865 struct mlx5_flow_table *ft;
4866 int err;
4867
7c34ec19 4868 if (!ns || !mlx5_lag_is_roce(mdev))
9ef9c640
AH		 4869 return 0;
4870
4871 err = mlx5_cmd_create_vport_lag(mdev);
4872 if (err)
4873 return err;
4874
4875 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
4876 if (IS_ERR(ft)) {
4877 err = PTR_ERR(ft);
4878 goto err_destroy_vport_lag;
4879 }
4880
9a4ca38d 4881 dev->flow_db->lag_demux_ft = ft;
7c34ec19 4882 dev->lag_active = true;
9ef9c640
AH		 4883 return 0;
4884
4885err_destroy_vport_lag:
4886 mlx5_cmd_destroy_vport_lag(mdev);
4887 return err;
4888}
4889
45f95acd 4890static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 4891{
4892 struct mlx5_core_dev *mdev = dev->mdev;
4893
7c34ec19
AH		 4894 if (dev->lag_active) {
4895 dev->lag_active = false;
4896
9a4ca38d
MB		 4897 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
4898 dev->flow_db->lag_demux_ft = NULL;
9ef9c640
AH		 4899
4900 mlx5_cmd_destroy_vport_lag(mdev);
4901 }
4902}
4903
7fd8aefb 4904static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
d012f5d6
OG		 4905{
4906 int err;
4907
7fd8aefb
DJ		 4908 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
4909 err = register_netdevice_notifier(&dev->roce[port_num].nb);
d012f5d6 4910 if (err) {
7fd8aefb 4911 dev->roce[port_num].nb.notifier_call = NULL;
d012f5d6
OG		 4912 return err;
4913 }
4914
4915 return 0;
4916}
4917
7fd8aefb 4918static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5ec8c83e 4919{
7fd8aefb
DJ		 4920 if (dev->roce[port_num].nb.notifier_call) {
4921 unregister_netdevice_notifier(&dev->roce[port_num].nb);
4922 dev->roce[port_num].nb.notifier_call = NULL;
5ec8c83e
AH		 4923 }
4924}
4925
e3f1ed1f 4926static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 4927{
e53505a8
AS		 4928 int err;
4929
ca5b91d6
OG		 4930 if (MLX5_CAP_GEN(dev->mdev, roce)) {
4931 err = mlx5_nic_vport_enable_roce(dev->mdev);
4932 if (err)
8e6efa3a 4933 return err;
ca5b91d6 4934 }
e53505a8 4935
45f95acd 4936 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 4937 if (err)
4938 goto err_disable_roce;
4939
e53505a8
AS		 4940 return 0;
4941
9ef9c640 4942err_disable_roce:
ca5b91d6
OG		 4943 if (MLX5_CAP_GEN(dev->mdev, roce))
4944 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 4945
e53505a8 4946 return err;
fc24fc5e
AS		 4947}
4948
45f95acd 4949static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 4950{
45f95acd 4951 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 4952 if (MLX5_CAP_GEN(dev->mdev, roce))
4953 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 4954}
4955
e1f24a79 4956struct mlx5_ib_counter {
7c16f477
KH		 4957 const char *name;
4958 size_t offset;
4959};
4960
4961#define INIT_Q_COUNTER(_name) \
4962 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
4963
e1f24a79 4964static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 4965 INIT_Q_COUNTER(rx_write_requests),
4966 INIT_Q_COUNTER(rx_read_requests),
4967 INIT_Q_COUNTER(rx_atomic_requests),
4968 INIT_Q_COUNTER(out_of_buffer),
4969};
4970
e1f24a79 4971static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 4972 INIT_Q_COUNTER(out_of_sequence),
4973};
4974
e1f24a79 4975static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 4976 INIT_Q_COUNTER(duplicate_request),
4977 INIT_Q_COUNTER(rnr_nak_retry_err),
4978 INIT_Q_COUNTER(packet_seq_err),
4979 INIT_Q_COUNTER(implied_nak_seq_err),
4980 INIT_Q_COUNTER(local_ack_timeout_err),
4981};
4982
e1f24a79
PP		 4983#define INIT_CONG_COUNTER(_name) \
4984 { .name = #_name, .offset = \
4985 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
4986
4987static const struct mlx5_ib_counter cong_cnts[] = {
4988 INIT_CONG_COUNTER(rp_cnp_ignored),
4989 INIT_CONG_COUNTER(rp_cnp_handled),
4990 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
4991 INIT_CONG_COUNTER(np_cnp_sent),
4992};
4993
58dcb60a
PP		 4994static const struct mlx5_ib_counter extended_err_cnts[] = {
4995 INIT_Q_COUNTER(resp_local_length_error),
4996 INIT_Q_COUNTER(resp_cqe_error),
4997 INIT_Q_COUNTER(req_cqe_error),
4998 INIT_Q_COUNTER(req_remote_invalid_request),
4999 INIT_Q_COUNTER(req_remote_access_errors),
5000 INIT_Q_COUNTER(resp_remote_access_errors),
5001 INIT_Q_COUNTER(resp_cqe_flush_error),
5002 INIT_Q_COUNTER(req_cqe_flush_error),
5003};
5004
9f876f3d
TB		 5005#define INIT_EXT_PPCNT_COUNTER(_name) \
5006 { .name = #_name, .offset = \
5007 MLX5_BYTE_OFF(ppcnt_reg, \
5008 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
5009
5010static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
5011 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
5012};
5013
e1f24a79 5014static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a 5015{
aac4492e 5016 int i;
0837e86a 5017
7c16f477 5018 for (i = 0; i < dev->num_ports; i++) {
921c0f5b 5019 if (dev->port[i].cnts.set_id_valid)
aac4492e
DJ		 5020 mlx5_core_dealloc_q_counter(dev->mdev,
5021 dev->port[i].cnts.set_id);
e1f24a79
PP		 5022 kfree(dev->port[i].cnts.names);
5023 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 5024 }
5025}
5026
e1f24a79
PP		 5027static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
5028 struct mlx5_ib_counters *cnts)
7c16f477
KH		 5029{
5030 u32 num_counters;
5031
5032 num_counters = ARRAY_SIZE(basic_q_cnts);
5033
5034 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
5035 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
5036
5037 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
5038 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 5039
5040 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
5041 num_counters += ARRAY_SIZE(extended_err_cnts);
5042
e1f24a79 5043 cnts->num_q_counters = num_counters;
7c16f477 5044
e1f24a79
PP		 5045 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5046 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
5047 num_counters += ARRAY_SIZE(cong_cnts);
5048 }
9f876f3d
TB		 5049 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5050 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
5051 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
5052 }
e1f24a79
PP		 5053 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
5054 if (!cnts->names)
7c16f477
KH		 5055 return -ENOMEM;
5056
e1f24a79
PP		 5057 cnts->offsets = kcalloc(num_counters,
5058 sizeof(cnts->offsets), GFP_KERNEL);
5059 if (!cnts->offsets)
7c16f477
KH		 5060 goto err_names;
5061
7c16f477
KH		 5062 return 0;
5063
5064err_names:
e1f24a79 5065 kfree(cnts->names);
aac4492e 5066 cnts->names = NULL;
7c16f477
KH		 5067 return -ENOMEM;
5068}
5069
e1f24a79
PP		 5070static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
5071 const char **names,
5072 size_t *offsets)
7c16f477
KH		 5073{
5074 int i;
5075 int j = 0;
5076
5077 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
5078 names[j] = basic_q_cnts[i].name;
5079 offsets[j] = basic_q_cnts[i].offset;
5080 }
5081
5082 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
5083 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
5084 names[j] = out_of_seq_q_cnts[i].name;
5085 offsets[j] = out_of_seq_q_cnts[i].offset;
5086 }
5087 }
5088
5089 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
5090 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
5091 names[j] = retrans_q_cnts[i].name;
5092 offsets[j] = retrans_q_cnts[i].offset;
5093 }
5094 }
e1f24a79 5095
58dcb60a
PP		 5096 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
5097 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
5098 names[j] = extended_err_cnts[i].name;
5099 offsets[j] = extended_err_cnts[i].offset;
5100 }
5101 }
5102
e1f24a79
PP		 5103 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5104 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
5105 names[j] = cong_cnts[i].name;
5106 offsets[j] = cong_cnts[i].offset;
5107 }
5108 }
9f876f3d
TB		 5109
5110 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5111 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
5112 names[j] = ext_ppcnt_cnts[i].name;
5113 offsets[j] = ext_ppcnt_cnts[i].offset;
5114 }
5115 }
0837e86a
MB		 5116}
5117
e1f24a79 5118static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a 5119{
aac4492e 5120 int err = 0;
0837e86a 5121 int i;
aa74be6e
YH		 5122 bool is_shared;
5123
5124 is_shared = MLX5_CAP_GEN(dev->mdev, log_max_uctx) != 0;
0837e86a
MB		 5125
5126 for (i = 0; i < dev->num_ports; i++) {
aac4492e
DJ		 5127 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
5128 if (err)
5129 goto err_alloc;
5130
5131 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
5132 dev->port[i].cnts.offsets);
7c16f477 5133
aa74be6e
YH		 5134 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5135 &dev->port[i].cnts.set_id,
5136 is_shared ?
5137 MLX5_SHARED_RESOURCE_UID : 0);
aac4492e 5138 if (err) {
0837e86a
MB		 5139 mlx5_ib_warn(dev,
5140 "couldn't allocate queue counter for port %d, err %d\n",
aac4492e
DJ		 5141 i + 1, err);
5142 goto err_alloc;
0837e86a 5143 }
aac4492e 5144 dev->port[i].cnts.set_id_valid = true;
0837e86a
MB		 5145 }
5146
5147 return 0;
5148
aac4492e
DJ		 5149err_alloc:
5150 mlx5_ib_dealloc_counters(dev);
5151 return err;
0837e86a
MB		 5152}
5153
0ad17a8f
MB		 5154static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
5155 u8 port_num)
5156{
7c16f477
KH		 5157 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5158 struct mlx5_ib_port *port = &dev->port[port_num - 1];
0ad17a8f
MB		 5159
5160 /* We support only per port stats */
5161 if (port_num == 0)
5162 return NULL;
5163
e1f24a79
PP		 5164 return rdma_alloc_hw_stats_struct(port->cnts.names,
5165 port->cnts.num_q_counters +
9f876f3d
TB		 5166 port->cnts.num_cong_counters +
5167 port->cnts.num_ext_ppcnt_counters,
0ad17a8f
MB		 5168 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5169}
5170
aac4492e 5171static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
e1f24a79
PP		 5172 struct mlx5_ib_port *port,
5173 struct rdma_hw_stats *stats)
0ad17a8f 5174{
0ad17a8f
MB		 5175 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
5176 void *out;
5177 __be32 val;
e1f24a79 5178 int ret, i;
0ad17a8f 5179
1b9a07ee 5180 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 5181 if (!out)
5182 return -ENOMEM;
5183
aac4492e 5184 ret = mlx5_core_query_q_counter(mdev,
e1f24a79 5185 port->cnts.set_id, 0,
0ad17a8f
MB		 5186 out, outlen);
5187 if (ret)
5188 goto free;
5189
e1f24a79
PP		 5190 for (i = 0; i < port->cnts.num_q_counters; i++) {
5191 val = *(__be32 *)(out + port->cnts.offsets[i]);
0ad17a8f
MB		 5192 stats->value[i] = (u64)be32_to_cpu(val);
5193 }
7c16f477 5194
0ad17a8f
MB		 5195free:
5196 kvfree(out);
e1f24a79
PP		 5197 return ret;
5198}
5199
9f876f3d
TB		 5200static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
5201 struct mlx5_ib_port *port,
5202 struct rdma_hw_stats *stats)
5203{
5204 int offset = port->cnts.num_q_counters + port->cnts.num_cong_counters;
5205 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
5206 int ret, i;
5207 void *out;
5208
5209 out = kvzalloc(sz, GFP_KERNEL);
5210 if (!out)
5211 return -ENOMEM;
5212
5213 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
5214 if (ret)
5215 goto free;
5216
5217 for (i = 0; i < port->cnts.num_ext_ppcnt_counters; i++) {
5218 stats->value[i + offset] =
5219 be64_to_cpup((__be64 *)(out +
5220 port->cnts.offsets[i + offset]));
5221 }
5222
5223free:
5224 kvfree(out);
5225 return ret;
5226}
5227
e1f24a79
PP		 5228static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
5229 struct rdma_hw_stats *stats,
5230 u8 port_num, int index)
5231{
5232 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5233 struct mlx5_ib_port *port = &dev->port[port_num - 1];
aac4492e 5234 struct mlx5_core_dev *mdev;
e1f24a79 5235 int ret, num_counters;
aac4492e 5236 u8 mdev_port_num;
e1f24a79
PP		 5237
5238 if (!stats)
5239 return -EINVAL;
5240
9f876f3d
TB		 5241 num_counters = port->cnts.num_q_counters +
5242 port->cnts.num_cong_counters +
5243 port->cnts.num_ext_ppcnt_counters;
aac4492e
DJ		 5244
5245 /* q_counters are per IB device, query the master mdev */
5246 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
e1f24a79
PP		 5247 if (ret)
5248 return ret;
e1f24a79 5249
9f876f3d
TB		 5250 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5251 ret = mlx5_ib_query_ext_ppcnt_counters(dev, port, stats);
5252 if (ret)
5253 return ret;
5254 }
5255
e1f24a79 5256 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
aac4492e
DJ		 5257 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
5258 &mdev_port_num);
5259 if (!mdev) {
5260 /* If port is not affiliated yet, its in down state
5261 * which doesn't have any counters yet, so it would be
5262 * zero. So no need to read from the HCA.
5263 */
5264 goto done;
5265 }
71a0ff65
MD		 5266 ret = mlx5_lag_query_cong_counters(dev->mdev,
5267 stats->value +
5268 port->cnts.num_q_counters,
5269 port->cnts.num_cong_counters,
5270 port->cnts.offsets +
5271 port->cnts.num_q_counters);
aac4492e
DJ		 5272
5273 mlx5_ib_put_native_port_mdev(dev, port_num);
e1f24a79
PP		 5274 if (ret)
5275 return ret;
e1f24a79
PP		 5276 }
5277
aac4492e 5278done:
e1f24a79 5279 return num_counters;
0ad17a8f
MB		 5280}
5281
f6a8a19b
DD		 5282static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num,
5283 enum rdma_netdev_t type,
5284 struct rdma_netdev_alloc_params *params)
693dfd5a
ES		 5285{
5286 if (type != RDMA_NETDEV_IPOIB)
f6a8a19b 5287 return -EOPNOTSUPP;
693dfd5a 5288
f6a8a19b 5289 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
693dfd5a
ES		 5290}
5291
fe248c3a
MG		 5292static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
5293{
5294 if (!dev->delay_drop.dbg)
5295 return;
5296 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
5297 kfree(dev->delay_drop.dbg);
5298 dev->delay_drop.dbg = NULL;
5299}
5300
03404e8a
MG		 5301static void cancel_delay_drop(struct mlx5_ib_dev *dev)
5302{
5303 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5304 return;
5305
5306 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 5307 delay_drop_debugfs_cleanup(dev);
5308}
5309
5310static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5311 size_t count, loff_t *pos)
5312{
5313 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5314 char lbuf[20];
5315 int len;
5316
5317 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5318 return simple_read_from_buffer(buf, count, pos, lbuf, len);
5319}
5320
5321static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5322 size_t count, loff_t *pos)
5323{
5324 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5325 u32 timeout;
5326 u32 var;
5327
5328 if (kstrtouint_from_user(buf, count, 0, &var))
5329 return -EFAULT;
5330
5331 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5332 1000);
5333 if (timeout != var)
5334 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5335 timeout);
5336
5337 delay_drop->timeout = timeout;
5338
5339 return count;
5340}
5341
5342static const struct file_operations fops_delay_drop_timeout = {
5343 .owner = THIS_MODULE,
5344 .open = simple_open,
5345 .write = delay_drop_timeout_write,
5346 .read = delay_drop_timeout_read,
5347};
5348
5349static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5350{
5351 struct mlx5_ib_dbg_delay_drop *dbg;
5352
5353 if (!mlx5_debugfs_root)
5354 return 0;
5355
5356 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
5357 if (!dbg)
5358 return -ENOMEM;
5359
cbafad87
SM		 5360 dev->delay_drop.dbg = dbg;
5361
fe248c3a
MG		 5362 dbg->dir_debugfs =
5363 debugfs_create_dir("delay_drop",
5364 dev->mdev->priv.dbg_root);
5365 if (!dbg->dir_debugfs)
cbafad87 5366 goto out_debugfs;
fe248c3a
MG		 5367
5368 dbg->events_cnt_debugfs =
5369 debugfs_create_atomic_t("num_timeout_events", 0400,
5370 dbg->dir_debugfs,
5371 &dev->delay_drop.events_cnt);
5372 if (!dbg->events_cnt_debugfs)
5373 goto out_debugfs;
5374
5375 dbg->rqs_cnt_debugfs =
5376 debugfs_create_atomic_t("num_rqs", 0400,
5377 dbg->dir_debugfs,
5378 &dev->delay_drop.rqs_cnt);
5379 if (!dbg->rqs_cnt_debugfs)
5380 goto out_debugfs;
5381
5382 dbg->timeout_debugfs =
5383 debugfs_create_file("timeout", 0600,
5384 dbg->dir_debugfs,
5385 &dev->delay_drop,
5386 &fops_delay_drop_timeout);
5387 if (!dbg->timeout_debugfs)
5388 goto out_debugfs;
5389
5390 return 0;
5391
5392out_debugfs:
5393 delay_drop_debugfs_cleanup(dev);
5394 return -ENOMEM;
03404e8a
MG		 5395}
5396
5397static void init_delay_drop(struct mlx5_ib_dev *dev)
5398{
5399 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5400 return;
5401
5402 mutex_init(&dev->delay_drop.lock);
5403 dev->delay_drop.dev = dev;
5404 dev->delay_drop.activate = false;
5405 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5406 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 5407 atomic_set(&dev->delay_drop.rqs_cnt, 0);
5408 atomic_set(&dev->delay_drop.events_cnt, 0);
5409
5410 if (delay_drop_debugfs_init(dev))
5411 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
03404e8a
MG		 5412}
5413
32f69e4b
DJ		 5414/* The mlx5_ib_multiport_mutex should be held when calling this function */
5415static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5416 struct mlx5_ib_multiport_info *mpi)
5417{
5418 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5419 struct mlx5_ib_port *port = &ibdev->port[port_num];
5420 int comps;
5421 int err;
5422 int i;
5423
a9e546e7
PP		 5424 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5425
32f69e4b
DJ		 5426 spin_lock(&port->mp.mpi_lock);
5427 if (!mpi->ibdev) {
5428 spin_unlock(&port->mp.mpi_lock);
5429 return;
5430 }
df097a27
SM		 5431
5432 if (mpi->mdev_events.notifier_call)
5433 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
5434 mpi->mdev_events.notifier_call = NULL;
5435
32f69e4b
DJ		 5436 mpi->ibdev = NULL;
5437
5438 spin_unlock(&port->mp.mpi_lock);
5439 mlx5_remove_netdev_notifier(ibdev, port_num);
5440 spin_lock(&port->mp.mpi_lock);
5441
5442 comps = mpi->mdev_refcnt;
5443 if (comps) {
5444 mpi->unaffiliate = true;
5445 init_completion(&mpi->unref_comp);
5446 spin_unlock(&port->mp.mpi_lock);
5447
5448 for (i = 0; i < comps; i++)
5449 wait_for_completion(&mpi->unref_comp);
5450
5451 spin_lock(&port->mp.mpi_lock);
5452 mpi->unaffiliate = false;
5453 }
5454
5455 port->mp.mpi = NULL;
5456
5457 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5458
5459 spin_unlock(&port->mp.mpi_lock);
5460
5461 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5462
5463 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5464 /* Log an error, still needed to cleanup the pointers and add
5465 * it back to the list.
5466 */
5467 if (err)
5468 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5469 port_num + 1);
5470
5471 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
5472}
5473
5474/* The mlx5_ib_multiport_mutex should be held when calling this function */
5475static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5476 struct mlx5_ib_multiport_info *mpi)
5477{
5478 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5479 int err;
5480
5481 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5482 if (ibdev->port[port_num].mp.mpi) {
2577188e
QH		 5483 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
5484 port_num + 1);
32f69e4b
DJ		 5485 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5486 return false;
5487 }
5488
5489 ibdev->port[port_num].mp.mpi = mpi;
5490 mpi->ibdev = ibdev;
df097a27 5491 mpi->mdev_events.notifier_call = NULL;
32f69e4b
DJ		 5492 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5493
5494 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5495 if (err)
5496 goto unbind;
5497
5498 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5499 if (err)
5500 goto unbind;
5501
5502 err = mlx5_add_netdev_notifier(ibdev, port_num);
5503 if (err) {
5504 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5505 port_num + 1);
5506 goto unbind;
5507 }
5508
df097a27
SM		 5509 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
5510 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
5511
a9e546e7
PP		 5512 err = mlx5_ib_init_cong_debugfs(ibdev, port_num);
5513 if (err)
5514 goto unbind;
5515
32f69e4b
DJ		 5516 return true;
5517
5518unbind:
5519 mlx5_ib_unbind_slave_port(ibdev, mpi);
5520 return false;
5521}
5522
5523static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5524{
5525 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5526 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5527 port_num + 1);
5528 struct mlx5_ib_multiport_info *mpi;
5529 int err;
5530 int i;
5531
5532 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5533 return 0;
5534
5535 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5536 &dev->sys_image_guid);
5537 if (err)
5538 return err;
5539
5540 err = mlx5_nic_vport_enable_roce(dev->mdev);
5541 if (err)
5542 return err;
5543
5544 mutex_lock(&mlx5_ib_multiport_mutex);
5545 for (i = 0; i < dev->num_ports; i++) {
5546 bool bound = false;
5547
5548 /* build a stub multiport info struct for the native port. */
5549 if (i == port_num) {
5550 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5551 if (!mpi) {
5552 mutex_unlock(&mlx5_ib_multiport_mutex);
5553 mlx5_nic_vport_disable_roce(dev->mdev);
5554 return -ENOMEM;
5555 }
5556
5557 mpi->is_master = true;
5558 mpi->mdev = dev->mdev;
5559 mpi->sys_image_guid = dev->sys_image_guid;
5560 dev->port[i].mp.mpi = mpi;
5561 mpi->ibdev = dev;
5562 mpi = NULL;
5563 continue;
5564 }
5565
5566 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5567 list) {
5568 if (dev->sys_image_guid == mpi->sys_image_guid &&
5569 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5570 bound = mlx5_ib_bind_slave_port(dev, mpi);
5571 }
5572
5573 if (bound) {
5574 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
5575 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5576 list_del(&mpi->list);
5577 break;
5578 }
5579 }
5580 if (!bound) {
5581 get_port_caps(dev, i + 1);
5582 mlx5_ib_dbg(dev, "no free port found for port %d\n",
5583 i + 1);
5584 }
5585 }
5586
5587 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
5588 mutex_unlock(&mlx5_ib_multiport_mutex);
5589 return err;
5590}
5591
5592static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
5593{
5594 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5595 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5596 port_num + 1);
5597 int i;
5598
5599 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5600 return;
5601
5602 mutex_lock(&mlx5_ib_multiport_mutex);
5603 for (i = 0; i < dev->num_ports; i++) {
5604 if (dev->port[i].mp.mpi) {
5605 /* Destroy the native port stub */
5606 if (i == port_num) {
5607 kfree(dev->port[i].mp.mpi);
5608 dev->port[i].mp.mpi = NULL;
5609 } else {
5610 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
5611 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
5612 }
5613 }
5614 }
5615
5616 mlx5_ib_dbg(dev, "removing from devlist\n");
5617 list_del(&dev->ib_dev_list);
5618 mutex_unlock(&mlx5_ib_multiport_mutex);
5619
5620 mlx5_nic_vport_disable_roce(dev->mdev);
5621}
5622
9a119cd5
JG		 5623ADD_UVERBS_ATTRIBUTES_SIMPLE(
5624 mlx5_ib_dm,
5625 UVERBS_OBJECT_DM,
5626 UVERBS_METHOD_DM_ALLOC,
5627 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
5628 UVERBS_ATTR_TYPE(u64),
83bb4442 5629 UA_MANDATORY),
9a119cd5
JG		 5630 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
5631 UVERBS_ATTR_TYPE(u16),
83bb4442 5632 UA_MANDATORY));
9a119cd5
JG		 5633
5634ADD_UVERBS_ATTRIBUTES_SIMPLE(
5635 mlx5_ib_flow_action,
5636 UVERBS_OBJECT_FLOW_ACTION,
5637 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
bccd0622
JG		 5638 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
5639 enum mlx5_ib_uapi_flow_action_flags));
c6475a0b 5640
0cbf432d
JG		 5641static const struct uapi_definition mlx5_ib_defs[] = {
5642#if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)
36e235c8 5643 UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
0cbf432d
JG		 5644 UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
5645#endif
8c84660b 5646
0cbf432d
JG		 5647 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION,
5648 &mlx5_ib_flow_action),
5649 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm),
5650 {}
5651};
8c84660b 5652
1a1e03dc
RS		 5653static int mlx5_ib_read_counters(struct ib_counters *counters,
5654 struct ib_counters_read_attr *read_attr,
5655 struct uverbs_attr_bundle *attrs)
5656{
5657 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5658 struct mlx5_read_counters_attr mread_attr = {};
5659 struct mlx5_ib_flow_counters_desc *desc;
5660 int ret, i;
5661
5662 mutex_lock(&mcounters->mcntrs_mutex);
5663 if (mcounters->cntrs_max_index > read_attr->ncounters) {
5664 ret = -EINVAL;
5665 goto err_bound;
5666 }
5667
5668 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
5669 GFP_KERNEL);
5670 if (!mread_attr.out) {
5671 ret = -ENOMEM;
5672 goto err_bound;
5673 }
5674
5675 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
5676 mread_attr.flags = read_attr->flags;
5677 ret = mcounters->read_counters(counters->device, &mread_attr);
5678 if (ret)
5679 goto err_read;
5680
5681 /* do the pass over the counters data array to assign according to the
5682 * descriptions and indexing pairs
5683 */
5684 desc = mcounters->counters_data;
5685 for (i = 0; i < mcounters->ncounters; i++)
5686 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
5687
5688err_read:
5689 kfree(mread_attr.out);
5690err_bound:
5691 mutex_unlock(&mcounters->mcntrs_mutex);
5692 return ret;
5693}
5694
b29e2a13
RS		 5695static int mlx5_ib_destroy_counters(struct ib_counters *counters)
5696{
5697 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5698
3b3233fb
RS		 5699 counters_clear_description(counters);
5700 if (mcounters->hw_cntrs_hndl)
5701 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
5702 mcounters->hw_cntrs_hndl);
5703
b29e2a13
RS		 5704 kfree(mcounters);
5705
5706 return 0;
5707}
5708
5709static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
5710 struct uverbs_attr_bundle *attrs)
5711{
5712 struct mlx5_ib_mcounters *mcounters;
5713
5714 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
5715 if (!mcounters)
5716 return ERR_PTR(-ENOMEM);
5717
3b3233fb
RS		 5718 mutex_init(&mcounters->mcntrs_mutex);
5719
b29e2a13
RS		 5720 return &mcounters->ibcntrs;
5721}
5722
b5ca15ad 5723void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
e126ba97 5724{
32f69e4b 5725 mlx5_ib_cleanup_multiport_master(dev);
13859d5d 5726 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
534fd7aa 5727 srcu_barrier(&dev->mr_srcu);
13859d5d
LR		 5728 cleanup_srcu_struct(&dev->mr_srcu);
5729 drain_workqueue(dev->advise_mr_wq);
5730 destroy_workqueue(dev->advise_mr_wq);
5731 }
16c1975f
MB		 5732 kfree(dev->port);
5733}
5734
b5ca15ad 5735int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5736{
5737 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 5738 int err;
32f69e4b 5739 int i;
e126ba97 5740
508562d6 5741 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
0837e86a
MB		 5742 GFP_KERNEL);
5743 if (!dev->port)
16c1975f 5744 return -ENOMEM;
0837e86a 5745
32f69e4b
DJ		 5746 for (i = 0; i < dev->num_ports; i++) {
5747 spin_lock_init(&dev->port[i].mp.mpi_lock);
5748 rwlock_init(&dev->roce[i].netdev_lock);
5749 }
5750
5751 err = mlx5_ib_init_multiport_master(dev);
e126ba97 5752 if (err)
0837e86a 5753 goto err_free_port;
e126ba97 5754
32f69e4b 5755 if (!mlx5_core_mp_enabled(mdev)) {
32f69e4b
DJ		 5756 for (i = 1; i <= dev->num_ports; i++) {
5757 err = get_port_caps(dev, i);
5758 if (err)
5759 break;
5760 }
5761 } else {
5762 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
5763 }
5764 if (err)
5765 goto err_mp;
5766
1b5daf11
MD		 5767 if (mlx5_use_mad_ifc(dev))
5768 get_ext_port_caps(dev);
e126ba97 5769
e126ba97
EC		 5770 dev->ib_dev.owner = THIS_MODULE;
5771 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 5772 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
508562d6 5773 dev->ib_dev.phys_port_cnt = dev->num_ports;
f2f3df55 5774 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev);
9b0c289e 5775 dev->ib_dev.dev.parent = &mdev->pdev->dev;
e126ba97 5776
3cc297db
MB		 5777 mutex_init(&dev->cap_mask_mutex);
5778 INIT_LIST_HEAD(&dev->qp_list);
5779 spin_lock_init(&dev->reset_flow_resource_lock);
5780
24da0016
AL		 5781 spin_lock_init(&dev->memic.memic_lock);
5782 dev->memic.dev = mdev;
5783
13859d5d
LR		 5784 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
5785 dev->advise_mr_wq =
5786 alloc_ordered_workqueue("mlx5_ib_advise_mr_wq", 0);
5787 if (!dev->advise_mr_wq) {
5788 err = -ENOMEM;
5789 goto err_mp;
5790 }
813e90b1 5791
13859d5d
LR		 5792 err = init_srcu_struct(&dev->mr_srcu);
5793 if (err) {
5794 destroy_workqueue(dev->advise_mr_wq);
5795 goto err_mp;
5796 }
623d1543 5797 }
3cc297db 5798
16c1975f 5799 return 0;
32f69e4b
DJ		 5800err_mp:
5801 mlx5_ib_cleanup_multiport_master(dev);
16c1975f
MB		 5802
5803err_free_port:
5804 kfree(dev->port);
5805
5806 return -ENOMEM;
5807}
5808
9a4ca38d
MB		 5809static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
5810{
5811 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
5812
5813 if (!dev->flow_db)
5814 return -ENOMEM;
5815
5816 mutex_init(&dev->flow_db->lock);
5817
5818 return 0;
5819}
5820
b5ca15ad
MB		 5821int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev)
5822{
5823 struct mlx5_ib_dev *nic_dev;
5824
5825 nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch);
5826
5827 if (!nic_dev)
5828 return -EINVAL;
5829
5830 dev->flow_db = nic_dev->flow_db;
5831
5832 return 0;
5833}
5834
9a4ca38d
MB		 5835static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
5836{
5837 kfree(dev->flow_db);
5838}
5839
96458233
KH		 5840static const struct ib_device_ops mlx5_ib_dev_ops = {
5841 .add_gid = mlx5_ib_add_gid,
5842 .alloc_mr = mlx5_ib_alloc_mr,
5843 .alloc_pd = mlx5_ib_alloc_pd,
5844 .alloc_ucontext = mlx5_ib_alloc_ucontext,
5845 .attach_mcast = mlx5_ib_mcg_attach,
5846 .check_mr_status = mlx5_ib_check_mr_status,
5847 .create_ah = mlx5_ib_create_ah,
5848 .create_counters = mlx5_ib_create_counters,
5849 .create_cq = mlx5_ib_create_cq,
5850 .create_flow = mlx5_ib_create_flow,
5851 .create_qp = mlx5_ib_create_qp,
5852 .create_srq = mlx5_ib_create_srq,
5853 .dealloc_pd = mlx5_ib_dealloc_pd,
5854 .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
5855 .del_gid = mlx5_ib_del_gid,
5856 .dereg_mr = mlx5_ib_dereg_mr,
5857 .destroy_ah = mlx5_ib_destroy_ah,
5858 .destroy_counters = mlx5_ib_destroy_counters,
5859 .destroy_cq = mlx5_ib_destroy_cq,
5860 .destroy_flow = mlx5_ib_destroy_flow,
5861 .destroy_flow_action = mlx5_ib_destroy_flow_action,
5862 .destroy_qp = mlx5_ib_destroy_qp,
5863 .destroy_srq = mlx5_ib_destroy_srq,
5864 .detach_mcast = mlx5_ib_mcg_detach,
5865 .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
5866 .drain_rq = mlx5_ib_drain_rq,
5867 .drain_sq = mlx5_ib_drain_sq,
5868 .get_dev_fw_str = get_dev_fw_str,
5869 .get_dma_mr = mlx5_ib_get_dma_mr,
5870 .get_link_layer = mlx5_ib_port_link_layer,
5871 .map_mr_sg = mlx5_ib_map_mr_sg,
5872 .mmap = mlx5_ib_mmap,
5873 .modify_cq = mlx5_ib_modify_cq,
5874 .modify_device = mlx5_ib_modify_device,
5875 .modify_port = mlx5_ib_modify_port,
5876 .modify_qp = mlx5_ib_modify_qp,
5877 .modify_srq = mlx5_ib_modify_srq,
5878 .poll_cq = mlx5_ib_poll_cq,
5879 .post_recv = mlx5_ib_post_recv,
5880 .post_send = mlx5_ib_post_send,
5881 .post_srq_recv = mlx5_ib_post_srq_recv,
5882 .process_mad = mlx5_ib_process_mad,
5883 .query_ah = mlx5_ib_query_ah,
5884 .query_device = mlx5_ib_query_device,
5885 .query_gid = mlx5_ib_query_gid,
5886 .query_pkey = mlx5_ib_query_pkey,
5887 .query_qp = mlx5_ib_query_qp,
5888 .query_srq = mlx5_ib_query_srq,
5889 .read_counters = mlx5_ib_read_counters,
5890 .reg_user_mr = mlx5_ib_reg_user_mr,
5891 .req_notify_cq = mlx5_ib_arm_cq,
5892 .rereg_user_mr = mlx5_ib_rereg_user_mr,
5893 .resize_cq = mlx5_ib_resize_cq,
5894};
5895
5896static const struct ib_device_ops mlx5_ib_dev_flow_ipsec_ops = {
5897 .create_flow_action_esp = mlx5_ib_create_flow_action_esp,
5898 .modify_flow_action_esp = mlx5_ib_modify_flow_action_esp,
5899};
5900
5901static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
5902 .rdma_netdev_get_params = mlx5_ib_rn_get_params,
5903};
5904
5905static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
5906 .get_vf_config = mlx5_ib_get_vf_config,
5907 .get_vf_stats = mlx5_ib_get_vf_stats,
5908 .set_vf_guid = mlx5_ib_set_vf_guid,
5909 .set_vf_link_state = mlx5_ib_set_vf_link_state,
5910};
5911
5912static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
5913 .alloc_mw = mlx5_ib_alloc_mw,
5914 .dealloc_mw = mlx5_ib_dealloc_mw,
5915};
5916
5917static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
5918 .alloc_xrcd = mlx5_ib_alloc_xrcd,
5919 .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
5920};
5921
5922static const struct ib_device_ops mlx5_ib_dev_dm_ops = {
5923 .alloc_dm = mlx5_ib_alloc_dm,
5924 .dealloc_dm = mlx5_ib_dealloc_dm,
5925 .reg_dm_mr = mlx5_ib_reg_dm_mr,
5926};
5927
b5ca15ad 5928int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5929{
5930 struct mlx5_core_dev *mdev = dev->mdev;
16c1975f
MB		 5931 int err;
5932
e126ba97
EC		 5933 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
5934 dev->ib_dev.uverbs_cmd_mask =
5935 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
5936 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
5937 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
5938 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
5939 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 5940 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
5941 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 5942 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 5943 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 5944 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
5945 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
5946 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
5947 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
5948 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
5949 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
5950 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
5951 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
5952 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
5953 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
5954 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
5955 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
5956 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
5957 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
5958 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
5959 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
5960 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 5961 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 5962 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
5963 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349 5964 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
b0e9df6d 5965 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
96458233
KH		 5966 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ) |
5967 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
5968 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
5969
f6a8a19b
DD		 5970 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
5971 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
96458233
KH		 5972 ib_set_device_ops(&dev->ib_dev,
5973 &mlx5_ib_dev_ipoib_enhanced_ops);
8e959601 5974
96458233
KH		 5975 if (mlx5_core_is_pf(mdev))
5976 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
7c2344c3 5977
6e8484c5
MG		 5978 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
5979
d2370e0a 5980 if (MLX5_CAP_GEN(mdev, imaicl)) {
d2370e0a
MB		 5981 dev->ib_dev.uverbs_cmd_mask |=
5982 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
5983 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
96458233 5984 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
d2370e0a
MB		 5985 }
5986
938fe83c 5987 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 5988 dev->ib_dev.uverbs_cmd_mask |=
5989 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
5990 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
96458233 5991 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
e126ba97
EC		 5992 }
5993
96458233
KH		 5994 if (MLX5_CAP_DEV_MEM(mdev, memic))
5995 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
24da0016 5996
dfb631a1 5997 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
96458233
KH		 5998 MLX5_ACCEL_IPSEC_CAP_DEVICE)
5999 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_flow_ipsec_ops);
0ede73bc 6000 dev->ib_dev.driver_id = RDMA_DRIVER_MLX5;
96458233 6001 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
81e30880 6002
36e235c8
JG		 6003 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
6004 dev->ib_dev.driver_def = mlx5_ib_defs;
81e30880 6005
e126ba97
EC		 6006 err = init_node_data(dev);
6007 if (err)
16c1975f 6008 return err;
e126ba97 6009
c8b89924 6010 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
e7996a9a
JG		 6011 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
6012 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
a560f1d9 6013 mutex_init(&dev->lb.mutex);
c8b89924 6014
16c1975f
MB		 6015 return 0;
6016}
6017
96458233
KH		 6018static const struct ib_device_ops mlx5_ib_dev_port_ops = {
6019 .get_port_immutable = mlx5_port_immutable,
6020 .query_port = mlx5_ib_query_port,
6021};
6022
8e6efa3a
MB		 6023static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
6024{
96458233 6025 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
8e6efa3a
MB		 6026 return 0;
6027}
6028
96458233
KH		 6029static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
6030 .get_port_immutable = mlx5_port_rep_immutable,
6031 .query_port = mlx5_ib_rep_query_port,
6032};
6033
b5ca15ad 6034int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
8e6efa3a 6035{
96458233 6036 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
8e6efa3a
MB		 6037 return 0;
6038}
6039
96458233
KH		 6040static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
6041 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
6042 .create_wq = mlx5_ib_create_wq,
6043 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
6044 .destroy_wq = mlx5_ib_destroy_wq,
6045 .get_netdev = mlx5_ib_get_netdev,
6046 .modify_wq = mlx5_ib_modify_wq,
6047};
6048
e3f1ed1f 6049static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
8e6efa3a 6050{
e3f1ed1f 6051 u8 port_num;
8e6efa3a
MB		 6052 int i;
6053
6054 for (i = 0; i < dev->num_ports; i++) {
6055 dev->roce[i].dev = dev;
6056 dev->roce[i].native_port_num = i + 1;
6057 dev->roce[i].last_port_state = IB_PORT_DOWN;
6058 }
6059
8e6efa3a
MB		 6060 dev->ib_dev.uverbs_ex_cmd_mask |=
6061 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
6062 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
6063 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
6064 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
6065 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
96458233 6066 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
8e6efa3a 6067
e3f1ed1f
LR		 6068 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6069
8e6efa3a
MB		 6070 return mlx5_add_netdev_notifier(dev, port_num);
6071}
6072
6073static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
6074{
6075 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6076
6077 mlx5_remove_netdev_notifier(dev, port_num);
6078}
6079
6080int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
6081{
6082 struct mlx5_core_dev *mdev = dev->mdev;
6083 enum rdma_link_layer ll;
6084 int port_type_cap;
6085 int err = 0;
8e6efa3a 6086
8e6efa3a
MB		 6087 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6088 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6089
6090 if (ll == IB_LINK_LAYER_ETHERNET)
e3f1ed1f 6091 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 6092
6093 return err;
6094}
6095
6096void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
6097{
6098 mlx5_ib_stage_common_roce_cleanup(dev);
6099}
6100
16c1975f
MB		 6101static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
6102{
6103 struct mlx5_core_dev *mdev = dev->mdev;
6104 enum rdma_link_layer ll;
6105 int port_type_cap;
6106 int err;
6107
6108 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6109 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6110
fc24fc5e 6111 if (ll == IB_LINK_LAYER_ETHERNET) {
e3f1ed1f 6112 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 6113 if (err)
6114 return err;
7fd8aefb 6115
e3f1ed1f 6116 err = mlx5_enable_eth(dev);
fc24fc5e 6117 if (err)
8e6efa3a 6118 goto cleanup;
fc24fc5e
AS		 6119 }
6120
16c1975f 6121 return 0;
8e6efa3a
MB		 6122cleanup:
6123 mlx5_ib_stage_common_roce_cleanup(dev);
6124
6125 return err;
16c1975f 6126}
e126ba97 6127
16c1975f
MB		 6128static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
6129{
6130 struct mlx5_core_dev *mdev = dev->mdev;
6131 enum rdma_link_layer ll;
6132 int port_type_cap;
e126ba97 6133
16c1975f
MB		 6134 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6135 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6136
6137 if (ll == IB_LINK_LAYER_ETHERNET) {
6138 mlx5_disable_eth(dev);
8e6efa3a 6139 mlx5_ib_stage_common_roce_cleanup(dev);
45bded2c 6140 }
16c1975f 6141}
6aec21f6 6142
b5ca15ad 6143int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6144{
6145 return create_dev_resources(&dev->devr);
6146}
6147
b5ca15ad 6148void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6149{
6150 destroy_dev_resources(&dev->devr);
6151}
6152
6153static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
6154{
07321b3c
MB		 6155 mlx5_ib_internal_fill_odp_caps(dev);
6156
16c1975f
MB		 6157 return mlx5_ib_odp_init_one(dev);
6158}
4a2da0b8 6159
d5d284b8
SM		 6160void mlx5_ib_stage_odp_cleanup(struct mlx5_ib_dev *dev)
6161{
6162 mlx5_ib_odp_cleanup_one(dev);
6163}
6164
96458233
KH		 6165static const struct ib_device_ops mlx5_ib_dev_hw_stats_ops = {
6166 .alloc_hw_stats = mlx5_ib_alloc_hw_stats,
6167 .get_hw_stats = mlx5_ib_get_hw_stats,
6168};
6169
b5ca15ad 6170int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
16c1975f 6171{
5e1e7612 6172 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
96458233 6173 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_hw_stats_ops);
5e1e7612
MB		 6174
6175 return mlx5_ib_alloc_counters(dev);
6176 }
16c1975f
MB		 6177
6178 return 0;
6179}
6180
b5ca15ad 6181void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6182{
6183 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
6184 mlx5_ib_dealloc_counters(dev);
6185}
6186
6187static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
6188{
a9e546e7
PP		 6189 return mlx5_ib_init_cong_debugfs(dev,
6190 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 6191}
6192
6193static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
6194{
a9e546e7
PP		 6195 mlx5_ib_cleanup_cong_debugfs(dev,
6196 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 6197}
6198
6199static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
6200{
5fe9dec0 6201 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
444261ca 6202 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
16c1975f
MB		 6203}
6204
6205static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
6206{
6207 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
6208}
6209
b5ca15ad 6210int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6211{
6212 int err;
5fe9dec0
EC		 6213
6214 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
6215 if (err)
16c1975f 6216 return err;
5fe9dec0
EC		 6217
6218 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
6219 if (err)
16c1975f 6220 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5fe9dec0 6221
16c1975f
MB		 6222 return err;
6223}
0837e86a 6224
b5ca15ad 6225void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6226{
6227 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6228 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
6229}
e126ba97 6230
b5ca15ad 6231int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
16c1975f 6232{
e349f858
JG		 6233 const char *name;
6234
508a523f 6235 rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group);
7c34ec19 6236 if (!mlx5_lag_is_roce(dev->mdev))
e349f858
JG		 6237 name = "mlx5_%d";
6238 else
6239 name = "mlx5_bond_%d";
ea4baf7f 6240 return ib_register_device(&dev->ib_dev, name);
16c1975f
MB		 6241}
6242
03fe2deb 6243void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
16c1975f 6244{
42cea83f 6245 destroy_umrc_res(dev);
16c1975f
MB		 6246}
6247
03fe2deb 6248void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
16c1975f 6249{
42cea83f 6250 ib_unregister_device(&dev->ib_dev);
16c1975f
MB		 6251}
6252
03fe2deb 6253int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
16c1975f 6254{
42cea83f 6255 return create_umr_res(dev);
16c1975f
MB		 6256}
6257
6258static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
6259{
03404e8a
MG		 6260 init_delay_drop(dev);
6261
16c1975f
MB		 6262 return 0;
6263}
6264
6265static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
6266{
6267 cancel_delay_drop(dev);
6268}
6269
df097a27
SM		 6270static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
6271{
6272 dev->mdev_events.notifier_call = mlx5_ib_event;
6273 mlx5_notifier_register(dev->mdev, &dev->mdev_events);
6274 return 0;
6275}
6276
6277static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
6278{
6279 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
6280}
6281
81773ce5
LR		 6282static int mlx5_ib_stage_devx_init(struct mlx5_ib_dev *dev)
6283{
6284 int uid;
6285
fb98153b 6286 uid = mlx5_ib_devx_create(dev, false);
81773ce5
LR		 6287 if (uid > 0)
6288 dev->devx_whitelist_uid = uid;
6289
6290 return 0;
6291}
6292static void mlx5_ib_stage_devx_cleanup(struct mlx5_ib_dev *dev)
6293{
6294 if (dev->devx_whitelist_uid)
6295 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid);
6296}
6297
b5ca15ad
MB		 6298void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
6299 const struct mlx5_ib_profile *profile,
6300 int stage)
16c1975f
MB		 6301{
6302 /* Number of stages to cleanup */
6303 while (stage) {
6304 stage--;
6305 if (profile->stage[stage].cleanup)
6306 profile->stage[stage].cleanup(dev);
6307 }
16c1975f 6308}
e126ba97 6309
b5ca15ad
MB		 6310void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
6311 const struct mlx5_ib_profile *profile)
16c1975f 6312{
16c1975f
MB		 6313 int err;
6314 int i;
5fe9dec0 6315
16c1975f
MB		 6316 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
6317 if (profile->stage[i].init) {
6318 err = profile->stage[i].init(dev);
6319 if (err)
6320 goto err_out;
6321 }
6322 }
0837e86a 6323
16c1975f
MB		 6324 dev->profile = profile;
6325 dev->ib_active = true;
6aec21f6 6326
16c1975f 6327 return dev;
e126ba97 6328
16c1975f
MB		 6329err_out:
6330 __mlx5_ib_remove(dev, profile, i);
fc24fc5e 6331
16c1975f
MB		 6332 return NULL;
6333}
0837e86a 6334
16c1975f
MB		 6335static const struct mlx5_ib_profile pf_profile = {
6336 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6337 mlx5_ib_stage_init_init,
6338 mlx5_ib_stage_init_cleanup),
9a4ca38d
MB		 6339 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6340 mlx5_ib_stage_flow_db_init,
6341 mlx5_ib_stage_flow_db_cleanup),
16c1975f
MB		 6342 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6343 mlx5_ib_stage_caps_init,
6344 NULL),
8e6efa3a
MB		 6345 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6346 mlx5_ib_stage_non_default_cb,
6347 NULL),
16c1975f
MB		 6348 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6349 mlx5_ib_stage_roce_init,
6350 mlx5_ib_stage_roce_cleanup),
f3da6577
LR		 6351 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6352 mlx5_init_srq_table,
6353 mlx5_cleanup_srq_table),
16c1975f
MB		 6354 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6355 mlx5_ib_stage_dev_res_init,
6356 mlx5_ib_stage_dev_res_cleanup),
df097a27
SM		 6357 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6358 mlx5_ib_stage_dev_notifier_init,
6359 mlx5_ib_stage_dev_notifier_cleanup),
16c1975f
MB		 6360 STAGE_CREATE(MLX5_IB_STAGE_ODP,
6361 mlx5_ib_stage_odp_init,
d5d284b8 6362 mlx5_ib_stage_odp_cleanup),
16c1975f
MB		 6363 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6364 mlx5_ib_stage_counters_init,
6365 mlx5_ib_stage_counters_cleanup),
6366 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
6367 mlx5_ib_stage_cong_debugfs_init,
6368 mlx5_ib_stage_cong_debugfs_cleanup),
6369 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6370 mlx5_ib_stage_uar_init,
6371 mlx5_ib_stage_uar_cleanup),
6372 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6373 mlx5_ib_stage_bfrag_init,
6374 mlx5_ib_stage_bfrag_cleanup),
42cea83f
MB		 6375 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6376 NULL,
6377 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
81773ce5
LR		 6378 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
6379 mlx5_ib_stage_devx_init,
6380 mlx5_ib_stage_devx_cleanup),
16c1975f
MB		 6381 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6382 mlx5_ib_stage_ib_reg_init,
6383 mlx5_ib_stage_ib_reg_cleanup),
42cea83f
MB		 6384 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6385 mlx5_ib_stage_post_ib_reg_umr_init,
6386 NULL),
16c1975f
MB		 6387 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
6388 mlx5_ib_stage_delay_drop_init,
6389 mlx5_ib_stage_delay_drop_cleanup),
16c1975f 6390};
e126ba97 6391
b5ca15ad
MB		 6392static const struct mlx5_ib_profile nic_rep_profile = {
6393 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6394 mlx5_ib_stage_init_init,
6395 mlx5_ib_stage_init_cleanup),
6396 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6397 mlx5_ib_stage_flow_db_init,
6398 mlx5_ib_stage_flow_db_cleanup),
6399 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6400 mlx5_ib_stage_caps_init,
6401 NULL),
6402 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6403 mlx5_ib_stage_rep_non_default_cb,
6404 NULL),
6405 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6406 mlx5_ib_stage_rep_roce_init,
6407 mlx5_ib_stage_rep_roce_cleanup),
f3da6577
LR		 6408 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6409 mlx5_init_srq_table,
6410 mlx5_cleanup_srq_table),
b5ca15ad
MB		 6411 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6412 mlx5_ib_stage_dev_res_init,
6413 mlx5_ib_stage_dev_res_cleanup),
df097a27
SM		 6414 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6415 mlx5_ib_stage_dev_notifier_init,
6416 mlx5_ib_stage_dev_notifier_cleanup),
b5ca15ad
MB		 6417 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6418 mlx5_ib_stage_counters_init,
6419 mlx5_ib_stage_counters_cleanup),
6420 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6421 mlx5_ib_stage_uar_init,
6422 mlx5_ib_stage_uar_cleanup),
6423 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6424 mlx5_ib_stage_bfrag_init,
6425 mlx5_ib_stage_bfrag_cleanup),
03fe2deb
DM		 6426 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6427 NULL,
6428 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
b5ca15ad
MB		 6429 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6430 mlx5_ib_stage_ib_reg_init,
6431 mlx5_ib_stage_ib_reg_cleanup),
03fe2deb
DM		 6432 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6433 mlx5_ib_stage_post_ib_reg_umr_init,
6434 NULL),
b5ca15ad
MB		 6435};
6436
e3f1ed1f 6437static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
32f69e4b
DJ		 6438{
6439 struct mlx5_ib_multiport_info *mpi;
6440 struct mlx5_ib_dev *dev;
6441 bool bound = false;
6442 int err;
6443
6444 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6445 if (!mpi)
6446 return NULL;
6447
6448 mpi->mdev = mdev;
6449
6450 err = mlx5_query_nic_vport_system_image_guid(mdev,
6451 &mpi->sys_image_guid);
6452 if (err) {
6453 kfree(mpi);
6454 return NULL;
6455 }
6456
6457 mutex_lock(&mlx5_ib_multiport_mutex);
6458 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
6459 if (dev->sys_image_guid == mpi->sys_image_guid)
6460 bound = mlx5_ib_bind_slave_port(dev, mpi);
6461
6462 if (bound) {
6463 rdma_roce_rescan_device(&dev->ib_dev);
6464 break;
6465 }
6466 }
6467
6468 if (!bound) {
6469 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
6470 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
32f69e4b
DJ		 6471 }
6472 mutex_unlock(&mlx5_ib_multiport_mutex);
6473
6474 return mpi;
6475}
6476
16c1975f
MB		 6477static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
6478{
32f69e4b 6479 enum rdma_link_layer ll;
b5ca15ad 6480 struct mlx5_ib_dev *dev;
32f69e4b
DJ		 6481 int port_type_cap;
6482
b5ca15ad
MB		 6483 printk_once(KERN_INFO "%s", mlx5_version);
6484
32f69e4b
DJ		 6485 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6486 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6487
e3f1ed1f
LR		 6488 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
6489 return mlx5_ib_add_slave_port(mdev);
32f69e4b 6490
b5ca15ad
MB		 6491 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
6492 if (!dev)
6493 return NULL;
6494
6495 dev->mdev = mdev;
6496 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
6497 MLX5_CAP_GEN(mdev, num_vhca_ports));
6498
aff2252a 6499 if (MLX5_ESWITCH_MANAGER(mdev) &&
b5ca15ad
MB		 6500 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
6501 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0);
06cc74af
MB		 6502 dev->profile = &nic_rep_profile;
6503 mlx5_ib_register_vport_reps(dev);
6504 return dev;
b5ca15ad
MB		 6505 }
6506
6507 return __mlx5_ib_add(dev, &pf_profile);
e126ba97
EC		 6508}
6509
9603b61d 6510static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 6511{
32f69e4b
DJ		 6512 struct mlx5_ib_multiport_info *mpi;
6513 struct mlx5_ib_dev *dev;
6514
6515 if (mlx5_core_is_mp_slave(mdev)) {
6516 mpi = context;
6517 mutex_lock(&mlx5_ib_multiport_mutex);
6518 if (mpi->ibdev)
6519 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
6520 list_del(&mpi->list);
6521 mutex_unlock(&mlx5_ib_multiport_mutex);
6522 return;
6523 }
6aec21f6 6524
32f69e4b 6525 dev = context;
06cc74af
MB		 6526 if (dev->profile == &nic_rep_profile)
6527 mlx5_ib_unregister_vport_reps(dev);
6528 else
6529 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
6530
6531 ib_dealloc_device((struct ib_device *)dev);
e126ba97
EC		 6532}
6533
9603b61d
JM		 6534static struct mlx5_interface mlx5_ib_interface = {
6535 .add = mlx5_ib_add,
6536 .remove = mlx5_ib_remove,
64613d94 6537 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 6538};
6539
c44ef998
IL		 6540unsigned long mlx5_ib_get_xlt_emergency_page(void)
6541{
6542 mutex_lock(&xlt_emergency_page_mutex);
6543 return xlt_emergency_page;
6544}
6545
6546void mlx5_ib_put_xlt_emergency_page(void)
6547{
6548 mutex_unlock(&xlt_emergency_page_mutex);
6549}
6550
e126ba97
EC		 6551static int __init mlx5_ib_init(void)
6552{
6aec21f6
HE		 6553 int err;
6554
c44ef998
IL		 6555 xlt_emergency_page = __get_free_page(GFP_KERNEL);
6556 if (!xlt_emergency_page)
6557 return -ENOMEM;
6558
6559 mutex_init(&xlt_emergency_page_mutex);
6560
d69a24e0 6561 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
c44ef998
IL		 6562 if (!mlx5_ib_event_wq) {
6563 free_page(xlt_emergency_page);
d69a24e0 6564 return -ENOMEM;
c44ef998 6565 }
d69a24e0 6566
81713d37 6567 mlx5_ib_odp_init();
9603b61d 6568
6aec21f6 6569 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 6570
6aec21f6 6571 return err;
e126ba97
EC		 6572}
6573
6574static void __exit mlx5_ib_cleanup(void)
6575{
9603b61d 6576 mlx5_unregister_interface(&mlx5_ib_interface);
d69a24e0 6577 destroy_workqueue(mlx5_ib_event_wq);
c44ef998
IL		 6578 mutex_destroy(&xlt_emergency_page_mutex);
6579 free_page(xlt_emergency_page);
e126ba97
EC		 6580}
6581
6582module_init(mlx5_ib_init);
6583module_exit(mlx5_ib_cleanup);
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