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IB/mlx5: Report inner RSS capability
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
37aa5c36
GL		 41#if defined(CONFIG_X86)
42#include <asm/pat.h>
43#endif
e126ba97 44#include <linux/sched.h>
6e84f315 45#include <linux/sched/mm.h>
0881e7bd 46#include <linux/sched/task.h>
7c2344c3 47#include <linux/delay.h>
e126ba97 48#include <rdma/ib_user_verbs.h>
3f89a643 49#include <rdma/ib_addr.h>
2811ba51 50#include <rdma/ib_cache.h>
ada68c31 51#include <linux/mlx5/port.h>
1b5daf11 52#include <linux/mlx5/vport.h>
72c7fe90 53#include <linux/mlx5/fs.h>
7c2344c3 54#include <linux/list.h>
e126ba97
EC		 55#include <rdma/ib_smi.h>
56#include <rdma/ib_umem.h>
038d2ef8
MG		 57#include <linux/in.h>
58#include <linux/etherdevice.h>
e126ba97 59#include "mlx5_ib.h"
e1f24a79 60#include "cmd.h"
e126ba97
EC		 61
62#define DRIVER_NAME "mlx5_ib"
b359911d 63#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 64
65MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
66MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
67MODULE_LICENSE("Dual BSD/GPL");
e126ba97 68
e126ba97
EC		 69static char mlx5_version[] =
70 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 71 DRIVER_VERSION "\n";
e126ba97 72
da7525d2
EBE		 73enum {
74 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
75};
76
1b5daf11 77static enum rdma_link_layer
ebd61f68 78mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 79{
ebd61f68 80 switch (port_type_cap) {
1b5daf11
MD		 81 case MLX5_CAP_PORT_TYPE_IB:
82 return IB_LINK_LAYER_INFINIBAND;
83 case MLX5_CAP_PORT_TYPE_ETH:
84 return IB_LINK_LAYER_ETHERNET;
85 default:
86 return IB_LINK_LAYER_UNSPECIFIED;
87 }
88}
89
ebd61f68
AS		 90static enum rdma_link_layer
91mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
92{
93 struct mlx5_ib_dev *dev = to_mdev(device);
94 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
95
96 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
97}
98
fd65f1b8
MS		 99static int get_port_state(struct ib_device *ibdev,
100 u8 port_num,
101 enum ib_port_state *state)
102{
103 struct ib_port_attr attr;
104 int ret;
105
106 memset(&attr, 0, sizeof(attr));
107 ret = mlx5_ib_query_port(ibdev, port_num, &attr);
108 if (!ret)
109 *state = attr.state;
110 return ret;
111}
112
fc24fc5e
AS		 113static int mlx5_netdev_event(struct notifier_block *this,
114 unsigned long event, void *ptr)
115{
116 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
117 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
118 roce.nb);
119
5ec8c83e
AH		 120 switch (event) {
121 case NETDEV_REGISTER:
122 case NETDEV_UNREGISTER:
123 write_lock(&ibdev->roce.netdev_lock);
124 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
125 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
126 NULL : ndev;
127 write_unlock(&ibdev->roce.netdev_lock);
128 break;
fc24fc5e 129
fd65f1b8 130 case NETDEV_CHANGE:
5ec8c83e 131 case NETDEV_UP:
88621dfe
AH		 132 case NETDEV_DOWN: {
133 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
134 struct net_device *upper = NULL;
135
136 if (lag_ndev) {
137 upper = netdev_master_upper_dev_get(lag_ndev);
138 dev_put(lag_ndev);
139 }
140
141 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
142 && ibdev->ib_active) {
626bc02d 143 struct ib_event ibev = { };
fd65f1b8 144 enum ib_port_state port_state;
5ec8c83e 145
fd65f1b8
MS		 146 if (get_port_state(&ibdev->ib_dev, 1, &port_state))
147 return NOTIFY_DONE;
148
149 if (ibdev->roce.last_port_state == port_state)
150 return NOTIFY_DONE;
151
152 ibdev->roce.last_port_state = port_state;
5ec8c83e 153 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 154 if (port_state == IB_PORT_DOWN)
155 ibev.event = IB_EVENT_PORT_ERR;
156 else if (port_state == IB_PORT_ACTIVE)
157 ibev.event = IB_EVENT_PORT_ACTIVE;
158 else
159 return NOTIFY_DONE;
160
5ec8c83e
AH		 161 ibev.element.port_num = 1;
162 ib_dispatch_event(&ibev);
163 }
164 break;
88621dfe 165 }
fc24fc5e 166
5ec8c83e
AH		 167 default:
168 break;
169 }
fc24fc5e
AS		 170
171 return NOTIFY_DONE;
172}
173
174static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
175 u8 port_num)
176{
177 struct mlx5_ib_dev *ibdev = to_mdev(device);
178 struct net_device *ndev;
179
88621dfe
AH		 180 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
181 if (ndev)
182 return ndev;
183
fc24fc5e
AS		 184 /* Ensure ndev does not disappear before we invoke dev_hold()
185 */
186 read_lock(&ibdev->roce.netdev_lock);
187 ndev = ibdev->roce.netdev;
188 if (ndev)
189 dev_hold(ndev);
190 read_unlock(&ibdev->roce.netdev_lock);
191
192 return ndev;
193}
194
f1b65df5
NO		 195static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
196 u8 *active_width)
197{
198 switch (eth_proto_oper) {
199 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
200 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
201 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
202 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
203 *active_width = IB_WIDTH_1X;
204 *active_speed = IB_SPEED_SDR;
205 break;
206 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
207 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
208 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
209 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
210 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
211 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
212 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
213 *active_width = IB_WIDTH_1X;
214 *active_speed = IB_SPEED_QDR;
215 break;
216 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
217 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
218 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
219 *active_width = IB_WIDTH_1X;
220 *active_speed = IB_SPEED_EDR;
221 break;
222 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
223 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
224 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
225 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
226 *active_width = IB_WIDTH_4X;
227 *active_speed = IB_SPEED_QDR;
228 break;
229 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
230 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
231 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
232 *active_width = IB_WIDTH_1X;
233 *active_speed = IB_SPEED_HDR;
234 break;
235 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
236 *active_width = IB_WIDTH_4X;
237 *active_speed = IB_SPEED_FDR;
238 break;
239 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
240 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
241 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
242 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
243 *active_width = IB_WIDTH_4X;
244 *active_speed = IB_SPEED_EDR;
245 break;
246 default:
247 return -EINVAL;
248 }
249
250 return 0;
251}
252
095b0927
IT		 253static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
254 struct ib_port_attr *props)
3f89a643
AS		 255{
256 struct mlx5_ib_dev *dev = to_mdev(device);
f1b65df5 257 struct mlx5_core_dev *mdev = dev->mdev;
88621dfe 258 struct net_device *ndev, *upper;
3f89a643 259 enum ib_mtu ndev_ib_mtu;
c876a1b7 260 u16 qkey_viol_cntr;
f1b65df5 261 u32 eth_prot_oper;
095b0927 262 int err;
3f89a643 263
f1b65df5
NO		 264 /* Possible bad flows are checked before filling out props so in case
265 * of an error it will still be zeroed out.
50f22fd8 266 */
095b0927
IT		 267 err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper, port_num);
268 if (err)
269 return err;
f1b65df5
NO		 270
271 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
272 &props->active_width);
3f89a643
AS		 273
274 props->port_cap_flags |= IB_PORT_CM_SUP;
275 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
276
277 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
278 roce_address_table_size);
279 props->max_mtu = IB_MTU_4096;
280 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
281 props->pkey_tbl_len = 1;
282 props->state = IB_PORT_DOWN;
283 props->phys_state = 3;
284
c876a1b7
LR		 285 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
286 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643
AS		 287
288 ndev = mlx5_ib_get_netdev(device, port_num);
289 if (!ndev)
095b0927 290 return 0;
3f89a643 291
88621dfe
AH		 292 if (mlx5_lag_is_active(dev->mdev)) {
293 rcu_read_lock();
294 upper = netdev_master_upper_dev_get_rcu(ndev);
295 if (upper) {
296 dev_put(ndev);
297 ndev = upper;
298 dev_hold(ndev);
299 }
300 rcu_read_unlock();
301 }
302
3f89a643
AS		 303 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
304 props->state = IB_PORT_ACTIVE;
305 props->phys_state = 5;
306 }
307
308 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
309
310 dev_put(ndev);
311
312 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
095b0927 313 return 0;
3f89a643
AS		 314}
315
095b0927
IT		 316static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
317 unsigned int index, const union ib_gid *gid,
318 const struct ib_gid_attr *attr)
3cca2606 319{
095b0927
IT		 320 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
321 u8 roce_version = 0;
322 u8 roce_l3_type = 0;
323 bool vlan = false;
324 u8 mac[ETH_ALEN];
325 u16 vlan_id = 0;
326
327 if (gid) {
328 gid_type = attr->gid_type;
329 ether_addr_copy(mac, attr->ndev->dev_addr);
330
331 if (is_vlan_dev(attr->ndev)) {
332 vlan = true;
333 vlan_id = vlan_dev_vlan_id(attr->ndev);
334 }
3cca2606
AS		 335 }
336
095b0927 337 switch (gid_type) {
3cca2606 338 case IB_GID_TYPE_IB:
095b0927 339 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 340 break;
341 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 342 roce_version = MLX5_ROCE_VERSION_2;
343 if (ipv6_addr_v4mapped((void *)gid))
344 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
345 else
346 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 347 break;
348
349 default:
095b0927 350 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 351 }
352
095b0927
IT		 353 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
354 roce_l3_type, gid->raw, mac, vlan,
355 vlan_id);
3cca2606
AS		 356}
357
358static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
359 unsigned int index, const union ib_gid *gid,
360 const struct ib_gid_attr *attr,
361 __always_unused void **context)
362{
095b0927 363 return set_roce_addr(to_mdev(device), port_num, index, gid, attr);
3cca2606
AS		 364}
365
366static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
367 unsigned int index, __always_unused void **context)
368{
095b0927 369 return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL);
3cca2606
AS		 370}
371
2811ba51
AS		 372__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
373 int index)
374{
375 struct ib_gid_attr attr;
376 union ib_gid gid;
377
378 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
379 return 0;
380
381 if (!attr.ndev)
382 return 0;
383
384 dev_put(attr.ndev);
385
386 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
387 return 0;
388
389 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
390}
391
ed88451e
MD		 392int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
393 int index, enum ib_gid_type *gid_type)
394{
395 struct ib_gid_attr attr;
396 union ib_gid gid;
397 int ret;
398
399 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
400 if (ret)
401 return ret;
402
403 if (!attr.ndev)
404 return -ENODEV;
405
406 dev_put(attr.ndev);
407
408 *gid_type = attr.gid_type;
409
410 return 0;
411}
412
1b5daf11
MD		 413static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
414{
7fae6655
NO		 415 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
416 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
417 return 0;
1b5daf11
MD		 418}
419
420enum {
421 MLX5_VPORT_ACCESS_METHOD_MAD,
422 MLX5_VPORT_ACCESS_METHOD_HCA,
423 MLX5_VPORT_ACCESS_METHOD_NIC,
424};
425
426static int mlx5_get_vport_access_method(struct ib_device *ibdev)
427{
428 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
429 return MLX5_VPORT_ACCESS_METHOD_MAD;
430
ebd61f68 431 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 432 IB_LINK_LAYER_ETHERNET)
433 return MLX5_VPORT_ACCESS_METHOD_NIC;
434
435 return MLX5_VPORT_ACCESS_METHOD_HCA;
436}
437
da7525d2
EBE		 438static void get_atomic_caps(struct mlx5_ib_dev *dev,
439 struct ib_device_attr *props)
440{
441 u8 tmp;
442 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
443 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
444 u8 atomic_req_8B_endianness_mode =
bd10838a 445 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 446
447 /* Check if HW supports 8 bytes standard atomic operations and capable
448 * of host endianness respond
449 */
450 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
451 if (((atomic_operations & tmp) == tmp) &&
452 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
453 (atomic_req_8B_endianness_mode)) {
454 props->atomic_cap = IB_ATOMIC_HCA;
455 } else {
456 props->atomic_cap = IB_ATOMIC_NONE;
457 }
458}
459
1b5daf11
MD		 460static int mlx5_query_system_image_guid(struct ib_device *ibdev,
461 __be64 *sys_image_guid)
462{
463 struct mlx5_ib_dev *dev = to_mdev(ibdev);
464 struct mlx5_core_dev *mdev = dev->mdev;
465 u64 tmp;
466 int err;
467
468 switch (mlx5_get_vport_access_method(ibdev)) {
469 case MLX5_VPORT_ACCESS_METHOD_MAD:
470 return mlx5_query_mad_ifc_system_image_guid(ibdev,
471 sys_image_guid);
472
473 case MLX5_VPORT_ACCESS_METHOD_HCA:
474 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 475 break;
476
477 case MLX5_VPORT_ACCESS_METHOD_NIC:
478 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
479 break;
1b5daf11
MD		 480
481 default:
482 return -EINVAL;
483 }
3f89a643
AS		 484
485 if (!err)
486 *sys_image_guid = cpu_to_be64(tmp);
487
488 return err;
489
1b5daf11
MD		 490}
491
492static int mlx5_query_max_pkeys(struct ib_device *ibdev,
493 u16 *max_pkeys)
494{
495 struct mlx5_ib_dev *dev = to_mdev(ibdev);
496 struct mlx5_core_dev *mdev = dev->mdev;
497
498 switch (mlx5_get_vport_access_method(ibdev)) {
499 case MLX5_VPORT_ACCESS_METHOD_MAD:
500 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
501
502 case MLX5_VPORT_ACCESS_METHOD_HCA:
503 case MLX5_VPORT_ACCESS_METHOD_NIC:
504 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
505 pkey_table_size));
506 return 0;
507
508 default:
509 return -EINVAL;
510 }
511}
512
513static int mlx5_query_vendor_id(struct ib_device *ibdev,
514 u32 *vendor_id)
515{
516 struct mlx5_ib_dev *dev = to_mdev(ibdev);
517
518 switch (mlx5_get_vport_access_method(ibdev)) {
519 case MLX5_VPORT_ACCESS_METHOD_MAD:
520 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
521
522 case MLX5_VPORT_ACCESS_METHOD_HCA:
523 case MLX5_VPORT_ACCESS_METHOD_NIC:
524 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
525
526 default:
527 return -EINVAL;
528 }
529}
530
531static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
532 __be64 *node_guid)
533{
534 u64 tmp;
535 int err;
536
537 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
538 case MLX5_VPORT_ACCESS_METHOD_MAD:
539 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
540
541 case MLX5_VPORT_ACCESS_METHOD_HCA:
542 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 543 break;
544
545 case MLX5_VPORT_ACCESS_METHOD_NIC:
546 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
547 break;
1b5daf11
MD		 548
549 default:
550 return -EINVAL;
551 }
3f89a643
AS		 552
553 if (!err)
554 *node_guid = cpu_to_be64(tmp);
555
556 return err;
1b5daf11
MD		 557}
558
559struct mlx5_reg_node_desc {
bd99fdea 560 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 561};
562
563static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
564{
565 struct mlx5_reg_node_desc in;
566
567 if (mlx5_use_mad_ifc(dev))
568 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
569
570 memset(&in, 0, sizeof(in));
571
572 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
573 sizeof(struct mlx5_reg_node_desc),
574 MLX5_REG_NODE_DESC, 0, 0);
575}
576
e126ba97 577static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 578 struct ib_device_attr *props,
579 struct ib_udata *uhw)
e126ba97
EC		 580{
581 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 582 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 583 int err = -ENOMEM;
288c01b7 584 int max_sq_desc;
e126ba97
EC		 585 int max_rq_sg;
586 int max_sq_sg;
e0238a6a 587 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
402ca536
BW		 588 struct mlx5_ib_query_device_resp resp = {};
589 size_t resp_len;
590 u64 max_tso;
e126ba97 591
402ca536
BW		 592 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
593 if (uhw->outlen && uhw->outlen < resp_len)
594 return -EINVAL;
595 else
596 resp.response_length = resp_len;
597
598 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 599 return -EINVAL;
600
1b5daf11
MD		 601 memset(props, 0, sizeof(*props));
602 err = mlx5_query_system_image_guid(ibdev,
603 &props->sys_image_guid);
604 if (err)
605 return err;
e126ba97 606
1b5daf11 607 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 608 if (err)
1b5daf11 609 return err;
e126ba97 610
1b5daf11
MD		 611 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
612 if (err)
613 return err;
e126ba97 614
9603b61d
JM		 615 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
616 (fw_rev_min(dev->mdev) << 16) |
617 fw_rev_sub(dev->mdev);
e126ba97
EC		 618 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
619 IB_DEVICE_PORT_ACTIVE_EVENT |
620 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 621 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 622
623 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 624 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 625 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 626 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 627 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 628 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 629 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 630 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 631 if (MLX5_CAP_GEN(mdev, imaicl)) {
632 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
633 IB_DEVICE_MEM_WINDOW_TYPE_2B;
634 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 635 /* We support 'Gappy' memory registration too */
636 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 637 }
e126ba97 638 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 639 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 640 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
641 /* At this stage no support for signature handover */
642 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
643 IB_PROT_T10DIF_TYPE_2 |
644 IB_PROT_T10DIF_TYPE_3;
645 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
646 IB_GUARD_T10DIF_CSUM;
647 }
938fe83c 648 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 649 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 650
402ca536 651 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
e8161334
NO		 652 if (MLX5_CAP_ETH(mdev, csum_cap)) {
653 /* Legacy bit to support old userspace libraries */
88115fe7 654 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 655 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
656 }
657
658 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
659 props->raw_packet_caps |=
660 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 661
402ca536
BW		 662 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
663 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
664 if (max_tso) {
665 resp.tso_caps.max_tso = 1 << max_tso;
666 resp.tso_caps.supported_qpts |=
667 1 << IB_QPT_RAW_PACKET;
668 resp.response_length += sizeof(resp.tso_caps);
669 }
670 }
31f69a82
YH		 671
672 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
673 resp.rss_caps.rx_hash_function =
674 MLX5_RX_HASH_FUNC_TOEPLITZ;
675 resp.rss_caps.rx_hash_fields_mask =
676 MLX5_RX_HASH_SRC_IPV4 |
677 MLX5_RX_HASH_DST_IPV4 |
678 MLX5_RX_HASH_SRC_IPV6 |
679 MLX5_RX_HASH_DST_IPV6 |
680 MLX5_RX_HASH_SRC_PORT_TCP |
681 MLX5_RX_HASH_DST_PORT_TCP |
682 MLX5_RX_HASH_SRC_PORT_UDP |
4e2b53a5
MG		 683 MLX5_RX_HASH_DST_PORT_UDP |
684 MLX5_RX_HASH_INNER;
31f69a82
YH		 685 resp.response_length += sizeof(resp.rss_caps);
686 }
687 } else {
688 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
689 resp.response_length += sizeof(resp.tso_caps);
690 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
691 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 692 }
693
f0313965
ES		 694 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
695 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
696 props->device_cap_flags |= IB_DEVICE_UD_TSO;
697 }
698
03404e8a
MG		 699 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
700 MLX5_CAP_GEN(dev->mdev, general_notification_event))
701 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
702
1d54f890
YH		 703 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
704 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
705 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
706
cff5a0f3 707 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
e8161334
NO		 708 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
709 /* Legacy bit to support old userspace libraries */
cff5a0f3 710 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 711 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
712 }
cff5a0f3 713
da6d6ba3
MG		 714 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
715 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
716
b1383aa6
NO		 717 if (MLX5_CAP_GEN(mdev, end_pad))
718 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
719
1b5daf11
MD		 720 props->vendor_part_id = mdev->pdev->device;
721 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 722
723 props->max_mr_size = ~0ull;
e0238a6a 724 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 725 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
726 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
727 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
728 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 729 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
730 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
731 sizeof(struct mlx5_wqe_raddr_seg)) /
732 sizeof(struct mlx5_wqe_data_seg);
e126ba97 733 props->max_sge = min(max_rq_sg, max_sq_sg);
986ef95e 734 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 735 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 736 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 737 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
738 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
739 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
740 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
741 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
742 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
743 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 744 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 745 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 746 props->max_fast_reg_page_list_len =
747 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
da7525d2 748 get_atomic_caps(dev, props);
81bea28f 749 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 750 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
751 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 752 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
753 props->max_mcast_grp;
754 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 755 props->max_ah = INT_MAX;
7c60bcbb
MB		 756 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
757 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 758
8cdd312c 759#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 760 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 761 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
762 props->odp_caps = dev->odp_caps;
763#endif
764
051f2630
LR		 765 if (MLX5_CAP_GEN(mdev, cd))
766 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
767
eff901d3
EC		 768 if (!mlx5_core_is_pf(mdev))
769 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
770
31f69a82
YH		 771 if (mlx5_ib_port_link_layer(ibdev, 1) ==
772 IB_LINK_LAYER_ETHERNET) {
773 props->rss_caps.max_rwq_indirection_tables =
774 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
775 props->rss_caps.max_rwq_indirection_table_size =
776 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
777 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
778 props->max_wq_type_rq =
779 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
780 }
781
eb761894 782 if (MLX5_CAP_GEN(mdev, tag_matching)) {
78b1beb0
LR		 783 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
784 props->tm_caps.max_num_tags =
eb761894 785 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
78b1beb0
LR		 786 props->tm_caps.flags = IB_TM_CAP_RC;
787 props->tm_caps.max_ops =
eb761894 788 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
78b1beb0 789 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
eb761894
AK		 790 }
791
87ab3f52
YC		 792 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
793 props->cq_caps.max_cq_moderation_count =
794 MLX5_MAX_CQ_COUNT;
795 props->cq_caps.max_cq_moderation_period =
796 MLX5_MAX_CQ_PERIOD;
797 }
798
7e43a2a5
BW		 799 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
800 resp.cqe_comp_caps.max_num =
801 MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
802 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
803 resp.cqe_comp_caps.supported_format =
804 MLX5_IB_CQE_RES_FORMAT_HASH |
805 MLX5_IB_CQE_RES_FORMAT_CSUM;
806 resp.response_length += sizeof(resp.cqe_comp_caps);
807 }
808
d949167d
BW		 809 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) {
810 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
811 MLX5_CAP_GEN(mdev, qos)) {
812 resp.packet_pacing_caps.qp_rate_limit_max =
813 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
814 resp.packet_pacing_caps.qp_rate_limit_min =
815 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
816 resp.packet_pacing_caps.supported_qpts |=
817 1 << IB_QPT_RAW_PACKET;
818 }
819 resp.response_length += sizeof(resp.packet_pacing_caps);
820 }
821
9f885201
LR		 822 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
823 uhw->outlen)) {
795b609c
BW		 824 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
825 resp.mlx5_ib_support_multi_pkt_send_wqes =
826 MLX5_IB_ALLOW_MPW;
050da902
BW		 827
828 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
829 resp.mlx5_ib_support_multi_pkt_send_wqes |=
830 MLX5_IB_SUPPORT_EMPW;
831
9f885201
LR		 832 resp.response_length +=
833 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
834 }
835
de57f2ad
GL		 836 if (field_avail(typeof(resp), flags, uhw->outlen)) {
837 resp.response_length += sizeof(resp.flags);
7a0c8f42 838
de57f2ad
GL		 839 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
840 resp.flags |=
841 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
7a0c8f42
GL		 842
843 if (MLX5_CAP_GEN(mdev, cqe_128_always))
844 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
de57f2ad 845 }
9f885201 846
96dc3fc5
NO		 847 if (field_avail(typeof(resp), sw_parsing_caps,
848 uhw->outlen)) {
849 resp.response_length += sizeof(resp.sw_parsing_caps);
850 if (MLX5_CAP_ETH(mdev, swp)) {
851 resp.sw_parsing_caps.sw_parsing_offloads |=
852 MLX5_IB_SW_PARSING;
853
854 if (MLX5_CAP_ETH(mdev, swp_csum))
855 resp.sw_parsing_caps.sw_parsing_offloads |=
856 MLX5_IB_SW_PARSING_CSUM;
857
858 if (MLX5_CAP_ETH(mdev, swp_lso))
859 resp.sw_parsing_caps.sw_parsing_offloads |=
860 MLX5_IB_SW_PARSING_LSO;
861
862 if (resp.sw_parsing_caps.sw_parsing_offloads)
863 resp.sw_parsing_caps.supported_qpts =
864 BIT(IB_QPT_RAW_PACKET);
865 }
866 }
867
b4f34597
NO		 868 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen)) {
869 resp.response_length += sizeof(resp.striding_rq_caps);
870 if (MLX5_CAP_GEN(mdev, striding_rq)) {
871 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
872 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
873 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
874 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
875 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
876 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
877 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
878 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
879 resp.striding_rq_caps.supported_qpts =
880 BIT(IB_QPT_RAW_PACKET);
881 }
882 }
883
f95ef6cb
MG		 884 if (field_avail(typeof(resp), tunnel_offloads_caps,
885 uhw->outlen)) {
886 resp.response_length += sizeof(resp.tunnel_offloads_caps);
887 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
888 resp.tunnel_offloads_caps |=
889 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
890 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
891 resp.tunnel_offloads_caps |=
892 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
893 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
894 resp.tunnel_offloads_caps |=
895 MLX5_IB_TUNNELED_OFFLOADS_GRE;
896 }
897
402ca536
BW		 898 if (uhw->outlen) {
899 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
900
901 if (err)
902 return err;
903 }
904
1b5daf11 905 return 0;
e126ba97
EC		 906}
907
1b5daf11
MD		 908enum mlx5_ib_width {
909 MLX5_IB_WIDTH_1X = 1 << 0,
910 MLX5_IB_WIDTH_2X = 1 << 1,
911 MLX5_IB_WIDTH_4X = 1 << 2,
912 MLX5_IB_WIDTH_8X = 1 << 3,
913 MLX5_IB_WIDTH_12X = 1 << 4
914};
915
916static int translate_active_width(struct ib_device *ibdev, u8 active_width,
917 u8 *ib_width)
e126ba97
EC		 918{
919 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 920 int err = 0;
921
922 if (active_width & MLX5_IB_WIDTH_1X) {
923 *ib_width = IB_WIDTH_1X;
924 } else if (active_width & MLX5_IB_WIDTH_2X) {
925 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
926 (int)active_width);
927 err = -EINVAL;
928 } else if (active_width & MLX5_IB_WIDTH_4X) {
929 *ib_width = IB_WIDTH_4X;
930 } else if (active_width & MLX5_IB_WIDTH_8X) {
931 *ib_width = IB_WIDTH_8X;
932 } else if (active_width & MLX5_IB_WIDTH_12X) {
933 *ib_width = IB_WIDTH_12X;
934 } else {
935 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
936 (int)active_width);
937 err = -EINVAL;
e126ba97
EC		 938 }
939
1b5daf11
MD		 940 return err;
941}
e126ba97 942
1b5daf11
MD		 943static int mlx5_mtu_to_ib_mtu(int mtu)
944{
945 switch (mtu) {
946 case 256: return 1;
947 case 512: return 2;
948 case 1024: return 3;
949 case 2048: return 4;
950 case 4096: return 5;
951 default:
952 pr_warn("invalid mtu\n");
953 return -1;
e126ba97 954 }
1b5daf11 955}
e126ba97 956
1b5daf11
MD		 957enum ib_max_vl_num {
958 __IB_MAX_VL_0 = 1,
959 __IB_MAX_VL_0_1 = 2,
960 __IB_MAX_VL_0_3 = 3,
961 __IB_MAX_VL_0_7 = 4,
962 __IB_MAX_VL_0_14 = 5,
963};
e126ba97 964
1b5daf11
MD		 965enum mlx5_vl_hw_cap {
966 MLX5_VL_HW_0 = 1,
967 MLX5_VL_HW_0_1 = 2,
968 MLX5_VL_HW_0_2 = 3,
969 MLX5_VL_HW_0_3 = 4,
970 MLX5_VL_HW_0_4 = 5,
971 MLX5_VL_HW_0_5 = 6,
972 MLX5_VL_HW_0_6 = 7,
973 MLX5_VL_HW_0_7 = 8,
974 MLX5_VL_HW_0_14 = 15
975};
e126ba97 976
1b5daf11
MD		 977static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
978 u8 *max_vl_num)
979{
980 switch (vl_hw_cap) {
981 case MLX5_VL_HW_0:
982 *max_vl_num = __IB_MAX_VL_0;
983 break;
984 case MLX5_VL_HW_0_1:
985 *max_vl_num = __IB_MAX_VL_0_1;
986 break;
987 case MLX5_VL_HW_0_3:
988 *max_vl_num = __IB_MAX_VL_0_3;
989 break;
990 case MLX5_VL_HW_0_7:
991 *max_vl_num = __IB_MAX_VL_0_7;
992 break;
993 case MLX5_VL_HW_0_14:
994 *max_vl_num = __IB_MAX_VL_0_14;
995 break;
e126ba97 996
1b5daf11
MD		 997 default:
998 return -EINVAL;
e126ba97 999 }
e126ba97 1000
1b5daf11 1001 return 0;
e126ba97
EC		 1002}
1003
1b5daf11
MD		 1004static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1005 struct ib_port_attr *props)
e126ba97 1006{
1b5daf11
MD		 1007 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1008 struct mlx5_core_dev *mdev = dev->mdev;
1009 struct mlx5_hca_vport_context *rep;
046339ea
SM		 1010 u16 max_mtu;
1011 u16 oper_mtu;
1b5daf11
MD		 1012 int err;
1013 u8 ib_link_width_oper;
1014 u8 vl_hw_cap;
e126ba97 1015
1b5daf11
MD		 1016 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1017 if (!rep) {
1018 err = -ENOMEM;
e126ba97 1019 goto out;
e126ba97 1020 }
e126ba97 1021
c4550c63 1022 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 1023
1b5daf11 1024 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 1025 if (err)
1026 goto out;
1027
1b5daf11
MD		 1028 props->lid = rep->lid;
1029 props->lmc = rep->lmc;
1030 props->sm_lid = rep->sm_lid;
1031 props->sm_sl = rep->sm_sl;
1032 props->state = rep->vport_state;
1033 props->phys_state = rep->port_physical_state;
1034 props->port_cap_flags = rep->cap_mask1;
1035 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1036 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1037 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1038 props->bad_pkey_cntr = rep->pkey_violation_counter;
1039 props->qkey_viol_cntr = rep->qkey_violation_counter;
1040 props->subnet_timeout = rep->subnet_timeout;
1041 props->init_type_reply = rep->init_type_reply;
eff901d3 1042 props->grh_required = rep->grh_required;
e126ba97 1043
1b5daf11
MD		 1044 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1045 if (err)
e126ba97 1046 goto out;
e126ba97 1047
1b5daf11
MD		 1048 err = translate_active_width(ibdev, ib_link_width_oper,
1049 &props->active_width);
1050 if (err)
1051 goto out;
d5beb7f2 1052 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 1053 if (err)
1054 goto out;
1055
facc9699 1056 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 1057
1b5daf11 1058 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 1059
facc9699 1060 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 1061
1b5daf11 1062 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1063
1b5daf11
MD		 1064 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1065 if (err)
1066 goto out;
e126ba97 1067
1b5daf11
MD		 1068 err = translate_max_vl_num(ibdev, vl_hw_cap,
1069 &props->max_vl_num);
e126ba97 1070out:
1b5daf11 1071 kfree(rep);
e126ba97
EC		 1072 return err;
1073}
1074
1b5daf11
MD		 1075int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1076 struct ib_port_attr *props)
e126ba97 1077{
095b0927
IT		 1078 unsigned int count;
1079 int ret;
1080
1b5daf11
MD		 1081 switch (mlx5_get_vport_access_method(ibdev)) {
1082 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1083 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1084 break;
e126ba97 1085
1b5daf11 1086 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1087 ret = mlx5_query_hca_port(ibdev, port, props);
1088 break;
e126ba97 1089
3f89a643 1090 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1091 ret = mlx5_query_port_roce(ibdev, port, props);
1092 break;
3f89a643 1093
1b5daf11 1094 default:
095b0927
IT		 1095 ret = -EINVAL;
1096 }
1097
1098 if (!ret && props) {
1099 count = mlx5_core_reserved_gids_count(to_mdev(ibdev)->mdev);
1100 props->gid_tbl_len -= count;
1b5daf11 1101 }
095b0927 1102 return ret;
1b5daf11 1103}
e126ba97 1104
1b5daf11
MD		 1105static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1106 union ib_gid *gid)
1107{
1108 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1109 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1110
1b5daf11
MD		 1111 switch (mlx5_get_vport_access_method(ibdev)) {
1112 case MLX5_VPORT_ACCESS_METHOD_MAD:
1113 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1114
1b5daf11
MD		 1115 case MLX5_VPORT_ACCESS_METHOD_HCA:
1116 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1117
1118 default:
1119 return -EINVAL;
1120 }
e126ba97 1121
e126ba97
EC		 1122}
1123
1b5daf11
MD		 1124static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1125 u16 *pkey)
1126{
1127 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1128 struct mlx5_core_dev *mdev = dev->mdev;
1129
1130 switch (mlx5_get_vport_access_method(ibdev)) {
1131 case MLX5_VPORT_ACCESS_METHOD_MAD:
1132 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1133
1134 case MLX5_VPORT_ACCESS_METHOD_HCA:
1135 case MLX5_VPORT_ACCESS_METHOD_NIC:
1136 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
1137 pkey);
1138 default:
1139 return -EINVAL;
1140 }
1141}
e126ba97
EC		 1142
1143static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1144 struct ib_device_modify *props)
1145{
1146 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1147 struct mlx5_reg_node_desc in;
1148 struct mlx5_reg_node_desc out;
1149 int err;
1150
1151 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1152 return -EOPNOTSUPP;
1153
1154 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1155 return 0;
1156
1157 /*
1158 * If possible, pass node desc to FW, so it can generate
1159 * a 144 trap. If cmd fails, just ignore.
1160 */
bd99fdea 1161 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1162 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1163 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1164 if (err)
1165 return err;
1166
bd99fdea 1167 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1168
1169 return err;
1170}
1171
cdbe33d0
EC		 1172static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1173 u32 value)
1174{
1175 struct mlx5_hca_vport_context ctx = {};
1176 int err;
1177
1178 err = mlx5_query_hca_vport_context(dev->mdev, 0,
1179 port_num, 0, &ctx);
1180 if (err)
1181 return err;
1182
1183 if (~ctx.cap_mask1_perm & mask) {
1184 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1185 mask, ctx.cap_mask1_perm);
1186 return -EINVAL;
1187 }
1188
1189 ctx.cap_mask1 = value;
1190 ctx.cap_mask1_perm = mask;
1191 err = mlx5_core_modify_hca_vport_context(dev->mdev, 0,
1192 port_num, 0, &ctx);
1193
1194 return err;
1195}
1196
e126ba97
EC		 1197static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1198 struct ib_port_modify *props)
1199{
1200 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1201 struct ib_port_attr attr;
1202 u32 tmp;
1203 int err;
cdbe33d0
EC		 1204 u32 change_mask;
1205 u32 value;
1206 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1207 IB_LINK_LAYER_INFINIBAND);
1208
ec255879
MD		 1209 /* CM layer calls ib_modify_port() regardless of the link layer. For
1210 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1211 */
1212 if (!is_ib)
1213 return 0;
1214
cdbe33d0
EC		 1215 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1216 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1217 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1218 return set_port_caps_atomic(dev, port, change_mask, value);
1219 }
e126ba97
EC		 1220
1221 mutex_lock(&dev->cap_mask_mutex);
1222
c4550c63 1223 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1224 if (err)
1225 goto out;
1226
1227 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1228 ~props->clr_port_cap_mask;
1229
9603b61d 1230 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1231
1232out:
1233 mutex_unlock(&dev->cap_mask_mutex);
1234 return err;
1235}
1236
30aa60b3
EC		 1237static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1238{
1239 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1240 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1241}
1242
b037c29a
EC		 1243static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1244 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1245 u32 *num_sys_pages)
1246{
1247 int uars_per_sys_page;
1248 int bfregs_per_sys_page;
1249 int ref_bfregs = req->total_num_bfregs;
1250
1251 if (req->total_num_bfregs == 0)
1252 return -EINVAL;
1253
1254 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1255 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1256
1257 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1258 return -ENOMEM;
1259
1260 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1261 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1262 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1263 *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1264
1265 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1266 return -EINVAL;
1267
9c2d33d4 1268 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, using %d sys pages\n",
b037c29a
EC		 1269 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1270 lib_uar_4k ? "yes" : "no", ref_bfregs,
1271 req->total_num_bfregs, *num_sys_pages);
1272
1273 return 0;
1274}
1275
1276static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1277{
1278 struct mlx5_bfreg_info *bfregi;
1279 int err;
1280 int i;
1281
1282 bfregi = &context->bfregi;
1283 for (i = 0; i < bfregi->num_sys_pages; i++) {
1284 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1285 if (err)
1286 goto error;
1287
1288 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1289 }
1290 return 0;
1291
1292error:
1293 for (--i; i >= 0; i--)
1294 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1295 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1296
1297 return err;
1298}
1299
1300static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1301{
1302 struct mlx5_bfreg_info *bfregi;
1303 int err;
1304 int i;
1305
1306 bfregi = &context->bfregi;
1307 for (i = 0; i < bfregi->num_sys_pages; i++) {
1308 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1309 if (err) {
1310 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1311 return err;
1312 }
1313 }
1314 return 0;
1315}
1316
c85023e1
HN		 1317static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1318{
1319 int err;
1320
1321 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1322 if (err)
1323 return err;
1324
1325 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1326 !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1327 return err;
1328
1329 mutex_lock(&dev->lb_mutex);
1330 dev->user_td++;
1331
1332 if (dev->user_td == 2)
1333 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1334
1335 mutex_unlock(&dev->lb_mutex);
1336 return err;
1337}
1338
1339static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1340{
1341 mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1342
1343 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1344 !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1345 return;
1346
1347 mutex_lock(&dev->lb_mutex);
1348 dev->user_td--;
1349
1350 if (dev->user_td < 2)
1351 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1352
1353 mutex_unlock(&dev->lb_mutex);
1354}
1355
e126ba97
EC		 1356static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1357 struct ib_udata *udata)
1358{
1359 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1360 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1361 struct mlx5_ib_alloc_ucontext_resp resp = {};
e126ba97 1362 struct mlx5_ib_ucontext *context;
2f5ff264 1363 struct mlx5_bfreg_info *bfregi;
78c0f98c 1364 int ver;
e126ba97 1365 int err;
a168a41c
MD		 1366 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1367 max_cqe_version);
b037c29a 1368 bool lib_uar_4k;
e126ba97
EC		 1369
1370 if (!dev->ib_active)
1371 return ERR_PTR(-EAGAIN);
1372
e093111d 1373 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1374 ver = 0;
e093111d 1375 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1376 ver = 2;
1377 else
1378 return ERR_PTR(-EINVAL);
1379
e093111d 1380 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97
EC		 1381 if (err)
1382 return ERR_PTR(err);
1383
b368d7cb 1384 if (req.flags)
78c0f98c
EC		 1385 return ERR_PTR(-EINVAL);
1386
f72300c5 1387 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 1388 return ERR_PTR(-EOPNOTSUPP);
1389
2f5ff264
EC		 1390 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1391 MLX5_NON_FP_BFREGS_PER_UAR);
1392 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
e126ba97
EC		 1393 return ERR_PTR(-EINVAL);
1394
938fe83c 1395 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1396 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1397 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1398 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1399 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1400 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1401 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1402 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1403 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1404 resp.cqe_version = min_t(__u8,
1405 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1406 req.max_cqe_version);
30aa60b3
EC		 1407 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1408 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1409 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1410 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1411 resp.response_length = min(offsetof(typeof(resp), response_length) +
1412 sizeof(resp.response_length), udata->outlen);
e126ba97
EC		 1413
1414 context = kzalloc(sizeof(*context), GFP_KERNEL);
1415 if (!context)
1416 return ERR_PTR(-ENOMEM);
1417
30aa60b3 1418 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1419 bfregi = &context->bfregi;
b037c29a
EC		 1420
1421 /* updates req->total_num_bfregs */
1422 err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages);
1423 if (err)
e126ba97 1424 goto out_ctx;
e126ba97 1425
b037c29a
EC		 1426 mutex_init(&bfregi->lock);
1427 bfregi->lib_uar_4k = lib_uar_4k;
1428 bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1429 GFP_KERNEL);
b037c29a 1430 if (!bfregi->count) {
e126ba97 1431 err = -ENOMEM;
b037c29a 1432 goto out_ctx;
e126ba97
EC		 1433 }
1434
b037c29a
EC		 1435 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1436 sizeof(*bfregi->sys_pages),
1437 GFP_KERNEL);
1438 if (!bfregi->sys_pages) {
e126ba97 1439 err = -ENOMEM;
b037c29a 1440 goto out_count;
e126ba97
EC		 1441 }
1442
b037c29a
EC		 1443 err = allocate_uars(dev, context);
1444 if (err)
1445 goto out_sys_pages;
e126ba97 1446
b4cfe447
HE		 1447#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1448 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1449#endif
1450
7d0cc6ed
AK		 1451 context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1452 if (!context->upd_xlt_page) {
1453 err = -ENOMEM;
1454 goto out_uars;
1455 }
1456 mutex_init(&context->upd_xlt_page_mutex);
1457
146d2f1a 1458 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
c85023e1 1459 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
146d2f1a 1460 if (err)
7d0cc6ed 1461 goto out_page;
146d2f1a 1462 }
1463
7c2344c3 1464 INIT_LIST_HEAD(&context->vma_private_list);
ad9a3668 1465 mutex_init(&context->vma_private_list_mutex);
e126ba97
EC		 1466 INIT_LIST_HEAD(&context->db_page_list);
1467 mutex_init(&context->db_page_mutex);
1468
2f5ff264 1469 resp.tot_bfregs = req.total_num_bfregs;
938fe83c 1470 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
b368d7cb 1471
f72300c5
HA		 1472 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1473 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1474
402ca536 1475 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1476 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1477 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1478 resp.response_length += sizeof(resp.cmds_supp_uhw);
1479 }
1480
78984898
OG		 1481 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1482 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1483 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1484 resp.eth_min_inline++;
1485 }
1486 resp.response_length += sizeof(resp.eth_min_inline);
1487 }
1488
bc5c6eed
NO		 1489 /*
1490 * We don't want to expose information from the PCI bar that is located
1491 * after 4096 bytes, so if the arch only supports larger pages, let's
1492 * pretend we don't support reading the HCA's core clock. This is also
1493 * forced by mmap function.
1494 */
de8d6e02
EC		 1495 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1496 if (PAGE_SIZE <= 4096) {
1497 resp.comp_mask |=
1498 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1499 resp.hca_core_clock_offset =
1500 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1501 }
f72300c5 1502 resp.response_length += sizeof(resp.hca_core_clock_offset) +
402ca536 1503 sizeof(resp.reserved2);
b368d7cb
MB		 1504 }
1505
30aa60b3
EC		 1506 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1507 resp.response_length += sizeof(resp.log_uar_size);
1508
1509 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1510 resp.response_length += sizeof(resp.num_uars_per_page);
1511
b368d7cb 1512 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1513 if (err)
146d2f1a 1514 goto out_td;
e126ba97 1515
2f5ff264
EC		 1516 bfregi->ver = ver;
1517 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1518 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1519 context->lib_caps = req.lib_caps;
1520 print_lib_caps(dev, context->lib_caps);
f72300c5 1521
e126ba97
EC		 1522 return &context->ibucontext;
1523
146d2f1a 1524out_td:
1525 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
c85023e1 1526 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1527
7d0cc6ed
AK		 1528out_page:
1529 free_page(context->upd_xlt_page);
1530
e126ba97 1531out_uars:
b037c29a 1532 deallocate_uars(dev, context);
e126ba97 1533
b037c29a
EC		 1534out_sys_pages:
1535 kfree(bfregi->sys_pages);
e126ba97 1536
b037c29a
EC		 1537out_count:
1538 kfree(bfregi->count);
e126ba97
EC		 1539
1540out_ctx:
1541 kfree(context);
b037c29a 1542
e126ba97
EC		 1543 return ERR_PTR(err);
1544}
1545
1546static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1547{
1548 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1549 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 1550 struct mlx5_bfreg_info *bfregi;
e126ba97 1551
b037c29a 1552 bfregi = &context->bfregi;
146d2f1a 1553 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
c85023e1 1554 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1555
7d0cc6ed 1556 free_page(context->upd_xlt_page);
b037c29a
EC		 1557 deallocate_uars(dev, context);
1558 kfree(bfregi->sys_pages);
2f5ff264 1559 kfree(bfregi->count);
e126ba97
EC		 1560 kfree(context);
1561
1562 return 0;
1563}
1564
b037c29a
EC		 1565static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1566 struct mlx5_bfreg_info *bfregi,
1567 int idx)
e126ba97 1568{
b037c29a
EC		 1569 int fw_uars_per_page;
1570
1571 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1572
1573 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) +
1574 bfregi->sys_pages[idx] / fw_uars_per_page;
e126ba97
EC		 1575}
1576
1577static int get_command(unsigned long offset)
1578{
1579 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1580}
1581
1582static int get_arg(unsigned long offset)
1583{
1584 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1585}
1586
1587static int get_index(unsigned long offset)
1588{
1589 return get_arg(offset);
1590}
1591
7c2344c3
MG		 1592static void mlx5_ib_vma_open(struct vm_area_struct *area)
1593{
1594 /* vma_open is called when a new VMA is created on top of our VMA. This
1595 * is done through either mremap flow or split_vma (usually due to
1596 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1597 * as this VMA is strongly hardware related. Therefore we set the
1598 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1599 * calling us again and trying to do incorrect actions. We assume that
1600 * the original VMA size is exactly a single page, and therefore all
1601 * "splitting" operation will not happen to it.
1602 */
1603 area->vm_ops = NULL;
1604}
1605
1606static void mlx5_ib_vma_close(struct vm_area_struct *area)
1607{
1608 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1609
1610 /* It's guaranteed that all VMAs opened on a FD are closed before the
1611 * file itself is closed, therefore no sync is needed with the regular
1612 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1613 * However need a sync with accessing the vma as part of
1614 * mlx5_ib_disassociate_ucontext.
1615 * The close operation is usually called under mm->mmap_sem except when
1616 * process is exiting.
1617 * The exiting case is handled explicitly as part of
1618 * mlx5_ib_disassociate_ucontext.
1619 */
1620 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1621
1622 /* setting the vma context pointer to null in the mlx5_ib driver's
1623 * private data, to protect a race condition in
1624 * mlx5_ib_disassociate_ucontext().
1625 */
1626 mlx5_ib_vma_priv_data->vma = NULL;
ad9a3668 1627 mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
7c2344c3 1628 list_del(&mlx5_ib_vma_priv_data->list);
ad9a3668 1629 mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
7c2344c3
MG		 1630 kfree(mlx5_ib_vma_priv_data);
1631}
1632
1633static const struct vm_operations_struct mlx5_ib_vm_ops = {
1634 .open = mlx5_ib_vma_open,
1635 .close = mlx5_ib_vma_close
1636};
1637
1638static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1639 struct mlx5_ib_ucontext *ctx)
1640{
1641 struct mlx5_ib_vma_private_data *vma_prv;
1642 struct list_head *vma_head = &ctx->vma_private_list;
1643
1644 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1645 if (!vma_prv)
1646 return -ENOMEM;
1647
1648 vma_prv->vma = vma;
ad9a3668 1649 vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
7c2344c3
MG		 1650 vma->vm_private_data = vma_prv;
1651 vma->vm_ops = &mlx5_ib_vm_ops;
1652
ad9a3668 1653 mutex_lock(&ctx->vma_private_list_mutex);
7c2344c3 1654 list_add(&vma_prv->list, vma_head);
ad9a3668 1655 mutex_unlock(&ctx->vma_private_list_mutex);
7c2344c3
MG		 1656
1657 return 0;
1658}
1659
1660static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1661{
1662 int ret;
1663 struct vm_area_struct *vma;
1664 struct mlx5_ib_vma_private_data *vma_private, *n;
1665 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1666 struct task_struct *owning_process = NULL;
1667 struct mm_struct *owning_mm = NULL;
1668
1669 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1670 if (!owning_process)
1671 return;
1672
1673 owning_mm = get_task_mm(owning_process);
1674 if (!owning_mm) {
1675 pr_info("no mm, disassociate ucontext is pending task termination\n");
1676 while (1) {
1677 put_task_struct(owning_process);
1678 usleep_range(1000, 2000);
1679 owning_process = get_pid_task(ibcontext->tgid,
1680 PIDTYPE_PID);
1681 if (!owning_process ||
1682 owning_process->state == TASK_DEAD) {
1683 pr_info("disassociate ucontext done, task was terminated\n");
1684 /* in case task was dead need to release the
1685 * task struct.
1686 */
1687 if (owning_process)
1688 put_task_struct(owning_process);
1689 return;
1690 }
1691 }
1692 }
1693
1694 /* need to protect from a race on closing the vma as part of
1695 * mlx5_ib_vma_close.
1696 */
ecc7d83b 1697 down_write(&owning_mm->mmap_sem);
ad9a3668 1698 mutex_lock(&context->vma_private_list_mutex);
7c2344c3
MG		 1699 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1700 list) {
1701 vma = vma_private->vma;
1702 ret = zap_vma_ptes(vma, vma->vm_start,
1703 PAGE_SIZE);
1704 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1705 /* context going to be destroyed, should
1706 * not access ops any more.
1707 */
13776612 1708 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
7c2344c3
MG		 1709 vma->vm_ops = NULL;
1710 list_del(&vma_private->list);
1711 kfree(vma_private);
1712 }
ad9a3668 1713 mutex_unlock(&context->vma_private_list_mutex);
ecc7d83b 1714 up_write(&owning_mm->mmap_sem);
7c2344c3
MG		 1715 mmput(owning_mm);
1716 put_task_struct(owning_process);
1717}
1718
37aa5c36
GL		 1719static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1720{
1721 switch (cmd) {
1722 case MLX5_IB_MMAP_WC_PAGE:
1723 return "WC";
1724 case MLX5_IB_MMAP_REGULAR_PAGE:
1725 return "best effort WC";
1726 case MLX5_IB_MMAP_NC_PAGE:
1727 return "NC";
1728 default:
1729 return NULL;
1730 }
1731}
1732
1733static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 1734 struct vm_area_struct *vma,
1735 struct mlx5_ib_ucontext *context)
37aa5c36 1736{
2f5ff264 1737 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 1738 int err;
1739 unsigned long idx;
1740 phys_addr_t pfn, pa;
1741 pgprot_t prot;
b037c29a
EC		 1742 int uars_per_page;
1743
1744 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1745 return -EINVAL;
1746
1747 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
1748 idx = get_index(vma->vm_pgoff);
1749 if (idx % uars_per_page ||
1750 idx * uars_per_page >= bfregi->num_sys_pages) {
1751 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx);
1752 return -EINVAL;
1753 }
37aa5c36
GL		 1754
1755 switch (cmd) {
1756 case MLX5_IB_MMAP_WC_PAGE:
1757/* Some architectures don't support WC memory */
1758#if defined(CONFIG_X86)
1759 if (!pat_enabled())
1760 return -EPERM;
1761#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1762 return -EPERM;
1763#endif
1764 /* fall through */
1765 case MLX5_IB_MMAP_REGULAR_PAGE:
1766 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1767 prot = pgprot_writecombine(vma->vm_page_prot);
1768 break;
1769 case MLX5_IB_MMAP_NC_PAGE:
1770 prot = pgprot_noncached(vma->vm_page_prot);
1771 break;
1772 default:
1773 return -EINVAL;
1774 }
1775
b037c29a 1776 pfn = uar_index2pfn(dev, bfregi, idx);
37aa5c36
GL		 1777 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1778
1779 vma->vm_page_prot = prot;
1780 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1781 PAGE_SIZE, vma->vm_page_prot);
1782 if (err) {
1783 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1784 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1785 return -EAGAIN;
1786 }
1787
1788 pa = pfn << PAGE_SHIFT;
1789 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1790 vma->vm_start, &pa);
1791
7c2344c3 1792 return mlx5_ib_set_vma_data(vma, context);
37aa5c36
GL		 1793}
1794
e126ba97
EC		 1795static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1796{
1797 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1798 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 1799 unsigned long command;
e126ba97
EC		 1800 phys_addr_t pfn;
1801
1802 command = get_command(vma->vm_pgoff);
1803 switch (command) {
37aa5c36
GL		 1804 case MLX5_IB_MMAP_WC_PAGE:
1805 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 1806 case MLX5_IB_MMAP_REGULAR_PAGE:
7c2344c3 1807 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 1808
1809 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1810 return -ENOSYS;
1811
d69e3bcf 1812 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 1813 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1814 return -EINVAL;
1815
6cbac1e4 1816 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 1817 return -EPERM;
1818
1819 /* Don't expose to user-space information it shouldn't have */
1820 if (PAGE_SIZE > 4096)
1821 return -EOPNOTSUPP;
1822
1823 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1824 pfn = (dev->mdev->iseg_base +
1825 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1826 PAGE_SHIFT;
1827 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1828 PAGE_SIZE, vma->vm_page_prot))
1829 return -EAGAIN;
1830
1831 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1832 vma->vm_start,
1833 (unsigned long long)pfn << PAGE_SHIFT);
1834 break;
d69e3bcf 1835
e126ba97
EC		 1836 default:
1837 return -EINVAL;
1838 }
1839
1840 return 0;
1841}
1842
e126ba97
EC		 1843static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1844 struct ib_ucontext *context,
1845 struct ib_udata *udata)
1846{
1847 struct mlx5_ib_alloc_pd_resp resp;
1848 struct mlx5_ib_pd *pd;
1849 int err;
1850
1851 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1852 if (!pd)
1853 return ERR_PTR(-ENOMEM);
1854
9603b61d 1855 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 1856 if (err) {
1857 kfree(pd);
1858 return ERR_PTR(err);
1859 }
1860
1861 if (context) {
1862 resp.pdn = pd->pdn;
1863 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 1864 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 1865 kfree(pd);
1866 return ERR_PTR(-EFAULT);
1867 }
e126ba97
EC		 1868 }
1869
1870 return &pd->ibpd;
1871}
1872
1873static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1874{
1875 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1876 struct mlx5_ib_pd *mpd = to_mpd(pd);
1877
9603b61d 1878 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 1879 kfree(mpd);
1880
1881 return 0;
1882}
1883
466fa6d2
MG		 1884enum {
1885 MATCH_CRITERIA_ENABLE_OUTER_BIT,
1886 MATCH_CRITERIA_ENABLE_MISC_BIT,
1887 MATCH_CRITERIA_ENABLE_INNER_BIT
1888};
1889
1890#define HEADER_IS_ZERO(match_criteria, headers) \
1891 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1892 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 1893
466fa6d2 1894static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 1895{
466fa6d2 1896 u8 match_criteria_enable;
038d2ef8 1897
466fa6d2
MG		 1898 match_criteria_enable =
1899 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1900 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1901 match_criteria_enable |=
1902 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1903 MATCH_CRITERIA_ENABLE_MISC_BIT;
1904 match_criteria_enable |=
1905 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1906 MATCH_CRITERIA_ENABLE_INNER_BIT;
1907
1908 return match_criteria_enable;
038d2ef8
MG		 1909}
1910
ca0d4753
MG		 1911static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1912{
1913 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1914 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
038d2ef8
MG		 1915}
1916
2d1e697e
MR		 1917static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
1918 bool inner)
1919{
1920 if (inner) {
1921 MLX5_SET(fte_match_set_misc,
1922 misc_c, inner_ipv6_flow_label, mask);
1923 MLX5_SET(fte_match_set_misc,
1924 misc_v, inner_ipv6_flow_label, val);
1925 } else {
1926 MLX5_SET(fte_match_set_misc,
1927 misc_c, outer_ipv6_flow_label, mask);
1928 MLX5_SET(fte_match_set_misc,
1929 misc_v, outer_ipv6_flow_label, val);
1930 }
1931}
1932
ca0d4753
MG		 1933static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1934{
1935 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1936 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1937 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1938 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1939}
1940
c47ac6ae
MG		 1941#define LAST_ETH_FIELD vlan_tag
1942#define LAST_IB_FIELD sl
ca0d4753 1943#define LAST_IPV4_FIELD tos
466fa6d2 1944#define LAST_IPV6_FIELD traffic_class
c47ac6ae 1945#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 1946#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 1947#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 1948#define LAST_DROP_FIELD size
c47ac6ae
MG		 1949
1950/* Field is the last supported field */
1951#define FIELDS_NOT_SUPPORTED(filter, field)\
1952 memchr_inv((void *)&filter.field +\
1953 sizeof(filter.field), 0,\
1954 sizeof(filter) -\
1955 offsetof(typeof(filter), field) -\
1956 sizeof(filter.field))
1957
19cc7524
AL		 1958#define IPV4_VERSION 4
1959#define IPV6_VERSION 6
1960static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
1961 u32 *match_v, const union ib_flow_spec *ib_spec,
a22ed86c 1962 u32 *tag_id, bool *is_drop)
038d2ef8 1963{
466fa6d2
MG		 1964 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1965 misc_parameters);
1966 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1967 misc_parameters);
2d1e697e
MR		 1968 void *headers_c;
1969 void *headers_v;
19cc7524 1970 int match_ipv;
2d1e697e
MR		 1971
1972 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
1973 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1974 inner_headers);
1975 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1976 inner_headers);
19cc7524
AL		 1977 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1978 ft_field_support.inner_ip_version);
2d1e697e
MR		 1979 } else {
1980 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1981 outer_headers);
1982 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1983 outer_headers);
19cc7524
AL		 1984 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1985 ft_field_support.outer_ip_version);
2d1e697e 1986 }
466fa6d2 1987
2d1e697e 1988 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 1989 case IB_FLOW_SPEC_ETH:
c47ac6ae 1990 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 1991 return -EOPNOTSUPP;
038d2ef8 1992
2d1e697e 1993 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1994 dmac_47_16),
1995 ib_spec->eth.mask.dst_mac);
2d1e697e 1996 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1997 dmac_47_16),
1998 ib_spec->eth.val.dst_mac);
1999
2d1e697e 2000 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 2001 smac_47_16),
2002 ib_spec->eth.mask.src_mac);
2d1e697e 2003 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 2004 smac_47_16),
2005 ib_spec->eth.val.src_mac);
2006
038d2ef8 2007 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 2008 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 2009 cvlan_tag, 1);
2d1e697e 2010 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 2011 cvlan_tag, 1);
038d2ef8 2012
2d1e697e 2013 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2014 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 2015 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2016 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2017
2d1e697e 2018 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2019 first_cfi,
2020 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 2021 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2022 first_cfi,
2023 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2024
2d1e697e 2025 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2026 first_prio,
2027 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 2028 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2029 first_prio,
2030 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2031 }
2d1e697e 2032 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2033 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 2034 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2035 ethertype, ntohs(ib_spec->eth.val.ether_type));
2036 break;
2037 case IB_FLOW_SPEC_IPV4:
c47ac6ae 2038 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 2039 return -EOPNOTSUPP;
038d2ef8 2040
19cc7524
AL		 2041 if (match_ipv) {
2042 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2043 ip_version, 0xf);
2044 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2045 ip_version, IPV4_VERSION);
2046 } else {
2047 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2048 ethertype, 0xffff);
2049 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2050 ethertype, ETH_P_IP);
2051 }
038d2ef8 2052
2d1e697e 2053 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2054 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2055 &ib_spec->ipv4.mask.src_ip,
2056 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 2057 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2058 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2059 &ib_spec->ipv4.val.src_ip,
2060 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 2061 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2062 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2063 &ib_spec->ipv4.mask.dst_ip,
2064 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 2065 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2066 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2067 &ib_spec->ipv4.val.dst_ip,
2068 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 2069
2d1e697e 2070 set_tos(headers_c, headers_v,
ca0d4753
MG		 2071 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2072
2d1e697e 2073 set_proto(headers_c, headers_v,
ca0d4753 2074 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
038d2ef8 2075 break;
026bae0c 2076 case IB_FLOW_SPEC_IPV6:
c47ac6ae 2077 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 2078 return -EOPNOTSUPP;
026bae0c 2079
19cc7524
AL		 2080 if (match_ipv) {
2081 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2082 ip_version, 0xf);
2083 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2084 ip_version, IPV6_VERSION);
2085 } else {
2086 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2087 ethertype, 0xffff);
2088 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2089 ethertype, ETH_P_IPV6);
2090 }
026bae0c 2091
2d1e697e 2092 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2093 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2094 &ib_spec->ipv6.mask.src_ip,
2095 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2096 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2097 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2098 &ib_spec->ipv6.val.src_ip,
2099 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2100 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2101 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2102 &ib_spec->ipv6.mask.dst_ip,
2103 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2104 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2105 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2106 &ib_spec->ipv6.val.dst_ip,
2107 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2108
2d1e697e 2109 set_tos(headers_c, headers_v,
466fa6d2
MG		 2110 ib_spec->ipv6.mask.traffic_class,
2111 ib_spec->ipv6.val.traffic_class);
2112
2d1e697e 2113 set_proto(headers_c, headers_v,
466fa6d2
MG		 2114 ib_spec->ipv6.mask.next_hdr,
2115 ib_spec->ipv6.val.next_hdr);
2116
2d1e697e
MR		 2117 set_flow_label(misc_params_c, misc_params_v,
2118 ntohl(ib_spec->ipv6.mask.flow_label),
2119 ntohl(ib_spec->ipv6.val.flow_label),
2120 ib_spec->type & IB_FLOW_SPEC_INNER);
2121
026bae0c 2122 break;
038d2ef8 2123 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2124 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2125 LAST_TCP_UDP_FIELD))
1ffd3a26 2126 return -EOPNOTSUPP;
038d2ef8 2127
2d1e697e 2128 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2129 0xff);
2d1e697e 2130 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2131 IPPROTO_TCP);
2132
2d1e697e 2133 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2134 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2135 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2136 ntohs(ib_spec->tcp_udp.val.src_port));
2137
2d1e697e 2138 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2139 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2140 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2141 ntohs(ib_spec->tcp_udp.val.dst_port));
2142 break;
2143 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2144 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2145 LAST_TCP_UDP_FIELD))
1ffd3a26 2146 return -EOPNOTSUPP;
038d2ef8 2147
2d1e697e 2148 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2149 0xff);
2d1e697e 2150 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2151 IPPROTO_UDP);
2152
2d1e697e 2153 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2154 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2155 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2156 ntohs(ib_spec->tcp_udp.val.src_port));
2157
2d1e697e 2158 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2159 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2160 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2161 ntohs(ib_spec->tcp_udp.val.dst_port));
2162 break;
ffb30d8f
MR		 2163 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2164 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2165 LAST_TUNNEL_FIELD))
1ffd3a26 2166 return -EOPNOTSUPP;
ffb30d8f
MR		 2167
2168 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2169 ntohl(ib_spec->tunnel.mask.tunnel_id));
2170 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2171 ntohl(ib_spec->tunnel.val.tunnel_id));
2172 break;
2ac693f9
MR		 2173 case IB_FLOW_SPEC_ACTION_TAG:
2174 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2175 LAST_FLOW_TAG_FIELD))
2176 return -EOPNOTSUPP;
2177 if (ib_spec->flow_tag.tag_id >= BIT(24))
2178 return -EINVAL;
2179
2180 *tag_id = ib_spec->flow_tag.tag_id;
2181 break;
a22ed86c
SS		 2182 case IB_FLOW_SPEC_ACTION_DROP:
2183 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2184 LAST_DROP_FIELD))
2185 return -EOPNOTSUPP;
2186 *is_drop = true;
2187 break;
038d2ef8
MG		 2188 default:
2189 return -EINVAL;
2190 }
2191
2192 return 0;
2193}
2194
2195/* If a flow could catch both multicast and unicast packets,
2196 * it won't fall into the multicast flow steering table and this rule
2197 * could steal other multicast packets.
2198 */
a550ddfc 2199static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
038d2ef8 2200{
81e30880 2201 union ib_flow_spec *flow_spec;
038d2ef8
MG		 2202
2203 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 2204 ib_attr->num_of_specs < 1)
2205 return false;
2206
81e30880
YH		 2207 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2208 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2209 struct ib_flow_spec_ipv4 *ipv4_spec;
2210
2211 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2212 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2213 return true;
2214
038d2ef8 2215 return false;
81e30880
YH		 2216 }
2217
2218 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2219 struct ib_flow_spec_eth *eth_spec;
2220
2221 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2222 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2223 is_multicast_ether_addr(eth_spec->val.dst_mac);
2224 }
038d2ef8 2225
81e30880 2226 return false;
038d2ef8
MG		 2227}
2228
19cc7524
AL		 2229static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2230 const struct ib_flow_attr *flow_attr,
0f750966 2231 bool check_inner)
038d2ef8
MG		 2232{
2233 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 2234 int match_ipv = check_inner ?
2235 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2236 ft_field_support.inner_ip_version) :
2237 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2238 ft_field_support.outer_ip_version);
0f750966
AL		 2239 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2240 bool ipv4_spec_valid, ipv6_spec_valid;
2241 unsigned int ip_spec_type = 0;
2242 bool has_ethertype = false;
038d2ef8 2243 unsigned int spec_index;
0f750966
AL		 2244 bool mask_valid = true;
2245 u16 eth_type = 0;
2246 bool type_valid;
038d2ef8
MG		 2247
2248 /* Validate that ethertype is correct */
2249 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 2250 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 2251 ib_spec->eth.mask.ether_type) {
0f750966
AL		 2252 mask_valid = (ib_spec->eth.mask.ether_type ==
2253 htons(0xffff));
2254 has_ethertype = true;
2255 eth_type = ntohs(ib_spec->eth.val.ether_type);
2256 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2257 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2258 ip_spec_type = ib_spec->type;
038d2ef8
MG		 2259 }
2260 ib_spec = (void *)ib_spec + ib_spec->size;
2261 }
0f750966
AL		 2262
2263 type_valid = (!has_ethertype) || (!ip_spec_type);
2264 if (!type_valid && mask_valid) {
2265 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2266 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2267 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2268 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 2269
2270 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2271 (((eth_type == ETH_P_MPLS_UC) ||
2272 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 2273 }
2274
2275 return type_valid;
2276}
2277
19cc7524
AL		 2278static bool is_valid_attr(struct mlx5_core_dev *mdev,
2279 const struct ib_flow_attr *flow_attr)
0f750966 2280{
19cc7524
AL		 2281 return is_valid_ethertype(mdev, flow_attr, false) &&
2282 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 2283}
2284
2285static void put_flow_table(struct mlx5_ib_dev *dev,
2286 struct mlx5_ib_flow_prio *prio, bool ft_added)
2287{
2288 prio->refcount -= !!ft_added;
2289 if (!prio->refcount) {
2290 mlx5_destroy_flow_table(prio->flow_table);
2291 prio->flow_table = NULL;
2292 }
2293}
2294
2295static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2296{
2297 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2298 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2299 struct mlx5_ib_flow_handler,
2300 ibflow);
2301 struct mlx5_ib_flow_handler *iter, *tmp;
2302
2303 mutex_lock(&dev->flow_db.lock);
2304
2305 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 2306 mlx5_del_flow_rules(iter->rule);
cc0e5d42 2307 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 2308 list_del(&iter->list);
2309 kfree(iter);
2310 }
2311
74491de9 2312 mlx5_del_flow_rules(handler->rule);
5497adc6 2313 put_flow_table(dev, handler->prio, true);
038d2ef8
MG		 2314 mutex_unlock(&dev->flow_db.lock);
2315
2316 kfree(handler);
2317
2318 return 0;
2319}
2320
35d19011
MG		 2321static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2322{
2323 priority *= 2;
2324 if (!dont_trap)
2325 priority++;
2326 return priority;
2327}
2328
cc0e5d42
MG		 2329enum flow_table_type {
2330 MLX5_IB_FT_RX,
2331 MLX5_IB_FT_TX
2332};
2333
00b7c2ab
MG		 2334#define MLX5_FS_MAX_TYPES 6
2335#define MLX5_FS_MAX_ENTRIES BIT(16)
038d2ef8 2336static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 2337 struct ib_flow_attr *flow_attr,
2338 enum flow_table_type ft_type)
038d2ef8 2339{
35d19011 2340 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 2341 struct mlx5_flow_namespace *ns = NULL;
2342 struct mlx5_ib_flow_prio *prio;
2343 struct mlx5_flow_table *ft;
dac388ef 2344 int max_table_size;
038d2ef8
MG		 2345 int num_entries;
2346 int num_groups;
2347 int priority;
2348 int err = 0;
2349
dac388ef
MG		 2350 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2351 log_max_ft_size));
038d2ef8 2352 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2353 if (flow_is_multicast_only(flow_attr) &&
2354 !dont_trap)
038d2ef8
MG		 2355 priority = MLX5_IB_FLOW_MCAST_PRIO;
2356 else
35d19011
MG		 2357 priority = ib_prio_to_core_prio(flow_attr->priority,
2358 dont_trap);
038d2ef8
MG		 2359 ns = mlx5_get_flow_namespace(dev->mdev,
2360 MLX5_FLOW_NAMESPACE_BYPASS);
2361 num_entries = MLX5_FS_MAX_ENTRIES;
2362 num_groups = MLX5_FS_MAX_TYPES;
2363 prio = &dev->flow_db.prios[priority];
2364 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2365 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2366 ns = mlx5_get_flow_namespace(dev->mdev,
2367 MLX5_FLOW_NAMESPACE_LEFTOVERS);
2368 build_leftovers_ft_param(&priority,
2369 &num_entries,
2370 &num_groups);
2371 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 2372 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2373 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2374 allow_sniffer_and_nic_rx_shared_tir))
2375 return ERR_PTR(-ENOTSUPP);
2376
2377 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2378 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2379 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2380
2381 prio = &dev->flow_db.sniffer[ft_type];
2382 priority = 0;
2383 num_entries = 1;
2384 num_groups = 1;
038d2ef8
MG		 2385 }
2386
2387 if (!ns)
2388 return ERR_PTR(-ENOTSUPP);
2389
dac388ef
MG		 2390 if (num_entries > max_table_size)
2391 return ERR_PTR(-ENOMEM);
2392
038d2ef8
MG		 2393 ft = prio->flow_table;
2394 if (!ft) {
2395 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2396 num_entries,
d63cd286 2397 num_groups,
c9f1b073 2398 0, 0);
038d2ef8
MG		 2399
2400 if (!IS_ERR(ft)) {
2401 prio->refcount = 0;
2402 prio->flow_table = ft;
2403 } else {
2404 err = PTR_ERR(ft);
2405 }
2406 }
2407
2408 return err ? ERR_PTR(err) : prio;
2409}
2410
a550ddfc
YH		 2411static void set_underlay_qp(struct mlx5_ib_dev *dev,
2412 struct mlx5_flow_spec *spec,
2413 u32 underlay_qpn)
2414{
2415 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
2416 spec->match_criteria,
2417 misc_parameters);
2418 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2419 misc_parameters);
2420
2421 if (underlay_qpn &&
2422 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2423 ft_field_support.bth_dst_qp)) {
2424 MLX5_SET(fte_match_set_misc,
2425 misc_params_v, bth_dst_qp, underlay_qpn);
2426 MLX5_SET(fte_match_set_misc,
2427 misc_params_c, bth_dst_qp, 0xffffff);
2428 }
2429}
2430
2431static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
2432 struct mlx5_ib_flow_prio *ft_prio,
2433 const struct ib_flow_attr *flow_attr,
2434 struct mlx5_flow_destination *dst,
2435 u32 underlay_qpn)
038d2ef8
MG		 2436{
2437 struct mlx5_flow_table *ft = ft_prio->flow_table;
2438 struct mlx5_ib_flow_handler *handler;
66958ed9 2439 struct mlx5_flow_act flow_act = {0};
c5bb1730 2440 struct mlx5_flow_spec *spec;
a22ed86c 2441 struct mlx5_flow_destination *rule_dst = dst;
dd063d0e 2442 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 2443 unsigned int spec_index;
2ac693f9 2444 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
a22ed86c 2445 bool is_drop = false;
038d2ef8 2446 int err = 0;
a22ed86c 2447 int dest_num = 1;
038d2ef8 2448
19cc7524 2449 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 2450 return ERR_PTR(-EINVAL);
2451
1b9a07ee 2452 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 2453 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 2454 if (!handler || !spec) {
038d2ef8
MG		 2455 err = -ENOMEM;
2456 goto free;
2457 }
2458
2459 INIT_LIST_HEAD(&handler->list);
2460
2461 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
19cc7524 2462 err = parse_flow_attr(dev->mdev, spec->match_criteria,
a22ed86c
SS		 2463 spec->match_value,
2464 ib_flow, &flow_tag, &is_drop);
038d2ef8
MG		 2465 if (err < 0)
2466 goto free;
2467
2468 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2469 }
2470
a550ddfc
YH		 2471 if (!flow_is_multicast_only(flow_attr))
2472 set_underlay_qp(dev, spec, underlay_qpn);
2473
466fa6d2 2474 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
a22ed86c
SS		 2475 if (is_drop) {
2476 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2477 rule_dst = NULL;
2478 dest_num = 0;
2479 } else {
2480 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2481 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2482 }
2ac693f9
MR		 2483
2484 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG &&
2485 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2486 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
2487 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
2488 flow_tag, flow_attr->type);
2489 err = -EINVAL;
2490 goto free;
2491 }
2492 flow_act.flow_tag = flow_tag;
74491de9 2493 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 2494 &flow_act,
a22ed86c 2495 rule_dst, dest_num);
038d2ef8
MG		 2496
2497 if (IS_ERR(handler->rule)) {
2498 err = PTR_ERR(handler->rule);
2499 goto free;
2500 }
2501
d9d4980a 2502 ft_prio->refcount++;
5497adc6 2503 handler->prio = ft_prio;
038d2ef8
MG		 2504
2505 ft_prio->flow_table = ft;
2506free:
2507 if (err)
2508 kfree(handler);
c5bb1730 2509 kvfree(spec);
038d2ef8
MG		 2510 return err ? ERR_PTR(err) : handler;
2511}
2512
a550ddfc
YH		 2513static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2514 struct mlx5_ib_flow_prio *ft_prio,
2515 const struct ib_flow_attr *flow_attr,
2516 struct mlx5_flow_destination *dst)
2517{
2518 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0);
2519}
2520
35d19011
MG		 2521static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2522 struct mlx5_ib_flow_prio *ft_prio,
2523 struct ib_flow_attr *flow_attr,
2524 struct mlx5_flow_destination *dst)
2525{
2526 struct mlx5_ib_flow_handler *handler_dst = NULL;
2527 struct mlx5_ib_flow_handler *handler = NULL;
2528
2529 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2530 if (!IS_ERR(handler)) {
2531 handler_dst = create_flow_rule(dev, ft_prio,
2532 flow_attr, dst);
2533 if (IS_ERR(handler_dst)) {
74491de9 2534 mlx5_del_flow_rules(handler->rule);
d9d4980a 2535 ft_prio->refcount--;
35d19011
MG		 2536 kfree(handler);
2537 handler = handler_dst;
2538 } else {
2539 list_add(&handler_dst->list, &handler->list);
2540 }
2541 }
2542
2543 return handler;
2544}
038d2ef8
MG		 2545enum {
2546 LEFTOVERS_MC,
2547 LEFTOVERS_UC,
2548};
2549
2550static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2551 struct mlx5_ib_flow_prio *ft_prio,
2552 struct ib_flow_attr *flow_attr,
2553 struct mlx5_flow_destination *dst)
2554{
2555 struct mlx5_ib_flow_handler *handler_ucast = NULL;
2556 struct mlx5_ib_flow_handler *handler = NULL;
2557
2558 static struct {
2559 struct ib_flow_attr flow_attr;
2560 struct ib_flow_spec_eth eth_flow;
2561 } leftovers_specs[] = {
2562 [LEFTOVERS_MC] = {
2563 .flow_attr = {
2564 .num_of_specs = 1,
2565 .size = sizeof(leftovers_specs[0])
2566 },
2567 .eth_flow = {
2568 .type = IB_FLOW_SPEC_ETH,
2569 .size = sizeof(struct ib_flow_spec_eth),
2570 .mask = {.dst_mac = {0x1} },
2571 .val = {.dst_mac = {0x1} }
2572 }
2573 },
2574 [LEFTOVERS_UC] = {
2575 .flow_attr = {
2576 .num_of_specs = 1,
2577 .size = sizeof(leftovers_specs[0])
2578 },
2579 .eth_flow = {
2580 .type = IB_FLOW_SPEC_ETH,
2581 .size = sizeof(struct ib_flow_spec_eth),
2582 .mask = {.dst_mac = {0x1} },
2583 .val = {.dst_mac = {} }
2584 }
2585 }
2586 };
2587
2588 handler = create_flow_rule(dev, ft_prio,
2589 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2590 dst);
2591 if (!IS_ERR(handler) &&
2592 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2593 handler_ucast = create_flow_rule(dev, ft_prio,
2594 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2595 dst);
2596 if (IS_ERR(handler_ucast)) {
74491de9 2597 mlx5_del_flow_rules(handler->rule);
d9d4980a 2598 ft_prio->refcount--;
038d2ef8
MG		 2599 kfree(handler);
2600 handler = handler_ucast;
2601 } else {
2602 list_add(&handler_ucast->list, &handler->list);
2603 }
2604 }
2605
2606 return handler;
2607}
2608
cc0e5d42
MG		 2609static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2610 struct mlx5_ib_flow_prio *ft_rx,
2611 struct mlx5_ib_flow_prio *ft_tx,
2612 struct mlx5_flow_destination *dst)
2613{
2614 struct mlx5_ib_flow_handler *handler_rx;
2615 struct mlx5_ib_flow_handler *handler_tx;
2616 int err;
2617 static const struct ib_flow_attr flow_attr = {
2618 .num_of_specs = 0,
2619 .size = sizeof(flow_attr)
2620 };
2621
2622 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2623 if (IS_ERR(handler_rx)) {
2624 err = PTR_ERR(handler_rx);
2625 goto err;
2626 }
2627
2628 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2629 if (IS_ERR(handler_tx)) {
2630 err = PTR_ERR(handler_tx);
2631 goto err_tx;
2632 }
2633
2634 list_add(&handler_tx->list, &handler_rx->list);
2635
2636 return handler_rx;
2637
2638err_tx:
74491de9 2639 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 2640 ft_rx->refcount--;
2641 kfree(handler_rx);
2642err:
2643 return ERR_PTR(err);
2644}
2645
038d2ef8
MG		 2646static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2647 struct ib_flow_attr *flow_attr,
2648 int domain)
2649{
2650 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 2651 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 2652 struct mlx5_ib_flow_handler *handler = NULL;
2653 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 2654 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8
MG		 2655 struct mlx5_ib_flow_prio *ft_prio;
2656 int err;
a550ddfc 2657 int underlay_qpn;
038d2ef8
MG		 2658
2659 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
dac388ef 2660 return ERR_PTR(-ENOMEM);
038d2ef8
MG		 2661
2662 if (domain != IB_FLOW_DOMAIN_USER ||
2663 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
35d19011 2664 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
038d2ef8
MG		 2665 return ERR_PTR(-EINVAL);
2666
2667 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2668 if (!dst)
2669 return ERR_PTR(-ENOMEM);
2670
2671 mutex_lock(&dev->flow_db.lock);
2672
cc0e5d42 2673 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
038d2ef8
MG		 2674 if (IS_ERR(ft_prio)) {
2675 err = PTR_ERR(ft_prio);
2676 goto unlock;
2677 }
cc0e5d42
MG		 2678 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2679 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2680 if (IS_ERR(ft_prio_tx)) {
2681 err = PTR_ERR(ft_prio_tx);
2682 ft_prio_tx = NULL;
2683 goto destroy_ft;
2684 }
2685 }
038d2ef8
MG		 2686
2687 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
d9f88e5a
YH		 2688 if (mqp->flags & MLX5_IB_QP_RSS)
2689 dst->tir_num = mqp->rss_qp.tirn;
2690 else
2691 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
038d2ef8
MG		 2692
2693 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2694 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2695 handler = create_dont_trap_rule(dev, ft_prio,
2696 flow_attr, dst);
2697 } else {
a550ddfc
YH		 2698 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
2699 mqp->underlay_qpn : 0;
2700 handler = _create_flow_rule(dev, ft_prio, flow_attr,
2701 dst, underlay_qpn);
35d19011 2702 }
038d2ef8
MG		 2703 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2704 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2705 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2706 dst);
cc0e5d42
MG		 2707 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2708 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 2709 } else {
2710 err = -EINVAL;
2711 goto destroy_ft;
2712 }
2713
2714 if (IS_ERR(handler)) {
2715 err = PTR_ERR(handler);
2716 handler = NULL;
2717 goto destroy_ft;
2718 }
2719
038d2ef8
MG		 2720 mutex_unlock(&dev->flow_db.lock);
2721 kfree(dst);
2722
2723 return &handler->ibflow;
2724
2725destroy_ft:
2726 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 2727 if (ft_prio_tx)
2728 put_flow_table(dev, ft_prio_tx, false);
038d2ef8
MG		 2729unlock:
2730 mutex_unlock(&dev->flow_db.lock);
2731 kfree(dst);
2732 kfree(handler);
2733 return ERR_PTR(err);
2734}
2735
e126ba97
EC		 2736static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2737{
2738 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 2739 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97
EC		 2740 int err;
2741
81e30880
YH		 2742 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
2743 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
2744 return -EOPNOTSUPP;
2745 }
2746
9603b61d 2747 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2748 if (err)
2749 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2750 ibqp->qp_num, gid->raw);
2751
2752 return err;
2753}
2754
2755static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2756{
2757 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2758 int err;
2759
9603b61d 2760 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2761 if (err)
2762 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2763 ibqp->qp_num, gid->raw);
2764
2765 return err;
2766}
2767
2768static int init_node_data(struct mlx5_ib_dev *dev)
2769{
1b5daf11 2770 int err;
e126ba97 2771
1b5daf11 2772 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 2773 if (err)
1b5daf11 2774 return err;
e126ba97 2775
1b5daf11 2776 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 2777
1b5daf11 2778 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 2779}
2780
2781static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2782 char *buf)
2783{
2784 struct mlx5_ib_dev *dev =
2785 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2786
9603b61d 2787 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 2788}
2789
2790static ssize_t show_reg_pages(struct device *device,
2791 struct device_attribute *attr, char *buf)
2792{
2793 struct mlx5_ib_dev *dev =
2794 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2795
6aec21f6 2796 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 2797}
2798
2799static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2800 char *buf)
2801{
2802 struct mlx5_ib_dev *dev =
2803 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 2804 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 2805}
2806
e126ba97
EC		 2807static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2808 char *buf)
2809{
2810 struct mlx5_ib_dev *dev =
2811 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 2812 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 2813}
2814
2815static ssize_t show_board(struct device *device, struct device_attribute *attr,
2816 char *buf)
2817{
2818 struct mlx5_ib_dev *dev =
2819 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2820 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 2821 dev->mdev->board_id);
e126ba97
EC		 2822}
2823
2824static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
e126ba97
EC		 2825static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2826static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2827static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2828static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2829
2830static struct device_attribute *mlx5_class_attributes[] = {
2831 &dev_attr_hw_rev,
e126ba97
EC		 2832 &dev_attr_hca_type,
2833 &dev_attr_board_id,
2834 &dev_attr_fw_pages,
2835 &dev_attr_reg_pages,
2836};
2837
7722f47e
HE		 2838static void pkey_change_handler(struct work_struct *work)
2839{
2840 struct mlx5_ib_port_resources *ports =
2841 container_of(work, struct mlx5_ib_port_resources,
2842 pkey_change_work);
2843
2844 mutex_lock(&ports->devr->mutex);
2845 mlx5_ib_gsi_pkey_change(ports->gsi);
2846 mutex_unlock(&ports->devr->mutex);
2847}
2848
89ea94a7
MG		 2849static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2850{
2851 struct mlx5_ib_qp *mqp;
2852 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2853 struct mlx5_core_cq *mcq;
2854 struct list_head cq_armed_list;
2855 unsigned long flags_qp;
2856 unsigned long flags_cq;
2857 unsigned long flags;
2858
2859 INIT_LIST_HEAD(&cq_armed_list);
2860
2861 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2862 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2863 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2864 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2865 if (mqp->sq.tail != mqp->sq.head) {
2866 send_mcq = to_mcq(mqp->ibqp.send_cq);
2867 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2868 if (send_mcq->mcq.comp &&
2869 mqp->ibqp.send_cq->comp_handler) {
2870 if (!send_mcq->mcq.reset_notify_added) {
2871 send_mcq->mcq.reset_notify_added = 1;
2872 list_add_tail(&send_mcq->mcq.reset_notify,
2873 &cq_armed_list);
2874 }
2875 }
2876 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2877 }
2878 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2879 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2880 /* no handling is needed for SRQ */
2881 if (!mqp->ibqp.srq) {
2882 if (mqp->rq.tail != mqp->rq.head) {
2883 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2884 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2885 if (recv_mcq->mcq.comp &&
2886 mqp->ibqp.recv_cq->comp_handler) {
2887 if (!recv_mcq->mcq.reset_notify_added) {
2888 recv_mcq->mcq.reset_notify_added = 1;
2889 list_add_tail(&recv_mcq->mcq.reset_notify,
2890 &cq_armed_list);
2891 }
2892 }
2893 spin_unlock_irqrestore(&recv_mcq->lock,
2894 flags_cq);
2895 }
2896 }
2897 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2898 }
2899 /*At that point all inflight post send were put to be executed as of we
2900 * lock/unlock above locks Now need to arm all involved CQs.
2901 */
2902 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2903 mcq->comp(mcq);
2904 }
2905 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2906}
2907
03404e8a
MG		 2908static void delay_drop_handler(struct work_struct *work)
2909{
2910 int err;
2911 struct mlx5_ib_delay_drop *delay_drop =
2912 container_of(work, struct mlx5_ib_delay_drop,
2913 delay_drop_work);
2914
fe248c3a
MG		 2915 atomic_inc(&delay_drop->events_cnt);
2916
03404e8a
MG		 2917 mutex_lock(&delay_drop->lock);
2918 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
2919 delay_drop->timeout);
2920 if (err) {
2921 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
2922 delay_drop->timeout);
2923 delay_drop->activate = false;
2924 }
2925 mutex_unlock(&delay_drop->lock);
2926}
2927
9603b61d 2928static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 2929 enum mlx5_dev_event event, unsigned long param)
e126ba97 2930{
9603b61d 2931 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
e126ba97 2932 struct ib_event ibev;
dbaaff2a 2933 bool fatal = false;
e126ba97
EC		 2934 u8 port = 0;
2935
2936 switch (event) {
2937 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 2938 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 2939 mlx5_ib_handle_internal_error(ibdev);
dbaaff2a 2940 fatal = true;
e126ba97
EC		 2941 break;
2942
2943 case MLX5_DEV_EVENT_PORT_UP:
e126ba97 2944 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 2945 case MLX5_DEV_EVENT_PORT_INITIALIZED:
4d2f9bbb 2946 port = (u8)param;
5ec8c83e
AH		 2947
2948 /* In RoCE, port up/down events are handled in
2949 * mlx5_netdev_event().
2950 */
2951 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2952 IB_LINK_LAYER_ETHERNET)
2953 return;
2954
2955 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2956 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
e126ba97
EC		 2957 break;
2958
e126ba97
EC		 2959 case MLX5_DEV_EVENT_LID_CHANGE:
2960 ibev.event = IB_EVENT_LID_CHANGE;
4d2f9bbb 2961 port = (u8)param;
e126ba97
EC		 2962 break;
2963
2964 case MLX5_DEV_EVENT_PKEY_CHANGE:
2965 ibev.event = IB_EVENT_PKEY_CHANGE;
4d2f9bbb 2966 port = (u8)param;
7722f47e
HE		 2967
2968 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 2969 break;
2970
2971 case MLX5_DEV_EVENT_GUID_CHANGE:
2972 ibev.event = IB_EVENT_GID_CHANGE;
4d2f9bbb 2973 port = (u8)param;
e126ba97
EC		 2974 break;
2975
2976 case MLX5_DEV_EVENT_CLIENT_REREG:
2977 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4d2f9bbb 2978 port = (u8)param;
e126ba97 2979 break;
03404e8a
MG		 2980 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
2981 schedule_work(&ibdev->delay_drop.delay_drop_work);
2982 goto out;
bdc37924 2983 default:
03404e8a 2984 goto out;
e126ba97
EC		 2985 }
2986
2987 ibev.device = &ibdev->ib_dev;
2988 ibev.element.port_num = port;
2989
a0c84c32
EC		 2990 if (port < 1 || port > ibdev->num_ports) {
2991 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
03404e8a 2992 goto out;
a0c84c32
EC		 2993 }
2994
e126ba97
EC		 2995 if (ibdev->ib_active)
2996 ib_dispatch_event(&ibev);
dbaaff2a
EC		 2997
2998 if (fatal)
2999 ibdev->ib_active = false;
03404e8a
MG		 3000
3001out:
3002 return;
e126ba97
EC		 3003}
3004
c43f1112
MG		 3005static int set_has_smi_cap(struct mlx5_ib_dev *dev)
3006{
3007 struct mlx5_hca_vport_context vport_ctx;
3008 int err;
3009 int port;
3010
3011 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
3012 dev->mdev->port_caps[port - 1].has_smi = false;
3013 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
3014 MLX5_CAP_PORT_TYPE_IB) {
3015 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
3016 err = mlx5_query_hca_vport_context(dev->mdev, 0,
3017 port, 0,
3018 &vport_ctx);
3019 if (err) {
3020 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
3021 port, err);
3022 return err;
3023 }
3024 dev->mdev->port_caps[port - 1].has_smi =
3025 vport_ctx.has_smi;
3026 } else {
3027 dev->mdev->port_caps[port - 1].has_smi = true;
3028 }
3029 }
3030 }
3031 return 0;
3032}
3033
e126ba97
EC		 3034static void get_ext_port_caps(struct mlx5_ib_dev *dev)
3035{
3036 int port;
3037
938fe83c 3038 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
e126ba97
EC		 3039 mlx5_query_ext_port_caps(dev, port);
3040}
3041
3042static int get_port_caps(struct mlx5_ib_dev *dev)
3043{
3044 struct ib_device_attr *dprops = NULL;
3045 struct ib_port_attr *pprops = NULL;
f614fc15 3046 int err = -ENOMEM;
e126ba97 3047 int port;
2528e33e 3048 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 3049
3050 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
3051 if (!pprops)
3052 goto out;
3053
3054 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
3055 if (!dprops)
3056 goto out;
3057
c43f1112
MG		 3058 err = set_has_smi_cap(dev);
3059 if (err)
3060 goto out;
3061
2528e33e 3062 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 3063 if (err) {
3064 mlx5_ib_warn(dev, "query_device failed %d\n", err);
3065 goto out;
3066 }
3067
938fe83c 3068 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
c4550c63 3069 memset(pprops, 0, sizeof(*pprops));
e126ba97
EC		 3070 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
3071 if (err) {
938fe83c
SM		 3072 mlx5_ib_warn(dev, "query_port %d failed %d\n",
3073 port, err);
e126ba97
EC		 3074 break;
3075 }
938fe83c
SM		 3076 dev->mdev->port_caps[port - 1].pkey_table_len =
3077 dprops->max_pkeys;
3078 dev->mdev->port_caps[port - 1].gid_table_len =
3079 pprops->gid_tbl_len;
e126ba97
EC		 3080 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
3081 dprops->max_pkeys, pprops->gid_tbl_len);
3082 }
3083
3084out:
3085 kfree(pprops);
3086 kfree(dprops);
3087
3088 return err;
3089}
3090
3091static void destroy_umrc_res(struct mlx5_ib_dev *dev)
3092{
3093 int err;
3094
3095 err = mlx5_mr_cache_cleanup(dev);
3096 if (err)
3097 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
3098
3099 mlx5_ib_destroy_qp(dev->umrc.qp);
add08d76 3100 ib_free_cq(dev->umrc.cq);
e126ba97
EC		 3101 ib_dealloc_pd(dev->umrc.pd);
3102}
3103
3104enum {
3105 MAX_UMR_WR = 128,
3106};
3107
3108static int create_umr_res(struct mlx5_ib_dev *dev)
3109{
3110 struct ib_qp_init_attr *init_attr = NULL;
3111 struct ib_qp_attr *attr = NULL;
3112 struct ib_pd *pd;
3113 struct ib_cq *cq;
3114 struct ib_qp *qp;
e126ba97
EC		 3115 int ret;
3116
3117 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
3118 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
3119 if (!attr || !init_attr) {
3120 ret = -ENOMEM;
3121 goto error_0;
3122 }
3123
ed082d36 3124 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 3125 if (IS_ERR(pd)) {
3126 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
3127 ret = PTR_ERR(pd);
3128 goto error_0;
3129 }
3130
add08d76 3131 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 3132 if (IS_ERR(cq)) {
3133 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
3134 ret = PTR_ERR(cq);
3135 goto error_2;
3136 }
e126ba97
EC		 3137
3138 init_attr->send_cq = cq;
3139 init_attr->recv_cq = cq;
3140 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
3141 init_attr->cap.max_send_wr = MAX_UMR_WR;
3142 init_attr->cap.max_send_sge = 1;
3143 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
3144 init_attr->port_num = 1;
3145 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
3146 if (IS_ERR(qp)) {
3147 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
3148 ret = PTR_ERR(qp);
3149 goto error_3;
3150 }
3151 qp->device = &dev->ib_dev;
3152 qp->real_qp = qp;
3153 qp->uobject = NULL;
3154 qp->qp_type = MLX5_IB_QPT_REG_UMR;
31fde034
MD		 3155 qp->send_cq = init_attr->send_cq;
3156 qp->recv_cq = init_attr->recv_cq;
e126ba97
EC		 3157
3158 attr->qp_state = IB_QPS_INIT;
3159 attr->port_num = 1;
3160 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
3161 IB_QP_PORT, NULL);
3162 if (ret) {
3163 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
3164 goto error_4;
3165 }
3166
3167 memset(attr, 0, sizeof(*attr));
3168 attr->qp_state = IB_QPS_RTR;
3169 attr->path_mtu = IB_MTU_256;
3170
3171 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3172 if (ret) {
3173 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
3174 goto error_4;
3175 }
3176
3177 memset(attr, 0, sizeof(*attr));
3178 attr->qp_state = IB_QPS_RTS;
3179 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3180 if (ret) {
3181 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
3182 goto error_4;
3183 }
3184
3185 dev->umrc.qp = qp;
3186 dev->umrc.cq = cq;
e126ba97
EC		 3187 dev->umrc.pd = pd;
3188
3189 sema_init(&dev->umrc.sem, MAX_UMR_WR);
3190 ret = mlx5_mr_cache_init(dev);
3191 if (ret) {
3192 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
3193 goto error_4;
3194 }
3195
3196 kfree(attr);
3197 kfree(init_attr);
3198
3199 return 0;
3200
3201error_4:
3202 mlx5_ib_destroy_qp(qp);
3203
3204error_3:
add08d76 3205 ib_free_cq(cq);
e126ba97
EC		 3206
3207error_2:
e126ba97
EC		 3208 ib_dealloc_pd(pd);
3209
3210error_0:
3211 kfree(attr);
3212 kfree(init_attr);
3213 return ret;
3214}
3215
6e8484c5
MG		 3216static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
3217{
3218 switch (umr_fence_cap) {
3219 case MLX5_CAP_UMR_FENCE_NONE:
3220 return MLX5_FENCE_MODE_NONE;
3221 case MLX5_CAP_UMR_FENCE_SMALL:
3222 return MLX5_FENCE_MODE_INITIATOR_SMALL;
3223 default:
3224 return MLX5_FENCE_MODE_STRONG_ORDERING;
3225 }
3226}
3227
e126ba97
EC		 3228static int create_dev_resources(struct mlx5_ib_resources *devr)
3229{
3230 struct ib_srq_init_attr attr;
3231 struct mlx5_ib_dev *dev;
bcf4c1ea 3232 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 3233 int port;
e126ba97
EC		 3234 int ret = 0;
3235
3236 dev = container_of(devr, struct mlx5_ib_dev, devr);
3237
d16e91da
HE		 3238 mutex_init(&devr->mutex);
3239
e126ba97
EC		 3240 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
3241 if (IS_ERR(devr->p0)) {
3242 ret = PTR_ERR(devr->p0);
3243 goto error0;
3244 }
3245 devr->p0->device = &dev->ib_dev;
3246 devr->p0->uobject = NULL;
3247 atomic_set(&devr->p0->usecnt, 0);
3248
bcf4c1ea 3249 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 3250 if (IS_ERR(devr->c0)) {
3251 ret = PTR_ERR(devr->c0);
3252 goto error1;
3253 }
3254 devr->c0->device = &dev->ib_dev;
3255 devr->c0->uobject = NULL;
3256 devr->c0->comp_handler = NULL;
3257 devr->c0->event_handler = NULL;
3258 devr->c0->cq_context = NULL;
3259 atomic_set(&devr->c0->usecnt, 0);
3260
3261 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3262 if (IS_ERR(devr->x0)) {
3263 ret = PTR_ERR(devr->x0);
3264 goto error2;
3265 }
3266 devr->x0->device = &dev->ib_dev;
3267 devr->x0->inode = NULL;
3268 atomic_set(&devr->x0->usecnt, 0);
3269 mutex_init(&devr->x0->tgt_qp_mutex);
3270 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
3271
3272 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3273 if (IS_ERR(devr->x1)) {
3274 ret = PTR_ERR(devr->x1);
3275 goto error3;
3276 }
3277 devr->x1->device = &dev->ib_dev;
3278 devr->x1->inode = NULL;
3279 atomic_set(&devr->x1->usecnt, 0);
3280 mutex_init(&devr->x1->tgt_qp_mutex);
3281 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
3282
3283 memset(&attr, 0, sizeof(attr));
3284 attr.attr.max_sge = 1;
3285 attr.attr.max_wr = 1;
3286 attr.srq_type = IB_SRQT_XRC;
1a56ff6d 3287 attr.ext.cq = devr->c0;
e126ba97
EC		 3288 attr.ext.xrc.xrcd = devr->x0;
3289
3290 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3291 if (IS_ERR(devr->s0)) {
3292 ret = PTR_ERR(devr->s0);
3293 goto error4;
3294 }
3295 devr->s0->device = &dev->ib_dev;
3296 devr->s0->pd = devr->p0;
3297 devr->s0->uobject = NULL;
3298 devr->s0->event_handler = NULL;
3299 devr->s0->srq_context = NULL;
3300 devr->s0->srq_type = IB_SRQT_XRC;
3301 devr->s0->ext.xrc.xrcd = devr->x0;
1a56ff6d 3302 devr->s0->ext.cq = devr->c0;
e126ba97 3303 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1a56ff6d 3304 atomic_inc(&devr->s0->ext.cq->usecnt);
e126ba97
EC		 3305 atomic_inc(&devr->p0->usecnt);
3306 atomic_set(&devr->s0->usecnt, 0);
3307
4aa17b28
HA		 3308 memset(&attr, 0, sizeof(attr));
3309 attr.attr.max_sge = 1;
3310 attr.attr.max_wr = 1;
3311 attr.srq_type = IB_SRQT_BASIC;
3312 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3313 if (IS_ERR(devr->s1)) {
3314 ret = PTR_ERR(devr->s1);
3315 goto error5;
3316 }
3317 devr->s1->device = &dev->ib_dev;
3318 devr->s1->pd = devr->p0;
3319 devr->s1->uobject = NULL;
3320 devr->s1->event_handler = NULL;
3321 devr->s1->srq_context = NULL;
3322 devr->s1->srq_type = IB_SRQT_BASIC;
1a56ff6d 3323 devr->s1->ext.cq = devr->c0;
4aa17b28 3324 atomic_inc(&devr->p0->usecnt);
1a56ff6d 3325 atomic_set(&devr->s1->usecnt, 0);
4aa17b28 3326
7722f47e
HE		 3327 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
3328 INIT_WORK(&devr->ports[port].pkey_change_work,
3329 pkey_change_handler);
3330 devr->ports[port].devr = devr;
3331 }
3332
e126ba97
EC		 3333 return 0;
3334
4aa17b28
HA		 3335error5:
3336 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 3337error4:
3338 mlx5_ib_dealloc_xrcd(devr->x1);
3339error3:
3340 mlx5_ib_dealloc_xrcd(devr->x0);
3341error2:
3342 mlx5_ib_destroy_cq(devr->c0);
3343error1:
3344 mlx5_ib_dealloc_pd(devr->p0);
3345error0:
3346 return ret;
3347}
3348
3349static void destroy_dev_resources(struct mlx5_ib_resources *devr)
3350{
7722f47e
HE		 3351 struct mlx5_ib_dev *dev =
3352 container_of(devr, struct mlx5_ib_dev, devr);
3353 int port;
3354
4aa17b28 3355 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 3356 mlx5_ib_destroy_srq(devr->s0);
3357 mlx5_ib_dealloc_xrcd(devr->x0);
3358 mlx5_ib_dealloc_xrcd(devr->x1);
3359 mlx5_ib_destroy_cq(devr->c0);
3360 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 3361
3362 /* Make sure no change P_Key work items are still executing */
3363 for (port = 0; port < dev->num_ports; ++port)
3364 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 3365}
3366
e53505a8
AS		 3367static u32 get_core_cap_flags(struct ib_device *ibdev)
3368{
3369 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3370 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3371 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3372 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3373 u32 ret = 0;
3374
3375 if (ll == IB_LINK_LAYER_INFINIBAND)
3376 return RDMA_CORE_PORT_IBA_IB;
3377
72cd5717
OG		 3378 ret = RDMA_CORE_PORT_RAW_PACKET;
3379
e53505a8 3380 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 3381 return ret;
e53505a8
AS		 3382
3383 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 3384 return ret;
e53505a8
AS		 3385
3386 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3387 ret |= RDMA_CORE_PORT_IBA_ROCE;
3388
3389 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3390 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3391
3392 return ret;
3393}
3394
7738613e
IW		 3395static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3396 struct ib_port_immutable *immutable)
3397{
3398 struct ib_port_attr attr;
ca5b91d6
OG		 3399 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3400 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
7738613e
IW		 3401 int err;
3402
c4550c63
OG		 3403 immutable->core_cap_flags = get_core_cap_flags(ibdev);
3404
3405 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 3406 if (err)
3407 return err;
3408
3409 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3410 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 3411 immutable->core_cap_flags = get_core_cap_flags(ibdev);
ca5b91d6
OG		 3412 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3413 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 3414
3415 return 0;
3416}
3417
9abb0d1b 3418static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 3419{
3420 struct mlx5_ib_dev *dev =
3421 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 3422 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
3423 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
3424 fw_rev_sub(dev->mdev));
c7342823
IW		 3425}
3426
45f95acd 3427static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 3428{
3429 struct mlx5_core_dev *mdev = dev->mdev;
3430 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3431 MLX5_FLOW_NAMESPACE_LAG);
3432 struct mlx5_flow_table *ft;
3433 int err;
3434
3435 if (!ns || !mlx5_lag_is_active(mdev))
3436 return 0;
3437
3438 err = mlx5_cmd_create_vport_lag(mdev);
3439 if (err)
3440 return err;
3441
3442 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3443 if (IS_ERR(ft)) {
3444 err = PTR_ERR(ft);
3445 goto err_destroy_vport_lag;
3446 }
3447
3448 dev->flow_db.lag_demux_ft = ft;
3449 return 0;
3450
3451err_destroy_vport_lag:
3452 mlx5_cmd_destroy_vport_lag(mdev);
3453 return err;
3454}
3455
45f95acd 3456static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 3457{
3458 struct mlx5_core_dev *mdev = dev->mdev;
3459
3460 if (dev->flow_db.lag_demux_ft) {
3461 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
3462 dev->flow_db.lag_demux_ft = NULL;
3463
3464 mlx5_cmd_destroy_vport_lag(mdev);
3465 }
3466}
3467
d012f5d6
OG		 3468static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev)
3469{
3470 int err;
3471
3472 dev->roce.nb.notifier_call = mlx5_netdev_event;
3473 err = register_netdevice_notifier(&dev->roce.nb);
3474 if (err) {
3475 dev->roce.nb.notifier_call = NULL;
3476 return err;
3477 }
3478
3479 return 0;
3480}
3481
3482static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev)
5ec8c83e
AH		 3483{
3484 if (dev->roce.nb.notifier_call) {
3485 unregister_netdevice_notifier(&dev->roce.nb);
3486 dev->roce.nb.notifier_call = NULL;
3487 }
3488}
3489
45f95acd 3490static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 3491{
e53505a8
AS		 3492 int err;
3493
d012f5d6
OG		 3494 err = mlx5_add_netdev_notifier(dev);
3495 if (err)
e53505a8
AS		 3496 return err;
3497
ca5b91d6
OG		 3498 if (MLX5_CAP_GEN(dev->mdev, roce)) {
3499 err = mlx5_nic_vport_enable_roce(dev->mdev);
3500 if (err)
3501 goto err_unregister_netdevice_notifier;
3502 }
e53505a8 3503
45f95acd 3504 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 3505 if (err)
3506 goto err_disable_roce;
3507
e53505a8
AS		 3508 return 0;
3509
9ef9c640 3510err_disable_roce:
ca5b91d6
OG		 3511 if (MLX5_CAP_GEN(dev->mdev, roce))
3512 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 3513
e53505a8 3514err_unregister_netdevice_notifier:
d012f5d6 3515 mlx5_remove_netdev_notifier(dev);
e53505a8 3516 return err;
fc24fc5e
AS		 3517}
3518
45f95acd 3519static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 3520{
45f95acd 3521 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 3522 if (MLX5_CAP_GEN(dev->mdev, roce))
3523 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 3524}
3525
e1f24a79 3526struct mlx5_ib_counter {
7c16f477
KH		 3527 const char *name;
3528 size_t offset;
3529};
3530
3531#define INIT_Q_COUNTER(_name) \
3532 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3533
e1f24a79 3534static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 3535 INIT_Q_COUNTER(rx_write_requests),
3536 INIT_Q_COUNTER(rx_read_requests),
3537 INIT_Q_COUNTER(rx_atomic_requests),
3538 INIT_Q_COUNTER(out_of_buffer),
3539};
3540
e1f24a79 3541static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 3542 INIT_Q_COUNTER(out_of_sequence),
3543};
3544
e1f24a79 3545static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 3546 INIT_Q_COUNTER(duplicate_request),
3547 INIT_Q_COUNTER(rnr_nak_retry_err),
3548 INIT_Q_COUNTER(packet_seq_err),
3549 INIT_Q_COUNTER(implied_nak_seq_err),
3550 INIT_Q_COUNTER(local_ack_timeout_err),
3551};
3552
e1f24a79
PP		 3553#define INIT_CONG_COUNTER(_name) \
3554 { .name = #_name, .offset = \
3555 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
3556
3557static const struct mlx5_ib_counter cong_cnts[] = {
3558 INIT_CONG_COUNTER(rp_cnp_ignored),
3559 INIT_CONG_COUNTER(rp_cnp_handled),
3560 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
3561 INIT_CONG_COUNTER(np_cnp_sent),
3562};
3563
58dcb60a
PP		 3564static const struct mlx5_ib_counter extended_err_cnts[] = {
3565 INIT_Q_COUNTER(resp_local_length_error),
3566 INIT_Q_COUNTER(resp_cqe_error),
3567 INIT_Q_COUNTER(req_cqe_error),
3568 INIT_Q_COUNTER(req_remote_invalid_request),
3569 INIT_Q_COUNTER(req_remote_access_errors),
3570 INIT_Q_COUNTER(resp_remote_access_errors),
3571 INIT_Q_COUNTER(resp_cqe_flush_error),
3572 INIT_Q_COUNTER(req_cqe_flush_error),
3573};
3574
e1f24a79 3575static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a
MB		 3576{
3577 unsigned int i;
3578
7c16f477 3579 for (i = 0; i < dev->num_ports; i++) {
0837e86a 3580 mlx5_core_dealloc_q_counter(dev->mdev,
e1f24a79
PP		 3581 dev->port[i].cnts.set_id);
3582 kfree(dev->port[i].cnts.names);
3583 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 3584 }
3585}
3586
e1f24a79
PP		 3587static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
3588 struct mlx5_ib_counters *cnts)
7c16f477
KH		 3589{
3590 u32 num_counters;
3591
3592 num_counters = ARRAY_SIZE(basic_q_cnts);
3593
3594 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
3595 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
3596
3597 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
3598 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 3599
3600 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
3601 num_counters += ARRAY_SIZE(extended_err_cnts);
3602
e1f24a79 3603 cnts->num_q_counters = num_counters;
7c16f477 3604
e1f24a79
PP		 3605 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3606 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
3607 num_counters += ARRAY_SIZE(cong_cnts);
3608 }
3609
3610 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
3611 if (!cnts->names)
7c16f477
KH		 3612 return -ENOMEM;
3613
e1f24a79
PP		 3614 cnts->offsets = kcalloc(num_counters,
3615 sizeof(cnts->offsets), GFP_KERNEL);
3616 if (!cnts->offsets)
7c16f477
KH		 3617 goto err_names;
3618
7c16f477
KH		 3619 return 0;
3620
3621err_names:
e1f24a79 3622 kfree(cnts->names);
7c16f477
KH		 3623 return -ENOMEM;
3624}
3625
e1f24a79
PP		 3626static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
3627 const char **names,
3628 size_t *offsets)
7c16f477
KH		 3629{
3630 int i;
3631 int j = 0;
3632
3633 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
3634 names[j] = basic_q_cnts[i].name;
3635 offsets[j] = basic_q_cnts[i].offset;
3636 }
3637
3638 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
3639 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
3640 names[j] = out_of_seq_q_cnts[i].name;
3641 offsets[j] = out_of_seq_q_cnts[i].offset;
3642 }
3643 }
3644
3645 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3646 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
3647 names[j] = retrans_q_cnts[i].name;
3648 offsets[j] = retrans_q_cnts[i].offset;
3649 }
3650 }
e1f24a79 3651
58dcb60a
PP		 3652 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
3653 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
3654 names[j] = extended_err_cnts[i].name;
3655 offsets[j] = extended_err_cnts[i].offset;
3656 }
3657 }
3658
e1f24a79
PP		 3659 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3660 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
3661 names[j] = cong_cnts[i].name;
3662 offsets[j] = cong_cnts[i].offset;
3663 }
3664 }
0837e86a
MB		 3665}
3666
e1f24a79 3667static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a
MB		 3668{
3669 int i;
3670 int ret;
3671
3672 for (i = 0; i < dev->num_ports; i++) {
7c16f477
KH		 3673 struct mlx5_ib_port *port = &dev->port[i];
3674
0837e86a 3675 ret = mlx5_core_alloc_q_counter(dev->mdev,
e1f24a79 3676 &port->cnts.set_id);
0837e86a
MB		 3677 if (ret) {
3678 mlx5_ib_warn(dev,
3679 "couldn't allocate queue counter for port %d, err %d\n",
3680 i + 1, ret);
3681 goto dealloc_counters;
3682 }
7c16f477 3683
e1f24a79 3684 ret = __mlx5_ib_alloc_counters(dev, &port->cnts);
7c16f477
KH		 3685 if (ret)
3686 goto dealloc_counters;
3687
e1f24a79
PP		 3688 mlx5_ib_fill_counters(dev, port->cnts.names,
3689 port->cnts.offsets);
0837e86a
MB		 3690 }
3691
3692 return 0;
3693
3694dealloc_counters:
3695 while (--i >= 0)
3696 mlx5_core_dealloc_q_counter(dev->mdev,
e1f24a79 3697 dev->port[i].cnts.set_id);
0837e86a
MB		 3698
3699 return ret;
3700}
3701
0ad17a8f
MB		 3702static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
3703 u8 port_num)
3704{
7c16f477
KH		 3705 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3706 struct mlx5_ib_port *port = &dev->port[port_num - 1];
0ad17a8f
MB		 3707
3708 /* We support only per port stats */
3709 if (port_num == 0)
3710 return NULL;
3711
e1f24a79
PP		 3712 return rdma_alloc_hw_stats_struct(port->cnts.names,
3713 port->cnts.num_q_counters +
3714 port->cnts.num_cong_counters,
0ad17a8f
MB		 3715 RDMA_HW_STATS_DEFAULT_LIFESPAN);
3716}
3717
e1f24a79
PP		 3718static int mlx5_ib_query_q_counters(struct mlx5_ib_dev *dev,
3719 struct mlx5_ib_port *port,
3720 struct rdma_hw_stats *stats)
0ad17a8f 3721{
0ad17a8f
MB		 3722 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3723 void *out;
3724 __be32 val;
e1f24a79 3725 int ret, i;
0ad17a8f 3726
1b9a07ee 3727 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 3728 if (!out)
3729 return -ENOMEM;
3730
3731 ret = mlx5_core_query_q_counter(dev->mdev,
e1f24a79 3732 port->cnts.set_id, 0,
0ad17a8f
MB		 3733 out, outlen);
3734 if (ret)
3735 goto free;
3736
e1f24a79
PP		 3737 for (i = 0; i < port->cnts.num_q_counters; i++) {
3738 val = *(__be32 *)(out + port->cnts.offsets[i]);
0ad17a8f
MB		 3739 stats->value[i] = (u64)be32_to_cpu(val);
3740 }
7c16f477 3741
0ad17a8f
MB		 3742free:
3743 kvfree(out);
e1f24a79
PP		 3744 return ret;
3745}
3746
e1f24a79
PP		 3747static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
3748 struct rdma_hw_stats *stats,
3749 u8 port_num, int index)
3750{
3751 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3752 struct mlx5_ib_port *port = &dev->port[port_num - 1];
3753 int ret, num_counters;
3754
3755 if (!stats)
3756 return -EINVAL;
3757
3758 ret = mlx5_ib_query_q_counters(dev, port, stats);
3759 if (ret)
3760 return ret;
3761 num_counters = port->cnts.num_q_counters;
3762
3763 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
71a0ff65
MD		 3764 ret = mlx5_lag_query_cong_counters(dev->mdev,
3765 stats->value +
3766 port->cnts.num_q_counters,
3767 port->cnts.num_cong_counters,
3768 port->cnts.offsets +
3769 port->cnts.num_q_counters);
e1f24a79
PP		 3770 if (ret)
3771 return ret;
3772 num_counters += port->cnts.num_cong_counters;
3773 }
3774
3775 return num_counters;
0ad17a8f
MB		 3776}
3777
8e959601
NV		 3778static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
3779{
3780 return mlx5_rdma_netdev_free(netdev);
3781}
3782
693dfd5a
ES		 3783static struct net_device*
3784mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
3785 u8 port_num,
3786 enum rdma_netdev_t type,
3787 const char *name,
3788 unsigned char name_assign_type,
3789 void (*setup)(struct net_device *))
3790{
8e959601
NV		 3791 struct net_device *netdev;
3792 struct rdma_netdev *rn;
3793
693dfd5a
ES		 3794 if (type != RDMA_NETDEV_IPOIB)
3795 return ERR_PTR(-EOPNOTSUPP);
3796
8e959601
NV		 3797 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
3798 name, setup);
3799 if (likely(!IS_ERR_OR_NULL(netdev))) {
3800 rn = netdev_priv(netdev);
3801 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
3802 }
3803 return netdev;
693dfd5a
ES		 3804}
3805
fe248c3a
MG		 3806static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
3807{
3808 if (!dev->delay_drop.dbg)
3809 return;
3810 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
3811 kfree(dev->delay_drop.dbg);
3812 dev->delay_drop.dbg = NULL;
3813}
3814
03404e8a
MG		 3815static void cancel_delay_drop(struct mlx5_ib_dev *dev)
3816{
3817 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
3818 return;
3819
3820 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 3821 delay_drop_debugfs_cleanup(dev);
3822}
3823
3824static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
3825 size_t count, loff_t *pos)
3826{
3827 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3828 char lbuf[20];
3829 int len;
3830
3831 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
3832 return simple_read_from_buffer(buf, count, pos, lbuf, len);
3833}
3834
3835static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
3836 size_t count, loff_t *pos)
3837{
3838 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3839 u32 timeout;
3840 u32 var;
3841
3842 if (kstrtouint_from_user(buf, count, 0, &var))
3843 return -EFAULT;
3844
3845 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
3846 1000);
3847 if (timeout != var)
3848 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
3849 timeout);
3850
3851 delay_drop->timeout = timeout;
3852
3853 return count;
3854}
3855
3856static const struct file_operations fops_delay_drop_timeout = {
3857 .owner = THIS_MODULE,
3858 .open = simple_open,
3859 .write = delay_drop_timeout_write,
3860 .read = delay_drop_timeout_read,
3861};
3862
3863static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
3864{
3865 struct mlx5_ib_dbg_delay_drop *dbg;
3866
3867 if (!mlx5_debugfs_root)
3868 return 0;
3869
3870 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
3871 if (!dbg)
3872 return -ENOMEM;
3873
cbafad87
SM		 3874 dev->delay_drop.dbg = dbg;
3875
fe248c3a
MG		 3876 dbg->dir_debugfs =
3877 debugfs_create_dir("delay_drop",
3878 dev->mdev->priv.dbg_root);
3879 if (!dbg->dir_debugfs)
cbafad87 3880 goto out_debugfs;
fe248c3a
MG		 3881
3882 dbg->events_cnt_debugfs =
3883 debugfs_create_atomic_t("num_timeout_events", 0400,
3884 dbg->dir_debugfs,
3885 &dev->delay_drop.events_cnt);
3886 if (!dbg->events_cnt_debugfs)
3887 goto out_debugfs;
3888
3889 dbg->rqs_cnt_debugfs =
3890 debugfs_create_atomic_t("num_rqs", 0400,
3891 dbg->dir_debugfs,
3892 &dev->delay_drop.rqs_cnt);
3893 if (!dbg->rqs_cnt_debugfs)
3894 goto out_debugfs;
3895
3896 dbg->timeout_debugfs =
3897 debugfs_create_file("timeout", 0600,
3898 dbg->dir_debugfs,
3899 &dev->delay_drop,
3900 &fops_delay_drop_timeout);
3901 if (!dbg->timeout_debugfs)
3902 goto out_debugfs;
3903
3904 return 0;
3905
3906out_debugfs:
3907 delay_drop_debugfs_cleanup(dev);
3908 return -ENOMEM;
03404e8a
MG		 3909}
3910
3911static void init_delay_drop(struct mlx5_ib_dev *dev)
3912{
3913 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
3914 return;
3915
3916 mutex_init(&dev->delay_drop.lock);
3917 dev->delay_drop.dev = dev;
3918 dev->delay_drop.activate = false;
3919 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
3920 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 3921 atomic_set(&dev->delay_drop.rqs_cnt, 0);
3922 atomic_set(&dev->delay_drop.events_cnt, 0);
3923
3924 if (delay_drop_debugfs_init(dev))
3925 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
03404e8a
MG		 3926}
3927
84305d71
LR		 3928static const struct cpumask *
3929mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
40b24403
SG		 3930{
3931 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3932
3933 return mlx5_get_vector_affinity(dev->mdev, comp_vector);
3934}
3935
9603b61d 3936static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
e126ba97 3937{
e126ba97 3938 struct mlx5_ib_dev *dev;
ebd61f68
AS		 3939 enum rdma_link_layer ll;
3940 int port_type_cap;
4babcf97 3941 const char *name;
e126ba97
EC		 3942 int err;
3943 int i;
3944
ebd61f68
AS		 3945 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3946 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3947
e126ba97
EC		 3948 printk_once(KERN_INFO "%s", mlx5_version);
3949
3950 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
3951 if (!dev)
9603b61d 3952 return NULL;
e126ba97 3953
9603b61d 3954 dev->mdev = mdev;
e126ba97 3955
0837e86a
MB		 3956 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
3957 GFP_KERNEL);
3958 if (!dev->port)
3959 goto err_dealloc;
3960
fc24fc5e 3961 rwlock_init(&dev->roce.netdev_lock);
e126ba97
EC		 3962 err = get_port_caps(dev);
3963 if (err)
0837e86a 3964 goto err_free_port;
e126ba97 3965
1b5daf11
MD		 3966 if (mlx5_use_mad_ifc(dev))
3967 get_ext_port_caps(dev);
e126ba97 3968
4babcf97
AH		 3969 if (!mlx5_lag_is_active(mdev))
3970 name = "mlx5_%d";
3971 else
3972 name = "mlx5_bond_%d";
3973
3974 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
e126ba97
EC		 3975 dev->ib_dev.owner = THIS_MODULE;
3976 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 3977 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
938fe83c 3978 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
e126ba97 3979 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 3980 dev->ib_dev.num_comp_vectors =
3981 dev->mdev->priv.eq_table.num_comp_vectors;
9b0c289e 3982 dev->ib_dev.dev.parent = &mdev->pdev->dev;
e126ba97
EC		 3983
3984 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
3985 dev->ib_dev.uverbs_cmd_mask =
3986 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
3987 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
3988 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
3989 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
3990 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 3991 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
3992 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 3993 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 3994 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 3995 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
3996 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
3997 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
3998 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
3999 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
4000 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
4001 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
4002 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
4003 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
4004 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
4005 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
4006 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
4007 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
4008 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
4009 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
4010 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
4011 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 4012 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 4013 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
4014 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349 4015 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
b0e9df6d
YC		 4016 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
4017 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
e126ba97
EC		 4018
4019 dev->ib_dev.query_device = mlx5_ib_query_device;
4020 dev->ib_dev.query_port = mlx5_ib_query_port;
ebd61f68 4021 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
fc24fc5e
AS		 4022 if (ll == IB_LINK_LAYER_ETHERNET)
4023 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
e126ba97 4024 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 4025 dev->ib_dev.add_gid = mlx5_ib_add_gid;
4026 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 4027 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
4028 dev->ib_dev.modify_device = mlx5_ib_modify_device;
4029 dev->ib_dev.modify_port = mlx5_ib_modify_port;
4030 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
4031 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
4032 dev->ib_dev.mmap = mlx5_ib_mmap;
4033 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
4034 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
4035 dev->ib_dev.create_ah = mlx5_ib_create_ah;
4036 dev->ib_dev.query_ah = mlx5_ib_query_ah;
4037 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
4038 dev->ib_dev.create_srq = mlx5_ib_create_srq;
4039 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
4040 dev->ib_dev.query_srq = mlx5_ib_query_srq;
4041 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
4042 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
4043 dev->ib_dev.create_qp = mlx5_ib_create_qp;
4044 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
4045 dev->ib_dev.query_qp = mlx5_ib_query_qp;
4046 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
4047 dev->ib_dev.post_send = mlx5_ib_post_send;
4048 dev->ib_dev.post_recv = mlx5_ib_post_recv;
4049 dev->ib_dev.create_cq = mlx5_ib_create_cq;
4050 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
4051 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
4052 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
4053 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
4054 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
4055 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
4056 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 4057 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 4058 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
4059 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
4060 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
4061 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 4062 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 4063 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 4064 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
7738613e 4065 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
c7342823 4066 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
40b24403 4067 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
8e959601 4068 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
022d038a 4069 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
8e959601 4070
eff901d3
EC		 4071 if (mlx5_core_is_pf(mdev)) {
4072 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
4073 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
4074 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
4075 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
4076 }
e126ba97 4077
7c2344c3
MG		 4078 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
4079
938fe83c 4080 mlx5_ib_internal_fill_odp_caps(dev);
8cdd312c 4081
6e8484c5
MG		 4082 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
4083
d2370e0a
MB		 4084 if (MLX5_CAP_GEN(mdev, imaicl)) {
4085 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
4086 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
4087 dev->ib_dev.uverbs_cmd_mask |=
4088 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
4089 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
4090 }
4091
7c16f477 4092 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
0ad17a8f
MB		 4093 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
4094 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
4095 }
4096
938fe83c 4097 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 4098 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
4099 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
4100 dev->ib_dev.uverbs_cmd_mask |=
4101 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
4102 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
4103 }
4104
81e30880
YH		 4105 dev->ib_dev.create_flow = mlx5_ib_create_flow;
4106 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
4107 dev->ib_dev.uverbs_ex_cmd_mask |=
4108 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
4109 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
4110
048ccca8 4111 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
038d2ef8 4112 IB_LINK_LAYER_ETHERNET) {
79b20a6c
YH		 4113 dev->ib_dev.create_wq = mlx5_ib_create_wq;
4114 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
4115 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
c5f90929
YH		 4116 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
4117 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
038d2ef8 4118 dev->ib_dev.uverbs_ex_cmd_mask |=
79b20a6c
YH		 4119 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
4120 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
c5f90929
YH		 4121 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
4122 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
4123 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
038d2ef8 4124 }
e126ba97
EC		 4125 err = init_node_data(dev);
4126 if (err)
90be7c8a 4127 goto err_free_port;
e126ba97 4128
038d2ef8 4129 mutex_init(&dev->flow_db.lock);
e126ba97 4130 mutex_init(&dev->cap_mask_mutex);
89ea94a7
MG		 4131 INIT_LIST_HEAD(&dev->qp_list);
4132 spin_lock_init(&dev->reset_flow_resource_lock);
e126ba97 4133
fc24fc5e 4134 if (ll == IB_LINK_LAYER_ETHERNET) {
45f95acd 4135 err = mlx5_enable_eth(dev);
fc24fc5e 4136 if (err)
90be7c8a 4137 goto err_free_port;
fd65f1b8 4138 dev->roce.last_port_state = IB_PORT_DOWN;
fc24fc5e
AS		 4139 }
4140
e126ba97
EC		 4141 err = create_dev_resources(&dev->devr);
4142 if (err)
45f95acd 4143 goto err_disable_eth;
e126ba97 4144
6aec21f6 4145 err = mlx5_ib_odp_init_one(dev);
281d1a92 4146 if (err)
e126ba97
EC		 4147 goto err_rsrc;
4148
45bded2c 4149 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
e1f24a79 4150 err = mlx5_ib_alloc_counters(dev);
45bded2c
KH		 4151 if (err)
4152 goto err_odp;
4153 }
6aec21f6 4154
4a2da0b8
PP		 4155 err = mlx5_ib_init_cong_debugfs(dev);
4156 if (err)
4157 goto err_cnt;
4158
5fe9dec0
EC		 4159 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
4160 if (!dev->mdev->priv.uar)
4a2da0b8 4161 goto err_cong;
5fe9dec0
EC		 4162
4163 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4164 if (err)
4165 goto err_uar_page;
4166
4167 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4168 if (err)
4169 goto err_bfreg;
4170
0837e86a
MB		 4171 err = ib_register_device(&dev->ib_dev, NULL);
4172 if (err)
5fe9dec0 4173 goto err_fp_bfreg;
0837e86a 4174
e126ba97
EC		 4175 err = create_umr_res(dev);
4176 if (err)
4177 goto err_dev;
4178
03404e8a
MG		 4179 init_delay_drop(dev);
4180
e126ba97 4181 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 4182 err = device_create_file(&dev->ib_dev.dev,
4183 mlx5_class_attributes[i]);
4184 if (err)
03404e8a 4185 goto err_delay_drop;
e126ba97
EC		 4186 }
4187
c85023e1
HN		 4188 if ((MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
4189 MLX5_CAP_GEN(mdev, disable_local_lb))
4190 mutex_init(&dev->lb_mutex);
4191
e126ba97
EC		 4192 dev->ib_active = true;
4193
9603b61d 4194 return dev;
e126ba97 4195
03404e8a
MG		 4196err_delay_drop:
4197 cancel_delay_drop(dev);
e126ba97
EC		 4198 destroy_umrc_res(dev);
4199
4200err_dev:
4201 ib_unregister_device(&dev->ib_dev);
4202
5fe9dec0
EC		 4203err_fp_bfreg:
4204 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4205
4206err_bfreg:
4207 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4208
4209err_uar_page:
4210 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4211
4a2da0b8 4212err_cong:
e19cd282
PP		 4213 mlx5_ib_cleanup_cong_debugfs(dev);
4214err_cnt:
45bded2c 4215 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
e1f24a79 4216 mlx5_ib_dealloc_counters(dev);
0837e86a 4217
6aec21f6
HE		 4218err_odp:
4219 mlx5_ib_odp_remove_one(dev);
4220
e126ba97
EC		 4221err_rsrc:
4222 destroy_dev_resources(&dev->devr);
4223
45f95acd 4224err_disable_eth:
5ec8c83e 4225 if (ll == IB_LINK_LAYER_ETHERNET) {
45f95acd 4226 mlx5_disable_eth(dev);
d012f5d6 4227 mlx5_remove_netdev_notifier(dev);
5ec8c83e 4228 }
fc24fc5e 4229
0837e86a
MB		 4230err_free_port:
4231 kfree(dev->port);
4232
9603b61d 4233err_dealloc:
e126ba97
EC		 4234 ib_dealloc_device((struct ib_device *)dev);
4235
9603b61d 4236 return NULL;
e126ba97
EC		 4237}
4238
9603b61d 4239static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 4240{
9603b61d 4241 struct mlx5_ib_dev *dev = context;
fc24fc5e 4242 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
6aec21f6 4243
03404e8a 4244 cancel_delay_drop(dev);
d012f5d6 4245 mlx5_remove_netdev_notifier(dev);
e126ba97 4246 ib_unregister_device(&dev->ib_dev);
5fe9dec0
EC		 4247 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4248 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4249 mlx5_put_uars_page(dev->mdev, mdev->priv.uar);
4a2da0b8 4250 mlx5_ib_cleanup_cong_debugfs(dev);
45bded2c 4251 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
e1f24a79 4252 mlx5_ib_dealloc_counters(dev);
eefd56e5 4253 destroy_umrc_res(dev);
6aec21f6 4254 mlx5_ib_odp_remove_one(dev);
e126ba97 4255 destroy_dev_resources(&dev->devr);
fc24fc5e 4256 if (ll == IB_LINK_LAYER_ETHERNET)
45f95acd 4257 mlx5_disable_eth(dev);
0837e86a 4258 kfree(dev->port);
e126ba97
EC		 4259 ib_dealloc_device(&dev->ib_dev);
4260}
4261
9603b61d
JM		 4262static struct mlx5_interface mlx5_ib_interface = {
4263 .add = mlx5_ib_add,
4264 .remove = mlx5_ib_remove,
4265 .event = mlx5_ib_event,
d9aaed83
AK		 4266#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4267 .pfault = mlx5_ib_pfault,
4268#endif
64613d94 4269 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 4270};
4271
4272static int __init mlx5_ib_init(void)
4273{
6aec21f6
HE		 4274 int err;
4275
81713d37 4276 mlx5_ib_odp_init();
9603b61d 4277
6aec21f6 4278 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 4279
6aec21f6 4280 return err;
e126ba97
EC		 4281}
4282
4283static void __exit mlx5_ib_cleanup(void)
4284{
9603b61d 4285 mlx5_unregister_interface(&mlx5_ib_interface);
e126ba97
EC		 4286}
4287
4288module_init(mlx5_ib_init);
4289module_exit(mlx5_ib_cleanup);
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