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IB/mlx5: Refactor code for counters allocation
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
24da0016 41#include <linux/bitmap.h>
37aa5c36
GL		 42#if defined(CONFIG_X86)
43#include <asm/pat.h>
44#endif
e126ba97 45#include <linux/sched.h>
6e84f315 46#include <linux/sched/mm.h>
0881e7bd 47#include <linux/sched/task.h>
7c2344c3 48#include <linux/delay.h>
e126ba97 49#include <rdma/ib_user_verbs.h>
3f89a643 50#include <rdma/ib_addr.h>
2811ba51 51#include <rdma/ib_cache.h>
ada68c31 52#include <linux/mlx5/port.h>
1b5daf11 53#include <linux/mlx5/vport.h>
72c7fe90 54#include <linux/mlx5/fs.h>
cecae747 55#include <linux/mlx5/eswitch.h>
7c2344c3 56#include <linux/list.h>
e126ba97
EC		 57#include <rdma/ib_smi.h>
58#include <rdma/ib_umem.h>
038d2ef8
MG		 59#include <linux/in.h>
60#include <linux/etherdevice.h>
e126ba97 61#include "mlx5_ib.h"
fc385b7a 62#include "ib_rep.h"
e1f24a79 63#include "cmd.h"
f3da6577 64#include "srq.h"
3346c487 65#include <linux/mlx5/fs_helpers.h>
c6475a0b 66#include <linux/mlx5/accel.h>
8c84660b 67#include <rdma/uverbs_std_types.h>
c6475a0b
AY		 68#include <rdma/mlx5_user_ioctl_verbs.h>
69#include <rdma/mlx5_user_ioctl_cmds.h>
8c84660b
MB		 70
71#define UVERBS_MODULE_NAME mlx5_ib
72#include <rdma/uverbs_named_ioctl.h>
e126ba97
EC		 73
74#define DRIVER_NAME "mlx5_ib"
b359911d 75#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 76
77MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
78MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
79MODULE_LICENSE("Dual BSD/GPL");
e126ba97 80
e126ba97
EC		 81static char mlx5_version[] =
82 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 83 DRIVER_VERSION "\n";
e126ba97 84
d69a24e0
DJ		 85struct mlx5_ib_event_work {
86 struct work_struct work;
df097a27
SM		 87 union {
88 struct mlx5_ib_dev *dev;
89 struct mlx5_ib_multiport_info *mpi;
90 };
91 bool is_slave;
134e9349 92 unsigned int event;
df097a27 93 void *param;
d69a24e0
DJ		 94};
95
da7525d2
EBE		 96enum {
97 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
98};
99
d69a24e0 100static struct workqueue_struct *mlx5_ib_event_wq;
32f69e4b
DJ		 101static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
102static LIST_HEAD(mlx5_ib_dev_list);
103/*
104 * This mutex should be held when accessing either of the above lists
105 */
106static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
107
c44ef998
IL		 108/* We can't use an array for xlt_emergency_page because dma_map_single
109 * doesn't work on kernel modules memory
110 */
111static unsigned long xlt_emergency_page;
112static struct mutex xlt_emergency_page_mutex;
113
32f69e4b
DJ		 114struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
115{
116 struct mlx5_ib_dev *dev;
117
118 mutex_lock(&mlx5_ib_multiport_mutex);
119 dev = mpi->ibdev;
120 mutex_unlock(&mlx5_ib_multiport_mutex);
121 return dev;
122}
123
1b5daf11 124static enum rdma_link_layer
ebd61f68 125mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 126{
ebd61f68 127 switch (port_type_cap) {
1b5daf11
MD		 128 case MLX5_CAP_PORT_TYPE_IB:
129 return IB_LINK_LAYER_INFINIBAND;
130 case MLX5_CAP_PORT_TYPE_ETH:
131 return IB_LINK_LAYER_ETHERNET;
132 default:
133 return IB_LINK_LAYER_UNSPECIFIED;
134 }
135}
136
ebd61f68
AS		 137static enum rdma_link_layer
138mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
139{
140 struct mlx5_ib_dev *dev = to_mdev(device);
141 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
142
143 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
144}
145
fd65f1b8
MS		 146static int get_port_state(struct ib_device *ibdev,
147 u8 port_num,
148 enum ib_port_state *state)
149{
150 struct ib_port_attr attr;
151 int ret;
152
153 memset(&attr, 0, sizeof(attr));
3023a1e9 154 ret = ibdev->ops.query_port(ibdev, port_num, &attr);
fd65f1b8
MS		 155 if (!ret)
156 *state = attr.state;
157 return ret;
158}
159
35b0aa67
MB		 160static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
161 struct net_device *ndev,
162 u8 *port_num)
163{
164 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
165 struct net_device *rep_ndev;
166 struct mlx5_ib_port *port;
167 int i;
168
169 for (i = 0; i < dev->num_ports; i++) {
170 port = &dev->port[i];
171 if (!port->rep)
172 continue;
173
174 read_lock(&port->roce.netdev_lock);
175 rep_ndev = mlx5_ib_get_rep_netdev(esw,
176 port->rep->vport);
177 if (rep_ndev == ndev) {
178 read_unlock(&port->roce.netdev_lock);
179 *port_num = i + 1;
180 return &port->roce;
181 }
182 read_unlock(&port->roce.netdev_lock);
183 }
184
185 return NULL;
186}
187
fc24fc5e
AS		 188static int mlx5_netdev_event(struct notifier_block *this,
189 unsigned long event, void *ptr)
190{
7fd8aefb 191 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
fc24fc5e 192 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
7fd8aefb
DJ		 193 u8 port_num = roce->native_port_num;
194 struct mlx5_core_dev *mdev;
195 struct mlx5_ib_dev *ibdev;
196
197 ibdev = roce->dev;
32f69e4b
DJ		 198 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
199 if (!mdev)
200 return NOTIFY_DONE;
fc24fc5e 201
5ec8c83e
AH		 202 switch (event) {
203 case NETDEV_REGISTER:
35b0aa67
MB		 204 /* Should already be registered during the load */
205 if (ibdev->is_rep)
206 break;
7fd8aefb 207 write_lock(&roce->netdev_lock);
dce45af5 208 if (ndev->dev.parent == mdev->device)
842a9c83 209 roce->netdev = ndev;
7fd8aefb 210 write_unlock(&roce->netdev_lock);
5ec8c83e 211 break;
fc24fc5e 212
842a9c83 213 case NETDEV_UNREGISTER:
35b0aa67 214 /* In case of reps, ib device goes away before the netdevs */
842a9c83
OG		 215 write_lock(&roce->netdev_lock);
216 if (roce->netdev == ndev)
217 roce->netdev = NULL;
218 write_unlock(&roce->netdev_lock);
219 break;
220
fd65f1b8 221 case NETDEV_CHANGE:
5ec8c83e 222 case NETDEV_UP:
88621dfe 223 case NETDEV_DOWN: {
7fd8aefb 224 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe
AH		 225 struct net_device *upper = NULL;
226
227 if (lag_ndev) {
228 upper = netdev_master_upper_dev_get(lag_ndev);
229 dev_put(lag_ndev);
230 }
231
35b0aa67
MB		 232 if (ibdev->is_rep)
233 roce = mlx5_get_rep_roce(ibdev, ndev, &port_num);
234 if (!roce)
235 return NOTIFY_DONE;
7fd8aefb 236 if ((upper == ndev || (!upper && ndev == roce->netdev))
88621dfe 237 && ibdev->ib_active) {
626bc02d 238 struct ib_event ibev = { };
fd65f1b8 239 enum ib_port_state port_state;
5ec8c83e 240
7fd8aefb
DJ		 241 if (get_port_state(&ibdev->ib_dev, port_num,
242 &port_state))
243 goto done;
fd65f1b8 244
7fd8aefb
DJ		 245 if (roce->last_port_state == port_state)
246 goto done;
fd65f1b8 247
7fd8aefb 248 roce->last_port_state = port_state;
5ec8c83e 249 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 250 if (port_state == IB_PORT_DOWN)
251 ibev.event = IB_EVENT_PORT_ERR;
252 else if (port_state == IB_PORT_ACTIVE)
253 ibev.event = IB_EVENT_PORT_ACTIVE;
254 else
7fd8aefb 255 goto done;
fd65f1b8 256
7fd8aefb 257 ibev.element.port_num = port_num;
5ec8c83e
AH		 258 ib_dispatch_event(&ibev);
259 }
260 break;
88621dfe 261 }
fc24fc5e 262
5ec8c83e
AH		 263 default:
264 break;
265 }
7fd8aefb 266done:
32f69e4b 267 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 268 return NOTIFY_DONE;
269}
270
271static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
272 u8 port_num)
273{
274 struct mlx5_ib_dev *ibdev = to_mdev(device);
275 struct net_device *ndev;
32f69e4b
DJ		 276 struct mlx5_core_dev *mdev;
277
278 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
279 if (!mdev)
280 return NULL;
fc24fc5e 281
32f69e4b 282 ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe 283 if (ndev)
32f69e4b 284 goto out;
88621dfe 285
fc24fc5e
AS		 286 /* Ensure ndev does not disappear before we invoke dev_hold()
287 */
95579e78
MB		 288 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock);
289 ndev = ibdev->port[port_num - 1].roce.netdev;
fc24fc5e
AS		 290 if (ndev)
291 dev_hold(ndev);
95579e78 292 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock);
fc24fc5e 293
32f69e4b
DJ		 294out:
295 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 296 return ndev;
297}
298
32f69e4b
DJ		 299struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
300 u8 ib_port_num,
301 u8 *native_port_num)
302{
303 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
304 ib_port_num);
305 struct mlx5_core_dev *mdev = NULL;
306 struct mlx5_ib_multiport_info *mpi;
307 struct mlx5_ib_port *port;
308
210b1f78
MB		 309 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
310 ll != IB_LINK_LAYER_ETHERNET) {
311 if (native_port_num)
312 *native_port_num = ib_port_num;
313 return ibdev->mdev;
314 }
315
32f69e4b
DJ		 316 if (native_port_num)
317 *native_port_num = 1;
318
32f69e4b
DJ		 319 port = &ibdev->port[ib_port_num - 1];
320 if (!port)
321 return NULL;
322
323 spin_lock(&port->mp.mpi_lock);
324 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
325 if (mpi && !mpi->unaffiliate) {
326 mdev = mpi->mdev;
327 /* If it's the master no need to refcount, it'll exist
328 * as long as the ib_dev exists.
329 */
330 if (!mpi->is_master)
331 mpi->mdev_refcnt++;
332 }
333 spin_unlock(&port->mp.mpi_lock);
334
335 return mdev;
336}
337
338void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
339{
340 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
341 port_num);
342 struct mlx5_ib_multiport_info *mpi;
343 struct mlx5_ib_port *port;
344
345 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
346 return;
347
348 port = &ibdev->port[port_num - 1];
349
350 spin_lock(&port->mp.mpi_lock);
351 mpi = ibdev->port[port_num - 1].mp.mpi;
352 if (mpi->is_master)
353 goto out;
354
355 mpi->mdev_refcnt--;
356 if (mpi->unaffiliate)
357 complete(&mpi->unref_comp);
358out:
359 spin_unlock(&port->mp.mpi_lock);
360}
361
08e8676f
AL		 362static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, u8 *active_speed,
363 u8 *active_width)
f1b65df5
NO		 364{
365 switch (eth_proto_oper) {
366 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
367 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
368 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
369 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
370 *active_width = IB_WIDTH_1X;
371 *active_speed = IB_SPEED_SDR;
372 break;
373 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
374 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
375 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
376 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
377 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
378 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
379 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
380 *active_width = IB_WIDTH_1X;
381 *active_speed = IB_SPEED_QDR;
382 break;
383 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
384 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
385 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
386 *active_width = IB_WIDTH_1X;
387 *active_speed = IB_SPEED_EDR;
388 break;
389 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
390 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
391 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
392 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
393 *active_width = IB_WIDTH_4X;
394 *active_speed = IB_SPEED_QDR;
395 break;
396 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
397 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
398 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
399 *active_width = IB_WIDTH_1X;
400 *active_speed = IB_SPEED_HDR;
401 break;
402 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
403 *active_width = IB_WIDTH_4X;
404 *active_speed = IB_SPEED_FDR;
405 break;
406 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
407 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
408 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
409 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
410 *active_width = IB_WIDTH_4X;
411 *active_speed = IB_SPEED_EDR;
412 break;
413 default:
414 return -EINVAL;
415 }
416
417 return 0;
418}
419
08e8676f
AL		 420static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed,
421 u8 *active_width)
422{
423 switch (eth_proto_oper) {
424 case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
425 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
426 *active_width = IB_WIDTH_1X;
427 *active_speed = IB_SPEED_SDR;
428 break;
429 case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
430 *active_width = IB_WIDTH_1X;
431 *active_speed = IB_SPEED_DDR;
432 break;
433 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
434 *active_width = IB_WIDTH_1X;
435 *active_speed = IB_SPEED_QDR;
436 break;
437 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
438 *active_width = IB_WIDTH_4X;
439 *active_speed = IB_SPEED_QDR;
440 break;
441 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
442 *active_width = IB_WIDTH_1X;
443 *active_speed = IB_SPEED_EDR;
444 break;
445 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
cd272875
AL		 446 *active_width = IB_WIDTH_2X;
447 *active_speed = IB_SPEED_EDR;
448 break;
08e8676f
AL		 449 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
450 *active_width = IB_WIDTH_1X;
451 *active_speed = IB_SPEED_HDR;
452 break;
cd272875
AL		 453 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
454 *active_width = IB_WIDTH_4X;
455 *active_speed = IB_SPEED_EDR;
456 break;
08e8676f
AL		 457 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
458 *active_width = IB_WIDTH_2X;
459 *active_speed = IB_SPEED_HDR;
460 break;
461 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
462 *active_width = IB_WIDTH_4X;
463 *active_speed = IB_SPEED_HDR;
464 break;
465 default:
466 return -EINVAL;
467 }
468
469 return 0;
470}
471
472static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
473 u8 *active_width, bool ext)
474{
475 return ext ?
476 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
477 active_width) :
478 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
479 active_width);
480}
481
095b0927
IT		 482static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
483 struct ib_port_attr *props)
3f89a643
AS		 484{
485 struct mlx5_ib_dev *dev = to_mdev(device);
bc4e12ff 486 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
da005f9f 487 struct mlx5_core_dev *mdev;
88621dfe 488 struct net_device *ndev, *upper;
3f89a643 489 enum ib_mtu ndev_ib_mtu;
b3cbd6f0 490 bool put_mdev = true;
c876a1b7 491 u16 qkey_viol_cntr;
f1b65df5 492 u32 eth_prot_oper;
b3cbd6f0 493 u8 mdev_port_num;
08e8676f 494 bool ext;
095b0927 495 int err;
3f89a643 496
b3cbd6f0
DJ		 497 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
498 if (!mdev) {
499 /* This means the port isn't affiliated yet. Get the
500 * info for the master port instead.
501 */
502 put_mdev = false;
503 mdev = dev->mdev;
504 mdev_port_num = 1;
505 port_num = 1;
506 }
507
f1b65df5
NO		 508 /* Possible bad flows are checked before filling out props so in case
509 * of an error it will still be zeroed out.
26628e2d 510 * Use native port in case of reps
50f22fd8 511 */
26628e2d
MB		 512 if (dev->is_rep)
513 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
514 1);
515 else
516 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
517 mdev_port_num);
095b0927 518 if (err)
b3cbd6f0 519 goto out;
08e8676f
AL		 520 ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet);
521 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
f1b65df5 522
7672ed33
HL		 523 props->active_width = IB_WIDTH_4X;
524 props->active_speed = IB_SPEED_QDR;
525
f1b65df5 526 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
08e8676f 527 &props->active_width, ext);
3f89a643 528
2f944c0f
JG		 529 props->port_cap_flags |= IB_PORT_CM_SUP;
530 props->ip_gids = true;
3f89a643
AS		 531
532 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
533 roce_address_table_size);
534 props->max_mtu = IB_MTU_4096;
535 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
536 props->pkey_tbl_len = 1;
537 props->state = IB_PORT_DOWN;
538 props->phys_state = 3;
539
b3cbd6f0 540 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
c876a1b7 541 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643 542
b3cbd6f0
DJ		 543 /* If this is a stub query for an unaffiliated port stop here */
544 if (!put_mdev)
545 goto out;
546
3f89a643
AS		 547 ndev = mlx5_ib_get_netdev(device, port_num);
548 if (!ndev)
b3cbd6f0 549 goto out;
3f89a643 550
7c34ec19 551 if (dev->lag_active) {
88621dfe
AH		 552 rcu_read_lock();
553 upper = netdev_master_upper_dev_get_rcu(ndev);
554 if (upper) {
555 dev_put(ndev);
556 ndev = upper;
557 dev_hold(ndev);
558 }
559 rcu_read_unlock();
560 }
561
3f89a643
AS		 562 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
563 props->state = IB_PORT_ACTIVE;
564 props->phys_state = 5;
565 }
566
567 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
568
569 dev_put(ndev);
570
571 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
b3cbd6f0
DJ		 572out:
573 if (put_mdev)
574 mlx5_ib_put_native_port_mdev(dev, port_num);
575 return err;
3f89a643
AS		 576}
577
095b0927
IT		 578static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
579 unsigned int index, const union ib_gid *gid,
580 const struct ib_gid_attr *attr)
3cca2606 581{
095b0927 582 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
a70c0739 583 u16 vlan_id = 0xffff;
095b0927
IT		 584 u8 roce_version = 0;
585 u8 roce_l3_type = 0;
095b0927 586 u8 mac[ETH_ALEN];
a70c0739 587 int ret;
095b0927
IT		 588
589 if (gid) {
590 gid_type = attr->gid_type;
a70c0739
PP		 591 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
592 if (ret)
593 return ret;
3cca2606
AS		 594 }
595
095b0927 596 switch (gid_type) {
3cca2606 597 case IB_GID_TYPE_IB:
095b0927 598 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 599 break;
600 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 601 roce_version = MLX5_ROCE_VERSION_2;
602 if (ipv6_addr_v4mapped((void *)gid))
603 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
604 else
605 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 606 break;
607
608 default:
095b0927 609 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 610 }
611
095b0927 612 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
cf34e1fe 613 roce_l3_type, gid->raw, mac,
a70c0739 614 vlan_id < VLAN_CFI_MASK, vlan_id,
cf34e1fe 615 port_num);
3cca2606
AS		 616}
617
f4df9a7c 618static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
3cca2606
AS		 619 __always_unused void **context)
620{
414448d2 621 return set_roce_addr(to_mdev(attr->device), attr->port_num,
f4df9a7c 622 attr->index, &attr->gid, attr);
3cca2606
AS		 623}
624
414448d2
PP		 625static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
626 __always_unused void **context)
3cca2606 627{
414448d2
PP		 628 return set_roce_addr(to_mdev(attr->device), attr->port_num,
629 attr->index, NULL, NULL);
3cca2606
AS		 630}
631
47ec3866
PP		 632__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
633 const struct ib_gid_attr *attr)
2811ba51 634{
47ec3866 635 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
2811ba51
AS		 636 return 0;
637
638 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
639}
640
1b5daf11
MD		 641static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
642{
7fae6655
NO		 643 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
644 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
645 return 0;
1b5daf11
MD		 646}
647
648enum {
649 MLX5_VPORT_ACCESS_METHOD_MAD,
650 MLX5_VPORT_ACCESS_METHOD_HCA,
651 MLX5_VPORT_ACCESS_METHOD_NIC,
652};
653
654static int mlx5_get_vport_access_method(struct ib_device *ibdev)
655{
656 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
657 return MLX5_VPORT_ACCESS_METHOD_MAD;
658
ebd61f68 659 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 660 IB_LINK_LAYER_ETHERNET)
661 return MLX5_VPORT_ACCESS_METHOD_NIC;
662
663 return MLX5_VPORT_ACCESS_METHOD_HCA;
664}
665
da7525d2 666static void get_atomic_caps(struct mlx5_ib_dev *dev,
776a3906 667 u8 atomic_size_qp,
da7525d2
EBE		 668 struct ib_device_attr *props)
669{
670 u8 tmp;
671 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
da7525d2 672 u8 atomic_req_8B_endianness_mode =
bd10838a 673 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 674
675 /* Check if HW supports 8 bytes standard atomic operations and capable
676 * of host endianness respond
677 */
678 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
679 if (((atomic_operations & tmp) == tmp) &&
680 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
681 (atomic_req_8B_endianness_mode)) {
682 props->atomic_cap = IB_ATOMIC_HCA;
683 } else {
684 props->atomic_cap = IB_ATOMIC_NONE;
685 }
686}
687
776a3906
MS		 688static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
689 struct ib_device_attr *props)
690{
691 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
692
693 get_atomic_caps(dev, atomic_size_qp, props);
694}
695
696static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
697 struct ib_device_attr *props)
698{
699 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
700
701 get_atomic_caps(dev, atomic_size_qp, props);
702}
703
704bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
705{
706 struct ib_device_attr props = {};
707
708 get_atomic_caps_dc(dev, &props);
709 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
710}
1b5daf11
MD		 711static int mlx5_query_system_image_guid(struct ib_device *ibdev,
712 __be64 *sys_image_guid)
713{
714 struct mlx5_ib_dev *dev = to_mdev(ibdev);
715 struct mlx5_core_dev *mdev = dev->mdev;
716 u64 tmp;
717 int err;
718
719 switch (mlx5_get_vport_access_method(ibdev)) {
720 case MLX5_VPORT_ACCESS_METHOD_MAD:
721 return mlx5_query_mad_ifc_system_image_guid(ibdev,
722 sys_image_guid);
723
724 case MLX5_VPORT_ACCESS_METHOD_HCA:
725 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 726 break;
727
728 case MLX5_VPORT_ACCESS_METHOD_NIC:
729 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
730 break;
1b5daf11
MD		 731
732 default:
733 return -EINVAL;
734 }
3f89a643
AS		 735
736 if (!err)
737 *sys_image_guid = cpu_to_be64(tmp);
738
739 return err;
740
1b5daf11
MD		 741}
742
743static int mlx5_query_max_pkeys(struct ib_device *ibdev,
744 u16 *max_pkeys)
745{
746 struct mlx5_ib_dev *dev = to_mdev(ibdev);
747 struct mlx5_core_dev *mdev = dev->mdev;
748
749 switch (mlx5_get_vport_access_method(ibdev)) {
750 case MLX5_VPORT_ACCESS_METHOD_MAD:
751 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
752
753 case MLX5_VPORT_ACCESS_METHOD_HCA:
754 case MLX5_VPORT_ACCESS_METHOD_NIC:
755 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
756 pkey_table_size));
757 return 0;
758
759 default:
760 return -EINVAL;
761 }
762}
763
764static int mlx5_query_vendor_id(struct ib_device *ibdev,
765 u32 *vendor_id)
766{
767 struct mlx5_ib_dev *dev = to_mdev(ibdev);
768
769 switch (mlx5_get_vport_access_method(ibdev)) {
770 case MLX5_VPORT_ACCESS_METHOD_MAD:
771 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
772
773 case MLX5_VPORT_ACCESS_METHOD_HCA:
774 case MLX5_VPORT_ACCESS_METHOD_NIC:
775 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
776
777 default:
778 return -EINVAL;
779 }
780}
781
782static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
783 __be64 *node_guid)
784{
785 u64 tmp;
786 int err;
787
788 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
789 case MLX5_VPORT_ACCESS_METHOD_MAD:
790 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
791
792 case MLX5_VPORT_ACCESS_METHOD_HCA:
793 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 794 break;
795
796 case MLX5_VPORT_ACCESS_METHOD_NIC:
797 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
798 break;
1b5daf11
MD		 799
800 default:
801 return -EINVAL;
802 }
3f89a643
AS		 803
804 if (!err)
805 *node_guid = cpu_to_be64(tmp);
806
807 return err;
1b5daf11
MD		 808}
809
810struct mlx5_reg_node_desc {
bd99fdea 811 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 812};
813
814static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
815{
816 struct mlx5_reg_node_desc in;
817
818 if (mlx5_use_mad_ifc(dev))
819 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
820
821 memset(&in, 0, sizeof(in));
822
823 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
824 sizeof(struct mlx5_reg_node_desc),
825 MLX5_REG_NODE_DESC, 0, 0);
826}
827
e126ba97 828static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 829 struct ib_device_attr *props,
830 struct ib_udata *uhw)
e126ba97
EC		 831{
832 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 833 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 834 int err = -ENOMEM;
288c01b7 835 int max_sq_desc;
e126ba97
EC		 836 int max_rq_sg;
837 int max_sq_sg;
e0238a6a 838 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
85c7c014 839 bool raw_support = !mlx5_core_mp_enabled(mdev);
402ca536
BW		 840 struct mlx5_ib_query_device_resp resp = {};
841 size_t resp_len;
842 u64 max_tso;
e126ba97 843
402ca536
BW		 844 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
845 if (uhw->outlen && uhw->outlen < resp_len)
846 return -EINVAL;
847 else
848 resp.response_length = resp_len;
849
850 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 851 return -EINVAL;
852
1b5daf11
MD		 853 memset(props, 0, sizeof(*props));
854 err = mlx5_query_system_image_guid(ibdev,
855 &props->sys_image_guid);
856 if (err)
857 return err;
e126ba97 858
1b5daf11 859 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 860 if (err)
1b5daf11 861 return err;
e126ba97 862
1b5daf11
MD		 863 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
864 if (err)
865 return err;
e126ba97 866
9603b61d
JM		 867 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
868 (fw_rev_min(dev->mdev) << 16) |
869 fw_rev_sub(dev->mdev);
e126ba97
EC		 870 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
871 IB_DEVICE_PORT_ACTIVE_EVENT |
872 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 873 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 874
875 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 876 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 877 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 878 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 879 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 880 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 881 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 882 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 883 if (MLX5_CAP_GEN(mdev, imaicl)) {
884 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
885 IB_DEVICE_MEM_WINDOW_TYPE_2B;
886 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 887 /* We support 'Gappy' memory registration too */
888 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 889 }
e126ba97 890 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 891 if (MLX5_CAP_GEN(mdev, sho)) {
c0a6cbb9 892 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER;
2dea9094
SG		 893 /* At this stage no support for signature handover */
894 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
895 IB_PROT_T10DIF_TYPE_2 |
896 IB_PROT_T10DIF_TYPE_3;
897 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
898 IB_GUARD_T10DIF_CSUM;
899 }
938fe83c 900 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 901 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 902
85c7c014 903 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
e8161334
NO		 904 if (MLX5_CAP_ETH(mdev, csum_cap)) {
905 /* Legacy bit to support old userspace libraries */
88115fe7 906 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 907 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
908 }
909
910 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
911 props->raw_packet_caps |=
912 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 913
402ca536
BW		 914 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
915 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
916 if (max_tso) {
917 resp.tso_caps.max_tso = 1 << max_tso;
918 resp.tso_caps.supported_qpts |=
919 1 << IB_QPT_RAW_PACKET;
920 resp.response_length += sizeof(resp.tso_caps);
921 }
922 }
31f69a82
YH		 923
924 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
925 resp.rss_caps.rx_hash_function =
926 MLX5_RX_HASH_FUNC_TOEPLITZ;
927 resp.rss_caps.rx_hash_fields_mask =
928 MLX5_RX_HASH_SRC_IPV4 |
929 MLX5_RX_HASH_DST_IPV4 |
930 MLX5_RX_HASH_SRC_IPV6 |
931 MLX5_RX_HASH_DST_IPV6 |
932 MLX5_RX_HASH_SRC_PORT_TCP |
933 MLX5_RX_HASH_DST_PORT_TCP |
934 MLX5_RX_HASH_SRC_PORT_UDP |
4e2b53a5
MG		 935 MLX5_RX_HASH_DST_PORT_UDP |
936 MLX5_RX_HASH_INNER;
2d93fc85
MB		 937 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
938 MLX5_ACCEL_IPSEC_CAP_DEVICE)
939 resp.rss_caps.rx_hash_fields_mask |=
940 MLX5_RX_HASH_IPSEC_SPI;
31f69a82
YH		 941 resp.response_length += sizeof(resp.rss_caps);
942 }
943 } else {
944 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
945 resp.response_length += sizeof(resp.tso_caps);
946 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
947 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 948 }
949
f0313965
ES		 950 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
951 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
952 props->device_cap_flags |= IB_DEVICE_UD_TSO;
953 }
954
03404e8a 955 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
85c7c014
DJ		 956 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
957 raw_support)
03404e8a
MG		 958 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
959
1d54f890
YH		 960 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
961 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
962 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
963
cff5a0f3 964 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
85c7c014
DJ		 965 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
966 raw_support) {
e8161334 967 /* Legacy bit to support old userspace libraries */
cff5a0f3 968 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 969 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
970 }
cff5a0f3 971
24da0016
AL		 972 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
973 props->max_dm_size =
974 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
975 }
976
da6d6ba3
MG		 977 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
978 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
979
b1383aa6
NO		 980 if (MLX5_CAP_GEN(mdev, end_pad))
981 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
982
1b5daf11
MD		 983 props->vendor_part_id = mdev->pdev->device;
984 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 985
986 props->max_mr_size = ~0ull;
e0238a6a 987 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 988 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
989 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
990 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
991 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 992 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
993 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
994 sizeof(struct mlx5_wqe_raddr_seg)) /
995 sizeof(struct mlx5_wqe_data_seg);
33023fb8
SW		 996 props->max_send_sge = max_sq_sg;
997 props->max_recv_sge = max_rq_sg;
986ef95e 998 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 999 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 1000 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 1001 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
1002 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
1003 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
1004 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
1005 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
1006 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
1007 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 1008 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 1009 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 1010 props->max_fast_reg_page_list_len =
1011 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
62e3c379
MG		 1012 props->max_pi_fast_reg_page_list_len =
1013 props->max_fast_reg_page_list_len / 2;
776a3906 1014 get_atomic_caps_qp(dev, props);
81bea28f 1015 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 1016 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
1017 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 1018 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1019 props->max_mcast_grp;
1020 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 1021 props->max_ah = INT_MAX;
7c60bcbb
MB		 1022 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
1023 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 1024
e502b8b0
LR		 1025 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
1026 if (MLX5_CAP_GEN(mdev, pg))
1027 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
1028 props->odp_caps = dev->odp_caps;
1029 }
8cdd312c 1030
051f2630
LR		 1031 if (MLX5_CAP_GEN(mdev, cd))
1032 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
1033
eff901d3
EC		 1034 if (!mlx5_core_is_pf(mdev))
1035 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
1036
31f69a82 1037 if (mlx5_ib_port_link_layer(ibdev, 1) ==
85c7c014 1038 IB_LINK_LAYER_ETHERNET && raw_support) {
31f69a82
YH		 1039 props->rss_caps.max_rwq_indirection_tables =
1040 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1041 props->rss_caps.max_rwq_indirection_table_size =
1042 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1043 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1044 props->max_wq_type_rq =
1045 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1046 }
1047
eb761894 1048 if (MLX5_CAP_GEN(mdev, tag_matching)) {
78b1beb0 1049 props->tm_caps.max_num_tags =
eb761894 1050 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
78b1beb0 1051 props->tm_caps.max_ops =
eb761894 1052 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
78b1beb0 1053 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
eb761894
AK		 1054 }
1055
89705e92
DG		 1056 if (MLX5_CAP_GEN(mdev, tag_matching) &&
1057 MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
1058 props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
1059 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1060 }
1061
87ab3f52
YC		 1062 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1063 props->cq_caps.max_cq_moderation_count =
1064 MLX5_MAX_CQ_COUNT;
1065 props->cq_caps.max_cq_moderation_period =
1066 MLX5_MAX_CQ_PERIOD;
1067 }
1068
7e43a2a5 1069 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
7e43a2a5 1070 resp.response_length += sizeof(resp.cqe_comp_caps);
572f46bf
YC		 1071
1072 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1073 resp.cqe_comp_caps.max_num =
1074 MLX5_CAP_GEN(dev->mdev,
1075 cqe_compression_max_num);
1076
1077 resp.cqe_comp_caps.supported_format =
1078 MLX5_IB_CQE_RES_FORMAT_HASH |
1079 MLX5_IB_CQE_RES_FORMAT_CSUM;
6f1006a4
YC		 1080
1081 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1082 resp.cqe_comp_caps.supported_format |=
1083 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
572f46bf 1084 }
7e43a2a5
BW		 1085 }
1086
85c7c014
DJ		 1087 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
1088 raw_support) {
d949167d
BW		 1089 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1090 MLX5_CAP_GEN(mdev, qos)) {
1091 resp.packet_pacing_caps.qp_rate_limit_max =
1092 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1093 resp.packet_pacing_caps.qp_rate_limit_min =
1094 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1095 resp.packet_pacing_caps.supported_qpts |=
1096 1 << IB_QPT_RAW_PACKET;
61147f39
BW		 1097 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1098 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1099 resp.packet_pacing_caps.cap_flags |=
1100 MLX5_IB_PP_SUPPORT_BURST;
d949167d
BW		 1101 }
1102 resp.response_length += sizeof(resp.packet_pacing_caps);
1103 }
1104
9f885201
LR		 1105 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
1106 uhw->outlen)) {
795b609c
BW		 1107 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1108 resp.mlx5_ib_support_multi_pkt_send_wqes =
1109 MLX5_IB_ALLOW_MPW;
050da902
BW		 1110
1111 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1112 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1113 MLX5_IB_SUPPORT_EMPW;
1114
9f885201
LR		 1115 resp.response_length +=
1116 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1117 }
1118
de57f2ad
GL		 1119 if (field_avail(typeof(resp), flags, uhw->outlen)) {
1120 resp.response_length += sizeof(resp.flags);
7a0c8f42 1121
de57f2ad
GL		 1122 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1123 resp.flags |=
1124 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
7a0c8f42
GL		 1125
1126 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1127 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
7e11b911
DG		 1128 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1129 resp.flags |=
1130 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
7249c8ea
GL		 1131
1132 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
de57f2ad 1133 }
9f885201 1134
96dc3fc5
NO		 1135 if (field_avail(typeof(resp), sw_parsing_caps,
1136 uhw->outlen)) {
1137 resp.response_length += sizeof(resp.sw_parsing_caps);
1138 if (MLX5_CAP_ETH(mdev, swp)) {
1139 resp.sw_parsing_caps.sw_parsing_offloads |=
1140 MLX5_IB_SW_PARSING;
1141
1142 if (MLX5_CAP_ETH(mdev, swp_csum))
1143 resp.sw_parsing_caps.sw_parsing_offloads |=
1144 MLX5_IB_SW_PARSING_CSUM;
1145
1146 if (MLX5_CAP_ETH(mdev, swp_lso))
1147 resp.sw_parsing_caps.sw_parsing_offloads |=
1148 MLX5_IB_SW_PARSING_LSO;
1149
1150 if (resp.sw_parsing_caps.sw_parsing_offloads)
1151 resp.sw_parsing_caps.supported_qpts =
1152 BIT(IB_QPT_RAW_PACKET);
1153 }
1154 }
1155
85c7c014
DJ		 1156 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1157 raw_support) {
b4f34597
NO		 1158 resp.response_length += sizeof(resp.striding_rq_caps);
1159 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1160 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1161 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1162 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1163 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1164 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1165 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1166 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1167 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1168 resp.striding_rq_caps.supported_qpts =
1169 BIT(IB_QPT_RAW_PACKET);
1170 }
1171 }
1172
f95ef6cb
MG		 1173 if (field_avail(typeof(resp), tunnel_offloads_caps,
1174 uhw->outlen)) {
1175 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1176 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1177 resp.tunnel_offloads_caps |=
1178 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1179 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1180 resp.tunnel_offloads_caps |=
1181 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1182 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1183 resp.tunnel_offloads_caps |=
1184 MLX5_IB_TUNNELED_OFFLOADS_GRE;
e818e255
AL		 1185 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1186 MLX5_FLEX_PROTO_CW_MPLS_GRE)
1187 resp.tunnel_offloads_caps |=
1188 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1189 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1190 MLX5_FLEX_PROTO_CW_MPLS_UDP)
1191 resp.tunnel_offloads_caps |=
1192 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
f95ef6cb
MG		 1193 }
1194
402ca536
BW		 1195 if (uhw->outlen) {
1196 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1197
1198 if (err)
1199 return err;
1200 }
1201
1b5daf11 1202 return 0;
e126ba97
EC		 1203}
1204
1b5daf11
MD		 1205enum mlx5_ib_width {
1206 MLX5_IB_WIDTH_1X = 1 << 0,
1207 MLX5_IB_WIDTH_2X = 1 << 1,
1208 MLX5_IB_WIDTH_4X = 1 << 2,
1209 MLX5_IB_WIDTH_8X = 1 << 3,
1210 MLX5_IB_WIDTH_12X = 1 << 4
1211};
1212
db7a691a 1213static void translate_active_width(struct ib_device *ibdev, u8 active_width,
1b5daf11 1214 u8 *ib_width)
e126ba97
EC		 1215{
1216 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11 1217
db7a691a 1218 if (active_width & MLX5_IB_WIDTH_1X)
1b5daf11 1219 *ib_width = IB_WIDTH_1X;
d764970b
MG		 1220 else if (active_width & MLX5_IB_WIDTH_2X)
1221 *ib_width = IB_WIDTH_2X;
db7a691a 1222 else if (active_width & MLX5_IB_WIDTH_4X)
1b5daf11 1223 *ib_width = IB_WIDTH_4X;
db7a691a 1224 else if (active_width & MLX5_IB_WIDTH_8X)
1b5daf11 1225 *ib_width = IB_WIDTH_8X;
db7a691a 1226 else if (active_width & MLX5_IB_WIDTH_12X)
1b5daf11 1227 *ib_width = IB_WIDTH_12X;
db7a691a
MG		 1228 else {
1229 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1b5daf11 1230 (int)active_width);
db7a691a 1231 *ib_width = IB_WIDTH_4X;
e126ba97
EC		 1232 }
1233
db7a691a 1234 return;
1b5daf11 1235}
e126ba97 1236
1b5daf11
MD		 1237static int mlx5_mtu_to_ib_mtu(int mtu)
1238{
1239 switch (mtu) {
1240 case 256: return 1;
1241 case 512: return 2;
1242 case 1024: return 3;
1243 case 2048: return 4;
1244 case 4096: return 5;
1245 default:
1246 pr_warn("invalid mtu\n");
1247 return -1;
e126ba97 1248 }
1b5daf11 1249}
e126ba97 1250
1b5daf11
MD		 1251enum ib_max_vl_num {
1252 __IB_MAX_VL_0 = 1,
1253 __IB_MAX_VL_0_1 = 2,
1254 __IB_MAX_VL_0_3 = 3,
1255 __IB_MAX_VL_0_7 = 4,
1256 __IB_MAX_VL_0_14 = 5,
1257};
e126ba97 1258
1b5daf11
MD		 1259enum mlx5_vl_hw_cap {
1260 MLX5_VL_HW_0 = 1,
1261 MLX5_VL_HW_0_1 = 2,
1262 MLX5_VL_HW_0_2 = 3,
1263 MLX5_VL_HW_0_3 = 4,
1264 MLX5_VL_HW_0_4 = 5,
1265 MLX5_VL_HW_0_5 = 6,
1266 MLX5_VL_HW_0_6 = 7,
1267 MLX5_VL_HW_0_7 = 8,
1268 MLX5_VL_HW_0_14 = 15
1269};
e126ba97 1270
1b5daf11
MD		 1271static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1272 u8 *max_vl_num)
1273{
1274 switch (vl_hw_cap) {
1275 case MLX5_VL_HW_0:
1276 *max_vl_num = __IB_MAX_VL_0;
1277 break;
1278 case MLX5_VL_HW_0_1:
1279 *max_vl_num = __IB_MAX_VL_0_1;
1280 break;
1281 case MLX5_VL_HW_0_3:
1282 *max_vl_num = __IB_MAX_VL_0_3;
1283 break;
1284 case MLX5_VL_HW_0_7:
1285 *max_vl_num = __IB_MAX_VL_0_7;
1286 break;
1287 case MLX5_VL_HW_0_14:
1288 *max_vl_num = __IB_MAX_VL_0_14;
1289 break;
e126ba97 1290
1b5daf11
MD		 1291 default:
1292 return -EINVAL;
e126ba97 1293 }
e126ba97 1294
1b5daf11 1295 return 0;
e126ba97
EC		 1296}
1297
1b5daf11
MD		 1298static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1299 struct ib_port_attr *props)
e126ba97 1300{
1b5daf11
MD		 1301 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1302 struct mlx5_core_dev *mdev = dev->mdev;
1303 struct mlx5_hca_vport_context *rep;
046339ea
SM		 1304 u16 max_mtu;
1305 u16 oper_mtu;
1b5daf11
MD		 1306 int err;
1307 u8 ib_link_width_oper;
1308 u8 vl_hw_cap;
e126ba97 1309
1b5daf11
MD		 1310 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1311 if (!rep) {
1312 err = -ENOMEM;
e126ba97 1313 goto out;
e126ba97 1314 }
e126ba97 1315
c4550c63 1316 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 1317
1b5daf11 1318 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 1319 if (err)
1320 goto out;
1321
1b5daf11
MD		 1322 props->lid = rep->lid;
1323 props->lmc = rep->lmc;
1324 props->sm_lid = rep->sm_lid;
1325 props->sm_sl = rep->sm_sl;
1326 props->state = rep->vport_state;
1327 props->phys_state = rep->port_physical_state;
1328 props->port_cap_flags = rep->cap_mask1;
1329 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1330 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1331 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1332 props->bad_pkey_cntr = rep->pkey_violation_counter;
1333 props->qkey_viol_cntr = rep->qkey_violation_counter;
1334 props->subnet_timeout = rep->subnet_timeout;
1335 props->init_type_reply = rep->init_type_reply;
e126ba97 1336
4106a758
MG		 1337 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1338 props->port_cap_flags2 = rep->cap_mask2;
1339
1b5daf11
MD		 1340 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1341 if (err)
e126ba97 1342 goto out;
e126ba97 1343
db7a691a
MG		 1344 translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1345
d5beb7f2 1346 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 1347 if (err)
1348 goto out;
1349
facc9699 1350 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 1351
1b5daf11 1352 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 1353
facc9699 1354 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 1355
1b5daf11 1356 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1357
1b5daf11
MD		 1358 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1359 if (err)
1360 goto out;
e126ba97 1361
1b5daf11
MD		 1362 err = translate_max_vl_num(ibdev, vl_hw_cap,
1363 &props->max_vl_num);
e126ba97 1364out:
1b5daf11 1365 kfree(rep);
e126ba97
EC		 1366 return err;
1367}
1368
1b5daf11
MD		 1369int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1370 struct ib_port_attr *props)
e126ba97 1371{
095b0927
IT		 1372 unsigned int count;
1373 int ret;
1374
1b5daf11
MD		 1375 switch (mlx5_get_vport_access_method(ibdev)) {
1376 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1377 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1378 break;
e126ba97 1379
1b5daf11 1380 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1381 ret = mlx5_query_hca_port(ibdev, port, props);
1382 break;
e126ba97 1383
3f89a643 1384 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1385 ret = mlx5_query_port_roce(ibdev, port, props);
1386 break;
3f89a643 1387
1b5daf11 1388 default:
095b0927
IT		 1389 ret = -EINVAL;
1390 }
1391
1392 if (!ret && props) {
b3cbd6f0
DJ		 1393 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1394 struct mlx5_core_dev *mdev;
1395 bool put_mdev = true;
1396
1397 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1398 if (!mdev) {
1399 /* If the port isn't affiliated yet query the master.
1400 * The master and slave will have the same values.
1401 */
1402 mdev = dev->mdev;
1403 port = 1;
1404 put_mdev = false;
1405 }
1406 count = mlx5_core_reserved_gids_count(mdev);
1407 if (put_mdev)
1408 mlx5_ib_put_native_port_mdev(dev, port);
095b0927 1409 props->gid_tbl_len -= count;
1b5daf11 1410 }
095b0927 1411 return ret;
1b5daf11 1412}
e126ba97 1413
8e6efa3a
MB		 1414static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1415 struct ib_port_attr *props)
1416{
1417 int ret;
1418
26628e2d
MB		 1419 /* Only link layer == ethernet is valid for representors
1420 * and we always use port 1
1421 */
8e6efa3a
MB		 1422 ret = mlx5_query_port_roce(ibdev, port, props);
1423 if (ret || !props)
1424 return ret;
1425
1426 /* We don't support GIDS */
1427 props->gid_tbl_len = 0;
1428
1429 return ret;
1430}
1431
1b5daf11
MD		 1432static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1433 union ib_gid *gid)
1434{
1435 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1436 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1437
1b5daf11
MD		 1438 switch (mlx5_get_vport_access_method(ibdev)) {
1439 case MLX5_VPORT_ACCESS_METHOD_MAD:
1440 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1441
1b5daf11
MD		 1442 case MLX5_VPORT_ACCESS_METHOD_HCA:
1443 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1444
1445 default:
1446 return -EINVAL;
1447 }
e126ba97 1448
e126ba97
EC		 1449}
1450
b3cbd6f0
DJ		 1451static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1452 u16 index, u16 *pkey)
1b5daf11
MD		 1453{
1454 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b3cbd6f0
DJ		 1455 struct mlx5_core_dev *mdev;
1456 bool put_mdev = true;
1457 u8 mdev_port_num;
1458 int err;
1b5daf11 1459
b3cbd6f0
DJ		 1460 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1461 if (!mdev) {
1462 /* The port isn't affiliated yet, get the PKey from the master
1463 * port. For RoCE the PKey tables will be the same.
1464 */
1465 put_mdev = false;
1466 mdev = dev->mdev;
1467 mdev_port_num = 1;
1468 }
1469
1470 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1471 index, pkey);
1472 if (put_mdev)
1473 mlx5_ib_put_native_port_mdev(dev, port);
1474
1475 return err;
1476}
1477
1478static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1479 u16 *pkey)
1480{
1b5daf11
MD		 1481 switch (mlx5_get_vport_access_method(ibdev)) {
1482 case MLX5_VPORT_ACCESS_METHOD_MAD:
1483 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1484
1485 case MLX5_VPORT_ACCESS_METHOD_HCA:
1486 case MLX5_VPORT_ACCESS_METHOD_NIC:
b3cbd6f0 1487 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1b5daf11
MD		 1488 default:
1489 return -EINVAL;
1490 }
1491}
e126ba97
EC		 1492
1493static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1494 struct ib_device_modify *props)
1495{
1496 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1497 struct mlx5_reg_node_desc in;
1498 struct mlx5_reg_node_desc out;
1499 int err;
1500
1501 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1502 return -EOPNOTSUPP;
1503
1504 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1505 return 0;
1506
1507 /*
1508 * If possible, pass node desc to FW, so it can generate
1509 * a 144 trap. If cmd fails, just ignore.
1510 */
bd99fdea 1511 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1512 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1513 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1514 if (err)
1515 return err;
1516
bd99fdea 1517 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1518
1519 return err;
1520}
1521
cdbe33d0
EC		 1522static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1523 u32 value)
1524{
1525 struct mlx5_hca_vport_context ctx = {};
b3cbd6f0
DJ		 1526 struct mlx5_core_dev *mdev;
1527 u8 mdev_port_num;
cdbe33d0
EC		 1528 int err;
1529
b3cbd6f0
DJ		 1530 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1531 if (!mdev)
1532 return -ENODEV;
1533
1534 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
cdbe33d0 1535 if (err)
b3cbd6f0 1536 goto out;
cdbe33d0
EC		 1537
1538 if (~ctx.cap_mask1_perm & mask) {
1539 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1540 mask, ctx.cap_mask1_perm);
b3cbd6f0
DJ		 1541 err = -EINVAL;
1542 goto out;
cdbe33d0
EC		 1543 }
1544
1545 ctx.cap_mask1 = value;
1546 ctx.cap_mask1_perm = mask;
b3cbd6f0
DJ		 1547 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1548 0, &ctx);
1549
1550out:
1551 mlx5_ib_put_native_port_mdev(dev, port_num);
cdbe33d0
EC		 1552
1553 return err;
1554}
1555
e126ba97
EC		 1556static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1557 struct ib_port_modify *props)
1558{
1559 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1560 struct ib_port_attr attr;
1561 u32 tmp;
1562 int err;
cdbe33d0
EC		 1563 u32 change_mask;
1564 u32 value;
1565 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1566 IB_LINK_LAYER_INFINIBAND);
1567
ec255879
MD		 1568 /* CM layer calls ib_modify_port() regardless of the link layer. For
1569 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1570 */
1571 if (!is_ib)
1572 return 0;
1573
cdbe33d0
EC		 1574 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1575 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1576 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1577 return set_port_caps_atomic(dev, port, change_mask, value);
1578 }
e126ba97
EC		 1579
1580 mutex_lock(&dev->cap_mask_mutex);
1581
c4550c63 1582 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1583 if (err)
1584 goto out;
1585
1586 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1587 ~props->clr_port_cap_mask;
1588
9603b61d 1589 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1590
1591out:
1592 mutex_unlock(&dev->cap_mask_mutex);
1593 return err;
1594}
1595
30aa60b3
EC		 1596static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1597{
1598 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1599 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1600}
1601
31a78a5a
YH		 1602static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1603{
1604 /* Large page with non 4k uar support might limit the dynamic size */
1605 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1606 return MLX5_MIN_DYN_BFREGS;
1607
1608 return MLX5_MAX_DYN_BFREGS;
1609}
1610
b037c29a
EC		 1611static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1612 struct mlx5_ib_alloc_ucontext_req_v2 *req,
31a78a5a 1613 struct mlx5_bfreg_info *bfregi)
b037c29a
EC		 1614{
1615 int uars_per_sys_page;
1616 int bfregs_per_sys_page;
1617 int ref_bfregs = req->total_num_bfregs;
1618
1619 if (req->total_num_bfregs == 0)
1620 return -EINVAL;
1621
1622 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1623 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1624
1625 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1626 return -ENOMEM;
1627
1628 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1629 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
31a78a5a 1630 /* This holds the required static allocation asked by the user */
b037c29a 1631 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
b037c29a
EC		 1632 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1633 return -EINVAL;
1634
31a78a5a
YH		 1635 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1636 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1637 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1638 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1639
1640 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
b037c29a
EC		 1641 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1642 lib_uar_4k ? "yes" : "no", ref_bfregs,
31a78a5a
YH		 1643 req->total_num_bfregs, bfregi->total_num_bfregs,
1644 bfregi->num_sys_pages);
b037c29a
EC		 1645
1646 return 0;
1647}
1648
1649static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1650{
1651 struct mlx5_bfreg_info *bfregi;
1652 int err;
1653 int i;
1654
1655 bfregi = &context->bfregi;
31a78a5a 1656 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
b037c29a
EC		 1657 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1658 if (err)
1659 goto error;
1660
1661 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1662 }
4ed131d0
YH		 1663
1664 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1665 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1666
b037c29a
EC		 1667 return 0;
1668
1669error:
1670 for (--i; i >= 0; i--)
1671 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1672 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1673
1674 return err;
1675}
1676
15177999
LR		 1677static void deallocate_uars(struct mlx5_ib_dev *dev,
1678 struct mlx5_ib_ucontext *context)
b037c29a
EC		 1679{
1680 struct mlx5_bfreg_info *bfregi;
b037c29a
EC		 1681 int i;
1682
1683 bfregi = &context->bfregi;
15177999 1684 for (i = 0; i < bfregi->num_sys_pages; i++)
4ed131d0 1685 if (i < bfregi->num_static_sys_pages ||
15177999
LR		 1686 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1687 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
b037c29a
EC		 1688}
1689
0042f9e4 1690int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
a560f1d9
MB		 1691{
1692 int err = 0;
1693
1694 mutex_lock(&dev->lb.mutex);
0042f9e4
MB		 1695 if (td)
1696 dev->lb.user_td++;
1697 if (qp)
1698 dev->lb.qps++;
1699
1700 if (dev->lb.user_td == 2 ||
1701 dev->lb.qps == 1) {
1702 if (!dev->lb.enabled) {
1703 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1704 dev->lb.enabled = true;
1705 }
1706 }
a560f1d9
MB		 1707
1708 mutex_unlock(&dev->lb.mutex);
1709
1710 return err;
1711}
1712
0042f9e4 1713void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
a560f1d9
MB		 1714{
1715 mutex_lock(&dev->lb.mutex);
0042f9e4
MB		 1716 if (td)
1717 dev->lb.user_td--;
1718 if (qp)
1719 dev->lb.qps--;
1720
1721 if (dev->lb.user_td == 1 &&
1722 dev->lb.qps == 0) {
1723 if (dev->lb.enabled) {
1724 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1725 dev->lb.enabled = false;
1726 }
1727 }
a560f1d9
MB		 1728
1729 mutex_unlock(&dev->lb.mutex);
1730}
1731
d2d19121
YH		 1732static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1733 u16 uid)
c85023e1
HN		 1734{
1735 int err;
1736
cfdeb893
LR		 1737 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1738 return 0;
1739
d2d19121 1740 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
c85023e1
HN		 1741 if (err)
1742 return err;
1743
1744 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1745 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1746 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1747 return err;
1748
0042f9e4 1749 return mlx5_ib_enable_lb(dev, true, false);
c85023e1
HN		 1750}
1751
d2d19121
YH		 1752static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1753 u16 uid)
c85023e1 1754{
cfdeb893
LR		 1755 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1756 return;
1757
d2d19121 1758 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
c85023e1
HN		 1759
1760 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1761 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1762 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1763 return;
1764
0042f9e4 1765 mlx5_ib_disable_lb(dev, true, false);
c85023e1
HN		 1766}
1767
a2a074ef
LR		 1768static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1769 struct ib_udata *udata)
e126ba97 1770{
a2a074ef 1771 struct ib_device *ibdev = uctx->device;
e126ba97 1772 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1773 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1774 struct mlx5_ib_alloc_ucontext_resp resp = {};
5c99eaec 1775 struct mlx5_core_dev *mdev = dev->mdev;
a2a074ef 1776 struct mlx5_ib_ucontext *context = to_mucontext(uctx);
2f5ff264 1777 struct mlx5_bfreg_info *bfregi;
78c0f98c 1778 int ver;
e126ba97 1779 int err;
a168a41c
MD		 1780 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1781 max_cqe_version);
25bb36e7 1782 u32 dump_fill_mkey;
b037c29a 1783 bool lib_uar_4k;
e126ba97
EC		 1784
1785 if (!dev->ib_active)
a2a074ef 1786 return -EAGAIN;
e126ba97 1787
e093111d 1788 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1789 ver = 0;
e093111d 1790 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1791 ver = 2;
1792 else
a2a074ef 1793 return -EINVAL;
78c0f98c 1794
e093111d 1795 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97 1796 if (err)
a2a074ef 1797 return err;
e126ba97 1798
a8b92ca1 1799 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
a2a074ef 1800 return -EOPNOTSUPP;
78c0f98c 1801
f72300c5 1802 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
a2a074ef 1803 return -EOPNOTSUPP;
b368d7cb 1804
2f5ff264
EC		 1805 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1806 MLX5_NON_FP_BFREGS_PER_UAR);
1807 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
a2a074ef 1808 return -EINVAL;
e126ba97 1809
938fe83c 1810 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1811 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1812 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1813 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1814 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1815 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1816 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1817 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1818 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1819 resp.cqe_version = min_t(__u8,
1820 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1821 req.max_cqe_version);
30aa60b3
EC		 1822 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1823 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1824 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1825 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1826 resp.response_length = min(offsetof(typeof(resp), response_length) +
1827 sizeof(resp.response_length), udata->outlen);
e126ba97 1828
c03faa56
MB		 1829 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1830 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1831 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1832 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1833 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1834 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1835 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1836 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1837 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1838 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1839 }
1840
30aa60b3 1841 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1842 bfregi = &context->bfregi;
b037c29a
EC		 1843
1844 /* updates req->total_num_bfregs */
31a78a5a 1845 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
b037c29a 1846 if (err)
e126ba97 1847 goto out_ctx;
e126ba97 1848
b037c29a
EC		 1849 mutex_init(&bfregi->lock);
1850 bfregi->lib_uar_4k = lib_uar_4k;
31a78a5a 1851 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1852 GFP_KERNEL);
b037c29a 1853 if (!bfregi->count) {
e126ba97 1854 err = -ENOMEM;
b037c29a 1855 goto out_ctx;
e126ba97
EC		 1856 }
1857
b037c29a
EC		 1858 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1859 sizeof(*bfregi->sys_pages),
1860 GFP_KERNEL);
1861 if (!bfregi->sys_pages) {
e126ba97 1862 err = -ENOMEM;
b037c29a 1863 goto out_count;
e126ba97
EC		 1864 }
1865
b037c29a
EC		 1866 err = allocate_uars(dev, context);
1867 if (err)
1868 goto out_sys_pages;
e126ba97 1869
13859d5d
LR		 1870 if (ibdev->attrs.device_cap_flags & IB_DEVICE_ON_DEMAND_PAGING)
1871 context->ibucontext.invalidate_range =
1872 &mlx5_ib_invalidate_range;
b4cfe447 1873
a8b92ca1 1874 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
fb98153b 1875 err = mlx5_ib_devx_create(dev, true);
76dc5a84 1876 if (err < 0)
d2d19121 1877 goto out_uars;
76dc5a84 1878 context->devx_uid = err;
a8b92ca1
YH		 1879 }
1880
d2d19121
YH		 1881 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1882 context->devx_uid);
1883 if (err)
1884 goto out_devx;
1885
25bb36e7
YC		 1886 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1887 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1888 if (err)
8193abb6 1889 goto out_mdev;
25bb36e7
YC		 1890 }
1891
e126ba97
EC		 1892 INIT_LIST_HEAD(&context->db_page_list);
1893 mutex_init(&context->db_page_mutex);
1894
2f5ff264 1895 resp.tot_bfregs = req.total_num_bfregs;
508562d6 1896 resp.num_ports = dev->num_ports;
b368d7cb 1897
f72300c5
HA		 1898 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1899 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1900
402ca536 1901 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1902 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1903 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1904 resp.response_length += sizeof(resp.cmds_supp_uhw);
1905 }
1906
78984898
OG		 1907 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1908 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1909 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1910 resp.eth_min_inline++;
1911 }
1912 resp.response_length += sizeof(resp.eth_min_inline);
1913 }
1914
5c99eaec
FD		 1915 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1916 if (mdev->clock_info)
1917 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1918 resp.response_length += sizeof(resp.clock_info_versions);
1919 }
1920
bc5c6eed
NO		 1921 /*
1922 * We don't want to expose information from the PCI bar that is located
1923 * after 4096 bytes, so if the arch only supports larger pages, let's
1924 * pretend we don't support reading the HCA's core clock. This is also
1925 * forced by mmap function.
1926 */
de8d6e02
EC		 1927 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1928 if (PAGE_SIZE <= 4096) {
1929 resp.comp_mask |=
1930 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1931 resp.hca_core_clock_offset =
1932 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1933 }
5c99eaec 1934 resp.response_length += sizeof(resp.hca_core_clock_offset);
b368d7cb
MB		 1935 }
1936
30aa60b3
EC		 1937 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1938 resp.response_length += sizeof(resp.log_uar_size);
1939
1940 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1941 resp.response_length += sizeof(resp.num_uars_per_page);
1942
31a78a5a
YH		 1943 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1944 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1945 resp.response_length += sizeof(resp.num_dyn_bfregs);
1946 }
1947
25bb36e7
YC		 1948 if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) {
1949 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1950 resp.dump_fill_mkey = dump_fill_mkey;
1951 resp.comp_mask |=
1952 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1953 }
1954 resp.response_length += sizeof(resp.dump_fill_mkey);
1955 }
1956
b368d7cb 1957 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1958 if (err)
a8b92ca1 1959 goto out_mdev;
e126ba97 1960
2f5ff264
EC		 1961 bfregi->ver = ver;
1962 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1963 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1964 context->lib_caps = req.lib_caps;
1965 print_lib_caps(dev, context->lib_caps);
f72300c5 1966
7c34ec19 1967 if (dev->lag_active) {
95579e78 1968 u8 port = mlx5_core_native_port_num(dev->mdev) - 1;
c6a21c38
MD		 1969
1970 atomic_set(&context->tx_port_affinity,
1971 atomic_add_return(
95579e78 1972 1, &dev->port[port].roce.tx_port_affinity));
c6a21c38
MD		 1973 }
1974
a2a074ef 1975 return 0;
e126ba97 1976
a8b92ca1 1977out_mdev:
d2d19121
YH		 1978 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1979out_devx:
a8b92ca1 1980 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
76dc5a84 1981 mlx5_ib_devx_destroy(dev, context->devx_uid);
146d2f1a 1982
e126ba97 1983out_uars:
b037c29a 1984 deallocate_uars(dev, context);
e126ba97 1985
b037c29a
EC		 1986out_sys_pages:
1987 kfree(bfregi->sys_pages);
e126ba97 1988
b037c29a
EC		 1989out_count:
1990 kfree(bfregi->count);
e126ba97
EC		 1991
1992out_ctx:
a2a074ef 1993 return err;
e126ba97
EC		 1994}
1995
a2a074ef 1996static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
e126ba97
EC		 1997{
1998 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1999 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 2000 struct mlx5_bfreg_info *bfregi;
e126ba97 2001
f27a0d50
JG		 2002 /* All umem's must be destroyed before destroying the ucontext. */
2003 mutex_lock(&ibcontext->per_mm_list_lock);
2004 WARN_ON(!list_empty(&ibcontext->per_mm_list));
2005 mutex_unlock(&ibcontext->per_mm_list_lock);
a8b92ca1 2006
b037c29a 2007 bfregi = &context->bfregi;
d2d19121
YH		 2008 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
2009
a8b92ca1 2010 if (context->devx_uid)
76dc5a84 2011 mlx5_ib_devx_destroy(dev, context->devx_uid);
146d2f1a 2012
b037c29a
EC		 2013 deallocate_uars(dev, context);
2014 kfree(bfregi->sys_pages);
2f5ff264 2015 kfree(bfregi->count);
e126ba97
EC		 2016}
2017
b037c29a 2018static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
4ed131d0 2019 int uar_idx)
e126ba97 2020{
b037c29a
EC		 2021 int fw_uars_per_page;
2022
2023 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2024
aa8106f1 2025 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
e126ba97
EC		 2026}
2027
2028static int get_command(unsigned long offset)
2029{
2030 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2031}
2032
2033static int get_arg(unsigned long offset)
2034{
2035 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2036}
2037
2038static int get_index(unsigned long offset)
2039{
2040 return get_arg(offset);
2041}
2042
4ed131d0
YH		 2043/* Index resides in an extra byte to enable larger values than 255 */
2044static int get_extended_index(unsigned long offset)
2045{
2046 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2047}
2048
7c2344c3
MG		 2049
2050static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2051{
7c2344c3
MG		 2052}
2053
37aa5c36
GL		 2054static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2055{
2056 switch (cmd) {
2057 case MLX5_IB_MMAP_WC_PAGE:
2058 return "WC";
2059 case MLX5_IB_MMAP_REGULAR_PAGE:
2060 return "best effort WC";
2061 case MLX5_IB_MMAP_NC_PAGE:
2062 return "NC";
24da0016
AL		 2063 case MLX5_IB_MMAP_DEVICE_MEM:
2064 return "Device Memory";
37aa5c36
GL		 2065 default:
2066 return NULL;
2067 }
2068}
2069
5c99eaec
FD		 2070static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2071 struct vm_area_struct *vma,
2072 struct mlx5_ib_ucontext *context)
2073{
4eb6ab13
JG		 2074 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2075 !(vma->vm_flags & VM_SHARED))
5c99eaec
FD		 2076 return -EINVAL;
2077
2078 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2079 return -EOPNOTSUPP;
2080
4eb6ab13 2081 if (vma->vm_flags & (VM_WRITE | VM_EXEC))
5c99eaec 2082 return -EPERM;
c660133c 2083 vma->vm_flags &= ~VM_MAYWRITE;
5c99eaec 2084
ddcdc368 2085 if (!dev->mdev->clock_info)
5c99eaec
FD		 2086 return -EOPNOTSUPP;
2087
4eb6ab13
JG		 2088 return vm_insert_page(vma, vma->vm_start,
2089 virt_to_page(dev->mdev->clock_info));
5c99eaec
FD		 2090}
2091
37aa5c36 2092static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 2093 struct vm_area_struct *vma,
2094 struct mlx5_ib_ucontext *context)
37aa5c36 2095{
2f5ff264 2096 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 2097 int err;
2098 unsigned long idx;
aa09ea6e 2099 phys_addr_t pfn;
37aa5c36 2100 pgprot_t prot;
4ed131d0
YH		 2101 u32 bfreg_dyn_idx = 0;
2102 u32 uar_index;
2103 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2104 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2105 bfregi->num_static_sys_pages;
b037c29a
EC		 2106
2107 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2108 return -EINVAL;
2109
4ed131d0
YH		 2110 if (dyn_uar)
2111 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2112 else
2113 idx = get_index(vma->vm_pgoff);
2114
2115 if (idx >= max_valid_idx) {
2116 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2117 idx, max_valid_idx);
b037c29a
EC		 2118 return -EINVAL;
2119 }
37aa5c36
GL		 2120
2121 switch (cmd) {
2122 case MLX5_IB_MMAP_WC_PAGE:
4ed131d0 2123 case MLX5_IB_MMAP_ALLOC_WC:
37aa5c36
GL		 2124/* Some architectures don't support WC memory */
2125#if defined(CONFIG_X86)
2126 if (!pat_enabled())
2127 return -EPERM;
2128#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2129 return -EPERM;
2130#endif
2131 /* fall through */
2132 case MLX5_IB_MMAP_REGULAR_PAGE:
2133 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2134 prot = pgprot_writecombine(vma->vm_page_prot);
2135 break;
2136 case MLX5_IB_MMAP_NC_PAGE:
2137 prot = pgprot_noncached(vma->vm_page_prot);
2138 break;
2139 default:
2140 return -EINVAL;
2141 }
2142
4ed131d0
YH		 2143 if (dyn_uar) {
2144 int uars_per_page;
2145
2146 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2147 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2148 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2149 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2150 bfreg_dyn_idx, bfregi->total_num_bfregs);
2151 return -EINVAL;
2152 }
2153
2154 mutex_lock(&bfregi->lock);
2155 /* Fail if uar already allocated, first bfreg index of each
2156 * page holds its count.
2157 */
2158 if (bfregi->count[bfreg_dyn_idx]) {
2159 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2160 mutex_unlock(&bfregi->lock);
2161 return -EINVAL;
2162 }
2163
2164 bfregi->count[bfreg_dyn_idx]++;
2165 mutex_unlock(&bfregi->lock);
2166
2167 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2168 if (err) {
2169 mlx5_ib_warn(dev, "UAR alloc failed\n");
2170 goto free_bfreg;
2171 }
2172 } else {
2173 uar_index = bfregi->sys_pages[idx];
2174 }
2175
2176 pfn = uar_index2pfn(dev, uar_index);
37aa5c36
GL		 2177 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2178
e2cd1d1a
JG		 2179 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2180 prot);
37aa5c36 2181 if (err) {
8f062287 2182 mlx5_ib_err(dev,
e2cd1d1a 2183 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
8f062287 2184 err, mmap_cmd2str(cmd));
4ed131d0 2185 goto err;
37aa5c36
GL		 2186 }
2187
4ed131d0
YH		 2188 if (dyn_uar)
2189 bfregi->sys_pages[idx] = uar_index;
2190 return 0;
2191
2192err:
2193 if (!dyn_uar)
2194 return err;
2195
2196 mlx5_cmd_free_uar(dev->mdev, idx);
2197
2198free_bfreg:
2199 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2200
2201 return err;
37aa5c36
GL		 2202}
2203
24da0016
AL		 2204static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2205{
2206 struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2207 struct mlx5_ib_dev *dev = to_mdev(context->device);
2208 u16 page_idx = get_extended_index(vma->vm_pgoff);
2209 size_t map_size = vma->vm_end - vma->vm_start;
2210 u32 npages = map_size >> PAGE_SHIFT;
2211 phys_addr_t pfn;
24da0016
AL		 2212
2213 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2214 page_idx + npages)
2215 return -EINVAL;
2216
aa8106f1 2217 pfn = ((dev->mdev->bar_addr +
24da0016
AL		 2218 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2219 PAGE_SHIFT) +
2220 page_idx;
e2cd1d1a
JG		 2221 return rdma_user_mmap_io(context, vma, pfn, map_size,
2222 pgprot_writecombine(vma->vm_page_prot));
24da0016
AL		 2223}
2224
e126ba97
EC		 2225static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2226{
2227 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2228 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 2229 unsigned long command;
e126ba97
EC		 2230 phys_addr_t pfn;
2231
2232 command = get_command(vma->vm_pgoff);
2233 switch (command) {
37aa5c36
GL		 2234 case MLX5_IB_MMAP_WC_PAGE:
2235 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 2236 case MLX5_IB_MMAP_REGULAR_PAGE:
4ed131d0 2237 case MLX5_IB_MMAP_ALLOC_WC:
7c2344c3 2238 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 2239
2240 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2241 return -ENOSYS;
2242
d69e3bcf 2243 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 2244 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2245 return -EINVAL;
2246
6cbac1e4 2247 if (vma->vm_flags & VM_WRITE)
d69e3bcf 2248 return -EPERM;
c660133c 2249 vma->vm_flags &= ~VM_MAYWRITE;
d69e3bcf
MB		 2250
2251 /* Don't expose to user-space information it shouldn't have */
2252 if (PAGE_SIZE > 4096)
2253 return -EOPNOTSUPP;
2254
d69e3bcf
MB		 2255 pfn = (dev->mdev->iseg_base +
2256 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2257 PAGE_SHIFT;
d5e560d3
JG		 2258 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2259 PAGE_SIZE,
2260 pgprot_noncached(vma->vm_page_prot));
5c99eaec
FD		 2261 case MLX5_IB_MMAP_CLOCK_INFO:
2262 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
d69e3bcf 2263
24da0016
AL		 2264 case MLX5_IB_MMAP_DEVICE_MEM:
2265 return dm_mmap(ibcontext, vma);
2266
e126ba97
EC		 2267 default:
2268 return -EINVAL;
2269 }
2270
2271 return 0;
2272}
2273
25c13324
AL		 2274static inline int check_dm_type_support(struct mlx5_ib_dev *dev,
2275 u32 type)
24da0016 2276{
25c13324
AL		 2277 switch (type) {
2278 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2279 if (!MLX5_CAP_DEV_MEM(dev->mdev, memic))
2280 return -EOPNOTSUPP;
2281 break;
2282 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2283 if (!capable(CAP_SYS_RAWIO) ||
2284 !capable(CAP_NET_RAW))
2285 return -EPERM;
2286
2287 if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
2288 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner)))
2289 return -EOPNOTSUPP;
2290 break;
2291 }
2292
2293 return 0;
2294}
2295
3b113a1e
AL		 2296static int handle_alloc_dm_memic(struct ib_ucontext *ctx,
2297 struct mlx5_ib_dm *dm,
2298 struct ib_dm_alloc_attr *attr,
2299 struct uverbs_attr_bundle *attrs)
24da0016 2300{
3b113a1e 2301 struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm;
24da0016
AL		 2302 u64 start_offset;
2303 u32 page_idx;
2304 int err;
2305
3b113a1e 2306 dm->size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
24da0016 2307
3b113a1e
AL		 2308 err = mlx5_cmd_alloc_memic(dm_db, &dm->dev_addr,
2309 dm->size, attr->alignment);
24da0016 2310 if (err)
3b113a1e 2311 return err;
24da0016 2312
3b113a1e
AL		 2313 page_idx = (dm->dev_addr - pci_resource_start(dm_db->dev->pdev, 0) -
2314 MLX5_CAP64_DEV_MEM(dm_db->dev, memic_bar_start_addr)) >>
24da0016
AL		 2315 PAGE_SHIFT;
2316
2317 err = uverbs_copy_to(attrs,
3b113a1e
AL		 2318 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2319 &page_idx, sizeof(page_idx));
24da0016
AL		 2320 if (err)
2321 goto err_dealloc;
2322
3b113a1e 2323 start_offset = dm->dev_addr & ~PAGE_MASK;
24da0016
AL		 2324 err = uverbs_copy_to(attrs,
2325 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2326 &start_offset, sizeof(start_offset));
2327 if (err)
2328 goto err_dealloc;
2329
3b113a1e
AL		 2330 bitmap_set(to_mucontext(ctx)->dm_pages, page_idx,
2331 DIV_ROUND_UP(dm->size, PAGE_SIZE));
2332
2333 return 0;
2334
2335err_dealloc:
2336 mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2337
2338 return err;
2339}
2340
25c13324
AL		 2341static int handle_alloc_dm_sw_icm(struct ib_ucontext *ctx,
2342 struct mlx5_ib_dm *dm,
2343 struct ib_dm_alloc_attr *attr,
2344 struct uverbs_attr_bundle *attrs,
2345 int type)
2346{
2347 struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm;
2348 u64 act_size;
2349 int err;
2350
2351 /* Allocation size must a multiple of the basic block size
2352 * and a power of 2.
2353 */
37eb86c4 2354 act_size = round_up(attr->length, MLX5_SW_ICM_BLOCK_SIZE(dm_db->dev));
25c13324
AL		 2355 act_size = roundup_pow_of_two(act_size);
2356
2357 dm->size = act_size;
2358 err = mlx5_cmd_alloc_sw_icm(dm_db, type, act_size,
2359 to_mucontext(ctx)->devx_uid, &dm->dev_addr,
2360 &dm->icm_dm.obj_id);
2361 if (err)
2362 return err;
2363
24da0016 2364 err = uverbs_copy_to(attrs,
25c13324
AL		 2365 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2366 &dm->dev_addr, sizeof(dm->dev_addr));
24da0016 2367 if (err)
25c13324
AL		 2368 mlx5_cmd_dealloc_sw_icm(dm_db, type, dm->size,
2369 to_mucontext(ctx)->devx_uid,
2370 dm->dev_addr, dm->icm_dm.obj_id);
2371
2372 return err;
2373}
2374
3b113a1e
AL		 2375struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2376 struct ib_ucontext *context,
2377 struct ib_dm_alloc_attr *attr,
2378 struct uverbs_attr_bundle *attrs)
2379{
2380 struct mlx5_ib_dm *dm;
2381 enum mlx5_ib_uapi_dm_type type;
2382 int err;
24da0016 2383
3b113a1e
AL		 2384 err = uverbs_get_const_default(&type, attrs,
2385 MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
2386 MLX5_IB_UAPI_DM_TYPE_MEMIC);
2387 if (err)
2388 return ERR_PTR(err);
24da0016 2389
3b113a1e
AL		 2390 mlx5_ib_dbg(to_mdev(ibdev), "alloc_dm req: dm_type=%d user_length=0x%llx log_alignment=%d\n",
2391 type, attr->length, attr->alignment);
2392
25c13324
AL		 2393 err = check_dm_type_support(to_mdev(ibdev), type);
2394 if (err)
2395 return ERR_PTR(err);
2396
3b113a1e
AL		 2397 dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2398 if (!dm)
2399 return ERR_PTR(-ENOMEM);
2400
2401 dm->type = type;
2402
2403 switch (type) {
2404 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2405 err = handle_alloc_dm_memic(context, dm,
2406 attr,
2407 attrs);
2408 break;
25c13324
AL		 2409 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2410 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2411 err = handle_alloc_dm_sw_icm(context, dm, attr, attrs, type);
2412 break;
3b113a1e
AL		 2413 default:
2414 err = -EOPNOTSUPP;
2415 }
24da0016 2416
3b113a1e
AL		 2417 if (err)
2418 goto err_free;
24da0016
AL		 2419
2420 return &dm->ibdm;
2421
24da0016
AL		 2422err_free:
2423 kfree(dm);
2424 return ERR_PTR(err);
2425}
2426
c4367a26 2427int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs)
24da0016 2428{
25c13324
AL		 2429 struct mlx5_ib_ucontext *ctx = rdma_udata_to_drv_context(
2430 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
3b113a1e 2431 struct mlx5_dm *dm_db = &to_mdev(ibdm->device)->dm;
24da0016 2432 struct mlx5_ib_dm *dm = to_mdm(ibdm);
24da0016
AL		 2433 u32 page_idx;
2434 int ret;
2435
3b113a1e
AL		 2436 switch (dm->type) {
2437 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2438 ret = mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2439 if (ret)
2440 return ret;
24da0016 2441
3b113a1e
AL		 2442 page_idx = (dm->dev_addr -
2443 pci_resource_start(dm_db->dev->pdev, 0) -
2444 MLX5_CAP64_DEV_MEM(dm_db->dev,
2445 memic_bar_start_addr)) >>
2446 PAGE_SHIFT;
25c13324
AL		 2447 bitmap_clear(ctx->dm_pages, page_idx,
2448 DIV_ROUND_UP(dm->size, PAGE_SIZE));
2449 break;
2450 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2451 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2452 ret = mlx5_cmd_dealloc_sw_icm(dm_db, dm->type, dm->size,
2453 ctx->devx_uid, dm->dev_addr,
2454 dm->icm_dm.obj_id);
2455 if (ret)
2456 return ret;
3b113a1e
AL		 2457 break;
2458 default:
2459 return -EOPNOTSUPP;
2460 }
24da0016
AL		 2461
2462 kfree(dm);
2463
2464 return 0;
2465}
2466
ff23dfa1 2467static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
e126ba97 2468{
21a428a0
LR		 2469 struct mlx5_ib_pd *pd = to_mpd(ibpd);
2470 struct ib_device *ibdev = ibpd->device;
e126ba97 2471 struct mlx5_ib_alloc_pd_resp resp;
e126ba97 2472 int err;
a1069c1c
YH		 2473 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2474 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
2475 u16 uid = 0;
ff23dfa1
SR		 2476 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2477 udata, struct mlx5_ib_ucontext, ibucontext);
e126ba97 2478
ff23dfa1 2479 uid = context ? context->devx_uid : 0;
a1069c1c
YH		 2480 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2481 MLX5_SET(alloc_pd_in, in, uid, uid);
2482 err = mlx5_cmd_exec(to_mdev(ibdev)->mdev, in, sizeof(in),
2483 out, sizeof(out));
21a428a0
LR		 2484 if (err)
2485 return err;
e126ba97 2486
a1069c1c
YH		 2487 pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2488 pd->uid = uid;
ff23dfa1 2489 if (udata) {
e126ba97
EC		 2490 resp.pdn = pd->pdn;
2491 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
a1069c1c 2492 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
21a428a0 2493 return -EFAULT;
e126ba97 2494 }
e126ba97
EC		 2495 }
2496
21a428a0 2497 return 0;
e126ba97
EC		 2498}
2499
c4367a26 2500static void mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
e126ba97
EC		 2501{
2502 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2503 struct mlx5_ib_pd *mpd = to_mpd(pd);
2504
a1069c1c 2505 mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
e126ba97
EC		 2506}
2507
466fa6d2
MG		 2508enum {
2509 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2510 MATCH_CRITERIA_ENABLE_MISC_BIT,
71c6e863
AL		 2511 MATCH_CRITERIA_ENABLE_INNER_BIT,
2512 MATCH_CRITERIA_ENABLE_MISC2_BIT
466fa6d2
MG		 2513};
2514
2515#define HEADER_IS_ZERO(match_criteria, headers) \
2516 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2517 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 2518
466fa6d2 2519static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 2520{
466fa6d2 2521 u8 match_criteria_enable;
038d2ef8 2522
466fa6d2
MG		 2523 match_criteria_enable =
2524 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2525 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2526 match_criteria_enable |=
2527 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2528 MATCH_CRITERIA_ENABLE_MISC_BIT;
2529 match_criteria_enable |=
2530 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2531 MATCH_CRITERIA_ENABLE_INNER_BIT;
71c6e863
AL		 2532 match_criteria_enable |=
2533 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2534 MATCH_CRITERIA_ENABLE_MISC2_BIT;
466fa6d2
MG		 2535
2536 return match_criteria_enable;
038d2ef8
MG		 2537}
2538
6113cc44 2539static int set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
ca0d4753 2540{
6113cc44
MG		 2541 u8 entry_mask;
2542 u8 entry_val;
2543 int err = 0;
2544
2545 if (!mask)
2546 goto out;
2547
2548 entry_mask = MLX5_GET(fte_match_set_lyr_2_4, outer_c,
2549 ip_protocol);
2550 entry_val = MLX5_GET(fte_match_set_lyr_2_4, outer_v,
2551 ip_protocol);
2552 if (!entry_mask) {
2553 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2554 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2555 goto out;
2556 }
2557 /* Don't override existing ip protocol */
2558 if (mask != entry_mask || val != entry_val)
2559 err = -EINVAL;
2560out:
2561 return err;
038d2ef8
MG		 2562}
2563
37da2a03 2564static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2d1e697e
MR		 2565 bool inner)
2566{
2567 if (inner) {
2568 MLX5_SET(fte_match_set_misc,
2569 misc_c, inner_ipv6_flow_label, mask);
2570 MLX5_SET(fte_match_set_misc,
2571 misc_v, inner_ipv6_flow_label, val);
2572 } else {
2573 MLX5_SET(fte_match_set_misc,
2574 misc_c, outer_ipv6_flow_label, mask);
2575 MLX5_SET(fte_match_set_misc,
2576 misc_v, outer_ipv6_flow_label, val);
2577 }
2578}
2579
ca0d4753
MG		 2580static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2581{
2582 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2583 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2584 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2585 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2586}
2587
71c6e863
AL		 2588static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2589{
2590 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2591 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2592 return -EOPNOTSUPP;
2593
2594 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2595 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2596 return -EOPNOTSUPP;
2597
2598 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2599 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2600 return -EOPNOTSUPP;
2601
2602 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2603 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2604 return -EOPNOTSUPP;
2605
2606 return 0;
2607}
2608
c47ac6ae
MG		 2609#define LAST_ETH_FIELD vlan_tag
2610#define LAST_IB_FIELD sl
ca0d4753 2611#define LAST_IPV4_FIELD tos
466fa6d2 2612#define LAST_IPV6_FIELD traffic_class
c47ac6ae 2613#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 2614#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 2615#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 2616#define LAST_DROP_FIELD size
3b3233fb 2617#define LAST_COUNTERS_FIELD counters
c47ac6ae
MG		 2618
2619/* Field is the last supported field */
2620#define FIELDS_NOT_SUPPORTED(filter, field)\
2621 memchr_inv((void *)&filter.field +\
2622 sizeof(filter.field), 0,\
2623 sizeof(filter) -\
2624 offsetof(typeof(filter), field) -\
2625 sizeof(filter.field))
2626
2ea26203
MB		 2627int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
2628 bool is_egress,
2629 struct mlx5_flow_act *action)
802c2125 2630{
802c2125
AY		 2631
2632 switch (maction->ib_action.type) {
2633 case IB_FLOW_ACTION_ESP:
501f14e3
MB		 2634 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2635 MLX5_FLOW_CONTEXT_ACTION_DECRYPT))
2636 return -EINVAL;
802c2125
AY		 2637 /* Currently only AES_GCM keymat is supported by the driver */
2638 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2ea26203 2639 action->action |= is_egress ?
802c2125
AY		 2640 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2641 MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2642 return 0;
b1085be3
MB		 2643 case IB_FLOW_ACTION_UNSPECIFIED:
2644 if (maction->flow_action_raw.sub_type ==
2645 MLX5_IB_FLOW_ACTION_MODIFY_HEADER) {
501f14e3
MB		 2646 if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2647 return -EINVAL;
b1085be3
MB		 2648 action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2649 action->modify_id = maction->flow_action_raw.action_id;
2650 return 0;
2651 }
10a30896
MB		 2652 if (maction->flow_action_raw.sub_type ==
2653 MLX5_IB_FLOW_ACTION_DECAP) {
501f14e3
MB		 2654 if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP)
2655 return -EINVAL;
10a30896
MB		 2656 action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2657 return 0;
2658 }
e806f932
MB		 2659 if (maction->flow_action_raw.sub_type ==
2660 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) {
501f14e3
MB		 2661 if (action->action &
2662 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT)
2663 return -EINVAL;
e806f932
MB		 2664 action->action |=
2665 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
2666 action->reformat_id =
2667 maction->flow_action_raw.action_id;
2668 return 0;
2669 }
b1085be3 2670 /* fall through */
802c2125
AY		 2671 default:
2672 return -EOPNOTSUPP;
2673 }
2674}
2675
bb0ee7dc
JL		 2676static int parse_flow_attr(struct mlx5_core_dev *mdev,
2677 struct mlx5_flow_spec *spec,
2678 const union ib_flow_spec *ib_spec,
802c2125 2679 const struct ib_flow_attr *flow_attr,
71c6e863 2680 struct mlx5_flow_act *action, u32 prev_type)
038d2ef8 2681{
bb0ee7dc
JL		 2682 struct mlx5_flow_context *flow_context = &spec->flow_context;
2683 u32 *match_c = spec->match_criteria;
2684 u32 *match_v = spec->match_value;
466fa6d2
MG		 2685 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2686 misc_parameters);
2687 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2688 misc_parameters);
71c6e863
AL		 2689 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2690 misc_parameters_2);
2691 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2692 misc_parameters_2);
2d1e697e
MR		 2693 void *headers_c;
2694 void *headers_v;
19cc7524 2695 int match_ipv;
802c2125 2696 int ret;
2d1e697e
MR		 2697
2698 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2699 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2700 inner_headers);
2701 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2702 inner_headers);
19cc7524
AL		 2703 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2704 ft_field_support.inner_ip_version);
2d1e697e
MR		 2705 } else {
2706 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2707 outer_headers);
2708 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2709 outer_headers);
19cc7524
AL		 2710 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2711 ft_field_support.outer_ip_version);
2d1e697e 2712 }
466fa6d2 2713
2d1e697e 2714 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 2715 case IB_FLOW_SPEC_ETH:
c47ac6ae 2716 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 2717 return -EOPNOTSUPP;
038d2ef8 2718
2d1e697e 2719 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2720 dmac_47_16),
2721 ib_spec->eth.mask.dst_mac);
2d1e697e 2722 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2723 dmac_47_16),
2724 ib_spec->eth.val.dst_mac);
2725
2d1e697e 2726 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 2727 smac_47_16),
2728 ib_spec->eth.mask.src_mac);
2d1e697e 2729 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 2730 smac_47_16),
2731 ib_spec->eth.val.src_mac);
2732
038d2ef8 2733 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 2734 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 2735 cvlan_tag, 1);
2d1e697e 2736 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 2737 cvlan_tag, 1);
038d2ef8 2738
2d1e697e 2739 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2740 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 2741 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2742 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2743
2d1e697e 2744 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2745 first_cfi,
2746 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 2747 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2748 first_cfi,
2749 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2750
2d1e697e 2751 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2752 first_prio,
2753 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 2754 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2755 first_prio,
2756 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2757 }
2d1e697e 2758 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2759 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 2760 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2761 ethertype, ntohs(ib_spec->eth.val.ether_type));
2762 break;
2763 case IB_FLOW_SPEC_IPV4:
c47ac6ae 2764 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 2765 return -EOPNOTSUPP;
038d2ef8 2766
19cc7524
AL		 2767 if (match_ipv) {
2768 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2769 ip_version, 0xf);
2770 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2771 ip_version, MLX5_FS_IPV4_VERSION);
19cc7524
AL		 2772 } else {
2773 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2774 ethertype, 0xffff);
2775 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2776 ethertype, ETH_P_IP);
2777 }
038d2ef8 2778
2d1e697e 2779 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2780 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2781 &ib_spec->ipv4.mask.src_ip,
2782 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 2783 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2784 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2785 &ib_spec->ipv4.val.src_ip,
2786 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 2787 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2788 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2789 &ib_spec->ipv4.mask.dst_ip,
2790 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 2791 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2792 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2793 &ib_spec->ipv4.val.dst_ip,
2794 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 2795
2d1e697e 2796 set_tos(headers_c, headers_v,
ca0d4753
MG		 2797 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2798
6113cc44
MG		 2799 if (set_proto(headers_c, headers_v,
2800 ib_spec->ipv4.mask.proto,
2801 ib_spec->ipv4.val.proto))
2802 return -EINVAL;
038d2ef8 2803 break;
026bae0c 2804 case IB_FLOW_SPEC_IPV6:
c47ac6ae 2805 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 2806 return -EOPNOTSUPP;
026bae0c 2807
19cc7524
AL		 2808 if (match_ipv) {
2809 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2810 ip_version, 0xf);
2811 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2812 ip_version, MLX5_FS_IPV6_VERSION);
19cc7524
AL		 2813 } else {
2814 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2815 ethertype, 0xffff);
2816 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2817 ethertype, ETH_P_IPV6);
2818 }
026bae0c 2819
2d1e697e 2820 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2821 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2822 &ib_spec->ipv6.mask.src_ip,
2823 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2824 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2825 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2826 &ib_spec->ipv6.val.src_ip,
2827 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2828 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2829 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2830 &ib_spec->ipv6.mask.dst_ip,
2831 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2832 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2833 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2834 &ib_spec->ipv6.val.dst_ip,
2835 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2836
2d1e697e 2837 set_tos(headers_c, headers_v,
466fa6d2
MG		 2838 ib_spec->ipv6.mask.traffic_class,
2839 ib_spec->ipv6.val.traffic_class);
2840
6113cc44
MG		 2841 if (set_proto(headers_c, headers_v,
2842 ib_spec->ipv6.mask.next_hdr,
2843 ib_spec->ipv6.val.next_hdr))
2844 return -EINVAL;
466fa6d2 2845
2d1e697e
MR		 2846 set_flow_label(misc_params_c, misc_params_v,
2847 ntohl(ib_spec->ipv6.mask.flow_label),
2848 ntohl(ib_spec->ipv6.val.flow_label),
2849 ib_spec->type & IB_FLOW_SPEC_INNER);
802c2125
AY		 2850 break;
2851 case IB_FLOW_SPEC_ESP:
2852 if (ib_spec->esp.mask.seq)
2853 return -EOPNOTSUPP;
2d1e697e 2854
802c2125
AY		 2855 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2856 ntohl(ib_spec->esp.mask.spi));
2857 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2858 ntohl(ib_spec->esp.val.spi));
026bae0c 2859 break;
038d2ef8 2860 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2861 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2862 LAST_TCP_UDP_FIELD))
1ffd3a26 2863 return -EOPNOTSUPP;
038d2ef8 2864
6113cc44
MG		 2865 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_TCP))
2866 return -EINVAL;
038d2ef8 2867
2d1e697e 2868 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2869 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2870 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2871 ntohs(ib_spec->tcp_udp.val.src_port));
2872
2d1e697e 2873 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2874 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2875 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2876 ntohs(ib_spec->tcp_udp.val.dst_port));
2877 break;
2878 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2879 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2880 LAST_TCP_UDP_FIELD))
1ffd3a26 2881 return -EOPNOTSUPP;
038d2ef8 2882
6113cc44
MG		 2883 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_UDP))
2884 return -EINVAL;
038d2ef8 2885
2d1e697e 2886 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2887 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2888 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2889 ntohs(ib_spec->tcp_udp.val.src_port));
2890
2d1e697e 2891 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2892 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2893 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2894 ntohs(ib_spec->tcp_udp.val.dst_port));
2895 break;
da2f22ae
AL		 2896 case IB_FLOW_SPEC_GRE:
2897 if (ib_spec->gre.mask.c_ks_res0_ver)
2898 return -EOPNOTSUPP;
2899
6113cc44
MG		 2900 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_GRE))
2901 return -EINVAL;
2902
da2f22ae
AL		 2903 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2904 0xff);
2905 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2906 IPPROTO_GRE);
2907
2908 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
a93b632c 2909 ntohs(ib_spec->gre.mask.protocol));
da2f22ae
AL		 2910 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2911 ntohs(ib_spec->gre.val.protocol));
2912
2913 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
5886a96a 2914 gre_key.nvgre.hi),
da2f22ae
AL		 2915 &ib_spec->gre.mask.key,
2916 sizeof(ib_spec->gre.mask.key));
2917 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
5886a96a 2918 gre_key.nvgre.hi),
da2f22ae
AL		 2919 &ib_spec->gre.val.key,
2920 sizeof(ib_spec->gre.val.key));
2921 break;
71c6e863
AL		 2922 case IB_FLOW_SPEC_MPLS:
2923 switch (prev_type) {
2924 case IB_FLOW_SPEC_UDP:
2925 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2926 ft_field_support.outer_first_mpls_over_udp),
2927 &ib_spec->mpls.mask.tag))
2928 return -EOPNOTSUPP;
2929
2930 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2931 outer_first_mpls_over_udp),
2932 &ib_spec->mpls.val.tag,
2933 sizeof(ib_spec->mpls.val.tag));
2934 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2935 outer_first_mpls_over_udp),
2936 &ib_spec->mpls.mask.tag,
2937 sizeof(ib_spec->mpls.mask.tag));
2938 break;
2939 case IB_FLOW_SPEC_GRE:
2940 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2941 ft_field_support.outer_first_mpls_over_gre),
2942 &ib_spec->mpls.mask.tag))
2943 return -EOPNOTSUPP;
2944
2945 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2946 outer_first_mpls_over_gre),
2947 &ib_spec->mpls.val.tag,
2948 sizeof(ib_spec->mpls.val.tag));
2949 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2950 outer_first_mpls_over_gre),
2951 &ib_spec->mpls.mask.tag,
2952 sizeof(ib_spec->mpls.mask.tag));
2953 break;
2954 default:
2955 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2956 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2957 ft_field_support.inner_first_mpls),
2958 &ib_spec->mpls.mask.tag))
2959 return -EOPNOTSUPP;
2960
2961 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2962 inner_first_mpls),
2963 &ib_spec->mpls.val.tag,
2964 sizeof(ib_spec->mpls.val.tag));
2965 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2966 inner_first_mpls),
2967 &ib_spec->mpls.mask.tag,
2968 sizeof(ib_spec->mpls.mask.tag));
2969 } else {
2970 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2971 ft_field_support.outer_first_mpls),
2972 &ib_spec->mpls.mask.tag))
2973 return -EOPNOTSUPP;
2974
2975 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2976 outer_first_mpls),
2977 &ib_spec->mpls.val.tag,
2978 sizeof(ib_spec->mpls.val.tag));
2979 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2980 outer_first_mpls),
2981 &ib_spec->mpls.mask.tag,
2982 sizeof(ib_spec->mpls.mask.tag));
2983 }
2984 }
2985 break;
ffb30d8f
MR		 2986 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2987 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2988 LAST_TUNNEL_FIELD))
1ffd3a26 2989 return -EOPNOTSUPP;
ffb30d8f
MR		 2990
2991 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2992 ntohl(ib_spec->tunnel.mask.tunnel_id));
2993 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2994 ntohl(ib_spec->tunnel.val.tunnel_id));
2995 break;
2ac693f9
MR		 2996 case IB_FLOW_SPEC_ACTION_TAG:
2997 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2998 LAST_FLOW_TAG_FIELD))
2999 return -EOPNOTSUPP;
3000 if (ib_spec->flow_tag.tag_id >= BIT(24))
3001 return -EINVAL;
3002
bb0ee7dc
JL		 3003 flow_context->flow_tag = ib_spec->flow_tag.tag_id;
3004 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
2ac693f9 3005 break;
a22ed86c
SS		 3006 case IB_FLOW_SPEC_ACTION_DROP:
3007 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
3008 LAST_DROP_FIELD))
3009 return -EOPNOTSUPP;
075572d4 3010 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
a22ed86c 3011 break;
802c2125 3012 case IB_FLOW_SPEC_ACTION_HANDLE:
2ea26203
MB		 3013 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act),
3014 flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action);
802c2125
AY		 3015 if (ret)
3016 return ret;
3017 break;
3b3233fb
RS		 3018 case IB_FLOW_SPEC_ACTION_COUNT:
3019 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
3020 LAST_COUNTERS_FIELD))
3021 return -EOPNOTSUPP;
3022
3023 /* for now support only one counters spec per flow */
3024 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
3025 return -EINVAL;
3026
3027 action->counters = ib_spec->flow_count.counters;
3028 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3029 break;
038d2ef8
MG		 3030 default:
3031 return -EINVAL;
3032 }
3033
3034 return 0;
3035}
3036
3037/* If a flow could catch both multicast and unicast packets,
3038 * it won't fall into the multicast flow steering table and this rule
3039 * could steal other multicast packets.
3040 */
a550ddfc 3041static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
038d2ef8 3042{
81e30880 3043 union ib_flow_spec *flow_spec;
038d2ef8
MG		 3044
3045 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 3046 ib_attr->num_of_specs < 1)
3047 return false;
3048
81e30880
YH		 3049 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
3050 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
3051 struct ib_flow_spec_ipv4 *ipv4_spec;
3052
3053 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
3054 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
3055 return true;
3056
038d2ef8 3057 return false;
81e30880
YH		 3058 }
3059
3060 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
3061 struct ib_flow_spec_eth *eth_spec;
3062
3063 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
3064 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
3065 is_multicast_ether_addr(eth_spec->val.dst_mac);
3066 }
038d2ef8 3067
81e30880 3068 return false;
038d2ef8
MG		 3069}
3070
802c2125
AY		 3071enum valid_spec {
3072 VALID_SPEC_INVALID,
3073 VALID_SPEC_VALID,
3074 VALID_SPEC_NA,
3075};
3076
3077static enum valid_spec
3078is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
3079 const struct mlx5_flow_spec *spec,
3080 const struct mlx5_flow_act *flow_act,
3081 bool egress)
3082{
3083 const u32 *match_c = spec->match_criteria;
3084 bool is_crypto =
3085 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
3086 MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
3087 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
3088 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
3089
3090 /*
3091 * Currently only crypto is supported in egress, when regular egress
3092 * rules would be supported, always return VALID_SPEC_NA.
3093 */
3094 if (!is_crypto)
78dd0c43 3095 return VALID_SPEC_NA;
802c2125
AY		 3096
3097 return is_crypto && is_ipsec &&
bb0ee7dc
JL		 3098 (!egress || (!is_drop &&
3099 !(spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG))) ?
802c2125
AY		 3100 VALID_SPEC_VALID : VALID_SPEC_INVALID;
3101}
3102
3103static bool is_valid_spec(struct mlx5_core_dev *mdev,
3104 const struct mlx5_flow_spec *spec,
3105 const struct mlx5_flow_act *flow_act,
3106 bool egress)
3107{
3108 /* We curretly only support ipsec egress flow */
3109 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
3110}
3111
19cc7524
AL		 3112static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
3113 const struct ib_flow_attr *flow_attr,
0f750966 3114 bool check_inner)
038d2ef8
MG		 3115{
3116 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 3117 int match_ipv = check_inner ?
3118 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3119 ft_field_support.inner_ip_version) :
3120 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3121 ft_field_support.outer_ip_version);
0f750966
AL		 3122 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
3123 bool ipv4_spec_valid, ipv6_spec_valid;
3124 unsigned int ip_spec_type = 0;
3125 bool has_ethertype = false;
038d2ef8 3126 unsigned int spec_index;
0f750966
AL		 3127 bool mask_valid = true;
3128 u16 eth_type = 0;
3129 bool type_valid;
038d2ef8
MG		 3130
3131 /* Validate that ethertype is correct */
3132 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 3133 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 3134 ib_spec->eth.mask.ether_type) {
0f750966
AL		 3135 mask_valid = (ib_spec->eth.mask.ether_type ==
3136 htons(0xffff));
3137 has_ethertype = true;
3138 eth_type = ntohs(ib_spec->eth.val.ether_type);
3139 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
3140 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
3141 ip_spec_type = ib_spec->type;
038d2ef8
MG		 3142 }
3143 ib_spec = (void *)ib_spec + ib_spec->size;
3144 }
0f750966
AL		 3145
3146 type_valid = (!has_ethertype) || (!ip_spec_type);
3147 if (!type_valid && mask_valid) {
3148 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
3149 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
3150 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
3151 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 3152
3153 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
3154 (((eth_type == ETH_P_MPLS_UC) ||
3155 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 3156 }
3157
3158 return type_valid;
3159}
3160
19cc7524
AL		 3161static bool is_valid_attr(struct mlx5_core_dev *mdev,
3162 const struct ib_flow_attr *flow_attr)
0f750966 3163{
19cc7524
AL		 3164 return is_valid_ethertype(mdev, flow_attr, false) &&
3165 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 3166}
3167
3168static void put_flow_table(struct mlx5_ib_dev *dev,
3169 struct mlx5_ib_flow_prio *prio, bool ft_added)
3170{
3171 prio->refcount -= !!ft_added;
3172 if (!prio->refcount) {
3173 mlx5_destroy_flow_table(prio->flow_table);
3174 prio->flow_table = NULL;
3175 }
3176}
3177
3b3233fb
RS		 3178static void counters_clear_description(struct ib_counters *counters)
3179{
3180 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3181
3182 mutex_lock(&mcounters->mcntrs_mutex);
3183 kfree(mcounters->counters_data);
3184 mcounters->counters_data = NULL;
3185 mcounters->cntrs_max_index = 0;
3186 mutex_unlock(&mcounters->mcntrs_mutex);
3187}
3188
038d2ef8
MG		 3189static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
3190{
038d2ef8
MG		 3191 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
3192 struct mlx5_ib_flow_handler,
3193 ibflow);
3194 struct mlx5_ib_flow_handler *iter, *tmp;
d4be3f44 3195 struct mlx5_ib_dev *dev = handler->dev;
038d2ef8 3196
9a4ca38d 3197 mutex_lock(&dev->flow_db->lock);
038d2ef8
MG		 3198
3199 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 3200 mlx5_del_flow_rules(iter->rule);
cc0e5d42 3201 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 3202 list_del(&iter->list);
3203 kfree(iter);
3204 }
3205
74491de9 3206 mlx5_del_flow_rules(handler->rule);
5497adc6 3207 put_flow_table(dev, handler->prio, true);
3b3233fb
RS		 3208 if (handler->ibcounters &&
3209 atomic_read(&handler->ibcounters->usecnt) == 1)
3210 counters_clear_description(handler->ibcounters);
038d2ef8 3211
3b3233fb 3212 mutex_unlock(&dev->flow_db->lock);
d4be3f44
YH		 3213 if (handler->flow_matcher)
3214 atomic_dec(&handler->flow_matcher->usecnt);
038d2ef8
MG		 3215 kfree(handler);
3216
3217 return 0;
3218}
3219
35d19011
MG		 3220static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
3221{
3222 priority *= 2;
3223 if (!dont_trap)
3224 priority++;
3225 return priority;
3226}
3227
cc0e5d42
MG		 3228enum flow_table_type {
3229 MLX5_IB_FT_RX,
3230 MLX5_IB_FT_TX
3231};
3232
00b7c2ab
MG		 3233#define MLX5_FS_MAX_TYPES 6
3234#define MLX5_FS_MAX_ENTRIES BIT(16)
d4be3f44
YH		 3235
3236static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns,
3237 struct mlx5_ib_flow_prio *prio,
3238 int priority,
4adda112
MB		 3239 int num_entries, int num_groups,
3240 u32 flags)
d4be3f44
YH		 3241{
3242 struct mlx5_flow_table *ft;
3243
3244 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3245 num_entries,
3246 num_groups,
4adda112 3247 0, flags);
d4be3f44
YH		 3248 if (IS_ERR(ft))
3249 return ERR_CAST(ft);
3250
3251 prio->flow_table = ft;
3252 prio->refcount = 0;
3253 return prio;
3254}
3255
038d2ef8 3256static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 3257 struct ib_flow_attr *flow_attr,
3258 enum flow_table_type ft_type)
038d2ef8 3259{
35d19011 3260 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 3261 struct mlx5_flow_namespace *ns = NULL;
3262 struct mlx5_ib_flow_prio *prio;
3263 struct mlx5_flow_table *ft;
dac388ef 3264 int max_table_size;
038d2ef8
MG		 3265 int num_entries;
3266 int num_groups;
cecae747 3267 bool esw_encap;
4adda112 3268 u32 flags = 0;
038d2ef8 3269 int priority;
038d2ef8 3270
dac388ef
MG		 3271 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3272 log_max_ft_size));
cecae747
MG		 3273 esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
3274 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
038d2ef8 3275 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
78dd0c43
MB		 3276 enum mlx5_flow_namespace_type fn_type;
3277
3278 if (flow_is_multicast_only(flow_attr) &&
3279 !dont_trap)
038d2ef8
MG		 3280 priority = MLX5_IB_FLOW_MCAST_PRIO;
3281 else
35d19011
MG		 3282 priority = ib_prio_to_core_prio(flow_attr->priority,
3283 dont_trap);
78dd0c43
MB		 3284 if (ft_type == MLX5_IB_FT_RX) {
3285 fn_type = MLX5_FLOW_NAMESPACE_BYPASS;
3286 prio = &dev->flow_db->prios[priority];
cecae747 3287 if (!dev->is_rep && !esw_encap &&
4adda112
MB		 3288 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3289 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
cecae747 3290 if (!dev->is_rep && !esw_encap &&
5c2db53f
MB		 3291 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3292 reformat_l3_tunnel_to_l2))
3293 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
78dd0c43
MB		 3294 } else {
3295 max_table_size =
3296 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3297 log_max_ft_size));
3298 fn_type = MLX5_FLOW_NAMESPACE_EGRESS;
3299 prio = &dev->flow_db->egress_prios[priority];
cecae747 3300 if (!dev->is_rep && !esw_encap &&
4adda112
MB		 3301 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3302 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
78dd0c43
MB		 3303 }
3304 ns = mlx5_get_flow_namespace(dev->mdev, fn_type);
038d2ef8
MG		 3305 num_entries = MLX5_FS_MAX_ENTRIES;
3306 num_groups = MLX5_FS_MAX_TYPES;
038d2ef8
MG		 3307 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3308 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3309 ns = mlx5_get_flow_namespace(dev->mdev,
3310 MLX5_FLOW_NAMESPACE_LEFTOVERS);
3311 build_leftovers_ft_param(&priority,
3312 &num_entries,
3313 &num_groups);
9a4ca38d 3314 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 3315 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3316 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3317 allow_sniffer_and_nic_rx_shared_tir))
3318 return ERR_PTR(-ENOTSUPP);
3319
3320 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3321 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3322 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3323
9a4ca38d 3324 prio = &dev->flow_db->sniffer[ft_type];
cc0e5d42
MG		 3325 priority = 0;
3326 num_entries = 1;
3327 num_groups = 1;
038d2ef8
MG		 3328 }
3329
3330 if (!ns)
3331 return ERR_PTR(-ENOTSUPP);
3332
3b70508a 3333 max_table_size = min_t(int, num_entries, max_table_size);
dac388ef 3334
038d2ef8 3335 ft = prio->flow_table;
d4be3f44 3336 if (!ft)
3b70508a 3337 return _get_prio(ns, prio, priority, max_table_size, num_groups,
4adda112 3338 flags);
038d2ef8 3339
d4be3f44 3340 return prio;
038d2ef8
MG		 3341}
3342
a550ddfc
YH		 3343static void set_underlay_qp(struct mlx5_ib_dev *dev,
3344 struct mlx5_flow_spec *spec,
3345 u32 underlay_qpn)
3346{
3347 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3348 spec->match_criteria,
3349 misc_parameters);
3350 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3351 misc_parameters);
3352
3353 if (underlay_qpn &&
3354 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3355 ft_field_support.bth_dst_qp)) {
3356 MLX5_SET(fte_match_set_misc,
3357 misc_params_v, bth_dst_qp, underlay_qpn);
3358 MLX5_SET(fte_match_set_misc,
3359 misc_params_c, bth_dst_qp, 0xffffff);
3360 }
3361}
3362
5e95af5f
RS		 3363static int read_flow_counters(struct ib_device *ibdev,
3364 struct mlx5_read_counters_attr *read_attr)
3365{
3366 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3367 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3368
3369 return mlx5_fc_query(dev->mdev, fc,
3370 &read_attr->out[IB_COUNTER_PACKETS],
3371 &read_attr->out[IB_COUNTER_BYTES]);
3372}
3373
3374/* flow counters currently expose two counters packets and bytes */
3375#define FLOW_COUNTERS_NUM 2
3b3233fb
RS		 3376static int counters_set_description(struct ib_counters *counters,
3377 enum mlx5_ib_counters_type counters_type,
3378 struct mlx5_ib_flow_counters_desc *desc_data,
3379 u32 ncounters)
3380{
3381 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3382 u32 cntrs_max_index = 0;
3383 int i;
3384
3385 if (counters_type != MLX5_IB_COUNTERS_FLOW)
3386 return -EINVAL;
3387
3388 /* init the fields for the object */
3389 mcounters->type = counters_type;
5e95af5f
RS		 3390 mcounters->read_counters = read_flow_counters;
3391 mcounters->counters_num = FLOW_COUNTERS_NUM;
3b3233fb
RS		 3392 mcounters->ncounters = ncounters;
3393 /* each counter entry have both description and index pair */
3394 for (i = 0; i < ncounters; i++) {
3395 if (desc_data[i].description > IB_COUNTER_BYTES)
3396 return -EINVAL;
3397
3398 if (cntrs_max_index <= desc_data[i].index)
3399 cntrs_max_index = desc_data[i].index + 1;
3400 }
3401
3402 mutex_lock(&mcounters->mcntrs_mutex);
3403 mcounters->counters_data = desc_data;
3404 mcounters->cntrs_max_index = cntrs_max_index;
3405 mutex_unlock(&mcounters->mcntrs_mutex);
3406
3407 return 0;
3408}
3409
3410#define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3411static int flow_counters_set_data(struct ib_counters *ibcounters,
3412 struct mlx5_ib_create_flow *ucmd)
3413{
3414 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3415 struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3416 struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3417 bool hw_hndl = false;
3418 int ret = 0;
3419
3420 if (ucmd && ucmd->ncounters_data != 0) {
3421 cntrs_data = ucmd->data;
3422 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3423 return -EINVAL;
3424
3425 desc_data = kcalloc(cntrs_data->ncounters,
3426 sizeof(*desc_data),
3427 GFP_KERNEL);
3428 if (!desc_data)
3429 return -ENOMEM;
3430
3431 if (copy_from_user(desc_data,
3432 u64_to_user_ptr(cntrs_data->counters_data),
3433 sizeof(*desc_data) * cntrs_data->ncounters)) {
3434 ret = -EFAULT;
3435 goto free;
3436 }
3437 }
3438
3439 if (!mcounters->hw_cntrs_hndl) {
3440 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3441 to_mdev(ibcounters->device)->mdev, false);
e31abf76 3442 if (IS_ERR(mcounters->hw_cntrs_hndl)) {
3443 ret = PTR_ERR(mcounters->hw_cntrs_hndl);
3b3233fb
RS		 3444 goto free;
3445 }
3446 hw_hndl = true;
3447 }
3448
3449 if (desc_data) {
3450 /* counters already bound to at least one flow */
3451 if (mcounters->cntrs_max_index) {
3452 ret = -EINVAL;
3453 goto free_hndl;
3454 }
3455
3456 ret = counters_set_description(ibcounters,
3457 MLX5_IB_COUNTERS_FLOW,
3458 desc_data,
3459 cntrs_data->ncounters);
3460 if (ret)
3461 goto free_hndl;
3462
3463 } else if (!mcounters->cntrs_max_index) {
3464 /* counters not bound yet, must have udata passed */
3465 ret = -EINVAL;
3466 goto free_hndl;
3467 }
3468
3469 return 0;
3470
3471free_hndl:
3472 if (hw_hndl) {
3473 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3474 mcounters->hw_cntrs_hndl);
3475 mcounters->hw_cntrs_hndl = NULL;
3476 }
3477free:
3478 kfree(desc_data);
3479 return ret;
3480}
3481
669ff1e3
JL		 3482static void mlx5_ib_set_rule_source_port(struct mlx5_ib_dev *dev,
3483 struct mlx5_flow_spec *spec,
3484 struct mlx5_eswitch_rep *rep)
3485{
3486 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
3487 void *misc;
3488
3489 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
3490 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3491 misc_parameters_2);
3492
3493 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
3494 mlx5_eswitch_get_vport_metadata_for_match(esw,
3495 rep->vport));
3496 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3497 misc_parameters_2);
3498
3499 MLX5_SET_TO_ONES(fte_match_set_misc2, misc, metadata_reg_c_0);
3500 } else {
3501 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3502 misc_parameters);
3503
3504 MLX5_SET(fte_match_set_misc, misc, source_port, rep->vport);
3505
3506 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3507 misc_parameters);
3508
3509 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3510 }
3511}
3512
a550ddfc
YH		 3513static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3514 struct mlx5_ib_flow_prio *ft_prio,
3515 const struct ib_flow_attr *flow_attr,
3516 struct mlx5_flow_destination *dst,
3b3233fb
RS		 3517 u32 underlay_qpn,
3518 struct mlx5_ib_create_flow *ucmd)
038d2ef8
MG		 3519{
3520 struct mlx5_flow_table *ft = ft_prio->flow_table;
3521 struct mlx5_ib_flow_handler *handler;
bb0ee7dc 3522 struct mlx5_flow_act flow_act = {};
c5bb1730 3523 struct mlx5_flow_spec *spec;
3b3233fb
RS		 3524 struct mlx5_flow_destination dest_arr[2] = {};
3525 struct mlx5_flow_destination *rule_dst = dest_arr;
dd063d0e 3526 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 3527 unsigned int spec_index;
71c6e863 3528 u32 prev_type = 0;
038d2ef8 3529 int err = 0;
3b3233fb 3530 int dest_num = 0;
802c2125 3531 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
038d2ef8 3532
19cc7524 3533 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 3534 return ERR_PTR(-EINVAL);
3535
6a4d00be 3536 if (dev->is_rep && is_egress)
78dd0c43
MB		 3537 return ERR_PTR(-EINVAL);
3538
1b9a07ee 3539 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 3540 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 3541 if (!handler || !spec) {
038d2ef8
MG		 3542 err = -ENOMEM;
3543 goto free;
3544 }
3545
3546 INIT_LIST_HEAD(&handler->list);
3b3233fb
RS		 3547 if (dst) {
3548 memcpy(&dest_arr[0], dst, sizeof(*dst));
3549 dest_num++;
3550 }
038d2ef8
MG		 3551
3552 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
bb0ee7dc 3553 err = parse_flow_attr(dev->mdev, spec,
71c6e863
AL		 3554 ib_flow, flow_attr, &flow_act,
3555 prev_type);
038d2ef8
MG		 3556 if (err < 0)
3557 goto free;
3558
71c6e863 3559 prev_type = ((union ib_flow_spec *)ib_flow)->type;
038d2ef8
MG		 3560 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3561 }
3562
a550ddfc
YH		 3563 if (!flow_is_multicast_only(flow_attr))
3564 set_underlay_qp(dev, spec, underlay_qpn);
3565
6a4d00be 3566 if (dev->is_rep) {
669ff1e3 3567 struct mlx5_eswitch_rep *rep;
018a94ee 3568
669ff1e3
JL		 3569 rep = dev->port[flow_attr->port - 1].rep;
3570 if (!rep) {
6a4d00be
MB		 3571 err = -EINVAL;
3572 goto free;
3573 }
669ff1e3
JL		 3574
3575 mlx5_ib_set_rule_source_port(dev, spec, rep);
018a94ee
MB		 3576 }
3577
466fa6d2 3578 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
802c2125
AY		 3579
3580 if (is_egress &&
3581 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3582 err = -EINVAL;
3583 goto free;
3584 }
3585
3b3233fb 3586 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
171c7625
MB		 3587 struct mlx5_ib_mcounters *mcounters;
3588
3b3233fb
RS		 3589 err = flow_counters_set_data(flow_act.counters, ucmd);
3590 if (err)
3591 goto free;
3592
171c7625 3593 mcounters = to_mcounters(flow_act.counters);
3b3233fb
RS		 3594 handler->ibcounters = flow_act.counters;
3595 dest_arr[dest_num].type =
3596 MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625
MB		 3597 dest_arr[dest_num].counter_id =
3598 mlx5_fc_id(mcounters->hw_cntrs_hndl);
3b3233fb
RS		 3599 dest_num++;
3600 }
3601
075572d4 3602 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3b3233fb
RS		 3603 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) {
3604 rule_dst = NULL;
3605 dest_num = 0;
3606 }
a22ed86c 3607 } else {
802c2125
AY		 3608 if (is_egress)
3609 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3610 else
3611 flow_act.action |=
3b3233fb 3612 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
802c2125 3613 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
a22ed86c 3614 }
2ac693f9 3615
bb0ee7dc 3616 if ((spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG) &&
2ac693f9
MR		 3617 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3618 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3619 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
bb0ee7dc 3620 spec->flow_context.flow_tag, flow_attr->type);
2ac693f9
MR		 3621 err = -EINVAL;
3622 goto free;
3623 }
74491de9 3624 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 3625 &flow_act,
a22ed86c 3626 rule_dst, dest_num);
038d2ef8
MG		 3627
3628 if (IS_ERR(handler->rule)) {
3629 err = PTR_ERR(handler->rule);
3630 goto free;
3631 }
3632
d9d4980a 3633 ft_prio->refcount++;
5497adc6 3634 handler->prio = ft_prio;
d4be3f44 3635 handler->dev = dev;
038d2ef8
MG		 3636
3637 ft_prio->flow_table = ft;
3638free:
3b3233fb
RS		 3639 if (err && handler) {
3640 if (handler->ibcounters &&
3641 atomic_read(&handler->ibcounters->usecnt) == 1)
3642 counters_clear_description(handler->ibcounters);
038d2ef8 3643 kfree(handler);
3b3233fb 3644 }
c5bb1730 3645 kvfree(spec);
038d2ef8
MG		 3646 return err ? ERR_PTR(err) : handler;
3647}
3648
a550ddfc
YH		 3649static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3650 struct mlx5_ib_flow_prio *ft_prio,
3651 const struct ib_flow_attr *flow_attr,
3652 struct mlx5_flow_destination *dst)
3653{
3b3233fb 3654 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
a550ddfc
YH		 3655}
3656
35d19011
MG		 3657static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3658 struct mlx5_ib_flow_prio *ft_prio,
3659 struct ib_flow_attr *flow_attr,
3660 struct mlx5_flow_destination *dst)
3661{
3662 struct mlx5_ib_flow_handler *handler_dst = NULL;
3663 struct mlx5_ib_flow_handler *handler = NULL;
3664
3665 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3666 if (!IS_ERR(handler)) {
3667 handler_dst = create_flow_rule(dev, ft_prio,
3668 flow_attr, dst);
3669 if (IS_ERR(handler_dst)) {
74491de9 3670 mlx5_del_flow_rules(handler->rule);
d9d4980a 3671 ft_prio->refcount--;
35d19011
MG		 3672 kfree(handler);
3673 handler = handler_dst;
3674 } else {
3675 list_add(&handler_dst->list, &handler->list);
3676 }
3677 }
3678
3679 return handler;
3680}
038d2ef8
MG		 3681enum {
3682 LEFTOVERS_MC,
3683 LEFTOVERS_UC,
3684};
3685
3686static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3687 struct mlx5_ib_flow_prio *ft_prio,
3688 struct ib_flow_attr *flow_attr,
3689 struct mlx5_flow_destination *dst)
3690{
3691 struct mlx5_ib_flow_handler *handler_ucast = NULL;
3692 struct mlx5_ib_flow_handler *handler = NULL;
3693
3694 static struct {
3695 struct ib_flow_attr flow_attr;
3696 struct ib_flow_spec_eth eth_flow;
3697 } leftovers_specs[] = {
3698 [LEFTOVERS_MC] = {
3699 .flow_attr = {
3700 .num_of_specs = 1,
3701 .size = sizeof(leftovers_specs[0])
3702 },
3703 .eth_flow = {
3704 .type = IB_FLOW_SPEC_ETH,
3705 .size = sizeof(struct ib_flow_spec_eth),
3706 .mask = {.dst_mac = {0x1} },
3707 .val = {.dst_mac = {0x1} }
3708 }
3709 },
3710 [LEFTOVERS_UC] = {
3711 .flow_attr = {
3712 .num_of_specs = 1,
3713 .size = sizeof(leftovers_specs[0])
3714 },
3715 .eth_flow = {
3716 .type = IB_FLOW_SPEC_ETH,
3717 .size = sizeof(struct ib_flow_spec_eth),
3718 .mask = {.dst_mac = {0x1} },
3719 .val = {.dst_mac = {} }
3720 }
3721 }
3722 };
3723
3724 handler = create_flow_rule(dev, ft_prio,
3725 &leftovers_specs[LEFTOVERS_MC].flow_attr,
3726 dst);
3727 if (!IS_ERR(handler) &&
3728 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3729 handler_ucast = create_flow_rule(dev, ft_prio,
3730 &leftovers_specs[LEFTOVERS_UC].flow_attr,
3731 dst);
3732 if (IS_ERR(handler_ucast)) {
74491de9 3733 mlx5_del_flow_rules(handler->rule);
d9d4980a 3734 ft_prio->refcount--;
038d2ef8
MG		 3735 kfree(handler);
3736 handler = handler_ucast;
3737 } else {
3738 list_add(&handler_ucast->list, &handler->list);
3739 }
3740 }
3741
3742 return handler;
3743}
3744
cc0e5d42
MG		 3745static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3746 struct mlx5_ib_flow_prio *ft_rx,
3747 struct mlx5_ib_flow_prio *ft_tx,
3748 struct mlx5_flow_destination *dst)
3749{
3750 struct mlx5_ib_flow_handler *handler_rx;
3751 struct mlx5_ib_flow_handler *handler_tx;
3752 int err;
3753 static const struct ib_flow_attr flow_attr = {
3754 .num_of_specs = 0,
3755 .size = sizeof(flow_attr)
3756 };
3757
3758 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3759 if (IS_ERR(handler_rx)) {
3760 err = PTR_ERR(handler_rx);
3761 goto err;
3762 }
3763
3764 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3765 if (IS_ERR(handler_tx)) {
3766 err = PTR_ERR(handler_tx);
3767 goto err_tx;
3768 }
3769
3770 list_add(&handler_tx->list, &handler_rx->list);
3771
3772 return handler_rx;
3773
3774err_tx:
74491de9 3775 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 3776 ft_rx->refcount--;
3777 kfree(handler_rx);
3778err:
3779 return ERR_PTR(err);
3780}
3781
038d2ef8
MG		 3782static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3783 struct ib_flow_attr *flow_attr,
59082a32
MB		 3784 int domain,
3785 struct ib_udata *udata)
038d2ef8
MG		 3786{
3787 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 3788 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 3789 struct mlx5_ib_flow_handler *handler = NULL;
3790 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 3791 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8 3792 struct mlx5_ib_flow_prio *ft_prio;
802c2125 3793 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3b3233fb
RS		 3794 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3795 size_t min_ucmd_sz, required_ucmd_sz;
038d2ef8 3796 int err;
a550ddfc 3797 int underlay_qpn;
038d2ef8 3798
3b3233fb
RS		 3799 if (udata && udata->inlen) {
3800 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3801 sizeof(ucmd_hdr.reserved);
3802 if (udata->inlen < min_ucmd_sz)
3803 return ERR_PTR(-EOPNOTSUPP);
3804
3805 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3806 if (err)
3807 return ERR_PTR(err);
3808
3809 /* currently supports only one counters data */
3810 if (ucmd_hdr.ncounters_data > 1)
3811 return ERR_PTR(-EINVAL);
3812
3813 required_ucmd_sz = min_ucmd_sz +
3814 sizeof(struct mlx5_ib_flow_counters_data) *
3815 ucmd_hdr.ncounters_data;
3816 if (udata->inlen > required_ucmd_sz &&
3817 !ib_is_udata_cleared(udata, required_ucmd_sz,
3818 udata->inlen - required_ucmd_sz))
3819 return ERR_PTR(-EOPNOTSUPP);
3820
3821 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3822 if (!ucmd)
3823 return ERR_PTR(-ENOMEM);
3824
3825 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
299eafee
GS		 3826 if (err)
3827 goto free_ucmd;
3b3233fb 3828 }
59082a32 3829
299eafee
GS		 3830 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) {
3831 err = -ENOMEM;
3832 goto free_ucmd;
3833 }
038d2ef8
MG		 3834
3835 if (domain != IB_FLOW_DOMAIN_USER ||
508562d6 3836 flow_attr->port > dev->num_ports ||
802c2125 3837 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
299eafee
GS		 3838 IB_FLOW_ATTR_FLAGS_EGRESS))) {
3839 err = -EINVAL;
3840 goto free_ucmd;
3841 }
802c2125
AY		 3842
3843 if (is_egress &&
3844 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
299eafee
GS		 3845 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3846 err = -EINVAL;
3847 goto free_ucmd;
3848 }
038d2ef8
MG		 3849
3850 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
299eafee
GS		 3851 if (!dst) {
3852 err = -ENOMEM;
3853 goto free_ucmd;
3854 }
038d2ef8 3855
9a4ca38d 3856 mutex_lock(&dev->flow_db->lock);
038d2ef8 3857
802c2125
AY		 3858 ft_prio = get_flow_table(dev, flow_attr,
3859 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
038d2ef8
MG		 3860 if (IS_ERR(ft_prio)) {
3861 err = PTR_ERR(ft_prio);
3862 goto unlock;
3863 }
cc0e5d42
MG		 3864 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3865 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3866 if (IS_ERR(ft_prio_tx)) {
3867 err = PTR_ERR(ft_prio_tx);
3868 ft_prio_tx = NULL;
3869 goto destroy_ft;
3870 }
3871 }
038d2ef8 3872
802c2125
AY		 3873 if (is_egress) {
3874 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3875 } else {
3876 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3877 if (mqp->flags & MLX5_IB_QP_RSS)
3878 dst->tir_num = mqp->rss_qp.tirn;
3879 else
3880 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3881 }
038d2ef8
MG		 3882
3883 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 3884 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3885 handler = create_dont_trap_rule(dev, ft_prio,
3886 flow_attr, dst);
3887 } else {
a550ddfc
YH		 3888 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3889 mqp->underlay_qpn : 0;
3890 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3b3233fb 3891 dst, underlay_qpn, ucmd);
35d19011 3892 }
038d2ef8
MG		 3893 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3894 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3895 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3896 dst);
cc0e5d42
MG		 3897 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3898 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 3899 } else {
3900 err = -EINVAL;
3901 goto destroy_ft;
3902 }
3903
3904 if (IS_ERR(handler)) {
3905 err = PTR_ERR(handler);
3906 handler = NULL;
3907 goto destroy_ft;
3908 }
3909
9a4ca38d 3910 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3911 kfree(dst);
3b3233fb 3912 kfree(ucmd);
038d2ef8
MG		 3913
3914 return &handler->ibflow;
3915
3916destroy_ft:
3917 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 3918 if (ft_prio_tx)
3919 put_flow_table(dev, ft_prio_tx, false);
038d2ef8 3920unlock:
9a4ca38d 3921 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3922 kfree(dst);
299eafee 3923free_ucmd:
3b3233fb 3924 kfree(ucmd);
038d2ef8
MG		 3925 return ERR_PTR(err);
3926}
3927
b47fd4ff
MB		 3928static struct mlx5_ib_flow_prio *
3929_get_flow_table(struct mlx5_ib_dev *dev,
3930 struct mlx5_ib_flow_matcher *fs_matcher,
3931 bool mcast)
d4be3f44 3932{
d4be3f44 3933 struct mlx5_flow_namespace *ns = NULL;
13a43765
MB		 3934 struct mlx5_ib_flow_prio *prio = NULL;
3935 int max_table_size = 0;
cecae747 3936 bool esw_encap;
b47fd4ff
MB		 3937 u32 flags = 0;
3938 int priority;
3939
13a43765
MB		 3940 if (mcast)
3941 priority = MLX5_IB_FLOW_MCAST_PRIO;
3942 else
3943 priority = ib_prio_to_core_prio(fs_matcher->priority, false);
3944
cecae747
MG		 3945 esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
3946 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
b47fd4ff
MB		 3947 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) {
3948 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3949 log_max_ft_size));
cecae747 3950 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap) && !esw_encap)
b47fd4ff
MB		 3951 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3952 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
cecae747
MG		 3953 reformat_l3_tunnel_to_l2) &&
3954 !esw_encap)
b47fd4ff 3955 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
13a43765
MB		 3956 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS) {
3957 max_table_size = BIT(
3958 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, log_max_ft_size));
cecae747 3959 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat) && !esw_encap)
b47fd4ff 3960 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
13a43765
MB		 3961 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB) {
3962 max_table_size = BIT(
3963 MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, log_max_ft_size));
09d985be
MG		 3964 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, decap) && esw_encap)
3965 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3966 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, reformat_l3_tunnel_to_l2) &&
3967 esw_encap)
3968 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
13a43765 3969 priority = FDB_BYPASS_PATH;
b47fd4ff 3970 }
d4be3f44 3971
3b70508a 3972 max_table_size = min_t(int, max_table_size, MLX5_FS_MAX_ENTRIES);
d4be3f44 3973
b47fd4ff 3974 ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type);
d4be3f44
YH		 3975 if (!ns)
3976 return ERR_PTR(-ENOTSUPP);
3977
b47fd4ff
MB		 3978 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS)
3979 prio = &dev->flow_db->prios[priority];
13a43765 3980 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS)
b47fd4ff 3981 prio = &dev->flow_db->egress_prios[priority];
13a43765
MB		 3982 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB)
3983 prio = &dev->flow_db->fdb;
3984
3985 if (!prio)
3986 return ERR_PTR(-EINVAL);
d4be3f44
YH		 3987
3988 if (prio->flow_table)
3989 return prio;
3990
3b70508a 3991 return _get_prio(ns, prio, priority, max_table_size,
b47fd4ff 3992 MLX5_FS_MAX_TYPES, flags);
d4be3f44
YH		 3993}
3994
3995static struct mlx5_ib_flow_handler *
3996_create_raw_flow_rule(struct mlx5_ib_dev *dev,
3997 struct mlx5_ib_flow_prio *ft_prio,
3998 struct mlx5_flow_destination *dst,
3999 struct mlx5_ib_flow_matcher *fs_matcher,
bb0ee7dc 4000 struct mlx5_flow_context *flow_context,
b823dd6d 4001 struct mlx5_flow_act *flow_act,
bfc5d839
MB		 4002 void *cmd_in, int inlen,
4003 int dst_num)
d4be3f44
YH		 4004{
4005 struct mlx5_ib_flow_handler *handler;
d4be3f44
YH		 4006 struct mlx5_flow_spec *spec;
4007 struct mlx5_flow_table *ft = ft_prio->flow_table;
4008 int err = 0;
4009
4010 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
4011 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
4012 if (!handler || !spec) {
4013 err = -ENOMEM;
4014 goto free;
4015 }
4016
4017 INIT_LIST_HEAD(&handler->list);
4018
4019 memcpy(spec->match_value, cmd_in, inlen);
4020 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params,
4021 fs_matcher->mask_len);
4022 spec->match_criteria_enable = fs_matcher->match_criteria_enable;
bb0ee7dc 4023 spec->flow_context = *flow_context;
d4be3f44 4024
d4be3f44 4025 handler->rule = mlx5_add_flow_rules(ft, spec,
bfc5d839 4026 flow_act, dst, dst_num);
d4be3f44
YH		 4027
4028 if (IS_ERR(handler->rule)) {
4029 err = PTR_ERR(handler->rule);
4030 goto free;
4031 }
4032
4033 ft_prio->refcount++;
4034 handler->prio = ft_prio;
4035 handler->dev = dev;
4036 ft_prio->flow_table = ft;
4037
4038free:
4039 if (err)
4040 kfree(handler);
4041 kvfree(spec);
4042 return err ? ERR_PTR(err) : handler;
4043}
4044
4045static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher,
4046 void *match_v)
4047{
4048 void *match_c;
4049 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4;
4050 void *dmac, *dmac_mask;
4051 void *ipv4, *ipv4_mask;
4052
4053 if (!(fs_matcher->match_criteria_enable &
4054 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT)))
4055 return false;
4056
4057 match_c = fs_matcher->matcher_mask.match_params;
4058 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v,
4059 outer_headers);
4060 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c,
4061 outer_headers);
4062
4063 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4064 dmac_47_16);
4065 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4066 dmac_47_16);
4067
4068 if (is_multicast_ether_addr(dmac) &&
4069 is_multicast_ether_addr(dmac_mask))
4070 return true;
4071
4072 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4073 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4074
4075 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4076 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4077
4078 if (ipv4_is_multicast(*(__be32 *)(ipv4)) &&
4079 ipv4_is_multicast(*(__be32 *)(ipv4_mask)))
4080 return true;
4081
4082 return false;
4083}
4084
32269441
YH		 4085struct mlx5_ib_flow_handler *
4086mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
4087 struct mlx5_ib_flow_matcher *fs_matcher,
bb0ee7dc 4088 struct mlx5_flow_context *flow_context,
b823dd6d 4089 struct mlx5_flow_act *flow_act,
bfc5d839 4090 u32 counter_id,
32269441
YH		 4091 void *cmd_in, int inlen, int dest_id,
4092 int dest_type)
4093{
d4be3f44
YH		 4094 struct mlx5_flow_destination *dst;
4095 struct mlx5_ib_flow_prio *ft_prio;
d4be3f44 4096 struct mlx5_ib_flow_handler *handler;
bfc5d839 4097 int dst_num = 0;
d4be3f44
YH		 4098 bool mcast;
4099 int err;
4100
4101 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL)
4102 return ERR_PTR(-EOPNOTSUPP);
4103
4104 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO)
4105 return ERR_PTR(-ENOMEM);
4106
8e8aa145 4107 dst = kcalloc(2, sizeof(*dst), GFP_KERNEL);
d4be3f44
YH		 4108 if (!dst)
4109 return ERR_PTR(-ENOMEM);
4110
4111 mcast = raw_fs_is_multicast(fs_matcher, cmd_in);
4112 mutex_lock(&dev->flow_db->lock);
4113
b47fd4ff 4114 ft_prio = _get_flow_table(dev, fs_matcher, mcast);
d4be3f44
YH		 4115 if (IS_ERR(ft_prio)) {
4116 err = PTR_ERR(ft_prio);
4117 goto unlock;
4118 }
4119
6346f0bf 4120 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
bfc5d839
MB		 4121 dst[dst_num].type = dest_type;
4122 dst[dst_num].tir_num = dest_id;
b823dd6d 4123 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
a7ee18bd 4124 } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) {
bfc5d839
MB		 4125 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
4126 dst[dst_num].ft_num = dest_id;
b823dd6d 4127 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
a7ee18bd 4128 } else {
bfc5d839 4129 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_PORT;
a7ee18bd 4130 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
6346f0bf
YH		 4131 }
4132
bfc5d839
MB		 4133 dst_num++;
4134
4135 if (flow_act->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
4136 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
4137 dst[dst_num].counter_id = counter_id;
4138 dst_num++;
4139 }
4140
bb0ee7dc
JL		 4141 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher,
4142 flow_context, flow_act,
bfc5d839 4143 cmd_in, inlen, dst_num);
d4be3f44
YH		 4144
4145 if (IS_ERR(handler)) {
4146 err = PTR_ERR(handler);
4147 goto destroy_ft;
4148 }
4149
4150 mutex_unlock(&dev->flow_db->lock);
4151 atomic_inc(&fs_matcher->usecnt);
4152 handler->flow_matcher = fs_matcher;
4153
4154 kfree(dst);
4155
4156 return handler;
4157
4158destroy_ft:
4159 put_flow_table(dev, ft_prio, false);
4160unlock:
4161 mutex_unlock(&dev->flow_db->lock);
4162 kfree(dst);
4163
4164 return ERR_PTR(err);
32269441
YH		 4165}
4166
c6475a0b
AY		 4167static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
4168{
4169 u32 flags = 0;
4170
4171 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
4172 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
4173
4174 return flags;
4175}
4176
4177#define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
4178static struct ib_flow_action *
4179mlx5_ib_create_flow_action_esp(struct ib_device *device,
4180 const struct ib_flow_action_attrs_esp *attr,
4181 struct uverbs_attr_bundle *attrs)
4182{
4183 struct mlx5_ib_dev *mdev = to_mdev(device);
4184 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
4185 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
4186 struct mlx5_ib_flow_action *action;
4187 u64 action_flags;
4188 u64 flags;
4189 int err = 0;
4190
bccd0622
JG		 4191 err = uverbs_get_flags64(
4192 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
4193 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1));
4194 if (err)
4195 return ERR_PTR(err);
c6475a0b
AY		 4196
4197 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
4198
4199 /* We current only support a subset of the standard features. Only a
4200 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
4201 * (with overlap). Full offload mode isn't supported.
4202 */
4203 if (!attr->keymat || attr->replay || attr->encap ||
4204 attr->spi || attr->seq || attr->tfc_pad ||
4205 attr->hard_limit_pkts ||
4206 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4207 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
4208 return ERR_PTR(-EOPNOTSUPP);
4209
4210 if (attr->keymat->protocol !=
4211 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
4212 return ERR_PTR(-EOPNOTSUPP);
4213
4214 aes_gcm = &attr->keymat->keymat.aes_gcm;
4215
4216 if (aes_gcm->icv_len != 16 ||
4217 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
4218 return ERR_PTR(-EOPNOTSUPP);
4219
4220 action = kmalloc(sizeof(*action), GFP_KERNEL);
4221 if (!action)
4222 return ERR_PTR(-ENOMEM);
4223
4224 action->esp_aes_gcm.ib_flags = attr->flags;
4225 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
4226 sizeof(accel_attrs.keymat.aes_gcm.aes_key));
4227 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
4228 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
4229 sizeof(accel_attrs.keymat.aes_gcm.salt));
4230 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
4231 sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
4232 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
4233 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
4234 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
4235
4236 accel_attrs.esn = attr->esn;
4237 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
4238 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
4239 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4240 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4241
4242 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
4243 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
4244
4245 action->esp_aes_gcm.ctx =
4246 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
4247 if (IS_ERR(action->esp_aes_gcm.ctx)) {
4248 err = PTR_ERR(action->esp_aes_gcm.ctx);
4249 goto err_parse;
4250 }
4251
4252 action->esp_aes_gcm.ib_flags = attr->flags;
4253
4254 return &action->ib_action;
4255
4256err_parse:
4257 kfree(action);
4258 return ERR_PTR(err);
4259}
4260
349705c1
MB		 4261static int
4262mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
4263 const struct ib_flow_action_attrs_esp *attr,
4264 struct uverbs_attr_bundle *attrs)
4265{
4266 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4267 struct mlx5_accel_esp_xfrm_attrs accel_attrs;
4268 int err = 0;
4269
4270 if (attr->keymat || attr->replay || attr->encap ||
4271 attr->spi || attr->seq || attr->tfc_pad ||
4272 attr->hard_limit_pkts ||
4273 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4274 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
4275 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
4276 return -EOPNOTSUPP;
4277
4278 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
4279 * be modified.
4280 */
4281 if (!(maction->esp_aes_gcm.ib_flags &
4282 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
4283 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4284 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
4285 return -EINVAL;
4286
4287 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
4288 sizeof(accel_attrs));
4289
4290 accel_attrs.esn = attr->esn;
4291 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4292 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4293 else
4294 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4295
4296 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
4297 &accel_attrs);
4298 if (err)
4299 return err;
4300
4301 maction->esp_aes_gcm.ib_flags &=
4302 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4303 maction->esp_aes_gcm.ib_flags |=
4304 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4305
4306 return 0;
4307}
4308
c6475a0b
AY		 4309static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
4310{
4311 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4312
4313 switch (action->type) {
4314 case IB_FLOW_ACTION_ESP:
4315 /*
4316 * We only support aes_gcm by now, so we implicitly know this is
4317 * the underline crypto.
4318 */
4319 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
4320 break;
b4749bf2
MB		 4321 case IB_FLOW_ACTION_UNSPECIFIED:
4322 mlx5_ib_destroy_flow_action_raw(maction);
4323 break;
c6475a0b
AY		 4324 default:
4325 WARN_ON(true);
4326 break;
4327 }
4328
4329 kfree(maction);
4330 return 0;
4331}
4332
e126ba97
EC		 4333static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4334{
4335 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 4336 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97 4337 int err;
539ec982
YH		 4338 u16 uid;
4339
4340 uid = ibqp->pd ?
4341 to_mpd(ibqp->pd)->uid : 0;
e126ba97 4342
81e30880
YH		 4343 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
4344 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
4345 return -EOPNOTSUPP;
4346 }
4347
539ec982 4348 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
e126ba97
EC		 4349 if (err)
4350 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
4351 ibqp->qp_num, gid->raw);
4352
4353 return err;
4354}
4355
4356static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4357{
4358 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4359 int err;
539ec982 4360 u16 uid;
e126ba97 4361
539ec982
YH		 4362 uid = ibqp->pd ?
4363 to_mpd(ibqp->pd)->uid : 0;
4364 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
e126ba97
EC		 4365 if (err)
4366 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
4367 ibqp->qp_num, gid->raw);
4368
4369 return err;
4370}
4371
4372static int init_node_data(struct mlx5_ib_dev *dev)
4373{
1b5daf11 4374 int err;
e126ba97 4375
1b5daf11 4376 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 4377 if (err)
1b5daf11 4378 return err;
e126ba97 4379
1b5daf11 4380 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 4381
1b5daf11 4382 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 4383}
4384
508a523f
PP		 4385static ssize_t fw_pages_show(struct device *device,
4386 struct device_attribute *attr, char *buf)
e126ba97
EC		 4387{
4388 struct mlx5_ib_dev *dev =
54747231 4389 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
e126ba97 4390
9603b61d 4391 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97 4392}
508a523f 4393static DEVICE_ATTR_RO(fw_pages);
e126ba97 4394
508a523f 4395static ssize_t reg_pages_show(struct device *device,
e126ba97
EC		 4396 struct device_attribute *attr, char *buf)
4397{
4398 struct mlx5_ib_dev *dev =
54747231 4399 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
e126ba97 4400
6aec21f6 4401 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97 4402}
508a523f 4403static DEVICE_ATTR_RO(reg_pages);
e126ba97 4404
508a523f
PP		 4405static ssize_t hca_type_show(struct device *device,
4406 struct device_attribute *attr, char *buf)
e126ba97
EC		 4407{
4408 struct mlx5_ib_dev *dev =
54747231
PP		 4409 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4410
9603b61d 4411 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97 4412}
508a523f 4413static DEVICE_ATTR_RO(hca_type);
e126ba97 4414
508a523f
PP		 4415static ssize_t hw_rev_show(struct device *device,
4416 struct device_attribute *attr, char *buf)
e126ba97
EC		 4417{
4418 struct mlx5_ib_dev *dev =
54747231
PP		 4419 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4420
9603b61d 4421 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97 4422}
508a523f 4423static DEVICE_ATTR_RO(hw_rev);
e126ba97 4424
508a523f
PP		 4425static ssize_t board_id_show(struct device *device,
4426 struct device_attribute *attr, char *buf)
e126ba97
EC		 4427{
4428 struct mlx5_ib_dev *dev =
54747231
PP		 4429 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4430
e126ba97 4431 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 4432 dev->mdev->board_id);
e126ba97 4433}
508a523f 4434static DEVICE_ATTR_RO(board_id);
e126ba97 4435
508a523f
PP		 4436static struct attribute *mlx5_class_attributes[] = {
4437 &dev_attr_hw_rev.attr,
4438 &dev_attr_hca_type.attr,
4439 &dev_attr_board_id.attr,
4440 &dev_attr_fw_pages.attr,
4441 &dev_attr_reg_pages.attr,
4442 NULL,
4443};
e126ba97 4444
508a523f
PP		 4445static const struct attribute_group mlx5_attr_group = {
4446 .attrs = mlx5_class_attributes,
e126ba97
EC		 4447};
4448
7722f47e
HE		 4449static void pkey_change_handler(struct work_struct *work)
4450{
4451 struct mlx5_ib_port_resources *ports =
4452 container_of(work, struct mlx5_ib_port_resources,
4453 pkey_change_work);
4454
4455 mutex_lock(&ports->devr->mutex);
4456 mlx5_ib_gsi_pkey_change(ports->gsi);
4457 mutex_unlock(&ports->devr->mutex);
4458}
4459
89ea94a7
MG		 4460static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
4461{
4462 struct mlx5_ib_qp *mqp;
4463 struct mlx5_ib_cq *send_mcq, *recv_mcq;
4464 struct mlx5_core_cq *mcq;
4465 struct list_head cq_armed_list;
4466 unsigned long flags_qp;
4467 unsigned long flags_cq;
4468 unsigned long flags;
4469
4470 INIT_LIST_HEAD(&cq_armed_list);
4471
4472 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
4473 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
4474 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
4475 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
4476 if (mqp->sq.tail != mqp->sq.head) {
4477 send_mcq = to_mcq(mqp->ibqp.send_cq);
4478 spin_lock_irqsave(&send_mcq->lock, flags_cq);
4479 if (send_mcq->mcq.comp &&
4480 mqp->ibqp.send_cq->comp_handler) {
4481 if (!send_mcq->mcq.reset_notify_added) {
4482 send_mcq->mcq.reset_notify_added = 1;
4483 list_add_tail(&send_mcq->mcq.reset_notify,
4484 &cq_armed_list);
4485 }
4486 }
4487 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
4488 }
4489 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
4490 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
4491 /* no handling is needed for SRQ */
4492 if (!mqp->ibqp.srq) {
4493 if (mqp->rq.tail != mqp->rq.head) {
4494 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
4495 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
4496 if (recv_mcq->mcq.comp &&
4497 mqp->ibqp.recv_cq->comp_handler) {
4498 if (!recv_mcq->mcq.reset_notify_added) {
4499 recv_mcq->mcq.reset_notify_added = 1;
4500 list_add_tail(&recv_mcq->mcq.reset_notify,
4501 &cq_armed_list);
4502 }
4503 }
4504 spin_unlock_irqrestore(&recv_mcq->lock,
4505 flags_cq);
4506 }
4507 }
4508 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
4509 }
4510 /*At that point all inflight post send were put to be executed as of we
4511 * lock/unlock above locks Now need to arm all involved CQs.
4512 */
4513 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4e0e2ea1 4514 mcq->comp(mcq, NULL);
89ea94a7
MG		 4515 }
4516 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
4517}
4518
03404e8a
MG		 4519static void delay_drop_handler(struct work_struct *work)
4520{
4521 int err;
4522 struct mlx5_ib_delay_drop *delay_drop =
4523 container_of(work, struct mlx5_ib_delay_drop,
4524 delay_drop_work);
4525
fe248c3a
MG		 4526 atomic_inc(&delay_drop->events_cnt);
4527
03404e8a
MG		 4528 mutex_lock(&delay_drop->lock);
4529 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
4530 delay_drop->timeout);
4531 if (err) {
4532 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4533 delay_drop->timeout);
4534 delay_drop->activate = false;
4535 }
4536 mutex_unlock(&delay_drop->lock);
4537}
4538
09e574fa
SM		 4539static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4540 struct ib_event *ibev)
4541{
6cfdc7e4
AL		 4542 u8 port = (eqe->data.port.port >> 4) & 0xf;
4543
09e574fa
SM		 4544 switch (eqe->sub_type) {
4545 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
6cfdc7e4
AL		 4546 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4547 IB_LINK_LAYER_ETHERNET)
4548 schedule_work(&ibdev->delay_drop.delay_drop_work);
09e574fa
SM		 4549 break;
4550 default: /* do nothing */
4551 return;
4552 }
4553}
4554
134e9349
SM		 4555static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4556 struct ib_event *ibev)
4557{
4558 u8 port = (eqe->data.port.port >> 4) & 0xf;
4559
4560 ibev->element.port_num = port;
4561
4562 switch (eqe->sub_type) {
4563 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
4564 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
4565 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
4566 /* In RoCE, port up/down events are handled in
4567 * mlx5_netdev_event().
4568 */
4569 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4570 IB_LINK_LAYER_ETHERNET)
4571 return -EINVAL;
4572
4573 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
4574 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
4575 break;
4576
4577 case MLX5_PORT_CHANGE_SUBTYPE_LID:
4578 ibev->event = IB_EVENT_LID_CHANGE;
4579 break;
4580
4581 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
4582 ibev->event = IB_EVENT_PKEY_CHANGE;
4583 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
4584 break;
4585
4586 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
4587 ibev->event = IB_EVENT_GID_CHANGE;
4588 break;
4589
4590 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
4591 ibev->event = IB_EVENT_CLIENT_REREGISTER;
4592 break;
4593 default:
4594 return -EINVAL;
4595 }
4596
4597 return 0;
4598}
4599
d69a24e0 4600static void mlx5_ib_handle_event(struct work_struct *_work)
e126ba97 4601{
d69a24e0
DJ		 4602 struct mlx5_ib_event_work *work =
4603 container_of(_work, struct mlx5_ib_event_work, work);
4604 struct mlx5_ib_dev *ibdev;
e126ba97 4605 struct ib_event ibev;
dbaaff2a 4606 bool fatal = false;
e126ba97 4607
df097a27
SM		 4608 if (work->is_slave) {
4609 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
d69a24e0
DJ		 4610 if (!ibdev)
4611 goto out;
4612 } else {
df097a27 4613 ibdev = work->dev;
d69a24e0
DJ		 4614 }
4615
4616 switch (work->event) {
e126ba97 4617 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 4618 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 4619 mlx5_ib_handle_internal_error(ibdev);
134e9349 4620 ibev.element.port_num = (u8)(unsigned long)work->param;
dbaaff2a 4621 fatal = true;
e126ba97 4622 break;
134e9349
SM		 4623 case MLX5_EVENT_TYPE_PORT_CHANGE:
4624 if (handle_port_change(ibdev, work->param, &ibev))
d69a24e0 4625 goto out;
e126ba97 4626 break;
09e574fa
SM		 4627 case MLX5_EVENT_TYPE_GENERAL_EVENT:
4628 handle_general_event(ibdev, work->param, &ibev);
4629 /* fall through */
bdc37924 4630 default:
03404e8a 4631 goto out;
e126ba97
EC		 4632 }
4633
134e9349 4634 ibev.device = &ibdev->ib_dev;
e126ba97 4635
134e9349
SM		 4636 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
4637 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num);
03404e8a 4638 goto out;
a0c84c32
EC		 4639 }
4640
e126ba97
EC		 4641 if (ibdev->ib_active)
4642 ib_dispatch_event(&ibev);
dbaaff2a
EC		 4643
4644 if (fatal)
4645 ibdev->ib_active = false;
03404e8a 4646out:
d69a24e0
DJ		 4647 kfree(work);
4648}
4649
df097a27
SM		 4650static int mlx5_ib_event(struct notifier_block *nb,
4651 unsigned long event, void *param)
d69a24e0
DJ		 4652{
4653 struct mlx5_ib_event_work *work;
4654
4655 work = kmalloc(sizeof(*work), GFP_ATOMIC);
10bea9c8 4656 if (!work)
df097a27 4657 return NOTIFY_DONE;
d69a24e0 4658
10bea9c8 4659 INIT_WORK(&work->work, mlx5_ib_handle_event);
df097a27
SM		 4660 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
4661 work->is_slave = false;
10bea9c8 4662 work->param = param;
10bea9c8
LR		 4663 work->event = event;
4664
4665 queue_work(mlx5_ib_event_wq, &work->work);
df097a27
SM		 4666
4667 return NOTIFY_OK;
4668}
4669
4670static int mlx5_ib_event_slave_port(struct notifier_block *nb,
4671 unsigned long event, void *param)
4672{
4673 struct mlx5_ib_event_work *work;
4674
4675 work = kmalloc(sizeof(*work), GFP_ATOMIC);
4676 if (!work)
4677 return NOTIFY_DONE;
4678
4679 INIT_WORK(&work->work, mlx5_ib_handle_event);
4680 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
4681 work->is_slave = true;
4682 work->param = param;
4683 work->event = event;
4684 queue_work(mlx5_ib_event_wq, &work->work);
4685
4686 return NOTIFY_OK;
e126ba97
EC		 4687}
4688
c43f1112
MG		 4689static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4690{
4691 struct mlx5_hca_vport_context vport_ctx;
4692 int err;
4693 int port;
4694
a989ea01 4695 for (port = 1; port <= ARRAY_SIZE(dev->mdev->port_caps); port++) {
c43f1112
MG		 4696 dev->mdev->port_caps[port - 1].has_smi = false;
4697 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4698 MLX5_CAP_PORT_TYPE_IB) {
4699 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4700 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4701 port, 0,
4702 &vport_ctx);
4703 if (err) {
4704 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4705 port, err);
4706 return err;
4707 }
4708 dev->mdev->port_caps[port - 1].has_smi =
4709 vport_ctx.has_smi;
4710 } else {
4711 dev->mdev->port_caps[port - 1].has_smi = true;
4712 }
4713 }
4714 }
4715 return 0;
4716}
4717
e126ba97
EC		 4718static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4719{
4720 int port;
4721
508562d6 4722 for (port = 1; port <= dev->num_ports; port++)
e126ba97
EC		 4723 mlx5_query_ext_port_caps(dev, port);
4724}
4725
26628e2d 4726static int __get_port_caps(struct mlx5_ib_dev *dev, u8 port)
e126ba97
EC		 4727{
4728 struct ib_device_attr *dprops = NULL;
4729 struct ib_port_attr *pprops = NULL;
f614fc15 4730 int err = -ENOMEM;
2528e33e 4731 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97 4732
50ba3c18 4733 pprops = kzalloc(sizeof(*pprops), GFP_KERNEL);
e126ba97
EC		 4734 if (!pprops)
4735 goto out;
4736
4737 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4738 if (!dprops)
4739 goto out;
4740
2528e33e 4741 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 4742 if (err) {
4743 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4744 goto out;
4745 }
4746
32f69e4b
DJ		 4747 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4748 if (err) {
4749 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4750 port, err);
4751 goto out;
e126ba97
EC		 4752 }
4753
32f69e4b
DJ		 4754 dev->mdev->port_caps[port - 1].pkey_table_len =
4755 dprops->max_pkeys;
4756 dev->mdev->port_caps[port - 1].gid_table_len =
4757 pprops->gid_tbl_len;
4758 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4759 port, dprops->max_pkeys, pprops->gid_tbl_len);
4760
e126ba97
EC		 4761out:
4762 kfree(pprops);
4763 kfree(dprops);
4764
4765 return err;
4766}
4767
26628e2d
MB		 4768static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4769{
4770 /* For representors use port 1, is this is the only native
4771 * port
4772 */
4773 if (dev->is_rep)
4774 return __get_port_caps(dev, 1);
4775 return __get_port_caps(dev, port);
4776}
4777
e126ba97
EC		 4778static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4779{
4780 int err;
4781
4782 err = mlx5_mr_cache_cleanup(dev);
4783 if (err)
4784 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4785
32927e28 4786 if (dev->umrc.qp)
c4367a26 4787 mlx5_ib_destroy_qp(dev->umrc.qp, NULL);
32927e28
MB		 4788 if (dev->umrc.cq)
4789 ib_free_cq(dev->umrc.cq);
4790 if (dev->umrc.pd)
4791 ib_dealloc_pd(dev->umrc.pd);
e126ba97
EC		 4792}
4793
4794enum {
4795 MAX_UMR_WR = 128,
4796};
4797
4798static int create_umr_res(struct mlx5_ib_dev *dev)
4799{
4800 struct ib_qp_init_attr *init_attr = NULL;
4801 struct ib_qp_attr *attr = NULL;
4802 struct ib_pd *pd;
4803 struct ib_cq *cq;
4804 struct ib_qp *qp;
e126ba97
EC		 4805 int ret;
4806
4807 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4808 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4809 if (!attr || !init_attr) {
4810 ret = -ENOMEM;
4811 goto error_0;
4812 }
4813
ed082d36 4814 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 4815 if (IS_ERR(pd)) {
4816 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4817 ret = PTR_ERR(pd);
4818 goto error_0;
4819 }
4820
add08d76 4821 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 4822 if (IS_ERR(cq)) {
4823 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4824 ret = PTR_ERR(cq);
4825 goto error_2;
4826 }
e126ba97
EC		 4827
4828 init_attr->send_cq = cq;
4829 init_attr->recv_cq = cq;
4830 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4831 init_attr->cap.max_send_wr = MAX_UMR_WR;
4832 init_attr->cap.max_send_sge = 1;
4833 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4834 init_attr->port_num = 1;
4835 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4836 if (IS_ERR(qp)) {
4837 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4838 ret = PTR_ERR(qp);
4839 goto error_3;
4840 }
4841 qp->device = &dev->ib_dev;
4842 qp->real_qp = qp;
4843 qp->uobject = NULL;
4844 qp->qp_type = MLX5_IB_QPT_REG_UMR;
31fde034
MD		 4845 qp->send_cq = init_attr->send_cq;
4846 qp->recv_cq = init_attr->recv_cq;
e126ba97
EC		 4847
4848 attr->qp_state = IB_QPS_INIT;
4849 attr->port_num = 1;
4850 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4851 IB_QP_PORT, NULL);
4852 if (ret) {
4853 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4854 goto error_4;
4855 }
4856
4857 memset(attr, 0, sizeof(*attr));
4858 attr->qp_state = IB_QPS_RTR;
4859 attr->path_mtu = IB_MTU_256;
4860
4861 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4862 if (ret) {
4863 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4864 goto error_4;
4865 }
4866
4867 memset(attr, 0, sizeof(*attr));
4868 attr->qp_state = IB_QPS_RTS;
4869 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4870 if (ret) {
4871 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4872 goto error_4;
4873 }
4874
4875 dev->umrc.qp = qp;
4876 dev->umrc.cq = cq;
e126ba97
EC		 4877 dev->umrc.pd = pd;
4878
4879 sema_init(&dev->umrc.sem, MAX_UMR_WR);
4880 ret = mlx5_mr_cache_init(dev);
4881 if (ret) {
4882 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4883 goto error_4;
4884 }
4885
4886 kfree(attr);
4887 kfree(init_attr);
4888
4889 return 0;
4890
4891error_4:
c4367a26 4892 mlx5_ib_destroy_qp(qp, NULL);
32927e28 4893 dev->umrc.qp = NULL;
e126ba97
EC		 4894
4895error_3:
add08d76 4896 ib_free_cq(cq);
32927e28 4897 dev->umrc.cq = NULL;
e126ba97
EC		 4898
4899error_2:
e126ba97 4900 ib_dealloc_pd(pd);
32927e28 4901 dev->umrc.pd = NULL;
e126ba97
EC		 4902
4903error_0:
4904 kfree(attr);
4905 kfree(init_attr);
4906 return ret;
4907}
4908
6e8484c5
MG		 4909static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4910{
4911 switch (umr_fence_cap) {
4912 case MLX5_CAP_UMR_FENCE_NONE:
4913 return MLX5_FENCE_MODE_NONE;
4914 case MLX5_CAP_UMR_FENCE_SMALL:
4915 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4916 default:
4917 return MLX5_FENCE_MODE_STRONG_ORDERING;
4918 }
4919}
4920
e126ba97
EC		 4921static int create_dev_resources(struct mlx5_ib_resources *devr)
4922{
4923 struct ib_srq_init_attr attr;
4924 struct mlx5_ib_dev *dev;
21a428a0 4925 struct ib_device *ibdev;
bcf4c1ea 4926 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 4927 int port;
e126ba97
EC		 4928 int ret = 0;
4929
4930 dev = container_of(devr, struct mlx5_ib_dev, devr);
21a428a0 4931 ibdev = &dev->ib_dev;
e126ba97 4932
d16e91da
HE		 4933 mutex_init(&devr->mutex);
4934
21a428a0
LR		 4935 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd);
4936 if (!devr->p0)
4937 return -ENOMEM;
4938
4939 devr->p0->device = ibdev;
e126ba97
EC		 4940 devr->p0->uobject = NULL;
4941 atomic_set(&devr->p0->usecnt, 0);
4942
ff23dfa1 4943 ret = mlx5_ib_alloc_pd(devr->p0, NULL);
21a428a0
LR		 4944 if (ret)
4945 goto error0;
4946
e39afe3d
LR		 4947 devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq);
4948 if (!devr->c0) {
4949 ret = -ENOMEM;
e126ba97
EC		 4950 goto error1;
4951 }
e39afe3d
LR		 4952
4953 devr->c0->device = &dev->ib_dev;
e126ba97
EC		 4954 atomic_set(&devr->c0->usecnt, 0);
4955
e39afe3d
LR		 4956 ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL);
4957 if (ret)
4958 goto err_create_cq;
4959
ff23dfa1 4960 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
e126ba97
EC		 4961 if (IS_ERR(devr->x0)) {
4962 ret = PTR_ERR(devr->x0);
4963 goto error2;
4964 }
4965 devr->x0->device = &dev->ib_dev;
4966 devr->x0->inode = NULL;
4967 atomic_set(&devr->x0->usecnt, 0);
4968 mutex_init(&devr->x0->tgt_qp_mutex);
4969 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4970
ff23dfa1 4971 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
e126ba97
EC		 4972 if (IS_ERR(devr->x1)) {
4973 ret = PTR_ERR(devr->x1);
4974 goto error3;
4975 }
4976 devr->x1->device = &dev->ib_dev;
4977 devr->x1->inode = NULL;
4978 atomic_set(&devr->x1->usecnt, 0);
4979 mutex_init(&devr->x1->tgt_qp_mutex);
4980 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4981
4982 memset(&attr, 0, sizeof(attr));
4983 attr.attr.max_sge = 1;
4984 attr.attr.max_wr = 1;
4985 attr.srq_type = IB_SRQT_XRC;
1a56ff6d 4986 attr.ext.cq = devr->c0;
e126ba97
EC		 4987 attr.ext.xrc.xrcd = devr->x0;
4988
68e326de
LR		 4989 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq);
4990 if (!devr->s0) {
4991 ret = -ENOMEM;
e126ba97
EC		 4992 goto error4;
4993 }
68e326de 4994
e126ba97
EC		 4995 devr->s0->device = &dev->ib_dev;
4996 devr->s0->pd = devr->p0;
e126ba97
EC		 4997 devr->s0->srq_type = IB_SRQT_XRC;
4998 devr->s0->ext.xrc.xrcd = devr->x0;
1a56ff6d 4999 devr->s0->ext.cq = devr->c0;
68e326de
LR		 5000 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL);
5001 if (ret)
5002 goto err_create;
5003
e126ba97 5004 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1a56ff6d 5005 atomic_inc(&devr->s0->ext.cq->usecnt);
e126ba97
EC		 5006 atomic_inc(&devr->p0->usecnt);
5007 atomic_set(&devr->s0->usecnt, 0);
5008
4aa17b28
HA		 5009 memset(&attr, 0, sizeof(attr));
5010 attr.attr.max_sge = 1;
5011 attr.attr.max_wr = 1;
5012 attr.srq_type = IB_SRQT_BASIC;
68e326de
LR		 5013 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq);
5014 if (!devr->s1) {
5015 ret = -ENOMEM;
4aa17b28
HA		 5016 goto error5;
5017 }
68e326de 5018
4aa17b28
HA		 5019 devr->s1->device = &dev->ib_dev;
5020 devr->s1->pd = devr->p0;
4aa17b28 5021 devr->s1->srq_type = IB_SRQT_BASIC;
1a56ff6d 5022 devr->s1->ext.cq = devr->c0;
68e326de
LR		 5023
5024 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL);
5025 if (ret)
5026 goto error6;
5027
4aa17b28 5028 atomic_inc(&devr->p0->usecnt);
1a56ff6d 5029 atomic_set(&devr->s1->usecnt, 0);
4aa17b28 5030
7722f47e
HE		 5031 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
5032 INIT_WORK(&devr->ports[port].pkey_change_work,
5033 pkey_change_handler);
5034 devr->ports[port].devr = devr;
5035 }
5036
e126ba97
EC		 5037 return 0;
5038
68e326de
LR		 5039error6:
5040 kfree(devr->s1);
4aa17b28 5041error5:
c4367a26 5042 mlx5_ib_destroy_srq(devr->s0, NULL);
68e326de
LR		 5043err_create:
5044 kfree(devr->s0);
e126ba97 5045error4:
c4367a26 5046 mlx5_ib_dealloc_xrcd(devr->x1, NULL);
e126ba97 5047error3:
c4367a26 5048 mlx5_ib_dealloc_xrcd(devr->x0, NULL);
e126ba97 5049error2:
c4367a26 5050 mlx5_ib_destroy_cq(devr->c0, NULL);
e39afe3d
LR		 5051err_create_cq:
5052 kfree(devr->c0);
e126ba97 5053error1:
c4367a26 5054 mlx5_ib_dealloc_pd(devr->p0, NULL);
e126ba97 5055error0:
21a428a0 5056 kfree(devr->p0);
e126ba97
EC		 5057 return ret;
5058}
5059
5060static void destroy_dev_resources(struct mlx5_ib_resources *devr)
5061{
7722f47e
HE		 5062 int port;
5063
c4367a26 5064 mlx5_ib_destroy_srq(devr->s1, NULL);
68e326de 5065 kfree(devr->s1);
c4367a26 5066 mlx5_ib_destroy_srq(devr->s0, NULL);
68e326de 5067 kfree(devr->s0);
c4367a26
SR		 5068 mlx5_ib_dealloc_xrcd(devr->x0, NULL);
5069 mlx5_ib_dealloc_xrcd(devr->x1, NULL);
5070 mlx5_ib_destroy_cq(devr->c0, NULL);
e39afe3d 5071 kfree(devr->c0);
c4367a26 5072 mlx5_ib_dealloc_pd(devr->p0, NULL);
21a428a0 5073 kfree(devr->p0);
7722f47e
HE		 5074
5075 /* Make sure no change P_Key work items are still executing */
5d8f6a0e 5076 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
7722f47e 5077 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 5078}
5079
b02289b3
AK		 5080static u32 get_core_cap_flags(struct ib_device *ibdev,
5081 struct mlx5_hca_vport_context *rep)
e53505a8
AS		 5082{
5083 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5084 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
5085 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
5086 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
85c7c014 5087 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
e53505a8
AS		 5088 u32 ret = 0;
5089
b02289b3
AK		 5090 if (rep->grh_required)
5091 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
5092
e53505a8 5093 if (ll == IB_LINK_LAYER_INFINIBAND)
b02289b3 5094 return ret | RDMA_CORE_PORT_IBA_IB;
e53505a8 5095
85c7c014 5096 if (raw_support)
b02289b3 5097 ret |= RDMA_CORE_PORT_RAW_PACKET;
72cd5717 5098
e53505a8 5099 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 5100 return ret;
e53505a8
AS		 5101
5102 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 5103 return ret;
e53505a8
AS		 5104
5105 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
5106 ret |= RDMA_CORE_PORT_IBA_ROCE;
5107
5108 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
5109 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
5110
5111 return ret;
5112}
5113
7738613e
IW		 5114static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
5115 struct ib_port_immutable *immutable)
5116{
5117 struct ib_port_attr attr;
ca5b91d6
OG		 5118 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5119 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
b02289b3 5120 struct mlx5_hca_vport_context rep = {0};
7738613e
IW		 5121 int err;
5122
c4550c63 5123 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 5124 if (err)
5125 return err;
5126
b02289b3
AK		 5127 if (ll == IB_LINK_LAYER_INFINIBAND) {
5128 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
5129 &rep);
5130 if (err)
5131 return err;
5132 }
5133
7738613e
IW		 5134 immutable->pkey_tbl_len = attr.pkey_tbl_len;
5135 immutable->gid_tbl_len = attr.gid_tbl_len;
b02289b3 5136 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
ca5b91d6
OG		 5137 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
5138 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 5139
5140 return 0;
5141}
5142
8e6efa3a
MB		 5143static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
5144 struct ib_port_immutable *immutable)
5145{
5146 struct ib_port_attr attr;
5147 int err;
5148
5149 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5150
5151 err = ib_query_port(ibdev, port_num, &attr);
5152 if (err)
5153 return err;
5154
5155 immutable->pkey_tbl_len = attr.pkey_tbl_len;
5156 immutable->gid_tbl_len = attr.gid_tbl_len;
5157 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5158
5159 return 0;
5160}
5161
9abb0d1b 5162static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 5163{
5164 struct mlx5_ib_dev *dev =
5165 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 5166 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
5167 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
5168 fw_rev_sub(dev->mdev));
c7342823
IW		 5169}
5170
45f95acd 5171static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 5172{
5173 struct mlx5_core_dev *mdev = dev->mdev;
5174 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
5175 MLX5_FLOW_NAMESPACE_LAG);
5176 struct mlx5_flow_table *ft;
5177 int err;
5178
7c34ec19 5179 if (!ns || !mlx5_lag_is_roce(mdev))
9ef9c640
AH		 5180 return 0;
5181
5182 err = mlx5_cmd_create_vport_lag(mdev);
5183 if (err)
5184 return err;
5185
5186 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
5187 if (IS_ERR(ft)) {
5188 err = PTR_ERR(ft);
5189 goto err_destroy_vport_lag;
5190 }
5191
9a4ca38d 5192 dev->flow_db->lag_demux_ft = ft;
7c34ec19 5193 dev->lag_active = true;
9ef9c640
AH		 5194 return 0;
5195
5196err_destroy_vport_lag:
5197 mlx5_cmd_destroy_vport_lag(mdev);
5198 return err;
5199}
5200
45f95acd 5201static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 5202{
5203 struct mlx5_core_dev *mdev = dev->mdev;
5204
7c34ec19
AH		 5205 if (dev->lag_active) {
5206 dev->lag_active = false;
5207
9a4ca38d
MB		 5208 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
5209 dev->flow_db->lag_demux_ft = NULL;
9ef9c640
AH		 5210
5211 mlx5_cmd_destroy_vport_lag(mdev);
5212 }
5213}
5214
7fd8aefb 5215static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
d012f5d6
OG		 5216{
5217 int err;
5218
95579e78
MB		 5219 dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event;
5220 err = register_netdevice_notifier(&dev->port[port_num].roce.nb);
d012f5d6 5221 if (err) {
95579e78 5222 dev->port[port_num].roce.nb.notifier_call = NULL;
d012f5d6
OG		 5223 return err;
5224 }
5225
5226 return 0;
5227}
5228
7fd8aefb 5229static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5ec8c83e 5230{
95579e78
MB		 5231 if (dev->port[port_num].roce.nb.notifier_call) {
5232 unregister_netdevice_notifier(&dev->port[port_num].roce.nb);
5233 dev->port[port_num].roce.nb.notifier_call = NULL;
5ec8c83e
AH		 5234 }
5235}
5236
e3f1ed1f 5237static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 5238{
e53505a8
AS		 5239 int err;
5240
ca5b91d6
OG		 5241 if (MLX5_CAP_GEN(dev->mdev, roce)) {
5242 err = mlx5_nic_vport_enable_roce(dev->mdev);
5243 if (err)
8e6efa3a 5244 return err;
ca5b91d6 5245 }
e53505a8 5246
45f95acd 5247 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 5248 if (err)
5249 goto err_disable_roce;
5250
e53505a8
AS		 5251 return 0;
5252
9ef9c640 5253err_disable_roce:
ca5b91d6
OG		 5254 if (MLX5_CAP_GEN(dev->mdev, roce))
5255 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 5256
e53505a8 5257 return err;
fc24fc5e
AS		 5258}
5259
45f95acd 5260static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 5261{
45f95acd 5262 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 5263 if (MLX5_CAP_GEN(dev->mdev, roce))
5264 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 5265}
5266
e1f24a79 5267struct mlx5_ib_counter {
7c16f477
KH		 5268 const char *name;
5269 size_t offset;
5270};
5271
5272#define INIT_Q_COUNTER(_name) \
5273 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
5274
e1f24a79 5275static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 5276 INIT_Q_COUNTER(rx_write_requests),
5277 INIT_Q_COUNTER(rx_read_requests),
5278 INIT_Q_COUNTER(rx_atomic_requests),
5279 INIT_Q_COUNTER(out_of_buffer),
5280};
5281
e1f24a79 5282static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 5283 INIT_Q_COUNTER(out_of_sequence),
5284};
5285
e1f24a79 5286static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 5287 INIT_Q_COUNTER(duplicate_request),
5288 INIT_Q_COUNTER(rnr_nak_retry_err),
5289 INIT_Q_COUNTER(packet_seq_err),
5290 INIT_Q_COUNTER(implied_nak_seq_err),
5291 INIT_Q_COUNTER(local_ack_timeout_err),
5292};
5293
e1f24a79
PP		 5294#define INIT_CONG_COUNTER(_name) \
5295 { .name = #_name, .offset = \
5296 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
5297
5298static const struct mlx5_ib_counter cong_cnts[] = {
5299 INIT_CONG_COUNTER(rp_cnp_ignored),
5300 INIT_CONG_COUNTER(rp_cnp_handled),
5301 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
5302 INIT_CONG_COUNTER(np_cnp_sent),
5303};
5304
58dcb60a
PP		 5305static const struct mlx5_ib_counter extended_err_cnts[] = {
5306 INIT_Q_COUNTER(resp_local_length_error),
5307 INIT_Q_COUNTER(resp_cqe_error),
5308 INIT_Q_COUNTER(req_cqe_error),
5309 INIT_Q_COUNTER(req_remote_invalid_request),
5310 INIT_Q_COUNTER(req_remote_access_errors),
5311 INIT_Q_COUNTER(resp_remote_access_errors),
5312 INIT_Q_COUNTER(resp_cqe_flush_error),
5313 INIT_Q_COUNTER(req_cqe_flush_error),
5314};
5315
9f876f3d
TB		 5316#define INIT_EXT_PPCNT_COUNTER(_name) \
5317 { .name = #_name, .offset = \
5318 MLX5_BYTE_OFF(ppcnt_reg, \
5319 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
5320
5321static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
5322 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
5323};
5324
e1f24a79 5325static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a 5326{
aac4492e 5327 int i;
0837e86a 5328
7c16f477 5329 for (i = 0; i < dev->num_ports; i++) {
921c0f5b 5330 if (dev->port[i].cnts.set_id_valid)
aac4492e
DJ		 5331 mlx5_core_dealloc_q_counter(dev->mdev,
5332 dev->port[i].cnts.set_id);
e1f24a79
PP		 5333 kfree(dev->port[i].cnts.names);
5334 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 5335 }
5336}
5337
e1f24a79
PP		 5338static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
5339 struct mlx5_ib_counters *cnts)
7c16f477
KH		 5340{
5341 u32 num_counters;
5342
5343 num_counters = ARRAY_SIZE(basic_q_cnts);
5344
5345 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
5346 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
5347
5348 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
5349 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 5350
5351 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
5352 num_counters += ARRAY_SIZE(extended_err_cnts);
5353
e1f24a79 5354 cnts->num_q_counters = num_counters;
7c16f477 5355
e1f24a79
PP		 5356 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5357 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
5358 num_counters += ARRAY_SIZE(cong_cnts);
5359 }
9f876f3d
TB		 5360 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5361 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
5362 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
5363 }
e1f24a79
PP		 5364 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
5365 if (!cnts->names)
7c16f477
KH		 5366 return -ENOMEM;
5367
e1f24a79
PP		 5368 cnts->offsets = kcalloc(num_counters,
5369 sizeof(cnts->offsets), GFP_KERNEL);
5370 if (!cnts->offsets)
7c16f477
KH		 5371 goto err_names;
5372
7c16f477
KH		 5373 return 0;
5374
5375err_names:
e1f24a79 5376 kfree(cnts->names);
aac4492e 5377 cnts->names = NULL;
7c16f477
KH		 5378 return -ENOMEM;
5379}
5380
e1f24a79
PP		 5381static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
5382 const char **names,
5383 size_t *offsets)
7c16f477
KH		 5384{
5385 int i;
5386 int j = 0;
5387
5388 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
5389 names[j] = basic_q_cnts[i].name;
5390 offsets[j] = basic_q_cnts[i].offset;
5391 }
5392
5393 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
5394 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
5395 names[j] = out_of_seq_q_cnts[i].name;
5396 offsets[j] = out_of_seq_q_cnts[i].offset;
5397 }
5398 }
5399
5400 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
5401 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
5402 names[j] = retrans_q_cnts[i].name;
5403 offsets[j] = retrans_q_cnts[i].offset;
5404 }
5405 }
e1f24a79 5406
58dcb60a
PP		 5407 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
5408 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
5409 names[j] = extended_err_cnts[i].name;
5410 offsets[j] = extended_err_cnts[i].offset;
5411 }
5412 }
5413
e1f24a79
PP		 5414 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5415 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
5416 names[j] = cong_cnts[i].name;
5417 offsets[j] = cong_cnts[i].offset;
5418 }
5419 }
9f876f3d
TB		 5420
5421 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5422 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
5423 names[j] = ext_ppcnt_cnts[i].name;
5424 offsets[j] = ext_ppcnt_cnts[i].offset;
5425 }
5426 }
0837e86a
MB		 5427}
5428
e1f24a79 5429static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a 5430{
aac4492e 5431 int err = 0;
0837e86a 5432 int i;
aa74be6e
YH		 5433 bool is_shared;
5434
5435 is_shared = MLX5_CAP_GEN(dev->mdev, log_max_uctx) != 0;
0837e86a
MB		 5436
5437 for (i = 0; i < dev->num_ports; i++) {
aac4492e
DJ		 5438 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
5439 if (err)
5440 goto err_alloc;
5441
5442 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
5443 dev->port[i].cnts.offsets);
7c16f477 5444
aa74be6e
YH		 5445 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5446 &dev->port[i].cnts.set_id,
5447 is_shared ?
5448 MLX5_SHARED_RESOURCE_UID : 0);
aac4492e 5449 if (err) {
0837e86a
MB		 5450 mlx5_ib_warn(dev,
5451 "couldn't allocate queue counter for port %d, err %d\n",
aac4492e
DJ		 5452 i + 1, err);
5453 goto err_alloc;
0837e86a 5454 }
aac4492e 5455 dev->port[i].cnts.set_id_valid = true;
0837e86a
MB		 5456 }
5457
5458 return 0;
5459
aac4492e
DJ		 5460err_alloc:
5461 mlx5_ib_dealloc_counters(dev);
5462 return err;
0837e86a
MB		 5463}
5464
0ad17a8f
MB		 5465static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
5466 u8 port_num)
5467{
7c16f477 5468 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5dcecbc9 5469 const struct mlx5_ib_counters *cnts = &dev->port[port_num - 1].cnts;
0ad17a8f
MB		 5470
5471 /* We support only per port stats */
5472 if (port_num == 0)
5473 return NULL;
5474
5dcecbc9
PP		 5475 return rdma_alloc_hw_stats_struct(cnts->names,
5476 cnts->num_q_counters +
5477 cnts->num_cong_counters +
5478 cnts->num_ext_ppcnt_counters,
0ad17a8f
MB		 5479 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5480}
5481
aac4492e 5482static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
5dcecbc9 5483 const struct mlx5_ib_counters *cnts,
318d535c
MZ		 5484 struct rdma_hw_stats *stats,
5485 u16 set_id)
0ad17a8f 5486{
0ad17a8f
MB		 5487 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
5488 void *out;
5489 __be32 val;
e1f24a79 5490 int ret, i;
0ad17a8f 5491
1b9a07ee 5492 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 5493 if (!out)
5494 return -ENOMEM;
5495
318d535c 5496 ret = mlx5_core_query_q_counter(mdev, set_id, 0, out, outlen);
0ad17a8f
MB		 5497 if (ret)
5498 goto free;
5499
5dcecbc9
PP		 5500 for (i = 0; i < cnts->num_q_counters; i++) {
5501 val = *(__be32 *)(out + cnts->offsets[i]);
0ad17a8f
MB		 5502 stats->value[i] = (u64)be32_to_cpu(val);
5503 }
7c16f477 5504
0ad17a8f
MB		 5505free:
5506 kvfree(out);
e1f24a79
PP		 5507 return ret;
5508}
5509
9f876f3d 5510static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
5dcecbc9
PP		 5511 const struct mlx5_ib_counters *cnts,
5512 struct rdma_hw_stats *stats)
9f876f3d 5513{
5dcecbc9 5514 int offset = cnts->num_q_counters + cnts->num_cong_counters;
9f876f3d
TB		 5515 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
5516 int ret, i;
5517 void *out;
5518
5519 out = kvzalloc(sz, GFP_KERNEL);
5520 if (!out)
5521 return -ENOMEM;
5522
5523 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
5524 if (ret)
5525 goto free;
5526
5dcecbc9 5527 for (i = 0; i < cnts->num_ext_ppcnt_counters; i++)
9f876f3d
TB		 5528 stats->value[i + offset] =
5529 be64_to_cpup((__be64 *)(out +
5dcecbc9 5530 cnts->offsets[i + offset]));
9f876f3d
TB		 5531free:
5532 kvfree(out);
5533 return ret;
5534}
5535
e1f24a79
PP		 5536static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
5537 struct rdma_hw_stats *stats,
5538 u8 port_num, int index)
5539{
5540 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5dcecbc9 5541 struct mlx5_ib_counters *cnts = &dev->port[port_num - 1].cnts;
aac4492e 5542 struct mlx5_core_dev *mdev;
e1f24a79 5543 int ret, num_counters;
aac4492e 5544 u8 mdev_port_num;
e1f24a79
PP		 5545
5546 if (!stats)
5547 return -EINVAL;
5548
5dcecbc9
PP		 5549 num_counters = cnts->num_q_counters +
5550 cnts->num_cong_counters +
5551 cnts->num_ext_ppcnt_counters;
aac4492e
DJ		 5552
5553 /* q_counters are per IB device, query the master mdev */
5dcecbc9 5554 ret = mlx5_ib_query_q_counters(dev->mdev, cnts, stats, cnts->set_id);
e1f24a79
PP		 5555 if (ret)
5556 return ret;
e1f24a79 5557
9f876f3d 5558 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5dcecbc9 5559 ret = mlx5_ib_query_ext_ppcnt_counters(dev, cnts, stats);
9f876f3d
TB		 5560 if (ret)
5561 return ret;
5562 }
5563
e1f24a79 5564 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
aac4492e
DJ		 5565 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
5566 &mdev_port_num);
5567 if (!mdev) {
5568 /* If port is not affiliated yet, its in down state
5569 * which doesn't have any counters yet, so it would be
5570 * zero. So no need to read from the HCA.
5571 */
5572 goto done;
5573 }
71a0ff65
MD		 5574 ret = mlx5_lag_query_cong_counters(dev->mdev,
5575 stats->value +
5dcecbc9
PP		 5576 cnts->num_q_counters,
5577 cnts->num_cong_counters,
5578 cnts->offsets +
5579 cnts->num_q_counters);
aac4492e
DJ		 5580
5581 mlx5_ib_put_native_port_mdev(dev, port_num);
e1f24a79
PP		 5582 if (ret)
5583 return ret;
e1f24a79
PP		 5584 }
5585
aac4492e 5586done:
e1f24a79 5587 return num_counters;
0ad17a8f
MB		 5588}
5589
18d422ce
MZ		 5590static struct rdma_hw_stats *
5591mlx5_ib_counter_alloc_stats(struct rdma_counter *counter)
5592{
5593 struct mlx5_ib_dev *dev = to_mdev(counter->device);
5dcecbc9
PP		 5594 const struct mlx5_ib_counters *cnts =
5595 &dev->port[counter->port - 1].cnts;
18d422ce
MZ		 5596
5597 /* Q counters are in the beginning of all counters */
5dcecbc9
PP		 5598 return rdma_alloc_hw_stats_struct(cnts->names,
5599 cnts->num_q_counters,
18d422ce
MZ		 5600 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5601}
5602
5603static int mlx5_ib_counter_update_stats(struct rdma_counter *counter)
5604{
5605 struct mlx5_ib_dev *dev = to_mdev(counter->device);
5dcecbc9 5606 struct mlx5_ib_counters *cnts = &dev->port[counter->port - 1].cnts;
18d422ce 5607
5dcecbc9 5608 return mlx5_ib_query_q_counters(dev->mdev, cnts,
18d422ce
MZ		 5609 counter->stats, counter->id);
5610}
5611
45842fc6
MZ		 5612static int mlx5_ib_counter_bind_qp(struct rdma_counter *counter,
5613 struct ib_qp *qp)
5614{
5615 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5616 u16 cnt_set_id = 0;
5617 int err;
5618
5619 if (!counter->id) {
5620 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5621 &cnt_set_id,
5622 MLX5_SHARED_RESOURCE_UID);
5623 if (err)
5624 return err;
5625 counter->id = cnt_set_id;
5626 }
5627
5628 err = mlx5_ib_qp_set_counter(qp, counter);
5629 if (err)
5630 goto fail_set_counter;
5631
5632 return 0;
5633
5634fail_set_counter:
5635 mlx5_core_dealloc_q_counter(dev->mdev, cnt_set_id);
5636 counter->id = 0;
5637
5638 return err;
5639}
5640
5641static int mlx5_ib_counter_unbind_qp(struct ib_qp *qp)
5642{
5643 return mlx5_ib_qp_set_counter(qp, NULL);
5644}
5645
5646static int mlx5_ib_counter_dealloc(struct rdma_counter *counter)
5647{
5648 struct mlx5_ib_dev *dev = to_mdev(counter->device);
5649
5650 return mlx5_core_dealloc_q_counter(dev->mdev, counter->id);
5651}
5652
f6a8a19b
DD		 5653static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num,
5654 enum rdma_netdev_t type,
5655 struct rdma_netdev_alloc_params *params)
693dfd5a
ES		 5656{
5657 if (type != RDMA_NETDEV_IPOIB)
f6a8a19b 5658 return -EOPNOTSUPP;
693dfd5a 5659
f6a8a19b 5660 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
693dfd5a
ES		 5661}
5662
fe248c3a
MG		 5663static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
5664{
5665 if (!dev->delay_drop.dbg)
5666 return;
5667 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
5668 kfree(dev->delay_drop.dbg);
5669 dev->delay_drop.dbg = NULL;
5670}
5671
03404e8a
MG		 5672static void cancel_delay_drop(struct mlx5_ib_dev *dev)
5673{
5674 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5675 return;
5676
5677 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 5678 delay_drop_debugfs_cleanup(dev);
5679}
5680
5681static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5682 size_t count, loff_t *pos)
5683{
5684 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5685 char lbuf[20];
5686 int len;
5687
5688 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5689 return simple_read_from_buffer(buf, count, pos, lbuf, len);
5690}
5691
5692static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5693 size_t count, loff_t *pos)
5694{
5695 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5696 u32 timeout;
5697 u32 var;
5698
5699 if (kstrtouint_from_user(buf, count, 0, &var))
5700 return -EFAULT;
5701
5702 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5703 1000);
5704 if (timeout != var)
5705 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5706 timeout);
5707
5708 delay_drop->timeout = timeout;
5709
5710 return count;
5711}
5712
5713static const struct file_operations fops_delay_drop_timeout = {
5714 .owner = THIS_MODULE,
5715 .open = simple_open,
5716 .write = delay_drop_timeout_write,
5717 .read = delay_drop_timeout_read,
5718};
5719
5720static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5721{
5722 struct mlx5_ib_dbg_delay_drop *dbg;
5723
5724 if (!mlx5_debugfs_root)
5725 return 0;
5726
5727 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
5728 if (!dbg)
5729 return -ENOMEM;
5730
cbafad87
SM		 5731 dev->delay_drop.dbg = dbg;
5732
fe248c3a
MG		 5733 dbg->dir_debugfs =
5734 debugfs_create_dir("delay_drop",
5735 dev->mdev->priv.dbg_root);
5736 if (!dbg->dir_debugfs)
cbafad87 5737 goto out_debugfs;
fe248c3a
MG		 5738
5739 dbg->events_cnt_debugfs =
5740 debugfs_create_atomic_t("num_timeout_events", 0400,
5741 dbg->dir_debugfs,
5742 &dev->delay_drop.events_cnt);
5743 if (!dbg->events_cnt_debugfs)
5744 goto out_debugfs;
5745
5746 dbg->rqs_cnt_debugfs =
5747 debugfs_create_atomic_t("num_rqs", 0400,
5748 dbg->dir_debugfs,
5749 &dev->delay_drop.rqs_cnt);
5750 if (!dbg->rqs_cnt_debugfs)
5751 goto out_debugfs;
5752
5753 dbg->timeout_debugfs =
5754 debugfs_create_file("timeout", 0600,
5755 dbg->dir_debugfs,
5756 &dev->delay_drop,
5757 &fops_delay_drop_timeout);
5758 if (!dbg->timeout_debugfs)
5759 goto out_debugfs;
5760
5761 return 0;
5762
5763out_debugfs:
5764 delay_drop_debugfs_cleanup(dev);
5765 return -ENOMEM;
03404e8a
MG		 5766}
5767
5768static void init_delay_drop(struct mlx5_ib_dev *dev)
5769{
5770 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5771 return;
5772
5773 mutex_init(&dev->delay_drop.lock);
5774 dev->delay_drop.dev = dev;
5775 dev->delay_drop.activate = false;
5776 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5777 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 5778 atomic_set(&dev->delay_drop.rqs_cnt, 0);
5779 atomic_set(&dev->delay_drop.events_cnt, 0);
5780
5781 if (delay_drop_debugfs_init(dev))
5782 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
03404e8a
MG		 5783}
5784
32f69e4b
DJ		 5785/* The mlx5_ib_multiport_mutex should be held when calling this function */
5786static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5787 struct mlx5_ib_multiport_info *mpi)
5788{
5789 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5790 struct mlx5_ib_port *port = &ibdev->port[port_num];
5791 int comps;
5792 int err;
5793 int i;
5794
a9e546e7
PP		 5795 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5796
32f69e4b
DJ		 5797 spin_lock(&port->mp.mpi_lock);
5798 if (!mpi->ibdev) {
5799 spin_unlock(&port->mp.mpi_lock);
5800 return;
5801 }
df097a27
SM		 5802
5803 if (mpi->mdev_events.notifier_call)
5804 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
5805 mpi->mdev_events.notifier_call = NULL;
5806
32f69e4b
DJ		 5807 mpi->ibdev = NULL;
5808
5809 spin_unlock(&port->mp.mpi_lock);
5810 mlx5_remove_netdev_notifier(ibdev, port_num);
5811 spin_lock(&port->mp.mpi_lock);
5812
5813 comps = mpi->mdev_refcnt;
5814 if (comps) {
5815 mpi->unaffiliate = true;
5816 init_completion(&mpi->unref_comp);
5817 spin_unlock(&port->mp.mpi_lock);
5818
5819 for (i = 0; i < comps; i++)
5820 wait_for_completion(&mpi->unref_comp);
5821
5822 spin_lock(&port->mp.mpi_lock);
5823 mpi->unaffiliate = false;
5824 }
5825
5826 port->mp.mpi = NULL;
5827
5828 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5829
5830 spin_unlock(&port->mp.mpi_lock);
5831
5832 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5833
5834 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5835 /* Log an error, still needed to cleanup the pointers and add
5836 * it back to the list.
5837 */
5838 if (err)
5839 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5840 port_num + 1);
5841
95579e78 5842 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
32f69e4b
DJ		 5843}
5844
5845/* The mlx5_ib_multiport_mutex should be held when calling this function */
5846static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5847 struct mlx5_ib_multiport_info *mpi)
5848{
5849 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5850 int err;
5851
5852 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5853 if (ibdev->port[port_num].mp.mpi) {
2577188e
QH		 5854 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
5855 port_num + 1);
32f69e4b
DJ		 5856 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5857 return false;
5858 }
5859
5860 ibdev->port[port_num].mp.mpi = mpi;
5861 mpi->ibdev = ibdev;
df097a27 5862 mpi->mdev_events.notifier_call = NULL;
32f69e4b
DJ		 5863 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5864
5865 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5866 if (err)
5867 goto unbind;
5868
5869 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5870 if (err)
5871 goto unbind;
5872
5873 err = mlx5_add_netdev_notifier(ibdev, port_num);
5874 if (err) {
5875 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5876 port_num + 1);
5877 goto unbind;
5878 }
5879
df097a27
SM		 5880 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
5881 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
5882
73eb8f03 5883 mlx5_ib_init_cong_debugfs(ibdev, port_num);
a9e546e7 5884
32f69e4b
DJ		 5885 return true;
5886
5887unbind:
5888 mlx5_ib_unbind_slave_port(ibdev, mpi);
5889 return false;
5890}
5891
5892static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5893{
5894 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5895 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5896 port_num + 1);
5897 struct mlx5_ib_multiport_info *mpi;
5898 int err;
5899 int i;
5900
5901 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5902 return 0;
5903
5904 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5905 &dev->sys_image_guid);
5906 if (err)
5907 return err;
5908
5909 err = mlx5_nic_vport_enable_roce(dev->mdev);
5910 if (err)
5911 return err;
5912
5913 mutex_lock(&mlx5_ib_multiport_mutex);
5914 for (i = 0; i < dev->num_ports; i++) {
5915 bool bound = false;
5916
5917 /* build a stub multiport info struct for the native port. */
5918 if (i == port_num) {
5919 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5920 if (!mpi) {
5921 mutex_unlock(&mlx5_ib_multiport_mutex);
5922 mlx5_nic_vport_disable_roce(dev->mdev);
5923 return -ENOMEM;
5924 }
5925
5926 mpi->is_master = true;
5927 mpi->mdev = dev->mdev;
5928 mpi->sys_image_guid = dev->sys_image_guid;
5929 dev->port[i].mp.mpi = mpi;
5930 mpi->ibdev = dev;
5931 mpi = NULL;
5932 continue;
5933 }
5934
5935 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5936 list) {
5937 if (dev->sys_image_guid == mpi->sys_image_guid &&
5938 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5939 bound = mlx5_ib_bind_slave_port(dev, mpi);
5940 }
5941
5942 if (bound) {
c42260f1
VP		 5943 dev_dbg(mpi->mdev->device,
5944 "removing port from unaffiliated list.\n");
32f69e4b
DJ		 5945 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5946 list_del(&mpi->list);
5947 break;
5948 }
5949 }
5950 if (!bound) {
5951 get_port_caps(dev, i + 1);
5952 mlx5_ib_dbg(dev, "no free port found for port %d\n",
5953 i + 1);
5954 }
5955 }
5956
5957 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
5958 mutex_unlock(&mlx5_ib_multiport_mutex);
5959 return err;
5960}
5961
5962static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
5963{
5964 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5965 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5966 port_num + 1);
5967 int i;
5968
5969 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5970 return;
5971
5972 mutex_lock(&mlx5_ib_multiport_mutex);
5973 for (i = 0; i < dev->num_ports; i++) {
5974 if (dev->port[i].mp.mpi) {
5975 /* Destroy the native port stub */
5976 if (i == port_num) {
5977 kfree(dev->port[i].mp.mpi);
5978 dev->port[i].mp.mpi = NULL;
5979 } else {
5980 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
5981 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
5982 }
5983 }
5984 }
5985
5986 mlx5_ib_dbg(dev, "removing from devlist\n");
5987 list_del(&dev->ib_dev_list);
5988 mutex_unlock(&mlx5_ib_multiport_mutex);
5989
5990 mlx5_nic_vport_disable_roce(dev->mdev);
5991}
5992
9a119cd5
JG		 5993ADD_UVERBS_ATTRIBUTES_SIMPLE(
5994 mlx5_ib_dm,
5995 UVERBS_OBJECT_DM,
5996 UVERBS_METHOD_DM_ALLOC,
5997 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
5998 UVERBS_ATTR_TYPE(u64),
83bb4442 5999 UA_MANDATORY),
9a119cd5
JG		 6000 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
6001 UVERBS_ATTR_TYPE(u16),
3b113a1e
AL		 6002 UA_OPTIONAL),
6003 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
6004 enum mlx5_ib_uapi_dm_type,
6005 UA_OPTIONAL));
9a119cd5
JG		 6006
6007ADD_UVERBS_ATTRIBUTES_SIMPLE(
6008 mlx5_ib_flow_action,
6009 UVERBS_OBJECT_FLOW_ACTION,
6010 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
bccd0622
JG		 6011 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
6012 enum mlx5_ib_uapi_flow_action_flags));
c6475a0b 6013
0cbf432d
JG		 6014static const struct uapi_definition mlx5_ib_defs[] = {
6015#if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)
36e235c8 6016 UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
0cbf432d
JG		 6017 UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
6018#endif
8c84660b 6019
0cbf432d
JG		 6020 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION,
6021 &mlx5_ib_flow_action),
6022 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm),
6023 {}
6024};
8c84660b 6025
1a1e03dc
RS		 6026static int mlx5_ib_read_counters(struct ib_counters *counters,
6027 struct ib_counters_read_attr *read_attr,
6028 struct uverbs_attr_bundle *attrs)
6029{
6030 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
6031 struct mlx5_read_counters_attr mread_attr = {};
6032 struct mlx5_ib_flow_counters_desc *desc;
6033 int ret, i;
6034
6035 mutex_lock(&mcounters->mcntrs_mutex);
6036 if (mcounters->cntrs_max_index > read_attr->ncounters) {
6037 ret = -EINVAL;
6038 goto err_bound;
6039 }
6040
6041 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
6042 GFP_KERNEL);
6043 if (!mread_attr.out) {
6044 ret = -ENOMEM;
6045 goto err_bound;
6046 }
6047
6048 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
6049 mread_attr.flags = read_attr->flags;
6050 ret = mcounters->read_counters(counters->device, &mread_attr);
6051 if (ret)
6052 goto err_read;
6053
6054 /* do the pass over the counters data array to assign according to the
6055 * descriptions and indexing pairs
6056 */
6057 desc = mcounters->counters_data;
6058 for (i = 0; i < mcounters->ncounters; i++)
6059 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
6060
6061err_read:
6062 kfree(mread_attr.out);
6063err_bound:
6064 mutex_unlock(&mcounters->mcntrs_mutex);
6065 return ret;
6066}
6067
b29e2a13
RS		 6068static int mlx5_ib_destroy_counters(struct ib_counters *counters)
6069{
6070 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
6071
3b3233fb
RS		 6072 counters_clear_description(counters);
6073 if (mcounters->hw_cntrs_hndl)
6074 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
6075 mcounters->hw_cntrs_hndl);
6076
b29e2a13
RS		 6077 kfree(mcounters);
6078
6079 return 0;
6080}
6081
6082static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
6083 struct uverbs_attr_bundle *attrs)
6084{
6085 struct mlx5_ib_mcounters *mcounters;
6086
6087 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
6088 if (!mcounters)
6089 return ERR_PTR(-ENOMEM);
6090
3b3233fb
RS		 6091 mutex_init(&mcounters->mcntrs_mutex);
6092
b29e2a13
RS		 6093 return &mcounters->ibcntrs;
6094}
6095
fb652d32 6096static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
e126ba97 6097{
25c13324
AL		 6098 struct mlx5_core_dev *mdev = dev->mdev;
6099
32f69e4b 6100 mlx5_ib_cleanup_multiport_master(dev);
13859d5d 6101 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
534fd7aa 6102 srcu_barrier(&dev->mr_srcu);
13859d5d 6103 cleanup_srcu_struct(&dev->mr_srcu);
13859d5d 6104 }
4056b12e
AL		 6105
6106 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
25c13324
AL		 6107
6108 WARN_ON(dev->dm.steering_sw_icm_alloc_blocks &&
6109 !bitmap_empty(
6110 dev->dm.steering_sw_icm_alloc_blocks,
6111 BIT(MLX5_CAP_DEV_MEM(mdev, log_steering_sw_icm_size) -
6112 MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev))));
6113
6114 kfree(dev->dm.steering_sw_icm_alloc_blocks);
6115
6116 WARN_ON(dev->dm.header_modify_sw_icm_alloc_blocks &&
6117 !bitmap_empty(dev->dm.header_modify_sw_icm_alloc_blocks,
6118 BIT(MLX5_CAP_DEV_MEM(
6119 mdev, log_header_modify_sw_icm_size) -
6120 MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev))));
6121
6122 kfree(dev->dm.header_modify_sw_icm_alloc_blocks);
16c1975f
MB		 6123}
6124
fb652d32 6125static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6126{
6127 struct mlx5_core_dev *mdev = dev->mdev;
25c13324
AL		 6128 u64 header_modify_icm_blocks = 0;
6129 u64 steering_icm_blocks = 0;
e126ba97 6130 int err;
32f69e4b 6131 int i;
e126ba97 6132
32f69e4b
DJ		 6133 for (i = 0; i < dev->num_ports; i++) {
6134 spin_lock_init(&dev->port[i].mp.mpi_lock);
95579e78 6135 rwlock_init(&dev->port[i].roce.netdev_lock);
d3b5cc1c
MB		 6136 dev->port[i].roce.dev = dev;
6137 dev->port[i].roce.native_port_num = i + 1;
6138 dev->port[i].roce.last_port_state = IB_PORT_DOWN;
32f69e4b
DJ		 6139 }
6140
6141 err = mlx5_ib_init_multiport_master(dev);
e126ba97 6142 if (err)
da796ccb 6143 return err;
e126ba97 6144
a989ea01
MB		 6145 err = set_has_smi_cap(dev);
6146 if (err)
6147 return err;
e126ba97 6148
32f69e4b 6149 if (!mlx5_core_mp_enabled(mdev)) {
32f69e4b
DJ		 6150 for (i = 1; i <= dev->num_ports; i++) {
6151 err = get_port_caps(dev, i);
6152 if (err)
6153 break;
6154 }
6155 } else {
6156 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
6157 }
6158 if (err)
6159 goto err_mp;
6160
1b5daf11
MD		 6161 if (mlx5_use_mad_ifc(dev))
6162 get_ext_port_caps(dev);
e126ba97 6163
e126ba97 6164 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 6165 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
508562d6 6166 dev->ib_dev.phys_port_cnt = dev->num_ports;
f2f3df55 6167 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev);
c42260f1 6168 dev->ib_dev.dev.parent = mdev->device;
e126ba97 6169
3cc297db
MB		 6170 mutex_init(&dev->cap_mask_mutex);
6171 INIT_LIST_HEAD(&dev->qp_list);
6172 spin_lock_init(&dev->reset_flow_resource_lock);
6173
25c13324
AL		 6174 if (MLX5_CAP_GEN_64(mdev, general_obj_types) &
6175 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) {
6176 if (MLX5_CAP64_DEV_MEM(mdev, steering_sw_icm_start_address)) {
6177 steering_icm_blocks =
6178 BIT(MLX5_CAP_DEV_MEM(mdev,
6179 log_steering_sw_icm_size) -
6180 MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev));
6181
6182 dev->dm.steering_sw_icm_alloc_blocks =
6183 kcalloc(BITS_TO_LONGS(steering_icm_blocks),
6184 sizeof(unsigned long), GFP_KERNEL);
6185 if (!dev->dm.steering_sw_icm_alloc_blocks)
6186 goto err_mp;
6187 }
6188
6189 if (MLX5_CAP64_DEV_MEM(mdev,
6190 header_modify_sw_icm_start_address)) {
6191 header_modify_icm_blocks = BIT(
6192 MLX5_CAP_DEV_MEM(
6193 mdev, log_header_modify_sw_icm_size) -
6194 MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev));
6195
6196 dev->dm.header_modify_sw_icm_alloc_blocks =
6197 kcalloc(BITS_TO_LONGS(header_modify_icm_blocks),
6198 sizeof(unsigned long), GFP_KERNEL);
6199 if (!dev->dm.header_modify_sw_icm_alloc_blocks)
6200 goto err_dm;
6201 }
6202 }
6203
3b113a1e
AL		 6204 spin_lock_init(&dev->dm.lock);
6205 dev->dm.dev = mdev;
24da0016 6206
13859d5d 6207 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
13859d5d 6208 err = init_srcu_struct(&dev->mr_srcu);
a6bc3875 6209 if (err)
25c13324 6210 goto err_dm;
623d1543 6211 }
3cc297db 6212
16c1975f 6213 return 0;
25c13324
AL		 6214
6215err_dm:
6216 kfree(dev->dm.steering_sw_icm_alloc_blocks);
6217 kfree(dev->dm.header_modify_sw_icm_alloc_blocks);
6218
32f69e4b
DJ		 6219err_mp:
6220 mlx5_ib_cleanup_multiport_master(dev);
16c1975f 6221
16c1975f
MB		 6222 return -ENOMEM;
6223}
6224
9a4ca38d
MB		 6225static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
6226{
6227 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
6228
6229 if (!dev->flow_db)
6230 return -ENOMEM;
6231
6232 mutex_init(&dev->flow_db->lock);
6233
6234 return 0;
6235}
6236
6237static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
6238{
6239 kfree(dev->flow_db);
6240}
6241
96458233 6242static const struct ib_device_ops mlx5_ib_dev_ops = {
7a154142 6243 .owner = THIS_MODULE,
b9560a41 6244 .driver_id = RDMA_DRIVER_MLX5,
72c6ec18 6245 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
b9560a41 6246
96458233
KH		 6247 .add_gid = mlx5_ib_add_gid,
6248 .alloc_mr = mlx5_ib_alloc_mr,
6c984472 6249 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
96458233
KH		 6250 .alloc_pd = mlx5_ib_alloc_pd,
6251 .alloc_ucontext = mlx5_ib_alloc_ucontext,
6252 .attach_mcast = mlx5_ib_mcg_attach,
6253 .check_mr_status = mlx5_ib_check_mr_status,
6254 .create_ah = mlx5_ib_create_ah,
6255 .create_counters = mlx5_ib_create_counters,
6256 .create_cq = mlx5_ib_create_cq,
6257 .create_flow = mlx5_ib_create_flow,
6258 .create_qp = mlx5_ib_create_qp,
6259 .create_srq = mlx5_ib_create_srq,
6260 .dealloc_pd = mlx5_ib_dealloc_pd,
6261 .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
6262 .del_gid = mlx5_ib_del_gid,
6263 .dereg_mr = mlx5_ib_dereg_mr,
6264 .destroy_ah = mlx5_ib_destroy_ah,
6265 .destroy_counters = mlx5_ib_destroy_counters,
6266 .destroy_cq = mlx5_ib_destroy_cq,
6267 .destroy_flow = mlx5_ib_destroy_flow,
6268 .destroy_flow_action = mlx5_ib_destroy_flow_action,
6269 .destroy_qp = mlx5_ib_destroy_qp,
6270 .destroy_srq = mlx5_ib_destroy_srq,
6271 .detach_mcast = mlx5_ib_mcg_detach,
6272 .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
6273 .drain_rq = mlx5_ib_drain_rq,
6274 .drain_sq = mlx5_ib_drain_sq,
6275 .get_dev_fw_str = get_dev_fw_str,
6276 .get_dma_mr = mlx5_ib_get_dma_mr,
6277 .get_link_layer = mlx5_ib_port_link_layer,
6278 .map_mr_sg = mlx5_ib_map_mr_sg,
6c984472 6279 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi,
96458233
KH		 6280 .mmap = mlx5_ib_mmap,
6281 .modify_cq = mlx5_ib_modify_cq,
6282 .modify_device = mlx5_ib_modify_device,
6283 .modify_port = mlx5_ib_modify_port,
6284 .modify_qp = mlx5_ib_modify_qp,
6285 .modify_srq = mlx5_ib_modify_srq,
6286 .poll_cq = mlx5_ib_poll_cq,
6287 .post_recv = mlx5_ib_post_recv,
6288 .post_send = mlx5_ib_post_send,
6289 .post_srq_recv = mlx5_ib_post_srq_recv,
6290 .process_mad = mlx5_ib_process_mad,
6291 .query_ah = mlx5_ib_query_ah,
6292 .query_device = mlx5_ib_query_device,
6293 .query_gid = mlx5_ib_query_gid,
6294 .query_pkey = mlx5_ib_query_pkey,
6295 .query_qp = mlx5_ib_query_qp,
6296 .query_srq = mlx5_ib_query_srq,
6297 .read_counters = mlx5_ib_read_counters,
6298 .reg_user_mr = mlx5_ib_reg_user_mr,
6299 .req_notify_cq = mlx5_ib_arm_cq,
6300 .rereg_user_mr = mlx5_ib_rereg_user_mr,
6301 .resize_cq = mlx5_ib_resize_cq,
d3456914
LR		 6302
6303 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
e39afe3d 6304 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
21a428a0 6305 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
68e326de 6306 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
a2a074ef 6307 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
96458233
KH		 6308};
6309
6310static const struct ib_device_ops mlx5_ib_dev_flow_ipsec_ops = {
6311 .create_flow_action_esp = mlx5_ib_create_flow_action_esp,
6312 .modify_flow_action_esp = mlx5_ib_modify_flow_action_esp,
6313};
6314
6315static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
6316 .rdma_netdev_get_params = mlx5_ib_rn_get_params,
6317};
6318
6319static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
6320 .get_vf_config = mlx5_ib_get_vf_config,
6321 .get_vf_stats = mlx5_ib_get_vf_stats,
6322 .set_vf_guid = mlx5_ib_set_vf_guid,
6323 .set_vf_link_state = mlx5_ib_set_vf_link_state,
6324};
6325
6326static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
6327 .alloc_mw = mlx5_ib_alloc_mw,
6328 .dealloc_mw = mlx5_ib_dealloc_mw,
6329};
6330
6331static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
6332 .alloc_xrcd = mlx5_ib_alloc_xrcd,
6333 .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
6334};
6335
6336static const struct ib_device_ops mlx5_ib_dev_dm_ops = {
6337 .alloc_dm = mlx5_ib_alloc_dm,
6338 .dealloc_dm = mlx5_ib_dealloc_dm,
6339 .reg_dm_mr = mlx5_ib_reg_dm_mr,
6340};
6341
fb652d32 6342static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6343{
6344 struct mlx5_core_dev *mdev = dev->mdev;
16c1975f
MB		 6345 int err;
6346
e126ba97
EC		 6347 dev->ib_dev.uverbs_cmd_mask =
6348 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
6349 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
6350 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
6351 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
6352 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 6353 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
6354 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 6355 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 6356 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 6357 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
6358 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
6359 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
6360 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
6361 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
6362 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
6363 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
6364 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
6365 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
6366 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
6367 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
6368 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
6369 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
6370 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
6371 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
6372 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
6373 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 6374 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 6375 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
6376 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349 6377 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
b0e9df6d 6378 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
96458233
KH		 6379 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ) |
6380 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
6381 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
6382
f6a8a19b
DD		 6383 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
6384 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
96458233
KH		 6385 ib_set_device_ops(&dev->ib_dev,
6386 &mlx5_ib_dev_ipoib_enhanced_ops);
8e959601 6387
96458233
KH		 6388 if (mlx5_core_is_pf(mdev))
6389 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
7c2344c3 6390
6e8484c5
MG		 6391 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
6392
d2370e0a 6393 if (MLX5_CAP_GEN(mdev, imaicl)) {
d2370e0a
MB		 6394 dev->ib_dev.uverbs_cmd_mask |=
6395 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
6396 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
96458233 6397 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
d2370e0a
MB		 6398 }
6399
938fe83c 6400 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 6401 dev->ib_dev.uverbs_cmd_mask |=
6402 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
6403 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
96458233 6404 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
e126ba97
EC		 6405 }
6406
25c13324
AL		 6407 if (MLX5_CAP_DEV_MEM(mdev, memic) ||
6408 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
6409 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
96458233 6410 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
24da0016 6411
dfb631a1 6412 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
96458233
KH		 6413 MLX5_ACCEL_IPSEC_CAP_DEVICE)
6414 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_flow_ipsec_ops);
96458233 6415 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
81e30880 6416
36e235c8
JG		 6417 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
6418 dev->ib_dev.driver_def = mlx5_ib_defs;
81e30880 6419
e126ba97
EC		 6420 err = init_node_data(dev);
6421 if (err)
16c1975f 6422 return err;
e126ba97 6423
c8b89924 6424 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
e7996a9a
JG		 6425 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
6426 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
a560f1d9 6427 mutex_init(&dev->lb.mutex);
c8b89924 6428
96e2fd73
LR		 6429 dev->ib_dev.use_cq_dim = true;
6430
16c1975f
MB		 6431 return 0;
6432}
6433
96458233
KH		 6434static const struct ib_device_ops mlx5_ib_dev_port_ops = {
6435 .get_port_immutable = mlx5_port_immutable,
6436 .query_port = mlx5_ib_query_port,
6437};
6438
8e6efa3a
MB		 6439static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
6440{
96458233 6441 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
8e6efa3a
MB		 6442 return 0;
6443}
6444
96458233
KH		 6445static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
6446 .get_port_immutable = mlx5_port_rep_immutable,
6447 .query_port = mlx5_ib_rep_query_port,
6448};
6449
fb652d32 6450static int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
8e6efa3a 6451{
96458233 6452 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
8e6efa3a
MB		 6453 return 0;
6454}
6455
96458233
KH		 6456static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
6457 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
6458 .create_wq = mlx5_ib_create_wq,
6459 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
6460 .destroy_wq = mlx5_ib_destroy_wq,
6461 .get_netdev = mlx5_ib_get_netdev,
6462 .modify_wq = mlx5_ib_modify_wq,
6463};
6464
e3f1ed1f 6465static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
8e6efa3a 6466{
e3f1ed1f 6467 u8 port_num;
8e6efa3a 6468
8e6efa3a
MB		 6469 dev->ib_dev.uverbs_ex_cmd_mask |=
6470 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
6471 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
6472 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
6473 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
6474 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
96458233 6475 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
8e6efa3a 6476
e3f1ed1f
LR		 6477 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6478
26628e2d 6479 /* Register only for native ports */
8e6efa3a
MB		 6480 return mlx5_add_netdev_notifier(dev, port_num);
6481}
6482
6483static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
6484{
6485 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6486
6487 mlx5_remove_netdev_notifier(dev, port_num);
6488}
6489
fb652d32 6490static int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
8e6efa3a
MB		 6491{
6492 struct mlx5_core_dev *mdev = dev->mdev;
6493 enum rdma_link_layer ll;
6494 int port_type_cap;
6495 int err = 0;
8e6efa3a 6496
8e6efa3a
MB		 6497 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6498 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6499
6500 if (ll == IB_LINK_LAYER_ETHERNET)
e3f1ed1f 6501 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 6502
6503 return err;
6504}
6505
fb652d32 6506static void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
8e6efa3a
MB		 6507{
6508 mlx5_ib_stage_common_roce_cleanup(dev);
6509}
6510
16c1975f
MB		 6511static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
6512{
6513 struct mlx5_core_dev *mdev = dev->mdev;
6514 enum rdma_link_layer ll;
6515 int port_type_cap;
6516 int err;
6517
6518 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6519 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6520
fc24fc5e 6521 if (ll == IB_LINK_LAYER_ETHERNET) {
e3f1ed1f 6522 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 6523 if (err)
6524 return err;
7fd8aefb 6525
e3f1ed1f 6526 err = mlx5_enable_eth(dev);
fc24fc5e 6527 if (err)
8e6efa3a 6528 goto cleanup;
fc24fc5e
AS		 6529 }
6530
16c1975f 6531 return 0;
8e6efa3a
MB		 6532cleanup:
6533 mlx5_ib_stage_common_roce_cleanup(dev);
6534
6535 return err;
16c1975f 6536}
e126ba97 6537
16c1975f
MB		 6538static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
6539{
6540 struct mlx5_core_dev *mdev = dev->mdev;
6541 enum rdma_link_layer ll;
6542 int port_type_cap;
e126ba97 6543
16c1975f
MB		 6544 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6545 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6546
6547 if (ll == IB_LINK_LAYER_ETHERNET) {
6548 mlx5_disable_eth(dev);
8e6efa3a 6549 mlx5_ib_stage_common_roce_cleanup(dev);
45bded2c 6550 }
16c1975f 6551}
6aec21f6 6552
fb652d32 6553static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6554{
6555 return create_dev_resources(&dev->devr);
6556}
6557
fb652d32 6558static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6559{
6560 destroy_dev_resources(&dev->devr);
6561}
6562
6563static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
6564{
07321b3c
MB		 6565 mlx5_ib_internal_fill_odp_caps(dev);
6566
16c1975f
MB		 6567 return mlx5_ib_odp_init_one(dev);
6568}
4a2da0b8 6569
f3ffed0c 6570static void mlx5_ib_stage_odp_cleanup(struct mlx5_ib_dev *dev)
d5d284b8
SM		 6571{
6572 mlx5_ib_odp_cleanup_one(dev);
6573}
6574
96458233
KH		 6575static const struct ib_device_ops mlx5_ib_dev_hw_stats_ops = {
6576 .alloc_hw_stats = mlx5_ib_alloc_hw_stats,
6577 .get_hw_stats = mlx5_ib_get_hw_stats,
45842fc6
MZ		 6578 .counter_bind_qp = mlx5_ib_counter_bind_qp,
6579 .counter_unbind_qp = mlx5_ib_counter_unbind_qp,
6580 .counter_dealloc = mlx5_ib_counter_dealloc,
18d422ce
MZ		 6581 .counter_alloc_stats = mlx5_ib_counter_alloc_stats,
6582 .counter_update_stats = mlx5_ib_counter_update_stats,
96458233
KH		 6583};
6584
fb652d32 6585static int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
16c1975f 6586{
5e1e7612 6587 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
96458233 6588 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_hw_stats_ops);
5e1e7612
MB		 6589
6590 return mlx5_ib_alloc_counters(dev);
6591 }
16c1975f
MB		 6592
6593 return 0;
6594}
6595
fb652d32 6596static void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6597{
6598 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
6599 mlx5_ib_dealloc_counters(dev);
6600}
6601
6602static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
6603{
73eb8f03
GKH		 6604 mlx5_ib_init_cong_debugfs(dev,
6605 mlx5_core_native_port_num(dev->mdev) - 1);
6606 return 0;
16c1975f
MB		 6607}
6608
6609static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
6610{
a9e546e7
PP		 6611 mlx5_ib_cleanup_cong_debugfs(dev,
6612 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 6613}
6614
6615static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
6616{
5fe9dec0 6617 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
444261ca 6618 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
16c1975f
MB		 6619}
6620
6621static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
6622{
6623 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
6624}
6625
fb652d32 6626static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6627{
6628 int err;
5fe9dec0
EC		 6629
6630 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
6631 if (err)
16c1975f 6632 return err;
5fe9dec0
EC		 6633
6634 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
6635 if (err)
16c1975f 6636 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5fe9dec0 6637
16c1975f
MB		 6638 return err;
6639}
0837e86a 6640
fb652d32 6641static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6642{
6643 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6644 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
6645}
e126ba97 6646
fb652d32 6647static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
16c1975f 6648{
e349f858
JG		 6649 const char *name;
6650
508a523f 6651 rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group);
7c34ec19 6652 if (!mlx5_lag_is_roce(dev->mdev))
e349f858
JG		 6653 name = "mlx5_%d";
6654 else
6655 name = "mlx5_bond_%d";
ea4baf7f 6656 return ib_register_device(&dev->ib_dev, name);
16c1975f
MB		 6657}
6658
fb652d32 6659static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
16c1975f 6660{
42cea83f 6661 destroy_umrc_res(dev);
16c1975f
MB		 6662}
6663
fb652d32 6664static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
16c1975f 6665{
42cea83f 6666 ib_unregister_device(&dev->ib_dev);
16c1975f
MB		 6667}
6668
fb652d32 6669static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
16c1975f 6670{
42cea83f 6671 return create_umr_res(dev);
16c1975f
MB		 6672}
6673
6674static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
6675{
03404e8a
MG		 6676 init_delay_drop(dev);
6677
16c1975f
MB		 6678 return 0;
6679}
6680
6681static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
6682{
6683 cancel_delay_drop(dev);
6684}
6685
df097a27
SM		 6686static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
6687{
6688 dev->mdev_events.notifier_call = mlx5_ib_event;
6689 mlx5_notifier_register(dev->mdev, &dev->mdev_events);
6690 return 0;
6691}
6692
6693static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
6694{
6695 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
6696}
6697
81773ce5
LR		 6698static int mlx5_ib_stage_devx_init(struct mlx5_ib_dev *dev)
6699{
6700 int uid;
6701
fb98153b 6702 uid = mlx5_ib_devx_create(dev, false);
e337dd53 6703 if (uid > 0) {
81773ce5 6704 dev->devx_whitelist_uid = uid;
e337dd53
YH		 6705 mlx5_ib_devx_init_event_table(dev);
6706 }
81773ce5
LR		 6707
6708 return 0;
6709}
6710static void mlx5_ib_stage_devx_cleanup(struct mlx5_ib_dev *dev)
6711{
e337dd53
YH		 6712 if (dev->devx_whitelist_uid) {
6713 mlx5_ib_devx_cleanup_event_table(dev);
81773ce5 6714 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid);
e337dd53 6715 }
81773ce5
LR		 6716}
6717
b5ca15ad
MB		 6718void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
6719 const struct mlx5_ib_profile *profile,
6720 int stage)
16c1975f
MB		 6721{
6722 /* Number of stages to cleanup */
6723 while (stage) {
6724 stage--;
6725 if (profile->stage[stage].cleanup)
6726 profile->stage[stage].cleanup(dev);
6727 }
4a6dc855 6728
da796ccb 6729 kfree(dev->port);
4a6dc855 6730 ib_dealloc_device(&dev->ib_dev);
16c1975f 6731}
e126ba97 6732
b5ca15ad
MB		 6733void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
6734 const struct mlx5_ib_profile *profile)
16c1975f 6735{
16c1975f
MB		 6736 int err;
6737 int i;
5fe9dec0 6738
16c1975f
MB		 6739 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
6740 if (profile->stage[i].init) {
6741 err = profile->stage[i].init(dev);
6742 if (err)
6743 goto err_out;
6744 }
6745 }
0837e86a 6746
16c1975f
MB		 6747 dev->profile = profile;
6748 dev->ib_active = true;
6aec21f6 6749
16c1975f 6750 return dev;
e126ba97 6751
16c1975f
MB		 6752err_out:
6753 __mlx5_ib_remove(dev, profile, i);
fc24fc5e 6754
16c1975f
MB		 6755 return NULL;
6756}
0837e86a 6757
16c1975f
MB		 6758static const struct mlx5_ib_profile pf_profile = {
6759 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6760 mlx5_ib_stage_init_init,
6761 mlx5_ib_stage_init_cleanup),
9a4ca38d
MB		 6762 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6763 mlx5_ib_stage_flow_db_init,
6764 mlx5_ib_stage_flow_db_cleanup),
16c1975f
MB		 6765 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6766 mlx5_ib_stage_caps_init,
6767 NULL),
8e6efa3a
MB		 6768 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6769 mlx5_ib_stage_non_default_cb,
6770 NULL),
16c1975f
MB		 6771 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6772 mlx5_ib_stage_roce_init,
6773 mlx5_ib_stage_roce_cleanup),
f3da6577
LR		 6774 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6775 mlx5_init_srq_table,
6776 mlx5_cleanup_srq_table),
16c1975f
MB		 6777 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6778 mlx5_ib_stage_dev_res_init,
6779 mlx5_ib_stage_dev_res_cleanup),
df097a27
SM		 6780 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6781 mlx5_ib_stage_dev_notifier_init,
6782 mlx5_ib_stage_dev_notifier_cleanup),
16c1975f
MB		 6783 STAGE_CREATE(MLX5_IB_STAGE_ODP,
6784 mlx5_ib_stage_odp_init,
d5d284b8 6785 mlx5_ib_stage_odp_cleanup),
16c1975f
MB		 6786 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6787 mlx5_ib_stage_counters_init,
6788 mlx5_ib_stage_counters_cleanup),
6789 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
6790 mlx5_ib_stage_cong_debugfs_init,
6791 mlx5_ib_stage_cong_debugfs_cleanup),
6792 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6793 mlx5_ib_stage_uar_init,
6794 mlx5_ib_stage_uar_cleanup),
6795 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6796 mlx5_ib_stage_bfrag_init,
6797 mlx5_ib_stage_bfrag_cleanup),
42cea83f
MB		 6798 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6799 NULL,
6800 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
81773ce5
LR		 6801 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
6802 mlx5_ib_stage_devx_init,
6803 mlx5_ib_stage_devx_cleanup),
16c1975f
MB		 6804 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6805 mlx5_ib_stage_ib_reg_init,
6806 mlx5_ib_stage_ib_reg_cleanup),
42cea83f
MB		 6807 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6808 mlx5_ib_stage_post_ib_reg_umr_init,
6809 NULL),
16c1975f
MB		 6810 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
6811 mlx5_ib_stage_delay_drop_init,
6812 mlx5_ib_stage_delay_drop_cleanup),
16c1975f 6813};
e126ba97 6814
f0666f1f 6815const struct mlx5_ib_profile uplink_rep_profile = {
b5ca15ad
MB		 6816 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6817 mlx5_ib_stage_init_init,
6818 mlx5_ib_stage_init_cleanup),
6819 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6820 mlx5_ib_stage_flow_db_init,
6821 mlx5_ib_stage_flow_db_cleanup),
6822 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6823 mlx5_ib_stage_caps_init,
6824 NULL),
6825 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6826 mlx5_ib_stage_rep_non_default_cb,
6827 NULL),
6828 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6829 mlx5_ib_stage_rep_roce_init,
6830 mlx5_ib_stage_rep_roce_cleanup),
f3da6577
LR		 6831 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6832 mlx5_init_srq_table,
6833 mlx5_cleanup_srq_table),
b5ca15ad
MB		 6834 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6835 mlx5_ib_stage_dev_res_init,
6836 mlx5_ib_stage_dev_res_cleanup),
df097a27
SM		 6837 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6838 mlx5_ib_stage_dev_notifier_init,
6839 mlx5_ib_stage_dev_notifier_cleanup),
b5ca15ad
MB		 6840 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6841 mlx5_ib_stage_counters_init,
6842 mlx5_ib_stage_counters_cleanup),
6843 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6844 mlx5_ib_stage_uar_init,
6845 mlx5_ib_stage_uar_cleanup),
6846 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6847 mlx5_ib_stage_bfrag_init,
6848 mlx5_ib_stage_bfrag_cleanup),
03fe2deb
DM		 6849 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6850 NULL,
6851 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
7f575103
MB		 6852 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
6853 mlx5_ib_stage_devx_init,
6854 mlx5_ib_stage_devx_cleanup),
b5ca15ad
MB		 6855 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6856 mlx5_ib_stage_ib_reg_init,
6857 mlx5_ib_stage_ib_reg_cleanup),
03fe2deb
DM		 6858 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6859 mlx5_ib_stage_post_ib_reg_umr_init,
6860 NULL),
b5ca15ad
MB		 6861};
6862
e3f1ed1f 6863static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
32f69e4b
DJ		 6864{
6865 struct mlx5_ib_multiport_info *mpi;
6866 struct mlx5_ib_dev *dev;
6867 bool bound = false;
6868 int err;
6869
6870 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6871 if (!mpi)
6872 return NULL;
6873
6874 mpi->mdev = mdev;
6875
6876 err = mlx5_query_nic_vport_system_image_guid(mdev,
6877 &mpi->sys_image_guid);
6878 if (err) {
6879 kfree(mpi);
6880 return NULL;
6881 }
6882
6883 mutex_lock(&mlx5_ib_multiport_mutex);
6884 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
6885 if (dev->sys_image_guid == mpi->sys_image_guid)
6886 bound = mlx5_ib_bind_slave_port(dev, mpi);
6887
6888 if (bound) {
6889 rdma_roce_rescan_device(&dev->ib_dev);
6890 break;
6891 }
6892 }
6893
6894 if (!bound) {
6895 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
c42260f1
VP		 6896 dev_dbg(mdev->device,
6897 "no suitable IB device found to bind to, added to unaffiliated list.\n");
32f69e4b
DJ		 6898 }
6899 mutex_unlock(&mlx5_ib_multiport_mutex);
6900
6901 return mpi;
6902}
6903
16c1975f
MB		 6904static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
6905{
32f69e4b 6906 enum rdma_link_layer ll;
b5ca15ad 6907 struct mlx5_ib_dev *dev;
32f69e4b 6908 int port_type_cap;
da796ccb 6909 int num_ports;
32f69e4b 6910
b5ca15ad
MB		 6911 printk_once(KERN_INFO "%s", mlx5_version);
6912
f0666f1f 6913 if (MLX5_ESWITCH_MANAGER(mdev) &&
f6455de0 6914 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
5fb58c9e
MB		 6915 if (!mlx5_core_mp_enabled(mdev))
6916 mlx5_ib_register_vport_reps(mdev);
f0666f1f
BW		 6917 return mdev;
6918 }
6919
32f69e4b
DJ		 6920 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6921 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6922
e3f1ed1f
LR		 6923 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
6924 return mlx5_ib_add_slave_port(mdev);
32f69e4b 6925
da796ccb
MB		 6926 num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
6927 MLX5_CAP_GEN(mdev, num_vhca_ports));
459cc69f 6928 dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
b5ca15ad
MB		 6929 if (!dev)
6930 return NULL;
da796ccb
MB		 6931 dev->port = kcalloc(num_ports, sizeof(*dev->port),
6932 GFP_KERNEL);
6933 if (!dev->port) {
a5c9c299 6934 ib_dealloc_device(&dev->ib_dev);
da796ccb
MB		 6935 return NULL;
6936 }
b5ca15ad
MB		 6937
6938 dev->mdev = mdev;
da796ccb 6939 dev->num_ports = num_ports;
b5ca15ad 6940
b5ca15ad 6941 return __mlx5_ib_add(dev, &pf_profile);
e126ba97
EC		 6942}
6943
9603b61d 6944static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 6945{
32f69e4b
DJ		 6946 struct mlx5_ib_multiport_info *mpi;
6947 struct mlx5_ib_dev *dev;
6948
f0666f1f
BW		 6949 if (MLX5_ESWITCH_MANAGER(mdev) && context == mdev) {
6950 mlx5_ib_unregister_vport_reps(mdev);
6951 return;
6952 }
6953
32f69e4b
DJ		 6954 if (mlx5_core_is_mp_slave(mdev)) {
6955 mpi = context;
6956 mutex_lock(&mlx5_ib_multiport_mutex);
6957 if (mpi->ibdev)
6958 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
6959 list_del(&mpi->list);
6960 mutex_unlock(&mlx5_ib_multiport_mutex);
6961 return;
6962 }
6aec21f6 6963
32f69e4b 6964 dev = context;
f0666f1f 6965 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
e126ba97
EC		 6966}
6967
9603b61d
JM		 6968static struct mlx5_interface mlx5_ib_interface = {
6969 .add = mlx5_ib_add,
6970 .remove = mlx5_ib_remove,
64613d94 6971 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 6972};
6973
c44ef998
IL		 6974unsigned long mlx5_ib_get_xlt_emergency_page(void)
6975{
6976 mutex_lock(&xlt_emergency_page_mutex);
6977 return xlt_emergency_page;
6978}
6979
6980void mlx5_ib_put_xlt_emergency_page(void)
6981{
6982 mutex_unlock(&xlt_emergency_page_mutex);
6983}
6984
e126ba97
EC		 6985static int __init mlx5_ib_init(void)
6986{
6aec21f6
HE		 6987 int err;
6988
c44ef998
IL		 6989 xlt_emergency_page = __get_free_page(GFP_KERNEL);
6990 if (!xlt_emergency_page)
6991 return -ENOMEM;
6992
6993 mutex_init(&xlt_emergency_page_mutex);
6994
d69a24e0 6995 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
c44ef998
IL		 6996 if (!mlx5_ib_event_wq) {
6997 free_page(xlt_emergency_page);
d69a24e0 6998 return -ENOMEM;
c44ef998 6999 }
d69a24e0 7000
81713d37 7001 mlx5_ib_odp_init();
9603b61d 7002
6aec21f6 7003 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 7004
6aec21f6 7005 return err;
e126ba97
EC		 7006}
7007
7008static void __exit mlx5_ib_cleanup(void)
7009{
9603b61d 7010 mlx5_unregister_interface(&mlx5_ib_interface);
d69a24e0 7011 destroy_workqueue(mlx5_ib_event_wq);
c44ef998
IL		 7012 mutex_destroy(&xlt_emergency_page_mutex);
7013 free_page(xlt_emergency_page);
e126ba97
EC		 7014}
7015
7016module_init(mlx5_ib_init);
7017module_exit(mlx5_ib_cleanup);
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