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IB/mlx5: Only synchronize RCU once when removing mkeys
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
37aa5c36
GL		 41#if defined(CONFIG_X86)
42#include <asm/pat.h>
43#endif
e126ba97 44#include <linux/sched.h>
6e84f315 45#include <linux/sched/mm.h>
0881e7bd 46#include <linux/sched/task.h>
7c2344c3 47#include <linux/delay.h>
e126ba97 48#include <rdma/ib_user_verbs.h>
3f89a643 49#include <rdma/ib_addr.h>
2811ba51 50#include <rdma/ib_cache.h>
ada68c31 51#include <linux/mlx5/port.h>
1b5daf11 52#include <linux/mlx5/vport.h>
72c7fe90 53#include <linux/mlx5/fs.h>
7c2344c3 54#include <linux/list.h>
e126ba97
EC		 55#include <rdma/ib_smi.h>
56#include <rdma/ib_umem.h>
038d2ef8
MG		 57#include <linux/in.h>
58#include <linux/etherdevice.h>
e126ba97 59#include "mlx5_ib.h"
fc385b7a 60#include "ib_rep.h"
e1f24a79 61#include "cmd.h"
3346c487 62#include <linux/mlx5/fs_helpers.h>
e126ba97
EC		 63
64#define DRIVER_NAME "mlx5_ib"
b359911d 65#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 66
67MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
68MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
69MODULE_LICENSE("Dual BSD/GPL");
e126ba97 70
e126ba97
EC		 71static char mlx5_version[] =
72 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 73 DRIVER_VERSION "\n";
e126ba97 74
d69a24e0
DJ		 75struct mlx5_ib_event_work {
76 struct work_struct work;
77 struct mlx5_core_dev *dev;
78 void *context;
79 enum mlx5_dev_event event;
80 unsigned long param;
81};
82
da7525d2
EBE		 83enum {
84 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
85};
86
d69a24e0 87static struct workqueue_struct *mlx5_ib_event_wq;
32f69e4b
DJ		 88static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
89static LIST_HEAD(mlx5_ib_dev_list);
90/*
91 * This mutex should be held when accessing either of the above lists
92 */
93static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
94
95struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
96{
97 struct mlx5_ib_dev *dev;
98
99 mutex_lock(&mlx5_ib_multiport_mutex);
100 dev = mpi->ibdev;
101 mutex_unlock(&mlx5_ib_multiport_mutex);
102 return dev;
103}
104
1b5daf11 105static enum rdma_link_layer
ebd61f68 106mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 107{
ebd61f68 108 switch (port_type_cap) {
1b5daf11
MD		 109 case MLX5_CAP_PORT_TYPE_IB:
110 return IB_LINK_LAYER_INFINIBAND;
111 case MLX5_CAP_PORT_TYPE_ETH:
112 return IB_LINK_LAYER_ETHERNET;
113 default:
114 return IB_LINK_LAYER_UNSPECIFIED;
115 }
116}
117
ebd61f68
AS		 118static enum rdma_link_layer
119mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
120{
121 struct mlx5_ib_dev *dev = to_mdev(device);
122 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
123
124 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
125}
126
fd65f1b8
MS		 127static int get_port_state(struct ib_device *ibdev,
128 u8 port_num,
129 enum ib_port_state *state)
130{
131 struct ib_port_attr attr;
132 int ret;
133
134 memset(&attr, 0, sizeof(attr));
8e6efa3a 135 ret = ibdev->query_port(ibdev, port_num, &attr);
fd65f1b8
MS		 136 if (!ret)
137 *state = attr.state;
138 return ret;
139}
140
fc24fc5e
AS		 141static int mlx5_netdev_event(struct notifier_block *this,
142 unsigned long event, void *ptr)
143{
7fd8aefb 144 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
fc24fc5e 145 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
7fd8aefb
DJ		 146 u8 port_num = roce->native_port_num;
147 struct mlx5_core_dev *mdev;
148 struct mlx5_ib_dev *ibdev;
149
150 ibdev = roce->dev;
32f69e4b
DJ		 151 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
152 if (!mdev)
153 return NOTIFY_DONE;
fc24fc5e 154
5ec8c83e
AH		 155 switch (event) {
156 case NETDEV_REGISTER:
157 case NETDEV_UNREGISTER:
7fd8aefb 158 write_lock(&roce->netdev_lock);
bcf87f1d
MB		 159 if (ibdev->rep) {
160 struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch;
161 struct net_device *rep_ndev;
162
163 rep_ndev = mlx5_ib_get_rep_netdev(esw,
164 ibdev->rep->vport);
165 if (rep_ndev == ndev)
166 roce->netdev = (event == NETDEV_UNREGISTER) ?
7fd8aefb 167 NULL : ndev;
bcf87f1d
MB		 168 } else if (ndev->dev.parent == &ibdev->mdev->pdev->dev) {
169 roce->netdev = (event == NETDEV_UNREGISTER) ?
170 NULL : ndev;
171 }
7fd8aefb 172 write_unlock(&roce->netdev_lock);
5ec8c83e 173 break;
fc24fc5e 174
fd65f1b8 175 case NETDEV_CHANGE:
5ec8c83e 176 case NETDEV_UP:
88621dfe 177 case NETDEV_DOWN: {
7fd8aefb 178 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe
AH		 179 struct net_device *upper = NULL;
180
181 if (lag_ndev) {
182 upper = netdev_master_upper_dev_get(lag_ndev);
183 dev_put(lag_ndev);
184 }
185
7fd8aefb 186 if ((upper == ndev || (!upper && ndev == roce->netdev))
88621dfe 187 && ibdev->ib_active) {
626bc02d 188 struct ib_event ibev = { };
fd65f1b8 189 enum ib_port_state port_state;
5ec8c83e 190
7fd8aefb
DJ		 191 if (get_port_state(&ibdev->ib_dev, port_num,
192 &port_state))
193 goto done;
fd65f1b8 194
7fd8aefb
DJ		 195 if (roce->last_port_state == port_state)
196 goto done;
fd65f1b8 197
7fd8aefb 198 roce->last_port_state = port_state;
5ec8c83e 199 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 200 if (port_state == IB_PORT_DOWN)
201 ibev.event = IB_EVENT_PORT_ERR;
202 else if (port_state == IB_PORT_ACTIVE)
203 ibev.event = IB_EVENT_PORT_ACTIVE;
204 else
7fd8aefb 205 goto done;
fd65f1b8 206
7fd8aefb 207 ibev.element.port_num = port_num;
5ec8c83e
AH		 208 ib_dispatch_event(&ibev);
209 }
210 break;
88621dfe 211 }
fc24fc5e 212
5ec8c83e
AH		 213 default:
214 break;
215 }
7fd8aefb 216done:
32f69e4b 217 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 218 return NOTIFY_DONE;
219}
220
221static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
222 u8 port_num)
223{
224 struct mlx5_ib_dev *ibdev = to_mdev(device);
225 struct net_device *ndev;
32f69e4b
DJ		 226 struct mlx5_core_dev *mdev;
227
228 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
229 if (!mdev)
230 return NULL;
fc24fc5e 231
32f69e4b 232 ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe 233 if (ndev)
32f69e4b 234 goto out;
88621dfe 235
fc24fc5e
AS		 236 /* Ensure ndev does not disappear before we invoke dev_hold()
237 */
7fd8aefb
DJ		 238 read_lock(&ibdev->roce[port_num - 1].netdev_lock);
239 ndev = ibdev->roce[port_num - 1].netdev;
fc24fc5e
AS		 240 if (ndev)
241 dev_hold(ndev);
7fd8aefb 242 read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
fc24fc5e 243
32f69e4b
DJ		 244out:
245 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 246 return ndev;
247}
248
32f69e4b
DJ		 249struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
250 u8 ib_port_num,
251 u8 *native_port_num)
252{
253 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
254 ib_port_num);
255 struct mlx5_core_dev *mdev = NULL;
256 struct mlx5_ib_multiport_info *mpi;
257 struct mlx5_ib_port *port;
258
259 if (native_port_num)
260 *native_port_num = 1;
261
262 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
263 return ibdev->mdev;
264
265 port = &ibdev->port[ib_port_num - 1];
266 if (!port)
267 return NULL;
268
269 spin_lock(&port->mp.mpi_lock);
270 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
271 if (mpi && !mpi->unaffiliate) {
272 mdev = mpi->mdev;
273 /* If it's the master no need to refcount, it'll exist
274 * as long as the ib_dev exists.
275 */
276 if (!mpi->is_master)
277 mpi->mdev_refcnt++;
278 }
279 spin_unlock(&port->mp.mpi_lock);
280
281 return mdev;
282}
283
284void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
285{
286 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
287 port_num);
288 struct mlx5_ib_multiport_info *mpi;
289 struct mlx5_ib_port *port;
290
291 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
292 return;
293
294 port = &ibdev->port[port_num - 1];
295
296 spin_lock(&port->mp.mpi_lock);
297 mpi = ibdev->port[port_num - 1].mp.mpi;
298 if (mpi->is_master)
299 goto out;
300
301 mpi->mdev_refcnt--;
302 if (mpi->unaffiliate)
303 complete(&mpi->unref_comp);
304out:
305 spin_unlock(&port->mp.mpi_lock);
306}
307
f1b65df5
NO		 308static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
309 u8 *active_width)
310{
311 switch (eth_proto_oper) {
312 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
313 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
314 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
315 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
316 *active_width = IB_WIDTH_1X;
317 *active_speed = IB_SPEED_SDR;
318 break;
319 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
320 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
321 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
322 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
323 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
324 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
325 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
326 *active_width = IB_WIDTH_1X;
327 *active_speed = IB_SPEED_QDR;
328 break;
329 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
330 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
331 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
332 *active_width = IB_WIDTH_1X;
333 *active_speed = IB_SPEED_EDR;
334 break;
335 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
336 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
337 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
338 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
339 *active_width = IB_WIDTH_4X;
340 *active_speed = IB_SPEED_QDR;
341 break;
342 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
343 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
344 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
345 *active_width = IB_WIDTH_1X;
346 *active_speed = IB_SPEED_HDR;
347 break;
348 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
349 *active_width = IB_WIDTH_4X;
350 *active_speed = IB_SPEED_FDR;
351 break;
352 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
353 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
354 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
355 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
356 *active_width = IB_WIDTH_4X;
357 *active_speed = IB_SPEED_EDR;
358 break;
359 default:
360 return -EINVAL;
361 }
362
363 return 0;
364}
365
095b0927
IT		 366static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
367 struct ib_port_attr *props)
3f89a643
AS		 368{
369 struct mlx5_ib_dev *dev = to_mdev(device);
da005f9f 370 struct mlx5_core_dev *mdev;
88621dfe 371 struct net_device *ndev, *upper;
3f89a643 372 enum ib_mtu ndev_ib_mtu;
b3cbd6f0 373 bool put_mdev = true;
c876a1b7 374 u16 qkey_viol_cntr;
f1b65df5 375 u32 eth_prot_oper;
b3cbd6f0 376 u8 mdev_port_num;
095b0927 377 int err;
3f89a643 378
b3cbd6f0
DJ		 379 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
380 if (!mdev) {
381 /* This means the port isn't affiliated yet. Get the
382 * info for the master port instead.
383 */
384 put_mdev = false;
385 mdev = dev->mdev;
386 mdev_port_num = 1;
387 port_num = 1;
388 }
389
f1b65df5
NO		 390 /* Possible bad flows are checked before filling out props so in case
391 * of an error it will still be zeroed out.
50f22fd8 392 */
b3cbd6f0
DJ		 393 err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper,
394 mdev_port_num);
095b0927 395 if (err)
b3cbd6f0 396 goto out;
f1b65df5
NO		 397
398 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
399 &props->active_width);
3f89a643
AS		 400
401 props->port_cap_flags |= IB_PORT_CM_SUP;
402 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
403
404 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
405 roce_address_table_size);
406 props->max_mtu = IB_MTU_4096;
407 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
408 props->pkey_tbl_len = 1;
409 props->state = IB_PORT_DOWN;
410 props->phys_state = 3;
411
b3cbd6f0 412 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
c876a1b7 413 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643 414
b3cbd6f0
DJ		 415 /* If this is a stub query for an unaffiliated port stop here */
416 if (!put_mdev)
417 goto out;
418
3f89a643
AS		 419 ndev = mlx5_ib_get_netdev(device, port_num);
420 if (!ndev)
b3cbd6f0 421 goto out;
3f89a643 422
88621dfe
AH		 423 if (mlx5_lag_is_active(dev->mdev)) {
424 rcu_read_lock();
425 upper = netdev_master_upper_dev_get_rcu(ndev);
426 if (upper) {
427 dev_put(ndev);
428 ndev = upper;
429 dev_hold(ndev);
430 }
431 rcu_read_unlock();
432 }
433
3f89a643
AS		 434 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
435 props->state = IB_PORT_ACTIVE;
436 props->phys_state = 5;
437 }
438
439 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
440
441 dev_put(ndev);
442
443 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
b3cbd6f0
DJ		 444out:
445 if (put_mdev)
446 mlx5_ib_put_native_port_mdev(dev, port_num);
447 return err;
3f89a643
AS		 448}
449
095b0927
IT		 450static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
451 unsigned int index, const union ib_gid *gid,
452 const struct ib_gid_attr *attr)
3cca2606 453{
095b0927
IT		 454 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
455 u8 roce_version = 0;
456 u8 roce_l3_type = 0;
457 bool vlan = false;
458 u8 mac[ETH_ALEN];
459 u16 vlan_id = 0;
460
461 if (gid) {
462 gid_type = attr->gid_type;
463 ether_addr_copy(mac, attr->ndev->dev_addr);
464
465 if (is_vlan_dev(attr->ndev)) {
466 vlan = true;
467 vlan_id = vlan_dev_vlan_id(attr->ndev);
468 }
3cca2606
AS		 469 }
470
095b0927 471 switch (gid_type) {
3cca2606 472 case IB_GID_TYPE_IB:
095b0927 473 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 474 break;
475 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 476 roce_version = MLX5_ROCE_VERSION_2;
477 if (ipv6_addr_v4mapped((void *)gid))
478 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
479 else
480 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 481 break;
482
483 default:
095b0927 484 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 485 }
486
095b0927
IT		 487 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
488 roce_l3_type, gid->raw, mac, vlan,
cfe4e37f 489 vlan_id, port_num);
3cca2606
AS		 490}
491
492static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
493 unsigned int index, const union ib_gid *gid,
494 const struct ib_gid_attr *attr,
495 __always_unused void **context)
496{
095b0927 497 return set_roce_addr(to_mdev(device), port_num, index, gid, attr);
3cca2606
AS		 498}
499
500static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
501 unsigned int index, __always_unused void **context)
502{
095b0927 503 return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL);
3cca2606
AS		 504}
505
2811ba51
AS		 506__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
507 int index)
508{
509 struct ib_gid_attr attr;
510 union ib_gid gid;
511
512 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
513 return 0;
514
515 if (!attr.ndev)
516 return 0;
517
518 dev_put(attr.ndev);
519
520 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
521 return 0;
522
523 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
524}
525
ed88451e
MD		 526int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
527 int index, enum ib_gid_type *gid_type)
528{
529 struct ib_gid_attr attr;
530 union ib_gid gid;
531 int ret;
532
533 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
534 if (ret)
535 return ret;
536
537 if (!attr.ndev)
538 return -ENODEV;
539
540 dev_put(attr.ndev);
541
542 *gid_type = attr.gid_type;
543
544 return 0;
545}
546
1b5daf11
MD		 547static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
548{
7fae6655
NO		 549 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
550 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
551 return 0;
1b5daf11
MD		 552}
553
554enum {
555 MLX5_VPORT_ACCESS_METHOD_MAD,
556 MLX5_VPORT_ACCESS_METHOD_HCA,
557 MLX5_VPORT_ACCESS_METHOD_NIC,
558};
559
560static int mlx5_get_vport_access_method(struct ib_device *ibdev)
561{
562 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
563 return MLX5_VPORT_ACCESS_METHOD_MAD;
564
ebd61f68 565 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 566 IB_LINK_LAYER_ETHERNET)
567 return MLX5_VPORT_ACCESS_METHOD_NIC;
568
569 return MLX5_VPORT_ACCESS_METHOD_HCA;
570}
571
da7525d2 572static void get_atomic_caps(struct mlx5_ib_dev *dev,
776a3906 573 u8 atomic_size_qp,
da7525d2
EBE		 574 struct ib_device_attr *props)
575{
576 u8 tmp;
577 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
da7525d2 578 u8 atomic_req_8B_endianness_mode =
bd10838a 579 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 580
581 /* Check if HW supports 8 bytes standard atomic operations and capable
582 * of host endianness respond
583 */
584 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
585 if (((atomic_operations & tmp) == tmp) &&
586 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
587 (atomic_req_8B_endianness_mode)) {
588 props->atomic_cap = IB_ATOMIC_HCA;
589 } else {
590 props->atomic_cap = IB_ATOMIC_NONE;
591 }
592}
593
776a3906
MS		 594static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
595 struct ib_device_attr *props)
596{
597 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
598
599 get_atomic_caps(dev, atomic_size_qp, props);
600}
601
602static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
603 struct ib_device_attr *props)
604{
605 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
606
607 get_atomic_caps(dev, atomic_size_qp, props);
608}
609
610bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
611{
612 struct ib_device_attr props = {};
613
614 get_atomic_caps_dc(dev, &props);
615 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
616}
1b5daf11
MD		 617static int mlx5_query_system_image_guid(struct ib_device *ibdev,
618 __be64 *sys_image_guid)
619{
620 struct mlx5_ib_dev *dev = to_mdev(ibdev);
621 struct mlx5_core_dev *mdev = dev->mdev;
622 u64 tmp;
623 int err;
624
625 switch (mlx5_get_vport_access_method(ibdev)) {
626 case MLX5_VPORT_ACCESS_METHOD_MAD:
627 return mlx5_query_mad_ifc_system_image_guid(ibdev,
628 sys_image_guid);
629
630 case MLX5_VPORT_ACCESS_METHOD_HCA:
631 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 632 break;
633
634 case MLX5_VPORT_ACCESS_METHOD_NIC:
635 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
636 break;
1b5daf11
MD		 637
638 default:
639 return -EINVAL;
640 }
3f89a643
AS		 641
642 if (!err)
643 *sys_image_guid = cpu_to_be64(tmp);
644
645 return err;
646
1b5daf11
MD		 647}
648
649static int mlx5_query_max_pkeys(struct ib_device *ibdev,
650 u16 *max_pkeys)
651{
652 struct mlx5_ib_dev *dev = to_mdev(ibdev);
653 struct mlx5_core_dev *mdev = dev->mdev;
654
655 switch (mlx5_get_vport_access_method(ibdev)) {
656 case MLX5_VPORT_ACCESS_METHOD_MAD:
657 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
658
659 case MLX5_VPORT_ACCESS_METHOD_HCA:
660 case MLX5_VPORT_ACCESS_METHOD_NIC:
661 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
662 pkey_table_size));
663 return 0;
664
665 default:
666 return -EINVAL;
667 }
668}
669
670static int mlx5_query_vendor_id(struct ib_device *ibdev,
671 u32 *vendor_id)
672{
673 struct mlx5_ib_dev *dev = to_mdev(ibdev);
674
675 switch (mlx5_get_vport_access_method(ibdev)) {
676 case MLX5_VPORT_ACCESS_METHOD_MAD:
677 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
678
679 case MLX5_VPORT_ACCESS_METHOD_HCA:
680 case MLX5_VPORT_ACCESS_METHOD_NIC:
681 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
682
683 default:
684 return -EINVAL;
685 }
686}
687
688static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
689 __be64 *node_guid)
690{
691 u64 tmp;
692 int err;
693
694 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
695 case MLX5_VPORT_ACCESS_METHOD_MAD:
696 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
697
698 case MLX5_VPORT_ACCESS_METHOD_HCA:
699 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 700 break;
701
702 case MLX5_VPORT_ACCESS_METHOD_NIC:
703 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
704 break;
1b5daf11
MD		 705
706 default:
707 return -EINVAL;
708 }
3f89a643
AS		 709
710 if (!err)
711 *node_guid = cpu_to_be64(tmp);
712
713 return err;
1b5daf11
MD		 714}
715
716struct mlx5_reg_node_desc {
bd99fdea 717 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 718};
719
720static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
721{
722 struct mlx5_reg_node_desc in;
723
724 if (mlx5_use_mad_ifc(dev))
725 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
726
727 memset(&in, 0, sizeof(in));
728
729 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
730 sizeof(struct mlx5_reg_node_desc),
731 MLX5_REG_NODE_DESC, 0, 0);
732}
733
e126ba97 734static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 735 struct ib_device_attr *props,
736 struct ib_udata *uhw)
e126ba97
EC		 737{
738 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 739 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 740 int err = -ENOMEM;
288c01b7 741 int max_sq_desc;
e126ba97
EC		 742 int max_rq_sg;
743 int max_sq_sg;
e0238a6a 744 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
85c7c014 745 bool raw_support = !mlx5_core_mp_enabled(mdev);
402ca536
BW		 746 struct mlx5_ib_query_device_resp resp = {};
747 size_t resp_len;
748 u64 max_tso;
e126ba97 749
402ca536
BW		 750 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
751 if (uhw->outlen && uhw->outlen < resp_len)
752 return -EINVAL;
753 else
754 resp.response_length = resp_len;
755
756 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 757 return -EINVAL;
758
1b5daf11
MD		 759 memset(props, 0, sizeof(*props));
760 err = mlx5_query_system_image_guid(ibdev,
761 &props->sys_image_guid);
762 if (err)
763 return err;
e126ba97 764
1b5daf11 765 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 766 if (err)
1b5daf11 767 return err;
e126ba97 768
1b5daf11
MD		 769 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
770 if (err)
771 return err;
e126ba97 772
9603b61d
JM		 773 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
774 (fw_rev_min(dev->mdev) << 16) |
775 fw_rev_sub(dev->mdev);
e126ba97
EC		 776 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
777 IB_DEVICE_PORT_ACTIVE_EVENT |
778 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 779 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 780
781 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 782 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 783 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 784 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 785 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 786 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 787 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 788 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 789 if (MLX5_CAP_GEN(mdev, imaicl)) {
790 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
791 IB_DEVICE_MEM_WINDOW_TYPE_2B;
792 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 793 /* We support 'Gappy' memory registration too */
794 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 795 }
e126ba97 796 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 797 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 798 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
799 /* At this stage no support for signature handover */
800 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
801 IB_PROT_T10DIF_TYPE_2 |
802 IB_PROT_T10DIF_TYPE_3;
803 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
804 IB_GUARD_T10DIF_CSUM;
805 }
938fe83c 806 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 807 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 808
85c7c014 809 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
e8161334
NO		 810 if (MLX5_CAP_ETH(mdev, csum_cap)) {
811 /* Legacy bit to support old userspace libraries */
88115fe7 812 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 813 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
814 }
815
816 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
817 props->raw_packet_caps |=
818 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 819
402ca536
BW		 820 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
821 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
822 if (max_tso) {
823 resp.tso_caps.max_tso = 1 << max_tso;
824 resp.tso_caps.supported_qpts |=
825 1 << IB_QPT_RAW_PACKET;
826 resp.response_length += sizeof(resp.tso_caps);
827 }
828 }
31f69a82
YH		 829
830 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
831 resp.rss_caps.rx_hash_function =
832 MLX5_RX_HASH_FUNC_TOEPLITZ;
833 resp.rss_caps.rx_hash_fields_mask =
834 MLX5_RX_HASH_SRC_IPV4 |
835 MLX5_RX_HASH_DST_IPV4 |
836 MLX5_RX_HASH_SRC_IPV6 |
837 MLX5_RX_HASH_DST_IPV6 |
838 MLX5_RX_HASH_SRC_PORT_TCP |
839 MLX5_RX_HASH_DST_PORT_TCP |
840 MLX5_RX_HASH_SRC_PORT_UDP |
4e2b53a5
MG		 841 MLX5_RX_HASH_DST_PORT_UDP |
842 MLX5_RX_HASH_INNER;
31f69a82
YH		 843 resp.response_length += sizeof(resp.rss_caps);
844 }
845 } else {
846 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
847 resp.response_length += sizeof(resp.tso_caps);
848 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
849 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 850 }
851
f0313965
ES		 852 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
853 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
854 props->device_cap_flags |= IB_DEVICE_UD_TSO;
855 }
856
03404e8a 857 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
85c7c014
DJ		 858 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
859 raw_support)
03404e8a
MG		 860 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
861
1d54f890
YH		 862 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
863 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
864 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
865
cff5a0f3 866 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
85c7c014
DJ		 867 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
868 raw_support) {
e8161334 869 /* Legacy bit to support old userspace libraries */
cff5a0f3 870 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 871 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
872 }
cff5a0f3 873
da6d6ba3
MG		 874 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
875 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
876
b1383aa6
NO		 877 if (MLX5_CAP_GEN(mdev, end_pad))
878 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
879
1b5daf11
MD		 880 props->vendor_part_id = mdev->pdev->device;
881 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 882
883 props->max_mr_size = ~0ull;
e0238a6a 884 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 885 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
886 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
887 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
888 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 889 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
890 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
891 sizeof(struct mlx5_wqe_raddr_seg)) /
892 sizeof(struct mlx5_wqe_data_seg);
e126ba97 893 props->max_sge = min(max_rq_sg, max_sq_sg);
986ef95e 894 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 895 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 896 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 897 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
898 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
899 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
900 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
901 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
902 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
903 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 904 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 905 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 906 props->max_fast_reg_page_list_len =
907 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
776a3906 908 get_atomic_caps_qp(dev, props);
81bea28f 909 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 910 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
911 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 912 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
913 props->max_mcast_grp;
914 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 915 props->max_ah = INT_MAX;
7c60bcbb
MB		 916 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
917 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 918
8cdd312c 919#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 920 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 921 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
922 props->odp_caps = dev->odp_caps;
923#endif
924
051f2630
LR		 925 if (MLX5_CAP_GEN(mdev, cd))
926 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
927
eff901d3
EC		 928 if (!mlx5_core_is_pf(mdev))
929 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
930
31f69a82 931 if (mlx5_ib_port_link_layer(ibdev, 1) ==
85c7c014 932 IB_LINK_LAYER_ETHERNET && raw_support) {
31f69a82
YH		 933 props->rss_caps.max_rwq_indirection_tables =
934 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
935 props->rss_caps.max_rwq_indirection_table_size =
936 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
937 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
938 props->max_wq_type_rq =
939 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
940 }
941
eb761894 942 if (MLX5_CAP_GEN(mdev, tag_matching)) {
78b1beb0
LR		 943 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
944 props->tm_caps.max_num_tags =
eb761894 945 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
78b1beb0
LR		 946 props->tm_caps.flags = IB_TM_CAP_RC;
947 props->tm_caps.max_ops =
eb761894 948 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
78b1beb0 949 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
eb761894
AK		 950 }
951
87ab3f52
YC		 952 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
953 props->cq_caps.max_cq_moderation_count =
954 MLX5_MAX_CQ_COUNT;
955 props->cq_caps.max_cq_moderation_period =
956 MLX5_MAX_CQ_PERIOD;
957 }
958
7e43a2a5
BW		 959 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
960 resp.cqe_comp_caps.max_num =
961 MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
962 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
963 resp.cqe_comp_caps.supported_format =
964 MLX5_IB_CQE_RES_FORMAT_HASH |
965 MLX5_IB_CQE_RES_FORMAT_CSUM;
966 resp.response_length += sizeof(resp.cqe_comp_caps);
967 }
968
85c7c014
DJ		 969 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
970 raw_support) {
d949167d
BW		 971 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
972 MLX5_CAP_GEN(mdev, qos)) {
973 resp.packet_pacing_caps.qp_rate_limit_max =
974 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
975 resp.packet_pacing_caps.qp_rate_limit_min =
976 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
977 resp.packet_pacing_caps.supported_qpts |=
978 1 << IB_QPT_RAW_PACKET;
979 }
980 resp.response_length += sizeof(resp.packet_pacing_caps);
981 }
982
9f885201
LR		 983 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
984 uhw->outlen)) {
795b609c
BW		 985 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
986 resp.mlx5_ib_support_multi_pkt_send_wqes =
987 MLX5_IB_ALLOW_MPW;
050da902
BW		 988
989 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
990 resp.mlx5_ib_support_multi_pkt_send_wqes |=
991 MLX5_IB_SUPPORT_EMPW;
992
9f885201
LR		 993 resp.response_length +=
994 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
995 }
996
de57f2ad
GL		 997 if (field_avail(typeof(resp), flags, uhw->outlen)) {
998 resp.response_length += sizeof(resp.flags);
7a0c8f42 999
de57f2ad
GL		 1000 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1001 resp.flags |=
1002 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
7a0c8f42
GL		 1003
1004 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1005 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
de57f2ad 1006 }
9f885201 1007
96dc3fc5
NO		 1008 if (field_avail(typeof(resp), sw_parsing_caps,
1009 uhw->outlen)) {
1010 resp.response_length += sizeof(resp.sw_parsing_caps);
1011 if (MLX5_CAP_ETH(mdev, swp)) {
1012 resp.sw_parsing_caps.sw_parsing_offloads |=
1013 MLX5_IB_SW_PARSING;
1014
1015 if (MLX5_CAP_ETH(mdev, swp_csum))
1016 resp.sw_parsing_caps.sw_parsing_offloads |=
1017 MLX5_IB_SW_PARSING_CSUM;
1018
1019 if (MLX5_CAP_ETH(mdev, swp_lso))
1020 resp.sw_parsing_caps.sw_parsing_offloads |=
1021 MLX5_IB_SW_PARSING_LSO;
1022
1023 if (resp.sw_parsing_caps.sw_parsing_offloads)
1024 resp.sw_parsing_caps.supported_qpts =
1025 BIT(IB_QPT_RAW_PACKET);
1026 }
1027 }
1028
85c7c014
DJ		 1029 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1030 raw_support) {
b4f34597
NO		 1031 resp.response_length += sizeof(resp.striding_rq_caps);
1032 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1033 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1034 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1035 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1036 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1037 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1038 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1039 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1040 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1041 resp.striding_rq_caps.supported_qpts =
1042 BIT(IB_QPT_RAW_PACKET);
1043 }
1044 }
1045
f95ef6cb
MG		 1046 if (field_avail(typeof(resp), tunnel_offloads_caps,
1047 uhw->outlen)) {
1048 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1049 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1050 resp.tunnel_offloads_caps |=
1051 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1052 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1053 resp.tunnel_offloads_caps |=
1054 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1055 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1056 resp.tunnel_offloads_caps |=
1057 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1058 }
1059
402ca536
BW		 1060 if (uhw->outlen) {
1061 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1062
1063 if (err)
1064 return err;
1065 }
1066
1b5daf11 1067 return 0;
e126ba97
EC		 1068}
1069
1b5daf11
MD		 1070enum mlx5_ib_width {
1071 MLX5_IB_WIDTH_1X = 1 << 0,
1072 MLX5_IB_WIDTH_2X = 1 << 1,
1073 MLX5_IB_WIDTH_4X = 1 << 2,
1074 MLX5_IB_WIDTH_8X = 1 << 3,
1075 MLX5_IB_WIDTH_12X = 1 << 4
1076};
1077
1078static int translate_active_width(struct ib_device *ibdev, u8 active_width,
1079 u8 *ib_width)
e126ba97
EC		 1080{
1081 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 1082 int err = 0;
1083
1084 if (active_width & MLX5_IB_WIDTH_1X) {
1085 *ib_width = IB_WIDTH_1X;
1086 } else if (active_width & MLX5_IB_WIDTH_2X) {
1087 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
1088 (int)active_width);
1089 err = -EINVAL;
1090 } else if (active_width & MLX5_IB_WIDTH_4X) {
1091 *ib_width = IB_WIDTH_4X;
1092 } else if (active_width & MLX5_IB_WIDTH_8X) {
1093 *ib_width = IB_WIDTH_8X;
1094 } else if (active_width & MLX5_IB_WIDTH_12X) {
1095 *ib_width = IB_WIDTH_12X;
1096 } else {
1097 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
1098 (int)active_width);
1099 err = -EINVAL;
e126ba97
EC		 1100 }
1101
1b5daf11
MD		 1102 return err;
1103}
e126ba97 1104
1b5daf11
MD		 1105static int mlx5_mtu_to_ib_mtu(int mtu)
1106{
1107 switch (mtu) {
1108 case 256: return 1;
1109 case 512: return 2;
1110 case 1024: return 3;
1111 case 2048: return 4;
1112 case 4096: return 5;
1113 default:
1114 pr_warn("invalid mtu\n");
1115 return -1;
e126ba97 1116 }
1b5daf11 1117}
e126ba97 1118
1b5daf11
MD		 1119enum ib_max_vl_num {
1120 __IB_MAX_VL_0 = 1,
1121 __IB_MAX_VL_0_1 = 2,
1122 __IB_MAX_VL_0_3 = 3,
1123 __IB_MAX_VL_0_7 = 4,
1124 __IB_MAX_VL_0_14 = 5,
1125};
e126ba97 1126
1b5daf11
MD		 1127enum mlx5_vl_hw_cap {
1128 MLX5_VL_HW_0 = 1,
1129 MLX5_VL_HW_0_1 = 2,
1130 MLX5_VL_HW_0_2 = 3,
1131 MLX5_VL_HW_0_3 = 4,
1132 MLX5_VL_HW_0_4 = 5,
1133 MLX5_VL_HW_0_5 = 6,
1134 MLX5_VL_HW_0_6 = 7,
1135 MLX5_VL_HW_0_7 = 8,
1136 MLX5_VL_HW_0_14 = 15
1137};
e126ba97 1138
1b5daf11
MD		 1139static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1140 u8 *max_vl_num)
1141{
1142 switch (vl_hw_cap) {
1143 case MLX5_VL_HW_0:
1144 *max_vl_num = __IB_MAX_VL_0;
1145 break;
1146 case MLX5_VL_HW_0_1:
1147 *max_vl_num = __IB_MAX_VL_0_1;
1148 break;
1149 case MLX5_VL_HW_0_3:
1150 *max_vl_num = __IB_MAX_VL_0_3;
1151 break;
1152 case MLX5_VL_HW_0_7:
1153 *max_vl_num = __IB_MAX_VL_0_7;
1154 break;
1155 case MLX5_VL_HW_0_14:
1156 *max_vl_num = __IB_MAX_VL_0_14;
1157 break;
e126ba97 1158
1b5daf11
MD		 1159 default:
1160 return -EINVAL;
e126ba97 1161 }
e126ba97 1162
1b5daf11 1163 return 0;
e126ba97
EC		 1164}
1165
1b5daf11
MD		 1166static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1167 struct ib_port_attr *props)
e126ba97 1168{
1b5daf11
MD		 1169 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1170 struct mlx5_core_dev *mdev = dev->mdev;
1171 struct mlx5_hca_vport_context *rep;
046339ea
SM		 1172 u16 max_mtu;
1173 u16 oper_mtu;
1b5daf11
MD		 1174 int err;
1175 u8 ib_link_width_oper;
1176 u8 vl_hw_cap;
e126ba97 1177
1b5daf11
MD		 1178 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1179 if (!rep) {
1180 err = -ENOMEM;
e126ba97 1181 goto out;
e126ba97 1182 }
e126ba97 1183
c4550c63 1184 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 1185
1b5daf11 1186 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 1187 if (err)
1188 goto out;
1189
1b5daf11
MD		 1190 props->lid = rep->lid;
1191 props->lmc = rep->lmc;
1192 props->sm_lid = rep->sm_lid;
1193 props->sm_sl = rep->sm_sl;
1194 props->state = rep->vport_state;
1195 props->phys_state = rep->port_physical_state;
1196 props->port_cap_flags = rep->cap_mask1;
1197 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1198 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1199 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1200 props->bad_pkey_cntr = rep->pkey_violation_counter;
1201 props->qkey_viol_cntr = rep->qkey_violation_counter;
1202 props->subnet_timeout = rep->subnet_timeout;
1203 props->init_type_reply = rep->init_type_reply;
eff901d3 1204 props->grh_required = rep->grh_required;
e126ba97 1205
1b5daf11
MD		 1206 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1207 if (err)
e126ba97 1208 goto out;
e126ba97 1209
1b5daf11
MD		 1210 err = translate_active_width(ibdev, ib_link_width_oper,
1211 &props->active_width);
1212 if (err)
1213 goto out;
d5beb7f2 1214 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 1215 if (err)
1216 goto out;
1217
facc9699 1218 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 1219
1b5daf11 1220 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 1221
facc9699 1222 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 1223
1b5daf11 1224 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1225
1b5daf11
MD		 1226 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1227 if (err)
1228 goto out;
e126ba97 1229
1b5daf11
MD		 1230 err = translate_max_vl_num(ibdev, vl_hw_cap,
1231 &props->max_vl_num);
e126ba97 1232out:
1b5daf11 1233 kfree(rep);
e126ba97
EC		 1234 return err;
1235}
1236
1b5daf11
MD		 1237int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1238 struct ib_port_attr *props)
e126ba97 1239{
095b0927
IT		 1240 unsigned int count;
1241 int ret;
1242
1b5daf11
MD		 1243 switch (mlx5_get_vport_access_method(ibdev)) {
1244 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1245 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1246 break;
e126ba97 1247
1b5daf11 1248 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1249 ret = mlx5_query_hca_port(ibdev, port, props);
1250 break;
e126ba97 1251
3f89a643 1252 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1253 ret = mlx5_query_port_roce(ibdev, port, props);
1254 break;
3f89a643 1255
1b5daf11 1256 default:
095b0927
IT		 1257 ret = -EINVAL;
1258 }
1259
1260 if (!ret && props) {
b3cbd6f0
DJ		 1261 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1262 struct mlx5_core_dev *mdev;
1263 bool put_mdev = true;
1264
1265 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1266 if (!mdev) {
1267 /* If the port isn't affiliated yet query the master.
1268 * The master and slave will have the same values.
1269 */
1270 mdev = dev->mdev;
1271 port = 1;
1272 put_mdev = false;
1273 }
1274 count = mlx5_core_reserved_gids_count(mdev);
1275 if (put_mdev)
1276 mlx5_ib_put_native_port_mdev(dev, port);
095b0927 1277 props->gid_tbl_len -= count;
1b5daf11 1278 }
095b0927 1279 return ret;
1b5daf11 1280}
e126ba97 1281
8e6efa3a
MB		 1282static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1283 struct ib_port_attr *props)
1284{
1285 int ret;
1286
1287 /* Only link layer == ethernet is valid for representors */
1288 ret = mlx5_query_port_roce(ibdev, port, props);
1289 if (ret || !props)
1290 return ret;
1291
1292 /* We don't support GIDS */
1293 props->gid_tbl_len = 0;
1294
1295 return ret;
1296}
1297
1b5daf11
MD		 1298static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1299 union ib_gid *gid)
1300{
1301 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1302 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1303
1b5daf11
MD		 1304 switch (mlx5_get_vport_access_method(ibdev)) {
1305 case MLX5_VPORT_ACCESS_METHOD_MAD:
1306 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1307
1b5daf11
MD		 1308 case MLX5_VPORT_ACCESS_METHOD_HCA:
1309 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1310
1311 default:
1312 return -EINVAL;
1313 }
e126ba97 1314
e126ba97
EC		 1315}
1316
b3cbd6f0
DJ		 1317static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1318 u16 index, u16 *pkey)
1b5daf11
MD		 1319{
1320 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b3cbd6f0
DJ		 1321 struct mlx5_core_dev *mdev;
1322 bool put_mdev = true;
1323 u8 mdev_port_num;
1324 int err;
1b5daf11 1325
b3cbd6f0
DJ		 1326 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1327 if (!mdev) {
1328 /* The port isn't affiliated yet, get the PKey from the master
1329 * port. For RoCE the PKey tables will be the same.
1330 */
1331 put_mdev = false;
1332 mdev = dev->mdev;
1333 mdev_port_num = 1;
1334 }
1335
1336 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1337 index, pkey);
1338 if (put_mdev)
1339 mlx5_ib_put_native_port_mdev(dev, port);
1340
1341 return err;
1342}
1343
1344static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1345 u16 *pkey)
1346{
1b5daf11
MD		 1347 switch (mlx5_get_vport_access_method(ibdev)) {
1348 case MLX5_VPORT_ACCESS_METHOD_MAD:
1349 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1350
1351 case MLX5_VPORT_ACCESS_METHOD_HCA:
1352 case MLX5_VPORT_ACCESS_METHOD_NIC:
b3cbd6f0 1353 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1b5daf11
MD		 1354 default:
1355 return -EINVAL;
1356 }
1357}
e126ba97
EC		 1358
1359static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1360 struct ib_device_modify *props)
1361{
1362 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1363 struct mlx5_reg_node_desc in;
1364 struct mlx5_reg_node_desc out;
1365 int err;
1366
1367 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1368 return -EOPNOTSUPP;
1369
1370 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1371 return 0;
1372
1373 /*
1374 * If possible, pass node desc to FW, so it can generate
1375 * a 144 trap. If cmd fails, just ignore.
1376 */
bd99fdea 1377 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1378 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1379 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1380 if (err)
1381 return err;
1382
bd99fdea 1383 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1384
1385 return err;
1386}
1387
cdbe33d0
EC		 1388static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1389 u32 value)
1390{
1391 struct mlx5_hca_vport_context ctx = {};
b3cbd6f0
DJ		 1392 struct mlx5_core_dev *mdev;
1393 u8 mdev_port_num;
cdbe33d0
EC		 1394 int err;
1395
b3cbd6f0
DJ		 1396 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1397 if (!mdev)
1398 return -ENODEV;
1399
1400 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
cdbe33d0 1401 if (err)
b3cbd6f0 1402 goto out;
cdbe33d0
EC		 1403
1404 if (~ctx.cap_mask1_perm & mask) {
1405 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1406 mask, ctx.cap_mask1_perm);
b3cbd6f0
DJ		 1407 err = -EINVAL;
1408 goto out;
cdbe33d0
EC		 1409 }
1410
1411 ctx.cap_mask1 = value;
1412 ctx.cap_mask1_perm = mask;
b3cbd6f0
DJ		 1413 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1414 0, &ctx);
1415
1416out:
1417 mlx5_ib_put_native_port_mdev(dev, port_num);
cdbe33d0
EC		 1418
1419 return err;
1420}
1421
e126ba97
EC		 1422static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1423 struct ib_port_modify *props)
1424{
1425 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1426 struct ib_port_attr attr;
1427 u32 tmp;
1428 int err;
cdbe33d0
EC		 1429 u32 change_mask;
1430 u32 value;
1431 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1432 IB_LINK_LAYER_INFINIBAND);
1433
ec255879
MD		 1434 /* CM layer calls ib_modify_port() regardless of the link layer. For
1435 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1436 */
1437 if (!is_ib)
1438 return 0;
1439
cdbe33d0
EC		 1440 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1441 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1442 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1443 return set_port_caps_atomic(dev, port, change_mask, value);
1444 }
e126ba97
EC		 1445
1446 mutex_lock(&dev->cap_mask_mutex);
1447
c4550c63 1448 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1449 if (err)
1450 goto out;
1451
1452 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1453 ~props->clr_port_cap_mask;
1454
9603b61d 1455 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1456
1457out:
1458 mutex_unlock(&dev->cap_mask_mutex);
1459 return err;
1460}
1461
30aa60b3
EC		 1462static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1463{
1464 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1465 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1466}
1467
31a78a5a
YH		 1468static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1469{
1470 /* Large page with non 4k uar support might limit the dynamic size */
1471 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1472 return MLX5_MIN_DYN_BFREGS;
1473
1474 return MLX5_MAX_DYN_BFREGS;
1475}
1476
b037c29a
EC		 1477static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1478 struct mlx5_ib_alloc_ucontext_req_v2 *req,
31a78a5a 1479 struct mlx5_bfreg_info *bfregi)
b037c29a
EC		 1480{
1481 int uars_per_sys_page;
1482 int bfregs_per_sys_page;
1483 int ref_bfregs = req->total_num_bfregs;
1484
1485 if (req->total_num_bfregs == 0)
1486 return -EINVAL;
1487
1488 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1489 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1490
1491 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1492 return -ENOMEM;
1493
1494 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1495 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
31a78a5a 1496 /* This holds the required static allocation asked by the user */
b037c29a 1497 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
b037c29a
EC		 1498 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1499 return -EINVAL;
1500
31a78a5a
YH		 1501 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1502 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1503 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1504 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1505
1506 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
b037c29a
EC		 1507 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1508 lib_uar_4k ? "yes" : "no", ref_bfregs,
31a78a5a
YH		 1509 req->total_num_bfregs, bfregi->total_num_bfregs,
1510 bfregi->num_sys_pages);
b037c29a
EC		 1511
1512 return 0;
1513}
1514
1515static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1516{
1517 struct mlx5_bfreg_info *bfregi;
1518 int err;
1519 int i;
1520
1521 bfregi = &context->bfregi;
31a78a5a 1522 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
b037c29a
EC		 1523 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1524 if (err)
1525 goto error;
1526
1527 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1528 }
4ed131d0
YH		 1529
1530 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1531 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1532
b037c29a
EC		 1533 return 0;
1534
1535error:
1536 for (--i; i >= 0; i--)
1537 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1538 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1539
1540 return err;
1541}
1542
1543static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1544{
1545 struct mlx5_bfreg_info *bfregi;
1546 int err;
1547 int i;
1548
1549 bfregi = &context->bfregi;
4ed131d0
YH		 1550 for (i = 0; i < bfregi->num_sys_pages; i++) {
1551 if (i < bfregi->num_static_sys_pages ||
1552 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) {
1553 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1554 if (err) {
1555 mlx5_ib_warn(dev, "failed to free uar %d, err=%d\n", i, err);
1556 return err;
1557 }
b037c29a
EC		 1558 }
1559 }
4ed131d0 1560
b037c29a
EC		 1561 return 0;
1562}
1563
c85023e1
HN		 1564static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1565{
1566 int err;
1567
1568 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1569 if (err)
1570 return err;
1571
1572 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1573 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1574 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1575 return err;
1576
1577 mutex_lock(&dev->lb_mutex);
1578 dev->user_td++;
1579
1580 if (dev->user_td == 2)
1581 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1582
1583 mutex_unlock(&dev->lb_mutex);
1584 return err;
1585}
1586
1587static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1588{
1589 mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1590
1591 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1592 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1593 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1594 return;
1595
1596 mutex_lock(&dev->lb_mutex);
1597 dev->user_td--;
1598
1599 if (dev->user_td < 2)
1600 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1601
1602 mutex_unlock(&dev->lb_mutex);
1603}
1604
e126ba97
EC		 1605static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1606 struct ib_udata *udata)
1607{
1608 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1609 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1610 struct mlx5_ib_alloc_ucontext_resp resp = {};
5c99eaec 1611 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1612 struct mlx5_ib_ucontext *context;
2f5ff264 1613 struct mlx5_bfreg_info *bfregi;
78c0f98c 1614 int ver;
e126ba97 1615 int err;
a168a41c
MD		 1616 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1617 max_cqe_version);
b037c29a 1618 bool lib_uar_4k;
e126ba97
EC		 1619
1620 if (!dev->ib_active)
1621 return ERR_PTR(-EAGAIN);
1622
e093111d 1623 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1624 ver = 0;
e093111d 1625 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1626 ver = 2;
1627 else
1628 return ERR_PTR(-EINVAL);
1629
e093111d 1630 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97
EC		 1631 if (err)
1632 return ERR_PTR(err);
1633
b368d7cb 1634 if (req.flags)
78c0f98c
EC		 1635 return ERR_PTR(-EINVAL);
1636
f72300c5 1637 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 1638 return ERR_PTR(-EOPNOTSUPP);
1639
2f5ff264
EC		 1640 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1641 MLX5_NON_FP_BFREGS_PER_UAR);
1642 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
e126ba97
EC		 1643 return ERR_PTR(-EINVAL);
1644
938fe83c 1645 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1646 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1647 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1648 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1649 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1650 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1651 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1652 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1653 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1654 resp.cqe_version = min_t(__u8,
1655 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1656 req.max_cqe_version);
30aa60b3
EC		 1657 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1658 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1659 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1660 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1661 resp.response_length = min(offsetof(typeof(resp), response_length) +
1662 sizeof(resp.response_length), udata->outlen);
e126ba97
EC		 1663
1664 context = kzalloc(sizeof(*context), GFP_KERNEL);
1665 if (!context)
1666 return ERR_PTR(-ENOMEM);
1667
30aa60b3 1668 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1669 bfregi = &context->bfregi;
b037c29a
EC		 1670
1671 /* updates req->total_num_bfregs */
31a78a5a 1672 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
b037c29a 1673 if (err)
e126ba97 1674 goto out_ctx;
e126ba97 1675
b037c29a
EC		 1676 mutex_init(&bfregi->lock);
1677 bfregi->lib_uar_4k = lib_uar_4k;
31a78a5a 1678 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1679 GFP_KERNEL);
b037c29a 1680 if (!bfregi->count) {
e126ba97 1681 err = -ENOMEM;
b037c29a 1682 goto out_ctx;
e126ba97
EC		 1683 }
1684
b037c29a
EC		 1685 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1686 sizeof(*bfregi->sys_pages),
1687 GFP_KERNEL);
1688 if (!bfregi->sys_pages) {
e126ba97 1689 err = -ENOMEM;
b037c29a 1690 goto out_count;
e126ba97
EC		 1691 }
1692
b037c29a
EC		 1693 err = allocate_uars(dev, context);
1694 if (err)
1695 goto out_sys_pages;
e126ba97 1696
b4cfe447
HE		 1697#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1698 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1699#endif
1700
7d0cc6ed
AK		 1701 context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1702 if (!context->upd_xlt_page) {
1703 err = -ENOMEM;
1704 goto out_uars;
1705 }
1706 mutex_init(&context->upd_xlt_page_mutex);
1707
146d2f1a 1708 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
c85023e1 1709 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
146d2f1a 1710 if (err)
7d0cc6ed 1711 goto out_page;
146d2f1a 1712 }
1713
7c2344c3 1714 INIT_LIST_HEAD(&context->vma_private_list);
ad9a3668 1715 mutex_init(&context->vma_private_list_mutex);
e126ba97
EC		 1716 INIT_LIST_HEAD(&context->db_page_list);
1717 mutex_init(&context->db_page_mutex);
1718
2f5ff264 1719 resp.tot_bfregs = req.total_num_bfregs;
508562d6 1720 resp.num_ports = dev->num_ports;
b368d7cb 1721
f72300c5
HA		 1722 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1723 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1724
402ca536 1725 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1726 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1727 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1728 resp.response_length += sizeof(resp.cmds_supp_uhw);
1729 }
1730
78984898
OG		 1731 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1732 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1733 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1734 resp.eth_min_inline++;
1735 }
1736 resp.response_length += sizeof(resp.eth_min_inline);
1737 }
1738
5c99eaec
FD		 1739 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1740 if (mdev->clock_info)
1741 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1742 resp.response_length += sizeof(resp.clock_info_versions);
1743 }
1744
bc5c6eed
NO		 1745 /*
1746 * We don't want to expose information from the PCI bar that is located
1747 * after 4096 bytes, so if the arch only supports larger pages, let's
1748 * pretend we don't support reading the HCA's core clock. This is also
1749 * forced by mmap function.
1750 */
de8d6e02
EC		 1751 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1752 if (PAGE_SIZE <= 4096) {
1753 resp.comp_mask |=
1754 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1755 resp.hca_core_clock_offset =
1756 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1757 }
5c99eaec 1758 resp.response_length += sizeof(resp.hca_core_clock_offset);
b368d7cb
MB		 1759 }
1760
30aa60b3
EC		 1761 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1762 resp.response_length += sizeof(resp.log_uar_size);
1763
1764 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1765 resp.response_length += sizeof(resp.num_uars_per_page);
1766
31a78a5a
YH		 1767 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1768 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1769 resp.response_length += sizeof(resp.num_dyn_bfregs);
1770 }
1771
b368d7cb 1772 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1773 if (err)
146d2f1a 1774 goto out_td;
e126ba97 1775
2f5ff264
EC		 1776 bfregi->ver = ver;
1777 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1778 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1779 context->lib_caps = req.lib_caps;
1780 print_lib_caps(dev, context->lib_caps);
f72300c5 1781
e126ba97
EC		 1782 return &context->ibucontext;
1783
146d2f1a 1784out_td:
1785 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
c85023e1 1786 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1787
7d0cc6ed
AK		 1788out_page:
1789 free_page(context->upd_xlt_page);
1790
e126ba97 1791out_uars:
b037c29a 1792 deallocate_uars(dev, context);
e126ba97 1793
b037c29a
EC		 1794out_sys_pages:
1795 kfree(bfregi->sys_pages);
e126ba97 1796
b037c29a
EC		 1797out_count:
1798 kfree(bfregi->count);
e126ba97
EC		 1799
1800out_ctx:
1801 kfree(context);
b037c29a 1802
e126ba97
EC		 1803 return ERR_PTR(err);
1804}
1805
1806static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1807{
1808 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1809 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 1810 struct mlx5_bfreg_info *bfregi;
e126ba97 1811
b037c29a 1812 bfregi = &context->bfregi;
146d2f1a 1813 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
c85023e1 1814 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1815
7d0cc6ed 1816 free_page(context->upd_xlt_page);
b037c29a
EC		 1817 deallocate_uars(dev, context);
1818 kfree(bfregi->sys_pages);
2f5ff264 1819 kfree(bfregi->count);
e126ba97
EC		 1820 kfree(context);
1821
1822 return 0;
1823}
1824
b037c29a 1825static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
4ed131d0 1826 int uar_idx)
e126ba97 1827{
b037c29a
EC		 1828 int fw_uars_per_page;
1829
1830 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1831
4ed131d0 1832 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
e126ba97
EC		 1833}
1834
1835static int get_command(unsigned long offset)
1836{
1837 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1838}
1839
1840static int get_arg(unsigned long offset)
1841{
1842 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1843}
1844
1845static int get_index(unsigned long offset)
1846{
1847 return get_arg(offset);
1848}
1849
4ed131d0
YH		 1850/* Index resides in an extra byte to enable larger values than 255 */
1851static int get_extended_index(unsigned long offset)
1852{
1853 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1854}
1855
7c2344c3
MG		 1856static void mlx5_ib_vma_open(struct vm_area_struct *area)
1857{
1858 /* vma_open is called when a new VMA is created on top of our VMA. This
1859 * is done through either mremap flow or split_vma (usually due to
1860 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1861 * as this VMA is strongly hardware related. Therefore we set the
1862 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1863 * calling us again and trying to do incorrect actions. We assume that
1864 * the original VMA size is exactly a single page, and therefore all
1865 * "splitting" operation will not happen to it.
1866 */
1867 area->vm_ops = NULL;
1868}
1869
1870static void mlx5_ib_vma_close(struct vm_area_struct *area)
1871{
1872 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1873
1874 /* It's guaranteed that all VMAs opened on a FD are closed before the
1875 * file itself is closed, therefore no sync is needed with the regular
1876 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1877 * However need a sync with accessing the vma as part of
1878 * mlx5_ib_disassociate_ucontext.
1879 * The close operation is usually called under mm->mmap_sem except when
1880 * process is exiting.
1881 * The exiting case is handled explicitly as part of
1882 * mlx5_ib_disassociate_ucontext.
1883 */
1884 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1885
1886 /* setting the vma context pointer to null in the mlx5_ib driver's
1887 * private data, to protect a race condition in
1888 * mlx5_ib_disassociate_ucontext().
1889 */
1890 mlx5_ib_vma_priv_data->vma = NULL;
ad9a3668 1891 mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
7c2344c3 1892 list_del(&mlx5_ib_vma_priv_data->list);
ad9a3668 1893 mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
7c2344c3
MG		 1894 kfree(mlx5_ib_vma_priv_data);
1895}
1896
1897static const struct vm_operations_struct mlx5_ib_vm_ops = {
1898 .open = mlx5_ib_vma_open,
1899 .close = mlx5_ib_vma_close
1900};
1901
1902static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1903 struct mlx5_ib_ucontext *ctx)
1904{
1905 struct mlx5_ib_vma_private_data *vma_prv;
1906 struct list_head *vma_head = &ctx->vma_private_list;
1907
1908 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1909 if (!vma_prv)
1910 return -ENOMEM;
1911
1912 vma_prv->vma = vma;
ad9a3668 1913 vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
7c2344c3
MG		 1914 vma->vm_private_data = vma_prv;
1915 vma->vm_ops = &mlx5_ib_vm_ops;
1916
ad9a3668 1917 mutex_lock(&ctx->vma_private_list_mutex);
7c2344c3 1918 list_add(&vma_prv->list, vma_head);
ad9a3668 1919 mutex_unlock(&ctx->vma_private_list_mutex);
7c2344c3
MG		 1920
1921 return 0;
1922}
1923
1924static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1925{
1926 int ret;
1927 struct vm_area_struct *vma;
1928 struct mlx5_ib_vma_private_data *vma_private, *n;
1929 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1930 struct task_struct *owning_process = NULL;
1931 struct mm_struct *owning_mm = NULL;
1932
1933 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1934 if (!owning_process)
1935 return;
1936
1937 owning_mm = get_task_mm(owning_process);
1938 if (!owning_mm) {
1939 pr_info("no mm, disassociate ucontext is pending task termination\n");
1940 while (1) {
1941 put_task_struct(owning_process);
1942 usleep_range(1000, 2000);
1943 owning_process = get_pid_task(ibcontext->tgid,
1944 PIDTYPE_PID);
1945 if (!owning_process ||
1946 owning_process->state == TASK_DEAD) {
1947 pr_info("disassociate ucontext done, task was terminated\n");
1948 /* in case task was dead need to release the
1949 * task struct.
1950 */
1951 if (owning_process)
1952 put_task_struct(owning_process);
1953 return;
1954 }
1955 }
1956 }
1957
1958 /* need to protect from a race on closing the vma as part of
1959 * mlx5_ib_vma_close.
1960 */
ecc7d83b 1961 down_write(&owning_mm->mmap_sem);
ad9a3668 1962 mutex_lock(&context->vma_private_list_mutex);
7c2344c3
MG		 1963 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1964 list) {
1965 vma = vma_private->vma;
1966 ret = zap_vma_ptes(vma, vma->vm_start,
1967 PAGE_SIZE);
1968 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1969 /* context going to be destroyed, should
1970 * not access ops any more.
1971 */
13776612 1972 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
7c2344c3
MG		 1973 vma->vm_ops = NULL;
1974 list_del(&vma_private->list);
1975 kfree(vma_private);
1976 }
ad9a3668 1977 mutex_unlock(&context->vma_private_list_mutex);
ecc7d83b 1978 up_write(&owning_mm->mmap_sem);
7c2344c3
MG		 1979 mmput(owning_mm);
1980 put_task_struct(owning_process);
1981}
1982
37aa5c36
GL		 1983static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1984{
1985 switch (cmd) {
1986 case MLX5_IB_MMAP_WC_PAGE:
1987 return "WC";
1988 case MLX5_IB_MMAP_REGULAR_PAGE:
1989 return "best effort WC";
1990 case MLX5_IB_MMAP_NC_PAGE:
1991 return "NC";
1992 default:
1993 return NULL;
1994 }
1995}
1996
5c99eaec
FD		 1997static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
1998 struct vm_area_struct *vma,
1999 struct mlx5_ib_ucontext *context)
2000{
2001 phys_addr_t pfn;
2002 int err;
2003
2004 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2005 return -EINVAL;
2006
2007 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2008 return -EOPNOTSUPP;
2009
2010 if (vma->vm_flags & VM_WRITE)
2011 return -EPERM;
2012
2013 if (!dev->mdev->clock_info_page)
2014 return -EOPNOTSUPP;
2015
2016 pfn = page_to_pfn(dev->mdev->clock_info_page);
2017 err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE,
2018 vma->vm_page_prot);
2019 if (err)
2020 return err;
2021
2022 mlx5_ib_dbg(dev, "mapped clock info at 0x%lx, PA 0x%llx\n",
2023 vma->vm_start,
2024 (unsigned long long)pfn << PAGE_SHIFT);
2025
2026 return mlx5_ib_set_vma_data(vma, context);
2027}
2028
37aa5c36 2029static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 2030 struct vm_area_struct *vma,
2031 struct mlx5_ib_ucontext *context)
37aa5c36 2032{
2f5ff264 2033 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 2034 int err;
2035 unsigned long idx;
2036 phys_addr_t pfn, pa;
2037 pgprot_t prot;
4ed131d0
YH		 2038 u32 bfreg_dyn_idx = 0;
2039 u32 uar_index;
2040 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2041 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2042 bfregi->num_static_sys_pages;
b037c29a
EC		 2043
2044 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2045 return -EINVAL;
2046
4ed131d0
YH		 2047 if (dyn_uar)
2048 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2049 else
2050 idx = get_index(vma->vm_pgoff);
2051
2052 if (idx >= max_valid_idx) {
2053 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2054 idx, max_valid_idx);
b037c29a
EC		 2055 return -EINVAL;
2056 }
37aa5c36
GL		 2057
2058 switch (cmd) {
2059 case MLX5_IB_MMAP_WC_PAGE:
4ed131d0 2060 case MLX5_IB_MMAP_ALLOC_WC:
37aa5c36
GL		 2061/* Some architectures don't support WC memory */
2062#if defined(CONFIG_X86)
2063 if (!pat_enabled())
2064 return -EPERM;
2065#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2066 return -EPERM;
2067#endif
2068 /* fall through */
2069 case MLX5_IB_MMAP_REGULAR_PAGE:
2070 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2071 prot = pgprot_writecombine(vma->vm_page_prot);
2072 break;
2073 case MLX5_IB_MMAP_NC_PAGE:
2074 prot = pgprot_noncached(vma->vm_page_prot);
2075 break;
2076 default:
2077 return -EINVAL;
2078 }
2079
4ed131d0
YH		 2080 if (dyn_uar) {
2081 int uars_per_page;
2082
2083 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2084 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2085 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2086 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2087 bfreg_dyn_idx, bfregi->total_num_bfregs);
2088 return -EINVAL;
2089 }
2090
2091 mutex_lock(&bfregi->lock);
2092 /* Fail if uar already allocated, first bfreg index of each
2093 * page holds its count.
2094 */
2095 if (bfregi->count[bfreg_dyn_idx]) {
2096 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2097 mutex_unlock(&bfregi->lock);
2098 return -EINVAL;
2099 }
2100
2101 bfregi->count[bfreg_dyn_idx]++;
2102 mutex_unlock(&bfregi->lock);
2103
2104 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2105 if (err) {
2106 mlx5_ib_warn(dev, "UAR alloc failed\n");
2107 goto free_bfreg;
2108 }
2109 } else {
2110 uar_index = bfregi->sys_pages[idx];
2111 }
2112
2113 pfn = uar_index2pfn(dev, uar_index);
37aa5c36
GL		 2114 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2115
2116 vma->vm_page_prot = prot;
2117 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
2118 PAGE_SIZE, vma->vm_page_prot);
2119 if (err) {
2120 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
2121 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
4ed131d0
YH		 2122 err = -EAGAIN;
2123 goto err;
37aa5c36
GL		 2124 }
2125
2126 pa = pfn << PAGE_SHIFT;
2127 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
2128 vma->vm_start, &pa);
2129
4ed131d0
YH		 2130 err = mlx5_ib_set_vma_data(vma, context);
2131 if (err)
2132 goto err;
2133
2134 if (dyn_uar)
2135 bfregi->sys_pages[idx] = uar_index;
2136 return 0;
2137
2138err:
2139 if (!dyn_uar)
2140 return err;
2141
2142 mlx5_cmd_free_uar(dev->mdev, idx);
2143
2144free_bfreg:
2145 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2146
2147 return err;
37aa5c36
GL		 2148}
2149
e126ba97
EC		 2150static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2151{
2152 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2153 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 2154 unsigned long command;
e126ba97
EC		 2155 phys_addr_t pfn;
2156
2157 command = get_command(vma->vm_pgoff);
2158 switch (command) {
37aa5c36
GL		 2159 case MLX5_IB_MMAP_WC_PAGE:
2160 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 2161 case MLX5_IB_MMAP_REGULAR_PAGE:
4ed131d0 2162 case MLX5_IB_MMAP_ALLOC_WC:
7c2344c3 2163 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 2164
2165 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2166 return -ENOSYS;
2167
d69e3bcf 2168 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 2169 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2170 return -EINVAL;
2171
6cbac1e4 2172 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 2173 return -EPERM;
2174
2175 /* Don't expose to user-space information it shouldn't have */
2176 if (PAGE_SIZE > 4096)
2177 return -EOPNOTSUPP;
2178
2179 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2180 pfn = (dev->mdev->iseg_base +
2181 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2182 PAGE_SHIFT;
2183 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2184 PAGE_SIZE, vma->vm_page_prot))
2185 return -EAGAIN;
2186
2187 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
2188 vma->vm_start,
2189 (unsigned long long)pfn << PAGE_SHIFT);
2190 break;
5c99eaec
FD		 2191 case MLX5_IB_MMAP_CLOCK_INFO:
2192 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
d69e3bcf 2193
e126ba97
EC		 2194 default:
2195 return -EINVAL;
2196 }
2197
2198 return 0;
2199}
2200
e126ba97
EC		 2201static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2202 struct ib_ucontext *context,
2203 struct ib_udata *udata)
2204{
2205 struct mlx5_ib_alloc_pd_resp resp;
2206 struct mlx5_ib_pd *pd;
2207 int err;
2208
2209 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
2210 if (!pd)
2211 return ERR_PTR(-ENOMEM);
2212
9603b61d 2213 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 2214 if (err) {
2215 kfree(pd);
2216 return ERR_PTR(err);
2217 }
2218
2219 if (context) {
2220 resp.pdn = pd->pdn;
2221 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 2222 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 2223 kfree(pd);
2224 return ERR_PTR(-EFAULT);
2225 }
e126ba97
EC		 2226 }
2227
2228 return &pd->ibpd;
2229}
2230
2231static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2232{
2233 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2234 struct mlx5_ib_pd *mpd = to_mpd(pd);
2235
9603b61d 2236 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 2237 kfree(mpd);
2238
2239 return 0;
2240}
2241
466fa6d2
MG		 2242enum {
2243 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2244 MATCH_CRITERIA_ENABLE_MISC_BIT,
2245 MATCH_CRITERIA_ENABLE_INNER_BIT
2246};
2247
2248#define HEADER_IS_ZERO(match_criteria, headers) \
2249 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2250 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 2251
466fa6d2 2252static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 2253{
466fa6d2 2254 u8 match_criteria_enable;
038d2ef8 2255
466fa6d2
MG		 2256 match_criteria_enable =
2257 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2258 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2259 match_criteria_enable |=
2260 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2261 MATCH_CRITERIA_ENABLE_MISC_BIT;
2262 match_criteria_enable |=
2263 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2264 MATCH_CRITERIA_ENABLE_INNER_BIT;
2265
2266 return match_criteria_enable;
038d2ef8
MG		 2267}
2268
ca0d4753
MG		 2269static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2270{
2271 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2272 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
038d2ef8
MG		 2273}
2274
2d1e697e
MR		 2275static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
2276 bool inner)
2277{
2278 if (inner) {
2279 MLX5_SET(fte_match_set_misc,
2280 misc_c, inner_ipv6_flow_label, mask);
2281 MLX5_SET(fte_match_set_misc,
2282 misc_v, inner_ipv6_flow_label, val);
2283 } else {
2284 MLX5_SET(fte_match_set_misc,
2285 misc_c, outer_ipv6_flow_label, mask);
2286 MLX5_SET(fte_match_set_misc,
2287 misc_v, outer_ipv6_flow_label, val);
2288 }
2289}
2290
ca0d4753
MG		 2291static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2292{
2293 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2294 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2295 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2296 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2297}
2298
c47ac6ae
MG		 2299#define LAST_ETH_FIELD vlan_tag
2300#define LAST_IB_FIELD sl
ca0d4753 2301#define LAST_IPV4_FIELD tos
466fa6d2 2302#define LAST_IPV6_FIELD traffic_class
c47ac6ae 2303#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 2304#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 2305#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 2306#define LAST_DROP_FIELD size
c47ac6ae
MG		 2307
2308/* Field is the last supported field */
2309#define FIELDS_NOT_SUPPORTED(filter, field)\
2310 memchr_inv((void *)&filter.field +\
2311 sizeof(filter.field), 0,\
2312 sizeof(filter) -\
2313 offsetof(typeof(filter), field) -\
2314 sizeof(filter.field))
2315
19cc7524
AL		 2316static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2317 u32 *match_v, const union ib_flow_spec *ib_spec,
075572d4 2318 struct mlx5_flow_act *action)
038d2ef8 2319{
466fa6d2
MG		 2320 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2321 misc_parameters);
2322 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2323 misc_parameters);
2d1e697e
MR		 2324 void *headers_c;
2325 void *headers_v;
19cc7524 2326 int match_ipv;
2d1e697e
MR		 2327
2328 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2329 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2330 inner_headers);
2331 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2332 inner_headers);
19cc7524
AL		 2333 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2334 ft_field_support.inner_ip_version);
2d1e697e
MR		 2335 } else {
2336 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2337 outer_headers);
2338 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2339 outer_headers);
19cc7524
AL		 2340 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2341 ft_field_support.outer_ip_version);
2d1e697e 2342 }
466fa6d2 2343
2d1e697e 2344 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 2345 case IB_FLOW_SPEC_ETH:
c47ac6ae 2346 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 2347 return -EOPNOTSUPP;
038d2ef8 2348
2d1e697e 2349 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2350 dmac_47_16),
2351 ib_spec->eth.mask.dst_mac);
2d1e697e 2352 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2353 dmac_47_16),
2354 ib_spec->eth.val.dst_mac);
2355
2d1e697e 2356 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 2357 smac_47_16),
2358 ib_spec->eth.mask.src_mac);
2d1e697e 2359 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 2360 smac_47_16),
2361 ib_spec->eth.val.src_mac);
2362
038d2ef8 2363 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 2364 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 2365 cvlan_tag, 1);
2d1e697e 2366 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 2367 cvlan_tag, 1);
038d2ef8 2368
2d1e697e 2369 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2370 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 2371 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2372 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2373
2d1e697e 2374 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2375 first_cfi,
2376 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 2377 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2378 first_cfi,
2379 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2380
2d1e697e 2381 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2382 first_prio,
2383 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 2384 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2385 first_prio,
2386 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2387 }
2d1e697e 2388 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2389 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 2390 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2391 ethertype, ntohs(ib_spec->eth.val.ether_type));
2392 break;
2393 case IB_FLOW_SPEC_IPV4:
c47ac6ae 2394 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 2395 return -EOPNOTSUPP;
038d2ef8 2396
19cc7524
AL		 2397 if (match_ipv) {
2398 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2399 ip_version, 0xf);
2400 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2401 ip_version, MLX5_FS_IPV4_VERSION);
19cc7524
AL		 2402 } else {
2403 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2404 ethertype, 0xffff);
2405 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2406 ethertype, ETH_P_IP);
2407 }
038d2ef8 2408
2d1e697e 2409 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2410 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2411 &ib_spec->ipv4.mask.src_ip,
2412 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 2413 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2414 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2415 &ib_spec->ipv4.val.src_ip,
2416 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 2417 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2418 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2419 &ib_spec->ipv4.mask.dst_ip,
2420 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 2421 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2422 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2423 &ib_spec->ipv4.val.dst_ip,
2424 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 2425
2d1e697e 2426 set_tos(headers_c, headers_v,
ca0d4753
MG		 2427 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2428
2d1e697e 2429 set_proto(headers_c, headers_v,
ca0d4753 2430 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
038d2ef8 2431 break;
026bae0c 2432 case IB_FLOW_SPEC_IPV6:
c47ac6ae 2433 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 2434 return -EOPNOTSUPP;
026bae0c 2435
19cc7524
AL		 2436 if (match_ipv) {
2437 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2438 ip_version, 0xf);
2439 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2440 ip_version, MLX5_FS_IPV6_VERSION);
19cc7524
AL		 2441 } else {
2442 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2443 ethertype, 0xffff);
2444 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2445 ethertype, ETH_P_IPV6);
2446 }
026bae0c 2447
2d1e697e 2448 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2449 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2450 &ib_spec->ipv6.mask.src_ip,
2451 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2452 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2453 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2454 &ib_spec->ipv6.val.src_ip,
2455 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2456 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2457 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2458 &ib_spec->ipv6.mask.dst_ip,
2459 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2460 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2461 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2462 &ib_spec->ipv6.val.dst_ip,
2463 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2464
2d1e697e 2465 set_tos(headers_c, headers_v,
466fa6d2
MG		 2466 ib_spec->ipv6.mask.traffic_class,
2467 ib_spec->ipv6.val.traffic_class);
2468
2d1e697e 2469 set_proto(headers_c, headers_v,
466fa6d2
MG		 2470 ib_spec->ipv6.mask.next_hdr,
2471 ib_spec->ipv6.val.next_hdr);
2472
2d1e697e
MR		 2473 set_flow_label(misc_params_c, misc_params_v,
2474 ntohl(ib_spec->ipv6.mask.flow_label),
2475 ntohl(ib_spec->ipv6.val.flow_label),
2476 ib_spec->type & IB_FLOW_SPEC_INNER);
2477
026bae0c 2478 break;
038d2ef8 2479 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2480 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2481 LAST_TCP_UDP_FIELD))
1ffd3a26 2482 return -EOPNOTSUPP;
038d2ef8 2483
2d1e697e 2484 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2485 0xff);
2d1e697e 2486 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2487 IPPROTO_TCP);
2488
2d1e697e 2489 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2490 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2491 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2492 ntohs(ib_spec->tcp_udp.val.src_port));
2493
2d1e697e 2494 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2495 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2496 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2497 ntohs(ib_spec->tcp_udp.val.dst_port));
2498 break;
2499 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2500 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2501 LAST_TCP_UDP_FIELD))
1ffd3a26 2502 return -EOPNOTSUPP;
038d2ef8 2503
2d1e697e 2504 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2505 0xff);
2d1e697e 2506 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2507 IPPROTO_UDP);
2508
2d1e697e 2509 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2510 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2511 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2512 ntohs(ib_spec->tcp_udp.val.src_port));
2513
2d1e697e 2514 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2515 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2516 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2517 ntohs(ib_spec->tcp_udp.val.dst_port));
2518 break;
ffb30d8f
MR		 2519 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2520 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2521 LAST_TUNNEL_FIELD))
1ffd3a26 2522 return -EOPNOTSUPP;
ffb30d8f
MR		 2523
2524 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2525 ntohl(ib_spec->tunnel.mask.tunnel_id));
2526 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2527 ntohl(ib_spec->tunnel.val.tunnel_id));
2528 break;
2ac693f9
MR		 2529 case IB_FLOW_SPEC_ACTION_TAG:
2530 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2531 LAST_FLOW_TAG_FIELD))
2532 return -EOPNOTSUPP;
2533 if (ib_spec->flow_tag.tag_id >= BIT(24))
2534 return -EINVAL;
2535
075572d4 2536 action->flow_tag = ib_spec->flow_tag.tag_id;
a9db0ecf 2537 action->has_flow_tag = true;
2ac693f9 2538 break;
a22ed86c
SS		 2539 case IB_FLOW_SPEC_ACTION_DROP:
2540 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2541 LAST_DROP_FIELD))
2542 return -EOPNOTSUPP;
075572d4 2543 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
a22ed86c 2544 break;
038d2ef8
MG		 2545 default:
2546 return -EINVAL;
2547 }
2548
2549 return 0;
2550}
2551
2552/* If a flow could catch both multicast and unicast packets,
2553 * it won't fall into the multicast flow steering table and this rule
2554 * could steal other multicast packets.
2555 */
a550ddfc 2556static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
038d2ef8 2557{
81e30880 2558 union ib_flow_spec *flow_spec;
038d2ef8
MG		 2559
2560 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 2561 ib_attr->num_of_specs < 1)
2562 return false;
2563
81e30880
YH		 2564 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2565 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2566 struct ib_flow_spec_ipv4 *ipv4_spec;
2567
2568 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2569 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2570 return true;
2571
038d2ef8 2572 return false;
81e30880
YH		 2573 }
2574
2575 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2576 struct ib_flow_spec_eth *eth_spec;
2577
2578 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2579 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2580 is_multicast_ether_addr(eth_spec->val.dst_mac);
2581 }
038d2ef8 2582
81e30880 2583 return false;
038d2ef8
MG		 2584}
2585
19cc7524
AL		 2586static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2587 const struct ib_flow_attr *flow_attr,
0f750966 2588 bool check_inner)
038d2ef8
MG		 2589{
2590 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 2591 int match_ipv = check_inner ?
2592 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2593 ft_field_support.inner_ip_version) :
2594 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2595 ft_field_support.outer_ip_version);
0f750966
AL		 2596 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2597 bool ipv4_spec_valid, ipv6_spec_valid;
2598 unsigned int ip_spec_type = 0;
2599 bool has_ethertype = false;
038d2ef8 2600 unsigned int spec_index;
0f750966
AL		 2601 bool mask_valid = true;
2602 u16 eth_type = 0;
2603 bool type_valid;
038d2ef8
MG		 2604
2605 /* Validate that ethertype is correct */
2606 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 2607 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 2608 ib_spec->eth.mask.ether_type) {
0f750966
AL		 2609 mask_valid = (ib_spec->eth.mask.ether_type ==
2610 htons(0xffff));
2611 has_ethertype = true;
2612 eth_type = ntohs(ib_spec->eth.val.ether_type);
2613 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2614 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2615 ip_spec_type = ib_spec->type;
038d2ef8
MG		 2616 }
2617 ib_spec = (void *)ib_spec + ib_spec->size;
2618 }
0f750966
AL		 2619
2620 type_valid = (!has_ethertype) || (!ip_spec_type);
2621 if (!type_valid && mask_valid) {
2622 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2623 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2624 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2625 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 2626
2627 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2628 (((eth_type == ETH_P_MPLS_UC) ||
2629 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 2630 }
2631
2632 return type_valid;
2633}
2634
19cc7524
AL		 2635static bool is_valid_attr(struct mlx5_core_dev *mdev,
2636 const struct ib_flow_attr *flow_attr)
0f750966 2637{
19cc7524
AL		 2638 return is_valid_ethertype(mdev, flow_attr, false) &&
2639 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 2640}
2641
2642static void put_flow_table(struct mlx5_ib_dev *dev,
2643 struct mlx5_ib_flow_prio *prio, bool ft_added)
2644{
2645 prio->refcount -= !!ft_added;
2646 if (!prio->refcount) {
2647 mlx5_destroy_flow_table(prio->flow_table);
2648 prio->flow_table = NULL;
2649 }
2650}
2651
2652static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2653{
2654 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2655 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2656 struct mlx5_ib_flow_handler,
2657 ibflow);
2658 struct mlx5_ib_flow_handler *iter, *tmp;
2659
9a4ca38d 2660 mutex_lock(&dev->flow_db->lock);
038d2ef8
MG		 2661
2662 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 2663 mlx5_del_flow_rules(iter->rule);
cc0e5d42 2664 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 2665 list_del(&iter->list);
2666 kfree(iter);
2667 }
2668
74491de9 2669 mlx5_del_flow_rules(handler->rule);
5497adc6 2670 put_flow_table(dev, handler->prio, true);
9a4ca38d 2671 mutex_unlock(&dev->flow_db->lock);
038d2ef8
MG		 2672
2673 kfree(handler);
2674
2675 return 0;
2676}
2677
35d19011
MG		 2678static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2679{
2680 priority *= 2;
2681 if (!dont_trap)
2682 priority++;
2683 return priority;
2684}
2685
cc0e5d42
MG		 2686enum flow_table_type {
2687 MLX5_IB_FT_RX,
2688 MLX5_IB_FT_TX
2689};
2690
00b7c2ab
MG		 2691#define MLX5_FS_MAX_TYPES 6
2692#define MLX5_FS_MAX_ENTRIES BIT(16)
038d2ef8 2693static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 2694 struct ib_flow_attr *flow_attr,
2695 enum flow_table_type ft_type)
038d2ef8 2696{
35d19011 2697 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 2698 struct mlx5_flow_namespace *ns = NULL;
2699 struct mlx5_ib_flow_prio *prio;
2700 struct mlx5_flow_table *ft;
dac388ef 2701 int max_table_size;
038d2ef8
MG		 2702 int num_entries;
2703 int num_groups;
2704 int priority;
2705 int err = 0;
2706
dac388ef
MG		 2707 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2708 log_max_ft_size));
038d2ef8 2709 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2710 if (flow_is_multicast_only(flow_attr) &&
2711 !dont_trap)
038d2ef8
MG		 2712 priority = MLX5_IB_FLOW_MCAST_PRIO;
2713 else
35d19011
MG		 2714 priority = ib_prio_to_core_prio(flow_attr->priority,
2715 dont_trap);
038d2ef8
MG		 2716 ns = mlx5_get_flow_namespace(dev->mdev,
2717 MLX5_FLOW_NAMESPACE_BYPASS);
2718 num_entries = MLX5_FS_MAX_ENTRIES;
2719 num_groups = MLX5_FS_MAX_TYPES;
9a4ca38d 2720 prio = &dev->flow_db->prios[priority];
038d2ef8
MG		 2721 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2722 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2723 ns = mlx5_get_flow_namespace(dev->mdev,
2724 MLX5_FLOW_NAMESPACE_LEFTOVERS);
2725 build_leftovers_ft_param(&priority,
2726 &num_entries,
2727 &num_groups);
9a4ca38d 2728 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 2729 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2730 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2731 allow_sniffer_and_nic_rx_shared_tir))
2732 return ERR_PTR(-ENOTSUPP);
2733
2734 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2735 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2736 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2737
9a4ca38d 2738 prio = &dev->flow_db->sniffer[ft_type];
cc0e5d42
MG		 2739 priority = 0;
2740 num_entries = 1;
2741 num_groups = 1;
038d2ef8
MG		 2742 }
2743
2744 if (!ns)
2745 return ERR_PTR(-ENOTSUPP);
2746
dac388ef
MG		 2747 if (num_entries > max_table_size)
2748 return ERR_PTR(-ENOMEM);
2749
038d2ef8
MG		 2750 ft = prio->flow_table;
2751 if (!ft) {
2752 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2753 num_entries,
d63cd286 2754 num_groups,
c9f1b073 2755 0, 0);
038d2ef8
MG		 2756
2757 if (!IS_ERR(ft)) {
2758 prio->refcount = 0;
2759 prio->flow_table = ft;
2760 } else {
2761 err = PTR_ERR(ft);
2762 }
2763 }
2764
2765 return err ? ERR_PTR(err) : prio;
2766}
2767
a550ddfc
YH		 2768static void set_underlay_qp(struct mlx5_ib_dev *dev,
2769 struct mlx5_flow_spec *spec,
2770 u32 underlay_qpn)
2771{
2772 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
2773 spec->match_criteria,
2774 misc_parameters);
2775 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2776 misc_parameters);
2777
2778 if (underlay_qpn &&
2779 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2780 ft_field_support.bth_dst_qp)) {
2781 MLX5_SET(fte_match_set_misc,
2782 misc_params_v, bth_dst_qp, underlay_qpn);
2783 MLX5_SET(fte_match_set_misc,
2784 misc_params_c, bth_dst_qp, 0xffffff);
2785 }
2786}
2787
2788static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
2789 struct mlx5_ib_flow_prio *ft_prio,
2790 const struct ib_flow_attr *flow_attr,
2791 struct mlx5_flow_destination *dst,
2792 u32 underlay_qpn)
038d2ef8
MG		 2793{
2794 struct mlx5_flow_table *ft = ft_prio->flow_table;
2795 struct mlx5_ib_flow_handler *handler;
075572d4 2796 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
c5bb1730 2797 struct mlx5_flow_spec *spec;
a22ed86c 2798 struct mlx5_flow_destination *rule_dst = dst;
dd063d0e 2799 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 2800 unsigned int spec_index;
038d2ef8 2801 int err = 0;
a22ed86c 2802 int dest_num = 1;
038d2ef8 2803
19cc7524 2804 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 2805 return ERR_PTR(-EINVAL);
2806
1b9a07ee 2807 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 2808 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 2809 if (!handler || !spec) {
038d2ef8
MG		 2810 err = -ENOMEM;
2811 goto free;
2812 }
2813
2814 INIT_LIST_HEAD(&handler->list);
2815
2816 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
19cc7524 2817 err = parse_flow_attr(dev->mdev, spec->match_criteria,
a22ed86c 2818 spec->match_value,
075572d4 2819 ib_flow, &flow_act);
038d2ef8
MG		 2820 if (err < 0)
2821 goto free;
2822
2823 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2824 }
2825
a550ddfc
YH		 2826 if (!flow_is_multicast_only(flow_attr))
2827 set_underlay_qp(dev, spec, underlay_qpn);
2828
018a94ee
MB		 2829 if (dev->rep) {
2830 void *misc;
2831
2832 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2833 misc_parameters);
2834 MLX5_SET(fte_match_set_misc, misc, source_port,
2835 dev->rep->vport);
2836 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2837 misc_parameters);
2838 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
2839 }
2840
466fa6d2 2841 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
075572d4 2842 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
a22ed86c
SS		 2843 rule_dst = NULL;
2844 dest_num = 0;
2845 } else {
2846 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2847 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2848 }
2ac693f9 2849
a9db0ecf 2850 if (flow_act.has_flow_tag &&
2ac693f9
MR		 2851 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2852 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
2853 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
075572d4 2854 flow_act.flow_tag, flow_attr->type);
2ac693f9
MR		 2855 err = -EINVAL;
2856 goto free;
2857 }
74491de9 2858 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 2859 &flow_act,
a22ed86c 2860 rule_dst, dest_num);
038d2ef8
MG		 2861
2862 if (IS_ERR(handler->rule)) {
2863 err = PTR_ERR(handler->rule);
2864 goto free;
2865 }
2866
d9d4980a 2867 ft_prio->refcount++;
5497adc6 2868 handler->prio = ft_prio;
038d2ef8
MG		 2869
2870 ft_prio->flow_table = ft;
2871free:
2872 if (err)
2873 kfree(handler);
c5bb1730 2874 kvfree(spec);
038d2ef8
MG		 2875 return err ? ERR_PTR(err) : handler;
2876}
2877
a550ddfc
YH		 2878static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2879 struct mlx5_ib_flow_prio *ft_prio,
2880 const struct ib_flow_attr *flow_attr,
2881 struct mlx5_flow_destination *dst)
2882{
2883 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0);
2884}
2885
35d19011
MG		 2886static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2887 struct mlx5_ib_flow_prio *ft_prio,
2888 struct ib_flow_attr *flow_attr,
2889 struct mlx5_flow_destination *dst)
2890{
2891 struct mlx5_ib_flow_handler *handler_dst = NULL;
2892 struct mlx5_ib_flow_handler *handler = NULL;
2893
2894 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2895 if (!IS_ERR(handler)) {
2896 handler_dst = create_flow_rule(dev, ft_prio,
2897 flow_attr, dst);
2898 if (IS_ERR(handler_dst)) {
74491de9 2899 mlx5_del_flow_rules(handler->rule);
d9d4980a 2900 ft_prio->refcount--;
35d19011
MG		 2901 kfree(handler);
2902 handler = handler_dst;
2903 } else {
2904 list_add(&handler_dst->list, &handler->list);
2905 }
2906 }
2907
2908 return handler;
2909}
038d2ef8
MG		 2910enum {
2911 LEFTOVERS_MC,
2912 LEFTOVERS_UC,
2913};
2914
2915static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2916 struct mlx5_ib_flow_prio *ft_prio,
2917 struct ib_flow_attr *flow_attr,
2918 struct mlx5_flow_destination *dst)
2919{
2920 struct mlx5_ib_flow_handler *handler_ucast = NULL;
2921 struct mlx5_ib_flow_handler *handler = NULL;
2922
2923 static struct {
2924 struct ib_flow_attr flow_attr;
2925 struct ib_flow_spec_eth eth_flow;
2926 } leftovers_specs[] = {
2927 [LEFTOVERS_MC] = {
2928 .flow_attr = {
2929 .num_of_specs = 1,
2930 .size = sizeof(leftovers_specs[0])
2931 },
2932 .eth_flow = {
2933 .type = IB_FLOW_SPEC_ETH,
2934 .size = sizeof(struct ib_flow_spec_eth),
2935 .mask = {.dst_mac = {0x1} },
2936 .val = {.dst_mac = {0x1} }
2937 }
2938 },
2939 [LEFTOVERS_UC] = {
2940 .flow_attr = {
2941 .num_of_specs = 1,
2942 .size = sizeof(leftovers_specs[0])
2943 },
2944 .eth_flow = {
2945 .type = IB_FLOW_SPEC_ETH,
2946 .size = sizeof(struct ib_flow_spec_eth),
2947 .mask = {.dst_mac = {0x1} },
2948 .val = {.dst_mac = {} }
2949 }
2950 }
2951 };
2952
2953 handler = create_flow_rule(dev, ft_prio,
2954 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2955 dst);
2956 if (!IS_ERR(handler) &&
2957 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2958 handler_ucast = create_flow_rule(dev, ft_prio,
2959 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2960 dst);
2961 if (IS_ERR(handler_ucast)) {
74491de9 2962 mlx5_del_flow_rules(handler->rule);
d9d4980a 2963 ft_prio->refcount--;
038d2ef8
MG		 2964 kfree(handler);
2965 handler = handler_ucast;
2966 } else {
2967 list_add(&handler_ucast->list, &handler->list);
2968 }
2969 }
2970
2971 return handler;
2972}
2973
cc0e5d42
MG		 2974static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2975 struct mlx5_ib_flow_prio *ft_rx,
2976 struct mlx5_ib_flow_prio *ft_tx,
2977 struct mlx5_flow_destination *dst)
2978{
2979 struct mlx5_ib_flow_handler *handler_rx;
2980 struct mlx5_ib_flow_handler *handler_tx;
2981 int err;
2982 static const struct ib_flow_attr flow_attr = {
2983 .num_of_specs = 0,
2984 .size = sizeof(flow_attr)
2985 };
2986
2987 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2988 if (IS_ERR(handler_rx)) {
2989 err = PTR_ERR(handler_rx);
2990 goto err;
2991 }
2992
2993 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2994 if (IS_ERR(handler_tx)) {
2995 err = PTR_ERR(handler_tx);
2996 goto err_tx;
2997 }
2998
2999 list_add(&handler_tx->list, &handler_rx->list);
3000
3001 return handler_rx;
3002
3003err_tx:
74491de9 3004 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 3005 ft_rx->refcount--;
3006 kfree(handler_rx);
3007err:
3008 return ERR_PTR(err);
3009}
3010
038d2ef8
MG		 3011static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3012 struct ib_flow_attr *flow_attr,
3013 int domain)
3014{
3015 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 3016 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 3017 struct mlx5_ib_flow_handler *handler = NULL;
3018 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 3019 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8
MG		 3020 struct mlx5_ib_flow_prio *ft_prio;
3021 int err;
a550ddfc 3022 int underlay_qpn;
038d2ef8
MG		 3023
3024 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
dac388ef 3025 return ERR_PTR(-ENOMEM);
038d2ef8
MG		 3026
3027 if (domain != IB_FLOW_DOMAIN_USER ||
508562d6 3028 flow_attr->port > dev->num_ports ||
35d19011 3029 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
038d2ef8
MG		 3030 return ERR_PTR(-EINVAL);
3031
3032 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3033 if (!dst)
3034 return ERR_PTR(-ENOMEM);
3035
9a4ca38d 3036 mutex_lock(&dev->flow_db->lock);
038d2ef8 3037
cc0e5d42 3038 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
038d2ef8
MG		 3039 if (IS_ERR(ft_prio)) {
3040 err = PTR_ERR(ft_prio);
3041 goto unlock;
3042 }
cc0e5d42
MG		 3043 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3044 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3045 if (IS_ERR(ft_prio_tx)) {
3046 err = PTR_ERR(ft_prio_tx);
3047 ft_prio_tx = NULL;
3048 goto destroy_ft;
3049 }
3050 }
038d2ef8
MG		 3051
3052 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
d9f88e5a
YH		 3053 if (mqp->flags & MLX5_IB_QP_RSS)
3054 dst->tir_num = mqp->rss_qp.tirn;
3055 else
3056 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
038d2ef8
MG		 3057
3058 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 3059 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3060 handler = create_dont_trap_rule(dev, ft_prio,
3061 flow_attr, dst);
3062 } else {
a550ddfc
YH		 3063 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3064 mqp->underlay_qpn : 0;
3065 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3066 dst, underlay_qpn);
35d19011 3067 }
038d2ef8
MG		 3068 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3069 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3070 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3071 dst);
cc0e5d42
MG		 3072 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3073 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 3074 } else {
3075 err = -EINVAL;
3076 goto destroy_ft;
3077 }
3078
3079 if (IS_ERR(handler)) {
3080 err = PTR_ERR(handler);
3081 handler = NULL;
3082 goto destroy_ft;
3083 }
3084
9a4ca38d 3085 mutex_unlock(&dev->flow_db->lock);
038d2ef8
MG		 3086 kfree(dst);
3087
3088 return &handler->ibflow;
3089
3090destroy_ft:
3091 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 3092 if (ft_prio_tx)
3093 put_flow_table(dev, ft_prio_tx, false);
038d2ef8 3094unlock:
9a4ca38d 3095 mutex_unlock(&dev->flow_db->lock);
038d2ef8
MG		 3096 kfree(dst);
3097 kfree(handler);
3098 return ERR_PTR(err);
3099}
3100
e126ba97
EC		 3101static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3102{
3103 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 3104 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97
EC		 3105 int err;
3106
81e30880
YH		 3107 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
3108 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
3109 return -EOPNOTSUPP;
3110 }
3111
9603b61d 3112 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 3113 if (err)
3114 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
3115 ibqp->qp_num, gid->raw);
3116
3117 return err;
3118}
3119
3120static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3121{
3122 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3123 int err;
3124
9603b61d 3125 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 3126 if (err)
3127 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
3128 ibqp->qp_num, gid->raw);
3129
3130 return err;
3131}
3132
3133static int init_node_data(struct mlx5_ib_dev *dev)
3134{
1b5daf11 3135 int err;
e126ba97 3136
1b5daf11 3137 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 3138 if (err)
1b5daf11 3139 return err;
e126ba97 3140
1b5daf11 3141 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 3142
1b5daf11 3143 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 3144}
3145
3146static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
3147 char *buf)
3148{
3149 struct mlx5_ib_dev *dev =
3150 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3151
9603b61d 3152 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 3153}
3154
3155static ssize_t show_reg_pages(struct device *device,
3156 struct device_attribute *attr, char *buf)
3157{
3158 struct mlx5_ib_dev *dev =
3159 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3160
6aec21f6 3161 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 3162}
3163
3164static ssize_t show_hca(struct device *device, struct device_attribute *attr,
3165 char *buf)
3166{
3167 struct mlx5_ib_dev *dev =
3168 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 3169 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 3170}
3171
e126ba97
EC		 3172static ssize_t show_rev(struct device *device, struct device_attribute *attr,
3173 char *buf)
3174{
3175 struct mlx5_ib_dev *dev =
3176 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 3177 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 3178}
3179
3180static ssize_t show_board(struct device *device, struct device_attribute *attr,
3181 char *buf)
3182{
3183 struct mlx5_ib_dev *dev =
3184 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3185 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 3186 dev->mdev->board_id);
e126ba97
EC		 3187}
3188
3189static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
e126ba97
EC		 3190static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
3191static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
3192static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
3193static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
3194
3195static struct device_attribute *mlx5_class_attributes[] = {
3196 &dev_attr_hw_rev,
e126ba97
EC		 3197 &dev_attr_hca_type,
3198 &dev_attr_board_id,
3199 &dev_attr_fw_pages,
3200 &dev_attr_reg_pages,
3201};
3202
7722f47e
HE		 3203static void pkey_change_handler(struct work_struct *work)
3204{
3205 struct mlx5_ib_port_resources *ports =
3206 container_of(work, struct mlx5_ib_port_resources,
3207 pkey_change_work);
3208
3209 mutex_lock(&ports->devr->mutex);
3210 mlx5_ib_gsi_pkey_change(ports->gsi);
3211 mutex_unlock(&ports->devr->mutex);
3212}
3213
89ea94a7
MG		 3214static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
3215{
3216 struct mlx5_ib_qp *mqp;
3217 struct mlx5_ib_cq *send_mcq, *recv_mcq;
3218 struct mlx5_core_cq *mcq;
3219 struct list_head cq_armed_list;
3220 unsigned long flags_qp;
3221 unsigned long flags_cq;
3222 unsigned long flags;
3223
3224 INIT_LIST_HEAD(&cq_armed_list);
3225
3226 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3227 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
3228 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
3229 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
3230 if (mqp->sq.tail != mqp->sq.head) {
3231 send_mcq = to_mcq(mqp->ibqp.send_cq);
3232 spin_lock_irqsave(&send_mcq->lock, flags_cq);
3233 if (send_mcq->mcq.comp &&
3234 mqp->ibqp.send_cq->comp_handler) {
3235 if (!send_mcq->mcq.reset_notify_added) {
3236 send_mcq->mcq.reset_notify_added = 1;
3237 list_add_tail(&send_mcq->mcq.reset_notify,
3238 &cq_armed_list);
3239 }
3240 }
3241 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
3242 }
3243 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
3244 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
3245 /* no handling is needed for SRQ */
3246 if (!mqp->ibqp.srq) {
3247 if (mqp->rq.tail != mqp->rq.head) {
3248 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
3249 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
3250 if (recv_mcq->mcq.comp &&
3251 mqp->ibqp.recv_cq->comp_handler) {
3252 if (!recv_mcq->mcq.reset_notify_added) {
3253 recv_mcq->mcq.reset_notify_added = 1;
3254 list_add_tail(&recv_mcq->mcq.reset_notify,
3255 &cq_armed_list);
3256 }
3257 }
3258 spin_unlock_irqrestore(&recv_mcq->lock,
3259 flags_cq);
3260 }
3261 }
3262 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3263 }
3264 /*At that point all inflight post send were put to be executed as of we
3265 * lock/unlock above locks Now need to arm all involved CQs.
3266 */
3267 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
3268 mcq->comp(mcq);
3269 }
3270 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3271}
3272
03404e8a
MG		 3273static void delay_drop_handler(struct work_struct *work)
3274{
3275 int err;
3276 struct mlx5_ib_delay_drop *delay_drop =
3277 container_of(work, struct mlx5_ib_delay_drop,
3278 delay_drop_work);
3279
fe248c3a
MG		 3280 atomic_inc(&delay_drop->events_cnt);
3281
03404e8a
MG		 3282 mutex_lock(&delay_drop->lock);
3283 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
3284 delay_drop->timeout);
3285 if (err) {
3286 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
3287 delay_drop->timeout);
3288 delay_drop->activate = false;
3289 }
3290 mutex_unlock(&delay_drop->lock);
3291}
3292
d69a24e0 3293static void mlx5_ib_handle_event(struct work_struct *_work)
e126ba97 3294{
d69a24e0
DJ		 3295 struct mlx5_ib_event_work *work =
3296 container_of(_work, struct mlx5_ib_event_work, work);
3297 struct mlx5_ib_dev *ibdev;
e126ba97 3298 struct ib_event ibev;
dbaaff2a 3299 bool fatal = false;
e126ba97
EC		 3300 u8 port = 0;
3301
d69a24e0
DJ		 3302 if (mlx5_core_is_mp_slave(work->dev)) {
3303 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context);
3304 if (!ibdev)
3305 goto out;
3306 } else {
3307 ibdev = work->context;
3308 }
3309
3310 switch (work->event) {
e126ba97 3311 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 3312 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 3313 mlx5_ib_handle_internal_error(ibdev);
dbaaff2a 3314 fatal = true;
e126ba97
EC		 3315 break;
3316
3317 case MLX5_DEV_EVENT_PORT_UP:
e126ba97 3318 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 3319 case MLX5_DEV_EVENT_PORT_INITIALIZED:
d69a24e0 3320 port = (u8)work->param;
5ec8c83e
AH		 3321
3322 /* In RoCE, port up/down events are handled in
3323 * mlx5_netdev_event().
3324 */
3325 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
3326 IB_LINK_LAYER_ETHERNET)
d69a24e0 3327 goto out;
5ec8c83e 3328
d69a24e0 3329 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ?
5ec8c83e 3330 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
e126ba97
EC		 3331 break;
3332
e126ba97
EC		 3333 case MLX5_DEV_EVENT_LID_CHANGE:
3334 ibev.event = IB_EVENT_LID_CHANGE;
d69a24e0 3335 port = (u8)work->param;
e126ba97
EC		 3336 break;
3337
3338 case MLX5_DEV_EVENT_PKEY_CHANGE:
3339 ibev.event = IB_EVENT_PKEY_CHANGE;
d69a24e0 3340 port = (u8)work->param;
7722f47e
HE		 3341
3342 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 3343 break;
3344
3345 case MLX5_DEV_EVENT_GUID_CHANGE:
3346 ibev.event = IB_EVENT_GID_CHANGE;
d69a24e0 3347 port = (u8)work->param;
e126ba97
EC		 3348 break;
3349
3350 case MLX5_DEV_EVENT_CLIENT_REREG:
3351 ibev.event = IB_EVENT_CLIENT_REREGISTER;
d69a24e0 3352 port = (u8)work->param;
e126ba97 3353 break;
03404e8a
MG		 3354 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
3355 schedule_work(&ibdev->delay_drop.delay_drop_work);
3356 goto out;
bdc37924 3357 default:
03404e8a 3358 goto out;
e126ba97
EC		 3359 }
3360
3361 ibev.device = &ibdev->ib_dev;
3362 ibev.element.port_num = port;
3363
a0c84c32
EC		 3364 if (port < 1 || port > ibdev->num_ports) {
3365 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
03404e8a 3366 goto out;
a0c84c32
EC		 3367 }
3368
e126ba97
EC		 3369 if (ibdev->ib_active)
3370 ib_dispatch_event(&ibev);
dbaaff2a
EC		 3371
3372 if (fatal)
3373 ibdev->ib_active = false;
03404e8a 3374out:
d69a24e0
DJ		 3375 kfree(work);
3376}
3377
3378static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
3379 enum mlx5_dev_event event, unsigned long param)
3380{
3381 struct mlx5_ib_event_work *work;
3382
3383 work = kmalloc(sizeof(*work), GFP_ATOMIC);
10bea9c8 3384 if (!work)
d69a24e0 3385 return;
d69a24e0 3386
10bea9c8
LR		 3387 INIT_WORK(&work->work, mlx5_ib_handle_event);
3388 work->dev = dev;
3389 work->param = param;
3390 work->context = context;
3391 work->event = event;
3392
3393 queue_work(mlx5_ib_event_wq, &work->work);
e126ba97
EC		 3394}
3395
c43f1112
MG		 3396static int set_has_smi_cap(struct mlx5_ib_dev *dev)
3397{
3398 struct mlx5_hca_vport_context vport_ctx;
3399 int err;
3400 int port;
3401
508562d6 3402 for (port = 1; port <= dev->num_ports; port++) {
c43f1112
MG		 3403 dev->mdev->port_caps[port - 1].has_smi = false;
3404 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
3405 MLX5_CAP_PORT_TYPE_IB) {
3406 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
3407 err = mlx5_query_hca_vport_context(dev->mdev, 0,
3408 port, 0,
3409 &vport_ctx);
3410 if (err) {
3411 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
3412 port, err);
3413 return err;
3414 }
3415 dev->mdev->port_caps[port - 1].has_smi =
3416 vport_ctx.has_smi;
3417 } else {
3418 dev->mdev->port_caps[port - 1].has_smi = true;
3419 }
3420 }
3421 }
3422 return 0;
3423}
3424
e126ba97
EC		 3425static void get_ext_port_caps(struct mlx5_ib_dev *dev)
3426{
3427 int port;
3428
508562d6 3429 for (port = 1; port <= dev->num_ports; port++)
e126ba97
EC		 3430 mlx5_query_ext_port_caps(dev, port);
3431}
3432
32f69e4b 3433static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
e126ba97
EC		 3434{
3435 struct ib_device_attr *dprops = NULL;
3436 struct ib_port_attr *pprops = NULL;
f614fc15 3437 int err = -ENOMEM;
2528e33e 3438 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 3439
3440 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
3441 if (!pprops)
3442 goto out;
3443
3444 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
3445 if (!dprops)
3446 goto out;
3447
c43f1112
MG		 3448 err = set_has_smi_cap(dev);
3449 if (err)
3450 goto out;
3451
2528e33e 3452 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 3453 if (err) {
3454 mlx5_ib_warn(dev, "query_device failed %d\n", err);
3455 goto out;
3456 }
3457
32f69e4b
DJ		 3458 memset(pprops, 0, sizeof(*pprops));
3459 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
3460 if (err) {
3461 mlx5_ib_warn(dev, "query_port %d failed %d\n",
3462 port, err);
3463 goto out;
e126ba97
EC		 3464 }
3465
32f69e4b
DJ		 3466 dev->mdev->port_caps[port - 1].pkey_table_len =
3467 dprops->max_pkeys;
3468 dev->mdev->port_caps[port - 1].gid_table_len =
3469 pprops->gid_tbl_len;
3470 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
3471 port, dprops->max_pkeys, pprops->gid_tbl_len);
3472
e126ba97
EC		 3473out:
3474 kfree(pprops);
3475 kfree(dprops);
3476
3477 return err;
3478}
3479
3480static void destroy_umrc_res(struct mlx5_ib_dev *dev)
3481{
3482 int err;
3483
3484 err = mlx5_mr_cache_cleanup(dev);
3485 if (err)
3486 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
3487
3488 mlx5_ib_destroy_qp(dev->umrc.qp);
add08d76 3489 ib_free_cq(dev->umrc.cq);
e126ba97
EC		 3490 ib_dealloc_pd(dev->umrc.pd);
3491}
3492
3493enum {
3494 MAX_UMR_WR = 128,
3495};
3496
3497static int create_umr_res(struct mlx5_ib_dev *dev)
3498{
3499 struct ib_qp_init_attr *init_attr = NULL;
3500 struct ib_qp_attr *attr = NULL;
3501 struct ib_pd *pd;
3502 struct ib_cq *cq;
3503 struct ib_qp *qp;
e126ba97
EC		 3504 int ret;
3505
3506 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
3507 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
3508 if (!attr || !init_attr) {
3509 ret = -ENOMEM;
3510 goto error_0;
3511 }
3512
ed082d36 3513 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 3514 if (IS_ERR(pd)) {
3515 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
3516 ret = PTR_ERR(pd);
3517 goto error_0;
3518 }
3519
add08d76 3520 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 3521 if (IS_ERR(cq)) {
3522 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
3523 ret = PTR_ERR(cq);
3524 goto error_2;
3525 }
e126ba97
EC		 3526
3527 init_attr->send_cq = cq;
3528 init_attr->recv_cq = cq;
3529 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
3530 init_attr->cap.max_send_wr = MAX_UMR_WR;
3531 init_attr->cap.max_send_sge = 1;
3532 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
3533 init_attr->port_num = 1;
3534 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
3535 if (IS_ERR(qp)) {
3536 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
3537 ret = PTR_ERR(qp);
3538 goto error_3;
3539 }
3540 qp->device = &dev->ib_dev;
3541 qp->real_qp = qp;
3542 qp->uobject = NULL;
3543 qp->qp_type = MLX5_IB_QPT_REG_UMR;
31fde034
MD		 3544 qp->send_cq = init_attr->send_cq;
3545 qp->recv_cq = init_attr->recv_cq;
e126ba97
EC		 3546
3547 attr->qp_state = IB_QPS_INIT;
3548 attr->port_num = 1;
3549 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
3550 IB_QP_PORT, NULL);
3551 if (ret) {
3552 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
3553 goto error_4;
3554 }
3555
3556 memset(attr, 0, sizeof(*attr));
3557 attr->qp_state = IB_QPS_RTR;
3558 attr->path_mtu = IB_MTU_256;
3559
3560 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3561 if (ret) {
3562 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
3563 goto error_4;
3564 }
3565
3566 memset(attr, 0, sizeof(*attr));
3567 attr->qp_state = IB_QPS_RTS;
3568 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3569 if (ret) {
3570 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
3571 goto error_4;
3572 }
3573
3574 dev->umrc.qp = qp;
3575 dev->umrc.cq = cq;
e126ba97
EC		 3576 dev->umrc.pd = pd;
3577
3578 sema_init(&dev->umrc.sem, MAX_UMR_WR);
3579 ret = mlx5_mr_cache_init(dev);
3580 if (ret) {
3581 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
3582 goto error_4;
3583 }
3584
3585 kfree(attr);
3586 kfree(init_attr);
3587
3588 return 0;
3589
3590error_4:
3591 mlx5_ib_destroy_qp(qp);
3592
3593error_3:
add08d76 3594 ib_free_cq(cq);
e126ba97
EC		 3595
3596error_2:
e126ba97
EC		 3597 ib_dealloc_pd(pd);
3598
3599error_0:
3600 kfree(attr);
3601 kfree(init_attr);
3602 return ret;
3603}
3604
6e8484c5
MG		 3605static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
3606{
3607 switch (umr_fence_cap) {
3608 case MLX5_CAP_UMR_FENCE_NONE:
3609 return MLX5_FENCE_MODE_NONE;
3610 case MLX5_CAP_UMR_FENCE_SMALL:
3611 return MLX5_FENCE_MODE_INITIATOR_SMALL;
3612 default:
3613 return MLX5_FENCE_MODE_STRONG_ORDERING;
3614 }
3615}
3616
e126ba97
EC		 3617static int create_dev_resources(struct mlx5_ib_resources *devr)
3618{
3619 struct ib_srq_init_attr attr;
3620 struct mlx5_ib_dev *dev;
bcf4c1ea 3621 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 3622 int port;
e126ba97
EC		 3623 int ret = 0;
3624
3625 dev = container_of(devr, struct mlx5_ib_dev, devr);
3626
d16e91da
HE		 3627 mutex_init(&devr->mutex);
3628
e126ba97
EC		 3629 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
3630 if (IS_ERR(devr->p0)) {
3631 ret = PTR_ERR(devr->p0);
3632 goto error0;
3633 }
3634 devr->p0->device = &dev->ib_dev;
3635 devr->p0->uobject = NULL;
3636 atomic_set(&devr->p0->usecnt, 0);
3637
bcf4c1ea 3638 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 3639 if (IS_ERR(devr->c0)) {
3640 ret = PTR_ERR(devr->c0);
3641 goto error1;
3642 }
3643 devr->c0->device = &dev->ib_dev;
3644 devr->c0->uobject = NULL;
3645 devr->c0->comp_handler = NULL;
3646 devr->c0->event_handler = NULL;
3647 devr->c0->cq_context = NULL;
3648 atomic_set(&devr->c0->usecnt, 0);
3649
3650 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3651 if (IS_ERR(devr->x0)) {
3652 ret = PTR_ERR(devr->x0);
3653 goto error2;
3654 }
3655 devr->x0->device = &dev->ib_dev;
3656 devr->x0->inode = NULL;
3657 atomic_set(&devr->x0->usecnt, 0);
3658 mutex_init(&devr->x0->tgt_qp_mutex);
3659 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
3660
3661 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3662 if (IS_ERR(devr->x1)) {
3663 ret = PTR_ERR(devr->x1);
3664 goto error3;
3665 }
3666 devr->x1->device = &dev->ib_dev;
3667 devr->x1->inode = NULL;
3668 atomic_set(&devr->x1->usecnt, 0);
3669 mutex_init(&devr->x1->tgt_qp_mutex);
3670 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
3671
3672 memset(&attr, 0, sizeof(attr));
3673 attr.attr.max_sge = 1;
3674 attr.attr.max_wr = 1;
3675 attr.srq_type = IB_SRQT_XRC;
1a56ff6d 3676 attr.ext.cq = devr->c0;
e126ba97
EC		 3677 attr.ext.xrc.xrcd = devr->x0;
3678
3679 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3680 if (IS_ERR(devr->s0)) {
3681 ret = PTR_ERR(devr->s0);
3682 goto error4;
3683 }
3684 devr->s0->device = &dev->ib_dev;
3685 devr->s0->pd = devr->p0;
3686 devr->s0->uobject = NULL;
3687 devr->s0->event_handler = NULL;
3688 devr->s0->srq_context = NULL;
3689 devr->s0->srq_type = IB_SRQT_XRC;
3690 devr->s0->ext.xrc.xrcd = devr->x0;
1a56ff6d 3691 devr->s0->ext.cq = devr->c0;
e126ba97 3692 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1a56ff6d 3693 atomic_inc(&devr->s0->ext.cq->usecnt);
e126ba97
EC		 3694 atomic_inc(&devr->p0->usecnt);
3695 atomic_set(&devr->s0->usecnt, 0);
3696
4aa17b28
HA		 3697 memset(&attr, 0, sizeof(attr));
3698 attr.attr.max_sge = 1;
3699 attr.attr.max_wr = 1;
3700 attr.srq_type = IB_SRQT_BASIC;
3701 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3702 if (IS_ERR(devr->s1)) {
3703 ret = PTR_ERR(devr->s1);
3704 goto error5;
3705 }
3706 devr->s1->device = &dev->ib_dev;
3707 devr->s1->pd = devr->p0;
3708 devr->s1->uobject = NULL;
3709 devr->s1->event_handler = NULL;
3710 devr->s1->srq_context = NULL;
3711 devr->s1->srq_type = IB_SRQT_BASIC;
1a56ff6d 3712 devr->s1->ext.cq = devr->c0;
4aa17b28 3713 atomic_inc(&devr->p0->usecnt);
1a56ff6d 3714 atomic_set(&devr->s1->usecnt, 0);
4aa17b28 3715
7722f47e
HE		 3716 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
3717 INIT_WORK(&devr->ports[port].pkey_change_work,
3718 pkey_change_handler);
3719 devr->ports[port].devr = devr;
3720 }
3721
e126ba97
EC		 3722 return 0;
3723
4aa17b28
HA		 3724error5:
3725 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 3726error4:
3727 mlx5_ib_dealloc_xrcd(devr->x1);
3728error3:
3729 mlx5_ib_dealloc_xrcd(devr->x0);
3730error2:
3731 mlx5_ib_destroy_cq(devr->c0);
3732error1:
3733 mlx5_ib_dealloc_pd(devr->p0);
3734error0:
3735 return ret;
3736}
3737
3738static void destroy_dev_resources(struct mlx5_ib_resources *devr)
3739{
7722f47e
HE		 3740 struct mlx5_ib_dev *dev =
3741 container_of(devr, struct mlx5_ib_dev, devr);
3742 int port;
3743
4aa17b28 3744 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 3745 mlx5_ib_destroy_srq(devr->s0);
3746 mlx5_ib_dealloc_xrcd(devr->x0);
3747 mlx5_ib_dealloc_xrcd(devr->x1);
3748 mlx5_ib_destroy_cq(devr->c0);
3749 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 3750
3751 /* Make sure no change P_Key work items are still executing */
3752 for (port = 0; port < dev->num_ports; ++port)
3753 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 3754}
3755
e53505a8
AS		 3756static u32 get_core_cap_flags(struct ib_device *ibdev)
3757{
3758 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3759 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3760 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3761 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
85c7c014 3762 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
e53505a8
AS		 3763 u32 ret = 0;
3764
3765 if (ll == IB_LINK_LAYER_INFINIBAND)
3766 return RDMA_CORE_PORT_IBA_IB;
3767
85c7c014
DJ		 3768 if (raw_support)
3769 ret = RDMA_CORE_PORT_RAW_PACKET;
72cd5717 3770
e53505a8 3771 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 3772 return ret;
e53505a8
AS		 3773
3774 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 3775 return ret;
e53505a8
AS		 3776
3777 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3778 ret |= RDMA_CORE_PORT_IBA_ROCE;
3779
3780 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3781 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3782
3783 return ret;
3784}
3785
7738613e
IW		 3786static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3787 struct ib_port_immutable *immutable)
3788{
3789 struct ib_port_attr attr;
ca5b91d6
OG		 3790 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3791 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
7738613e
IW		 3792 int err;
3793
c4550c63
OG		 3794 immutable->core_cap_flags = get_core_cap_flags(ibdev);
3795
3796 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 3797 if (err)
3798 return err;
3799
3800 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3801 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 3802 immutable->core_cap_flags = get_core_cap_flags(ibdev);
ca5b91d6
OG		 3803 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3804 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 3805
3806 return 0;
3807}
3808
8e6efa3a
MB		 3809static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
3810 struct ib_port_immutable *immutable)
3811{
3812 struct ib_port_attr attr;
3813 int err;
3814
3815 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
3816
3817 err = ib_query_port(ibdev, port_num, &attr);
3818 if (err)
3819 return err;
3820
3821 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3822 immutable->gid_tbl_len = attr.gid_tbl_len;
3823 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
3824
3825 return 0;
3826}
3827
9abb0d1b 3828static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 3829{
3830 struct mlx5_ib_dev *dev =
3831 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 3832 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
3833 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
3834 fw_rev_sub(dev->mdev));
c7342823
IW		 3835}
3836
45f95acd 3837static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 3838{
3839 struct mlx5_core_dev *mdev = dev->mdev;
3840 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3841 MLX5_FLOW_NAMESPACE_LAG);
3842 struct mlx5_flow_table *ft;
3843 int err;
3844
3845 if (!ns || !mlx5_lag_is_active(mdev))
3846 return 0;
3847
3848 err = mlx5_cmd_create_vport_lag(mdev);
3849 if (err)
3850 return err;
3851
3852 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3853 if (IS_ERR(ft)) {
3854 err = PTR_ERR(ft);
3855 goto err_destroy_vport_lag;
3856 }
3857
9a4ca38d 3858 dev->flow_db->lag_demux_ft = ft;
9ef9c640
AH		 3859 return 0;
3860
3861err_destroy_vport_lag:
3862 mlx5_cmd_destroy_vport_lag(mdev);
3863 return err;
3864}
3865
45f95acd 3866static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 3867{
3868 struct mlx5_core_dev *mdev = dev->mdev;
3869
9a4ca38d
MB		 3870 if (dev->flow_db->lag_demux_ft) {
3871 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
3872 dev->flow_db->lag_demux_ft = NULL;
9ef9c640
AH		 3873
3874 mlx5_cmd_destroy_vport_lag(mdev);
3875 }
3876}
3877
7fd8aefb 3878static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
d012f5d6
OG		 3879{
3880 int err;
3881
7fd8aefb
DJ		 3882 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
3883 err = register_netdevice_notifier(&dev->roce[port_num].nb);
d012f5d6 3884 if (err) {
7fd8aefb 3885 dev->roce[port_num].nb.notifier_call = NULL;
d012f5d6
OG		 3886 return err;
3887 }
3888
3889 return 0;
3890}
3891
7fd8aefb 3892static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5ec8c83e 3893{
7fd8aefb
DJ		 3894 if (dev->roce[port_num].nb.notifier_call) {
3895 unregister_netdevice_notifier(&dev->roce[port_num].nb);
3896 dev->roce[port_num].nb.notifier_call = NULL;
5ec8c83e
AH		 3897 }
3898}
3899
7fd8aefb 3900static int mlx5_enable_eth(struct mlx5_ib_dev *dev, u8 port_num)
fc24fc5e 3901{
e53505a8
AS		 3902 int err;
3903
ca5b91d6
OG		 3904 if (MLX5_CAP_GEN(dev->mdev, roce)) {
3905 err = mlx5_nic_vport_enable_roce(dev->mdev);
3906 if (err)
8e6efa3a 3907 return err;
ca5b91d6 3908 }
e53505a8 3909
45f95acd 3910 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 3911 if (err)
3912 goto err_disable_roce;
3913
e53505a8
AS		 3914 return 0;
3915
9ef9c640 3916err_disable_roce:
ca5b91d6
OG		 3917 if (MLX5_CAP_GEN(dev->mdev, roce))
3918 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 3919
e53505a8 3920 return err;
fc24fc5e
AS		 3921}
3922
45f95acd 3923static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 3924{
45f95acd 3925 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 3926 if (MLX5_CAP_GEN(dev->mdev, roce))
3927 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 3928}
3929
e1f24a79 3930struct mlx5_ib_counter {
7c16f477
KH		 3931 const char *name;
3932 size_t offset;
3933};
3934
3935#define INIT_Q_COUNTER(_name) \
3936 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3937
e1f24a79 3938static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 3939 INIT_Q_COUNTER(rx_write_requests),
3940 INIT_Q_COUNTER(rx_read_requests),
3941 INIT_Q_COUNTER(rx_atomic_requests),
3942 INIT_Q_COUNTER(out_of_buffer),
3943};
3944
e1f24a79 3945static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 3946 INIT_Q_COUNTER(out_of_sequence),
3947};
3948
e1f24a79 3949static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 3950 INIT_Q_COUNTER(duplicate_request),
3951 INIT_Q_COUNTER(rnr_nak_retry_err),
3952 INIT_Q_COUNTER(packet_seq_err),
3953 INIT_Q_COUNTER(implied_nak_seq_err),
3954 INIT_Q_COUNTER(local_ack_timeout_err),
3955};
3956
e1f24a79
PP		 3957#define INIT_CONG_COUNTER(_name) \
3958 { .name = #_name, .offset = \
3959 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
3960
3961static const struct mlx5_ib_counter cong_cnts[] = {
3962 INIT_CONG_COUNTER(rp_cnp_ignored),
3963 INIT_CONG_COUNTER(rp_cnp_handled),
3964 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
3965 INIT_CONG_COUNTER(np_cnp_sent),
3966};
3967
58dcb60a
PP		 3968static const struct mlx5_ib_counter extended_err_cnts[] = {
3969 INIT_Q_COUNTER(resp_local_length_error),
3970 INIT_Q_COUNTER(resp_cqe_error),
3971 INIT_Q_COUNTER(req_cqe_error),
3972 INIT_Q_COUNTER(req_remote_invalid_request),
3973 INIT_Q_COUNTER(req_remote_access_errors),
3974 INIT_Q_COUNTER(resp_remote_access_errors),
3975 INIT_Q_COUNTER(resp_cqe_flush_error),
3976 INIT_Q_COUNTER(req_cqe_flush_error),
3977};
3978
e1f24a79 3979static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a 3980{
aac4492e 3981 int i;
0837e86a 3982
7c16f477 3983 for (i = 0; i < dev->num_ports; i++) {
aac4492e
DJ		 3984 if (dev->port[i].cnts.set_id)
3985 mlx5_core_dealloc_q_counter(dev->mdev,
3986 dev->port[i].cnts.set_id);
e1f24a79
PP		 3987 kfree(dev->port[i].cnts.names);
3988 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 3989 }
3990}
3991
e1f24a79
PP		 3992static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
3993 struct mlx5_ib_counters *cnts)
7c16f477
KH		 3994{
3995 u32 num_counters;
3996
3997 num_counters = ARRAY_SIZE(basic_q_cnts);
3998
3999 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
4000 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
4001
4002 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
4003 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 4004
4005 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
4006 num_counters += ARRAY_SIZE(extended_err_cnts);
4007
e1f24a79 4008 cnts->num_q_counters = num_counters;
7c16f477 4009
e1f24a79
PP		 4010 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4011 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
4012 num_counters += ARRAY_SIZE(cong_cnts);
4013 }
4014
4015 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
4016 if (!cnts->names)
7c16f477
KH		 4017 return -ENOMEM;
4018
e1f24a79
PP		 4019 cnts->offsets = kcalloc(num_counters,
4020 sizeof(cnts->offsets), GFP_KERNEL);
4021 if (!cnts->offsets)
7c16f477
KH		 4022 goto err_names;
4023
7c16f477
KH		 4024 return 0;
4025
4026err_names:
e1f24a79 4027 kfree(cnts->names);
aac4492e 4028 cnts->names = NULL;
7c16f477
KH		 4029 return -ENOMEM;
4030}
4031
e1f24a79
PP		 4032static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
4033 const char **names,
4034 size_t *offsets)
7c16f477
KH		 4035{
4036 int i;
4037 int j = 0;
4038
4039 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
4040 names[j] = basic_q_cnts[i].name;
4041 offsets[j] = basic_q_cnts[i].offset;
4042 }
4043
4044 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
4045 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
4046 names[j] = out_of_seq_q_cnts[i].name;
4047 offsets[j] = out_of_seq_q_cnts[i].offset;
4048 }
4049 }
4050
4051 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
4052 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
4053 names[j] = retrans_q_cnts[i].name;
4054 offsets[j] = retrans_q_cnts[i].offset;
4055 }
4056 }
e1f24a79 4057
58dcb60a
PP		 4058 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
4059 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
4060 names[j] = extended_err_cnts[i].name;
4061 offsets[j] = extended_err_cnts[i].offset;
4062 }
4063 }
4064
e1f24a79
PP		 4065 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4066 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
4067 names[j] = cong_cnts[i].name;
4068 offsets[j] = cong_cnts[i].offset;
4069 }
4070 }
0837e86a
MB		 4071}
4072
e1f24a79 4073static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a 4074{
aac4492e 4075 int err = 0;
0837e86a 4076 int i;
0837e86a
MB		 4077
4078 for (i = 0; i < dev->num_ports; i++) {
aac4492e
DJ		 4079 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
4080 if (err)
4081 goto err_alloc;
4082
4083 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
4084 dev->port[i].cnts.offsets);
7c16f477 4085
aac4492e
DJ		 4086 err = mlx5_core_alloc_q_counter(dev->mdev,
4087 &dev->port[i].cnts.set_id);
4088 if (err) {
0837e86a
MB		 4089 mlx5_ib_warn(dev,
4090 "couldn't allocate queue counter for port %d, err %d\n",
aac4492e
DJ		 4091 i + 1, err);
4092 goto err_alloc;
0837e86a 4093 }
aac4492e 4094 dev->port[i].cnts.set_id_valid = true;
0837e86a
MB		 4095 }
4096
4097 return 0;
4098
aac4492e
DJ		 4099err_alloc:
4100 mlx5_ib_dealloc_counters(dev);
4101 return err;
0837e86a
MB		 4102}
4103
0ad17a8f
MB		 4104static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
4105 u8 port_num)
4106{
7c16f477
KH		 4107 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4108 struct mlx5_ib_port *port = &dev->port[port_num - 1];
0ad17a8f
MB		 4109
4110 /* We support only per port stats */
4111 if (port_num == 0)
4112 return NULL;
4113
e1f24a79
PP		 4114 return rdma_alloc_hw_stats_struct(port->cnts.names,
4115 port->cnts.num_q_counters +
4116 port->cnts.num_cong_counters,
0ad17a8f
MB		 4117 RDMA_HW_STATS_DEFAULT_LIFESPAN);
4118}
4119
aac4492e 4120static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
e1f24a79
PP		 4121 struct mlx5_ib_port *port,
4122 struct rdma_hw_stats *stats)
0ad17a8f 4123{
0ad17a8f
MB		 4124 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
4125 void *out;
4126 __be32 val;
e1f24a79 4127 int ret, i;
0ad17a8f 4128
1b9a07ee 4129 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 4130 if (!out)
4131 return -ENOMEM;
4132
aac4492e 4133 ret = mlx5_core_query_q_counter(mdev,
e1f24a79 4134 port->cnts.set_id, 0,
0ad17a8f
MB		 4135 out, outlen);
4136 if (ret)
4137 goto free;
4138
e1f24a79
PP		 4139 for (i = 0; i < port->cnts.num_q_counters; i++) {
4140 val = *(__be32 *)(out + port->cnts.offsets[i]);
0ad17a8f
MB		 4141 stats->value[i] = (u64)be32_to_cpu(val);
4142 }
7c16f477 4143
0ad17a8f
MB		 4144free:
4145 kvfree(out);
e1f24a79
PP		 4146 return ret;
4147}
4148
e1f24a79
PP		 4149static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
4150 struct rdma_hw_stats *stats,
4151 u8 port_num, int index)
4152{
4153 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4154 struct mlx5_ib_port *port = &dev->port[port_num - 1];
aac4492e 4155 struct mlx5_core_dev *mdev;
e1f24a79 4156 int ret, num_counters;
aac4492e 4157 u8 mdev_port_num;
e1f24a79
PP		 4158
4159 if (!stats)
4160 return -EINVAL;
4161
aac4492e
DJ		 4162 num_counters = port->cnts.num_q_counters + port->cnts.num_cong_counters;
4163
4164 /* q_counters are per IB device, query the master mdev */
4165 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
e1f24a79
PP		 4166 if (ret)
4167 return ret;
e1f24a79
PP		 4168
4169 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
aac4492e
DJ		 4170 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
4171 &mdev_port_num);
4172 if (!mdev) {
4173 /* If port is not affiliated yet, its in down state
4174 * which doesn't have any counters yet, so it would be
4175 * zero. So no need to read from the HCA.
4176 */
4177 goto done;
4178 }
71a0ff65
MD		 4179 ret = mlx5_lag_query_cong_counters(dev->mdev,
4180 stats->value +
4181 port->cnts.num_q_counters,
4182 port->cnts.num_cong_counters,
4183 port->cnts.offsets +
4184 port->cnts.num_q_counters);
aac4492e
DJ		 4185
4186 mlx5_ib_put_native_port_mdev(dev, port_num);
e1f24a79
PP		 4187 if (ret)
4188 return ret;
e1f24a79
PP		 4189 }
4190
aac4492e 4191done:
e1f24a79 4192 return num_counters;
0ad17a8f
MB		 4193}
4194
8e959601
NV		 4195static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
4196{
4197 return mlx5_rdma_netdev_free(netdev);
4198}
4199
693dfd5a
ES		 4200static struct net_device*
4201mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
4202 u8 port_num,
4203 enum rdma_netdev_t type,
4204 const char *name,
4205 unsigned char name_assign_type,
4206 void (*setup)(struct net_device *))
4207{
8e959601
NV		 4208 struct net_device *netdev;
4209 struct rdma_netdev *rn;
4210
693dfd5a
ES		 4211 if (type != RDMA_NETDEV_IPOIB)
4212 return ERR_PTR(-EOPNOTSUPP);
4213
8e959601
NV		 4214 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
4215 name, setup);
4216 if (likely(!IS_ERR_OR_NULL(netdev))) {
4217 rn = netdev_priv(netdev);
4218 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
4219 }
4220 return netdev;
693dfd5a
ES		 4221}
4222
fe248c3a
MG		 4223static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
4224{
4225 if (!dev->delay_drop.dbg)
4226 return;
4227 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
4228 kfree(dev->delay_drop.dbg);
4229 dev->delay_drop.dbg = NULL;
4230}
4231
03404e8a
MG		 4232static void cancel_delay_drop(struct mlx5_ib_dev *dev)
4233{
4234 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4235 return;
4236
4237 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 4238 delay_drop_debugfs_cleanup(dev);
4239}
4240
4241static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
4242 size_t count, loff_t *pos)
4243{
4244 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4245 char lbuf[20];
4246 int len;
4247
4248 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
4249 return simple_read_from_buffer(buf, count, pos, lbuf, len);
4250}
4251
4252static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
4253 size_t count, loff_t *pos)
4254{
4255 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4256 u32 timeout;
4257 u32 var;
4258
4259 if (kstrtouint_from_user(buf, count, 0, &var))
4260 return -EFAULT;
4261
4262 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
4263 1000);
4264 if (timeout != var)
4265 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
4266 timeout);
4267
4268 delay_drop->timeout = timeout;
4269
4270 return count;
4271}
4272
4273static const struct file_operations fops_delay_drop_timeout = {
4274 .owner = THIS_MODULE,
4275 .open = simple_open,
4276 .write = delay_drop_timeout_write,
4277 .read = delay_drop_timeout_read,
4278};
4279
4280static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
4281{
4282 struct mlx5_ib_dbg_delay_drop *dbg;
4283
4284 if (!mlx5_debugfs_root)
4285 return 0;
4286
4287 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
4288 if (!dbg)
4289 return -ENOMEM;
4290
cbafad87
SM		 4291 dev->delay_drop.dbg = dbg;
4292
fe248c3a
MG		 4293 dbg->dir_debugfs =
4294 debugfs_create_dir("delay_drop",
4295 dev->mdev->priv.dbg_root);
4296 if (!dbg->dir_debugfs)
cbafad87 4297 goto out_debugfs;
fe248c3a
MG		 4298
4299 dbg->events_cnt_debugfs =
4300 debugfs_create_atomic_t("num_timeout_events", 0400,
4301 dbg->dir_debugfs,
4302 &dev->delay_drop.events_cnt);
4303 if (!dbg->events_cnt_debugfs)
4304 goto out_debugfs;
4305
4306 dbg->rqs_cnt_debugfs =
4307 debugfs_create_atomic_t("num_rqs", 0400,
4308 dbg->dir_debugfs,
4309 &dev->delay_drop.rqs_cnt);
4310 if (!dbg->rqs_cnt_debugfs)
4311 goto out_debugfs;
4312
4313 dbg->timeout_debugfs =
4314 debugfs_create_file("timeout", 0600,
4315 dbg->dir_debugfs,
4316 &dev->delay_drop,
4317 &fops_delay_drop_timeout);
4318 if (!dbg->timeout_debugfs)
4319 goto out_debugfs;
4320
4321 return 0;
4322
4323out_debugfs:
4324 delay_drop_debugfs_cleanup(dev);
4325 return -ENOMEM;
03404e8a
MG		 4326}
4327
4328static void init_delay_drop(struct mlx5_ib_dev *dev)
4329{
4330 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4331 return;
4332
4333 mutex_init(&dev->delay_drop.lock);
4334 dev->delay_drop.dev = dev;
4335 dev->delay_drop.activate = false;
4336 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
4337 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 4338 atomic_set(&dev->delay_drop.rqs_cnt, 0);
4339 atomic_set(&dev->delay_drop.events_cnt, 0);
4340
4341 if (delay_drop_debugfs_init(dev))
4342 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
03404e8a
MG		 4343}
4344
84305d71
LR		 4345static const struct cpumask *
4346mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
40b24403
SG		 4347{
4348 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4349
4350 return mlx5_get_vector_affinity(dev->mdev, comp_vector);
4351}
4352
32f69e4b
DJ		 4353/* The mlx5_ib_multiport_mutex should be held when calling this function */
4354static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
4355 struct mlx5_ib_multiport_info *mpi)
4356{
4357 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
4358 struct mlx5_ib_port *port = &ibdev->port[port_num];
4359 int comps;
4360 int err;
4361 int i;
4362
a9e546e7
PP		 4363 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
4364
32f69e4b
DJ		 4365 spin_lock(&port->mp.mpi_lock);
4366 if (!mpi->ibdev) {
4367 spin_unlock(&port->mp.mpi_lock);
4368 return;
4369 }
4370 mpi->ibdev = NULL;
4371
4372 spin_unlock(&port->mp.mpi_lock);
4373 mlx5_remove_netdev_notifier(ibdev, port_num);
4374 spin_lock(&port->mp.mpi_lock);
4375
4376 comps = mpi->mdev_refcnt;
4377 if (comps) {
4378 mpi->unaffiliate = true;
4379 init_completion(&mpi->unref_comp);
4380 spin_unlock(&port->mp.mpi_lock);
4381
4382 for (i = 0; i < comps; i++)
4383 wait_for_completion(&mpi->unref_comp);
4384
4385 spin_lock(&port->mp.mpi_lock);
4386 mpi->unaffiliate = false;
4387 }
4388
4389 port->mp.mpi = NULL;
4390
4391 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
4392
4393 spin_unlock(&port->mp.mpi_lock);
4394
4395 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
4396
4397 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
4398 /* Log an error, still needed to cleanup the pointers and add
4399 * it back to the list.
4400 */
4401 if (err)
4402 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
4403 port_num + 1);
4404
4405 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
4406}
4407
4408/* The mlx5_ib_multiport_mutex should be held when calling this function */
4409static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
4410 struct mlx5_ib_multiport_info *mpi)
4411{
4412 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
4413 int err;
4414
4415 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
4416 if (ibdev->port[port_num].mp.mpi) {
4417 mlx5_ib_warn(ibdev, "port %d already affiliated.\n",
4418 port_num + 1);
4419 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
4420 return false;
4421 }
4422
4423 ibdev->port[port_num].mp.mpi = mpi;
4424 mpi->ibdev = ibdev;
4425 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
4426
4427 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
4428 if (err)
4429 goto unbind;
4430
4431 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
4432 if (err)
4433 goto unbind;
4434
4435 err = mlx5_add_netdev_notifier(ibdev, port_num);
4436 if (err) {
4437 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
4438 port_num + 1);
4439 goto unbind;
4440 }
4441
a9e546e7
PP		 4442 err = mlx5_ib_init_cong_debugfs(ibdev, port_num);
4443 if (err)
4444 goto unbind;
4445
32f69e4b
DJ		 4446 return true;
4447
4448unbind:
4449 mlx5_ib_unbind_slave_port(ibdev, mpi);
4450 return false;
4451}
4452
4453static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
4454{
4455 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4456 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
4457 port_num + 1);
4458 struct mlx5_ib_multiport_info *mpi;
4459 int err;
4460 int i;
4461
4462 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
4463 return 0;
4464
4465 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
4466 &dev->sys_image_guid);
4467 if (err)
4468 return err;
4469
4470 err = mlx5_nic_vport_enable_roce(dev->mdev);
4471 if (err)
4472 return err;
4473
4474 mutex_lock(&mlx5_ib_multiport_mutex);
4475 for (i = 0; i < dev->num_ports; i++) {
4476 bool bound = false;
4477
4478 /* build a stub multiport info struct for the native port. */
4479 if (i == port_num) {
4480 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
4481 if (!mpi) {
4482 mutex_unlock(&mlx5_ib_multiport_mutex);
4483 mlx5_nic_vport_disable_roce(dev->mdev);
4484 return -ENOMEM;
4485 }
4486
4487 mpi->is_master = true;
4488 mpi->mdev = dev->mdev;
4489 mpi->sys_image_guid = dev->sys_image_guid;
4490 dev->port[i].mp.mpi = mpi;
4491 mpi->ibdev = dev;
4492 mpi = NULL;
4493 continue;
4494 }
4495
4496 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
4497 list) {
4498 if (dev->sys_image_guid == mpi->sys_image_guid &&
4499 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
4500 bound = mlx5_ib_bind_slave_port(dev, mpi);
4501 }
4502
4503 if (bound) {
4504 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
4505 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
4506 list_del(&mpi->list);
4507 break;
4508 }
4509 }
4510 if (!bound) {
4511 get_port_caps(dev, i + 1);
4512 mlx5_ib_dbg(dev, "no free port found for port %d\n",
4513 i + 1);
4514 }
4515 }
4516
4517 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
4518 mutex_unlock(&mlx5_ib_multiport_mutex);
4519 return err;
4520}
4521
4522static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
4523{
4524 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4525 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
4526 port_num + 1);
4527 int i;
4528
4529 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
4530 return;
4531
4532 mutex_lock(&mlx5_ib_multiport_mutex);
4533 for (i = 0; i < dev->num_ports; i++) {
4534 if (dev->port[i].mp.mpi) {
4535 /* Destroy the native port stub */
4536 if (i == port_num) {
4537 kfree(dev->port[i].mp.mpi);
4538 dev->port[i].mp.mpi = NULL;
4539 } else {
4540 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
4541 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
4542 }
4543 }
4544 }
4545
4546 mlx5_ib_dbg(dev, "removing from devlist\n");
4547 list_del(&dev->ib_dev_list);
4548 mutex_unlock(&mlx5_ib_multiport_mutex);
4549
4550 mlx5_nic_vport_disable_roce(dev->mdev);
4551}
4552
b5ca15ad 4553void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
e126ba97 4554{
32f69e4b 4555 mlx5_ib_cleanup_multiport_master(dev);
3cc297db
MB		 4556#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4557 cleanup_srcu_struct(&dev->mr_srcu);
4558#endif
16c1975f
MB		 4559 kfree(dev->port);
4560}
4561
b5ca15ad 4562int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 4563{
4564 struct mlx5_core_dev *mdev = dev->mdev;
4babcf97 4565 const char *name;
e126ba97 4566 int err;
32f69e4b 4567 int i;
e126ba97 4568
508562d6 4569 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
0837e86a
MB		 4570 GFP_KERNEL);
4571 if (!dev->port)
16c1975f 4572 return -ENOMEM;
0837e86a 4573
32f69e4b
DJ		 4574 for (i = 0; i < dev->num_ports; i++) {
4575 spin_lock_init(&dev->port[i].mp.mpi_lock);
4576 rwlock_init(&dev->roce[i].netdev_lock);
4577 }
4578
4579 err = mlx5_ib_init_multiport_master(dev);
e126ba97 4580 if (err)
0837e86a 4581 goto err_free_port;
e126ba97 4582
32f69e4b 4583 if (!mlx5_core_mp_enabled(mdev)) {
32f69e4b
DJ		 4584 for (i = 1; i <= dev->num_ports; i++) {
4585 err = get_port_caps(dev, i);
4586 if (err)
4587 break;
4588 }
4589 } else {
4590 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
4591 }
4592 if (err)
4593 goto err_mp;
4594
1b5daf11
MD		 4595 if (mlx5_use_mad_ifc(dev))
4596 get_ext_port_caps(dev);
e126ba97 4597
4babcf97
AH		 4598 if (!mlx5_lag_is_active(mdev))
4599 name = "mlx5_%d";
4600 else
4601 name = "mlx5_bond_%d";
4602
4603 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
e126ba97
EC		 4604 dev->ib_dev.owner = THIS_MODULE;
4605 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 4606 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
508562d6 4607 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 4608 dev->ib_dev.num_comp_vectors =
4609 dev->mdev->priv.eq_table.num_comp_vectors;
9b0c289e 4610 dev->ib_dev.dev.parent = &mdev->pdev->dev;
e126ba97 4611
3cc297db
MB		 4612 mutex_init(&dev->cap_mask_mutex);
4613 INIT_LIST_HEAD(&dev->qp_list);
4614 spin_lock_init(&dev->reset_flow_resource_lock);
4615
4616#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4617 err = init_srcu_struct(&dev->mr_srcu);
4618 if (err)
4619 goto err_free_port;
4620#endif
4621
16c1975f 4622 return 0;
32f69e4b
DJ		 4623err_mp:
4624 mlx5_ib_cleanup_multiport_master(dev);
16c1975f
MB		 4625
4626err_free_port:
4627 kfree(dev->port);
4628
4629 return -ENOMEM;
4630}
4631
9a4ca38d
MB		 4632static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
4633{
4634 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
4635
4636 if (!dev->flow_db)
4637 return -ENOMEM;
4638
4639 mutex_init(&dev->flow_db->lock);
4640
4641 return 0;
4642}
4643
b5ca15ad
MB		 4644int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev)
4645{
4646 struct mlx5_ib_dev *nic_dev;
4647
4648 nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch);
4649
4650 if (!nic_dev)
4651 return -EINVAL;
4652
4653 dev->flow_db = nic_dev->flow_db;
4654
4655 return 0;
4656}
4657
9a4ca38d
MB		 4658static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
4659{
4660 kfree(dev->flow_db);
4661}
4662
b5ca15ad 4663int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 4664{
4665 struct mlx5_core_dev *mdev = dev->mdev;
16c1975f
MB		 4666 int err;
4667
e126ba97
EC		 4668 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
4669 dev->ib_dev.uverbs_cmd_mask =
4670 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
4671 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
4672 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
4673 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
4674 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 4675 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
4676 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 4677 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 4678 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 4679 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
4680 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
4681 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
4682 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
4683 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
4684 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
4685 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
4686 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
4687 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
4688 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
4689 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
4690 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
4691 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
4692 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
4693 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
4694 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
4695 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 4696 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 4697 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
4698 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349 4699 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
b0e9df6d
YC		 4700 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
4701 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
e126ba97
EC		 4702
4703 dev->ib_dev.query_device = mlx5_ib_query_device;
ebd61f68 4704 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
e126ba97 4705 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 4706 dev->ib_dev.add_gid = mlx5_ib_add_gid;
4707 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 4708 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
4709 dev->ib_dev.modify_device = mlx5_ib_modify_device;
4710 dev->ib_dev.modify_port = mlx5_ib_modify_port;
4711 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
4712 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
4713 dev->ib_dev.mmap = mlx5_ib_mmap;
4714 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
4715 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
4716 dev->ib_dev.create_ah = mlx5_ib_create_ah;
4717 dev->ib_dev.query_ah = mlx5_ib_query_ah;
4718 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
4719 dev->ib_dev.create_srq = mlx5_ib_create_srq;
4720 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
4721 dev->ib_dev.query_srq = mlx5_ib_query_srq;
4722 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
4723 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
4724 dev->ib_dev.create_qp = mlx5_ib_create_qp;
4725 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
4726 dev->ib_dev.query_qp = mlx5_ib_query_qp;
4727 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
4728 dev->ib_dev.post_send = mlx5_ib_post_send;
4729 dev->ib_dev.post_recv = mlx5_ib_post_recv;
4730 dev->ib_dev.create_cq = mlx5_ib_create_cq;
4731 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
4732 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
4733 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
4734 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
4735 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
4736 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
4737 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 4738 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 4739 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
4740 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
4741 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
4742 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 4743 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 4744 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 4745 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
c7342823 4746 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
40b24403 4747 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
8e959601 4748 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
022d038a 4749 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
8e959601 4750
eff901d3
EC		 4751 if (mlx5_core_is_pf(mdev)) {
4752 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
4753 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
4754 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
4755 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
4756 }
e126ba97 4757
7c2344c3
MG		 4758 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
4759
6e8484c5
MG		 4760 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
4761
d2370e0a
MB		 4762 if (MLX5_CAP_GEN(mdev, imaicl)) {
4763 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
4764 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
4765 dev->ib_dev.uverbs_cmd_mask |=
4766 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
4767 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
4768 }
4769
938fe83c 4770 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 4771 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
4772 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
4773 dev->ib_dev.uverbs_cmd_mask |=
4774 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
4775 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
4776 }
4777
81e30880
YH		 4778 dev->ib_dev.create_flow = mlx5_ib_create_flow;
4779 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
4780 dev->ib_dev.uverbs_ex_cmd_mask |=
4781 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
4782 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
4783
e126ba97
EC		 4784 err = init_node_data(dev);
4785 if (err)
16c1975f 4786 return err;
e126ba97 4787
c8b89924 4788 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
e7996a9a
JG		 4789 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
4790 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c8b89924
MB		 4791 mutex_init(&dev->lb_mutex);
4792
16c1975f
MB		 4793 return 0;
4794}
4795
8e6efa3a
MB		 4796static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
4797{
4798 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
4799 dev->ib_dev.query_port = mlx5_ib_query_port;
4800
4801 return 0;
4802}
4803
b5ca15ad 4804int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
8e6efa3a
MB		 4805{
4806 dev->ib_dev.get_port_immutable = mlx5_port_rep_immutable;
4807 dev->ib_dev.query_port = mlx5_ib_rep_query_port;
4808
4809 return 0;
4810}
4811
4812static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev,
4813 u8 port_num)
4814{
4815 int i;
4816
4817 for (i = 0; i < dev->num_ports; i++) {
4818 dev->roce[i].dev = dev;
4819 dev->roce[i].native_port_num = i + 1;
4820 dev->roce[i].last_port_state = IB_PORT_DOWN;
4821 }
4822
4823 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
4824 dev->ib_dev.create_wq = mlx5_ib_create_wq;
4825 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
4826 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
4827 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
4828 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
4829
4830 dev->ib_dev.uverbs_ex_cmd_mask |=
4831 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
4832 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
4833 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
4834 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
4835 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
4836
4837 return mlx5_add_netdev_notifier(dev, port_num);
4838}
4839
4840static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
4841{
4842 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4843
4844 mlx5_remove_netdev_notifier(dev, port_num);
4845}
4846
4847int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
4848{
4849 struct mlx5_core_dev *mdev = dev->mdev;
4850 enum rdma_link_layer ll;
4851 int port_type_cap;
4852 int err = 0;
4853 u8 port_num;
4854
4855 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4856 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4857 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4858
4859 if (ll == IB_LINK_LAYER_ETHERNET)
4860 err = mlx5_ib_stage_common_roce_init(dev, port_num);
4861
4862 return err;
4863}
4864
4865void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
4866{
4867 mlx5_ib_stage_common_roce_cleanup(dev);
4868}
4869
16c1975f
MB		 4870static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
4871{
4872 struct mlx5_core_dev *mdev = dev->mdev;
4873 enum rdma_link_layer ll;
4874 int port_type_cap;
32f69e4b 4875 u8 port_num;
16c1975f
MB		 4876 int err;
4877
32f69e4b 4878 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
16c1975f
MB		 4879 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4880 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4881
fc24fc5e 4882 if (ll == IB_LINK_LAYER_ETHERNET) {
8e6efa3a
MB		 4883 err = mlx5_ib_stage_common_roce_init(dev, port_num);
4884 if (err)
4885 return err;
7fd8aefb 4886
7fd8aefb 4887 err = mlx5_enable_eth(dev, port_num);
fc24fc5e 4888 if (err)
8e6efa3a 4889 goto cleanup;
fc24fc5e
AS		 4890 }
4891
16c1975f 4892 return 0;
8e6efa3a
MB		 4893cleanup:
4894 mlx5_ib_stage_common_roce_cleanup(dev);
4895
4896 return err;
16c1975f 4897}
e126ba97 4898
16c1975f
MB		 4899static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
4900{
4901 struct mlx5_core_dev *mdev = dev->mdev;
4902 enum rdma_link_layer ll;
4903 int port_type_cap;
32f69e4b 4904 u8 port_num;
e126ba97 4905
32f69e4b 4906 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
16c1975f
MB		 4907 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4908 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4909
4910 if (ll == IB_LINK_LAYER_ETHERNET) {
4911 mlx5_disable_eth(dev);
8e6efa3a 4912 mlx5_ib_stage_common_roce_cleanup(dev);
45bded2c 4913 }
16c1975f 4914}
6aec21f6 4915
b5ca15ad 4916int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 4917{
4918 return create_dev_resources(&dev->devr);
4919}
4920
b5ca15ad 4921void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 4922{
4923 destroy_dev_resources(&dev->devr);
4924}
4925
4926static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
4927{
07321b3c
MB		 4928 mlx5_ib_internal_fill_odp_caps(dev);
4929
16c1975f
MB		 4930 return mlx5_ib_odp_init_one(dev);
4931}
4a2da0b8 4932
b5ca15ad 4933int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
16c1975f 4934{
5e1e7612
MB		 4935 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
4936 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
4937 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
4938
4939 return mlx5_ib_alloc_counters(dev);
4940 }
16c1975f
MB		 4941
4942 return 0;
4943}
4944
b5ca15ad 4945void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 4946{
4947 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
4948 mlx5_ib_dealloc_counters(dev);
4949}
4950
4951static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
4952{
a9e546e7
PP		 4953 return mlx5_ib_init_cong_debugfs(dev,
4954 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 4955}
4956
4957static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
4958{
a9e546e7
PP		 4959 mlx5_ib_cleanup_cong_debugfs(dev,
4960 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 4961}
4962
4963static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
4964{
5fe9dec0
EC		 4965 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
4966 if (!dev->mdev->priv.uar)
16c1975f
MB		 4967 return -ENOMEM;
4968 return 0;
4969}
4970
4971static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
4972{
4973 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4974}
4975
b5ca15ad 4976int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 4977{
4978 int err;
5fe9dec0
EC		 4979
4980 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4981 if (err)
16c1975f 4982 return err;
5fe9dec0
EC		 4983
4984 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4985 if (err)
16c1975f 4986 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5fe9dec0 4987
16c1975f
MB		 4988 return err;
4989}
0837e86a 4990
b5ca15ad 4991void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 4992{
4993 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4994 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4995}
e126ba97 4996
b5ca15ad 4997int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 4998{
4999 return ib_register_device(&dev->ib_dev, NULL);
5000}
5001
b5ca15ad 5002void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 5003{
5004 ib_unregister_device(&dev->ib_dev);
5005}
5006
b5ca15ad 5007int mlx5_ib_stage_umr_res_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5008{
5009 return create_umr_res(dev);
5010}
5011
b5ca15ad 5012void mlx5_ib_stage_umr_res_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 5013{
5014 destroy_umrc_res(dev);
5015}
5016
5017static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
5018{
03404e8a
MG		 5019 init_delay_drop(dev);
5020
16c1975f
MB		 5021 return 0;
5022}
5023
5024static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
5025{
5026 cancel_delay_drop(dev);
5027}
5028
b5ca15ad 5029int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5030{
5031 int err;
5032 int i;
5033
e126ba97 5034 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 5035 err = device_create_file(&dev->ib_dev.dev,
5036 mlx5_class_attributes[i]);
5037 if (err)
16c1975f 5038 return err;
e126ba97
EC		 5039 }
5040
16c1975f
MB		 5041 return 0;
5042}
5043
fc385b7a
MB		 5044static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev *dev)
5045{
5046 mlx5_ib_register_vport_reps(dev);
5047
5048 return 0;
5049}
5050
5051static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev *dev)
5052{
5053 mlx5_ib_unregister_vport_reps(dev);
5054}
5055
b5ca15ad
MB		 5056void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
5057 const struct mlx5_ib_profile *profile,
5058 int stage)
16c1975f
MB		 5059{
5060 /* Number of stages to cleanup */
5061 while (stage) {
5062 stage--;
5063 if (profile->stage[stage].cleanup)
5064 profile->stage[stage].cleanup(dev);
5065 }
e126ba97 5066
16c1975f
MB		 5067 ib_dealloc_device((struct ib_device *)dev);
5068}
e126ba97 5069
32f69e4b
DJ		 5070static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num);
5071
b5ca15ad
MB		 5072void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
5073 const struct mlx5_ib_profile *profile)
16c1975f 5074{
16c1975f
MB		 5075 int err;
5076 int i;
e126ba97 5077
16c1975f 5078 printk_once(KERN_INFO "%s", mlx5_version);
5fe9dec0 5079
16c1975f
MB		 5080 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
5081 if (profile->stage[i].init) {
5082 err = profile->stage[i].init(dev);
5083 if (err)
5084 goto err_out;
5085 }
5086 }
0837e86a 5087
16c1975f
MB		 5088 dev->profile = profile;
5089 dev->ib_active = true;
6aec21f6 5090
16c1975f 5091 return dev;
e126ba97 5092
16c1975f
MB		 5093err_out:
5094 __mlx5_ib_remove(dev, profile, i);
fc24fc5e 5095
16c1975f
MB		 5096 return NULL;
5097}
0837e86a 5098
16c1975f
MB		 5099static const struct mlx5_ib_profile pf_profile = {
5100 STAGE_CREATE(MLX5_IB_STAGE_INIT,
5101 mlx5_ib_stage_init_init,
5102 mlx5_ib_stage_init_cleanup),
9a4ca38d
MB		 5103 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
5104 mlx5_ib_stage_flow_db_init,
5105 mlx5_ib_stage_flow_db_cleanup),
16c1975f
MB		 5106 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
5107 mlx5_ib_stage_caps_init,
5108 NULL),
8e6efa3a
MB		 5109 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
5110 mlx5_ib_stage_non_default_cb,
5111 NULL),
16c1975f
MB		 5112 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
5113 mlx5_ib_stage_roce_init,
5114 mlx5_ib_stage_roce_cleanup),
5115 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
5116 mlx5_ib_stage_dev_res_init,
5117 mlx5_ib_stage_dev_res_cleanup),
5118 STAGE_CREATE(MLX5_IB_STAGE_ODP,
5119 mlx5_ib_stage_odp_init,
3cc297db 5120 NULL),
16c1975f
MB		 5121 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
5122 mlx5_ib_stage_counters_init,
5123 mlx5_ib_stage_counters_cleanup),
5124 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
5125 mlx5_ib_stage_cong_debugfs_init,
5126 mlx5_ib_stage_cong_debugfs_cleanup),
5127 STAGE_CREATE(MLX5_IB_STAGE_UAR,
5128 mlx5_ib_stage_uar_init,
5129 mlx5_ib_stage_uar_cleanup),
5130 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
5131 mlx5_ib_stage_bfrag_init,
5132 mlx5_ib_stage_bfrag_cleanup),
5133 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
5134 mlx5_ib_stage_ib_reg_init,
5135 mlx5_ib_stage_ib_reg_cleanup),
5136 STAGE_CREATE(MLX5_IB_STAGE_UMR_RESOURCES,
5137 mlx5_ib_stage_umr_res_init,
5138 mlx5_ib_stage_umr_res_cleanup),
5139 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
5140 mlx5_ib_stage_delay_drop_init,
5141 mlx5_ib_stage_delay_drop_cleanup),
5142 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
5143 mlx5_ib_stage_class_attr_init,
5144 NULL),
16c1975f 5145};
e126ba97 5146
b5ca15ad
MB		 5147static const struct mlx5_ib_profile nic_rep_profile = {
5148 STAGE_CREATE(MLX5_IB_STAGE_INIT,
5149 mlx5_ib_stage_init_init,
5150 mlx5_ib_stage_init_cleanup),
5151 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
5152 mlx5_ib_stage_flow_db_init,
5153 mlx5_ib_stage_flow_db_cleanup),
5154 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
5155 mlx5_ib_stage_caps_init,
5156 NULL),
5157 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
5158 mlx5_ib_stage_rep_non_default_cb,
5159 NULL),
5160 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
5161 mlx5_ib_stage_rep_roce_init,
5162 mlx5_ib_stage_rep_roce_cleanup),
5163 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
5164 mlx5_ib_stage_dev_res_init,
5165 mlx5_ib_stage_dev_res_cleanup),
5166 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
5167 mlx5_ib_stage_counters_init,
5168 mlx5_ib_stage_counters_cleanup),
5169 STAGE_CREATE(MLX5_IB_STAGE_UAR,
5170 mlx5_ib_stage_uar_init,
5171 mlx5_ib_stage_uar_cleanup),
5172 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
5173 mlx5_ib_stage_bfrag_init,
5174 mlx5_ib_stage_bfrag_cleanup),
5175 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
5176 mlx5_ib_stage_ib_reg_init,
5177 mlx5_ib_stage_ib_reg_cleanup),
5178 STAGE_CREATE(MLX5_IB_STAGE_UMR_RESOURCES,
5179 mlx5_ib_stage_umr_res_init,
5180 mlx5_ib_stage_umr_res_cleanup),
5181 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
5182 mlx5_ib_stage_class_attr_init,
5183 NULL),
5184 STAGE_CREATE(MLX5_IB_STAGE_REP_REG,
5185 mlx5_ib_stage_rep_reg_init,
5186 mlx5_ib_stage_rep_reg_cleanup),
5187};
5188
32f69e4b
DJ		 5189static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num)
5190{
5191 struct mlx5_ib_multiport_info *mpi;
5192 struct mlx5_ib_dev *dev;
5193 bool bound = false;
5194 int err;
5195
5196 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5197 if (!mpi)
5198 return NULL;
5199
5200 mpi->mdev = mdev;
5201
5202 err = mlx5_query_nic_vport_system_image_guid(mdev,
5203 &mpi->sys_image_guid);
5204 if (err) {
5205 kfree(mpi);
5206 return NULL;
5207 }
5208
5209 mutex_lock(&mlx5_ib_multiport_mutex);
5210 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
5211 if (dev->sys_image_guid == mpi->sys_image_guid)
5212 bound = mlx5_ib_bind_slave_port(dev, mpi);
5213
5214 if (bound) {
5215 rdma_roce_rescan_device(&dev->ib_dev);
5216 break;
5217 }
5218 }
5219
5220 if (!bound) {
5221 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5222 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
5223 } else {
5224 mlx5_ib_dbg(dev, "bound port %u\n", port_num + 1);
5225 }
5226 mutex_unlock(&mlx5_ib_multiport_mutex);
5227
5228 return mpi;
5229}
5230
16c1975f
MB		 5231static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
5232{
32f69e4b 5233 enum rdma_link_layer ll;
b5ca15ad 5234 struct mlx5_ib_dev *dev;
32f69e4b
DJ		 5235 int port_type_cap;
5236
b5ca15ad
MB		 5237 printk_once(KERN_INFO "%s", mlx5_version);
5238
32f69e4b
DJ		 5239 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5240 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5241
5242 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) {
5243 u8 port_num = mlx5_core_native_port_num(mdev) - 1;
5244
5245 return mlx5_ib_add_slave_port(mdev, port_num);
5246 }
5247
b5ca15ad
MB		 5248 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
5249 if (!dev)
5250 return NULL;
5251
5252 dev->mdev = mdev;
5253 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
5254 MLX5_CAP_GEN(mdev, num_vhca_ports));
5255
5256 if (MLX5_VPORT_MANAGER(mdev) &&
5257 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
5258 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0);
5259
5260 return __mlx5_ib_add(dev, &nic_rep_profile);
5261 }
5262
5263 return __mlx5_ib_add(dev, &pf_profile);
e126ba97
EC		 5264}
5265
9603b61d 5266static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 5267{
32f69e4b
DJ		 5268 struct mlx5_ib_multiport_info *mpi;
5269 struct mlx5_ib_dev *dev;
5270
5271 if (mlx5_core_is_mp_slave(mdev)) {
5272 mpi = context;
5273 mutex_lock(&mlx5_ib_multiport_mutex);
5274 if (mpi->ibdev)
5275 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
5276 list_del(&mpi->list);
5277 mutex_unlock(&mlx5_ib_multiport_mutex);
5278 return;
5279 }
6aec21f6 5280
32f69e4b 5281 dev = context;
16c1975f 5282 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
e126ba97
EC		 5283}
5284
9603b61d
JM		 5285static struct mlx5_interface mlx5_ib_interface = {
5286 .add = mlx5_ib_add,
5287 .remove = mlx5_ib_remove,
5288 .event = mlx5_ib_event,
d9aaed83
AK		 5289#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5290 .pfault = mlx5_ib_pfault,
5291#endif
64613d94 5292 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 5293};
5294
5295static int __init mlx5_ib_init(void)
5296{
6aec21f6
HE		 5297 int err;
5298
d69a24e0
DJ		 5299 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
5300 if (!mlx5_ib_event_wq)
5301 return -ENOMEM;
5302
81713d37 5303 mlx5_ib_odp_init();
9603b61d 5304
6aec21f6 5305 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 5306
6aec21f6 5307 return err;
e126ba97
EC		 5308}
5309
5310static void __exit mlx5_ib_cleanup(void)
5311{
9603b61d 5312 mlx5_unregister_interface(&mlx5_ib_interface);
d69a24e0 5313 destroy_workqueue(mlx5_ib_event_wq);
e126ba97
EC		 5314}
5315
5316module_init(mlx5_ib_init);
5317module_exit(mlx5_ib_cleanup);
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