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IB/core: Add XRQ capabilities
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
37aa5c36
GL		 41#if defined(CONFIG_X86)
42#include <asm/pat.h>
43#endif
e126ba97 44#include <linux/sched.h>
6e84f315 45#include <linux/sched/mm.h>
0881e7bd 46#include <linux/sched/task.h>
7c2344c3 47#include <linux/delay.h>
e126ba97 48#include <rdma/ib_user_verbs.h>
3f89a643 49#include <rdma/ib_addr.h>
2811ba51 50#include <rdma/ib_cache.h>
ada68c31 51#include <linux/mlx5/port.h>
1b5daf11 52#include <linux/mlx5/vport.h>
7c2344c3 53#include <linux/list.h>
e126ba97
EC		 54#include <rdma/ib_smi.h>
55#include <rdma/ib_umem.h>
038d2ef8
MG		 56#include <linux/in.h>
57#include <linux/etherdevice.h>
58#include <linux/mlx5/fs.h>
78984898 59#include <linux/mlx5/vport.h>
e126ba97 60#include "mlx5_ib.h"
e1f24a79 61#include "cmd.h"
c85023e1 62#include <linux/mlx5/vport.h>
e126ba97
EC		 63
64#define DRIVER_NAME "mlx5_ib"
b359911d 65#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 66
67MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
68MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
69MODULE_LICENSE("Dual BSD/GPL");
e126ba97 70
e126ba97
EC		 71static char mlx5_version[] =
72 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 73 DRIVER_VERSION "\n";
e126ba97 74
da7525d2
EBE		 75enum {
76 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
77};
78
1b5daf11 79static enum rdma_link_layer
ebd61f68 80mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 81{
ebd61f68 82 switch (port_type_cap) {
1b5daf11
MD		 83 case MLX5_CAP_PORT_TYPE_IB:
84 return IB_LINK_LAYER_INFINIBAND;
85 case MLX5_CAP_PORT_TYPE_ETH:
86 return IB_LINK_LAYER_ETHERNET;
87 default:
88 return IB_LINK_LAYER_UNSPECIFIED;
89 }
90}
91
ebd61f68
AS		 92static enum rdma_link_layer
93mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
94{
95 struct mlx5_ib_dev *dev = to_mdev(device);
96 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
97
98 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
99}
100
fd65f1b8
MS		 101static int get_port_state(struct ib_device *ibdev,
102 u8 port_num,
103 enum ib_port_state *state)
104{
105 struct ib_port_attr attr;
106 int ret;
107
108 memset(&attr, 0, sizeof(attr));
109 ret = mlx5_ib_query_port(ibdev, port_num, &attr);
110 if (!ret)
111 *state = attr.state;
112 return ret;
113}
114
fc24fc5e
AS		 115static int mlx5_netdev_event(struct notifier_block *this,
116 unsigned long event, void *ptr)
117{
118 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
119 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
120 roce.nb);
121
5ec8c83e
AH		 122 switch (event) {
123 case NETDEV_REGISTER:
124 case NETDEV_UNREGISTER:
125 write_lock(&ibdev->roce.netdev_lock);
126 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
127 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
128 NULL : ndev;
129 write_unlock(&ibdev->roce.netdev_lock);
130 break;
fc24fc5e 131
fd65f1b8 132 case NETDEV_CHANGE:
5ec8c83e 133 case NETDEV_UP:
88621dfe
AH		 134 case NETDEV_DOWN: {
135 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
136 struct net_device *upper = NULL;
137
138 if (lag_ndev) {
139 upper = netdev_master_upper_dev_get(lag_ndev);
140 dev_put(lag_ndev);
141 }
142
143 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
144 && ibdev->ib_active) {
626bc02d 145 struct ib_event ibev = { };
fd65f1b8 146 enum ib_port_state port_state;
5ec8c83e 147
fd65f1b8
MS		 148 if (get_port_state(&ibdev->ib_dev, 1, &port_state))
149 return NOTIFY_DONE;
150
151 if (ibdev->roce.last_port_state == port_state)
152 return NOTIFY_DONE;
153
154 ibdev->roce.last_port_state = port_state;
5ec8c83e 155 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 156 if (port_state == IB_PORT_DOWN)
157 ibev.event = IB_EVENT_PORT_ERR;
158 else if (port_state == IB_PORT_ACTIVE)
159 ibev.event = IB_EVENT_PORT_ACTIVE;
160 else
161 return NOTIFY_DONE;
162
5ec8c83e
AH		 163 ibev.element.port_num = 1;
164 ib_dispatch_event(&ibev);
165 }
166 break;
88621dfe 167 }
fc24fc5e 168
5ec8c83e
AH		 169 default:
170 break;
171 }
fc24fc5e
AS		 172
173 return NOTIFY_DONE;
174}
175
176static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
177 u8 port_num)
178{
179 struct mlx5_ib_dev *ibdev = to_mdev(device);
180 struct net_device *ndev;
181
88621dfe
AH		 182 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
183 if (ndev)
184 return ndev;
185
fc24fc5e
AS		 186 /* Ensure ndev does not disappear before we invoke dev_hold()
187 */
188 read_lock(&ibdev->roce.netdev_lock);
189 ndev = ibdev->roce.netdev;
190 if (ndev)
191 dev_hold(ndev);
192 read_unlock(&ibdev->roce.netdev_lock);
193
194 return ndev;
195}
196
f1b65df5
NO		 197static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
198 u8 *active_width)
199{
200 switch (eth_proto_oper) {
201 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
202 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
203 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
204 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
205 *active_width = IB_WIDTH_1X;
206 *active_speed = IB_SPEED_SDR;
207 break;
208 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
209 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
210 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
211 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
212 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
213 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
214 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
215 *active_width = IB_WIDTH_1X;
216 *active_speed = IB_SPEED_QDR;
217 break;
218 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
219 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
220 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
221 *active_width = IB_WIDTH_1X;
222 *active_speed = IB_SPEED_EDR;
223 break;
224 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
225 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
226 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
227 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
228 *active_width = IB_WIDTH_4X;
229 *active_speed = IB_SPEED_QDR;
230 break;
231 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
232 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
233 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
234 *active_width = IB_WIDTH_1X;
235 *active_speed = IB_SPEED_HDR;
236 break;
237 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
238 *active_width = IB_WIDTH_4X;
239 *active_speed = IB_SPEED_FDR;
240 break;
241 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
242 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
243 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
244 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
245 *active_width = IB_WIDTH_4X;
246 *active_speed = IB_SPEED_EDR;
247 break;
248 default:
249 return -EINVAL;
250 }
251
252 return 0;
253}
254
095b0927
IT		 255static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
256 struct ib_port_attr *props)
3f89a643
AS		 257{
258 struct mlx5_ib_dev *dev = to_mdev(device);
f1b65df5 259 struct mlx5_core_dev *mdev = dev->mdev;
88621dfe 260 struct net_device *ndev, *upper;
3f89a643 261 enum ib_mtu ndev_ib_mtu;
c876a1b7 262 u16 qkey_viol_cntr;
f1b65df5 263 u32 eth_prot_oper;
095b0927 264 int err;
3f89a643 265
f1b65df5
NO		 266 /* Possible bad flows are checked before filling out props so in case
267 * of an error it will still be zeroed out.
50f22fd8 268 */
095b0927
IT		 269 err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper, port_num);
270 if (err)
271 return err;
f1b65df5
NO		 272
273 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
274 &props->active_width);
3f89a643
AS		 275
276 props->port_cap_flags |= IB_PORT_CM_SUP;
277 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
278
279 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
280 roce_address_table_size);
281 props->max_mtu = IB_MTU_4096;
282 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
283 props->pkey_tbl_len = 1;
284 props->state = IB_PORT_DOWN;
285 props->phys_state = 3;
286
c876a1b7
LR		 287 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
288 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643
AS		 289
290 ndev = mlx5_ib_get_netdev(device, port_num);
291 if (!ndev)
095b0927 292 return 0;
3f89a643 293
88621dfe
AH		 294 if (mlx5_lag_is_active(dev->mdev)) {
295 rcu_read_lock();
296 upper = netdev_master_upper_dev_get_rcu(ndev);
297 if (upper) {
298 dev_put(ndev);
299 ndev = upper;
300 dev_hold(ndev);
301 }
302 rcu_read_unlock();
303 }
304
3f89a643
AS		 305 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
306 props->state = IB_PORT_ACTIVE;
307 props->phys_state = 5;
308 }
309
310 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
311
312 dev_put(ndev);
313
314 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
095b0927 315 return 0;
3f89a643
AS		 316}
317
095b0927
IT		 318static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
319 unsigned int index, const union ib_gid *gid,
320 const struct ib_gid_attr *attr)
3cca2606 321{
095b0927
IT		 322 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
323 u8 roce_version = 0;
324 u8 roce_l3_type = 0;
325 bool vlan = false;
326 u8 mac[ETH_ALEN];
327 u16 vlan_id = 0;
328
329 if (gid) {
330 gid_type = attr->gid_type;
331 ether_addr_copy(mac, attr->ndev->dev_addr);
332
333 if (is_vlan_dev(attr->ndev)) {
334 vlan = true;
335 vlan_id = vlan_dev_vlan_id(attr->ndev);
336 }
3cca2606
AS		 337 }
338
095b0927 339 switch (gid_type) {
3cca2606 340 case IB_GID_TYPE_IB:
095b0927 341 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 342 break;
343 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 344 roce_version = MLX5_ROCE_VERSION_2;
345 if (ipv6_addr_v4mapped((void *)gid))
346 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
347 else
348 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 349 break;
350
351 default:
095b0927 352 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 353 }
354
095b0927
IT		 355 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
356 roce_l3_type, gid->raw, mac, vlan,
357 vlan_id);
3cca2606
AS		 358}
359
360static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
361 unsigned int index, const union ib_gid *gid,
362 const struct ib_gid_attr *attr,
363 __always_unused void **context)
364{
095b0927 365 return set_roce_addr(to_mdev(device), port_num, index, gid, attr);
3cca2606
AS		 366}
367
368static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
369 unsigned int index, __always_unused void **context)
370{
095b0927 371 return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL);
3cca2606
AS		 372}
373
2811ba51
AS		 374__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
375 int index)
376{
377 struct ib_gid_attr attr;
378 union ib_gid gid;
379
380 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
381 return 0;
382
383 if (!attr.ndev)
384 return 0;
385
386 dev_put(attr.ndev);
387
388 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
389 return 0;
390
391 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
392}
393
ed88451e
MD		 394int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
395 int index, enum ib_gid_type *gid_type)
396{
397 struct ib_gid_attr attr;
398 union ib_gid gid;
399 int ret;
400
401 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
402 if (ret)
403 return ret;
404
405 if (!attr.ndev)
406 return -ENODEV;
407
408 dev_put(attr.ndev);
409
410 *gid_type = attr.gid_type;
411
412 return 0;
413}
414
1b5daf11
MD		 415static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
416{
7fae6655
NO		 417 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
418 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
419 return 0;
1b5daf11
MD		 420}
421
422enum {
423 MLX5_VPORT_ACCESS_METHOD_MAD,
424 MLX5_VPORT_ACCESS_METHOD_HCA,
425 MLX5_VPORT_ACCESS_METHOD_NIC,
426};
427
428static int mlx5_get_vport_access_method(struct ib_device *ibdev)
429{
430 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
431 return MLX5_VPORT_ACCESS_METHOD_MAD;
432
ebd61f68 433 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 434 IB_LINK_LAYER_ETHERNET)
435 return MLX5_VPORT_ACCESS_METHOD_NIC;
436
437 return MLX5_VPORT_ACCESS_METHOD_HCA;
438}
439
da7525d2
EBE		 440static void get_atomic_caps(struct mlx5_ib_dev *dev,
441 struct ib_device_attr *props)
442{
443 u8 tmp;
444 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
445 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
446 u8 atomic_req_8B_endianness_mode =
bd10838a 447 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 448
449 /* Check if HW supports 8 bytes standard atomic operations and capable
450 * of host endianness respond
451 */
452 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
453 if (((atomic_operations & tmp) == tmp) &&
454 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
455 (atomic_req_8B_endianness_mode)) {
456 props->atomic_cap = IB_ATOMIC_HCA;
457 } else {
458 props->atomic_cap = IB_ATOMIC_NONE;
459 }
460}
461
1b5daf11
MD		 462static int mlx5_query_system_image_guid(struct ib_device *ibdev,
463 __be64 *sys_image_guid)
464{
465 struct mlx5_ib_dev *dev = to_mdev(ibdev);
466 struct mlx5_core_dev *mdev = dev->mdev;
467 u64 tmp;
468 int err;
469
470 switch (mlx5_get_vport_access_method(ibdev)) {
471 case MLX5_VPORT_ACCESS_METHOD_MAD:
472 return mlx5_query_mad_ifc_system_image_guid(ibdev,
473 sys_image_guid);
474
475 case MLX5_VPORT_ACCESS_METHOD_HCA:
476 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 477 break;
478
479 case MLX5_VPORT_ACCESS_METHOD_NIC:
480 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
481 break;
1b5daf11
MD		 482
483 default:
484 return -EINVAL;
485 }
3f89a643
AS		 486
487 if (!err)
488 *sys_image_guid = cpu_to_be64(tmp);
489
490 return err;
491
1b5daf11
MD		 492}
493
494static int mlx5_query_max_pkeys(struct ib_device *ibdev,
495 u16 *max_pkeys)
496{
497 struct mlx5_ib_dev *dev = to_mdev(ibdev);
498 struct mlx5_core_dev *mdev = dev->mdev;
499
500 switch (mlx5_get_vport_access_method(ibdev)) {
501 case MLX5_VPORT_ACCESS_METHOD_MAD:
502 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
503
504 case MLX5_VPORT_ACCESS_METHOD_HCA:
505 case MLX5_VPORT_ACCESS_METHOD_NIC:
506 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
507 pkey_table_size));
508 return 0;
509
510 default:
511 return -EINVAL;
512 }
513}
514
515static int mlx5_query_vendor_id(struct ib_device *ibdev,
516 u32 *vendor_id)
517{
518 struct mlx5_ib_dev *dev = to_mdev(ibdev);
519
520 switch (mlx5_get_vport_access_method(ibdev)) {
521 case MLX5_VPORT_ACCESS_METHOD_MAD:
522 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
523
524 case MLX5_VPORT_ACCESS_METHOD_HCA:
525 case MLX5_VPORT_ACCESS_METHOD_NIC:
526 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
527
528 default:
529 return -EINVAL;
530 }
531}
532
533static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
534 __be64 *node_guid)
535{
536 u64 tmp;
537 int err;
538
539 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
540 case MLX5_VPORT_ACCESS_METHOD_MAD:
541 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
542
543 case MLX5_VPORT_ACCESS_METHOD_HCA:
544 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 545 break;
546
547 case MLX5_VPORT_ACCESS_METHOD_NIC:
548 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
549 break;
1b5daf11
MD		 550
551 default:
552 return -EINVAL;
553 }
3f89a643
AS		 554
555 if (!err)
556 *node_guid = cpu_to_be64(tmp);
557
558 return err;
1b5daf11
MD		 559}
560
561struct mlx5_reg_node_desc {
bd99fdea 562 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 563};
564
565static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
566{
567 struct mlx5_reg_node_desc in;
568
569 if (mlx5_use_mad_ifc(dev))
570 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
571
572 memset(&in, 0, sizeof(in));
573
574 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
575 sizeof(struct mlx5_reg_node_desc),
576 MLX5_REG_NODE_DESC, 0, 0);
577}
578
e126ba97 579static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 580 struct ib_device_attr *props,
581 struct ib_udata *uhw)
e126ba97
EC		 582{
583 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 584 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 585 int err = -ENOMEM;
288c01b7 586 int max_sq_desc;
e126ba97
EC		 587 int max_rq_sg;
588 int max_sq_sg;
e0238a6a 589 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
402ca536
BW		 590 struct mlx5_ib_query_device_resp resp = {};
591 size_t resp_len;
592 u64 max_tso;
e126ba97 593
402ca536
BW		 594 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
595 if (uhw->outlen && uhw->outlen < resp_len)
596 return -EINVAL;
597 else
598 resp.response_length = resp_len;
599
600 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 601 return -EINVAL;
602
1b5daf11
MD		 603 memset(props, 0, sizeof(*props));
604 err = mlx5_query_system_image_guid(ibdev,
605 &props->sys_image_guid);
606 if (err)
607 return err;
e126ba97 608
1b5daf11 609 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 610 if (err)
1b5daf11 611 return err;
e126ba97 612
1b5daf11
MD		 613 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
614 if (err)
615 return err;
e126ba97 616
9603b61d
JM		 617 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
618 (fw_rev_min(dev->mdev) << 16) |
619 fw_rev_sub(dev->mdev);
e126ba97
EC		 620 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
621 IB_DEVICE_PORT_ACTIVE_EVENT |
622 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 623 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 624
625 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 626 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 627 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 628 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 629 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 630 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 631 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 632 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 633 if (MLX5_CAP_GEN(mdev, imaicl)) {
634 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
635 IB_DEVICE_MEM_WINDOW_TYPE_2B;
636 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 637 /* We support 'Gappy' memory registration too */
638 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 639 }
e126ba97 640 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 641 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 642 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
643 /* At this stage no support for signature handover */
644 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
645 IB_PROT_T10DIF_TYPE_2 |
646 IB_PROT_T10DIF_TYPE_3;
647 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
648 IB_GUARD_T10DIF_CSUM;
649 }
938fe83c 650 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 651 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 652
402ca536 653 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
e8161334
NO		 654 if (MLX5_CAP_ETH(mdev, csum_cap)) {
655 /* Legacy bit to support old userspace libraries */
88115fe7 656 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 657 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
658 }
659
660 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
661 props->raw_packet_caps |=
662 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 663
402ca536
BW		 664 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
665 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
666 if (max_tso) {
667 resp.tso_caps.max_tso = 1 << max_tso;
668 resp.tso_caps.supported_qpts |=
669 1 << IB_QPT_RAW_PACKET;
670 resp.response_length += sizeof(resp.tso_caps);
671 }
672 }
31f69a82
YH		 673
674 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
675 resp.rss_caps.rx_hash_function =
676 MLX5_RX_HASH_FUNC_TOEPLITZ;
677 resp.rss_caps.rx_hash_fields_mask =
678 MLX5_RX_HASH_SRC_IPV4 |
679 MLX5_RX_HASH_DST_IPV4 |
680 MLX5_RX_HASH_SRC_IPV6 |
681 MLX5_RX_HASH_DST_IPV6 |
682 MLX5_RX_HASH_SRC_PORT_TCP |
683 MLX5_RX_HASH_DST_PORT_TCP |
684 MLX5_RX_HASH_SRC_PORT_UDP |
685 MLX5_RX_HASH_DST_PORT_UDP;
686 resp.response_length += sizeof(resp.rss_caps);
687 }
688 } else {
689 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
690 resp.response_length += sizeof(resp.tso_caps);
691 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
692 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 693 }
694
f0313965
ES		 695 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
696 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
697 props->device_cap_flags |= IB_DEVICE_UD_TSO;
698 }
699
03404e8a
MG		 700 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
701 MLX5_CAP_GEN(dev->mdev, general_notification_event))
702 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
703
1d54f890
YH		 704 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
705 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
706 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
707
cff5a0f3 708 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
e8161334
NO		 709 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
710 /* Legacy bit to support old userspace libraries */
cff5a0f3 711 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 712 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
713 }
cff5a0f3 714
da6d6ba3
MG		 715 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
716 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
717
1b5daf11
MD		 718 props->vendor_part_id = mdev->pdev->device;
719 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 720
721 props->max_mr_size = ~0ull;
e0238a6a 722 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 723 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
724 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
725 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
726 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 727 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
728 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
729 sizeof(struct mlx5_wqe_raddr_seg)) /
730 sizeof(struct mlx5_wqe_data_seg);
e126ba97 731 props->max_sge = min(max_rq_sg, max_sq_sg);
986ef95e 732 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 733 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 734 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 735 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
736 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
737 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
738 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
739 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
740 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
741 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 742 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 743 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 744 props->max_fast_reg_page_list_len =
745 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
da7525d2 746 get_atomic_caps(dev, props);
81bea28f 747 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 748 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
749 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 750 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
751 props->max_mcast_grp;
752 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 753 props->max_ah = INT_MAX;
7c60bcbb
MB		 754 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
755 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 756
8cdd312c 757#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 758 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 759 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
760 props->odp_caps = dev->odp_caps;
761#endif
762
051f2630
LR		 763 if (MLX5_CAP_GEN(mdev, cd))
764 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
765
eff901d3
EC		 766 if (!mlx5_core_is_pf(mdev))
767 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
768
31f69a82
YH		 769 if (mlx5_ib_port_link_layer(ibdev, 1) ==
770 IB_LINK_LAYER_ETHERNET) {
771 props->rss_caps.max_rwq_indirection_tables =
772 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
773 props->rss_caps.max_rwq_indirection_table_size =
774 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
775 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
776 props->max_wq_type_rq =
777 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
778 }
779
7e43a2a5
BW		 780 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
781 resp.cqe_comp_caps.max_num =
782 MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
783 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
784 resp.cqe_comp_caps.supported_format =
785 MLX5_IB_CQE_RES_FORMAT_HASH |
786 MLX5_IB_CQE_RES_FORMAT_CSUM;
787 resp.response_length += sizeof(resp.cqe_comp_caps);
788 }
789
d949167d
BW		 790 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) {
791 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
792 MLX5_CAP_GEN(mdev, qos)) {
793 resp.packet_pacing_caps.qp_rate_limit_max =
794 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
795 resp.packet_pacing_caps.qp_rate_limit_min =
796 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
797 resp.packet_pacing_caps.supported_qpts |=
798 1 << IB_QPT_RAW_PACKET;
799 }
800 resp.response_length += sizeof(resp.packet_pacing_caps);
801 }
802
9f885201
LR		 803 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
804 uhw->outlen)) {
795b609c
BW		 805 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
806 resp.mlx5_ib_support_multi_pkt_send_wqes =
807 MLX5_IB_ALLOW_MPW;
050da902
BW		 808
809 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
810 resp.mlx5_ib_support_multi_pkt_send_wqes |=
811 MLX5_IB_SUPPORT_EMPW;
812
9f885201
LR		 813 resp.response_length +=
814 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
815 }
816
817 if (field_avail(typeof(resp), reserved, uhw->outlen))
818 resp.response_length += sizeof(resp.reserved);
819
96dc3fc5
NO		 820 if (field_avail(typeof(resp), sw_parsing_caps,
821 uhw->outlen)) {
822 resp.response_length += sizeof(resp.sw_parsing_caps);
823 if (MLX5_CAP_ETH(mdev, swp)) {
824 resp.sw_parsing_caps.sw_parsing_offloads |=
825 MLX5_IB_SW_PARSING;
826
827 if (MLX5_CAP_ETH(mdev, swp_csum))
828 resp.sw_parsing_caps.sw_parsing_offloads |=
829 MLX5_IB_SW_PARSING_CSUM;
830
831 if (MLX5_CAP_ETH(mdev, swp_lso))
832 resp.sw_parsing_caps.sw_parsing_offloads |=
833 MLX5_IB_SW_PARSING_LSO;
834
835 if (resp.sw_parsing_caps.sw_parsing_offloads)
836 resp.sw_parsing_caps.supported_qpts =
837 BIT(IB_QPT_RAW_PACKET);
838 }
839 }
840
402ca536
BW		 841 if (uhw->outlen) {
842 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
843
844 if (err)
845 return err;
846 }
847
1b5daf11 848 return 0;
e126ba97
EC		 849}
850
1b5daf11
MD		 851enum mlx5_ib_width {
852 MLX5_IB_WIDTH_1X = 1 << 0,
853 MLX5_IB_WIDTH_2X = 1 << 1,
854 MLX5_IB_WIDTH_4X = 1 << 2,
855 MLX5_IB_WIDTH_8X = 1 << 3,
856 MLX5_IB_WIDTH_12X = 1 << 4
857};
858
859static int translate_active_width(struct ib_device *ibdev, u8 active_width,
860 u8 *ib_width)
e126ba97
EC		 861{
862 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 863 int err = 0;
864
865 if (active_width & MLX5_IB_WIDTH_1X) {
866 *ib_width = IB_WIDTH_1X;
867 } else if (active_width & MLX5_IB_WIDTH_2X) {
868 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
869 (int)active_width);
870 err = -EINVAL;
871 } else if (active_width & MLX5_IB_WIDTH_4X) {
872 *ib_width = IB_WIDTH_4X;
873 } else if (active_width & MLX5_IB_WIDTH_8X) {
874 *ib_width = IB_WIDTH_8X;
875 } else if (active_width & MLX5_IB_WIDTH_12X) {
876 *ib_width = IB_WIDTH_12X;
877 } else {
878 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
879 (int)active_width);
880 err = -EINVAL;
e126ba97
EC		 881 }
882
1b5daf11
MD		 883 return err;
884}
e126ba97 885
1b5daf11
MD		 886static int mlx5_mtu_to_ib_mtu(int mtu)
887{
888 switch (mtu) {
889 case 256: return 1;
890 case 512: return 2;
891 case 1024: return 3;
892 case 2048: return 4;
893 case 4096: return 5;
894 default:
895 pr_warn("invalid mtu\n");
896 return -1;
e126ba97 897 }
1b5daf11 898}
e126ba97 899
1b5daf11
MD		 900enum ib_max_vl_num {
901 __IB_MAX_VL_0 = 1,
902 __IB_MAX_VL_0_1 = 2,
903 __IB_MAX_VL_0_3 = 3,
904 __IB_MAX_VL_0_7 = 4,
905 __IB_MAX_VL_0_14 = 5,
906};
e126ba97 907
1b5daf11
MD		 908enum mlx5_vl_hw_cap {
909 MLX5_VL_HW_0 = 1,
910 MLX5_VL_HW_0_1 = 2,
911 MLX5_VL_HW_0_2 = 3,
912 MLX5_VL_HW_0_3 = 4,
913 MLX5_VL_HW_0_4 = 5,
914 MLX5_VL_HW_0_5 = 6,
915 MLX5_VL_HW_0_6 = 7,
916 MLX5_VL_HW_0_7 = 8,
917 MLX5_VL_HW_0_14 = 15
918};
e126ba97 919
1b5daf11
MD		 920static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
921 u8 *max_vl_num)
922{
923 switch (vl_hw_cap) {
924 case MLX5_VL_HW_0:
925 *max_vl_num = __IB_MAX_VL_0;
926 break;
927 case MLX5_VL_HW_0_1:
928 *max_vl_num = __IB_MAX_VL_0_1;
929 break;
930 case MLX5_VL_HW_0_3:
931 *max_vl_num = __IB_MAX_VL_0_3;
932 break;
933 case MLX5_VL_HW_0_7:
934 *max_vl_num = __IB_MAX_VL_0_7;
935 break;
936 case MLX5_VL_HW_0_14:
937 *max_vl_num = __IB_MAX_VL_0_14;
938 break;
e126ba97 939
1b5daf11
MD		 940 default:
941 return -EINVAL;
e126ba97 942 }
e126ba97 943
1b5daf11 944 return 0;
e126ba97
EC		 945}
946
1b5daf11
MD		 947static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
948 struct ib_port_attr *props)
e126ba97 949{
1b5daf11
MD		 950 struct mlx5_ib_dev *dev = to_mdev(ibdev);
951 struct mlx5_core_dev *mdev = dev->mdev;
952 struct mlx5_hca_vport_context *rep;
046339ea
SM		 953 u16 max_mtu;
954 u16 oper_mtu;
1b5daf11
MD		 955 int err;
956 u8 ib_link_width_oper;
957 u8 vl_hw_cap;
e126ba97 958
1b5daf11
MD		 959 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
960 if (!rep) {
961 err = -ENOMEM;
e126ba97 962 goto out;
e126ba97 963 }
e126ba97 964
c4550c63 965 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 966
1b5daf11 967 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 968 if (err)
969 goto out;
970
1b5daf11
MD		 971 props->lid = rep->lid;
972 props->lmc = rep->lmc;
973 props->sm_lid = rep->sm_lid;
974 props->sm_sl = rep->sm_sl;
975 props->state = rep->vport_state;
976 props->phys_state = rep->port_physical_state;
977 props->port_cap_flags = rep->cap_mask1;
978 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
979 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
980 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
981 props->bad_pkey_cntr = rep->pkey_violation_counter;
982 props->qkey_viol_cntr = rep->qkey_violation_counter;
983 props->subnet_timeout = rep->subnet_timeout;
984 props->init_type_reply = rep->init_type_reply;
eff901d3 985 props->grh_required = rep->grh_required;
e126ba97 986
1b5daf11
MD		 987 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
988 if (err)
e126ba97 989 goto out;
e126ba97 990
1b5daf11
MD		 991 err = translate_active_width(ibdev, ib_link_width_oper,
992 &props->active_width);
993 if (err)
994 goto out;
d5beb7f2 995 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 996 if (err)
997 goto out;
998
facc9699 999 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 1000
1b5daf11 1001 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 1002
facc9699 1003 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 1004
1b5daf11 1005 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1006
1b5daf11
MD		 1007 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1008 if (err)
1009 goto out;
e126ba97 1010
1b5daf11
MD		 1011 err = translate_max_vl_num(ibdev, vl_hw_cap,
1012 &props->max_vl_num);
e126ba97 1013out:
1b5daf11 1014 kfree(rep);
e126ba97
EC		 1015 return err;
1016}
1017
1b5daf11
MD		 1018int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1019 struct ib_port_attr *props)
e126ba97 1020{
095b0927
IT		 1021 unsigned int count;
1022 int ret;
1023
1b5daf11
MD		 1024 switch (mlx5_get_vport_access_method(ibdev)) {
1025 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1026 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1027 break;
e126ba97 1028
1b5daf11 1029 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1030 ret = mlx5_query_hca_port(ibdev, port, props);
1031 break;
e126ba97 1032
3f89a643 1033 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1034 ret = mlx5_query_port_roce(ibdev, port, props);
1035 break;
3f89a643 1036
1b5daf11 1037 default:
095b0927
IT		 1038 ret = -EINVAL;
1039 }
1040
1041 if (!ret && props) {
1042 count = mlx5_core_reserved_gids_count(to_mdev(ibdev)->mdev);
1043 props->gid_tbl_len -= count;
1b5daf11 1044 }
095b0927 1045 return ret;
1b5daf11 1046}
e126ba97 1047
1b5daf11
MD		 1048static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1049 union ib_gid *gid)
1050{
1051 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1052 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1053
1b5daf11
MD		 1054 switch (mlx5_get_vport_access_method(ibdev)) {
1055 case MLX5_VPORT_ACCESS_METHOD_MAD:
1056 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1057
1b5daf11
MD		 1058 case MLX5_VPORT_ACCESS_METHOD_HCA:
1059 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1060
1061 default:
1062 return -EINVAL;
1063 }
e126ba97 1064
e126ba97
EC		 1065}
1066
1b5daf11
MD		 1067static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1068 u16 *pkey)
1069{
1070 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1071 struct mlx5_core_dev *mdev = dev->mdev;
1072
1073 switch (mlx5_get_vport_access_method(ibdev)) {
1074 case MLX5_VPORT_ACCESS_METHOD_MAD:
1075 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1076
1077 case MLX5_VPORT_ACCESS_METHOD_HCA:
1078 case MLX5_VPORT_ACCESS_METHOD_NIC:
1079 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
1080 pkey);
1081 default:
1082 return -EINVAL;
1083 }
1084}
e126ba97
EC		 1085
1086static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1087 struct ib_device_modify *props)
1088{
1089 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1090 struct mlx5_reg_node_desc in;
1091 struct mlx5_reg_node_desc out;
1092 int err;
1093
1094 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1095 return -EOPNOTSUPP;
1096
1097 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1098 return 0;
1099
1100 /*
1101 * If possible, pass node desc to FW, so it can generate
1102 * a 144 trap. If cmd fails, just ignore.
1103 */
bd99fdea 1104 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1105 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1106 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1107 if (err)
1108 return err;
1109
bd99fdea 1110 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1111
1112 return err;
1113}
1114
cdbe33d0
EC		 1115static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1116 u32 value)
1117{
1118 struct mlx5_hca_vport_context ctx = {};
1119 int err;
1120
1121 err = mlx5_query_hca_vport_context(dev->mdev, 0,
1122 port_num, 0, &ctx);
1123 if (err)
1124 return err;
1125
1126 if (~ctx.cap_mask1_perm & mask) {
1127 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1128 mask, ctx.cap_mask1_perm);
1129 return -EINVAL;
1130 }
1131
1132 ctx.cap_mask1 = value;
1133 ctx.cap_mask1_perm = mask;
1134 err = mlx5_core_modify_hca_vport_context(dev->mdev, 0,
1135 port_num, 0, &ctx);
1136
1137 return err;
1138}
1139
e126ba97
EC		 1140static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1141 struct ib_port_modify *props)
1142{
1143 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1144 struct ib_port_attr attr;
1145 u32 tmp;
1146 int err;
cdbe33d0
EC		 1147 u32 change_mask;
1148 u32 value;
1149 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1150 IB_LINK_LAYER_INFINIBAND);
1151
ec255879
MD		 1152 /* CM layer calls ib_modify_port() regardless of the link layer. For
1153 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1154 */
1155 if (!is_ib)
1156 return 0;
1157
cdbe33d0
EC		 1158 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1159 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1160 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1161 return set_port_caps_atomic(dev, port, change_mask, value);
1162 }
e126ba97
EC		 1163
1164 mutex_lock(&dev->cap_mask_mutex);
1165
c4550c63 1166 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1167 if (err)
1168 goto out;
1169
1170 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1171 ~props->clr_port_cap_mask;
1172
9603b61d 1173 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1174
1175out:
1176 mutex_unlock(&dev->cap_mask_mutex);
1177 return err;
1178}
1179
30aa60b3
EC		 1180static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1181{
1182 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1183 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1184}
1185
b037c29a
EC		 1186static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1187 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1188 u32 *num_sys_pages)
1189{
1190 int uars_per_sys_page;
1191 int bfregs_per_sys_page;
1192 int ref_bfregs = req->total_num_bfregs;
1193
1194 if (req->total_num_bfregs == 0)
1195 return -EINVAL;
1196
1197 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1198 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1199
1200 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1201 return -ENOMEM;
1202
1203 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1204 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1205 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1206 *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1207
1208 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1209 return -EINVAL;
1210
9c2d33d4 1211 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, using %d sys pages\n",
b037c29a
EC		 1212 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1213 lib_uar_4k ? "yes" : "no", ref_bfregs,
1214 req->total_num_bfregs, *num_sys_pages);
1215
1216 return 0;
1217}
1218
1219static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1220{
1221 struct mlx5_bfreg_info *bfregi;
1222 int err;
1223 int i;
1224
1225 bfregi = &context->bfregi;
1226 for (i = 0; i < bfregi->num_sys_pages; i++) {
1227 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1228 if (err)
1229 goto error;
1230
1231 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1232 }
1233 return 0;
1234
1235error:
1236 for (--i; i >= 0; i--)
1237 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1238 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1239
1240 return err;
1241}
1242
1243static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1244{
1245 struct mlx5_bfreg_info *bfregi;
1246 int err;
1247 int i;
1248
1249 bfregi = &context->bfregi;
1250 for (i = 0; i < bfregi->num_sys_pages; i++) {
1251 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1252 if (err) {
1253 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1254 return err;
1255 }
1256 }
1257 return 0;
1258}
1259
c85023e1
HN		 1260static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1261{
1262 int err;
1263
1264 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1265 if (err)
1266 return err;
1267
1268 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1269 !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1270 return err;
1271
1272 mutex_lock(&dev->lb_mutex);
1273 dev->user_td++;
1274
1275 if (dev->user_td == 2)
1276 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1277
1278 mutex_unlock(&dev->lb_mutex);
1279 return err;
1280}
1281
1282static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1283{
1284 mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1285
1286 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1287 !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1288 return;
1289
1290 mutex_lock(&dev->lb_mutex);
1291 dev->user_td--;
1292
1293 if (dev->user_td < 2)
1294 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1295
1296 mutex_unlock(&dev->lb_mutex);
1297}
1298
e126ba97
EC		 1299static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1300 struct ib_udata *udata)
1301{
1302 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1303 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1304 struct mlx5_ib_alloc_ucontext_resp resp = {};
e126ba97 1305 struct mlx5_ib_ucontext *context;
2f5ff264 1306 struct mlx5_bfreg_info *bfregi;
78c0f98c 1307 int ver;
e126ba97 1308 int err;
a168a41c
MD		 1309 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1310 max_cqe_version);
b037c29a 1311 bool lib_uar_4k;
e126ba97
EC		 1312
1313 if (!dev->ib_active)
1314 return ERR_PTR(-EAGAIN);
1315
e093111d 1316 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1317 ver = 0;
e093111d 1318 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1319 ver = 2;
1320 else
1321 return ERR_PTR(-EINVAL);
1322
e093111d 1323 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97
EC		 1324 if (err)
1325 return ERR_PTR(err);
1326
b368d7cb 1327 if (req.flags)
78c0f98c
EC		 1328 return ERR_PTR(-EINVAL);
1329
f72300c5 1330 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 1331 return ERR_PTR(-EOPNOTSUPP);
1332
2f5ff264
EC		 1333 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1334 MLX5_NON_FP_BFREGS_PER_UAR);
1335 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
e126ba97
EC		 1336 return ERR_PTR(-EINVAL);
1337
938fe83c 1338 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1339 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1340 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1341 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1342 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1343 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1344 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1345 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1346 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1347 resp.cqe_version = min_t(__u8,
1348 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1349 req.max_cqe_version);
30aa60b3
EC		 1350 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1351 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1352 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1353 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1354 resp.response_length = min(offsetof(typeof(resp), response_length) +
1355 sizeof(resp.response_length), udata->outlen);
e126ba97
EC		 1356
1357 context = kzalloc(sizeof(*context), GFP_KERNEL);
1358 if (!context)
1359 return ERR_PTR(-ENOMEM);
1360
30aa60b3 1361 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1362 bfregi = &context->bfregi;
b037c29a
EC		 1363
1364 /* updates req->total_num_bfregs */
1365 err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages);
1366 if (err)
e126ba97 1367 goto out_ctx;
e126ba97 1368
b037c29a
EC		 1369 mutex_init(&bfregi->lock);
1370 bfregi->lib_uar_4k = lib_uar_4k;
1371 bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1372 GFP_KERNEL);
b037c29a 1373 if (!bfregi->count) {
e126ba97 1374 err = -ENOMEM;
b037c29a 1375 goto out_ctx;
e126ba97
EC		 1376 }
1377
b037c29a
EC		 1378 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1379 sizeof(*bfregi->sys_pages),
1380 GFP_KERNEL);
1381 if (!bfregi->sys_pages) {
e126ba97 1382 err = -ENOMEM;
b037c29a 1383 goto out_count;
e126ba97
EC		 1384 }
1385
b037c29a
EC		 1386 err = allocate_uars(dev, context);
1387 if (err)
1388 goto out_sys_pages;
e126ba97 1389
b4cfe447
HE		 1390#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1391 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1392#endif
1393
7d0cc6ed
AK		 1394 context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1395 if (!context->upd_xlt_page) {
1396 err = -ENOMEM;
1397 goto out_uars;
1398 }
1399 mutex_init(&context->upd_xlt_page_mutex);
1400
146d2f1a 1401 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
c85023e1 1402 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
146d2f1a 1403 if (err)
7d0cc6ed 1404 goto out_page;
146d2f1a 1405 }
1406
7c2344c3 1407 INIT_LIST_HEAD(&context->vma_private_list);
e126ba97
EC		 1408 INIT_LIST_HEAD(&context->db_page_list);
1409 mutex_init(&context->db_page_mutex);
1410
2f5ff264 1411 resp.tot_bfregs = req.total_num_bfregs;
938fe83c 1412 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
b368d7cb 1413
f72300c5
HA		 1414 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1415 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1416
402ca536 1417 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1418 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1419 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1420 resp.response_length += sizeof(resp.cmds_supp_uhw);
1421 }
1422
78984898
OG		 1423 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1424 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1425 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1426 resp.eth_min_inline++;
1427 }
1428 resp.response_length += sizeof(resp.eth_min_inline);
1429 }
1430
bc5c6eed
NO		 1431 /*
1432 * We don't want to expose information from the PCI bar that is located
1433 * after 4096 bytes, so if the arch only supports larger pages, let's
1434 * pretend we don't support reading the HCA's core clock. This is also
1435 * forced by mmap function.
1436 */
de8d6e02
EC		 1437 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1438 if (PAGE_SIZE <= 4096) {
1439 resp.comp_mask |=
1440 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1441 resp.hca_core_clock_offset =
1442 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1443 }
f72300c5 1444 resp.response_length += sizeof(resp.hca_core_clock_offset) +
402ca536 1445 sizeof(resp.reserved2);
b368d7cb
MB		 1446 }
1447
30aa60b3
EC		 1448 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1449 resp.response_length += sizeof(resp.log_uar_size);
1450
1451 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1452 resp.response_length += sizeof(resp.num_uars_per_page);
1453
b368d7cb 1454 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1455 if (err)
146d2f1a 1456 goto out_td;
e126ba97 1457
2f5ff264
EC		 1458 bfregi->ver = ver;
1459 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1460 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1461 context->lib_caps = req.lib_caps;
1462 print_lib_caps(dev, context->lib_caps);
f72300c5 1463
e126ba97
EC		 1464 return &context->ibucontext;
1465
146d2f1a 1466out_td:
1467 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
c85023e1 1468 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1469
7d0cc6ed
AK		 1470out_page:
1471 free_page(context->upd_xlt_page);
1472
e126ba97 1473out_uars:
b037c29a 1474 deallocate_uars(dev, context);
e126ba97 1475
b037c29a
EC		 1476out_sys_pages:
1477 kfree(bfregi->sys_pages);
e126ba97 1478
b037c29a
EC		 1479out_count:
1480 kfree(bfregi->count);
e126ba97
EC		 1481
1482out_ctx:
1483 kfree(context);
b037c29a 1484
e126ba97
EC		 1485 return ERR_PTR(err);
1486}
1487
1488static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1489{
1490 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1491 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 1492 struct mlx5_bfreg_info *bfregi;
e126ba97 1493
b037c29a 1494 bfregi = &context->bfregi;
146d2f1a 1495 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
c85023e1 1496 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1497
7d0cc6ed 1498 free_page(context->upd_xlt_page);
b037c29a
EC		 1499 deallocate_uars(dev, context);
1500 kfree(bfregi->sys_pages);
2f5ff264 1501 kfree(bfregi->count);
e126ba97
EC		 1502 kfree(context);
1503
1504 return 0;
1505}
1506
b037c29a
EC		 1507static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1508 struct mlx5_bfreg_info *bfregi,
1509 int idx)
e126ba97 1510{
b037c29a
EC		 1511 int fw_uars_per_page;
1512
1513 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1514
1515 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) +
1516 bfregi->sys_pages[idx] / fw_uars_per_page;
e126ba97
EC		 1517}
1518
1519static int get_command(unsigned long offset)
1520{
1521 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1522}
1523
1524static int get_arg(unsigned long offset)
1525{
1526 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1527}
1528
1529static int get_index(unsigned long offset)
1530{
1531 return get_arg(offset);
1532}
1533
7c2344c3
MG		 1534static void mlx5_ib_vma_open(struct vm_area_struct *area)
1535{
1536 /* vma_open is called when a new VMA is created on top of our VMA. This
1537 * is done through either mremap flow or split_vma (usually due to
1538 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1539 * as this VMA is strongly hardware related. Therefore we set the
1540 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1541 * calling us again and trying to do incorrect actions. We assume that
1542 * the original VMA size is exactly a single page, and therefore all
1543 * "splitting" operation will not happen to it.
1544 */
1545 area->vm_ops = NULL;
1546}
1547
1548static void mlx5_ib_vma_close(struct vm_area_struct *area)
1549{
1550 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1551
1552 /* It's guaranteed that all VMAs opened on a FD are closed before the
1553 * file itself is closed, therefore no sync is needed with the regular
1554 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1555 * However need a sync with accessing the vma as part of
1556 * mlx5_ib_disassociate_ucontext.
1557 * The close operation is usually called under mm->mmap_sem except when
1558 * process is exiting.
1559 * The exiting case is handled explicitly as part of
1560 * mlx5_ib_disassociate_ucontext.
1561 */
1562 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1563
1564 /* setting the vma context pointer to null in the mlx5_ib driver's
1565 * private data, to protect a race condition in
1566 * mlx5_ib_disassociate_ucontext().
1567 */
1568 mlx5_ib_vma_priv_data->vma = NULL;
1569 list_del(&mlx5_ib_vma_priv_data->list);
1570 kfree(mlx5_ib_vma_priv_data);
1571}
1572
1573static const struct vm_operations_struct mlx5_ib_vm_ops = {
1574 .open = mlx5_ib_vma_open,
1575 .close = mlx5_ib_vma_close
1576};
1577
1578static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1579 struct mlx5_ib_ucontext *ctx)
1580{
1581 struct mlx5_ib_vma_private_data *vma_prv;
1582 struct list_head *vma_head = &ctx->vma_private_list;
1583
1584 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1585 if (!vma_prv)
1586 return -ENOMEM;
1587
1588 vma_prv->vma = vma;
1589 vma->vm_private_data = vma_prv;
1590 vma->vm_ops = &mlx5_ib_vm_ops;
1591
1592 list_add(&vma_prv->list, vma_head);
1593
1594 return 0;
1595}
1596
1597static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1598{
1599 int ret;
1600 struct vm_area_struct *vma;
1601 struct mlx5_ib_vma_private_data *vma_private, *n;
1602 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1603 struct task_struct *owning_process = NULL;
1604 struct mm_struct *owning_mm = NULL;
1605
1606 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1607 if (!owning_process)
1608 return;
1609
1610 owning_mm = get_task_mm(owning_process);
1611 if (!owning_mm) {
1612 pr_info("no mm, disassociate ucontext is pending task termination\n");
1613 while (1) {
1614 put_task_struct(owning_process);
1615 usleep_range(1000, 2000);
1616 owning_process = get_pid_task(ibcontext->tgid,
1617 PIDTYPE_PID);
1618 if (!owning_process ||
1619 owning_process->state == TASK_DEAD) {
1620 pr_info("disassociate ucontext done, task was terminated\n");
1621 /* in case task was dead need to release the
1622 * task struct.
1623 */
1624 if (owning_process)
1625 put_task_struct(owning_process);
1626 return;
1627 }
1628 }
1629 }
1630
1631 /* need to protect from a race on closing the vma as part of
1632 * mlx5_ib_vma_close.
1633 */
ecc7d83b 1634 down_write(&owning_mm->mmap_sem);
7c2344c3
MG		 1635 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1636 list) {
1637 vma = vma_private->vma;
1638 ret = zap_vma_ptes(vma, vma->vm_start,
1639 PAGE_SIZE);
1640 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1641 /* context going to be destroyed, should
1642 * not access ops any more.
1643 */
13776612 1644 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
7c2344c3
MG		 1645 vma->vm_ops = NULL;
1646 list_del(&vma_private->list);
1647 kfree(vma_private);
1648 }
ecc7d83b 1649 up_write(&owning_mm->mmap_sem);
7c2344c3
MG		 1650 mmput(owning_mm);
1651 put_task_struct(owning_process);
1652}
1653
37aa5c36
GL		 1654static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1655{
1656 switch (cmd) {
1657 case MLX5_IB_MMAP_WC_PAGE:
1658 return "WC";
1659 case MLX5_IB_MMAP_REGULAR_PAGE:
1660 return "best effort WC";
1661 case MLX5_IB_MMAP_NC_PAGE:
1662 return "NC";
1663 default:
1664 return NULL;
1665 }
1666}
1667
1668static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 1669 struct vm_area_struct *vma,
1670 struct mlx5_ib_ucontext *context)
37aa5c36 1671{
2f5ff264 1672 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 1673 int err;
1674 unsigned long idx;
1675 phys_addr_t pfn, pa;
1676 pgprot_t prot;
b037c29a
EC		 1677 int uars_per_page;
1678
1679 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1680 return -EINVAL;
1681
1682 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
1683 idx = get_index(vma->vm_pgoff);
1684 if (idx % uars_per_page ||
1685 idx * uars_per_page >= bfregi->num_sys_pages) {
1686 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx);
1687 return -EINVAL;
1688 }
37aa5c36
GL		 1689
1690 switch (cmd) {
1691 case MLX5_IB_MMAP_WC_PAGE:
1692/* Some architectures don't support WC memory */
1693#if defined(CONFIG_X86)
1694 if (!pat_enabled())
1695 return -EPERM;
1696#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1697 return -EPERM;
1698#endif
1699 /* fall through */
1700 case MLX5_IB_MMAP_REGULAR_PAGE:
1701 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1702 prot = pgprot_writecombine(vma->vm_page_prot);
1703 break;
1704 case MLX5_IB_MMAP_NC_PAGE:
1705 prot = pgprot_noncached(vma->vm_page_prot);
1706 break;
1707 default:
1708 return -EINVAL;
1709 }
1710
b037c29a 1711 pfn = uar_index2pfn(dev, bfregi, idx);
37aa5c36
GL		 1712 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1713
1714 vma->vm_page_prot = prot;
1715 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1716 PAGE_SIZE, vma->vm_page_prot);
1717 if (err) {
1718 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1719 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1720 return -EAGAIN;
1721 }
1722
1723 pa = pfn << PAGE_SHIFT;
1724 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1725 vma->vm_start, &pa);
1726
7c2344c3 1727 return mlx5_ib_set_vma_data(vma, context);
37aa5c36
GL		 1728}
1729
e126ba97
EC		 1730static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1731{
1732 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1733 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 1734 unsigned long command;
e126ba97
EC		 1735 phys_addr_t pfn;
1736
1737 command = get_command(vma->vm_pgoff);
1738 switch (command) {
37aa5c36
GL		 1739 case MLX5_IB_MMAP_WC_PAGE:
1740 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 1741 case MLX5_IB_MMAP_REGULAR_PAGE:
7c2344c3 1742 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 1743
1744 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1745 return -ENOSYS;
1746
d69e3bcf 1747 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 1748 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1749 return -EINVAL;
1750
6cbac1e4 1751 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 1752 return -EPERM;
1753
1754 /* Don't expose to user-space information it shouldn't have */
1755 if (PAGE_SIZE > 4096)
1756 return -EOPNOTSUPP;
1757
1758 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1759 pfn = (dev->mdev->iseg_base +
1760 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1761 PAGE_SHIFT;
1762 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1763 PAGE_SIZE, vma->vm_page_prot))
1764 return -EAGAIN;
1765
1766 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1767 vma->vm_start,
1768 (unsigned long long)pfn << PAGE_SHIFT);
1769 break;
d69e3bcf 1770
e126ba97
EC		 1771 default:
1772 return -EINVAL;
1773 }
1774
1775 return 0;
1776}
1777
e126ba97
EC		 1778static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1779 struct ib_ucontext *context,
1780 struct ib_udata *udata)
1781{
1782 struct mlx5_ib_alloc_pd_resp resp;
1783 struct mlx5_ib_pd *pd;
1784 int err;
1785
1786 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1787 if (!pd)
1788 return ERR_PTR(-ENOMEM);
1789
9603b61d 1790 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 1791 if (err) {
1792 kfree(pd);
1793 return ERR_PTR(err);
1794 }
1795
1796 if (context) {
1797 resp.pdn = pd->pdn;
1798 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 1799 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 1800 kfree(pd);
1801 return ERR_PTR(-EFAULT);
1802 }
e126ba97
EC		 1803 }
1804
1805 return &pd->ibpd;
1806}
1807
1808static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1809{
1810 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1811 struct mlx5_ib_pd *mpd = to_mpd(pd);
1812
9603b61d 1813 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 1814 kfree(mpd);
1815
1816 return 0;
1817}
1818
466fa6d2
MG		 1819enum {
1820 MATCH_CRITERIA_ENABLE_OUTER_BIT,
1821 MATCH_CRITERIA_ENABLE_MISC_BIT,
1822 MATCH_CRITERIA_ENABLE_INNER_BIT
1823};
1824
1825#define HEADER_IS_ZERO(match_criteria, headers) \
1826 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1827 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 1828
466fa6d2 1829static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 1830{
466fa6d2 1831 u8 match_criteria_enable;
038d2ef8 1832
466fa6d2
MG		 1833 match_criteria_enable =
1834 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1835 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1836 match_criteria_enable |=
1837 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1838 MATCH_CRITERIA_ENABLE_MISC_BIT;
1839 match_criteria_enable |=
1840 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1841 MATCH_CRITERIA_ENABLE_INNER_BIT;
1842
1843 return match_criteria_enable;
038d2ef8
MG		 1844}
1845
ca0d4753
MG		 1846static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1847{
1848 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1849 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
038d2ef8
MG		 1850}
1851
2d1e697e
MR		 1852static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
1853 bool inner)
1854{
1855 if (inner) {
1856 MLX5_SET(fte_match_set_misc,
1857 misc_c, inner_ipv6_flow_label, mask);
1858 MLX5_SET(fte_match_set_misc,
1859 misc_v, inner_ipv6_flow_label, val);
1860 } else {
1861 MLX5_SET(fte_match_set_misc,
1862 misc_c, outer_ipv6_flow_label, mask);
1863 MLX5_SET(fte_match_set_misc,
1864 misc_v, outer_ipv6_flow_label, val);
1865 }
1866}
1867
ca0d4753
MG		 1868static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1869{
1870 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1871 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1872 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1873 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1874}
1875
c47ac6ae
MG		 1876#define LAST_ETH_FIELD vlan_tag
1877#define LAST_IB_FIELD sl
ca0d4753 1878#define LAST_IPV4_FIELD tos
466fa6d2 1879#define LAST_IPV6_FIELD traffic_class
c47ac6ae 1880#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 1881#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 1882#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 1883#define LAST_DROP_FIELD size
c47ac6ae
MG		 1884
1885/* Field is the last supported field */
1886#define FIELDS_NOT_SUPPORTED(filter, field)\
1887 memchr_inv((void *)&filter.field +\
1888 sizeof(filter.field), 0,\
1889 sizeof(filter) -\
1890 offsetof(typeof(filter), field) -\
1891 sizeof(filter.field))
1892
19cc7524
AL		 1893#define IPV4_VERSION 4
1894#define IPV6_VERSION 6
1895static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
1896 u32 *match_v, const union ib_flow_spec *ib_spec,
a22ed86c 1897 u32 *tag_id, bool *is_drop)
038d2ef8 1898{
466fa6d2
MG		 1899 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1900 misc_parameters);
1901 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1902 misc_parameters);
2d1e697e
MR		 1903 void *headers_c;
1904 void *headers_v;
19cc7524 1905 int match_ipv;
2d1e697e
MR		 1906
1907 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
1908 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1909 inner_headers);
1910 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1911 inner_headers);
19cc7524
AL		 1912 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1913 ft_field_support.inner_ip_version);
2d1e697e
MR		 1914 } else {
1915 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1916 outer_headers);
1917 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1918 outer_headers);
19cc7524
AL		 1919 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1920 ft_field_support.outer_ip_version);
2d1e697e 1921 }
466fa6d2 1922
2d1e697e 1923 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 1924 case IB_FLOW_SPEC_ETH:
c47ac6ae 1925 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 1926 return -EOPNOTSUPP;
038d2ef8 1927
2d1e697e 1928 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1929 dmac_47_16),
1930 ib_spec->eth.mask.dst_mac);
2d1e697e 1931 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1932 dmac_47_16),
1933 ib_spec->eth.val.dst_mac);
1934
2d1e697e 1935 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 1936 smac_47_16),
1937 ib_spec->eth.mask.src_mac);
2d1e697e 1938 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 1939 smac_47_16),
1940 ib_spec->eth.val.src_mac);
1941
038d2ef8 1942 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 1943 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 1944 cvlan_tag, 1);
2d1e697e 1945 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 1946 cvlan_tag, 1);
038d2ef8 1947
2d1e697e 1948 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 1949 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 1950 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1951 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1952
2d1e697e 1953 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1954 first_cfi,
1955 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 1956 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1957 first_cfi,
1958 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1959
2d1e697e 1960 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1961 first_prio,
1962 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 1963 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1964 first_prio,
1965 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1966 }
2d1e697e 1967 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 1968 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 1969 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1970 ethertype, ntohs(ib_spec->eth.val.ether_type));
1971 break;
1972 case IB_FLOW_SPEC_IPV4:
c47ac6ae 1973 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 1974 return -EOPNOTSUPP;
038d2ef8 1975
19cc7524
AL		 1976 if (match_ipv) {
1977 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1978 ip_version, 0xf);
1979 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1980 ip_version, IPV4_VERSION);
1981 } else {
1982 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1983 ethertype, 0xffff);
1984 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1985 ethertype, ETH_P_IP);
1986 }
038d2ef8 1987
2d1e697e 1988 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1989 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1990 &ib_spec->ipv4.mask.src_ip,
1991 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 1992 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1993 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1994 &ib_spec->ipv4.val.src_ip,
1995 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 1996 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1997 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1998 &ib_spec->ipv4.mask.dst_ip,
1999 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 2000 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2001 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2002 &ib_spec->ipv4.val.dst_ip,
2003 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 2004
2d1e697e 2005 set_tos(headers_c, headers_v,
ca0d4753
MG		 2006 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2007
2d1e697e 2008 set_proto(headers_c, headers_v,
ca0d4753 2009 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
038d2ef8 2010 break;
026bae0c 2011 case IB_FLOW_SPEC_IPV6:
c47ac6ae 2012 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 2013 return -EOPNOTSUPP;
026bae0c 2014
19cc7524
AL		 2015 if (match_ipv) {
2016 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2017 ip_version, 0xf);
2018 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2019 ip_version, IPV6_VERSION);
2020 } else {
2021 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2022 ethertype, 0xffff);
2023 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2024 ethertype, ETH_P_IPV6);
2025 }
026bae0c 2026
2d1e697e 2027 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2028 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2029 &ib_spec->ipv6.mask.src_ip,
2030 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2031 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2032 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2033 &ib_spec->ipv6.val.src_ip,
2034 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2035 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2036 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2037 &ib_spec->ipv6.mask.dst_ip,
2038 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2039 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2040 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2041 &ib_spec->ipv6.val.dst_ip,
2042 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2043
2d1e697e 2044 set_tos(headers_c, headers_v,
466fa6d2
MG		 2045 ib_spec->ipv6.mask.traffic_class,
2046 ib_spec->ipv6.val.traffic_class);
2047
2d1e697e 2048 set_proto(headers_c, headers_v,
466fa6d2
MG		 2049 ib_spec->ipv6.mask.next_hdr,
2050 ib_spec->ipv6.val.next_hdr);
2051
2d1e697e
MR		 2052 set_flow_label(misc_params_c, misc_params_v,
2053 ntohl(ib_spec->ipv6.mask.flow_label),
2054 ntohl(ib_spec->ipv6.val.flow_label),
2055 ib_spec->type & IB_FLOW_SPEC_INNER);
2056
026bae0c 2057 break;
038d2ef8 2058 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2059 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2060 LAST_TCP_UDP_FIELD))
1ffd3a26 2061 return -EOPNOTSUPP;
038d2ef8 2062
2d1e697e 2063 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2064 0xff);
2d1e697e 2065 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2066 IPPROTO_TCP);
2067
2d1e697e 2068 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2069 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2070 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2071 ntohs(ib_spec->tcp_udp.val.src_port));
2072
2d1e697e 2073 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2074 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2075 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2076 ntohs(ib_spec->tcp_udp.val.dst_port));
2077 break;
2078 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2079 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2080 LAST_TCP_UDP_FIELD))
1ffd3a26 2081 return -EOPNOTSUPP;
038d2ef8 2082
2d1e697e 2083 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2084 0xff);
2d1e697e 2085 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2086 IPPROTO_UDP);
2087
2d1e697e 2088 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2089 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2090 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2091 ntohs(ib_spec->tcp_udp.val.src_port));
2092
2d1e697e 2093 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2094 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2095 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2096 ntohs(ib_spec->tcp_udp.val.dst_port));
2097 break;
ffb30d8f
MR		 2098 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2099 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2100 LAST_TUNNEL_FIELD))
1ffd3a26 2101 return -EOPNOTSUPP;
ffb30d8f
MR		 2102
2103 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2104 ntohl(ib_spec->tunnel.mask.tunnel_id));
2105 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2106 ntohl(ib_spec->tunnel.val.tunnel_id));
2107 break;
2ac693f9
MR		 2108 case IB_FLOW_SPEC_ACTION_TAG:
2109 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2110 LAST_FLOW_TAG_FIELD))
2111 return -EOPNOTSUPP;
2112 if (ib_spec->flow_tag.tag_id >= BIT(24))
2113 return -EINVAL;
2114
2115 *tag_id = ib_spec->flow_tag.tag_id;
2116 break;
a22ed86c
SS		 2117 case IB_FLOW_SPEC_ACTION_DROP:
2118 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2119 LAST_DROP_FIELD))
2120 return -EOPNOTSUPP;
2121 *is_drop = true;
2122 break;
038d2ef8
MG		 2123 default:
2124 return -EINVAL;
2125 }
2126
2127 return 0;
2128}
2129
2130/* If a flow could catch both multicast and unicast packets,
2131 * it won't fall into the multicast flow steering table and this rule
2132 * could steal other multicast packets.
2133 */
a550ddfc 2134static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
038d2ef8 2135{
81e30880 2136 union ib_flow_spec *flow_spec;
038d2ef8
MG		 2137
2138 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 2139 ib_attr->num_of_specs < 1)
2140 return false;
2141
81e30880
YH		 2142 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2143 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2144 struct ib_flow_spec_ipv4 *ipv4_spec;
2145
2146 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2147 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2148 return true;
2149
038d2ef8 2150 return false;
81e30880
YH		 2151 }
2152
2153 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2154 struct ib_flow_spec_eth *eth_spec;
2155
2156 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2157 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2158 is_multicast_ether_addr(eth_spec->val.dst_mac);
2159 }
038d2ef8 2160
81e30880 2161 return false;
038d2ef8
MG		 2162}
2163
19cc7524
AL		 2164static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2165 const struct ib_flow_attr *flow_attr,
0f750966 2166 bool check_inner)
038d2ef8
MG		 2167{
2168 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 2169 int match_ipv = check_inner ?
2170 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2171 ft_field_support.inner_ip_version) :
2172 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2173 ft_field_support.outer_ip_version);
0f750966
AL		 2174 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2175 bool ipv4_spec_valid, ipv6_spec_valid;
2176 unsigned int ip_spec_type = 0;
2177 bool has_ethertype = false;
038d2ef8 2178 unsigned int spec_index;
0f750966
AL		 2179 bool mask_valid = true;
2180 u16 eth_type = 0;
2181 bool type_valid;
038d2ef8
MG		 2182
2183 /* Validate that ethertype is correct */
2184 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 2185 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 2186 ib_spec->eth.mask.ether_type) {
0f750966
AL		 2187 mask_valid = (ib_spec->eth.mask.ether_type ==
2188 htons(0xffff));
2189 has_ethertype = true;
2190 eth_type = ntohs(ib_spec->eth.val.ether_type);
2191 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2192 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2193 ip_spec_type = ib_spec->type;
038d2ef8
MG		 2194 }
2195 ib_spec = (void *)ib_spec + ib_spec->size;
2196 }
0f750966
AL		 2197
2198 type_valid = (!has_ethertype) || (!ip_spec_type);
2199 if (!type_valid && mask_valid) {
2200 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2201 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2202 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2203 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 2204
2205 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2206 (((eth_type == ETH_P_MPLS_UC) ||
2207 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 2208 }
2209
2210 return type_valid;
2211}
2212
19cc7524
AL		 2213static bool is_valid_attr(struct mlx5_core_dev *mdev,
2214 const struct ib_flow_attr *flow_attr)
0f750966 2215{
19cc7524
AL		 2216 return is_valid_ethertype(mdev, flow_attr, false) &&
2217 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 2218}
2219
2220static void put_flow_table(struct mlx5_ib_dev *dev,
2221 struct mlx5_ib_flow_prio *prio, bool ft_added)
2222{
2223 prio->refcount -= !!ft_added;
2224 if (!prio->refcount) {
2225 mlx5_destroy_flow_table(prio->flow_table);
2226 prio->flow_table = NULL;
2227 }
2228}
2229
2230static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2231{
2232 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2233 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2234 struct mlx5_ib_flow_handler,
2235 ibflow);
2236 struct mlx5_ib_flow_handler *iter, *tmp;
2237
2238 mutex_lock(&dev->flow_db.lock);
2239
2240 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 2241 mlx5_del_flow_rules(iter->rule);
cc0e5d42 2242 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 2243 list_del(&iter->list);
2244 kfree(iter);
2245 }
2246
74491de9 2247 mlx5_del_flow_rules(handler->rule);
5497adc6 2248 put_flow_table(dev, handler->prio, true);
038d2ef8
MG		 2249 mutex_unlock(&dev->flow_db.lock);
2250
2251 kfree(handler);
2252
2253 return 0;
2254}
2255
35d19011
MG		 2256static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2257{
2258 priority *= 2;
2259 if (!dont_trap)
2260 priority++;
2261 return priority;
2262}
2263
cc0e5d42
MG		 2264enum flow_table_type {
2265 MLX5_IB_FT_RX,
2266 MLX5_IB_FT_TX
2267};
2268
00b7c2ab
MG		 2269#define MLX5_FS_MAX_TYPES 6
2270#define MLX5_FS_MAX_ENTRIES BIT(16)
038d2ef8 2271static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 2272 struct ib_flow_attr *flow_attr,
2273 enum flow_table_type ft_type)
038d2ef8 2274{
35d19011 2275 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 2276 struct mlx5_flow_namespace *ns = NULL;
2277 struct mlx5_ib_flow_prio *prio;
2278 struct mlx5_flow_table *ft;
dac388ef 2279 int max_table_size;
038d2ef8
MG		 2280 int num_entries;
2281 int num_groups;
2282 int priority;
2283 int err = 0;
2284
dac388ef
MG		 2285 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2286 log_max_ft_size));
038d2ef8 2287 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2288 if (flow_is_multicast_only(flow_attr) &&
2289 !dont_trap)
038d2ef8
MG		 2290 priority = MLX5_IB_FLOW_MCAST_PRIO;
2291 else
35d19011
MG		 2292 priority = ib_prio_to_core_prio(flow_attr->priority,
2293 dont_trap);
038d2ef8
MG		 2294 ns = mlx5_get_flow_namespace(dev->mdev,
2295 MLX5_FLOW_NAMESPACE_BYPASS);
2296 num_entries = MLX5_FS_MAX_ENTRIES;
2297 num_groups = MLX5_FS_MAX_TYPES;
2298 prio = &dev->flow_db.prios[priority];
2299 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2300 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2301 ns = mlx5_get_flow_namespace(dev->mdev,
2302 MLX5_FLOW_NAMESPACE_LEFTOVERS);
2303 build_leftovers_ft_param(&priority,
2304 &num_entries,
2305 &num_groups);
2306 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 2307 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2308 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2309 allow_sniffer_and_nic_rx_shared_tir))
2310 return ERR_PTR(-ENOTSUPP);
2311
2312 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2313 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2314 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2315
2316 prio = &dev->flow_db.sniffer[ft_type];
2317 priority = 0;
2318 num_entries = 1;
2319 num_groups = 1;
038d2ef8
MG		 2320 }
2321
2322 if (!ns)
2323 return ERR_PTR(-ENOTSUPP);
2324
dac388ef
MG		 2325 if (num_entries > max_table_size)
2326 return ERR_PTR(-ENOMEM);
2327
038d2ef8
MG		 2328 ft = prio->flow_table;
2329 if (!ft) {
2330 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2331 num_entries,
d63cd286 2332 num_groups,
c9f1b073 2333 0, 0);
038d2ef8
MG		 2334
2335 if (!IS_ERR(ft)) {
2336 prio->refcount = 0;
2337 prio->flow_table = ft;
2338 } else {
2339 err = PTR_ERR(ft);
2340 }
2341 }
2342
2343 return err ? ERR_PTR(err) : prio;
2344}
2345
a550ddfc
YH		 2346static void set_underlay_qp(struct mlx5_ib_dev *dev,
2347 struct mlx5_flow_spec *spec,
2348 u32 underlay_qpn)
2349{
2350 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
2351 spec->match_criteria,
2352 misc_parameters);
2353 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2354 misc_parameters);
2355
2356 if (underlay_qpn &&
2357 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2358 ft_field_support.bth_dst_qp)) {
2359 MLX5_SET(fte_match_set_misc,
2360 misc_params_v, bth_dst_qp, underlay_qpn);
2361 MLX5_SET(fte_match_set_misc,
2362 misc_params_c, bth_dst_qp, 0xffffff);
2363 }
2364}
2365
2366static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
2367 struct mlx5_ib_flow_prio *ft_prio,
2368 const struct ib_flow_attr *flow_attr,
2369 struct mlx5_flow_destination *dst,
2370 u32 underlay_qpn)
038d2ef8
MG		 2371{
2372 struct mlx5_flow_table *ft = ft_prio->flow_table;
2373 struct mlx5_ib_flow_handler *handler;
66958ed9 2374 struct mlx5_flow_act flow_act = {0};
c5bb1730 2375 struct mlx5_flow_spec *spec;
a22ed86c 2376 struct mlx5_flow_destination *rule_dst = dst;
dd063d0e 2377 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 2378 unsigned int spec_index;
2ac693f9 2379 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
a22ed86c 2380 bool is_drop = false;
038d2ef8 2381 int err = 0;
a22ed86c 2382 int dest_num = 1;
038d2ef8 2383
19cc7524 2384 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 2385 return ERR_PTR(-EINVAL);
2386
1b9a07ee 2387 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 2388 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 2389 if (!handler || !spec) {
038d2ef8
MG		 2390 err = -ENOMEM;
2391 goto free;
2392 }
2393
2394 INIT_LIST_HEAD(&handler->list);
2395
2396 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
19cc7524 2397 err = parse_flow_attr(dev->mdev, spec->match_criteria,
a22ed86c
SS		 2398 spec->match_value,
2399 ib_flow, &flow_tag, &is_drop);
038d2ef8
MG		 2400 if (err < 0)
2401 goto free;
2402
2403 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2404 }
2405
a550ddfc
YH		 2406 if (!flow_is_multicast_only(flow_attr))
2407 set_underlay_qp(dev, spec, underlay_qpn);
2408
466fa6d2 2409 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
a22ed86c
SS		 2410 if (is_drop) {
2411 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2412 rule_dst = NULL;
2413 dest_num = 0;
2414 } else {
2415 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2416 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2417 }
2ac693f9
MR		 2418
2419 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG &&
2420 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2421 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
2422 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
2423 flow_tag, flow_attr->type);
2424 err = -EINVAL;
2425 goto free;
2426 }
2427 flow_act.flow_tag = flow_tag;
74491de9 2428 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 2429 &flow_act,
a22ed86c 2430 rule_dst, dest_num);
038d2ef8
MG		 2431
2432 if (IS_ERR(handler->rule)) {
2433 err = PTR_ERR(handler->rule);
2434 goto free;
2435 }
2436
d9d4980a 2437 ft_prio->refcount++;
5497adc6 2438 handler->prio = ft_prio;
038d2ef8
MG		 2439
2440 ft_prio->flow_table = ft;
2441free:
2442 if (err)
2443 kfree(handler);
c5bb1730 2444 kvfree(spec);
038d2ef8
MG		 2445 return err ? ERR_PTR(err) : handler;
2446}
2447
a550ddfc
YH		 2448static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2449 struct mlx5_ib_flow_prio *ft_prio,
2450 const struct ib_flow_attr *flow_attr,
2451 struct mlx5_flow_destination *dst)
2452{
2453 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0);
2454}
2455
35d19011
MG		 2456static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2457 struct mlx5_ib_flow_prio *ft_prio,
2458 struct ib_flow_attr *flow_attr,
2459 struct mlx5_flow_destination *dst)
2460{
2461 struct mlx5_ib_flow_handler *handler_dst = NULL;
2462 struct mlx5_ib_flow_handler *handler = NULL;
2463
2464 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2465 if (!IS_ERR(handler)) {
2466 handler_dst = create_flow_rule(dev, ft_prio,
2467 flow_attr, dst);
2468 if (IS_ERR(handler_dst)) {
74491de9 2469 mlx5_del_flow_rules(handler->rule);
d9d4980a 2470 ft_prio->refcount--;
35d19011
MG		 2471 kfree(handler);
2472 handler = handler_dst;
2473 } else {
2474 list_add(&handler_dst->list, &handler->list);
2475 }
2476 }
2477
2478 return handler;
2479}
038d2ef8
MG		 2480enum {
2481 LEFTOVERS_MC,
2482 LEFTOVERS_UC,
2483};
2484
2485static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2486 struct mlx5_ib_flow_prio *ft_prio,
2487 struct ib_flow_attr *flow_attr,
2488 struct mlx5_flow_destination *dst)
2489{
2490 struct mlx5_ib_flow_handler *handler_ucast = NULL;
2491 struct mlx5_ib_flow_handler *handler = NULL;
2492
2493 static struct {
2494 struct ib_flow_attr flow_attr;
2495 struct ib_flow_spec_eth eth_flow;
2496 } leftovers_specs[] = {
2497 [LEFTOVERS_MC] = {
2498 .flow_attr = {
2499 .num_of_specs = 1,
2500 .size = sizeof(leftovers_specs[0])
2501 },
2502 .eth_flow = {
2503 .type = IB_FLOW_SPEC_ETH,
2504 .size = sizeof(struct ib_flow_spec_eth),
2505 .mask = {.dst_mac = {0x1} },
2506 .val = {.dst_mac = {0x1} }
2507 }
2508 },
2509 [LEFTOVERS_UC] = {
2510 .flow_attr = {
2511 .num_of_specs = 1,
2512 .size = sizeof(leftovers_specs[0])
2513 },
2514 .eth_flow = {
2515 .type = IB_FLOW_SPEC_ETH,
2516 .size = sizeof(struct ib_flow_spec_eth),
2517 .mask = {.dst_mac = {0x1} },
2518 .val = {.dst_mac = {} }
2519 }
2520 }
2521 };
2522
2523 handler = create_flow_rule(dev, ft_prio,
2524 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2525 dst);
2526 if (!IS_ERR(handler) &&
2527 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2528 handler_ucast = create_flow_rule(dev, ft_prio,
2529 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2530 dst);
2531 if (IS_ERR(handler_ucast)) {
74491de9 2532 mlx5_del_flow_rules(handler->rule);
d9d4980a 2533 ft_prio->refcount--;
038d2ef8
MG		 2534 kfree(handler);
2535 handler = handler_ucast;
2536 } else {
2537 list_add(&handler_ucast->list, &handler->list);
2538 }
2539 }
2540
2541 return handler;
2542}
2543
cc0e5d42
MG		 2544static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2545 struct mlx5_ib_flow_prio *ft_rx,
2546 struct mlx5_ib_flow_prio *ft_tx,
2547 struct mlx5_flow_destination *dst)
2548{
2549 struct mlx5_ib_flow_handler *handler_rx;
2550 struct mlx5_ib_flow_handler *handler_tx;
2551 int err;
2552 static const struct ib_flow_attr flow_attr = {
2553 .num_of_specs = 0,
2554 .size = sizeof(flow_attr)
2555 };
2556
2557 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2558 if (IS_ERR(handler_rx)) {
2559 err = PTR_ERR(handler_rx);
2560 goto err;
2561 }
2562
2563 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2564 if (IS_ERR(handler_tx)) {
2565 err = PTR_ERR(handler_tx);
2566 goto err_tx;
2567 }
2568
2569 list_add(&handler_tx->list, &handler_rx->list);
2570
2571 return handler_rx;
2572
2573err_tx:
74491de9 2574 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 2575 ft_rx->refcount--;
2576 kfree(handler_rx);
2577err:
2578 return ERR_PTR(err);
2579}
2580
038d2ef8
MG		 2581static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2582 struct ib_flow_attr *flow_attr,
2583 int domain)
2584{
2585 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 2586 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 2587 struct mlx5_ib_flow_handler *handler = NULL;
2588 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 2589 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8
MG		 2590 struct mlx5_ib_flow_prio *ft_prio;
2591 int err;
a550ddfc 2592 int underlay_qpn;
038d2ef8
MG		 2593
2594 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
dac388ef 2595 return ERR_PTR(-ENOMEM);
038d2ef8
MG		 2596
2597 if (domain != IB_FLOW_DOMAIN_USER ||
2598 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
35d19011 2599 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
038d2ef8
MG		 2600 return ERR_PTR(-EINVAL);
2601
2602 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2603 if (!dst)
2604 return ERR_PTR(-ENOMEM);
2605
2606 mutex_lock(&dev->flow_db.lock);
2607
cc0e5d42 2608 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
038d2ef8
MG		 2609 if (IS_ERR(ft_prio)) {
2610 err = PTR_ERR(ft_prio);
2611 goto unlock;
2612 }
cc0e5d42
MG		 2613 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2614 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2615 if (IS_ERR(ft_prio_tx)) {
2616 err = PTR_ERR(ft_prio_tx);
2617 ft_prio_tx = NULL;
2618 goto destroy_ft;
2619 }
2620 }
038d2ef8
MG		 2621
2622 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
d9f88e5a
YH		 2623 if (mqp->flags & MLX5_IB_QP_RSS)
2624 dst->tir_num = mqp->rss_qp.tirn;
2625 else
2626 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
038d2ef8
MG		 2627
2628 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2629 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2630 handler = create_dont_trap_rule(dev, ft_prio,
2631 flow_attr, dst);
2632 } else {
a550ddfc
YH		 2633 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
2634 mqp->underlay_qpn : 0;
2635 handler = _create_flow_rule(dev, ft_prio, flow_attr,
2636 dst, underlay_qpn);
35d19011 2637 }
038d2ef8
MG		 2638 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2639 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2640 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2641 dst);
cc0e5d42
MG		 2642 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2643 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 2644 } else {
2645 err = -EINVAL;
2646 goto destroy_ft;
2647 }
2648
2649 if (IS_ERR(handler)) {
2650 err = PTR_ERR(handler);
2651 handler = NULL;
2652 goto destroy_ft;
2653 }
2654
038d2ef8
MG		 2655 mutex_unlock(&dev->flow_db.lock);
2656 kfree(dst);
2657
2658 return &handler->ibflow;
2659
2660destroy_ft:
2661 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 2662 if (ft_prio_tx)
2663 put_flow_table(dev, ft_prio_tx, false);
038d2ef8
MG		 2664unlock:
2665 mutex_unlock(&dev->flow_db.lock);
2666 kfree(dst);
2667 kfree(handler);
2668 return ERR_PTR(err);
2669}
2670
e126ba97
EC		 2671static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2672{
2673 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 2674 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97
EC		 2675 int err;
2676
81e30880
YH		 2677 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
2678 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
2679 return -EOPNOTSUPP;
2680 }
2681
9603b61d 2682 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2683 if (err)
2684 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2685 ibqp->qp_num, gid->raw);
2686
2687 return err;
2688}
2689
2690static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2691{
2692 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2693 int err;
2694
9603b61d 2695 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2696 if (err)
2697 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2698 ibqp->qp_num, gid->raw);
2699
2700 return err;
2701}
2702
2703static int init_node_data(struct mlx5_ib_dev *dev)
2704{
1b5daf11 2705 int err;
e126ba97 2706
1b5daf11 2707 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 2708 if (err)
1b5daf11 2709 return err;
e126ba97 2710
1b5daf11 2711 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 2712
1b5daf11 2713 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 2714}
2715
2716static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2717 char *buf)
2718{
2719 struct mlx5_ib_dev *dev =
2720 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2721
9603b61d 2722 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 2723}
2724
2725static ssize_t show_reg_pages(struct device *device,
2726 struct device_attribute *attr, char *buf)
2727{
2728 struct mlx5_ib_dev *dev =
2729 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2730
6aec21f6 2731 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 2732}
2733
2734static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2735 char *buf)
2736{
2737 struct mlx5_ib_dev *dev =
2738 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 2739 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 2740}
2741
e126ba97
EC		 2742static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2743 char *buf)
2744{
2745 struct mlx5_ib_dev *dev =
2746 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 2747 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 2748}
2749
2750static ssize_t show_board(struct device *device, struct device_attribute *attr,
2751 char *buf)
2752{
2753 struct mlx5_ib_dev *dev =
2754 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2755 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 2756 dev->mdev->board_id);
e126ba97
EC		 2757}
2758
2759static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
e126ba97
EC		 2760static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2761static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2762static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2763static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2764
2765static struct device_attribute *mlx5_class_attributes[] = {
2766 &dev_attr_hw_rev,
e126ba97
EC		 2767 &dev_attr_hca_type,
2768 &dev_attr_board_id,
2769 &dev_attr_fw_pages,
2770 &dev_attr_reg_pages,
2771};
2772
7722f47e
HE		 2773static void pkey_change_handler(struct work_struct *work)
2774{
2775 struct mlx5_ib_port_resources *ports =
2776 container_of(work, struct mlx5_ib_port_resources,
2777 pkey_change_work);
2778
2779 mutex_lock(&ports->devr->mutex);
2780 mlx5_ib_gsi_pkey_change(ports->gsi);
2781 mutex_unlock(&ports->devr->mutex);
2782}
2783
89ea94a7
MG		 2784static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2785{
2786 struct mlx5_ib_qp *mqp;
2787 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2788 struct mlx5_core_cq *mcq;
2789 struct list_head cq_armed_list;
2790 unsigned long flags_qp;
2791 unsigned long flags_cq;
2792 unsigned long flags;
2793
2794 INIT_LIST_HEAD(&cq_armed_list);
2795
2796 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2797 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2798 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2799 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2800 if (mqp->sq.tail != mqp->sq.head) {
2801 send_mcq = to_mcq(mqp->ibqp.send_cq);
2802 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2803 if (send_mcq->mcq.comp &&
2804 mqp->ibqp.send_cq->comp_handler) {
2805 if (!send_mcq->mcq.reset_notify_added) {
2806 send_mcq->mcq.reset_notify_added = 1;
2807 list_add_tail(&send_mcq->mcq.reset_notify,
2808 &cq_armed_list);
2809 }
2810 }
2811 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2812 }
2813 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2814 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2815 /* no handling is needed for SRQ */
2816 if (!mqp->ibqp.srq) {
2817 if (mqp->rq.tail != mqp->rq.head) {
2818 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2819 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2820 if (recv_mcq->mcq.comp &&
2821 mqp->ibqp.recv_cq->comp_handler) {
2822 if (!recv_mcq->mcq.reset_notify_added) {
2823 recv_mcq->mcq.reset_notify_added = 1;
2824 list_add_tail(&recv_mcq->mcq.reset_notify,
2825 &cq_armed_list);
2826 }
2827 }
2828 spin_unlock_irqrestore(&recv_mcq->lock,
2829 flags_cq);
2830 }
2831 }
2832 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2833 }
2834 /*At that point all inflight post send were put to be executed as of we
2835 * lock/unlock above locks Now need to arm all involved CQs.
2836 */
2837 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2838 mcq->comp(mcq);
2839 }
2840 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2841}
2842
03404e8a
MG		 2843static void delay_drop_handler(struct work_struct *work)
2844{
2845 int err;
2846 struct mlx5_ib_delay_drop *delay_drop =
2847 container_of(work, struct mlx5_ib_delay_drop,
2848 delay_drop_work);
2849
fe248c3a
MG		 2850 atomic_inc(&delay_drop->events_cnt);
2851
03404e8a
MG		 2852 mutex_lock(&delay_drop->lock);
2853 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
2854 delay_drop->timeout);
2855 if (err) {
2856 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
2857 delay_drop->timeout);
2858 delay_drop->activate = false;
2859 }
2860 mutex_unlock(&delay_drop->lock);
2861}
2862
9603b61d 2863static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 2864 enum mlx5_dev_event event, unsigned long param)
e126ba97 2865{
9603b61d 2866 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
e126ba97 2867 struct ib_event ibev;
dbaaff2a 2868 bool fatal = false;
e126ba97
EC		 2869 u8 port = 0;
2870
2871 switch (event) {
2872 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 2873 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 2874 mlx5_ib_handle_internal_error(ibdev);
dbaaff2a 2875 fatal = true;
e126ba97
EC		 2876 break;
2877
2878 case MLX5_DEV_EVENT_PORT_UP:
e126ba97 2879 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 2880 case MLX5_DEV_EVENT_PORT_INITIALIZED:
4d2f9bbb 2881 port = (u8)param;
5ec8c83e
AH		 2882
2883 /* In RoCE, port up/down events are handled in
2884 * mlx5_netdev_event().
2885 */
2886 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2887 IB_LINK_LAYER_ETHERNET)
2888 return;
2889
2890 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2891 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
e126ba97
EC		 2892 break;
2893
e126ba97
EC		 2894 case MLX5_DEV_EVENT_LID_CHANGE:
2895 ibev.event = IB_EVENT_LID_CHANGE;
4d2f9bbb 2896 port = (u8)param;
e126ba97
EC		 2897 break;
2898
2899 case MLX5_DEV_EVENT_PKEY_CHANGE:
2900 ibev.event = IB_EVENT_PKEY_CHANGE;
4d2f9bbb 2901 port = (u8)param;
7722f47e
HE		 2902
2903 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 2904 break;
2905
2906 case MLX5_DEV_EVENT_GUID_CHANGE:
2907 ibev.event = IB_EVENT_GID_CHANGE;
4d2f9bbb 2908 port = (u8)param;
e126ba97
EC		 2909 break;
2910
2911 case MLX5_DEV_EVENT_CLIENT_REREG:
2912 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4d2f9bbb 2913 port = (u8)param;
e126ba97 2914 break;
03404e8a
MG		 2915 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
2916 schedule_work(&ibdev->delay_drop.delay_drop_work);
2917 goto out;
bdc37924 2918 default:
03404e8a 2919 goto out;
e126ba97
EC		 2920 }
2921
2922 ibev.device = &ibdev->ib_dev;
2923 ibev.element.port_num = port;
2924
a0c84c32
EC		 2925 if (port < 1 || port > ibdev->num_ports) {
2926 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
03404e8a 2927 goto out;
a0c84c32
EC		 2928 }
2929
e126ba97
EC		 2930 if (ibdev->ib_active)
2931 ib_dispatch_event(&ibev);
dbaaff2a
EC		 2932
2933 if (fatal)
2934 ibdev->ib_active = false;
03404e8a
MG		 2935
2936out:
2937 return;
e126ba97
EC		 2938}
2939
c43f1112
MG		 2940static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2941{
2942 struct mlx5_hca_vport_context vport_ctx;
2943 int err;
2944 int port;
2945
2946 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2947 dev->mdev->port_caps[port - 1].has_smi = false;
2948 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
2949 MLX5_CAP_PORT_TYPE_IB) {
2950 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2951 err = mlx5_query_hca_vport_context(dev->mdev, 0,
2952 port, 0,
2953 &vport_ctx);
2954 if (err) {
2955 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2956 port, err);
2957 return err;
2958 }
2959 dev->mdev->port_caps[port - 1].has_smi =
2960 vport_ctx.has_smi;
2961 } else {
2962 dev->mdev->port_caps[port - 1].has_smi = true;
2963 }
2964 }
2965 }
2966 return 0;
2967}
2968
e126ba97
EC		 2969static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2970{
2971 int port;
2972
938fe83c 2973 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
e126ba97
EC		 2974 mlx5_query_ext_port_caps(dev, port);
2975}
2976
2977static int get_port_caps(struct mlx5_ib_dev *dev)
2978{
2979 struct ib_device_attr *dprops = NULL;
2980 struct ib_port_attr *pprops = NULL;
f614fc15 2981 int err = -ENOMEM;
e126ba97 2982 int port;
2528e33e 2983 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 2984
2985 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2986 if (!pprops)
2987 goto out;
2988
2989 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2990 if (!dprops)
2991 goto out;
2992
c43f1112
MG		 2993 err = set_has_smi_cap(dev);
2994 if (err)
2995 goto out;
2996
2528e33e 2997 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 2998 if (err) {
2999 mlx5_ib_warn(dev, "query_device failed %d\n", err);
3000 goto out;
3001 }
3002
938fe83c 3003 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
c4550c63 3004 memset(pprops, 0, sizeof(*pprops));
e126ba97
EC		 3005 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
3006 if (err) {
938fe83c
SM		 3007 mlx5_ib_warn(dev, "query_port %d failed %d\n",
3008 port, err);
e126ba97
EC		 3009 break;
3010 }
938fe83c
SM		 3011 dev->mdev->port_caps[port - 1].pkey_table_len =
3012 dprops->max_pkeys;
3013 dev->mdev->port_caps[port - 1].gid_table_len =
3014 pprops->gid_tbl_len;
e126ba97
EC		 3015 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
3016 dprops->max_pkeys, pprops->gid_tbl_len);
3017 }
3018
3019out:
3020 kfree(pprops);
3021 kfree(dprops);
3022
3023 return err;
3024}
3025
3026static void destroy_umrc_res(struct mlx5_ib_dev *dev)
3027{
3028 int err;
3029
3030 err = mlx5_mr_cache_cleanup(dev);
3031 if (err)
3032 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
3033
3034 mlx5_ib_destroy_qp(dev->umrc.qp);
add08d76 3035 ib_free_cq(dev->umrc.cq);
e126ba97
EC		 3036 ib_dealloc_pd(dev->umrc.pd);
3037}
3038
3039enum {
3040 MAX_UMR_WR = 128,
3041};
3042
3043static int create_umr_res(struct mlx5_ib_dev *dev)
3044{
3045 struct ib_qp_init_attr *init_attr = NULL;
3046 struct ib_qp_attr *attr = NULL;
3047 struct ib_pd *pd;
3048 struct ib_cq *cq;
3049 struct ib_qp *qp;
e126ba97
EC		 3050 int ret;
3051
3052 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
3053 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
3054 if (!attr || !init_attr) {
3055 ret = -ENOMEM;
3056 goto error_0;
3057 }
3058
ed082d36 3059 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 3060 if (IS_ERR(pd)) {
3061 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
3062 ret = PTR_ERR(pd);
3063 goto error_0;
3064 }
3065
add08d76 3066 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 3067 if (IS_ERR(cq)) {
3068 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
3069 ret = PTR_ERR(cq);
3070 goto error_2;
3071 }
e126ba97
EC		 3072
3073 init_attr->send_cq = cq;
3074 init_attr->recv_cq = cq;
3075 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
3076 init_attr->cap.max_send_wr = MAX_UMR_WR;
3077 init_attr->cap.max_send_sge = 1;
3078 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
3079 init_attr->port_num = 1;
3080 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
3081 if (IS_ERR(qp)) {
3082 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
3083 ret = PTR_ERR(qp);
3084 goto error_3;
3085 }
3086 qp->device = &dev->ib_dev;
3087 qp->real_qp = qp;
3088 qp->uobject = NULL;
3089 qp->qp_type = MLX5_IB_QPT_REG_UMR;
3090
3091 attr->qp_state = IB_QPS_INIT;
3092 attr->port_num = 1;
3093 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
3094 IB_QP_PORT, NULL);
3095 if (ret) {
3096 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
3097 goto error_4;
3098 }
3099
3100 memset(attr, 0, sizeof(*attr));
3101 attr->qp_state = IB_QPS_RTR;
3102 attr->path_mtu = IB_MTU_256;
3103
3104 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3105 if (ret) {
3106 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
3107 goto error_4;
3108 }
3109
3110 memset(attr, 0, sizeof(*attr));
3111 attr->qp_state = IB_QPS_RTS;
3112 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3113 if (ret) {
3114 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
3115 goto error_4;
3116 }
3117
3118 dev->umrc.qp = qp;
3119 dev->umrc.cq = cq;
e126ba97
EC		 3120 dev->umrc.pd = pd;
3121
3122 sema_init(&dev->umrc.sem, MAX_UMR_WR);
3123 ret = mlx5_mr_cache_init(dev);
3124 if (ret) {
3125 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
3126 goto error_4;
3127 }
3128
3129 kfree(attr);
3130 kfree(init_attr);
3131
3132 return 0;
3133
3134error_4:
3135 mlx5_ib_destroy_qp(qp);
3136
3137error_3:
add08d76 3138 ib_free_cq(cq);
e126ba97
EC		 3139
3140error_2:
e126ba97
EC		 3141 ib_dealloc_pd(pd);
3142
3143error_0:
3144 kfree(attr);
3145 kfree(init_attr);
3146 return ret;
3147}
3148
6e8484c5
MG		 3149static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
3150{
3151 switch (umr_fence_cap) {
3152 case MLX5_CAP_UMR_FENCE_NONE:
3153 return MLX5_FENCE_MODE_NONE;
3154 case MLX5_CAP_UMR_FENCE_SMALL:
3155 return MLX5_FENCE_MODE_INITIATOR_SMALL;
3156 default:
3157 return MLX5_FENCE_MODE_STRONG_ORDERING;
3158 }
3159}
3160
e126ba97
EC		 3161static int create_dev_resources(struct mlx5_ib_resources *devr)
3162{
3163 struct ib_srq_init_attr attr;
3164 struct mlx5_ib_dev *dev;
bcf4c1ea 3165 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 3166 int port;
e126ba97
EC		 3167 int ret = 0;
3168
3169 dev = container_of(devr, struct mlx5_ib_dev, devr);
3170
d16e91da
HE		 3171 mutex_init(&devr->mutex);
3172
e126ba97
EC		 3173 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
3174 if (IS_ERR(devr->p0)) {
3175 ret = PTR_ERR(devr->p0);
3176 goto error0;
3177 }
3178 devr->p0->device = &dev->ib_dev;
3179 devr->p0->uobject = NULL;
3180 atomic_set(&devr->p0->usecnt, 0);
3181
bcf4c1ea 3182 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 3183 if (IS_ERR(devr->c0)) {
3184 ret = PTR_ERR(devr->c0);
3185 goto error1;
3186 }
3187 devr->c0->device = &dev->ib_dev;
3188 devr->c0->uobject = NULL;
3189 devr->c0->comp_handler = NULL;
3190 devr->c0->event_handler = NULL;
3191 devr->c0->cq_context = NULL;
3192 atomic_set(&devr->c0->usecnt, 0);
3193
3194 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3195 if (IS_ERR(devr->x0)) {
3196 ret = PTR_ERR(devr->x0);
3197 goto error2;
3198 }
3199 devr->x0->device = &dev->ib_dev;
3200 devr->x0->inode = NULL;
3201 atomic_set(&devr->x0->usecnt, 0);
3202 mutex_init(&devr->x0->tgt_qp_mutex);
3203 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
3204
3205 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3206 if (IS_ERR(devr->x1)) {
3207 ret = PTR_ERR(devr->x1);
3208 goto error3;
3209 }
3210 devr->x1->device = &dev->ib_dev;
3211 devr->x1->inode = NULL;
3212 atomic_set(&devr->x1->usecnt, 0);
3213 mutex_init(&devr->x1->tgt_qp_mutex);
3214 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
3215
3216 memset(&attr, 0, sizeof(attr));
3217 attr.attr.max_sge = 1;
3218 attr.attr.max_wr = 1;
3219 attr.srq_type = IB_SRQT_XRC;
3220 attr.ext.xrc.cq = devr->c0;
3221 attr.ext.xrc.xrcd = devr->x0;
3222
3223 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3224 if (IS_ERR(devr->s0)) {
3225 ret = PTR_ERR(devr->s0);
3226 goto error4;
3227 }
3228 devr->s0->device = &dev->ib_dev;
3229 devr->s0->pd = devr->p0;
3230 devr->s0->uobject = NULL;
3231 devr->s0->event_handler = NULL;
3232 devr->s0->srq_context = NULL;
3233 devr->s0->srq_type = IB_SRQT_XRC;
3234 devr->s0->ext.xrc.xrcd = devr->x0;
3235 devr->s0->ext.xrc.cq = devr->c0;
3236 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
3237 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
3238 atomic_inc(&devr->p0->usecnt);
3239 atomic_set(&devr->s0->usecnt, 0);
3240
4aa17b28
HA		 3241 memset(&attr, 0, sizeof(attr));
3242 attr.attr.max_sge = 1;
3243 attr.attr.max_wr = 1;
3244 attr.srq_type = IB_SRQT_BASIC;
3245 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3246 if (IS_ERR(devr->s1)) {
3247 ret = PTR_ERR(devr->s1);
3248 goto error5;
3249 }
3250 devr->s1->device = &dev->ib_dev;
3251 devr->s1->pd = devr->p0;
3252 devr->s1->uobject = NULL;
3253 devr->s1->event_handler = NULL;
3254 devr->s1->srq_context = NULL;
3255 devr->s1->srq_type = IB_SRQT_BASIC;
3256 devr->s1->ext.xrc.cq = devr->c0;
3257 atomic_inc(&devr->p0->usecnt);
3258 atomic_set(&devr->s0->usecnt, 0);
3259
7722f47e
HE		 3260 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
3261 INIT_WORK(&devr->ports[port].pkey_change_work,
3262 pkey_change_handler);
3263 devr->ports[port].devr = devr;
3264 }
3265
e126ba97
EC		 3266 return 0;
3267
4aa17b28
HA		 3268error5:
3269 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 3270error4:
3271 mlx5_ib_dealloc_xrcd(devr->x1);
3272error3:
3273 mlx5_ib_dealloc_xrcd(devr->x0);
3274error2:
3275 mlx5_ib_destroy_cq(devr->c0);
3276error1:
3277 mlx5_ib_dealloc_pd(devr->p0);
3278error0:
3279 return ret;
3280}
3281
3282static void destroy_dev_resources(struct mlx5_ib_resources *devr)
3283{
7722f47e
HE		 3284 struct mlx5_ib_dev *dev =
3285 container_of(devr, struct mlx5_ib_dev, devr);
3286 int port;
3287
4aa17b28 3288 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 3289 mlx5_ib_destroy_srq(devr->s0);
3290 mlx5_ib_dealloc_xrcd(devr->x0);
3291 mlx5_ib_dealloc_xrcd(devr->x1);
3292 mlx5_ib_destroy_cq(devr->c0);
3293 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 3294
3295 /* Make sure no change P_Key work items are still executing */
3296 for (port = 0; port < dev->num_ports; ++port)
3297 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 3298}
3299
e53505a8
AS		 3300static u32 get_core_cap_flags(struct ib_device *ibdev)
3301{
3302 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3303 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3304 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3305 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3306 u32 ret = 0;
3307
3308 if (ll == IB_LINK_LAYER_INFINIBAND)
3309 return RDMA_CORE_PORT_IBA_IB;
3310
72cd5717
OG		 3311 ret = RDMA_CORE_PORT_RAW_PACKET;
3312
e53505a8 3313 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 3314 return ret;
e53505a8
AS		 3315
3316 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 3317 return ret;
e53505a8
AS		 3318
3319 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3320 ret |= RDMA_CORE_PORT_IBA_ROCE;
3321
3322 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3323 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3324
3325 return ret;
3326}
3327
7738613e
IW		 3328static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3329 struct ib_port_immutable *immutable)
3330{
3331 struct ib_port_attr attr;
ca5b91d6
OG		 3332 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3333 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
7738613e
IW		 3334 int err;
3335
c4550c63
OG		 3336 immutable->core_cap_flags = get_core_cap_flags(ibdev);
3337
3338 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 3339 if (err)
3340 return err;
3341
3342 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3343 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 3344 immutable->core_cap_flags = get_core_cap_flags(ibdev);
ca5b91d6
OG		 3345 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3346 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 3347
3348 return 0;
3349}
3350
9abb0d1b 3351static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 3352{
3353 struct mlx5_ib_dev *dev =
3354 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 3355 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
3356 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
3357 fw_rev_sub(dev->mdev));
c7342823
IW		 3358}
3359
45f95acd 3360static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 3361{
3362 struct mlx5_core_dev *mdev = dev->mdev;
3363 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3364 MLX5_FLOW_NAMESPACE_LAG);
3365 struct mlx5_flow_table *ft;
3366 int err;
3367
3368 if (!ns || !mlx5_lag_is_active(mdev))
3369 return 0;
3370
3371 err = mlx5_cmd_create_vport_lag(mdev);
3372 if (err)
3373 return err;
3374
3375 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3376 if (IS_ERR(ft)) {
3377 err = PTR_ERR(ft);
3378 goto err_destroy_vport_lag;
3379 }
3380
3381 dev->flow_db.lag_demux_ft = ft;
3382 return 0;
3383
3384err_destroy_vport_lag:
3385 mlx5_cmd_destroy_vport_lag(mdev);
3386 return err;
3387}
3388
45f95acd 3389static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 3390{
3391 struct mlx5_core_dev *mdev = dev->mdev;
3392
3393 if (dev->flow_db.lag_demux_ft) {
3394 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
3395 dev->flow_db.lag_demux_ft = NULL;
3396
3397 mlx5_cmd_destroy_vport_lag(mdev);
3398 }
3399}
3400
d012f5d6
OG		 3401static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev)
3402{
3403 int err;
3404
3405 dev->roce.nb.notifier_call = mlx5_netdev_event;
3406 err = register_netdevice_notifier(&dev->roce.nb);
3407 if (err) {
3408 dev->roce.nb.notifier_call = NULL;
3409 return err;
3410 }
3411
3412 return 0;
3413}
3414
3415static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev)
5ec8c83e
AH		 3416{
3417 if (dev->roce.nb.notifier_call) {
3418 unregister_netdevice_notifier(&dev->roce.nb);
3419 dev->roce.nb.notifier_call = NULL;
3420 }
3421}
3422
45f95acd 3423static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 3424{
e53505a8
AS		 3425 int err;
3426
d012f5d6
OG		 3427 err = mlx5_add_netdev_notifier(dev);
3428 if (err)
e53505a8
AS		 3429 return err;
3430
ca5b91d6
OG		 3431 if (MLX5_CAP_GEN(dev->mdev, roce)) {
3432 err = mlx5_nic_vport_enable_roce(dev->mdev);
3433 if (err)
3434 goto err_unregister_netdevice_notifier;
3435 }
e53505a8 3436
45f95acd 3437 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 3438 if (err)
3439 goto err_disable_roce;
3440
e53505a8
AS		 3441 return 0;
3442
9ef9c640 3443err_disable_roce:
ca5b91d6
OG		 3444 if (MLX5_CAP_GEN(dev->mdev, roce))
3445 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 3446
e53505a8 3447err_unregister_netdevice_notifier:
d012f5d6 3448 mlx5_remove_netdev_notifier(dev);
e53505a8 3449 return err;
fc24fc5e
AS		 3450}
3451
45f95acd 3452static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 3453{
45f95acd 3454 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 3455 if (MLX5_CAP_GEN(dev->mdev, roce))
3456 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 3457}
3458
e1f24a79 3459struct mlx5_ib_counter {
7c16f477
KH		 3460 const char *name;
3461 size_t offset;
3462};
3463
3464#define INIT_Q_COUNTER(_name) \
3465 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3466
e1f24a79 3467static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 3468 INIT_Q_COUNTER(rx_write_requests),
3469 INIT_Q_COUNTER(rx_read_requests),
3470 INIT_Q_COUNTER(rx_atomic_requests),
3471 INIT_Q_COUNTER(out_of_buffer),
3472};
3473
e1f24a79 3474static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 3475 INIT_Q_COUNTER(out_of_sequence),
3476};
3477
e1f24a79 3478static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 3479 INIT_Q_COUNTER(duplicate_request),
3480 INIT_Q_COUNTER(rnr_nak_retry_err),
3481 INIT_Q_COUNTER(packet_seq_err),
3482 INIT_Q_COUNTER(implied_nak_seq_err),
3483 INIT_Q_COUNTER(local_ack_timeout_err),
3484};
3485
e1f24a79
PP		 3486#define INIT_CONG_COUNTER(_name) \
3487 { .name = #_name, .offset = \
3488 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
3489
3490static const struct mlx5_ib_counter cong_cnts[] = {
3491 INIT_CONG_COUNTER(rp_cnp_ignored),
3492 INIT_CONG_COUNTER(rp_cnp_handled),
3493 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
3494 INIT_CONG_COUNTER(np_cnp_sent),
3495};
3496
58dcb60a
PP		 3497static const struct mlx5_ib_counter extended_err_cnts[] = {
3498 INIT_Q_COUNTER(resp_local_length_error),
3499 INIT_Q_COUNTER(resp_cqe_error),
3500 INIT_Q_COUNTER(req_cqe_error),
3501 INIT_Q_COUNTER(req_remote_invalid_request),
3502 INIT_Q_COUNTER(req_remote_access_errors),
3503 INIT_Q_COUNTER(resp_remote_access_errors),
3504 INIT_Q_COUNTER(resp_cqe_flush_error),
3505 INIT_Q_COUNTER(req_cqe_flush_error),
3506};
3507
e1f24a79 3508static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a
MB		 3509{
3510 unsigned int i;
3511
7c16f477 3512 for (i = 0; i < dev->num_ports; i++) {
0837e86a 3513 mlx5_core_dealloc_q_counter(dev->mdev,
e1f24a79
PP		 3514 dev->port[i].cnts.set_id);
3515 kfree(dev->port[i].cnts.names);
3516 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 3517 }
3518}
3519
e1f24a79
PP		 3520static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
3521 struct mlx5_ib_counters *cnts)
7c16f477
KH		 3522{
3523 u32 num_counters;
3524
3525 num_counters = ARRAY_SIZE(basic_q_cnts);
3526
3527 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
3528 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
3529
3530 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
3531 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 3532
3533 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
3534 num_counters += ARRAY_SIZE(extended_err_cnts);
3535
e1f24a79 3536 cnts->num_q_counters = num_counters;
7c16f477 3537
e1f24a79
PP		 3538 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3539 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
3540 num_counters += ARRAY_SIZE(cong_cnts);
3541 }
3542
3543 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
3544 if (!cnts->names)
7c16f477
KH		 3545 return -ENOMEM;
3546
e1f24a79
PP		 3547 cnts->offsets = kcalloc(num_counters,
3548 sizeof(cnts->offsets), GFP_KERNEL);
3549 if (!cnts->offsets)
7c16f477
KH		 3550 goto err_names;
3551
7c16f477
KH		 3552 return 0;
3553
3554err_names:
e1f24a79 3555 kfree(cnts->names);
7c16f477
KH		 3556 return -ENOMEM;
3557}
3558
e1f24a79
PP		 3559static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
3560 const char **names,
3561 size_t *offsets)
7c16f477
KH		 3562{
3563 int i;
3564 int j = 0;
3565
3566 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
3567 names[j] = basic_q_cnts[i].name;
3568 offsets[j] = basic_q_cnts[i].offset;
3569 }
3570
3571 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
3572 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
3573 names[j] = out_of_seq_q_cnts[i].name;
3574 offsets[j] = out_of_seq_q_cnts[i].offset;
3575 }
3576 }
3577
3578 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3579 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
3580 names[j] = retrans_q_cnts[i].name;
3581 offsets[j] = retrans_q_cnts[i].offset;
3582 }
3583 }
e1f24a79 3584
58dcb60a
PP		 3585 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
3586 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
3587 names[j] = extended_err_cnts[i].name;
3588 offsets[j] = extended_err_cnts[i].offset;
3589 }
3590 }
3591
e1f24a79
PP		 3592 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3593 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
3594 names[j] = cong_cnts[i].name;
3595 offsets[j] = cong_cnts[i].offset;
3596 }
3597 }
0837e86a
MB		 3598}
3599
e1f24a79 3600static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a
MB		 3601{
3602 int i;
3603 int ret;
3604
3605 for (i = 0; i < dev->num_ports; i++) {
7c16f477
KH		 3606 struct mlx5_ib_port *port = &dev->port[i];
3607
0837e86a 3608 ret = mlx5_core_alloc_q_counter(dev->mdev,
e1f24a79 3609 &port->cnts.set_id);
0837e86a
MB		 3610 if (ret) {
3611 mlx5_ib_warn(dev,
3612 "couldn't allocate queue counter for port %d, err %d\n",
3613 i + 1, ret);
3614 goto dealloc_counters;
3615 }
7c16f477 3616
e1f24a79 3617 ret = __mlx5_ib_alloc_counters(dev, &port->cnts);
7c16f477
KH		 3618 if (ret)
3619 goto dealloc_counters;
3620
e1f24a79
PP		 3621 mlx5_ib_fill_counters(dev, port->cnts.names,
3622 port->cnts.offsets);
0837e86a
MB		 3623 }
3624
3625 return 0;
3626
3627dealloc_counters:
3628 while (--i >= 0)
3629 mlx5_core_dealloc_q_counter(dev->mdev,
e1f24a79 3630 dev->port[i].cnts.set_id);
0837e86a
MB		 3631
3632 return ret;
3633}
3634
0ad17a8f
MB		 3635static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
3636 u8 port_num)
3637{
7c16f477
KH		 3638 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3639 struct mlx5_ib_port *port = &dev->port[port_num - 1];
0ad17a8f
MB		 3640
3641 /* We support only per port stats */
3642 if (port_num == 0)
3643 return NULL;
3644
e1f24a79
PP		 3645 return rdma_alloc_hw_stats_struct(port->cnts.names,
3646 port->cnts.num_q_counters +
3647 port->cnts.num_cong_counters,
0ad17a8f
MB		 3648 RDMA_HW_STATS_DEFAULT_LIFESPAN);
3649}
3650
e1f24a79
PP		 3651static int mlx5_ib_query_q_counters(struct mlx5_ib_dev *dev,
3652 struct mlx5_ib_port *port,
3653 struct rdma_hw_stats *stats)
0ad17a8f 3654{
0ad17a8f
MB		 3655 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3656 void *out;
3657 __be32 val;
e1f24a79 3658 int ret, i;
0ad17a8f 3659
1b9a07ee 3660 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 3661 if (!out)
3662 return -ENOMEM;
3663
3664 ret = mlx5_core_query_q_counter(dev->mdev,
e1f24a79 3665 port->cnts.set_id, 0,
0ad17a8f
MB		 3666 out, outlen);
3667 if (ret)
3668 goto free;
3669
e1f24a79
PP		 3670 for (i = 0; i < port->cnts.num_q_counters; i++) {
3671 val = *(__be32 *)(out + port->cnts.offsets[i]);
0ad17a8f
MB		 3672 stats->value[i] = (u64)be32_to_cpu(val);
3673 }
7c16f477 3674
0ad17a8f
MB		 3675free:
3676 kvfree(out);
e1f24a79
PP		 3677 return ret;
3678}
3679
3680static int mlx5_ib_query_cong_counters(struct mlx5_ib_dev *dev,
3681 struct mlx5_ib_port *port,
3682 struct rdma_hw_stats *stats)
3683{
3684 int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out);
3685 void *out;
3686 int ret, i;
3687 int offset = port->cnts.num_q_counters;
3688
1b9a07ee 3689 out = kvzalloc(outlen, GFP_KERNEL);
e1f24a79
PP		 3690 if (!out)
3691 return -ENOMEM;
3692
3693 ret = mlx5_cmd_query_cong_counter(dev->mdev, false, out, outlen);
3694 if (ret)
3695 goto free;
3696
3697 for (i = 0; i < port->cnts.num_cong_counters; i++) {
3698 stats->value[i + offset] =
3699 be64_to_cpup((__be64 *)(out +
3700 port->cnts.offsets[i + offset]));
3701 }
3702
3703free:
3704 kvfree(out);
3705 return ret;
3706}
3707
3708static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
3709 struct rdma_hw_stats *stats,
3710 u8 port_num, int index)
3711{
3712 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3713 struct mlx5_ib_port *port = &dev->port[port_num - 1];
3714 int ret, num_counters;
3715
3716 if (!stats)
3717 return -EINVAL;
3718
3719 ret = mlx5_ib_query_q_counters(dev, port, stats);
3720 if (ret)
3721 return ret;
3722 num_counters = port->cnts.num_q_counters;
3723
3724 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3725 ret = mlx5_ib_query_cong_counters(dev, port, stats);
3726 if (ret)
3727 return ret;
3728 num_counters += port->cnts.num_cong_counters;
3729 }
3730
3731 return num_counters;
0ad17a8f
MB		 3732}
3733
8e959601
NV		 3734static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
3735{
3736 return mlx5_rdma_netdev_free(netdev);
3737}
3738
693dfd5a
ES		 3739static struct net_device*
3740mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
3741 u8 port_num,
3742 enum rdma_netdev_t type,
3743 const char *name,
3744 unsigned char name_assign_type,
3745 void (*setup)(struct net_device *))
3746{
8e959601
NV		 3747 struct net_device *netdev;
3748 struct rdma_netdev *rn;
3749
693dfd5a
ES		 3750 if (type != RDMA_NETDEV_IPOIB)
3751 return ERR_PTR(-EOPNOTSUPP);
3752
8e959601
NV		 3753 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
3754 name, setup);
3755 if (likely(!IS_ERR_OR_NULL(netdev))) {
3756 rn = netdev_priv(netdev);
3757 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
3758 }
3759 return netdev;
693dfd5a
ES		 3760}
3761
fe248c3a
MG		 3762static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
3763{
3764 if (!dev->delay_drop.dbg)
3765 return;
3766 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
3767 kfree(dev->delay_drop.dbg);
3768 dev->delay_drop.dbg = NULL;
3769}
3770
03404e8a
MG		 3771static void cancel_delay_drop(struct mlx5_ib_dev *dev)
3772{
3773 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
3774 return;
3775
3776 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 3777 delay_drop_debugfs_cleanup(dev);
3778}
3779
3780static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
3781 size_t count, loff_t *pos)
3782{
3783 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3784 char lbuf[20];
3785 int len;
3786
3787 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
3788 return simple_read_from_buffer(buf, count, pos, lbuf, len);
3789}
3790
3791static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
3792 size_t count, loff_t *pos)
3793{
3794 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3795 u32 timeout;
3796 u32 var;
3797
3798 if (kstrtouint_from_user(buf, count, 0, &var))
3799 return -EFAULT;
3800
3801 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
3802 1000);
3803 if (timeout != var)
3804 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
3805 timeout);
3806
3807 delay_drop->timeout = timeout;
3808
3809 return count;
3810}
3811
3812static const struct file_operations fops_delay_drop_timeout = {
3813 .owner = THIS_MODULE,
3814 .open = simple_open,
3815 .write = delay_drop_timeout_write,
3816 .read = delay_drop_timeout_read,
3817};
3818
3819static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
3820{
3821 struct mlx5_ib_dbg_delay_drop *dbg;
3822
3823 if (!mlx5_debugfs_root)
3824 return 0;
3825
3826 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
3827 if (!dbg)
3828 return -ENOMEM;
3829
3830 dbg->dir_debugfs =
3831 debugfs_create_dir("delay_drop",
3832 dev->mdev->priv.dbg_root);
3833 if (!dbg->dir_debugfs)
3834 return -ENOMEM;
3835
3836 dbg->events_cnt_debugfs =
3837 debugfs_create_atomic_t("num_timeout_events", 0400,
3838 dbg->dir_debugfs,
3839 &dev->delay_drop.events_cnt);
3840 if (!dbg->events_cnt_debugfs)
3841 goto out_debugfs;
3842
3843 dbg->rqs_cnt_debugfs =
3844 debugfs_create_atomic_t("num_rqs", 0400,
3845 dbg->dir_debugfs,
3846 &dev->delay_drop.rqs_cnt);
3847 if (!dbg->rqs_cnt_debugfs)
3848 goto out_debugfs;
3849
3850 dbg->timeout_debugfs =
3851 debugfs_create_file("timeout", 0600,
3852 dbg->dir_debugfs,
3853 &dev->delay_drop,
3854 &fops_delay_drop_timeout);
3855 if (!dbg->timeout_debugfs)
3856 goto out_debugfs;
3857
4a5fd5d2
MG		 3858 dev->delay_drop.dbg = dbg;
3859
fe248c3a
MG		 3860 return 0;
3861
3862out_debugfs:
3863 delay_drop_debugfs_cleanup(dev);
3864 return -ENOMEM;
03404e8a
MG		 3865}
3866
3867static void init_delay_drop(struct mlx5_ib_dev *dev)
3868{
3869 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
3870 return;
3871
3872 mutex_init(&dev->delay_drop.lock);
3873 dev->delay_drop.dev = dev;
3874 dev->delay_drop.activate = false;
3875 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
3876 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 3877 atomic_set(&dev->delay_drop.rqs_cnt, 0);
3878 atomic_set(&dev->delay_drop.events_cnt, 0);
3879
3880 if (delay_drop_debugfs_init(dev))
3881 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
03404e8a
MG		 3882}
3883
84305d71
LR		 3884static const struct cpumask *
3885mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
40b24403
SG		 3886{
3887 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3888
3889 return mlx5_get_vector_affinity(dev->mdev, comp_vector);
3890}
3891
9603b61d 3892static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
e126ba97 3893{
e126ba97 3894 struct mlx5_ib_dev *dev;
ebd61f68
AS		 3895 enum rdma_link_layer ll;
3896 int port_type_cap;
4babcf97 3897 const char *name;
e126ba97
EC		 3898 int err;
3899 int i;
3900
ebd61f68
AS		 3901 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3902 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3903
e126ba97
EC		 3904 printk_once(KERN_INFO "%s", mlx5_version);
3905
3906 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
3907 if (!dev)
9603b61d 3908 return NULL;
e126ba97 3909
9603b61d 3910 dev->mdev = mdev;
e126ba97 3911
0837e86a
MB		 3912 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
3913 GFP_KERNEL);
3914 if (!dev->port)
3915 goto err_dealloc;
3916
fc24fc5e 3917 rwlock_init(&dev->roce.netdev_lock);
e126ba97
EC		 3918 err = get_port_caps(dev);
3919 if (err)
0837e86a 3920 goto err_free_port;
e126ba97 3921
1b5daf11
MD		 3922 if (mlx5_use_mad_ifc(dev))
3923 get_ext_port_caps(dev);
e126ba97 3924
4babcf97
AH		 3925 if (!mlx5_lag_is_active(mdev))
3926 name = "mlx5_%d";
3927 else
3928 name = "mlx5_bond_%d";
3929
3930 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
e126ba97
EC		 3931 dev->ib_dev.owner = THIS_MODULE;
3932 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 3933 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
938fe83c 3934 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
e126ba97 3935 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 3936 dev->ib_dev.num_comp_vectors =
3937 dev->mdev->priv.eq_table.num_comp_vectors;
9b0c289e 3938 dev->ib_dev.dev.parent = &mdev->pdev->dev;
e126ba97
EC		 3939
3940 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
3941 dev->ib_dev.uverbs_cmd_mask =
3942 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
3943 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
3944 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
3945 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
3946 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 3947 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
3948 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 3949 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 3950 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 3951 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
3952 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
3953 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
3954 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
3955 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
3956 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
3957 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
3958 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
3959 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
3960 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
3961 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
3962 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
3963 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
3964 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
3965 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
3966 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
3967 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 3968 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 3969 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
3970 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349
BW		 3971 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
3972 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP);
e126ba97
EC		 3973
3974 dev->ib_dev.query_device = mlx5_ib_query_device;
3975 dev->ib_dev.query_port = mlx5_ib_query_port;
ebd61f68 3976 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
fc24fc5e
AS		 3977 if (ll == IB_LINK_LAYER_ETHERNET)
3978 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
e126ba97 3979 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 3980 dev->ib_dev.add_gid = mlx5_ib_add_gid;
3981 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 3982 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
3983 dev->ib_dev.modify_device = mlx5_ib_modify_device;
3984 dev->ib_dev.modify_port = mlx5_ib_modify_port;
3985 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
3986 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
3987 dev->ib_dev.mmap = mlx5_ib_mmap;
3988 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
3989 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
3990 dev->ib_dev.create_ah = mlx5_ib_create_ah;
3991 dev->ib_dev.query_ah = mlx5_ib_query_ah;
3992 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
3993 dev->ib_dev.create_srq = mlx5_ib_create_srq;
3994 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
3995 dev->ib_dev.query_srq = mlx5_ib_query_srq;
3996 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
3997 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
3998 dev->ib_dev.create_qp = mlx5_ib_create_qp;
3999 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
4000 dev->ib_dev.query_qp = mlx5_ib_query_qp;
4001 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
4002 dev->ib_dev.post_send = mlx5_ib_post_send;
4003 dev->ib_dev.post_recv = mlx5_ib_post_recv;
4004 dev->ib_dev.create_cq = mlx5_ib_create_cq;
4005 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
4006 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
4007 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
4008 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
4009 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
4010 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
4011 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 4012 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 4013 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
4014 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
4015 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
4016 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 4017 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 4018 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 4019 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
7738613e 4020 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
c7342823 4021 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
40b24403 4022 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
8e959601 4023 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
022d038a 4024 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
8e959601 4025
eff901d3
EC		 4026 if (mlx5_core_is_pf(mdev)) {
4027 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
4028 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
4029 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
4030 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
4031 }
e126ba97 4032
7c2344c3
MG		 4033 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
4034
938fe83c 4035 mlx5_ib_internal_fill_odp_caps(dev);
8cdd312c 4036
6e8484c5
MG		 4037 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
4038
d2370e0a
MB		 4039 if (MLX5_CAP_GEN(mdev, imaicl)) {
4040 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
4041 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
4042 dev->ib_dev.uverbs_cmd_mask |=
4043 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
4044 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
4045 }
4046
7c16f477 4047 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
0ad17a8f
MB		 4048 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
4049 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
4050 }
4051
938fe83c 4052 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 4053 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
4054 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
4055 dev->ib_dev.uverbs_cmd_mask |=
4056 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
4057 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
4058 }
4059
81e30880
YH		 4060 dev->ib_dev.create_flow = mlx5_ib_create_flow;
4061 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
4062 dev->ib_dev.uverbs_ex_cmd_mask |=
4063 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
4064 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
4065
048ccca8 4066 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
038d2ef8 4067 IB_LINK_LAYER_ETHERNET) {
79b20a6c
YH		 4068 dev->ib_dev.create_wq = mlx5_ib_create_wq;
4069 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
4070 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
c5f90929
YH		 4071 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
4072 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
038d2ef8 4073 dev->ib_dev.uverbs_ex_cmd_mask |=
79b20a6c
YH		 4074 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
4075 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
c5f90929
YH		 4076 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
4077 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
4078 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
038d2ef8 4079 }
e126ba97
EC		 4080 err = init_node_data(dev);
4081 if (err)
90be7c8a 4082 goto err_free_port;
e126ba97 4083
038d2ef8 4084 mutex_init(&dev->flow_db.lock);
e126ba97 4085 mutex_init(&dev->cap_mask_mutex);
89ea94a7
MG		 4086 INIT_LIST_HEAD(&dev->qp_list);
4087 spin_lock_init(&dev->reset_flow_resource_lock);
e126ba97 4088
fc24fc5e 4089 if (ll == IB_LINK_LAYER_ETHERNET) {
45f95acd 4090 err = mlx5_enable_eth(dev);
fc24fc5e 4091 if (err)
90be7c8a 4092 goto err_free_port;
fd65f1b8 4093 dev->roce.last_port_state = IB_PORT_DOWN;
fc24fc5e
AS		 4094 }
4095
e126ba97
EC		 4096 err = create_dev_resources(&dev->devr);
4097 if (err)
45f95acd 4098 goto err_disable_eth;
e126ba97 4099
6aec21f6 4100 err = mlx5_ib_odp_init_one(dev);
281d1a92 4101 if (err)
e126ba97
EC		 4102 goto err_rsrc;
4103
45bded2c 4104 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
e1f24a79 4105 err = mlx5_ib_alloc_counters(dev);
45bded2c
KH		 4106 if (err)
4107 goto err_odp;
4108 }
6aec21f6 4109
4a2da0b8
PP		 4110 err = mlx5_ib_init_cong_debugfs(dev);
4111 if (err)
4112 goto err_cnt;
4113
5fe9dec0
EC		 4114 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
4115 if (!dev->mdev->priv.uar)
4a2da0b8 4116 goto err_cong;
5fe9dec0
EC		 4117
4118 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4119 if (err)
4120 goto err_uar_page;
4121
4122 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4123 if (err)
4124 goto err_bfreg;
4125
0837e86a
MB		 4126 err = ib_register_device(&dev->ib_dev, NULL);
4127 if (err)
5fe9dec0 4128 goto err_fp_bfreg;
0837e86a 4129
e126ba97
EC		 4130 err = create_umr_res(dev);
4131 if (err)
4132 goto err_dev;
4133
03404e8a
MG		 4134 init_delay_drop(dev);
4135
e126ba97 4136 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 4137 err = device_create_file(&dev->ib_dev.dev,
4138 mlx5_class_attributes[i]);
4139 if (err)
03404e8a 4140 goto err_delay_drop;
e126ba97
EC		 4141 }
4142
c85023e1
HN		 4143 if ((MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
4144 MLX5_CAP_GEN(mdev, disable_local_lb))
4145 mutex_init(&dev->lb_mutex);
4146
e126ba97
EC		 4147 dev->ib_active = true;
4148
9603b61d 4149 return dev;
e126ba97 4150
03404e8a
MG		 4151err_delay_drop:
4152 cancel_delay_drop(dev);
e126ba97
EC		 4153 destroy_umrc_res(dev);
4154
4155err_dev:
4156 ib_unregister_device(&dev->ib_dev);
4157
5fe9dec0
EC		 4158err_fp_bfreg:
4159 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4160
4161err_bfreg:
4162 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4163
4164err_uar_page:
4165 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4166
e1f24a79 4167err_cnt:
4a2da0b8
PP		 4168 mlx5_ib_cleanup_cong_debugfs(dev);
4169err_cong:
45bded2c 4170 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
e1f24a79 4171 mlx5_ib_dealloc_counters(dev);
0837e86a 4172
6aec21f6
HE		 4173err_odp:
4174 mlx5_ib_odp_remove_one(dev);
4175
e126ba97
EC		 4176err_rsrc:
4177 destroy_dev_resources(&dev->devr);
4178
45f95acd 4179err_disable_eth:
5ec8c83e 4180 if (ll == IB_LINK_LAYER_ETHERNET) {
45f95acd 4181 mlx5_disable_eth(dev);
d012f5d6 4182 mlx5_remove_netdev_notifier(dev);
5ec8c83e 4183 }
fc24fc5e 4184
0837e86a
MB		 4185err_free_port:
4186 kfree(dev->port);
4187
9603b61d 4188err_dealloc:
e126ba97
EC		 4189 ib_dealloc_device((struct ib_device *)dev);
4190
9603b61d 4191 return NULL;
e126ba97
EC		 4192}
4193
9603b61d 4194static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 4195{
9603b61d 4196 struct mlx5_ib_dev *dev = context;
fc24fc5e 4197 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
6aec21f6 4198
03404e8a 4199 cancel_delay_drop(dev);
d012f5d6 4200 mlx5_remove_netdev_notifier(dev);
e126ba97 4201 ib_unregister_device(&dev->ib_dev);
5fe9dec0
EC		 4202 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4203 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4204 mlx5_put_uars_page(dev->mdev, mdev->priv.uar);
4a2da0b8 4205 mlx5_ib_cleanup_cong_debugfs(dev);
45bded2c 4206 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
e1f24a79 4207 mlx5_ib_dealloc_counters(dev);
eefd56e5 4208 destroy_umrc_res(dev);
6aec21f6 4209 mlx5_ib_odp_remove_one(dev);
e126ba97 4210 destroy_dev_resources(&dev->devr);
fc24fc5e 4211 if (ll == IB_LINK_LAYER_ETHERNET)
45f95acd 4212 mlx5_disable_eth(dev);
0837e86a 4213 kfree(dev->port);
e126ba97
EC		 4214 ib_dealloc_device(&dev->ib_dev);
4215}
4216
9603b61d
JM		 4217static struct mlx5_interface mlx5_ib_interface = {
4218 .add = mlx5_ib_add,
4219 .remove = mlx5_ib_remove,
4220 .event = mlx5_ib_event,
d9aaed83
AK		 4221#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4222 .pfault = mlx5_ib_pfault,
4223#endif
64613d94 4224 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 4225};
4226
4227static int __init mlx5_ib_init(void)
4228{
6aec21f6
HE		 4229 int err;
4230
81713d37 4231 mlx5_ib_odp_init();
9603b61d 4232
6aec21f6 4233 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 4234
6aec21f6 4235 return err;
e126ba97
EC		 4236}
4237
4238static void __exit mlx5_ib_cleanup(void)
4239{
9603b61d 4240 mlx5_unregister_interface(&mlx5_ib_interface);
e126ba97
EC		 4241}
4242
4243module_init(mlx5_ib_init);
4244module_exit(mlx5_ib_cleanup);
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