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IB/mlx5: Report that device has udata response in create_ah
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97
EC		 34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
37aa5c36
GL		 40#if defined(CONFIG_X86)
41#include <asm/pat.h>
42#endif
e126ba97 43#include <linux/sched.h>
7c2344c3 44#include <linux/delay.h>
e126ba97 45#include <rdma/ib_user_verbs.h>
3f89a643 46#include <rdma/ib_addr.h>
2811ba51 47#include <rdma/ib_cache.h>
ada68c31 48#include <linux/mlx5/port.h>
1b5daf11 49#include <linux/mlx5/vport.h>
7c2344c3 50#include <linux/list.h>
e126ba97
EC		 51#include <rdma/ib_smi.h>
52#include <rdma/ib_umem.h>
038d2ef8
MG		 53#include <linux/in.h>
54#include <linux/etherdevice.h>
55#include <linux/mlx5/fs.h>
e126ba97
EC		 56#include "mlx5_ib.h"
57
58#define DRIVER_NAME "mlx5_ib"
169a1d85
AV		 59#define DRIVER_VERSION "2.2-1"
60#define DRIVER_RELDATE "Feb 2014"
e126ba97
EC		 61
62MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
63MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
64MODULE_LICENSE("Dual BSD/GPL");
65MODULE_VERSION(DRIVER_VERSION);
66
9603b61d
JM		 67static int deprecated_prof_sel = 2;
68module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
69MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
e126ba97
EC		 70
71static char mlx5_version[] =
72 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
73 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
74
da7525d2
EBE		 75enum {
76 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
77};
78
1b5daf11 79static enum rdma_link_layer
ebd61f68 80mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 81{
ebd61f68 82 switch (port_type_cap) {
1b5daf11
MD		 83 case MLX5_CAP_PORT_TYPE_IB:
84 return IB_LINK_LAYER_INFINIBAND;
85 case MLX5_CAP_PORT_TYPE_ETH:
86 return IB_LINK_LAYER_ETHERNET;
87 default:
88 return IB_LINK_LAYER_UNSPECIFIED;
89 }
90}
91
ebd61f68
AS		 92static enum rdma_link_layer
93mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
94{
95 struct mlx5_ib_dev *dev = to_mdev(device);
96 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
97
98 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
99}
100
fc24fc5e
AS		 101static int mlx5_netdev_event(struct notifier_block *this,
102 unsigned long event, void *ptr)
103{
104 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
105 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
106 roce.nb);
107
5ec8c83e
AH		 108 switch (event) {
109 case NETDEV_REGISTER:
110 case NETDEV_UNREGISTER:
111 write_lock(&ibdev->roce.netdev_lock);
112 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
113 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
114 NULL : ndev;
115 write_unlock(&ibdev->roce.netdev_lock);
116 break;
fc24fc5e 117
5ec8c83e 118 case NETDEV_UP:
88621dfe
AH		 119 case NETDEV_DOWN: {
120 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
121 struct net_device *upper = NULL;
122
123 if (lag_ndev) {
124 upper = netdev_master_upper_dev_get(lag_ndev);
125 dev_put(lag_ndev);
126 }
127
128 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
129 && ibdev->ib_active) {
5ec8c83e
AH		 130 struct ib_event ibev = {0};
131
132 ibev.device = &ibdev->ib_dev;
133 ibev.event = (event == NETDEV_UP) ?
134 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
135 ibev.element.port_num = 1;
136 ib_dispatch_event(&ibev);
137 }
138 break;
88621dfe 139 }
fc24fc5e 140
5ec8c83e
AH		 141 default:
142 break;
143 }
fc24fc5e
AS		 144
145 return NOTIFY_DONE;
146}
147
148static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
149 u8 port_num)
150{
151 struct mlx5_ib_dev *ibdev = to_mdev(device);
152 struct net_device *ndev;
153
88621dfe
AH		 154 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
155 if (ndev)
156 return ndev;
157
fc24fc5e
AS		 158 /* Ensure ndev does not disappear before we invoke dev_hold()
159 */
160 read_lock(&ibdev->roce.netdev_lock);
161 ndev = ibdev->roce.netdev;
162 if (ndev)
163 dev_hold(ndev);
164 read_unlock(&ibdev->roce.netdev_lock);
165
166 return ndev;
167}
168
3f89a643
AS		 169static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
170 struct ib_port_attr *props)
171{
172 struct mlx5_ib_dev *dev = to_mdev(device);
88621dfe 173 struct net_device *ndev, *upper;
3f89a643 174 enum ib_mtu ndev_ib_mtu;
c876a1b7 175 u16 qkey_viol_cntr;
3f89a643
AS		 176
177 memset(props, 0, sizeof(*props));
178
179 props->port_cap_flags |= IB_PORT_CM_SUP;
180 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
181
182 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
183 roce_address_table_size);
184 props->max_mtu = IB_MTU_4096;
185 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
186 props->pkey_tbl_len = 1;
187 props->state = IB_PORT_DOWN;
188 props->phys_state = 3;
189
c876a1b7
LR		 190 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
191 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643
AS		 192
193 ndev = mlx5_ib_get_netdev(device, port_num);
194 if (!ndev)
195 return 0;
196
88621dfe
AH		 197 if (mlx5_lag_is_active(dev->mdev)) {
198 rcu_read_lock();
199 upper = netdev_master_upper_dev_get_rcu(ndev);
200 if (upper) {
201 dev_put(ndev);
202 ndev = upper;
203 dev_hold(ndev);
204 }
205 rcu_read_unlock();
206 }
207
3f89a643
AS		 208 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
209 props->state = IB_PORT_ACTIVE;
210 props->phys_state = 5;
211 }
212
213 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
214
215 dev_put(ndev);
216
217 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
218
219 props->active_width = IB_WIDTH_4X; /* TODO */
220 props->active_speed = IB_SPEED_QDR; /* TODO */
221
222 return 0;
223}
224
3cca2606
AS		 225static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
226 const struct ib_gid_attr *attr,
227 void *mlx5_addr)
228{
229#define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
230 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
231 source_l3_address);
232 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
233 source_mac_47_32);
234
235 if (!gid)
236 return;
237
238 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
239
240 if (is_vlan_dev(attr->ndev)) {
241 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
242 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
243 }
244
245 switch (attr->gid_type) {
246 case IB_GID_TYPE_IB:
247 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
248 break;
249 case IB_GID_TYPE_ROCE_UDP_ENCAP:
250 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
251 break;
252
253 default:
254 WARN_ON(true);
255 }
256
257 if (attr->gid_type != IB_GID_TYPE_IB) {
258 if (ipv6_addr_v4mapped((void *)gid))
259 MLX5_SET_RA(mlx5_addr, roce_l3_type,
260 MLX5_ROCE_L3_TYPE_IPV4);
261 else
262 MLX5_SET_RA(mlx5_addr, roce_l3_type,
263 MLX5_ROCE_L3_TYPE_IPV6);
264 }
265
266 if ((attr->gid_type == IB_GID_TYPE_IB) ||
267 !ipv6_addr_v4mapped((void *)gid))
268 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
269 else
270 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
271}
272
273static int set_roce_addr(struct ib_device *device, u8 port_num,
274 unsigned int index,
275 const union ib_gid *gid,
276 const struct ib_gid_attr *attr)
277{
c4f287c4
SM		 278 struct mlx5_ib_dev *dev = to_mdev(device);
279 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0};
280 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
3cca2606
AS		 281 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
282 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
283
284 if (ll != IB_LINK_LAYER_ETHERNET)
285 return -EINVAL;
286
3cca2606
AS		 287 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
288
289 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
290 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
3cca2606
AS		 291 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
292}
293
294static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
295 unsigned int index, const union ib_gid *gid,
296 const struct ib_gid_attr *attr,
297 __always_unused void **context)
298{
299 return set_roce_addr(device, port_num, index, gid, attr);
300}
301
302static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
303 unsigned int index, __always_unused void **context)
304{
305 return set_roce_addr(device, port_num, index, NULL, NULL);
306}
307
2811ba51
AS		 308__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
309 int index)
310{
311 struct ib_gid_attr attr;
312 union ib_gid gid;
313
314 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
315 return 0;
316
317 if (!attr.ndev)
318 return 0;
319
320 dev_put(attr.ndev);
321
322 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
323 return 0;
324
325 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
326}
327
1b5daf11
MD		 328static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
329{
7fae6655
NO		 330 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
331 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
332 return 0;
1b5daf11
MD		 333}
334
335enum {
336 MLX5_VPORT_ACCESS_METHOD_MAD,
337 MLX5_VPORT_ACCESS_METHOD_HCA,
338 MLX5_VPORT_ACCESS_METHOD_NIC,
339};
340
341static int mlx5_get_vport_access_method(struct ib_device *ibdev)
342{
343 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
344 return MLX5_VPORT_ACCESS_METHOD_MAD;
345
ebd61f68 346 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 347 IB_LINK_LAYER_ETHERNET)
348 return MLX5_VPORT_ACCESS_METHOD_NIC;
349
350 return MLX5_VPORT_ACCESS_METHOD_HCA;
351}
352
da7525d2
EBE		 353static void get_atomic_caps(struct mlx5_ib_dev *dev,
354 struct ib_device_attr *props)
355{
356 u8 tmp;
357 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
358 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
359 u8 atomic_req_8B_endianness_mode =
360 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
361
362 /* Check if HW supports 8 bytes standard atomic operations and capable
363 * of host endianness respond
364 */
365 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
366 if (((atomic_operations & tmp) == tmp) &&
367 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
368 (atomic_req_8B_endianness_mode)) {
369 props->atomic_cap = IB_ATOMIC_HCA;
370 } else {
371 props->atomic_cap = IB_ATOMIC_NONE;
372 }
373}
374
1b5daf11
MD		 375static int mlx5_query_system_image_guid(struct ib_device *ibdev,
376 __be64 *sys_image_guid)
377{
378 struct mlx5_ib_dev *dev = to_mdev(ibdev);
379 struct mlx5_core_dev *mdev = dev->mdev;
380 u64 tmp;
381 int err;
382
383 switch (mlx5_get_vport_access_method(ibdev)) {
384 case MLX5_VPORT_ACCESS_METHOD_MAD:
385 return mlx5_query_mad_ifc_system_image_guid(ibdev,
386 sys_image_guid);
387
388 case MLX5_VPORT_ACCESS_METHOD_HCA:
389 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 390 break;
391
392 case MLX5_VPORT_ACCESS_METHOD_NIC:
393 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
394 break;
1b5daf11
MD		 395
396 default:
397 return -EINVAL;
398 }
3f89a643
AS		 399
400 if (!err)
401 *sys_image_guid = cpu_to_be64(tmp);
402
403 return err;
404
1b5daf11
MD		 405}
406
407static int mlx5_query_max_pkeys(struct ib_device *ibdev,
408 u16 *max_pkeys)
409{
410 struct mlx5_ib_dev *dev = to_mdev(ibdev);
411 struct mlx5_core_dev *mdev = dev->mdev;
412
413 switch (mlx5_get_vport_access_method(ibdev)) {
414 case MLX5_VPORT_ACCESS_METHOD_MAD:
415 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
416
417 case MLX5_VPORT_ACCESS_METHOD_HCA:
418 case MLX5_VPORT_ACCESS_METHOD_NIC:
419 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
420 pkey_table_size));
421 return 0;
422
423 default:
424 return -EINVAL;
425 }
426}
427
428static int mlx5_query_vendor_id(struct ib_device *ibdev,
429 u32 *vendor_id)
430{
431 struct mlx5_ib_dev *dev = to_mdev(ibdev);
432
433 switch (mlx5_get_vport_access_method(ibdev)) {
434 case MLX5_VPORT_ACCESS_METHOD_MAD:
435 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
436
437 case MLX5_VPORT_ACCESS_METHOD_HCA:
438 case MLX5_VPORT_ACCESS_METHOD_NIC:
439 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
440
441 default:
442 return -EINVAL;
443 }
444}
445
446static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
447 __be64 *node_guid)
448{
449 u64 tmp;
450 int err;
451
452 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
453 case MLX5_VPORT_ACCESS_METHOD_MAD:
454 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
455
456 case MLX5_VPORT_ACCESS_METHOD_HCA:
457 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 458 break;
459
460 case MLX5_VPORT_ACCESS_METHOD_NIC:
461 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
462 break;
1b5daf11
MD		 463
464 default:
465 return -EINVAL;
466 }
3f89a643
AS		 467
468 if (!err)
469 *node_guid = cpu_to_be64(tmp);
470
471 return err;
1b5daf11
MD		 472}
473
474struct mlx5_reg_node_desc {
bd99fdea 475 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 476};
477
478static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
479{
480 struct mlx5_reg_node_desc in;
481
482 if (mlx5_use_mad_ifc(dev))
483 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
484
485 memset(&in, 0, sizeof(in));
486
487 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
488 sizeof(struct mlx5_reg_node_desc),
489 MLX5_REG_NODE_DESC, 0, 0);
490}
491
e126ba97 492static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 493 struct ib_device_attr *props,
494 struct ib_udata *uhw)
e126ba97
EC		 495{
496 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 497 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 498 int err = -ENOMEM;
288c01b7 499 int max_sq_desc;
e126ba97
EC		 500 int max_rq_sg;
501 int max_sq_sg;
e0238a6a 502 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
402ca536
BW		 503 struct mlx5_ib_query_device_resp resp = {};
504 size_t resp_len;
505 u64 max_tso;
e126ba97 506
402ca536
BW		 507 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
508 if (uhw->outlen && uhw->outlen < resp_len)
509 return -EINVAL;
510 else
511 resp.response_length = resp_len;
512
513 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 514 return -EINVAL;
515
1b5daf11
MD		 516 memset(props, 0, sizeof(*props));
517 err = mlx5_query_system_image_guid(ibdev,
518 &props->sys_image_guid);
519 if (err)
520 return err;
e126ba97 521
1b5daf11 522 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 523 if (err)
1b5daf11 524 return err;
e126ba97 525
1b5daf11
MD		 526 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
527 if (err)
528 return err;
e126ba97 529
9603b61d
JM		 530 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
531 (fw_rev_min(dev->mdev) << 16) |
532 fw_rev_sub(dev->mdev);
e126ba97
EC		 533 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
534 IB_DEVICE_PORT_ACTIVE_EVENT |
535 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 536 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 537
538 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 539 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 540 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 541 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 542 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 543 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 544 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 545 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 546 if (MLX5_CAP_GEN(mdev, imaicl)) {
547 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
548 IB_DEVICE_MEM_WINDOW_TYPE_2B;
549 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 550 /* We support 'Gappy' memory registration too */
551 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 552 }
e126ba97 553 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 554 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 555 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
556 /* At this stage no support for signature handover */
557 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
558 IB_PROT_T10DIF_TYPE_2 |
559 IB_PROT_T10DIF_TYPE_3;
560 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
561 IB_GUARD_T10DIF_CSUM;
562 }
938fe83c 563 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 564 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 565
402ca536
BW		 566 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
567 if (MLX5_CAP_ETH(mdev, csum_cap))
88115fe7
BW		 568 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
569
402ca536
BW		 570 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
571 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
572 if (max_tso) {
573 resp.tso_caps.max_tso = 1 << max_tso;
574 resp.tso_caps.supported_qpts |=
575 1 << IB_QPT_RAW_PACKET;
576 resp.response_length += sizeof(resp.tso_caps);
577 }
578 }
31f69a82
YH		 579
580 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
581 resp.rss_caps.rx_hash_function =
582 MLX5_RX_HASH_FUNC_TOEPLITZ;
583 resp.rss_caps.rx_hash_fields_mask =
584 MLX5_RX_HASH_SRC_IPV4 |
585 MLX5_RX_HASH_DST_IPV4 |
586 MLX5_RX_HASH_SRC_IPV6 |
587 MLX5_RX_HASH_DST_IPV6 |
588 MLX5_RX_HASH_SRC_PORT_TCP |
589 MLX5_RX_HASH_DST_PORT_TCP |
590 MLX5_RX_HASH_SRC_PORT_UDP |
591 MLX5_RX_HASH_DST_PORT_UDP;
592 resp.response_length += sizeof(resp.rss_caps);
593 }
594 } else {
595 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
596 resp.response_length += sizeof(resp.tso_caps);
597 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
598 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 599 }
600
f0313965
ES		 601 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
602 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
603 props->device_cap_flags |= IB_DEVICE_UD_TSO;
604 }
605
cff5a0f3
MD		 606 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
607 MLX5_CAP_ETH(dev->mdev, scatter_fcs))
608 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
609
da6d6ba3
MG		 610 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
611 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
612
1b5daf11
MD		 613 props->vendor_part_id = mdev->pdev->device;
614 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 615
616 props->max_mr_size = ~0ull;
e0238a6a 617 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 618 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
619 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
620 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
621 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 622 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
623 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
624 sizeof(struct mlx5_wqe_raddr_seg)) /
625 sizeof(struct mlx5_wqe_data_seg);
e126ba97 626 props->max_sge = min(max_rq_sg, max_sq_sg);
986ef95e 627 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 628 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 629 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 630 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
631 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
632 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
633 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
634 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
635 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
636 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 637 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 638 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 639 props->max_fast_reg_page_list_len =
640 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
da7525d2 641 get_atomic_caps(dev, props);
81bea28f 642 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 643 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
644 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 645 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
646 props->max_mcast_grp;
647 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 648 props->max_ah = INT_MAX;
7c60bcbb
MB		 649 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
650 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 651
8cdd312c 652#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 653 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 654 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
655 props->odp_caps = dev->odp_caps;
656#endif
657
051f2630
LR		 658 if (MLX5_CAP_GEN(mdev, cd))
659 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
660
eff901d3
EC		 661 if (!mlx5_core_is_pf(mdev))
662 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
663
31f69a82
YH		 664 if (mlx5_ib_port_link_layer(ibdev, 1) ==
665 IB_LINK_LAYER_ETHERNET) {
666 props->rss_caps.max_rwq_indirection_tables =
667 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
668 props->rss_caps.max_rwq_indirection_table_size =
669 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
670 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
671 props->max_wq_type_rq =
672 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
673 }
674
191ded4a
BW		 675 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
676 uhw->outlen)) {
677 resp.mlx5_ib_support_multi_pkt_send_wqes =
678 MLX5_CAP_ETH(mdev, multi_pkt_send_wqe);
679 resp.response_length +=
680 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
681 }
682
683 if (field_avail(typeof(resp), reserved, uhw->outlen))
684 resp.response_length += sizeof(resp.reserved);
685
7e43a2a5
BW		 686 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
687 resp.cqe_comp_caps.max_num =
688 MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
689 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
690 resp.cqe_comp_caps.supported_format =
691 MLX5_IB_CQE_RES_FORMAT_HASH |
692 MLX5_IB_CQE_RES_FORMAT_CSUM;
693 resp.response_length += sizeof(resp.cqe_comp_caps);
694 }
695
402ca536
BW		 696 if (uhw->outlen) {
697 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
698
699 if (err)
700 return err;
701 }
702
1b5daf11 703 return 0;
e126ba97
EC		 704}
705
1b5daf11
MD		 706enum mlx5_ib_width {
707 MLX5_IB_WIDTH_1X = 1 << 0,
708 MLX5_IB_WIDTH_2X = 1 << 1,
709 MLX5_IB_WIDTH_4X = 1 << 2,
710 MLX5_IB_WIDTH_8X = 1 << 3,
711 MLX5_IB_WIDTH_12X = 1 << 4
712};
713
714static int translate_active_width(struct ib_device *ibdev, u8 active_width,
715 u8 *ib_width)
e126ba97
EC		 716{
717 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 718 int err = 0;
719
720 if (active_width & MLX5_IB_WIDTH_1X) {
721 *ib_width = IB_WIDTH_1X;
722 } else if (active_width & MLX5_IB_WIDTH_2X) {
723 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
724 (int)active_width);
725 err = -EINVAL;
726 } else if (active_width & MLX5_IB_WIDTH_4X) {
727 *ib_width = IB_WIDTH_4X;
728 } else if (active_width & MLX5_IB_WIDTH_8X) {
729 *ib_width = IB_WIDTH_8X;
730 } else if (active_width & MLX5_IB_WIDTH_12X) {
731 *ib_width = IB_WIDTH_12X;
732 } else {
733 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
734 (int)active_width);
735 err = -EINVAL;
e126ba97
EC		 736 }
737
1b5daf11
MD		 738 return err;
739}
e126ba97 740
1b5daf11
MD		 741static int mlx5_mtu_to_ib_mtu(int mtu)
742{
743 switch (mtu) {
744 case 256: return 1;
745 case 512: return 2;
746 case 1024: return 3;
747 case 2048: return 4;
748 case 4096: return 5;
749 default:
750 pr_warn("invalid mtu\n");
751 return -1;
e126ba97 752 }
1b5daf11 753}
e126ba97 754
1b5daf11
MD		 755enum ib_max_vl_num {
756 __IB_MAX_VL_0 = 1,
757 __IB_MAX_VL_0_1 = 2,
758 __IB_MAX_VL_0_3 = 3,
759 __IB_MAX_VL_0_7 = 4,
760 __IB_MAX_VL_0_14 = 5,
761};
e126ba97 762
1b5daf11
MD		 763enum mlx5_vl_hw_cap {
764 MLX5_VL_HW_0 = 1,
765 MLX5_VL_HW_0_1 = 2,
766 MLX5_VL_HW_0_2 = 3,
767 MLX5_VL_HW_0_3 = 4,
768 MLX5_VL_HW_0_4 = 5,
769 MLX5_VL_HW_0_5 = 6,
770 MLX5_VL_HW_0_6 = 7,
771 MLX5_VL_HW_0_7 = 8,
772 MLX5_VL_HW_0_14 = 15
773};
e126ba97 774
1b5daf11
MD		 775static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
776 u8 *max_vl_num)
777{
778 switch (vl_hw_cap) {
779 case MLX5_VL_HW_0:
780 *max_vl_num = __IB_MAX_VL_0;
781 break;
782 case MLX5_VL_HW_0_1:
783 *max_vl_num = __IB_MAX_VL_0_1;
784 break;
785 case MLX5_VL_HW_0_3:
786 *max_vl_num = __IB_MAX_VL_0_3;
787 break;
788 case MLX5_VL_HW_0_7:
789 *max_vl_num = __IB_MAX_VL_0_7;
790 break;
791 case MLX5_VL_HW_0_14:
792 *max_vl_num = __IB_MAX_VL_0_14;
793 break;
e126ba97 794
1b5daf11
MD		 795 default:
796 return -EINVAL;
e126ba97 797 }
e126ba97 798
1b5daf11 799 return 0;
e126ba97
EC		 800}
801
1b5daf11
MD		 802static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
803 struct ib_port_attr *props)
e126ba97 804{
1b5daf11
MD		 805 struct mlx5_ib_dev *dev = to_mdev(ibdev);
806 struct mlx5_core_dev *mdev = dev->mdev;
807 struct mlx5_hca_vport_context *rep;
046339ea
SM		 808 u16 max_mtu;
809 u16 oper_mtu;
1b5daf11
MD		 810 int err;
811 u8 ib_link_width_oper;
812 u8 vl_hw_cap;
e126ba97 813
1b5daf11
MD		 814 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
815 if (!rep) {
816 err = -ENOMEM;
e126ba97 817 goto out;
e126ba97 818 }
e126ba97 819
1b5daf11 820 memset(props, 0, sizeof(*props));
e126ba97 821
1b5daf11 822 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 823 if (err)
824 goto out;
825
1b5daf11
MD		 826 props->lid = rep->lid;
827 props->lmc = rep->lmc;
828 props->sm_lid = rep->sm_lid;
829 props->sm_sl = rep->sm_sl;
830 props->state = rep->vport_state;
831 props->phys_state = rep->port_physical_state;
832 props->port_cap_flags = rep->cap_mask1;
833 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
834 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
835 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
836 props->bad_pkey_cntr = rep->pkey_violation_counter;
837 props->qkey_viol_cntr = rep->qkey_violation_counter;
838 props->subnet_timeout = rep->subnet_timeout;
839 props->init_type_reply = rep->init_type_reply;
eff901d3 840 props->grh_required = rep->grh_required;
e126ba97 841
1b5daf11
MD		 842 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
843 if (err)
e126ba97 844 goto out;
e126ba97 845
1b5daf11
MD		 846 err = translate_active_width(ibdev, ib_link_width_oper,
847 &props->active_width);
848 if (err)
849 goto out;
d5beb7f2 850 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 851 if (err)
852 goto out;
853
facc9699 854 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 855
1b5daf11 856 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 857
facc9699 858 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 859
1b5daf11 860 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 861
1b5daf11
MD		 862 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
863 if (err)
864 goto out;
e126ba97 865
1b5daf11
MD		 866 err = translate_max_vl_num(ibdev, vl_hw_cap,
867 &props->max_vl_num);
e126ba97 868out:
1b5daf11 869 kfree(rep);
e126ba97
EC		 870 return err;
871}
872
1b5daf11
MD		 873int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
874 struct ib_port_attr *props)
e126ba97 875{
1b5daf11
MD		 876 switch (mlx5_get_vport_access_method(ibdev)) {
877 case MLX5_VPORT_ACCESS_METHOD_MAD:
878 return mlx5_query_mad_ifc_port(ibdev, port, props);
e126ba97 879
1b5daf11
MD		 880 case MLX5_VPORT_ACCESS_METHOD_HCA:
881 return mlx5_query_hca_port(ibdev, port, props);
e126ba97 882
3f89a643
AS		 883 case MLX5_VPORT_ACCESS_METHOD_NIC:
884 return mlx5_query_port_roce(ibdev, port, props);
885
1b5daf11
MD		 886 default:
887 return -EINVAL;
888 }
889}
e126ba97 890
1b5daf11
MD		 891static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
892 union ib_gid *gid)
893{
894 struct mlx5_ib_dev *dev = to_mdev(ibdev);
895 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 896
1b5daf11
MD		 897 switch (mlx5_get_vport_access_method(ibdev)) {
898 case MLX5_VPORT_ACCESS_METHOD_MAD:
899 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 900
1b5daf11
MD		 901 case MLX5_VPORT_ACCESS_METHOD_HCA:
902 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
903
904 default:
905 return -EINVAL;
906 }
e126ba97 907
e126ba97
EC		 908}
909
1b5daf11
MD		 910static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
911 u16 *pkey)
912{
913 struct mlx5_ib_dev *dev = to_mdev(ibdev);
914 struct mlx5_core_dev *mdev = dev->mdev;
915
916 switch (mlx5_get_vport_access_method(ibdev)) {
917 case MLX5_VPORT_ACCESS_METHOD_MAD:
918 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
919
920 case MLX5_VPORT_ACCESS_METHOD_HCA:
921 case MLX5_VPORT_ACCESS_METHOD_NIC:
922 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
923 pkey);
924 default:
925 return -EINVAL;
926 }
927}
e126ba97
EC		 928
929static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
930 struct ib_device_modify *props)
931{
932 struct mlx5_ib_dev *dev = to_mdev(ibdev);
933 struct mlx5_reg_node_desc in;
934 struct mlx5_reg_node_desc out;
935 int err;
936
937 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
938 return -EOPNOTSUPP;
939
940 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
941 return 0;
942
943 /*
944 * If possible, pass node desc to FW, so it can generate
945 * a 144 trap. If cmd fails, just ignore.
946 */
bd99fdea 947 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 948 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 949 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
950 if (err)
951 return err;
952
bd99fdea 953 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 954
955 return err;
956}
957
958static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
959 struct ib_port_modify *props)
960{
961 struct mlx5_ib_dev *dev = to_mdev(ibdev);
962 struct ib_port_attr attr;
963 u32 tmp;
964 int err;
965
966 mutex_lock(&dev->cap_mask_mutex);
967
968 err = mlx5_ib_query_port(ibdev, port, &attr);
969 if (err)
970 goto out;
971
972 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
973 ~props->clr_port_cap_mask;
974
9603b61d 975 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 976
977out:
978 mutex_unlock(&dev->cap_mask_mutex);
979 return err;
980}
981
982static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
983 struct ib_udata *udata)
984{
985 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 986 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
987 struct mlx5_ib_alloc_ucontext_resp resp = {};
e126ba97
EC		 988 struct mlx5_ib_ucontext *context;
989 struct mlx5_uuar_info *uuari;
990 struct mlx5_uar *uars;
c1be5232 991 int gross_uuars;
e126ba97 992 int num_uars;
78c0f98c 993 int ver;
e126ba97
EC		 994 int uuarn;
995 int err;
996 int i;
f241e749 997 size_t reqlen;
a168a41c
MD		 998 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
999 max_cqe_version);
e126ba97
EC		 1000
1001 if (!dev->ib_active)
1002 return ERR_PTR(-EAGAIN);
1003
dfbee859
HA		 1004 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
1005 return ERR_PTR(-EINVAL);
1006
78c0f98c
EC		 1007 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
1008 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1009 ver = 0;
a168a41c 1010 else if (reqlen >= min_req_v2)
78c0f98c
EC		 1011 ver = 2;
1012 else
1013 return ERR_PTR(-EINVAL);
1014
b368d7cb 1015 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
e126ba97
EC		 1016 if (err)
1017 return ERR_PTR(err);
1018
b368d7cb 1019 if (req.flags)
78c0f98c
EC		 1020 return ERR_PTR(-EINVAL);
1021
e126ba97
EC		 1022 if (req.total_num_uuars > MLX5_MAX_UUARS)
1023 return ERR_PTR(-ENOMEM);
1024
1025 if (req.total_num_uuars == 0)
1026 return ERR_PTR(-EINVAL);
1027
f72300c5 1028 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 1029 return ERR_PTR(-EOPNOTSUPP);
1030
1031 if (reqlen > sizeof(req) &&
1032 !ib_is_udata_cleared(udata, sizeof(req),
dfbee859 1033 reqlen - sizeof(req)))
b368d7cb
MB		 1034 return ERR_PTR(-EOPNOTSUPP);
1035
c1be5232
EC		 1036 req.total_num_uuars = ALIGN(req.total_num_uuars,
1037 MLX5_NON_FP_BF_REGS_PER_PAGE);
e126ba97
EC		 1038 if (req.num_low_latency_uuars > req.total_num_uuars - 1)
1039 return ERR_PTR(-EINVAL);
1040
c1be5232
EC		 1041 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
1042 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
938fe83c 1043 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1044 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1045 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
938fe83c
SM		 1046 resp.cache_line_size = L1_CACHE_BYTES;
1047 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1048 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1049 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1050 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1051 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1052 resp.cqe_version = min_t(__u8,
1053 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1054 req.max_cqe_version);
b368d7cb
MB		 1055 resp.response_length = min(offsetof(typeof(resp), response_length) +
1056 sizeof(resp.response_length), udata->outlen);
e126ba97
EC		 1057
1058 context = kzalloc(sizeof(*context), GFP_KERNEL);
1059 if (!context)
1060 return ERR_PTR(-ENOMEM);
1061
1062 uuari = &context->uuari;
1063 mutex_init(&uuari->lock);
1064 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
1065 if (!uars) {
1066 err = -ENOMEM;
1067 goto out_ctx;
1068 }
1069
c1be5232 1070 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
e126ba97
EC		 1071 sizeof(*uuari->bitmap),
1072 GFP_KERNEL);
1073 if (!uuari->bitmap) {
1074 err = -ENOMEM;
1075 goto out_uar_ctx;
1076 }
1077 /*
1078 * clear all fast path uuars
1079 */
c1be5232 1080 for (i = 0; i < gross_uuars; i++) {
e126ba97
EC		 1081 uuarn = i & 3;
1082 if (uuarn == 2 || uuarn == 3)
1083 set_bit(i, uuari->bitmap);
1084 }
1085
c1be5232 1086 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
e126ba97
EC		 1087 if (!uuari->count) {
1088 err = -ENOMEM;
1089 goto out_bitmap;
1090 }
1091
1092 for (i = 0; i < num_uars; i++) {
9603b61d 1093 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
e126ba97
EC		 1094 if (err)
1095 goto out_count;
1096 }
1097
b4cfe447
HE		 1098#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1099 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1100#endif
1101
146d2f1a 1102 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1103 err = mlx5_core_alloc_transport_domain(dev->mdev,
1104 &context->tdn);
1105 if (err)
1106 goto out_uars;
1107 }
1108
7c2344c3 1109 INIT_LIST_HEAD(&context->vma_private_list);
e126ba97
EC		 1110 INIT_LIST_HEAD(&context->db_page_list);
1111 mutex_init(&context->db_page_mutex);
1112
1113 resp.tot_uuars = req.total_num_uuars;
938fe83c 1114 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
b368d7cb 1115
f72300c5
HA		 1116 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1117 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1118
402ca536 1119 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1120 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1121 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1122 resp.response_length += sizeof(resp.cmds_supp_uhw);
1123 }
1124
bc5c6eed
NO		 1125 /*
1126 * We don't want to expose information from the PCI bar that is located
1127 * after 4096 bytes, so if the arch only supports larger pages, let's
1128 * pretend we don't support reading the HCA's core clock. This is also
1129 * forced by mmap function.
1130 */
1131 if (PAGE_SIZE <= 4096 &&
1132 field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
b368d7cb
MB		 1133 resp.comp_mask |=
1134 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1135 resp.hca_core_clock_offset =
1136 offsetof(struct mlx5_init_seg, internal_timer_h) %
1137 PAGE_SIZE;
f72300c5 1138 resp.response_length += sizeof(resp.hca_core_clock_offset) +
402ca536 1139 sizeof(resp.reserved2);
b368d7cb
MB		 1140 }
1141
1142 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1143 if (err)
146d2f1a 1144 goto out_td;
e126ba97 1145
78c0f98c 1146 uuari->ver = ver;
e126ba97
EC		 1147 uuari->num_low_latency_uuars = req.num_low_latency_uuars;
1148 uuari->uars = uars;
1149 uuari->num_uars = num_uars;
f72300c5
HA		 1150 context->cqe_version = resp.cqe_version;
1151
e126ba97
EC		 1152 return &context->ibucontext;
1153
146d2f1a 1154out_td:
1155 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1156 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1157
e126ba97
EC		 1158out_uars:
1159 for (i--; i >= 0; i--)
9603b61d 1160 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
e126ba97
EC		 1161out_count:
1162 kfree(uuari->count);
1163
1164out_bitmap:
1165 kfree(uuari->bitmap);
1166
1167out_uar_ctx:
1168 kfree(uars);
1169
1170out_ctx:
1171 kfree(context);
1172 return ERR_PTR(err);
1173}
1174
1175static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1176{
1177 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1178 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1179 struct mlx5_uuar_info *uuari = &context->uuari;
1180 int i;
1181
146d2f1a 1182 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1183 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1184
e126ba97 1185 for (i = 0; i < uuari->num_uars; i++) {
9603b61d 1186 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
e126ba97
EC		 1187 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
1188 }
1189
1190 kfree(uuari->count);
1191 kfree(uuari->bitmap);
1192 kfree(uuari->uars);
1193 kfree(context);
1194
1195 return 0;
1196}
1197
1198static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1199{
9603b61d 1200 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
e126ba97
EC		 1201}
1202
1203static int get_command(unsigned long offset)
1204{
1205 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1206}
1207
1208static int get_arg(unsigned long offset)
1209{
1210 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1211}
1212
1213static int get_index(unsigned long offset)
1214{
1215 return get_arg(offset);
1216}
1217
7c2344c3
MG		 1218static void mlx5_ib_vma_open(struct vm_area_struct *area)
1219{
1220 /* vma_open is called when a new VMA is created on top of our VMA. This
1221 * is done through either mremap flow or split_vma (usually due to
1222 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1223 * as this VMA is strongly hardware related. Therefore we set the
1224 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1225 * calling us again and trying to do incorrect actions. We assume that
1226 * the original VMA size is exactly a single page, and therefore all
1227 * "splitting" operation will not happen to it.
1228 */
1229 area->vm_ops = NULL;
1230}
1231
1232static void mlx5_ib_vma_close(struct vm_area_struct *area)
1233{
1234 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1235
1236 /* It's guaranteed that all VMAs opened on a FD are closed before the
1237 * file itself is closed, therefore no sync is needed with the regular
1238 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1239 * However need a sync with accessing the vma as part of
1240 * mlx5_ib_disassociate_ucontext.
1241 * The close operation is usually called under mm->mmap_sem except when
1242 * process is exiting.
1243 * The exiting case is handled explicitly as part of
1244 * mlx5_ib_disassociate_ucontext.
1245 */
1246 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1247
1248 /* setting the vma context pointer to null in the mlx5_ib driver's
1249 * private data, to protect a race condition in
1250 * mlx5_ib_disassociate_ucontext().
1251 */
1252 mlx5_ib_vma_priv_data->vma = NULL;
1253 list_del(&mlx5_ib_vma_priv_data->list);
1254 kfree(mlx5_ib_vma_priv_data);
1255}
1256
1257static const struct vm_operations_struct mlx5_ib_vm_ops = {
1258 .open = mlx5_ib_vma_open,
1259 .close = mlx5_ib_vma_close
1260};
1261
1262static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1263 struct mlx5_ib_ucontext *ctx)
1264{
1265 struct mlx5_ib_vma_private_data *vma_prv;
1266 struct list_head *vma_head = &ctx->vma_private_list;
1267
1268 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1269 if (!vma_prv)
1270 return -ENOMEM;
1271
1272 vma_prv->vma = vma;
1273 vma->vm_private_data = vma_prv;
1274 vma->vm_ops = &mlx5_ib_vm_ops;
1275
1276 list_add(&vma_prv->list, vma_head);
1277
1278 return 0;
1279}
1280
1281static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1282{
1283 int ret;
1284 struct vm_area_struct *vma;
1285 struct mlx5_ib_vma_private_data *vma_private, *n;
1286 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1287 struct task_struct *owning_process = NULL;
1288 struct mm_struct *owning_mm = NULL;
1289
1290 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1291 if (!owning_process)
1292 return;
1293
1294 owning_mm = get_task_mm(owning_process);
1295 if (!owning_mm) {
1296 pr_info("no mm, disassociate ucontext is pending task termination\n");
1297 while (1) {
1298 put_task_struct(owning_process);
1299 usleep_range(1000, 2000);
1300 owning_process = get_pid_task(ibcontext->tgid,
1301 PIDTYPE_PID);
1302 if (!owning_process ||
1303 owning_process->state == TASK_DEAD) {
1304 pr_info("disassociate ucontext done, task was terminated\n");
1305 /* in case task was dead need to release the
1306 * task struct.
1307 */
1308 if (owning_process)
1309 put_task_struct(owning_process);
1310 return;
1311 }
1312 }
1313 }
1314
1315 /* need to protect from a race on closing the vma as part of
1316 * mlx5_ib_vma_close.
1317 */
1318 down_read(&owning_mm->mmap_sem);
1319 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1320 list) {
1321 vma = vma_private->vma;
1322 ret = zap_vma_ptes(vma, vma->vm_start,
1323 PAGE_SIZE);
1324 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1325 /* context going to be destroyed, should
1326 * not access ops any more.
1327 */
1328 vma->vm_ops = NULL;
1329 list_del(&vma_private->list);
1330 kfree(vma_private);
1331 }
1332 up_read(&owning_mm->mmap_sem);
1333 mmput(owning_mm);
1334 put_task_struct(owning_process);
1335}
1336
37aa5c36
GL		 1337static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1338{
1339 switch (cmd) {
1340 case MLX5_IB_MMAP_WC_PAGE:
1341 return "WC";
1342 case MLX5_IB_MMAP_REGULAR_PAGE:
1343 return "best effort WC";
1344 case MLX5_IB_MMAP_NC_PAGE:
1345 return "NC";
1346 default:
1347 return NULL;
1348 }
1349}
1350
1351static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 1352 struct vm_area_struct *vma,
1353 struct mlx5_ib_ucontext *context)
37aa5c36 1354{
7c2344c3 1355 struct mlx5_uuar_info *uuari = &context->uuari;
37aa5c36
GL		 1356 int err;
1357 unsigned long idx;
1358 phys_addr_t pfn, pa;
1359 pgprot_t prot;
1360
1361 switch (cmd) {
1362 case MLX5_IB_MMAP_WC_PAGE:
1363/* Some architectures don't support WC memory */
1364#if defined(CONFIG_X86)
1365 if (!pat_enabled())
1366 return -EPERM;
1367#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1368 return -EPERM;
1369#endif
1370 /* fall through */
1371 case MLX5_IB_MMAP_REGULAR_PAGE:
1372 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1373 prot = pgprot_writecombine(vma->vm_page_prot);
1374 break;
1375 case MLX5_IB_MMAP_NC_PAGE:
1376 prot = pgprot_noncached(vma->vm_page_prot);
1377 break;
1378 default:
1379 return -EINVAL;
1380 }
1381
1382 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1383 return -EINVAL;
1384
1385 idx = get_index(vma->vm_pgoff);
1386 if (idx >= uuari->num_uars)
1387 return -EINVAL;
1388
1389 pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1390 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1391
1392 vma->vm_page_prot = prot;
1393 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1394 PAGE_SIZE, vma->vm_page_prot);
1395 if (err) {
1396 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1397 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1398 return -EAGAIN;
1399 }
1400
1401 pa = pfn << PAGE_SHIFT;
1402 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1403 vma->vm_start, &pa);
1404
7c2344c3 1405 return mlx5_ib_set_vma_data(vma, context);
37aa5c36
GL		 1406}
1407
e126ba97
EC		 1408static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1409{
1410 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1411 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 1412 unsigned long command;
e126ba97
EC		 1413 phys_addr_t pfn;
1414
1415 command = get_command(vma->vm_pgoff);
1416 switch (command) {
37aa5c36
GL		 1417 case MLX5_IB_MMAP_WC_PAGE:
1418 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 1419 case MLX5_IB_MMAP_REGULAR_PAGE:
7c2344c3 1420 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 1421
1422 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1423 return -ENOSYS;
1424
d69e3bcf 1425 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 1426 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1427 return -EINVAL;
1428
6cbac1e4 1429 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 1430 return -EPERM;
1431
1432 /* Don't expose to user-space information it shouldn't have */
1433 if (PAGE_SIZE > 4096)
1434 return -EOPNOTSUPP;
1435
1436 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1437 pfn = (dev->mdev->iseg_base +
1438 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1439 PAGE_SHIFT;
1440 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1441 PAGE_SIZE, vma->vm_page_prot))
1442 return -EAGAIN;
1443
1444 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1445 vma->vm_start,
1446 (unsigned long long)pfn << PAGE_SHIFT);
1447 break;
d69e3bcf 1448
e126ba97
EC		 1449 default:
1450 return -EINVAL;
1451 }
1452
1453 return 0;
1454}
1455
e126ba97
EC		 1456static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1457 struct ib_ucontext *context,
1458 struct ib_udata *udata)
1459{
1460 struct mlx5_ib_alloc_pd_resp resp;
1461 struct mlx5_ib_pd *pd;
1462 int err;
1463
1464 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1465 if (!pd)
1466 return ERR_PTR(-ENOMEM);
1467
9603b61d 1468 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 1469 if (err) {
1470 kfree(pd);
1471 return ERR_PTR(err);
1472 }
1473
1474 if (context) {
1475 resp.pdn = pd->pdn;
1476 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 1477 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 1478 kfree(pd);
1479 return ERR_PTR(-EFAULT);
1480 }
e126ba97
EC		 1481 }
1482
1483 return &pd->ibpd;
1484}
1485
1486static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1487{
1488 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1489 struct mlx5_ib_pd *mpd = to_mpd(pd);
1490
9603b61d 1491 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 1492 kfree(mpd);
1493
1494 return 0;
1495}
1496
466fa6d2
MG		 1497enum {
1498 MATCH_CRITERIA_ENABLE_OUTER_BIT,
1499 MATCH_CRITERIA_ENABLE_MISC_BIT,
1500 MATCH_CRITERIA_ENABLE_INNER_BIT
1501};
1502
1503#define HEADER_IS_ZERO(match_criteria, headers) \
1504 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1505 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 1506
466fa6d2 1507static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 1508{
466fa6d2 1509 u8 match_criteria_enable;
038d2ef8 1510
466fa6d2
MG		 1511 match_criteria_enable =
1512 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1513 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1514 match_criteria_enable |=
1515 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1516 MATCH_CRITERIA_ENABLE_MISC_BIT;
1517 match_criteria_enable |=
1518 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1519 MATCH_CRITERIA_ENABLE_INNER_BIT;
1520
1521 return match_criteria_enable;
038d2ef8
MG		 1522}
1523
ca0d4753
MG		 1524static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1525{
1526 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1527 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
038d2ef8
MG		 1528}
1529
2d1e697e
MR		 1530static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
1531 bool inner)
1532{
1533 if (inner) {
1534 MLX5_SET(fte_match_set_misc,
1535 misc_c, inner_ipv6_flow_label, mask);
1536 MLX5_SET(fte_match_set_misc,
1537 misc_v, inner_ipv6_flow_label, val);
1538 } else {
1539 MLX5_SET(fte_match_set_misc,
1540 misc_c, outer_ipv6_flow_label, mask);
1541 MLX5_SET(fte_match_set_misc,
1542 misc_v, outer_ipv6_flow_label, val);
1543 }
1544}
1545
ca0d4753
MG		 1546static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1547{
1548 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1549 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1550 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1551 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1552}
1553
c47ac6ae
MG		 1554#define LAST_ETH_FIELD vlan_tag
1555#define LAST_IB_FIELD sl
ca0d4753 1556#define LAST_IPV4_FIELD tos
466fa6d2 1557#define LAST_IPV6_FIELD traffic_class
c47ac6ae 1558#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 1559#define LAST_TUNNEL_FIELD tunnel_id
c47ac6ae
MG		 1560
1561/* Field is the last supported field */
1562#define FIELDS_NOT_SUPPORTED(filter, field)\
1563 memchr_inv((void *)&filter.field +\
1564 sizeof(filter.field), 0,\
1565 sizeof(filter) -\
1566 offsetof(typeof(filter), field) -\
1567 sizeof(filter.field))
1568
038d2ef8 1569static int parse_flow_attr(u32 *match_c, u32 *match_v,
dd063d0e 1570 const union ib_flow_spec *ib_spec)
038d2ef8 1571{
466fa6d2
MG		 1572 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1573 misc_parameters);
1574 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1575 misc_parameters);
2d1e697e
MR		 1576 void *headers_c;
1577 void *headers_v;
1578
1579 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
1580 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1581 inner_headers);
1582 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1583 inner_headers);
1584 } else {
1585 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1586 outer_headers);
1587 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1588 outer_headers);
1589 }
466fa6d2 1590
2d1e697e 1591 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 1592 case IB_FLOW_SPEC_ETH:
c47ac6ae
MG		 1593 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1594 return -ENOTSUPP;
038d2ef8 1595
2d1e697e 1596 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1597 dmac_47_16),
1598 ib_spec->eth.mask.dst_mac);
2d1e697e 1599 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1600 dmac_47_16),
1601 ib_spec->eth.val.dst_mac);
1602
2d1e697e 1603 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 1604 smac_47_16),
1605 ib_spec->eth.mask.src_mac);
2d1e697e 1606 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 1607 smac_47_16),
1608 ib_spec->eth.val.src_mac);
1609
038d2ef8 1610 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 1611 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 1612 vlan_tag, 1);
2d1e697e 1613 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1614 vlan_tag, 1);
1615
2d1e697e 1616 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 1617 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 1618 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1619 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1620
2d1e697e 1621 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1622 first_cfi,
1623 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 1624 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1625 first_cfi,
1626 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1627
2d1e697e 1628 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1629 first_prio,
1630 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 1631 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1632 first_prio,
1633 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1634 }
2d1e697e 1635 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 1636 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 1637 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1638 ethertype, ntohs(ib_spec->eth.val.ether_type));
1639 break;
1640 case IB_FLOW_SPEC_IPV4:
c47ac6ae
MG		 1641 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1642 return -ENOTSUPP;
038d2ef8 1643
2d1e697e 1644 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 1645 ethertype, 0xffff);
2d1e697e 1646 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1647 ethertype, ETH_P_IP);
1648
2d1e697e 1649 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1650 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1651 &ib_spec->ipv4.mask.src_ip,
1652 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 1653 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1654 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1655 &ib_spec->ipv4.val.src_ip,
1656 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 1657 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1658 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1659 &ib_spec->ipv4.mask.dst_ip,
1660 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 1661 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1662 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1663 &ib_spec->ipv4.val.dst_ip,
1664 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 1665
2d1e697e 1666 set_tos(headers_c, headers_v,
ca0d4753
MG		 1667 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1668
2d1e697e 1669 set_proto(headers_c, headers_v,
ca0d4753 1670 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
038d2ef8 1671 break;
026bae0c 1672 case IB_FLOW_SPEC_IPV6:
c47ac6ae
MG		 1673 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1674 return -ENOTSUPP;
026bae0c 1675
2d1e697e 1676 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
026bae0c 1677 ethertype, 0xffff);
2d1e697e 1678 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 1679 ethertype, ETH_P_IPV6);
1680
2d1e697e 1681 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 1682 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1683 &ib_spec->ipv6.mask.src_ip,
1684 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 1685 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 1686 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1687 &ib_spec->ipv6.val.src_ip,
1688 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 1689 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 1690 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1691 &ib_spec->ipv6.mask.dst_ip,
1692 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 1693 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 1694 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1695 &ib_spec->ipv6.val.dst_ip,
1696 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 1697
2d1e697e 1698 set_tos(headers_c, headers_v,
466fa6d2
MG		 1699 ib_spec->ipv6.mask.traffic_class,
1700 ib_spec->ipv6.val.traffic_class);
1701
2d1e697e 1702 set_proto(headers_c, headers_v,
466fa6d2
MG		 1703 ib_spec->ipv6.mask.next_hdr,
1704 ib_spec->ipv6.val.next_hdr);
1705
2d1e697e
MR		 1706 set_flow_label(misc_params_c, misc_params_v,
1707 ntohl(ib_spec->ipv6.mask.flow_label),
1708 ntohl(ib_spec->ipv6.val.flow_label),
1709 ib_spec->type & IB_FLOW_SPEC_INNER);
1710
026bae0c 1711 break;
038d2ef8 1712 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 1713 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1714 LAST_TCP_UDP_FIELD))
1715 return -ENOTSUPP;
038d2ef8 1716
2d1e697e 1717 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 1718 0xff);
2d1e697e 1719 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 1720 IPPROTO_TCP);
1721
2d1e697e 1722 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 1723 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 1724 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 1725 ntohs(ib_spec->tcp_udp.val.src_port));
1726
2d1e697e 1727 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 1728 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 1729 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 1730 ntohs(ib_spec->tcp_udp.val.dst_port));
1731 break;
1732 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 1733 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1734 LAST_TCP_UDP_FIELD))
1735 return -ENOTSUPP;
038d2ef8 1736
2d1e697e 1737 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 1738 0xff);
2d1e697e 1739 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 1740 IPPROTO_UDP);
1741
2d1e697e 1742 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 1743 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 1744 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 1745 ntohs(ib_spec->tcp_udp.val.src_port));
1746
2d1e697e 1747 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 1748 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 1749 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 1750 ntohs(ib_spec->tcp_udp.val.dst_port));
1751 break;
ffb30d8f
MR		 1752 case IB_FLOW_SPEC_VXLAN_TUNNEL:
1753 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
1754 LAST_TUNNEL_FIELD))
1755 return -ENOTSUPP;
1756
1757 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
1758 ntohl(ib_spec->tunnel.mask.tunnel_id));
1759 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
1760 ntohl(ib_spec->tunnel.val.tunnel_id));
1761 break;
038d2ef8
MG		 1762 default:
1763 return -EINVAL;
1764 }
1765
1766 return 0;
1767}
1768
1769/* If a flow could catch both multicast and unicast packets,
1770 * it won't fall into the multicast flow steering table and this rule
1771 * could steal other multicast packets.
1772 */
1773static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1774{
1775 struct ib_flow_spec_eth *eth_spec;
1776
1777 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1778 ib_attr->size < sizeof(struct ib_flow_attr) +
1779 sizeof(struct ib_flow_spec_eth) ||
1780 ib_attr->num_of_specs < 1)
1781 return false;
1782
1783 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1784 if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1785 eth_spec->size != sizeof(*eth_spec))
1786 return false;
1787
1788 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1789 is_multicast_ether_addr(eth_spec->val.dst_mac);
1790}
1791
dd063d0e 1792static bool is_valid_attr(const struct ib_flow_attr *flow_attr)
038d2ef8
MG		 1793{
1794 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1795 bool has_ipv4_spec = false;
1796 bool eth_type_ipv4 = true;
1797 unsigned int spec_index;
1798
1799 /* Validate that ethertype is correct */
1800 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1801 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1802 ib_spec->eth.mask.ether_type) {
1803 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1804 ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1805 eth_type_ipv4 = false;
1806 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1807 has_ipv4_spec = true;
1808 }
1809 ib_spec = (void *)ib_spec + ib_spec->size;
1810 }
1811 return !has_ipv4_spec || eth_type_ipv4;
1812}
1813
1814static void put_flow_table(struct mlx5_ib_dev *dev,
1815 struct mlx5_ib_flow_prio *prio, bool ft_added)
1816{
1817 prio->refcount -= !!ft_added;
1818 if (!prio->refcount) {
1819 mlx5_destroy_flow_table(prio->flow_table);
1820 prio->flow_table = NULL;
1821 }
1822}
1823
1824static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1825{
1826 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1827 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1828 struct mlx5_ib_flow_handler,
1829 ibflow);
1830 struct mlx5_ib_flow_handler *iter, *tmp;
1831
1832 mutex_lock(&dev->flow_db.lock);
1833
1834 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 1835 mlx5_del_flow_rules(iter->rule);
cc0e5d42 1836 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 1837 list_del(&iter->list);
1838 kfree(iter);
1839 }
1840
74491de9 1841 mlx5_del_flow_rules(handler->rule);
5497adc6 1842 put_flow_table(dev, handler->prio, true);
038d2ef8
MG		 1843 mutex_unlock(&dev->flow_db.lock);
1844
1845 kfree(handler);
1846
1847 return 0;
1848}
1849
35d19011
MG		 1850static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1851{
1852 priority *= 2;
1853 if (!dont_trap)
1854 priority++;
1855 return priority;
1856}
1857
cc0e5d42
MG		 1858enum flow_table_type {
1859 MLX5_IB_FT_RX,
1860 MLX5_IB_FT_TX
1861};
1862
038d2ef8
MG		 1863#define MLX5_FS_MAX_TYPES 10
1864#define MLX5_FS_MAX_ENTRIES 32000UL
1865static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 1866 struct ib_flow_attr *flow_attr,
1867 enum flow_table_type ft_type)
038d2ef8 1868{
35d19011 1869 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 1870 struct mlx5_flow_namespace *ns = NULL;
1871 struct mlx5_ib_flow_prio *prio;
1872 struct mlx5_flow_table *ft;
1873 int num_entries;
1874 int num_groups;
1875 int priority;
1876 int err = 0;
1877
1878 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 1879 if (flow_is_multicast_only(flow_attr) &&
1880 !dont_trap)
038d2ef8
MG		 1881 priority = MLX5_IB_FLOW_MCAST_PRIO;
1882 else
35d19011
MG		 1883 priority = ib_prio_to_core_prio(flow_attr->priority,
1884 dont_trap);
038d2ef8
MG		 1885 ns = mlx5_get_flow_namespace(dev->mdev,
1886 MLX5_FLOW_NAMESPACE_BYPASS);
1887 num_entries = MLX5_FS_MAX_ENTRIES;
1888 num_groups = MLX5_FS_MAX_TYPES;
1889 prio = &dev->flow_db.prios[priority];
1890 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1891 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1892 ns = mlx5_get_flow_namespace(dev->mdev,
1893 MLX5_FLOW_NAMESPACE_LEFTOVERS);
1894 build_leftovers_ft_param(&priority,
1895 &num_entries,
1896 &num_groups);
1897 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 1898 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
1899 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
1900 allow_sniffer_and_nic_rx_shared_tir))
1901 return ERR_PTR(-ENOTSUPP);
1902
1903 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
1904 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
1905 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
1906
1907 prio = &dev->flow_db.sniffer[ft_type];
1908 priority = 0;
1909 num_entries = 1;
1910 num_groups = 1;
038d2ef8
MG		 1911 }
1912
1913 if (!ns)
1914 return ERR_PTR(-ENOTSUPP);
1915
1916 ft = prio->flow_table;
1917 if (!ft) {
1918 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
1919 num_entries,
d63cd286
MG		 1920 num_groups,
1921 0);
038d2ef8
MG		 1922
1923 if (!IS_ERR(ft)) {
1924 prio->refcount = 0;
1925 prio->flow_table = ft;
1926 } else {
1927 err = PTR_ERR(ft);
1928 }
1929 }
1930
1931 return err ? ERR_PTR(err) : prio;
1932}
1933
1934static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1935 struct mlx5_ib_flow_prio *ft_prio,
dd063d0e 1936 const struct ib_flow_attr *flow_attr,
038d2ef8
MG		 1937 struct mlx5_flow_destination *dst)
1938{
1939 struct mlx5_flow_table *ft = ft_prio->flow_table;
1940 struct mlx5_ib_flow_handler *handler;
c5bb1730 1941 struct mlx5_flow_spec *spec;
dd063d0e 1942 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 1943 unsigned int spec_index;
35d19011 1944 u32 action;
038d2ef8
MG		 1945 int err = 0;
1946
1947 if (!is_valid_attr(flow_attr))
1948 return ERR_PTR(-EINVAL);
1949
c5bb1730 1950 spec = mlx5_vzalloc(sizeof(*spec));
038d2ef8 1951 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 1952 if (!handler || !spec) {
038d2ef8
MG		 1953 err = -ENOMEM;
1954 goto free;
1955 }
1956
1957 INIT_LIST_HEAD(&handler->list);
1958
1959 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
c5bb1730
MG		 1960 err = parse_flow_attr(spec->match_criteria,
1961 spec->match_value, ib_flow);
038d2ef8
MG		 1962 if (err < 0)
1963 goto free;
1964
1965 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1966 }
1967
466fa6d2 1968 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
35d19011
MG		 1969 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
1970 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
74491de9 1971 handler->rule = mlx5_add_flow_rules(ft, spec,
35d19011 1972 action,
038d2ef8 1973 MLX5_FS_DEFAULT_FLOW_TAG,
74491de9 1974 dst, 1);
038d2ef8
MG		 1975
1976 if (IS_ERR(handler->rule)) {
1977 err = PTR_ERR(handler->rule);
1978 goto free;
1979 }
1980
d9d4980a 1981 ft_prio->refcount++;
5497adc6 1982 handler->prio = ft_prio;
038d2ef8
MG		 1983
1984 ft_prio->flow_table = ft;
1985free:
1986 if (err)
1987 kfree(handler);
c5bb1730 1988 kvfree(spec);
038d2ef8
MG		 1989 return err ? ERR_PTR(err) : handler;
1990}
1991
35d19011
MG		 1992static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
1993 struct mlx5_ib_flow_prio *ft_prio,
1994 struct ib_flow_attr *flow_attr,
1995 struct mlx5_flow_destination *dst)
1996{
1997 struct mlx5_ib_flow_handler *handler_dst = NULL;
1998 struct mlx5_ib_flow_handler *handler = NULL;
1999
2000 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2001 if (!IS_ERR(handler)) {
2002 handler_dst = create_flow_rule(dev, ft_prio,
2003 flow_attr, dst);
2004 if (IS_ERR(handler_dst)) {
74491de9 2005 mlx5_del_flow_rules(handler->rule);
d9d4980a 2006 ft_prio->refcount--;
35d19011
MG		 2007 kfree(handler);
2008 handler = handler_dst;
2009 } else {
2010 list_add(&handler_dst->list, &handler->list);
2011 }
2012 }
2013
2014 return handler;
2015}
038d2ef8
MG		 2016enum {
2017 LEFTOVERS_MC,
2018 LEFTOVERS_UC,
2019};
2020
2021static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2022 struct mlx5_ib_flow_prio *ft_prio,
2023 struct ib_flow_attr *flow_attr,
2024 struct mlx5_flow_destination *dst)
2025{
2026 struct mlx5_ib_flow_handler *handler_ucast = NULL;
2027 struct mlx5_ib_flow_handler *handler = NULL;
2028
2029 static struct {
2030 struct ib_flow_attr flow_attr;
2031 struct ib_flow_spec_eth eth_flow;
2032 } leftovers_specs[] = {
2033 [LEFTOVERS_MC] = {
2034 .flow_attr = {
2035 .num_of_specs = 1,
2036 .size = sizeof(leftovers_specs[0])
2037 },
2038 .eth_flow = {
2039 .type = IB_FLOW_SPEC_ETH,
2040 .size = sizeof(struct ib_flow_spec_eth),
2041 .mask = {.dst_mac = {0x1} },
2042 .val = {.dst_mac = {0x1} }
2043 }
2044 },
2045 [LEFTOVERS_UC] = {
2046 .flow_attr = {
2047 .num_of_specs = 1,
2048 .size = sizeof(leftovers_specs[0])
2049 },
2050 .eth_flow = {
2051 .type = IB_FLOW_SPEC_ETH,
2052 .size = sizeof(struct ib_flow_spec_eth),
2053 .mask = {.dst_mac = {0x1} },
2054 .val = {.dst_mac = {} }
2055 }
2056 }
2057 };
2058
2059 handler = create_flow_rule(dev, ft_prio,
2060 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2061 dst);
2062 if (!IS_ERR(handler) &&
2063 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2064 handler_ucast = create_flow_rule(dev, ft_prio,
2065 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2066 dst);
2067 if (IS_ERR(handler_ucast)) {
74491de9 2068 mlx5_del_flow_rules(handler->rule);
d9d4980a 2069 ft_prio->refcount--;
038d2ef8
MG		 2070 kfree(handler);
2071 handler = handler_ucast;
2072 } else {
2073 list_add(&handler_ucast->list, &handler->list);
2074 }
2075 }
2076
2077 return handler;
2078}
2079
cc0e5d42
MG		 2080static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2081 struct mlx5_ib_flow_prio *ft_rx,
2082 struct mlx5_ib_flow_prio *ft_tx,
2083 struct mlx5_flow_destination *dst)
2084{
2085 struct mlx5_ib_flow_handler *handler_rx;
2086 struct mlx5_ib_flow_handler *handler_tx;
2087 int err;
2088 static const struct ib_flow_attr flow_attr = {
2089 .num_of_specs = 0,
2090 .size = sizeof(flow_attr)
2091 };
2092
2093 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2094 if (IS_ERR(handler_rx)) {
2095 err = PTR_ERR(handler_rx);
2096 goto err;
2097 }
2098
2099 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2100 if (IS_ERR(handler_tx)) {
2101 err = PTR_ERR(handler_tx);
2102 goto err_tx;
2103 }
2104
2105 list_add(&handler_tx->list, &handler_rx->list);
2106
2107 return handler_rx;
2108
2109err_tx:
74491de9 2110 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 2111 ft_rx->refcount--;
2112 kfree(handler_rx);
2113err:
2114 return ERR_PTR(err);
2115}
2116
038d2ef8
MG		 2117static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2118 struct ib_flow_attr *flow_attr,
2119 int domain)
2120{
2121 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 2122 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 2123 struct mlx5_ib_flow_handler *handler = NULL;
2124 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 2125 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8
MG		 2126 struct mlx5_ib_flow_prio *ft_prio;
2127 int err;
2128
2129 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2130 return ERR_PTR(-ENOSPC);
2131
2132 if (domain != IB_FLOW_DOMAIN_USER ||
2133 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
35d19011 2134 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
038d2ef8
MG		 2135 return ERR_PTR(-EINVAL);
2136
2137 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2138 if (!dst)
2139 return ERR_PTR(-ENOMEM);
2140
2141 mutex_lock(&dev->flow_db.lock);
2142
cc0e5d42 2143 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
038d2ef8
MG		 2144 if (IS_ERR(ft_prio)) {
2145 err = PTR_ERR(ft_prio);
2146 goto unlock;
2147 }
cc0e5d42
MG		 2148 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2149 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2150 if (IS_ERR(ft_prio_tx)) {
2151 err = PTR_ERR(ft_prio_tx);
2152 ft_prio_tx = NULL;
2153 goto destroy_ft;
2154 }
2155 }
038d2ef8
MG		 2156
2157 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
d9f88e5a
YH		 2158 if (mqp->flags & MLX5_IB_QP_RSS)
2159 dst->tir_num = mqp->rss_qp.tirn;
2160 else
2161 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
038d2ef8
MG		 2162
2163 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2164 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2165 handler = create_dont_trap_rule(dev, ft_prio,
2166 flow_attr, dst);
2167 } else {
2168 handler = create_flow_rule(dev, ft_prio, flow_attr,
2169 dst);
2170 }
038d2ef8
MG		 2171 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2172 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2173 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2174 dst);
cc0e5d42
MG		 2175 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2176 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 2177 } else {
2178 err = -EINVAL;
2179 goto destroy_ft;
2180 }
2181
2182 if (IS_ERR(handler)) {
2183 err = PTR_ERR(handler);
2184 handler = NULL;
2185 goto destroy_ft;
2186 }
2187
038d2ef8
MG		 2188 mutex_unlock(&dev->flow_db.lock);
2189 kfree(dst);
2190
2191 return &handler->ibflow;
2192
2193destroy_ft:
2194 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 2195 if (ft_prio_tx)
2196 put_flow_table(dev, ft_prio_tx, false);
038d2ef8
MG		 2197unlock:
2198 mutex_unlock(&dev->flow_db.lock);
2199 kfree(dst);
2200 kfree(handler);
2201 return ERR_PTR(err);
2202}
2203
e126ba97
EC		 2204static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2205{
2206 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2207 int err;
2208
9603b61d 2209 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2210 if (err)
2211 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2212 ibqp->qp_num, gid->raw);
2213
2214 return err;
2215}
2216
2217static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2218{
2219 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2220 int err;
2221
9603b61d 2222 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2223 if (err)
2224 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2225 ibqp->qp_num, gid->raw);
2226
2227 return err;
2228}
2229
2230static int init_node_data(struct mlx5_ib_dev *dev)
2231{
1b5daf11 2232 int err;
e126ba97 2233
1b5daf11 2234 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 2235 if (err)
1b5daf11 2236 return err;
e126ba97 2237
1b5daf11 2238 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 2239
1b5daf11 2240 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 2241}
2242
2243static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2244 char *buf)
2245{
2246 struct mlx5_ib_dev *dev =
2247 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2248
9603b61d 2249 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 2250}
2251
2252static ssize_t show_reg_pages(struct device *device,
2253 struct device_attribute *attr, char *buf)
2254{
2255 struct mlx5_ib_dev *dev =
2256 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2257
6aec21f6 2258 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 2259}
2260
2261static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2262 char *buf)
2263{
2264 struct mlx5_ib_dev *dev =
2265 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 2266 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 2267}
2268
e126ba97
EC		 2269static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2270 char *buf)
2271{
2272 struct mlx5_ib_dev *dev =
2273 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 2274 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 2275}
2276
2277static ssize_t show_board(struct device *device, struct device_attribute *attr,
2278 char *buf)
2279{
2280 struct mlx5_ib_dev *dev =
2281 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2282 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 2283 dev->mdev->board_id);
e126ba97
EC		 2284}
2285
2286static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
e126ba97
EC		 2287static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2288static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2289static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2290static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2291
2292static struct device_attribute *mlx5_class_attributes[] = {
2293 &dev_attr_hw_rev,
e126ba97
EC		 2294 &dev_attr_hca_type,
2295 &dev_attr_board_id,
2296 &dev_attr_fw_pages,
2297 &dev_attr_reg_pages,
2298};
2299
7722f47e
HE		 2300static void pkey_change_handler(struct work_struct *work)
2301{
2302 struct mlx5_ib_port_resources *ports =
2303 container_of(work, struct mlx5_ib_port_resources,
2304 pkey_change_work);
2305
2306 mutex_lock(&ports->devr->mutex);
2307 mlx5_ib_gsi_pkey_change(ports->gsi);
2308 mutex_unlock(&ports->devr->mutex);
2309}
2310
89ea94a7
MG		 2311static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2312{
2313 struct mlx5_ib_qp *mqp;
2314 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2315 struct mlx5_core_cq *mcq;
2316 struct list_head cq_armed_list;
2317 unsigned long flags_qp;
2318 unsigned long flags_cq;
2319 unsigned long flags;
2320
2321 INIT_LIST_HEAD(&cq_armed_list);
2322
2323 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2324 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2325 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2326 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2327 if (mqp->sq.tail != mqp->sq.head) {
2328 send_mcq = to_mcq(mqp->ibqp.send_cq);
2329 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2330 if (send_mcq->mcq.comp &&
2331 mqp->ibqp.send_cq->comp_handler) {
2332 if (!send_mcq->mcq.reset_notify_added) {
2333 send_mcq->mcq.reset_notify_added = 1;
2334 list_add_tail(&send_mcq->mcq.reset_notify,
2335 &cq_armed_list);
2336 }
2337 }
2338 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2339 }
2340 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2341 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2342 /* no handling is needed for SRQ */
2343 if (!mqp->ibqp.srq) {
2344 if (mqp->rq.tail != mqp->rq.head) {
2345 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2346 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2347 if (recv_mcq->mcq.comp &&
2348 mqp->ibqp.recv_cq->comp_handler) {
2349 if (!recv_mcq->mcq.reset_notify_added) {
2350 recv_mcq->mcq.reset_notify_added = 1;
2351 list_add_tail(&recv_mcq->mcq.reset_notify,
2352 &cq_armed_list);
2353 }
2354 }
2355 spin_unlock_irqrestore(&recv_mcq->lock,
2356 flags_cq);
2357 }
2358 }
2359 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2360 }
2361 /*At that point all inflight post send were put to be executed as of we
2362 * lock/unlock above locks Now need to arm all involved CQs.
2363 */
2364 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2365 mcq->comp(mcq);
2366 }
2367 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2368}
2369
9603b61d 2370static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 2371 enum mlx5_dev_event event, unsigned long param)
e126ba97 2372{
9603b61d 2373 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
e126ba97 2374 struct ib_event ibev;
9603b61d 2375
e126ba97
EC		 2376 u8 port = 0;
2377
2378 switch (event) {
2379 case MLX5_DEV_EVENT_SYS_ERROR:
2380 ibdev->ib_active = false;
2381 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 2382 mlx5_ib_handle_internal_error(ibdev);
e126ba97
EC		 2383 break;
2384
2385 case MLX5_DEV_EVENT_PORT_UP:
e126ba97 2386 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 2387 case MLX5_DEV_EVENT_PORT_INITIALIZED:
4d2f9bbb 2388 port = (u8)param;
5ec8c83e
AH		 2389
2390 /* In RoCE, port up/down events are handled in
2391 * mlx5_netdev_event().
2392 */
2393 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2394 IB_LINK_LAYER_ETHERNET)
2395 return;
2396
2397 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2398 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
e126ba97
EC		 2399 break;
2400
e126ba97
EC		 2401 case MLX5_DEV_EVENT_LID_CHANGE:
2402 ibev.event = IB_EVENT_LID_CHANGE;
4d2f9bbb 2403 port = (u8)param;
e126ba97
EC		 2404 break;
2405
2406 case MLX5_DEV_EVENT_PKEY_CHANGE:
2407 ibev.event = IB_EVENT_PKEY_CHANGE;
4d2f9bbb 2408 port = (u8)param;
7722f47e
HE		 2409
2410 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 2411 break;
2412
2413 case MLX5_DEV_EVENT_GUID_CHANGE:
2414 ibev.event = IB_EVENT_GID_CHANGE;
4d2f9bbb 2415 port = (u8)param;
e126ba97
EC		 2416 break;
2417
2418 case MLX5_DEV_EVENT_CLIENT_REREG:
2419 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4d2f9bbb 2420 port = (u8)param;
e126ba97 2421 break;
bdc37924
SM		 2422 default:
2423 return;
e126ba97
EC		 2424 }
2425
2426 ibev.device = &ibdev->ib_dev;
2427 ibev.element.port_num = port;
2428
a0c84c32
EC		 2429 if (port < 1 || port > ibdev->num_ports) {
2430 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2431 return;
2432 }
2433
e126ba97
EC		 2434 if (ibdev->ib_active)
2435 ib_dispatch_event(&ibev);
2436}
2437
2438static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2439{
2440 int port;
2441
938fe83c 2442 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
e126ba97
EC		 2443 mlx5_query_ext_port_caps(dev, port);
2444}
2445
2446static int get_port_caps(struct mlx5_ib_dev *dev)
2447{
2448 struct ib_device_attr *dprops = NULL;
2449 struct ib_port_attr *pprops = NULL;
f614fc15 2450 int err = -ENOMEM;
e126ba97 2451 int port;
2528e33e 2452 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 2453
2454 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2455 if (!pprops)
2456 goto out;
2457
2458 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2459 if (!dprops)
2460 goto out;
2461
2528e33e 2462 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 2463 if (err) {
2464 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2465 goto out;
2466 }
2467
938fe83c 2468 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
e126ba97
EC		 2469 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2470 if (err) {
938fe83c
SM		 2471 mlx5_ib_warn(dev, "query_port %d failed %d\n",
2472 port, err);
e126ba97
EC		 2473 break;
2474 }
938fe83c
SM		 2475 dev->mdev->port_caps[port - 1].pkey_table_len =
2476 dprops->max_pkeys;
2477 dev->mdev->port_caps[port - 1].gid_table_len =
2478 pprops->gid_tbl_len;
e126ba97
EC		 2479 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2480 dprops->max_pkeys, pprops->gid_tbl_len);
2481 }
2482
2483out:
2484 kfree(pprops);
2485 kfree(dprops);
2486
2487 return err;
2488}
2489
2490static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2491{
2492 int err;
2493
2494 err = mlx5_mr_cache_cleanup(dev);
2495 if (err)
2496 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2497
2498 mlx5_ib_destroy_qp(dev->umrc.qp);
add08d76 2499 ib_free_cq(dev->umrc.cq);
e126ba97
EC		 2500 ib_dealloc_pd(dev->umrc.pd);
2501}
2502
2503enum {
2504 MAX_UMR_WR = 128,
2505};
2506
2507static int create_umr_res(struct mlx5_ib_dev *dev)
2508{
2509 struct ib_qp_init_attr *init_attr = NULL;
2510 struct ib_qp_attr *attr = NULL;
2511 struct ib_pd *pd;
2512 struct ib_cq *cq;
2513 struct ib_qp *qp;
e126ba97
EC		 2514 int ret;
2515
2516 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2517 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2518 if (!attr || !init_attr) {
2519 ret = -ENOMEM;
2520 goto error_0;
2521 }
2522
ed082d36 2523 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 2524 if (IS_ERR(pd)) {
2525 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2526 ret = PTR_ERR(pd);
2527 goto error_0;
2528 }
2529
add08d76 2530 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 2531 if (IS_ERR(cq)) {
2532 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2533 ret = PTR_ERR(cq);
2534 goto error_2;
2535 }
e126ba97
EC		 2536
2537 init_attr->send_cq = cq;
2538 init_attr->recv_cq = cq;
2539 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2540 init_attr->cap.max_send_wr = MAX_UMR_WR;
2541 init_attr->cap.max_send_sge = 1;
2542 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2543 init_attr->port_num = 1;
2544 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2545 if (IS_ERR(qp)) {
2546 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2547 ret = PTR_ERR(qp);
2548 goto error_3;
2549 }
2550 qp->device = &dev->ib_dev;
2551 qp->real_qp = qp;
2552 qp->uobject = NULL;
2553 qp->qp_type = MLX5_IB_QPT_REG_UMR;
2554
2555 attr->qp_state = IB_QPS_INIT;
2556 attr->port_num = 1;
2557 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2558 IB_QP_PORT, NULL);
2559 if (ret) {
2560 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2561 goto error_4;
2562 }
2563
2564 memset(attr, 0, sizeof(*attr));
2565 attr->qp_state = IB_QPS_RTR;
2566 attr->path_mtu = IB_MTU_256;
2567
2568 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2569 if (ret) {
2570 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2571 goto error_4;
2572 }
2573
2574 memset(attr, 0, sizeof(*attr));
2575 attr->qp_state = IB_QPS_RTS;
2576 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2577 if (ret) {
2578 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2579 goto error_4;
2580 }
2581
2582 dev->umrc.qp = qp;
2583 dev->umrc.cq = cq;
e126ba97
EC		 2584 dev->umrc.pd = pd;
2585
2586 sema_init(&dev->umrc.sem, MAX_UMR_WR);
2587 ret = mlx5_mr_cache_init(dev);
2588 if (ret) {
2589 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2590 goto error_4;
2591 }
2592
2593 kfree(attr);
2594 kfree(init_attr);
2595
2596 return 0;
2597
2598error_4:
2599 mlx5_ib_destroy_qp(qp);
2600
2601error_3:
add08d76 2602 ib_free_cq(cq);
e126ba97
EC		 2603
2604error_2:
e126ba97
EC		 2605 ib_dealloc_pd(pd);
2606
2607error_0:
2608 kfree(attr);
2609 kfree(init_attr);
2610 return ret;
2611}
2612
2613static int create_dev_resources(struct mlx5_ib_resources *devr)
2614{
2615 struct ib_srq_init_attr attr;
2616 struct mlx5_ib_dev *dev;
bcf4c1ea 2617 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 2618 int port;
e126ba97
EC		 2619 int ret = 0;
2620
2621 dev = container_of(devr, struct mlx5_ib_dev, devr);
2622
d16e91da
HE		 2623 mutex_init(&devr->mutex);
2624
e126ba97
EC		 2625 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2626 if (IS_ERR(devr->p0)) {
2627 ret = PTR_ERR(devr->p0);
2628 goto error0;
2629 }
2630 devr->p0->device = &dev->ib_dev;
2631 devr->p0->uobject = NULL;
2632 atomic_set(&devr->p0->usecnt, 0);
2633
bcf4c1ea 2634 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 2635 if (IS_ERR(devr->c0)) {
2636 ret = PTR_ERR(devr->c0);
2637 goto error1;
2638 }
2639 devr->c0->device = &dev->ib_dev;
2640 devr->c0->uobject = NULL;
2641 devr->c0->comp_handler = NULL;
2642 devr->c0->event_handler = NULL;
2643 devr->c0->cq_context = NULL;
2644 atomic_set(&devr->c0->usecnt, 0);
2645
2646 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2647 if (IS_ERR(devr->x0)) {
2648 ret = PTR_ERR(devr->x0);
2649 goto error2;
2650 }
2651 devr->x0->device = &dev->ib_dev;
2652 devr->x0->inode = NULL;
2653 atomic_set(&devr->x0->usecnt, 0);
2654 mutex_init(&devr->x0->tgt_qp_mutex);
2655 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2656
2657 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2658 if (IS_ERR(devr->x1)) {
2659 ret = PTR_ERR(devr->x1);
2660 goto error3;
2661 }
2662 devr->x1->device = &dev->ib_dev;
2663 devr->x1->inode = NULL;
2664 atomic_set(&devr->x1->usecnt, 0);
2665 mutex_init(&devr->x1->tgt_qp_mutex);
2666 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2667
2668 memset(&attr, 0, sizeof(attr));
2669 attr.attr.max_sge = 1;
2670 attr.attr.max_wr = 1;
2671 attr.srq_type = IB_SRQT_XRC;
2672 attr.ext.xrc.cq = devr->c0;
2673 attr.ext.xrc.xrcd = devr->x0;
2674
2675 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2676 if (IS_ERR(devr->s0)) {
2677 ret = PTR_ERR(devr->s0);
2678 goto error4;
2679 }
2680 devr->s0->device = &dev->ib_dev;
2681 devr->s0->pd = devr->p0;
2682 devr->s0->uobject = NULL;
2683 devr->s0->event_handler = NULL;
2684 devr->s0->srq_context = NULL;
2685 devr->s0->srq_type = IB_SRQT_XRC;
2686 devr->s0->ext.xrc.xrcd = devr->x0;
2687 devr->s0->ext.xrc.cq = devr->c0;
2688 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2689 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2690 atomic_inc(&devr->p0->usecnt);
2691 atomic_set(&devr->s0->usecnt, 0);
2692
4aa17b28
HA		 2693 memset(&attr, 0, sizeof(attr));
2694 attr.attr.max_sge = 1;
2695 attr.attr.max_wr = 1;
2696 attr.srq_type = IB_SRQT_BASIC;
2697 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2698 if (IS_ERR(devr->s1)) {
2699 ret = PTR_ERR(devr->s1);
2700 goto error5;
2701 }
2702 devr->s1->device = &dev->ib_dev;
2703 devr->s1->pd = devr->p0;
2704 devr->s1->uobject = NULL;
2705 devr->s1->event_handler = NULL;
2706 devr->s1->srq_context = NULL;
2707 devr->s1->srq_type = IB_SRQT_BASIC;
2708 devr->s1->ext.xrc.cq = devr->c0;
2709 atomic_inc(&devr->p0->usecnt);
2710 atomic_set(&devr->s0->usecnt, 0);
2711
7722f47e
HE		 2712 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2713 INIT_WORK(&devr->ports[port].pkey_change_work,
2714 pkey_change_handler);
2715 devr->ports[port].devr = devr;
2716 }
2717
e126ba97
EC		 2718 return 0;
2719
4aa17b28
HA		 2720error5:
2721 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 2722error4:
2723 mlx5_ib_dealloc_xrcd(devr->x1);
2724error3:
2725 mlx5_ib_dealloc_xrcd(devr->x0);
2726error2:
2727 mlx5_ib_destroy_cq(devr->c0);
2728error1:
2729 mlx5_ib_dealloc_pd(devr->p0);
2730error0:
2731 return ret;
2732}
2733
2734static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2735{
7722f47e
HE		 2736 struct mlx5_ib_dev *dev =
2737 container_of(devr, struct mlx5_ib_dev, devr);
2738 int port;
2739
4aa17b28 2740 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 2741 mlx5_ib_destroy_srq(devr->s0);
2742 mlx5_ib_dealloc_xrcd(devr->x0);
2743 mlx5_ib_dealloc_xrcd(devr->x1);
2744 mlx5_ib_destroy_cq(devr->c0);
2745 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 2746
2747 /* Make sure no change P_Key work items are still executing */
2748 for (port = 0; port < dev->num_ports; ++port)
2749 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 2750}
2751
e53505a8
AS		 2752static u32 get_core_cap_flags(struct ib_device *ibdev)
2753{
2754 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2755 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2756 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2757 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2758 u32 ret = 0;
2759
2760 if (ll == IB_LINK_LAYER_INFINIBAND)
2761 return RDMA_CORE_PORT_IBA_IB;
2762
2763 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2764 return 0;
2765
2766 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2767 return 0;
2768
2769 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2770 ret |= RDMA_CORE_PORT_IBA_ROCE;
2771
2772 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2773 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2774
2775 return ret;
2776}
2777
7738613e
IW		 2778static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2779 struct ib_port_immutable *immutable)
2780{
2781 struct ib_port_attr attr;
2782 int err;
2783
2784 err = mlx5_ib_query_port(ibdev, port_num, &attr);
2785 if (err)
2786 return err;
2787
2788 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2789 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 2790 immutable->core_cap_flags = get_core_cap_flags(ibdev);
337877a4 2791 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 2792
2793 return 0;
2794}
2795
c7342823
IW		 2796static void get_dev_fw_str(struct ib_device *ibdev, char *str,
2797 size_t str_len)
2798{
2799 struct mlx5_ib_dev *dev =
2800 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
2801 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
2802 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
2803}
2804
9ef9c640
AH		 2805static int mlx5_roce_lag_init(struct mlx5_ib_dev *dev)
2806{
2807 struct mlx5_core_dev *mdev = dev->mdev;
2808 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
2809 MLX5_FLOW_NAMESPACE_LAG);
2810 struct mlx5_flow_table *ft;
2811 int err;
2812
2813 if (!ns || !mlx5_lag_is_active(mdev))
2814 return 0;
2815
2816 err = mlx5_cmd_create_vport_lag(mdev);
2817 if (err)
2818 return err;
2819
2820 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
2821 if (IS_ERR(ft)) {
2822 err = PTR_ERR(ft);
2823 goto err_destroy_vport_lag;
2824 }
2825
2826 dev->flow_db.lag_demux_ft = ft;
2827 return 0;
2828
2829err_destroy_vport_lag:
2830 mlx5_cmd_destroy_vport_lag(mdev);
2831 return err;
2832}
2833
2834static void mlx5_roce_lag_cleanup(struct mlx5_ib_dev *dev)
2835{
2836 struct mlx5_core_dev *mdev = dev->mdev;
2837
2838 if (dev->flow_db.lag_demux_ft) {
2839 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
2840 dev->flow_db.lag_demux_ft = NULL;
2841
2842 mlx5_cmd_destroy_vport_lag(mdev);
2843 }
2844}
2845
5ec8c83e
AH		 2846static void mlx5_remove_roce_notifier(struct mlx5_ib_dev *dev)
2847{
2848 if (dev->roce.nb.notifier_call) {
2849 unregister_netdevice_notifier(&dev->roce.nb);
2850 dev->roce.nb.notifier_call = NULL;
2851 }
2852}
2853
fc24fc5e
AS		 2854static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
2855{
e53505a8
AS		 2856 int err;
2857
fc24fc5e 2858 dev->roce.nb.notifier_call = mlx5_netdev_event;
e53505a8 2859 err = register_netdevice_notifier(&dev->roce.nb);
5ec8c83e
AH		 2860 if (err) {
2861 dev->roce.nb.notifier_call = NULL;
e53505a8 2862 return err;
5ec8c83e 2863 }
e53505a8
AS		 2864
2865 err = mlx5_nic_vport_enable_roce(dev->mdev);
2866 if (err)
2867 goto err_unregister_netdevice_notifier;
2868
9ef9c640
AH		 2869 err = mlx5_roce_lag_init(dev);
2870 if (err)
2871 goto err_disable_roce;
2872
e53505a8
AS		 2873 return 0;
2874
9ef9c640
AH		 2875err_disable_roce:
2876 mlx5_nic_vport_disable_roce(dev->mdev);
2877
e53505a8 2878err_unregister_netdevice_notifier:
5ec8c83e 2879 mlx5_remove_roce_notifier(dev);
e53505a8 2880 return err;
fc24fc5e
AS		 2881}
2882
2883static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
2884{
9ef9c640 2885 mlx5_roce_lag_cleanup(dev);
e53505a8 2886 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 2887}
2888
0837e86a
MB		 2889static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
2890{
2891 unsigned int i;
2892
2893 for (i = 0; i < dev->num_ports; i++)
2894 mlx5_core_dealloc_q_counter(dev->mdev,
2895 dev->port[i].q_cnt_id);
2896}
2897
2898static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
2899{
2900 int i;
2901 int ret;
2902
2903 for (i = 0; i < dev->num_ports; i++) {
2904 ret = mlx5_core_alloc_q_counter(dev->mdev,
2905 &dev->port[i].q_cnt_id);
2906 if (ret) {
2907 mlx5_ib_warn(dev,
2908 "couldn't allocate queue counter for port %d, err %d\n",
2909 i + 1, ret);
2910 goto dealloc_counters;
2911 }
2912 }
2913
2914 return 0;
2915
2916dealloc_counters:
2917 while (--i >= 0)
2918 mlx5_core_dealloc_q_counter(dev->mdev,
2919 dev->port[i].q_cnt_id);
2920
2921 return ret;
2922}
2923
61961500 2924static const char * const names[] = {
0ad17a8f
MB		 2925 "rx_write_requests",
2926 "rx_read_requests",
2927 "rx_atomic_requests",
2928 "out_of_buffer",
2929 "out_of_sequence",
2930 "duplicate_request",
2931 "rnr_nak_retry_err",
2932 "packet_seq_err",
2933 "implied_nak_seq_err",
2934 "local_ack_timeout_err",
2935};
2936
2937static const size_t stats_offsets[] = {
2938 MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests),
2939 MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests),
2940 MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests),
2941 MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer),
2942 MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence),
2943 MLX5_BYTE_OFF(query_q_counter_out, duplicate_request),
2944 MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err),
2945 MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err),
2946 MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err),
2947 MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err),
2948};
2949
2950static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
2951 u8 port_num)
2952{
2953 BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets));
2954
2955 /* We support only per port stats */
2956 if (port_num == 0)
2957 return NULL;
2958
2959 return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names),
2960 RDMA_HW_STATS_DEFAULT_LIFESPAN);
2961}
2962
2963static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
2964 struct rdma_hw_stats *stats,
2965 u8 port, int index)
2966{
2967 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2968 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
2969 void *out;
2970 __be32 val;
2971 int ret;
2972 int i;
2973
2974 if (!port || !stats)
2975 return -ENOSYS;
2976
2977 out = mlx5_vzalloc(outlen);
2978 if (!out)
2979 return -ENOMEM;
2980
2981 ret = mlx5_core_query_q_counter(dev->mdev,
2982 dev->port[port - 1].q_cnt_id, 0,
2983 out, outlen);
2984 if (ret)
2985 goto free;
2986
2987 for (i = 0; i < ARRAY_SIZE(names); i++) {
2988 val = *(__be32 *)(out + stats_offsets[i]);
2989 stats->value[i] = (u64)be32_to_cpu(val);
2990 }
2991free:
2992 kvfree(out);
2993 return ARRAY_SIZE(names);
2994}
2995
9603b61d 2996static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
e126ba97 2997{
e126ba97 2998 struct mlx5_ib_dev *dev;
ebd61f68
AS		 2999 enum rdma_link_layer ll;
3000 int port_type_cap;
4babcf97 3001 const char *name;
e126ba97
EC		 3002 int err;
3003 int i;
3004
ebd61f68
AS		 3005 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3006 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3007
e53505a8 3008 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
647241ea
MD		 3009 return NULL;
3010
e126ba97
EC		 3011 printk_once(KERN_INFO "%s", mlx5_version);
3012
3013 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
3014 if (!dev)
9603b61d 3015 return NULL;
e126ba97 3016
9603b61d 3017 dev->mdev = mdev;
e126ba97 3018
0837e86a
MB		 3019 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
3020 GFP_KERNEL);
3021 if (!dev->port)
3022 goto err_dealloc;
3023
fc24fc5e 3024 rwlock_init(&dev->roce.netdev_lock);
e126ba97
EC		 3025 err = get_port_caps(dev);
3026 if (err)
0837e86a 3027 goto err_free_port;
e126ba97 3028
1b5daf11
MD		 3029 if (mlx5_use_mad_ifc(dev))
3030 get_ext_port_caps(dev);
e126ba97 3031
e126ba97
EC		 3032 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
3033
4babcf97
AH		 3034 if (!mlx5_lag_is_active(mdev))
3035 name = "mlx5_%d";
3036 else
3037 name = "mlx5_bond_%d";
3038
3039 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
e126ba97
EC		 3040 dev->ib_dev.owner = THIS_MODULE;
3041 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 3042 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
938fe83c 3043 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
e126ba97 3044 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 3045 dev->ib_dev.num_comp_vectors =
3046 dev->mdev->priv.eq_table.num_comp_vectors;
e126ba97
EC		 3047 dev->ib_dev.dma_device = &mdev->pdev->dev;
3048
3049 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
3050 dev->ib_dev.uverbs_cmd_mask =
3051 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
3052 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
3053 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
3054 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
3055 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
3056 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 3057 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 3058 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
3059 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
3060 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
3061 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
3062 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
3063 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
3064 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
3065 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
3066 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
3067 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
3068 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
3069 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
3070 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
3071 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
3072 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
3073 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
3074 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 3075 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 3076 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
3077 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
3078 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
e126ba97
EC		 3079
3080 dev->ib_dev.query_device = mlx5_ib_query_device;
3081 dev->ib_dev.query_port = mlx5_ib_query_port;
ebd61f68 3082 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
fc24fc5e
AS		 3083 if (ll == IB_LINK_LAYER_ETHERNET)
3084 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
e126ba97 3085 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 3086 dev->ib_dev.add_gid = mlx5_ib_add_gid;
3087 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 3088 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
3089 dev->ib_dev.modify_device = mlx5_ib_modify_device;
3090 dev->ib_dev.modify_port = mlx5_ib_modify_port;
3091 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
3092 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
3093 dev->ib_dev.mmap = mlx5_ib_mmap;
3094 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
3095 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
3096 dev->ib_dev.create_ah = mlx5_ib_create_ah;
3097 dev->ib_dev.query_ah = mlx5_ib_query_ah;
3098 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
3099 dev->ib_dev.create_srq = mlx5_ib_create_srq;
3100 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
3101 dev->ib_dev.query_srq = mlx5_ib_query_srq;
3102 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
3103 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
3104 dev->ib_dev.create_qp = mlx5_ib_create_qp;
3105 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
3106 dev->ib_dev.query_qp = mlx5_ib_query_qp;
3107 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
3108 dev->ib_dev.post_send = mlx5_ib_post_send;
3109 dev->ib_dev.post_recv = mlx5_ib_post_recv;
3110 dev->ib_dev.create_cq = mlx5_ib_create_cq;
3111 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
3112 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
3113 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
3114 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
3115 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
3116 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
3117 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 3118 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 3119 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
3120 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
3121 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
3122 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 3123 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 3124 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 3125 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
7738613e 3126 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
c7342823 3127 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
eff901d3
EC		 3128 if (mlx5_core_is_pf(mdev)) {
3129 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
3130 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
3131 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
3132 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
3133 }
e126ba97 3134
7c2344c3
MG		 3135 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3136
938fe83c 3137 mlx5_ib_internal_fill_odp_caps(dev);
8cdd312c 3138
d2370e0a
MB		 3139 if (MLX5_CAP_GEN(mdev, imaicl)) {
3140 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
3141 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
3142 dev->ib_dev.uverbs_cmd_mask |=
3143 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
3144 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3145 }
3146
0ad17a8f
MB		 3147 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) &&
3148 MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3149 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
3150 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
3151 }
3152
938fe83c 3153 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 3154 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3155 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3156 dev->ib_dev.uverbs_cmd_mask |=
3157 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3158 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3159 }
3160
048ccca8 3161 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
038d2ef8
MG		 3162 IB_LINK_LAYER_ETHERNET) {
3163 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3164 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
79b20a6c
YH		 3165 dev->ib_dev.create_wq = mlx5_ib_create_wq;
3166 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
3167 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
c5f90929
YH		 3168 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
3169 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
038d2ef8
MG		 3170 dev->ib_dev.uverbs_ex_cmd_mask |=
3171 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
79b20a6c
YH		 3172 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
3173 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
3174 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
c5f90929
YH		 3175 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
3176 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
3177 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
038d2ef8 3178 }
e126ba97
EC		 3179 err = init_node_data(dev);
3180 if (err)
233d05d2 3181 goto err_dealloc;
e126ba97 3182
038d2ef8 3183 mutex_init(&dev->flow_db.lock);
e126ba97 3184 mutex_init(&dev->cap_mask_mutex);
89ea94a7
MG		 3185 INIT_LIST_HEAD(&dev->qp_list);
3186 spin_lock_init(&dev->reset_flow_resource_lock);
e126ba97 3187
fc24fc5e
AS		 3188 if (ll == IB_LINK_LAYER_ETHERNET) {
3189 err = mlx5_enable_roce(dev);
3190 if (err)
3191 goto err_dealloc;
3192 }
3193
e126ba97
EC		 3194 err = create_dev_resources(&dev->devr);
3195 if (err)
fc24fc5e 3196 goto err_disable_roce;
e126ba97 3197
6aec21f6 3198 err = mlx5_ib_odp_init_one(dev);
281d1a92 3199 if (err)
e126ba97
EC		 3200 goto err_rsrc;
3201
0837e86a 3202 err = mlx5_ib_alloc_q_counters(dev);
6aec21f6
HE		 3203 if (err)
3204 goto err_odp;
3205
0837e86a
MB		 3206 err = ib_register_device(&dev->ib_dev, NULL);
3207 if (err)
3208 goto err_q_cnt;
3209
e126ba97
EC		 3210 err = create_umr_res(dev);
3211 if (err)
3212 goto err_dev;
3213
3214 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 3215 err = device_create_file(&dev->ib_dev.dev,
3216 mlx5_class_attributes[i]);
3217 if (err)
e126ba97
EC		 3218 goto err_umrc;
3219 }
3220
3221 dev->ib_active = true;
3222
9603b61d 3223 return dev;
e126ba97
EC		 3224
3225err_umrc:
3226 destroy_umrc_res(dev);
3227
3228err_dev:
3229 ib_unregister_device(&dev->ib_dev);
3230
0837e86a
MB		 3231err_q_cnt:
3232 mlx5_ib_dealloc_q_counters(dev);
3233
6aec21f6
HE		 3234err_odp:
3235 mlx5_ib_odp_remove_one(dev);
3236
e126ba97
EC		 3237err_rsrc:
3238 destroy_dev_resources(&dev->devr);
3239
fc24fc5e 3240err_disable_roce:
5ec8c83e 3241 if (ll == IB_LINK_LAYER_ETHERNET) {
fc24fc5e 3242 mlx5_disable_roce(dev);
5ec8c83e
AH		 3243 mlx5_remove_roce_notifier(dev);
3244 }
fc24fc5e 3245
0837e86a
MB		 3246err_free_port:
3247 kfree(dev->port);
3248
9603b61d 3249err_dealloc:
e126ba97
EC		 3250 ib_dealloc_device((struct ib_device *)dev);
3251
9603b61d 3252 return NULL;
e126ba97
EC		 3253}
3254
9603b61d 3255static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 3256{
9603b61d 3257 struct mlx5_ib_dev *dev = context;
fc24fc5e 3258 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
6aec21f6 3259
5ec8c83e 3260 mlx5_remove_roce_notifier(dev);
e126ba97 3261 ib_unregister_device(&dev->ib_dev);
0837e86a 3262 mlx5_ib_dealloc_q_counters(dev);
eefd56e5 3263 destroy_umrc_res(dev);
6aec21f6 3264 mlx5_ib_odp_remove_one(dev);
e126ba97 3265 destroy_dev_resources(&dev->devr);
fc24fc5e
AS		 3266 if (ll == IB_LINK_LAYER_ETHERNET)
3267 mlx5_disable_roce(dev);
0837e86a 3268 kfree(dev->port);
e126ba97
EC		 3269 ib_dealloc_device(&dev->ib_dev);
3270}
3271
9603b61d
JM		 3272static struct mlx5_interface mlx5_ib_interface = {
3273 .add = mlx5_ib_add,
3274 .remove = mlx5_ib_remove,
3275 .event = mlx5_ib_event,
64613d94 3276 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 3277};
3278
3279static int __init mlx5_ib_init(void)
3280{
6aec21f6
HE		 3281 int err;
3282
9603b61d
JM		 3283 if (deprecated_prof_sel != 2)
3284 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
3285
6aec21f6
HE		 3286 err = mlx5_ib_odp_init();
3287 if (err)
3288 return err;
3289
3290 err = mlx5_register_interface(&mlx5_ib_interface);
3291 if (err)
3292 goto clean_odp;
3293
3294 return err;
3295
3296clean_odp:
3297 mlx5_ib_odp_cleanup();
3298 return err;
e126ba97
EC		 3299}
3300
3301static void __exit mlx5_ib_cleanup(void)
3302{
9603b61d 3303 mlx5_unregister_interface(&mlx5_ib_interface);
6aec21f6 3304 mlx5_ib_odp_cleanup();
e126ba97
EC		 3305}
3306
3307module_init(mlx5_ib_init);
3308module_exit(mlx5_ib_cleanup);
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