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IB/mlx5: Fix integer overflow when page_shift == 31
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
37aa5c36
GL		 41#if defined(CONFIG_X86)
42#include <asm/pat.h>
43#endif
e126ba97 44#include <linux/sched.h>
6e84f315 45#include <linux/sched/mm.h>
0881e7bd 46#include <linux/sched/task.h>
7c2344c3 47#include <linux/delay.h>
e126ba97 48#include <rdma/ib_user_verbs.h>
3f89a643 49#include <rdma/ib_addr.h>
2811ba51 50#include <rdma/ib_cache.h>
ada68c31 51#include <linux/mlx5/port.h>
1b5daf11 52#include <linux/mlx5/vport.h>
7c2344c3 53#include <linux/list.h>
e126ba97
EC		 54#include <rdma/ib_smi.h>
55#include <rdma/ib_umem.h>
038d2ef8
MG		 56#include <linux/in.h>
57#include <linux/etherdevice.h>
58#include <linux/mlx5/fs.h>
78984898 59#include <linux/mlx5/vport.h>
e126ba97 60#include "mlx5_ib.h"
e1f24a79 61#include "cmd.h"
c85023e1 62#include <linux/mlx5/vport.h>
e126ba97
EC		 63
64#define DRIVER_NAME "mlx5_ib"
b359911d 65#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 66
67MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
68MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
69MODULE_LICENSE("Dual BSD/GPL");
e126ba97 70
e126ba97
EC		 71static char mlx5_version[] =
72 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 73 DRIVER_VERSION "\n";
e126ba97 74
da7525d2
EBE		 75enum {
76 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
77};
78
1b5daf11 79static enum rdma_link_layer
ebd61f68 80mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 81{
ebd61f68 82 switch (port_type_cap) {
1b5daf11
MD		 83 case MLX5_CAP_PORT_TYPE_IB:
84 return IB_LINK_LAYER_INFINIBAND;
85 case MLX5_CAP_PORT_TYPE_ETH:
86 return IB_LINK_LAYER_ETHERNET;
87 default:
88 return IB_LINK_LAYER_UNSPECIFIED;
89 }
90}
91
ebd61f68
AS		 92static enum rdma_link_layer
93mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
94{
95 struct mlx5_ib_dev *dev = to_mdev(device);
96 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
97
98 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
99}
100
fd65f1b8
MS		 101static int get_port_state(struct ib_device *ibdev,
102 u8 port_num,
103 enum ib_port_state *state)
104{
105 struct ib_port_attr attr;
106 int ret;
107
108 memset(&attr, 0, sizeof(attr));
109 ret = mlx5_ib_query_port(ibdev, port_num, &attr);
110 if (!ret)
111 *state = attr.state;
112 return ret;
113}
114
fc24fc5e
AS		 115static int mlx5_netdev_event(struct notifier_block *this,
116 unsigned long event, void *ptr)
117{
118 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
119 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
120 roce.nb);
121
5ec8c83e
AH		 122 switch (event) {
123 case NETDEV_REGISTER:
124 case NETDEV_UNREGISTER:
125 write_lock(&ibdev->roce.netdev_lock);
126 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
127 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
128 NULL : ndev;
129 write_unlock(&ibdev->roce.netdev_lock);
130 break;
fc24fc5e 131
fd65f1b8 132 case NETDEV_CHANGE:
5ec8c83e 133 case NETDEV_UP:
88621dfe
AH		 134 case NETDEV_DOWN: {
135 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
136 struct net_device *upper = NULL;
137
138 if (lag_ndev) {
139 upper = netdev_master_upper_dev_get(lag_ndev);
140 dev_put(lag_ndev);
141 }
142
143 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
144 && ibdev->ib_active) {
626bc02d 145 struct ib_event ibev = { };
fd65f1b8 146 enum ib_port_state port_state;
5ec8c83e 147
fd65f1b8
MS		 148 if (get_port_state(&ibdev->ib_dev, 1, &port_state))
149 return NOTIFY_DONE;
150
151 if (ibdev->roce.last_port_state == port_state)
152 return NOTIFY_DONE;
153
154 ibdev->roce.last_port_state = port_state;
5ec8c83e 155 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 156 if (port_state == IB_PORT_DOWN)
157 ibev.event = IB_EVENT_PORT_ERR;
158 else if (port_state == IB_PORT_ACTIVE)
159 ibev.event = IB_EVENT_PORT_ACTIVE;
160 else
161 return NOTIFY_DONE;
162
5ec8c83e
AH		 163 ibev.element.port_num = 1;
164 ib_dispatch_event(&ibev);
165 }
166 break;
88621dfe 167 }
fc24fc5e 168
5ec8c83e
AH		 169 default:
170 break;
171 }
fc24fc5e
AS		 172
173 return NOTIFY_DONE;
174}
175
176static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
177 u8 port_num)
178{
179 struct mlx5_ib_dev *ibdev = to_mdev(device);
180 struct net_device *ndev;
181
88621dfe
AH		 182 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
183 if (ndev)
184 return ndev;
185
fc24fc5e
AS		 186 /* Ensure ndev does not disappear before we invoke dev_hold()
187 */
188 read_lock(&ibdev->roce.netdev_lock);
189 ndev = ibdev->roce.netdev;
190 if (ndev)
191 dev_hold(ndev);
192 read_unlock(&ibdev->roce.netdev_lock);
193
194 return ndev;
195}
196
f1b65df5
NO		 197static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
198 u8 *active_width)
199{
200 switch (eth_proto_oper) {
201 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
202 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
203 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
204 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
205 *active_width = IB_WIDTH_1X;
206 *active_speed = IB_SPEED_SDR;
207 break;
208 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
209 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
210 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
211 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
212 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
213 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
214 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
215 *active_width = IB_WIDTH_1X;
216 *active_speed = IB_SPEED_QDR;
217 break;
218 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
219 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
220 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
221 *active_width = IB_WIDTH_1X;
222 *active_speed = IB_SPEED_EDR;
223 break;
224 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
225 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
226 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
227 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
228 *active_width = IB_WIDTH_4X;
229 *active_speed = IB_SPEED_QDR;
230 break;
231 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
232 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
233 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
234 *active_width = IB_WIDTH_1X;
235 *active_speed = IB_SPEED_HDR;
236 break;
237 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
238 *active_width = IB_WIDTH_4X;
239 *active_speed = IB_SPEED_FDR;
240 break;
241 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
242 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
243 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
244 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
245 *active_width = IB_WIDTH_4X;
246 *active_speed = IB_SPEED_EDR;
247 break;
248 default:
249 return -EINVAL;
250 }
251
252 return 0;
253}
254
095b0927
IT		 255static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
256 struct ib_port_attr *props)
3f89a643
AS		 257{
258 struct mlx5_ib_dev *dev = to_mdev(device);
f1b65df5 259 struct mlx5_core_dev *mdev = dev->mdev;
88621dfe 260 struct net_device *ndev, *upper;
3f89a643 261 enum ib_mtu ndev_ib_mtu;
c876a1b7 262 u16 qkey_viol_cntr;
f1b65df5 263 u32 eth_prot_oper;
095b0927 264 int err;
3f89a643 265
f1b65df5
NO		 266 /* Possible bad flows are checked before filling out props so in case
267 * of an error it will still be zeroed out.
50f22fd8 268 */
095b0927
IT		 269 err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper, port_num);
270 if (err)
271 return err;
f1b65df5
NO		 272
273 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
274 &props->active_width);
3f89a643
AS		 275
276 props->port_cap_flags |= IB_PORT_CM_SUP;
277 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
278
279 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
280 roce_address_table_size);
281 props->max_mtu = IB_MTU_4096;
282 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
283 props->pkey_tbl_len = 1;
284 props->state = IB_PORT_DOWN;
285 props->phys_state = 3;
286
c876a1b7
LR		 287 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
288 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643
AS		 289
290 ndev = mlx5_ib_get_netdev(device, port_num);
291 if (!ndev)
095b0927 292 return 0;
3f89a643 293
88621dfe
AH		 294 if (mlx5_lag_is_active(dev->mdev)) {
295 rcu_read_lock();
296 upper = netdev_master_upper_dev_get_rcu(ndev);
297 if (upper) {
298 dev_put(ndev);
299 ndev = upper;
300 dev_hold(ndev);
301 }
302 rcu_read_unlock();
303 }
304
3f89a643
AS		 305 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
306 props->state = IB_PORT_ACTIVE;
307 props->phys_state = 5;
308 }
309
310 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
311
312 dev_put(ndev);
313
314 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
095b0927 315 return 0;
3f89a643
AS		 316}
317
095b0927
IT		 318static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
319 unsigned int index, const union ib_gid *gid,
320 const struct ib_gid_attr *attr)
3cca2606 321{
095b0927
IT		 322 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
323 u8 roce_version = 0;
324 u8 roce_l3_type = 0;
325 bool vlan = false;
326 u8 mac[ETH_ALEN];
327 u16 vlan_id = 0;
328
329 if (gid) {
330 gid_type = attr->gid_type;
331 ether_addr_copy(mac, attr->ndev->dev_addr);
332
333 if (is_vlan_dev(attr->ndev)) {
334 vlan = true;
335 vlan_id = vlan_dev_vlan_id(attr->ndev);
336 }
3cca2606
AS		 337 }
338
095b0927 339 switch (gid_type) {
3cca2606 340 case IB_GID_TYPE_IB:
095b0927 341 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 342 break;
343 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 344 roce_version = MLX5_ROCE_VERSION_2;
345 if (ipv6_addr_v4mapped((void *)gid))
346 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
347 else
348 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 349 break;
350
351 default:
095b0927 352 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 353 }
354
095b0927
IT		 355 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
356 roce_l3_type, gid->raw, mac, vlan,
357 vlan_id);
3cca2606
AS		 358}
359
360static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
361 unsigned int index, const union ib_gid *gid,
362 const struct ib_gid_attr *attr,
363 __always_unused void **context)
364{
095b0927 365 return set_roce_addr(to_mdev(device), port_num, index, gid, attr);
3cca2606
AS		 366}
367
368static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
369 unsigned int index, __always_unused void **context)
370{
095b0927 371 return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL);
3cca2606
AS		 372}
373
2811ba51
AS		 374__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
375 int index)
376{
377 struct ib_gid_attr attr;
378 union ib_gid gid;
379
380 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
381 return 0;
382
383 if (!attr.ndev)
384 return 0;
385
386 dev_put(attr.ndev);
387
388 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
389 return 0;
390
391 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
392}
393
ed88451e
MD		 394int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
395 int index, enum ib_gid_type *gid_type)
396{
397 struct ib_gid_attr attr;
398 union ib_gid gid;
399 int ret;
400
401 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
402 if (ret)
403 return ret;
404
405 if (!attr.ndev)
406 return -ENODEV;
407
408 dev_put(attr.ndev);
409
410 *gid_type = attr.gid_type;
411
412 return 0;
413}
414
1b5daf11
MD		 415static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
416{
7fae6655
NO		 417 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
418 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
419 return 0;
1b5daf11
MD		 420}
421
422enum {
423 MLX5_VPORT_ACCESS_METHOD_MAD,
424 MLX5_VPORT_ACCESS_METHOD_HCA,
425 MLX5_VPORT_ACCESS_METHOD_NIC,
426};
427
428static int mlx5_get_vport_access_method(struct ib_device *ibdev)
429{
430 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
431 return MLX5_VPORT_ACCESS_METHOD_MAD;
432
ebd61f68 433 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 434 IB_LINK_LAYER_ETHERNET)
435 return MLX5_VPORT_ACCESS_METHOD_NIC;
436
437 return MLX5_VPORT_ACCESS_METHOD_HCA;
438}
439
da7525d2
EBE		 440static void get_atomic_caps(struct mlx5_ib_dev *dev,
441 struct ib_device_attr *props)
442{
443 u8 tmp;
444 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
445 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
446 u8 atomic_req_8B_endianness_mode =
bd10838a 447 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 448
449 /* Check if HW supports 8 bytes standard atomic operations and capable
450 * of host endianness respond
451 */
452 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
453 if (((atomic_operations & tmp) == tmp) &&
454 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
455 (atomic_req_8B_endianness_mode)) {
456 props->atomic_cap = IB_ATOMIC_HCA;
457 } else {
458 props->atomic_cap = IB_ATOMIC_NONE;
459 }
460}
461
1b5daf11
MD		 462static int mlx5_query_system_image_guid(struct ib_device *ibdev,
463 __be64 *sys_image_guid)
464{
465 struct mlx5_ib_dev *dev = to_mdev(ibdev);
466 struct mlx5_core_dev *mdev = dev->mdev;
467 u64 tmp;
468 int err;
469
470 switch (mlx5_get_vport_access_method(ibdev)) {
471 case MLX5_VPORT_ACCESS_METHOD_MAD:
472 return mlx5_query_mad_ifc_system_image_guid(ibdev,
473 sys_image_guid);
474
475 case MLX5_VPORT_ACCESS_METHOD_HCA:
476 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 477 break;
478
479 case MLX5_VPORT_ACCESS_METHOD_NIC:
480 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
481 break;
1b5daf11
MD		 482
483 default:
484 return -EINVAL;
485 }
3f89a643
AS		 486
487 if (!err)
488 *sys_image_guid = cpu_to_be64(tmp);
489
490 return err;
491
1b5daf11
MD		 492}
493
494static int mlx5_query_max_pkeys(struct ib_device *ibdev,
495 u16 *max_pkeys)
496{
497 struct mlx5_ib_dev *dev = to_mdev(ibdev);
498 struct mlx5_core_dev *mdev = dev->mdev;
499
500 switch (mlx5_get_vport_access_method(ibdev)) {
501 case MLX5_VPORT_ACCESS_METHOD_MAD:
502 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
503
504 case MLX5_VPORT_ACCESS_METHOD_HCA:
505 case MLX5_VPORT_ACCESS_METHOD_NIC:
506 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
507 pkey_table_size));
508 return 0;
509
510 default:
511 return -EINVAL;
512 }
513}
514
515static int mlx5_query_vendor_id(struct ib_device *ibdev,
516 u32 *vendor_id)
517{
518 struct mlx5_ib_dev *dev = to_mdev(ibdev);
519
520 switch (mlx5_get_vport_access_method(ibdev)) {
521 case MLX5_VPORT_ACCESS_METHOD_MAD:
522 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
523
524 case MLX5_VPORT_ACCESS_METHOD_HCA:
525 case MLX5_VPORT_ACCESS_METHOD_NIC:
526 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
527
528 default:
529 return -EINVAL;
530 }
531}
532
533static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
534 __be64 *node_guid)
535{
536 u64 tmp;
537 int err;
538
539 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
540 case MLX5_VPORT_ACCESS_METHOD_MAD:
541 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
542
543 case MLX5_VPORT_ACCESS_METHOD_HCA:
544 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 545 break;
546
547 case MLX5_VPORT_ACCESS_METHOD_NIC:
548 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
549 break;
1b5daf11
MD		 550
551 default:
552 return -EINVAL;
553 }
3f89a643
AS		 554
555 if (!err)
556 *node_guid = cpu_to_be64(tmp);
557
558 return err;
1b5daf11
MD		 559}
560
561struct mlx5_reg_node_desc {
bd99fdea 562 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 563};
564
565static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
566{
567 struct mlx5_reg_node_desc in;
568
569 if (mlx5_use_mad_ifc(dev))
570 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
571
572 memset(&in, 0, sizeof(in));
573
574 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
575 sizeof(struct mlx5_reg_node_desc),
576 MLX5_REG_NODE_DESC, 0, 0);
577}
578
e126ba97 579static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 580 struct ib_device_attr *props,
581 struct ib_udata *uhw)
e126ba97
EC		 582{
583 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 584 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 585 int err = -ENOMEM;
288c01b7 586 int max_sq_desc;
e126ba97
EC		 587 int max_rq_sg;
588 int max_sq_sg;
e0238a6a 589 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
402ca536
BW		 590 struct mlx5_ib_query_device_resp resp = {};
591 size_t resp_len;
592 u64 max_tso;
e126ba97 593
402ca536
BW		 594 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
595 if (uhw->outlen && uhw->outlen < resp_len)
596 return -EINVAL;
597 else
598 resp.response_length = resp_len;
599
600 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 601 return -EINVAL;
602
1b5daf11
MD		 603 memset(props, 0, sizeof(*props));
604 err = mlx5_query_system_image_guid(ibdev,
605 &props->sys_image_guid);
606 if (err)
607 return err;
e126ba97 608
1b5daf11 609 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 610 if (err)
1b5daf11 611 return err;
e126ba97 612
1b5daf11
MD		 613 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
614 if (err)
615 return err;
e126ba97 616
9603b61d
JM		 617 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
618 (fw_rev_min(dev->mdev) << 16) |
619 fw_rev_sub(dev->mdev);
e126ba97
EC		 620 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
621 IB_DEVICE_PORT_ACTIVE_EVENT |
622 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 623 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 624
625 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 626 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 627 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 628 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 629 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 630 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 631 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 632 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 633 if (MLX5_CAP_GEN(mdev, imaicl)) {
634 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
635 IB_DEVICE_MEM_WINDOW_TYPE_2B;
636 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 637 /* We support 'Gappy' memory registration too */
638 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 639 }
e126ba97 640 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 641 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 642 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
643 /* At this stage no support for signature handover */
644 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
645 IB_PROT_T10DIF_TYPE_2 |
646 IB_PROT_T10DIF_TYPE_3;
647 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
648 IB_GUARD_T10DIF_CSUM;
649 }
938fe83c 650 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 651 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 652
402ca536 653 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
e8161334
NO		 654 if (MLX5_CAP_ETH(mdev, csum_cap)) {
655 /* Legacy bit to support old userspace libraries */
88115fe7 656 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 657 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
658 }
659
660 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
661 props->raw_packet_caps |=
662 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 663
402ca536
BW		 664 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
665 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
666 if (max_tso) {
667 resp.tso_caps.max_tso = 1 << max_tso;
668 resp.tso_caps.supported_qpts |=
669 1 << IB_QPT_RAW_PACKET;
670 resp.response_length += sizeof(resp.tso_caps);
671 }
672 }
31f69a82
YH		 673
674 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
675 resp.rss_caps.rx_hash_function =
676 MLX5_RX_HASH_FUNC_TOEPLITZ;
677 resp.rss_caps.rx_hash_fields_mask =
678 MLX5_RX_HASH_SRC_IPV4 |
679 MLX5_RX_HASH_DST_IPV4 |
680 MLX5_RX_HASH_SRC_IPV6 |
681 MLX5_RX_HASH_DST_IPV6 |
682 MLX5_RX_HASH_SRC_PORT_TCP |
683 MLX5_RX_HASH_DST_PORT_TCP |
684 MLX5_RX_HASH_SRC_PORT_UDP |
685 MLX5_RX_HASH_DST_PORT_UDP;
686 resp.response_length += sizeof(resp.rss_caps);
687 }
688 } else {
689 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
690 resp.response_length += sizeof(resp.tso_caps);
691 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
692 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 693 }
694
f0313965
ES		 695 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
696 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
697 props->device_cap_flags |= IB_DEVICE_UD_TSO;
698 }
699
03404e8a
MG		 700 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
701 MLX5_CAP_GEN(dev->mdev, general_notification_event))
702 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
703
1d54f890
YH		 704 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
705 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
706 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
707
cff5a0f3 708 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
e8161334
NO		 709 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
710 /* Legacy bit to support old userspace libraries */
cff5a0f3 711 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 712 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
713 }
cff5a0f3 714
da6d6ba3
MG		 715 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
716 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
717
1b5daf11
MD		 718 props->vendor_part_id = mdev->pdev->device;
719 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 720
721 props->max_mr_size = ~0ull;
e0238a6a 722 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 723 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
724 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
725 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
726 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 727 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
728 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
729 sizeof(struct mlx5_wqe_raddr_seg)) /
730 sizeof(struct mlx5_wqe_data_seg);
e126ba97 731 props->max_sge = min(max_rq_sg, max_sq_sg);
986ef95e 732 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 733 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 734 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 735 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
736 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
737 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
738 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
739 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
740 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
741 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 742 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 743 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 744 props->max_fast_reg_page_list_len =
745 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
da7525d2 746 get_atomic_caps(dev, props);
81bea28f 747 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 748 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
749 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 750 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
751 props->max_mcast_grp;
752 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 753 props->max_ah = INT_MAX;
7c60bcbb
MB		 754 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
755 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 756
8cdd312c 757#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 758 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 759 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
760 props->odp_caps = dev->odp_caps;
761#endif
762
051f2630
LR		 763 if (MLX5_CAP_GEN(mdev, cd))
764 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
765
eff901d3
EC		 766 if (!mlx5_core_is_pf(mdev))
767 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
768
31f69a82
YH		 769 if (mlx5_ib_port_link_layer(ibdev, 1) ==
770 IB_LINK_LAYER_ETHERNET) {
771 props->rss_caps.max_rwq_indirection_tables =
772 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
773 props->rss_caps.max_rwq_indirection_table_size =
774 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
775 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
776 props->max_wq_type_rq =
777 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
778 }
779
7e43a2a5
BW		 780 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
781 resp.cqe_comp_caps.max_num =
782 MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
783 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
784 resp.cqe_comp_caps.supported_format =
785 MLX5_IB_CQE_RES_FORMAT_HASH |
786 MLX5_IB_CQE_RES_FORMAT_CSUM;
787 resp.response_length += sizeof(resp.cqe_comp_caps);
788 }
789
d949167d
BW		 790 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) {
791 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
792 MLX5_CAP_GEN(mdev, qos)) {
793 resp.packet_pacing_caps.qp_rate_limit_max =
794 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
795 resp.packet_pacing_caps.qp_rate_limit_min =
796 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
797 resp.packet_pacing_caps.supported_qpts |=
798 1 << IB_QPT_RAW_PACKET;
799 }
800 resp.response_length += sizeof(resp.packet_pacing_caps);
801 }
802
9f885201
LR		 803 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
804 uhw->outlen)) {
805 resp.mlx5_ib_support_multi_pkt_send_wqes =
806 MLX5_CAP_ETH(mdev, multi_pkt_send_wqe);
807 resp.response_length +=
808 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
809 }
810
811 if (field_avail(typeof(resp), reserved, uhw->outlen))
812 resp.response_length += sizeof(resp.reserved);
813
96dc3fc5
NO		 814 if (field_avail(typeof(resp), sw_parsing_caps,
815 uhw->outlen)) {
816 resp.response_length += sizeof(resp.sw_parsing_caps);
817 if (MLX5_CAP_ETH(mdev, swp)) {
818 resp.sw_parsing_caps.sw_parsing_offloads |=
819 MLX5_IB_SW_PARSING;
820
821 if (MLX5_CAP_ETH(mdev, swp_csum))
822 resp.sw_parsing_caps.sw_parsing_offloads |=
823 MLX5_IB_SW_PARSING_CSUM;
824
825 if (MLX5_CAP_ETH(mdev, swp_lso))
826 resp.sw_parsing_caps.sw_parsing_offloads |=
827 MLX5_IB_SW_PARSING_LSO;
828
829 if (resp.sw_parsing_caps.sw_parsing_offloads)
830 resp.sw_parsing_caps.supported_qpts =
831 BIT(IB_QPT_RAW_PACKET);
832 }
833 }
834
402ca536
BW		 835 if (uhw->outlen) {
836 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
837
838 if (err)
839 return err;
840 }
841
1b5daf11 842 return 0;
e126ba97
EC		 843}
844
1b5daf11
MD		 845enum mlx5_ib_width {
846 MLX5_IB_WIDTH_1X = 1 << 0,
847 MLX5_IB_WIDTH_2X = 1 << 1,
848 MLX5_IB_WIDTH_4X = 1 << 2,
849 MLX5_IB_WIDTH_8X = 1 << 3,
850 MLX5_IB_WIDTH_12X = 1 << 4
851};
852
853static int translate_active_width(struct ib_device *ibdev, u8 active_width,
854 u8 *ib_width)
e126ba97
EC		 855{
856 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 857 int err = 0;
858
859 if (active_width & MLX5_IB_WIDTH_1X) {
860 *ib_width = IB_WIDTH_1X;
861 } else if (active_width & MLX5_IB_WIDTH_2X) {
862 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
863 (int)active_width);
864 err = -EINVAL;
865 } else if (active_width & MLX5_IB_WIDTH_4X) {
866 *ib_width = IB_WIDTH_4X;
867 } else if (active_width & MLX5_IB_WIDTH_8X) {
868 *ib_width = IB_WIDTH_8X;
869 } else if (active_width & MLX5_IB_WIDTH_12X) {
870 *ib_width = IB_WIDTH_12X;
871 } else {
872 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
873 (int)active_width);
874 err = -EINVAL;
e126ba97
EC		 875 }
876
1b5daf11
MD		 877 return err;
878}
e126ba97 879
1b5daf11
MD		 880static int mlx5_mtu_to_ib_mtu(int mtu)
881{
882 switch (mtu) {
883 case 256: return 1;
884 case 512: return 2;
885 case 1024: return 3;
886 case 2048: return 4;
887 case 4096: return 5;
888 default:
889 pr_warn("invalid mtu\n");
890 return -1;
e126ba97 891 }
1b5daf11 892}
e126ba97 893
1b5daf11
MD		 894enum ib_max_vl_num {
895 __IB_MAX_VL_0 = 1,
896 __IB_MAX_VL_0_1 = 2,
897 __IB_MAX_VL_0_3 = 3,
898 __IB_MAX_VL_0_7 = 4,
899 __IB_MAX_VL_0_14 = 5,
900};
e126ba97 901
1b5daf11
MD		 902enum mlx5_vl_hw_cap {
903 MLX5_VL_HW_0 = 1,
904 MLX5_VL_HW_0_1 = 2,
905 MLX5_VL_HW_0_2 = 3,
906 MLX5_VL_HW_0_3 = 4,
907 MLX5_VL_HW_0_4 = 5,
908 MLX5_VL_HW_0_5 = 6,
909 MLX5_VL_HW_0_6 = 7,
910 MLX5_VL_HW_0_7 = 8,
911 MLX5_VL_HW_0_14 = 15
912};
e126ba97 913
1b5daf11
MD		 914static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
915 u8 *max_vl_num)
916{
917 switch (vl_hw_cap) {
918 case MLX5_VL_HW_0:
919 *max_vl_num = __IB_MAX_VL_0;
920 break;
921 case MLX5_VL_HW_0_1:
922 *max_vl_num = __IB_MAX_VL_0_1;
923 break;
924 case MLX5_VL_HW_0_3:
925 *max_vl_num = __IB_MAX_VL_0_3;
926 break;
927 case MLX5_VL_HW_0_7:
928 *max_vl_num = __IB_MAX_VL_0_7;
929 break;
930 case MLX5_VL_HW_0_14:
931 *max_vl_num = __IB_MAX_VL_0_14;
932 break;
e126ba97 933
1b5daf11
MD		 934 default:
935 return -EINVAL;
e126ba97 936 }
e126ba97 937
1b5daf11 938 return 0;
e126ba97
EC		 939}
940
1b5daf11
MD		 941static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
942 struct ib_port_attr *props)
e126ba97 943{
1b5daf11
MD		 944 struct mlx5_ib_dev *dev = to_mdev(ibdev);
945 struct mlx5_core_dev *mdev = dev->mdev;
946 struct mlx5_hca_vport_context *rep;
046339ea
SM		 947 u16 max_mtu;
948 u16 oper_mtu;
1b5daf11
MD		 949 int err;
950 u8 ib_link_width_oper;
951 u8 vl_hw_cap;
e126ba97 952
1b5daf11
MD		 953 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
954 if (!rep) {
955 err = -ENOMEM;
e126ba97 956 goto out;
e126ba97 957 }
e126ba97 958
c4550c63 959 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 960
1b5daf11 961 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 962 if (err)
963 goto out;
964
1b5daf11
MD		 965 props->lid = rep->lid;
966 props->lmc = rep->lmc;
967 props->sm_lid = rep->sm_lid;
968 props->sm_sl = rep->sm_sl;
969 props->state = rep->vport_state;
970 props->phys_state = rep->port_physical_state;
971 props->port_cap_flags = rep->cap_mask1;
972 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
973 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
974 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
975 props->bad_pkey_cntr = rep->pkey_violation_counter;
976 props->qkey_viol_cntr = rep->qkey_violation_counter;
977 props->subnet_timeout = rep->subnet_timeout;
978 props->init_type_reply = rep->init_type_reply;
eff901d3 979 props->grh_required = rep->grh_required;
e126ba97 980
1b5daf11
MD		 981 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
982 if (err)
e126ba97 983 goto out;
e126ba97 984
1b5daf11
MD		 985 err = translate_active_width(ibdev, ib_link_width_oper,
986 &props->active_width);
987 if (err)
988 goto out;
d5beb7f2 989 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 990 if (err)
991 goto out;
992
facc9699 993 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 994
1b5daf11 995 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 996
facc9699 997 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 998
1b5daf11 999 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1000
1b5daf11
MD		 1001 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1002 if (err)
1003 goto out;
e126ba97 1004
1b5daf11
MD		 1005 err = translate_max_vl_num(ibdev, vl_hw_cap,
1006 &props->max_vl_num);
e126ba97 1007out:
1b5daf11 1008 kfree(rep);
e126ba97
EC		 1009 return err;
1010}
1011
1b5daf11
MD		 1012int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1013 struct ib_port_attr *props)
e126ba97 1014{
095b0927
IT		 1015 unsigned int count;
1016 int ret;
1017
1b5daf11
MD		 1018 switch (mlx5_get_vport_access_method(ibdev)) {
1019 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1020 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1021 break;
e126ba97 1022
1b5daf11 1023 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1024 ret = mlx5_query_hca_port(ibdev, port, props);
1025 break;
e126ba97 1026
3f89a643 1027 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1028 ret = mlx5_query_port_roce(ibdev, port, props);
1029 break;
3f89a643 1030
1b5daf11 1031 default:
095b0927
IT		 1032 ret = -EINVAL;
1033 }
1034
1035 if (!ret && props) {
1036 count = mlx5_core_reserved_gids_count(to_mdev(ibdev)->mdev);
1037 props->gid_tbl_len -= count;
1b5daf11 1038 }
095b0927 1039 return ret;
1b5daf11 1040}
e126ba97 1041
1b5daf11
MD		 1042static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1043 union ib_gid *gid)
1044{
1045 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1046 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1047
1b5daf11
MD		 1048 switch (mlx5_get_vport_access_method(ibdev)) {
1049 case MLX5_VPORT_ACCESS_METHOD_MAD:
1050 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1051
1b5daf11
MD		 1052 case MLX5_VPORT_ACCESS_METHOD_HCA:
1053 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1054
1055 default:
1056 return -EINVAL;
1057 }
e126ba97 1058
e126ba97
EC		 1059}
1060
1b5daf11
MD		 1061static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1062 u16 *pkey)
1063{
1064 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1065 struct mlx5_core_dev *mdev = dev->mdev;
1066
1067 switch (mlx5_get_vport_access_method(ibdev)) {
1068 case MLX5_VPORT_ACCESS_METHOD_MAD:
1069 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1070
1071 case MLX5_VPORT_ACCESS_METHOD_HCA:
1072 case MLX5_VPORT_ACCESS_METHOD_NIC:
1073 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
1074 pkey);
1075 default:
1076 return -EINVAL;
1077 }
1078}
e126ba97
EC		 1079
1080static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1081 struct ib_device_modify *props)
1082{
1083 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1084 struct mlx5_reg_node_desc in;
1085 struct mlx5_reg_node_desc out;
1086 int err;
1087
1088 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1089 return -EOPNOTSUPP;
1090
1091 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1092 return 0;
1093
1094 /*
1095 * If possible, pass node desc to FW, so it can generate
1096 * a 144 trap. If cmd fails, just ignore.
1097 */
bd99fdea 1098 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1099 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1100 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1101 if (err)
1102 return err;
1103
bd99fdea 1104 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1105
1106 return err;
1107}
1108
cdbe33d0
EC		 1109static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1110 u32 value)
1111{
1112 struct mlx5_hca_vport_context ctx = {};
1113 int err;
1114
1115 err = mlx5_query_hca_vport_context(dev->mdev, 0,
1116 port_num, 0, &ctx);
1117 if (err)
1118 return err;
1119
1120 if (~ctx.cap_mask1_perm & mask) {
1121 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1122 mask, ctx.cap_mask1_perm);
1123 return -EINVAL;
1124 }
1125
1126 ctx.cap_mask1 = value;
1127 ctx.cap_mask1_perm = mask;
1128 err = mlx5_core_modify_hca_vport_context(dev->mdev, 0,
1129 port_num, 0, &ctx);
1130
1131 return err;
1132}
1133
e126ba97
EC		 1134static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1135 struct ib_port_modify *props)
1136{
1137 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1138 struct ib_port_attr attr;
1139 u32 tmp;
1140 int err;
cdbe33d0
EC		 1141 u32 change_mask;
1142 u32 value;
1143 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1144 IB_LINK_LAYER_INFINIBAND);
1145
ec255879
MD		 1146 /* CM layer calls ib_modify_port() regardless of the link layer. For
1147 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1148 */
1149 if (!is_ib)
1150 return 0;
1151
cdbe33d0
EC		 1152 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1153 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1154 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1155 return set_port_caps_atomic(dev, port, change_mask, value);
1156 }
e126ba97
EC		 1157
1158 mutex_lock(&dev->cap_mask_mutex);
1159
c4550c63 1160 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1161 if (err)
1162 goto out;
1163
1164 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1165 ~props->clr_port_cap_mask;
1166
9603b61d 1167 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1168
1169out:
1170 mutex_unlock(&dev->cap_mask_mutex);
1171 return err;
1172}
1173
30aa60b3
EC		 1174static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1175{
1176 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1177 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1178}
1179
b037c29a
EC		 1180static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1181 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1182 u32 *num_sys_pages)
1183{
1184 int uars_per_sys_page;
1185 int bfregs_per_sys_page;
1186 int ref_bfregs = req->total_num_bfregs;
1187
1188 if (req->total_num_bfregs == 0)
1189 return -EINVAL;
1190
1191 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1192 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1193
1194 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1195 return -ENOMEM;
1196
1197 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1198 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1199 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1200 *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1201
1202 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1203 return -EINVAL;
1204
9c2d33d4 1205 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, using %d sys pages\n",
b037c29a
EC		 1206 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1207 lib_uar_4k ? "yes" : "no", ref_bfregs,
1208 req->total_num_bfregs, *num_sys_pages);
1209
1210 return 0;
1211}
1212
1213static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1214{
1215 struct mlx5_bfreg_info *bfregi;
1216 int err;
1217 int i;
1218
1219 bfregi = &context->bfregi;
1220 for (i = 0; i < bfregi->num_sys_pages; i++) {
1221 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1222 if (err)
1223 goto error;
1224
1225 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1226 }
1227 return 0;
1228
1229error:
1230 for (--i; i >= 0; i--)
1231 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1232 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1233
1234 return err;
1235}
1236
1237static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1238{
1239 struct mlx5_bfreg_info *bfregi;
1240 int err;
1241 int i;
1242
1243 bfregi = &context->bfregi;
1244 for (i = 0; i < bfregi->num_sys_pages; i++) {
1245 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1246 if (err) {
1247 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1248 return err;
1249 }
1250 }
1251 return 0;
1252}
1253
c85023e1
HN		 1254static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1255{
1256 int err;
1257
1258 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1259 if (err)
1260 return err;
1261
1262 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1263 !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1264 return err;
1265
1266 mutex_lock(&dev->lb_mutex);
1267 dev->user_td++;
1268
1269 if (dev->user_td == 2)
1270 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1271
1272 mutex_unlock(&dev->lb_mutex);
1273 return err;
1274}
1275
1276static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1277{
1278 mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1279
1280 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1281 !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1282 return;
1283
1284 mutex_lock(&dev->lb_mutex);
1285 dev->user_td--;
1286
1287 if (dev->user_td < 2)
1288 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1289
1290 mutex_unlock(&dev->lb_mutex);
1291}
1292
e126ba97
EC		 1293static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1294 struct ib_udata *udata)
1295{
1296 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1297 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1298 struct mlx5_ib_alloc_ucontext_resp resp = {};
e126ba97 1299 struct mlx5_ib_ucontext *context;
2f5ff264 1300 struct mlx5_bfreg_info *bfregi;
78c0f98c 1301 int ver;
e126ba97 1302 int err;
a168a41c
MD		 1303 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1304 max_cqe_version);
b037c29a 1305 bool lib_uar_4k;
e126ba97
EC		 1306
1307 if (!dev->ib_active)
1308 return ERR_PTR(-EAGAIN);
1309
e093111d 1310 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1311 ver = 0;
e093111d 1312 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1313 ver = 2;
1314 else
1315 return ERR_PTR(-EINVAL);
1316
e093111d 1317 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97
EC		 1318 if (err)
1319 return ERR_PTR(err);
1320
b368d7cb 1321 if (req.flags)
78c0f98c
EC		 1322 return ERR_PTR(-EINVAL);
1323
f72300c5 1324 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 1325 return ERR_PTR(-EOPNOTSUPP);
1326
2f5ff264
EC		 1327 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1328 MLX5_NON_FP_BFREGS_PER_UAR);
1329 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
e126ba97
EC		 1330 return ERR_PTR(-EINVAL);
1331
938fe83c 1332 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1333 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1334 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1335 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1336 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1337 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1338 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1339 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1340 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1341 resp.cqe_version = min_t(__u8,
1342 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1343 req.max_cqe_version);
30aa60b3
EC		 1344 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1345 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1346 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1347 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1348 resp.response_length = min(offsetof(typeof(resp), response_length) +
1349 sizeof(resp.response_length), udata->outlen);
e126ba97
EC		 1350
1351 context = kzalloc(sizeof(*context), GFP_KERNEL);
1352 if (!context)
1353 return ERR_PTR(-ENOMEM);
1354
30aa60b3 1355 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1356 bfregi = &context->bfregi;
b037c29a
EC		 1357
1358 /* updates req->total_num_bfregs */
1359 err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages);
1360 if (err)
e126ba97 1361 goto out_ctx;
e126ba97 1362
b037c29a
EC		 1363 mutex_init(&bfregi->lock);
1364 bfregi->lib_uar_4k = lib_uar_4k;
1365 bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1366 GFP_KERNEL);
b037c29a 1367 if (!bfregi->count) {
e126ba97 1368 err = -ENOMEM;
b037c29a 1369 goto out_ctx;
e126ba97
EC		 1370 }
1371
b037c29a
EC		 1372 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1373 sizeof(*bfregi->sys_pages),
1374 GFP_KERNEL);
1375 if (!bfregi->sys_pages) {
e126ba97 1376 err = -ENOMEM;
b037c29a 1377 goto out_count;
e126ba97
EC		 1378 }
1379
b037c29a
EC		 1380 err = allocate_uars(dev, context);
1381 if (err)
1382 goto out_sys_pages;
e126ba97 1383
b4cfe447
HE		 1384#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1385 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1386#endif
1387
7d0cc6ed
AK		 1388 context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1389 if (!context->upd_xlt_page) {
1390 err = -ENOMEM;
1391 goto out_uars;
1392 }
1393 mutex_init(&context->upd_xlt_page_mutex);
1394
146d2f1a 1395 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
c85023e1 1396 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
146d2f1a 1397 if (err)
7d0cc6ed 1398 goto out_page;
146d2f1a 1399 }
1400
7c2344c3 1401 INIT_LIST_HEAD(&context->vma_private_list);
e126ba97
EC		 1402 INIT_LIST_HEAD(&context->db_page_list);
1403 mutex_init(&context->db_page_mutex);
1404
2f5ff264 1405 resp.tot_bfregs = req.total_num_bfregs;
938fe83c 1406 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
b368d7cb 1407
f72300c5
HA		 1408 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1409 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1410
402ca536 1411 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1412 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1413 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1414 resp.response_length += sizeof(resp.cmds_supp_uhw);
1415 }
1416
78984898
OG		 1417 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1418 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1419 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1420 resp.eth_min_inline++;
1421 }
1422 resp.response_length += sizeof(resp.eth_min_inline);
1423 }
1424
bc5c6eed
NO		 1425 /*
1426 * We don't want to expose information from the PCI bar that is located
1427 * after 4096 bytes, so if the arch only supports larger pages, let's
1428 * pretend we don't support reading the HCA's core clock. This is also
1429 * forced by mmap function.
1430 */
de8d6e02
EC		 1431 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1432 if (PAGE_SIZE <= 4096) {
1433 resp.comp_mask |=
1434 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1435 resp.hca_core_clock_offset =
1436 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1437 }
f72300c5 1438 resp.response_length += sizeof(resp.hca_core_clock_offset) +
402ca536 1439 sizeof(resp.reserved2);
b368d7cb
MB		 1440 }
1441
30aa60b3
EC		 1442 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1443 resp.response_length += sizeof(resp.log_uar_size);
1444
1445 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1446 resp.response_length += sizeof(resp.num_uars_per_page);
1447
b368d7cb 1448 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1449 if (err)
146d2f1a 1450 goto out_td;
e126ba97 1451
2f5ff264
EC		 1452 bfregi->ver = ver;
1453 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1454 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1455 context->lib_caps = req.lib_caps;
1456 print_lib_caps(dev, context->lib_caps);
f72300c5 1457
e126ba97
EC		 1458 return &context->ibucontext;
1459
146d2f1a 1460out_td:
1461 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
c85023e1 1462 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1463
7d0cc6ed
AK		 1464out_page:
1465 free_page(context->upd_xlt_page);
1466
e126ba97 1467out_uars:
b037c29a 1468 deallocate_uars(dev, context);
e126ba97 1469
b037c29a
EC		 1470out_sys_pages:
1471 kfree(bfregi->sys_pages);
e126ba97 1472
b037c29a
EC		 1473out_count:
1474 kfree(bfregi->count);
e126ba97
EC		 1475
1476out_ctx:
1477 kfree(context);
b037c29a 1478
e126ba97
EC		 1479 return ERR_PTR(err);
1480}
1481
1482static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1483{
1484 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1485 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 1486 struct mlx5_bfreg_info *bfregi;
e126ba97 1487
b037c29a 1488 bfregi = &context->bfregi;
146d2f1a 1489 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
c85023e1 1490 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1491
7d0cc6ed 1492 free_page(context->upd_xlt_page);
b037c29a
EC		 1493 deallocate_uars(dev, context);
1494 kfree(bfregi->sys_pages);
2f5ff264 1495 kfree(bfregi->count);
e126ba97
EC		 1496 kfree(context);
1497
1498 return 0;
1499}
1500
b037c29a
EC		 1501static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1502 struct mlx5_bfreg_info *bfregi,
1503 int idx)
e126ba97 1504{
b037c29a
EC		 1505 int fw_uars_per_page;
1506
1507 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1508
1509 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) +
1510 bfregi->sys_pages[idx] / fw_uars_per_page;
e126ba97
EC		 1511}
1512
1513static int get_command(unsigned long offset)
1514{
1515 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1516}
1517
1518static int get_arg(unsigned long offset)
1519{
1520 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1521}
1522
1523static int get_index(unsigned long offset)
1524{
1525 return get_arg(offset);
1526}
1527
7c2344c3
MG		 1528static void mlx5_ib_vma_open(struct vm_area_struct *area)
1529{
1530 /* vma_open is called when a new VMA is created on top of our VMA. This
1531 * is done through either mremap flow or split_vma (usually due to
1532 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1533 * as this VMA is strongly hardware related. Therefore we set the
1534 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1535 * calling us again and trying to do incorrect actions. We assume that
1536 * the original VMA size is exactly a single page, and therefore all
1537 * "splitting" operation will not happen to it.
1538 */
1539 area->vm_ops = NULL;
1540}
1541
1542static void mlx5_ib_vma_close(struct vm_area_struct *area)
1543{
1544 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1545
1546 /* It's guaranteed that all VMAs opened on a FD are closed before the
1547 * file itself is closed, therefore no sync is needed with the regular
1548 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1549 * However need a sync with accessing the vma as part of
1550 * mlx5_ib_disassociate_ucontext.
1551 * The close operation is usually called under mm->mmap_sem except when
1552 * process is exiting.
1553 * The exiting case is handled explicitly as part of
1554 * mlx5_ib_disassociate_ucontext.
1555 */
1556 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1557
1558 /* setting the vma context pointer to null in the mlx5_ib driver's
1559 * private data, to protect a race condition in
1560 * mlx5_ib_disassociate_ucontext().
1561 */
1562 mlx5_ib_vma_priv_data->vma = NULL;
1563 list_del(&mlx5_ib_vma_priv_data->list);
1564 kfree(mlx5_ib_vma_priv_data);
1565}
1566
1567static const struct vm_operations_struct mlx5_ib_vm_ops = {
1568 .open = mlx5_ib_vma_open,
1569 .close = mlx5_ib_vma_close
1570};
1571
1572static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1573 struct mlx5_ib_ucontext *ctx)
1574{
1575 struct mlx5_ib_vma_private_data *vma_prv;
1576 struct list_head *vma_head = &ctx->vma_private_list;
1577
1578 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1579 if (!vma_prv)
1580 return -ENOMEM;
1581
1582 vma_prv->vma = vma;
1583 vma->vm_private_data = vma_prv;
1584 vma->vm_ops = &mlx5_ib_vm_ops;
1585
1586 list_add(&vma_prv->list, vma_head);
1587
1588 return 0;
1589}
1590
1591static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1592{
1593 int ret;
1594 struct vm_area_struct *vma;
1595 struct mlx5_ib_vma_private_data *vma_private, *n;
1596 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1597 struct task_struct *owning_process = NULL;
1598 struct mm_struct *owning_mm = NULL;
1599
1600 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1601 if (!owning_process)
1602 return;
1603
1604 owning_mm = get_task_mm(owning_process);
1605 if (!owning_mm) {
1606 pr_info("no mm, disassociate ucontext is pending task termination\n");
1607 while (1) {
1608 put_task_struct(owning_process);
1609 usleep_range(1000, 2000);
1610 owning_process = get_pid_task(ibcontext->tgid,
1611 PIDTYPE_PID);
1612 if (!owning_process ||
1613 owning_process->state == TASK_DEAD) {
1614 pr_info("disassociate ucontext done, task was terminated\n");
1615 /* in case task was dead need to release the
1616 * task struct.
1617 */
1618 if (owning_process)
1619 put_task_struct(owning_process);
1620 return;
1621 }
1622 }
1623 }
1624
1625 /* need to protect from a race on closing the vma as part of
1626 * mlx5_ib_vma_close.
1627 */
ecc7d83b 1628 down_write(&owning_mm->mmap_sem);
7c2344c3
MG		 1629 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1630 list) {
1631 vma = vma_private->vma;
1632 ret = zap_vma_ptes(vma, vma->vm_start,
1633 PAGE_SIZE);
1634 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1635 /* context going to be destroyed, should
1636 * not access ops any more.
1637 */
13776612 1638 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
7c2344c3
MG		 1639 vma->vm_ops = NULL;
1640 list_del(&vma_private->list);
1641 kfree(vma_private);
1642 }
ecc7d83b 1643 up_write(&owning_mm->mmap_sem);
7c2344c3
MG		 1644 mmput(owning_mm);
1645 put_task_struct(owning_process);
1646}
1647
37aa5c36
GL		 1648static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1649{
1650 switch (cmd) {
1651 case MLX5_IB_MMAP_WC_PAGE:
1652 return "WC";
1653 case MLX5_IB_MMAP_REGULAR_PAGE:
1654 return "best effort WC";
1655 case MLX5_IB_MMAP_NC_PAGE:
1656 return "NC";
1657 default:
1658 return NULL;
1659 }
1660}
1661
1662static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 1663 struct vm_area_struct *vma,
1664 struct mlx5_ib_ucontext *context)
37aa5c36 1665{
2f5ff264 1666 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 1667 int err;
1668 unsigned long idx;
1669 phys_addr_t pfn, pa;
1670 pgprot_t prot;
b037c29a
EC		 1671 int uars_per_page;
1672
1673 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1674 return -EINVAL;
1675
1676 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
1677 idx = get_index(vma->vm_pgoff);
1678 if (idx % uars_per_page ||
1679 idx * uars_per_page >= bfregi->num_sys_pages) {
1680 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx);
1681 return -EINVAL;
1682 }
37aa5c36
GL		 1683
1684 switch (cmd) {
1685 case MLX5_IB_MMAP_WC_PAGE:
1686/* Some architectures don't support WC memory */
1687#if defined(CONFIG_X86)
1688 if (!pat_enabled())
1689 return -EPERM;
1690#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1691 return -EPERM;
1692#endif
1693 /* fall through */
1694 case MLX5_IB_MMAP_REGULAR_PAGE:
1695 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1696 prot = pgprot_writecombine(vma->vm_page_prot);
1697 break;
1698 case MLX5_IB_MMAP_NC_PAGE:
1699 prot = pgprot_noncached(vma->vm_page_prot);
1700 break;
1701 default:
1702 return -EINVAL;
1703 }
1704
b037c29a 1705 pfn = uar_index2pfn(dev, bfregi, idx);
37aa5c36
GL		 1706 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1707
1708 vma->vm_page_prot = prot;
1709 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1710 PAGE_SIZE, vma->vm_page_prot);
1711 if (err) {
1712 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1713 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1714 return -EAGAIN;
1715 }
1716
1717 pa = pfn << PAGE_SHIFT;
1718 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1719 vma->vm_start, &pa);
1720
7c2344c3 1721 return mlx5_ib_set_vma_data(vma, context);
37aa5c36
GL		 1722}
1723
e126ba97
EC		 1724static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1725{
1726 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1727 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 1728 unsigned long command;
e126ba97
EC		 1729 phys_addr_t pfn;
1730
1731 command = get_command(vma->vm_pgoff);
1732 switch (command) {
37aa5c36
GL		 1733 case MLX5_IB_MMAP_WC_PAGE:
1734 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 1735 case MLX5_IB_MMAP_REGULAR_PAGE:
7c2344c3 1736 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 1737
1738 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1739 return -ENOSYS;
1740
d69e3bcf 1741 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 1742 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1743 return -EINVAL;
1744
6cbac1e4 1745 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 1746 return -EPERM;
1747
1748 /* Don't expose to user-space information it shouldn't have */
1749 if (PAGE_SIZE > 4096)
1750 return -EOPNOTSUPP;
1751
1752 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1753 pfn = (dev->mdev->iseg_base +
1754 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1755 PAGE_SHIFT;
1756 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1757 PAGE_SIZE, vma->vm_page_prot))
1758 return -EAGAIN;
1759
1760 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1761 vma->vm_start,
1762 (unsigned long long)pfn << PAGE_SHIFT);
1763 break;
d69e3bcf 1764
e126ba97
EC		 1765 default:
1766 return -EINVAL;
1767 }
1768
1769 return 0;
1770}
1771
e126ba97
EC		 1772static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1773 struct ib_ucontext *context,
1774 struct ib_udata *udata)
1775{
1776 struct mlx5_ib_alloc_pd_resp resp;
1777 struct mlx5_ib_pd *pd;
1778 int err;
1779
1780 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1781 if (!pd)
1782 return ERR_PTR(-ENOMEM);
1783
9603b61d 1784 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 1785 if (err) {
1786 kfree(pd);
1787 return ERR_PTR(err);
1788 }
1789
1790 if (context) {
1791 resp.pdn = pd->pdn;
1792 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 1793 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 1794 kfree(pd);
1795 return ERR_PTR(-EFAULT);
1796 }
e126ba97
EC		 1797 }
1798
1799 return &pd->ibpd;
1800}
1801
1802static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1803{
1804 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1805 struct mlx5_ib_pd *mpd = to_mpd(pd);
1806
9603b61d 1807 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 1808 kfree(mpd);
1809
1810 return 0;
1811}
1812
466fa6d2
MG		 1813enum {
1814 MATCH_CRITERIA_ENABLE_OUTER_BIT,
1815 MATCH_CRITERIA_ENABLE_MISC_BIT,
1816 MATCH_CRITERIA_ENABLE_INNER_BIT
1817};
1818
1819#define HEADER_IS_ZERO(match_criteria, headers) \
1820 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1821 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 1822
466fa6d2 1823static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 1824{
466fa6d2 1825 u8 match_criteria_enable;
038d2ef8 1826
466fa6d2
MG		 1827 match_criteria_enable =
1828 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1829 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1830 match_criteria_enable |=
1831 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1832 MATCH_CRITERIA_ENABLE_MISC_BIT;
1833 match_criteria_enable |=
1834 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1835 MATCH_CRITERIA_ENABLE_INNER_BIT;
1836
1837 return match_criteria_enable;
038d2ef8
MG		 1838}
1839
ca0d4753
MG		 1840static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1841{
1842 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1843 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
038d2ef8
MG		 1844}
1845
2d1e697e
MR		 1846static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
1847 bool inner)
1848{
1849 if (inner) {
1850 MLX5_SET(fte_match_set_misc,
1851 misc_c, inner_ipv6_flow_label, mask);
1852 MLX5_SET(fte_match_set_misc,
1853 misc_v, inner_ipv6_flow_label, val);
1854 } else {
1855 MLX5_SET(fte_match_set_misc,
1856 misc_c, outer_ipv6_flow_label, mask);
1857 MLX5_SET(fte_match_set_misc,
1858 misc_v, outer_ipv6_flow_label, val);
1859 }
1860}
1861
ca0d4753
MG		 1862static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1863{
1864 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1865 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1866 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1867 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1868}
1869
c47ac6ae
MG		 1870#define LAST_ETH_FIELD vlan_tag
1871#define LAST_IB_FIELD sl
ca0d4753 1872#define LAST_IPV4_FIELD tos
466fa6d2 1873#define LAST_IPV6_FIELD traffic_class
c47ac6ae 1874#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 1875#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 1876#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 1877#define LAST_DROP_FIELD size
c47ac6ae
MG		 1878
1879/* Field is the last supported field */
1880#define FIELDS_NOT_SUPPORTED(filter, field)\
1881 memchr_inv((void *)&filter.field +\
1882 sizeof(filter.field), 0,\
1883 sizeof(filter) -\
1884 offsetof(typeof(filter), field) -\
1885 sizeof(filter.field))
1886
19cc7524
AL		 1887#define IPV4_VERSION 4
1888#define IPV6_VERSION 6
1889static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
1890 u32 *match_v, const union ib_flow_spec *ib_spec,
a22ed86c 1891 u32 *tag_id, bool *is_drop)
038d2ef8 1892{
466fa6d2
MG		 1893 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1894 misc_parameters);
1895 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1896 misc_parameters);
2d1e697e
MR		 1897 void *headers_c;
1898 void *headers_v;
19cc7524 1899 int match_ipv;
2d1e697e
MR		 1900
1901 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
1902 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1903 inner_headers);
1904 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1905 inner_headers);
19cc7524
AL		 1906 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1907 ft_field_support.inner_ip_version);
2d1e697e
MR		 1908 } else {
1909 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1910 outer_headers);
1911 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1912 outer_headers);
19cc7524
AL		 1913 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1914 ft_field_support.outer_ip_version);
2d1e697e 1915 }
466fa6d2 1916
2d1e697e 1917 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 1918 case IB_FLOW_SPEC_ETH:
c47ac6ae 1919 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 1920 return -EOPNOTSUPP;
038d2ef8 1921
2d1e697e 1922 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1923 dmac_47_16),
1924 ib_spec->eth.mask.dst_mac);
2d1e697e 1925 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1926 dmac_47_16),
1927 ib_spec->eth.val.dst_mac);
1928
2d1e697e 1929 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 1930 smac_47_16),
1931 ib_spec->eth.mask.src_mac);
2d1e697e 1932 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 1933 smac_47_16),
1934 ib_spec->eth.val.src_mac);
1935
038d2ef8 1936 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 1937 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 1938 cvlan_tag, 1);
2d1e697e 1939 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 1940 cvlan_tag, 1);
038d2ef8 1941
2d1e697e 1942 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 1943 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 1944 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1945 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1946
2d1e697e 1947 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1948 first_cfi,
1949 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 1950 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1951 first_cfi,
1952 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1953
2d1e697e 1954 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1955 first_prio,
1956 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 1957 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1958 first_prio,
1959 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1960 }
2d1e697e 1961 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 1962 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 1963 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1964 ethertype, ntohs(ib_spec->eth.val.ether_type));
1965 break;
1966 case IB_FLOW_SPEC_IPV4:
c47ac6ae 1967 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 1968 return -EOPNOTSUPP;
038d2ef8 1969
19cc7524
AL		 1970 if (match_ipv) {
1971 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1972 ip_version, 0xf);
1973 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1974 ip_version, IPV4_VERSION);
1975 } else {
1976 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1977 ethertype, 0xffff);
1978 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1979 ethertype, ETH_P_IP);
1980 }
038d2ef8 1981
2d1e697e 1982 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1983 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1984 &ib_spec->ipv4.mask.src_ip,
1985 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 1986 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1987 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1988 &ib_spec->ipv4.val.src_ip,
1989 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 1990 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1991 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1992 &ib_spec->ipv4.mask.dst_ip,
1993 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 1994 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1995 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1996 &ib_spec->ipv4.val.dst_ip,
1997 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 1998
2d1e697e 1999 set_tos(headers_c, headers_v,
ca0d4753
MG		 2000 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2001
2d1e697e 2002 set_proto(headers_c, headers_v,
ca0d4753 2003 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
038d2ef8 2004 break;
026bae0c 2005 case IB_FLOW_SPEC_IPV6:
c47ac6ae 2006 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 2007 return -EOPNOTSUPP;
026bae0c 2008
19cc7524
AL		 2009 if (match_ipv) {
2010 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2011 ip_version, 0xf);
2012 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2013 ip_version, IPV6_VERSION);
2014 } else {
2015 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2016 ethertype, 0xffff);
2017 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2018 ethertype, ETH_P_IPV6);
2019 }
026bae0c 2020
2d1e697e 2021 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2022 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2023 &ib_spec->ipv6.mask.src_ip,
2024 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2025 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2026 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2027 &ib_spec->ipv6.val.src_ip,
2028 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2029 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2030 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2031 &ib_spec->ipv6.mask.dst_ip,
2032 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2033 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2034 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2035 &ib_spec->ipv6.val.dst_ip,
2036 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2037
2d1e697e 2038 set_tos(headers_c, headers_v,
466fa6d2
MG		 2039 ib_spec->ipv6.mask.traffic_class,
2040 ib_spec->ipv6.val.traffic_class);
2041
2d1e697e 2042 set_proto(headers_c, headers_v,
466fa6d2
MG		 2043 ib_spec->ipv6.mask.next_hdr,
2044 ib_spec->ipv6.val.next_hdr);
2045
2d1e697e
MR		 2046 set_flow_label(misc_params_c, misc_params_v,
2047 ntohl(ib_spec->ipv6.mask.flow_label),
2048 ntohl(ib_spec->ipv6.val.flow_label),
2049 ib_spec->type & IB_FLOW_SPEC_INNER);
2050
026bae0c 2051 break;
038d2ef8 2052 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2053 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2054 LAST_TCP_UDP_FIELD))
1ffd3a26 2055 return -EOPNOTSUPP;
038d2ef8 2056
2d1e697e 2057 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2058 0xff);
2d1e697e 2059 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2060 IPPROTO_TCP);
2061
2d1e697e 2062 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2063 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2064 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2065 ntohs(ib_spec->tcp_udp.val.src_port));
2066
2d1e697e 2067 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2068 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2069 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2070 ntohs(ib_spec->tcp_udp.val.dst_port));
2071 break;
2072 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2073 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2074 LAST_TCP_UDP_FIELD))
1ffd3a26 2075 return -EOPNOTSUPP;
038d2ef8 2076
2d1e697e 2077 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2078 0xff);
2d1e697e 2079 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2080 IPPROTO_UDP);
2081
2d1e697e 2082 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2083 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2084 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2085 ntohs(ib_spec->tcp_udp.val.src_port));
2086
2d1e697e 2087 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2088 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2089 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2090 ntohs(ib_spec->tcp_udp.val.dst_port));
2091 break;
ffb30d8f
MR		 2092 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2093 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2094 LAST_TUNNEL_FIELD))
1ffd3a26 2095 return -EOPNOTSUPP;
ffb30d8f
MR		 2096
2097 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2098 ntohl(ib_spec->tunnel.mask.tunnel_id));
2099 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2100 ntohl(ib_spec->tunnel.val.tunnel_id));
2101 break;
2ac693f9
MR		 2102 case IB_FLOW_SPEC_ACTION_TAG:
2103 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2104 LAST_FLOW_TAG_FIELD))
2105 return -EOPNOTSUPP;
2106 if (ib_spec->flow_tag.tag_id >= BIT(24))
2107 return -EINVAL;
2108
2109 *tag_id = ib_spec->flow_tag.tag_id;
2110 break;
a22ed86c
SS		 2111 case IB_FLOW_SPEC_ACTION_DROP:
2112 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2113 LAST_DROP_FIELD))
2114 return -EOPNOTSUPP;
2115 *is_drop = true;
2116 break;
038d2ef8
MG		 2117 default:
2118 return -EINVAL;
2119 }
2120
2121 return 0;
2122}
2123
2124/* If a flow could catch both multicast and unicast packets,
2125 * it won't fall into the multicast flow steering table and this rule
2126 * could steal other multicast packets.
2127 */
2128static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
2129{
81e30880 2130 union ib_flow_spec *flow_spec;
038d2ef8
MG		 2131
2132 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 2133 ib_attr->num_of_specs < 1)
2134 return false;
2135
81e30880
YH		 2136 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2137 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2138 struct ib_flow_spec_ipv4 *ipv4_spec;
2139
2140 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2141 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2142 return true;
2143
038d2ef8 2144 return false;
81e30880
YH		 2145 }
2146
2147 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2148 struct ib_flow_spec_eth *eth_spec;
2149
2150 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2151 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2152 is_multicast_ether_addr(eth_spec->val.dst_mac);
2153 }
038d2ef8 2154
81e30880 2155 return false;
038d2ef8
MG		 2156}
2157
19cc7524
AL		 2158static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2159 const struct ib_flow_attr *flow_attr,
0f750966 2160 bool check_inner)
038d2ef8
MG		 2161{
2162 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 2163 int match_ipv = check_inner ?
2164 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2165 ft_field_support.inner_ip_version) :
2166 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2167 ft_field_support.outer_ip_version);
0f750966
AL		 2168 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2169 bool ipv4_spec_valid, ipv6_spec_valid;
2170 unsigned int ip_spec_type = 0;
2171 bool has_ethertype = false;
038d2ef8 2172 unsigned int spec_index;
0f750966
AL		 2173 bool mask_valid = true;
2174 u16 eth_type = 0;
2175 bool type_valid;
038d2ef8
MG		 2176
2177 /* Validate that ethertype is correct */
2178 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 2179 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 2180 ib_spec->eth.mask.ether_type) {
0f750966
AL		 2181 mask_valid = (ib_spec->eth.mask.ether_type ==
2182 htons(0xffff));
2183 has_ethertype = true;
2184 eth_type = ntohs(ib_spec->eth.val.ether_type);
2185 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2186 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2187 ip_spec_type = ib_spec->type;
038d2ef8
MG		 2188 }
2189 ib_spec = (void *)ib_spec + ib_spec->size;
2190 }
0f750966
AL		 2191
2192 type_valid = (!has_ethertype) || (!ip_spec_type);
2193 if (!type_valid && mask_valid) {
2194 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2195 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2196 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2197 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 2198
2199 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2200 (((eth_type == ETH_P_MPLS_UC) ||
2201 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 2202 }
2203
2204 return type_valid;
2205}
2206
19cc7524
AL		 2207static bool is_valid_attr(struct mlx5_core_dev *mdev,
2208 const struct ib_flow_attr *flow_attr)
0f750966 2209{
19cc7524
AL		 2210 return is_valid_ethertype(mdev, flow_attr, false) &&
2211 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 2212}
2213
2214static void put_flow_table(struct mlx5_ib_dev *dev,
2215 struct mlx5_ib_flow_prio *prio, bool ft_added)
2216{
2217 prio->refcount -= !!ft_added;
2218 if (!prio->refcount) {
2219 mlx5_destroy_flow_table(prio->flow_table);
2220 prio->flow_table = NULL;
2221 }
2222}
2223
2224static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2225{
2226 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2227 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2228 struct mlx5_ib_flow_handler,
2229 ibflow);
2230 struct mlx5_ib_flow_handler *iter, *tmp;
2231
2232 mutex_lock(&dev->flow_db.lock);
2233
2234 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 2235 mlx5_del_flow_rules(iter->rule);
cc0e5d42 2236 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 2237 list_del(&iter->list);
2238 kfree(iter);
2239 }
2240
74491de9 2241 mlx5_del_flow_rules(handler->rule);
5497adc6 2242 put_flow_table(dev, handler->prio, true);
038d2ef8
MG		 2243 mutex_unlock(&dev->flow_db.lock);
2244
2245 kfree(handler);
2246
2247 return 0;
2248}
2249
35d19011
MG		 2250static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2251{
2252 priority *= 2;
2253 if (!dont_trap)
2254 priority++;
2255 return priority;
2256}
2257
cc0e5d42
MG		 2258enum flow_table_type {
2259 MLX5_IB_FT_RX,
2260 MLX5_IB_FT_TX
2261};
2262
00b7c2ab
MG		 2263#define MLX5_FS_MAX_TYPES 6
2264#define MLX5_FS_MAX_ENTRIES BIT(16)
038d2ef8 2265static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 2266 struct ib_flow_attr *flow_attr,
2267 enum flow_table_type ft_type)
038d2ef8 2268{
35d19011 2269 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 2270 struct mlx5_flow_namespace *ns = NULL;
2271 struct mlx5_ib_flow_prio *prio;
2272 struct mlx5_flow_table *ft;
dac388ef 2273 int max_table_size;
038d2ef8
MG		 2274 int num_entries;
2275 int num_groups;
2276 int priority;
2277 int err = 0;
2278
dac388ef
MG		 2279 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2280 log_max_ft_size));
038d2ef8 2281 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2282 if (flow_is_multicast_only(flow_attr) &&
2283 !dont_trap)
038d2ef8
MG		 2284 priority = MLX5_IB_FLOW_MCAST_PRIO;
2285 else
35d19011
MG		 2286 priority = ib_prio_to_core_prio(flow_attr->priority,
2287 dont_trap);
038d2ef8
MG		 2288 ns = mlx5_get_flow_namespace(dev->mdev,
2289 MLX5_FLOW_NAMESPACE_BYPASS);
2290 num_entries = MLX5_FS_MAX_ENTRIES;
2291 num_groups = MLX5_FS_MAX_TYPES;
2292 prio = &dev->flow_db.prios[priority];
2293 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2294 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2295 ns = mlx5_get_flow_namespace(dev->mdev,
2296 MLX5_FLOW_NAMESPACE_LEFTOVERS);
2297 build_leftovers_ft_param(&priority,
2298 &num_entries,
2299 &num_groups);
2300 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 2301 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2302 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2303 allow_sniffer_and_nic_rx_shared_tir))
2304 return ERR_PTR(-ENOTSUPP);
2305
2306 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2307 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2308 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2309
2310 prio = &dev->flow_db.sniffer[ft_type];
2311 priority = 0;
2312 num_entries = 1;
2313 num_groups = 1;
038d2ef8
MG		 2314 }
2315
2316 if (!ns)
2317 return ERR_PTR(-ENOTSUPP);
2318
dac388ef
MG		 2319 if (num_entries > max_table_size)
2320 return ERR_PTR(-ENOMEM);
2321
038d2ef8
MG		 2322 ft = prio->flow_table;
2323 if (!ft) {
2324 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2325 num_entries,
d63cd286 2326 num_groups,
c9f1b073 2327 0, 0);
038d2ef8
MG		 2328
2329 if (!IS_ERR(ft)) {
2330 prio->refcount = 0;
2331 prio->flow_table = ft;
2332 } else {
2333 err = PTR_ERR(ft);
2334 }
2335 }
2336
2337 return err ? ERR_PTR(err) : prio;
2338}
2339
2340static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2341 struct mlx5_ib_flow_prio *ft_prio,
dd063d0e 2342 const struct ib_flow_attr *flow_attr,
038d2ef8
MG		 2343 struct mlx5_flow_destination *dst)
2344{
2345 struct mlx5_flow_table *ft = ft_prio->flow_table;
2346 struct mlx5_ib_flow_handler *handler;
66958ed9 2347 struct mlx5_flow_act flow_act = {0};
c5bb1730 2348 struct mlx5_flow_spec *spec;
a22ed86c 2349 struct mlx5_flow_destination *rule_dst = dst;
dd063d0e 2350 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 2351 unsigned int spec_index;
2ac693f9 2352 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
a22ed86c 2353 bool is_drop = false;
038d2ef8 2354 int err = 0;
a22ed86c 2355 int dest_num = 1;
038d2ef8 2356
19cc7524 2357 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 2358 return ERR_PTR(-EINVAL);
2359
1b9a07ee 2360 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 2361 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 2362 if (!handler || !spec) {
038d2ef8
MG		 2363 err = -ENOMEM;
2364 goto free;
2365 }
2366
2367 INIT_LIST_HEAD(&handler->list);
2368
2369 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
19cc7524 2370 err = parse_flow_attr(dev->mdev, spec->match_criteria,
a22ed86c
SS		 2371 spec->match_value,
2372 ib_flow, &flow_tag, &is_drop);
038d2ef8
MG		 2373 if (err < 0)
2374 goto free;
2375
2376 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2377 }
2378
466fa6d2 2379 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
a22ed86c
SS		 2380 if (is_drop) {
2381 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2382 rule_dst = NULL;
2383 dest_num = 0;
2384 } else {
2385 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2386 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2387 }
2ac693f9
MR		 2388
2389 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG &&
2390 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2391 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
2392 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
2393 flow_tag, flow_attr->type);
2394 err = -EINVAL;
2395 goto free;
2396 }
2397 flow_act.flow_tag = flow_tag;
74491de9 2398 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 2399 &flow_act,
a22ed86c 2400 rule_dst, dest_num);
038d2ef8
MG		 2401
2402 if (IS_ERR(handler->rule)) {
2403 err = PTR_ERR(handler->rule);
2404 goto free;
2405 }
2406
d9d4980a 2407 ft_prio->refcount++;
5497adc6 2408 handler->prio = ft_prio;
038d2ef8
MG		 2409
2410 ft_prio->flow_table = ft;
2411free:
2412 if (err)
2413 kfree(handler);
c5bb1730 2414 kvfree(spec);
038d2ef8
MG		 2415 return err ? ERR_PTR(err) : handler;
2416}
2417
35d19011
MG		 2418static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2419 struct mlx5_ib_flow_prio *ft_prio,
2420 struct ib_flow_attr *flow_attr,
2421 struct mlx5_flow_destination *dst)
2422{
2423 struct mlx5_ib_flow_handler *handler_dst = NULL;
2424 struct mlx5_ib_flow_handler *handler = NULL;
2425
2426 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2427 if (!IS_ERR(handler)) {
2428 handler_dst = create_flow_rule(dev, ft_prio,
2429 flow_attr, dst);
2430 if (IS_ERR(handler_dst)) {
74491de9 2431 mlx5_del_flow_rules(handler->rule);
d9d4980a 2432 ft_prio->refcount--;
35d19011
MG		 2433 kfree(handler);
2434 handler = handler_dst;
2435 } else {
2436 list_add(&handler_dst->list, &handler->list);
2437 }
2438 }
2439
2440 return handler;
2441}
038d2ef8
MG		 2442enum {
2443 LEFTOVERS_MC,
2444 LEFTOVERS_UC,
2445};
2446
2447static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2448 struct mlx5_ib_flow_prio *ft_prio,
2449 struct ib_flow_attr *flow_attr,
2450 struct mlx5_flow_destination *dst)
2451{
2452 struct mlx5_ib_flow_handler *handler_ucast = NULL;
2453 struct mlx5_ib_flow_handler *handler = NULL;
2454
2455 static struct {
2456 struct ib_flow_attr flow_attr;
2457 struct ib_flow_spec_eth eth_flow;
2458 } leftovers_specs[] = {
2459 [LEFTOVERS_MC] = {
2460 .flow_attr = {
2461 .num_of_specs = 1,
2462 .size = sizeof(leftovers_specs[0])
2463 },
2464 .eth_flow = {
2465 .type = IB_FLOW_SPEC_ETH,
2466 .size = sizeof(struct ib_flow_spec_eth),
2467 .mask = {.dst_mac = {0x1} },
2468 .val = {.dst_mac = {0x1} }
2469 }
2470 },
2471 [LEFTOVERS_UC] = {
2472 .flow_attr = {
2473 .num_of_specs = 1,
2474 .size = sizeof(leftovers_specs[0])
2475 },
2476 .eth_flow = {
2477 .type = IB_FLOW_SPEC_ETH,
2478 .size = sizeof(struct ib_flow_spec_eth),
2479 .mask = {.dst_mac = {0x1} },
2480 .val = {.dst_mac = {} }
2481 }
2482 }
2483 };
2484
2485 handler = create_flow_rule(dev, ft_prio,
2486 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2487 dst);
2488 if (!IS_ERR(handler) &&
2489 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2490 handler_ucast = create_flow_rule(dev, ft_prio,
2491 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2492 dst);
2493 if (IS_ERR(handler_ucast)) {
74491de9 2494 mlx5_del_flow_rules(handler->rule);
d9d4980a 2495 ft_prio->refcount--;
038d2ef8
MG		 2496 kfree(handler);
2497 handler = handler_ucast;
2498 } else {
2499 list_add(&handler_ucast->list, &handler->list);
2500 }
2501 }
2502
2503 return handler;
2504}
2505
cc0e5d42
MG		 2506static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2507 struct mlx5_ib_flow_prio *ft_rx,
2508 struct mlx5_ib_flow_prio *ft_tx,
2509 struct mlx5_flow_destination *dst)
2510{
2511 struct mlx5_ib_flow_handler *handler_rx;
2512 struct mlx5_ib_flow_handler *handler_tx;
2513 int err;
2514 static const struct ib_flow_attr flow_attr = {
2515 .num_of_specs = 0,
2516 .size = sizeof(flow_attr)
2517 };
2518
2519 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2520 if (IS_ERR(handler_rx)) {
2521 err = PTR_ERR(handler_rx);
2522 goto err;
2523 }
2524
2525 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2526 if (IS_ERR(handler_tx)) {
2527 err = PTR_ERR(handler_tx);
2528 goto err_tx;
2529 }
2530
2531 list_add(&handler_tx->list, &handler_rx->list);
2532
2533 return handler_rx;
2534
2535err_tx:
74491de9 2536 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 2537 ft_rx->refcount--;
2538 kfree(handler_rx);
2539err:
2540 return ERR_PTR(err);
2541}
2542
038d2ef8
MG		 2543static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2544 struct ib_flow_attr *flow_attr,
2545 int domain)
2546{
2547 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 2548 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 2549 struct mlx5_ib_flow_handler *handler = NULL;
2550 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 2551 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8
MG		 2552 struct mlx5_ib_flow_prio *ft_prio;
2553 int err;
2554
2555 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
dac388ef 2556 return ERR_PTR(-ENOMEM);
038d2ef8
MG		 2557
2558 if (domain != IB_FLOW_DOMAIN_USER ||
2559 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
35d19011 2560 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
038d2ef8
MG		 2561 return ERR_PTR(-EINVAL);
2562
2563 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2564 if (!dst)
2565 return ERR_PTR(-ENOMEM);
2566
2567 mutex_lock(&dev->flow_db.lock);
2568
cc0e5d42 2569 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
038d2ef8
MG		 2570 if (IS_ERR(ft_prio)) {
2571 err = PTR_ERR(ft_prio);
2572 goto unlock;
2573 }
cc0e5d42
MG		 2574 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2575 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2576 if (IS_ERR(ft_prio_tx)) {
2577 err = PTR_ERR(ft_prio_tx);
2578 ft_prio_tx = NULL;
2579 goto destroy_ft;
2580 }
2581 }
038d2ef8
MG		 2582
2583 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
d9f88e5a
YH		 2584 if (mqp->flags & MLX5_IB_QP_RSS)
2585 dst->tir_num = mqp->rss_qp.tirn;
2586 else
2587 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
038d2ef8
MG		 2588
2589 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2590 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2591 handler = create_dont_trap_rule(dev, ft_prio,
2592 flow_attr, dst);
2593 } else {
2594 handler = create_flow_rule(dev, ft_prio, flow_attr,
2595 dst);
2596 }
038d2ef8
MG		 2597 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2598 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2599 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2600 dst);
cc0e5d42
MG		 2601 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2602 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 2603 } else {
2604 err = -EINVAL;
2605 goto destroy_ft;
2606 }
2607
2608 if (IS_ERR(handler)) {
2609 err = PTR_ERR(handler);
2610 handler = NULL;
2611 goto destroy_ft;
2612 }
2613
038d2ef8
MG		 2614 mutex_unlock(&dev->flow_db.lock);
2615 kfree(dst);
2616
2617 return &handler->ibflow;
2618
2619destroy_ft:
2620 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 2621 if (ft_prio_tx)
2622 put_flow_table(dev, ft_prio_tx, false);
038d2ef8
MG		 2623unlock:
2624 mutex_unlock(&dev->flow_db.lock);
2625 kfree(dst);
2626 kfree(handler);
2627 return ERR_PTR(err);
2628}
2629
e126ba97
EC		 2630static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2631{
2632 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 2633 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97
EC		 2634 int err;
2635
81e30880
YH		 2636 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
2637 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
2638 return -EOPNOTSUPP;
2639 }
2640
9603b61d 2641 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2642 if (err)
2643 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2644 ibqp->qp_num, gid->raw);
2645
2646 return err;
2647}
2648
2649static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2650{
2651 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2652 int err;
2653
9603b61d 2654 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2655 if (err)
2656 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2657 ibqp->qp_num, gid->raw);
2658
2659 return err;
2660}
2661
2662static int init_node_data(struct mlx5_ib_dev *dev)
2663{
1b5daf11 2664 int err;
e126ba97 2665
1b5daf11 2666 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 2667 if (err)
1b5daf11 2668 return err;
e126ba97 2669
1b5daf11 2670 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 2671
1b5daf11 2672 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 2673}
2674
2675static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2676 char *buf)
2677{
2678 struct mlx5_ib_dev *dev =
2679 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2680
9603b61d 2681 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 2682}
2683
2684static ssize_t show_reg_pages(struct device *device,
2685 struct device_attribute *attr, char *buf)
2686{
2687 struct mlx5_ib_dev *dev =
2688 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2689
6aec21f6 2690 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 2691}
2692
2693static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2694 char *buf)
2695{
2696 struct mlx5_ib_dev *dev =
2697 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 2698 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 2699}
2700
e126ba97
EC		 2701static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2702 char *buf)
2703{
2704 struct mlx5_ib_dev *dev =
2705 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 2706 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 2707}
2708
2709static ssize_t show_board(struct device *device, struct device_attribute *attr,
2710 char *buf)
2711{
2712 struct mlx5_ib_dev *dev =
2713 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2714 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 2715 dev->mdev->board_id);
e126ba97
EC		 2716}
2717
2718static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
e126ba97
EC		 2719static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2720static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2721static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2722static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2723
2724static struct device_attribute *mlx5_class_attributes[] = {
2725 &dev_attr_hw_rev,
e126ba97
EC		 2726 &dev_attr_hca_type,
2727 &dev_attr_board_id,
2728 &dev_attr_fw_pages,
2729 &dev_attr_reg_pages,
2730};
2731
7722f47e
HE		 2732static void pkey_change_handler(struct work_struct *work)
2733{
2734 struct mlx5_ib_port_resources *ports =
2735 container_of(work, struct mlx5_ib_port_resources,
2736 pkey_change_work);
2737
2738 mutex_lock(&ports->devr->mutex);
2739 mlx5_ib_gsi_pkey_change(ports->gsi);
2740 mutex_unlock(&ports->devr->mutex);
2741}
2742
89ea94a7
MG		 2743static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2744{
2745 struct mlx5_ib_qp *mqp;
2746 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2747 struct mlx5_core_cq *mcq;
2748 struct list_head cq_armed_list;
2749 unsigned long flags_qp;
2750 unsigned long flags_cq;
2751 unsigned long flags;
2752
2753 INIT_LIST_HEAD(&cq_armed_list);
2754
2755 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2756 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2757 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2758 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2759 if (mqp->sq.tail != mqp->sq.head) {
2760 send_mcq = to_mcq(mqp->ibqp.send_cq);
2761 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2762 if (send_mcq->mcq.comp &&
2763 mqp->ibqp.send_cq->comp_handler) {
2764 if (!send_mcq->mcq.reset_notify_added) {
2765 send_mcq->mcq.reset_notify_added = 1;
2766 list_add_tail(&send_mcq->mcq.reset_notify,
2767 &cq_armed_list);
2768 }
2769 }
2770 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2771 }
2772 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2773 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2774 /* no handling is needed for SRQ */
2775 if (!mqp->ibqp.srq) {
2776 if (mqp->rq.tail != mqp->rq.head) {
2777 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2778 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2779 if (recv_mcq->mcq.comp &&
2780 mqp->ibqp.recv_cq->comp_handler) {
2781 if (!recv_mcq->mcq.reset_notify_added) {
2782 recv_mcq->mcq.reset_notify_added = 1;
2783 list_add_tail(&recv_mcq->mcq.reset_notify,
2784 &cq_armed_list);
2785 }
2786 }
2787 spin_unlock_irqrestore(&recv_mcq->lock,
2788 flags_cq);
2789 }
2790 }
2791 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2792 }
2793 /*At that point all inflight post send were put to be executed as of we
2794 * lock/unlock above locks Now need to arm all involved CQs.
2795 */
2796 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2797 mcq->comp(mcq);
2798 }
2799 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2800}
2801
03404e8a
MG		 2802static void delay_drop_handler(struct work_struct *work)
2803{
2804 int err;
2805 struct mlx5_ib_delay_drop *delay_drop =
2806 container_of(work, struct mlx5_ib_delay_drop,
2807 delay_drop_work);
2808
fe248c3a
MG		 2809 atomic_inc(&delay_drop->events_cnt);
2810
03404e8a
MG		 2811 mutex_lock(&delay_drop->lock);
2812 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
2813 delay_drop->timeout);
2814 if (err) {
2815 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
2816 delay_drop->timeout);
2817 delay_drop->activate = false;
2818 }
2819 mutex_unlock(&delay_drop->lock);
2820}
2821
9603b61d 2822static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 2823 enum mlx5_dev_event event, unsigned long param)
e126ba97 2824{
9603b61d 2825 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
e126ba97 2826 struct ib_event ibev;
dbaaff2a 2827 bool fatal = false;
e126ba97
EC		 2828 u8 port = 0;
2829
2830 switch (event) {
2831 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 2832 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 2833 mlx5_ib_handle_internal_error(ibdev);
dbaaff2a 2834 fatal = true;
e126ba97
EC		 2835 break;
2836
2837 case MLX5_DEV_EVENT_PORT_UP:
e126ba97 2838 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 2839 case MLX5_DEV_EVENT_PORT_INITIALIZED:
4d2f9bbb 2840 port = (u8)param;
5ec8c83e
AH		 2841
2842 /* In RoCE, port up/down events are handled in
2843 * mlx5_netdev_event().
2844 */
2845 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2846 IB_LINK_LAYER_ETHERNET)
2847 return;
2848
2849 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2850 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
e126ba97
EC		 2851 break;
2852
e126ba97
EC		 2853 case MLX5_DEV_EVENT_LID_CHANGE:
2854 ibev.event = IB_EVENT_LID_CHANGE;
4d2f9bbb 2855 port = (u8)param;
e126ba97
EC		 2856 break;
2857
2858 case MLX5_DEV_EVENT_PKEY_CHANGE:
2859 ibev.event = IB_EVENT_PKEY_CHANGE;
4d2f9bbb 2860 port = (u8)param;
7722f47e
HE		 2861
2862 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 2863 break;
2864
2865 case MLX5_DEV_EVENT_GUID_CHANGE:
2866 ibev.event = IB_EVENT_GID_CHANGE;
4d2f9bbb 2867 port = (u8)param;
e126ba97
EC		 2868 break;
2869
2870 case MLX5_DEV_EVENT_CLIENT_REREG:
2871 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4d2f9bbb 2872 port = (u8)param;
e126ba97 2873 break;
03404e8a
MG		 2874 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
2875 schedule_work(&ibdev->delay_drop.delay_drop_work);
2876 goto out;
bdc37924 2877 default:
03404e8a 2878 goto out;
e126ba97
EC		 2879 }
2880
2881 ibev.device = &ibdev->ib_dev;
2882 ibev.element.port_num = port;
2883
a0c84c32
EC		 2884 if (port < 1 || port > ibdev->num_ports) {
2885 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
03404e8a 2886 goto out;
a0c84c32
EC		 2887 }
2888
e126ba97
EC		 2889 if (ibdev->ib_active)
2890 ib_dispatch_event(&ibev);
dbaaff2a
EC		 2891
2892 if (fatal)
2893 ibdev->ib_active = false;
03404e8a
MG		 2894
2895out:
2896 return;
e126ba97
EC		 2897}
2898
c43f1112
MG		 2899static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2900{
2901 struct mlx5_hca_vport_context vport_ctx;
2902 int err;
2903 int port;
2904
2905 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2906 dev->mdev->port_caps[port - 1].has_smi = false;
2907 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
2908 MLX5_CAP_PORT_TYPE_IB) {
2909 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2910 err = mlx5_query_hca_vport_context(dev->mdev, 0,
2911 port, 0,
2912 &vport_ctx);
2913 if (err) {
2914 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2915 port, err);
2916 return err;
2917 }
2918 dev->mdev->port_caps[port - 1].has_smi =
2919 vport_ctx.has_smi;
2920 } else {
2921 dev->mdev->port_caps[port - 1].has_smi = true;
2922 }
2923 }
2924 }
2925 return 0;
2926}
2927
e126ba97
EC		 2928static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2929{
2930 int port;
2931
938fe83c 2932 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
e126ba97
EC		 2933 mlx5_query_ext_port_caps(dev, port);
2934}
2935
2936static int get_port_caps(struct mlx5_ib_dev *dev)
2937{
2938 struct ib_device_attr *dprops = NULL;
2939 struct ib_port_attr *pprops = NULL;
f614fc15 2940 int err = -ENOMEM;
e126ba97 2941 int port;
2528e33e 2942 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 2943
2944 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2945 if (!pprops)
2946 goto out;
2947
2948 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2949 if (!dprops)
2950 goto out;
2951
c43f1112
MG		 2952 err = set_has_smi_cap(dev);
2953 if (err)
2954 goto out;
2955
2528e33e 2956 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 2957 if (err) {
2958 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2959 goto out;
2960 }
2961
938fe83c 2962 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
c4550c63 2963 memset(pprops, 0, sizeof(*pprops));
e126ba97
EC		 2964 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2965 if (err) {
938fe83c
SM		 2966 mlx5_ib_warn(dev, "query_port %d failed %d\n",
2967 port, err);
e126ba97
EC		 2968 break;
2969 }
938fe83c
SM		 2970 dev->mdev->port_caps[port - 1].pkey_table_len =
2971 dprops->max_pkeys;
2972 dev->mdev->port_caps[port - 1].gid_table_len =
2973 pprops->gid_tbl_len;
e126ba97
EC		 2974 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2975 dprops->max_pkeys, pprops->gid_tbl_len);
2976 }
2977
2978out:
2979 kfree(pprops);
2980 kfree(dprops);
2981
2982 return err;
2983}
2984
2985static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2986{
2987 int err;
2988
2989 err = mlx5_mr_cache_cleanup(dev);
2990 if (err)
2991 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2992
2993 mlx5_ib_destroy_qp(dev->umrc.qp);
add08d76 2994 ib_free_cq(dev->umrc.cq);
e126ba97
EC		 2995 ib_dealloc_pd(dev->umrc.pd);
2996}
2997
2998enum {
2999 MAX_UMR_WR = 128,
3000};
3001
3002static int create_umr_res(struct mlx5_ib_dev *dev)
3003{
3004 struct ib_qp_init_attr *init_attr = NULL;
3005 struct ib_qp_attr *attr = NULL;
3006 struct ib_pd *pd;
3007 struct ib_cq *cq;
3008 struct ib_qp *qp;
e126ba97
EC		 3009 int ret;
3010
3011 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
3012 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
3013 if (!attr || !init_attr) {
3014 ret = -ENOMEM;
3015 goto error_0;
3016 }
3017
ed082d36 3018 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 3019 if (IS_ERR(pd)) {
3020 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
3021 ret = PTR_ERR(pd);
3022 goto error_0;
3023 }
3024
add08d76 3025 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 3026 if (IS_ERR(cq)) {
3027 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
3028 ret = PTR_ERR(cq);
3029 goto error_2;
3030 }
e126ba97
EC		 3031
3032 init_attr->send_cq = cq;
3033 init_attr->recv_cq = cq;
3034 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
3035 init_attr->cap.max_send_wr = MAX_UMR_WR;
3036 init_attr->cap.max_send_sge = 1;
3037 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
3038 init_attr->port_num = 1;
3039 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
3040 if (IS_ERR(qp)) {
3041 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
3042 ret = PTR_ERR(qp);
3043 goto error_3;
3044 }
3045 qp->device = &dev->ib_dev;
3046 qp->real_qp = qp;
3047 qp->uobject = NULL;
3048 qp->qp_type = MLX5_IB_QPT_REG_UMR;
3049
3050 attr->qp_state = IB_QPS_INIT;
3051 attr->port_num = 1;
3052 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
3053 IB_QP_PORT, NULL);
3054 if (ret) {
3055 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
3056 goto error_4;
3057 }
3058
3059 memset(attr, 0, sizeof(*attr));
3060 attr->qp_state = IB_QPS_RTR;
3061 attr->path_mtu = IB_MTU_256;
3062
3063 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3064 if (ret) {
3065 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
3066 goto error_4;
3067 }
3068
3069 memset(attr, 0, sizeof(*attr));
3070 attr->qp_state = IB_QPS_RTS;
3071 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3072 if (ret) {
3073 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
3074 goto error_4;
3075 }
3076
3077 dev->umrc.qp = qp;
3078 dev->umrc.cq = cq;
e126ba97
EC		 3079 dev->umrc.pd = pd;
3080
3081 sema_init(&dev->umrc.sem, MAX_UMR_WR);
3082 ret = mlx5_mr_cache_init(dev);
3083 if (ret) {
3084 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
3085 goto error_4;
3086 }
3087
3088 kfree(attr);
3089 kfree(init_attr);
3090
3091 return 0;
3092
3093error_4:
3094 mlx5_ib_destroy_qp(qp);
3095
3096error_3:
add08d76 3097 ib_free_cq(cq);
e126ba97
EC		 3098
3099error_2:
e126ba97
EC		 3100 ib_dealloc_pd(pd);
3101
3102error_0:
3103 kfree(attr);
3104 kfree(init_attr);
3105 return ret;
3106}
3107
6e8484c5
MG		 3108static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
3109{
3110 switch (umr_fence_cap) {
3111 case MLX5_CAP_UMR_FENCE_NONE:
3112 return MLX5_FENCE_MODE_NONE;
3113 case MLX5_CAP_UMR_FENCE_SMALL:
3114 return MLX5_FENCE_MODE_INITIATOR_SMALL;
3115 default:
3116 return MLX5_FENCE_MODE_STRONG_ORDERING;
3117 }
3118}
3119
e126ba97
EC		 3120static int create_dev_resources(struct mlx5_ib_resources *devr)
3121{
3122 struct ib_srq_init_attr attr;
3123 struct mlx5_ib_dev *dev;
bcf4c1ea 3124 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 3125 int port;
e126ba97
EC		 3126 int ret = 0;
3127
3128 dev = container_of(devr, struct mlx5_ib_dev, devr);
3129
d16e91da
HE		 3130 mutex_init(&devr->mutex);
3131
e126ba97
EC		 3132 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
3133 if (IS_ERR(devr->p0)) {
3134 ret = PTR_ERR(devr->p0);
3135 goto error0;
3136 }
3137 devr->p0->device = &dev->ib_dev;
3138 devr->p0->uobject = NULL;
3139 atomic_set(&devr->p0->usecnt, 0);
3140
bcf4c1ea 3141 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 3142 if (IS_ERR(devr->c0)) {
3143 ret = PTR_ERR(devr->c0);
3144 goto error1;
3145 }
3146 devr->c0->device = &dev->ib_dev;
3147 devr->c0->uobject = NULL;
3148 devr->c0->comp_handler = NULL;
3149 devr->c0->event_handler = NULL;
3150 devr->c0->cq_context = NULL;
3151 atomic_set(&devr->c0->usecnt, 0);
3152
3153 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3154 if (IS_ERR(devr->x0)) {
3155 ret = PTR_ERR(devr->x0);
3156 goto error2;
3157 }
3158 devr->x0->device = &dev->ib_dev;
3159 devr->x0->inode = NULL;
3160 atomic_set(&devr->x0->usecnt, 0);
3161 mutex_init(&devr->x0->tgt_qp_mutex);
3162 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
3163
3164 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3165 if (IS_ERR(devr->x1)) {
3166 ret = PTR_ERR(devr->x1);
3167 goto error3;
3168 }
3169 devr->x1->device = &dev->ib_dev;
3170 devr->x1->inode = NULL;
3171 atomic_set(&devr->x1->usecnt, 0);
3172 mutex_init(&devr->x1->tgt_qp_mutex);
3173 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
3174
3175 memset(&attr, 0, sizeof(attr));
3176 attr.attr.max_sge = 1;
3177 attr.attr.max_wr = 1;
3178 attr.srq_type = IB_SRQT_XRC;
3179 attr.ext.xrc.cq = devr->c0;
3180 attr.ext.xrc.xrcd = devr->x0;
3181
3182 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3183 if (IS_ERR(devr->s0)) {
3184 ret = PTR_ERR(devr->s0);
3185 goto error4;
3186 }
3187 devr->s0->device = &dev->ib_dev;
3188 devr->s0->pd = devr->p0;
3189 devr->s0->uobject = NULL;
3190 devr->s0->event_handler = NULL;
3191 devr->s0->srq_context = NULL;
3192 devr->s0->srq_type = IB_SRQT_XRC;
3193 devr->s0->ext.xrc.xrcd = devr->x0;
3194 devr->s0->ext.xrc.cq = devr->c0;
3195 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
3196 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
3197 atomic_inc(&devr->p0->usecnt);
3198 atomic_set(&devr->s0->usecnt, 0);
3199
4aa17b28
HA		 3200 memset(&attr, 0, sizeof(attr));
3201 attr.attr.max_sge = 1;
3202 attr.attr.max_wr = 1;
3203 attr.srq_type = IB_SRQT_BASIC;
3204 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3205 if (IS_ERR(devr->s1)) {
3206 ret = PTR_ERR(devr->s1);
3207 goto error5;
3208 }
3209 devr->s1->device = &dev->ib_dev;
3210 devr->s1->pd = devr->p0;
3211 devr->s1->uobject = NULL;
3212 devr->s1->event_handler = NULL;
3213 devr->s1->srq_context = NULL;
3214 devr->s1->srq_type = IB_SRQT_BASIC;
3215 devr->s1->ext.xrc.cq = devr->c0;
3216 atomic_inc(&devr->p0->usecnt);
3217 atomic_set(&devr->s0->usecnt, 0);
3218
7722f47e
HE		 3219 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
3220 INIT_WORK(&devr->ports[port].pkey_change_work,
3221 pkey_change_handler);
3222 devr->ports[port].devr = devr;
3223 }
3224
e126ba97
EC		 3225 return 0;
3226
4aa17b28
HA		 3227error5:
3228 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 3229error4:
3230 mlx5_ib_dealloc_xrcd(devr->x1);
3231error3:
3232 mlx5_ib_dealloc_xrcd(devr->x0);
3233error2:
3234 mlx5_ib_destroy_cq(devr->c0);
3235error1:
3236 mlx5_ib_dealloc_pd(devr->p0);
3237error0:
3238 return ret;
3239}
3240
3241static void destroy_dev_resources(struct mlx5_ib_resources *devr)
3242{
7722f47e
HE		 3243 struct mlx5_ib_dev *dev =
3244 container_of(devr, struct mlx5_ib_dev, devr);
3245 int port;
3246
4aa17b28 3247 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 3248 mlx5_ib_destroy_srq(devr->s0);
3249 mlx5_ib_dealloc_xrcd(devr->x0);
3250 mlx5_ib_dealloc_xrcd(devr->x1);
3251 mlx5_ib_destroy_cq(devr->c0);
3252 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 3253
3254 /* Make sure no change P_Key work items are still executing */
3255 for (port = 0; port < dev->num_ports; ++port)
3256 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 3257}
3258
e53505a8
AS		 3259static u32 get_core_cap_flags(struct ib_device *ibdev)
3260{
3261 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3262 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3263 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3264 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3265 u32 ret = 0;
3266
3267 if (ll == IB_LINK_LAYER_INFINIBAND)
3268 return RDMA_CORE_PORT_IBA_IB;
3269
72cd5717
OG		 3270 ret = RDMA_CORE_PORT_RAW_PACKET;
3271
e53505a8 3272 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 3273 return ret;
e53505a8
AS		 3274
3275 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 3276 return ret;
e53505a8
AS		 3277
3278 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3279 ret |= RDMA_CORE_PORT_IBA_ROCE;
3280
3281 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3282 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3283
3284 return ret;
3285}
3286
7738613e
IW		 3287static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3288 struct ib_port_immutable *immutable)
3289{
3290 struct ib_port_attr attr;
ca5b91d6
OG		 3291 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3292 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
7738613e
IW		 3293 int err;
3294
c4550c63
OG		 3295 immutable->core_cap_flags = get_core_cap_flags(ibdev);
3296
3297 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 3298 if (err)
3299 return err;
3300
3301 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3302 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 3303 immutable->core_cap_flags = get_core_cap_flags(ibdev);
ca5b91d6
OG		 3304 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3305 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 3306
3307 return 0;
3308}
3309
9abb0d1b 3310static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 3311{
3312 struct mlx5_ib_dev *dev =
3313 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 3314 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
3315 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
3316 fw_rev_sub(dev->mdev));
c7342823
IW		 3317}
3318
45f95acd 3319static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 3320{
3321 struct mlx5_core_dev *mdev = dev->mdev;
3322 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3323 MLX5_FLOW_NAMESPACE_LAG);
3324 struct mlx5_flow_table *ft;
3325 int err;
3326
3327 if (!ns || !mlx5_lag_is_active(mdev))
3328 return 0;
3329
3330 err = mlx5_cmd_create_vport_lag(mdev);
3331 if (err)
3332 return err;
3333
3334 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3335 if (IS_ERR(ft)) {
3336 err = PTR_ERR(ft);
3337 goto err_destroy_vport_lag;
3338 }
3339
3340 dev->flow_db.lag_demux_ft = ft;
3341 return 0;
3342
3343err_destroy_vport_lag:
3344 mlx5_cmd_destroy_vport_lag(mdev);
3345 return err;
3346}
3347
45f95acd 3348static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 3349{
3350 struct mlx5_core_dev *mdev = dev->mdev;
3351
3352 if (dev->flow_db.lag_demux_ft) {
3353 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
3354 dev->flow_db.lag_demux_ft = NULL;
3355
3356 mlx5_cmd_destroy_vport_lag(mdev);
3357 }
3358}
3359
d012f5d6
OG		 3360static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev)
3361{
3362 int err;
3363
3364 dev->roce.nb.notifier_call = mlx5_netdev_event;
3365 err = register_netdevice_notifier(&dev->roce.nb);
3366 if (err) {
3367 dev->roce.nb.notifier_call = NULL;
3368 return err;
3369 }
3370
3371 return 0;
3372}
3373
3374static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev)
5ec8c83e
AH		 3375{
3376 if (dev->roce.nb.notifier_call) {
3377 unregister_netdevice_notifier(&dev->roce.nb);
3378 dev->roce.nb.notifier_call = NULL;
3379 }
3380}
3381
45f95acd 3382static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 3383{
e53505a8
AS		 3384 int err;
3385
d012f5d6
OG		 3386 err = mlx5_add_netdev_notifier(dev);
3387 if (err)
e53505a8
AS		 3388 return err;
3389
ca5b91d6
OG		 3390 if (MLX5_CAP_GEN(dev->mdev, roce)) {
3391 err = mlx5_nic_vport_enable_roce(dev->mdev);
3392 if (err)
3393 goto err_unregister_netdevice_notifier;
3394 }
e53505a8 3395
45f95acd 3396 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 3397 if (err)
3398 goto err_disable_roce;
3399
e53505a8
AS		 3400 return 0;
3401
9ef9c640 3402err_disable_roce:
ca5b91d6
OG		 3403 if (MLX5_CAP_GEN(dev->mdev, roce))
3404 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 3405
e53505a8 3406err_unregister_netdevice_notifier:
d012f5d6 3407 mlx5_remove_netdev_notifier(dev);
e53505a8 3408 return err;
fc24fc5e
AS		 3409}
3410
45f95acd 3411static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 3412{
45f95acd 3413 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 3414 if (MLX5_CAP_GEN(dev->mdev, roce))
3415 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 3416}
3417
e1f24a79 3418struct mlx5_ib_counter {
7c16f477
KH		 3419 const char *name;
3420 size_t offset;
3421};
3422
3423#define INIT_Q_COUNTER(_name) \
3424 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3425
e1f24a79 3426static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 3427 INIT_Q_COUNTER(rx_write_requests),
3428 INIT_Q_COUNTER(rx_read_requests),
3429 INIT_Q_COUNTER(rx_atomic_requests),
3430 INIT_Q_COUNTER(out_of_buffer),
3431};
3432
e1f24a79 3433static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 3434 INIT_Q_COUNTER(out_of_sequence),
3435};
3436
e1f24a79 3437static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 3438 INIT_Q_COUNTER(duplicate_request),
3439 INIT_Q_COUNTER(rnr_nak_retry_err),
3440 INIT_Q_COUNTER(packet_seq_err),
3441 INIT_Q_COUNTER(implied_nak_seq_err),
3442 INIT_Q_COUNTER(local_ack_timeout_err),
3443};
3444
e1f24a79
PP		 3445#define INIT_CONG_COUNTER(_name) \
3446 { .name = #_name, .offset = \
3447 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
3448
3449static const struct mlx5_ib_counter cong_cnts[] = {
3450 INIT_CONG_COUNTER(rp_cnp_ignored),
3451 INIT_CONG_COUNTER(rp_cnp_handled),
3452 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
3453 INIT_CONG_COUNTER(np_cnp_sent),
3454};
3455
58dcb60a
PP		 3456static const struct mlx5_ib_counter extended_err_cnts[] = {
3457 INIT_Q_COUNTER(resp_local_length_error),
3458 INIT_Q_COUNTER(resp_cqe_error),
3459 INIT_Q_COUNTER(req_cqe_error),
3460 INIT_Q_COUNTER(req_remote_invalid_request),
3461 INIT_Q_COUNTER(req_remote_access_errors),
3462 INIT_Q_COUNTER(resp_remote_access_errors),
3463 INIT_Q_COUNTER(resp_cqe_flush_error),
3464 INIT_Q_COUNTER(req_cqe_flush_error),
3465};
3466
e1f24a79 3467static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a
MB		 3468{
3469 unsigned int i;
3470
7c16f477 3471 for (i = 0; i < dev->num_ports; i++) {
0837e86a 3472 mlx5_core_dealloc_q_counter(dev->mdev,
e1f24a79
PP		 3473 dev->port[i].cnts.set_id);
3474 kfree(dev->port[i].cnts.names);
3475 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 3476 }
3477}
3478
e1f24a79
PP		 3479static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
3480 struct mlx5_ib_counters *cnts)
7c16f477
KH		 3481{
3482 u32 num_counters;
3483
3484 num_counters = ARRAY_SIZE(basic_q_cnts);
3485
3486 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
3487 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
3488
3489 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
3490 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 3491
3492 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
3493 num_counters += ARRAY_SIZE(extended_err_cnts);
3494
e1f24a79 3495 cnts->num_q_counters = num_counters;
7c16f477 3496
e1f24a79
PP		 3497 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3498 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
3499 num_counters += ARRAY_SIZE(cong_cnts);
3500 }
3501
3502 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
3503 if (!cnts->names)
7c16f477
KH		 3504 return -ENOMEM;
3505
e1f24a79
PP		 3506 cnts->offsets = kcalloc(num_counters,
3507 sizeof(cnts->offsets), GFP_KERNEL);
3508 if (!cnts->offsets)
7c16f477
KH		 3509 goto err_names;
3510
7c16f477
KH		 3511 return 0;
3512
3513err_names:
e1f24a79 3514 kfree(cnts->names);
7c16f477
KH		 3515 return -ENOMEM;
3516}
3517
e1f24a79
PP		 3518static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
3519 const char **names,
3520 size_t *offsets)
7c16f477
KH		 3521{
3522 int i;
3523 int j = 0;
3524
3525 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
3526 names[j] = basic_q_cnts[i].name;
3527 offsets[j] = basic_q_cnts[i].offset;
3528 }
3529
3530 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
3531 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
3532 names[j] = out_of_seq_q_cnts[i].name;
3533 offsets[j] = out_of_seq_q_cnts[i].offset;
3534 }
3535 }
3536
3537 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3538 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
3539 names[j] = retrans_q_cnts[i].name;
3540 offsets[j] = retrans_q_cnts[i].offset;
3541 }
3542 }
e1f24a79 3543
58dcb60a
PP		 3544 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
3545 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
3546 names[j] = extended_err_cnts[i].name;
3547 offsets[j] = extended_err_cnts[i].offset;
3548 }
3549 }
3550
e1f24a79
PP		 3551 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3552 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
3553 names[j] = cong_cnts[i].name;
3554 offsets[j] = cong_cnts[i].offset;
3555 }
3556 }
0837e86a
MB		 3557}
3558
e1f24a79 3559static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a
MB		 3560{
3561 int i;
3562 int ret;
3563
3564 for (i = 0; i < dev->num_ports; i++) {
7c16f477
KH		 3565 struct mlx5_ib_port *port = &dev->port[i];
3566
0837e86a 3567 ret = mlx5_core_alloc_q_counter(dev->mdev,
e1f24a79 3568 &port->cnts.set_id);
0837e86a
MB		 3569 if (ret) {
3570 mlx5_ib_warn(dev,
3571 "couldn't allocate queue counter for port %d, err %d\n",
3572 i + 1, ret);
3573 goto dealloc_counters;
3574 }
7c16f477 3575
e1f24a79 3576 ret = __mlx5_ib_alloc_counters(dev, &port->cnts);
7c16f477
KH		 3577 if (ret)
3578 goto dealloc_counters;
3579
e1f24a79
PP		 3580 mlx5_ib_fill_counters(dev, port->cnts.names,
3581 port->cnts.offsets);
0837e86a
MB		 3582 }
3583
3584 return 0;
3585
3586dealloc_counters:
3587 while (--i >= 0)
3588 mlx5_core_dealloc_q_counter(dev->mdev,
e1f24a79 3589 dev->port[i].cnts.set_id);
0837e86a
MB		 3590
3591 return ret;
3592}
3593
0ad17a8f
MB		 3594static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
3595 u8 port_num)
3596{
7c16f477
KH		 3597 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3598 struct mlx5_ib_port *port = &dev->port[port_num - 1];
0ad17a8f
MB		 3599
3600 /* We support only per port stats */
3601 if (port_num == 0)
3602 return NULL;
3603
e1f24a79
PP		 3604 return rdma_alloc_hw_stats_struct(port->cnts.names,
3605 port->cnts.num_q_counters +
3606 port->cnts.num_cong_counters,
0ad17a8f
MB		 3607 RDMA_HW_STATS_DEFAULT_LIFESPAN);
3608}
3609
e1f24a79
PP		 3610static int mlx5_ib_query_q_counters(struct mlx5_ib_dev *dev,
3611 struct mlx5_ib_port *port,
3612 struct rdma_hw_stats *stats)
0ad17a8f 3613{
0ad17a8f
MB		 3614 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3615 void *out;
3616 __be32 val;
e1f24a79 3617 int ret, i;
0ad17a8f 3618
1b9a07ee 3619 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 3620 if (!out)
3621 return -ENOMEM;
3622
3623 ret = mlx5_core_query_q_counter(dev->mdev,
e1f24a79 3624 port->cnts.set_id, 0,
0ad17a8f
MB		 3625 out, outlen);
3626 if (ret)
3627 goto free;
3628
e1f24a79
PP		 3629 for (i = 0; i < port->cnts.num_q_counters; i++) {
3630 val = *(__be32 *)(out + port->cnts.offsets[i]);
0ad17a8f
MB		 3631 stats->value[i] = (u64)be32_to_cpu(val);
3632 }
7c16f477 3633
0ad17a8f
MB		 3634free:
3635 kvfree(out);
e1f24a79
PP		 3636 return ret;
3637}
3638
3639static int mlx5_ib_query_cong_counters(struct mlx5_ib_dev *dev,
3640 struct mlx5_ib_port *port,
3641 struct rdma_hw_stats *stats)
3642{
3643 int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out);
3644 void *out;
3645 int ret, i;
3646 int offset = port->cnts.num_q_counters;
3647
1b9a07ee 3648 out = kvzalloc(outlen, GFP_KERNEL);
e1f24a79
PP		 3649 if (!out)
3650 return -ENOMEM;
3651
3652 ret = mlx5_cmd_query_cong_counter(dev->mdev, false, out, outlen);
3653 if (ret)
3654 goto free;
3655
3656 for (i = 0; i < port->cnts.num_cong_counters; i++) {
3657 stats->value[i + offset] =
3658 be64_to_cpup((__be64 *)(out +
3659 port->cnts.offsets[i + offset]));
3660 }
3661
3662free:
3663 kvfree(out);
3664 return ret;
3665}
3666
3667static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
3668 struct rdma_hw_stats *stats,
3669 u8 port_num, int index)
3670{
3671 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3672 struct mlx5_ib_port *port = &dev->port[port_num - 1];
3673 int ret, num_counters;
3674
3675 if (!stats)
3676 return -EINVAL;
3677
3678 ret = mlx5_ib_query_q_counters(dev, port, stats);
3679 if (ret)
3680 return ret;
3681 num_counters = port->cnts.num_q_counters;
3682
3683 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3684 ret = mlx5_ib_query_cong_counters(dev, port, stats);
3685 if (ret)
3686 return ret;
3687 num_counters += port->cnts.num_cong_counters;
3688 }
3689
3690 return num_counters;
0ad17a8f
MB		 3691}
3692
8e959601
NV		 3693static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
3694{
3695 return mlx5_rdma_netdev_free(netdev);
3696}
3697
693dfd5a
ES		 3698static struct net_device*
3699mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
3700 u8 port_num,
3701 enum rdma_netdev_t type,
3702 const char *name,
3703 unsigned char name_assign_type,
3704 void (*setup)(struct net_device *))
3705{
8e959601
NV		 3706 struct net_device *netdev;
3707 struct rdma_netdev *rn;
3708
693dfd5a
ES		 3709 if (type != RDMA_NETDEV_IPOIB)
3710 return ERR_PTR(-EOPNOTSUPP);
3711
8e959601
NV		 3712 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
3713 name, setup);
3714 if (likely(!IS_ERR_OR_NULL(netdev))) {
3715 rn = netdev_priv(netdev);
3716 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
3717 }
3718 return netdev;
693dfd5a
ES		 3719}
3720
fe248c3a
MG		 3721static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
3722{
3723 if (!dev->delay_drop.dbg)
3724 return;
3725 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
3726 kfree(dev->delay_drop.dbg);
3727 dev->delay_drop.dbg = NULL;
3728}
3729
03404e8a
MG		 3730static void cancel_delay_drop(struct mlx5_ib_dev *dev)
3731{
3732 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
3733 return;
3734
3735 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 3736 delay_drop_debugfs_cleanup(dev);
3737}
3738
3739static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
3740 size_t count, loff_t *pos)
3741{
3742 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3743 char lbuf[20];
3744 int len;
3745
3746 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
3747 return simple_read_from_buffer(buf, count, pos, lbuf, len);
3748}
3749
3750static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
3751 size_t count, loff_t *pos)
3752{
3753 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3754 u32 timeout;
3755 u32 var;
3756
3757 if (kstrtouint_from_user(buf, count, 0, &var))
3758 return -EFAULT;
3759
3760 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
3761 1000);
3762 if (timeout != var)
3763 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
3764 timeout);
3765
3766 delay_drop->timeout = timeout;
3767
3768 return count;
3769}
3770
3771static const struct file_operations fops_delay_drop_timeout = {
3772 .owner = THIS_MODULE,
3773 .open = simple_open,
3774 .write = delay_drop_timeout_write,
3775 .read = delay_drop_timeout_read,
3776};
3777
3778static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
3779{
3780 struct mlx5_ib_dbg_delay_drop *dbg;
3781
3782 if (!mlx5_debugfs_root)
3783 return 0;
3784
3785 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
3786 if (!dbg)
3787 return -ENOMEM;
3788
3789 dbg->dir_debugfs =
3790 debugfs_create_dir("delay_drop",
3791 dev->mdev->priv.dbg_root);
3792 if (!dbg->dir_debugfs)
3793 return -ENOMEM;
3794
3795 dbg->events_cnt_debugfs =
3796 debugfs_create_atomic_t("num_timeout_events", 0400,
3797 dbg->dir_debugfs,
3798 &dev->delay_drop.events_cnt);
3799 if (!dbg->events_cnt_debugfs)
3800 goto out_debugfs;
3801
3802 dbg->rqs_cnt_debugfs =
3803 debugfs_create_atomic_t("num_rqs", 0400,
3804 dbg->dir_debugfs,
3805 &dev->delay_drop.rqs_cnt);
3806 if (!dbg->rqs_cnt_debugfs)
3807 goto out_debugfs;
3808
3809 dbg->timeout_debugfs =
3810 debugfs_create_file("timeout", 0600,
3811 dbg->dir_debugfs,
3812 &dev->delay_drop,
3813 &fops_delay_drop_timeout);
3814 if (!dbg->timeout_debugfs)
3815 goto out_debugfs;
3816
4a5fd5d2
MG		 3817 dev->delay_drop.dbg = dbg;
3818
fe248c3a
MG		 3819 return 0;
3820
3821out_debugfs:
3822 delay_drop_debugfs_cleanup(dev);
3823 return -ENOMEM;
03404e8a
MG		 3824}
3825
3826static void init_delay_drop(struct mlx5_ib_dev *dev)
3827{
3828 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
3829 return;
3830
3831 mutex_init(&dev->delay_drop.lock);
3832 dev->delay_drop.dev = dev;
3833 dev->delay_drop.activate = false;
3834 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
3835 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 3836 atomic_set(&dev->delay_drop.rqs_cnt, 0);
3837 atomic_set(&dev->delay_drop.events_cnt, 0);
3838
3839 if (delay_drop_debugfs_init(dev))
3840 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
03404e8a
MG		 3841}
3842
84305d71
LR		 3843static const struct cpumask *
3844mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
40b24403
SG		 3845{
3846 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3847
3848 return mlx5_get_vector_affinity(dev->mdev, comp_vector);
3849}
3850
9603b61d 3851static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
e126ba97 3852{
e126ba97 3853 struct mlx5_ib_dev *dev;
ebd61f68
AS		 3854 enum rdma_link_layer ll;
3855 int port_type_cap;
4babcf97 3856 const char *name;
e126ba97
EC		 3857 int err;
3858 int i;
3859
ebd61f68
AS		 3860 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3861 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3862
e126ba97
EC		 3863 printk_once(KERN_INFO "%s", mlx5_version);
3864
3865 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
3866 if (!dev)
9603b61d 3867 return NULL;
e126ba97 3868
9603b61d 3869 dev->mdev = mdev;
e126ba97 3870
0837e86a
MB		 3871 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
3872 GFP_KERNEL);
3873 if (!dev->port)
3874 goto err_dealloc;
3875
fc24fc5e 3876 rwlock_init(&dev->roce.netdev_lock);
e126ba97
EC		 3877 err = get_port_caps(dev);
3878 if (err)
0837e86a 3879 goto err_free_port;
e126ba97 3880
1b5daf11
MD		 3881 if (mlx5_use_mad_ifc(dev))
3882 get_ext_port_caps(dev);
e126ba97 3883
4babcf97
AH		 3884 if (!mlx5_lag_is_active(mdev))
3885 name = "mlx5_%d";
3886 else
3887 name = "mlx5_bond_%d";
3888
3889 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
e126ba97
EC		 3890 dev->ib_dev.owner = THIS_MODULE;
3891 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 3892 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
938fe83c 3893 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
e126ba97 3894 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 3895 dev->ib_dev.num_comp_vectors =
3896 dev->mdev->priv.eq_table.num_comp_vectors;
9b0c289e 3897 dev->ib_dev.dev.parent = &mdev->pdev->dev;
e126ba97
EC		 3898
3899 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
3900 dev->ib_dev.uverbs_cmd_mask =
3901 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
3902 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
3903 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
3904 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
3905 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 3906 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
3907 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 3908 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 3909 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 3910 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
3911 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
3912 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
3913 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
3914 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
3915 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
3916 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
3917 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
3918 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
3919 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
3920 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
3921 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
3922 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
3923 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
3924 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
3925 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
3926 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 3927 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 3928 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
3929 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349
BW		 3930 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
3931 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP);
e126ba97
EC		 3932
3933 dev->ib_dev.query_device = mlx5_ib_query_device;
3934 dev->ib_dev.query_port = mlx5_ib_query_port;
ebd61f68 3935 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
fc24fc5e
AS		 3936 if (ll == IB_LINK_LAYER_ETHERNET)
3937 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
e126ba97 3938 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 3939 dev->ib_dev.add_gid = mlx5_ib_add_gid;
3940 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 3941 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
3942 dev->ib_dev.modify_device = mlx5_ib_modify_device;
3943 dev->ib_dev.modify_port = mlx5_ib_modify_port;
3944 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
3945 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
3946 dev->ib_dev.mmap = mlx5_ib_mmap;
3947 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
3948 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
3949 dev->ib_dev.create_ah = mlx5_ib_create_ah;
3950 dev->ib_dev.query_ah = mlx5_ib_query_ah;
3951 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
3952 dev->ib_dev.create_srq = mlx5_ib_create_srq;
3953 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
3954 dev->ib_dev.query_srq = mlx5_ib_query_srq;
3955 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
3956 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
3957 dev->ib_dev.create_qp = mlx5_ib_create_qp;
3958 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
3959 dev->ib_dev.query_qp = mlx5_ib_query_qp;
3960 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
3961 dev->ib_dev.post_send = mlx5_ib_post_send;
3962 dev->ib_dev.post_recv = mlx5_ib_post_recv;
3963 dev->ib_dev.create_cq = mlx5_ib_create_cq;
3964 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
3965 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
3966 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
3967 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
3968 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
3969 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
3970 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 3971 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 3972 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
3973 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
3974 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
3975 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 3976 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 3977 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 3978 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
7738613e 3979 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
c7342823 3980 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
40b24403 3981 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
8e959601 3982 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
022d038a 3983 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
8e959601 3984
eff901d3
EC		 3985 if (mlx5_core_is_pf(mdev)) {
3986 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
3987 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
3988 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
3989 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
3990 }
e126ba97 3991
7c2344c3
MG		 3992 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3993
938fe83c 3994 mlx5_ib_internal_fill_odp_caps(dev);
8cdd312c 3995
6e8484c5
MG		 3996 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
3997
d2370e0a
MB		 3998 if (MLX5_CAP_GEN(mdev, imaicl)) {
3999 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
4000 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
4001 dev->ib_dev.uverbs_cmd_mask |=
4002 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
4003 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
4004 }
4005
7c16f477 4006 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
0ad17a8f
MB		 4007 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
4008 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
4009 }
4010
938fe83c 4011 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 4012 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
4013 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
4014 dev->ib_dev.uverbs_cmd_mask |=
4015 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
4016 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
4017 }
4018
81e30880
YH		 4019 dev->ib_dev.create_flow = mlx5_ib_create_flow;
4020 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
4021 dev->ib_dev.uverbs_ex_cmd_mask |=
4022 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
4023 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
4024
048ccca8 4025 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
038d2ef8 4026 IB_LINK_LAYER_ETHERNET) {
79b20a6c
YH		 4027 dev->ib_dev.create_wq = mlx5_ib_create_wq;
4028 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
4029 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
c5f90929
YH		 4030 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
4031 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
038d2ef8 4032 dev->ib_dev.uverbs_ex_cmd_mask |=
79b20a6c
YH		 4033 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
4034 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
c5f90929
YH		 4035 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
4036 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
4037 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
038d2ef8 4038 }
e126ba97
EC		 4039 err = init_node_data(dev);
4040 if (err)
90be7c8a 4041 goto err_free_port;
e126ba97 4042
038d2ef8 4043 mutex_init(&dev->flow_db.lock);
e126ba97 4044 mutex_init(&dev->cap_mask_mutex);
89ea94a7
MG		 4045 INIT_LIST_HEAD(&dev->qp_list);
4046 spin_lock_init(&dev->reset_flow_resource_lock);
e126ba97 4047
fc24fc5e 4048 if (ll == IB_LINK_LAYER_ETHERNET) {
45f95acd 4049 err = mlx5_enable_eth(dev);
fc24fc5e 4050 if (err)
90be7c8a 4051 goto err_free_port;
fd65f1b8 4052 dev->roce.last_port_state = IB_PORT_DOWN;
fc24fc5e
AS		 4053 }
4054
e126ba97
EC		 4055 err = create_dev_resources(&dev->devr);
4056 if (err)
45f95acd 4057 goto err_disable_eth;
e126ba97 4058
6aec21f6 4059 err = mlx5_ib_odp_init_one(dev);
281d1a92 4060 if (err)
e126ba97
EC		 4061 goto err_rsrc;
4062
45bded2c 4063 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
e1f24a79 4064 err = mlx5_ib_alloc_counters(dev);
45bded2c
KH		 4065 if (err)
4066 goto err_odp;
4067 }
6aec21f6 4068
4a2da0b8
PP		 4069 err = mlx5_ib_init_cong_debugfs(dev);
4070 if (err)
4071 goto err_cnt;
4072
5fe9dec0
EC		 4073 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
4074 if (!dev->mdev->priv.uar)
4a2da0b8 4075 goto err_cong;
5fe9dec0
EC		 4076
4077 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4078 if (err)
4079 goto err_uar_page;
4080
4081 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4082 if (err)
4083 goto err_bfreg;
4084
0837e86a
MB		 4085 err = ib_register_device(&dev->ib_dev, NULL);
4086 if (err)
5fe9dec0 4087 goto err_fp_bfreg;
0837e86a 4088
e126ba97
EC		 4089 err = create_umr_res(dev);
4090 if (err)
4091 goto err_dev;
4092
03404e8a
MG		 4093 init_delay_drop(dev);
4094
e126ba97 4095 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 4096 err = device_create_file(&dev->ib_dev.dev,
4097 mlx5_class_attributes[i]);
4098 if (err)
03404e8a 4099 goto err_delay_drop;
e126ba97
EC		 4100 }
4101
c85023e1
HN		 4102 if ((MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
4103 MLX5_CAP_GEN(mdev, disable_local_lb))
4104 mutex_init(&dev->lb_mutex);
4105
e126ba97
EC		 4106 dev->ib_active = true;
4107
9603b61d 4108 return dev;
e126ba97 4109
03404e8a
MG		 4110err_delay_drop:
4111 cancel_delay_drop(dev);
e126ba97
EC		 4112 destroy_umrc_res(dev);
4113
4114err_dev:
4115 ib_unregister_device(&dev->ib_dev);
4116
5fe9dec0
EC		 4117err_fp_bfreg:
4118 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4119
4120err_bfreg:
4121 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4122
4123err_uar_page:
4124 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4125
e1f24a79 4126err_cnt:
4a2da0b8
PP		 4127 mlx5_ib_cleanup_cong_debugfs(dev);
4128err_cong:
45bded2c 4129 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
e1f24a79 4130 mlx5_ib_dealloc_counters(dev);
0837e86a 4131
6aec21f6
HE		 4132err_odp:
4133 mlx5_ib_odp_remove_one(dev);
4134
e126ba97
EC		 4135err_rsrc:
4136 destroy_dev_resources(&dev->devr);
4137
45f95acd 4138err_disable_eth:
5ec8c83e 4139 if (ll == IB_LINK_LAYER_ETHERNET) {
45f95acd 4140 mlx5_disable_eth(dev);
d012f5d6 4141 mlx5_remove_netdev_notifier(dev);
5ec8c83e 4142 }
fc24fc5e 4143
0837e86a
MB		 4144err_free_port:
4145 kfree(dev->port);
4146
9603b61d 4147err_dealloc:
e126ba97
EC		 4148 ib_dealloc_device((struct ib_device *)dev);
4149
9603b61d 4150 return NULL;
e126ba97
EC		 4151}
4152
9603b61d 4153static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 4154{
9603b61d 4155 struct mlx5_ib_dev *dev = context;
fc24fc5e 4156 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
6aec21f6 4157
03404e8a 4158 cancel_delay_drop(dev);
d012f5d6 4159 mlx5_remove_netdev_notifier(dev);
e126ba97 4160 ib_unregister_device(&dev->ib_dev);
5fe9dec0
EC		 4161 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4162 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4163 mlx5_put_uars_page(dev->mdev, mdev->priv.uar);
4a2da0b8 4164 mlx5_ib_cleanup_cong_debugfs(dev);
45bded2c 4165 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
e1f24a79 4166 mlx5_ib_dealloc_counters(dev);
eefd56e5 4167 destroy_umrc_res(dev);
6aec21f6 4168 mlx5_ib_odp_remove_one(dev);
e126ba97 4169 destroy_dev_resources(&dev->devr);
fc24fc5e 4170 if (ll == IB_LINK_LAYER_ETHERNET)
45f95acd 4171 mlx5_disable_eth(dev);
0837e86a 4172 kfree(dev->port);
e126ba97
EC		 4173 ib_dealloc_device(&dev->ib_dev);
4174}
4175
9603b61d
JM		 4176static struct mlx5_interface mlx5_ib_interface = {
4177 .add = mlx5_ib_add,
4178 .remove = mlx5_ib_remove,
4179 .event = mlx5_ib_event,
d9aaed83
AK		 4180#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4181 .pfault = mlx5_ib_pfault,
4182#endif
64613d94 4183 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 4184};
4185
4186static int __init mlx5_ib_init(void)
4187{
6aec21f6
HE		 4188 int err;
4189
81713d37 4190 mlx5_ib_odp_init();
9603b61d 4191
6aec21f6 4192 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 4193
6aec21f6 4194 return err;
e126ba97
EC		 4195}
4196
4197static void __exit mlx5_ib_cleanup(void)
4198{
9603b61d 4199 mlx5_unregister_interface(&mlx5_ib_interface);
e126ba97
EC		 4200}
4201
4202module_init(mlx5_ib_init);
4203module_exit(mlx5_ib_cleanup);
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