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IB/mlx5: Fix represent correct netdevice in dual port RoCE
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
24da0016 41#include <linux/bitmap.h>
37aa5c36
GL		 42#if defined(CONFIG_X86)
43#include <asm/pat.h>
44#endif
e126ba97 45#include <linux/sched.h>
6e84f315 46#include <linux/sched/mm.h>
0881e7bd 47#include <linux/sched/task.h>
7c2344c3 48#include <linux/delay.h>
e126ba97 49#include <rdma/ib_user_verbs.h>
3f89a643 50#include <rdma/ib_addr.h>
2811ba51 51#include <rdma/ib_cache.h>
ada68c31 52#include <linux/mlx5/port.h>
1b5daf11 53#include <linux/mlx5/vport.h>
72c7fe90 54#include <linux/mlx5/fs.h>
7c2344c3 55#include <linux/list.h>
e126ba97
EC		 56#include <rdma/ib_smi.h>
57#include <rdma/ib_umem.h>
038d2ef8
MG		 58#include <linux/in.h>
59#include <linux/etherdevice.h>
e126ba97 60#include "mlx5_ib.h"
fc385b7a 61#include "ib_rep.h"
e1f24a79 62#include "cmd.h"
3346c487 63#include <linux/mlx5/fs_helpers.h>
c6475a0b 64#include <linux/mlx5/accel.h>
8c84660b 65#include <rdma/uverbs_std_types.h>
c6475a0b
AY		 66#include <rdma/mlx5_user_ioctl_verbs.h>
67#include <rdma/mlx5_user_ioctl_cmds.h>
8c84660b
MB		 68
69#define UVERBS_MODULE_NAME mlx5_ib
70#include <rdma/uverbs_named_ioctl.h>
e126ba97
EC		 71
72#define DRIVER_NAME "mlx5_ib"
b359911d 73#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 74
75MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
76MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
77MODULE_LICENSE("Dual BSD/GPL");
e126ba97 78
e126ba97
EC		 79static char mlx5_version[] =
80 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 81 DRIVER_VERSION "\n";
e126ba97 82
d69a24e0
DJ		 83struct mlx5_ib_event_work {
84 struct work_struct work;
85 struct mlx5_core_dev *dev;
86 void *context;
87 enum mlx5_dev_event event;
88 unsigned long param;
89};
90
da7525d2
EBE		 91enum {
92 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
93};
94
d69a24e0 95static struct workqueue_struct *mlx5_ib_event_wq;
32f69e4b
DJ		 96static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
97static LIST_HEAD(mlx5_ib_dev_list);
98/*
99 * This mutex should be held when accessing either of the above lists
100 */
101static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
102
c44ef998
IL		 103/* We can't use an array for xlt_emergency_page because dma_map_single
104 * doesn't work on kernel modules memory
105 */
106static unsigned long xlt_emergency_page;
107static struct mutex xlt_emergency_page_mutex;
108
32f69e4b
DJ		 109struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
110{
111 struct mlx5_ib_dev *dev;
112
113 mutex_lock(&mlx5_ib_multiport_mutex);
114 dev = mpi->ibdev;
115 mutex_unlock(&mlx5_ib_multiport_mutex);
116 return dev;
117}
118
1b5daf11 119static enum rdma_link_layer
ebd61f68 120mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 121{
ebd61f68 122 switch (port_type_cap) {
1b5daf11
MD		 123 case MLX5_CAP_PORT_TYPE_IB:
124 return IB_LINK_LAYER_INFINIBAND;
125 case MLX5_CAP_PORT_TYPE_ETH:
126 return IB_LINK_LAYER_ETHERNET;
127 default:
128 return IB_LINK_LAYER_UNSPECIFIED;
129 }
130}
131
ebd61f68
AS		 132static enum rdma_link_layer
133mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
134{
135 struct mlx5_ib_dev *dev = to_mdev(device);
136 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
137
138 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
139}
140
fd65f1b8
MS		 141static int get_port_state(struct ib_device *ibdev,
142 u8 port_num,
143 enum ib_port_state *state)
144{
145 struct ib_port_attr attr;
146 int ret;
147
148 memset(&attr, 0, sizeof(attr));
8e6efa3a 149 ret = ibdev->query_port(ibdev, port_num, &attr);
fd65f1b8
MS		 150 if (!ret)
151 *state = attr.state;
152 return ret;
153}
154
fc24fc5e
AS		 155static int mlx5_netdev_event(struct notifier_block *this,
156 unsigned long event, void *ptr)
157{
7fd8aefb 158 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
fc24fc5e 159 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
7fd8aefb
DJ		 160 u8 port_num = roce->native_port_num;
161 struct mlx5_core_dev *mdev;
162 struct mlx5_ib_dev *ibdev;
163
164 ibdev = roce->dev;
32f69e4b
DJ		 165 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
166 if (!mdev)
167 return NOTIFY_DONE;
fc24fc5e 168
5ec8c83e
AH		 169 switch (event) {
170 case NETDEV_REGISTER:
171 case NETDEV_UNREGISTER:
7fd8aefb 172 write_lock(&roce->netdev_lock);
bcf87f1d
MB		 173 if (ibdev->rep) {
174 struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch;
175 struct net_device *rep_ndev;
176
177 rep_ndev = mlx5_ib_get_rep_netdev(esw,
178 ibdev->rep->vport);
179 if (rep_ndev == ndev)
180 roce->netdev = (event == NETDEV_UNREGISTER) ?
7fd8aefb 181 NULL : ndev;
84a6a7a9 182 } else if (ndev->dev.parent == &mdev->pdev->dev) {
bcf87f1d
MB		 183 roce->netdev = (event == NETDEV_UNREGISTER) ?
184 NULL : ndev;
185 }
7fd8aefb 186 write_unlock(&roce->netdev_lock);
5ec8c83e 187 break;
fc24fc5e 188
fd65f1b8 189 case NETDEV_CHANGE:
5ec8c83e 190 case NETDEV_UP:
88621dfe 191 case NETDEV_DOWN: {
7fd8aefb 192 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe
AH		 193 struct net_device *upper = NULL;
194
195 if (lag_ndev) {
196 upper = netdev_master_upper_dev_get(lag_ndev);
197 dev_put(lag_ndev);
198 }
199
7fd8aefb 200 if ((upper == ndev || (!upper && ndev == roce->netdev))
88621dfe 201 && ibdev->ib_active) {
626bc02d 202 struct ib_event ibev = { };
fd65f1b8 203 enum ib_port_state port_state;
5ec8c83e 204
7fd8aefb
DJ		 205 if (get_port_state(&ibdev->ib_dev, port_num,
206 &port_state))
207 goto done;
fd65f1b8 208
7fd8aefb
DJ		 209 if (roce->last_port_state == port_state)
210 goto done;
fd65f1b8 211
7fd8aefb 212 roce->last_port_state = port_state;
5ec8c83e 213 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 214 if (port_state == IB_PORT_DOWN)
215 ibev.event = IB_EVENT_PORT_ERR;
216 else if (port_state == IB_PORT_ACTIVE)
217 ibev.event = IB_EVENT_PORT_ACTIVE;
218 else
7fd8aefb 219 goto done;
fd65f1b8 220
7fd8aefb 221 ibev.element.port_num = port_num;
5ec8c83e
AH		 222 ib_dispatch_event(&ibev);
223 }
224 break;
88621dfe 225 }
fc24fc5e 226
5ec8c83e
AH		 227 default:
228 break;
229 }
7fd8aefb 230done:
32f69e4b 231 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 232 return NOTIFY_DONE;
233}
234
235static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
236 u8 port_num)
237{
238 struct mlx5_ib_dev *ibdev = to_mdev(device);
239 struct net_device *ndev;
32f69e4b
DJ		 240 struct mlx5_core_dev *mdev;
241
242 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
243 if (!mdev)
244 return NULL;
fc24fc5e 245
32f69e4b 246 ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe 247 if (ndev)
32f69e4b 248 goto out;
88621dfe 249
fc24fc5e
AS		 250 /* Ensure ndev does not disappear before we invoke dev_hold()
251 */
7fd8aefb
DJ		 252 read_lock(&ibdev->roce[port_num - 1].netdev_lock);
253 ndev = ibdev->roce[port_num - 1].netdev;
fc24fc5e
AS		 254 if (ndev)
255 dev_hold(ndev);
7fd8aefb 256 read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
fc24fc5e 257
32f69e4b
DJ		 258out:
259 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 260 return ndev;
261}
262
32f69e4b
DJ		 263struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
264 u8 ib_port_num,
265 u8 *native_port_num)
266{
267 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
268 ib_port_num);
269 struct mlx5_core_dev *mdev = NULL;
270 struct mlx5_ib_multiport_info *mpi;
271 struct mlx5_ib_port *port;
272
210b1f78
MB		 273 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
274 ll != IB_LINK_LAYER_ETHERNET) {
275 if (native_port_num)
276 *native_port_num = ib_port_num;
277 return ibdev->mdev;
278 }
279
32f69e4b
DJ		 280 if (native_port_num)
281 *native_port_num = 1;
282
32f69e4b
DJ		 283 port = &ibdev->port[ib_port_num - 1];
284 if (!port)
285 return NULL;
286
287 spin_lock(&port->mp.mpi_lock);
288 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
289 if (mpi && !mpi->unaffiliate) {
290 mdev = mpi->mdev;
291 /* If it's the master no need to refcount, it'll exist
292 * as long as the ib_dev exists.
293 */
294 if (!mpi->is_master)
295 mpi->mdev_refcnt++;
296 }
297 spin_unlock(&port->mp.mpi_lock);
298
299 return mdev;
300}
301
302void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
303{
304 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
305 port_num);
306 struct mlx5_ib_multiport_info *mpi;
307 struct mlx5_ib_port *port;
308
309 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
310 return;
311
312 port = &ibdev->port[port_num - 1];
313
314 spin_lock(&port->mp.mpi_lock);
315 mpi = ibdev->port[port_num - 1].mp.mpi;
316 if (mpi->is_master)
317 goto out;
318
319 mpi->mdev_refcnt--;
320 if (mpi->unaffiliate)
321 complete(&mpi->unref_comp);
322out:
323 spin_unlock(&port->mp.mpi_lock);
324}
325
f1b65df5
NO		 326static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
327 u8 *active_width)
328{
329 switch (eth_proto_oper) {
330 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
331 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
332 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
333 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
334 *active_width = IB_WIDTH_1X;
335 *active_speed = IB_SPEED_SDR;
336 break;
337 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
338 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
339 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
340 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
341 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
342 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
343 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
344 *active_width = IB_WIDTH_1X;
345 *active_speed = IB_SPEED_QDR;
346 break;
347 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
348 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
349 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
350 *active_width = IB_WIDTH_1X;
351 *active_speed = IB_SPEED_EDR;
352 break;
353 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
354 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
355 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
356 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
357 *active_width = IB_WIDTH_4X;
358 *active_speed = IB_SPEED_QDR;
359 break;
360 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
361 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
362 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
363 *active_width = IB_WIDTH_1X;
364 *active_speed = IB_SPEED_HDR;
365 break;
366 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
367 *active_width = IB_WIDTH_4X;
368 *active_speed = IB_SPEED_FDR;
369 break;
370 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
371 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
372 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
373 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
374 *active_width = IB_WIDTH_4X;
375 *active_speed = IB_SPEED_EDR;
376 break;
377 default:
378 return -EINVAL;
379 }
380
381 return 0;
382}
383
095b0927
IT		 384static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
385 struct ib_port_attr *props)
3f89a643
AS		 386{
387 struct mlx5_ib_dev *dev = to_mdev(device);
da005f9f 388 struct mlx5_core_dev *mdev;
88621dfe 389 struct net_device *ndev, *upper;
3f89a643 390 enum ib_mtu ndev_ib_mtu;
b3cbd6f0 391 bool put_mdev = true;
c876a1b7 392 u16 qkey_viol_cntr;
f1b65df5 393 u32 eth_prot_oper;
b3cbd6f0 394 u8 mdev_port_num;
095b0927 395 int err;
3f89a643 396
b3cbd6f0
DJ		 397 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
398 if (!mdev) {
399 /* This means the port isn't affiliated yet. Get the
400 * info for the master port instead.
401 */
402 put_mdev = false;
403 mdev = dev->mdev;
404 mdev_port_num = 1;
405 port_num = 1;
406 }
407
f1b65df5
NO		 408 /* Possible bad flows are checked before filling out props so in case
409 * of an error it will still be zeroed out.
50f22fd8 410 */
b3cbd6f0
DJ		 411 err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper,
412 mdev_port_num);
095b0927 413 if (err)
b3cbd6f0 414 goto out;
f1b65df5 415
7672ed33
HL		 416 props->active_width = IB_WIDTH_4X;
417 props->active_speed = IB_SPEED_QDR;
418
f1b65df5
NO		 419 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
420 &props->active_width);
3f89a643
AS		 421
422 props->port_cap_flags |= IB_PORT_CM_SUP;
423 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
424
425 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
426 roce_address_table_size);
427 props->max_mtu = IB_MTU_4096;
428 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
429 props->pkey_tbl_len = 1;
430 props->state = IB_PORT_DOWN;
431 props->phys_state = 3;
432
b3cbd6f0 433 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
c876a1b7 434 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643 435
b3cbd6f0
DJ		 436 /* If this is a stub query for an unaffiliated port stop here */
437 if (!put_mdev)
438 goto out;
439
3f89a643
AS		 440 ndev = mlx5_ib_get_netdev(device, port_num);
441 if (!ndev)
b3cbd6f0 442 goto out;
3f89a643 443
88621dfe
AH		 444 if (mlx5_lag_is_active(dev->mdev)) {
445 rcu_read_lock();
446 upper = netdev_master_upper_dev_get_rcu(ndev);
447 if (upper) {
448 dev_put(ndev);
449 ndev = upper;
450 dev_hold(ndev);
451 }
452 rcu_read_unlock();
453 }
454
3f89a643
AS		 455 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
456 props->state = IB_PORT_ACTIVE;
457 props->phys_state = 5;
458 }
459
460 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
461
462 dev_put(ndev);
463
464 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
b3cbd6f0
DJ		 465out:
466 if (put_mdev)
467 mlx5_ib_put_native_port_mdev(dev, port_num);
468 return err;
3f89a643
AS		 469}
470
095b0927
IT		 471static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
472 unsigned int index, const union ib_gid *gid,
473 const struct ib_gid_attr *attr)
3cca2606 474{
095b0927
IT		 475 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
476 u8 roce_version = 0;
477 u8 roce_l3_type = 0;
478 bool vlan = false;
479 u8 mac[ETH_ALEN];
480 u16 vlan_id = 0;
481
482 if (gid) {
483 gid_type = attr->gid_type;
484 ether_addr_copy(mac, attr->ndev->dev_addr);
485
486 if (is_vlan_dev(attr->ndev)) {
487 vlan = true;
488 vlan_id = vlan_dev_vlan_id(attr->ndev);
489 }
3cca2606
AS		 490 }
491
095b0927 492 switch (gid_type) {
3cca2606 493 case IB_GID_TYPE_IB:
095b0927 494 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 495 break;
496 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 497 roce_version = MLX5_ROCE_VERSION_2;
498 if (ipv6_addr_v4mapped((void *)gid))
499 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
500 else
501 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 502 break;
503
504 default:
095b0927 505 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 506 }
507
095b0927
IT		 508 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
509 roce_l3_type, gid->raw, mac, vlan,
cfe4e37f 510 vlan_id, port_num);
3cca2606
AS		 511}
512
414448d2 513static int mlx5_ib_add_gid(const union ib_gid *gid,
3cca2606
AS		 514 const struct ib_gid_attr *attr,
515 __always_unused void **context)
516{
414448d2
PP		 517 return set_roce_addr(to_mdev(attr->device), attr->port_num,
518 attr->index, gid, attr);
3cca2606
AS		 519}
520
414448d2
PP		 521static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
522 __always_unused void **context)
3cca2606 523{
414448d2
PP		 524 return set_roce_addr(to_mdev(attr->device), attr->port_num,
525 attr->index, NULL, NULL);
3cca2606
AS		 526}
527
2811ba51
AS		 528__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
529 int index)
530{
531 struct ib_gid_attr attr;
532 union ib_gid gid;
533
534 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
535 return 0;
536
2811ba51
AS		 537 dev_put(attr.ndev);
538
539 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
540 return 0;
541
542 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
543}
544
ed88451e
MD		 545int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
546 int index, enum ib_gid_type *gid_type)
547{
548 struct ib_gid_attr attr;
549 union ib_gid gid;
550 int ret;
551
552 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
553 if (ret)
554 return ret;
555
ed88451e
MD		 556 dev_put(attr.ndev);
557
558 *gid_type = attr.gid_type;
559
560 return 0;
561}
562
1b5daf11
MD		 563static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
564{
7fae6655
NO		 565 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
566 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
567 return 0;
1b5daf11
MD		 568}
569
570enum {
571 MLX5_VPORT_ACCESS_METHOD_MAD,
572 MLX5_VPORT_ACCESS_METHOD_HCA,
573 MLX5_VPORT_ACCESS_METHOD_NIC,
574};
575
576static int mlx5_get_vport_access_method(struct ib_device *ibdev)
577{
578 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
579 return MLX5_VPORT_ACCESS_METHOD_MAD;
580
ebd61f68 581 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 582 IB_LINK_LAYER_ETHERNET)
583 return MLX5_VPORT_ACCESS_METHOD_NIC;
584
585 return MLX5_VPORT_ACCESS_METHOD_HCA;
586}
587
da7525d2 588static void get_atomic_caps(struct mlx5_ib_dev *dev,
776a3906 589 u8 atomic_size_qp,
da7525d2
EBE		 590 struct ib_device_attr *props)
591{
592 u8 tmp;
593 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
da7525d2 594 u8 atomic_req_8B_endianness_mode =
bd10838a 595 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 596
597 /* Check if HW supports 8 bytes standard atomic operations and capable
598 * of host endianness respond
599 */
600 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
601 if (((atomic_operations & tmp) == tmp) &&
602 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
603 (atomic_req_8B_endianness_mode)) {
604 props->atomic_cap = IB_ATOMIC_HCA;
605 } else {
606 props->atomic_cap = IB_ATOMIC_NONE;
607 }
608}
609
776a3906
MS		 610static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
611 struct ib_device_attr *props)
612{
613 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
614
615 get_atomic_caps(dev, atomic_size_qp, props);
616}
617
618static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
619 struct ib_device_attr *props)
620{
621 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
622
623 get_atomic_caps(dev, atomic_size_qp, props);
624}
625
626bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
627{
628 struct ib_device_attr props = {};
629
630 get_atomic_caps_dc(dev, &props);
631 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
632}
1b5daf11
MD		 633static int mlx5_query_system_image_guid(struct ib_device *ibdev,
634 __be64 *sys_image_guid)
635{
636 struct mlx5_ib_dev *dev = to_mdev(ibdev);
637 struct mlx5_core_dev *mdev = dev->mdev;
638 u64 tmp;
639 int err;
640
641 switch (mlx5_get_vport_access_method(ibdev)) {
642 case MLX5_VPORT_ACCESS_METHOD_MAD:
643 return mlx5_query_mad_ifc_system_image_guid(ibdev,
644 sys_image_guid);
645
646 case MLX5_VPORT_ACCESS_METHOD_HCA:
647 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 648 break;
649
650 case MLX5_VPORT_ACCESS_METHOD_NIC:
651 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
652 break;
1b5daf11
MD		 653
654 default:
655 return -EINVAL;
656 }
3f89a643
AS		 657
658 if (!err)
659 *sys_image_guid = cpu_to_be64(tmp);
660
661 return err;
662
1b5daf11
MD		 663}
664
665static int mlx5_query_max_pkeys(struct ib_device *ibdev,
666 u16 *max_pkeys)
667{
668 struct mlx5_ib_dev *dev = to_mdev(ibdev);
669 struct mlx5_core_dev *mdev = dev->mdev;
670
671 switch (mlx5_get_vport_access_method(ibdev)) {
672 case MLX5_VPORT_ACCESS_METHOD_MAD:
673 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
674
675 case MLX5_VPORT_ACCESS_METHOD_HCA:
676 case MLX5_VPORT_ACCESS_METHOD_NIC:
677 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
678 pkey_table_size));
679 return 0;
680
681 default:
682 return -EINVAL;
683 }
684}
685
686static int mlx5_query_vendor_id(struct ib_device *ibdev,
687 u32 *vendor_id)
688{
689 struct mlx5_ib_dev *dev = to_mdev(ibdev);
690
691 switch (mlx5_get_vport_access_method(ibdev)) {
692 case MLX5_VPORT_ACCESS_METHOD_MAD:
693 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
694
695 case MLX5_VPORT_ACCESS_METHOD_HCA:
696 case MLX5_VPORT_ACCESS_METHOD_NIC:
697 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
698
699 default:
700 return -EINVAL;
701 }
702}
703
704static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
705 __be64 *node_guid)
706{
707 u64 tmp;
708 int err;
709
710 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
711 case MLX5_VPORT_ACCESS_METHOD_MAD:
712 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
713
714 case MLX5_VPORT_ACCESS_METHOD_HCA:
715 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 716 break;
717
718 case MLX5_VPORT_ACCESS_METHOD_NIC:
719 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
720 break;
1b5daf11
MD		 721
722 default:
723 return -EINVAL;
724 }
3f89a643
AS		 725
726 if (!err)
727 *node_guid = cpu_to_be64(tmp);
728
729 return err;
1b5daf11
MD		 730}
731
732struct mlx5_reg_node_desc {
bd99fdea 733 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 734};
735
736static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
737{
738 struct mlx5_reg_node_desc in;
739
740 if (mlx5_use_mad_ifc(dev))
741 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
742
743 memset(&in, 0, sizeof(in));
744
745 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
746 sizeof(struct mlx5_reg_node_desc),
747 MLX5_REG_NODE_DESC, 0, 0);
748}
749
e126ba97 750static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 751 struct ib_device_attr *props,
752 struct ib_udata *uhw)
e126ba97
EC		 753{
754 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 755 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 756 int err = -ENOMEM;
288c01b7 757 int max_sq_desc;
e126ba97
EC		 758 int max_rq_sg;
759 int max_sq_sg;
e0238a6a 760 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
85c7c014 761 bool raw_support = !mlx5_core_mp_enabled(mdev);
402ca536
BW		 762 struct mlx5_ib_query_device_resp resp = {};
763 size_t resp_len;
764 u64 max_tso;
e126ba97 765
402ca536
BW		 766 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
767 if (uhw->outlen && uhw->outlen < resp_len)
768 return -EINVAL;
769 else
770 resp.response_length = resp_len;
771
772 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 773 return -EINVAL;
774
1b5daf11
MD		 775 memset(props, 0, sizeof(*props));
776 err = mlx5_query_system_image_guid(ibdev,
777 &props->sys_image_guid);
778 if (err)
779 return err;
e126ba97 780
1b5daf11 781 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 782 if (err)
1b5daf11 783 return err;
e126ba97 784
1b5daf11
MD		 785 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
786 if (err)
787 return err;
e126ba97 788
9603b61d
JM		 789 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
790 (fw_rev_min(dev->mdev) << 16) |
791 fw_rev_sub(dev->mdev);
e126ba97
EC		 792 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
793 IB_DEVICE_PORT_ACTIVE_EVENT |
794 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 795 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 796
797 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 798 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 799 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 800 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 801 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 802 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 803 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 804 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 805 if (MLX5_CAP_GEN(mdev, imaicl)) {
806 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
807 IB_DEVICE_MEM_WINDOW_TYPE_2B;
808 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 809 /* We support 'Gappy' memory registration too */
810 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 811 }
e126ba97 812 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 813 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 814 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
815 /* At this stage no support for signature handover */
816 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
817 IB_PROT_T10DIF_TYPE_2 |
818 IB_PROT_T10DIF_TYPE_3;
819 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
820 IB_GUARD_T10DIF_CSUM;
821 }
938fe83c 822 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 823 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 824
85c7c014 825 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
e8161334
NO		 826 if (MLX5_CAP_ETH(mdev, csum_cap)) {
827 /* Legacy bit to support old userspace libraries */
88115fe7 828 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 829 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
830 }
831
832 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
833 props->raw_packet_caps |=
834 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 835
402ca536
BW		 836 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
837 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
838 if (max_tso) {
839 resp.tso_caps.max_tso = 1 << max_tso;
840 resp.tso_caps.supported_qpts |=
841 1 << IB_QPT_RAW_PACKET;
842 resp.response_length += sizeof(resp.tso_caps);
843 }
844 }
31f69a82
YH		 845
846 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
847 resp.rss_caps.rx_hash_function =
848 MLX5_RX_HASH_FUNC_TOEPLITZ;
849 resp.rss_caps.rx_hash_fields_mask =
850 MLX5_RX_HASH_SRC_IPV4 |
851 MLX5_RX_HASH_DST_IPV4 |
852 MLX5_RX_HASH_SRC_IPV6 |
853 MLX5_RX_HASH_DST_IPV6 |
854 MLX5_RX_HASH_SRC_PORT_TCP |
855 MLX5_RX_HASH_DST_PORT_TCP |
856 MLX5_RX_HASH_SRC_PORT_UDP |
4e2b53a5
MG		 857 MLX5_RX_HASH_DST_PORT_UDP |
858 MLX5_RX_HASH_INNER;
2d93fc85
MB		 859 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
860 MLX5_ACCEL_IPSEC_CAP_DEVICE)
861 resp.rss_caps.rx_hash_fields_mask |=
862 MLX5_RX_HASH_IPSEC_SPI;
31f69a82
YH		 863 resp.response_length += sizeof(resp.rss_caps);
864 }
865 } else {
866 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
867 resp.response_length += sizeof(resp.tso_caps);
868 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
869 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 870 }
871
f0313965
ES		 872 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
873 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
874 props->device_cap_flags |= IB_DEVICE_UD_TSO;
875 }
876
03404e8a 877 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
85c7c014
DJ		 878 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
879 raw_support)
03404e8a
MG		 880 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
881
1d54f890
YH		 882 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
883 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
884 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
885
cff5a0f3 886 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
85c7c014
DJ		 887 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
888 raw_support) {
e8161334 889 /* Legacy bit to support old userspace libraries */
cff5a0f3 890 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 891 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
892 }
cff5a0f3 893
24da0016
AL		 894 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
895 props->max_dm_size =
896 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
897 }
898
da6d6ba3
MG		 899 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
900 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
901
b1383aa6
NO		 902 if (MLX5_CAP_GEN(mdev, end_pad))
903 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
904
1b5daf11
MD		 905 props->vendor_part_id = mdev->pdev->device;
906 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 907
908 props->max_mr_size = ~0ull;
e0238a6a 909 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 910 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
911 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
912 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
913 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 914 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
915 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
916 sizeof(struct mlx5_wqe_raddr_seg)) /
917 sizeof(struct mlx5_wqe_data_seg);
e126ba97 918 props->max_sge = min(max_rq_sg, max_sq_sg);
986ef95e 919 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 920 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 921 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 922 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
923 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
924 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
925 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
926 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
927 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
928 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 929 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 930 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 931 props->max_fast_reg_page_list_len =
932 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
776a3906 933 get_atomic_caps_qp(dev, props);
81bea28f 934 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 935 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
936 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 937 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
938 props->max_mcast_grp;
939 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 940 props->max_ah = INT_MAX;
7c60bcbb
MB		 941 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
942 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 943
8cdd312c 944#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 945 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 946 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
947 props->odp_caps = dev->odp_caps;
948#endif
949
051f2630
LR		 950 if (MLX5_CAP_GEN(mdev, cd))
951 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
952
eff901d3
EC		 953 if (!mlx5_core_is_pf(mdev))
954 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
955
31f69a82 956 if (mlx5_ib_port_link_layer(ibdev, 1) ==
85c7c014 957 IB_LINK_LAYER_ETHERNET && raw_support) {
31f69a82
YH		 958 props->rss_caps.max_rwq_indirection_tables =
959 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
960 props->rss_caps.max_rwq_indirection_table_size =
961 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
962 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
963 props->max_wq_type_rq =
964 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
965 }
966
eb761894 967 if (MLX5_CAP_GEN(mdev, tag_matching)) {
78b1beb0
LR		 968 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
969 props->tm_caps.max_num_tags =
eb761894 970 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
78b1beb0
LR		 971 props->tm_caps.flags = IB_TM_CAP_RC;
972 props->tm_caps.max_ops =
eb761894 973 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
78b1beb0 974 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
eb761894
AK		 975 }
976
87ab3f52
YC		 977 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
978 props->cq_caps.max_cq_moderation_count =
979 MLX5_MAX_CQ_COUNT;
980 props->cq_caps.max_cq_moderation_period =
981 MLX5_MAX_CQ_PERIOD;
982 }
983
7e43a2a5
BW		 984 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
985 resp.cqe_comp_caps.max_num =
986 MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
987 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
988 resp.cqe_comp_caps.supported_format =
989 MLX5_IB_CQE_RES_FORMAT_HASH |
990 MLX5_IB_CQE_RES_FORMAT_CSUM;
991 resp.response_length += sizeof(resp.cqe_comp_caps);
992 }
993
85c7c014
DJ		 994 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
995 raw_support) {
d949167d
BW		 996 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
997 MLX5_CAP_GEN(mdev, qos)) {
998 resp.packet_pacing_caps.qp_rate_limit_max =
999 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1000 resp.packet_pacing_caps.qp_rate_limit_min =
1001 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1002 resp.packet_pacing_caps.supported_qpts |=
1003 1 << IB_QPT_RAW_PACKET;
61147f39
BW		 1004 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1005 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1006 resp.packet_pacing_caps.cap_flags |=
1007 MLX5_IB_PP_SUPPORT_BURST;
d949167d
BW		 1008 }
1009 resp.response_length += sizeof(resp.packet_pacing_caps);
1010 }
1011
9f885201
LR		 1012 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
1013 uhw->outlen)) {
795b609c
BW		 1014 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1015 resp.mlx5_ib_support_multi_pkt_send_wqes =
1016 MLX5_IB_ALLOW_MPW;
050da902
BW		 1017
1018 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1019 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1020 MLX5_IB_SUPPORT_EMPW;
1021
9f885201
LR		 1022 resp.response_length +=
1023 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1024 }
1025
de57f2ad
GL		 1026 if (field_avail(typeof(resp), flags, uhw->outlen)) {
1027 resp.response_length += sizeof(resp.flags);
7a0c8f42 1028
de57f2ad
GL		 1029 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1030 resp.flags |=
1031 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
7a0c8f42
GL		 1032
1033 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1034 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
de57f2ad 1035 }
9f885201 1036
96dc3fc5
NO		 1037 if (field_avail(typeof(resp), sw_parsing_caps,
1038 uhw->outlen)) {
1039 resp.response_length += sizeof(resp.sw_parsing_caps);
1040 if (MLX5_CAP_ETH(mdev, swp)) {
1041 resp.sw_parsing_caps.sw_parsing_offloads |=
1042 MLX5_IB_SW_PARSING;
1043
1044 if (MLX5_CAP_ETH(mdev, swp_csum))
1045 resp.sw_parsing_caps.sw_parsing_offloads |=
1046 MLX5_IB_SW_PARSING_CSUM;
1047
1048 if (MLX5_CAP_ETH(mdev, swp_lso))
1049 resp.sw_parsing_caps.sw_parsing_offloads |=
1050 MLX5_IB_SW_PARSING_LSO;
1051
1052 if (resp.sw_parsing_caps.sw_parsing_offloads)
1053 resp.sw_parsing_caps.supported_qpts =
1054 BIT(IB_QPT_RAW_PACKET);
1055 }
1056 }
1057
85c7c014
DJ		 1058 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1059 raw_support) {
b4f34597
NO		 1060 resp.response_length += sizeof(resp.striding_rq_caps);
1061 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1062 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1063 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1064 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1065 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1066 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1067 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1068 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1069 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1070 resp.striding_rq_caps.supported_qpts =
1071 BIT(IB_QPT_RAW_PACKET);
1072 }
1073 }
1074
f95ef6cb
MG		 1075 if (field_avail(typeof(resp), tunnel_offloads_caps,
1076 uhw->outlen)) {
1077 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1078 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1079 resp.tunnel_offloads_caps |=
1080 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1081 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1082 resp.tunnel_offloads_caps |=
1083 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1084 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1085 resp.tunnel_offloads_caps |=
1086 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1087 }
1088
402ca536
BW		 1089 if (uhw->outlen) {
1090 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1091
1092 if (err)
1093 return err;
1094 }
1095
1b5daf11 1096 return 0;
e126ba97
EC		 1097}
1098
1b5daf11
MD		 1099enum mlx5_ib_width {
1100 MLX5_IB_WIDTH_1X = 1 << 0,
1101 MLX5_IB_WIDTH_2X = 1 << 1,
1102 MLX5_IB_WIDTH_4X = 1 << 2,
1103 MLX5_IB_WIDTH_8X = 1 << 3,
1104 MLX5_IB_WIDTH_12X = 1 << 4
1105};
1106
1107static int translate_active_width(struct ib_device *ibdev, u8 active_width,
1108 u8 *ib_width)
e126ba97
EC		 1109{
1110 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 1111 int err = 0;
1112
1113 if (active_width & MLX5_IB_WIDTH_1X) {
1114 *ib_width = IB_WIDTH_1X;
1115 } else if (active_width & MLX5_IB_WIDTH_2X) {
1116 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
1117 (int)active_width);
1118 err = -EINVAL;
1119 } else if (active_width & MLX5_IB_WIDTH_4X) {
1120 *ib_width = IB_WIDTH_4X;
1121 } else if (active_width & MLX5_IB_WIDTH_8X) {
1122 *ib_width = IB_WIDTH_8X;
1123 } else if (active_width & MLX5_IB_WIDTH_12X) {
1124 *ib_width = IB_WIDTH_12X;
1125 } else {
1126 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
1127 (int)active_width);
1128 err = -EINVAL;
e126ba97
EC		 1129 }
1130
1b5daf11
MD		 1131 return err;
1132}
e126ba97 1133
1b5daf11
MD		 1134static int mlx5_mtu_to_ib_mtu(int mtu)
1135{
1136 switch (mtu) {
1137 case 256: return 1;
1138 case 512: return 2;
1139 case 1024: return 3;
1140 case 2048: return 4;
1141 case 4096: return 5;
1142 default:
1143 pr_warn("invalid mtu\n");
1144 return -1;
e126ba97 1145 }
1b5daf11 1146}
e126ba97 1147
1b5daf11
MD		 1148enum ib_max_vl_num {
1149 __IB_MAX_VL_0 = 1,
1150 __IB_MAX_VL_0_1 = 2,
1151 __IB_MAX_VL_0_3 = 3,
1152 __IB_MAX_VL_0_7 = 4,
1153 __IB_MAX_VL_0_14 = 5,
1154};
e126ba97 1155
1b5daf11
MD		 1156enum mlx5_vl_hw_cap {
1157 MLX5_VL_HW_0 = 1,
1158 MLX5_VL_HW_0_1 = 2,
1159 MLX5_VL_HW_0_2 = 3,
1160 MLX5_VL_HW_0_3 = 4,
1161 MLX5_VL_HW_0_4 = 5,
1162 MLX5_VL_HW_0_5 = 6,
1163 MLX5_VL_HW_0_6 = 7,
1164 MLX5_VL_HW_0_7 = 8,
1165 MLX5_VL_HW_0_14 = 15
1166};
e126ba97 1167
1b5daf11
MD		 1168static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1169 u8 *max_vl_num)
1170{
1171 switch (vl_hw_cap) {
1172 case MLX5_VL_HW_0:
1173 *max_vl_num = __IB_MAX_VL_0;
1174 break;
1175 case MLX5_VL_HW_0_1:
1176 *max_vl_num = __IB_MAX_VL_0_1;
1177 break;
1178 case MLX5_VL_HW_0_3:
1179 *max_vl_num = __IB_MAX_VL_0_3;
1180 break;
1181 case MLX5_VL_HW_0_7:
1182 *max_vl_num = __IB_MAX_VL_0_7;
1183 break;
1184 case MLX5_VL_HW_0_14:
1185 *max_vl_num = __IB_MAX_VL_0_14;
1186 break;
e126ba97 1187
1b5daf11
MD		 1188 default:
1189 return -EINVAL;
e126ba97 1190 }
e126ba97 1191
1b5daf11 1192 return 0;
e126ba97
EC		 1193}
1194
1b5daf11
MD		 1195static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1196 struct ib_port_attr *props)
e126ba97 1197{
1b5daf11
MD		 1198 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1199 struct mlx5_core_dev *mdev = dev->mdev;
1200 struct mlx5_hca_vport_context *rep;
046339ea
SM		 1201 u16 max_mtu;
1202 u16 oper_mtu;
1b5daf11
MD		 1203 int err;
1204 u8 ib_link_width_oper;
1205 u8 vl_hw_cap;
e126ba97 1206
1b5daf11
MD		 1207 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1208 if (!rep) {
1209 err = -ENOMEM;
e126ba97 1210 goto out;
e126ba97 1211 }
e126ba97 1212
c4550c63 1213 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 1214
1b5daf11 1215 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 1216 if (err)
1217 goto out;
1218
1b5daf11
MD		 1219 props->lid = rep->lid;
1220 props->lmc = rep->lmc;
1221 props->sm_lid = rep->sm_lid;
1222 props->sm_sl = rep->sm_sl;
1223 props->state = rep->vport_state;
1224 props->phys_state = rep->port_physical_state;
1225 props->port_cap_flags = rep->cap_mask1;
1226 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1227 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1228 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1229 props->bad_pkey_cntr = rep->pkey_violation_counter;
1230 props->qkey_viol_cntr = rep->qkey_violation_counter;
1231 props->subnet_timeout = rep->subnet_timeout;
1232 props->init_type_reply = rep->init_type_reply;
eff901d3 1233 props->grh_required = rep->grh_required;
e126ba97 1234
1b5daf11
MD		 1235 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1236 if (err)
e126ba97 1237 goto out;
e126ba97 1238
1b5daf11
MD		 1239 err = translate_active_width(ibdev, ib_link_width_oper,
1240 &props->active_width);
1241 if (err)
1242 goto out;
d5beb7f2 1243 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 1244 if (err)
1245 goto out;
1246
facc9699 1247 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 1248
1b5daf11 1249 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 1250
facc9699 1251 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 1252
1b5daf11 1253 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1254
1b5daf11
MD		 1255 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1256 if (err)
1257 goto out;
e126ba97 1258
1b5daf11
MD		 1259 err = translate_max_vl_num(ibdev, vl_hw_cap,
1260 &props->max_vl_num);
e126ba97 1261out:
1b5daf11 1262 kfree(rep);
e126ba97
EC		 1263 return err;
1264}
1265
1b5daf11
MD		 1266int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1267 struct ib_port_attr *props)
e126ba97 1268{
095b0927
IT		 1269 unsigned int count;
1270 int ret;
1271
1b5daf11
MD		 1272 switch (mlx5_get_vport_access_method(ibdev)) {
1273 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1274 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1275 break;
e126ba97 1276
1b5daf11 1277 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1278 ret = mlx5_query_hca_port(ibdev, port, props);
1279 break;
e126ba97 1280
3f89a643 1281 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1282 ret = mlx5_query_port_roce(ibdev, port, props);
1283 break;
3f89a643 1284
1b5daf11 1285 default:
095b0927
IT		 1286 ret = -EINVAL;
1287 }
1288
1289 if (!ret && props) {
b3cbd6f0
DJ		 1290 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1291 struct mlx5_core_dev *mdev;
1292 bool put_mdev = true;
1293
1294 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1295 if (!mdev) {
1296 /* If the port isn't affiliated yet query the master.
1297 * The master and slave will have the same values.
1298 */
1299 mdev = dev->mdev;
1300 port = 1;
1301 put_mdev = false;
1302 }
1303 count = mlx5_core_reserved_gids_count(mdev);
1304 if (put_mdev)
1305 mlx5_ib_put_native_port_mdev(dev, port);
095b0927 1306 props->gid_tbl_len -= count;
1b5daf11 1307 }
095b0927 1308 return ret;
1b5daf11 1309}
e126ba97 1310
8e6efa3a
MB		 1311static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1312 struct ib_port_attr *props)
1313{
1314 int ret;
1315
1316 /* Only link layer == ethernet is valid for representors */
1317 ret = mlx5_query_port_roce(ibdev, port, props);
1318 if (ret || !props)
1319 return ret;
1320
1321 /* We don't support GIDS */
1322 props->gid_tbl_len = 0;
1323
1324 return ret;
1325}
1326
1b5daf11
MD		 1327static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1328 union ib_gid *gid)
1329{
1330 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1331 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1332
1b5daf11
MD		 1333 switch (mlx5_get_vport_access_method(ibdev)) {
1334 case MLX5_VPORT_ACCESS_METHOD_MAD:
1335 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1336
1b5daf11
MD		 1337 case MLX5_VPORT_ACCESS_METHOD_HCA:
1338 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1339
1340 default:
1341 return -EINVAL;
1342 }
e126ba97 1343
e126ba97
EC		 1344}
1345
b3cbd6f0
DJ		 1346static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1347 u16 index, u16 *pkey)
1b5daf11
MD		 1348{
1349 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b3cbd6f0
DJ		 1350 struct mlx5_core_dev *mdev;
1351 bool put_mdev = true;
1352 u8 mdev_port_num;
1353 int err;
1b5daf11 1354
b3cbd6f0
DJ		 1355 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1356 if (!mdev) {
1357 /* The port isn't affiliated yet, get the PKey from the master
1358 * port. For RoCE the PKey tables will be the same.
1359 */
1360 put_mdev = false;
1361 mdev = dev->mdev;
1362 mdev_port_num = 1;
1363 }
1364
1365 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1366 index, pkey);
1367 if (put_mdev)
1368 mlx5_ib_put_native_port_mdev(dev, port);
1369
1370 return err;
1371}
1372
1373static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1374 u16 *pkey)
1375{
1b5daf11
MD		 1376 switch (mlx5_get_vport_access_method(ibdev)) {
1377 case MLX5_VPORT_ACCESS_METHOD_MAD:
1378 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1379
1380 case MLX5_VPORT_ACCESS_METHOD_HCA:
1381 case MLX5_VPORT_ACCESS_METHOD_NIC:
b3cbd6f0 1382 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1b5daf11
MD		 1383 default:
1384 return -EINVAL;
1385 }
1386}
e126ba97
EC		 1387
1388static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1389 struct ib_device_modify *props)
1390{
1391 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1392 struct mlx5_reg_node_desc in;
1393 struct mlx5_reg_node_desc out;
1394 int err;
1395
1396 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1397 return -EOPNOTSUPP;
1398
1399 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1400 return 0;
1401
1402 /*
1403 * If possible, pass node desc to FW, so it can generate
1404 * a 144 trap. If cmd fails, just ignore.
1405 */
bd99fdea 1406 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1407 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1408 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1409 if (err)
1410 return err;
1411
bd99fdea 1412 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1413
1414 return err;
1415}
1416
cdbe33d0
EC		 1417static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1418 u32 value)
1419{
1420 struct mlx5_hca_vport_context ctx = {};
b3cbd6f0
DJ		 1421 struct mlx5_core_dev *mdev;
1422 u8 mdev_port_num;
cdbe33d0
EC		 1423 int err;
1424
b3cbd6f0
DJ		 1425 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1426 if (!mdev)
1427 return -ENODEV;
1428
1429 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
cdbe33d0 1430 if (err)
b3cbd6f0 1431 goto out;
cdbe33d0
EC		 1432
1433 if (~ctx.cap_mask1_perm & mask) {
1434 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1435 mask, ctx.cap_mask1_perm);
b3cbd6f0
DJ		 1436 err = -EINVAL;
1437 goto out;
cdbe33d0
EC		 1438 }
1439
1440 ctx.cap_mask1 = value;
1441 ctx.cap_mask1_perm = mask;
b3cbd6f0
DJ		 1442 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1443 0, &ctx);
1444
1445out:
1446 mlx5_ib_put_native_port_mdev(dev, port_num);
cdbe33d0
EC		 1447
1448 return err;
1449}
1450
e126ba97
EC		 1451static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1452 struct ib_port_modify *props)
1453{
1454 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1455 struct ib_port_attr attr;
1456 u32 tmp;
1457 int err;
cdbe33d0
EC		 1458 u32 change_mask;
1459 u32 value;
1460 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1461 IB_LINK_LAYER_INFINIBAND);
1462
ec255879
MD		 1463 /* CM layer calls ib_modify_port() regardless of the link layer. For
1464 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1465 */
1466 if (!is_ib)
1467 return 0;
1468
cdbe33d0
EC		 1469 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1470 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1471 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1472 return set_port_caps_atomic(dev, port, change_mask, value);
1473 }
e126ba97
EC		 1474
1475 mutex_lock(&dev->cap_mask_mutex);
1476
c4550c63 1477 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1478 if (err)
1479 goto out;
1480
1481 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1482 ~props->clr_port_cap_mask;
1483
9603b61d 1484 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1485
1486out:
1487 mutex_unlock(&dev->cap_mask_mutex);
1488 return err;
1489}
1490
30aa60b3
EC		 1491static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1492{
1493 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1494 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1495}
1496
31a78a5a
YH		 1497static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1498{
1499 /* Large page with non 4k uar support might limit the dynamic size */
1500 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1501 return MLX5_MIN_DYN_BFREGS;
1502
1503 return MLX5_MAX_DYN_BFREGS;
1504}
1505
b037c29a
EC		 1506static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1507 struct mlx5_ib_alloc_ucontext_req_v2 *req,
31a78a5a 1508 struct mlx5_bfreg_info *bfregi)
b037c29a
EC		 1509{
1510 int uars_per_sys_page;
1511 int bfregs_per_sys_page;
1512 int ref_bfregs = req->total_num_bfregs;
1513
1514 if (req->total_num_bfregs == 0)
1515 return -EINVAL;
1516
1517 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1518 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1519
1520 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1521 return -ENOMEM;
1522
1523 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1524 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
31a78a5a 1525 /* This holds the required static allocation asked by the user */
b037c29a 1526 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
b037c29a
EC		 1527 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1528 return -EINVAL;
1529
31a78a5a
YH		 1530 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1531 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1532 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1533 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1534
1535 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
b037c29a
EC		 1536 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1537 lib_uar_4k ? "yes" : "no", ref_bfregs,
31a78a5a
YH		 1538 req->total_num_bfregs, bfregi->total_num_bfregs,
1539 bfregi->num_sys_pages);
b037c29a
EC		 1540
1541 return 0;
1542}
1543
1544static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1545{
1546 struct mlx5_bfreg_info *bfregi;
1547 int err;
1548 int i;
1549
1550 bfregi = &context->bfregi;
31a78a5a 1551 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
b037c29a
EC		 1552 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1553 if (err)
1554 goto error;
1555
1556 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1557 }
4ed131d0
YH		 1558
1559 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1560 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1561
b037c29a
EC		 1562 return 0;
1563
1564error:
1565 for (--i; i >= 0; i--)
1566 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1567 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1568
1569 return err;
1570}
1571
1572static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1573{
1574 struct mlx5_bfreg_info *bfregi;
1575 int err;
1576 int i;
1577
1578 bfregi = &context->bfregi;
4ed131d0
YH		 1579 for (i = 0; i < bfregi->num_sys_pages; i++) {
1580 if (i < bfregi->num_static_sys_pages ||
1581 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) {
1582 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1583 if (err) {
1584 mlx5_ib_warn(dev, "failed to free uar %d, err=%d\n", i, err);
1585 return err;
1586 }
b037c29a
EC		 1587 }
1588 }
4ed131d0 1589
b037c29a
EC		 1590 return 0;
1591}
1592
c85023e1
HN		 1593static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1594{
1595 int err;
1596
1597 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1598 if (err)
1599 return err;
1600
1601 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1602 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1603 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1604 return err;
1605
1606 mutex_lock(&dev->lb_mutex);
1607 dev->user_td++;
1608
1609 if (dev->user_td == 2)
1610 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1611
1612 mutex_unlock(&dev->lb_mutex);
1613 return err;
1614}
1615
1616static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1617{
1618 mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1619
1620 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1621 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1622 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1623 return;
1624
1625 mutex_lock(&dev->lb_mutex);
1626 dev->user_td--;
1627
1628 if (dev->user_td < 2)
1629 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1630
1631 mutex_unlock(&dev->lb_mutex);
1632}
1633
e126ba97
EC		 1634static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1635 struct ib_udata *udata)
1636{
1637 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1638 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1639 struct mlx5_ib_alloc_ucontext_resp resp = {};
5c99eaec 1640 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1641 struct mlx5_ib_ucontext *context;
2f5ff264 1642 struct mlx5_bfreg_info *bfregi;
78c0f98c 1643 int ver;
e126ba97 1644 int err;
a168a41c
MD		 1645 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1646 max_cqe_version);
b037c29a 1647 bool lib_uar_4k;
e126ba97
EC		 1648
1649 if (!dev->ib_active)
1650 return ERR_PTR(-EAGAIN);
1651
e093111d 1652 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1653 ver = 0;
e093111d 1654 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1655 ver = 2;
1656 else
1657 return ERR_PTR(-EINVAL);
1658
e093111d 1659 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97
EC		 1660 if (err)
1661 return ERR_PTR(err);
1662
b368d7cb 1663 if (req.flags)
78c0f98c
EC		 1664 return ERR_PTR(-EINVAL);
1665
f72300c5 1666 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 1667 return ERR_PTR(-EOPNOTSUPP);
1668
2f5ff264
EC		 1669 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1670 MLX5_NON_FP_BFREGS_PER_UAR);
1671 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
e126ba97
EC		 1672 return ERR_PTR(-EINVAL);
1673
938fe83c 1674 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1675 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1676 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1677 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1678 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1679 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1680 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1681 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1682 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1683 resp.cqe_version = min_t(__u8,
1684 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1685 req.max_cqe_version);
30aa60b3
EC		 1686 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1687 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1688 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1689 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1690 resp.response_length = min(offsetof(typeof(resp), response_length) +
1691 sizeof(resp.response_length), udata->outlen);
e126ba97 1692
c03faa56
MB		 1693 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1694 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1695 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1696 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1697 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1698 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1699 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1700 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1701 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1702 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1703 }
1704
e126ba97
EC		 1705 context = kzalloc(sizeof(*context), GFP_KERNEL);
1706 if (!context)
1707 return ERR_PTR(-ENOMEM);
1708
30aa60b3 1709 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1710 bfregi = &context->bfregi;
b037c29a
EC		 1711
1712 /* updates req->total_num_bfregs */
31a78a5a 1713 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
b037c29a 1714 if (err)
e126ba97 1715 goto out_ctx;
e126ba97 1716
b037c29a
EC		 1717 mutex_init(&bfregi->lock);
1718 bfregi->lib_uar_4k = lib_uar_4k;
31a78a5a 1719 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1720 GFP_KERNEL);
b037c29a 1721 if (!bfregi->count) {
e126ba97 1722 err = -ENOMEM;
b037c29a 1723 goto out_ctx;
e126ba97
EC		 1724 }
1725
b037c29a
EC		 1726 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1727 sizeof(*bfregi->sys_pages),
1728 GFP_KERNEL);
1729 if (!bfregi->sys_pages) {
e126ba97 1730 err = -ENOMEM;
b037c29a 1731 goto out_count;
e126ba97
EC		 1732 }
1733
b037c29a
EC		 1734 err = allocate_uars(dev, context);
1735 if (err)
1736 goto out_sys_pages;
e126ba97 1737
b4cfe447
HE		 1738#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1739 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1740#endif
1741
146d2f1a 1742 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
c85023e1 1743 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
146d2f1a 1744 if (err)
c44ef998 1745 goto out_uars;
146d2f1a 1746 }
1747
7c2344c3 1748 INIT_LIST_HEAD(&context->vma_private_list);
ad9a3668 1749 mutex_init(&context->vma_private_list_mutex);
e126ba97
EC		 1750 INIT_LIST_HEAD(&context->db_page_list);
1751 mutex_init(&context->db_page_mutex);
1752
2f5ff264 1753 resp.tot_bfregs = req.total_num_bfregs;
508562d6 1754 resp.num_ports = dev->num_ports;
b368d7cb 1755
f72300c5
HA		 1756 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1757 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1758
402ca536 1759 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1760 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1761 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1762 resp.response_length += sizeof(resp.cmds_supp_uhw);
1763 }
1764
78984898
OG		 1765 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1766 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1767 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1768 resp.eth_min_inline++;
1769 }
1770 resp.response_length += sizeof(resp.eth_min_inline);
1771 }
1772
5c99eaec
FD		 1773 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1774 if (mdev->clock_info)
1775 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1776 resp.response_length += sizeof(resp.clock_info_versions);
1777 }
1778
bc5c6eed
NO		 1779 /*
1780 * We don't want to expose information from the PCI bar that is located
1781 * after 4096 bytes, so if the arch only supports larger pages, let's
1782 * pretend we don't support reading the HCA's core clock. This is also
1783 * forced by mmap function.
1784 */
de8d6e02
EC		 1785 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1786 if (PAGE_SIZE <= 4096) {
1787 resp.comp_mask |=
1788 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1789 resp.hca_core_clock_offset =
1790 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1791 }
5c99eaec 1792 resp.response_length += sizeof(resp.hca_core_clock_offset);
b368d7cb
MB		 1793 }
1794
30aa60b3
EC		 1795 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1796 resp.response_length += sizeof(resp.log_uar_size);
1797
1798 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1799 resp.response_length += sizeof(resp.num_uars_per_page);
1800
31a78a5a
YH		 1801 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1802 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1803 resp.response_length += sizeof(resp.num_dyn_bfregs);
1804 }
1805
b368d7cb 1806 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1807 if (err)
146d2f1a 1808 goto out_td;
e126ba97 1809
2f5ff264
EC		 1810 bfregi->ver = ver;
1811 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1812 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1813 context->lib_caps = req.lib_caps;
1814 print_lib_caps(dev, context->lib_caps);
f72300c5 1815
e126ba97
EC		 1816 return &context->ibucontext;
1817
146d2f1a 1818out_td:
1819 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
c85023e1 1820 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1821
e126ba97 1822out_uars:
b037c29a 1823 deallocate_uars(dev, context);
e126ba97 1824
b037c29a
EC		 1825out_sys_pages:
1826 kfree(bfregi->sys_pages);
e126ba97 1827
b037c29a
EC		 1828out_count:
1829 kfree(bfregi->count);
e126ba97
EC		 1830
1831out_ctx:
1832 kfree(context);
b037c29a 1833
e126ba97
EC		 1834 return ERR_PTR(err);
1835}
1836
1837static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1838{
1839 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1840 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 1841 struct mlx5_bfreg_info *bfregi;
e126ba97 1842
b037c29a 1843 bfregi = &context->bfregi;
146d2f1a 1844 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
c85023e1 1845 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1846
b037c29a
EC		 1847 deallocate_uars(dev, context);
1848 kfree(bfregi->sys_pages);
2f5ff264 1849 kfree(bfregi->count);
e126ba97
EC		 1850 kfree(context);
1851
1852 return 0;
1853}
1854
b037c29a 1855static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
4ed131d0 1856 int uar_idx)
e126ba97 1857{
b037c29a
EC		 1858 int fw_uars_per_page;
1859
1860 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1861
4ed131d0 1862 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
e126ba97
EC		 1863}
1864
1865static int get_command(unsigned long offset)
1866{
1867 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1868}
1869
1870static int get_arg(unsigned long offset)
1871{
1872 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1873}
1874
1875static int get_index(unsigned long offset)
1876{
1877 return get_arg(offset);
1878}
1879
4ed131d0
YH		 1880/* Index resides in an extra byte to enable larger values than 255 */
1881static int get_extended_index(unsigned long offset)
1882{
1883 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1884}
1885
7c2344c3
MG		 1886static void mlx5_ib_vma_open(struct vm_area_struct *area)
1887{
1888 /* vma_open is called when a new VMA is created on top of our VMA. This
1889 * is done through either mremap flow or split_vma (usually due to
1890 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1891 * as this VMA is strongly hardware related. Therefore we set the
1892 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1893 * calling us again and trying to do incorrect actions. We assume that
1894 * the original VMA size is exactly a single page, and therefore all
1895 * "splitting" operation will not happen to it.
1896 */
1897 area->vm_ops = NULL;
1898}
1899
1900static void mlx5_ib_vma_close(struct vm_area_struct *area)
1901{
1902 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1903
1904 /* It's guaranteed that all VMAs opened on a FD are closed before the
1905 * file itself is closed, therefore no sync is needed with the regular
1906 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1907 * However need a sync with accessing the vma as part of
1908 * mlx5_ib_disassociate_ucontext.
1909 * The close operation is usually called under mm->mmap_sem except when
1910 * process is exiting.
1911 * The exiting case is handled explicitly as part of
1912 * mlx5_ib_disassociate_ucontext.
1913 */
1914 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1915
1916 /* setting the vma context pointer to null in the mlx5_ib driver's
1917 * private data, to protect a race condition in
1918 * mlx5_ib_disassociate_ucontext().
1919 */
1920 mlx5_ib_vma_priv_data->vma = NULL;
ad9a3668 1921 mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
7c2344c3 1922 list_del(&mlx5_ib_vma_priv_data->list);
ad9a3668 1923 mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
7c2344c3
MG		 1924 kfree(mlx5_ib_vma_priv_data);
1925}
1926
1927static const struct vm_operations_struct mlx5_ib_vm_ops = {
1928 .open = mlx5_ib_vma_open,
1929 .close = mlx5_ib_vma_close
1930};
1931
1932static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1933 struct mlx5_ib_ucontext *ctx)
1934{
1935 struct mlx5_ib_vma_private_data *vma_prv;
1936 struct list_head *vma_head = &ctx->vma_private_list;
1937
1938 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1939 if (!vma_prv)
1940 return -ENOMEM;
1941
1942 vma_prv->vma = vma;
ad9a3668 1943 vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
7c2344c3
MG		 1944 vma->vm_private_data = vma_prv;
1945 vma->vm_ops = &mlx5_ib_vm_ops;
1946
ad9a3668 1947 mutex_lock(&ctx->vma_private_list_mutex);
7c2344c3 1948 list_add(&vma_prv->list, vma_head);
ad9a3668 1949 mutex_unlock(&ctx->vma_private_list_mutex);
7c2344c3
MG		 1950
1951 return 0;
1952}
1953
1954static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1955{
1956 int ret;
1957 struct vm_area_struct *vma;
1958 struct mlx5_ib_vma_private_data *vma_private, *n;
1959 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1960 struct task_struct *owning_process = NULL;
1961 struct mm_struct *owning_mm = NULL;
1962
1963 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1964 if (!owning_process)
1965 return;
1966
1967 owning_mm = get_task_mm(owning_process);
1968 if (!owning_mm) {
1969 pr_info("no mm, disassociate ucontext is pending task termination\n");
1970 while (1) {
1971 put_task_struct(owning_process);
1972 usleep_range(1000, 2000);
1973 owning_process = get_pid_task(ibcontext->tgid,
1974 PIDTYPE_PID);
1975 if (!owning_process ||
1976 owning_process->state == TASK_DEAD) {
1977 pr_info("disassociate ucontext done, task was terminated\n");
1978 /* in case task was dead need to release the
1979 * task struct.
1980 */
1981 if (owning_process)
1982 put_task_struct(owning_process);
1983 return;
1984 }
1985 }
1986 }
1987
1988 /* need to protect from a race on closing the vma as part of
1989 * mlx5_ib_vma_close.
1990 */
ecc7d83b 1991 down_write(&owning_mm->mmap_sem);
ad9a3668 1992 mutex_lock(&context->vma_private_list_mutex);
7c2344c3
MG		 1993 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1994 list) {
1995 vma = vma_private->vma;
1996 ret = zap_vma_ptes(vma, vma->vm_start,
1997 PAGE_SIZE);
1998 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1999 /* context going to be destroyed, should
2000 * not access ops any more.
2001 */
13776612 2002 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
7c2344c3
MG		 2003 vma->vm_ops = NULL;
2004 list_del(&vma_private->list);
2005 kfree(vma_private);
2006 }
ad9a3668 2007 mutex_unlock(&context->vma_private_list_mutex);
ecc7d83b 2008 up_write(&owning_mm->mmap_sem);
7c2344c3
MG		 2009 mmput(owning_mm);
2010 put_task_struct(owning_process);
2011}
2012
37aa5c36
GL		 2013static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2014{
2015 switch (cmd) {
2016 case MLX5_IB_MMAP_WC_PAGE:
2017 return "WC";
2018 case MLX5_IB_MMAP_REGULAR_PAGE:
2019 return "best effort WC";
2020 case MLX5_IB_MMAP_NC_PAGE:
2021 return "NC";
24da0016
AL		 2022 case MLX5_IB_MMAP_DEVICE_MEM:
2023 return "Device Memory";
37aa5c36
GL		 2024 default:
2025 return NULL;
2026 }
2027}
2028
5c99eaec
FD		 2029static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2030 struct vm_area_struct *vma,
2031 struct mlx5_ib_ucontext *context)
2032{
2033 phys_addr_t pfn;
2034 int err;
2035
2036 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2037 return -EINVAL;
2038
2039 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2040 return -EOPNOTSUPP;
2041
2042 if (vma->vm_flags & VM_WRITE)
2043 return -EPERM;
2044
2045 if (!dev->mdev->clock_info_page)
2046 return -EOPNOTSUPP;
2047
2048 pfn = page_to_pfn(dev->mdev->clock_info_page);
2049 err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE,
2050 vma->vm_page_prot);
2051 if (err)
2052 return err;
2053
2054 mlx5_ib_dbg(dev, "mapped clock info at 0x%lx, PA 0x%llx\n",
2055 vma->vm_start,
2056 (unsigned long long)pfn << PAGE_SHIFT);
2057
2058 return mlx5_ib_set_vma_data(vma, context);
2059}
2060
37aa5c36 2061static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 2062 struct vm_area_struct *vma,
2063 struct mlx5_ib_ucontext *context)
37aa5c36 2064{
2f5ff264 2065 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 2066 int err;
2067 unsigned long idx;
2068 phys_addr_t pfn, pa;
2069 pgprot_t prot;
4ed131d0
YH		 2070 u32 bfreg_dyn_idx = 0;
2071 u32 uar_index;
2072 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2073 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2074 bfregi->num_static_sys_pages;
b037c29a
EC		 2075
2076 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2077 return -EINVAL;
2078
4ed131d0
YH		 2079 if (dyn_uar)
2080 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2081 else
2082 idx = get_index(vma->vm_pgoff);
2083
2084 if (idx >= max_valid_idx) {
2085 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2086 idx, max_valid_idx);
b037c29a
EC		 2087 return -EINVAL;
2088 }
37aa5c36
GL		 2089
2090 switch (cmd) {
2091 case MLX5_IB_MMAP_WC_PAGE:
4ed131d0 2092 case MLX5_IB_MMAP_ALLOC_WC:
37aa5c36
GL		 2093/* Some architectures don't support WC memory */
2094#if defined(CONFIG_X86)
2095 if (!pat_enabled())
2096 return -EPERM;
2097#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2098 return -EPERM;
2099#endif
2100 /* fall through */
2101 case MLX5_IB_MMAP_REGULAR_PAGE:
2102 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2103 prot = pgprot_writecombine(vma->vm_page_prot);
2104 break;
2105 case MLX5_IB_MMAP_NC_PAGE:
2106 prot = pgprot_noncached(vma->vm_page_prot);
2107 break;
2108 default:
2109 return -EINVAL;
2110 }
2111
4ed131d0
YH		 2112 if (dyn_uar) {
2113 int uars_per_page;
2114
2115 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2116 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2117 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2118 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2119 bfreg_dyn_idx, bfregi->total_num_bfregs);
2120 return -EINVAL;
2121 }
2122
2123 mutex_lock(&bfregi->lock);
2124 /* Fail if uar already allocated, first bfreg index of each
2125 * page holds its count.
2126 */
2127 if (bfregi->count[bfreg_dyn_idx]) {
2128 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2129 mutex_unlock(&bfregi->lock);
2130 return -EINVAL;
2131 }
2132
2133 bfregi->count[bfreg_dyn_idx]++;
2134 mutex_unlock(&bfregi->lock);
2135
2136 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2137 if (err) {
2138 mlx5_ib_warn(dev, "UAR alloc failed\n");
2139 goto free_bfreg;
2140 }
2141 } else {
2142 uar_index = bfregi->sys_pages[idx];
2143 }
2144
2145 pfn = uar_index2pfn(dev, uar_index);
37aa5c36
GL		 2146 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2147
2148 vma->vm_page_prot = prot;
2149 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
2150 PAGE_SIZE, vma->vm_page_prot);
2151 if (err) {
2152 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
2153 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
4ed131d0
YH		 2154 err = -EAGAIN;
2155 goto err;
37aa5c36
GL		 2156 }
2157
2158 pa = pfn << PAGE_SHIFT;
2159 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
2160 vma->vm_start, &pa);
2161
4ed131d0
YH		 2162 err = mlx5_ib_set_vma_data(vma, context);
2163 if (err)
2164 goto err;
2165
2166 if (dyn_uar)
2167 bfregi->sys_pages[idx] = uar_index;
2168 return 0;
2169
2170err:
2171 if (!dyn_uar)
2172 return err;
2173
2174 mlx5_cmd_free_uar(dev->mdev, idx);
2175
2176free_bfreg:
2177 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2178
2179 return err;
37aa5c36
GL		 2180}
2181
24da0016
AL		 2182static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2183{
2184 struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2185 struct mlx5_ib_dev *dev = to_mdev(context->device);
2186 u16 page_idx = get_extended_index(vma->vm_pgoff);
2187 size_t map_size = vma->vm_end - vma->vm_start;
2188 u32 npages = map_size >> PAGE_SHIFT;
2189 phys_addr_t pfn;
2190 pgprot_t prot;
2191
2192 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2193 page_idx + npages)
2194 return -EINVAL;
2195
2196 pfn = ((pci_resource_start(dev->mdev->pdev, 0) +
2197 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2198 PAGE_SHIFT) +
2199 page_idx;
2200 prot = pgprot_writecombine(vma->vm_page_prot);
2201 vma->vm_page_prot = prot;
2202
2203 if (io_remap_pfn_range(vma, vma->vm_start, pfn, map_size,
2204 vma->vm_page_prot))
2205 return -EAGAIN;
2206
2207 return mlx5_ib_set_vma_data(vma, mctx);
2208}
2209
e126ba97
EC		 2210static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2211{
2212 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2213 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 2214 unsigned long command;
e126ba97
EC		 2215 phys_addr_t pfn;
2216
2217 command = get_command(vma->vm_pgoff);
2218 switch (command) {
37aa5c36
GL		 2219 case MLX5_IB_MMAP_WC_PAGE:
2220 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 2221 case MLX5_IB_MMAP_REGULAR_PAGE:
4ed131d0 2222 case MLX5_IB_MMAP_ALLOC_WC:
7c2344c3 2223 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 2224
2225 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2226 return -ENOSYS;
2227
d69e3bcf 2228 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 2229 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2230 return -EINVAL;
2231
6cbac1e4 2232 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 2233 return -EPERM;
2234
2235 /* Don't expose to user-space information it shouldn't have */
2236 if (PAGE_SIZE > 4096)
2237 return -EOPNOTSUPP;
2238
2239 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2240 pfn = (dev->mdev->iseg_base +
2241 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2242 PAGE_SHIFT;
2243 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2244 PAGE_SIZE, vma->vm_page_prot))
2245 return -EAGAIN;
2246
2247 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
2248 vma->vm_start,
2249 (unsigned long long)pfn << PAGE_SHIFT);
2250 break;
5c99eaec
FD		 2251 case MLX5_IB_MMAP_CLOCK_INFO:
2252 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
d69e3bcf 2253
24da0016
AL		 2254 case MLX5_IB_MMAP_DEVICE_MEM:
2255 return dm_mmap(ibcontext, vma);
2256
e126ba97
EC		 2257 default:
2258 return -EINVAL;
2259 }
2260
2261 return 0;
2262}
2263
24da0016
AL		 2264struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2265 struct ib_ucontext *context,
2266 struct ib_dm_alloc_attr *attr,
2267 struct uverbs_attr_bundle *attrs)
2268{
2269 u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2270 struct mlx5_memic *memic = &to_mdev(ibdev)->memic;
2271 phys_addr_t memic_addr;
2272 struct mlx5_ib_dm *dm;
2273 u64 start_offset;
2274 u32 page_idx;
2275 int err;
2276
2277 dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2278 if (!dm)
2279 return ERR_PTR(-ENOMEM);
2280
2281 mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n",
2282 attr->length, act_size, attr->alignment);
2283
2284 err = mlx5_cmd_alloc_memic(memic, &memic_addr,
2285 act_size, attr->alignment);
2286 if (err)
2287 goto err_free;
2288
2289 start_offset = memic_addr & ~PAGE_MASK;
2290 page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) -
2291 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2292 PAGE_SHIFT;
2293
2294 err = uverbs_copy_to(attrs,
2295 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2296 &start_offset, sizeof(start_offset));
2297 if (err)
2298 goto err_dealloc;
2299
2300 err = uverbs_copy_to(attrs,
2301 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2302 &page_idx, sizeof(page_idx));
2303 if (err)
2304 goto err_dealloc;
2305
2306 bitmap_set(to_mucontext(context)->dm_pages, page_idx,
2307 DIV_ROUND_UP(act_size, PAGE_SIZE));
2308
2309 dm->dev_addr = memic_addr;
2310
2311 return &dm->ibdm;
2312
2313err_dealloc:
2314 mlx5_cmd_dealloc_memic(memic, memic_addr,
2315 act_size);
2316err_free:
2317 kfree(dm);
2318 return ERR_PTR(err);
2319}
2320
2321int mlx5_ib_dealloc_dm(struct ib_dm *ibdm)
2322{
2323 struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic;
2324 struct mlx5_ib_dm *dm = to_mdm(ibdm);
2325 u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE);
2326 u32 page_idx;
2327 int ret;
2328
2329 ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size);
2330 if (ret)
2331 return ret;
2332
2333 page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) -
2334 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2335 PAGE_SHIFT;
2336 bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages,
2337 page_idx,
2338 DIV_ROUND_UP(act_size, PAGE_SIZE));
2339
2340 kfree(dm);
2341
2342 return 0;
2343}
2344
e126ba97
EC		 2345static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2346 struct ib_ucontext *context,
2347 struct ib_udata *udata)
2348{
2349 struct mlx5_ib_alloc_pd_resp resp;
2350 struct mlx5_ib_pd *pd;
2351 int err;
2352
2353 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
2354 if (!pd)
2355 return ERR_PTR(-ENOMEM);
2356
9603b61d 2357 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 2358 if (err) {
2359 kfree(pd);
2360 return ERR_PTR(err);
2361 }
2362
2363 if (context) {
2364 resp.pdn = pd->pdn;
2365 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 2366 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 2367 kfree(pd);
2368 return ERR_PTR(-EFAULT);
2369 }
e126ba97
EC		 2370 }
2371
2372 return &pd->ibpd;
2373}
2374
2375static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2376{
2377 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2378 struct mlx5_ib_pd *mpd = to_mpd(pd);
2379
9603b61d 2380 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 2381 kfree(mpd);
2382
2383 return 0;
2384}
2385
466fa6d2
MG		 2386enum {
2387 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2388 MATCH_CRITERIA_ENABLE_MISC_BIT,
2389 MATCH_CRITERIA_ENABLE_INNER_BIT
2390};
2391
2392#define HEADER_IS_ZERO(match_criteria, headers) \
2393 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2394 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 2395
466fa6d2 2396static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 2397{
466fa6d2 2398 u8 match_criteria_enable;
038d2ef8 2399
466fa6d2
MG		 2400 match_criteria_enable =
2401 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2402 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2403 match_criteria_enable |=
2404 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2405 MATCH_CRITERIA_ENABLE_MISC_BIT;
2406 match_criteria_enable |=
2407 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2408 MATCH_CRITERIA_ENABLE_INNER_BIT;
2409
2410 return match_criteria_enable;
038d2ef8
MG		 2411}
2412
ca0d4753
MG		 2413static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2414{
2415 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2416 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
038d2ef8
MG		 2417}
2418
2d1e697e
MR		 2419static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
2420 bool inner)
2421{
2422 if (inner) {
2423 MLX5_SET(fte_match_set_misc,
2424 misc_c, inner_ipv6_flow_label, mask);
2425 MLX5_SET(fte_match_set_misc,
2426 misc_v, inner_ipv6_flow_label, val);
2427 } else {
2428 MLX5_SET(fte_match_set_misc,
2429 misc_c, outer_ipv6_flow_label, mask);
2430 MLX5_SET(fte_match_set_misc,
2431 misc_v, outer_ipv6_flow_label, val);
2432 }
2433}
2434
ca0d4753
MG		 2435static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2436{
2437 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2438 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2439 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2440 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2441}
2442
c47ac6ae
MG		 2443#define LAST_ETH_FIELD vlan_tag
2444#define LAST_IB_FIELD sl
ca0d4753 2445#define LAST_IPV4_FIELD tos
466fa6d2 2446#define LAST_IPV6_FIELD traffic_class
c47ac6ae 2447#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 2448#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 2449#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 2450#define LAST_DROP_FIELD size
c47ac6ae
MG		 2451
2452/* Field is the last supported field */
2453#define FIELDS_NOT_SUPPORTED(filter, field)\
2454 memchr_inv((void *)&filter.field +\
2455 sizeof(filter.field), 0,\
2456 sizeof(filter) -\
2457 offsetof(typeof(filter), field) -\
2458 sizeof(filter.field))
2459
802c2125
AY		 2460static int parse_flow_flow_action(const union ib_flow_spec *ib_spec,
2461 const struct ib_flow_attr *flow_attr,
2462 struct mlx5_flow_act *action)
2463{
2464 struct mlx5_ib_flow_action *maction = to_mflow_act(ib_spec->action.act);
2465
2466 switch (maction->ib_action.type) {
2467 case IB_FLOW_ACTION_ESP:
2468 /* Currently only AES_GCM keymat is supported by the driver */
2469 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2470 action->action |= flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS ?
2471 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2472 MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2473 return 0;
2474 default:
2475 return -EOPNOTSUPP;
2476 }
2477}
2478
19cc7524
AL		 2479static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2480 u32 *match_v, const union ib_flow_spec *ib_spec,
802c2125 2481 const struct ib_flow_attr *flow_attr,
075572d4 2482 struct mlx5_flow_act *action)
038d2ef8 2483{
466fa6d2
MG		 2484 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2485 misc_parameters);
2486 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2487 misc_parameters);
2d1e697e
MR		 2488 void *headers_c;
2489 void *headers_v;
19cc7524 2490 int match_ipv;
802c2125 2491 int ret;
2d1e697e
MR		 2492
2493 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2494 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2495 inner_headers);
2496 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2497 inner_headers);
19cc7524
AL		 2498 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2499 ft_field_support.inner_ip_version);
2d1e697e
MR		 2500 } else {
2501 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2502 outer_headers);
2503 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2504 outer_headers);
19cc7524
AL		 2505 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2506 ft_field_support.outer_ip_version);
2d1e697e 2507 }
466fa6d2 2508
2d1e697e 2509 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 2510 case IB_FLOW_SPEC_ETH:
c47ac6ae 2511 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 2512 return -EOPNOTSUPP;
038d2ef8 2513
2d1e697e 2514 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2515 dmac_47_16),
2516 ib_spec->eth.mask.dst_mac);
2d1e697e 2517 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2518 dmac_47_16),
2519 ib_spec->eth.val.dst_mac);
2520
2d1e697e 2521 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 2522 smac_47_16),
2523 ib_spec->eth.mask.src_mac);
2d1e697e 2524 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 2525 smac_47_16),
2526 ib_spec->eth.val.src_mac);
2527
038d2ef8 2528 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 2529 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 2530 cvlan_tag, 1);
2d1e697e 2531 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 2532 cvlan_tag, 1);
038d2ef8 2533
2d1e697e 2534 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2535 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 2536 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2537 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2538
2d1e697e 2539 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2540 first_cfi,
2541 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 2542 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2543 first_cfi,
2544 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2545
2d1e697e 2546 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2547 first_prio,
2548 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 2549 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2550 first_prio,
2551 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2552 }
2d1e697e 2553 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2554 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 2555 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2556 ethertype, ntohs(ib_spec->eth.val.ether_type));
2557 break;
2558 case IB_FLOW_SPEC_IPV4:
c47ac6ae 2559 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 2560 return -EOPNOTSUPP;
038d2ef8 2561
19cc7524
AL		 2562 if (match_ipv) {
2563 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2564 ip_version, 0xf);
2565 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2566 ip_version, MLX5_FS_IPV4_VERSION);
19cc7524
AL		 2567 } else {
2568 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2569 ethertype, 0xffff);
2570 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2571 ethertype, ETH_P_IP);
2572 }
038d2ef8 2573
2d1e697e 2574 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2575 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2576 &ib_spec->ipv4.mask.src_ip,
2577 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 2578 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2579 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2580 &ib_spec->ipv4.val.src_ip,
2581 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 2582 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2583 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2584 &ib_spec->ipv4.mask.dst_ip,
2585 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 2586 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2587 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2588 &ib_spec->ipv4.val.dst_ip,
2589 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 2590
2d1e697e 2591 set_tos(headers_c, headers_v,
ca0d4753
MG		 2592 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2593
2d1e697e 2594 set_proto(headers_c, headers_v,
ca0d4753 2595 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
038d2ef8 2596 break;
026bae0c 2597 case IB_FLOW_SPEC_IPV6:
c47ac6ae 2598 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 2599 return -EOPNOTSUPP;
026bae0c 2600
19cc7524
AL		 2601 if (match_ipv) {
2602 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2603 ip_version, 0xf);
2604 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2605 ip_version, MLX5_FS_IPV6_VERSION);
19cc7524
AL		 2606 } else {
2607 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2608 ethertype, 0xffff);
2609 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2610 ethertype, ETH_P_IPV6);
2611 }
026bae0c 2612
2d1e697e 2613 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2614 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2615 &ib_spec->ipv6.mask.src_ip,
2616 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2617 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2618 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2619 &ib_spec->ipv6.val.src_ip,
2620 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2621 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2622 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2623 &ib_spec->ipv6.mask.dst_ip,
2624 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2625 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2626 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2627 &ib_spec->ipv6.val.dst_ip,
2628 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2629
2d1e697e 2630 set_tos(headers_c, headers_v,
466fa6d2
MG		 2631 ib_spec->ipv6.mask.traffic_class,
2632 ib_spec->ipv6.val.traffic_class);
2633
2d1e697e 2634 set_proto(headers_c, headers_v,
466fa6d2
MG		 2635 ib_spec->ipv6.mask.next_hdr,
2636 ib_spec->ipv6.val.next_hdr);
2637
2d1e697e
MR		 2638 set_flow_label(misc_params_c, misc_params_v,
2639 ntohl(ib_spec->ipv6.mask.flow_label),
2640 ntohl(ib_spec->ipv6.val.flow_label),
2641 ib_spec->type & IB_FLOW_SPEC_INNER);
802c2125
AY		 2642 break;
2643 case IB_FLOW_SPEC_ESP:
2644 if (ib_spec->esp.mask.seq)
2645 return -EOPNOTSUPP;
2d1e697e 2646
802c2125
AY		 2647 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2648 ntohl(ib_spec->esp.mask.spi));
2649 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2650 ntohl(ib_spec->esp.val.spi));
026bae0c 2651 break;
038d2ef8 2652 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2653 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2654 LAST_TCP_UDP_FIELD))
1ffd3a26 2655 return -EOPNOTSUPP;
038d2ef8 2656
2d1e697e 2657 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2658 0xff);
2d1e697e 2659 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2660 IPPROTO_TCP);
2661
2d1e697e 2662 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2663 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2664 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2665 ntohs(ib_spec->tcp_udp.val.src_port));
2666
2d1e697e 2667 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2668 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2669 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2670 ntohs(ib_spec->tcp_udp.val.dst_port));
2671 break;
2672 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2673 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2674 LAST_TCP_UDP_FIELD))
1ffd3a26 2675 return -EOPNOTSUPP;
038d2ef8 2676
2d1e697e 2677 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2678 0xff);
2d1e697e 2679 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2680 IPPROTO_UDP);
2681
2d1e697e 2682 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2683 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2684 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2685 ntohs(ib_spec->tcp_udp.val.src_port));
2686
2d1e697e 2687 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2688 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2689 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2690 ntohs(ib_spec->tcp_udp.val.dst_port));
2691 break;
ffb30d8f
MR		 2692 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2693 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2694 LAST_TUNNEL_FIELD))
1ffd3a26 2695 return -EOPNOTSUPP;
ffb30d8f
MR		 2696
2697 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2698 ntohl(ib_spec->tunnel.mask.tunnel_id));
2699 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2700 ntohl(ib_spec->tunnel.val.tunnel_id));
2701 break;
2ac693f9
MR		 2702 case IB_FLOW_SPEC_ACTION_TAG:
2703 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2704 LAST_FLOW_TAG_FIELD))
2705 return -EOPNOTSUPP;
2706 if (ib_spec->flow_tag.tag_id >= BIT(24))
2707 return -EINVAL;
2708
075572d4 2709 action->flow_tag = ib_spec->flow_tag.tag_id;
a9db0ecf 2710 action->has_flow_tag = true;
2ac693f9 2711 break;
a22ed86c
SS		 2712 case IB_FLOW_SPEC_ACTION_DROP:
2713 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2714 LAST_DROP_FIELD))
2715 return -EOPNOTSUPP;
075572d4 2716 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
a22ed86c 2717 break;
802c2125
AY		 2718 case IB_FLOW_SPEC_ACTION_HANDLE:
2719 ret = parse_flow_flow_action(ib_spec, flow_attr, action);
2720 if (ret)
2721 return ret;
2722 break;
038d2ef8
MG		 2723 default:
2724 return -EINVAL;
2725 }
2726
2727 return 0;
2728}
2729
2730/* If a flow could catch both multicast and unicast packets,
2731 * it won't fall into the multicast flow steering table and this rule
2732 * could steal other multicast packets.
2733 */
a550ddfc 2734static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
038d2ef8 2735{
81e30880 2736 union ib_flow_spec *flow_spec;
038d2ef8
MG		 2737
2738 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 2739 ib_attr->num_of_specs < 1)
2740 return false;
2741
81e30880
YH		 2742 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2743 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2744 struct ib_flow_spec_ipv4 *ipv4_spec;
2745
2746 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2747 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2748 return true;
2749
038d2ef8 2750 return false;
81e30880
YH		 2751 }
2752
2753 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2754 struct ib_flow_spec_eth *eth_spec;
2755
2756 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2757 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2758 is_multicast_ether_addr(eth_spec->val.dst_mac);
2759 }
038d2ef8 2760
81e30880 2761 return false;
038d2ef8
MG		 2762}
2763
802c2125
AY		 2764enum valid_spec {
2765 VALID_SPEC_INVALID,
2766 VALID_SPEC_VALID,
2767 VALID_SPEC_NA,
2768};
2769
2770static enum valid_spec
2771is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
2772 const struct mlx5_flow_spec *spec,
2773 const struct mlx5_flow_act *flow_act,
2774 bool egress)
2775{
2776 const u32 *match_c = spec->match_criteria;
2777 bool is_crypto =
2778 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2779 MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
2780 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
2781 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
2782
2783 /*
2784 * Currently only crypto is supported in egress, when regular egress
2785 * rules would be supported, always return VALID_SPEC_NA.
2786 */
2787 if (!is_crypto)
2788 return egress ? VALID_SPEC_INVALID : VALID_SPEC_NA;
2789
2790 return is_crypto && is_ipsec &&
2791 (!egress || (!is_drop && !flow_act->has_flow_tag)) ?
2792 VALID_SPEC_VALID : VALID_SPEC_INVALID;
2793}
2794
2795static bool is_valid_spec(struct mlx5_core_dev *mdev,
2796 const struct mlx5_flow_spec *spec,
2797 const struct mlx5_flow_act *flow_act,
2798 bool egress)
2799{
2800 /* We curretly only support ipsec egress flow */
2801 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
2802}
2803
19cc7524
AL		 2804static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2805 const struct ib_flow_attr *flow_attr,
0f750966 2806 bool check_inner)
038d2ef8
MG		 2807{
2808 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 2809 int match_ipv = check_inner ?
2810 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2811 ft_field_support.inner_ip_version) :
2812 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2813 ft_field_support.outer_ip_version);
0f750966
AL		 2814 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2815 bool ipv4_spec_valid, ipv6_spec_valid;
2816 unsigned int ip_spec_type = 0;
2817 bool has_ethertype = false;
038d2ef8 2818 unsigned int spec_index;
0f750966
AL		 2819 bool mask_valid = true;
2820 u16 eth_type = 0;
2821 bool type_valid;
038d2ef8
MG		 2822
2823 /* Validate that ethertype is correct */
2824 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 2825 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 2826 ib_spec->eth.mask.ether_type) {
0f750966
AL		 2827 mask_valid = (ib_spec->eth.mask.ether_type ==
2828 htons(0xffff));
2829 has_ethertype = true;
2830 eth_type = ntohs(ib_spec->eth.val.ether_type);
2831 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2832 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2833 ip_spec_type = ib_spec->type;
038d2ef8
MG		 2834 }
2835 ib_spec = (void *)ib_spec + ib_spec->size;
2836 }
0f750966
AL		 2837
2838 type_valid = (!has_ethertype) || (!ip_spec_type);
2839 if (!type_valid && mask_valid) {
2840 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2841 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2842 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2843 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 2844
2845 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2846 (((eth_type == ETH_P_MPLS_UC) ||
2847 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 2848 }
2849
2850 return type_valid;
2851}
2852
19cc7524
AL		 2853static bool is_valid_attr(struct mlx5_core_dev *mdev,
2854 const struct ib_flow_attr *flow_attr)
0f750966 2855{
19cc7524
AL		 2856 return is_valid_ethertype(mdev, flow_attr, false) &&
2857 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 2858}
2859
2860static void put_flow_table(struct mlx5_ib_dev *dev,
2861 struct mlx5_ib_flow_prio *prio, bool ft_added)
2862{
2863 prio->refcount -= !!ft_added;
2864 if (!prio->refcount) {
2865 mlx5_destroy_flow_table(prio->flow_table);
2866 prio->flow_table = NULL;
2867 }
2868}
2869
2870static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2871{
2872 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2873 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2874 struct mlx5_ib_flow_handler,
2875 ibflow);
2876 struct mlx5_ib_flow_handler *iter, *tmp;
2877
9a4ca38d 2878 mutex_lock(&dev->flow_db->lock);
038d2ef8
MG		 2879
2880 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 2881 mlx5_del_flow_rules(iter->rule);
cc0e5d42 2882 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 2883 list_del(&iter->list);
2884 kfree(iter);
2885 }
2886
74491de9 2887 mlx5_del_flow_rules(handler->rule);
5497adc6 2888 put_flow_table(dev, handler->prio, true);
9a4ca38d 2889 mutex_unlock(&dev->flow_db->lock);
038d2ef8
MG		 2890
2891 kfree(handler);
2892
2893 return 0;
2894}
2895
35d19011
MG		 2896static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2897{
2898 priority *= 2;
2899 if (!dont_trap)
2900 priority++;
2901 return priority;
2902}
2903
cc0e5d42
MG		 2904enum flow_table_type {
2905 MLX5_IB_FT_RX,
2906 MLX5_IB_FT_TX
2907};
2908
00b7c2ab
MG		 2909#define MLX5_FS_MAX_TYPES 6
2910#define MLX5_FS_MAX_ENTRIES BIT(16)
038d2ef8 2911static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 2912 struct ib_flow_attr *flow_attr,
2913 enum flow_table_type ft_type)
038d2ef8 2914{
35d19011 2915 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 2916 struct mlx5_flow_namespace *ns = NULL;
2917 struct mlx5_ib_flow_prio *prio;
2918 struct mlx5_flow_table *ft;
dac388ef 2919 int max_table_size;
038d2ef8
MG		 2920 int num_entries;
2921 int num_groups;
2922 int priority;
2923 int err = 0;
2924
dac388ef
MG		 2925 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2926 log_max_ft_size));
038d2ef8 2927 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
802c2125
AY		 2928 if (ft_type == MLX5_IB_FT_TX)
2929 priority = 0;
2930 else if (flow_is_multicast_only(flow_attr) &&
2931 !dont_trap)
038d2ef8
MG		 2932 priority = MLX5_IB_FLOW_MCAST_PRIO;
2933 else
35d19011
MG		 2934 priority = ib_prio_to_core_prio(flow_attr->priority,
2935 dont_trap);
038d2ef8 2936 ns = mlx5_get_flow_namespace(dev->mdev,
802c2125
AY		 2937 ft_type == MLX5_IB_FT_TX ?
2938 MLX5_FLOW_NAMESPACE_EGRESS :
038d2ef8
MG		 2939 MLX5_FLOW_NAMESPACE_BYPASS);
2940 num_entries = MLX5_FS_MAX_ENTRIES;
2941 num_groups = MLX5_FS_MAX_TYPES;
9a4ca38d 2942 prio = &dev->flow_db->prios[priority];
038d2ef8
MG		 2943 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2944 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2945 ns = mlx5_get_flow_namespace(dev->mdev,
2946 MLX5_FLOW_NAMESPACE_LEFTOVERS);
2947 build_leftovers_ft_param(&priority,
2948 &num_entries,
2949 &num_groups);
9a4ca38d 2950 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 2951 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2952 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2953 allow_sniffer_and_nic_rx_shared_tir))
2954 return ERR_PTR(-ENOTSUPP);
2955
2956 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2957 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2958 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2959
9a4ca38d 2960 prio = &dev->flow_db->sniffer[ft_type];
cc0e5d42
MG		 2961 priority = 0;
2962 num_entries = 1;
2963 num_groups = 1;
038d2ef8
MG		 2964 }
2965
2966 if (!ns)
2967 return ERR_PTR(-ENOTSUPP);
2968
dac388ef
MG		 2969 if (num_entries > max_table_size)
2970 return ERR_PTR(-ENOMEM);
2971
038d2ef8
MG		 2972 ft = prio->flow_table;
2973 if (!ft) {
2974 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2975 num_entries,
d63cd286 2976 num_groups,
c9f1b073 2977 0, 0);
038d2ef8
MG		 2978
2979 if (!IS_ERR(ft)) {
2980 prio->refcount = 0;
2981 prio->flow_table = ft;
2982 } else {
2983 err = PTR_ERR(ft);
2984 }
2985 }
2986
2987 return err ? ERR_PTR(err) : prio;
2988}
2989
a550ddfc
YH		 2990static void set_underlay_qp(struct mlx5_ib_dev *dev,
2991 struct mlx5_flow_spec *spec,
2992 u32 underlay_qpn)
2993{
2994 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
2995 spec->match_criteria,
2996 misc_parameters);
2997 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2998 misc_parameters);
2999
3000 if (underlay_qpn &&
3001 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3002 ft_field_support.bth_dst_qp)) {
3003 MLX5_SET(fte_match_set_misc,
3004 misc_params_v, bth_dst_qp, underlay_qpn);
3005 MLX5_SET(fte_match_set_misc,
3006 misc_params_c, bth_dst_qp, 0xffffff);
3007 }
3008}
3009
3010static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3011 struct mlx5_ib_flow_prio *ft_prio,
3012 const struct ib_flow_attr *flow_attr,
3013 struct mlx5_flow_destination *dst,
3014 u32 underlay_qpn)
038d2ef8
MG		 3015{
3016 struct mlx5_flow_table *ft = ft_prio->flow_table;
3017 struct mlx5_ib_flow_handler *handler;
075572d4 3018 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
c5bb1730 3019 struct mlx5_flow_spec *spec;
a22ed86c 3020 struct mlx5_flow_destination *rule_dst = dst;
dd063d0e 3021 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 3022 unsigned int spec_index;
038d2ef8 3023 int err = 0;
a22ed86c 3024 int dest_num = 1;
802c2125 3025 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
038d2ef8 3026
19cc7524 3027 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 3028 return ERR_PTR(-EINVAL);
3029
1b9a07ee 3030 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 3031 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 3032 if (!handler || !spec) {
038d2ef8
MG		 3033 err = -ENOMEM;
3034 goto free;
3035 }
3036
3037 INIT_LIST_HEAD(&handler->list);
3038
3039 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
19cc7524 3040 err = parse_flow_attr(dev->mdev, spec->match_criteria,
a22ed86c 3041 spec->match_value,
802c2125 3042 ib_flow, flow_attr, &flow_act);
038d2ef8
MG		 3043 if (err < 0)
3044 goto free;
3045
3046 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3047 }
3048
a550ddfc
YH		 3049 if (!flow_is_multicast_only(flow_attr))
3050 set_underlay_qp(dev, spec, underlay_qpn);
3051
018a94ee
MB		 3052 if (dev->rep) {
3053 void *misc;
3054
3055 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3056 misc_parameters);
3057 MLX5_SET(fte_match_set_misc, misc, source_port,
3058 dev->rep->vport);
3059 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3060 misc_parameters);
3061 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3062 }
3063
466fa6d2 3064 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
802c2125
AY		 3065
3066 if (is_egress &&
3067 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3068 err = -EINVAL;
3069 goto free;
3070 }
3071
075572d4 3072 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
a22ed86c
SS		 3073 rule_dst = NULL;
3074 dest_num = 0;
3075 } else {
802c2125
AY		 3076 if (is_egress)
3077 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3078 else
3079 flow_act.action |=
3080 dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
3081 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
a22ed86c 3082 }
2ac693f9 3083
a9db0ecf 3084 if (flow_act.has_flow_tag &&
2ac693f9
MR		 3085 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3086 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3087 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
075572d4 3088 flow_act.flow_tag, flow_attr->type);
2ac693f9
MR		 3089 err = -EINVAL;
3090 goto free;
3091 }
74491de9 3092 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 3093 &flow_act,
a22ed86c 3094 rule_dst, dest_num);
038d2ef8
MG		 3095
3096 if (IS_ERR(handler->rule)) {
3097 err = PTR_ERR(handler->rule);
3098 goto free;
3099 }
3100
d9d4980a 3101 ft_prio->refcount++;
5497adc6 3102 handler->prio = ft_prio;
038d2ef8
MG		 3103
3104 ft_prio->flow_table = ft;
3105free:
3106 if (err)
3107 kfree(handler);
c5bb1730 3108 kvfree(spec);
038d2ef8
MG		 3109 return err ? ERR_PTR(err) : handler;
3110}
3111
a550ddfc
YH		 3112static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3113 struct mlx5_ib_flow_prio *ft_prio,
3114 const struct ib_flow_attr *flow_attr,
3115 struct mlx5_flow_destination *dst)
3116{
3117 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0);
3118}
3119
35d19011
MG		 3120static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3121 struct mlx5_ib_flow_prio *ft_prio,
3122 struct ib_flow_attr *flow_attr,
3123 struct mlx5_flow_destination *dst)
3124{
3125 struct mlx5_ib_flow_handler *handler_dst = NULL;
3126 struct mlx5_ib_flow_handler *handler = NULL;
3127
3128 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3129 if (!IS_ERR(handler)) {
3130 handler_dst = create_flow_rule(dev, ft_prio,
3131 flow_attr, dst);
3132 if (IS_ERR(handler_dst)) {
74491de9 3133 mlx5_del_flow_rules(handler->rule);
d9d4980a 3134 ft_prio->refcount--;
35d19011
MG		 3135 kfree(handler);
3136 handler = handler_dst;
3137 } else {
3138 list_add(&handler_dst->list, &handler->list);
3139 }
3140 }
3141
3142 return handler;
3143}
038d2ef8
MG		 3144enum {
3145 LEFTOVERS_MC,
3146 LEFTOVERS_UC,
3147};
3148
3149static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3150 struct mlx5_ib_flow_prio *ft_prio,
3151 struct ib_flow_attr *flow_attr,
3152 struct mlx5_flow_destination *dst)
3153{
3154 struct mlx5_ib_flow_handler *handler_ucast = NULL;
3155 struct mlx5_ib_flow_handler *handler = NULL;
3156
3157 static struct {
3158 struct ib_flow_attr flow_attr;
3159 struct ib_flow_spec_eth eth_flow;
3160 } leftovers_specs[] = {
3161 [LEFTOVERS_MC] = {
3162 .flow_attr = {
3163 .num_of_specs = 1,
3164 .size = sizeof(leftovers_specs[0])
3165 },
3166 .eth_flow = {
3167 .type = IB_FLOW_SPEC_ETH,
3168 .size = sizeof(struct ib_flow_spec_eth),
3169 .mask = {.dst_mac = {0x1} },
3170 .val = {.dst_mac = {0x1} }
3171 }
3172 },
3173 [LEFTOVERS_UC] = {
3174 .flow_attr = {
3175 .num_of_specs = 1,
3176 .size = sizeof(leftovers_specs[0])
3177 },
3178 .eth_flow = {
3179 .type = IB_FLOW_SPEC_ETH,
3180 .size = sizeof(struct ib_flow_spec_eth),
3181 .mask = {.dst_mac = {0x1} },
3182 .val = {.dst_mac = {} }
3183 }
3184 }
3185 };
3186
3187 handler = create_flow_rule(dev, ft_prio,
3188 &leftovers_specs[LEFTOVERS_MC].flow_attr,
3189 dst);
3190 if (!IS_ERR(handler) &&
3191 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3192 handler_ucast = create_flow_rule(dev, ft_prio,
3193 &leftovers_specs[LEFTOVERS_UC].flow_attr,
3194 dst);
3195 if (IS_ERR(handler_ucast)) {
74491de9 3196 mlx5_del_flow_rules(handler->rule);
d9d4980a 3197 ft_prio->refcount--;
038d2ef8
MG		 3198 kfree(handler);
3199 handler = handler_ucast;
3200 } else {
3201 list_add(&handler_ucast->list, &handler->list);
3202 }
3203 }
3204
3205 return handler;
3206}
3207
cc0e5d42
MG		 3208static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3209 struct mlx5_ib_flow_prio *ft_rx,
3210 struct mlx5_ib_flow_prio *ft_tx,
3211 struct mlx5_flow_destination *dst)
3212{
3213 struct mlx5_ib_flow_handler *handler_rx;
3214 struct mlx5_ib_flow_handler *handler_tx;
3215 int err;
3216 static const struct ib_flow_attr flow_attr = {
3217 .num_of_specs = 0,
3218 .size = sizeof(flow_attr)
3219 };
3220
3221 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3222 if (IS_ERR(handler_rx)) {
3223 err = PTR_ERR(handler_rx);
3224 goto err;
3225 }
3226
3227 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3228 if (IS_ERR(handler_tx)) {
3229 err = PTR_ERR(handler_tx);
3230 goto err_tx;
3231 }
3232
3233 list_add(&handler_tx->list, &handler_rx->list);
3234
3235 return handler_rx;
3236
3237err_tx:
74491de9 3238 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 3239 ft_rx->refcount--;
3240 kfree(handler_rx);
3241err:
3242 return ERR_PTR(err);
3243}
3244
038d2ef8
MG		 3245static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3246 struct ib_flow_attr *flow_attr,
3247 int domain)
3248{
3249 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 3250 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 3251 struct mlx5_ib_flow_handler *handler = NULL;
3252 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 3253 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8 3254 struct mlx5_ib_flow_prio *ft_prio;
802c2125 3255 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
038d2ef8 3256 int err;
a550ddfc 3257 int underlay_qpn;
038d2ef8
MG		 3258
3259 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
dac388ef 3260 return ERR_PTR(-ENOMEM);
038d2ef8
MG		 3261
3262 if (domain != IB_FLOW_DOMAIN_USER ||
508562d6 3263 flow_attr->port > dev->num_ports ||
802c2125
AY		 3264 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
3265 IB_FLOW_ATTR_FLAGS_EGRESS)))
3266 return ERR_PTR(-EINVAL);
3267
3268 if (is_egress &&
3269 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3270 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT))
038d2ef8
MG		 3271 return ERR_PTR(-EINVAL);
3272
3273 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3274 if (!dst)
3275 return ERR_PTR(-ENOMEM);
3276
9a4ca38d 3277 mutex_lock(&dev->flow_db->lock);
038d2ef8 3278
802c2125
AY		 3279 ft_prio = get_flow_table(dev, flow_attr,
3280 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
038d2ef8
MG		 3281 if (IS_ERR(ft_prio)) {
3282 err = PTR_ERR(ft_prio);
3283 goto unlock;
3284 }
cc0e5d42
MG		 3285 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3286 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3287 if (IS_ERR(ft_prio_tx)) {
3288 err = PTR_ERR(ft_prio_tx);
3289 ft_prio_tx = NULL;
3290 goto destroy_ft;
3291 }
3292 }
038d2ef8 3293
802c2125
AY		 3294 if (is_egress) {
3295 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3296 } else {
3297 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3298 if (mqp->flags & MLX5_IB_QP_RSS)
3299 dst->tir_num = mqp->rss_qp.tirn;
3300 else
3301 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3302 }
038d2ef8
MG		 3303
3304 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 3305 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3306 handler = create_dont_trap_rule(dev, ft_prio,
3307 flow_attr, dst);
3308 } else {
a550ddfc
YH		 3309 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3310 mqp->underlay_qpn : 0;
3311 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3312 dst, underlay_qpn);
35d19011 3313 }
038d2ef8
MG		 3314 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3315 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3316 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3317 dst);
cc0e5d42
MG		 3318 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3319 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 3320 } else {
3321 err = -EINVAL;
3322 goto destroy_ft;
3323 }
3324
3325 if (IS_ERR(handler)) {
3326 err = PTR_ERR(handler);
3327 handler = NULL;
3328 goto destroy_ft;
3329 }
3330
9a4ca38d 3331 mutex_unlock(&dev->flow_db->lock);
038d2ef8
MG		 3332 kfree(dst);
3333
3334 return &handler->ibflow;
3335
3336destroy_ft:
3337 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 3338 if (ft_prio_tx)
3339 put_flow_table(dev, ft_prio_tx, false);
038d2ef8 3340unlock:
9a4ca38d 3341 mutex_unlock(&dev->flow_db->lock);
038d2ef8
MG		 3342 kfree(dst);
3343 kfree(handler);
3344 return ERR_PTR(err);
3345}
3346
c6475a0b
AY		 3347static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
3348{
3349 u32 flags = 0;
3350
3351 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
3352 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
3353
3354 return flags;
3355}
3356
3357#define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
3358static struct ib_flow_action *
3359mlx5_ib_create_flow_action_esp(struct ib_device *device,
3360 const struct ib_flow_action_attrs_esp *attr,
3361 struct uverbs_attr_bundle *attrs)
3362{
3363 struct mlx5_ib_dev *mdev = to_mdev(device);
3364 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
3365 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
3366 struct mlx5_ib_flow_action *action;
3367 u64 action_flags;
3368 u64 flags;
3369 int err = 0;
3370
3371 if (IS_UVERBS_COPY_ERR(uverbs_copy_from(&action_flags, attrs,
3372 MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS)))
3373 return ERR_PTR(-EFAULT);
3374
3375 if (action_flags >= (MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1))
3376 return ERR_PTR(-EOPNOTSUPP);
3377
3378 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
3379
3380 /* We current only support a subset of the standard features. Only a
3381 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
3382 * (with overlap). Full offload mode isn't supported.
3383 */
3384 if (!attr->keymat || attr->replay || attr->encap ||
3385 attr->spi || attr->seq || attr->tfc_pad ||
3386 attr->hard_limit_pkts ||
3387 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3388 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
3389 return ERR_PTR(-EOPNOTSUPP);
3390
3391 if (attr->keymat->protocol !=
3392 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
3393 return ERR_PTR(-EOPNOTSUPP);
3394
3395 aes_gcm = &attr->keymat->keymat.aes_gcm;
3396
3397 if (aes_gcm->icv_len != 16 ||
3398 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
3399 return ERR_PTR(-EOPNOTSUPP);
3400
3401 action = kmalloc(sizeof(*action), GFP_KERNEL);
3402 if (!action)
3403 return ERR_PTR(-ENOMEM);
3404
3405 action->esp_aes_gcm.ib_flags = attr->flags;
3406 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
3407 sizeof(accel_attrs.keymat.aes_gcm.aes_key));
3408 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
3409 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
3410 sizeof(accel_attrs.keymat.aes_gcm.salt));
3411 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
3412 sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
3413 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
3414 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
3415 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
3416
3417 accel_attrs.esn = attr->esn;
3418 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
3419 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
3420 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3421 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3422
3423 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
3424 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
3425
3426 action->esp_aes_gcm.ctx =
3427 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
3428 if (IS_ERR(action->esp_aes_gcm.ctx)) {
3429 err = PTR_ERR(action->esp_aes_gcm.ctx);
3430 goto err_parse;
3431 }
3432
3433 action->esp_aes_gcm.ib_flags = attr->flags;
3434
3435 return &action->ib_action;
3436
3437err_parse:
3438 kfree(action);
3439 return ERR_PTR(err);
3440}
3441
349705c1
MB		 3442static int
3443mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
3444 const struct ib_flow_action_attrs_esp *attr,
3445 struct uverbs_attr_bundle *attrs)
3446{
3447 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3448 struct mlx5_accel_esp_xfrm_attrs accel_attrs;
3449 int err = 0;
3450
3451 if (attr->keymat || attr->replay || attr->encap ||
3452 attr->spi || attr->seq || attr->tfc_pad ||
3453 attr->hard_limit_pkts ||
3454 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3455 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
3456 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
3457 return -EOPNOTSUPP;
3458
3459 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
3460 * be modified.
3461 */
3462 if (!(maction->esp_aes_gcm.ib_flags &
3463 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
3464 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3465 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
3466 return -EINVAL;
3467
3468 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
3469 sizeof(accel_attrs));
3470
3471 accel_attrs.esn = attr->esn;
3472 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3473 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3474 else
3475 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3476
3477 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
3478 &accel_attrs);
3479 if (err)
3480 return err;
3481
3482 maction->esp_aes_gcm.ib_flags &=
3483 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
3484 maction->esp_aes_gcm.ib_flags |=
3485 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
3486
3487 return 0;
3488}
3489
c6475a0b
AY		 3490static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
3491{
3492 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3493
3494 switch (action->type) {
3495 case IB_FLOW_ACTION_ESP:
3496 /*
3497 * We only support aes_gcm by now, so we implicitly know this is
3498 * the underline crypto.
3499 */
3500 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
3501 break;
3502 default:
3503 WARN_ON(true);
3504 break;
3505 }
3506
3507 kfree(maction);
3508 return 0;
3509}
3510
e126ba97
EC		 3511static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3512{
3513 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 3514 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97
EC		 3515 int err;
3516
81e30880
YH		 3517 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
3518 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
3519 return -EOPNOTSUPP;
3520 }
3521
9603b61d 3522 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 3523 if (err)
3524 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
3525 ibqp->qp_num, gid->raw);
3526
3527 return err;
3528}
3529
3530static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3531{
3532 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3533 int err;
3534
9603b61d 3535 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 3536 if (err)
3537 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
3538 ibqp->qp_num, gid->raw);
3539
3540 return err;
3541}
3542
3543static int init_node_data(struct mlx5_ib_dev *dev)
3544{
1b5daf11 3545 int err;
e126ba97 3546
1b5daf11 3547 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 3548 if (err)
1b5daf11 3549 return err;
e126ba97 3550
1b5daf11 3551 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 3552
1b5daf11 3553 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 3554}
3555
3556static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
3557 char *buf)
3558{
3559 struct mlx5_ib_dev *dev =
3560 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3561
9603b61d 3562 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 3563}
3564
3565static ssize_t show_reg_pages(struct device *device,
3566 struct device_attribute *attr, char *buf)
3567{
3568 struct mlx5_ib_dev *dev =
3569 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3570
6aec21f6 3571 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 3572}
3573
3574static ssize_t show_hca(struct device *device, struct device_attribute *attr,
3575 char *buf)
3576{
3577 struct mlx5_ib_dev *dev =
3578 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 3579 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 3580}
3581
e126ba97
EC		 3582static ssize_t show_rev(struct device *device, struct device_attribute *attr,
3583 char *buf)
3584{
3585 struct mlx5_ib_dev *dev =
3586 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 3587 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 3588}
3589
3590static ssize_t show_board(struct device *device, struct device_attribute *attr,
3591 char *buf)
3592{
3593 struct mlx5_ib_dev *dev =
3594 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3595 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 3596 dev->mdev->board_id);
e126ba97
EC		 3597}
3598
3599static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
e126ba97
EC		 3600static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
3601static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
3602static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
3603static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
3604
3605static struct device_attribute *mlx5_class_attributes[] = {
3606 &dev_attr_hw_rev,
e126ba97
EC		 3607 &dev_attr_hca_type,
3608 &dev_attr_board_id,
3609 &dev_attr_fw_pages,
3610 &dev_attr_reg_pages,
3611};
3612
7722f47e
HE		 3613static void pkey_change_handler(struct work_struct *work)
3614{
3615 struct mlx5_ib_port_resources *ports =
3616 container_of(work, struct mlx5_ib_port_resources,
3617 pkey_change_work);
3618
3619 mutex_lock(&ports->devr->mutex);
3620 mlx5_ib_gsi_pkey_change(ports->gsi);
3621 mutex_unlock(&ports->devr->mutex);
3622}
3623
89ea94a7
MG		 3624static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
3625{
3626 struct mlx5_ib_qp *mqp;
3627 struct mlx5_ib_cq *send_mcq, *recv_mcq;
3628 struct mlx5_core_cq *mcq;
3629 struct list_head cq_armed_list;
3630 unsigned long flags_qp;
3631 unsigned long flags_cq;
3632 unsigned long flags;
3633
3634 INIT_LIST_HEAD(&cq_armed_list);
3635
3636 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3637 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
3638 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
3639 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
3640 if (mqp->sq.tail != mqp->sq.head) {
3641 send_mcq = to_mcq(mqp->ibqp.send_cq);
3642 spin_lock_irqsave(&send_mcq->lock, flags_cq);
3643 if (send_mcq->mcq.comp &&
3644 mqp->ibqp.send_cq->comp_handler) {
3645 if (!send_mcq->mcq.reset_notify_added) {
3646 send_mcq->mcq.reset_notify_added = 1;
3647 list_add_tail(&send_mcq->mcq.reset_notify,
3648 &cq_armed_list);
3649 }
3650 }
3651 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
3652 }
3653 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
3654 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
3655 /* no handling is needed for SRQ */
3656 if (!mqp->ibqp.srq) {
3657 if (mqp->rq.tail != mqp->rq.head) {
3658 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
3659 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
3660 if (recv_mcq->mcq.comp &&
3661 mqp->ibqp.recv_cq->comp_handler) {
3662 if (!recv_mcq->mcq.reset_notify_added) {
3663 recv_mcq->mcq.reset_notify_added = 1;
3664 list_add_tail(&recv_mcq->mcq.reset_notify,
3665 &cq_armed_list);
3666 }
3667 }
3668 spin_unlock_irqrestore(&recv_mcq->lock,
3669 flags_cq);
3670 }
3671 }
3672 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3673 }
3674 /*At that point all inflight post send were put to be executed as of we
3675 * lock/unlock above locks Now need to arm all involved CQs.
3676 */
3677 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
3678 mcq->comp(mcq);
3679 }
3680 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3681}
3682
03404e8a
MG		 3683static void delay_drop_handler(struct work_struct *work)
3684{
3685 int err;
3686 struct mlx5_ib_delay_drop *delay_drop =
3687 container_of(work, struct mlx5_ib_delay_drop,
3688 delay_drop_work);
3689
fe248c3a
MG		 3690 atomic_inc(&delay_drop->events_cnt);
3691
03404e8a
MG		 3692 mutex_lock(&delay_drop->lock);
3693 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
3694 delay_drop->timeout);
3695 if (err) {
3696 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
3697 delay_drop->timeout);
3698 delay_drop->activate = false;
3699 }
3700 mutex_unlock(&delay_drop->lock);
3701}
3702
d69a24e0 3703static void mlx5_ib_handle_event(struct work_struct *_work)
e126ba97 3704{
d69a24e0
DJ		 3705 struct mlx5_ib_event_work *work =
3706 container_of(_work, struct mlx5_ib_event_work, work);
3707 struct mlx5_ib_dev *ibdev;
e126ba97 3708 struct ib_event ibev;
dbaaff2a 3709 bool fatal = false;
aba46213 3710 u8 port = (u8)work->param;
e126ba97 3711
d69a24e0
DJ		 3712 if (mlx5_core_is_mp_slave(work->dev)) {
3713 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context);
3714 if (!ibdev)
3715 goto out;
3716 } else {
3717 ibdev = work->context;
3718 }
3719
3720 switch (work->event) {
e126ba97 3721 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 3722 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 3723 mlx5_ib_handle_internal_error(ibdev);
dbaaff2a 3724 fatal = true;
e126ba97
EC		 3725 break;
3726
3727 case MLX5_DEV_EVENT_PORT_UP:
e126ba97 3728 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 3729 case MLX5_DEV_EVENT_PORT_INITIALIZED:
5ec8c83e
AH		 3730 /* In RoCE, port up/down events are handled in
3731 * mlx5_netdev_event().
3732 */
3733 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
3734 IB_LINK_LAYER_ETHERNET)
d69a24e0 3735 goto out;
5ec8c83e 3736
d69a24e0 3737 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ?
5ec8c83e 3738 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
e126ba97
EC		 3739 break;
3740
e126ba97
EC		 3741 case MLX5_DEV_EVENT_LID_CHANGE:
3742 ibev.event = IB_EVENT_LID_CHANGE;
e126ba97
EC		 3743 break;
3744
3745 case MLX5_DEV_EVENT_PKEY_CHANGE:
3746 ibev.event = IB_EVENT_PKEY_CHANGE;
7722f47e 3747 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 3748 break;
3749
3750 case MLX5_DEV_EVENT_GUID_CHANGE:
3751 ibev.event = IB_EVENT_GID_CHANGE;
e126ba97
EC		 3752 break;
3753
3754 case MLX5_DEV_EVENT_CLIENT_REREG:
3755 ibev.event = IB_EVENT_CLIENT_REREGISTER;
e126ba97 3756 break;
03404e8a
MG		 3757 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
3758 schedule_work(&ibdev->delay_drop.delay_drop_work);
3759 goto out;
bdc37924 3760 default:
03404e8a 3761 goto out;
e126ba97
EC		 3762 }
3763
3764 ibev.device = &ibdev->ib_dev;
3765 ibev.element.port_num = port;
3766
aba46213 3767 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) {
a0c84c32 3768 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
03404e8a 3769 goto out;
a0c84c32
EC		 3770 }
3771
e126ba97
EC		 3772 if (ibdev->ib_active)
3773 ib_dispatch_event(&ibev);
dbaaff2a
EC		 3774
3775 if (fatal)
3776 ibdev->ib_active = false;
03404e8a 3777out:
d69a24e0
DJ		 3778 kfree(work);
3779}
3780
3781static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
3782 enum mlx5_dev_event event, unsigned long param)
3783{
3784 struct mlx5_ib_event_work *work;
3785
3786 work = kmalloc(sizeof(*work), GFP_ATOMIC);
10bea9c8 3787 if (!work)
d69a24e0 3788 return;
d69a24e0 3789
10bea9c8
LR		 3790 INIT_WORK(&work->work, mlx5_ib_handle_event);
3791 work->dev = dev;
3792 work->param = param;
3793 work->context = context;
3794 work->event = event;
3795
3796 queue_work(mlx5_ib_event_wq, &work->work);
e126ba97
EC		 3797}
3798
c43f1112
MG		 3799static int set_has_smi_cap(struct mlx5_ib_dev *dev)
3800{
3801 struct mlx5_hca_vport_context vport_ctx;
3802 int err;
3803 int port;
3804
508562d6 3805 for (port = 1; port <= dev->num_ports; port++) {
c43f1112
MG		 3806 dev->mdev->port_caps[port - 1].has_smi = false;
3807 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
3808 MLX5_CAP_PORT_TYPE_IB) {
3809 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
3810 err = mlx5_query_hca_vport_context(dev->mdev, 0,
3811 port, 0,
3812 &vport_ctx);
3813 if (err) {
3814 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
3815 port, err);
3816 return err;
3817 }
3818 dev->mdev->port_caps[port - 1].has_smi =
3819 vport_ctx.has_smi;
3820 } else {
3821 dev->mdev->port_caps[port - 1].has_smi = true;
3822 }
3823 }
3824 }
3825 return 0;
3826}
3827
e126ba97
EC		 3828static void get_ext_port_caps(struct mlx5_ib_dev *dev)
3829{
3830 int port;
3831
508562d6 3832 for (port = 1; port <= dev->num_ports; port++)
e126ba97
EC		 3833 mlx5_query_ext_port_caps(dev, port);
3834}
3835
32f69e4b 3836static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
e126ba97
EC		 3837{
3838 struct ib_device_attr *dprops = NULL;
3839 struct ib_port_attr *pprops = NULL;
f614fc15 3840 int err = -ENOMEM;
2528e33e 3841 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 3842
3843 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
3844 if (!pprops)
3845 goto out;
3846
3847 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
3848 if (!dprops)
3849 goto out;
3850
c43f1112
MG		 3851 err = set_has_smi_cap(dev);
3852 if (err)
3853 goto out;
3854
2528e33e 3855 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 3856 if (err) {
3857 mlx5_ib_warn(dev, "query_device failed %d\n", err);
3858 goto out;
3859 }
3860
32f69e4b
DJ		 3861 memset(pprops, 0, sizeof(*pprops));
3862 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
3863 if (err) {
3864 mlx5_ib_warn(dev, "query_port %d failed %d\n",
3865 port, err);
3866 goto out;
e126ba97
EC		 3867 }
3868
32f69e4b
DJ		 3869 dev->mdev->port_caps[port - 1].pkey_table_len =
3870 dprops->max_pkeys;
3871 dev->mdev->port_caps[port - 1].gid_table_len =
3872 pprops->gid_tbl_len;
3873 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
3874 port, dprops->max_pkeys, pprops->gid_tbl_len);
3875
e126ba97
EC		 3876out:
3877 kfree(pprops);
3878 kfree(dprops);
3879
3880 return err;
3881}
3882
3883static void destroy_umrc_res(struct mlx5_ib_dev *dev)
3884{
3885 int err;
3886
3887 err = mlx5_mr_cache_cleanup(dev);
3888 if (err)
3889 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
3890
32927e28
MB		 3891 if (dev->umrc.qp)
3892 mlx5_ib_destroy_qp(dev->umrc.qp);
3893 if (dev->umrc.cq)
3894 ib_free_cq(dev->umrc.cq);
3895 if (dev->umrc.pd)
3896 ib_dealloc_pd(dev->umrc.pd);
e126ba97
EC		 3897}
3898
3899enum {
3900 MAX_UMR_WR = 128,
3901};
3902
3903static int create_umr_res(struct mlx5_ib_dev *dev)
3904{
3905 struct ib_qp_init_attr *init_attr = NULL;
3906 struct ib_qp_attr *attr = NULL;
3907 struct ib_pd *pd;
3908 struct ib_cq *cq;
3909 struct ib_qp *qp;
e126ba97
EC		 3910 int ret;
3911
3912 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
3913 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
3914 if (!attr || !init_attr) {
3915 ret = -ENOMEM;
3916 goto error_0;
3917 }
3918
ed082d36 3919 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 3920 if (IS_ERR(pd)) {
3921 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
3922 ret = PTR_ERR(pd);
3923 goto error_0;
3924 }
3925
add08d76 3926 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 3927 if (IS_ERR(cq)) {
3928 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
3929 ret = PTR_ERR(cq);
3930 goto error_2;
3931 }
e126ba97
EC		 3932
3933 init_attr->send_cq = cq;
3934 init_attr->recv_cq = cq;
3935 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
3936 init_attr->cap.max_send_wr = MAX_UMR_WR;
3937 init_attr->cap.max_send_sge = 1;
3938 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
3939 init_attr->port_num = 1;
3940 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
3941 if (IS_ERR(qp)) {
3942 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
3943 ret = PTR_ERR(qp);
3944 goto error_3;
3945 }
3946 qp->device = &dev->ib_dev;
3947 qp->real_qp = qp;
3948 qp->uobject = NULL;
3949 qp->qp_type = MLX5_IB_QPT_REG_UMR;
31fde034
MD		 3950 qp->send_cq = init_attr->send_cq;
3951 qp->recv_cq = init_attr->recv_cq;
e126ba97
EC		 3952
3953 attr->qp_state = IB_QPS_INIT;
3954 attr->port_num = 1;
3955 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
3956 IB_QP_PORT, NULL);
3957 if (ret) {
3958 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
3959 goto error_4;
3960 }
3961
3962 memset(attr, 0, sizeof(*attr));
3963 attr->qp_state = IB_QPS_RTR;
3964 attr->path_mtu = IB_MTU_256;
3965
3966 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3967 if (ret) {
3968 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
3969 goto error_4;
3970 }
3971
3972 memset(attr, 0, sizeof(*attr));
3973 attr->qp_state = IB_QPS_RTS;
3974 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3975 if (ret) {
3976 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
3977 goto error_4;
3978 }
3979
3980 dev->umrc.qp = qp;
3981 dev->umrc.cq = cq;
e126ba97
EC		 3982 dev->umrc.pd = pd;
3983
3984 sema_init(&dev->umrc.sem, MAX_UMR_WR);
3985 ret = mlx5_mr_cache_init(dev);
3986 if (ret) {
3987 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
3988 goto error_4;
3989 }
3990
3991 kfree(attr);
3992 kfree(init_attr);
3993
3994 return 0;
3995
3996error_4:
3997 mlx5_ib_destroy_qp(qp);
32927e28 3998 dev->umrc.qp = NULL;
e126ba97
EC		 3999
4000error_3:
add08d76 4001 ib_free_cq(cq);
32927e28 4002 dev->umrc.cq = NULL;
e126ba97
EC		 4003
4004error_2:
e126ba97 4005 ib_dealloc_pd(pd);
32927e28 4006 dev->umrc.pd = NULL;
e126ba97
EC		 4007
4008error_0:
4009 kfree(attr);
4010 kfree(init_attr);
4011 return ret;
4012}
4013
6e8484c5
MG		 4014static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4015{
4016 switch (umr_fence_cap) {
4017 case MLX5_CAP_UMR_FENCE_NONE:
4018 return MLX5_FENCE_MODE_NONE;
4019 case MLX5_CAP_UMR_FENCE_SMALL:
4020 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4021 default:
4022 return MLX5_FENCE_MODE_STRONG_ORDERING;
4023 }
4024}
4025
e126ba97
EC		 4026static int create_dev_resources(struct mlx5_ib_resources *devr)
4027{
4028 struct ib_srq_init_attr attr;
4029 struct mlx5_ib_dev *dev;
bcf4c1ea 4030 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 4031 int port;
e126ba97
EC		 4032 int ret = 0;
4033
4034 dev = container_of(devr, struct mlx5_ib_dev, devr);
4035
d16e91da
HE		 4036 mutex_init(&devr->mutex);
4037
e126ba97
EC		 4038 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
4039 if (IS_ERR(devr->p0)) {
4040 ret = PTR_ERR(devr->p0);
4041 goto error0;
4042 }
4043 devr->p0->device = &dev->ib_dev;
4044 devr->p0->uobject = NULL;
4045 atomic_set(&devr->p0->usecnt, 0);
4046
bcf4c1ea 4047 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 4048 if (IS_ERR(devr->c0)) {
4049 ret = PTR_ERR(devr->c0);
4050 goto error1;
4051 }
4052 devr->c0->device = &dev->ib_dev;
4053 devr->c0->uobject = NULL;
4054 devr->c0->comp_handler = NULL;
4055 devr->c0->event_handler = NULL;
4056 devr->c0->cq_context = NULL;
4057 atomic_set(&devr->c0->usecnt, 0);
4058
4059 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4060 if (IS_ERR(devr->x0)) {
4061 ret = PTR_ERR(devr->x0);
4062 goto error2;
4063 }
4064 devr->x0->device = &dev->ib_dev;
4065 devr->x0->inode = NULL;
4066 atomic_set(&devr->x0->usecnt, 0);
4067 mutex_init(&devr->x0->tgt_qp_mutex);
4068 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4069
4070 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4071 if (IS_ERR(devr->x1)) {
4072 ret = PTR_ERR(devr->x1);
4073 goto error3;
4074 }
4075 devr->x1->device = &dev->ib_dev;
4076 devr->x1->inode = NULL;
4077 atomic_set(&devr->x1->usecnt, 0);
4078 mutex_init(&devr->x1->tgt_qp_mutex);
4079 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4080
4081 memset(&attr, 0, sizeof(attr));
4082 attr.attr.max_sge = 1;
4083 attr.attr.max_wr = 1;
4084 attr.srq_type = IB_SRQT_XRC;
1a56ff6d 4085 attr.ext.cq = devr->c0;
e126ba97
EC		 4086 attr.ext.xrc.xrcd = devr->x0;
4087
4088 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4089 if (IS_ERR(devr->s0)) {
4090 ret = PTR_ERR(devr->s0);
4091 goto error4;
4092 }
4093 devr->s0->device = &dev->ib_dev;
4094 devr->s0->pd = devr->p0;
4095 devr->s0->uobject = NULL;
4096 devr->s0->event_handler = NULL;
4097 devr->s0->srq_context = NULL;
4098 devr->s0->srq_type = IB_SRQT_XRC;
4099 devr->s0->ext.xrc.xrcd = devr->x0;
1a56ff6d 4100 devr->s0->ext.cq = devr->c0;
e126ba97 4101 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1a56ff6d 4102 atomic_inc(&devr->s0->ext.cq->usecnt);
e126ba97
EC		 4103 atomic_inc(&devr->p0->usecnt);
4104 atomic_set(&devr->s0->usecnt, 0);
4105
4aa17b28
HA		 4106 memset(&attr, 0, sizeof(attr));
4107 attr.attr.max_sge = 1;
4108 attr.attr.max_wr = 1;
4109 attr.srq_type = IB_SRQT_BASIC;
4110 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4111 if (IS_ERR(devr->s1)) {
4112 ret = PTR_ERR(devr->s1);
4113 goto error5;
4114 }
4115 devr->s1->device = &dev->ib_dev;
4116 devr->s1->pd = devr->p0;
4117 devr->s1->uobject = NULL;
4118 devr->s1->event_handler = NULL;
4119 devr->s1->srq_context = NULL;
4120 devr->s1->srq_type = IB_SRQT_BASIC;
1a56ff6d 4121 devr->s1->ext.cq = devr->c0;
4aa17b28 4122 atomic_inc(&devr->p0->usecnt);
1a56ff6d 4123 atomic_set(&devr->s1->usecnt, 0);
4aa17b28 4124
7722f47e
HE		 4125 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
4126 INIT_WORK(&devr->ports[port].pkey_change_work,
4127 pkey_change_handler);
4128 devr->ports[port].devr = devr;
4129 }
4130
e126ba97
EC		 4131 return 0;
4132
4aa17b28
HA		 4133error5:
4134 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 4135error4:
4136 mlx5_ib_dealloc_xrcd(devr->x1);
4137error3:
4138 mlx5_ib_dealloc_xrcd(devr->x0);
4139error2:
4140 mlx5_ib_destroy_cq(devr->c0);
4141error1:
4142 mlx5_ib_dealloc_pd(devr->p0);
4143error0:
4144 return ret;
4145}
4146
4147static void destroy_dev_resources(struct mlx5_ib_resources *devr)
4148{
7722f47e
HE		 4149 struct mlx5_ib_dev *dev =
4150 container_of(devr, struct mlx5_ib_dev, devr);
4151 int port;
4152
4aa17b28 4153 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 4154 mlx5_ib_destroy_srq(devr->s0);
4155 mlx5_ib_dealloc_xrcd(devr->x0);
4156 mlx5_ib_dealloc_xrcd(devr->x1);
4157 mlx5_ib_destroy_cq(devr->c0);
4158 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 4159
4160 /* Make sure no change P_Key work items are still executing */
4161 for (port = 0; port < dev->num_ports; ++port)
4162 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 4163}
4164
e53505a8
AS		 4165static u32 get_core_cap_flags(struct ib_device *ibdev)
4166{
4167 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4168 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
4169 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
4170 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
85c7c014 4171 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
e53505a8
AS		 4172 u32 ret = 0;
4173
4174 if (ll == IB_LINK_LAYER_INFINIBAND)
4175 return RDMA_CORE_PORT_IBA_IB;
4176
85c7c014
DJ		 4177 if (raw_support)
4178 ret = RDMA_CORE_PORT_RAW_PACKET;
72cd5717 4179
e53505a8 4180 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 4181 return ret;
e53505a8
AS		 4182
4183 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 4184 return ret;
e53505a8
AS		 4185
4186 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
4187 ret |= RDMA_CORE_PORT_IBA_ROCE;
4188
4189 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
4190 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
4191
4192 return ret;
4193}
4194
7738613e
IW		 4195static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
4196 struct ib_port_immutable *immutable)
4197{
4198 struct ib_port_attr attr;
ca5b91d6
OG		 4199 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4200 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
7738613e
IW		 4201 int err;
4202
c4550c63
OG		 4203 immutable->core_cap_flags = get_core_cap_flags(ibdev);
4204
4205 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 4206 if (err)
4207 return err;
4208
4209 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4210 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 4211 immutable->core_cap_flags = get_core_cap_flags(ibdev);
ca5b91d6
OG		 4212 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
4213 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 4214
4215 return 0;
4216}
4217
8e6efa3a
MB		 4218static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
4219 struct ib_port_immutable *immutable)
4220{
4221 struct ib_port_attr attr;
4222 int err;
4223
4224 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4225
4226 err = ib_query_port(ibdev, port_num, &attr);
4227 if (err)
4228 return err;
4229
4230 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4231 immutable->gid_tbl_len = attr.gid_tbl_len;
4232 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4233
4234 return 0;
4235}
4236
9abb0d1b 4237static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 4238{
4239 struct mlx5_ib_dev *dev =
4240 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 4241 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
4242 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
4243 fw_rev_sub(dev->mdev));
c7342823
IW		 4244}
4245
45f95acd 4246static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 4247{
4248 struct mlx5_core_dev *mdev = dev->mdev;
4249 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
4250 MLX5_FLOW_NAMESPACE_LAG);
4251 struct mlx5_flow_table *ft;
4252 int err;
4253
4254 if (!ns || !mlx5_lag_is_active(mdev))
4255 return 0;
4256
4257 err = mlx5_cmd_create_vport_lag(mdev);
4258 if (err)
4259 return err;
4260
4261 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
4262 if (IS_ERR(ft)) {
4263 err = PTR_ERR(ft);
4264 goto err_destroy_vport_lag;
4265 }
4266
9a4ca38d 4267 dev->flow_db->lag_demux_ft = ft;
9ef9c640
AH		 4268 return 0;
4269
4270err_destroy_vport_lag:
4271 mlx5_cmd_destroy_vport_lag(mdev);
4272 return err;
4273}
4274
45f95acd 4275static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 4276{
4277 struct mlx5_core_dev *mdev = dev->mdev;
4278
9a4ca38d
MB		 4279 if (dev->flow_db->lag_demux_ft) {
4280 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
4281 dev->flow_db->lag_demux_ft = NULL;
9ef9c640
AH		 4282
4283 mlx5_cmd_destroy_vport_lag(mdev);
4284 }
4285}
4286
7fd8aefb 4287static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
d012f5d6
OG		 4288{
4289 int err;
4290
7fd8aefb
DJ		 4291 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
4292 err = register_netdevice_notifier(&dev->roce[port_num].nb);
d012f5d6 4293 if (err) {
7fd8aefb 4294 dev->roce[port_num].nb.notifier_call = NULL;
d012f5d6
OG		 4295 return err;
4296 }
4297
4298 return 0;
4299}
4300
7fd8aefb 4301static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5ec8c83e 4302{
7fd8aefb
DJ		 4303 if (dev->roce[port_num].nb.notifier_call) {
4304 unregister_netdevice_notifier(&dev->roce[port_num].nb);
4305 dev->roce[port_num].nb.notifier_call = NULL;
5ec8c83e
AH		 4306 }
4307}
4308
7fd8aefb 4309static int mlx5_enable_eth(struct mlx5_ib_dev *dev, u8 port_num)
fc24fc5e 4310{
e53505a8
AS		 4311 int err;
4312
ca5b91d6
OG		 4313 if (MLX5_CAP_GEN(dev->mdev, roce)) {
4314 err = mlx5_nic_vport_enable_roce(dev->mdev);
4315 if (err)
8e6efa3a 4316 return err;
ca5b91d6 4317 }
e53505a8 4318
45f95acd 4319 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 4320 if (err)
4321 goto err_disable_roce;
4322
e53505a8
AS		 4323 return 0;
4324
9ef9c640 4325err_disable_roce:
ca5b91d6
OG		 4326 if (MLX5_CAP_GEN(dev->mdev, roce))
4327 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 4328
e53505a8 4329 return err;
fc24fc5e
AS		 4330}
4331
45f95acd 4332static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 4333{
45f95acd 4334 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 4335 if (MLX5_CAP_GEN(dev->mdev, roce))
4336 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 4337}
4338
e1f24a79 4339struct mlx5_ib_counter {
7c16f477
KH		 4340 const char *name;
4341 size_t offset;
4342};
4343
4344#define INIT_Q_COUNTER(_name) \
4345 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
4346
e1f24a79 4347static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 4348 INIT_Q_COUNTER(rx_write_requests),
4349 INIT_Q_COUNTER(rx_read_requests),
4350 INIT_Q_COUNTER(rx_atomic_requests),
4351 INIT_Q_COUNTER(out_of_buffer),
4352};
4353
e1f24a79 4354static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 4355 INIT_Q_COUNTER(out_of_sequence),
4356};
4357
e1f24a79 4358static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 4359 INIT_Q_COUNTER(duplicate_request),
4360 INIT_Q_COUNTER(rnr_nak_retry_err),
4361 INIT_Q_COUNTER(packet_seq_err),
4362 INIT_Q_COUNTER(implied_nak_seq_err),
4363 INIT_Q_COUNTER(local_ack_timeout_err),
4364};
4365
e1f24a79
PP		 4366#define INIT_CONG_COUNTER(_name) \
4367 { .name = #_name, .offset = \
4368 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
4369
4370static const struct mlx5_ib_counter cong_cnts[] = {
4371 INIT_CONG_COUNTER(rp_cnp_ignored),
4372 INIT_CONG_COUNTER(rp_cnp_handled),
4373 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
4374 INIT_CONG_COUNTER(np_cnp_sent),
4375};
4376
58dcb60a
PP		 4377static const struct mlx5_ib_counter extended_err_cnts[] = {
4378 INIT_Q_COUNTER(resp_local_length_error),
4379 INIT_Q_COUNTER(resp_cqe_error),
4380 INIT_Q_COUNTER(req_cqe_error),
4381 INIT_Q_COUNTER(req_remote_invalid_request),
4382 INIT_Q_COUNTER(req_remote_access_errors),
4383 INIT_Q_COUNTER(resp_remote_access_errors),
4384 INIT_Q_COUNTER(resp_cqe_flush_error),
4385 INIT_Q_COUNTER(req_cqe_flush_error),
4386};
4387
e1f24a79 4388static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a 4389{
aac4492e 4390 int i;
0837e86a 4391
7c16f477 4392 for (i = 0; i < dev->num_ports; i++) {
aac4492e
DJ		 4393 if (dev->port[i].cnts.set_id)
4394 mlx5_core_dealloc_q_counter(dev->mdev,
4395 dev->port[i].cnts.set_id);
e1f24a79
PP		 4396 kfree(dev->port[i].cnts.names);
4397 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 4398 }
4399}
4400
e1f24a79
PP		 4401static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
4402 struct mlx5_ib_counters *cnts)
7c16f477
KH		 4403{
4404 u32 num_counters;
4405
4406 num_counters = ARRAY_SIZE(basic_q_cnts);
4407
4408 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
4409 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
4410
4411 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
4412 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 4413
4414 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
4415 num_counters += ARRAY_SIZE(extended_err_cnts);
4416
e1f24a79 4417 cnts->num_q_counters = num_counters;
7c16f477 4418
e1f24a79
PP		 4419 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4420 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
4421 num_counters += ARRAY_SIZE(cong_cnts);
4422 }
4423
4424 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
4425 if (!cnts->names)
7c16f477
KH		 4426 return -ENOMEM;
4427
e1f24a79
PP		 4428 cnts->offsets = kcalloc(num_counters,
4429 sizeof(cnts->offsets), GFP_KERNEL);
4430 if (!cnts->offsets)
7c16f477
KH		 4431 goto err_names;
4432
7c16f477
KH		 4433 return 0;
4434
4435err_names:
e1f24a79 4436 kfree(cnts->names);
aac4492e 4437 cnts->names = NULL;
7c16f477
KH		 4438 return -ENOMEM;
4439}
4440
e1f24a79
PP		 4441static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
4442 const char **names,
4443 size_t *offsets)
7c16f477
KH		 4444{
4445 int i;
4446 int j = 0;
4447
4448 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
4449 names[j] = basic_q_cnts[i].name;
4450 offsets[j] = basic_q_cnts[i].offset;
4451 }
4452
4453 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
4454 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
4455 names[j] = out_of_seq_q_cnts[i].name;
4456 offsets[j] = out_of_seq_q_cnts[i].offset;
4457 }
4458 }
4459
4460 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
4461 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
4462 names[j] = retrans_q_cnts[i].name;
4463 offsets[j] = retrans_q_cnts[i].offset;
4464 }
4465 }
e1f24a79 4466
58dcb60a
PP		 4467 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
4468 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
4469 names[j] = extended_err_cnts[i].name;
4470 offsets[j] = extended_err_cnts[i].offset;
4471 }
4472 }
4473
e1f24a79
PP		 4474 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4475 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
4476 names[j] = cong_cnts[i].name;
4477 offsets[j] = cong_cnts[i].offset;
4478 }
4479 }
0837e86a
MB		 4480}
4481
e1f24a79 4482static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a 4483{
aac4492e 4484 int err = 0;
0837e86a 4485 int i;
0837e86a
MB		 4486
4487 for (i = 0; i < dev->num_ports; i++) {
aac4492e
DJ		 4488 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
4489 if (err)
4490 goto err_alloc;
4491
4492 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
4493 dev->port[i].cnts.offsets);
7c16f477 4494
aac4492e
DJ		 4495 err = mlx5_core_alloc_q_counter(dev->mdev,
4496 &dev->port[i].cnts.set_id);
4497 if (err) {
0837e86a
MB		 4498 mlx5_ib_warn(dev,
4499 "couldn't allocate queue counter for port %d, err %d\n",
aac4492e
DJ		 4500 i + 1, err);
4501 goto err_alloc;
0837e86a 4502 }
aac4492e 4503 dev->port[i].cnts.set_id_valid = true;
0837e86a
MB		 4504 }
4505
4506 return 0;
4507
aac4492e
DJ		 4508err_alloc:
4509 mlx5_ib_dealloc_counters(dev);
4510 return err;
0837e86a
MB		 4511}
4512
0ad17a8f
MB		 4513static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
4514 u8 port_num)
4515{
7c16f477
KH		 4516 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4517 struct mlx5_ib_port *port = &dev->port[port_num - 1];
0ad17a8f
MB		 4518
4519 /* We support only per port stats */
4520 if (port_num == 0)
4521 return NULL;
4522
e1f24a79
PP		 4523 return rdma_alloc_hw_stats_struct(port->cnts.names,
4524 port->cnts.num_q_counters +
4525 port->cnts.num_cong_counters,
0ad17a8f
MB		 4526 RDMA_HW_STATS_DEFAULT_LIFESPAN);
4527}
4528
aac4492e 4529static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
e1f24a79
PP		 4530 struct mlx5_ib_port *port,
4531 struct rdma_hw_stats *stats)
0ad17a8f 4532{
0ad17a8f
MB		 4533 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
4534 void *out;
4535 __be32 val;
e1f24a79 4536 int ret, i;
0ad17a8f 4537
1b9a07ee 4538 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 4539 if (!out)
4540 return -ENOMEM;
4541
aac4492e 4542 ret = mlx5_core_query_q_counter(mdev,
e1f24a79 4543 port->cnts.set_id, 0,
0ad17a8f
MB		 4544 out, outlen);
4545 if (ret)
4546 goto free;
4547
e1f24a79
PP		 4548 for (i = 0; i < port->cnts.num_q_counters; i++) {
4549 val = *(__be32 *)(out + port->cnts.offsets[i]);
0ad17a8f
MB		 4550 stats->value[i] = (u64)be32_to_cpu(val);
4551 }
7c16f477 4552
0ad17a8f
MB		 4553free:
4554 kvfree(out);
e1f24a79
PP		 4555 return ret;
4556}
4557
e1f24a79
PP		 4558static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
4559 struct rdma_hw_stats *stats,
4560 u8 port_num, int index)
4561{
4562 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4563 struct mlx5_ib_port *port = &dev->port[port_num - 1];
aac4492e 4564 struct mlx5_core_dev *mdev;
e1f24a79 4565 int ret, num_counters;
aac4492e 4566 u8 mdev_port_num;
e1f24a79
PP		 4567
4568 if (!stats)
4569 return -EINVAL;
4570
aac4492e
DJ		 4571 num_counters = port->cnts.num_q_counters + port->cnts.num_cong_counters;
4572
4573 /* q_counters are per IB device, query the master mdev */
4574 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
e1f24a79
PP		 4575 if (ret)
4576 return ret;
e1f24a79
PP		 4577
4578 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
aac4492e
DJ		 4579 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
4580 &mdev_port_num);
4581 if (!mdev) {
4582 /* If port is not affiliated yet, its in down state
4583 * which doesn't have any counters yet, so it would be
4584 * zero. So no need to read from the HCA.
4585 */
4586 goto done;
4587 }
71a0ff65
MD		 4588 ret = mlx5_lag_query_cong_counters(dev->mdev,
4589 stats->value +
4590 port->cnts.num_q_counters,
4591 port->cnts.num_cong_counters,
4592 port->cnts.offsets +
4593 port->cnts.num_q_counters);
aac4492e
DJ		 4594
4595 mlx5_ib_put_native_port_mdev(dev, port_num);
e1f24a79
PP		 4596 if (ret)
4597 return ret;
e1f24a79
PP		 4598 }
4599
aac4492e 4600done:
e1f24a79 4601 return num_counters;
0ad17a8f
MB		 4602}
4603
8e959601
NV		 4604static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
4605{
4606 return mlx5_rdma_netdev_free(netdev);
4607}
4608
693dfd5a
ES		 4609static struct net_device*
4610mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
4611 u8 port_num,
4612 enum rdma_netdev_t type,
4613 const char *name,
4614 unsigned char name_assign_type,
4615 void (*setup)(struct net_device *))
4616{
8e959601
NV		 4617 struct net_device *netdev;
4618 struct rdma_netdev *rn;
4619
693dfd5a
ES		 4620 if (type != RDMA_NETDEV_IPOIB)
4621 return ERR_PTR(-EOPNOTSUPP);
4622
8e959601
NV		 4623 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
4624 name, setup);
4625 if (likely(!IS_ERR_OR_NULL(netdev))) {
4626 rn = netdev_priv(netdev);
4627 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
4628 }
4629 return netdev;
693dfd5a
ES		 4630}
4631
fe248c3a
MG		 4632static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
4633{
4634 if (!dev->delay_drop.dbg)
4635 return;
4636 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
4637 kfree(dev->delay_drop.dbg);
4638 dev->delay_drop.dbg = NULL;
4639}
4640
03404e8a
MG		 4641static void cancel_delay_drop(struct mlx5_ib_dev *dev)
4642{
4643 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4644 return;
4645
4646 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 4647 delay_drop_debugfs_cleanup(dev);
4648}
4649
4650static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
4651 size_t count, loff_t *pos)
4652{
4653 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4654 char lbuf[20];
4655 int len;
4656
4657 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
4658 return simple_read_from_buffer(buf, count, pos, lbuf, len);
4659}
4660
4661static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
4662 size_t count, loff_t *pos)
4663{
4664 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4665 u32 timeout;
4666 u32 var;
4667
4668 if (kstrtouint_from_user(buf, count, 0, &var))
4669 return -EFAULT;
4670
4671 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
4672 1000);
4673 if (timeout != var)
4674 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
4675 timeout);
4676
4677 delay_drop->timeout = timeout;
4678
4679 return count;
4680}
4681
4682static const struct file_operations fops_delay_drop_timeout = {
4683 .owner = THIS_MODULE,
4684 .open = simple_open,
4685 .write = delay_drop_timeout_write,
4686 .read = delay_drop_timeout_read,
4687};
4688
4689static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
4690{
4691 struct mlx5_ib_dbg_delay_drop *dbg;
4692
4693 if (!mlx5_debugfs_root)
4694 return 0;
4695
4696 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
4697 if (!dbg)
4698 return -ENOMEM;
4699
cbafad87
SM		 4700 dev->delay_drop.dbg = dbg;
4701
fe248c3a
MG		 4702 dbg->dir_debugfs =
4703 debugfs_create_dir("delay_drop",
4704 dev->mdev->priv.dbg_root);
4705 if (!dbg->dir_debugfs)
cbafad87 4706 goto out_debugfs;
fe248c3a
MG		 4707
4708 dbg->events_cnt_debugfs =
4709 debugfs_create_atomic_t("num_timeout_events", 0400,
4710 dbg->dir_debugfs,
4711 &dev->delay_drop.events_cnt);
4712 if (!dbg->events_cnt_debugfs)
4713 goto out_debugfs;
4714
4715 dbg->rqs_cnt_debugfs =
4716 debugfs_create_atomic_t("num_rqs", 0400,
4717 dbg->dir_debugfs,
4718 &dev->delay_drop.rqs_cnt);
4719 if (!dbg->rqs_cnt_debugfs)
4720 goto out_debugfs;
4721
4722 dbg->timeout_debugfs =
4723 debugfs_create_file("timeout", 0600,
4724 dbg->dir_debugfs,
4725 &dev->delay_drop,
4726 &fops_delay_drop_timeout);
4727 if (!dbg->timeout_debugfs)
4728 goto out_debugfs;
4729
4730 return 0;
4731
4732out_debugfs:
4733 delay_drop_debugfs_cleanup(dev);
4734 return -ENOMEM;
03404e8a
MG		 4735}
4736
4737static void init_delay_drop(struct mlx5_ib_dev *dev)
4738{
4739 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4740 return;
4741
4742 mutex_init(&dev->delay_drop.lock);
4743 dev->delay_drop.dev = dev;
4744 dev->delay_drop.activate = false;
4745 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
4746 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 4747 atomic_set(&dev->delay_drop.rqs_cnt, 0);
4748 atomic_set(&dev->delay_drop.events_cnt, 0);
4749
4750 if (delay_drop_debugfs_init(dev))
4751 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
03404e8a
MG		 4752}
4753
84305d71
LR		 4754static const struct cpumask *
4755mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
40b24403
SG		 4756{
4757 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4758
4759 return mlx5_get_vector_affinity(dev->mdev, comp_vector);
4760}
4761
32f69e4b
DJ		 4762/* The mlx5_ib_multiport_mutex should be held when calling this function */
4763static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
4764 struct mlx5_ib_multiport_info *mpi)
4765{
4766 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
4767 struct mlx5_ib_port *port = &ibdev->port[port_num];
4768 int comps;
4769 int err;
4770 int i;
4771
a9e546e7
PP		 4772 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
4773
32f69e4b
DJ		 4774 spin_lock(&port->mp.mpi_lock);
4775 if (!mpi->ibdev) {
4776 spin_unlock(&port->mp.mpi_lock);
4777 return;
4778 }
4779 mpi->ibdev = NULL;
4780
4781 spin_unlock(&port->mp.mpi_lock);
4782 mlx5_remove_netdev_notifier(ibdev, port_num);
4783 spin_lock(&port->mp.mpi_lock);
4784
4785 comps = mpi->mdev_refcnt;
4786 if (comps) {
4787 mpi->unaffiliate = true;
4788 init_completion(&mpi->unref_comp);
4789 spin_unlock(&port->mp.mpi_lock);
4790
4791 for (i = 0; i < comps; i++)
4792 wait_for_completion(&mpi->unref_comp);
4793
4794 spin_lock(&port->mp.mpi_lock);
4795 mpi->unaffiliate = false;
4796 }
4797
4798 port->mp.mpi = NULL;
4799
4800 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
4801
4802 spin_unlock(&port->mp.mpi_lock);
4803
4804 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
4805
4806 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
4807 /* Log an error, still needed to cleanup the pointers and add
4808 * it back to the list.
4809 */
4810 if (err)
4811 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
4812 port_num + 1);
4813
4814 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
4815}
4816
4817/* The mlx5_ib_multiport_mutex should be held when calling this function */
4818static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
4819 struct mlx5_ib_multiport_info *mpi)
4820{
4821 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
4822 int err;
4823
4824 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
4825 if (ibdev->port[port_num].mp.mpi) {
4826 mlx5_ib_warn(ibdev, "port %d already affiliated.\n",
4827 port_num + 1);
4828 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
4829 return false;
4830 }
4831
4832 ibdev->port[port_num].mp.mpi = mpi;
4833 mpi->ibdev = ibdev;
4834 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
4835
4836 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
4837 if (err)
4838 goto unbind;
4839
4840 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
4841 if (err)
4842 goto unbind;
4843
4844 err = mlx5_add_netdev_notifier(ibdev, port_num);
4845 if (err) {
4846 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
4847 port_num + 1);
4848 goto unbind;
4849 }
4850
a9e546e7
PP		 4851 err = mlx5_ib_init_cong_debugfs(ibdev, port_num);
4852 if (err)
4853 goto unbind;
4854
32f69e4b
DJ		 4855 return true;
4856
4857unbind:
4858 mlx5_ib_unbind_slave_port(ibdev, mpi);
4859 return false;
4860}
4861
4862static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
4863{
4864 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4865 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
4866 port_num + 1);
4867 struct mlx5_ib_multiport_info *mpi;
4868 int err;
4869 int i;
4870
4871 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
4872 return 0;
4873
4874 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
4875 &dev->sys_image_guid);
4876 if (err)
4877 return err;
4878
4879 err = mlx5_nic_vport_enable_roce(dev->mdev);
4880 if (err)
4881 return err;
4882
4883 mutex_lock(&mlx5_ib_multiport_mutex);
4884 for (i = 0; i < dev->num_ports; i++) {
4885 bool bound = false;
4886
4887 /* build a stub multiport info struct for the native port. */
4888 if (i == port_num) {
4889 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
4890 if (!mpi) {
4891 mutex_unlock(&mlx5_ib_multiport_mutex);
4892 mlx5_nic_vport_disable_roce(dev->mdev);
4893 return -ENOMEM;
4894 }
4895
4896 mpi->is_master = true;
4897 mpi->mdev = dev->mdev;
4898 mpi->sys_image_guid = dev->sys_image_guid;
4899 dev->port[i].mp.mpi = mpi;
4900 mpi->ibdev = dev;
4901 mpi = NULL;
4902 continue;
4903 }
4904
4905 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
4906 list) {
4907 if (dev->sys_image_guid == mpi->sys_image_guid &&
4908 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
4909 bound = mlx5_ib_bind_slave_port(dev, mpi);
4910 }
4911
4912 if (bound) {
4913 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
4914 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
4915 list_del(&mpi->list);
4916 break;
4917 }
4918 }
4919 if (!bound) {
4920 get_port_caps(dev, i + 1);
4921 mlx5_ib_dbg(dev, "no free port found for port %d\n",
4922 i + 1);
4923 }
4924 }
4925
4926 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
4927 mutex_unlock(&mlx5_ib_multiport_mutex);
4928 return err;
4929}
4930
4931static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
4932{
4933 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4934 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
4935 port_num + 1);
4936 int i;
4937
4938 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
4939 return;
4940
4941 mutex_lock(&mlx5_ib_multiport_mutex);
4942 for (i = 0; i < dev->num_ports; i++) {
4943 if (dev->port[i].mp.mpi) {
4944 /* Destroy the native port stub */
4945 if (i == port_num) {
4946 kfree(dev->port[i].mp.mpi);
4947 dev->port[i].mp.mpi = NULL;
4948 } else {
4949 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
4950 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
4951 }
4952 }
4953 }
4954
4955 mlx5_ib_dbg(dev, "removing from devlist\n");
4956 list_del(&dev->ib_dev_list);
4957 mutex_unlock(&mlx5_ib_multiport_mutex);
4958
4959 mlx5_nic_vport_disable_roce(dev->mdev);
4960}
4961
24da0016
AL		 4962ADD_UVERBS_ATTRIBUTES_SIMPLE(mlx5_ib_dm, UVERBS_OBJECT_DM,
4963 UVERBS_METHOD_DM_ALLOC,
4964 &UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
4965 UVERBS_ATTR_TYPE(u64),
4966 UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)),
4967 &UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
4968 UVERBS_ATTR_TYPE(u16),
4969 UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)));
4970
c6475a0b
AY		 4971ADD_UVERBS_ATTRIBUTES_SIMPLE(mlx5_ib_flow_action, UVERBS_OBJECT_FLOW_ACTION,
4972 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
4973 &UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
4974 UVERBS_ATTR_TYPE(u64),
4975 UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)));
4976
24da0016 4977#define NUM_TREES 2
8c84660b
MB		 4978static int populate_specs_root(struct mlx5_ib_dev *dev)
4979{
4980 const struct uverbs_object_tree_def *default_root[NUM_TREES + 1] = {
4981 uverbs_default_get_objects()};
4982 size_t num_trees = 1;
4983
c6475a0b
AY		 4984 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE &&
4985 !WARN_ON(num_trees >= ARRAY_SIZE(default_root)))
4986 default_root[num_trees++] = &mlx5_ib_flow_action;
4987
24da0016
AL		 4988 if (MLX5_CAP_DEV_MEM(dev->mdev, memic) &&
4989 !WARN_ON(num_trees >= ARRAY_SIZE(default_root)))
4990 default_root[num_trees++] = &mlx5_ib_dm;
4991
8c84660b
MB		 4992 dev->ib_dev.specs_root =
4993 uverbs_alloc_spec_tree(num_trees, default_root);
4994
4995 return PTR_ERR_OR_ZERO(dev->ib_dev.specs_root);
4996}
4997
4998static void depopulate_specs_root(struct mlx5_ib_dev *dev)
4999{
5000 uverbs_free_spec_tree(dev->ib_dev.specs_root);
5001}
5002
b5ca15ad 5003void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
e126ba97 5004{
32f69e4b 5005 mlx5_ib_cleanup_multiport_master(dev);
3cc297db
MB		 5006#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5007 cleanup_srcu_struct(&dev->mr_srcu);
5008#endif
16c1975f
MB		 5009 kfree(dev->port);
5010}
5011
b5ca15ad 5012int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5013{
5014 struct mlx5_core_dev *mdev = dev->mdev;
4babcf97 5015 const char *name;
e126ba97 5016 int err;
32f69e4b 5017 int i;
e126ba97 5018
508562d6 5019 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
0837e86a
MB		 5020 GFP_KERNEL);
5021 if (!dev->port)
16c1975f 5022 return -ENOMEM;
0837e86a 5023
32f69e4b
DJ		 5024 for (i = 0; i < dev->num_ports; i++) {
5025 spin_lock_init(&dev->port[i].mp.mpi_lock);
5026 rwlock_init(&dev->roce[i].netdev_lock);
5027 }
5028
5029 err = mlx5_ib_init_multiport_master(dev);
e126ba97 5030 if (err)
0837e86a 5031 goto err_free_port;
e126ba97 5032
32f69e4b 5033 if (!mlx5_core_mp_enabled(mdev)) {
32f69e4b
DJ		 5034 for (i = 1; i <= dev->num_ports; i++) {
5035 err = get_port_caps(dev, i);
5036 if (err)
5037 break;
5038 }
5039 } else {
5040 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
5041 }
5042 if (err)
5043 goto err_mp;
5044
1b5daf11
MD		 5045 if (mlx5_use_mad_ifc(dev))
5046 get_ext_port_caps(dev);
e126ba97 5047
4babcf97
AH		 5048 if (!mlx5_lag_is_active(mdev))
5049 name = "mlx5_%d";
5050 else
5051 name = "mlx5_bond_%d";
5052
5053 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
e126ba97
EC		 5054 dev->ib_dev.owner = THIS_MODULE;
5055 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 5056 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
508562d6 5057 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 5058 dev->ib_dev.num_comp_vectors =
5059 dev->mdev->priv.eq_table.num_comp_vectors;
9b0c289e 5060 dev->ib_dev.dev.parent = &mdev->pdev->dev;
e126ba97 5061
3cc297db
MB		 5062 mutex_init(&dev->cap_mask_mutex);
5063 INIT_LIST_HEAD(&dev->qp_list);
5064 spin_lock_init(&dev->reset_flow_resource_lock);
5065
24da0016
AL		 5066 spin_lock_init(&dev->memic.memic_lock);
5067 dev->memic.dev = mdev;
5068
3cc297db
MB		 5069#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5070 err = init_srcu_struct(&dev->mr_srcu);
5071 if (err)
5072 goto err_free_port;
5073#endif
5074
16c1975f 5075 return 0;
32f69e4b
DJ		 5076err_mp:
5077 mlx5_ib_cleanup_multiport_master(dev);
16c1975f
MB		 5078
5079err_free_port:
5080 kfree(dev->port);
5081
5082 return -ENOMEM;
5083}
5084
9a4ca38d
MB		 5085static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
5086{
5087 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
5088
5089 if (!dev->flow_db)
5090 return -ENOMEM;
5091
5092 mutex_init(&dev->flow_db->lock);
5093
5094 return 0;
5095}
5096
b5ca15ad
MB		 5097int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev)
5098{
5099 struct mlx5_ib_dev *nic_dev;
5100
5101 nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch);
5102
5103 if (!nic_dev)
5104 return -EINVAL;
5105
5106 dev->flow_db = nic_dev->flow_db;
5107
5108 return 0;
5109}
5110
9a4ca38d
MB		 5111static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
5112{
5113 kfree(dev->flow_db);
5114}
5115
b5ca15ad 5116int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5117{
5118 struct mlx5_core_dev *mdev = dev->mdev;
16c1975f
MB		 5119 int err;
5120
e126ba97
EC		 5121 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
5122 dev->ib_dev.uverbs_cmd_mask =
5123 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
5124 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
5125 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
5126 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
5127 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 5128 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
5129 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 5130 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 5131 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 5132 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
5133 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
5134 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
5135 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
5136 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
5137 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
5138 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
5139 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
5140 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
5141 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
5142 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
5143 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
5144 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
5145 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
5146 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
5147 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
5148 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 5149 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 5150 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
5151 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349 5152 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
b0e9df6d
YC		 5153 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
5154 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
e126ba97
EC		 5155
5156 dev->ib_dev.query_device = mlx5_ib_query_device;
ebd61f68 5157 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
e126ba97 5158 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 5159 dev->ib_dev.add_gid = mlx5_ib_add_gid;
5160 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 5161 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
5162 dev->ib_dev.modify_device = mlx5_ib_modify_device;
5163 dev->ib_dev.modify_port = mlx5_ib_modify_port;
5164 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
5165 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
5166 dev->ib_dev.mmap = mlx5_ib_mmap;
5167 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
5168 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
5169 dev->ib_dev.create_ah = mlx5_ib_create_ah;
5170 dev->ib_dev.query_ah = mlx5_ib_query_ah;
5171 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
5172 dev->ib_dev.create_srq = mlx5_ib_create_srq;
5173 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
5174 dev->ib_dev.query_srq = mlx5_ib_query_srq;
5175 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
5176 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
5177 dev->ib_dev.create_qp = mlx5_ib_create_qp;
5178 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
5179 dev->ib_dev.query_qp = mlx5_ib_query_qp;
5180 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
5181 dev->ib_dev.post_send = mlx5_ib_post_send;
5182 dev->ib_dev.post_recv = mlx5_ib_post_recv;
5183 dev->ib_dev.create_cq = mlx5_ib_create_cq;
5184 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
5185 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
5186 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
5187 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
5188 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
5189 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
5190 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 5191 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 5192 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
5193 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
5194 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
5195 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 5196 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 5197 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 5198 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
c7342823 5199 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
40b24403 5200 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
8e959601 5201 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
022d038a 5202 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
8e959601 5203
eff901d3
EC		 5204 if (mlx5_core_is_pf(mdev)) {
5205 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
5206 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
5207 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
5208 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
5209 }
e126ba97 5210
7c2344c3
MG		 5211 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
5212
6e8484c5
MG		 5213 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
5214
d2370e0a
MB		 5215 if (MLX5_CAP_GEN(mdev, imaicl)) {
5216 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
5217 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
5218 dev->ib_dev.uverbs_cmd_mask |=
5219 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
5220 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
5221 }
5222
938fe83c 5223 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 5224 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
5225 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
5226 dev->ib_dev.uverbs_cmd_mask |=
5227 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
5228 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
5229 }
5230
24da0016
AL		 5231 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
5232 dev->ib_dev.alloc_dm = mlx5_ib_alloc_dm;
5233 dev->ib_dev.dealloc_dm = mlx5_ib_dealloc_dm;
6c29f57e 5234 dev->ib_dev.reg_dm_mr = mlx5_ib_reg_dm_mr;
24da0016
AL		 5235 }
5236
81e30880
YH		 5237 dev->ib_dev.create_flow = mlx5_ib_create_flow;
5238 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
5239 dev->ib_dev.uverbs_ex_cmd_mask |=
5240 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
5241 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
c6475a0b
AY		 5242 dev->ib_dev.create_flow_action_esp = mlx5_ib_create_flow_action_esp;
5243 dev->ib_dev.destroy_flow_action = mlx5_ib_destroy_flow_action;
349705c1 5244 dev->ib_dev.modify_flow_action_esp = mlx5_ib_modify_flow_action_esp;
0ede73bc 5245 dev->ib_dev.driver_id = RDMA_DRIVER_MLX5;
81e30880 5246
e126ba97
EC		 5247 err = init_node_data(dev);
5248 if (err)
16c1975f 5249 return err;
e126ba97 5250
c8b89924 5251 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
e7996a9a
JG		 5252 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
5253 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c8b89924
MB		 5254 mutex_init(&dev->lb_mutex);
5255
16c1975f
MB		 5256 return 0;
5257}
5258
8e6efa3a
MB		 5259static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
5260{
5261 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
5262 dev->ib_dev.query_port = mlx5_ib_query_port;
5263
5264 return 0;
5265}
5266
b5ca15ad 5267int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
8e6efa3a
MB		 5268{
5269 dev->ib_dev.get_port_immutable = mlx5_port_rep_immutable;
5270 dev->ib_dev.query_port = mlx5_ib_rep_query_port;
5271
5272 return 0;
5273}
5274
5275static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev,
5276 u8 port_num)
5277{
5278 int i;
5279
5280 for (i = 0; i < dev->num_ports; i++) {
5281 dev->roce[i].dev = dev;
5282 dev->roce[i].native_port_num = i + 1;
5283 dev->roce[i].last_port_state = IB_PORT_DOWN;
5284 }
5285
5286 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
5287 dev->ib_dev.create_wq = mlx5_ib_create_wq;
5288 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
5289 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
5290 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
5291 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
5292
5293 dev->ib_dev.uverbs_ex_cmd_mask |=
5294 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
5295 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
5296 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
5297 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
5298 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
5299
5300 return mlx5_add_netdev_notifier(dev, port_num);
5301}
5302
5303static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
5304{
5305 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5306
5307 mlx5_remove_netdev_notifier(dev, port_num);
5308}
5309
5310int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
5311{
5312 struct mlx5_core_dev *mdev = dev->mdev;
5313 enum rdma_link_layer ll;
5314 int port_type_cap;
5315 int err = 0;
5316 u8 port_num;
5317
5318 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5319 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5320 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5321
5322 if (ll == IB_LINK_LAYER_ETHERNET)
5323 err = mlx5_ib_stage_common_roce_init(dev, port_num);
5324
5325 return err;
5326}
5327
5328void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
5329{
5330 mlx5_ib_stage_common_roce_cleanup(dev);
5331}
5332
16c1975f
MB		 5333static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
5334{
5335 struct mlx5_core_dev *mdev = dev->mdev;
5336 enum rdma_link_layer ll;
5337 int port_type_cap;
32f69e4b 5338 u8 port_num;
16c1975f
MB		 5339 int err;
5340
32f69e4b 5341 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
16c1975f
MB		 5342 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5343 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5344
fc24fc5e 5345 if (ll == IB_LINK_LAYER_ETHERNET) {
8e6efa3a
MB		 5346 err = mlx5_ib_stage_common_roce_init(dev, port_num);
5347 if (err)
5348 return err;
7fd8aefb 5349
7fd8aefb 5350 err = mlx5_enable_eth(dev, port_num);
fc24fc5e 5351 if (err)
8e6efa3a 5352 goto cleanup;
fc24fc5e
AS		 5353 }
5354
16c1975f 5355 return 0;
8e6efa3a
MB		 5356cleanup:
5357 mlx5_ib_stage_common_roce_cleanup(dev);
5358
5359 return err;
16c1975f 5360}
e126ba97 5361
16c1975f
MB		 5362static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
5363{
5364 struct mlx5_core_dev *mdev = dev->mdev;
5365 enum rdma_link_layer ll;
5366 int port_type_cap;
32f69e4b 5367 u8 port_num;
e126ba97 5368
32f69e4b 5369 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
16c1975f
MB		 5370 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5371 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5372
5373 if (ll == IB_LINK_LAYER_ETHERNET) {
5374 mlx5_disable_eth(dev);
8e6efa3a 5375 mlx5_ib_stage_common_roce_cleanup(dev);
45bded2c 5376 }
16c1975f 5377}
6aec21f6 5378
b5ca15ad 5379int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5380{
5381 return create_dev_resources(&dev->devr);
5382}
5383
b5ca15ad 5384void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 5385{
5386 destroy_dev_resources(&dev->devr);
5387}
5388
5389static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
5390{
07321b3c
MB		 5391 mlx5_ib_internal_fill_odp_caps(dev);
5392
16c1975f
MB		 5393 return mlx5_ib_odp_init_one(dev);
5394}
4a2da0b8 5395
b5ca15ad 5396int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
16c1975f 5397{
5e1e7612
MB		 5398 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
5399 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
5400 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
5401
5402 return mlx5_ib_alloc_counters(dev);
5403 }
16c1975f
MB		 5404
5405 return 0;
5406}
5407
b5ca15ad 5408void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 5409{
5410 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
5411 mlx5_ib_dealloc_counters(dev);
5412}
5413
5414static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
5415{
a9e546e7
PP		 5416 return mlx5_ib_init_cong_debugfs(dev,
5417 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 5418}
5419
5420static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
5421{
a9e546e7
PP		 5422 mlx5_ib_cleanup_cong_debugfs(dev,
5423 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 5424}
5425
5426static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
5427{
5fe9dec0
EC		 5428 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
5429 if (!dev->mdev->priv.uar)
16c1975f
MB		 5430 return -ENOMEM;
5431 return 0;
5432}
5433
5434static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
5435{
5436 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
5437}
5438
b5ca15ad 5439int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5440{
5441 int err;
5fe9dec0
EC		 5442
5443 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
5444 if (err)
16c1975f 5445 return err;
5fe9dec0
EC		 5446
5447 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
5448 if (err)
16c1975f 5449 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5fe9dec0 5450
16c1975f
MB		 5451 return err;
5452}
0837e86a 5453
b5ca15ad 5454void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 5455{
5456 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5457 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
5458}
e126ba97 5459
8c84660b
MB		 5460static int mlx5_ib_stage_populate_specs(struct mlx5_ib_dev *dev)
5461{
5462 return populate_specs_root(dev);
5463}
5464
b5ca15ad 5465int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5466{
5467 return ib_register_device(&dev->ib_dev, NULL);
5468}
5469
8c84660b
MB		 5470static void mlx5_ib_stage_depopulate_specs(struct mlx5_ib_dev *dev)
5471{
5472 depopulate_specs_root(dev);
5473}
5474
03fe2deb 5475void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
16c1975f 5476{
42cea83f 5477 destroy_umrc_res(dev);
16c1975f
MB		 5478}
5479
03fe2deb 5480void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
16c1975f 5481{
42cea83f 5482 ib_unregister_device(&dev->ib_dev);
16c1975f
MB		 5483}
5484
03fe2deb 5485int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
16c1975f 5486{
42cea83f 5487 return create_umr_res(dev);
16c1975f
MB		 5488}
5489
5490static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
5491{
03404e8a
MG		 5492 init_delay_drop(dev);
5493
16c1975f
MB		 5494 return 0;
5495}
5496
5497static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
5498{
5499 cancel_delay_drop(dev);
5500}
5501
b5ca15ad 5502int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5503{
5504 int err;
5505 int i;
5506
e126ba97 5507 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 5508 err = device_create_file(&dev->ib_dev.dev,
5509 mlx5_class_attributes[i]);
5510 if (err)
16c1975f 5511 return err;
e126ba97
EC		 5512 }
5513
16c1975f
MB		 5514 return 0;
5515}
5516
fc385b7a
MB		 5517static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev *dev)
5518{
5519 mlx5_ib_register_vport_reps(dev);
5520
5521 return 0;
5522}
5523
5524static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev *dev)
5525{
5526 mlx5_ib_unregister_vport_reps(dev);
5527}
5528
b5ca15ad
MB		 5529void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
5530 const struct mlx5_ib_profile *profile,
5531 int stage)
16c1975f
MB		 5532{
5533 /* Number of stages to cleanup */
5534 while (stage) {
5535 stage--;
5536 if (profile->stage[stage].cleanup)
5537 profile->stage[stage].cleanup(dev);
5538 }
e126ba97 5539
16c1975f
MB		 5540 ib_dealloc_device((struct ib_device *)dev);
5541}
e126ba97 5542
32f69e4b
DJ		 5543static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num);
5544
b5ca15ad
MB		 5545void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
5546 const struct mlx5_ib_profile *profile)
16c1975f 5547{
16c1975f
MB		 5548 int err;
5549 int i;
e126ba97 5550
16c1975f 5551 printk_once(KERN_INFO "%s", mlx5_version);
5fe9dec0 5552
16c1975f
MB		 5553 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
5554 if (profile->stage[i].init) {
5555 err = profile->stage[i].init(dev);
5556 if (err)
5557 goto err_out;
5558 }
5559 }
0837e86a 5560
16c1975f
MB		 5561 dev->profile = profile;
5562 dev->ib_active = true;
6aec21f6 5563
16c1975f 5564 return dev;
e126ba97 5565
16c1975f
MB		 5566err_out:
5567 __mlx5_ib_remove(dev, profile, i);
fc24fc5e 5568
16c1975f
MB		 5569 return NULL;
5570}
0837e86a 5571
16c1975f
MB		 5572static const struct mlx5_ib_profile pf_profile = {
5573 STAGE_CREATE(MLX5_IB_STAGE_INIT,
5574 mlx5_ib_stage_init_init,
5575 mlx5_ib_stage_init_cleanup),
9a4ca38d
MB		 5576 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
5577 mlx5_ib_stage_flow_db_init,
5578 mlx5_ib_stage_flow_db_cleanup),
16c1975f
MB		 5579 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
5580 mlx5_ib_stage_caps_init,
5581 NULL),
8e6efa3a
MB		 5582 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
5583 mlx5_ib_stage_non_default_cb,
5584 NULL),
16c1975f
MB		 5585 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
5586 mlx5_ib_stage_roce_init,
5587 mlx5_ib_stage_roce_cleanup),
5588 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
5589 mlx5_ib_stage_dev_res_init,
5590 mlx5_ib_stage_dev_res_cleanup),
5591 STAGE_CREATE(MLX5_IB_STAGE_ODP,
5592 mlx5_ib_stage_odp_init,
3cc297db 5593 NULL),
16c1975f
MB		 5594 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
5595 mlx5_ib_stage_counters_init,
5596 mlx5_ib_stage_counters_cleanup),
5597 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
5598 mlx5_ib_stage_cong_debugfs_init,
5599 mlx5_ib_stage_cong_debugfs_cleanup),
5600 STAGE_CREATE(MLX5_IB_STAGE_UAR,
5601 mlx5_ib_stage_uar_init,
5602 mlx5_ib_stage_uar_cleanup),
5603 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
5604 mlx5_ib_stage_bfrag_init,
5605 mlx5_ib_stage_bfrag_cleanup),
42cea83f
MB		 5606 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
5607 NULL,
5608 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
8c84660b
MB		 5609 STAGE_CREATE(MLX5_IB_STAGE_SPECS,
5610 mlx5_ib_stage_populate_specs,
5611 mlx5_ib_stage_depopulate_specs),
16c1975f
MB		 5612 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
5613 mlx5_ib_stage_ib_reg_init,
5614 mlx5_ib_stage_ib_reg_cleanup),
42cea83f
MB		 5615 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
5616 mlx5_ib_stage_post_ib_reg_umr_init,
5617 NULL),
16c1975f
MB		 5618 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
5619 mlx5_ib_stage_delay_drop_init,
5620 mlx5_ib_stage_delay_drop_cleanup),
5621 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
5622 mlx5_ib_stage_class_attr_init,
5623 NULL),
16c1975f 5624};
e126ba97 5625
b5ca15ad
MB		 5626static const struct mlx5_ib_profile nic_rep_profile = {
5627 STAGE_CREATE(MLX5_IB_STAGE_INIT,
5628 mlx5_ib_stage_init_init,
5629 mlx5_ib_stage_init_cleanup),
5630 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
5631 mlx5_ib_stage_flow_db_init,
5632 mlx5_ib_stage_flow_db_cleanup),
5633 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
5634 mlx5_ib_stage_caps_init,
5635 NULL),
5636 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
5637 mlx5_ib_stage_rep_non_default_cb,
5638 NULL),
5639 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
5640 mlx5_ib_stage_rep_roce_init,
5641 mlx5_ib_stage_rep_roce_cleanup),
5642 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
5643 mlx5_ib_stage_dev_res_init,
5644 mlx5_ib_stage_dev_res_cleanup),
5645 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
5646 mlx5_ib_stage_counters_init,
5647 mlx5_ib_stage_counters_cleanup),
5648 STAGE_CREATE(MLX5_IB_STAGE_UAR,
5649 mlx5_ib_stage_uar_init,
5650 mlx5_ib_stage_uar_cleanup),
5651 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
5652 mlx5_ib_stage_bfrag_init,
5653 mlx5_ib_stage_bfrag_cleanup),
03fe2deb
DM		 5654 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
5655 NULL,
5656 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
8c84660b
MB		 5657 STAGE_CREATE(MLX5_IB_STAGE_SPECS,
5658 mlx5_ib_stage_populate_specs,
5659 mlx5_ib_stage_depopulate_specs),
b5ca15ad
MB		 5660 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
5661 mlx5_ib_stage_ib_reg_init,
5662 mlx5_ib_stage_ib_reg_cleanup),
03fe2deb
DM		 5663 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
5664 mlx5_ib_stage_post_ib_reg_umr_init,
5665 NULL),
b5ca15ad
MB		 5666 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
5667 mlx5_ib_stage_class_attr_init,
5668 NULL),
5669 STAGE_CREATE(MLX5_IB_STAGE_REP_REG,
5670 mlx5_ib_stage_rep_reg_init,
5671 mlx5_ib_stage_rep_reg_cleanup),
5672};
5673
32f69e4b
DJ		 5674static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num)
5675{
5676 struct mlx5_ib_multiport_info *mpi;
5677 struct mlx5_ib_dev *dev;
5678 bool bound = false;
5679 int err;
5680
5681 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5682 if (!mpi)
5683 return NULL;
5684
5685 mpi->mdev = mdev;
5686
5687 err = mlx5_query_nic_vport_system_image_guid(mdev,
5688 &mpi->sys_image_guid);
5689 if (err) {
5690 kfree(mpi);
5691 return NULL;
5692 }
5693
5694 mutex_lock(&mlx5_ib_multiport_mutex);
5695 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
5696 if (dev->sys_image_guid == mpi->sys_image_guid)
5697 bound = mlx5_ib_bind_slave_port(dev, mpi);
5698
5699 if (bound) {
5700 rdma_roce_rescan_device(&dev->ib_dev);
5701 break;
5702 }
5703 }
5704
5705 if (!bound) {
5706 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5707 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
5708 } else {
5709 mlx5_ib_dbg(dev, "bound port %u\n", port_num + 1);
5710 }
5711 mutex_unlock(&mlx5_ib_multiport_mutex);
5712
5713 return mpi;
5714}
5715
16c1975f
MB		 5716static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
5717{
32f69e4b 5718 enum rdma_link_layer ll;
b5ca15ad 5719 struct mlx5_ib_dev *dev;
32f69e4b
DJ		 5720 int port_type_cap;
5721
b5ca15ad
MB		 5722 printk_once(KERN_INFO "%s", mlx5_version);
5723
32f69e4b
DJ		 5724 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5725 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5726
5727 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) {
5728 u8 port_num = mlx5_core_native_port_num(mdev) - 1;
5729
5730 return mlx5_ib_add_slave_port(mdev, port_num);
5731 }
5732
b5ca15ad
MB		 5733 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
5734 if (!dev)
5735 return NULL;
5736
5737 dev->mdev = mdev;
5738 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
5739 MLX5_CAP_GEN(mdev, num_vhca_ports));
5740
5741 if (MLX5_VPORT_MANAGER(mdev) &&
5742 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
5743 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0);
5744
5745 return __mlx5_ib_add(dev, &nic_rep_profile);
5746 }
5747
5748 return __mlx5_ib_add(dev, &pf_profile);
e126ba97
EC		 5749}
5750
9603b61d 5751static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 5752{
32f69e4b
DJ		 5753 struct mlx5_ib_multiport_info *mpi;
5754 struct mlx5_ib_dev *dev;
5755
5756 if (mlx5_core_is_mp_slave(mdev)) {
5757 mpi = context;
5758 mutex_lock(&mlx5_ib_multiport_mutex);
5759 if (mpi->ibdev)
5760 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
5761 list_del(&mpi->list);
5762 mutex_unlock(&mlx5_ib_multiport_mutex);
5763 return;
5764 }
6aec21f6 5765
32f69e4b 5766 dev = context;
16c1975f 5767 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
e126ba97
EC		 5768}
5769
9603b61d
JM		 5770static struct mlx5_interface mlx5_ib_interface = {
5771 .add = mlx5_ib_add,
5772 .remove = mlx5_ib_remove,
5773 .event = mlx5_ib_event,
d9aaed83
AK		 5774#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5775 .pfault = mlx5_ib_pfault,
5776#endif
64613d94 5777 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 5778};
5779
c44ef998
IL		 5780unsigned long mlx5_ib_get_xlt_emergency_page(void)
5781{
5782 mutex_lock(&xlt_emergency_page_mutex);
5783 return xlt_emergency_page;
5784}
5785
5786void mlx5_ib_put_xlt_emergency_page(void)
5787{
5788 mutex_unlock(&xlt_emergency_page_mutex);
5789}
5790
e126ba97
EC		 5791static int __init mlx5_ib_init(void)
5792{
6aec21f6
HE		 5793 int err;
5794
c44ef998
IL		 5795 xlt_emergency_page = __get_free_page(GFP_KERNEL);
5796 if (!xlt_emergency_page)
5797 return -ENOMEM;
5798
5799 mutex_init(&xlt_emergency_page_mutex);
5800
d69a24e0 5801 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
c44ef998
IL		 5802 if (!mlx5_ib_event_wq) {
5803 free_page(xlt_emergency_page);
d69a24e0 5804 return -ENOMEM;
c44ef998 5805 }
d69a24e0 5806
81713d37 5807 mlx5_ib_odp_init();
9603b61d 5808
6aec21f6 5809 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 5810
6aec21f6 5811 return err;
e126ba97
EC		 5812}
5813
5814static void __exit mlx5_ib_cleanup(void)
5815{
9603b61d 5816 mlx5_unregister_interface(&mlx5_ib_interface);
d69a24e0 5817 destroy_workqueue(mlx5_ib_event_wq);
c44ef998
IL		 5818 mutex_destroy(&xlt_emergency_page_mutex);
5819 free_page(xlt_emergency_page);
e126ba97
EC		 5820}
5821
5822module_init(mlx5_ib_init);
5823module_exit(mlx5_ib_cleanup);
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