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IB/core: Change roce_rescan_device to return void
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
37aa5c36
GL		 41#if defined(CONFIG_X86)
42#include <asm/pat.h>
43#endif
e126ba97 44#include <linux/sched.h>
6e84f315 45#include <linux/sched/mm.h>
0881e7bd 46#include <linux/sched/task.h>
7c2344c3 47#include <linux/delay.h>
e126ba97 48#include <rdma/ib_user_verbs.h>
3f89a643 49#include <rdma/ib_addr.h>
2811ba51 50#include <rdma/ib_cache.h>
ada68c31 51#include <linux/mlx5/port.h>
1b5daf11 52#include <linux/mlx5/vport.h>
72c7fe90 53#include <linux/mlx5/fs.h>
7c2344c3 54#include <linux/list.h>
e126ba97
EC		 55#include <rdma/ib_smi.h>
56#include <rdma/ib_umem.h>
038d2ef8
MG		 57#include <linux/in.h>
58#include <linux/etherdevice.h>
e126ba97 59#include "mlx5_ib.h"
e1f24a79 60#include "cmd.h"
e126ba97
EC		 61
62#define DRIVER_NAME "mlx5_ib"
b359911d 63#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 64
65MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
66MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
67MODULE_LICENSE("Dual BSD/GPL");
e126ba97 68
e126ba97
EC		 69static char mlx5_version[] =
70 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 71 DRIVER_VERSION "\n";
e126ba97 72
da7525d2
EBE		 73enum {
74 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
75};
76
1b5daf11 77static enum rdma_link_layer
ebd61f68 78mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 79{
ebd61f68 80 switch (port_type_cap) {
1b5daf11
MD		 81 case MLX5_CAP_PORT_TYPE_IB:
82 return IB_LINK_LAYER_INFINIBAND;
83 case MLX5_CAP_PORT_TYPE_ETH:
84 return IB_LINK_LAYER_ETHERNET;
85 default:
86 return IB_LINK_LAYER_UNSPECIFIED;
87 }
88}
89
ebd61f68
AS		 90static enum rdma_link_layer
91mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
92{
93 struct mlx5_ib_dev *dev = to_mdev(device);
94 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
95
96 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
97}
98
fd65f1b8
MS		 99static int get_port_state(struct ib_device *ibdev,
100 u8 port_num,
101 enum ib_port_state *state)
102{
103 struct ib_port_attr attr;
104 int ret;
105
106 memset(&attr, 0, sizeof(attr));
107 ret = mlx5_ib_query_port(ibdev, port_num, &attr);
108 if (!ret)
109 *state = attr.state;
110 return ret;
111}
112
fc24fc5e
AS		 113static int mlx5_netdev_event(struct notifier_block *this,
114 unsigned long event, void *ptr)
115{
116 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
117 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
118 roce.nb);
119
5ec8c83e
AH		 120 switch (event) {
121 case NETDEV_REGISTER:
122 case NETDEV_UNREGISTER:
123 write_lock(&ibdev->roce.netdev_lock);
124 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
125 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
126 NULL : ndev;
127 write_unlock(&ibdev->roce.netdev_lock);
128 break;
fc24fc5e 129
fd65f1b8 130 case NETDEV_CHANGE:
5ec8c83e 131 case NETDEV_UP:
88621dfe
AH		 132 case NETDEV_DOWN: {
133 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
134 struct net_device *upper = NULL;
135
136 if (lag_ndev) {
137 upper = netdev_master_upper_dev_get(lag_ndev);
138 dev_put(lag_ndev);
139 }
140
141 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
142 && ibdev->ib_active) {
626bc02d 143 struct ib_event ibev = { };
fd65f1b8 144 enum ib_port_state port_state;
5ec8c83e 145
fd65f1b8
MS		 146 if (get_port_state(&ibdev->ib_dev, 1, &port_state))
147 return NOTIFY_DONE;
148
149 if (ibdev->roce.last_port_state == port_state)
150 return NOTIFY_DONE;
151
152 ibdev->roce.last_port_state = port_state;
5ec8c83e 153 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 154 if (port_state == IB_PORT_DOWN)
155 ibev.event = IB_EVENT_PORT_ERR;
156 else if (port_state == IB_PORT_ACTIVE)
157 ibev.event = IB_EVENT_PORT_ACTIVE;
158 else
159 return NOTIFY_DONE;
160
5ec8c83e
AH		 161 ibev.element.port_num = 1;
162 ib_dispatch_event(&ibev);
163 }
164 break;
88621dfe 165 }
fc24fc5e 166
5ec8c83e
AH		 167 default:
168 break;
169 }
fc24fc5e
AS		 170
171 return NOTIFY_DONE;
172}
173
174static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
175 u8 port_num)
176{
177 struct mlx5_ib_dev *ibdev = to_mdev(device);
178 struct net_device *ndev;
179
88621dfe
AH		 180 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
181 if (ndev)
182 return ndev;
183
fc24fc5e
AS		 184 /* Ensure ndev does not disappear before we invoke dev_hold()
185 */
186 read_lock(&ibdev->roce.netdev_lock);
187 ndev = ibdev->roce.netdev;
188 if (ndev)
189 dev_hold(ndev);
190 read_unlock(&ibdev->roce.netdev_lock);
191
192 return ndev;
193}
194
f1b65df5
NO		 195static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
196 u8 *active_width)
197{
198 switch (eth_proto_oper) {
199 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
200 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
201 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
202 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
203 *active_width = IB_WIDTH_1X;
204 *active_speed = IB_SPEED_SDR;
205 break;
206 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
207 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
208 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
209 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
210 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
211 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
212 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
213 *active_width = IB_WIDTH_1X;
214 *active_speed = IB_SPEED_QDR;
215 break;
216 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
217 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
218 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
219 *active_width = IB_WIDTH_1X;
220 *active_speed = IB_SPEED_EDR;
221 break;
222 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
223 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
224 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
225 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
226 *active_width = IB_WIDTH_4X;
227 *active_speed = IB_SPEED_QDR;
228 break;
229 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
230 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
231 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
232 *active_width = IB_WIDTH_1X;
233 *active_speed = IB_SPEED_HDR;
234 break;
235 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
236 *active_width = IB_WIDTH_4X;
237 *active_speed = IB_SPEED_FDR;
238 break;
239 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
240 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
241 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
242 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
243 *active_width = IB_WIDTH_4X;
244 *active_speed = IB_SPEED_EDR;
245 break;
246 default:
247 return -EINVAL;
248 }
249
250 return 0;
251}
252
095b0927
IT		 253static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
254 struct ib_port_attr *props)
3f89a643
AS		 255{
256 struct mlx5_ib_dev *dev = to_mdev(device);
f1b65df5 257 struct mlx5_core_dev *mdev = dev->mdev;
88621dfe 258 struct net_device *ndev, *upper;
3f89a643 259 enum ib_mtu ndev_ib_mtu;
c876a1b7 260 u16 qkey_viol_cntr;
f1b65df5 261 u32 eth_prot_oper;
095b0927 262 int err;
3f89a643 263
f1b65df5
NO		 264 /* Possible bad flows are checked before filling out props so in case
265 * of an error it will still be zeroed out.
50f22fd8 266 */
095b0927
IT		 267 err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper, port_num);
268 if (err)
269 return err;
f1b65df5
NO		 270
271 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
272 &props->active_width);
3f89a643
AS		 273
274 props->port_cap_flags |= IB_PORT_CM_SUP;
275 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
276
277 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
278 roce_address_table_size);
279 props->max_mtu = IB_MTU_4096;
280 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
281 props->pkey_tbl_len = 1;
282 props->state = IB_PORT_DOWN;
283 props->phys_state = 3;
284
c876a1b7
LR		 285 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
286 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643
AS		 287
288 ndev = mlx5_ib_get_netdev(device, port_num);
289 if (!ndev)
095b0927 290 return 0;
3f89a643 291
88621dfe
AH		 292 if (mlx5_lag_is_active(dev->mdev)) {
293 rcu_read_lock();
294 upper = netdev_master_upper_dev_get_rcu(ndev);
295 if (upper) {
296 dev_put(ndev);
297 ndev = upper;
298 dev_hold(ndev);
299 }
300 rcu_read_unlock();
301 }
302
3f89a643
AS		 303 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
304 props->state = IB_PORT_ACTIVE;
305 props->phys_state = 5;
306 }
307
308 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
309
310 dev_put(ndev);
311
312 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
095b0927 313 return 0;
3f89a643
AS		 314}
315
095b0927
IT		 316static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
317 unsigned int index, const union ib_gid *gid,
318 const struct ib_gid_attr *attr)
3cca2606 319{
095b0927
IT		 320 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
321 u8 roce_version = 0;
322 u8 roce_l3_type = 0;
323 bool vlan = false;
324 u8 mac[ETH_ALEN];
325 u16 vlan_id = 0;
326
327 if (gid) {
328 gid_type = attr->gid_type;
329 ether_addr_copy(mac, attr->ndev->dev_addr);
330
331 if (is_vlan_dev(attr->ndev)) {
332 vlan = true;
333 vlan_id = vlan_dev_vlan_id(attr->ndev);
334 }
3cca2606
AS		 335 }
336
095b0927 337 switch (gid_type) {
3cca2606 338 case IB_GID_TYPE_IB:
095b0927 339 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 340 break;
341 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 342 roce_version = MLX5_ROCE_VERSION_2;
343 if (ipv6_addr_v4mapped((void *)gid))
344 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
345 else
346 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 347 break;
348
349 default:
095b0927 350 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 351 }
352
095b0927
IT		 353 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
354 roce_l3_type, gid->raw, mac, vlan,
355 vlan_id);
3cca2606
AS		 356}
357
358static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
359 unsigned int index, const union ib_gid *gid,
360 const struct ib_gid_attr *attr,
361 __always_unused void **context)
362{
095b0927 363 return set_roce_addr(to_mdev(device), port_num, index, gid, attr);
3cca2606
AS		 364}
365
366static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
367 unsigned int index, __always_unused void **context)
368{
095b0927 369 return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL);
3cca2606
AS		 370}
371
2811ba51
AS		 372__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
373 int index)
374{
375 struct ib_gid_attr attr;
376 union ib_gid gid;
377
378 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
379 return 0;
380
381 if (!attr.ndev)
382 return 0;
383
384 dev_put(attr.ndev);
385
386 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
387 return 0;
388
389 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
390}
391
ed88451e
MD		 392int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
393 int index, enum ib_gid_type *gid_type)
394{
395 struct ib_gid_attr attr;
396 union ib_gid gid;
397 int ret;
398
399 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
400 if (ret)
401 return ret;
402
403 if (!attr.ndev)
404 return -ENODEV;
405
406 dev_put(attr.ndev);
407
408 *gid_type = attr.gid_type;
409
410 return 0;
411}
412
1b5daf11
MD		 413static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
414{
7fae6655
NO		 415 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
416 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
417 return 0;
1b5daf11
MD		 418}
419
420enum {
421 MLX5_VPORT_ACCESS_METHOD_MAD,
422 MLX5_VPORT_ACCESS_METHOD_HCA,
423 MLX5_VPORT_ACCESS_METHOD_NIC,
424};
425
426static int mlx5_get_vport_access_method(struct ib_device *ibdev)
427{
428 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
429 return MLX5_VPORT_ACCESS_METHOD_MAD;
430
ebd61f68 431 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 432 IB_LINK_LAYER_ETHERNET)
433 return MLX5_VPORT_ACCESS_METHOD_NIC;
434
435 return MLX5_VPORT_ACCESS_METHOD_HCA;
436}
437
da7525d2 438static void get_atomic_caps(struct mlx5_ib_dev *dev,
776a3906 439 u8 atomic_size_qp,
da7525d2
EBE		 440 struct ib_device_attr *props)
441{
442 u8 tmp;
443 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
da7525d2 444 u8 atomic_req_8B_endianness_mode =
bd10838a 445 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 446
447 /* Check if HW supports 8 bytes standard atomic operations and capable
448 * of host endianness respond
449 */
450 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
451 if (((atomic_operations & tmp) == tmp) &&
452 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
453 (atomic_req_8B_endianness_mode)) {
454 props->atomic_cap = IB_ATOMIC_HCA;
455 } else {
456 props->atomic_cap = IB_ATOMIC_NONE;
457 }
458}
459
776a3906
MS		 460static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
461 struct ib_device_attr *props)
462{
463 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
464
465 get_atomic_caps(dev, atomic_size_qp, props);
466}
467
468static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
469 struct ib_device_attr *props)
470{
471 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
472
473 get_atomic_caps(dev, atomic_size_qp, props);
474}
475
476bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
477{
478 struct ib_device_attr props = {};
479
480 get_atomic_caps_dc(dev, &props);
481 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
482}
1b5daf11
MD		 483static int mlx5_query_system_image_guid(struct ib_device *ibdev,
484 __be64 *sys_image_guid)
485{
486 struct mlx5_ib_dev *dev = to_mdev(ibdev);
487 struct mlx5_core_dev *mdev = dev->mdev;
488 u64 tmp;
489 int err;
490
491 switch (mlx5_get_vport_access_method(ibdev)) {
492 case MLX5_VPORT_ACCESS_METHOD_MAD:
493 return mlx5_query_mad_ifc_system_image_guid(ibdev,
494 sys_image_guid);
495
496 case MLX5_VPORT_ACCESS_METHOD_HCA:
497 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 498 break;
499
500 case MLX5_VPORT_ACCESS_METHOD_NIC:
501 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
502 break;
1b5daf11
MD		 503
504 default:
505 return -EINVAL;
506 }
3f89a643
AS		 507
508 if (!err)
509 *sys_image_guid = cpu_to_be64(tmp);
510
511 return err;
512
1b5daf11
MD		 513}
514
515static int mlx5_query_max_pkeys(struct ib_device *ibdev,
516 u16 *max_pkeys)
517{
518 struct mlx5_ib_dev *dev = to_mdev(ibdev);
519 struct mlx5_core_dev *mdev = dev->mdev;
520
521 switch (mlx5_get_vport_access_method(ibdev)) {
522 case MLX5_VPORT_ACCESS_METHOD_MAD:
523 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
524
525 case MLX5_VPORT_ACCESS_METHOD_HCA:
526 case MLX5_VPORT_ACCESS_METHOD_NIC:
527 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
528 pkey_table_size));
529 return 0;
530
531 default:
532 return -EINVAL;
533 }
534}
535
536static int mlx5_query_vendor_id(struct ib_device *ibdev,
537 u32 *vendor_id)
538{
539 struct mlx5_ib_dev *dev = to_mdev(ibdev);
540
541 switch (mlx5_get_vport_access_method(ibdev)) {
542 case MLX5_VPORT_ACCESS_METHOD_MAD:
543 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
544
545 case MLX5_VPORT_ACCESS_METHOD_HCA:
546 case MLX5_VPORT_ACCESS_METHOD_NIC:
547 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
548
549 default:
550 return -EINVAL;
551 }
552}
553
554static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
555 __be64 *node_guid)
556{
557 u64 tmp;
558 int err;
559
560 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
561 case MLX5_VPORT_ACCESS_METHOD_MAD:
562 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
563
564 case MLX5_VPORT_ACCESS_METHOD_HCA:
565 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 566 break;
567
568 case MLX5_VPORT_ACCESS_METHOD_NIC:
569 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
570 break;
1b5daf11
MD		 571
572 default:
573 return -EINVAL;
574 }
3f89a643
AS		 575
576 if (!err)
577 *node_guid = cpu_to_be64(tmp);
578
579 return err;
1b5daf11
MD		 580}
581
582struct mlx5_reg_node_desc {
bd99fdea 583 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 584};
585
586static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
587{
588 struct mlx5_reg_node_desc in;
589
590 if (mlx5_use_mad_ifc(dev))
591 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
592
593 memset(&in, 0, sizeof(in));
594
595 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
596 sizeof(struct mlx5_reg_node_desc),
597 MLX5_REG_NODE_DESC, 0, 0);
598}
599
e126ba97 600static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 601 struct ib_device_attr *props,
602 struct ib_udata *uhw)
e126ba97
EC		 603{
604 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 605 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 606 int err = -ENOMEM;
288c01b7 607 int max_sq_desc;
e126ba97
EC		 608 int max_rq_sg;
609 int max_sq_sg;
e0238a6a 610 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
402ca536
BW		 611 struct mlx5_ib_query_device_resp resp = {};
612 size_t resp_len;
613 u64 max_tso;
e126ba97 614
402ca536
BW		 615 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
616 if (uhw->outlen && uhw->outlen < resp_len)
617 return -EINVAL;
618 else
619 resp.response_length = resp_len;
620
621 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 622 return -EINVAL;
623
1b5daf11
MD		 624 memset(props, 0, sizeof(*props));
625 err = mlx5_query_system_image_guid(ibdev,
626 &props->sys_image_guid);
627 if (err)
628 return err;
e126ba97 629
1b5daf11 630 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 631 if (err)
1b5daf11 632 return err;
e126ba97 633
1b5daf11
MD		 634 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
635 if (err)
636 return err;
e126ba97 637
9603b61d
JM		 638 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
639 (fw_rev_min(dev->mdev) << 16) |
640 fw_rev_sub(dev->mdev);
e126ba97
EC		 641 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
642 IB_DEVICE_PORT_ACTIVE_EVENT |
643 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 644 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 645
646 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 647 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 648 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 649 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 650 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 651 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 652 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 653 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 654 if (MLX5_CAP_GEN(mdev, imaicl)) {
655 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
656 IB_DEVICE_MEM_WINDOW_TYPE_2B;
657 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 658 /* We support 'Gappy' memory registration too */
659 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 660 }
e126ba97 661 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 662 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 663 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
664 /* At this stage no support for signature handover */
665 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
666 IB_PROT_T10DIF_TYPE_2 |
667 IB_PROT_T10DIF_TYPE_3;
668 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
669 IB_GUARD_T10DIF_CSUM;
670 }
938fe83c 671 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 672 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 673
402ca536 674 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
e8161334
NO		 675 if (MLX5_CAP_ETH(mdev, csum_cap)) {
676 /* Legacy bit to support old userspace libraries */
88115fe7 677 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 678 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
679 }
680
681 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
682 props->raw_packet_caps |=
683 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 684
402ca536
BW		 685 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
686 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
687 if (max_tso) {
688 resp.tso_caps.max_tso = 1 << max_tso;
689 resp.tso_caps.supported_qpts |=
690 1 << IB_QPT_RAW_PACKET;
691 resp.response_length += sizeof(resp.tso_caps);
692 }
693 }
31f69a82
YH		 694
695 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
696 resp.rss_caps.rx_hash_function =
697 MLX5_RX_HASH_FUNC_TOEPLITZ;
698 resp.rss_caps.rx_hash_fields_mask =
699 MLX5_RX_HASH_SRC_IPV4 |
700 MLX5_RX_HASH_DST_IPV4 |
701 MLX5_RX_HASH_SRC_IPV6 |
702 MLX5_RX_HASH_DST_IPV6 |
703 MLX5_RX_HASH_SRC_PORT_TCP |
704 MLX5_RX_HASH_DST_PORT_TCP |
705 MLX5_RX_HASH_SRC_PORT_UDP |
4e2b53a5
MG		 706 MLX5_RX_HASH_DST_PORT_UDP |
707 MLX5_RX_HASH_INNER;
31f69a82
YH		 708 resp.response_length += sizeof(resp.rss_caps);
709 }
710 } else {
711 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
712 resp.response_length += sizeof(resp.tso_caps);
713 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
714 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 715 }
716
f0313965
ES		 717 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
718 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
719 props->device_cap_flags |= IB_DEVICE_UD_TSO;
720 }
721
03404e8a
MG		 722 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
723 MLX5_CAP_GEN(dev->mdev, general_notification_event))
724 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
725
1d54f890
YH		 726 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
727 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
728 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
729
cff5a0f3 730 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
e8161334
NO		 731 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
732 /* Legacy bit to support old userspace libraries */
cff5a0f3 733 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 734 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
735 }
cff5a0f3 736
da6d6ba3
MG		 737 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
738 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
739
b1383aa6
NO		 740 if (MLX5_CAP_GEN(mdev, end_pad))
741 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
742
1b5daf11
MD		 743 props->vendor_part_id = mdev->pdev->device;
744 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 745
746 props->max_mr_size = ~0ull;
e0238a6a 747 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 748 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
749 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
750 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
751 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 752 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
753 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
754 sizeof(struct mlx5_wqe_raddr_seg)) /
755 sizeof(struct mlx5_wqe_data_seg);
e126ba97 756 props->max_sge = min(max_rq_sg, max_sq_sg);
986ef95e 757 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 758 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 759 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 760 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
761 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
762 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
763 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
764 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
765 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
766 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 767 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 768 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 769 props->max_fast_reg_page_list_len =
770 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
776a3906 771 get_atomic_caps_qp(dev, props);
81bea28f 772 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 773 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
774 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 775 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
776 props->max_mcast_grp;
777 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 778 props->max_ah = INT_MAX;
7c60bcbb
MB		 779 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
780 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 781
8cdd312c 782#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 783 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 784 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
785 props->odp_caps = dev->odp_caps;
786#endif
787
051f2630
LR		 788 if (MLX5_CAP_GEN(mdev, cd))
789 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
790
eff901d3
EC		 791 if (!mlx5_core_is_pf(mdev))
792 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
793
31f69a82
YH		 794 if (mlx5_ib_port_link_layer(ibdev, 1) ==
795 IB_LINK_LAYER_ETHERNET) {
796 props->rss_caps.max_rwq_indirection_tables =
797 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
798 props->rss_caps.max_rwq_indirection_table_size =
799 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
800 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
801 props->max_wq_type_rq =
802 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
803 }
804
eb761894 805 if (MLX5_CAP_GEN(mdev, tag_matching)) {
78b1beb0
LR		 806 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
807 props->tm_caps.max_num_tags =
eb761894 808 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
78b1beb0
LR		 809 props->tm_caps.flags = IB_TM_CAP_RC;
810 props->tm_caps.max_ops =
eb761894 811 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
78b1beb0 812 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
eb761894
AK		 813 }
814
87ab3f52
YC		 815 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
816 props->cq_caps.max_cq_moderation_count =
817 MLX5_MAX_CQ_COUNT;
818 props->cq_caps.max_cq_moderation_period =
819 MLX5_MAX_CQ_PERIOD;
820 }
821
7e43a2a5
BW		 822 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
823 resp.cqe_comp_caps.max_num =
824 MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
825 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
826 resp.cqe_comp_caps.supported_format =
827 MLX5_IB_CQE_RES_FORMAT_HASH |
828 MLX5_IB_CQE_RES_FORMAT_CSUM;
829 resp.response_length += sizeof(resp.cqe_comp_caps);
830 }
831
d949167d
BW		 832 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) {
833 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
834 MLX5_CAP_GEN(mdev, qos)) {
835 resp.packet_pacing_caps.qp_rate_limit_max =
836 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
837 resp.packet_pacing_caps.qp_rate_limit_min =
838 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
839 resp.packet_pacing_caps.supported_qpts |=
840 1 << IB_QPT_RAW_PACKET;
841 }
842 resp.response_length += sizeof(resp.packet_pacing_caps);
843 }
844
9f885201
LR		 845 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
846 uhw->outlen)) {
795b609c
BW		 847 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
848 resp.mlx5_ib_support_multi_pkt_send_wqes =
849 MLX5_IB_ALLOW_MPW;
050da902
BW		 850
851 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
852 resp.mlx5_ib_support_multi_pkt_send_wqes |=
853 MLX5_IB_SUPPORT_EMPW;
854
9f885201
LR		 855 resp.response_length +=
856 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
857 }
858
de57f2ad
GL		 859 if (field_avail(typeof(resp), flags, uhw->outlen)) {
860 resp.response_length += sizeof(resp.flags);
7a0c8f42 861
de57f2ad
GL		 862 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
863 resp.flags |=
864 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
7a0c8f42
GL		 865
866 if (MLX5_CAP_GEN(mdev, cqe_128_always))
867 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
de57f2ad 868 }
9f885201 869
96dc3fc5
NO		 870 if (field_avail(typeof(resp), sw_parsing_caps,
871 uhw->outlen)) {
872 resp.response_length += sizeof(resp.sw_parsing_caps);
873 if (MLX5_CAP_ETH(mdev, swp)) {
874 resp.sw_parsing_caps.sw_parsing_offloads |=
875 MLX5_IB_SW_PARSING;
876
877 if (MLX5_CAP_ETH(mdev, swp_csum))
878 resp.sw_parsing_caps.sw_parsing_offloads |=
879 MLX5_IB_SW_PARSING_CSUM;
880
881 if (MLX5_CAP_ETH(mdev, swp_lso))
882 resp.sw_parsing_caps.sw_parsing_offloads |=
883 MLX5_IB_SW_PARSING_LSO;
884
885 if (resp.sw_parsing_caps.sw_parsing_offloads)
886 resp.sw_parsing_caps.supported_qpts =
887 BIT(IB_QPT_RAW_PACKET);
888 }
889 }
890
b4f34597
NO		 891 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen)) {
892 resp.response_length += sizeof(resp.striding_rq_caps);
893 if (MLX5_CAP_GEN(mdev, striding_rq)) {
894 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
895 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
896 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
897 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
898 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
899 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
900 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
901 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
902 resp.striding_rq_caps.supported_qpts =
903 BIT(IB_QPT_RAW_PACKET);
904 }
905 }
906
f95ef6cb
MG		 907 if (field_avail(typeof(resp), tunnel_offloads_caps,
908 uhw->outlen)) {
909 resp.response_length += sizeof(resp.tunnel_offloads_caps);
910 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
911 resp.tunnel_offloads_caps |=
912 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
913 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
914 resp.tunnel_offloads_caps |=
915 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
916 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
917 resp.tunnel_offloads_caps |=
918 MLX5_IB_TUNNELED_OFFLOADS_GRE;
919 }
920
402ca536
BW		 921 if (uhw->outlen) {
922 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
923
924 if (err)
925 return err;
926 }
927
1b5daf11 928 return 0;
e126ba97
EC		 929}
930
1b5daf11
MD		 931enum mlx5_ib_width {
932 MLX5_IB_WIDTH_1X = 1 << 0,
933 MLX5_IB_WIDTH_2X = 1 << 1,
934 MLX5_IB_WIDTH_4X = 1 << 2,
935 MLX5_IB_WIDTH_8X = 1 << 3,
936 MLX5_IB_WIDTH_12X = 1 << 4
937};
938
939static int translate_active_width(struct ib_device *ibdev, u8 active_width,
940 u8 *ib_width)
e126ba97
EC		 941{
942 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 943 int err = 0;
944
945 if (active_width & MLX5_IB_WIDTH_1X) {
946 *ib_width = IB_WIDTH_1X;
947 } else if (active_width & MLX5_IB_WIDTH_2X) {
948 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
949 (int)active_width);
950 err = -EINVAL;
951 } else if (active_width & MLX5_IB_WIDTH_4X) {
952 *ib_width = IB_WIDTH_4X;
953 } else if (active_width & MLX5_IB_WIDTH_8X) {
954 *ib_width = IB_WIDTH_8X;
955 } else if (active_width & MLX5_IB_WIDTH_12X) {
956 *ib_width = IB_WIDTH_12X;
957 } else {
958 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
959 (int)active_width);
960 err = -EINVAL;
e126ba97
EC		 961 }
962
1b5daf11
MD		 963 return err;
964}
e126ba97 965
1b5daf11
MD		 966static int mlx5_mtu_to_ib_mtu(int mtu)
967{
968 switch (mtu) {
969 case 256: return 1;
970 case 512: return 2;
971 case 1024: return 3;
972 case 2048: return 4;
973 case 4096: return 5;
974 default:
975 pr_warn("invalid mtu\n");
976 return -1;
e126ba97 977 }
1b5daf11 978}
e126ba97 979
1b5daf11
MD		 980enum ib_max_vl_num {
981 __IB_MAX_VL_0 = 1,
982 __IB_MAX_VL_0_1 = 2,
983 __IB_MAX_VL_0_3 = 3,
984 __IB_MAX_VL_0_7 = 4,
985 __IB_MAX_VL_0_14 = 5,
986};
e126ba97 987
1b5daf11
MD		 988enum mlx5_vl_hw_cap {
989 MLX5_VL_HW_0 = 1,
990 MLX5_VL_HW_0_1 = 2,
991 MLX5_VL_HW_0_2 = 3,
992 MLX5_VL_HW_0_3 = 4,
993 MLX5_VL_HW_0_4 = 5,
994 MLX5_VL_HW_0_5 = 6,
995 MLX5_VL_HW_0_6 = 7,
996 MLX5_VL_HW_0_7 = 8,
997 MLX5_VL_HW_0_14 = 15
998};
e126ba97 999
1b5daf11
MD		 1000static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1001 u8 *max_vl_num)
1002{
1003 switch (vl_hw_cap) {
1004 case MLX5_VL_HW_0:
1005 *max_vl_num = __IB_MAX_VL_0;
1006 break;
1007 case MLX5_VL_HW_0_1:
1008 *max_vl_num = __IB_MAX_VL_0_1;
1009 break;
1010 case MLX5_VL_HW_0_3:
1011 *max_vl_num = __IB_MAX_VL_0_3;
1012 break;
1013 case MLX5_VL_HW_0_7:
1014 *max_vl_num = __IB_MAX_VL_0_7;
1015 break;
1016 case MLX5_VL_HW_0_14:
1017 *max_vl_num = __IB_MAX_VL_0_14;
1018 break;
e126ba97 1019
1b5daf11
MD		 1020 default:
1021 return -EINVAL;
e126ba97 1022 }
e126ba97 1023
1b5daf11 1024 return 0;
e126ba97
EC		 1025}
1026
1b5daf11
MD		 1027static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1028 struct ib_port_attr *props)
e126ba97 1029{
1b5daf11
MD		 1030 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1031 struct mlx5_core_dev *mdev = dev->mdev;
1032 struct mlx5_hca_vport_context *rep;
046339ea
SM		 1033 u16 max_mtu;
1034 u16 oper_mtu;
1b5daf11
MD		 1035 int err;
1036 u8 ib_link_width_oper;
1037 u8 vl_hw_cap;
e126ba97 1038
1b5daf11
MD		 1039 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1040 if (!rep) {
1041 err = -ENOMEM;
e126ba97 1042 goto out;
e126ba97 1043 }
e126ba97 1044
c4550c63 1045 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 1046
1b5daf11 1047 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 1048 if (err)
1049 goto out;
1050
1b5daf11
MD		 1051 props->lid = rep->lid;
1052 props->lmc = rep->lmc;
1053 props->sm_lid = rep->sm_lid;
1054 props->sm_sl = rep->sm_sl;
1055 props->state = rep->vport_state;
1056 props->phys_state = rep->port_physical_state;
1057 props->port_cap_flags = rep->cap_mask1;
1058 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1059 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1060 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1061 props->bad_pkey_cntr = rep->pkey_violation_counter;
1062 props->qkey_viol_cntr = rep->qkey_violation_counter;
1063 props->subnet_timeout = rep->subnet_timeout;
1064 props->init_type_reply = rep->init_type_reply;
eff901d3 1065 props->grh_required = rep->grh_required;
e126ba97 1066
1b5daf11
MD		 1067 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1068 if (err)
e126ba97 1069 goto out;
e126ba97 1070
1b5daf11
MD		 1071 err = translate_active_width(ibdev, ib_link_width_oper,
1072 &props->active_width);
1073 if (err)
1074 goto out;
d5beb7f2 1075 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 1076 if (err)
1077 goto out;
1078
facc9699 1079 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 1080
1b5daf11 1081 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 1082
facc9699 1083 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 1084
1b5daf11 1085 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1086
1b5daf11
MD		 1087 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1088 if (err)
1089 goto out;
e126ba97 1090
1b5daf11
MD		 1091 err = translate_max_vl_num(ibdev, vl_hw_cap,
1092 &props->max_vl_num);
e126ba97 1093out:
1b5daf11 1094 kfree(rep);
e126ba97
EC		 1095 return err;
1096}
1097
1b5daf11
MD		 1098int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1099 struct ib_port_attr *props)
e126ba97 1100{
095b0927
IT		 1101 unsigned int count;
1102 int ret;
1103
1b5daf11
MD		 1104 switch (mlx5_get_vport_access_method(ibdev)) {
1105 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1106 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1107 break;
e126ba97 1108
1b5daf11 1109 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1110 ret = mlx5_query_hca_port(ibdev, port, props);
1111 break;
e126ba97 1112
3f89a643 1113 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1114 ret = mlx5_query_port_roce(ibdev, port, props);
1115 break;
3f89a643 1116
1b5daf11 1117 default:
095b0927
IT		 1118 ret = -EINVAL;
1119 }
1120
1121 if (!ret && props) {
1122 count = mlx5_core_reserved_gids_count(to_mdev(ibdev)->mdev);
1123 props->gid_tbl_len -= count;
1b5daf11 1124 }
095b0927 1125 return ret;
1b5daf11 1126}
e126ba97 1127
1b5daf11
MD		 1128static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1129 union ib_gid *gid)
1130{
1131 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1132 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1133
1b5daf11
MD		 1134 switch (mlx5_get_vport_access_method(ibdev)) {
1135 case MLX5_VPORT_ACCESS_METHOD_MAD:
1136 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1137
1b5daf11
MD		 1138 case MLX5_VPORT_ACCESS_METHOD_HCA:
1139 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1140
1141 default:
1142 return -EINVAL;
1143 }
e126ba97 1144
e126ba97
EC		 1145}
1146
1b5daf11
MD		 1147static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1148 u16 *pkey)
1149{
1150 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1151 struct mlx5_core_dev *mdev = dev->mdev;
1152
1153 switch (mlx5_get_vport_access_method(ibdev)) {
1154 case MLX5_VPORT_ACCESS_METHOD_MAD:
1155 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1156
1157 case MLX5_VPORT_ACCESS_METHOD_HCA:
1158 case MLX5_VPORT_ACCESS_METHOD_NIC:
1159 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
1160 pkey);
1161 default:
1162 return -EINVAL;
1163 }
1164}
e126ba97
EC		 1165
1166static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1167 struct ib_device_modify *props)
1168{
1169 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1170 struct mlx5_reg_node_desc in;
1171 struct mlx5_reg_node_desc out;
1172 int err;
1173
1174 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1175 return -EOPNOTSUPP;
1176
1177 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1178 return 0;
1179
1180 /*
1181 * If possible, pass node desc to FW, so it can generate
1182 * a 144 trap. If cmd fails, just ignore.
1183 */
bd99fdea 1184 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1185 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1186 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1187 if (err)
1188 return err;
1189
bd99fdea 1190 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1191
1192 return err;
1193}
1194
cdbe33d0
EC		 1195static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1196 u32 value)
1197{
1198 struct mlx5_hca_vport_context ctx = {};
1199 int err;
1200
1201 err = mlx5_query_hca_vport_context(dev->mdev, 0,
1202 port_num, 0, &ctx);
1203 if (err)
1204 return err;
1205
1206 if (~ctx.cap_mask1_perm & mask) {
1207 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1208 mask, ctx.cap_mask1_perm);
1209 return -EINVAL;
1210 }
1211
1212 ctx.cap_mask1 = value;
1213 ctx.cap_mask1_perm = mask;
1214 err = mlx5_core_modify_hca_vport_context(dev->mdev, 0,
1215 port_num, 0, &ctx);
1216
1217 return err;
1218}
1219
e126ba97
EC		 1220static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1221 struct ib_port_modify *props)
1222{
1223 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1224 struct ib_port_attr attr;
1225 u32 tmp;
1226 int err;
cdbe33d0
EC		 1227 u32 change_mask;
1228 u32 value;
1229 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1230 IB_LINK_LAYER_INFINIBAND);
1231
ec255879
MD		 1232 /* CM layer calls ib_modify_port() regardless of the link layer. For
1233 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1234 */
1235 if (!is_ib)
1236 return 0;
1237
cdbe33d0
EC		 1238 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1239 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1240 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1241 return set_port_caps_atomic(dev, port, change_mask, value);
1242 }
e126ba97
EC		 1243
1244 mutex_lock(&dev->cap_mask_mutex);
1245
c4550c63 1246 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1247 if (err)
1248 goto out;
1249
1250 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1251 ~props->clr_port_cap_mask;
1252
9603b61d 1253 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1254
1255out:
1256 mutex_unlock(&dev->cap_mask_mutex);
1257 return err;
1258}
1259
30aa60b3
EC		 1260static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1261{
1262 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1263 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1264}
1265
31a78a5a
YH		 1266static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1267{
1268 /* Large page with non 4k uar support might limit the dynamic size */
1269 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1270 return MLX5_MIN_DYN_BFREGS;
1271
1272 return MLX5_MAX_DYN_BFREGS;
1273}
1274
b037c29a
EC		 1275static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1276 struct mlx5_ib_alloc_ucontext_req_v2 *req,
31a78a5a 1277 struct mlx5_bfreg_info *bfregi)
b037c29a
EC		 1278{
1279 int uars_per_sys_page;
1280 int bfregs_per_sys_page;
1281 int ref_bfregs = req->total_num_bfregs;
1282
1283 if (req->total_num_bfregs == 0)
1284 return -EINVAL;
1285
1286 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1287 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1288
1289 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1290 return -ENOMEM;
1291
1292 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1293 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
31a78a5a 1294 /* This holds the required static allocation asked by the user */
b037c29a 1295 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
b037c29a
EC		 1296 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1297 return -EINVAL;
1298
31a78a5a
YH		 1299 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1300 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1301 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1302 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1303
1304 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
b037c29a
EC		 1305 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1306 lib_uar_4k ? "yes" : "no", ref_bfregs,
31a78a5a
YH		 1307 req->total_num_bfregs, bfregi->total_num_bfregs,
1308 bfregi->num_sys_pages);
b037c29a
EC		 1309
1310 return 0;
1311}
1312
1313static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1314{
1315 struct mlx5_bfreg_info *bfregi;
1316 int err;
1317 int i;
1318
1319 bfregi = &context->bfregi;
31a78a5a 1320 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
b037c29a
EC		 1321 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1322 if (err)
1323 goto error;
1324
1325 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1326 }
4ed131d0
YH		 1327
1328 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1329 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1330
b037c29a
EC		 1331 return 0;
1332
1333error:
1334 for (--i; i >= 0; i--)
1335 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1336 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1337
1338 return err;
1339}
1340
1341static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1342{
1343 struct mlx5_bfreg_info *bfregi;
1344 int err;
1345 int i;
1346
1347 bfregi = &context->bfregi;
4ed131d0
YH		 1348 for (i = 0; i < bfregi->num_sys_pages; i++) {
1349 if (i < bfregi->num_static_sys_pages ||
1350 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) {
1351 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1352 if (err) {
1353 mlx5_ib_warn(dev, "failed to free uar %d, err=%d\n", i, err);
1354 return err;
1355 }
b037c29a
EC		 1356 }
1357 }
4ed131d0 1358
b037c29a
EC		 1359 return 0;
1360}
1361
c85023e1
HN		 1362static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1363{
1364 int err;
1365
1366 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1367 if (err)
1368 return err;
1369
1370 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1371 !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1372 return err;
1373
1374 mutex_lock(&dev->lb_mutex);
1375 dev->user_td++;
1376
1377 if (dev->user_td == 2)
1378 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1379
1380 mutex_unlock(&dev->lb_mutex);
1381 return err;
1382}
1383
1384static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1385{
1386 mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1387
1388 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1389 !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1390 return;
1391
1392 mutex_lock(&dev->lb_mutex);
1393 dev->user_td--;
1394
1395 if (dev->user_td < 2)
1396 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1397
1398 mutex_unlock(&dev->lb_mutex);
1399}
1400
e126ba97
EC		 1401static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1402 struct ib_udata *udata)
1403{
1404 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1405 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1406 struct mlx5_ib_alloc_ucontext_resp resp = {};
e126ba97 1407 struct mlx5_ib_ucontext *context;
2f5ff264 1408 struct mlx5_bfreg_info *bfregi;
78c0f98c 1409 int ver;
e126ba97 1410 int err;
a168a41c
MD		 1411 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1412 max_cqe_version);
b037c29a 1413 bool lib_uar_4k;
e126ba97
EC		 1414
1415 if (!dev->ib_active)
1416 return ERR_PTR(-EAGAIN);
1417
e093111d 1418 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1419 ver = 0;
e093111d 1420 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1421 ver = 2;
1422 else
1423 return ERR_PTR(-EINVAL);
1424
e093111d 1425 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97
EC		 1426 if (err)
1427 return ERR_PTR(err);
1428
b368d7cb 1429 if (req.flags)
78c0f98c
EC		 1430 return ERR_PTR(-EINVAL);
1431
f72300c5 1432 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 1433 return ERR_PTR(-EOPNOTSUPP);
1434
2f5ff264
EC		 1435 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1436 MLX5_NON_FP_BFREGS_PER_UAR);
1437 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
e126ba97
EC		 1438 return ERR_PTR(-EINVAL);
1439
938fe83c 1440 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1441 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1442 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1443 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1444 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1445 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1446 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1447 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1448 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1449 resp.cqe_version = min_t(__u8,
1450 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1451 req.max_cqe_version);
30aa60b3
EC		 1452 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1453 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1454 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1455 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1456 resp.response_length = min(offsetof(typeof(resp), response_length) +
1457 sizeof(resp.response_length), udata->outlen);
e126ba97
EC		 1458
1459 context = kzalloc(sizeof(*context), GFP_KERNEL);
1460 if (!context)
1461 return ERR_PTR(-ENOMEM);
1462
30aa60b3 1463 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1464 bfregi = &context->bfregi;
b037c29a
EC		 1465
1466 /* updates req->total_num_bfregs */
31a78a5a 1467 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
b037c29a 1468 if (err)
e126ba97 1469 goto out_ctx;
e126ba97 1470
b037c29a
EC		 1471 mutex_init(&bfregi->lock);
1472 bfregi->lib_uar_4k = lib_uar_4k;
31a78a5a 1473 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1474 GFP_KERNEL);
b037c29a 1475 if (!bfregi->count) {
e126ba97 1476 err = -ENOMEM;
b037c29a 1477 goto out_ctx;
e126ba97
EC		 1478 }
1479
b037c29a
EC		 1480 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1481 sizeof(*bfregi->sys_pages),
1482 GFP_KERNEL);
1483 if (!bfregi->sys_pages) {
e126ba97 1484 err = -ENOMEM;
b037c29a 1485 goto out_count;
e126ba97
EC		 1486 }
1487
b037c29a
EC		 1488 err = allocate_uars(dev, context);
1489 if (err)
1490 goto out_sys_pages;
e126ba97 1491
b4cfe447
HE		 1492#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1493 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1494#endif
1495
7d0cc6ed
AK		 1496 context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1497 if (!context->upd_xlt_page) {
1498 err = -ENOMEM;
1499 goto out_uars;
1500 }
1501 mutex_init(&context->upd_xlt_page_mutex);
1502
146d2f1a 1503 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
c85023e1 1504 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
146d2f1a 1505 if (err)
7d0cc6ed 1506 goto out_page;
146d2f1a 1507 }
1508
7c2344c3 1509 INIT_LIST_HEAD(&context->vma_private_list);
ad9a3668 1510 mutex_init(&context->vma_private_list_mutex);
e126ba97
EC		 1511 INIT_LIST_HEAD(&context->db_page_list);
1512 mutex_init(&context->db_page_mutex);
1513
2f5ff264 1514 resp.tot_bfregs = req.total_num_bfregs;
938fe83c 1515 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
b368d7cb 1516
f72300c5
HA		 1517 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1518 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1519
402ca536 1520 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1521 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1522 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1523 resp.response_length += sizeof(resp.cmds_supp_uhw);
1524 }
1525
78984898
OG		 1526 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1527 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1528 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1529 resp.eth_min_inline++;
1530 }
1531 resp.response_length += sizeof(resp.eth_min_inline);
1532 }
1533
bc5c6eed
NO		 1534 /*
1535 * We don't want to expose information from the PCI bar that is located
1536 * after 4096 bytes, so if the arch only supports larger pages, let's
1537 * pretend we don't support reading the HCA's core clock. This is also
1538 * forced by mmap function.
1539 */
de8d6e02
EC		 1540 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1541 if (PAGE_SIZE <= 4096) {
1542 resp.comp_mask |=
1543 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1544 resp.hca_core_clock_offset =
1545 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1546 }
f72300c5 1547 resp.response_length += sizeof(resp.hca_core_clock_offset) +
402ca536 1548 sizeof(resp.reserved2);
b368d7cb
MB		 1549 }
1550
30aa60b3
EC		 1551 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1552 resp.response_length += sizeof(resp.log_uar_size);
1553
1554 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1555 resp.response_length += sizeof(resp.num_uars_per_page);
1556
31a78a5a
YH		 1557 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1558 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1559 resp.response_length += sizeof(resp.num_dyn_bfregs);
1560 }
1561
b368d7cb 1562 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1563 if (err)
146d2f1a 1564 goto out_td;
e126ba97 1565
2f5ff264
EC		 1566 bfregi->ver = ver;
1567 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1568 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1569 context->lib_caps = req.lib_caps;
1570 print_lib_caps(dev, context->lib_caps);
f72300c5 1571
e126ba97
EC		 1572 return &context->ibucontext;
1573
146d2f1a 1574out_td:
1575 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
c85023e1 1576 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1577
7d0cc6ed
AK		 1578out_page:
1579 free_page(context->upd_xlt_page);
1580
e126ba97 1581out_uars:
b037c29a 1582 deallocate_uars(dev, context);
e126ba97 1583
b037c29a
EC		 1584out_sys_pages:
1585 kfree(bfregi->sys_pages);
e126ba97 1586
b037c29a
EC		 1587out_count:
1588 kfree(bfregi->count);
e126ba97
EC		 1589
1590out_ctx:
1591 kfree(context);
b037c29a 1592
e126ba97
EC		 1593 return ERR_PTR(err);
1594}
1595
1596static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1597{
1598 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1599 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 1600 struct mlx5_bfreg_info *bfregi;
e126ba97 1601
b037c29a 1602 bfregi = &context->bfregi;
146d2f1a 1603 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
c85023e1 1604 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1605
7d0cc6ed 1606 free_page(context->upd_xlt_page);
b037c29a
EC		 1607 deallocate_uars(dev, context);
1608 kfree(bfregi->sys_pages);
2f5ff264 1609 kfree(bfregi->count);
e126ba97
EC		 1610 kfree(context);
1611
1612 return 0;
1613}
1614
b037c29a 1615static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
4ed131d0 1616 int uar_idx)
e126ba97 1617{
b037c29a
EC		 1618 int fw_uars_per_page;
1619
1620 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1621
4ed131d0 1622 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
e126ba97
EC		 1623}
1624
1625static int get_command(unsigned long offset)
1626{
1627 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1628}
1629
1630static int get_arg(unsigned long offset)
1631{
1632 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1633}
1634
1635static int get_index(unsigned long offset)
1636{
1637 return get_arg(offset);
1638}
1639
4ed131d0
YH		 1640/* Index resides in an extra byte to enable larger values than 255 */
1641static int get_extended_index(unsigned long offset)
1642{
1643 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1644}
1645
7c2344c3
MG		 1646static void mlx5_ib_vma_open(struct vm_area_struct *area)
1647{
1648 /* vma_open is called when a new VMA is created on top of our VMA. This
1649 * is done through either mremap flow or split_vma (usually due to
1650 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1651 * as this VMA is strongly hardware related. Therefore we set the
1652 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1653 * calling us again and trying to do incorrect actions. We assume that
1654 * the original VMA size is exactly a single page, and therefore all
1655 * "splitting" operation will not happen to it.
1656 */
1657 area->vm_ops = NULL;
1658}
1659
1660static void mlx5_ib_vma_close(struct vm_area_struct *area)
1661{
1662 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1663
1664 /* It's guaranteed that all VMAs opened on a FD are closed before the
1665 * file itself is closed, therefore no sync is needed with the regular
1666 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1667 * However need a sync with accessing the vma as part of
1668 * mlx5_ib_disassociate_ucontext.
1669 * The close operation is usually called under mm->mmap_sem except when
1670 * process is exiting.
1671 * The exiting case is handled explicitly as part of
1672 * mlx5_ib_disassociate_ucontext.
1673 */
1674 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1675
1676 /* setting the vma context pointer to null in the mlx5_ib driver's
1677 * private data, to protect a race condition in
1678 * mlx5_ib_disassociate_ucontext().
1679 */
1680 mlx5_ib_vma_priv_data->vma = NULL;
ad9a3668 1681 mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
7c2344c3 1682 list_del(&mlx5_ib_vma_priv_data->list);
ad9a3668 1683 mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
7c2344c3
MG		 1684 kfree(mlx5_ib_vma_priv_data);
1685}
1686
1687static const struct vm_operations_struct mlx5_ib_vm_ops = {
1688 .open = mlx5_ib_vma_open,
1689 .close = mlx5_ib_vma_close
1690};
1691
1692static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1693 struct mlx5_ib_ucontext *ctx)
1694{
1695 struct mlx5_ib_vma_private_data *vma_prv;
1696 struct list_head *vma_head = &ctx->vma_private_list;
1697
1698 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1699 if (!vma_prv)
1700 return -ENOMEM;
1701
1702 vma_prv->vma = vma;
ad9a3668 1703 vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
7c2344c3
MG		 1704 vma->vm_private_data = vma_prv;
1705 vma->vm_ops = &mlx5_ib_vm_ops;
1706
ad9a3668 1707 mutex_lock(&ctx->vma_private_list_mutex);
7c2344c3 1708 list_add(&vma_prv->list, vma_head);
ad9a3668 1709 mutex_unlock(&ctx->vma_private_list_mutex);
7c2344c3
MG		 1710
1711 return 0;
1712}
1713
1714static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1715{
1716 int ret;
1717 struct vm_area_struct *vma;
1718 struct mlx5_ib_vma_private_data *vma_private, *n;
1719 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1720 struct task_struct *owning_process = NULL;
1721 struct mm_struct *owning_mm = NULL;
1722
1723 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1724 if (!owning_process)
1725 return;
1726
1727 owning_mm = get_task_mm(owning_process);
1728 if (!owning_mm) {
1729 pr_info("no mm, disassociate ucontext is pending task termination\n");
1730 while (1) {
1731 put_task_struct(owning_process);
1732 usleep_range(1000, 2000);
1733 owning_process = get_pid_task(ibcontext->tgid,
1734 PIDTYPE_PID);
1735 if (!owning_process ||
1736 owning_process->state == TASK_DEAD) {
1737 pr_info("disassociate ucontext done, task was terminated\n");
1738 /* in case task was dead need to release the
1739 * task struct.
1740 */
1741 if (owning_process)
1742 put_task_struct(owning_process);
1743 return;
1744 }
1745 }
1746 }
1747
1748 /* need to protect from a race on closing the vma as part of
1749 * mlx5_ib_vma_close.
1750 */
ecc7d83b 1751 down_write(&owning_mm->mmap_sem);
ad9a3668 1752 mutex_lock(&context->vma_private_list_mutex);
7c2344c3
MG		 1753 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1754 list) {
1755 vma = vma_private->vma;
1756 ret = zap_vma_ptes(vma, vma->vm_start,
1757 PAGE_SIZE);
1758 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1759 /* context going to be destroyed, should
1760 * not access ops any more.
1761 */
13776612 1762 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
7c2344c3
MG		 1763 vma->vm_ops = NULL;
1764 list_del(&vma_private->list);
1765 kfree(vma_private);
1766 }
ad9a3668 1767 mutex_unlock(&context->vma_private_list_mutex);
ecc7d83b 1768 up_write(&owning_mm->mmap_sem);
7c2344c3
MG		 1769 mmput(owning_mm);
1770 put_task_struct(owning_process);
1771}
1772
37aa5c36
GL		 1773static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1774{
1775 switch (cmd) {
1776 case MLX5_IB_MMAP_WC_PAGE:
1777 return "WC";
1778 case MLX5_IB_MMAP_REGULAR_PAGE:
1779 return "best effort WC";
1780 case MLX5_IB_MMAP_NC_PAGE:
1781 return "NC";
1782 default:
1783 return NULL;
1784 }
1785}
1786
1787static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 1788 struct vm_area_struct *vma,
1789 struct mlx5_ib_ucontext *context)
37aa5c36 1790{
2f5ff264 1791 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 1792 int err;
1793 unsigned long idx;
1794 phys_addr_t pfn, pa;
1795 pgprot_t prot;
4ed131d0
YH		 1796 u32 bfreg_dyn_idx = 0;
1797 u32 uar_index;
1798 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
1799 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
1800 bfregi->num_static_sys_pages;
b037c29a
EC		 1801
1802 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1803 return -EINVAL;
1804
4ed131d0
YH		 1805 if (dyn_uar)
1806 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
1807 else
1808 idx = get_index(vma->vm_pgoff);
1809
1810 if (idx >= max_valid_idx) {
1811 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
1812 idx, max_valid_idx);
b037c29a
EC		 1813 return -EINVAL;
1814 }
37aa5c36
GL		 1815
1816 switch (cmd) {
1817 case MLX5_IB_MMAP_WC_PAGE:
4ed131d0 1818 case MLX5_IB_MMAP_ALLOC_WC:
37aa5c36
GL		 1819/* Some architectures don't support WC memory */
1820#if defined(CONFIG_X86)
1821 if (!pat_enabled())
1822 return -EPERM;
1823#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1824 return -EPERM;
1825#endif
1826 /* fall through */
1827 case MLX5_IB_MMAP_REGULAR_PAGE:
1828 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1829 prot = pgprot_writecombine(vma->vm_page_prot);
1830 break;
1831 case MLX5_IB_MMAP_NC_PAGE:
1832 prot = pgprot_noncached(vma->vm_page_prot);
1833 break;
1834 default:
1835 return -EINVAL;
1836 }
1837
4ed131d0
YH		 1838 if (dyn_uar) {
1839 int uars_per_page;
1840
1841 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
1842 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
1843 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
1844 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
1845 bfreg_dyn_idx, bfregi->total_num_bfregs);
1846 return -EINVAL;
1847 }
1848
1849 mutex_lock(&bfregi->lock);
1850 /* Fail if uar already allocated, first bfreg index of each
1851 * page holds its count.
1852 */
1853 if (bfregi->count[bfreg_dyn_idx]) {
1854 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
1855 mutex_unlock(&bfregi->lock);
1856 return -EINVAL;
1857 }
1858
1859 bfregi->count[bfreg_dyn_idx]++;
1860 mutex_unlock(&bfregi->lock);
1861
1862 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
1863 if (err) {
1864 mlx5_ib_warn(dev, "UAR alloc failed\n");
1865 goto free_bfreg;
1866 }
1867 } else {
1868 uar_index = bfregi->sys_pages[idx];
1869 }
1870
1871 pfn = uar_index2pfn(dev, uar_index);
37aa5c36
GL		 1872 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1873
1874 vma->vm_page_prot = prot;
1875 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1876 PAGE_SIZE, vma->vm_page_prot);
1877 if (err) {
1878 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1879 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
4ed131d0
YH		 1880 err = -EAGAIN;
1881 goto err;
37aa5c36
GL		 1882 }
1883
1884 pa = pfn << PAGE_SHIFT;
1885 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1886 vma->vm_start, &pa);
1887
4ed131d0
YH		 1888 err = mlx5_ib_set_vma_data(vma, context);
1889 if (err)
1890 goto err;
1891
1892 if (dyn_uar)
1893 bfregi->sys_pages[idx] = uar_index;
1894 return 0;
1895
1896err:
1897 if (!dyn_uar)
1898 return err;
1899
1900 mlx5_cmd_free_uar(dev->mdev, idx);
1901
1902free_bfreg:
1903 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
1904
1905 return err;
37aa5c36
GL		 1906}
1907
e126ba97
EC		 1908static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1909{
1910 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1911 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 1912 unsigned long command;
e126ba97
EC		 1913 phys_addr_t pfn;
1914
1915 command = get_command(vma->vm_pgoff);
1916 switch (command) {
37aa5c36
GL		 1917 case MLX5_IB_MMAP_WC_PAGE:
1918 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 1919 case MLX5_IB_MMAP_REGULAR_PAGE:
4ed131d0 1920 case MLX5_IB_MMAP_ALLOC_WC:
7c2344c3 1921 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 1922
1923 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1924 return -ENOSYS;
1925
d69e3bcf 1926 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 1927 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1928 return -EINVAL;
1929
6cbac1e4 1930 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 1931 return -EPERM;
1932
1933 /* Don't expose to user-space information it shouldn't have */
1934 if (PAGE_SIZE > 4096)
1935 return -EOPNOTSUPP;
1936
1937 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1938 pfn = (dev->mdev->iseg_base +
1939 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1940 PAGE_SHIFT;
1941 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1942 PAGE_SIZE, vma->vm_page_prot))
1943 return -EAGAIN;
1944
1945 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1946 vma->vm_start,
1947 (unsigned long long)pfn << PAGE_SHIFT);
1948 break;
d69e3bcf 1949
e126ba97
EC		 1950 default:
1951 return -EINVAL;
1952 }
1953
1954 return 0;
1955}
1956
e126ba97
EC		 1957static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1958 struct ib_ucontext *context,
1959 struct ib_udata *udata)
1960{
1961 struct mlx5_ib_alloc_pd_resp resp;
1962 struct mlx5_ib_pd *pd;
1963 int err;
1964
1965 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1966 if (!pd)
1967 return ERR_PTR(-ENOMEM);
1968
9603b61d 1969 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 1970 if (err) {
1971 kfree(pd);
1972 return ERR_PTR(err);
1973 }
1974
1975 if (context) {
1976 resp.pdn = pd->pdn;
1977 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 1978 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 1979 kfree(pd);
1980 return ERR_PTR(-EFAULT);
1981 }
e126ba97
EC		 1982 }
1983
1984 return &pd->ibpd;
1985}
1986
1987static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1988{
1989 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1990 struct mlx5_ib_pd *mpd = to_mpd(pd);
1991
9603b61d 1992 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 1993 kfree(mpd);
1994
1995 return 0;
1996}
1997
466fa6d2
MG		 1998enum {
1999 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2000 MATCH_CRITERIA_ENABLE_MISC_BIT,
2001 MATCH_CRITERIA_ENABLE_INNER_BIT
2002};
2003
2004#define HEADER_IS_ZERO(match_criteria, headers) \
2005 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2006 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 2007
466fa6d2 2008static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 2009{
466fa6d2 2010 u8 match_criteria_enable;
038d2ef8 2011
466fa6d2
MG		 2012 match_criteria_enable =
2013 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2014 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2015 match_criteria_enable |=
2016 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2017 MATCH_CRITERIA_ENABLE_MISC_BIT;
2018 match_criteria_enable |=
2019 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2020 MATCH_CRITERIA_ENABLE_INNER_BIT;
2021
2022 return match_criteria_enable;
038d2ef8
MG		 2023}
2024
ca0d4753
MG		 2025static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2026{
2027 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2028 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
038d2ef8
MG		 2029}
2030
2d1e697e
MR		 2031static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
2032 bool inner)
2033{
2034 if (inner) {
2035 MLX5_SET(fte_match_set_misc,
2036 misc_c, inner_ipv6_flow_label, mask);
2037 MLX5_SET(fte_match_set_misc,
2038 misc_v, inner_ipv6_flow_label, val);
2039 } else {
2040 MLX5_SET(fte_match_set_misc,
2041 misc_c, outer_ipv6_flow_label, mask);
2042 MLX5_SET(fte_match_set_misc,
2043 misc_v, outer_ipv6_flow_label, val);
2044 }
2045}
2046
ca0d4753
MG		 2047static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2048{
2049 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2050 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2051 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2052 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2053}
2054
c47ac6ae
MG		 2055#define LAST_ETH_FIELD vlan_tag
2056#define LAST_IB_FIELD sl
ca0d4753 2057#define LAST_IPV4_FIELD tos
466fa6d2 2058#define LAST_IPV6_FIELD traffic_class
c47ac6ae 2059#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 2060#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 2061#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 2062#define LAST_DROP_FIELD size
c47ac6ae
MG		 2063
2064/* Field is the last supported field */
2065#define FIELDS_NOT_SUPPORTED(filter, field)\
2066 memchr_inv((void *)&filter.field +\
2067 sizeof(filter.field), 0,\
2068 sizeof(filter) -\
2069 offsetof(typeof(filter), field) -\
2070 sizeof(filter.field))
2071
19cc7524
AL		 2072#define IPV4_VERSION 4
2073#define IPV6_VERSION 6
2074static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2075 u32 *match_v, const union ib_flow_spec *ib_spec,
a22ed86c 2076 u32 *tag_id, bool *is_drop)
038d2ef8 2077{
466fa6d2
MG		 2078 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2079 misc_parameters);
2080 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2081 misc_parameters);
2d1e697e
MR		 2082 void *headers_c;
2083 void *headers_v;
19cc7524 2084 int match_ipv;
2d1e697e
MR		 2085
2086 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2087 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2088 inner_headers);
2089 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2090 inner_headers);
19cc7524
AL		 2091 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2092 ft_field_support.inner_ip_version);
2d1e697e
MR		 2093 } else {
2094 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2095 outer_headers);
2096 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2097 outer_headers);
19cc7524
AL		 2098 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2099 ft_field_support.outer_ip_version);
2d1e697e 2100 }
466fa6d2 2101
2d1e697e 2102 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 2103 case IB_FLOW_SPEC_ETH:
c47ac6ae 2104 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 2105 return -EOPNOTSUPP;
038d2ef8 2106
2d1e697e 2107 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2108 dmac_47_16),
2109 ib_spec->eth.mask.dst_mac);
2d1e697e 2110 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2111 dmac_47_16),
2112 ib_spec->eth.val.dst_mac);
2113
2d1e697e 2114 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 2115 smac_47_16),
2116 ib_spec->eth.mask.src_mac);
2d1e697e 2117 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 2118 smac_47_16),
2119 ib_spec->eth.val.src_mac);
2120
038d2ef8 2121 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 2122 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 2123 cvlan_tag, 1);
2d1e697e 2124 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 2125 cvlan_tag, 1);
038d2ef8 2126
2d1e697e 2127 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2128 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 2129 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2130 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2131
2d1e697e 2132 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2133 first_cfi,
2134 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 2135 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2136 first_cfi,
2137 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2138
2d1e697e 2139 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2140 first_prio,
2141 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 2142 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2143 first_prio,
2144 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2145 }
2d1e697e 2146 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2147 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 2148 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2149 ethertype, ntohs(ib_spec->eth.val.ether_type));
2150 break;
2151 case IB_FLOW_SPEC_IPV4:
c47ac6ae 2152 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 2153 return -EOPNOTSUPP;
038d2ef8 2154
19cc7524
AL		 2155 if (match_ipv) {
2156 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2157 ip_version, 0xf);
2158 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2159 ip_version, IPV4_VERSION);
2160 } else {
2161 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2162 ethertype, 0xffff);
2163 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2164 ethertype, ETH_P_IP);
2165 }
038d2ef8 2166
2d1e697e 2167 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2168 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2169 &ib_spec->ipv4.mask.src_ip,
2170 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 2171 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2172 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2173 &ib_spec->ipv4.val.src_ip,
2174 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 2175 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2176 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2177 &ib_spec->ipv4.mask.dst_ip,
2178 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 2179 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2180 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2181 &ib_spec->ipv4.val.dst_ip,
2182 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 2183
2d1e697e 2184 set_tos(headers_c, headers_v,
ca0d4753
MG		 2185 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2186
2d1e697e 2187 set_proto(headers_c, headers_v,
ca0d4753 2188 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
038d2ef8 2189 break;
026bae0c 2190 case IB_FLOW_SPEC_IPV6:
c47ac6ae 2191 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 2192 return -EOPNOTSUPP;
026bae0c 2193
19cc7524
AL		 2194 if (match_ipv) {
2195 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2196 ip_version, 0xf);
2197 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2198 ip_version, IPV6_VERSION);
2199 } else {
2200 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2201 ethertype, 0xffff);
2202 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2203 ethertype, ETH_P_IPV6);
2204 }
026bae0c 2205
2d1e697e 2206 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2207 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2208 &ib_spec->ipv6.mask.src_ip,
2209 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2210 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2211 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2212 &ib_spec->ipv6.val.src_ip,
2213 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2214 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2215 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2216 &ib_spec->ipv6.mask.dst_ip,
2217 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2218 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2219 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2220 &ib_spec->ipv6.val.dst_ip,
2221 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2222
2d1e697e 2223 set_tos(headers_c, headers_v,
466fa6d2
MG		 2224 ib_spec->ipv6.mask.traffic_class,
2225 ib_spec->ipv6.val.traffic_class);
2226
2d1e697e 2227 set_proto(headers_c, headers_v,
466fa6d2
MG		 2228 ib_spec->ipv6.mask.next_hdr,
2229 ib_spec->ipv6.val.next_hdr);
2230
2d1e697e
MR		 2231 set_flow_label(misc_params_c, misc_params_v,
2232 ntohl(ib_spec->ipv6.mask.flow_label),
2233 ntohl(ib_spec->ipv6.val.flow_label),
2234 ib_spec->type & IB_FLOW_SPEC_INNER);
2235
026bae0c 2236 break;
038d2ef8 2237 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2238 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2239 LAST_TCP_UDP_FIELD))
1ffd3a26 2240 return -EOPNOTSUPP;
038d2ef8 2241
2d1e697e 2242 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2243 0xff);
2d1e697e 2244 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2245 IPPROTO_TCP);
2246
2d1e697e 2247 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2248 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2249 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2250 ntohs(ib_spec->tcp_udp.val.src_port));
2251
2d1e697e 2252 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2253 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2254 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2255 ntohs(ib_spec->tcp_udp.val.dst_port));
2256 break;
2257 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2258 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2259 LAST_TCP_UDP_FIELD))
1ffd3a26 2260 return -EOPNOTSUPP;
038d2ef8 2261
2d1e697e 2262 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2263 0xff);
2d1e697e 2264 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2265 IPPROTO_UDP);
2266
2d1e697e 2267 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2268 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2269 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2270 ntohs(ib_spec->tcp_udp.val.src_port));
2271
2d1e697e 2272 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2273 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2274 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2275 ntohs(ib_spec->tcp_udp.val.dst_port));
2276 break;
ffb30d8f
MR		 2277 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2278 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2279 LAST_TUNNEL_FIELD))
1ffd3a26 2280 return -EOPNOTSUPP;
ffb30d8f
MR		 2281
2282 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2283 ntohl(ib_spec->tunnel.mask.tunnel_id));
2284 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2285 ntohl(ib_spec->tunnel.val.tunnel_id));
2286 break;
2ac693f9
MR		 2287 case IB_FLOW_SPEC_ACTION_TAG:
2288 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2289 LAST_FLOW_TAG_FIELD))
2290 return -EOPNOTSUPP;
2291 if (ib_spec->flow_tag.tag_id >= BIT(24))
2292 return -EINVAL;
2293
2294 *tag_id = ib_spec->flow_tag.tag_id;
2295 break;
a22ed86c
SS		 2296 case IB_FLOW_SPEC_ACTION_DROP:
2297 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2298 LAST_DROP_FIELD))
2299 return -EOPNOTSUPP;
2300 *is_drop = true;
2301 break;
038d2ef8
MG		 2302 default:
2303 return -EINVAL;
2304 }
2305
2306 return 0;
2307}
2308
2309/* If a flow could catch both multicast and unicast packets,
2310 * it won't fall into the multicast flow steering table and this rule
2311 * could steal other multicast packets.
2312 */
a550ddfc 2313static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
038d2ef8 2314{
81e30880 2315 union ib_flow_spec *flow_spec;
038d2ef8
MG		 2316
2317 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 2318 ib_attr->num_of_specs < 1)
2319 return false;
2320
81e30880
YH		 2321 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2322 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2323 struct ib_flow_spec_ipv4 *ipv4_spec;
2324
2325 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2326 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2327 return true;
2328
038d2ef8 2329 return false;
81e30880
YH		 2330 }
2331
2332 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2333 struct ib_flow_spec_eth *eth_spec;
2334
2335 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2336 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2337 is_multicast_ether_addr(eth_spec->val.dst_mac);
2338 }
038d2ef8 2339
81e30880 2340 return false;
038d2ef8
MG		 2341}
2342
19cc7524
AL		 2343static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2344 const struct ib_flow_attr *flow_attr,
0f750966 2345 bool check_inner)
038d2ef8
MG		 2346{
2347 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 2348 int match_ipv = check_inner ?
2349 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2350 ft_field_support.inner_ip_version) :
2351 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2352 ft_field_support.outer_ip_version);
0f750966
AL		 2353 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2354 bool ipv4_spec_valid, ipv6_spec_valid;
2355 unsigned int ip_spec_type = 0;
2356 bool has_ethertype = false;
038d2ef8 2357 unsigned int spec_index;
0f750966
AL		 2358 bool mask_valid = true;
2359 u16 eth_type = 0;
2360 bool type_valid;
038d2ef8
MG		 2361
2362 /* Validate that ethertype is correct */
2363 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 2364 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 2365 ib_spec->eth.mask.ether_type) {
0f750966
AL		 2366 mask_valid = (ib_spec->eth.mask.ether_type ==
2367 htons(0xffff));
2368 has_ethertype = true;
2369 eth_type = ntohs(ib_spec->eth.val.ether_type);
2370 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2371 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2372 ip_spec_type = ib_spec->type;
038d2ef8
MG		 2373 }
2374 ib_spec = (void *)ib_spec + ib_spec->size;
2375 }
0f750966
AL		 2376
2377 type_valid = (!has_ethertype) || (!ip_spec_type);
2378 if (!type_valid && mask_valid) {
2379 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2380 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2381 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2382 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 2383
2384 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2385 (((eth_type == ETH_P_MPLS_UC) ||
2386 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 2387 }
2388
2389 return type_valid;
2390}
2391
19cc7524
AL		 2392static bool is_valid_attr(struct mlx5_core_dev *mdev,
2393 const struct ib_flow_attr *flow_attr)
0f750966 2394{
19cc7524
AL		 2395 return is_valid_ethertype(mdev, flow_attr, false) &&
2396 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 2397}
2398
2399static void put_flow_table(struct mlx5_ib_dev *dev,
2400 struct mlx5_ib_flow_prio *prio, bool ft_added)
2401{
2402 prio->refcount -= !!ft_added;
2403 if (!prio->refcount) {
2404 mlx5_destroy_flow_table(prio->flow_table);
2405 prio->flow_table = NULL;
2406 }
2407}
2408
2409static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2410{
2411 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2412 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2413 struct mlx5_ib_flow_handler,
2414 ibflow);
2415 struct mlx5_ib_flow_handler *iter, *tmp;
2416
2417 mutex_lock(&dev->flow_db.lock);
2418
2419 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 2420 mlx5_del_flow_rules(iter->rule);
cc0e5d42 2421 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 2422 list_del(&iter->list);
2423 kfree(iter);
2424 }
2425
74491de9 2426 mlx5_del_flow_rules(handler->rule);
5497adc6 2427 put_flow_table(dev, handler->prio, true);
038d2ef8
MG		 2428 mutex_unlock(&dev->flow_db.lock);
2429
2430 kfree(handler);
2431
2432 return 0;
2433}
2434
35d19011
MG		 2435static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2436{
2437 priority *= 2;
2438 if (!dont_trap)
2439 priority++;
2440 return priority;
2441}
2442
cc0e5d42
MG		 2443enum flow_table_type {
2444 MLX5_IB_FT_RX,
2445 MLX5_IB_FT_TX
2446};
2447
00b7c2ab
MG		 2448#define MLX5_FS_MAX_TYPES 6
2449#define MLX5_FS_MAX_ENTRIES BIT(16)
038d2ef8 2450static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 2451 struct ib_flow_attr *flow_attr,
2452 enum flow_table_type ft_type)
038d2ef8 2453{
35d19011 2454 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 2455 struct mlx5_flow_namespace *ns = NULL;
2456 struct mlx5_ib_flow_prio *prio;
2457 struct mlx5_flow_table *ft;
dac388ef 2458 int max_table_size;
038d2ef8
MG		 2459 int num_entries;
2460 int num_groups;
2461 int priority;
2462 int err = 0;
2463
dac388ef
MG		 2464 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2465 log_max_ft_size));
038d2ef8 2466 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2467 if (flow_is_multicast_only(flow_attr) &&
2468 !dont_trap)
038d2ef8
MG		 2469 priority = MLX5_IB_FLOW_MCAST_PRIO;
2470 else
35d19011
MG		 2471 priority = ib_prio_to_core_prio(flow_attr->priority,
2472 dont_trap);
038d2ef8
MG		 2473 ns = mlx5_get_flow_namespace(dev->mdev,
2474 MLX5_FLOW_NAMESPACE_BYPASS);
2475 num_entries = MLX5_FS_MAX_ENTRIES;
2476 num_groups = MLX5_FS_MAX_TYPES;
2477 prio = &dev->flow_db.prios[priority];
2478 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2479 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2480 ns = mlx5_get_flow_namespace(dev->mdev,
2481 MLX5_FLOW_NAMESPACE_LEFTOVERS);
2482 build_leftovers_ft_param(&priority,
2483 &num_entries,
2484 &num_groups);
2485 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 2486 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2487 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2488 allow_sniffer_and_nic_rx_shared_tir))
2489 return ERR_PTR(-ENOTSUPP);
2490
2491 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2492 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2493 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2494
2495 prio = &dev->flow_db.sniffer[ft_type];
2496 priority = 0;
2497 num_entries = 1;
2498 num_groups = 1;
038d2ef8
MG		 2499 }
2500
2501 if (!ns)
2502 return ERR_PTR(-ENOTSUPP);
2503
dac388ef
MG		 2504 if (num_entries > max_table_size)
2505 return ERR_PTR(-ENOMEM);
2506
038d2ef8
MG		 2507 ft = prio->flow_table;
2508 if (!ft) {
2509 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2510 num_entries,
d63cd286 2511 num_groups,
c9f1b073 2512 0, 0);
038d2ef8
MG		 2513
2514 if (!IS_ERR(ft)) {
2515 prio->refcount = 0;
2516 prio->flow_table = ft;
2517 } else {
2518 err = PTR_ERR(ft);
2519 }
2520 }
2521
2522 return err ? ERR_PTR(err) : prio;
2523}
2524
a550ddfc
YH		 2525static void set_underlay_qp(struct mlx5_ib_dev *dev,
2526 struct mlx5_flow_spec *spec,
2527 u32 underlay_qpn)
2528{
2529 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
2530 spec->match_criteria,
2531 misc_parameters);
2532 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2533 misc_parameters);
2534
2535 if (underlay_qpn &&
2536 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2537 ft_field_support.bth_dst_qp)) {
2538 MLX5_SET(fte_match_set_misc,
2539 misc_params_v, bth_dst_qp, underlay_qpn);
2540 MLX5_SET(fte_match_set_misc,
2541 misc_params_c, bth_dst_qp, 0xffffff);
2542 }
2543}
2544
2545static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
2546 struct mlx5_ib_flow_prio *ft_prio,
2547 const struct ib_flow_attr *flow_attr,
2548 struct mlx5_flow_destination *dst,
2549 u32 underlay_qpn)
038d2ef8
MG		 2550{
2551 struct mlx5_flow_table *ft = ft_prio->flow_table;
2552 struct mlx5_ib_flow_handler *handler;
66958ed9 2553 struct mlx5_flow_act flow_act = {0};
c5bb1730 2554 struct mlx5_flow_spec *spec;
a22ed86c 2555 struct mlx5_flow_destination *rule_dst = dst;
dd063d0e 2556 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 2557 unsigned int spec_index;
2ac693f9 2558 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
a22ed86c 2559 bool is_drop = false;
038d2ef8 2560 int err = 0;
a22ed86c 2561 int dest_num = 1;
038d2ef8 2562
19cc7524 2563 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 2564 return ERR_PTR(-EINVAL);
2565
1b9a07ee 2566 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 2567 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 2568 if (!handler || !spec) {
038d2ef8
MG		 2569 err = -ENOMEM;
2570 goto free;
2571 }
2572
2573 INIT_LIST_HEAD(&handler->list);
2574
2575 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
19cc7524 2576 err = parse_flow_attr(dev->mdev, spec->match_criteria,
a22ed86c
SS		 2577 spec->match_value,
2578 ib_flow, &flow_tag, &is_drop);
038d2ef8
MG		 2579 if (err < 0)
2580 goto free;
2581
2582 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2583 }
2584
a550ddfc
YH		 2585 if (!flow_is_multicast_only(flow_attr))
2586 set_underlay_qp(dev, spec, underlay_qpn);
2587
466fa6d2 2588 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
a22ed86c
SS		 2589 if (is_drop) {
2590 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2591 rule_dst = NULL;
2592 dest_num = 0;
2593 } else {
2594 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2595 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2596 }
2ac693f9
MR		 2597
2598 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG &&
2599 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2600 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
2601 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
2602 flow_tag, flow_attr->type);
2603 err = -EINVAL;
2604 goto free;
2605 }
2606 flow_act.flow_tag = flow_tag;
74491de9 2607 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 2608 &flow_act,
a22ed86c 2609 rule_dst, dest_num);
038d2ef8
MG		 2610
2611 if (IS_ERR(handler->rule)) {
2612 err = PTR_ERR(handler->rule);
2613 goto free;
2614 }
2615
d9d4980a 2616 ft_prio->refcount++;
5497adc6 2617 handler->prio = ft_prio;
038d2ef8
MG		 2618
2619 ft_prio->flow_table = ft;
2620free:
2621 if (err)
2622 kfree(handler);
c5bb1730 2623 kvfree(spec);
038d2ef8
MG		 2624 return err ? ERR_PTR(err) : handler;
2625}
2626
a550ddfc
YH		 2627static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2628 struct mlx5_ib_flow_prio *ft_prio,
2629 const struct ib_flow_attr *flow_attr,
2630 struct mlx5_flow_destination *dst)
2631{
2632 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0);
2633}
2634
35d19011
MG		 2635static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2636 struct mlx5_ib_flow_prio *ft_prio,
2637 struct ib_flow_attr *flow_attr,
2638 struct mlx5_flow_destination *dst)
2639{
2640 struct mlx5_ib_flow_handler *handler_dst = NULL;
2641 struct mlx5_ib_flow_handler *handler = NULL;
2642
2643 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2644 if (!IS_ERR(handler)) {
2645 handler_dst = create_flow_rule(dev, ft_prio,
2646 flow_attr, dst);
2647 if (IS_ERR(handler_dst)) {
74491de9 2648 mlx5_del_flow_rules(handler->rule);
d9d4980a 2649 ft_prio->refcount--;
35d19011
MG		 2650 kfree(handler);
2651 handler = handler_dst;
2652 } else {
2653 list_add(&handler_dst->list, &handler->list);
2654 }
2655 }
2656
2657 return handler;
2658}
038d2ef8
MG		 2659enum {
2660 LEFTOVERS_MC,
2661 LEFTOVERS_UC,
2662};
2663
2664static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2665 struct mlx5_ib_flow_prio *ft_prio,
2666 struct ib_flow_attr *flow_attr,
2667 struct mlx5_flow_destination *dst)
2668{
2669 struct mlx5_ib_flow_handler *handler_ucast = NULL;
2670 struct mlx5_ib_flow_handler *handler = NULL;
2671
2672 static struct {
2673 struct ib_flow_attr flow_attr;
2674 struct ib_flow_spec_eth eth_flow;
2675 } leftovers_specs[] = {
2676 [LEFTOVERS_MC] = {
2677 .flow_attr = {
2678 .num_of_specs = 1,
2679 .size = sizeof(leftovers_specs[0])
2680 },
2681 .eth_flow = {
2682 .type = IB_FLOW_SPEC_ETH,
2683 .size = sizeof(struct ib_flow_spec_eth),
2684 .mask = {.dst_mac = {0x1} },
2685 .val = {.dst_mac = {0x1} }
2686 }
2687 },
2688 [LEFTOVERS_UC] = {
2689 .flow_attr = {
2690 .num_of_specs = 1,
2691 .size = sizeof(leftovers_specs[0])
2692 },
2693 .eth_flow = {
2694 .type = IB_FLOW_SPEC_ETH,
2695 .size = sizeof(struct ib_flow_spec_eth),
2696 .mask = {.dst_mac = {0x1} },
2697 .val = {.dst_mac = {} }
2698 }
2699 }
2700 };
2701
2702 handler = create_flow_rule(dev, ft_prio,
2703 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2704 dst);
2705 if (!IS_ERR(handler) &&
2706 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2707 handler_ucast = create_flow_rule(dev, ft_prio,
2708 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2709 dst);
2710 if (IS_ERR(handler_ucast)) {
74491de9 2711 mlx5_del_flow_rules(handler->rule);
d9d4980a 2712 ft_prio->refcount--;
038d2ef8
MG		 2713 kfree(handler);
2714 handler = handler_ucast;
2715 } else {
2716 list_add(&handler_ucast->list, &handler->list);
2717 }
2718 }
2719
2720 return handler;
2721}
2722
cc0e5d42
MG		 2723static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2724 struct mlx5_ib_flow_prio *ft_rx,
2725 struct mlx5_ib_flow_prio *ft_tx,
2726 struct mlx5_flow_destination *dst)
2727{
2728 struct mlx5_ib_flow_handler *handler_rx;
2729 struct mlx5_ib_flow_handler *handler_tx;
2730 int err;
2731 static const struct ib_flow_attr flow_attr = {
2732 .num_of_specs = 0,
2733 .size = sizeof(flow_attr)
2734 };
2735
2736 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2737 if (IS_ERR(handler_rx)) {
2738 err = PTR_ERR(handler_rx);
2739 goto err;
2740 }
2741
2742 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2743 if (IS_ERR(handler_tx)) {
2744 err = PTR_ERR(handler_tx);
2745 goto err_tx;
2746 }
2747
2748 list_add(&handler_tx->list, &handler_rx->list);
2749
2750 return handler_rx;
2751
2752err_tx:
74491de9 2753 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 2754 ft_rx->refcount--;
2755 kfree(handler_rx);
2756err:
2757 return ERR_PTR(err);
2758}
2759
038d2ef8
MG		 2760static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2761 struct ib_flow_attr *flow_attr,
2762 int domain)
2763{
2764 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 2765 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 2766 struct mlx5_ib_flow_handler *handler = NULL;
2767 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 2768 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8
MG		 2769 struct mlx5_ib_flow_prio *ft_prio;
2770 int err;
a550ddfc 2771 int underlay_qpn;
038d2ef8
MG		 2772
2773 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
dac388ef 2774 return ERR_PTR(-ENOMEM);
038d2ef8
MG		 2775
2776 if (domain != IB_FLOW_DOMAIN_USER ||
2777 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
35d19011 2778 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
038d2ef8
MG		 2779 return ERR_PTR(-EINVAL);
2780
2781 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2782 if (!dst)
2783 return ERR_PTR(-ENOMEM);
2784
2785 mutex_lock(&dev->flow_db.lock);
2786
cc0e5d42 2787 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
038d2ef8
MG		 2788 if (IS_ERR(ft_prio)) {
2789 err = PTR_ERR(ft_prio);
2790 goto unlock;
2791 }
cc0e5d42
MG		 2792 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2793 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2794 if (IS_ERR(ft_prio_tx)) {
2795 err = PTR_ERR(ft_prio_tx);
2796 ft_prio_tx = NULL;
2797 goto destroy_ft;
2798 }
2799 }
038d2ef8
MG		 2800
2801 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
d9f88e5a
YH		 2802 if (mqp->flags & MLX5_IB_QP_RSS)
2803 dst->tir_num = mqp->rss_qp.tirn;
2804 else
2805 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
038d2ef8
MG		 2806
2807 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2808 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2809 handler = create_dont_trap_rule(dev, ft_prio,
2810 flow_attr, dst);
2811 } else {
a550ddfc
YH		 2812 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
2813 mqp->underlay_qpn : 0;
2814 handler = _create_flow_rule(dev, ft_prio, flow_attr,
2815 dst, underlay_qpn);
35d19011 2816 }
038d2ef8
MG		 2817 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2818 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2819 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2820 dst);
cc0e5d42
MG		 2821 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2822 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 2823 } else {
2824 err = -EINVAL;
2825 goto destroy_ft;
2826 }
2827
2828 if (IS_ERR(handler)) {
2829 err = PTR_ERR(handler);
2830 handler = NULL;
2831 goto destroy_ft;
2832 }
2833
038d2ef8
MG		 2834 mutex_unlock(&dev->flow_db.lock);
2835 kfree(dst);
2836
2837 return &handler->ibflow;
2838
2839destroy_ft:
2840 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 2841 if (ft_prio_tx)
2842 put_flow_table(dev, ft_prio_tx, false);
038d2ef8
MG		 2843unlock:
2844 mutex_unlock(&dev->flow_db.lock);
2845 kfree(dst);
2846 kfree(handler);
2847 return ERR_PTR(err);
2848}
2849
e126ba97
EC		 2850static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2851{
2852 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 2853 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97
EC		 2854 int err;
2855
81e30880
YH		 2856 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
2857 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
2858 return -EOPNOTSUPP;
2859 }
2860
9603b61d 2861 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2862 if (err)
2863 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2864 ibqp->qp_num, gid->raw);
2865
2866 return err;
2867}
2868
2869static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2870{
2871 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2872 int err;
2873
9603b61d 2874 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2875 if (err)
2876 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2877 ibqp->qp_num, gid->raw);
2878
2879 return err;
2880}
2881
2882static int init_node_data(struct mlx5_ib_dev *dev)
2883{
1b5daf11 2884 int err;
e126ba97 2885
1b5daf11 2886 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 2887 if (err)
1b5daf11 2888 return err;
e126ba97 2889
1b5daf11 2890 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 2891
1b5daf11 2892 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 2893}
2894
2895static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2896 char *buf)
2897{
2898 struct mlx5_ib_dev *dev =
2899 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2900
9603b61d 2901 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 2902}
2903
2904static ssize_t show_reg_pages(struct device *device,
2905 struct device_attribute *attr, char *buf)
2906{
2907 struct mlx5_ib_dev *dev =
2908 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2909
6aec21f6 2910 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 2911}
2912
2913static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2914 char *buf)
2915{
2916 struct mlx5_ib_dev *dev =
2917 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 2918 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 2919}
2920
e126ba97
EC		 2921static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2922 char *buf)
2923{
2924 struct mlx5_ib_dev *dev =
2925 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 2926 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 2927}
2928
2929static ssize_t show_board(struct device *device, struct device_attribute *attr,
2930 char *buf)
2931{
2932 struct mlx5_ib_dev *dev =
2933 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2934 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 2935 dev->mdev->board_id);
e126ba97
EC		 2936}
2937
2938static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
e126ba97
EC		 2939static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2940static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2941static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2942static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2943
2944static struct device_attribute *mlx5_class_attributes[] = {
2945 &dev_attr_hw_rev,
e126ba97
EC		 2946 &dev_attr_hca_type,
2947 &dev_attr_board_id,
2948 &dev_attr_fw_pages,
2949 &dev_attr_reg_pages,
2950};
2951
7722f47e
HE		 2952static void pkey_change_handler(struct work_struct *work)
2953{
2954 struct mlx5_ib_port_resources *ports =
2955 container_of(work, struct mlx5_ib_port_resources,
2956 pkey_change_work);
2957
2958 mutex_lock(&ports->devr->mutex);
2959 mlx5_ib_gsi_pkey_change(ports->gsi);
2960 mutex_unlock(&ports->devr->mutex);
2961}
2962
89ea94a7
MG		 2963static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2964{
2965 struct mlx5_ib_qp *mqp;
2966 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2967 struct mlx5_core_cq *mcq;
2968 struct list_head cq_armed_list;
2969 unsigned long flags_qp;
2970 unsigned long flags_cq;
2971 unsigned long flags;
2972
2973 INIT_LIST_HEAD(&cq_armed_list);
2974
2975 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2976 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2977 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2978 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2979 if (mqp->sq.tail != mqp->sq.head) {
2980 send_mcq = to_mcq(mqp->ibqp.send_cq);
2981 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2982 if (send_mcq->mcq.comp &&
2983 mqp->ibqp.send_cq->comp_handler) {
2984 if (!send_mcq->mcq.reset_notify_added) {
2985 send_mcq->mcq.reset_notify_added = 1;
2986 list_add_tail(&send_mcq->mcq.reset_notify,
2987 &cq_armed_list);
2988 }
2989 }
2990 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2991 }
2992 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2993 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2994 /* no handling is needed for SRQ */
2995 if (!mqp->ibqp.srq) {
2996 if (mqp->rq.tail != mqp->rq.head) {
2997 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2998 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2999 if (recv_mcq->mcq.comp &&
3000 mqp->ibqp.recv_cq->comp_handler) {
3001 if (!recv_mcq->mcq.reset_notify_added) {
3002 recv_mcq->mcq.reset_notify_added = 1;
3003 list_add_tail(&recv_mcq->mcq.reset_notify,
3004 &cq_armed_list);
3005 }
3006 }
3007 spin_unlock_irqrestore(&recv_mcq->lock,
3008 flags_cq);
3009 }
3010 }
3011 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3012 }
3013 /*At that point all inflight post send were put to be executed as of we
3014 * lock/unlock above locks Now need to arm all involved CQs.
3015 */
3016 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
3017 mcq->comp(mcq);
3018 }
3019 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3020}
3021
03404e8a
MG		 3022static void delay_drop_handler(struct work_struct *work)
3023{
3024 int err;
3025 struct mlx5_ib_delay_drop *delay_drop =
3026 container_of(work, struct mlx5_ib_delay_drop,
3027 delay_drop_work);
3028
fe248c3a
MG		 3029 atomic_inc(&delay_drop->events_cnt);
3030
03404e8a
MG		 3031 mutex_lock(&delay_drop->lock);
3032 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
3033 delay_drop->timeout);
3034 if (err) {
3035 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
3036 delay_drop->timeout);
3037 delay_drop->activate = false;
3038 }
3039 mutex_unlock(&delay_drop->lock);
3040}
3041
9603b61d 3042static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 3043 enum mlx5_dev_event event, unsigned long param)
e126ba97 3044{
9603b61d 3045 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
e126ba97 3046 struct ib_event ibev;
dbaaff2a 3047 bool fatal = false;
e126ba97
EC		 3048 u8 port = 0;
3049
3050 switch (event) {
3051 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 3052 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 3053 mlx5_ib_handle_internal_error(ibdev);
dbaaff2a 3054 fatal = true;
e126ba97
EC		 3055 break;
3056
3057 case MLX5_DEV_EVENT_PORT_UP:
e126ba97 3058 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 3059 case MLX5_DEV_EVENT_PORT_INITIALIZED:
4d2f9bbb 3060 port = (u8)param;
5ec8c83e
AH		 3061
3062 /* In RoCE, port up/down events are handled in
3063 * mlx5_netdev_event().
3064 */
3065 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
3066 IB_LINK_LAYER_ETHERNET)
3067 return;
3068
3069 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
3070 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
e126ba97
EC		 3071 break;
3072
e126ba97
EC		 3073 case MLX5_DEV_EVENT_LID_CHANGE:
3074 ibev.event = IB_EVENT_LID_CHANGE;
4d2f9bbb 3075 port = (u8)param;
e126ba97
EC		 3076 break;
3077
3078 case MLX5_DEV_EVENT_PKEY_CHANGE:
3079 ibev.event = IB_EVENT_PKEY_CHANGE;
4d2f9bbb 3080 port = (u8)param;
7722f47e
HE		 3081
3082 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 3083 break;
3084
3085 case MLX5_DEV_EVENT_GUID_CHANGE:
3086 ibev.event = IB_EVENT_GID_CHANGE;
4d2f9bbb 3087 port = (u8)param;
e126ba97
EC		 3088 break;
3089
3090 case MLX5_DEV_EVENT_CLIENT_REREG:
3091 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4d2f9bbb 3092 port = (u8)param;
e126ba97 3093 break;
03404e8a
MG		 3094 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
3095 schedule_work(&ibdev->delay_drop.delay_drop_work);
3096 goto out;
bdc37924 3097 default:
03404e8a 3098 goto out;
e126ba97
EC		 3099 }
3100
3101 ibev.device = &ibdev->ib_dev;
3102 ibev.element.port_num = port;
3103
a0c84c32
EC		 3104 if (port < 1 || port > ibdev->num_ports) {
3105 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
03404e8a 3106 goto out;
a0c84c32
EC		 3107 }
3108
e126ba97
EC		 3109 if (ibdev->ib_active)
3110 ib_dispatch_event(&ibev);
dbaaff2a
EC		 3111
3112 if (fatal)
3113 ibdev->ib_active = false;
03404e8a
MG		 3114
3115out:
3116 return;
e126ba97
EC		 3117}
3118
c43f1112
MG		 3119static int set_has_smi_cap(struct mlx5_ib_dev *dev)
3120{
3121 struct mlx5_hca_vport_context vport_ctx;
3122 int err;
3123 int port;
3124
3125 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
3126 dev->mdev->port_caps[port - 1].has_smi = false;
3127 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
3128 MLX5_CAP_PORT_TYPE_IB) {
3129 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
3130 err = mlx5_query_hca_vport_context(dev->mdev, 0,
3131 port, 0,
3132 &vport_ctx);
3133 if (err) {
3134 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
3135 port, err);
3136 return err;
3137 }
3138 dev->mdev->port_caps[port - 1].has_smi =
3139 vport_ctx.has_smi;
3140 } else {
3141 dev->mdev->port_caps[port - 1].has_smi = true;
3142 }
3143 }
3144 }
3145 return 0;
3146}
3147
e126ba97
EC		 3148static void get_ext_port_caps(struct mlx5_ib_dev *dev)
3149{
3150 int port;
3151
938fe83c 3152 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
e126ba97
EC		 3153 mlx5_query_ext_port_caps(dev, port);
3154}
3155
3156static int get_port_caps(struct mlx5_ib_dev *dev)
3157{
3158 struct ib_device_attr *dprops = NULL;
3159 struct ib_port_attr *pprops = NULL;
f614fc15 3160 int err = -ENOMEM;
e126ba97 3161 int port;
2528e33e 3162 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 3163
3164 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
3165 if (!pprops)
3166 goto out;
3167
3168 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
3169 if (!dprops)
3170 goto out;
3171
c43f1112
MG		 3172 err = set_has_smi_cap(dev);
3173 if (err)
3174 goto out;
3175
2528e33e 3176 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 3177 if (err) {
3178 mlx5_ib_warn(dev, "query_device failed %d\n", err);
3179 goto out;
3180 }
3181
938fe83c 3182 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
c4550c63 3183 memset(pprops, 0, sizeof(*pprops));
e126ba97
EC		 3184 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
3185 if (err) {
938fe83c
SM		 3186 mlx5_ib_warn(dev, "query_port %d failed %d\n",
3187 port, err);
e126ba97
EC		 3188 break;
3189 }
938fe83c
SM		 3190 dev->mdev->port_caps[port - 1].pkey_table_len =
3191 dprops->max_pkeys;
3192 dev->mdev->port_caps[port - 1].gid_table_len =
3193 pprops->gid_tbl_len;
e126ba97
EC		 3194 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
3195 dprops->max_pkeys, pprops->gid_tbl_len);
3196 }
3197
3198out:
3199 kfree(pprops);
3200 kfree(dprops);
3201
3202 return err;
3203}
3204
3205static void destroy_umrc_res(struct mlx5_ib_dev *dev)
3206{
3207 int err;
3208
3209 err = mlx5_mr_cache_cleanup(dev);
3210 if (err)
3211 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
3212
3213 mlx5_ib_destroy_qp(dev->umrc.qp);
add08d76 3214 ib_free_cq(dev->umrc.cq);
e126ba97
EC		 3215 ib_dealloc_pd(dev->umrc.pd);
3216}
3217
3218enum {
3219 MAX_UMR_WR = 128,
3220};
3221
3222static int create_umr_res(struct mlx5_ib_dev *dev)
3223{
3224 struct ib_qp_init_attr *init_attr = NULL;
3225 struct ib_qp_attr *attr = NULL;
3226 struct ib_pd *pd;
3227 struct ib_cq *cq;
3228 struct ib_qp *qp;
e126ba97
EC		 3229 int ret;
3230
3231 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
3232 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
3233 if (!attr || !init_attr) {
3234 ret = -ENOMEM;
3235 goto error_0;
3236 }
3237
ed082d36 3238 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 3239 if (IS_ERR(pd)) {
3240 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
3241 ret = PTR_ERR(pd);
3242 goto error_0;
3243 }
3244
add08d76 3245 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 3246 if (IS_ERR(cq)) {
3247 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
3248 ret = PTR_ERR(cq);
3249 goto error_2;
3250 }
e126ba97
EC		 3251
3252 init_attr->send_cq = cq;
3253 init_attr->recv_cq = cq;
3254 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
3255 init_attr->cap.max_send_wr = MAX_UMR_WR;
3256 init_attr->cap.max_send_sge = 1;
3257 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
3258 init_attr->port_num = 1;
3259 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
3260 if (IS_ERR(qp)) {
3261 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
3262 ret = PTR_ERR(qp);
3263 goto error_3;
3264 }
3265 qp->device = &dev->ib_dev;
3266 qp->real_qp = qp;
3267 qp->uobject = NULL;
3268 qp->qp_type = MLX5_IB_QPT_REG_UMR;
31fde034
MD		 3269 qp->send_cq = init_attr->send_cq;
3270 qp->recv_cq = init_attr->recv_cq;
e126ba97
EC		 3271
3272 attr->qp_state = IB_QPS_INIT;
3273 attr->port_num = 1;
3274 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
3275 IB_QP_PORT, NULL);
3276 if (ret) {
3277 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
3278 goto error_4;
3279 }
3280
3281 memset(attr, 0, sizeof(*attr));
3282 attr->qp_state = IB_QPS_RTR;
3283 attr->path_mtu = IB_MTU_256;
3284
3285 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3286 if (ret) {
3287 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
3288 goto error_4;
3289 }
3290
3291 memset(attr, 0, sizeof(*attr));
3292 attr->qp_state = IB_QPS_RTS;
3293 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3294 if (ret) {
3295 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
3296 goto error_4;
3297 }
3298
3299 dev->umrc.qp = qp;
3300 dev->umrc.cq = cq;
e126ba97
EC		 3301 dev->umrc.pd = pd;
3302
3303 sema_init(&dev->umrc.sem, MAX_UMR_WR);
3304 ret = mlx5_mr_cache_init(dev);
3305 if (ret) {
3306 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
3307 goto error_4;
3308 }
3309
3310 kfree(attr);
3311 kfree(init_attr);
3312
3313 return 0;
3314
3315error_4:
3316 mlx5_ib_destroy_qp(qp);
3317
3318error_3:
add08d76 3319 ib_free_cq(cq);
e126ba97
EC		 3320
3321error_2:
e126ba97
EC		 3322 ib_dealloc_pd(pd);
3323
3324error_0:
3325 kfree(attr);
3326 kfree(init_attr);
3327 return ret;
3328}
3329
6e8484c5
MG		 3330static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
3331{
3332 switch (umr_fence_cap) {
3333 case MLX5_CAP_UMR_FENCE_NONE:
3334 return MLX5_FENCE_MODE_NONE;
3335 case MLX5_CAP_UMR_FENCE_SMALL:
3336 return MLX5_FENCE_MODE_INITIATOR_SMALL;
3337 default:
3338 return MLX5_FENCE_MODE_STRONG_ORDERING;
3339 }
3340}
3341
e126ba97
EC		 3342static int create_dev_resources(struct mlx5_ib_resources *devr)
3343{
3344 struct ib_srq_init_attr attr;
3345 struct mlx5_ib_dev *dev;
bcf4c1ea 3346 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 3347 int port;
e126ba97
EC		 3348 int ret = 0;
3349
3350 dev = container_of(devr, struct mlx5_ib_dev, devr);
3351
d16e91da
HE		 3352 mutex_init(&devr->mutex);
3353
e126ba97
EC		 3354 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
3355 if (IS_ERR(devr->p0)) {
3356 ret = PTR_ERR(devr->p0);
3357 goto error0;
3358 }
3359 devr->p0->device = &dev->ib_dev;
3360 devr->p0->uobject = NULL;
3361 atomic_set(&devr->p0->usecnt, 0);
3362
bcf4c1ea 3363 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 3364 if (IS_ERR(devr->c0)) {
3365 ret = PTR_ERR(devr->c0);
3366 goto error1;
3367 }
3368 devr->c0->device = &dev->ib_dev;
3369 devr->c0->uobject = NULL;
3370 devr->c0->comp_handler = NULL;
3371 devr->c0->event_handler = NULL;
3372 devr->c0->cq_context = NULL;
3373 atomic_set(&devr->c0->usecnt, 0);
3374
3375 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3376 if (IS_ERR(devr->x0)) {
3377 ret = PTR_ERR(devr->x0);
3378 goto error2;
3379 }
3380 devr->x0->device = &dev->ib_dev;
3381 devr->x0->inode = NULL;
3382 atomic_set(&devr->x0->usecnt, 0);
3383 mutex_init(&devr->x0->tgt_qp_mutex);
3384 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
3385
3386 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3387 if (IS_ERR(devr->x1)) {
3388 ret = PTR_ERR(devr->x1);
3389 goto error3;
3390 }
3391 devr->x1->device = &dev->ib_dev;
3392 devr->x1->inode = NULL;
3393 atomic_set(&devr->x1->usecnt, 0);
3394 mutex_init(&devr->x1->tgt_qp_mutex);
3395 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
3396
3397 memset(&attr, 0, sizeof(attr));
3398 attr.attr.max_sge = 1;
3399 attr.attr.max_wr = 1;
3400 attr.srq_type = IB_SRQT_XRC;
1a56ff6d 3401 attr.ext.cq = devr->c0;
e126ba97
EC		 3402 attr.ext.xrc.xrcd = devr->x0;
3403
3404 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3405 if (IS_ERR(devr->s0)) {
3406 ret = PTR_ERR(devr->s0);
3407 goto error4;
3408 }
3409 devr->s0->device = &dev->ib_dev;
3410 devr->s0->pd = devr->p0;
3411 devr->s0->uobject = NULL;
3412 devr->s0->event_handler = NULL;
3413 devr->s0->srq_context = NULL;
3414 devr->s0->srq_type = IB_SRQT_XRC;
3415 devr->s0->ext.xrc.xrcd = devr->x0;
1a56ff6d 3416 devr->s0->ext.cq = devr->c0;
e126ba97 3417 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1a56ff6d 3418 atomic_inc(&devr->s0->ext.cq->usecnt);
e126ba97
EC		 3419 atomic_inc(&devr->p0->usecnt);
3420 atomic_set(&devr->s0->usecnt, 0);
3421
4aa17b28
HA		 3422 memset(&attr, 0, sizeof(attr));
3423 attr.attr.max_sge = 1;
3424 attr.attr.max_wr = 1;
3425 attr.srq_type = IB_SRQT_BASIC;
3426 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3427 if (IS_ERR(devr->s1)) {
3428 ret = PTR_ERR(devr->s1);
3429 goto error5;
3430 }
3431 devr->s1->device = &dev->ib_dev;
3432 devr->s1->pd = devr->p0;
3433 devr->s1->uobject = NULL;
3434 devr->s1->event_handler = NULL;
3435 devr->s1->srq_context = NULL;
3436 devr->s1->srq_type = IB_SRQT_BASIC;
1a56ff6d 3437 devr->s1->ext.cq = devr->c0;
4aa17b28 3438 atomic_inc(&devr->p0->usecnt);
1a56ff6d 3439 atomic_set(&devr->s1->usecnt, 0);
4aa17b28 3440
7722f47e
HE		 3441 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
3442 INIT_WORK(&devr->ports[port].pkey_change_work,
3443 pkey_change_handler);
3444 devr->ports[port].devr = devr;
3445 }
3446
e126ba97
EC		 3447 return 0;
3448
4aa17b28
HA		 3449error5:
3450 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 3451error4:
3452 mlx5_ib_dealloc_xrcd(devr->x1);
3453error3:
3454 mlx5_ib_dealloc_xrcd(devr->x0);
3455error2:
3456 mlx5_ib_destroy_cq(devr->c0);
3457error1:
3458 mlx5_ib_dealloc_pd(devr->p0);
3459error0:
3460 return ret;
3461}
3462
3463static void destroy_dev_resources(struct mlx5_ib_resources *devr)
3464{
7722f47e
HE		 3465 struct mlx5_ib_dev *dev =
3466 container_of(devr, struct mlx5_ib_dev, devr);
3467 int port;
3468
4aa17b28 3469 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 3470 mlx5_ib_destroy_srq(devr->s0);
3471 mlx5_ib_dealloc_xrcd(devr->x0);
3472 mlx5_ib_dealloc_xrcd(devr->x1);
3473 mlx5_ib_destroy_cq(devr->c0);
3474 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 3475
3476 /* Make sure no change P_Key work items are still executing */
3477 for (port = 0; port < dev->num_ports; ++port)
3478 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 3479}
3480
e53505a8
AS		 3481static u32 get_core_cap_flags(struct ib_device *ibdev)
3482{
3483 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3484 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3485 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3486 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3487 u32 ret = 0;
3488
3489 if (ll == IB_LINK_LAYER_INFINIBAND)
3490 return RDMA_CORE_PORT_IBA_IB;
3491
72cd5717
OG		 3492 ret = RDMA_CORE_PORT_RAW_PACKET;
3493
e53505a8 3494 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 3495 return ret;
e53505a8
AS		 3496
3497 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 3498 return ret;
e53505a8
AS		 3499
3500 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3501 ret |= RDMA_CORE_PORT_IBA_ROCE;
3502
3503 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3504 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3505
3506 return ret;
3507}
3508
7738613e
IW		 3509static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3510 struct ib_port_immutable *immutable)
3511{
3512 struct ib_port_attr attr;
ca5b91d6
OG		 3513 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3514 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
7738613e
IW		 3515 int err;
3516
c4550c63
OG		 3517 immutable->core_cap_flags = get_core_cap_flags(ibdev);
3518
3519 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 3520 if (err)
3521 return err;
3522
3523 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3524 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 3525 immutable->core_cap_flags = get_core_cap_flags(ibdev);
ca5b91d6
OG		 3526 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3527 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 3528
3529 return 0;
3530}
3531
9abb0d1b 3532static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 3533{
3534 struct mlx5_ib_dev *dev =
3535 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 3536 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
3537 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
3538 fw_rev_sub(dev->mdev));
c7342823
IW		 3539}
3540
45f95acd 3541static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 3542{
3543 struct mlx5_core_dev *mdev = dev->mdev;
3544 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3545 MLX5_FLOW_NAMESPACE_LAG);
3546 struct mlx5_flow_table *ft;
3547 int err;
3548
3549 if (!ns || !mlx5_lag_is_active(mdev))
3550 return 0;
3551
3552 err = mlx5_cmd_create_vport_lag(mdev);
3553 if (err)
3554 return err;
3555
3556 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3557 if (IS_ERR(ft)) {
3558 err = PTR_ERR(ft);
3559 goto err_destroy_vport_lag;
3560 }
3561
3562 dev->flow_db.lag_demux_ft = ft;
3563 return 0;
3564
3565err_destroy_vport_lag:
3566 mlx5_cmd_destroy_vport_lag(mdev);
3567 return err;
3568}
3569
45f95acd 3570static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 3571{
3572 struct mlx5_core_dev *mdev = dev->mdev;
3573
3574 if (dev->flow_db.lag_demux_ft) {
3575 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
3576 dev->flow_db.lag_demux_ft = NULL;
3577
3578 mlx5_cmd_destroy_vport_lag(mdev);
3579 }
3580}
3581
d012f5d6
OG		 3582static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev)
3583{
3584 int err;
3585
3586 dev->roce.nb.notifier_call = mlx5_netdev_event;
3587 err = register_netdevice_notifier(&dev->roce.nb);
3588 if (err) {
3589 dev->roce.nb.notifier_call = NULL;
3590 return err;
3591 }
3592
3593 return 0;
3594}
3595
3596static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev)
5ec8c83e
AH		 3597{
3598 if (dev->roce.nb.notifier_call) {
3599 unregister_netdevice_notifier(&dev->roce.nb);
3600 dev->roce.nb.notifier_call = NULL;
3601 }
3602}
3603
45f95acd 3604static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 3605{
e53505a8
AS		 3606 int err;
3607
d012f5d6
OG		 3608 err = mlx5_add_netdev_notifier(dev);
3609 if (err)
e53505a8
AS		 3610 return err;
3611
ca5b91d6
OG		 3612 if (MLX5_CAP_GEN(dev->mdev, roce)) {
3613 err = mlx5_nic_vport_enable_roce(dev->mdev);
3614 if (err)
3615 goto err_unregister_netdevice_notifier;
3616 }
e53505a8 3617
45f95acd 3618 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 3619 if (err)
3620 goto err_disable_roce;
3621
e53505a8
AS		 3622 return 0;
3623
9ef9c640 3624err_disable_roce:
ca5b91d6
OG		 3625 if (MLX5_CAP_GEN(dev->mdev, roce))
3626 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 3627
e53505a8 3628err_unregister_netdevice_notifier:
d012f5d6 3629 mlx5_remove_netdev_notifier(dev);
e53505a8 3630 return err;
fc24fc5e
AS		 3631}
3632
45f95acd 3633static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 3634{
45f95acd 3635 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 3636 if (MLX5_CAP_GEN(dev->mdev, roce))
3637 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 3638}
3639
e1f24a79 3640struct mlx5_ib_counter {
7c16f477
KH		 3641 const char *name;
3642 size_t offset;
3643};
3644
3645#define INIT_Q_COUNTER(_name) \
3646 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3647
e1f24a79 3648static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 3649 INIT_Q_COUNTER(rx_write_requests),
3650 INIT_Q_COUNTER(rx_read_requests),
3651 INIT_Q_COUNTER(rx_atomic_requests),
3652 INIT_Q_COUNTER(out_of_buffer),
3653};
3654
e1f24a79 3655static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 3656 INIT_Q_COUNTER(out_of_sequence),
3657};
3658
e1f24a79 3659static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 3660 INIT_Q_COUNTER(duplicate_request),
3661 INIT_Q_COUNTER(rnr_nak_retry_err),
3662 INIT_Q_COUNTER(packet_seq_err),
3663 INIT_Q_COUNTER(implied_nak_seq_err),
3664 INIT_Q_COUNTER(local_ack_timeout_err),
3665};
3666
e1f24a79
PP		 3667#define INIT_CONG_COUNTER(_name) \
3668 { .name = #_name, .offset = \
3669 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
3670
3671static const struct mlx5_ib_counter cong_cnts[] = {
3672 INIT_CONG_COUNTER(rp_cnp_ignored),
3673 INIT_CONG_COUNTER(rp_cnp_handled),
3674 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
3675 INIT_CONG_COUNTER(np_cnp_sent),
3676};
3677
58dcb60a
PP		 3678static const struct mlx5_ib_counter extended_err_cnts[] = {
3679 INIT_Q_COUNTER(resp_local_length_error),
3680 INIT_Q_COUNTER(resp_cqe_error),
3681 INIT_Q_COUNTER(req_cqe_error),
3682 INIT_Q_COUNTER(req_remote_invalid_request),
3683 INIT_Q_COUNTER(req_remote_access_errors),
3684 INIT_Q_COUNTER(resp_remote_access_errors),
3685 INIT_Q_COUNTER(resp_cqe_flush_error),
3686 INIT_Q_COUNTER(req_cqe_flush_error),
3687};
3688
e1f24a79 3689static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a
MB		 3690{
3691 unsigned int i;
3692
7c16f477 3693 for (i = 0; i < dev->num_ports; i++) {
0837e86a 3694 mlx5_core_dealloc_q_counter(dev->mdev,
e1f24a79
PP		 3695 dev->port[i].cnts.set_id);
3696 kfree(dev->port[i].cnts.names);
3697 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 3698 }
3699}
3700
e1f24a79
PP		 3701static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
3702 struct mlx5_ib_counters *cnts)
7c16f477
KH		 3703{
3704 u32 num_counters;
3705
3706 num_counters = ARRAY_SIZE(basic_q_cnts);
3707
3708 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
3709 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
3710
3711 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
3712 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 3713
3714 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
3715 num_counters += ARRAY_SIZE(extended_err_cnts);
3716
e1f24a79 3717 cnts->num_q_counters = num_counters;
7c16f477 3718
e1f24a79
PP		 3719 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3720 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
3721 num_counters += ARRAY_SIZE(cong_cnts);
3722 }
3723
3724 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
3725 if (!cnts->names)
7c16f477
KH		 3726 return -ENOMEM;
3727
e1f24a79
PP		 3728 cnts->offsets = kcalloc(num_counters,
3729 sizeof(cnts->offsets), GFP_KERNEL);
3730 if (!cnts->offsets)
7c16f477
KH		 3731 goto err_names;
3732
7c16f477
KH		 3733 return 0;
3734
3735err_names:
e1f24a79 3736 kfree(cnts->names);
7c16f477
KH		 3737 return -ENOMEM;
3738}
3739
e1f24a79
PP		 3740static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
3741 const char **names,
3742 size_t *offsets)
7c16f477
KH		 3743{
3744 int i;
3745 int j = 0;
3746
3747 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
3748 names[j] = basic_q_cnts[i].name;
3749 offsets[j] = basic_q_cnts[i].offset;
3750 }
3751
3752 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
3753 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
3754 names[j] = out_of_seq_q_cnts[i].name;
3755 offsets[j] = out_of_seq_q_cnts[i].offset;
3756 }
3757 }
3758
3759 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3760 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
3761 names[j] = retrans_q_cnts[i].name;
3762 offsets[j] = retrans_q_cnts[i].offset;
3763 }
3764 }
e1f24a79 3765
58dcb60a
PP		 3766 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
3767 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
3768 names[j] = extended_err_cnts[i].name;
3769 offsets[j] = extended_err_cnts[i].offset;
3770 }
3771 }
3772
e1f24a79
PP		 3773 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3774 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
3775 names[j] = cong_cnts[i].name;
3776 offsets[j] = cong_cnts[i].offset;
3777 }
3778 }
0837e86a
MB		 3779}
3780
e1f24a79 3781static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a
MB		 3782{
3783 int i;
3784 int ret;
3785
3786 for (i = 0; i < dev->num_ports; i++) {
7c16f477
KH		 3787 struct mlx5_ib_port *port = &dev->port[i];
3788
0837e86a 3789 ret = mlx5_core_alloc_q_counter(dev->mdev,
e1f24a79 3790 &port->cnts.set_id);
0837e86a
MB		 3791 if (ret) {
3792 mlx5_ib_warn(dev,
3793 "couldn't allocate queue counter for port %d, err %d\n",
3794 i + 1, ret);
3795 goto dealloc_counters;
3796 }
7c16f477 3797
e1f24a79 3798 ret = __mlx5_ib_alloc_counters(dev, &port->cnts);
7c16f477
KH		 3799 if (ret)
3800 goto dealloc_counters;
3801
e1f24a79
PP		 3802 mlx5_ib_fill_counters(dev, port->cnts.names,
3803 port->cnts.offsets);
0837e86a
MB		 3804 }
3805
3806 return 0;
3807
3808dealloc_counters:
3809 while (--i >= 0)
3810 mlx5_core_dealloc_q_counter(dev->mdev,
e1f24a79 3811 dev->port[i].cnts.set_id);
0837e86a
MB		 3812
3813 return ret;
3814}
3815
0ad17a8f
MB		 3816static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
3817 u8 port_num)
3818{
7c16f477
KH		 3819 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3820 struct mlx5_ib_port *port = &dev->port[port_num - 1];
0ad17a8f
MB		 3821
3822 /* We support only per port stats */
3823 if (port_num == 0)
3824 return NULL;
3825
e1f24a79
PP		 3826 return rdma_alloc_hw_stats_struct(port->cnts.names,
3827 port->cnts.num_q_counters +
3828 port->cnts.num_cong_counters,
0ad17a8f
MB		 3829 RDMA_HW_STATS_DEFAULT_LIFESPAN);
3830}
3831
e1f24a79
PP		 3832static int mlx5_ib_query_q_counters(struct mlx5_ib_dev *dev,
3833 struct mlx5_ib_port *port,
3834 struct rdma_hw_stats *stats)
0ad17a8f 3835{
0ad17a8f
MB		 3836 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3837 void *out;
3838 __be32 val;
e1f24a79 3839 int ret, i;
0ad17a8f 3840
1b9a07ee 3841 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 3842 if (!out)
3843 return -ENOMEM;
3844
3845 ret = mlx5_core_query_q_counter(dev->mdev,
e1f24a79 3846 port->cnts.set_id, 0,
0ad17a8f
MB		 3847 out, outlen);
3848 if (ret)
3849 goto free;
3850
e1f24a79
PP		 3851 for (i = 0; i < port->cnts.num_q_counters; i++) {
3852 val = *(__be32 *)(out + port->cnts.offsets[i]);
0ad17a8f
MB		 3853 stats->value[i] = (u64)be32_to_cpu(val);
3854 }
7c16f477 3855
0ad17a8f
MB		 3856free:
3857 kvfree(out);
e1f24a79
PP		 3858 return ret;
3859}
3860
e1f24a79
PP		 3861static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
3862 struct rdma_hw_stats *stats,
3863 u8 port_num, int index)
3864{
3865 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3866 struct mlx5_ib_port *port = &dev->port[port_num - 1];
3867 int ret, num_counters;
3868
3869 if (!stats)
3870 return -EINVAL;
3871
3872 ret = mlx5_ib_query_q_counters(dev, port, stats);
3873 if (ret)
3874 return ret;
3875 num_counters = port->cnts.num_q_counters;
3876
3877 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
71a0ff65
MD		 3878 ret = mlx5_lag_query_cong_counters(dev->mdev,
3879 stats->value +
3880 port->cnts.num_q_counters,
3881 port->cnts.num_cong_counters,
3882 port->cnts.offsets +
3883 port->cnts.num_q_counters);
e1f24a79
PP		 3884 if (ret)
3885 return ret;
3886 num_counters += port->cnts.num_cong_counters;
3887 }
3888
3889 return num_counters;
0ad17a8f
MB		 3890}
3891
8e959601
NV		 3892static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
3893{
3894 return mlx5_rdma_netdev_free(netdev);
3895}
3896
693dfd5a
ES		 3897static struct net_device*
3898mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
3899 u8 port_num,
3900 enum rdma_netdev_t type,
3901 const char *name,
3902 unsigned char name_assign_type,
3903 void (*setup)(struct net_device *))
3904{
8e959601
NV		 3905 struct net_device *netdev;
3906 struct rdma_netdev *rn;
3907
693dfd5a
ES		 3908 if (type != RDMA_NETDEV_IPOIB)
3909 return ERR_PTR(-EOPNOTSUPP);
3910
8e959601
NV		 3911 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
3912 name, setup);
3913 if (likely(!IS_ERR_OR_NULL(netdev))) {
3914 rn = netdev_priv(netdev);
3915 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
3916 }
3917 return netdev;
693dfd5a
ES		 3918}
3919
fe248c3a
MG		 3920static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
3921{
3922 if (!dev->delay_drop.dbg)
3923 return;
3924 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
3925 kfree(dev->delay_drop.dbg);
3926 dev->delay_drop.dbg = NULL;
3927}
3928
03404e8a
MG		 3929static void cancel_delay_drop(struct mlx5_ib_dev *dev)
3930{
3931 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
3932 return;
3933
3934 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 3935 delay_drop_debugfs_cleanup(dev);
3936}
3937
3938static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
3939 size_t count, loff_t *pos)
3940{
3941 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3942 char lbuf[20];
3943 int len;
3944
3945 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
3946 return simple_read_from_buffer(buf, count, pos, lbuf, len);
3947}
3948
3949static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
3950 size_t count, loff_t *pos)
3951{
3952 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3953 u32 timeout;
3954 u32 var;
3955
3956 if (kstrtouint_from_user(buf, count, 0, &var))
3957 return -EFAULT;
3958
3959 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
3960 1000);
3961 if (timeout != var)
3962 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
3963 timeout);
3964
3965 delay_drop->timeout = timeout;
3966
3967 return count;
3968}
3969
3970static const struct file_operations fops_delay_drop_timeout = {
3971 .owner = THIS_MODULE,
3972 .open = simple_open,
3973 .write = delay_drop_timeout_write,
3974 .read = delay_drop_timeout_read,
3975};
3976
3977static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
3978{
3979 struct mlx5_ib_dbg_delay_drop *dbg;
3980
3981 if (!mlx5_debugfs_root)
3982 return 0;
3983
3984 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
3985 if (!dbg)
3986 return -ENOMEM;
3987
cbafad87
SM		 3988 dev->delay_drop.dbg = dbg;
3989
fe248c3a
MG		 3990 dbg->dir_debugfs =
3991 debugfs_create_dir("delay_drop",
3992 dev->mdev->priv.dbg_root);
3993 if (!dbg->dir_debugfs)
cbafad87 3994 goto out_debugfs;
fe248c3a
MG		 3995
3996 dbg->events_cnt_debugfs =
3997 debugfs_create_atomic_t("num_timeout_events", 0400,
3998 dbg->dir_debugfs,
3999 &dev->delay_drop.events_cnt);
4000 if (!dbg->events_cnt_debugfs)
4001 goto out_debugfs;
4002
4003 dbg->rqs_cnt_debugfs =
4004 debugfs_create_atomic_t("num_rqs", 0400,
4005 dbg->dir_debugfs,
4006 &dev->delay_drop.rqs_cnt);
4007 if (!dbg->rqs_cnt_debugfs)
4008 goto out_debugfs;
4009
4010 dbg->timeout_debugfs =
4011 debugfs_create_file("timeout", 0600,
4012 dbg->dir_debugfs,
4013 &dev->delay_drop,
4014 &fops_delay_drop_timeout);
4015 if (!dbg->timeout_debugfs)
4016 goto out_debugfs;
4017
4018 return 0;
4019
4020out_debugfs:
4021 delay_drop_debugfs_cleanup(dev);
4022 return -ENOMEM;
03404e8a
MG		 4023}
4024
4025static void init_delay_drop(struct mlx5_ib_dev *dev)
4026{
4027 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4028 return;
4029
4030 mutex_init(&dev->delay_drop.lock);
4031 dev->delay_drop.dev = dev;
4032 dev->delay_drop.activate = false;
4033 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
4034 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 4035 atomic_set(&dev->delay_drop.rqs_cnt, 0);
4036 atomic_set(&dev->delay_drop.events_cnt, 0);
4037
4038 if (delay_drop_debugfs_init(dev))
4039 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
03404e8a
MG		 4040}
4041
84305d71
LR		 4042static const struct cpumask *
4043mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
40b24403
SG		 4044{
4045 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4046
4047 return mlx5_get_vector_affinity(dev->mdev, comp_vector);
4048}
4049
16c1975f 4050static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
e126ba97 4051{
3cc297db
MB		 4052#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4053 cleanup_srcu_struct(&dev->mr_srcu);
4054#endif
16c1975f
MB		 4055 kfree(dev->port);
4056}
4057
4058static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
4059{
4060 struct mlx5_core_dev *mdev = dev->mdev;
4babcf97 4061 const char *name;
e126ba97 4062 int err;
e126ba97 4063
0837e86a
MB		 4064 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
4065 GFP_KERNEL);
4066 if (!dev->port)
16c1975f 4067 return -ENOMEM;
0837e86a 4068
fc24fc5e 4069 rwlock_init(&dev->roce.netdev_lock);
e126ba97
EC		 4070 err = get_port_caps(dev);
4071 if (err)
0837e86a 4072 goto err_free_port;
e126ba97 4073
1b5daf11
MD		 4074 if (mlx5_use_mad_ifc(dev))
4075 get_ext_port_caps(dev);
e126ba97 4076
4babcf97
AH		 4077 if (!mlx5_lag_is_active(mdev))
4078 name = "mlx5_%d";
4079 else
4080 name = "mlx5_bond_%d";
4081
4082 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
e126ba97
EC		 4083 dev->ib_dev.owner = THIS_MODULE;
4084 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 4085 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
938fe83c 4086 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
e126ba97 4087 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 4088 dev->ib_dev.num_comp_vectors =
4089 dev->mdev->priv.eq_table.num_comp_vectors;
9b0c289e 4090 dev->ib_dev.dev.parent = &mdev->pdev->dev;
e126ba97 4091
3cc297db
MB		 4092 mutex_init(&dev->flow_db.lock);
4093 mutex_init(&dev->cap_mask_mutex);
4094 INIT_LIST_HEAD(&dev->qp_list);
4095 spin_lock_init(&dev->reset_flow_resource_lock);
4096
4097#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4098 err = init_srcu_struct(&dev->mr_srcu);
4099 if (err)
4100 goto err_free_port;
4101#endif
4102
16c1975f
MB		 4103 return 0;
4104
4105err_free_port:
4106 kfree(dev->port);
4107
4108 return -ENOMEM;
4109}
4110
4111static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
4112{
4113 struct mlx5_core_dev *mdev = dev->mdev;
16c1975f
MB		 4114 int err;
4115
e126ba97
EC		 4116 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
4117 dev->ib_dev.uverbs_cmd_mask =
4118 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
4119 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
4120 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
4121 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
4122 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 4123 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
4124 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 4125 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 4126 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 4127 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
4128 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
4129 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
4130 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
4131 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
4132 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
4133 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
4134 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
4135 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
4136 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
4137 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
4138 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
4139 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
4140 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
4141 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
4142 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
4143 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 4144 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 4145 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
4146 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349 4147 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
b0e9df6d
YC		 4148 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
4149 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
e126ba97
EC		 4150
4151 dev->ib_dev.query_device = mlx5_ib_query_device;
4152 dev->ib_dev.query_port = mlx5_ib_query_port;
ebd61f68 4153 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
e126ba97 4154 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 4155 dev->ib_dev.add_gid = mlx5_ib_add_gid;
4156 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 4157 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
4158 dev->ib_dev.modify_device = mlx5_ib_modify_device;
4159 dev->ib_dev.modify_port = mlx5_ib_modify_port;
4160 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
4161 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
4162 dev->ib_dev.mmap = mlx5_ib_mmap;
4163 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
4164 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
4165 dev->ib_dev.create_ah = mlx5_ib_create_ah;
4166 dev->ib_dev.query_ah = mlx5_ib_query_ah;
4167 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
4168 dev->ib_dev.create_srq = mlx5_ib_create_srq;
4169 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
4170 dev->ib_dev.query_srq = mlx5_ib_query_srq;
4171 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
4172 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
4173 dev->ib_dev.create_qp = mlx5_ib_create_qp;
4174 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
4175 dev->ib_dev.query_qp = mlx5_ib_query_qp;
4176 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
4177 dev->ib_dev.post_send = mlx5_ib_post_send;
4178 dev->ib_dev.post_recv = mlx5_ib_post_recv;
4179 dev->ib_dev.create_cq = mlx5_ib_create_cq;
4180 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
4181 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
4182 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
4183 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
4184 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
4185 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
4186 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 4187 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 4188 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
4189 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
4190 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
4191 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 4192 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 4193 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 4194 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
7738613e 4195 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
c7342823 4196 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
40b24403 4197 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
8e959601 4198 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
022d038a 4199 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
8e959601 4200
eff901d3
EC		 4201 if (mlx5_core_is_pf(mdev)) {
4202 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
4203 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
4204 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
4205 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
4206 }
e126ba97 4207
7c2344c3
MG		 4208 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
4209
6e8484c5
MG		 4210 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
4211
d2370e0a
MB		 4212 if (MLX5_CAP_GEN(mdev, imaicl)) {
4213 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
4214 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
4215 dev->ib_dev.uverbs_cmd_mask |=
4216 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
4217 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
4218 }
4219
938fe83c 4220 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 4221 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
4222 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
4223 dev->ib_dev.uverbs_cmd_mask |=
4224 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
4225 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
4226 }
4227
81e30880
YH		 4228 dev->ib_dev.create_flow = mlx5_ib_create_flow;
4229 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
4230 dev->ib_dev.uverbs_ex_cmd_mask |=
4231 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
4232 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
4233
e126ba97
EC		 4234 err = init_node_data(dev);
4235 if (err)
16c1975f 4236 return err;
e126ba97 4237
c8b89924
MB		 4238 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
4239 MLX5_CAP_GEN(dev->mdev, disable_local_lb))
4240 mutex_init(&dev->lb_mutex);
4241
16c1975f
MB		 4242 return 0;
4243}
4244
4245static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
4246{
4247 struct mlx5_core_dev *mdev = dev->mdev;
4248 enum rdma_link_layer ll;
4249 int port_type_cap;
4250 int err;
4251
4252 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4253 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4254
fc24fc5e 4255 if (ll == IB_LINK_LAYER_ETHERNET) {
c11a226a
MB		 4256 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
4257 dev->ib_dev.create_wq = mlx5_ib_create_wq;
4258 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
4259 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
4260 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
4261 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
4262 dev->ib_dev.uverbs_ex_cmd_mask |=
4263 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
4264 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
4265 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
4266 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
4267 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
45f95acd 4268 err = mlx5_enable_eth(dev);
fc24fc5e 4269 if (err)
16c1975f 4270 return err;
fd65f1b8 4271 dev->roce.last_port_state = IB_PORT_DOWN;
fc24fc5e
AS		 4272 }
4273
16c1975f
MB		 4274 return 0;
4275}
e126ba97 4276
16c1975f
MB		 4277static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
4278{
4279 struct mlx5_core_dev *mdev = dev->mdev;
4280 enum rdma_link_layer ll;
4281 int port_type_cap;
e126ba97 4282
16c1975f
MB		 4283 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4284 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4285
4286 if (ll == IB_LINK_LAYER_ETHERNET) {
4287 mlx5_disable_eth(dev);
4288 mlx5_remove_netdev_notifier(dev);
45bded2c 4289 }
16c1975f 4290}
6aec21f6 4291
16c1975f
MB		 4292static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
4293{
4294 return create_dev_resources(&dev->devr);
4295}
4296
4297static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
4298{
4299 destroy_dev_resources(&dev->devr);
4300}
4301
4302static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
4303{
07321b3c
MB		 4304 mlx5_ib_internal_fill_odp_caps(dev);
4305
16c1975f
MB		 4306 return mlx5_ib_odp_init_one(dev);
4307}
4a2da0b8 4308
16c1975f
MB		 4309static int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
4310{
5e1e7612
MB		 4311 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
4312 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
4313 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
4314
4315 return mlx5_ib_alloc_counters(dev);
4316 }
16c1975f
MB		 4317
4318 return 0;
4319}
4320
4321static void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
4322{
4323 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
4324 mlx5_ib_dealloc_counters(dev);
4325}
4326
4327static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
4328{
4329 return mlx5_ib_init_cong_debugfs(dev);
4330}
4331
4332static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
4333{
4334 mlx5_ib_cleanup_cong_debugfs(dev);
4335}
4336
4337static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
4338{
5fe9dec0
EC		 4339 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
4340 if (!dev->mdev->priv.uar)
16c1975f
MB		 4341 return -ENOMEM;
4342 return 0;
4343}
4344
4345static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
4346{
4347 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4348}
4349
4350static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
4351{
4352 int err;
5fe9dec0
EC		 4353
4354 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4355 if (err)
16c1975f 4356 return err;
5fe9dec0
EC		 4357
4358 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4359 if (err)
16c1975f 4360 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5fe9dec0 4361
16c1975f
MB		 4362 return err;
4363}
0837e86a 4364
16c1975f
MB		 4365static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
4366{
4367 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4368 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4369}
e126ba97 4370
16c1975f
MB		 4371static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
4372{
4373 return ib_register_device(&dev->ib_dev, NULL);
4374}
4375
4376static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
4377{
4378 ib_unregister_device(&dev->ib_dev);
4379}
4380
4381static int mlx5_ib_stage_umr_res_init(struct mlx5_ib_dev *dev)
4382{
4383 return create_umr_res(dev);
4384}
4385
4386static void mlx5_ib_stage_umr_res_cleanup(struct mlx5_ib_dev *dev)
4387{
4388 destroy_umrc_res(dev);
4389}
4390
4391static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
4392{
03404e8a
MG		 4393 init_delay_drop(dev);
4394
16c1975f
MB		 4395 return 0;
4396}
4397
4398static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
4399{
4400 cancel_delay_drop(dev);
4401}
4402
4403static int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev)
4404{
4405 int err;
4406 int i;
4407
e126ba97 4408 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 4409 err = device_create_file(&dev->ib_dev.dev,
4410 mlx5_class_attributes[i]);
4411 if (err)
16c1975f 4412 return err;
e126ba97
EC		 4413 }
4414
16c1975f
MB		 4415 return 0;
4416}
4417
16c1975f
MB		 4418static void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
4419 const struct mlx5_ib_profile *profile,
4420 int stage)
4421{
4422 /* Number of stages to cleanup */
4423 while (stage) {
4424 stage--;
4425 if (profile->stage[stage].cleanup)
4426 profile->stage[stage].cleanup(dev);
4427 }
e126ba97 4428
16c1975f
MB		 4429 ib_dealloc_device((struct ib_device *)dev);
4430}
e126ba97 4431
16c1975f
MB		 4432static void *__mlx5_ib_add(struct mlx5_core_dev *mdev,
4433 const struct mlx5_ib_profile *profile)
4434{
4435 struct mlx5_ib_dev *dev;
4436 int err;
4437 int i;
e126ba97 4438
16c1975f 4439 printk_once(KERN_INFO "%s", mlx5_version);
5fe9dec0 4440
16c1975f
MB		 4441 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
4442 if (!dev)
4443 return NULL;
5fe9dec0 4444
16c1975f 4445 dev->mdev = mdev;
5fe9dec0 4446
16c1975f
MB		 4447 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
4448 if (profile->stage[i].init) {
4449 err = profile->stage[i].init(dev);
4450 if (err)
4451 goto err_out;
4452 }
4453 }
0837e86a 4454
16c1975f
MB		 4455 dev->profile = profile;
4456 dev->ib_active = true;
6aec21f6 4457
16c1975f 4458 return dev;
e126ba97 4459
16c1975f
MB		 4460err_out:
4461 __mlx5_ib_remove(dev, profile, i);
fc24fc5e 4462
16c1975f
MB		 4463 return NULL;
4464}
0837e86a 4465
16c1975f
MB		 4466static const struct mlx5_ib_profile pf_profile = {
4467 STAGE_CREATE(MLX5_IB_STAGE_INIT,
4468 mlx5_ib_stage_init_init,
4469 mlx5_ib_stage_init_cleanup),
4470 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4471 mlx5_ib_stage_caps_init,
4472 NULL),
4473 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4474 mlx5_ib_stage_roce_init,
4475 mlx5_ib_stage_roce_cleanup),
4476 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4477 mlx5_ib_stage_dev_res_init,
4478 mlx5_ib_stage_dev_res_cleanup),
4479 STAGE_CREATE(MLX5_IB_STAGE_ODP,
4480 mlx5_ib_stage_odp_init,
3cc297db 4481 NULL),
16c1975f
MB		 4482 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4483 mlx5_ib_stage_counters_init,
4484 mlx5_ib_stage_counters_cleanup),
4485 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4486 mlx5_ib_stage_cong_debugfs_init,
4487 mlx5_ib_stage_cong_debugfs_cleanup),
4488 STAGE_CREATE(MLX5_IB_STAGE_UAR,
4489 mlx5_ib_stage_uar_init,
4490 mlx5_ib_stage_uar_cleanup),
4491 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4492 mlx5_ib_stage_bfrag_init,
4493 mlx5_ib_stage_bfrag_cleanup),
4494 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4495 mlx5_ib_stage_ib_reg_init,
4496 mlx5_ib_stage_ib_reg_cleanup),
4497 STAGE_CREATE(MLX5_IB_STAGE_UMR_RESOURCES,
4498 mlx5_ib_stage_umr_res_init,
4499 mlx5_ib_stage_umr_res_cleanup),
4500 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
4501 mlx5_ib_stage_delay_drop_init,
4502 mlx5_ib_stage_delay_drop_cleanup),
4503 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
4504 mlx5_ib_stage_class_attr_init,
4505 NULL),
16c1975f 4506};
e126ba97 4507
16c1975f
MB		 4508static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
4509{
4510 return __mlx5_ib_add(mdev, &pf_profile);
e126ba97
EC		 4511}
4512
9603b61d 4513static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 4514{
9603b61d 4515 struct mlx5_ib_dev *dev = context;
6aec21f6 4516
16c1975f 4517 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
e126ba97
EC		 4518}
4519
9603b61d
JM		 4520static struct mlx5_interface mlx5_ib_interface = {
4521 .add = mlx5_ib_add,
4522 .remove = mlx5_ib_remove,
4523 .event = mlx5_ib_event,
d9aaed83
AK		 4524#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4525 .pfault = mlx5_ib_pfault,
4526#endif
64613d94 4527 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 4528};
4529
4530static int __init mlx5_ib_init(void)
4531{
6aec21f6
HE		 4532 int err;
4533
81713d37 4534 mlx5_ib_odp_init();
9603b61d 4535
6aec21f6 4536 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 4537
6aec21f6 4538 return err;
e126ba97
EC		 4539}
4540
4541static void __exit mlx5_ib_cleanup(void)
4542{
9603b61d 4543 mlx5_unregister_interface(&mlx5_ib_interface);
e126ba97
EC		 4544}
4545
4546module_init(mlx5_ib_init);
4547module_exit(mlx5_ib_cleanup);
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