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IB/mlx5: Set uid as part of DCT commands
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
24da0016 41#include <linux/bitmap.h>
37aa5c36
GL		 42#if defined(CONFIG_X86)
43#include <asm/pat.h>
44#endif
e126ba97 45#include <linux/sched.h>
6e84f315 46#include <linux/sched/mm.h>
0881e7bd 47#include <linux/sched/task.h>
7c2344c3 48#include <linux/delay.h>
e126ba97 49#include <rdma/ib_user_verbs.h>
3f89a643 50#include <rdma/ib_addr.h>
2811ba51 51#include <rdma/ib_cache.h>
ada68c31 52#include <linux/mlx5/port.h>
1b5daf11 53#include <linux/mlx5/vport.h>
72c7fe90 54#include <linux/mlx5/fs.h>
7c2344c3 55#include <linux/list.h>
e126ba97
EC		 56#include <rdma/ib_smi.h>
57#include <rdma/ib_umem.h>
038d2ef8
MG		 58#include <linux/in.h>
59#include <linux/etherdevice.h>
e126ba97 60#include "mlx5_ib.h"
fc385b7a 61#include "ib_rep.h"
e1f24a79 62#include "cmd.h"
3346c487 63#include <linux/mlx5/fs_helpers.h>
c6475a0b 64#include <linux/mlx5/accel.h>
8c84660b 65#include <rdma/uverbs_std_types.h>
c6475a0b
AY		 66#include <rdma/mlx5_user_ioctl_verbs.h>
67#include <rdma/mlx5_user_ioctl_cmds.h>
8c84660b
MB		 68
69#define UVERBS_MODULE_NAME mlx5_ib
70#include <rdma/uverbs_named_ioctl.h>
e126ba97
EC		 71
72#define DRIVER_NAME "mlx5_ib"
b359911d 73#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 74
75MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
76MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
77MODULE_LICENSE("Dual BSD/GPL");
e126ba97 78
e126ba97
EC		 79static char mlx5_version[] =
80 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 81 DRIVER_VERSION "\n";
e126ba97 82
d69a24e0
DJ		 83struct mlx5_ib_event_work {
84 struct work_struct work;
85 struct mlx5_core_dev *dev;
86 void *context;
87 enum mlx5_dev_event event;
88 unsigned long param;
89};
90
da7525d2
EBE		 91enum {
92 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
93};
94
d69a24e0 95static struct workqueue_struct *mlx5_ib_event_wq;
32f69e4b
DJ		 96static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
97static LIST_HEAD(mlx5_ib_dev_list);
98/*
99 * This mutex should be held when accessing either of the above lists
100 */
101static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
102
c44ef998
IL		 103/* We can't use an array for xlt_emergency_page because dma_map_single
104 * doesn't work on kernel modules memory
105 */
106static unsigned long xlt_emergency_page;
107static struct mutex xlt_emergency_page_mutex;
108
32f69e4b
DJ		 109struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
110{
111 struct mlx5_ib_dev *dev;
112
113 mutex_lock(&mlx5_ib_multiport_mutex);
114 dev = mpi->ibdev;
115 mutex_unlock(&mlx5_ib_multiport_mutex);
116 return dev;
117}
118
1b5daf11 119static enum rdma_link_layer
ebd61f68 120mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 121{
ebd61f68 122 switch (port_type_cap) {
1b5daf11
MD		 123 case MLX5_CAP_PORT_TYPE_IB:
124 return IB_LINK_LAYER_INFINIBAND;
125 case MLX5_CAP_PORT_TYPE_ETH:
126 return IB_LINK_LAYER_ETHERNET;
127 default:
128 return IB_LINK_LAYER_UNSPECIFIED;
129 }
130}
131
ebd61f68
AS		 132static enum rdma_link_layer
133mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
134{
135 struct mlx5_ib_dev *dev = to_mdev(device);
136 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
137
138 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
139}
140
fd65f1b8
MS		 141static int get_port_state(struct ib_device *ibdev,
142 u8 port_num,
143 enum ib_port_state *state)
144{
145 struct ib_port_attr attr;
146 int ret;
147
148 memset(&attr, 0, sizeof(attr));
8e6efa3a 149 ret = ibdev->query_port(ibdev, port_num, &attr);
fd65f1b8
MS		 150 if (!ret)
151 *state = attr.state;
152 return ret;
153}
154
fc24fc5e
AS		 155static int mlx5_netdev_event(struct notifier_block *this,
156 unsigned long event, void *ptr)
157{
7fd8aefb 158 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
fc24fc5e 159 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
7fd8aefb
DJ		 160 u8 port_num = roce->native_port_num;
161 struct mlx5_core_dev *mdev;
162 struct mlx5_ib_dev *ibdev;
163
164 ibdev = roce->dev;
32f69e4b
DJ		 165 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
166 if (!mdev)
167 return NOTIFY_DONE;
fc24fc5e 168
5ec8c83e
AH		 169 switch (event) {
170 case NETDEV_REGISTER:
171 case NETDEV_UNREGISTER:
7fd8aefb 172 write_lock(&roce->netdev_lock);
bcf87f1d
MB		 173 if (ibdev->rep) {
174 struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch;
175 struct net_device *rep_ndev;
176
177 rep_ndev = mlx5_ib_get_rep_netdev(esw,
178 ibdev->rep->vport);
179 if (rep_ndev == ndev)
180 roce->netdev = (event == NETDEV_UNREGISTER) ?
7fd8aefb 181 NULL : ndev;
84a6a7a9 182 } else if (ndev->dev.parent == &mdev->pdev->dev) {
bcf87f1d
MB		 183 roce->netdev = (event == NETDEV_UNREGISTER) ?
184 NULL : ndev;
185 }
7fd8aefb 186 write_unlock(&roce->netdev_lock);
5ec8c83e 187 break;
fc24fc5e 188
fd65f1b8 189 case NETDEV_CHANGE:
5ec8c83e 190 case NETDEV_UP:
88621dfe 191 case NETDEV_DOWN: {
7fd8aefb 192 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe
AH		 193 struct net_device *upper = NULL;
194
195 if (lag_ndev) {
196 upper = netdev_master_upper_dev_get(lag_ndev);
197 dev_put(lag_ndev);
198 }
199
7fd8aefb 200 if ((upper == ndev || (!upper && ndev == roce->netdev))
88621dfe 201 && ibdev->ib_active) {
626bc02d 202 struct ib_event ibev = { };
fd65f1b8 203 enum ib_port_state port_state;
5ec8c83e 204
7fd8aefb
DJ		 205 if (get_port_state(&ibdev->ib_dev, port_num,
206 &port_state))
207 goto done;
fd65f1b8 208
7fd8aefb
DJ		 209 if (roce->last_port_state == port_state)
210 goto done;
fd65f1b8 211
7fd8aefb 212 roce->last_port_state = port_state;
5ec8c83e 213 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 214 if (port_state == IB_PORT_DOWN)
215 ibev.event = IB_EVENT_PORT_ERR;
216 else if (port_state == IB_PORT_ACTIVE)
217 ibev.event = IB_EVENT_PORT_ACTIVE;
218 else
7fd8aefb 219 goto done;
fd65f1b8 220
7fd8aefb 221 ibev.element.port_num = port_num;
5ec8c83e
AH		 222 ib_dispatch_event(&ibev);
223 }
224 break;
88621dfe 225 }
fc24fc5e 226
5ec8c83e
AH		 227 default:
228 break;
229 }
7fd8aefb 230done:
32f69e4b 231 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 232 return NOTIFY_DONE;
233}
234
235static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
236 u8 port_num)
237{
238 struct mlx5_ib_dev *ibdev = to_mdev(device);
239 struct net_device *ndev;
32f69e4b
DJ		 240 struct mlx5_core_dev *mdev;
241
242 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
243 if (!mdev)
244 return NULL;
fc24fc5e 245
32f69e4b 246 ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe 247 if (ndev)
32f69e4b 248 goto out;
88621dfe 249
fc24fc5e
AS		 250 /* Ensure ndev does not disappear before we invoke dev_hold()
251 */
7fd8aefb
DJ		 252 read_lock(&ibdev->roce[port_num - 1].netdev_lock);
253 ndev = ibdev->roce[port_num - 1].netdev;
fc24fc5e
AS		 254 if (ndev)
255 dev_hold(ndev);
7fd8aefb 256 read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
fc24fc5e 257
32f69e4b
DJ		 258out:
259 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 260 return ndev;
261}
262
32f69e4b
DJ		 263struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
264 u8 ib_port_num,
265 u8 *native_port_num)
266{
267 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
268 ib_port_num);
269 struct mlx5_core_dev *mdev = NULL;
270 struct mlx5_ib_multiport_info *mpi;
271 struct mlx5_ib_port *port;
272
210b1f78
MB		 273 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
274 ll != IB_LINK_LAYER_ETHERNET) {
275 if (native_port_num)
276 *native_port_num = ib_port_num;
277 return ibdev->mdev;
278 }
279
32f69e4b
DJ		 280 if (native_port_num)
281 *native_port_num = 1;
282
32f69e4b
DJ		 283 port = &ibdev->port[ib_port_num - 1];
284 if (!port)
285 return NULL;
286
287 spin_lock(&port->mp.mpi_lock);
288 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
289 if (mpi && !mpi->unaffiliate) {
290 mdev = mpi->mdev;
291 /* If it's the master no need to refcount, it'll exist
292 * as long as the ib_dev exists.
293 */
294 if (!mpi->is_master)
295 mpi->mdev_refcnt++;
296 }
297 spin_unlock(&port->mp.mpi_lock);
298
299 return mdev;
300}
301
302void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
303{
304 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
305 port_num);
306 struct mlx5_ib_multiport_info *mpi;
307 struct mlx5_ib_port *port;
308
309 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
310 return;
311
312 port = &ibdev->port[port_num - 1];
313
314 spin_lock(&port->mp.mpi_lock);
315 mpi = ibdev->port[port_num - 1].mp.mpi;
316 if (mpi->is_master)
317 goto out;
318
319 mpi->mdev_refcnt--;
320 if (mpi->unaffiliate)
321 complete(&mpi->unref_comp);
322out:
323 spin_unlock(&port->mp.mpi_lock);
324}
325
f1b65df5
NO		 326static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
327 u8 *active_width)
328{
329 switch (eth_proto_oper) {
330 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
331 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
332 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
333 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
334 *active_width = IB_WIDTH_1X;
335 *active_speed = IB_SPEED_SDR;
336 break;
337 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
338 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
339 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
340 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
341 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
342 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
343 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
344 *active_width = IB_WIDTH_1X;
345 *active_speed = IB_SPEED_QDR;
346 break;
347 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
348 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
349 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
350 *active_width = IB_WIDTH_1X;
351 *active_speed = IB_SPEED_EDR;
352 break;
353 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
354 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
355 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
356 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
357 *active_width = IB_WIDTH_4X;
358 *active_speed = IB_SPEED_QDR;
359 break;
360 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
361 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
362 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
363 *active_width = IB_WIDTH_1X;
364 *active_speed = IB_SPEED_HDR;
365 break;
366 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
367 *active_width = IB_WIDTH_4X;
368 *active_speed = IB_SPEED_FDR;
369 break;
370 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
371 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
372 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
373 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
374 *active_width = IB_WIDTH_4X;
375 *active_speed = IB_SPEED_EDR;
376 break;
377 default:
378 return -EINVAL;
379 }
380
381 return 0;
382}
383
095b0927
IT		 384static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
385 struct ib_port_attr *props)
3f89a643
AS		 386{
387 struct mlx5_ib_dev *dev = to_mdev(device);
da005f9f 388 struct mlx5_core_dev *mdev;
88621dfe 389 struct net_device *ndev, *upper;
3f89a643 390 enum ib_mtu ndev_ib_mtu;
b3cbd6f0 391 bool put_mdev = true;
c876a1b7 392 u16 qkey_viol_cntr;
f1b65df5 393 u32 eth_prot_oper;
b3cbd6f0 394 u8 mdev_port_num;
095b0927 395 int err;
3f89a643 396
b3cbd6f0
DJ		 397 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
398 if (!mdev) {
399 /* This means the port isn't affiliated yet. Get the
400 * info for the master port instead.
401 */
402 put_mdev = false;
403 mdev = dev->mdev;
404 mdev_port_num = 1;
405 port_num = 1;
406 }
407
f1b65df5
NO		 408 /* Possible bad flows are checked before filling out props so in case
409 * of an error it will still be zeroed out.
50f22fd8 410 */
b3cbd6f0
DJ		 411 err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper,
412 mdev_port_num);
095b0927 413 if (err)
b3cbd6f0 414 goto out;
f1b65df5 415
7672ed33
HL		 416 props->active_width = IB_WIDTH_4X;
417 props->active_speed = IB_SPEED_QDR;
418
f1b65df5
NO		 419 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
420 &props->active_width);
3f89a643 421
2f944c0f
JG		 422 props->port_cap_flags |= IB_PORT_CM_SUP;
423 props->ip_gids = true;
3f89a643
AS		 424
425 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
426 roce_address_table_size);
427 props->max_mtu = IB_MTU_4096;
428 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
429 props->pkey_tbl_len = 1;
430 props->state = IB_PORT_DOWN;
431 props->phys_state = 3;
432
b3cbd6f0 433 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
c876a1b7 434 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643 435
b3cbd6f0
DJ		 436 /* If this is a stub query for an unaffiliated port stop here */
437 if (!put_mdev)
438 goto out;
439
3f89a643
AS		 440 ndev = mlx5_ib_get_netdev(device, port_num);
441 if (!ndev)
b3cbd6f0 442 goto out;
3f89a643 443
88621dfe
AH		 444 if (mlx5_lag_is_active(dev->mdev)) {
445 rcu_read_lock();
446 upper = netdev_master_upper_dev_get_rcu(ndev);
447 if (upper) {
448 dev_put(ndev);
449 ndev = upper;
450 dev_hold(ndev);
451 }
452 rcu_read_unlock();
453 }
454
3f89a643
AS		 455 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
456 props->state = IB_PORT_ACTIVE;
457 props->phys_state = 5;
458 }
459
460 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
461
462 dev_put(ndev);
463
464 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
b3cbd6f0
DJ		 465out:
466 if (put_mdev)
467 mlx5_ib_put_native_port_mdev(dev, port_num);
468 return err;
3f89a643
AS		 469}
470
095b0927
IT		 471static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
472 unsigned int index, const union ib_gid *gid,
473 const struct ib_gid_attr *attr)
3cca2606 474{
095b0927
IT		 475 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
476 u8 roce_version = 0;
477 u8 roce_l3_type = 0;
478 bool vlan = false;
479 u8 mac[ETH_ALEN];
480 u16 vlan_id = 0;
481
482 if (gid) {
483 gid_type = attr->gid_type;
484 ether_addr_copy(mac, attr->ndev->dev_addr);
485
486 if (is_vlan_dev(attr->ndev)) {
487 vlan = true;
488 vlan_id = vlan_dev_vlan_id(attr->ndev);
489 }
3cca2606
AS		 490 }
491
095b0927 492 switch (gid_type) {
3cca2606 493 case IB_GID_TYPE_IB:
095b0927 494 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 495 break;
496 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 497 roce_version = MLX5_ROCE_VERSION_2;
498 if (ipv6_addr_v4mapped((void *)gid))
499 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
500 else
501 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 502 break;
503
504 default:
095b0927 505 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 506 }
507
095b0927
IT		 508 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
509 roce_l3_type, gid->raw, mac, vlan,
cfe4e37f 510 vlan_id, port_num);
3cca2606
AS		 511}
512
f4df9a7c 513static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
3cca2606
AS		 514 __always_unused void **context)
515{
414448d2 516 return set_roce_addr(to_mdev(attr->device), attr->port_num,
f4df9a7c 517 attr->index, &attr->gid, attr);
3cca2606
AS		 518}
519
414448d2
PP		 520static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
521 __always_unused void **context)
3cca2606 522{
414448d2
PP		 523 return set_roce_addr(to_mdev(attr->device), attr->port_num,
524 attr->index, NULL, NULL);
3cca2606
AS		 525}
526
47ec3866
PP		 527__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
528 const struct ib_gid_attr *attr)
2811ba51 529{
47ec3866 530 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
2811ba51
AS		 531 return 0;
532
533 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
534}
535
1b5daf11
MD		 536static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
537{
7fae6655
NO		 538 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
539 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
540 return 0;
1b5daf11
MD		 541}
542
543enum {
544 MLX5_VPORT_ACCESS_METHOD_MAD,
545 MLX5_VPORT_ACCESS_METHOD_HCA,
546 MLX5_VPORT_ACCESS_METHOD_NIC,
547};
548
549static int mlx5_get_vport_access_method(struct ib_device *ibdev)
550{
551 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
552 return MLX5_VPORT_ACCESS_METHOD_MAD;
553
ebd61f68 554 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 555 IB_LINK_LAYER_ETHERNET)
556 return MLX5_VPORT_ACCESS_METHOD_NIC;
557
558 return MLX5_VPORT_ACCESS_METHOD_HCA;
559}
560
da7525d2 561static void get_atomic_caps(struct mlx5_ib_dev *dev,
776a3906 562 u8 atomic_size_qp,
da7525d2
EBE		 563 struct ib_device_attr *props)
564{
565 u8 tmp;
566 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
da7525d2 567 u8 atomic_req_8B_endianness_mode =
bd10838a 568 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 569
570 /* Check if HW supports 8 bytes standard atomic operations and capable
571 * of host endianness respond
572 */
573 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
574 if (((atomic_operations & tmp) == tmp) &&
575 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
576 (atomic_req_8B_endianness_mode)) {
577 props->atomic_cap = IB_ATOMIC_HCA;
578 } else {
579 props->atomic_cap = IB_ATOMIC_NONE;
580 }
581}
582
776a3906
MS		 583static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
584 struct ib_device_attr *props)
585{
586 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
587
588 get_atomic_caps(dev, atomic_size_qp, props);
589}
590
591static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
592 struct ib_device_attr *props)
593{
594 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
595
596 get_atomic_caps(dev, atomic_size_qp, props);
597}
598
599bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
600{
601 struct ib_device_attr props = {};
602
603 get_atomic_caps_dc(dev, &props);
604 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
605}
1b5daf11
MD		 606static int mlx5_query_system_image_guid(struct ib_device *ibdev,
607 __be64 *sys_image_guid)
608{
609 struct mlx5_ib_dev *dev = to_mdev(ibdev);
610 struct mlx5_core_dev *mdev = dev->mdev;
611 u64 tmp;
612 int err;
613
614 switch (mlx5_get_vport_access_method(ibdev)) {
615 case MLX5_VPORT_ACCESS_METHOD_MAD:
616 return mlx5_query_mad_ifc_system_image_guid(ibdev,
617 sys_image_guid);
618
619 case MLX5_VPORT_ACCESS_METHOD_HCA:
620 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 621 break;
622
623 case MLX5_VPORT_ACCESS_METHOD_NIC:
624 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
625 break;
1b5daf11
MD		 626
627 default:
628 return -EINVAL;
629 }
3f89a643
AS		 630
631 if (!err)
632 *sys_image_guid = cpu_to_be64(tmp);
633
634 return err;
635
1b5daf11
MD		 636}
637
638static int mlx5_query_max_pkeys(struct ib_device *ibdev,
639 u16 *max_pkeys)
640{
641 struct mlx5_ib_dev *dev = to_mdev(ibdev);
642 struct mlx5_core_dev *mdev = dev->mdev;
643
644 switch (mlx5_get_vport_access_method(ibdev)) {
645 case MLX5_VPORT_ACCESS_METHOD_MAD:
646 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
647
648 case MLX5_VPORT_ACCESS_METHOD_HCA:
649 case MLX5_VPORT_ACCESS_METHOD_NIC:
650 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
651 pkey_table_size));
652 return 0;
653
654 default:
655 return -EINVAL;
656 }
657}
658
659static int mlx5_query_vendor_id(struct ib_device *ibdev,
660 u32 *vendor_id)
661{
662 struct mlx5_ib_dev *dev = to_mdev(ibdev);
663
664 switch (mlx5_get_vport_access_method(ibdev)) {
665 case MLX5_VPORT_ACCESS_METHOD_MAD:
666 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
667
668 case MLX5_VPORT_ACCESS_METHOD_HCA:
669 case MLX5_VPORT_ACCESS_METHOD_NIC:
670 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
671
672 default:
673 return -EINVAL;
674 }
675}
676
677static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
678 __be64 *node_guid)
679{
680 u64 tmp;
681 int err;
682
683 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
684 case MLX5_VPORT_ACCESS_METHOD_MAD:
685 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
686
687 case MLX5_VPORT_ACCESS_METHOD_HCA:
688 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 689 break;
690
691 case MLX5_VPORT_ACCESS_METHOD_NIC:
692 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
693 break;
1b5daf11
MD		 694
695 default:
696 return -EINVAL;
697 }
3f89a643
AS		 698
699 if (!err)
700 *node_guid = cpu_to_be64(tmp);
701
702 return err;
1b5daf11
MD		 703}
704
705struct mlx5_reg_node_desc {
bd99fdea 706 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 707};
708
709static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
710{
711 struct mlx5_reg_node_desc in;
712
713 if (mlx5_use_mad_ifc(dev))
714 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
715
716 memset(&in, 0, sizeof(in));
717
718 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
719 sizeof(struct mlx5_reg_node_desc),
720 MLX5_REG_NODE_DESC, 0, 0);
721}
722
e126ba97 723static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 724 struct ib_device_attr *props,
725 struct ib_udata *uhw)
e126ba97
EC		 726{
727 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 728 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 729 int err = -ENOMEM;
288c01b7 730 int max_sq_desc;
e126ba97
EC		 731 int max_rq_sg;
732 int max_sq_sg;
e0238a6a 733 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
85c7c014 734 bool raw_support = !mlx5_core_mp_enabled(mdev);
402ca536
BW		 735 struct mlx5_ib_query_device_resp resp = {};
736 size_t resp_len;
737 u64 max_tso;
e126ba97 738
402ca536
BW		 739 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
740 if (uhw->outlen && uhw->outlen < resp_len)
741 return -EINVAL;
742 else
743 resp.response_length = resp_len;
744
745 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 746 return -EINVAL;
747
1b5daf11
MD		 748 memset(props, 0, sizeof(*props));
749 err = mlx5_query_system_image_guid(ibdev,
750 &props->sys_image_guid);
751 if (err)
752 return err;
e126ba97 753
1b5daf11 754 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 755 if (err)
1b5daf11 756 return err;
e126ba97 757
1b5daf11
MD		 758 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
759 if (err)
760 return err;
e126ba97 761
9603b61d
JM		 762 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
763 (fw_rev_min(dev->mdev) << 16) |
764 fw_rev_sub(dev->mdev);
e126ba97
EC		 765 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
766 IB_DEVICE_PORT_ACTIVE_EVENT |
767 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 768 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 769
770 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 771 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 772 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 773 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 774 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 775 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 776 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 777 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 778 if (MLX5_CAP_GEN(mdev, imaicl)) {
779 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
780 IB_DEVICE_MEM_WINDOW_TYPE_2B;
781 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 782 /* We support 'Gappy' memory registration too */
783 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 784 }
e126ba97 785 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 786 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 787 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
788 /* At this stage no support for signature handover */
789 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
790 IB_PROT_T10DIF_TYPE_2 |
791 IB_PROT_T10DIF_TYPE_3;
792 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
793 IB_GUARD_T10DIF_CSUM;
794 }
938fe83c 795 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 796 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 797
85c7c014 798 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
e8161334
NO		 799 if (MLX5_CAP_ETH(mdev, csum_cap)) {
800 /* Legacy bit to support old userspace libraries */
88115fe7 801 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 802 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
803 }
804
805 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
806 props->raw_packet_caps |=
807 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 808
402ca536
BW		 809 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
810 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
811 if (max_tso) {
812 resp.tso_caps.max_tso = 1 << max_tso;
813 resp.tso_caps.supported_qpts |=
814 1 << IB_QPT_RAW_PACKET;
815 resp.response_length += sizeof(resp.tso_caps);
816 }
817 }
31f69a82
YH		 818
819 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
820 resp.rss_caps.rx_hash_function =
821 MLX5_RX_HASH_FUNC_TOEPLITZ;
822 resp.rss_caps.rx_hash_fields_mask =
823 MLX5_RX_HASH_SRC_IPV4 |
824 MLX5_RX_HASH_DST_IPV4 |
825 MLX5_RX_HASH_SRC_IPV6 |
826 MLX5_RX_HASH_DST_IPV6 |
827 MLX5_RX_HASH_SRC_PORT_TCP |
828 MLX5_RX_HASH_DST_PORT_TCP |
829 MLX5_RX_HASH_SRC_PORT_UDP |
4e2b53a5
MG		 830 MLX5_RX_HASH_DST_PORT_UDP |
831 MLX5_RX_HASH_INNER;
2d93fc85
MB		 832 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
833 MLX5_ACCEL_IPSEC_CAP_DEVICE)
834 resp.rss_caps.rx_hash_fields_mask |=
835 MLX5_RX_HASH_IPSEC_SPI;
31f69a82
YH		 836 resp.response_length += sizeof(resp.rss_caps);
837 }
838 } else {
839 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
840 resp.response_length += sizeof(resp.tso_caps);
841 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
842 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 843 }
844
f0313965
ES		 845 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
846 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
847 props->device_cap_flags |= IB_DEVICE_UD_TSO;
848 }
849
03404e8a 850 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
85c7c014
DJ		 851 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
852 raw_support)
03404e8a
MG		 853 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
854
1d54f890
YH		 855 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
856 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
857 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
858
cff5a0f3 859 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
85c7c014
DJ		 860 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
861 raw_support) {
e8161334 862 /* Legacy bit to support old userspace libraries */
cff5a0f3 863 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 864 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
865 }
cff5a0f3 866
24da0016
AL		 867 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
868 props->max_dm_size =
869 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
870 }
871
da6d6ba3
MG		 872 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
873 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
874
b1383aa6
NO		 875 if (MLX5_CAP_GEN(mdev, end_pad))
876 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
877
1b5daf11
MD		 878 props->vendor_part_id = mdev->pdev->device;
879 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 880
881 props->max_mr_size = ~0ull;
e0238a6a 882 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 883 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
884 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
885 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
886 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 887 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
888 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
889 sizeof(struct mlx5_wqe_raddr_seg)) /
890 sizeof(struct mlx5_wqe_data_seg);
33023fb8
SW		 891 props->max_send_sge = max_sq_sg;
892 props->max_recv_sge = max_rq_sg;
986ef95e 893 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 894 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 895 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 896 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
897 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
898 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
899 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
900 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
901 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
902 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 903 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 904 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 905 props->max_fast_reg_page_list_len =
906 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
776a3906 907 get_atomic_caps_qp(dev, props);
81bea28f 908 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 909 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
910 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 911 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
912 props->max_mcast_grp;
913 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 914 props->max_ah = INT_MAX;
7c60bcbb
MB		 915 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
916 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 917
8cdd312c 918#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 919 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 920 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
921 props->odp_caps = dev->odp_caps;
922#endif
923
051f2630
LR		 924 if (MLX5_CAP_GEN(mdev, cd))
925 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
926
eff901d3
EC		 927 if (!mlx5_core_is_pf(mdev))
928 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
929
31f69a82 930 if (mlx5_ib_port_link_layer(ibdev, 1) ==
85c7c014 931 IB_LINK_LAYER_ETHERNET && raw_support) {
31f69a82
YH		 932 props->rss_caps.max_rwq_indirection_tables =
933 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
934 props->rss_caps.max_rwq_indirection_table_size =
935 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
936 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
937 props->max_wq_type_rq =
938 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
939 }
940
eb761894 941 if (MLX5_CAP_GEN(mdev, tag_matching)) {
78b1beb0
LR		 942 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
943 props->tm_caps.max_num_tags =
eb761894 944 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
78b1beb0
LR		 945 props->tm_caps.flags = IB_TM_CAP_RC;
946 props->tm_caps.max_ops =
eb761894 947 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
78b1beb0 948 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
eb761894
AK		 949 }
950
87ab3f52
YC		 951 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
952 props->cq_caps.max_cq_moderation_count =
953 MLX5_MAX_CQ_COUNT;
954 props->cq_caps.max_cq_moderation_period =
955 MLX5_MAX_CQ_PERIOD;
956 }
957
7e43a2a5 958 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
7e43a2a5 959 resp.response_length += sizeof(resp.cqe_comp_caps);
572f46bf
YC		 960
961 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
962 resp.cqe_comp_caps.max_num =
963 MLX5_CAP_GEN(dev->mdev,
964 cqe_compression_max_num);
965
966 resp.cqe_comp_caps.supported_format =
967 MLX5_IB_CQE_RES_FORMAT_HASH |
968 MLX5_IB_CQE_RES_FORMAT_CSUM;
6f1006a4
YC		 969
970 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
971 resp.cqe_comp_caps.supported_format |=
972 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
572f46bf 973 }
7e43a2a5
BW		 974 }
975
85c7c014
DJ		 976 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
977 raw_support) {
d949167d
BW		 978 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
979 MLX5_CAP_GEN(mdev, qos)) {
980 resp.packet_pacing_caps.qp_rate_limit_max =
981 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
982 resp.packet_pacing_caps.qp_rate_limit_min =
983 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
984 resp.packet_pacing_caps.supported_qpts |=
985 1 << IB_QPT_RAW_PACKET;
61147f39
BW		 986 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
987 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
988 resp.packet_pacing_caps.cap_flags |=
989 MLX5_IB_PP_SUPPORT_BURST;
d949167d
BW		 990 }
991 resp.response_length += sizeof(resp.packet_pacing_caps);
992 }
993
9f885201
LR		 994 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
995 uhw->outlen)) {
795b609c
BW		 996 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
997 resp.mlx5_ib_support_multi_pkt_send_wqes =
998 MLX5_IB_ALLOW_MPW;
050da902
BW		 999
1000 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1001 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1002 MLX5_IB_SUPPORT_EMPW;
1003
9f885201
LR		 1004 resp.response_length +=
1005 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1006 }
1007
de57f2ad
GL		 1008 if (field_avail(typeof(resp), flags, uhw->outlen)) {
1009 resp.response_length += sizeof(resp.flags);
7a0c8f42 1010
de57f2ad
GL		 1011 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1012 resp.flags |=
1013 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
7a0c8f42
GL		 1014
1015 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1016 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
de57f2ad 1017 }
9f885201 1018
96dc3fc5
NO		 1019 if (field_avail(typeof(resp), sw_parsing_caps,
1020 uhw->outlen)) {
1021 resp.response_length += sizeof(resp.sw_parsing_caps);
1022 if (MLX5_CAP_ETH(mdev, swp)) {
1023 resp.sw_parsing_caps.sw_parsing_offloads |=
1024 MLX5_IB_SW_PARSING;
1025
1026 if (MLX5_CAP_ETH(mdev, swp_csum))
1027 resp.sw_parsing_caps.sw_parsing_offloads |=
1028 MLX5_IB_SW_PARSING_CSUM;
1029
1030 if (MLX5_CAP_ETH(mdev, swp_lso))
1031 resp.sw_parsing_caps.sw_parsing_offloads |=
1032 MLX5_IB_SW_PARSING_LSO;
1033
1034 if (resp.sw_parsing_caps.sw_parsing_offloads)
1035 resp.sw_parsing_caps.supported_qpts =
1036 BIT(IB_QPT_RAW_PACKET);
1037 }
1038 }
1039
85c7c014
DJ		 1040 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1041 raw_support) {
b4f34597
NO		 1042 resp.response_length += sizeof(resp.striding_rq_caps);
1043 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1044 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1045 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1046 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1047 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1048 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1049 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1050 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1051 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1052 resp.striding_rq_caps.supported_qpts =
1053 BIT(IB_QPT_RAW_PACKET);
1054 }
1055 }
1056
f95ef6cb
MG		 1057 if (field_avail(typeof(resp), tunnel_offloads_caps,
1058 uhw->outlen)) {
1059 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1060 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1061 resp.tunnel_offloads_caps |=
1062 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1063 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1064 resp.tunnel_offloads_caps |=
1065 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1066 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1067 resp.tunnel_offloads_caps |=
1068 MLX5_IB_TUNNELED_OFFLOADS_GRE;
e818e255
AL		 1069 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1070 MLX5_FLEX_PROTO_CW_MPLS_GRE)
1071 resp.tunnel_offloads_caps |=
1072 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1073 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1074 MLX5_FLEX_PROTO_CW_MPLS_UDP)
1075 resp.tunnel_offloads_caps |=
1076 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
f95ef6cb
MG		 1077 }
1078
402ca536
BW		 1079 if (uhw->outlen) {
1080 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1081
1082 if (err)
1083 return err;
1084 }
1085
1b5daf11 1086 return 0;
e126ba97
EC		 1087}
1088
1b5daf11
MD		 1089enum mlx5_ib_width {
1090 MLX5_IB_WIDTH_1X = 1 << 0,
1091 MLX5_IB_WIDTH_2X = 1 << 1,
1092 MLX5_IB_WIDTH_4X = 1 << 2,
1093 MLX5_IB_WIDTH_8X = 1 << 3,
1094 MLX5_IB_WIDTH_12X = 1 << 4
1095};
1096
1097static int translate_active_width(struct ib_device *ibdev, u8 active_width,
1098 u8 *ib_width)
e126ba97
EC		 1099{
1100 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 1101 int err = 0;
1102
1103 if (active_width & MLX5_IB_WIDTH_1X) {
1104 *ib_width = IB_WIDTH_1X;
1105 } else if (active_width & MLX5_IB_WIDTH_2X) {
1106 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
1107 (int)active_width);
1108 err = -EINVAL;
1109 } else if (active_width & MLX5_IB_WIDTH_4X) {
1110 *ib_width = IB_WIDTH_4X;
1111 } else if (active_width & MLX5_IB_WIDTH_8X) {
1112 *ib_width = IB_WIDTH_8X;
1113 } else if (active_width & MLX5_IB_WIDTH_12X) {
1114 *ib_width = IB_WIDTH_12X;
1115 } else {
1116 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
1117 (int)active_width);
1118 err = -EINVAL;
e126ba97
EC		 1119 }
1120
1b5daf11
MD		 1121 return err;
1122}
e126ba97 1123
1b5daf11
MD		 1124static int mlx5_mtu_to_ib_mtu(int mtu)
1125{
1126 switch (mtu) {
1127 case 256: return 1;
1128 case 512: return 2;
1129 case 1024: return 3;
1130 case 2048: return 4;
1131 case 4096: return 5;
1132 default:
1133 pr_warn("invalid mtu\n");
1134 return -1;
e126ba97 1135 }
1b5daf11 1136}
e126ba97 1137
1b5daf11
MD		 1138enum ib_max_vl_num {
1139 __IB_MAX_VL_0 = 1,
1140 __IB_MAX_VL_0_1 = 2,
1141 __IB_MAX_VL_0_3 = 3,
1142 __IB_MAX_VL_0_7 = 4,
1143 __IB_MAX_VL_0_14 = 5,
1144};
e126ba97 1145
1b5daf11
MD		 1146enum mlx5_vl_hw_cap {
1147 MLX5_VL_HW_0 = 1,
1148 MLX5_VL_HW_0_1 = 2,
1149 MLX5_VL_HW_0_2 = 3,
1150 MLX5_VL_HW_0_3 = 4,
1151 MLX5_VL_HW_0_4 = 5,
1152 MLX5_VL_HW_0_5 = 6,
1153 MLX5_VL_HW_0_6 = 7,
1154 MLX5_VL_HW_0_7 = 8,
1155 MLX5_VL_HW_0_14 = 15
1156};
e126ba97 1157
1b5daf11
MD		 1158static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1159 u8 *max_vl_num)
1160{
1161 switch (vl_hw_cap) {
1162 case MLX5_VL_HW_0:
1163 *max_vl_num = __IB_MAX_VL_0;
1164 break;
1165 case MLX5_VL_HW_0_1:
1166 *max_vl_num = __IB_MAX_VL_0_1;
1167 break;
1168 case MLX5_VL_HW_0_3:
1169 *max_vl_num = __IB_MAX_VL_0_3;
1170 break;
1171 case MLX5_VL_HW_0_7:
1172 *max_vl_num = __IB_MAX_VL_0_7;
1173 break;
1174 case MLX5_VL_HW_0_14:
1175 *max_vl_num = __IB_MAX_VL_0_14;
1176 break;
e126ba97 1177
1b5daf11
MD		 1178 default:
1179 return -EINVAL;
e126ba97 1180 }
e126ba97 1181
1b5daf11 1182 return 0;
e126ba97
EC		 1183}
1184
1b5daf11
MD		 1185static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1186 struct ib_port_attr *props)
e126ba97 1187{
1b5daf11
MD		 1188 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1189 struct mlx5_core_dev *mdev = dev->mdev;
1190 struct mlx5_hca_vport_context *rep;
046339ea
SM		 1191 u16 max_mtu;
1192 u16 oper_mtu;
1b5daf11
MD		 1193 int err;
1194 u8 ib_link_width_oper;
1195 u8 vl_hw_cap;
e126ba97 1196
1b5daf11
MD		 1197 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1198 if (!rep) {
1199 err = -ENOMEM;
e126ba97 1200 goto out;
e126ba97 1201 }
e126ba97 1202
c4550c63 1203 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 1204
1b5daf11 1205 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 1206 if (err)
1207 goto out;
1208
1b5daf11
MD		 1209 props->lid = rep->lid;
1210 props->lmc = rep->lmc;
1211 props->sm_lid = rep->sm_lid;
1212 props->sm_sl = rep->sm_sl;
1213 props->state = rep->vport_state;
1214 props->phys_state = rep->port_physical_state;
1215 props->port_cap_flags = rep->cap_mask1;
1216 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1217 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1218 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1219 props->bad_pkey_cntr = rep->pkey_violation_counter;
1220 props->qkey_viol_cntr = rep->qkey_violation_counter;
1221 props->subnet_timeout = rep->subnet_timeout;
1222 props->init_type_reply = rep->init_type_reply;
e126ba97 1223
1b5daf11
MD		 1224 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1225 if (err)
e126ba97 1226 goto out;
e126ba97 1227
1b5daf11
MD		 1228 err = translate_active_width(ibdev, ib_link_width_oper,
1229 &props->active_width);
1230 if (err)
1231 goto out;
d5beb7f2 1232 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 1233 if (err)
1234 goto out;
1235
facc9699 1236 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 1237
1b5daf11 1238 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 1239
facc9699 1240 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 1241
1b5daf11 1242 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1243
1b5daf11
MD		 1244 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1245 if (err)
1246 goto out;
e126ba97 1247
1b5daf11
MD		 1248 err = translate_max_vl_num(ibdev, vl_hw_cap,
1249 &props->max_vl_num);
e126ba97 1250out:
1b5daf11 1251 kfree(rep);
e126ba97
EC		 1252 return err;
1253}
1254
1b5daf11
MD		 1255int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1256 struct ib_port_attr *props)
e126ba97 1257{
095b0927
IT		 1258 unsigned int count;
1259 int ret;
1260
1b5daf11
MD		 1261 switch (mlx5_get_vport_access_method(ibdev)) {
1262 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1263 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1264 break;
e126ba97 1265
1b5daf11 1266 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1267 ret = mlx5_query_hca_port(ibdev, port, props);
1268 break;
e126ba97 1269
3f89a643 1270 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1271 ret = mlx5_query_port_roce(ibdev, port, props);
1272 break;
3f89a643 1273
1b5daf11 1274 default:
095b0927
IT		 1275 ret = -EINVAL;
1276 }
1277
1278 if (!ret && props) {
b3cbd6f0
DJ		 1279 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1280 struct mlx5_core_dev *mdev;
1281 bool put_mdev = true;
1282
1283 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1284 if (!mdev) {
1285 /* If the port isn't affiliated yet query the master.
1286 * The master and slave will have the same values.
1287 */
1288 mdev = dev->mdev;
1289 port = 1;
1290 put_mdev = false;
1291 }
1292 count = mlx5_core_reserved_gids_count(mdev);
1293 if (put_mdev)
1294 mlx5_ib_put_native_port_mdev(dev, port);
095b0927 1295 props->gid_tbl_len -= count;
1b5daf11 1296 }
095b0927 1297 return ret;
1b5daf11 1298}
e126ba97 1299
8e6efa3a
MB		 1300static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1301 struct ib_port_attr *props)
1302{
1303 int ret;
1304
1305 /* Only link layer == ethernet is valid for representors */
1306 ret = mlx5_query_port_roce(ibdev, port, props);
1307 if (ret || !props)
1308 return ret;
1309
1310 /* We don't support GIDS */
1311 props->gid_tbl_len = 0;
1312
1313 return ret;
1314}
1315
1b5daf11
MD		 1316static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1317 union ib_gid *gid)
1318{
1319 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1320 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1321
1b5daf11
MD		 1322 switch (mlx5_get_vport_access_method(ibdev)) {
1323 case MLX5_VPORT_ACCESS_METHOD_MAD:
1324 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1325
1b5daf11
MD		 1326 case MLX5_VPORT_ACCESS_METHOD_HCA:
1327 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1328
1329 default:
1330 return -EINVAL;
1331 }
e126ba97 1332
e126ba97
EC		 1333}
1334
b3cbd6f0
DJ		 1335static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1336 u16 index, u16 *pkey)
1b5daf11
MD		 1337{
1338 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b3cbd6f0
DJ		 1339 struct mlx5_core_dev *mdev;
1340 bool put_mdev = true;
1341 u8 mdev_port_num;
1342 int err;
1b5daf11 1343
b3cbd6f0
DJ		 1344 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1345 if (!mdev) {
1346 /* The port isn't affiliated yet, get the PKey from the master
1347 * port. For RoCE the PKey tables will be the same.
1348 */
1349 put_mdev = false;
1350 mdev = dev->mdev;
1351 mdev_port_num = 1;
1352 }
1353
1354 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1355 index, pkey);
1356 if (put_mdev)
1357 mlx5_ib_put_native_port_mdev(dev, port);
1358
1359 return err;
1360}
1361
1362static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1363 u16 *pkey)
1364{
1b5daf11
MD		 1365 switch (mlx5_get_vport_access_method(ibdev)) {
1366 case MLX5_VPORT_ACCESS_METHOD_MAD:
1367 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1368
1369 case MLX5_VPORT_ACCESS_METHOD_HCA:
1370 case MLX5_VPORT_ACCESS_METHOD_NIC:
b3cbd6f0 1371 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1b5daf11
MD		 1372 default:
1373 return -EINVAL;
1374 }
1375}
e126ba97
EC		 1376
1377static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1378 struct ib_device_modify *props)
1379{
1380 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1381 struct mlx5_reg_node_desc in;
1382 struct mlx5_reg_node_desc out;
1383 int err;
1384
1385 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1386 return -EOPNOTSUPP;
1387
1388 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1389 return 0;
1390
1391 /*
1392 * If possible, pass node desc to FW, so it can generate
1393 * a 144 trap. If cmd fails, just ignore.
1394 */
bd99fdea 1395 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1396 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1397 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1398 if (err)
1399 return err;
1400
bd99fdea 1401 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1402
1403 return err;
1404}
1405
cdbe33d0
EC		 1406static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1407 u32 value)
1408{
1409 struct mlx5_hca_vport_context ctx = {};
b3cbd6f0
DJ		 1410 struct mlx5_core_dev *mdev;
1411 u8 mdev_port_num;
cdbe33d0
EC		 1412 int err;
1413
b3cbd6f0
DJ		 1414 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1415 if (!mdev)
1416 return -ENODEV;
1417
1418 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
cdbe33d0 1419 if (err)
b3cbd6f0 1420 goto out;
cdbe33d0
EC		 1421
1422 if (~ctx.cap_mask1_perm & mask) {
1423 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1424 mask, ctx.cap_mask1_perm);
b3cbd6f0
DJ		 1425 err = -EINVAL;
1426 goto out;
cdbe33d0
EC		 1427 }
1428
1429 ctx.cap_mask1 = value;
1430 ctx.cap_mask1_perm = mask;
b3cbd6f0
DJ		 1431 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1432 0, &ctx);
1433
1434out:
1435 mlx5_ib_put_native_port_mdev(dev, port_num);
cdbe33d0
EC		 1436
1437 return err;
1438}
1439
e126ba97
EC		 1440static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1441 struct ib_port_modify *props)
1442{
1443 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1444 struct ib_port_attr attr;
1445 u32 tmp;
1446 int err;
cdbe33d0
EC		 1447 u32 change_mask;
1448 u32 value;
1449 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1450 IB_LINK_LAYER_INFINIBAND);
1451
ec255879
MD		 1452 /* CM layer calls ib_modify_port() regardless of the link layer. For
1453 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1454 */
1455 if (!is_ib)
1456 return 0;
1457
cdbe33d0
EC		 1458 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1459 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1460 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1461 return set_port_caps_atomic(dev, port, change_mask, value);
1462 }
e126ba97
EC		 1463
1464 mutex_lock(&dev->cap_mask_mutex);
1465
c4550c63 1466 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1467 if (err)
1468 goto out;
1469
1470 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1471 ~props->clr_port_cap_mask;
1472
9603b61d 1473 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1474
1475out:
1476 mutex_unlock(&dev->cap_mask_mutex);
1477 return err;
1478}
1479
30aa60b3
EC		 1480static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1481{
1482 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1483 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1484}
1485
31a78a5a
YH		 1486static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1487{
1488 /* Large page with non 4k uar support might limit the dynamic size */
1489 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1490 return MLX5_MIN_DYN_BFREGS;
1491
1492 return MLX5_MAX_DYN_BFREGS;
1493}
1494
b037c29a
EC		 1495static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1496 struct mlx5_ib_alloc_ucontext_req_v2 *req,
31a78a5a 1497 struct mlx5_bfreg_info *bfregi)
b037c29a
EC		 1498{
1499 int uars_per_sys_page;
1500 int bfregs_per_sys_page;
1501 int ref_bfregs = req->total_num_bfregs;
1502
1503 if (req->total_num_bfregs == 0)
1504 return -EINVAL;
1505
1506 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1507 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1508
1509 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1510 return -ENOMEM;
1511
1512 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1513 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
31a78a5a 1514 /* This holds the required static allocation asked by the user */
b037c29a 1515 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
b037c29a
EC		 1516 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1517 return -EINVAL;
1518
31a78a5a
YH		 1519 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1520 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1521 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1522 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1523
1524 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
b037c29a
EC		 1525 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1526 lib_uar_4k ? "yes" : "no", ref_bfregs,
31a78a5a
YH		 1527 req->total_num_bfregs, bfregi->total_num_bfregs,
1528 bfregi->num_sys_pages);
b037c29a
EC		 1529
1530 return 0;
1531}
1532
1533static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1534{
1535 struct mlx5_bfreg_info *bfregi;
1536 int err;
1537 int i;
1538
1539 bfregi = &context->bfregi;
31a78a5a 1540 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
b037c29a
EC		 1541 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1542 if (err)
1543 goto error;
1544
1545 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1546 }
4ed131d0
YH		 1547
1548 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1549 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1550
b037c29a
EC		 1551 return 0;
1552
1553error:
1554 for (--i; i >= 0; i--)
1555 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1556 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1557
1558 return err;
1559}
1560
15177999
LR		 1561static void deallocate_uars(struct mlx5_ib_dev *dev,
1562 struct mlx5_ib_ucontext *context)
b037c29a
EC		 1563{
1564 struct mlx5_bfreg_info *bfregi;
b037c29a
EC		 1565 int i;
1566
1567 bfregi = &context->bfregi;
15177999 1568 for (i = 0; i < bfregi->num_sys_pages; i++)
4ed131d0 1569 if (i < bfregi->num_static_sys_pages ||
15177999
LR		 1570 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1571 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
b037c29a
EC		 1572}
1573
0042f9e4 1574int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
a560f1d9
MB		 1575{
1576 int err = 0;
1577
1578 mutex_lock(&dev->lb.mutex);
0042f9e4
MB		 1579 if (td)
1580 dev->lb.user_td++;
1581 if (qp)
1582 dev->lb.qps++;
1583
1584 if (dev->lb.user_td == 2 ||
1585 dev->lb.qps == 1) {
1586 if (!dev->lb.enabled) {
1587 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1588 dev->lb.enabled = true;
1589 }
1590 }
a560f1d9
MB		 1591
1592 mutex_unlock(&dev->lb.mutex);
1593
1594 return err;
1595}
1596
0042f9e4 1597void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
a560f1d9
MB		 1598{
1599 mutex_lock(&dev->lb.mutex);
0042f9e4
MB		 1600 if (td)
1601 dev->lb.user_td--;
1602 if (qp)
1603 dev->lb.qps--;
1604
1605 if (dev->lb.user_td == 1 &&
1606 dev->lb.qps == 0) {
1607 if (dev->lb.enabled) {
1608 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1609 dev->lb.enabled = false;
1610 }
1611 }
a560f1d9
MB		 1612
1613 mutex_unlock(&dev->lb.mutex);
1614}
1615
c85023e1
HN		 1616static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1617{
1618 int err;
1619
cfdeb893
LR		 1620 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1621 return 0;
1622
c85023e1
HN		 1623 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1624 if (err)
1625 return err;
1626
1627 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1628 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1629 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1630 return err;
1631
0042f9e4 1632 return mlx5_ib_enable_lb(dev, true, false);
c85023e1
HN		 1633}
1634
1635static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1636{
cfdeb893
LR		 1637 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1638 return;
1639
c85023e1
HN		 1640 mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1641
1642 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1643 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1644 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1645 return;
1646
0042f9e4 1647 mlx5_ib_disable_lb(dev, true, false);
c85023e1
HN		 1648}
1649
e126ba97
EC		 1650static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1651 struct ib_udata *udata)
1652{
1653 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1654 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1655 struct mlx5_ib_alloc_ucontext_resp resp = {};
5c99eaec 1656 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1657 struct mlx5_ib_ucontext *context;
2f5ff264 1658 struct mlx5_bfreg_info *bfregi;
78c0f98c 1659 int ver;
e126ba97 1660 int err;
a168a41c
MD		 1661 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1662 max_cqe_version);
25bb36e7 1663 u32 dump_fill_mkey;
b037c29a 1664 bool lib_uar_4k;
e126ba97
EC		 1665
1666 if (!dev->ib_active)
1667 return ERR_PTR(-EAGAIN);
1668
e093111d 1669 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1670 ver = 0;
e093111d 1671 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1672 ver = 2;
1673 else
1674 return ERR_PTR(-EINVAL);
1675
e093111d 1676 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97
EC		 1677 if (err)
1678 return ERR_PTR(err);
1679
a8b92ca1
YH		 1680 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1681 return ERR_PTR(-EOPNOTSUPP);
78c0f98c 1682
f72300c5 1683 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 1684 return ERR_PTR(-EOPNOTSUPP);
1685
2f5ff264
EC		 1686 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1687 MLX5_NON_FP_BFREGS_PER_UAR);
1688 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
e126ba97
EC		 1689 return ERR_PTR(-EINVAL);
1690
938fe83c 1691 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1692 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1693 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1694 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1695 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1696 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1697 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1698 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1699 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1700 resp.cqe_version = min_t(__u8,
1701 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1702 req.max_cqe_version);
30aa60b3
EC		 1703 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1704 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1705 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1706 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1707 resp.response_length = min(offsetof(typeof(resp), response_length) +
1708 sizeof(resp.response_length), udata->outlen);
e126ba97 1709
c03faa56
MB		 1710 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1711 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1712 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1713 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1714 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1715 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1716 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1717 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1718 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1719 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1720 }
1721
e126ba97
EC		 1722 context = kzalloc(sizeof(*context), GFP_KERNEL);
1723 if (!context)
1724 return ERR_PTR(-ENOMEM);
1725
30aa60b3 1726 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1727 bfregi = &context->bfregi;
b037c29a
EC		 1728
1729 /* updates req->total_num_bfregs */
31a78a5a 1730 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
b037c29a 1731 if (err)
e126ba97 1732 goto out_ctx;
e126ba97 1733
b037c29a
EC		 1734 mutex_init(&bfregi->lock);
1735 bfregi->lib_uar_4k = lib_uar_4k;
31a78a5a 1736 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1737 GFP_KERNEL);
b037c29a 1738 if (!bfregi->count) {
e126ba97 1739 err = -ENOMEM;
b037c29a 1740 goto out_ctx;
e126ba97
EC		 1741 }
1742
b037c29a
EC		 1743 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1744 sizeof(*bfregi->sys_pages),
1745 GFP_KERNEL);
1746 if (!bfregi->sys_pages) {
e126ba97 1747 err = -ENOMEM;
b037c29a 1748 goto out_count;
e126ba97
EC		 1749 }
1750
b037c29a
EC		 1751 err = allocate_uars(dev, context);
1752 if (err)
1753 goto out_sys_pages;
e126ba97 1754
b4cfe447
HE		 1755#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1756 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1757#endif
1758
cfdeb893
LR		 1759 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
1760 if (err)
1761 goto out_uars;
146d2f1a 1762
a8b92ca1
YH		 1763 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1764 /* Block DEVX on Infiniband as of SELinux */
1765 if (mlx5_ib_port_link_layer(ibdev, 1) != IB_LINK_LAYER_ETHERNET) {
1766 err = -EPERM;
1767 goto out_td;
1768 }
1769
1770 err = mlx5_ib_devx_create(dev, context);
1771 if (err)
1772 goto out_td;
1773 }
1774
25bb36e7
YC		 1775 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1776 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1777 if (err)
8193abb6 1778 goto out_mdev;
25bb36e7
YC		 1779 }
1780
e126ba97
EC		 1781 INIT_LIST_HEAD(&context->db_page_list);
1782 mutex_init(&context->db_page_mutex);
1783
2f5ff264 1784 resp.tot_bfregs = req.total_num_bfregs;
508562d6 1785 resp.num_ports = dev->num_ports;
b368d7cb 1786
f72300c5
HA		 1787 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1788 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1789
402ca536 1790 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1791 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1792 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1793 resp.response_length += sizeof(resp.cmds_supp_uhw);
1794 }
1795
78984898
OG		 1796 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1797 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1798 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1799 resp.eth_min_inline++;
1800 }
1801 resp.response_length += sizeof(resp.eth_min_inline);
1802 }
1803
5c99eaec
FD		 1804 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1805 if (mdev->clock_info)
1806 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1807 resp.response_length += sizeof(resp.clock_info_versions);
1808 }
1809
bc5c6eed
NO		 1810 /*
1811 * We don't want to expose information from the PCI bar that is located
1812 * after 4096 bytes, so if the arch only supports larger pages, let's
1813 * pretend we don't support reading the HCA's core clock. This is also
1814 * forced by mmap function.
1815 */
de8d6e02
EC		 1816 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1817 if (PAGE_SIZE <= 4096) {
1818 resp.comp_mask |=
1819 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1820 resp.hca_core_clock_offset =
1821 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1822 }
5c99eaec 1823 resp.response_length += sizeof(resp.hca_core_clock_offset);
b368d7cb
MB		 1824 }
1825
30aa60b3
EC		 1826 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1827 resp.response_length += sizeof(resp.log_uar_size);
1828
1829 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1830 resp.response_length += sizeof(resp.num_uars_per_page);
1831
31a78a5a
YH		 1832 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1833 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1834 resp.response_length += sizeof(resp.num_dyn_bfregs);
1835 }
1836
25bb36e7
YC		 1837 if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) {
1838 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1839 resp.dump_fill_mkey = dump_fill_mkey;
1840 resp.comp_mask |=
1841 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1842 }
1843 resp.response_length += sizeof(resp.dump_fill_mkey);
1844 }
1845
b368d7cb 1846 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1847 if (err)
a8b92ca1 1848 goto out_mdev;
e126ba97 1849
2f5ff264
EC		 1850 bfregi->ver = ver;
1851 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1852 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1853 context->lib_caps = req.lib_caps;
1854 print_lib_caps(dev, context->lib_caps);
f72300c5 1855
c6a21c38
MD		 1856 if (mlx5_lag_is_active(dev->mdev)) {
1857 u8 port = mlx5_core_native_port_num(dev->mdev);
1858
1859 atomic_set(&context->tx_port_affinity,
1860 atomic_add_return(
1861 1, &dev->roce[port].tx_port_affinity));
1862 }
1863
e126ba97
EC		 1864 return &context->ibucontext;
1865
a8b92ca1
YH		 1866out_mdev:
1867 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1868 mlx5_ib_devx_destroy(dev, context);
146d2f1a 1869out_td:
cfdeb893 1870 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1871
e126ba97 1872out_uars:
b037c29a 1873 deallocate_uars(dev, context);
e126ba97 1874
b037c29a
EC		 1875out_sys_pages:
1876 kfree(bfregi->sys_pages);
e126ba97 1877
b037c29a
EC		 1878out_count:
1879 kfree(bfregi->count);
e126ba97
EC		 1880
1881out_ctx:
1882 kfree(context);
b037c29a 1883
e126ba97
EC		 1884 return ERR_PTR(err);
1885}
1886
1887static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1888{
1889 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1890 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 1891 struct mlx5_bfreg_info *bfregi;
e126ba97 1892
f27a0d50
JG		 1893#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1894 /* All umem's must be destroyed before destroying the ucontext. */
1895 mutex_lock(&ibcontext->per_mm_list_lock);
1896 WARN_ON(!list_empty(&ibcontext->per_mm_list));
1897 mutex_unlock(&ibcontext->per_mm_list_lock);
1898#endif
1899
a8b92ca1
YH		 1900 if (context->devx_uid)
1901 mlx5_ib_devx_destroy(dev, context);
1902
b037c29a 1903 bfregi = &context->bfregi;
cfdeb893 1904 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1905
b037c29a
EC		 1906 deallocate_uars(dev, context);
1907 kfree(bfregi->sys_pages);
2f5ff264 1908 kfree(bfregi->count);
e126ba97
EC		 1909 kfree(context);
1910
1911 return 0;
1912}
1913
b037c29a 1914static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
4ed131d0 1915 int uar_idx)
e126ba97 1916{
b037c29a
EC		 1917 int fw_uars_per_page;
1918
1919 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1920
4ed131d0 1921 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
e126ba97
EC		 1922}
1923
1924static int get_command(unsigned long offset)
1925{
1926 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1927}
1928
1929static int get_arg(unsigned long offset)
1930{
1931 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1932}
1933
1934static int get_index(unsigned long offset)
1935{
1936 return get_arg(offset);
1937}
1938
4ed131d0
YH		 1939/* Index resides in an extra byte to enable larger values than 255 */
1940static int get_extended_index(unsigned long offset)
1941{
1942 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1943}
1944
7c2344c3
MG		 1945
1946static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1947{
7c2344c3
MG		 1948}
1949
37aa5c36
GL		 1950static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1951{
1952 switch (cmd) {
1953 case MLX5_IB_MMAP_WC_PAGE:
1954 return "WC";
1955 case MLX5_IB_MMAP_REGULAR_PAGE:
1956 return "best effort WC";
1957 case MLX5_IB_MMAP_NC_PAGE:
1958 return "NC";
24da0016
AL		 1959 case MLX5_IB_MMAP_DEVICE_MEM:
1960 return "Device Memory";
37aa5c36
GL		 1961 default:
1962 return NULL;
1963 }
1964}
1965
5c99eaec
FD		 1966static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
1967 struct vm_area_struct *vma,
1968 struct mlx5_ib_ucontext *context)
1969{
5c99eaec
FD		 1970 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1971 return -EINVAL;
1972
1973 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
1974 return -EOPNOTSUPP;
1975
1976 if (vma->vm_flags & VM_WRITE)
1977 return -EPERM;
1978
1979 if (!dev->mdev->clock_info_page)
1980 return -EOPNOTSUPP;
1981
e2cd1d1a
JG		 1982 return rdma_user_mmap_page(&context->ibucontext, vma,
1983 dev->mdev->clock_info_page, PAGE_SIZE);
5c99eaec
FD		 1984}
1985
37aa5c36 1986static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 1987 struct vm_area_struct *vma,
1988 struct mlx5_ib_ucontext *context)
37aa5c36 1989{
2f5ff264 1990 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 1991 int err;
1992 unsigned long idx;
aa09ea6e 1993 phys_addr_t pfn;
37aa5c36 1994 pgprot_t prot;
4ed131d0
YH		 1995 u32 bfreg_dyn_idx = 0;
1996 u32 uar_index;
1997 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
1998 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
1999 bfregi->num_static_sys_pages;
b037c29a
EC		 2000
2001 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2002 return -EINVAL;
2003
4ed131d0
YH		 2004 if (dyn_uar)
2005 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2006 else
2007 idx = get_index(vma->vm_pgoff);
2008
2009 if (idx >= max_valid_idx) {
2010 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2011 idx, max_valid_idx);
b037c29a
EC		 2012 return -EINVAL;
2013 }
37aa5c36
GL		 2014
2015 switch (cmd) {
2016 case MLX5_IB_MMAP_WC_PAGE:
4ed131d0 2017 case MLX5_IB_MMAP_ALLOC_WC:
37aa5c36
GL		 2018/* Some architectures don't support WC memory */
2019#if defined(CONFIG_X86)
2020 if (!pat_enabled())
2021 return -EPERM;
2022#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2023 return -EPERM;
2024#endif
2025 /* fall through */
2026 case MLX5_IB_MMAP_REGULAR_PAGE:
2027 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2028 prot = pgprot_writecombine(vma->vm_page_prot);
2029 break;
2030 case MLX5_IB_MMAP_NC_PAGE:
2031 prot = pgprot_noncached(vma->vm_page_prot);
2032 break;
2033 default:
2034 return -EINVAL;
2035 }
2036
4ed131d0
YH		 2037 if (dyn_uar) {
2038 int uars_per_page;
2039
2040 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2041 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2042 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2043 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2044 bfreg_dyn_idx, bfregi->total_num_bfregs);
2045 return -EINVAL;
2046 }
2047
2048 mutex_lock(&bfregi->lock);
2049 /* Fail if uar already allocated, first bfreg index of each
2050 * page holds its count.
2051 */
2052 if (bfregi->count[bfreg_dyn_idx]) {
2053 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2054 mutex_unlock(&bfregi->lock);
2055 return -EINVAL;
2056 }
2057
2058 bfregi->count[bfreg_dyn_idx]++;
2059 mutex_unlock(&bfregi->lock);
2060
2061 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2062 if (err) {
2063 mlx5_ib_warn(dev, "UAR alloc failed\n");
2064 goto free_bfreg;
2065 }
2066 } else {
2067 uar_index = bfregi->sys_pages[idx];
2068 }
2069
2070 pfn = uar_index2pfn(dev, uar_index);
37aa5c36
GL		 2071 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2072
e2cd1d1a
JG		 2073 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2074 prot);
37aa5c36 2075 if (err) {
8f062287 2076 mlx5_ib_err(dev,
e2cd1d1a 2077 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
8f062287 2078 err, mmap_cmd2str(cmd));
4ed131d0 2079 goto err;
37aa5c36
GL		 2080 }
2081
4ed131d0
YH		 2082 if (dyn_uar)
2083 bfregi->sys_pages[idx] = uar_index;
2084 return 0;
2085
2086err:
2087 if (!dyn_uar)
2088 return err;
2089
2090 mlx5_cmd_free_uar(dev->mdev, idx);
2091
2092free_bfreg:
2093 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2094
2095 return err;
37aa5c36
GL		 2096}
2097
24da0016
AL		 2098static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2099{
2100 struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2101 struct mlx5_ib_dev *dev = to_mdev(context->device);
2102 u16 page_idx = get_extended_index(vma->vm_pgoff);
2103 size_t map_size = vma->vm_end - vma->vm_start;
2104 u32 npages = map_size >> PAGE_SHIFT;
2105 phys_addr_t pfn;
24da0016
AL		 2106
2107 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2108 page_idx + npages)
2109 return -EINVAL;
2110
2111 pfn = ((pci_resource_start(dev->mdev->pdev, 0) +
2112 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2113 PAGE_SHIFT) +
2114 page_idx;
e2cd1d1a
JG		 2115 return rdma_user_mmap_io(context, vma, pfn, map_size,
2116 pgprot_writecombine(vma->vm_page_prot));
24da0016
AL		 2117}
2118
e126ba97
EC		 2119static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2120{
2121 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2122 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 2123 unsigned long command;
e126ba97
EC		 2124 phys_addr_t pfn;
2125
2126 command = get_command(vma->vm_pgoff);
2127 switch (command) {
37aa5c36
GL		 2128 case MLX5_IB_MMAP_WC_PAGE:
2129 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 2130 case MLX5_IB_MMAP_REGULAR_PAGE:
4ed131d0 2131 case MLX5_IB_MMAP_ALLOC_WC:
7c2344c3 2132 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 2133
2134 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2135 return -ENOSYS;
2136
d69e3bcf 2137 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 2138 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2139 return -EINVAL;
2140
6cbac1e4 2141 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 2142 return -EPERM;
2143
2144 /* Don't expose to user-space information it shouldn't have */
2145 if (PAGE_SIZE > 4096)
2146 return -EOPNOTSUPP;
2147
2148 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2149 pfn = (dev->mdev->iseg_base +
2150 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2151 PAGE_SHIFT;
2152 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2153 PAGE_SIZE, vma->vm_page_prot))
2154 return -EAGAIN;
d69e3bcf 2155 break;
5c99eaec
FD		 2156 case MLX5_IB_MMAP_CLOCK_INFO:
2157 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
d69e3bcf 2158
24da0016
AL		 2159 case MLX5_IB_MMAP_DEVICE_MEM:
2160 return dm_mmap(ibcontext, vma);
2161
e126ba97
EC		 2162 default:
2163 return -EINVAL;
2164 }
2165
2166 return 0;
2167}
2168
24da0016
AL		 2169struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2170 struct ib_ucontext *context,
2171 struct ib_dm_alloc_attr *attr,
2172 struct uverbs_attr_bundle *attrs)
2173{
2174 u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2175 struct mlx5_memic *memic = &to_mdev(ibdev)->memic;
2176 phys_addr_t memic_addr;
2177 struct mlx5_ib_dm *dm;
2178 u64 start_offset;
2179 u32 page_idx;
2180 int err;
2181
2182 dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2183 if (!dm)
2184 return ERR_PTR(-ENOMEM);
2185
2186 mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n",
2187 attr->length, act_size, attr->alignment);
2188
2189 err = mlx5_cmd_alloc_memic(memic, &memic_addr,
2190 act_size, attr->alignment);
2191 if (err)
2192 goto err_free;
2193
2194 start_offset = memic_addr & ~PAGE_MASK;
2195 page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) -
2196 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2197 PAGE_SHIFT;
2198
2199 err = uverbs_copy_to(attrs,
2200 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2201 &start_offset, sizeof(start_offset));
2202 if (err)
2203 goto err_dealloc;
2204
2205 err = uverbs_copy_to(attrs,
2206 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2207 &page_idx, sizeof(page_idx));
2208 if (err)
2209 goto err_dealloc;
2210
2211 bitmap_set(to_mucontext(context)->dm_pages, page_idx,
2212 DIV_ROUND_UP(act_size, PAGE_SIZE));
2213
2214 dm->dev_addr = memic_addr;
2215
2216 return &dm->ibdm;
2217
2218err_dealloc:
2219 mlx5_cmd_dealloc_memic(memic, memic_addr,
2220 act_size);
2221err_free:
2222 kfree(dm);
2223 return ERR_PTR(err);
2224}
2225
2226int mlx5_ib_dealloc_dm(struct ib_dm *ibdm)
2227{
2228 struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic;
2229 struct mlx5_ib_dm *dm = to_mdm(ibdm);
2230 u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE);
2231 u32 page_idx;
2232 int ret;
2233
2234 ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size);
2235 if (ret)
2236 return ret;
2237
2238 page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) -
2239 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2240 PAGE_SHIFT;
2241 bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages,
2242 page_idx,
2243 DIV_ROUND_UP(act_size, PAGE_SIZE));
2244
2245 kfree(dm);
2246
2247 return 0;
2248}
2249
e126ba97
EC		 2250static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2251 struct ib_ucontext *context,
2252 struct ib_udata *udata)
2253{
2254 struct mlx5_ib_alloc_pd_resp resp;
2255 struct mlx5_ib_pd *pd;
2256 int err;
a1069c1c
YH		 2257 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2258 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
2259 u16 uid = 0;
e126ba97
EC		 2260
2261 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
2262 if (!pd)
2263 return ERR_PTR(-ENOMEM);
2264
a1069c1c
YH		 2265 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2266 MLX5_SET(alloc_pd_in, in, uid, uid);
2267 err = mlx5_cmd_exec(to_mdev(ibdev)->mdev, in, sizeof(in),
2268 out, sizeof(out));
e126ba97
EC		 2269 if (err) {
2270 kfree(pd);
2271 return ERR_PTR(err);
2272 }
2273
a1069c1c
YH		 2274 pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2275 pd->uid = uid;
e126ba97
EC		 2276 if (context) {
2277 resp.pdn = pd->pdn;
2278 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
a1069c1c 2279 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
e126ba97
EC		 2280 kfree(pd);
2281 return ERR_PTR(-EFAULT);
2282 }
e126ba97
EC		 2283 }
2284
2285 return &pd->ibpd;
2286}
2287
2288static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2289{
2290 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2291 struct mlx5_ib_pd *mpd = to_mpd(pd);
2292
a1069c1c 2293 mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
e126ba97
EC		 2294 kfree(mpd);
2295
2296 return 0;
2297}
2298
466fa6d2
MG		 2299enum {
2300 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2301 MATCH_CRITERIA_ENABLE_MISC_BIT,
71c6e863
AL		 2302 MATCH_CRITERIA_ENABLE_INNER_BIT,
2303 MATCH_CRITERIA_ENABLE_MISC2_BIT
466fa6d2
MG		 2304};
2305
2306#define HEADER_IS_ZERO(match_criteria, headers) \
2307 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2308 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 2309
466fa6d2 2310static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 2311{
466fa6d2 2312 u8 match_criteria_enable;
038d2ef8 2313
466fa6d2
MG		 2314 match_criteria_enable =
2315 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2316 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2317 match_criteria_enable |=
2318 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2319 MATCH_CRITERIA_ENABLE_MISC_BIT;
2320 match_criteria_enable |=
2321 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2322 MATCH_CRITERIA_ENABLE_INNER_BIT;
71c6e863
AL		 2323 match_criteria_enable |=
2324 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2325 MATCH_CRITERIA_ENABLE_MISC2_BIT;
466fa6d2
MG		 2326
2327 return match_criteria_enable;
038d2ef8
MG		 2328}
2329
ca0d4753
MG		 2330static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2331{
2332 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2333 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
038d2ef8
MG		 2334}
2335
37da2a03 2336static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2d1e697e
MR		 2337 bool inner)
2338{
2339 if (inner) {
2340 MLX5_SET(fte_match_set_misc,
2341 misc_c, inner_ipv6_flow_label, mask);
2342 MLX5_SET(fte_match_set_misc,
2343 misc_v, inner_ipv6_flow_label, val);
2344 } else {
2345 MLX5_SET(fte_match_set_misc,
2346 misc_c, outer_ipv6_flow_label, mask);
2347 MLX5_SET(fte_match_set_misc,
2348 misc_v, outer_ipv6_flow_label, val);
2349 }
2350}
2351
ca0d4753
MG		 2352static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2353{
2354 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2355 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2356 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2357 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2358}
2359
71c6e863
AL		 2360static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2361{
2362 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2363 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2364 return -EOPNOTSUPP;
2365
2366 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2367 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2368 return -EOPNOTSUPP;
2369
2370 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2371 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2372 return -EOPNOTSUPP;
2373
2374 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2375 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2376 return -EOPNOTSUPP;
2377
2378 return 0;
2379}
2380
c47ac6ae
MG		 2381#define LAST_ETH_FIELD vlan_tag
2382#define LAST_IB_FIELD sl
ca0d4753 2383#define LAST_IPV4_FIELD tos
466fa6d2 2384#define LAST_IPV6_FIELD traffic_class
c47ac6ae 2385#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 2386#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 2387#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 2388#define LAST_DROP_FIELD size
3b3233fb 2389#define LAST_COUNTERS_FIELD counters
c47ac6ae
MG		 2390
2391/* Field is the last supported field */
2392#define FIELDS_NOT_SUPPORTED(filter, field)\
2393 memchr_inv((void *)&filter.field +\
2394 sizeof(filter.field), 0,\
2395 sizeof(filter) -\
2396 offsetof(typeof(filter), field) -\
2397 sizeof(filter.field))
2398
2ea26203
MB		 2399int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
2400 bool is_egress,
2401 struct mlx5_flow_act *action)
802c2125 2402{
802c2125
AY		 2403
2404 switch (maction->ib_action.type) {
2405 case IB_FLOW_ACTION_ESP:
501f14e3
MB		 2406 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2407 MLX5_FLOW_CONTEXT_ACTION_DECRYPT))
2408 return -EINVAL;
802c2125
AY		 2409 /* Currently only AES_GCM keymat is supported by the driver */
2410 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2ea26203 2411 action->action |= is_egress ?
802c2125
AY		 2412 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2413 MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2414 return 0;
b1085be3
MB		 2415 case IB_FLOW_ACTION_UNSPECIFIED:
2416 if (maction->flow_action_raw.sub_type ==
2417 MLX5_IB_FLOW_ACTION_MODIFY_HEADER) {
501f14e3
MB		 2418 if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2419 return -EINVAL;
b1085be3
MB		 2420 action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2421 action->modify_id = maction->flow_action_raw.action_id;
2422 return 0;
2423 }
10a30896
MB		 2424 if (maction->flow_action_raw.sub_type ==
2425 MLX5_IB_FLOW_ACTION_DECAP) {
501f14e3
MB		 2426 if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP)
2427 return -EINVAL;
10a30896
MB		 2428 action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2429 return 0;
2430 }
e806f932
MB		 2431 if (maction->flow_action_raw.sub_type ==
2432 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) {
501f14e3
MB		 2433 if (action->action &
2434 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT)
2435 return -EINVAL;
e806f932
MB		 2436 action->action |=
2437 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
2438 action->reformat_id =
2439 maction->flow_action_raw.action_id;
2440 return 0;
2441 }
b1085be3 2442 /* fall through */
802c2125
AY		 2443 default:
2444 return -EOPNOTSUPP;
2445 }
2446}
2447
19cc7524
AL		 2448static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2449 u32 *match_v, const union ib_flow_spec *ib_spec,
802c2125 2450 const struct ib_flow_attr *flow_attr,
71c6e863 2451 struct mlx5_flow_act *action, u32 prev_type)
038d2ef8 2452{
466fa6d2
MG		 2453 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2454 misc_parameters);
2455 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2456 misc_parameters);
71c6e863
AL		 2457 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2458 misc_parameters_2);
2459 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2460 misc_parameters_2);
2d1e697e
MR		 2461 void *headers_c;
2462 void *headers_v;
19cc7524 2463 int match_ipv;
802c2125 2464 int ret;
2d1e697e
MR		 2465
2466 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2467 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2468 inner_headers);
2469 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2470 inner_headers);
19cc7524
AL		 2471 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2472 ft_field_support.inner_ip_version);
2d1e697e
MR		 2473 } else {
2474 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2475 outer_headers);
2476 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2477 outer_headers);
19cc7524
AL		 2478 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2479 ft_field_support.outer_ip_version);
2d1e697e 2480 }
466fa6d2 2481
2d1e697e 2482 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 2483 case IB_FLOW_SPEC_ETH:
c47ac6ae 2484 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 2485 return -EOPNOTSUPP;
038d2ef8 2486
2d1e697e 2487 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2488 dmac_47_16),
2489 ib_spec->eth.mask.dst_mac);
2d1e697e 2490 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2491 dmac_47_16),
2492 ib_spec->eth.val.dst_mac);
2493
2d1e697e 2494 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 2495 smac_47_16),
2496 ib_spec->eth.mask.src_mac);
2d1e697e 2497 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 2498 smac_47_16),
2499 ib_spec->eth.val.src_mac);
2500
038d2ef8 2501 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 2502 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 2503 cvlan_tag, 1);
2d1e697e 2504 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 2505 cvlan_tag, 1);
038d2ef8 2506
2d1e697e 2507 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2508 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 2509 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2510 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2511
2d1e697e 2512 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2513 first_cfi,
2514 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 2515 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2516 first_cfi,
2517 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2518
2d1e697e 2519 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2520 first_prio,
2521 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 2522 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2523 first_prio,
2524 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2525 }
2d1e697e 2526 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2527 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 2528 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2529 ethertype, ntohs(ib_spec->eth.val.ether_type));
2530 break;
2531 case IB_FLOW_SPEC_IPV4:
c47ac6ae 2532 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 2533 return -EOPNOTSUPP;
038d2ef8 2534
19cc7524
AL		 2535 if (match_ipv) {
2536 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2537 ip_version, 0xf);
2538 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2539 ip_version, MLX5_FS_IPV4_VERSION);
19cc7524
AL		 2540 } else {
2541 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2542 ethertype, 0xffff);
2543 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2544 ethertype, ETH_P_IP);
2545 }
038d2ef8 2546
2d1e697e 2547 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2548 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2549 &ib_spec->ipv4.mask.src_ip,
2550 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 2551 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2552 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2553 &ib_spec->ipv4.val.src_ip,
2554 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 2555 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2556 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2557 &ib_spec->ipv4.mask.dst_ip,
2558 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 2559 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2560 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2561 &ib_spec->ipv4.val.dst_ip,
2562 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 2563
2d1e697e 2564 set_tos(headers_c, headers_v,
ca0d4753
MG		 2565 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2566
2d1e697e 2567 set_proto(headers_c, headers_v,
ca0d4753 2568 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
038d2ef8 2569 break;
026bae0c 2570 case IB_FLOW_SPEC_IPV6:
c47ac6ae 2571 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 2572 return -EOPNOTSUPP;
026bae0c 2573
19cc7524
AL		 2574 if (match_ipv) {
2575 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2576 ip_version, 0xf);
2577 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2578 ip_version, MLX5_FS_IPV6_VERSION);
19cc7524
AL		 2579 } else {
2580 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2581 ethertype, 0xffff);
2582 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2583 ethertype, ETH_P_IPV6);
2584 }
026bae0c 2585
2d1e697e 2586 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2587 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2588 &ib_spec->ipv6.mask.src_ip,
2589 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2590 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2591 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2592 &ib_spec->ipv6.val.src_ip,
2593 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2594 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2595 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2596 &ib_spec->ipv6.mask.dst_ip,
2597 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2598 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2599 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2600 &ib_spec->ipv6.val.dst_ip,
2601 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2602
2d1e697e 2603 set_tos(headers_c, headers_v,
466fa6d2
MG		 2604 ib_spec->ipv6.mask.traffic_class,
2605 ib_spec->ipv6.val.traffic_class);
2606
2d1e697e 2607 set_proto(headers_c, headers_v,
466fa6d2
MG		 2608 ib_spec->ipv6.mask.next_hdr,
2609 ib_spec->ipv6.val.next_hdr);
2610
2d1e697e
MR		 2611 set_flow_label(misc_params_c, misc_params_v,
2612 ntohl(ib_spec->ipv6.mask.flow_label),
2613 ntohl(ib_spec->ipv6.val.flow_label),
2614 ib_spec->type & IB_FLOW_SPEC_INNER);
802c2125
AY		 2615 break;
2616 case IB_FLOW_SPEC_ESP:
2617 if (ib_spec->esp.mask.seq)
2618 return -EOPNOTSUPP;
2d1e697e 2619
802c2125
AY		 2620 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2621 ntohl(ib_spec->esp.mask.spi));
2622 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2623 ntohl(ib_spec->esp.val.spi));
026bae0c 2624 break;
038d2ef8 2625 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2626 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2627 LAST_TCP_UDP_FIELD))
1ffd3a26 2628 return -EOPNOTSUPP;
038d2ef8 2629
2d1e697e 2630 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2631 0xff);
2d1e697e 2632 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2633 IPPROTO_TCP);
2634
2d1e697e 2635 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2636 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2637 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2638 ntohs(ib_spec->tcp_udp.val.src_port));
2639
2d1e697e 2640 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2641 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2642 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2643 ntohs(ib_spec->tcp_udp.val.dst_port));
2644 break;
2645 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2646 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2647 LAST_TCP_UDP_FIELD))
1ffd3a26 2648 return -EOPNOTSUPP;
038d2ef8 2649
2d1e697e 2650 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2651 0xff);
2d1e697e 2652 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2653 IPPROTO_UDP);
2654
2d1e697e 2655 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2656 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2657 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2658 ntohs(ib_spec->tcp_udp.val.src_port));
2659
2d1e697e 2660 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2661 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2662 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2663 ntohs(ib_spec->tcp_udp.val.dst_port));
2664 break;
da2f22ae
AL		 2665 case IB_FLOW_SPEC_GRE:
2666 if (ib_spec->gre.mask.c_ks_res0_ver)
2667 return -EOPNOTSUPP;
2668
2669 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2670 0xff);
2671 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2672 IPPROTO_GRE);
2673
2674 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
a93b632c 2675 ntohs(ib_spec->gre.mask.protocol));
da2f22ae
AL		 2676 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2677 ntohs(ib_spec->gre.val.protocol));
2678
2679 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
2680 gre_key_h),
2681 &ib_spec->gre.mask.key,
2682 sizeof(ib_spec->gre.mask.key));
2683 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
2684 gre_key_h),
2685 &ib_spec->gre.val.key,
2686 sizeof(ib_spec->gre.val.key));
2687 break;
71c6e863
AL		 2688 case IB_FLOW_SPEC_MPLS:
2689 switch (prev_type) {
2690 case IB_FLOW_SPEC_UDP:
2691 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2692 ft_field_support.outer_first_mpls_over_udp),
2693 &ib_spec->mpls.mask.tag))
2694 return -EOPNOTSUPP;
2695
2696 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2697 outer_first_mpls_over_udp),
2698 &ib_spec->mpls.val.tag,
2699 sizeof(ib_spec->mpls.val.tag));
2700 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2701 outer_first_mpls_over_udp),
2702 &ib_spec->mpls.mask.tag,
2703 sizeof(ib_spec->mpls.mask.tag));
2704 break;
2705 case IB_FLOW_SPEC_GRE:
2706 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2707 ft_field_support.outer_first_mpls_over_gre),
2708 &ib_spec->mpls.mask.tag))
2709 return -EOPNOTSUPP;
2710
2711 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2712 outer_first_mpls_over_gre),
2713 &ib_spec->mpls.val.tag,
2714 sizeof(ib_spec->mpls.val.tag));
2715 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2716 outer_first_mpls_over_gre),
2717 &ib_spec->mpls.mask.tag,
2718 sizeof(ib_spec->mpls.mask.tag));
2719 break;
2720 default:
2721 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2722 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2723 ft_field_support.inner_first_mpls),
2724 &ib_spec->mpls.mask.tag))
2725 return -EOPNOTSUPP;
2726
2727 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2728 inner_first_mpls),
2729 &ib_spec->mpls.val.tag,
2730 sizeof(ib_spec->mpls.val.tag));
2731 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2732 inner_first_mpls),
2733 &ib_spec->mpls.mask.tag,
2734 sizeof(ib_spec->mpls.mask.tag));
2735 } else {
2736 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2737 ft_field_support.outer_first_mpls),
2738 &ib_spec->mpls.mask.tag))
2739 return -EOPNOTSUPP;
2740
2741 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2742 outer_first_mpls),
2743 &ib_spec->mpls.val.tag,
2744 sizeof(ib_spec->mpls.val.tag));
2745 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2746 outer_first_mpls),
2747 &ib_spec->mpls.mask.tag,
2748 sizeof(ib_spec->mpls.mask.tag));
2749 }
2750 }
2751 break;
ffb30d8f
MR		 2752 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2753 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2754 LAST_TUNNEL_FIELD))
1ffd3a26 2755 return -EOPNOTSUPP;
ffb30d8f
MR		 2756
2757 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2758 ntohl(ib_spec->tunnel.mask.tunnel_id));
2759 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2760 ntohl(ib_spec->tunnel.val.tunnel_id));
2761 break;
2ac693f9
MR		 2762 case IB_FLOW_SPEC_ACTION_TAG:
2763 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2764 LAST_FLOW_TAG_FIELD))
2765 return -EOPNOTSUPP;
2766 if (ib_spec->flow_tag.tag_id >= BIT(24))
2767 return -EINVAL;
2768
075572d4 2769 action->flow_tag = ib_spec->flow_tag.tag_id;
a9db0ecf 2770 action->has_flow_tag = true;
2ac693f9 2771 break;
a22ed86c
SS		 2772 case IB_FLOW_SPEC_ACTION_DROP:
2773 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2774 LAST_DROP_FIELD))
2775 return -EOPNOTSUPP;
075572d4 2776 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
a22ed86c 2777 break;
802c2125 2778 case IB_FLOW_SPEC_ACTION_HANDLE:
2ea26203
MB		 2779 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act),
2780 flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action);
802c2125
AY		 2781 if (ret)
2782 return ret;
2783 break;
3b3233fb
RS		 2784 case IB_FLOW_SPEC_ACTION_COUNT:
2785 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
2786 LAST_COUNTERS_FIELD))
2787 return -EOPNOTSUPP;
2788
2789 /* for now support only one counters spec per flow */
2790 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
2791 return -EINVAL;
2792
2793 action->counters = ib_spec->flow_count.counters;
2794 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2795 break;
038d2ef8
MG		 2796 default:
2797 return -EINVAL;
2798 }
2799
2800 return 0;
2801}
2802
2803/* If a flow could catch both multicast and unicast packets,
2804 * it won't fall into the multicast flow steering table and this rule
2805 * could steal other multicast packets.
2806 */
a550ddfc 2807static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
038d2ef8 2808{
81e30880 2809 union ib_flow_spec *flow_spec;
038d2ef8
MG		 2810
2811 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 2812 ib_attr->num_of_specs < 1)
2813 return false;
2814
81e30880
YH		 2815 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2816 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2817 struct ib_flow_spec_ipv4 *ipv4_spec;
2818
2819 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2820 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2821 return true;
2822
038d2ef8 2823 return false;
81e30880
YH		 2824 }
2825
2826 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2827 struct ib_flow_spec_eth *eth_spec;
2828
2829 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2830 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2831 is_multicast_ether_addr(eth_spec->val.dst_mac);
2832 }
038d2ef8 2833
81e30880 2834 return false;
038d2ef8
MG		 2835}
2836
802c2125
AY		 2837enum valid_spec {
2838 VALID_SPEC_INVALID,
2839 VALID_SPEC_VALID,
2840 VALID_SPEC_NA,
2841};
2842
2843static enum valid_spec
2844is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
2845 const struct mlx5_flow_spec *spec,
2846 const struct mlx5_flow_act *flow_act,
2847 bool egress)
2848{
2849 const u32 *match_c = spec->match_criteria;
2850 bool is_crypto =
2851 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2852 MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
2853 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
2854 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
2855
2856 /*
2857 * Currently only crypto is supported in egress, when regular egress
2858 * rules would be supported, always return VALID_SPEC_NA.
2859 */
2860 if (!is_crypto)
78dd0c43 2861 return VALID_SPEC_NA;
802c2125
AY		 2862
2863 return is_crypto && is_ipsec &&
2864 (!egress || (!is_drop && !flow_act->has_flow_tag)) ?
2865 VALID_SPEC_VALID : VALID_SPEC_INVALID;
2866}
2867
2868static bool is_valid_spec(struct mlx5_core_dev *mdev,
2869 const struct mlx5_flow_spec *spec,
2870 const struct mlx5_flow_act *flow_act,
2871 bool egress)
2872{
2873 /* We curretly only support ipsec egress flow */
2874 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
2875}
2876
19cc7524
AL		 2877static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2878 const struct ib_flow_attr *flow_attr,
0f750966 2879 bool check_inner)
038d2ef8
MG		 2880{
2881 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 2882 int match_ipv = check_inner ?
2883 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2884 ft_field_support.inner_ip_version) :
2885 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2886 ft_field_support.outer_ip_version);
0f750966
AL		 2887 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2888 bool ipv4_spec_valid, ipv6_spec_valid;
2889 unsigned int ip_spec_type = 0;
2890 bool has_ethertype = false;
038d2ef8 2891 unsigned int spec_index;
0f750966
AL		 2892 bool mask_valid = true;
2893 u16 eth_type = 0;
2894 bool type_valid;
038d2ef8
MG		 2895
2896 /* Validate that ethertype is correct */
2897 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 2898 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 2899 ib_spec->eth.mask.ether_type) {
0f750966
AL		 2900 mask_valid = (ib_spec->eth.mask.ether_type ==
2901 htons(0xffff));
2902 has_ethertype = true;
2903 eth_type = ntohs(ib_spec->eth.val.ether_type);
2904 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2905 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2906 ip_spec_type = ib_spec->type;
038d2ef8
MG		 2907 }
2908 ib_spec = (void *)ib_spec + ib_spec->size;
2909 }
0f750966
AL		 2910
2911 type_valid = (!has_ethertype) || (!ip_spec_type);
2912 if (!type_valid && mask_valid) {
2913 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2914 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2915 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2916 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 2917
2918 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2919 (((eth_type == ETH_P_MPLS_UC) ||
2920 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 2921 }
2922
2923 return type_valid;
2924}
2925
19cc7524
AL		 2926static bool is_valid_attr(struct mlx5_core_dev *mdev,
2927 const struct ib_flow_attr *flow_attr)
0f750966 2928{
19cc7524
AL		 2929 return is_valid_ethertype(mdev, flow_attr, false) &&
2930 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 2931}
2932
2933static void put_flow_table(struct mlx5_ib_dev *dev,
2934 struct mlx5_ib_flow_prio *prio, bool ft_added)
2935{
2936 prio->refcount -= !!ft_added;
2937 if (!prio->refcount) {
2938 mlx5_destroy_flow_table(prio->flow_table);
2939 prio->flow_table = NULL;
2940 }
2941}
2942
3b3233fb
RS		 2943static void counters_clear_description(struct ib_counters *counters)
2944{
2945 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
2946
2947 mutex_lock(&mcounters->mcntrs_mutex);
2948 kfree(mcounters->counters_data);
2949 mcounters->counters_data = NULL;
2950 mcounters->cntrs_max_index = 0;
2951 mutex_unlock(&mcounters->mcntrs_mutex);
2952}
2953
038d2ef8
MG		 2954static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2955{
038d2ef8
MG		 2956 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2957 struct mlx5_ib_flow_handler,
2958 ibflow);
2959 struct mlx5_ib_flow_handler *iter, *tmp;
d4be3f44 2960 struct mlx5_ib_dev *dev = handler->dev;
038d2ef8 2961
9a4ca38d 2962 mutex_lock(&dev->flow_db->lock);
038d2ef8
MG		 2963
2964 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 2965 mlx5_del_flow_rules(iter->rule);
cc0e5d42 2966 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 2967 list_del(&iter->list);
2968 kfree(iter);
2969 }
2970
74491de9 2971 mlx5_del_flow_rules(handler->rule);
5497adc6 2972 put_flow_table(dev, handler->prio, true);
3b3233fb
RS		 2973 if (handler->ibcounters &&
2974 atomic_read(&handler->ibcounters->usecnt) == 1)
2975 counters_clear_description(handler->ibcounters);
038d2ef8 2976
3b3233fb 2977 mutex_unlock(&dev->flow_db->lock);
d4be3f44
YH		 2978 if (handler->flow_matcher)
2979 atomic_dec(&handler->flow_matcher->usecnt);
038d2ef8
MG		 2980 kfree(handler);
2981
2982 return 0;
2983}
2984
35d19011
MG		 2985static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2986{
2987 priority *= 2;
2988 if (!dont_trap)
2989 priority++;
2990 return priority;
2991}
2992
cc0e5d42
MG		 2993enum flow_table_type {
2994 MLX5_IB_FT_RX,
2995 MLX5_IB_FT_TX
2996};
2997
00b7c2ab
MG		 2998#define MLX5_FS_MAX_TYPES 6
2999#define MLX5_FS_MAX_ENTRIES BIT(16)
d4be3f44
YH		 3000
3001static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns,
3002 struct mlx5_ib_flow_prio *prio,
3003 int priority,
4adda112
MB		 3004 int num_entries, int num_groups,
3005 u32 flags)
d4be3f44
YH		 3006{
3007 struct mlx5_flow_table *ft;
3008
3009 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3010 num_entries,
3011 num_groups,
4adda112 3012 0, flags);
d4be3f44
YH		 3013 if (IS_ERR(ft))
3014 return ERR_CAST(ft);
3015
3016 prio->flow_table = ft;
3017 prio->refcount = 0;
3018 return prio;
3019}
3020
038d2ef8 3021static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 3022 struct ib_flow_attr *flow_attr,
3023 enum flow_table_type ft_type)
038d2ef8 3024{
35d19011 3025 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 3026 struct mlx5_flow_namespace *ns = NULL;
3027 struct mlx5_ib_flow_prio *prio;
3028 struct mlx5_flow_table *ft;
dac388ef 3029 int max_table_size;
038d2ef8
MG		 3030 int num_entries;
3031 int num_groups;
4adda112 3032 u32 flags = 0;
038d2ef8 3033 int priority;
038d2ef8 3034
dac388ef
MG		 3035 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3036 log_max_ft_size));
038d2ef8 3037 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
78dd0c43
MB		 3038 enum mlx5_flow_namespace_type fn_type;
3039
3040 if (flow_is_multicast_only(flow_attr) &&
3041 !dont_trap)
038d2ef8
MG		 3042 priority = MLX5_IB_FLOW_MCAST_PRIO;
3043 else
35d19011
MG		 3044 priority = ib_prio_to_core_prio(flow_attr->priority,
3045 dont_trap);
78dd0c43
MB		 3046 if (ft_type == MLX5_IB_FT_RX) {
3047 fn_type = MLX5_FLOW_NAMESPACE_BYPASS;
3048 prio = &dev->flow_db->prios[priority];
4adda112
MB		 3049 if (!dev->rep &&
3050 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3051 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
5c2db53f
MB		 3052 if (!dev->rep &&
3053 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3054 reformat_l3_tunnel_to_l2))
3055 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
78dd0c43
MB		 3056 } else {
3057 max_table_size =
3058 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3059 log_max_ft_size));
3060 fn_type = MLX5_FLOW_NAMESPACE_EGRESS;
3061 prio = &dev->flow_db->egress_prios[priority];
4adda112
MB		 3062 if (!dev->rep &&
3063 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3064 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
78dd0c43
MB		 3065 }
3066 ns = mlx5_get_flow_namespace(dev->mdev, fn_type);
038d2ef8
MG		 3067 num_entries = MLX5_FS_MAX_ENTRIES;
3068 num_groups = MLX5_FS_MAX_TYPES;
038d2ef8
MG		 3069 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3070 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3071 ns = mlx5_get_flow_namespace(dev->mdev,
3072 MLX5_FLOW_NAMESPACE_LEFTOVERS);
3073 build_leftovers_ft_param(&priority,
3074 &num_entries,
3075 &num_groups);
9a4ca38d 3076 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 3077 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3078 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3079 allow_sniffer_and_nic_rx_shared_tir))
3080 return ERR_PTR(-ENOTSUPP);
3081
3082 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3083 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3084 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3085
9a4ca38d 3086 prio = &dev->flow_db->sniffer[ft_type];
cc0e5d42
MG		 3087 priority = 0;
3088 num_entries = 1;
3089 num_groups = 1;
038d2ef8
MG		 3090 }
3091
3092 if (!ns)
3093 return ERR_PTR(-ENOTSUPP);
3094
dac388ef
MG		 3095 if (num_entries > max_table_size)
3096 return ERR_PTR(-ENOMEM);
3097
038d2ef8 3098 ft = prio->flow_table;
d4be3f44 3099 if (!ft)
4adda112
MB		 3100 return _get_prio(ns, prio, priority, num_entries, num_groups,
3101 flags);
038d2ef8 3102
d4be3f44 3103 return prio;
038d2ef8
MG		 3104}
3105
a550ddfc
YH		 3106static void set_underlay_qp(struct mlx5_ib_dev *dev,
3107 struct mlx5_flow_spec *spec,
3108 u32 underlay_qpn)
3109{
3110 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3111 spec->match_criteria,
3112 misc_parameters);
3113 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3114 misc_parameters);
3115
3116 if (underlay_qpn &&
3117 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3118 ft_field_support.bth_dst_qp)) {
3119 MLX5_SET(fte_match_set_misc,
3120 misc_params_v, bth_dst_qp, underlay_qpn);
3121 MLX5_SET(fte_match_set_misc,
3122 misc_params_c, bth_dst_qp, 0xffffff);
3123 }
3124}
3125
5e95af5f
RS		 3126static int read_flow_counters(struct ib_device *ibdev,
3127 struct mlx5_read_counters_attr *read_attr)
3128{
3129 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3130 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3131
3132 return mlx5_fc_query(dev->mdev, fc,
3133 &read_attr->out[IB_COUNTER_PACKETS],
3134 &read_attr->out[IB_COUNTER_BYTES]);
3135}
3136
3137/* flow counters currently expose two counters packets and bytes */
3138#define FLOW_COUNTERS_NUM 2
3b3233fb
RS		 3139static int counters_set_description(struct ib_counters *counters,
3140 enum mlx5_ib_counters_type counters_type,
3141 struct mlx5_ib_flow_counters_desc *desc_data,
3142 u32 ncounters)
3143{
3144 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3145 u32 cntrs_max_index = 0;
3146 int i;
3147
3148 if (counters_type != MLX5_IB_COUNTERS_FLOW)
3149 return -EINVAL;
3150
3151 /* init the fields for the object */
3152 mcounters->type = counters_type;
5e95af5f
RS		 3153 mcounters->read_counters = read_flow_counters;
3154 mcounters->counters_num = FLOW_COUNTERS_NUM;
3b3233fb
RS		 3155 mcounters->ncounters = ncounters;
3156 /* each counter entry have both description and index pair */
3157 for (i = 0; i < ncounters; i++) {
3158 if (desc_data[i].description > IB_COUNTER_BYTES)
3159 return -EINVAL;
3160
3161 if (cntrs_max_index <= desc_data[i].index)
3162 cntrs_max_index = desc_data[i].index + 1;
3163 }
3164
3165 mutex_lock(&mcounters->mcntrs_mutex);
3166 mcounters->counters_data = desc_data;
3167 mcounters->cntrs_max_index = cntrs_max_index;
3168 mutex_unlock(&mcounters->mcntrs_mutex);
3169
3170 return 0;
3171}
3172
3173#define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3174static int flow_counters_set_data(struct ib_counters *ibcounters,
3175 struct mlx5_ib_create_flow *ucmd)
3176{
3177 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3178 struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3179 struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3180 bool hw_hndl = false;
3181 int ret = 0;
3182
3183 if (ucmd && ucmd->ncounters_data != 0) {
3184 cntrs_data = ucmd->data;
3185 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3186 return -EINVAL;
3187
3188 desc_data = kcalloc(cntrs_data->ncounters,
3189 sizeof(*desc_data),
3190 GFP_KERNEL);
3191 if (!desc_data)
3192 return -ENOMEM;
3193
3194 if (copy_from_user(desc_data,
3195 u64_to_user_ptr(cntrs_data->counters_data),
3196 sizeof(*desc_data) * cntrs_data->ncounters)) {
3197 ret = -EFAULT;
3198 goto free;
3199 }
3200 }
3201
3202 if (!mcounters->hw_cntrs_hndl) {
3203 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3204 to_mdev(ibcounters->device)->mdev, false);
e31abf76 3205 if (IS_ERR(mcounters->hw_cntrs_hndl)) {
3206 ret = PTR_ERR(mcounters->hw_cntrs_hndl);
3b3233fb
RS		 3207 goto free;
3208 }
3209 hw_hndl = true;
3210 }
3211
3212 if (desc_data) {
3213 /* counters already bound to at least one flow */
3214 if (mcounters->cntrs_max_index) {
3215 ret = -EINVAL;
3216 goto free_hndl;
3217 }
3218
3219 ret = counters_set_description(ibcounters,
3220 MLX5_IB_COUNTERS_FLOW,
3221 desc_data,
3222 cntrs_data->ncounters);
3223 if (ret)
3224 goto free_hndl;
3225
3226 } else if (!mcounters->cntrs_max_index) {
3227 /* counters not bound yet, must have udata passed */
3228 ret = -EINVAL;
3229 goto free_hndl;
3230 }
3231
3232 return 0;
3233
3234free_hndl:
3235 if (hw_hndl) {
3236 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3237 mcounters->hw_cntrs_hndl);
3238 mcounters->hw_cntrs_hndl = NULL;
3239 }
3240free:
3241 kfree(desc_data);
3242 return ret;
3243}
3244
a550ddfc
YH		 3245static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3246 struct mlx5_ib_flow_prio *ft_prio,
3247 const struct ib_flow_attr *flow_attr,
3248 struct mlx5_flow_destination *dst,
3b3233fb
RS		 3249 u32 underlay_qpn,
3250 struct mlx5_ib_create_flow *ucmd)
038d2ef8
MG		 3251{
3252 struct mlx5_flow_table *ft = ft_prio->flow_table;
3253 struct mlx5_ib_flow_handler *handler;
075572d4 3254 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
c5bb1730 3255 struct mlx5_flow_spec *spec;
3b3233fb
RS		 3256 struct mlx5_flow_destination dest_arr[2] = {};
3257 struct mlx5_flow_destination *rule_dst = dest_arr;
dd063d0e 3258 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 3259 unsigned int spec_index;
71c6e863 3260 u32 prev_type = 0;
038d2ef8 3261 int err = 0;
3b3233fb 3262 int dest_num = 0;
802c2125 3263 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
038d2ef8 3264
19cc7524 3265 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 3266 return ERR_PTR(-EINVAL);
3267
78dd0c43
MB		 3268 if (dev->rep && is_egress)
3269 return ERR_PTR(-EINVAL);
3270
1b9a07ee 3271 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 3272 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 3273 if (!handler || !spec) {
038d2ef8
MG		 3274 err = -ENOMEM;
3275 goto free;
3276 }
3277
3278 INIT_LIST_HEAD(&handler->list);
3b3233fb
RS		 3279 if (dst) {
3280 memcpy(&dest_arr[0], dst, sizeof(*dst));
3281 dest_num++;
3282 }
038d2ef8
MG		 3283
3284 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
19cc7524 3285 err = parse_flow_attr(dev->mdev, spec->match_criteria,
a22ed86c 3286 spec->match_value,
71c6e863
AL		 3287 ib_flow, flow_attr, &flow_act,
3288 prev_type);
038d2ef8
MG		 3289 if (err < 0)
3290 goto free;
3291
71c6e863 3292 prev_type = ((union ib_flow_spec *)ib_flow)->type;
038d2ef8
MG		 3293 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3294 }
3295
a550ddfc
YH		 3296 if (!flow_is_multicast_only(flow_attr))
3297 set_underlay_qp(dev, spec, underlay_qpn);
3298
018a94ee
MB		 3299 if (dev->rep) {
3300 void *misc;
3301
3302 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3303 misc_parameters);
3304 MLX5_SET(fte_match_set_misc, misc, source_port,
3305 dev->rep->vport);
3306 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3307 misc_parameters);
3308 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3309 }
3310
466fa6d2 3311 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
802c2125
AY		 3312
3313 if (is_egress &&
3314 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3315 err = -EINVAL;
3316 goto free;
3317 }
3318
3b3233fb
RS		 3319 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
3320 err = flow_counters_set_data(flow_act.counters, ucmd);
3321 if (err)
3322 goto free;
3323
3324 handler->ibcounters = flow_act.counters;
3325 dest_arr[dest_num].type =
3326 MLX5_FLOW_DESTINATION_TYPE_COUNTER;
3327 dest_arr[dest_num].counter =
3328 to_mcounters(flow_act.counters)->hw_cntrs_hndl;
3329 dest_num++;
3330 }
3331
075572d4 3332 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3b3233fb
RS		 3333 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) {
3334 rule_dst = NULL;
3335 dest_num = 0;
3336 }
a22ed86c 3337 } else {
802c2125
AY		 3338 if (is_egress)
3339 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3340 else
3341 flow_act.action |=
3b3233fb 3342 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
802c2125 3343 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
a22ed86c 3344 }
2ac693f9 3345
a9db0ecf 3346 if (flow_act.has_flow_tag &&
2ac693f9
MR		 3347 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3348 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3349 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
075572d4 3350 flow_act.flow_tag, flow_attr->type);
2ac693f9
MR		 3351 err = -EINVAL;
3352 goto free;
3353 }
74491de9 3354 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 3355 &flow_act,
a22ed86c 3356 rule_dst, dest_num);
038d2ef8
MG		 3357
3358 if (IS_ERR(handler->rule)) {
3359 err = PTR_ERR(handler->rule);
3360 goto free;
3361 }
3362
d9d4980a 3363 ft_prio->refcount++;
5497adc6 3364 handler->prio = ft_prio;
d4be3f44 3365 handler->dev = dev;
038d2ef8
MG		 3366
3367 ft_prio->flow_table = ft;
3368free:
3b3233fb
RS		 3369 if (err && handler) {
3370 if (handler->ibcounters &&
3371 atomic_read(&handler->ibcounters->usecnt) == 1)
3372 counters_clear_description(handler->ibcounters);
038d2ef8 3373 kfree(handler);
3b3233fb 3374 }
c5bb1730 3375 kvfree(spec);
038d2ef8
MG		 3376 return err ? ERR_PTR(err) : handler;
3377}
3378
a550ddfc
YH		 3379static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3380 struct mlx5_ib_flow_prio *ft_prio,
3381 const struct ib_flow_attr *flow_attr,
3382 struct mlx5_flow_destination *dst)
3383{
3b3233fb 3384 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
a550ddfc
YH		 3385}
3386
35d19011
MG		 3387static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3388 struct mlx5_ib_flow_prio *ft_prio,
3389 struct ib_flow_attr *flow_attr,
3390 struct mlx5_flow_destination *dst)
3391{
3392 struct mlx5_ib_flow_handler *handler_dst = NULL;
3393 struct mlx5_ib_flow_handler *handler = NULL;
3394
3395 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3396 if (!IS_ERR(handler)) {
3397 handler_dst = create_flow_rule(dev, ft_prio,
3398 flow_attr, dst);
3399 if (IS_ERR(handler_dst)) {
74491de9 3400 mlx5_del_flow_rules(handler->rule);
d9d4980a 3401 ft_prio->refcount--;
35d19011
MG		 3402 kfree(handler);
3403 handler = handler_dst;
3404 } else {
3405 list_add(&handler_dst->list, &handler->list);
3406 }
3407 }
3408
3409 return handler;
3410}
038d2ef8
MG		 3411enum {
3412 LEFTOVERS_MC,
3413 LEFTOVERS_UC,
3414};
3415
3416static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3417 struct mlx5_ib_flow_prio *ft_prio,
3418 struct ib_flow_attr *flow_attr,
3419 struct mlx5_flow_destination *dst)
3420{
3421 struct mlx5_ib_flow_handler *handler_ucast = NULL;
3422 struct mlx5_ib_flow_handler *handler = NULL;
3423
3424 static struct {
3425 struct ib_flow_attr flow_attr;
3426 struct ib_flow_spec_eth eth_flow;
3427 } leftovers_specs[] = {
3428 [LEFTOVERS_MC] = {
3429 .flow_attr = {
3430 .num_of_specs = 1,
3431 .size = sizeof(leftovers_specs[0])
3432 },
3433 .eth_flow = {
3434 .type = IB_FLOW_SPEC_ETH,
3435 .size = sizeof(struct ib_flow_spec_eth),
3436 .mask = {.dst_mac = {0x1} },
3437 .val = {.dst_mac = {0x1} }
3438 }
3439 },
3440 [LEFTOVERS_UC] = {
3441 .flow_attr = {
3442 .num_of_specs = 1,
3443 .size = sizeof(leftovers_specs[0])
3444 },
3445 .eth_flow = {
3446 .type = IB_FLOW_SPEC_ETH,
3447 .size = sizeof(struct ib_flow_spec_eth),
3448 .mask = {.dst_mac = {0x1} },
3449 .val = {.dst_mac = {} }
3450 }
3451 }
3452 };
3453
3454 handler = create_flow_rule(dev, ft_prio,
3455 &leftovers_specs[LEFTOVERS_MC].flow_attr,
3456 dst);
3457 if (!IS_ERR(handler) &&
3458 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3459 handler_ucast = create_flow_rule(dev, ft_prio,
3460 &leftovers_specs[LEFTOVERS_UC].flow_attr,
3461 dst);
3462 if (IS_ERR(handler_ucast)) {
74491de9 3463 mlx5_del_flow_rules(handler->rule);
d9d4980a 3464 ft_prio->refcount--;
038d2ef8
MG		 3465 kfree(handler);
3466 handler = handler_ucast;
3467 } else {
3468 list_add(&handler_ucast->list, &handler->list);
3469 }
3470 }
3471
3472 return handler;
3473}
3474
cc0e5d42
MG		 3475static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3476 struct mlx5_ib_flow_prio *ft_rx,
3477 struct mlx5_ib_flow_prio *ft_tx,
3478 struct mlx5_flow_destination *dst)
3479{
3480 struct mlx5_ib_flow_handler *handler_rx;
3481 struct mlx5_ib_flow_handler *handler_tx;
3482 int err;
3483 static const struct ib_flow_attr flow_attr = {
3484 .num_of_specs = 0,
3485 .size = sizeof(flow_attr)
3486 };
3487
3488 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3489 if (IS_ERR(handler_rx)) {
3490 err = PTR_ERR(handler_rx);
3491 goto err;
3492 }
3493
3494 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3495 if (IS_ERR(handler_tx)) {
3496 err = PTR_ERR(handler_tx);
3497 goto err_tx;
3498 }
3499
3500 list_add(&handler_tx->list, &handler_rx->list);
3501
3502 return handler_rx;
3503
3504err_tx:
74491de9 3505 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 3506 ft_rx->refcount--;
3507 kfree(handler_rx);
3508err:
3509 return ERR_PTR(err);
3510}
3511
038d2ef8
MG		 3512static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3513 struct ib_flow_attr *flow_attr,
59082a32
MB		 3514 int domain,
3515 struct ib_udata *udata)
038d2ef8
MG		 3516{
3517 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 3518 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 3519 struct mlx5_ib_flow_handler *handler = NULL;
3520 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 3521 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8 3522 struct mlx5_ib_flow_prio *ft_prio;
802c2125 3523 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3b3233fb
RS		 3524 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3525 size_t min_ucmd_sz, required_ucmd_sz;
038d2ef8 3526 int err;
a550ddfc 3527 int underlay_qpn;
038d2ef8 3528
3b3233fb
RS		 3529 if (udata && udata->inlen) {
3530 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3531 sizeof(ucmd_hdr.reserved);
3532 if (udata->inlen < min_ucmd_sz)
3533 return ERR_PTR(-EOPNOTSUPP);
3534
3535 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3536 if (err)
3537 return ERR_PTR(err);
3538
3539 /* currently supports only one counters data */
3540 if (ucmd_hdr.ncounters_data > 1)
3541 return ERR_PTR(-EINVAL);
3542
3543 required_ucmd_sz = min_ucmd_sz +
3544 sizeof(struct mlx5_ib_flow_counters_data) *
3545 ucmd_hdr.ncounters_data;
3546 if (udata->inlen > required_ucmd_sz &&
3547 !ib_is_udata_cleared(udata, required_ucmd_sz,
3548 udata->inlen - required_ucmd_sz))
3549 return ERR_PTR(-EOPNOTSUPP);
3550
3551 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3552 if (!ucmd)
3553 return ERR_PTR(-ENOMEM);
3554
3555 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
299eafee
GS		 3556 if (err)
3557 goto free_ucmd;
3b3233fb 3558 }
59082a32 3559
299eafee
GS		 3560 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) {
3561 err = -ENOMEM;
3562 goto free_ucmd;
3563 }
038d2ef8
MG		 3564
3565 if (domain != IB_FLOW_DOMAIN_USER ||
508562d6 3566 flow_attr->port > dev->num_ports ||
802c2125 3567 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
299eafee
GS		 3568 IB_FLOW_ATTR_FLAGS_EGRESS))) {
3569 err = -EINVAL;
3570 goto free_ucmd;
3571 }
802c2125
AY		 3572
3573 if (is_egress &&
3574 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
299eafee
GS		 3575 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3576 err = -EINVAL;
3577 goto free_ucmd;
3578 }
038d2ef8
MG		 3579
3580 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
299eafee
GS		 3581 if (!dst) {
3582 err = -ENOMEM;
3583 goto free_ucmd;
3584 }
038d2ef8 3585
9a4ca38d 3586 mutex_lock(&dev->flow_db->lock);
038d2ef8 3587
802c2125
AY		 3588 ft_prio = get_flow_table(dev, flow_attr,
3589 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
038d2ef8
MG		 3590 if (IS_ERR(ft_prio)) {
3591 err = PTR_ERR(ft_prio);
3592 goto unlock;
3593 }
cc0e5d42
MG		 3594 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3595 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3596 if (IS_ERR(ft_prio_tx)) {
3597 err = PTR_ERR(ft_prio_tx);
3598 ft_prio_tx = NULL;
3599 goto destroy_ft;
3600 }
3601 }
038d2ef8 3602
802c2125
AY		 3603 if (is_egress) {
3604 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3605 } else {
3606 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3607 if (mqp->flags & MLX5_IB_QP_RSS)
3608 dst->tir_num = mqp->rss_qp.tirn;
3609 else
3610 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3611 }
038d2ef8
MG		 3612
3613 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 3614 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3615 handler = create_dont_trap_rule(dev, ft_prio,
3616 flow_attr, dst);
3617 } else {
a550ddfc
YH		 3618 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3619 mqp->underlay_qpn : 0;
3620 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3b3233fb 3621 dst, underlay_qpn, ucmd);
35d19011 3622 }
038d2ef8
MG		 3623 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3624 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3625 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3626 dst);
cc0e5d42
MG		 3627 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3628 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 3629 } else {
3630 err = -EINVAL;
3631 goto destroy_ft;
3632 }
3633
3634 if (IS_ERR(handler)) {
3635 err = PTR_ERR(handler);
3636 handler = NULL;
3637 goto destroy_ft;
3638 }
3639
9a4ca38d 3640 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3641 kfree(dst);
3b3233fb 3642 kfree(ucmd);
038d2ef8
MG		 3643
3644 return &handler->ibflow;
3645
3646destroy_ft:
3647 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 3648 if (ft_prio_tx)
3649 put_flow_table(dev, ft_prio_tx, false);
038d2ef8 3650unlock:
9a4ca38d 3651 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3652 kfree(dst);
299eafee 3653free_ucmd:
3b3233fb 3654 kfree(ucmd);
038d2ef8
MG		 3655 return ERR_PTR(err);
3656}
3657
b47fd4ff
MB		 3658static struct mlx5_ib_flow_prio *
3659_get_flow_table(struct mlx5_ib_dev *dev,
3660 struct mlx5_ib_flow_matcher *fs_matcher,
3661 bool mcast)
d4be3f44 3662{
d4be3f44
YH		 3663 struct mlx5_flow_namespace *ns = NULL;
3664 struct mlx5_ib_flow_prio *prio;
b47fd4ff
MB		 3665 int max_table_size;
3666 u32 flags = 0;
3667 int priority;
3668
3669 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) {
3670 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3671 log_max_ft_size));
3672 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3673 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3674 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3675 reformat_l3_tunnel_to_l2))
3676 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3677 } else { /* Can only be MLX5_FLOW_NAMESPACE_EGRESS */
3678 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3679 log_max_ft_size));
3680 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3681 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3682 }
d4be3f44 3683
d4be3f44
YH		 3684 if (max_table_size < MLX5_FS_MAX_ENTRIES)
3685 return ERR_PTR(-ENOMEM);
3686
3687 if (mcast)
3688 priority = MLX5_IB_FLOW_MCAST_PRIO;
3689 else
b47fd4ff 3690 priority = ib_prio_to_core_prio(fs_matcher->priority, false);
d4be3f44 3691
b47fd4ff 3692 ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type);
d4be3f44
YH		 3693 if (!ns)
3694 return ERR_PTR(-ENOTSUPP);
3695
b47fd4ff
MB		 3696 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS)
3697 prio = &dev->flow_db->prios[priority];
3698 else
3699 prio = &dev->flow_db->egress_prios[priority];
d4be3f44
YH		 3700
3701 if (prio->flow_table)
3702 return prio;
3703
3704 return _get_prio(ns, prio, priority, MLX5_FS_MAX_ENTRIES,
b47fd4ff 3705 MLX5_FS_MAX_TYPES, flags);
d4be3f44
YH		 3706}
3707
3708static struct mlx5_ib_flow_handler *
3709_create_raw_flow_rule(struct mlx5_ib_dev *dev,
3710 struct mlx5_ib_flow_prio *ft_prio,
3711 struct mlx5_flow_destination *dst,
3712 struct mlx5_ib_flow_matcher *fs_matcher,
b823dd6d 3713 struct mlx5_flow_act *flow_act,
d4be3f44
YH		 3714 void *cmd_in, int inlen)
3715{
3716 struct mlx5_ib_flow_handler *handler;
d4be3f44
YH		 3717 struct mlx5_flow_spec *spec;
3718 struct mlx5_flow_table *ft = ft_prio->flow_table;
3719 int err = 0;
3720
3721 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3722 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3723 if (!handler || !spec) {
3724 err = -ENOMEM;
3725 goto free;
3726 }
3727
3728 INIT_LIST_HEAD(&handler->list);
3729
3730 memcpy(spec->match_value, cmd_in, inlen);
3731 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params,
3732 fs_matcher->mask_len);
3733 spec->match_criteria_enable = fs_matcher->match_criteria_enable;
3734
d4be3f44 3735 handler->rule = mlx5_add_flow_rules(ft, spec,
b823dd6d 3736 flow_act, dst, 1);
d4be3f44
YH		 3737
3738 if (IS_ERR(handler->rule)) {
3739 err = PTR_ERR(handler->rule);
3740 goto free;
3741 }
3742
3743 ft_prio->refcount++;
3744 handler->prio = ft_prio;
3745 handler->dev = dev;
3746 ft_prio->flow_table = ft;
3747
3748free:
3749 if (err)
3750 kfree(handler);
3751 kvfree(spec);
3752 return err ? ERR_PTR(err) : handler;
3753}
3754
3755static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher,
3756 void *match_v)
3757{
3758 void *match_c;
3759 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4;
3760 void *dmac, *dmac_mask;
3761 void *ipv4, *ipv4_mask;
3762
3763 if (!(fs_matcher->match_criteria_enable &
3764 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT)))
3765 return false;
3766
3767 match_c = fs_matcher->matcher_mask.match_params;
3768 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v,
3769 outer_headers);
3770 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c,
3771 outer_headers);
3772
3773 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
3774 dmac_47_16);
3775 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
3776 dmac_47_16);
3777
3778 if (is_multicast_ether_addr(dmac) &&
3779 is_multicast_ether_addr(dmac_mask))
3780 return true;
3781
3782 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
3783 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3784
3785 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
3786 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3787
3788 if (ipv4_is_multicast(*(__be32 *)(ipv4)) &&
3789 ipv4_is_multicast(*(__be32 *)(ipv4_mask)))
3790 return true;
3791
3792 return false;
3793}
3794
32269441
YH		 3795struct mlx5_ib_flow_handler *
3796mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
3797 struct mlx5_ib_flow_matcher *fs_matcher,
b823dd6d 3798 struct mlx5_flow_act *flow_act,
32269441
YH		 3799 void *cmd_in, int inlen, int dest_id,
3800 int dest_type)
3801{
d4be3f44
YH		 3802 struct mlx5_flow_destination *dst;
3803 struct mlx5_ib_flow_prio *ft_prio;
d4be3f44
YH		 3804 struct mlx5_ib_flow_handler *handler;
3805 bool mcast;
3806 int err;
3807
3808 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL)
3809 return ERR_PTR(-EOPNOTSUPP);
3810
3811 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO)
3812 return ERR_PTR(-ENOMEM);
3813
d4be3f44
YH		 3814 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3815 if (!dst)
3816 return ERR_PTR(-ENOMEM);
3817
3818 mcast = raw_fs_is_multicast(fs_matcher, cmd_in);
3819 mutex_lock(&dev->flow_db->lock);
3820
b47fd4ff 3821 ft_prio = _get_flow_table(dev, fs_matcher, mcast);
d4be3f44
YH		 3822 if (IS_ERR(ft_prio)) {
3823 err = PTR_ERR(ft_prio);
3824 goto unlock;
3825 }
3826
6346f0bf
YH		 3827 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
3828 dst->type = dest_type;
3829 dst->tir_num = dest_id;
b823dd6d 3830 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
a7ee18bd 3831 } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) {
6346f0bf
YH		 3832 dst->type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
3833 dst->ft_num = dest_id;
b823dd6d 3834 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
a7ee18bd
MB		 3835 } else {
3836 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3837 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
6346f0bf
YH		 3838 }
3839
b823dd6d
MB		 3840 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher, flow_act,
3841 cmd_in, inlen);
d4be3f44
YH		 3842
3843 if (IS_ERR(handler)) {
3844 err = PTR_ERR(handler);
3845 goto destroy_ft;
3846 }
3847
3848 mutex_unlock(&dev->flow_db->lock);
3849 atomic_inc(&fs_matcher->usecnt);
3850 handler->flow_matcher = fs_matcher;
3851
3852 kfree(dst);
3853
3854 return handler;
3855
3856destroy_ft:
3857 put_flow_table(dev, ft_prio, false);
3858unlock:
3859 mutex_unlock(&dev->flow_db->lock);
3860 kfree(dst);
3861
3862 return ERR_PTR(err);
32269441
YH		 3863}
3864
c6475a0b
AY		 3865static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
3866{
3867 u32 flags = 0;
3868
3869 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
3870 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
3871
3872 return flags;
3873}
3874
3875#define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
3876static struct ib_flow_action *
3877mlx5_ib_create_flow_action_esp(struct ib_device *device,
3878 const struct ib_flow_action_attrs_esp *attr,
3879 struct uverbs_attr_bundle *attrs)
3880{
3881 struct mlx5_ib_dev *mdev = to_mdev(device);
3882 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
3883 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
3884 struct mlx5_ib_flow_action *action;
3885 u64 action_flags;
3886 u64 flags;
3887 int err = 0;
3888
bccd0622
JG		 3889 err = uverbs_get_flags64(
3890 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
3891 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1));
3892 if (err)
3893 return ERR_PTR(err);
c6475a0b
AY		 3894
3895 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
3896
3897 /* We current only support a subset of the standard features. Only a
3898 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
3899 * (with overlap). Full offload mode isn't supported.
3900 */
3901 if (!attr->keymat || attr->replay || attr->encap ||
3902 attr->spi || attr->seq || attr->tfc_pad ||
3903 attr->hard_limit_pkts ||
3904 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3905 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
3906 return ERR_PTR(-EOPNOTSUPP);
3907
3908 if (attr->keymat->protocol !=
3909 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
3910 return ERR_PTR(-EOPNOTSUPP);
3911
3912 aes_gcm = &attr->keymat->keymat.aes_gcm;
3913
3914 if (aes_gcm->icv_len != 16 ||
3915 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
3916 return ERR_PTR(-EOPNOTSUPP);
3917
3918 action = kmalloc(sizeof(*action), GFP_KERNEL);
3919 if (!action)
3920 return ERR_PTR(-ENOMEM);
3921
3922 action->esp_aes_gcm.ib_flags = attr->flags;
3923 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
3924 sizeof(accel_attrs.keymat.aes_gcm.aes_key));
3925 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
3926 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
3927 sizeof(accel_attrs.keymat.aes_gcm.salt));
3928 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
3929 sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
3930 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
3931 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
3932 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
3933
3934 accel_attrs.esn = attr->esn;
3935 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
3936 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
3937 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3938 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3939
3940 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
3941 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
3942
3943 action->esp_aes_gcm.ctx =
3944 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
3945 if (IS_ERR(action->esp_aes_gcm.ctx)) {
3946 err = PTR_ERR(action->esp_aes_gcm.ctx);
3947 goto err_parse;
3948 }
3949
3950 action->esp_aes_gcm.ib_flags = attr->flags;
3951
3952 return &action->ib_action;
3953
3954err_parse:
3955 kfree(action);
3956 return ERR_PTR(err);
3957}
3958
349705c1
MB		 3959static int
3960mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
3961 const struct ib_flow_action_attrs_esp *attr,
3962 struct uverbs_attr_bundle *attrs)
3963{
3964 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3965 struct mlx5_accel_esp_xfrm_attrs accel_attrs;
3966 int err = 0;
3967
3968 if (attr->keymat || attr->replay || attr->encap ||
3969 attr->spi || attr->seq || attr->tfc_pad ||
3970 attr->hard_limit_pkts ||
3971 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3972 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
3973 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
3974 return -EOPNOTSUPP;
3975
3976 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
3977 * be modified.
3978 */
3979 if (!(maction->esp_aes_gcm.ib_flags &
3980 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
3981 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3982 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
3983 return -EINVAL;
3984
3985 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
3986 sizeof(accel_attrs));
3987
3988 accel_attrs.esn = attr->esn;
3989 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3990 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3991 else
3992 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3993
3994 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
3995 &accel_attrs);
3996 if (err)
3997 return err;
3998
3999 maction->esp_aes_gcm.ib_flags &=
4000 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4001 maction->esp_aes_gcm.ib_flags |=
4002 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4003
4004 return 0;
4005}
4006
c6475a0b
AY		 4007static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
4008{
4009 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4010
4011 switch (action->type) {
4012 case IB_FLOW_ACTION_ESP:
4013 /*
4014 * We only support aes_gcm by now, so we implicitly know this is
4015 * the underline crypto.
4016 */
4017 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
4018 break;
b4749bf2
MB		 4019 case IB_FLOW_ACTION_UNSPECIFIED:
4020 mlx5_ib_destroy_flow_action_raw(maction);
4021 break;
c6475a0b
AY		 4022 default:
4023 WARN_ON(true);
4024 break;
4025 }
4026
4027 kfree(maction);
4028 return 0;
4029}
4030
e126ba97
EC		 4031static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4032{
4033 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 4034 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97
EC		 4035 int err;
4036
81e30880
YH		 4037 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
4038 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
4039 return -EOPNOTSUPP;
4040 }
4041
9603b61d 4042 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 4043 if (err)
4044 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
4045 ibqp->qp_num, gid->raw);
4046
4047 return err;
4048}
4049
4050static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4051{
4052 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4053 int err;
4054
9603b61d 4055 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 4056 if (err)
4057 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
4058 ibqp->qp_num, gid->raw);
4059
4060 return err;
4061}
4062
4063static int init_node_data(struct mlx5_ib_dev *dev)
4064{
1b5daf11 4065 int err;
e126ba97 4066
1b5daf11 4067 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 4068 if (err)
1b5daf11 4069 return err;
e126ba97 4070
1b5daf11 4071 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 4072
1b5daf11 4073 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 4074}
4075
4076static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
4077 char *buf)
4078{
4079 struct mlx5_ib_dev *dev =
4080 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4081
9603b61d 4082 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 4083}
4084
4085static ssize_t show_reg_pages(struct device *device,
4086 struct device_attribute *attr, char *buf)
4087{
4088 struct mlx5_ib_dev *dev =
4089 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4090
6aec21f6 4091 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 4092}
4093
4094static ssize_t show_hca(struct device *device, struct device_attribute *attr,
4095 char *buf)
4096{
4097 struct mlx5_ib_dev *dev =
4098 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 4099 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 4100}
4101
e126ba97
EC		 4102static ssize_t show_rev(struct device *device, struct device_attribute *attr,
4103 char *buf)
4104{
4105 struct mlx5_ib_dev *dev =
4106 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 4107 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 4108}
4109
4110static ssize_t show_board(struct device *device, struct device_attribute *attr,
4111 char *buf)
4112{
4113 struct mlx5_ib_dev *dev =
4114 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4115 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 4116 dev->mdev->board_id);
e126ba97
EC		 4117}
4118
4119static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
e126ba97
EC		 4120static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
4121static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
4122static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
4123static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
4124
4125static struct device_attribute *mlx5_class_attributes[] = {
4126 &dev_attr_hw_rev,
e126ba97
EC		 4127 &dev_attr_hca_type,
4128 &dev_attr_board_id,
4129 &dev_attr_fw_pages,
4130 &dev_attr_reg_pages,
4131};
4132
7722f47e
HE		 4133static void pkey_change_handler(struct work_struct *work)
4134{
4135 struct mlx5_ib_port_resources *ports =
4136 container_of(work, struct mlx5_ib_port_resources,
4137 pkey_change_work);
4138
4139 mutex_lock(&ports->devr->mutex);
4140 mlx5_ib_gsi_pkey_change(ports->gsi);
4141 mutex_unlock(&ports->devr->mutex);
4142}
4143
89ea94a7
MG		 4144static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
4145{
4146 struct mlx5_ib_qp *mqp;
4147 struct mlx5_ib_cq *send_mcq, *recv_mcq;
4148 struct mlx5_core_cq *mcq;
4149 struct list_head cq_armed_list;
4150 unsigned long flags_qp;
4151 unsigned long flags_cq;
4152 unsigned long flags;
4153
4154 INIT_LIST_HEAD(&cq_armed_list);
4155
4156 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
4157 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
4158 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
4159 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
4160 if (mqp->sq.tail != mqp->sq.head) {
4161 send_mcq = to_mcq(mqp->ibqp.send_cq);
4162 spin_lock_irqsave(&send_mcq->lock, flags_cq);
4163 if (send_mcq->mcq.comp &&
4164 mqp->ibqp.send_cq->comp_handler) {
4165 if (!send_mcq->mcq.reset_notify_added) {
4166 send_mcq->mcq.reset_notify_added = 1;
4167 list_add_tail(&send_mcq->mcq.reset_notify,
4168 &cq_armed_list);
4169 }
4170 }
4171 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
4172 }
4173 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
4174 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
4175 /* no handling is needed for SRQ */
4176 if (!mqp->ibqp.srq) {
4177 if (mqp->rq.tail != mqp->rq.head) {
4178 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
4179 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
4180 if (recv_mcq->mcq.comp &&
4181 mqp->ibqp.recv_cq->comp_handler) {
4182 if (!recv_mcq->mcq.reset_notify_added) {
4183 recv_mcq->mcq.reset_notify_added = 1;
4184 list_add_tail(&recv_mcq->mcq.reset_notify,
4185 &cq_armed_list);
4186 }
4187 }
4188 spin_unlock_irqrestore(&recv_mcq->lock,
4189 flags_cq);
4190 }
4191 }
4192 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
4193 }
4194 /*At that point all inflight post send were put to be executed as of we
4195 * lock/unlock above locks Now need to arm all involved CQs.
4196 */
4197 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4198 mcq->comp(mcq);
4199 }
4200 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
4201}
4202
03404e8a
MG		 4203static void delay_drop_handler(struct work_struct *work)
4204{
4205 int err;
4206 struct mlx5_ib_delay_drop *delay_drop =
4207 container_of(work, struct mlx5_ib_delay_drop,
4208 delay_drop_work);
4209
fe248c3a
MG		 4210 atomic_inc(&delay_drop->events_cnt);
4211
03404e8a
MG		 4212 mutex_lock(&delay_drop->lock);
4213 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
4214 delay_drop->timeout);
4215 if (err) {
4216 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4217 delay_drop->timeout);
4218 delay_drop->activate = false;
4219 }
4220 mutex_unlock(&delay_drop->lock);
4221}
4222
d69a24e0 4223static void mlx5_ib_handle_event(struct work_struct *_work)
e126ba97 4224{
d69a24e0
DJ		 4225 struct mlx5_ib_event_work *work =
4226 container_of(_work, struct mlx5_ib_event_work, work);
4227 struct mlx5_ib_dev *ibdev;
e126ba97 4228 struct ib_event ibev;
dbaaff2a 4229 bool fatal = false;
aba46213 4230 u8 port = (u8)work->param;
e126ba97 4231
d69a24e0
DJ		 4232 if (mlx5_core_is_mp_slave(work->dev)) {
4233 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context);
4234 if (!ibdev)
4235 goto out;
4236 } else {
4237 ibdev = work->context;
4238 }
4239
4240 switch (work->event) {
e126ba97 4241 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 4242 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 4243 mlx5_ib_handle_internal_error(ibdev);
dbaaff2a 4244 fatal = true;
e126ba97
EC		 4245 break;
4246
4247 case MLX5_DEV_EVENT_PORT_UP:
e126ba97 4248 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 4249 case MLX5_DEV_EVENT_PORT_INITIALIZED:
5ec8c83e
AH		 4250 /* In RoCE, port up/down events are handled in
4251 * mlx5_netdev_event().
4252 */
4253 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4254 IB_LINK_LAYER_ETHERNET)
d69a24e0 4255 goto out;
5ec8c83e 4256
d69a24e0 4257 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ?
5ec8c83e 4258 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
e126ba97
EC		 4259 break;
4260
e126ba97
EC		 4261 case MLX5_DEV_EVENT_LID_CHANGE:
4262 ibev.event = IB_EVENT_LID_CHANGE;
e126ba97
EC		 4263 break;
4264
4265 case MLX5_DEV_EVENT_PKEY_CHANGE:
4266 ibev.event = IB_EVENT_PKEY_CHANGE;
7722f47e 4267 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 4268 break;
4269
4270 case MLX5_DEV_EVENT_GUID_CHANGE:
4271 ibev.event = IB_EVENT_GID_CHANGE;
e126ba97
EC		 4272 break;
4273
4274 case MLX5_DEV_EVENT_CLIENT_REREG:
4275 ibev.event = IB_EVENT_CLIENT_REREGISTER;
e126ba97 4276 break;
03404e8a
MG		 4277 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
4278 schedule_work(&ibdev->delay_drop.delay_drop_work);
4279 goto out;
bdc37924 4280 default:
03404e8a 4281 goto out;
e126ba97
EC		 4282 }
4283
4284 ibev.device = &ibdev->ib_dev;
4285 ibev.element.port_num = port;
4286
aba46213 4287 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) {
a0c84c32 4288 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
03404e8a 4289 goto out;
a0c84c32
EC		 4290 }
4291
e126ba97
EC		 4292 if (ibdev->ib_active)
4293 ib_dispatch_event(&ibev);
dbaaff2a
EC		 4294
4295 if (fatal)
4296 ibdev->ib_active = false;
03404e8a 4297out:
d69a24e0
DJ		 4298 kfree(work);
4299}
4300
4301static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4302 enum mlx5_dev_event event, unsigned long param)
4303{
4304 struct mlx5_ib_event_work *work;
4305
4306 work = kmalloc(sizeof(*work), GFP_ATOMIC);
10bea9c8 4307 if (!work)
d69a24e0 4308 return;
d69a24e0 4309
10bea9c8
LR		 4310 INIT_WORK(&work->work, mlx5_ib_handle_event);
4311 work->dev = dev;
4312 work->param = param;
4313 work->context = context;
4314 work->event = event;
4315
4316 queue_work(mlx5_ib_event_wq, &work->work);
e126ba97
EC		 4317}
4318
c43f1112
MG		 4319static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4320{
4321 struct mlx5_hca_vport_context vport_ctx;
4322 int err;
4323 int port;
4324
508562d6 4325 for (port = 1; port <= dev->num_ports; port++) {
c43f1112
MG		 4326 dev->mdev->port_caps[port - 1].has_smi = false;
4327 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4328 MLX5_CAP_PORT_TYPE_IB) {
4329 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4330 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4331 port, 0,
4332 &vport_ctx);
4333 if (err) {
4334 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4335 port, err);
4336 return err;
4337 }
4338 dev->mdev->port_caps[port - 1].has_smi =
4339 vport_ctx.has_smi;
4340 } else {
4341 dev->mdev->port_caps[port - 1].has_smi = true;
4342 }
4343 }
4344 }
4345 return 0;
4346}
4347
e126ba97
EC		 4348static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4349{
4350 int port;
4351
508562d6 4352 for (port = 1; port <= dev->num_ports; port++)
e126ba97
EC		 4353 mlx5_query_ext_port_caps(dev, port);
4354}
4355
32f69e4b 4356static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
e126ba97
EC		 4357{
4358 struct ib_device_attr *dprops = NULL;
4359 struct ib_port_attr *pprops = NULL;
f614fc15 4360 int err = -ENOMEM;
2528e33e 4361 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 4362
4363 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
4364 if (!pprops)
4365 goto out;
4366
4367 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4368 if (!dprops)
4369 goto out;
4370
c43f1112
MG		 4371 err = set_has_smi_cap(dev);
4372 if (err)
4373 goto out;
4374
2528e33e 4375 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 4376 if (err) {
4377 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4378 goto out;
4379 }
4380
32f69e4b
DJ		 4381 memset(pprops, 0, sizeof(*pprops));
4382 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4383 if (err) {
4384 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4385 port, err);
4386 goto out;
e126ba97
EC		 4387 }
4388
32f69e4b
DJ		 4389 dev->mdev->port_caps[port - 1].pkey_table_len =
4390 dprops->max_pkeys;
4391 dev->mdev->port_caps[port - 1].gid_table_len =
4392 pprops->gid_tbl_len;
4393 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4394 port, dprops->max_pkeys, pprops->gid_tbl_len);
4395
e126ba97
EC		 4396out:
4397 kfree(pprops);
4398 kfree(dprops);
4399
4400 return err;
4401}
4402
4403static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4404{
4405 int err;
4406
4407 err = mlx5_mr_cache_cleanup(dev);
4408 if (err)
4409 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4410
32927e28
MB		 4411 if (dev->umrc.qp)
4412 mlx5_ib_destroy_qp(dev->umrc.qp);
4413 if (dev->umrc.cq)
4414 ib_free_cq(dev->umrc.cq);
4415 if (dev->umrc.pd)
4416 ib_dealloc_pd(dev->umrc.pd);
e126ba97
EC		 4417}
4418
4419enum {
4420 MAX_UMR_WR = 128,
4421};
4422
4423static int create_umr_res(struct mlx5_ib_dev *dev)
4424{
4425 struct ib_qp_init_attr *init_attr = NULL;
4426 struct ib_qp_attr *attr = NULL;
4427 struct ib_pd *pd;
4428 struct ib_cq *cq;
4429 struct ib_qp *qp;
e126ba97
EC		 4430 int ret;
4431
4432 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4433 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4434 if (!attr || !init_attr) {
4435 ret = -ENOMEM;
4436 goto error_0;
4437 }
4438
ed082d36 4439 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 4440 if (IS_ERR(pd)) {
4441 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4442 ret = PTR_ERR(pd);
4443 goto error_0;
4444 }
4445
add08d76 4446 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 4447 if (IS_ERR(cq)) {
4448 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4449 ret = PTR_ERR(cq);
4450 goto error_2;
4451 }
e126ba97
EC		 4452
4453 init_attr->send_cq = cq;
4454 init_attr->recv_cq = cq;
4455 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4456 init_attr->cap.max_send_wr = MAX_UMR_WR;
4457 init_attr->cap.max_send_sge = 1;
4458 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4459 init_attr->port_num = 1;
4460 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4461 if (IS_ERR(qp)) {
4462 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4463 ret = PTR_ERR(qp);
4464 goto error_3;
4465 }
4466 qp->device = &dev->ib_dev;
4467 qp->real_qp = qp;
4468 qp->uobject = NULL;
4469 qp->qp_type = MLX5_IB_QPT_REG_UMR;
31fde034
MD		 4470 qp->send_cq = init_attr->send_cq;
4471 qp->recv_cq = init_attr->recv_cq;
e126ba97
EC		 4472
4473 attr->qp_state = IB_QPS_INIT;
4474 attr->port_num = 1;
4475 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4476 IB_QP_PORT, NULL);
4477 if (ret) {
4478 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4479 goto error_4;
4480 }
4481
4482 memset(attr, 0, sizeof(*attr));
4483 attr->qp_state = IB_QPS_RTR;
4484 attr->path_mtu = IB_MTU_256;
4485
4486 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4487 if (ret) {
4488 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4489 goto error_4;
4490 }
4491
4492 memset(attr, 0, sizeof(*attr));
4493 attr->qp_state = IB_QPS_RTS;
4494 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4495 if (ret) {
4496 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4497 goto error_4;
4498 }
4499
4500 dev->umrc.qp = qp;
4501 dev->umrc.cq = cq;
e126ba97
EC		 4502 dev->umrc.pd = pd;
4503
4504 sema_init(&dev->umrc.sem, MAX_UMR_WR);
4505 ret = mlx5_mr_cache_init(dev);
4506 if (ret) {
4507 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4508 goto error_4;
4509 }
4510
4511 kfree(attr);
4512 kfree(init_attr);
4513
4514 return 0;
4515
4516error_4:
4517 mlx5_ib_destroy_qp(qp);
32927e28 4518 dev->umrc.qp = NULL;
e126ba97
EC		 4519
4520error_3:
add08d76 4521 ib_free_cq(cq);
32927e28 4522 dev->umrc.cq = NULL;
e126ba97
EC		 4523
4524error_2:
e126ba97 4525 ib_dealloc_pd(pd);
32927e28 4526 dev->umrc.pd = NULL;
e126ba97
EC		 4527
4528error_0:
4529 kfree(attr);
4530 kfree(init_attr);
4531 return ret;
4532}
4533
6e8484c5
MG		 4534static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4535{
4536 switch (umr_fence_cap) {
4537 case MLX5_CAP_UMR_FENCE_NONE:
4538 return MLX5_FENCE_MODE_NONE;
4539 case MLX5_CAP_UMR_FENCE_SMALL:
4540 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4541 default:
4542 return MLX5_FENCE_MODE_STRONG_ORDERING;
4543 }
4544}
4545
e126ba97
EC		 4546static int create_dev_resources(struct mlx5_ib_resources *devr)
4547{
4548 struct ib_srq_init_attr attr;
4549 struct mlx5_ib_dev *dev;
bcf4c1ea 4550 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 4551 int port;
e126ba97
EC		 4552 int ret = 0;
4553
4554 dev = container_of(devr, struct mlx5_ib_dev, devr);
4555
d16e91da
HE		 4556 mutex_init(&devr->mutex);
4557
e126ba97
EC		 4558 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
4559 if (IS_ERR(devr->p0)) {
4560 ret = PTR_ERR(devr->p0);
4561 goto error0;
4562 }
4563 devr->p0->device = &dev->ib_dev;
4564 devr->p0->uobject = NULL;
4565 atomic_set(&devr->p0->usecnt, 0);
4566
bcf4c1ea 4567 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 4568 if (IS_ERR(devr->c0)) {
4569 ret = PTR_ERR(devr->c0);
4570 goto error1;
4571 }
4572 devr->c0->device = &dev->ib_dev;
4573 devr->c0->uobject = NULL;
4574 devr->c0->comp_handler = NULL;
4575 devr->c0->event_handler = NULL;
4576 devr->c0->cq_context = NULL;
4577 atomic_set(&devr->c0->usecnt, 0);
4578
4579 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4580 if (IS_ERR(devr->x0)) {
4581 ret = PTR_ERR(devr->x0);
4582 goto error2;
4583 }
4584 devr->x0->device = &dev->ib_dev;
4585 devr->x0->inode = NULL;
4586 atomic_set(&devr->x0->usecnt, 0);
4587 mutex_init(&devr->x0->tgt_qp_mutex);
4588 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4589
4590 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4591 if (IS_ERR(devr->x1)) {
4592 ret = PTR_ERR(devr->x1);
4593 goto error3;
4594 }
4595 devr->x1->device = &dev->ib_dev;
4596 devr->x1->inode = NULL;
4597 atomic_set(&devr->x1->usecnt, 0);
4598 mutex_init(&devr->x1->tgt_qp_mutex);
4599 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4600
4601 memset(&attr, 0, sizeof(attr));
4602 attr.attr.max_sge = 1;
4603 attr.attr.max_wr = 1;
4604 attr.srq_type = IB_SRQT_XRC;
1a56ff6d 4605 attr.ext.cq = devr->c0;
e126ba97
EC		 4606 attr.ext.xrc.xrcd = devr->x0;
4607
4608 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4609 if (IS_ERR(devr->s0)) {
4610 ret = PTR_ERR(devr->s0);
4611 goto error4;
4612 }
4613 devr->s0->device = &dev->ib_dev;
4614 devr->s0->pd = devr->p0;
4615 devr->s0->uobject = NULL;
4616 devr->s0->event_handler = NULL;
4617 devr->s0->srq_context = NULL;
4618 devr->s0->srq_type = IB_SRQT_XRC;
4619 devr->s0->ext.xrc.xrcd = devr->x0;
1a56ff6d 4620 devr->s0->ext.cq = devr->c0;
e126ba97 4621 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1a56ff6d 4622 atomic_inc(&devr->s0->ext.cq->usecnt);
e126ba97
EC		 4623 atomic_inc(&devr->p0->usecnt);
4624 atomic_set(&devr->s0->usecnt, 0);
4625
4aa17b28
HA		 4626 memset(&attr, 0, sizeof(attr));
4627 attr.attr.max_sge = 1;
4628 attr.attr.max_wr = 1;
4629 attr.srq_type = IB_SRQT_BASIC;
4630 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4631 if (IS_ERR(devr->s1)) {
4632 ret = PTR_ERR(devr->s1);
4633 goto error5;
4634 }
4635 devr->s1->device = &dev->ib_dev;
4636 devr->s1->pd = devr->p0;
4637 devr->s1->uobject = NULL;
4638 devr->s1->event_handler = NULL;
4639 devr->s1->srq_context = NULL;
4640 devr->s1->srq_type = IB_SRQT_BASIC;
1a56ff6d 4641 devr->s1->ext.cq = devr->c0;
4aa17b28 4642 atomic_inc(&devr->p0->usecnt);
1a56ff6d 4643 atomic_set(&devr->s1->usecnt, 0);
4aa17b28 4644
7722f47e
HE		 4645 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
4646 INIT_WORK(&devr->ports[port].pkey_change_work,
4647 pkey_change_handler);
4648 devr->ports[port].devr = devr;
4649 }
4650
e126ba97
EC		 4651 return 0;
4652
4aa17b28
HA		 4653error5:
4654 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 4655error4:
4656 mlx5_ib_dealloc_xrcd(devr->x1);
4657error3:
4658 mlx5_ib_dealloc_xrcd(devr->x0);
4659error2:
4660 mlx5_ib_destroy_cq(devr->c0);
4661error1:
4662 mlx5_ib_dealloc_pd(devr->p0);
4663error0:
4664 return ret;
4665}
4666
4667static void destroy_dev_resources(struct mlx5_ib_resources *devr)
4668{
7722f47e
HE		 4669 struct mlx5_ib_dev *dev =
4670 container_of(devr, struct mlx5_ib_dev, devr);
4671 int port;
4672
4aa17b28 4673 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 4674 mlx5_ib_destroy_srq(devr->s0);
4675 mlx5_ib_dealloc_xrcd(devr->x0);
4676 mlx5_ib_dealloc_xrcd(devr->x1);
4677 mlx5_ib_destroy_cq(devr->c0);
4678 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 4679
4680 /* Make sure no change P_Key work items are still executing */
4681 for (port = 0; port < dev->num_ports; ++port)
4682 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 4683}
4684
b02289b3
AK		 4685static u32 get_core_cap_flags(struct ib_device *ibdev,
4686 struct mlx5_hca_vport_context *rep)
e53505a8
AS		 4687{
4688 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4689 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
4690 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
4691 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
85c7c014 4692 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
e53505a8
AS		 4693 u32 ret = 0;
4694
b02289b3
AK		 4695 if (rep->grh_required)
4696 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
4697
e53505a8 4698 if (ll == IB_LINK_LAYER_INFINIBAND)
b02289b3 4699 return ret | RDMA_CORE_PORT_IBA_IB;
e53505a8 4700
85c7c014 4701 if (raw_support)
b02289b3 4702 ret |= RDMA_CORE_PORT_RAW_PACKET;
72cd5717 4703
e53505a8 4704 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 4705 return ret;
e53505a8
AS		 4706
4707 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 4708 return ret;
e53505a8
AS		 4709
4710 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
4711 ret |= RDMA_CORE_PORT_IBA_ROCE;
4712
4713 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
4714 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
4715
4716 return ret;
4717}
4718
7738613e
IW		 4719static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
4720 struct ib_port_immutable *immutable)
4721{
4722 struct ib_port_attr attr;
ca5b91d6
OG		 4723 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4724 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
b02289b3 4725 struct mlx5_hca_vport_context rep = {0};
7738613e
IW		 4726 int err;
4727
c4550c63 4728 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 4729 if (err)
4730 return err;
4731
b02289b3
AK		 4732 if (ll == IB_LINK_LAYER_INFINIBAND) {
4733 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
4734 &rep);
4735 if (err)
4736 return err;
4737 }
4738
7738613e
IW		 4739 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4740 immutable->gid_tbl_len = attr.gid_tbl_len;
b02289b3 4741 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
ca5b91d6
OG		 4742 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
4743 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 4744
4745 return 0;
4746}
4747
8e6efa3a
MB		 4748static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
4749 struct ib_port_immutable *immutable)
4750{
4751 struct ib_port_attr attr;
4752 int err;
4753
4754 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4755
4756 err = ib_query_port(ibdev, port_num, &attr);
4757 if (err)
4758 return err;
4759
4760 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4761 immutable->gid_tbl_len = attr.gid_tbl_len;
4762 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4763
4764 return 0;
4765}
4766
9abb0d1b 4767static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 4768{
4769 struct mlx5_ib_dev *dev =
4770 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 4771 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
4772 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
4773 fw_rev_sub(dev->mdev));
c7342823
IW		 4774}
4775
45f95acd 4776static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 4777{
4778 struct mlx5_core_dev *mdev = dev->mdev;
4779 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
4780 MLX5_FLOW_NAMESPACE_LAG);
4781 struct mlx5_flow_table *ft;
4782 int err;
4783
4784 if (!ns || !mlx5_lag_is_active(mdev))
4785 return 0;
4786
4787 err = mlx5_cmd_create_vport_lag(mdev);
4788 if (err)
4789 return err;
4790
4791 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
4792 if (IS_ERR(ft)) {
4793 err = PTR_ERR(ft);
4794 goto err_destroy_vport_lag;
4795 }
4796
9a4ca38d 4797 dev->flow_db->lag_demux_ft = ft;
9ef9c640
AH		 4798 return 0;
4799
4800err_destroy_vport_lag:
4801 mlx5_cmd_destroy_vport_lag(mdev);
4802 return err;
4803}
4804
45f95acd 4805static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 4806{
4807 struct mlx5_core_dev *mdev = dev->mdev;
4808
9a4ca38d
MB		 4809 if (dev->flow_db->lag_demux_ft) {
4810 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
4811 dev->flow_db->lag_demux_ft = NULL;
9ef9c640
AH		 4812
4813 mlx5_cmd_destroy_vport_lag(mdev);
4814 }
4815}
4816
7fd8aefb 4817static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
d012f5d6
OG		 4818{
4819 int err;
4820
7fd8aefb
DJ		 4821 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
4822 err = register_netdevice_notifier(&dev->roce[port_num].nb);
d012f5d6 4823 if (err) {
7fd8aefb 4824 dev->roce[port_num].nb.notifier_call = NULL;
d012f5d6
OG		 4825 return err;
4826 }
4827
4828 return 0;
4829}
4830
7fd8aefb 4831static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5ec8c83e 4832{
7fd8aefb
DJ		 4833 if (dev->roce[port_num].nb.notifier_call) {
4834 unregister_netdevice_notifier(&dev->roce[port_num].nb);
4835 dev->roce[port_num].nb.notifier_call = NULL;
5ec8c83e
AH		 4836 }
4837}
4838
e3f1ed1f 4839static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 4840{
e53505a8
AS		 4841 int err;
4842
ca5b91d6
OG		 4843 if (MLX5_CAP_GEN(dev->mdev, roce)) {
4844 err = mlx5_nic_vport_enable_roce(dev->mdev);
4845 if (err)
8e6efa3a 4846 return err;
ca5b91d6 4847 }
e53505a8 4848
45f95acd 4849 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 4850 if (err)
4851 goto err_disable_roce;
4852
e53505a8
AS		 4853 return 0;
4854
9ef9c640 4855err_disable_roce:
ca5b91d6
OG		 4856 if (MLX5_CAP_GEN(dev->mdev, roce))
4857 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 4858
e53505a8 4859 return err;
fc24fc5e
AS		 4860}
4861
45f95acd 4862static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 4863{
45f95acd 4864 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 4865 if (MLX5_CAP_GEN(dev->mdev, roce))
4866 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 4867}
4868
e1f24a79 4869struct mlx5_ib_counter {
7c16f477
KH		 4870 const char *name;
4871 size_t offset;
4872};
4873
4874#define INIT_Q_COUNTER(_name) \
4875 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
4876
e1f24a79 4877static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 4878 INIT_Q_COUNTER(rx_write_requests),
4879 INIT_Q_COUNTER(rx_read_requests),
4880 INIT_Q_COUNTER(rx_atomic_requests),
4881 INIT_Q_COUNTER(out_of_buffer),
4882};
4883
e1f24a79 4884static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 4885 INIT_Q_COUNTER(out_of_sequence),
4886};
4887
e1f24a79 4888static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 4889 INIT_Q_COUNTER(duplicate_request),
4890 INIT_Q_COUNTER(rnr_nak_retry_err),
4891 INIT_Q_COUNTER(packet_seq_err),
4892 INIT_Q_COUNTER(implied_nak_seq_err),
4893 INIT_Q_COUNTER(local_ack_timeout_err),
4894};
4895
e1f24a79
PP		 4896#define INIT_CONG_COUNTER(_name) \
4897 { .name = #_name, .offset = \
4898 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
4899
4900static const struct mlx5_ib_counter cong_cnts[] = {
4901 INIT_CONG_COUNTER(rp_cnp_ignored),
4902 INIT_CONG_COUNTER(rp_cnp_handled),
4903 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
4904 INIT_CONG_COUNTER(np_cnp_sent),
4905};
4906
58dcb60a
PP		 4907static const struct mlx5_ib_counter extended_err_cnts[] = {
4908 INIT_Q_COUNTER(resp_local_length_error),
4909 INIT_Q_COUNTER(resp_cqe_error),
4910 INIT_Q_COUNTER(req_cqe_error),
4911 INIT_Q_COUNTER(req_remote_invalid_request),
4912 INIT_Q_COUNTER(req_remote_access_errors),
4913 INIT_Q_COUNTER(resp_remote_access_errors),
4914 INIT_Q_COUNTER(resp_cqe_flush_error),
4915 INIT_Q_COUNTER(req_cqe_flush_error),
4916};
4917
9f876f3d
TB		 4918#define INIT_EXT_PPCNT_COUNTER(_name) \
4919 { .name = #_name, .offset = \
4920 MLX5_BYTE_OFF(ppcnt_reg, \
4921 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
4922
4923static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
4924 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
4925};
4926
e1f24a79 4927static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a 4928{
aac4492e 4929 int i;
0837e86a 4930
7c16f477 4931 for (i = 0; i < dev->num_ports; i++) {
921c0f5b 4932 if (dev->port[i].cnts.set_id_valid)
aac4492e
DJ		 4933 mlx5_core_dealloc_q_counter(dev->mdev,
4934 dev->port[i].cnts.set_id);
e1f24a79
PP		 4935 kfree(dev->port[i].cnts.names);
4936 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 4937 }
4938}
4939
e1f24a79
PP		 4940static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
4941 struct mlx5_ib_counters *cnts)
7c16f477
KH		 4942{
4943 u32 num_counters;
4944
4945 num_counters = ARRAY_SIZE(basic_q_cnts);
4946
4947 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
4948 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
4949
4950 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
4951 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 4952
4953 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
4954 num_counters += ARRAY_SIZE(extended_err_cnts);
4955
e1f24a79 4956 cnts->num_q_counters = num_counters;
7c16f477 4957
e1f24a79
PP		 4958 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4959 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
4960 num_counters += ARRAY_SIZE(cong_cnts);
4961 }
9f876f3d
TB		 4962 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
4963 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
4964 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
4965 }
e1f24a79
PP		 4966 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
4967 if (!cnts->names)
7c16f477
KH		 4968 return -ENOMEM;
4969
e1f24a79
PP		 4970 cnts->offsets = kcalloc(num_counters,
4971 sizeof(cnts->offsets), GFP_KERNEL);
4972 if (!cnts->offsets)
7c16f477
KH		 4973 goto err_names;
4974
7c16f477
KH		 4975 return 0;
4976
4977err_names:
e1f24a79 4978 kfree(cnts->names);
aac4492e 4979 cnts->names = NULL;
7c16f477
KH		 4980 return -ENOMEM;
4981}
4982
e1f24a79
PP		 4983static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
4984 const char **names,
4985 size_t *offsets)
7c16f477
KH		 4986{
4987 int i;
4988 int j = 0;
4989
4990 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
4991 names[j] = basic_q_cnts[i].name;
4992 offsets[j] = basic_q_cnts[i].offset;
4993 }
4994
4995 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
4996 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
4997 names[j] = out_of_seq_q_cnts[i].name;
4998 offsets[j] = out_of_seq_q_cnts[i].offset;
4999 }
5000 }
5001
5002 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
5003 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
5004 names[j] = retrans_q_cnts[i].name;
5005 offsets[j] = retrans_q_cnts[i].offset;
5006 }
5007 }
e1f24a79 5008
58dcb60a
PP		 5009 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
5010 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
5011 names[j] = extended_err_cnts[i].name;
5012 offsets[j] = extended_err_cnts[i].offset;
5013 }
5014 }
5015
e1f24a79
PP		 5016 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5017 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
5018 names[j] = cong_cnts[i].name;
5019 offsets[j] = cong_cnts[i].offset;
5020 }
5021 }
9f876f3d
TB		 5022
5023 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5024 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
5025 names[j] = ext_ppcnt_cnts[i].name;
5026 offsets[j] = ext_ppcnt_cnts[i].offset;
5027 }
5028 }
0837e86a
MB		 5029}
5030
e1f24a79 5031static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a 5032{
aac4492e 5033 int err = 0;
0837e86a 5034 int i;
0837e86a
MB		 5035
5036 for (i = 0; i < dev->num_ports; i++) {
aac4492e
DJ		 5037 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
5038 if (err)
5039 goto err_alloc;
5040
5041 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
5042 dev->port[i].cnts.offsets);
7c16f477 5043
aac4492e
DJ		 5044 err = mlx5_core_alloc_q_counter(dev->mdev,
5045 &dev->port[i].cnts.set_id);
5046 if (err) {
0837e86a
MB		 5047 mlx5_ib_warn(dev,
5048 "couldn't allocate queue counter for port %d, err %d\n",
aac4492e
DJ		 5049 i + 1, err);
5050 goto err_alloc;
0837e86a 5051 }
aac4492e 5052 dev->port[i].cnts.set_id_valid = true;
0837e86a
MB		 5053 }
5054
5055 return 0;
5056
aac4492e
DJ		 5057err_alloc:
5058 mlx5_ib_dealloc_counters(dev);
5059 return err;
0837e86a
MB		 5060}
5061
0ad17a8f
MB		 5062static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
5063 u8 port_num)
5064{
7c16f477
KH		 5065 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5066 struct mlx5_ib_port *port = &dev->port[port_num - 1];
0ad17a8f
MB		 5067
5068 /* We support only per port stats */
5069 if (port_num == 0)
5070 return NULL;
5071
e1f24a79
PP		 5072 return rdma_alloc_hw_stats_struct(port->cnts.names,
5073 port->cnts.num_q_counters +
9f876f3d
TB		 5074 port->cnts.num_cong_counters +
5075 port->cnts.num_ext_ppcnt_counters,
0ad17a8f
MB		 5076 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5077}
5078
aac4492e 5079static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
e1f24a79
PP		 5080 struct mlx5_ib_port *port,
5081 struct rdma_hw_stats *stats)
0ad17a8f 5082{
0ad17a8f
MB		 5083 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
5084 void *out;
5085 __be32 val;
e1f24a79 5086 int ret, i;
0ad17a8f 5087
1b9a07ee 5088 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 5089 if (!out)
5090 return -ENOMEM;
5091
aac4492e 5092 ret = mlx5_core_query_q_counter(mdev,
e1f24a79 5093 port->cnts.set_id, 0,
0ad17a8f
MB		 5094 out, outlen);
5095 if (ret)
5096 goto free;
5097
e1f24a79
PP		 5098 for (i = 0; i < port->cnts.num_q_counters; i++) {
5099 val = *(__be32 *)(out + port->cnts.offsets[i]);
0ad17a8f
MB		 5100 stats->value[i] = (u64)be32_to_cpu(val);
5101 }
7c16f477 5102
0ad17a8f
MB		 5103free:
5104 kvfree(out);
e1f24a79
PP		 5105 return ret;
5106}
5107
9f876f3d
TB		 5108static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
5109 struct mlx5_ib_port *port,
5110 struct rdma_hw_stats *stats)
5111{
5112 int offset = port->cnts.num_q_counters + port->cnts.num_cong_counters;
5113 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
5114 int ret, i;
5115 void *out;
5116
5117 out = kvzalloc(sz, GFP_KERNEL);
5118 if (!out)
5119 return -ENOMEM;
5120
5121 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
5122 if (ret)
5123 goto free;
5124
5125 for (i = 0; i < port->cnts.num_ext_ppcnt_counters; i++) {
5126 stats->value[i + offset] =
5127 be64_to_cpup((__be64 *)(out +
5128 port->cnts.offsets[i + offset]));
5129 }
5130
5131free:
5132 kvfree(out);
5133 return ret;
5134}
5135
e1f24a79
PP		 5136static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
5137 struct rdma_hw_stats *stats,
5138 u8 port_num, int index)
5139{
5140 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5141 struct mlx5_ib_port *port = &dev->port[port_num - 1];
aac4492e 5142 struct mlx5_core_dev *mdev;
e1f24a79 5143 int ret, num_counters;
aac4492e 5144 u8 mdev_port_num;
e1f24a79
PP		 5145
5146 if (!stats)
5147 return -EINVAL;
5148
9f876f3d
TB		 5149 num_counters = port->cnts.num_q_counters +
5150 port->cnts.num_cong_counters +
5151 port->cnts.num_ext_ppcnt_counters;
aac4492e
DJ		 5152
5153 /* q_counters are per IB device, query the master mdev */
5154 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
e1f24a79
PP		 5155 if (ret)
5156 return ret;
e1f24a79 5157
9f876f3d
TB		 5158 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5159 ret = mlx5_ib_query_ext_ppcnt_counters(dev, port, stats);
5160 if (ret)
5161 return ret;
5162 }
5163
e1f24a79 5164 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
aac4492e
DJ		 5165 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
5166 &mdev_port_num);
5167 if (!mdev) {
5168 /* If port is not affiliated yet, its in down state
5169 * which doesn't have any counters yet, so it would be
5170 * zero. So no need to read from the HCA.
5171 */
5172 goto done;
5173 }
71a0ff65
MD		 5174 ret = mlx5_lag_query_cong_counters(dev->mdev,
5175 stats->value +
5176 port->cnts.num_q_counters,
5177 port->cnts.num_cong_counters,
5178 port->cnts.offsets +
5179 port->cnts.num_q_counters);
aac4492e
DJ		 5180
5181 mlx5_ib_put_native_port_mdev(dev, port_num);
e1f24a79
PP		 5182 if (ret)
5183 return ret;
e1f24a79
PP		 5184 }
5185
aac4492e 5186done:
e1f24a79 5187 return num_counters;
0ad17a8f
MB		 5188}
5189
693dfd5a
ES		 5190static struct net_device*
5191mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
5192 u8 port_num,
5193 enum rdma_netdev_t type,
5194 const char *name,
5195 unsigned char name_assign_type,
5196 void (*setup)(struct net_device *))
5197{
8e959601 5198 struct net_device *netdev;
8e959601 5199
693dfd5a
ES		 5200 if (type != RDMA_NETDEV_IPOIB)
5201 return ERR_PTR(-EOPNOTSUPP);
5202
8e959601
NV		 5203 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
5204 name, setup);
8e959601 5205 return netdev;
693dfd5a
ES		 5206}
5207
fe248c3a
MG		 5208static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
5209{
5210 if (!dev->delay_drop.dbg)
5211 return;
5212 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
5213 kfree(dev->delay_drop.dbg);
5214 dev->delay_drop.dbg = NULL;
5215}
5216
03404e8a
MG		 5217static void cancel_delay_drop(struct mlx5_ib_dev *dev)
5218{
5219 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5220 return;
5221
5222 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 5223 delay_drop_debugfs_cleanup(dev);
5224}
5225
5226static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5227 size_t count, loff_t *pos)
5228{
5229 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5230 char lbuf[20];
5231 int len;
5232
5233 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5234 return simple_read_from_buffer(buf, count, pos, lbuf, len);
5235}
5236
5237static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5238 size_t count, loff_t *pos)
5239{
5240 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5241 u32 timeout;
5242 u32 var;
5243
5244 if (kstrtouint_from_user(buf, count, 0, &var))
5245 return -EFAULT;
5246
5247 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5248 1000);
5249 if (timeout != var)
5250 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5251 timeout);
5252
5253 delay_drop->timeout = timeout;
5254
5255 return count;
5256}
5257
5258static const struct file_operations fops_delay_drop_timeout = {
5259 .owner = THIS_MODULE,
5260 .open = simple_open,
5261 .write = delay_drop_timeout_write,
5262 .read = delay_drop_timeout_read,
5263};
5264
5265static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5266{
5267 struct mlx5_ib_dbg_delay_drop *dbg;
5268
5269 if (!mlx5_debugfs_root)
5270 return 0;
5271
5272 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
5273 if (!dbg)
5274 return -ENOMEM;
5275
cbafad87
SM		 5276 dev->delay_drop.dbg = dbg;
5277
fe248c3a
MG		 5278 dbg->dir_debugfs =
5279 debugfs_create_dir("delay_drop",
5280 dev->mdev->priv.dbg_root);
5281 if (!dbg->dir_debugfs)
cbafad87 5282 goto out_debugfs;
fe248c3a
MG		 5283
5284 dbg->events_cnt_debugfs =
5285 debugfs_create_atomic_t("num_timeout_events", 0400,
5286 dbg->dir_debugfs,
5287 &dev->delay_drop.events_cnt);
5288 if (!dbg->events_cnt_debugfs)
5289 goto out_debugfs;
5290
5291 dbg->rqs_cnt_debugfs =
5292 debugfs_create_atomic_t("num_rqs", 0400,
5293 dbg->dir_debugfs,
5294 &dev->delay_drop.rqs_cnt);
5295 if (!dbg->rqs_cnt_debugfs)
5296 goto out_debugfs;
5297
5298 dbg->timeout_debugfs =
5299 debugfs_create_file("timeout", 0600,
5300 dbg->dir_debugfs,
5301 &dev->delay_drop,
5302 &fops_delay_drop_timeout);
5303 if (!dbg->timeout_debugfs)
5304 goto out_debugfs;
5305
5306 return 0;
5307
5308out_debugfs:
5309 delay_drop_debugfs_cleanup(dev);
5310 return -ENOMEM;
03404e8a
MG		 5311}
5312
5313static void init_delay_drop(struct mlx5_ib_dev *dev)
5314{
5315 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5316 return;
5317
5318 mutex_init(&dev->delay_drop.lock);
5319 dev->delay_drop.dev = dev;
5320 dev->delay_drop.activate = false;
5321 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5322 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 5323 atomic_set(&dev->delay_drop.rqs_cnt, 0);
5324 atomic_set(&dev->delay_drop.events_cnt, 0);
5325
5326 if (delay_drop_debugfs_init(dev))
5327 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
03404e8a
MG		 5328}
5329
84305d71
LR		 5330static const struct cpumask *
5331mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
40b24403
SG		 5332{
5333 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5334
6082d9c9 5335 return mlx5_get_vector_affinity_hint(dev->mdev, comp_vector);
40b24403
SG		 5336}
5337
32f69e4b
DJ		 5338/* The mlx5_ib_multiport_mutex should be held when calling this function */
5339static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5340 struct mlx5_ib_multiport_info *mpi)
5341{
5342 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5343 struct mlx5_ib_port *port = &ibdev->port[port_num];
5344 int comps;
5345 int err;
5346 int i;
5347
a9e546e7
PP		 5348 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5349
32f69e4b
DJ		 5350 spin_lock(&port->mp.mpi_lock);
5351 if (!mpi->ibdev) {
5352 spin_unlock(&port->mp.mpi_lock);
5353 return;
5354 }
5355 mpi->ibdev = NULL;
5356
5357 spin_unlock(&port->mp.mpi_lock);
5358 mlx5_remove_netdev_notifier(ibdev, port_num);
5359 spin_lock(&port->mp.mpi_lock);
5360
5361 comps = mpi->mdev_refcnt;
5362 if (comps) {
5363 mpi->unaffiliate = true;
5364 init_completion(&mpi->unref_comp);
5365 spin_unlock(&port->mp.mpi_lock);
5366
5367 for (i = 0; i < comps; i++)
5368 wait_for_completion(&mpi->unref_comp);
5369
5370 spin_lock(&port->mp.mpi_lock);
5371 mpi->unaffiliate = false;
5372 }
5373
5374 port->mp.mpi = NULL;
5375
5376 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5377
5378 spin_unlock(&port->mp.mpi_lock);
5379
5380 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5381
5382 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5383 /* Log an error, still needed to cleanup the pointers and add
5384 * it back to the list.
5385 */
5386 if (err)
5387 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5388 port_num + 1);
5389
5390 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
5391}
5392
5393/* The mlx5_ib_multiport_mutex should be held when calling this function */
5394static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5395 struct mlx5_ib_multiport_info *mpi)
5396{
5397 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5398 int err;
5399
5400 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5401 if (ibdev->port[port_num].mp.mpi) {
2577188e
QH		 5402 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
5403 port_num + 1);
32f69e4b
DJ		 5404 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5405 return false;
5406 }
5407
5408 ibdev->port[port_num].mp.mpi = mpi;
5409 mpi->ibdev = ibdev;
5410 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5411
5412 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5413 if (err)
5414 goto unbind;
5415
5416 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5417 if (err)
5418 goto unbind;
5419
5420 err = mlx5_add_netdev_notifier(ibdev, port_num);
5421 if (err) {
5422 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5423 port_num + 1);
5424 goto unbind;
5425 }
5426
a9e546e7
PP		 5427 err = mlx5_ib_init_cong_debugfs(ibdev, port_num);
5428 if (err)
5429 goto unbind;
5430
32f69e4b
DJ		 5431 return true;
5432
5433unbind:
5434 mlx5_ib_unbind_slave_port(ibdev, mpi);
5435 return false;
5436}
5437
5438static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5439{
5440 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5441 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5442 port_num + 1);
5443 struct mlx5_ib_multiport_info *mpi;
5444 int err;
5445 int i;
5446
5447 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5448 return 0;
5449
5450 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5451 &dev->sys_image_guid);
5452 if (err)
5453 return err;
5454
5455 err = mlx5_nic_vport_enable_roce(dev->mdev);
5456 if (err)
5457 return err;
5458
5459 mutex_lock(&mlx5_ib_multiport_mutex);
5460 for (i = 0; i < dev->num_ports; i++) {
5461 bool bound = false;
5462
5463 /* build a stub multiport info struct for the native port. */
5464 if (i == port_num) {
5465 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5466 if (!mpi) {
5467 mutex_unlock(&mlx5_ib_multiport_mutex);
5468 mlx5_nic_vport_disable_roce(dev->mdev);
5469 return -ENOMEM;
5470 }
5471
5472 mpi->is_master = true;
5473 mpi->mdev = dev->mdev;
5474 mpi->sys_image_guid = dev->sys_image_guid;
5475 dev->port[i].mp.mpi = mpi;
5476 mpi->ibdev = dev;
5477 mpi = NULL;
5478 continue;
5479 }
5480
5481 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5482 list) {
5483 if (dev->sys_image_guid == mpi->sys_image_guid &&
5484 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5485 bound = mlx5_ib_bind_slave_port(dev, mpi);
5486 }
5487
5488 if (bound) {
5489 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
5490 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5491 list_del(&mpi->list);
5492 break;
5493 }
5494 }
5495 if (!bound) {
5496 get_port_caps(dev, i + 1);
5497 mlx5_ib_dbg(dev, "no free port found for port %d\n",
5498 i + 1);
5499 }
5500 }
5501
5502 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
5503 mutex_unlock(&mlx5_ib_multiport_mutex);
5504 return err;
5505}
5506
5507static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
5508{
5509 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5510 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5511 port_num + 1);
5512 int i;
5513
5514 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5515 return;
5516
5517 mutex_lock(&mlx5_ib_multiport_mutex);
5518 for (i = 0; i < dev->num_ports; i++) {
5519 if (dev->port[i].mp.mpi) {
5520 /* Destroy the native port stub */
5521 if (i == port_num) {
5522 kfree(dev->port[i].mp.mpi);
5523 dev->port[i].mp.mpi = NULL;
5524 } else {
5525 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
5526 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
5527 }
5528 }
5529 }
5530
5531 mlx5_ib_dbg(dev, "removing from devlist\n");
5532 list_del(&dev->ib_dev_list);
5533 mutex_unlock(&mlx5_ib_multiport_mutex);
5534
5535 mlx5_nic_vport_disable_roce(dev->mdev);
5536}
5537
9a119cd5
JG		 5538ADD_UVERBS_ATTRIBUTES_SIMPLE(
5539 mlx5_ib_dm,
5540 UVERBS_OBJECT_DM,
5541 UVERBS_METHOD_DM_ALLOC,
5542 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
5543 UVERBS_ATTR_TYPE(u64),
83bb4442 5544 UA_MANDATORY),
9a119cd5
JG		 5545 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
5546 UVERBS_ATTR_TYPE(u16),
83bb4442 5547 UA_MANDATORY));
9a119cd5
JG		 5548
5549ADD_UVERBS_ATTRIBUTES_SIMPLE(
5550 mlx5_ib_flow_action,
5551 UVERBS_OBJECT_FLOW_ACTION,
5552 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
bccd0622
JG		 5553 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
5554 enum mlx5_ib_uapi_flow_action_flags));
c6475a0b 5555
8c84660b
MB		 5556static int populate_specs_root(struct mlx5_ib_dev *dev)
5557{
7d96c9b1
JG		 5558 const struct uverbs_object_tree_def **trees = dev->driver_trees;
5559 size_t num_trees = 0;
8c84660b 5560
7d96c9b1
JG		 5561 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
5562 MLX5_ACCEL_IPSEC_CAP_DEVICE)
5563 trees[num_trees++] = &mlx5_ib_flow_action;
c6475a0b 5564
7d96c9b1
JG		 5565 if (MLX5_CAP_DEV_MEM(dev->mdev, memic))
5566 trees[num_trees++] = &mlx5_ib_dm;
24da0016 5567
c59450c4 5568 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
7d96c9b1
JG		 5569 MLX5_GENERAL_OBJ_TYPES_CAP_UCTX)
5570 trees[num_trees++] = mlx5_ib_get_devx_tree();
c59450c4 5571
7d96c9b1 5572 num_trees += mlx5_ib_get_flow_trees(trees + num_trees);
cb80fb18 5573
7d96c9b1
JG		 5574 WARN_ON(num_trees >= ARRAY_SIZE(dev->driver_trees));
5575 trees[num_trees] = NULL;
5576 dev->ib_dev.driver_specs = trees;
8c84660b 5577
7d96c9b1 5578 return 0;
8c84660b
MB		 5579}
5580
1a1e03dc
RS		 5581static int mlx5_ib_read_counters(struct ib_counters *counters,
5582 struct ib_counters_read_attr *read_attr,
5583 struct uverbs_attr_bundle *attrs)
5584{
5585 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5586 struct mlx5_read_counters_attr mread_attr = {};
5587 struct mlx5_ib_flow_counters_desc *desc;
5588 int ret, i;
5589
5590 mutex_lock(&mcounters->mcntrs_mutex);
5591 if (mcounters->cntrs_max_index > read_attr->ncounters) {
5592 ret = -EINVAL;
5593 goto err_bound;
5594 }
5595
5596 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
5597 GFP_KERNEL);
5598 if (!mread_attr.out) {
5599 ret = -ENOMEM;
5600 goto err_bound;
5601 }
5602
5603 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
5604 mread_attr.flags = read_attr->flags;
5605 ret = mcounters->read_counters(counters->device, &mread_attr);
5606 if (ret)
5607 goto err_read;
5608
5609 /* do the pass over the counters data array to assign according to the
5610 * descriptions and indexing pairs
5611 */
5612 desc = mcounters->counters_data;
5613 for (i = 0; i < mcounters->ncounters; i++)
5614 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
5615
5616err_read:
5617 kfree(mread_attr.out);
5618err_bound:
5619 mutex_unlock(&mcounters->mcntrs_mutex);
5620 return ret;
5621}
5622
b29e2a13
RS		 5623static int mlx5_ib_destroy_counters(struct ib_counters *counters)
5624{
5625 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5626
3b3233fb
RS		 5627 counters_clear_description(counters);
5628 if (mcounters->hw_cntrs_hndl)
5629 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
5630 mcounters->hw_cntrs_hndl);
5631
b29e2a13
RS		 5632 kfree(mcounters);
5633
5634 return 0;
5635}
5636
5637static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
5638 struct uverbs_attr_bundle *attrs)
5639{
5640 struct mlx5_ib_mcounters *mcounters;
5641
5642 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
5643 if (!mcounters)
5644 return ERR_PTR(-ENOMEM);
5645
3b3233fb
RS		 5646 mutex_init(&mcounters->mcntrs_mutex);
5647
b29e2a13
RS		 5648 return &mcounters->ibcntrs;
5649}
5650
b5ca15ad 5651void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
e126ba97 5652{
32f69e4b 5653 mlx5_ib_cleanup_multiport_master(dev);
3cc297db
MB		 5654#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5655 cleanup_srcu_struct(&dev->mr_srcu);
5656#endif
16c1975f
MB		 5657 kfree(dev->port);
5658}
5659
b5ca15ad 5660int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5661{
5662 struct mlx5_core_dev *mdev = dev->mdev;
4babcf97 5663 const char *name;
e126ba97 5664 int err;
32f69e4b 5665 int i;
e126ba97 5666
508562d6 5667 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
0837e86a
MB		 5668 GFP_KERNEL);
5669 if (!dev->port)
16c1975f 5670 return -ENOMEM;
0837e86a 5671
32f69e4b
DJ		 5672 for (i = 0; i < dev->num_ports; i++) {
5673 spin_lock_init(&dev->port[i].mp.mpi_lock);
5674 rwlock_init(&dev->roce[i].netdev_lock);
5675 }
5676
5677 err = mlx5_ib_init_multiport_master(dev);
e126ba97 5678 if (err)
0837e86a 5679 goto err_free_port;
e126ba97 5680
32f69e4b 5681 if (!mlx5_core_mp_enabled(mdev)) {
32f69e4b
DJ		 5682 for (i = 1; i <= dev->num_ports; i++) {
5683 err = get_port_caps(dev, i);
5684 if (err)
5685 break;
5686 }
5687 } else {
5688 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
5689 }
5690 if (err)
5691 goto err_mp;
5692
1b5daf11
MD		 5693 if (mlx5_use_mad_ifc(dev))
5694 get_ext_port_caps(dev);
e126ba97 5695
4babcf97
AH		 5696 if (!mlx5_lag_is_active(mdev))
5697 name = "mlx5_%d";
5698 else
5699 name = "mlx5_bond_%d";
5700
5701 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
e126ba97
EC		 5702 dev->ib_dev.owner = THIS_MODULE;
5703 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 5704 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
508562d6 5705 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 5706 dev->ib_dev.num_comp_vectors =
5707 dev->mdev->priv.eq_table.num_comp_vectors;
9b0c289e 5708 dev->ib_dev.dev.parent = &mdev->pdev->dev;
e126ba97 5709
3cc297db
MB		 5710 mutex_init(&dev->cap_mask_mutex);
5711 INIT_LIST_HEAD(&dev->qp_list);
5712 spin_lock_init(&dev->reset_flow_resource_lock);
5713
24da0016
AL		 5714 spin_lock_init(&dev->memic.memic_lock);
5715 dev->memic.dev = mdev;
5716
3cc297db
MB		 5717#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5718 err = init_srcu_struct(&dev->mr_srcu);
5719 if (err)
5720 goto err_free_port;
5721#endif
5722
16c1975f 5723 return 0;
32f69e4b
DJ		 5724err_mp:
5725 mlx5_ib_cleanup_multiport_master(dev);
16c1975f
MB		 5726
5727err_free_port:
5728 kfree(dev->port);
5729
5730 return -ENOMEM;
5731}
5732
9a4ca38d
MB		 5733static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
5734{
5735 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
5736
5737 if (!dev->flow_db)
5738 return -ENOMEM;
5739
5740 mutex_init(&dev->flow_db->lock);
5741
5742 return 0;
5743}
5744
b5ca15ad
MB		 5745int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev)
5746{
5747 struct mlx5_ib_dev *nic_dev;
5748
5749 nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch);
5750
5751 if (!nic_dev)
5752 return -EINVAL;
5753
5754 dev->flow_db = nic_dev->flow_db;
5755
5756 return 0;
5757}
5758
9a4ca38d
MB		 5759static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
5760{
5761 kfree(dev->flow_db);
5762}
5763
b5ca15ad 5764int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5765{
5766 struct mlx5_core_dev *mdev = dev->mdev;
16c1975f
MB		 5767 int err;
5768
e126ba97
EC		 5769 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
5770 dev->ib_dev.uverbs_cmd_mask =
5771 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
5772 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
5773 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
5774 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
5775 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 5776 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
5777 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 5778 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 5779 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 5780 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
5781 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
5782 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
5783 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
5784 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
5785 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
5786 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
5787 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
5788 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
5789 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
5790 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
5791 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
5792 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
5793 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
5794 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
5795 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
5796 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 5797 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 5798 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
5799 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349 5800 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
b0e9df6d
YC		 5801 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
5802 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
e126ba97
EC		 5803
5804 dev->ib_dev.query_device = mlx5_ib_query_device;
ebd61f68 5805 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
e126ba97 5806 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 5807 dev->ib_dev.add_gid = mlx5_ib_add_gid;
5808 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 5809 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
5810 dev->ib_dev.modify_device = mlx5_ib_modify_device;
5811 dev->ib_dev.modify_port = mlx5_ib_modify_port;
5812 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
5813 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
5814 dev->ib_dev.mmap = mlx5_ib_mmap;
5815 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
5816 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
5817 dev->ib_dev.create_ah = mlx5_ib_create_ah;
5818 dev->ib_dev.query_ah = mlx5_ib_query_ah;
5819 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
5820 dev->ib_dev.create_srq = mlx5_ib_create_srq;
5821 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
5822 dev->ib_dev.query_srq = mlx5_ib_query_srq;
5823 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
5824 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
5825 dev->ib_dev.create_qp = mlx5_ib_create_qp;
5826 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
5827 dev->ib_dev.query_qp = mlx5_ib_query_qp;
5828 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
d0e84c0a
YH		 5829 dev->ib_dev.drain_sq = mlx5_ib_drain_sq;
5830 dev->ib_dev.drain_rq = mlx5_ib_drain_rq;
e126ba97
EC		 5831 dev->ib_dev.post_send = mlx5_ib_post_send;
5832 dev->ib_dev.post_recv = mlx5_ib_post_recv;
5833 dev->ib_dev.create_cq = mlx5_ib_create_cq;
5834 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
5835 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
5836 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
5837 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
5838 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
5839 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
5840 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 5841 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 5842 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
5843 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
5844 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
5845 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 5846 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 5847 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 5848 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
c7342823 5849 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
40b24403 5850 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
8e959601 5851 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
022d038a 5852 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
8e959601 5853
eff901d3
EC		 5854 if (mlx5_core_is_pf(mdev)) {
5855 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
5856 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
5857 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
5858 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
5859 }
e126ba97 5860
7c2344c3
MG		 5861 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
5862
6e8484c5
MG		 5863 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
5864
d2370e0a
MB		 5865 if (MLX5_CAP_GEN(mdev, imaicl)) {
5866 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
5867 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
5868 dev->ib_dev.uverbs_cmd_mask |=
5869 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
5870 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
5871 }
5872
938fe83c 5873 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 5874 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
5875 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
5876 dev->ib_dev.uverbs_cmd_mask |=
5877 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
5878 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
5879 }
5880
24da0016
AL		 5881 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
5882 dev->ib_dev.alloc_dm = mlx5_ib_alloc_dm;
5883 dev->ib_dev.dealloc_dm = mlx5_ib_dealloc_dm;
6c29f57e 5884 dev->ib_dev.reg_dm_mr = mlx5_ib_reg_dm_mr;
24da0016
AL		 5885 }
5886
81e30880
YH		 5887 dev->ib_dev.create_flow = mlx5_ib_create_flow;
5888 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
5889 dev->ib_dev.uverbs_ex_cmd_mask |=
5890 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
5891 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
c6475a0b
AY		 5892 dev->ib_dev.create_flow_action_esp = mlx5_ib_create_flow_action_esp;
5893 dev->ib_dev.destroy_flow_action = mlx5_ib_destroy_flow_action;
349705c1 5894 dev->ib_dev.modify_flow_action_esp = mlx5_ib_modify_flow_action_esp;
0ede73bc 5895 dev->ib_dev.driver_id = RDMA_DRIVER_MLX5;
b29e2a13
RS		 5896 dev->ib_dev.create_counters = mlx5_ib_create_counters;
5897 dev->ib_dev.destroy_counters = mlx5_ib_destroy_counters;
1a1e03dc 5898 dev->ib_dev.read_counters = mlx5_ib_read_counters;
81e30880 5899
e126ba97
EC		 5900 err = init_node_data(dev);
5901 if (err)
16c1975f 5902 return err;
e126ba97 5903
c8b89924 5904 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
e7996a9a
JG		 5905 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
5906 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
a560f1d9 5907 mutex_init(&dev->lb.mutex);
c8b89924 5908
16c1975f
MB		 5909 return 0;
5910}
5911
8e6efa3a
MB		 5912static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
5913{
5914 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
5915 dev->ib_dev.query_port = mlx5_ib_query_port;
5916
5917 return 0;
5918}
5919
b5ca15ad 5920int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
8e6efa3a
MB		 5921{
5922 dev->ib_dev.get_port_immutable = mlx5_port_rep_immutable;
5923 dev->ib_dev.query_port = mlx5_ib_rep_query_port;
5924
5925 return 0;
5926}
5927
e3f1ed1f 5928static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
8e6efa3a 5929{
e3f1ed1f 5930 u8 port_num;
8e6efa3a
MB		 5931 int i;
5932
5933 for (i = 0; i < dev->num_ports; i++) {
5934 dev->roce[i].dev = dev;
5935 dev->roce[i].native_port_num = i + 1;
5936 dev->roce[i].last_port_state = IB_PORT_DOWN;
5937 }
5938
5939 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
5940 dev->ib_dev.create_wq = mlx5_ib_create_wq;
5941 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
5942 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
5943 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
5944 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
5945
5946 dev->ib_dev.uverbs_ex_cmd_mask |=
5947 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
5948 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
5949 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
5950 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
5951 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
5952
e3f1ed1f
LR		 5953 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5954
8e6efa3a
MB		 5955 return mlx5_add_netdev_notifier(dev, port_num);
5956}
5957
5958static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
5959{
5960 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5961
5962 mlx5_remove_netdev_notifier(dev, port_num);
5963}
5964
5965int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
5966{
5967 struct mlx5_core_dev *mdev = dev->mdev;
5968 enum rdma_link_layer ll;
5969 int port_type_cap;
5970 int err = 0;
8e6efa3a 5971
8e6efa3a
MB		 5972 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5973 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5974
5975 if (ll == IB_LINK_LAYER_ETHERNET)
e3f1ed1f 5976 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 5977
5978 return err;
5979}
5980
5981void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
5982{
5983 mlx5_ib_stage_common_roce_cleanup(dev);
5984}
5985
16c1975f
MB		 5986static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
5987{
5988 struct mlx5_core_dev *mdev = dev->mdev;
5989 enum rdma_link_layer ll;
5990 int port_type_cap;
5991 int err;
5992
5993 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5994 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5995
fc24fc5e 5996 if (ll == IB_LINK_LAYER_ETHERNET) {
e3f1ed1f 5997 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 5998 if (err)
5999 return err;
7fd8aefb 6000
e3f1ed1f 6001 err = mlx5_enable_eth(dev);
fc24fc5e 6002 if (err)
8e6efa3a 6003 goto cleanup;
fc24fc5e
AS		 6004 }
6005
16c1975f 6006 return 0;
8e6efa3a
MB		 6007cleanup:
6008 mlx5_ib_stage_common_roce_cleanup(dev);
6009
6010 return err;
16c1975f 6011}
e126ba97 6012
16c1975f
MB		 6013static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
6014{
6015 struct mlx5_core_dev *mdev = dev->mdev;
6016 enum rdma_link_layer ll;
6017 int port_type_cap;
e126ba97 6018
16c1975f
MB		 6019 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6020 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6021
6022 if (ll == IB_LINK_LAYER_ETHERNET) {
6023 mlx5_disable_eth(dev);
8e6efa3a 6024 mlx5_ib_stage_common_roce_cleanup(dev);
45bded2c 6025 }
16c1975f 6026}
6aec21f6 6027
b5ca15ad 6028int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6029{
6030 return create_dev_resources(&dev->devr);
6031}
6032
b5ca15ad 6033void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6034{
6035 destroy_dev_resources(&dev->devr);
6036}
6037
6038static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
6039{
07321b3c
MB		 6040 mlx5_ib_internal_fill_odp_caps(dev);
6041
16c1975f
MB		 6042 return mlx5_ib_odp_init_one(dev);
6043}
4a2da0b8 6044
b5ca15ad 6045int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
16c1975f 6046{
5e1e7612
MB		 6047 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
6048 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
6049 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
6050
6051 return mlx5_ib_alloc_counters(dev);
6052 }
16c1975f
MB		 6053
6054 return 0;
6055}
6056
b5ca15ad 6057void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6058{
6059 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
6060 mlx5_ib_dealloc_counters(dev);
6061}
6062
6063static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
6064{
a9e546e7
PP		 6065 return mlx5_ib_init_cong_debugfs(dev,
6066 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 6067}
6068
6069static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
6070{
a9e546e7
PP		 6071 mlx5_ib_cleanup_cong_debugfs(dev,
6072 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 6073}
6074
6075static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
6076{
5fe9dec0 6077 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
444261ca 6078 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
16c1975f
MB		 6079}
6080
6081static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
6082{
6083 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
6084}
6085
b5ca15ad 6086int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6087{
6088 int err;
5fe9dec0
EC		 6089
6090 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
6091 if (err)
16c1975f 6092 return err;
5fe9dec0
EC		 6093
6094 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
6095 if (err)
16c1975f 6096 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5fe9dec0 6097
16c1975f
MB		 6098 return err;
6099}
0837e86a 6100
b5ca15ad 6101void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6102{
6103 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6104 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
6105}
e126ba97 6106
8c84660b
MB		 6107static int mlx5_ib_stage_populate_specs(struct mlx5_ib_dev *dev)
6108{
6109 return populate_specs_root(dev);
6110}
6111
b5ca15ad 6112int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6113{
6114 return ib_register_device(&dev->ib_dev, NULL);
6115}
6116
03fe2deb 6117void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
16c1975f 6118{
42cea83f 6119 destroy_umrc_res(dev);
16c1975f
MB		 6120}
6121
03fe2deb 6122void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
16c1975f 6123{
42cea83f 6124 ib_unregister_device(&dev->ib_dev);
16c1975f
MB		 6125}
6126
03fe2deb 6127int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
16c1975f 6128{
42cea83f 6129 return create_umr_res(dev);
16c1975f
MB		 6130}
6131
6132static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
6133{
03404e8a
MG		 6134 init_delay_drop(dev);
6135
16c1975f
MB		 6136 return 0;
6137}
6138
6139static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
6140{
6141 cancel_delay_drop(dev);
6142}
6143
b5ca15ad 6144int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6145{
6146 int err;
6147 int i;
6148
e126ba97 6149 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 6150 err = device_create_file(&dev->ib_dev.dev,
6151 mlx5_class_attributes[i]);
6152 if (err)
16c1975f 6153 return err;
e126ba97
EC		 6154 }
6155
16c1975f
MB		 6156 return 0;
6157}
6158
fc385b7a
MB		 6159static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev *dev)
6160{
6161 mlx5_ib_register_vport_reps(dev);
6162
6163 return 0;
6164}
6165
6166static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev *dev)
6167{
6168 mlx5_ib_unregister_vport_reps(dev);
6169}
6170
b5ca15ad
MB		 6171void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
6172 const struct mlx5_ib_profile *profile,
6173 int stage)
16c1975f
MB		 6174{
6175 /* Number of stages to cleanup */
6176 while (stage) {
6177 stage--;
6178 if (profile->stage[stage].cleanup)
6179 profile->stage[stage].cleanup(dev);
6180 }
e126ba97 6181
16c1975f
MB		 6182 ib_dealloc_device((struct ib_device *)dev);
6183}
e126ba97 6184
b5ca15ad
MB		 6185void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
6186 const struct mlx5_ib_profile *profile)
16c1975f 6187{
16c1975f
MB		 6188 int err;
6189 int i;
e126ba97 6190
16c1975f 6191 printk_once(KERN_INFO "%s", mlx5_version);
5fe9dec0 6192
16c1975f
MB		 6193 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
6194 if (profile->stage[i].init) {
6195 err = profile->stage[i].init(dev);
6196 if (err)
6197 goto err_out;
6198 }
6199 }
0837e86a 6200
16c1975f
MB		 6201 dev->profile = profile;
6202 dev->ib_active = true;
6aec21f6 6203
16c1975f 6204 return dev;
e126ba97 6205
16c1975f
MB		 6206err_out:
6207 __mlx5_ib_remove(dev, profile, i);
fc24fc5e 6208
16c1975f
MB		 6209 return NULL;
6210}
0837e86a 6211
16c1975f
MB		 6212static const struct mlx5_ib_profile pf_profile = {
6213 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6214 mlx5_ib_stage_init_init,
6215 mlx5_ib_stage_init_cleanup),
9a4ca38d
MB		 6216 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6217 mlx5_ib_stage_flow_db_init,
6218 mlx5_ib_stage_flow_db_cleanup),
16c1975f
MB		 6219 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6220 mlx5_ib_stage_caps_init,
6221 NULL),
8e6efa3a
MB		 6222 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6223 mlx5_ib_stage_non_default_cb,
6224 NULL),
16c1975f
MB		 6225 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6226 mlx5_ib_stage_roce_init,
6227 mlx5_ib_stage_roce_cleanup),
6228 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6229 mlx5_ib_stage_dev_res_init,
6230 mlx5_ib_stage_dev_res_cleanup),
6231 STAGE_CREATE(MLX5_IB_STAGE_ODP,
6232 mlx5_ib_stage_odp_init,
3cc297db 6233 NULL),
16c1975f
MB		 6234 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6235 mlx5_ib_stage_counters_init,
6236 mlx5_ib_stage_counters_cleanup),
6237 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
6238 mlx5_ib_stage_cong_debugfs_init,
6239 mlx5_ib_stage_cong_debugfs_cleanup),
6240 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6241 mlx5_ib_stage_uar_init,
6242 mlx5_ib_stage_uar_cleanup),
6243 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6244 mlx5_ib_stage_bfrag_init,
6245 mlx5_ib_stage_bfrag_cleanup),
42cea83f
MB		 6246 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6247 NULL,
6248 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
8c84660b
MB		 6249 STAGE_CREATE(MLX5_IB_STAGE_SPECS,
6250 mlx5_ib_stage_populate_specs,
7d96c9b1 6251 NULL),
16c1975f
MB		 6252 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6253 mlx5_ib_stage_ib_reg_init,
6254 mlx5_ib_stage_ib_reg_cleanup),
42cea83f
MB		 6255 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6256 mlx5_ib_stage_post_ib_reg_umr_init,
6257 NULL),
16c1975f
MB		 6258 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
6259 mlx5_ib_stage_delay_drop_init,
6260 mlx5_ib_stage_delay_drop_cleanup),
6261 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
6262 mlx5_ib_stage_class_attr_init,
6263 NULL),
16c1975f 6264};
e126ba97 6265
b5ca15ad
MB		 6266static const struct mlx5_ib_profile nic_rep_profile = {
6267 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6268 mlx5_ib_stage_init_init,
6269 mlx5_ib_stage_init_cleanup),
6270 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6271 mlx5_ib_stage_flow_db_init,
6272 mlx5_ib_stage_flow_db_cleanup),
6273 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6274 mlx5_ib_stage_caps_init,
6275 NULL),
6276 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6277 mlx5_ib_stage_rep_non_default_cb,
6278 NULL),
6279 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6280 mlx5_ib_stage_rep_roce_init,
6281 mlx5_ib_stage_rep_roce_cleanup),
6282 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6283 mlx5_ib_stage_dev_res_init,
6284 mlx5_ib_stage_dev_res_cleanup),
6285 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6286 mlx5_ib_stage_counters_init,
6287 mlx5_ib_stage_counters_cleanup),
6288 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6289 mlx5_ib_stage_uar_init,
6290 mlx5_ib_stage_uar_cleanup),
6291 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6292 mlx5_ib_stage_bfrag_init,
6293 mlx5_ib_stage_bfrag_cleanup),
03fe2deb
DM		 6294 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6295 NULL,
6296 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
8c84660b
MB		 6297 STAGE_CREATE(MLX5_IB_STAGE_SPECS,
6298 mlx5_ib_stage_populate_specs,
7d96c9b1 6299 NULL),
b5ca15ad
MB		 6300 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6301 mlx5_ib_stage_ib_reg_init,
6302 mlx5_ib_stage_ib_reg_cleanup),
03fe2deb
DM		 6303 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6304 mlx5_ib_stage_post_ib_reg_umr_init,
6305 NULL),
b5ca15ad
MB		 6306 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
6307 mlx5_ib_stage_class_attr_init,
6308 NULL),
6309 STAGE_CREATE(MLX5_IB_STAGE_REP_REG,
6310 mlx5_ib_stage_rep_reg_init,
6311 mlx5_ib_stage_rep_reg_cleanup),
6312};
6313
e3f1ed1f 6314static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
32f69e4b
DJ		 6315{
6316 struct mlx5_ib_multiport_info *mpi;
6317 struct mlx5_ib_dev *dev;
6318 bool bound = false;
6319 int err;
6320
6321 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6322 if (!mpi)
6323 return NULL;
6324
6325 mpi->mdev = mdev;
6326
6327 err = mlx5_query_nic_vport_system_image_guid(mdev,
6328 &mpi->sys_image_guid);
6329 if (err) {
6330 kfree(mpi);
6331 return NULL;
6332 }
6333
6334 mutex_lock(&mlx5_ib_multiport_mutex);
6335 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
6336 if (dev->sys_image_guid == mpi->sys_image_guid)
6337 bound = mlx5_ib_bind_slave_port(dev, mpi);
6338
6339 if (bound) {
6340 rdma_roce_rescan_device(&dev->ib_dev);
6341 break;
6342 }
6343 }
6344
6345 if (!bound) {
6346 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
6347 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
32f69e4b
DJ		 6348 }
6349 mutex_unlock(&mlx5_ib_multiport_mutex);
6350
6351 return mpi;
6352}
6353
16c1975f
MB		 6354static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
6355{
32f69e4b 6356 enum rdma_link_layer ll;
b5ca15ad 6357 struct mlx5_ib_dev *dev;
32f69e4b
DJ		 6358 int port_type_cap;
6359
b5ca15ad
MB		 6360 printk_once(KERN_INFO "%s", mlx5_version);
6361
32f69e4b
DJ		 6362 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6363 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6364
e3f1ed1f
LR		 6365 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
6366 return mlx5_ib_add_slave_port(mdev);
32f69e4b 6367
b5ca15ad
MB		 6368 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
6369 if (!dev)
6370 return NULL;
6371
6372 dev->mdev = mdev;
6373 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
6374 MLX5_CAP_GEN(mdev, num_vhca_ports));
6375
aff2252a 6376 if (MLX5_ESWITCH_MANAGER(mdev) &&
b5ca15ad
MB		 6377 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
6378 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0);
6379
6380 return __mlx5_ib_add(dev, &nic_rep_profile);
6381 }
6382
6383 return __mlx5_ib_add(dev, &pf_profile);
e126ba97
EC		 6384}
6385
9603b61d 6386static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 6387{
32f69e4b
DJ		 6388 struct mlx5_ib_multiport_info *mpi;
6389 struct mlx5_ib_dev *dev;
6390
6391 if (mlx5_core_is_mp_slave(mdev)) {
6392 mpi = context;
6393 mutex_lock(&mlx5_ib_multiport_mutex);
6394 if (mpi->ibdev)
6395 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
6396 list_del(&mpi->list);
6397 mutex_unlock(&mlx5_ib_multiport_mutex);
6398 return;
6399 }
6aec21f6 6400
32f69e4b 6401 dev = context;
16c1975f 6402 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
e126ba97
EC		 6403}
6404
9603b61d
JM		 6405static struct mlx5_interface mlx5_ib_interface = {
6406 .add = mlx5_ib_add,
6407 .remove = mlx5_ib_remove,
6408 .event = mlx5_ib_event,
d9aaed83
AK		 6409#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
6410 .pfault = mlx5_ib_pfault,
6411#endif
64613d94 6412 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 6413};
6414
c44ef998
IL		 6415unsigned long mlx5_ib_get_xlt_emergency_page(void)
6416{
6417 mutex_lock(&xlt_emergency_page_mutex);
6418 return xlt_emergency_page;
6419}
6420
6421void mlx5_ib_put_xlt_emergency_page(void)
6422{
6423 mutex_unlock(&xlt_emergency_page_mutex);
6424}
6425
e126ba97
EC		 6426static int __init mlx5_ib_init(void)
6427{
6aec21f6
HE		 6428 int err;
6429
c44ef998
IL		 6430 xlt_emergency_page = __get_free_page(GFP_KERNEL);
6431 if (!xlt_emergency_page)
6432 return -ENOMEM;
6433
6434 mutex_init(&xlt_emergency_page_mutex);
6435
d69a24e0 6436 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
c44ef998
IL		 6437 if (!mlx5_ib_event_wq) {
6438 free_page(xlt_emergency_page);
d69a24e0 6439 return -ENOMEM;
c44ef998 6440 }
d69a24e0 6441
81713d37 6442 mlx5_ib_odp_init();
9603b61d 6443
6aec21f6 6444 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 6445
6aec21f6 6446 return err;
e126ba97
EC		 6447}
6448
6449static void __exit mlx5_ib_cleanup(void)
6450{
9603b61d 6451 mlx5_unregister_interface(&mlx5_ib_interface);
d69a24e0 6452 destroy_workqueue(mlx5_ib_event_wq);
c44ef998
IL		 6453 mutex_destroy(&xlt_emergency_page_mutex);
6454 free_page(xlt_emergency_page);
e126ba97
EC		 6455}
6456
6457module_init(mlx5_ib_init);
6458module_exit(mlx5_ib_cleanup);
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