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Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox...
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
24da0016 41#include <linux/bitmap.h>
37aa5c36
GL		 42#if defined(CONFIG_X86)
43#include <asm/pat.h>
44#endif
e126ba97 45#include <linux/sched.h>
6e84f315 46#include <linux/sched/mm.h>
0881e7bd 47#include <linux/sched/task.h>
7c2344c3 48#include <linux/delay.h>
e126ba97 49#include <rdma/ib_user_verbs.h>
3f89a643 50#include <rdma/ib_addr.h>
2811ba51 51#include <rdma/ib_cache.h>
ada68c31 52#include <linux/mlx5/port.h>
1b5daf11 53#include <linux/mlx5/vport.h>
72c7fe90 54#include <linux/mlx5/fs.h>
cecae747 55#include <linux/mlx5/eswitch.h>
7c2344c3 56#include <linux/list.h>
e126ba97
EC		 57#include <rdma/ib_smi.h>
58#include <rdma/ib_umem.h>
038d2ef8
MG		 59#include <linux/in.h>
60#include <linux/etherdevice.h>
e126ba97 61#include "mlx5_ib.h"
fc385b7a 62#include "ib_rep.h"
e1f24a79 63#include "cmd.h"
f3da6577 64#include "srq.h"
3346c487 65#include <linux/mlx5/fs_helpers.h>
c6475a0b 66#include <linux/mlx5/accel.h>
8c84660b 67#include <rdma/uverbs_std_types.h>
c6475a0b
AY		 68#include <rdma/mlx5_user_ioctl_verbs.h>
69#include <rdma/mlx5_user_ioctl_cmds.h>
8c84660b
MB		 70
71#define UVERBS_MODULE_NAME mlx5_ib
72#include <rdma/uverbs_named_ioctl.h>
e126ba97
EC		 73
74#define DRIVER_NAME "mlx5_ib"
b359911d 75#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 76
77MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
78MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
79MODULE_LICENSE("Dual BSD/GPL");
e126ba97 80
e126ba97
EC		 81static char mlx5_version[] =
82 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 83 DRIVER_VERSION "\n";
e126ba97 84
d69a24e0
DJ		 85struct mlx5_ib_event_work {
86 struct work_struct work;
df097a27
SM		 87 union {
88 struct mlx5_ib_dev *dev;
89 struct mlx5_ib_multiport_info *mpi;
90 };
91 bool is_slave;
134e9349 92 unsigned int event;
df097a27 93 void *param;
d69a24e0
DJ		 94};
95
da7525d2
EBE		 96enum {
97 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
98};
99
d69a24e0 100static struct workqueue_struct *mlx5_ib_event_wq;
32f69e4b
DJ		 101static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
102static LIST_HEAD(mlx5_ib_dev_list);
103/*
104 * This mutex should be held when accessing either of the above lists
105 */
106static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
107
c44ef998
IL		 108/* We can't use an array for xlt_emergency_page because dma_map_single
109 * doesn't work on kernel modules memory
110 */
111static unsigned long xlt_emergency_page;
112static struct mutex xlt_emergency_page_mutex;
113
32f69e4b
DJ		 114struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
115{
116 struct mlx5_ib_dev *dev;
117
118 mutex_lock(&mlx5_ib_multiport_mutex);
119 dev = mpi->ibdev;
120 mutex_unlock(&mlx5_ib_multiport_mutex);
121 return dev;
122}
123
1b5daf11 124static enum rdma_link_layer
ebd61f68 125mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 126{
ebd61f68 127 switch (port_type_cap) {
1b5daf11
MD		 128 case MLX5_CAP_PORT_TYPE_IB:
129 return IB_LINK_LAYER_INFINIBAND;
130 case MLX5_CAP_PORT_TYPE_ETH:
131 return IB_LINK_LAYER_ETHERNET;
132 default:
133 return IB_LINK_LAYER_UNSPECIFIED;
134 }
135}
136
ebd61f68
AS		 137static enum rdma_link_layer
138mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
139{
140 struct mlx5_ib_dev *dev = to_mdev(device);
141 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
142
143 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
144}
145
fd65f1b8
MS		 146static int get_port_state(struct ib_device *ibdev,
147 u8 port_num,
148 enum ib_port_state *state)
149{
150 struct ib_port_attr attr;
151 int ret;
152
153 memset(&attr, 0, sizeof(attr));
3023a1e9 154 ret = ibdev->ops.query_port(ibdev, port_num, &attr);
fd65f1b8
MS		 155 if (!ret)
156 *state = attr.state;
157 return ret;
158}
159
35b0aa67
MB		 160static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
161 struct net_device *ndev,
162 u8 *port_num)
163{
164 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
165 struct net_device *rep_ndev;
166 struct mlx5_ib_port *port;
167 int i;
168
169 for (i = 0; i < dev->num_ports; i++) {
170 port = &dev->port[i];
171 if (!port->rep)
172 continue;
173
174 read_lock(&port->roce.netdev_lock);
175 rep_ndev = mlx5_ib_get_rep_netdev(esw,
176 port->rep->vport);
177 if (rep_ndev == ndev) {
178 read_unlock(&port->roce.netdev_lock);
179 *port_num = i + 1;
180 return &port->roce;
181 }
182 read_unlock(&port->roce.netdev_lock);
183 }
184
185 return NULL;
186}
187
fc24fc5e
AS		 188static int mlx5_netdev_event(struct notifier_block *this,
189 unsigned long event, void *ptr)
190{
7fd8aefb 191 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
fc24fc5e 192 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
7fd8aefb
DJ		 193 u8 port_num = roce->native_port_num;
194 struct mlx5_core_dev *mdev;
195 struct mlx5_ib_dev *ibdev;
196
197 ibdev = roce->dev;
32f69e4b
DJ		 198 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
199 if (!mdev)
200 return NOTIFY_DONE;
fc24fc5e 201
5ec8c83e
AH		 202 switch (event) {
203 case NETDEV_REGISTER:
35b0aa67
MB		 204 /* Should already be registered during the load */
205 if (ibdev->is_rep)
206 break;
7fd8aefb 207 write_lock(&roce->netdev_lock);
dce45af5 208 if (ndev->dev.parent == mdev->device)
842a9c83 209 roce->netdev = ndev;
7fd8aefb 210 write_unlock(&roce->netdev_lock);
5ec8c83e 211 break;
fc24fc5e 212
842a9c83 213 case NETDEV_UNREGISTER:
35b0aa67 214 /* In case of reps, ib device goes away before the netdevs */
842a9c83
OG		 215 write_lock(&roce->netdev_lock);
216 if (roce->netdev == ndev)
217 roce->netdev = NULL;
218 write_unlock(&roce->netdev_lock);
219 break;
220
fd65f1b8 221 case NETDEV_CHANGE:
5ec8c83e 222 case NETDEV_UP:
88621dfe 223 case NETDEV_DOWN: {
7fd8aefb 224 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe
AH		 225 struct net_device *upper = NULL;
226
227 if (lag_ndev) {
228 upper = netdev_master_upper_dev_get(lag_ndev);
229 dev_put(lag_ndev);
230 }
231
35b0aa67
MB		 232 if (ibdev->is_rep)
233 roce = mlx5_get_rep_roce(ibdev, ndev, &port_num);
234 if (!roce)
235 return NOTIFY_DONE;
7fd8aefb 236 if ((upper == ndev || (!upper && ndev == roce->netdev))
88621dfe 237 && ibdev->ib_active) {
626bc02d 238 struct ib_event ibev = { };
fd65f1b8 239 enum ib_port_state port_state;
5ec8c83e 240
7fd8aefb
DJ		 241 if (get_port_state(&ibdev->ib_dev, port_num,
242 &port_state))
243 goto done;
fd65f1b8 244
7fd8aefb
DJ		 245 if (roce->last_port_state == port_state)
246 goto done;
fd65f1b8 247
7fd8aefb 248 roce->last_port_state = port_state;
5ec8c83e 249 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 250 if (port_state == IB_PORT_DOWN)
251 ibev.event = IB_EVENT_PORT_ERR;
252 else if (port_state == IB_PORT_ACTIVE)
253 ibev.event = IB_EVENT_PORT_ACTIVE;
254 else
7fd8aefb 255 goto done;
fd65f1b8 256
7fd8aefb 257 ibev.element.port_num = port_num;
5ec8c83e
AH		 258 ib_dispatch_event(&ibev);
259 }
260 break;
88621dfe 261 }
fc24fc5e 262
5ec8c83e
AH		 263 default:
264 break;
265 }
7fd8aefb 266done:
32f69e4b 267 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 268 return NOTIFY_DONE;
269}
270
271static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
272 u8 port_num)
273{
274 struct mlx5_ib_dev *ibdev = to_mdev(device);
275 struct net_device *ndev;
32f69e4b
DJ		 276 struct mlx5_core_dev *mdev;
277
278 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
279 if (!mdev)
280 return NULL;
fc24fc5e 281
32f69e4b 282 ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe 283 if (ndev)
32f69e4b 284 goto out;
88621dfe 285
fc24fc5e
AS		 286 /* Ensure ndev does not disappear before we invoke dev_hold()
287 */
95579e78
MB		 288 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock);
289 ndev = ibdev->port[port_num - 1].roce.netdev;
fc24fc5e
AS		 290 if (ndev)
291 dev_hold(ndev);
95579e78 292 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock);
fc24fc5e 293
32f69e4b
DJ		 294out:
295 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 296 return ndev;
297}
298
32f69e4b
DJ		 299struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
300 u8 ib_port_num,
301 u8 *native_port_num)
302{
303 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
304 ib_port_num);
305 struct mlx5_core_dev *mdev = NULL;
306 struct mlx5_ib_multiport_info *mpi;
307 struct mlx5_ib_port *port;
308
210b1f78
MB		 309 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
310 ll != IB_LINK_LAYER_ETHERNET) {
311 if (native_port_num)
312 *native_port_num = ib_port_num;
313 return ibdev->mdev;
314 }
315
32f69e4b
DJ		 316 if (native_port_num)
317 *native_port_num = 1;
318
32f69e4b
DJ		 319 port = &ibdev->port[ib_port_num - 1];
320 if (!port)
321 return NULL;
322
323 spin_lock(&port->mp.mpi_lock);
324 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
325 if (mpi && !mpi->unaffiliate) {
326 mdev = mpi->mdev;
327 /* If it's the master no need to refcount, it'll exist
328 * as long as the ib_dev exists.
329 */
330 if (!mpi->is_master)
331 mpi->mdev_refcnt++;
332 }
333 spin_unlock(&port->mp.mpi_lock);
334
335 return mdev;
336}
337
338void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
339{
340 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
341 port_num);
342 struct mlx5_ib_multiport_info *mpi;
343 struct mlx5_ib_port *port;
344
345 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
346 return;
347
348 port = &ibdev->port[port_num - 1];
349
350 spin_lock(&port->mp.mpi_lock);
351 mpi = ibdev->port[port_num - 1].mp.mpi;
352 if (mpi->is_master)
353 goto out;
354
355 mpi->mdev_refcnt--;
356 if (mpi->unaffiliate)
357 complete(&mpi->unref_comp);
358out:
359 spin_unlock(&port->mp.mpi_lock);
360}
361
08e8676f
AL		 362static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, u8 *active_speed,
363 u8 *active_width)
f1b65df5
NO		 364{
365 switch (eth_proto_oper) {
366 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
367 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
368 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
369 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
370 *active_width = IB_WIDTH_1X;
371 *active_speed = IB_SPEED_SDR;
372 break;
373 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
374 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
375 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
376 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
377 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
378 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
379 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
380 *active_width = IB_WIDTH_1X;
381 *active_speed = IB_SPEED_QDR;
382 break;
383 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
384 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
385 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
386 *active_width = IB_WIDTH_1X;
387 *active_speed = IB_SPEED_EDR;
388 break;
389 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
390 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
391 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
392 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
393 *active_width = IB_WIDTH_4X;
394 *active_speed = IB_SPEED_QDR;
395 break;
396 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
397 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
398 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
399 *active_width = IB_WIDTH_1X;
400 *active_speed = IB_SPEED_HDR;
401 break;
402 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
403 *active_width = IB_WIDTH_4X;
404 *active_speed = IB_SPEED_FDR;
405 break;
406 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
407 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
408 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
409 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
410 *active_width = IB_WIDTH_4X;
411 *active_speed = IB_SPEED_EDR;
412 break;
413 default:
414 return -EINVAL;
415 }
416
417 return 0;
418}
419
08e8676f
AL		 420static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed,
421 u8 *active_width)
422{
423 switch (eth_proto_oper) {
424 case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
425 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
426 *active_width = IB_WIDTH_1X;
427 *active_speed = IB_SPEED_SDR;
428 break;
429 case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
430 *active_width = IB_WIDTH_1X;
431 *active_speed = IB_SPEED_DDR;
432 break;
433 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
434 *active_width = IB_WIDTH_1X;
435 *active_speed = IB_SPEED_QDR;
436 break;
437 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
438 *active_width = IB_WIDTH_4X;
439 *active_speed = IB_SPEED_QDR;
440 break;
441 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
442 *active_width = IB_WIDTH_1X;
443 *active_speed = IB_SPEED_EDR;
444 break;
445 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
cd272875
AL		 446 *active_width = IB_WIDTH_2X;
447 *active_speed = IB_SPEED_EDR;
448 break;
08e8676f
AL		 449 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
450 *active_width = IB_WIDTH_1X;
451 *active_speed = IB_SPEED_HDR;
452 break;
cd272875
AL		 453 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
454 *active_width = IB_WIDTH_4X;
455 *active_speed = IB_SPEED_EDR;
456 break;
08e8676f
AL		 457 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
458 *active_width = IB_WIDTH_2X;
459 *active_speed = IB_SPEED_HDR;
460 break;
461 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
462 *active_width = IB_WIDTH_4X;
463 *active_speed = IB_SPEED_HDR;
464 break;
465 default:
466 return -EINVAL;
467 }
468
469 return 0;
470}
471
472static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
473 u8 *active_width, bool ext)
474{
475 return ext ?
476 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
477 active_width) :
478 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
479 active_width);
480}
481
095b0927
IT		 482static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
483 struct ib_port_attr *props)
3f89a643
AS		 484{
485 struct mlx5_ib_dev *dev = to_mdev(device);
bc4e12ff 486 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
da005f9f 487 struct mlx5_core_dev *mdev;
88621dfe 488 struct net_device *ndev, *upper;
3f89a643 489 enum ib_mtu ndev_ib_mtu;
b3cbd6f0 490 bool put_mdev = true;
c876a1b7 491 u16 qkey_viol_cntr;
f1b65df5 492 u32 eth_prot_oper;
b3cbd6f0 493 u8 mdev_port_num;
08e8676f 494 bool ext;
095b0927 495 int err;
3f89a643 496
b3cbd6f0
DJ		 497 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
498 if (!mdev) {
499 /* This means the port isn't affiliated yet. Get the
500 * info for the master port instead.
501 */
502 put_mdev = false;
503 mdev = dev->mdev;
504 mdev_port_num = 1;
505 port_num = 1;
506 }
507
f1b65df5
NO		 508 /* Possible bad flows are checked before filling out props so in case
509 * of an error it will still be zeroed out.
26628e2d 510 * Use native port in case of reps
50f22fd8 511 */
26628e2d
MB		 512 if (dev->is_rep)
513 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
514 1);
515 else
516 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
517 mdev_port_num);
095b0927 518 if (err)
b3cbd6f0 519 goto out;
08e8676f
AL		 520 ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet);
521 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
f1b65df5 522
7672ed33
HL		 523 props->active_width = IB_WIDTH_4X;
524 props->active_speed = IB_SPEED_QDR;
525
f1b65df5 526 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
08e8676f 527 &props->active_width, ext);
3f89a643 528
2f944c0f
JG		 529 props->port_cap_flags |= IB_PORT_CM_SUP;
530 props->ip_gids = true;
3f89a643
AS		 531
532 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
533 roce_address_table_size);
534 props->max_mtu = IB_MTU_4096;
535 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
536 props->pkey_tbl_len = 1;
537 props->state = IB_PORT_DOWN;
538 props->phys_state = 3;
539
b3cbd6f0 540 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
c876a1b7 541 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643 542
b3cbd6f0
DJ		 543 /* If this is a stub query for an unaffiliated port stop here */
544 if (!put_mdev)
545 goto out;
546
3f89a643
AS		 547 ndev = mlx5_ib_get_netdev(device, port_num);
548 if (!ndev)
b3cbd6f0 549 goto out;
3f89a643 550
7c34ec19 551 if (dev->lag_active) {
88621dfe
AH		 552 rcu_read_lock();
553 upper = netdev_master_upper_dev_get_rcu(ndev);
554 if (upper) {
555 dev_put(ndev);
556 ndev = upper;
557 dev_hold(ndev);
558 }
559 rcu_read_unlock();
560 }
561
3f89a643
AS		 562 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
563 props->state = IB_PORT_ACTIVE;
564 props->phys_state = 5;
565 }
566
567 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
568
569 dev_put(ndev);
570
571 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
b3cbd6f0
DJ		 572out:
573 if (put_mdev)
574 mlx5_ib_put_native_port_mdev(dev, port_num);
575 return err;
3f89a643
AS		 576}
577
095b0927
IT		 578static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
579 unsigned int index, const union ib_gid *gid,
580 const struct ib_gid_attr *attr)
3cca2606 581{
095b0927 582 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
a70c0739 583 u16 vlan_id = 0xffff;
095b0927
IT		 584 u8 roce_version = 0;
585 u8 roce_l3_type = 0;
095b0927 586 u8 mac[ETH_ALEN];
a70c0739 587 int ret;
095b0927
IT		 588
589 if (gid) {
590 gid_type = attr->gid_type;
a70c0739
PP		 591 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
592 if (ret)
593 return ret;
3cca2606
AS		 594 }
595
095b0927 596 switch (gid_type) {
3cca2606 597 case IB_GID_TYPE_IB:
095b0927 598 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 599 break;
600 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 601 roce_version = MLX5_ROCE_VERSION_2;
602 if (ipv6_addr_v4mapped((void *)gid))
603 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
604 else
605 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 606 break;
607
608 default:
095b0927 609 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 610 }
611
095b0927 612 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
cf34e1fe 613 roce_l3_type, gid->raw, mac,
a70c0739 614 vlan_id < VLAN_CFI_MASK, vlan_id,
cf34e1fe 615 port_num);
3cca2606
AS		 616}
617
f4df9a7c 618static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
3cca2606
AS		 619 __always_unused void **context)
620{
414448d2 621 return set_roce_addr(to_mdev(attr->device), attr->port_num,
f4df9a7c 622 attr->index, &attr->gid, attr);
3cca2606
AS		 623}
624
414448d2
PP		 625static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
626 __always_unused void **context)
3cca2606 627{
414448d2
PP		 628 return set_roce_addr(to_mdev(attr->device), attr->port_num,
629 attr->index, NULL, NULL);
3cca2606
AS		 630}
631
47ec3866
PP		 632__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
633 const struct ib_gid_attr *attr)
2811ba51 634{
47ec3866 635 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
2811ba51
AS		 636 return 0;
637
638 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
639}
640
1b5daf11
MD		 641static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
642{
7fae6655
NO		 643 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
644 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
645 return 0;
1b5daf11
MD		 646}
647
648enum {
649 MLX5_VPORT_ACCESS_METHOD_MAD,
650 MLX5_VPORT_ACCESS_METHOD_HCA,
651 MLX5_VPORT_ACCESS_METHOD_NIC,
652};
653
654static int mlx5_get_vport_access_method(struct ib_device *ibdev)
655{
656 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
657 return MLX5_VPORT_ACCESS_METHOD_MAD;
658
ebd61f68 659 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 660 IB_LINK_LAYER_ETHERNET)
661 return MLX5_VPORT_ACCESS_METHOD_NIC;
662
663 return MLX5_VPORT_ACCESS_METHOD_HCA;
664}
665
da7525d2 666static void get_atomic_caps(struct mlx5_ib_dev *dev,
776a3906 667 u8 atomic_size_qp,
da7525d2
EBE		 668 struct ib_device_attr *props)
669{
670 u8 tmp;
671 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
da7525d2 672 u8 atomic_req_8B_endianness_mode =
bd10838a 673 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 674
675 /* Check if HW supports 8 bytes standard atomic operations and capable
676 * of host endianness respond
677 */
678 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
679 if (((atomic_operations & tmp) == tmp) &&
680 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
681 (atomic_req_8B_endianness_mode)) {
682 props->atomic_cap = IB_ATOMIC_HCA;
683 } else {
684 props->atomic_cap = IB_ATOMIC_NONE;
685 }
686}
687
776a3906
MS		 688static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
689 struct ib_device_attr *props)
690{
691 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
692
693 get_atomic_caps(dev, atomic_size_qp, props);
694}
695
696static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
697 struct ib_device_attr *props)
698{
699 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
700
701 get_atomic_caps(dev, atomic_size_qp, props);
702}
703
704bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
705{
706 struct ib_device_attr props = {};
707
708 get_atomic_caps_dc(dev, &props);
709 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
710}
1b5daf11
MD		 711static int mlx5_query_system_image_guid(struct ib_device *ibdev,
712 __be64 *sys_image_guid)
713{
714 struct mlx5_ib_dev *dev = to_mdev(ibdev);
715 struct mlx5_core_dev *mdev = dev->mdev;
716 u64 tmp;
717 int err;
718
719 switch (mlx5_get_vport_access_method(ibdev)) {
720 case MLX5_VPORT_ACCESS_METHOD_MAD:
721 return mlx5_query_mad_ifc_system_image_guid(ibdev,
722 sys_image_guid);
723
724 case MLX5_VPORT_ACCESS_METHOD_HCA:
725 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 726 break;
727
728 case MLX5_VPORT_ACCESS_METHOD_NIC:
729 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
730 break;
1b5daf11
MD		 731
732 default:
733 return -EINVAL;
734 }
3f89a643
AS		 735
736 if (!err)
737 *sys_image_guid = cpu_to_be64(tmp);
738
739 return err;
740
1b5daf11
MD		 741}
742
743static int mlx5_query_max_pkeys(struct ib_device *ibdev,
744 u16 *max_pkeys)
745{
746 struct mlx5_ib_dev *dev = to_mdev(ibdev);
747 struct mlx5_core_dev *mdev = dev->mdev;
748
749 switch (mlx5_get_vport_access_method(ibdev)) {
750 case MLX5_VPORT_ACCESS_METHOD_MAD:
751 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
752
753 case MLX5_VPORT_ACCESS_METHOD_HCA:
754 case MLX5_VPORT_ACCESS_METHOD_NIC:
755 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
756 pkey_table_size));
757 return 0;
758
759 default:
760 return -EINVAL;
761 }
762}
763
764static int mlx5_query_vendor_id(struct ib_device *ibdev,
765 u32 *vendor_id)
766{
767 struct mlx5_ib_dev *dev = to_mdev(ibdev);
768
769 switch (mlx5_get_vport_access_method(ibdev)) {
770 case MLX5_VPORT_ACCESS_METHOD_MAD:
771 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
772
773 case MLX5_VPORT_ACCESS_METHOD_HCA:
774 case MLX5_VPORT_ACCESS_METHOD_NIC:
775 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
776
777 default:
778 return -EINVAL;
779 }
780}
781
782static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
783 __be64 *node_guid)
784{
785 u64 tmp;
786 int err;
787
788 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
789 case MLX5_VPORT_ACCESS_METHOD_MAD:
790 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
791
792 case MLX5_VPORT_ACCESS_METHOD_HCA:
793 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 794 break;
795
796 case MLX5_VPORT_ACCESS_METHOD_NIC:
797 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
798 break;
1b5daf11
MD		 799
800 default:
801 return -EINVAL;
802 }
3f89a643
AS		 803
804 if (!err)
805 *node_guid = cpu_to_be64(tmp);
806
807 return err;
1b5daf11
MD		 808}
809
810struct mlx5_reg_node_desc {
bd99fdea 811 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 812};
813
814static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
815{
816 struct mlx5_reg_node_desc in;
817
818 if (mlx5_use_mad_ifc(dev))
819 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
820
821 memset(&in, 0, sizeof(in));
822
823 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
824 sizeof(struct mlx5_reg_node_desc),
825 MLX5_REG_NODE_DESC, 0, 0);
826}
827
e126ba97 828static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 829 struct ib_device_attr *props,
830 struct ib_udata *uhw)
e126ba97
EC		 831{
832 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 833 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 834 int err = -ENOMEM;
288c01b7 835 int max_sq_desc;
e126ba97
EC		 836 int max_rq_sg;
837 int max_sq_sg;
e0238a6a 838 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
85c7c014 839 bool raw_support = !mlx5_core_mp_enabled(mdev);
402ca536
BW		 840 struct mlx5_ib_query_device_resp resp = {};
841 size_t resp_len;
842 u64 max_tso;
e126ba97 843
402ca536
BW		 844 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
845 if (uhw->outlen && uhw->outlen < resp_len)
846 return -EINVAL;
847 else
848 resp.response_length = resp_len;
849
850 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 851 return -EINVAL;
852
1b5daf11
MD		 853 memset(props, 0, sizeof(*props));
854 err = mlx5_query_system_image_guid(ibdev,
855 &props->sys_image_guid);
856 if (err)
857 return err;
e126ba97 858
1b5daf11 859 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 860 if (err)
1b5daf11 861 return err;
e126ba97 862
1b5daf11
MD		 863 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
864 if (err)
865 return err;
e126ba97 866
9603b61d
JM		 867 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
868 (fw_rev_min(dev->mdev) << 16) |
869 fw_rev_sub(dev->mdev);
e126ba97
EC		 870 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
871 IB_DEVICE_PORT_ACTIVE_EVENT |
872 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 873 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 874
875 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 876 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 877 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 878 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 879 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 880 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 881 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 882 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 883 if (MLX5_CAP_GEN(mdev, imaicl)) {
884 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
885 IB_DEVICE_MEM_WINDOW_TYPE_2B;
886 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 887 /* We support 'Gappy' memory registration too */
888 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 889 }
e126ba97 890 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 891 if (MLX5_CAP_GEN(mdev, sho)) {
c0a6cbb9 892 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER;
2dea9094
SG		 893 /* At this stage no support for signature handover */
894 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
895 IB_PROT_T10DIF_TYPE_2 |
896 IB_PROT_T10DIF_TYPE_3;
897 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
898 IB_GUARD_T10DIF_CSUM;
899 }
938fe83c 900 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 901 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 902
85c7c014 903 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
e8161334
NO		 904 if (MLX5_CAP_ETH(mdev, csum_cap)) {
905 /* Legacy bit to support old userspace libraries */
88115fe7 906 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 907 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
908 }
909
910 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
911 props->raw_packet_caps |=
912 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 913
402ca536
BW		 914 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
915 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
916 if (max_tso) {
917 resp.tso_caps.max_tso = 1 << max_tso;
918 resp.tso_caps.supported_qpts |=
919 1 << IB_QPT_RAW_PACKET;
920 resp.response_length += sizeof(resp.tso_caps);
921 }
922 }
31f69a82
YH		 923
924 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
925 resp.rss_caps.rx_hash_function =
926 MLX5_RX_HASH_FUNC_TOEPLITZ;
927 resp.rss_caps.rx_hash_fields_mask =
928 MLX5_RX_HASH_SRC_IPV4 |
929 MLX5_RX_HASH_DST_IPV4 |
930 MLX5_RX_HASH_SRC_IPV6 |
931 MLX5_RX_HASH_DST_IPV6 |
932 MLX5_RX_HASH_SRC_PORT_TCP |
933 MLX5_RX_HASH_DST_PORT_TCP |
934 MLX5_RX_HASH_SRC_PORT_UDP |
4e2b53a5
MG		 935 MLX5_RX_HASH_DST_PORT_UDP |
936 MLX5_RX_HASH_INNER;
2d93fc85
MB		 937 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
938 MLX5_ACCEL_IPSEC_CAP_DEVICE)
939 resp.rss_caps.rx_hash_fields_mask |=
940 MLX5_RX_HASH_IPSEC_SPI;
31f69a82
YH		 941 resp.response_length += sizeof(resp.rss_caps);
942 }
943 } else {
944 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
945 resp.response_length += sizeof(resp.tso_caps);
946 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
947 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 948 }
949
f0313965
ES		 950 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
951 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
952 props->device_cap_flags |= IB_DEVICE_UD_TSO;
953 }
954
03404e8a 955 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
85c7c014
DJ		 956 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
957 raw_support)
03404e8a
MG		 958 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
959
1d54f890
YH		 960 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
961 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
962 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
963
cff5a0f3 964 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
85c7c014
DJ		 965 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
966 raw_support) {
e8161334 967 /* Legacy bit to support old userspace libraries */
cff5a0f3 968 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 969 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
970 }
cff5a0f3 971
24da0016
AL		 972 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
973 props->max_dm_size =
974 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
975 }
976
da6d6ba3
MG		 977 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
978 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
979
b1383aa6
NO		 980 if (MLX5_CAP_GEN(mdev, end_pad))
981 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
982
1b5daf11
MD		 983 props->vendor_part_id = mdev->pdev->device;
984 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 985
986 props->max_mr_size = ~0ull;
e0238a6a 987 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 988 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
989 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
990 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
991 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 992 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
993 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
994 sizeof(struct mlx5_wqe_raddr_seg)) /
995 sizeof(struct mlx5_wqe_data_seg);
33023fb8
SW		 996 props->max_send_sge = max_sq_sg;
997 props->max_recv_sge = max_rq_sg;
986ef95e 998 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 999 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 1000 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 1001 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
1002 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
1003 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
1004 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
1005 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
1006 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
1007 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 1008 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 1009 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 1010 props->max_fast_reg_page_list_len =
1011 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
62e3c379
MG		 1012 props->max_pi_fast_reg_page_list_len =
1013 props->max_fast_reg_page_list_len / 2;
776a3906 1014 get_atomic_caps_qp(dev, props);
81bea28f 1015 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 1016 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
1017 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 1018 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1019 props->max_mcast_grp;
1020 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 1021 props->max_ah = INT_MAX;
7c60bcbb
MB		 1022 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
1023 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 1024
e502b8b0 1025 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
00815752 1026 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT)
e502b8b0
LR		 1027 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
1028 props->odp_caps = dev->odp_caps;
1029 }
8cdd312c 1030
051f2630
LR		 1031 if (MLX5_CAP_GEN(mdev, cd))
1032 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
1033
eff901d3
EC		 1034 if (!mlx5_core_is_pf(mdev))
1035 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
1036
31f69a82 1037 if (mlx5_ib_port_link_layer(ibdev, 1) ==
85c7c014 1038 IB_LINK_LAYER_ETHERNET && raw_support) {
31f69a82
YH		 1039 props->rss_caps.max_rwq_indirection_tables =
1040 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1041 props->rss_caps.max_rwq_indirection_table_size =
1042 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1043 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1044 props->max_wq_type_rq =
1045 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1046 }
1047
eb761894 1048 if (MLX5_CAP_GEN(mdev, tag_matching)) {
78b1beb0 1049 props->tm_caps.max_num_tags =
eb761894 1050 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
78b1beb0 1051 props->tm_caps.max_ops =
eb761894 1052 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
78b1beb0 1053 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
eb761894
AK		 1054 }
1055
89705e92
DG		 1056 if (MLX5_CAP_GEN(mdev, tag_matching) &&
1057 MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
1058 props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
1059 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1060 }
1061
87ab3f52
YC		 1062 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1063 props->cq_caps.max_cq_moderation_count =
1064 MLX5_MAX_CQ_COUNT;
1065 props->cq_caps.max_cq_moderation_period =
1066 MLX5_MAX_CQ_PERIOD;
1067 }
1068
7e43a2a5 1069 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
7e43a2a5 1070 resp.response_length += sizeof(resp.cqe_comp_caps);
572f46bf
YC		 1071
1072 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1073 resp.cqe_comp_caps.max_num =
1074 MLX5_CAP_GEN(dev->mdev,
1075 cqe_compression_max_num);
1076
1077 resp.cqe_comp_caps.supported_format =
1078 MLX5_IB_CQE_RES_FORMAT_HASH |
1079 MLX5_IB_CQE_RES_FORMAT_CSUM;
6f1006a4
YC		 1080
1081 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1082 resp.cqe_comp_caps.supported_format |=
1083 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
572f46bf 1084 }
7e43a2a5
BW		 1085 }
1086
85c7c014
DJ		 1087 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
1088 raw_support) {
d949167d
BW		 1089 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1090 MLX5_CAP_GEN(mdev, qos)) {
1091 resp.packet_pacing_caps.qp_rate_limit_max =
1092 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1093 resp.packet_pacing_caps.qp_rate_limit_min =
1094 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1095 resp.packet_pacing_caps.supported_qpts |=
1096 1 << IB_QPT_RAW_PACKET;
61147f39
BW		 1097 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1098 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1099 resp.packet_pacing_caps.cap_flags |=
1100 MLX5_IB_PP_SUPPORT_BURST;
d949167d
BW		 1101 }
1102 resp.response_length += sizeof(resp.packet_pacing_caps);
1103 }
1104
9f885201
LR		 1105 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
1106 uhw->outlen)) {
795b609c
BW		 1107 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1108 resp.mlx5_ib_support_multi_pkt_send_wqes =
1109 MLX5_IB_ALLOW_MPW;
050da902
BW		 1110
1111 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1112 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1113 MLX5_IB_SUPPORT_EMPW;
1114
9f885201
LR		 1115 resp.response_length +=
1116 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1117 }
1118
de57f2ad
GL		 1119 if (field_avail(typeof(resp), flags, uhw->outlen)) {
1120 resp.response_length += sizeof(resp.flags);
7a0c8f42 1121
de57f2ad
GL		 1122 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1123 resp.flags |=
1124 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
7a0c8f42
GL		 1125
1126 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1127 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
7e11b911
DG		 1128 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1129 resp.flags |=
1130 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
7249c8ea
GL		 1131
1132 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
de57f2ad 1133 }
9f885201 1134
96dc3fc5
NO		 1135 if (field_avail(typeof(resp), sw_parsing_caps,
1136 uhw->outlen)) {
1137 resp.response_length += sizeof(resp.sw_parsing_caps);
1138 if (MLX5_CAP_ETH(mdev, swp)) {
1139 resp.sw_parsing_caps.sw_parsing_offloads |=
1140 MLX5_IB_SW_PARSING;
1141
1142 if (MLX5_CAP_ETH(mdev, swp_csum))
1143 resp.sw_parsing_caps.sw_parsing_offloads |=
1144 MLX5_IB_SW_PARSING_CSUM;
1145
1146 if (MLX5_CAP_ETH(mdev, swp_lso))
1147 resp.sw_parsing_caps.sw_parsing_offloads |=
1148 MLX5_IB_SW_PARSING_LSO;
1149
1150 if (resp.sw_parsing_caps.sw_parsing_offloads)
1151 resp.sw_parsing_caps.supported_qpts =
1152 BIT(IB_QPT_RAW_PACKET);
1153 }
1154 }
1155
85c7c014
DJ		 1156 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1157 raw_support) {
b4f34597
NO		 1158 resp.response_length += sizeof(resp.striding_rq_caps);
1159 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1160 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1161 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1162 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1163 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1164 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1165 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1166 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1167 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1168 resp.striding_rq_caps.supported_qpts =
1169 BIT(IB_QPT_RAW_PACKET);
1170 }
1171 }
1172
f95ef6cb
MG		 1173 if (field_avail(typeof(resp), tunnel_offloads_caps,
1174 uhw->outlen)) {
1175 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1176 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1177 resp.tunnel_offloads_caps |=
1178 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1179 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1180 resp.tunnel_offloads_caps |=
1181 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1182 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1183 resp.tunnel_offloads_caps |=
1184 MLX5_IB_TUNNELED_OFFLOADS_GRE;
e818e255
AL		 1185 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1186 MLX5_FLEX_PROTO_CW_MPLS_GRE)
1187 resp.tunnel_offloads_caps |=
1188 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1189 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1190 MLX5_FLEX_PROTO_CW_MPLS_UDP)
1191 resp.tunnel_offloads_caps |=
1192 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
f95ef6cb
MG		 1193 }
1194
402ca536
BW		 1195 if (uhw->outlen) {
1196 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1197
1198 if (err)
1199 return err;
1200 }
1201
1b5daf11 1202 return 0;
e126ba97
EC		 1203}
1204
1b5daf11
MD		 1205enum mlx5_ib_width {
1206 MLX5_IB_WIDTH_1X = 1 << 0,
1207 MLX5_IB_WIDTH_2X = 1 << 1,
1208 MLX5_IB_WIDTH_4X = 1 << 2,
1209 MLX5_IB_WIDTH_8X = 1 << 3,
1210 MLX5_IB_WIDTH_12X = 1 << 4
1211};
1212
db7a691a 1213static void translate_active_width(struct ib_device *ibdev, u8 active_width,
1b5daf11 1214 u8 *ib_width)
e126ba97
EC		 1215{
1216 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11 1217
db7a691a 1218 if (active_width & MLX5_IB_WIDTH_1X)
1b5daf11 1219 *ib_width = IB_WIDTH_1X;
d764970b
MG		 1220 else if (active_width & MLX5_IB_WIDTH_2X)
1221 *ib_width = IB_WIDTH_2X;
db7a691a 1222 else if (active_width & MLX5_IB_WIDTH_4X)
1b5daf11 1223 *ib_width = IB_WIDTH_4X;
db7a691a 1224 else if (active_width & MLX5_IB_WIDTH_8X)
1b5daf11 1225 *ib_width = IB_WIDTH_8X;
db7a691a 1226 else if (active_width & MLX5_IB_WIDTH_12X)
1b5daf11 1227 *ib_width = IB_WIDTH_12X;
db7a691a
MG		 1228 else {
1229 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1b5daf11 1230 (int)active_width);
db7a691a 1231 *ib_width = IB_WIDTH_4X;
e126ba97
EC		 1232 }
1233
db7a691a 1234 return;
1b5daf11 1235}
e126ba97 1236
1b5daf11
MD		 1237static int mlx5_mtu_to_ib_mtu(int mtu)
1238{
1239 switch (mtu) {
1240 case 256: return 1;
1241 case 512: return 2;
1242 case 1024: return 3;
1243 case 2048: return 4;
1244 case 4096: return 5;
1245 default:
1246 pr_warn("invalid mtu\n");
1247 return -1;
e126ba97 1248 }
1b5daf11 1249}
e126ba97 1250
1b5daf11
MD		 1251enum ib_max_vl_num {
1252 __IB_MAX_VL_0 = 1,
1253 __IB_MAX_VL_0_1 = 2,
1254 __IB_MAX_VL_0_3 = 3,
1255 __IB_MAX_VL_0_7 = 4,
1256 __IB_MAX_VL_0_14 = 5,
1257};
e126ba97 1258
1b5daf11
MD		 1259enum mlx5_vl_hw_cap {
1260 MLX5_VL_HW_0 = 1,
1261 MLX5_VL_HW_0_1 = 2,
1262 MLX5_VL_HW_0_2 = 3,
1263 MLX5_VL_HW_0_3 = 4,
1264 MLX5_VL_HW_0_4 = 5,
1265 MLX5_VL_HW_0_5 = 6,
1266 MLX5_VL_HW_0_6 = 7,
1267 MLX5_VL_HW_0_7 = 8,
1268 MLX5_VL_HW_0_14 = 15
1269};
e126ba97 1270
1b5daf11
MD		 1271static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1272 u8 *max_vl_num)
1273{
1274 switch (vl_hw_cap) {
1275 case MLX5_VL_HW_0:
1276 *max_vl_num = __IB_MAX_VL_0;
1277 break;
1278 case MLX5_VL_HW_0_1:
1279 *max_vl_num = __IB_MAX_VL_0_1;
1280 break;
1281 case MLX5_VL_HW_0_3:
1282 *max_vl_num = __IB_MAX_VL_0_3;
1283 break;
1284 case MLX5_VL_HW_0_7:
1285 *max_vl_num = __IB_MAX_VL_0_7;
1286 break;
1287 case MLX5_VL_HW_0_14:
1288 *max_vl_num = __IB_MAX_VL_0_14;
1289 break;
e126ba97 1290
1b5daf11
MD		 1291 default:
1292 return -EINVAL;
e126ba97 1293 }
e126ba97 1294
1b5daf11 1295 return 0;
e126ba97
EC		 1296}
1297
1b5daf11
MD		 1298static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1299 struct ib_port_attr *props)
e126ba97 1300{
1b5daf11
MD		 1301 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1302 struct mlx5_core_dev *mdev = dev->mdev;
1303 struct mlx5_hca_vport_context *rep;
046339ea
SM		 1304 u16 max_mtu;
1305 u16 oper_mtu;
1b5daf11
MD		 1306 int err;
1307 u8 ib_link_width_oper;
1308 u8 vl_hw_cap;
e126ba97 1309
1b5daf11
MD		 1310 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1311 if (!rep) {
1312 err = -ENOMEM;
e126ba97 1313 goto out;
e126ba97 1314 }
e126ba97 1315
c4550c63 1316 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 1317
1b5daf11 1318 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 1319 if (err)
1320 goto out;
1321
1b5daf11
MD		 1322 props->lid = rep->lid;
1323 props->lmc = rep->lmc;
1324 props->sm_lid = rep->sm_lid;
1325 props->sm_sl = rep->sm_sl;
1326 props->state = rep->vport_state;
1327 props->phys_state = rep->port_physical_state;
1328 props->port_cap_flags = rep->cap_mask1;
1329 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1330 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1331 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1332 props->bad_pkey_cntr = rep->pkey_violation_counter;
1333 props->qkey_viol_cntr = rep->qkey_violation_counter;
1334 props->subnet_timeout = rep->subnet_timeout;
1335 props->init_type_reply = rep->init_type_reply;
e126ba97 1336
4106a758
MG		 1337 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1338 props->port_cap_flags2 = rep->cap_mask2;
1339
1b5daf11
MD		 1340 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1341 if (err)
e126ba97 1342 goto out;
e126ba97 1343
db7a691a
MG		 1344 translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1345
d5beb7f2 1346 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 1347 if (err)
1348 goto out;
1349
facc9699 1350 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 1351
1b5daf11 1352 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 1353
facc9699 1354 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 1355
1b5daf11 1356 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1357
1b5daf11
MD		 1358 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1359 if (err)
1360 goto out;
e126ba97 1361
1b5daf11
MD		 1362 err = translate_max_vl_num(ibdev, vl_hw_cap,
1363 &props->max_vl_num);
e126ba97 1364out:
1b5daf11 1365 kfree(rep);
e126ba97
EC		 1366 return err;
1367}
1368
1b5daf11
MD		 1369int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1370 struct ib_port_attr *props)
e126ba97 1371{
095b0927
IT		 1372 unsigned int count;
1373 int ret;
1374
1b5daf11
MD		 1375 switch (mlx5_get_vport_access_method(ibdev)) {
1376 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1377 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1378 break;
e126ba97 1379
1b5daf11 1380 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1381 ret = mlx5_query_hca_port(ibdev, port, props);
1382 break;
e126ba97 1383
3f89a643 1384 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1385 ret = mlx5_query_port_roce(ibdev, port, props);
1386 break;
3f89a643 1387
1b5daf11 1388 default:
095b0927
IT		 1389 ret = -EINVAL;
1390 }
1391
1392 if (!ret && props) {
b3cbd6f0
DJ		 1393 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1394 struct mlx5_core_dev *mdev;
1395 bool put_mdev = true;
1396
1397 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1398 if (!mdev) {
1399 /* If the port isn't affiliated yet query the master.
1400 * The master and slave will have the same values.
1401 */
1402 mdev = dev->mdev;
1403 port = 1;
1404 put_mdev = false;
1405 }
1406 count = mlx5_core_reserved_gids_count(mdev);
1407 if (put_mdev)
1408 mlx5_ib_put_native_port_mdev(dev, port);
095b0927 1409 props->gid_tbl_len -= count;
1b5daf11 1410 }
095b0927 1411 return ret;
1b5daf11 1412}
e126ba97 1413
8e6efa3a
MB		 1414static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1415 struct ib_port_attr *props)
1416{
1417 int ret;
1418
26628e2d
MB		 1419 /* Only link layer == ethernet is valid for representors
1420 * and we always use port 1
1421 */
8e6efa3a
MB		 1422 ret = mlx5_query_port_roce(ibdev, port, props);
1423 if (ret || !props)
1424 return ret;
1425
1426 /* We don't support GIDS */
1427 props->gid_tbl_len = 0;
1428
1429 return ret;
1430}
1431
1b5daf11
MD		 1432static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1433 union ib_gid *gid)
1434{
1435 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1436 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1437
1b5daf11
MD		 1438 switch (mlx5_get_vport_access_method(ibdev)) {
1439 case MLX5_VPORT_ACCESS_METHOD_MAD:
1440 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1441
1b5daf11
MD		 1442 case MLX5_VPORT_ACCESS_METHOD_HCA:
1443 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1444
1445 default:
1446 return -EINVAL;
1447 }
e126ba97 1448
e126ba97
EC		 1449}
1450
b3cbd6f0
DJ		 1451static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1452 u16 index, u16 *pkey)
1b5daf11
MD		 1453{
1454 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b3cbd6f0
DJ		 1455 struct mlx5_core_dev *mdev;
1456 bool put_mdev = true;
1457 u8 mdev_port_num;
1458 int err;
1b5daf11 1459
b3cbd6f0
DJ		 1460 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1461 if (!mdev) {
1462 /* The port isn't affiliated yet, get the PKey from the master
1463 * port. For RoCE the PKey tables will be the same.
1464 */
1465 put_mdev = false;
1466 mdev = dev->mdev;
1467 mdev_port_num = 1;
1468 }
1469
1470 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1471 index, pkey);
1472 if (put_mdev)
1473 mlx5_ib_put_native_port_mdev(dev, port);
1474
1475 return err;
1476}
1477
1478static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1479 u16 *pkey)
1480{
1b5daf11
MD		 1481 switch (mlx5_get_vport_access_method(ibdev)) {
1482 case MLX5_VPORT_ACCESS_METHOD_MAD:
1483 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1484
1485 case MLX5_VPORT_ACCESS_METHOD_HCA:
1486 case MLX5_VPORT_ACCESS_METHOD_NIC:
b3cbd6f0 1487 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1b5daf11
MD		 1488 default:
1489 return -EINVAL;
1490 }
1491}
e126ba97
EC		 1492
1493static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1494 struct ib_device_modify *props)
1495{
1496 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1497 struct mlx5_reg_node_desc in;
1498 struct mlx5_reg_node_desc out;
1499 int err;
1500
1501 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1502 return -EOPNOTSUPP;
1503
1504 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1505 return 0;
1506
1507 /*
1508 * If possible, pass node desc to FW, so it can generate
1509 * a 144 trap. If cmd fails, just ignore.
1510 */
bd99fdea 1511 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1512 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1513 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1514 if (err)
1515 return err;
1516
bd99fdea 1517 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1518
1519 return err;
1520}
1521
cdbe33d0
EC		 1522static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1523 u32 value)
1524{
1525 struct mlx5_hca_vport_context ctx = {};
b3cbd6f0
DJ		 1526 struct mlx5_core_dev *mdev;
1527 u8 mdev_port_num;
cdbe33d0
EC		 1528 int err;
1529
b3cbd6f0
DJ		 1530 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1531 if (!mdev)
1532 return -ENODEV;
1533
1534 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
cdbe33d0 1535 if (err)
b3cbd6f0 1536 goto out;
cdbe33d0
EC		 1537
1538 if (~ctx.cap_mask1_perm & mask) {
1539 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1540 mask, ctx.cap_mask1_perm);
b3cbd6f0
DJ		 1541 err = -EINVAL;
1542 goto out;
cdbe33d0
EC		 1543 }
1544
1545 ctx.cap_mask1 = value;
1546 ctx.cap_mask1_perm = mask;
b3cbd6f0
DJ		 1547 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1548 0, &ctx);
1549
1550out:
1551 mlx5_ib_put_native_port_mdev(dev, port_num);
cdbe33d0
EC		 1552
1553 return err;
1554}
1555
e126ba97
EC		 1556static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1557 struct ib_port_modify *props)
1558{
1559 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1560 struct ib_port_attr attr;
1561 u32 tmp;
1562 int err;
cdbe33d0
EC		 1563 u32 change_mask;
1564 u32 value;
1565 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1566 IB_LINK_LAYER_INFINIBAND);
1567
ec255879
MD		 1568 /* CM layer calls ib_modify_port() regardless of the link layer. For
1569 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1570 */
1571 if (!is_ib)
1572 return 0;
1573
cdbe33d0
EC		 1574 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1575 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1576 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1577 return set_port_caps_atomic(dev, port, change_mask, value);
1578 }
e126ba97
EC		 1579
1580 mutex_lock(&dev->cap_mask_mutex);
1581
c4550c63 1582 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1583 if (err)
1584 goto out;
1585
1586 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1587 ~props->clr_port_cap_mask;
1588
9603b61d 1589 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1590
1591out:
1592 mutex_unlock(&dev->cap_mask_mutex);
1593 return err;
1594}
1595
30aa60b3
EC		 1596static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1597{
1598 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1599 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1600}
1601
31a78a5a
YH		 1602static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1603{
1604 /* Large page with non 4k uar support might limit the dynamic size */
1605 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1606 return MLX5_MIN_DYN_BFREGS;
1607
1608 return MLX5_MAX_DYN_BFREGS;
1609}
1610
b037c29a
EC		 1611static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1612 struct mlx5_ib_alloc_ucontext_req_v2 *req,
31a78a5a 1613 struct mlx5_bfreg_info *bfregi)
b037c29a
EC		 1614{
1615 int uars_per_sys_page;
1616 int bfregs_per_sys_page;
1617 int ref_bfregs = req->total_num_bfregs;
1618
1619 if (req->total_num_bfregs == 0)
1620 return -EINVAL;
1621
1622 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1623 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1624
1625 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1626 return -ENOMEM;
1627
1628 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1629 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
31a78a5a 1630 /* This holds the required static allocation asked by the user */
b037c29a 1631 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
b037c29a
EC		 1632 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1633 return -EINVAL;
1634
31a78a5a
YH		 1635 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1636 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1637 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1638 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1639
1640 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
b037c29a
EC		 1641 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1642 lib_uar_4k ? "yes" : "no", ref_bfregs,
31a78a5a
YH		 1643 req->total_num_bfregs, bfregi->total_num_bfregs,
1644 bfregi->num_sys_pages);
b037c29a
EC		 1645
1646 return 0;
1647}
1648
1649static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1650{
1651 struct mlx5_bfreg_info *bfregi;
1652 int err;
1653 int i;
1654
1655 bfregi = &context->bfregi;
31a78a5a 1656 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
b037c29a
EC		 1657 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1658 if (err)
1659 goto error;
1660
1661 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1662 }
4ed131d0
YH		 1663
1664 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1665 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1666
b037c29a
EC		 1667 return 0;
1668
1669error:
1670 for (--i; i >= 0; i--)
1671 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1672 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1673
1674 return err;
1675}
1676
15177999
LR		 1677static void deallocate_uars(struct mlx5_ib_dev *dev,
1678 struct mlx5_ib_ucontext *context)
b037c29a
EC		 1679{
1680 struct mlx5_bfreg_info *bfregi;
b037c29a
EC		 1681 int i;
1682
1683 bfregi = &context->bfregi;
15177999 1684 for (i = 0; i < bfregi->num_sys_pages; i++)
4ed131d0 1685 if (i < bfregi->num_static_sys_pages ||
15177999
LR		 1686 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1687 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
b037c29a
EC		 1688}
1689
0042f9e4 1690int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
a560f1d9
MB		 1691{
1692 int err = 0;
1693
1694 mutex_lock(&dev->lb.mutex);
0042f9e4
MB		 1695 if (td)
1696 dev->lb.user_td++;
1697 if (qp)
1698 dev->lb.qps++;
1699
1700 if (dev->lb.user_td == 2 ||
1701 dev->lb.qps == 1) {
1702 if (!dev->lb.enabled) {
1703 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1704 dev->lb.enabled = true;
1705 }
1706 }
a560f1d9
MB		 1707
1708 mutex_unlock(&dev->lb.mutex);
1709
1710 return err;
1711}
1712
0042f9e4 1713void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
a560f1d9
MB		 1714{
1715 mutex_lock(&dev->lb.mutex);
0042f9e4
MB		 1716 if (td)
1717 dev->lb.user_td--;
1718 if (qp)
1719 dev->lb.qps--;
1720
1721 if (dev->lb.user_td == 1 &&
1722 dev->lb.qps == 0) {
1723 if (dev->lb.enabled) {
1724 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1725 dev->lb.enabled = false;
1726 }
1727 }
a560f1d9
MB		 1728
1729 mutex_unlock(&dev->lb.mutex);
1730}
1731
d2d19121
YH		 1732static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1733 u16 uid)
c85023e1
HN		 1734{
1735 int err;
1736
cfdeb893
LR		 1737 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1738 return 0;
1739
d2d19121 1740 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
c85023e1
HN		 1741 if (err)
1742 return err;
1743
1744 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1745 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1746 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1747 return err;
1748
0042f9e4 1749 return mlx5_ib_enable_lb(dev, true, false);
c85023e1
HN		 1750}
1751
d2d19121
YH		 1752static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1753 u16 uid)
c85023e1 1754{
cfdeb893
LR		 1755 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1756 return;
1757
d2d19121 1758 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
c85023e1
HN		 1759
1760 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1761 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1762 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1763 return;
1764
0042f9e4 1765 mlx5_ib_disable_lb(dev, true, false);
c85023e1
HN		 1766}
1767
a2a074ef
LR		 1768static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1769 struct ib_udata *udata)
e126ba97 1770{
a2a074ef 1771 struct ib_device *ibdev = uctx->device;
e126ba97 1772 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1773 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1774 struct mlx5_ib_alloc_ucontext_resp resp = {};
5c99eaec 1775 struct mlx5_core_dev *mdev = dev->mdev;
a2a074ef 1776 struct mlx5_ib_ucontext *context = to_mucontext(uctx);
2f5ff264 1777 struct mlx5_bfreg_info *bfregi;
78c0f98c 1778 int ver;
e126ba97 1779 int err;
a168a41c
MD		 1780 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1781 max_cqe_version);
25bb36e7 1782 u32 dump_fill_mkey;
b037c29a 1783 bool lib_uar_4k;
e126ba97
EC		 1784
1785 if (!dev->ib_active)
a2a074ef 1786 return -EAGAIN;
e126ba97 1787
e093111d 1788 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1789 ver = 0;
e093111d 1790 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1791 ver = 2;
1792 else
a2a074ef 1793 return -EINVAL;
78c0f98c 1794
e093111d 1795 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97 1796 if (err)
a2a074ef 1797 return err;
e126ba97 1798
a8b92ca1 1799 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
a2a074ef 1800 return -EOPNOTSUPP;
78c0f98c 1801
f72300c5 1802 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
a2a074ef 1803 return -EOPNOTSUPP;
b368d7cb 1804
2f5ff264
EC		 1805 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1806 MLX5_NON_FP_BFREGS_PER_UAR);
1807 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
a2a074ef 1808 return -EINVAL;
e126ba97 1809
938fe83c 1810 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1811 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1812 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1813 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1814 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1815 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1816 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1817 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1818 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1819 resp.cqe_version = min_t(__u8,
1820 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1821 req.max_cqe_version);
30aa60b3
EC		 1822 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1823 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1824 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1825 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1826 resp.response_length = min(offsetof(typeof(resp), response_length) +
1827 sizeof(resp.response_length), udata->outlen);
e126ba97 1828
c03faa56
MB		 1829 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1830 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1831 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1832 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1833 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1834 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1835 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1836 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1837 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1838 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1839 }
1840
30aa60b3 1841 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1842 bfregi = &context->bfregi;
b037c29a
EC		 1843
1844 /* updates req->total_num_bfregs */
31a78a5a 1845 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
b037c29a 1846 if (err)
e126ba97 1847 goto out_ctx;
e126ba97 1848
b037c29a
EC		 1849 mutex_init(&bfregi->lock);
1850 bfregi->lib_uar_4k = lib_uar_4k;
31a78a5a 1851 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1852 GFP_KERNEL);
b037c29a 1853 if (!bfregi->count) {
e126ba97 1854 err = -ENOMEM;
b037c29a 1855 goto out_ctx;
e126ba97
EC		 1856 }
1857
b037c29a
EC		 1858 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1859 sizeof(*bfregi->sys_pages),
1860 GFP_KERNEL);
1861 if (!bfregi->sys_pages) {
e126ba97 1862 err = -ENOMEM;
b037c29a 1863 goto out_count;
e126ba97
EC		 1864 }
1865
b037c29a
EC		 1866 err = allocate_uars(dev, context);
1867 if (err)
1868 goto out_sys_pages;
e126ba97 1869
13859d5d
LR		 1870 if (ibdev->attrs.device_cap_flags & IB_DEVICE_ON_DEMAND_PAGING)
1871 context->ibucontext.invalidate_range =
1872 &mlx5_ib_invalidate_range;
b4cfe447 1873
a8b92ca1 1874 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
fb98153b 1875 err = mlx5_ib_devx_create(dev, true);
76dc5a84 1876 if (err < 0)
d2d19121 1877 goto out_uars;
76dc5a84 1878 context->devx_uid = err;
a8b92ca1
YH		 1879 }
1880
d2d19121
YH		 1881 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1882 context->devx_uid);
1883 if (err)
1884 goto out_devx;
1885
25bb36e7
YC		 1886 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1887 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1888 if (err)
8193abb6 1889 goto out_mdev;
25bb36e7
YC		 1890 }
1891
e126ba97
EC		 1892 INIT_LIST_HEAD(&context->db_page_list);
1893 mutex_init(&context->db_page_mutex);
1894
2f5ff264 1895 resp.tot_bfregs = req.total_num_bfregs;
508562d6 1896 resp.num_ports = dev->num_ports;
b368d7cb 1897
f72300c5
HA		 1898 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1899 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1900
402ca536 1901 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1902 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1903 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1904 resp.response_length += sizeof(resp.cmds_supp_uhw);
1905 }
1906
78984898
OG		 1907 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1908 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1909 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1910 resp.eth_min_inline++;
1911 }
1912 resp.response_length += sizeof(resp.eth_min_inline);
1913 }
1914
5c99eaec
FD		 1915 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1916 if (mdev->clock_info)
1917 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1918 resp.response_length += sizeof(resp.clock_info_versions);
1919 }
1920
bc5c6eed
NO		 1921 /*
1922 * We don't want to expose information from the PCI bar that is located
1923 * after 4096 bytes, so if the arch only supports larger pages, let's
1924 * pretend we don't support reading the HCA's core clock. This is also
1925 * forced by mmap function.
1926 */
de8d6e02
EC		 1927 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1928 if (PAGE_SIZE <= 4096) {
1929 resp.comp_mask |=
1930 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1931 resp.hca_core_clock_offset =
1932 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1933 }
5c99eaec 1934 resp.response_length += sizeof(resp.hca_core_clock_offset);
b368d7cb
MB		 1935 }
1936
30aa60b3
EC		 1937 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1938 resp.response_length += sizeof(resp.log_uar_size);
1939
1940 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1941 resp.response_length += sizeof(resp.num_uars_per_page);
1942
31a78a5a
YH		 1943 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1944 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1945 resp.response_length += sizeof(resp.num_dyn_bfregs);
1946 }
1947
25bb36e7
YC		 1948 if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) {
1949 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1950 resp.dump_fill_mkey = dump_fill_mkey;
1951 resp.comp_mask |=
1952 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1953 }
1954 resp.response_length += sizeof(resp.dump_fill_mkey);
1955 }
1956
b368d7cb 1957 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1958 if (err)
a8b92ca1 1959 goto out_mdev;
e126ba97 1960
2f5ff264
EC		 1961 bfregi->ver = ver;
1962 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1963 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1964 context->lib_caps = req.lib_caps;
1965 print_lib_caps(dev, context->lib_caps);
f72300c5 1966
7c34ec19 1967 if (dev->lag_active) {
95579e78 1968 u8 port = mlx5_core_native_port_num(dev->mdev) - 1;
c6a21c38
MD		 1969
1970 atomic_set(&context->tx_port_affinity,
1971 atomic_add_return(
95579e78 1972 1, &dev->port[port].roce.tx_port_affinity));
c6a21c38
MD		 1973 }
1974
a2a074ef 1975 return 0;
e126ba97 1976
a8b92ca1 1977out_mdev:
d2d19121
YH		 1978 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1979out_devx:
a8b92ca1 1980 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
76dc5a84 1981 mlx5_ib_devx_destroy(dev, context->devx_uid);
146d2f1a 1982
e126ba97 1983out_uars:
b037c29a 1984 deallocate_uars(dev, context);
e126ba97 1985
b037c29a
EC		 1986out_sys_pages:
1987 kfree(bfregi->sys_pages);
e126ba97 1988
b037c29a
EC		 1989out_count:
1990 kfree(bfregi->count);
e126ba97
EC		 1991
1992out_ctx:
a2a074ef 1993 return err;
e126ba97
EC		 1994}
1995
a2a074ef 1996static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
e126ba97
EC		 1997{
1998 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1999 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 2000 struct mlx5_bfreg_info *bfregi;
e126ba97 2001
f27a0d50
JG		 2002 /* All umem's must be destroyed before destroying the ucontext. */
2003 mutex_lock(&ibcontext->per_mm_list_lock);
2004 WARN_ON(!list_empty(&ibcontext->per_mm_list));
2005 mutex_unlock(&ibcontext->per_mm_list_lock);
a8b92ca1 2006
b037c29a 2007 bfregi = &context->bfregi;
d2d19121
YH		 2008 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
2009
a8b92ca1 2010 if (context->devx_uid)
76dc5a84 2011 mlx5_ib_devx_destroy(dev, context->devx_uid);
146d2f1a 2012
b037c29a
EC		 2013 deallocate_uars(dev, context);
2014 kfree(bfregi->sys_pages);
2f5ff264 2015 kfree(bfregi->count);
e126ba97
EC		 2016}
2017
b037c29a 2018static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
4ed131d0 2019 int uar_idx)
e126ba97 2020{
b037c29a
EC		 2021 int fw_uars_per_page;
2022
2023 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2024
aa8106f1 2025 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
e126ba97
EC		 2026}
2027
2028static int get_command(unsigned long offset)
2029{
2030 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2031}
2032
2033static int get_arg(unsigned long offset)
2034{
2035 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2036}
2037
2038static int get_index(unsigned long offset)
2039{
2040 return get_arg(offset);
2041}
2042
4ed131d0
YH		 2043/* Index resides in an extra byte to enable larger values than 255 */
2044static int get_extended_index(unsigned long offset)
2045{
2046 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2047}
2048
7c2344c3
MG		 2049
2050static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2051{
7c2344c3
MG		 2052}
2053
37aa5c36
GL		 2054static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2055{
2056 switch (cmd) {
2057 case MLX5_IB_MMAP_WC_PAGE:
2058 return "WC";
2059 case MLX5_IB_MMAP_REGULAR_PAGE:
2060 return "best effort WC";
2061 case MLX5_IB_MMAP_NC_PAGE:
2062 return "NC";
24da0016
AL		 2063 case MLX5_IB_MMAP_DEVICE_MEM:
2064 return "Device Memory";
37aa5c36
GL		 2065 default:
2066 return NULL;
2067 }
2068}
2069
5c99eaec
FD		 2070static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2071 struct vm_area_struct *vma,
2072 struct mlx5_ib_ucontext *context)
2073{
4eb6ab13
JG		 2074 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2075 !(vma->vm_flags & VM_SHARED))
5c99eaec
FD		 2076 return -EINVAL;
2077
2078 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2079 return -EOPNOTSUPP;
2080
4eb6ab13 2081 if (vma->vm_flags & (VM_WRITE | VM_EXEC))
5c99eaec 2082 return -EPERM;
c660133c 2083 vma->vm_flags &= ~VM_MAYWRITE;
5c99eaec 2084
ddcdc368 2085 if (!dev->mdev->clock_info)
5c99eaec
FD		 2086 return -EOPNOTSUPP;
2087
4eb6ab13
JG		 2088 return vm_insert_page(vma, vma->vm_start,
2089 virt_to_page(dev->mdev->clock_info));
5c99eaec
FD		 2090}
2091
37aa5c36 2092static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 2093 struct vm_area_struct *vma,
2094 struct mlx5_ib_ucontext *context)
37aa5c36 2095{
2f5ff264 2096 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 2097 int err;
2098 unsigned long idx;
aa09ea6e 2099 phys_addr_t pfn;
37aa5c36 2100 pgprot_t prot;
4ed131d0
YH		 2101 u32 bfreg_dyn_idx = 0;
2102 u32 uar_index;
2103 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2104 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2105 bfregi->num_static_sys_pages;
b037c29a
EC		 2106
2107 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2108 return -EINVAL;
2109
4ed131d0
YH		 2110 if (dyn_uar)
2111 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2112 else
2113 idx = get_index(vma->vm_pgoff);
2114
2115 if (idx >= max_valid_idx) {
2116 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2117 idx, max_valid_idx);
b037c29a
EC		 2118 return -EINVAL;
2119 }
37aa5c36
GL		 2120
2121 switch (cmd) {
2122 case MLX5_IB_MMAP_WC_PAGE:
4ed131d0 2123 case MLX5_IB_MMAP_ALLOC_WC:
37aa5c36
GL		 2124/* Some architectures don't support WC memory */
2125#if defined(CONFIG_X86)
2126 if (!pat_enabled())
2127 return -EPERM;
2128#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2129 return -EPERM;
2130#endif
2131 /* fall through */
2132 case MLX5_IB_MMAP_REGULAR_PAGE:
2133 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2134 prot = pgprot_writecombine(vma->vm_page_prot);
2135 break;
2136 case MLX5_IB_MMAP_NC_PAGE:
2137 prot = pgprot_noncached(vma->vm_page_prot);
2138 break;
2139 default:
2140 return -EINVAL;
2141 }
2142
4ed131d0
YH		 2143 if (dyn_uar) {
2144 int uars_per_page;
2145
2146 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2147 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2148 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2149 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2150 bfreg_dyn_idx, bfregi->total_num_bfregs);
2151 return -EINVAL;
2152 }
2153
2154 mutex_lock(&bfregi->lock);
2155 /* Fail if uar already allocated, first bfreg index of each
2156 * page holds its count.
2157 */
2158 if (bfregi->count[bfreg_dyn_idx]) {
2159 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2160 mutex_unlock(&bfregi->lock);
2161 return -EINVAL;
2162 }
2163
2164 bfregi->count[bfreg_dyn_idx]++;
2165 mutex_unlock(&bfregi->lock);
2166
2167 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2168 if (err) {
2169 mlx5_ib_warn(dev, "UAR alloc failed\n");
2170 goto free_bfreg;
2171 }
2172 } else {
2173 uar_index = bfregi->sys_pages[idx];
2174 }
2175
2176 pfn = uar_index2pfn(dev, uar_index);
37aa5c36
GL		 2177 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2178
e2cd1d1a
JG		 2179 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2180 prot);
37aa5c36 2181 if (err) {
8f062287 2182 mlx5_ib_err(dev,
e2cd1d1a 2183 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
8f062287 2184 err, mmap_cmd2str(cmd));
4ed131d0 2185 goto err;
37aa5c36
GL		 2186 }
2187
4ed131d0
YH		 2188 if (dyn_uar)
2189 bfregi->sys_pages[idx] = uar_index;
2190 return 0;
2191
2192err:
2193 if (!dyn_uar)
2194 return err;
2195
2196 mlx5_cmd_free_uar(dev->mdev, idx);
2197
2198free_bfreg:
2199 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2200
2201 return err;
37aa5c36
GL		 2202}
2203
24da0016
AL		 2204static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2205{
2206 struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2207 struct mlx5_ib_dev *dev = to_mdev(context->device);
2208 u16 page_idx = get_extended_index(vma->vm_pgoff);
2209 size_t map_size = vma->vm_end - vma->vm_start;
2210 u32 npages = map_size >> PAGE_SHIFT;
2211 phys_addr_t pfn;
24da0016
AL		 2212
2213 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2214 page_idx + npages)
2215 return -EINVAL;
2216
aa8106f1 2217 pfn = ((dev->mdev->bar_addr +
24da0016
AL		 2218 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2219 PAGE_SHIFT) +
2220 page_idx;
e2cd1d1a
JG		 2221 return rdma_user_mmap_io(context, vma, pfn, map_size,
2222 pgprot_writecombine(vma->vm_page_prot));
24da0016
AL		 2223}
2224
e126ba97
EC		 2225static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2226{
2227 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2228 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 2229 unsigned long command;
e126ba97
EC		 2230 phys_addr_t pfn;
2231
2232 command = get_command(vma->vm_pgoff);
2233 switch (command) {
37aa5c36
GL		 2234 case MLX5_IB_MMAP_WC_PAGE:
2235 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 2236 case MLX5_IB_MMAP_REGULAR_PAGE:
4ed131d0 2237 case MLX5_IB_MMAP_ALLOC_WC:
7c2344c3 2238 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 2239
2240 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2241 return -ENOSYS;
2242
d69e3bcf 2243 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 2244 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2245 return -EINVAL;
2246
6cbac1e4 2247 if (vma->vm_flags & VM_WRITE)
d69e3bcf 2248 return -EPERM;
c660133c 2249 vma->vm_flags &= ~VM_MAYWRITE;
d69e3bcf
MB		 2250
2251 /* Don't expose to user-space information it shouldn't have */
2252 if (PAGE_SIZE > 4096)
2253 return -EOPNOTSUPP;
2254
d69e3bcf
MB		 2255 pfn = (dev->mdev->iseg_base +
2256 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2257 PAGE_SHIFT;
d5e560d3
JG		 2258 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2259 PAGE_SIZE,
2260 pgprot_noncached(vma->vm_page_prot));
5c99eaec
FD		 2261 case MLX5_IB_MMAP_CLOCK_INFO:
2262 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
d69e3bcf 2263
24da0016
AL		 2264 case MLX5_IB_MMAP_DEVICE_MEM:
2265 return dm_mmap(ibcontext, vma);
2266
e126ba97
EC		 2267 default:
2268 return -EINVAL;
2269 }
2270
2271 return 0;
2272}
2273
25c13324
AL		 2274static inline int check_dm_type_support(struct mlx5_ib_dev *dev,
2275 u32 type)
24da0016 2276{
25c13324
AL		 2277 switch (type) {
2278 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2279 if (!MLX5_CAP_DEV_MEM(dev->mdev, memic))
2280 return -EOPNOTSUPP;
2281 break;
2282 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
c9b9dcb4 2283 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
25c13324
AL		 2284 if (!capable(CAP_SYS_RAWIO) ||
2285 !capable(CAP_NET_RAW))
2286 return -EPERM;
2287
2288 if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
2289 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner)))
2290 return -EOPNOTSUPP;
2291 break;
2292 }
2293
2294 return 0;
2295}
2296
3b113a1e
AL		 2297static int handle_alloc_dm_memic(struct ib_ucontext *ctx,
2298 struct mlx5_ib_dm *dm,
2299 struct ib_dm_alloc_attr *attr,
2300 struct uverbs_attr_bundle *attrs)
24da0016 2301{
3b113a1e 2302 struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm;
24da0016
AL		 2303 u64 start_offset;
2304 u32 page_idx;
2305 int err;
2306
3b113a1e 2307 dm->size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
24da0016 2308
3b113a1e
AL		 2309 err = mlx5_cmd_alloc_memic(dm_db, &dm->dev_addr,
2310 dm->size, attr->alignment);
24da0016 2311 if (err)
3b113a1e 2312 return err;
24da0016 2313
3b113a1e
AL		 2314 page_idx = (dm->dev_addr - pci_resource_start(dm_db->dev->pdev, 0) -
2315 MLX5_CAP64_DEV_MEM(dm_db->dev, memic_bar_start_addr)) >>
24da0016
AL		 2316 PAGE_SHIFT;
2317
2318 err = uverbs_copy_to(attrs,
3b113a1e
AL		 2319 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2320 &page_idx, sizeof(page_idx));
24da0016
AL		 2321 if (err)
2322 goto err_dealloc;
2323
3b113a1e 2324 start_offset = dm->dev_addr & ~PAGE_MASK;
24da0016
AL		 2325 err = uverbs_copy_to(attrs,
2326 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2327 &start_offset, sizeof(start_offset));
2328 if (err)
2329 goto err_dealloc;
2330
3b113a1e
AL		 2331 bitmap_set(to_mucontext(ctx)->dm_pages, page_idx,
2332 DIV_ROUND_UP(dm->size, PAGE_SIZE));
2333
2334 return 0;
2335
2336err_dealloc:
2337 mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2338
2339 return err;
2340}
2341
25c13324
AL		 2342static int handle_alloc_dm_sw_icm(struct ib_ucontext *ctx,
2343 struct mlx5_ib_dm *dm,
2344 struct ib_dm_alloc_attr *attr,
2345 struct uverbs_attr_bundle *attrs,
2346 int type)
2347{
c9b9dcb4 2348 struct mlx5_core_dev *dev = to_mdev(ctx->device)->mdev;
25c13324
AL		 2349 u64 act_size;
2350 int err;
2351
2352 /* Allocation size must a multiple of the basic block size
2353 * and a power of 2.
2354 */
c9b9dcb4 2355 act_size = round_up(attr->length, MLX5_SW_ICM_BLOCK_SIZE(dev));
25c13324
AL		 2356 act_size = roundup_pow_of_two(act_size);
2357
2358 dm->size = act_size;
c9b9dcb4
AL		 2359 err = mlx5_dm_sw_icm_alloc(dev, type, act_size,
2360 to_mucontext(ctx)->devx_uid, &dm->dev_addr,
2361 &dm->icm_dm.obj_id);
25c13324
AL		 2362 if (err)
2363 return err;
2364
24da0016 2365 err = uverbs_copy_to(attrs,
25c13324
AL		 2366 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2367 &dm->dev_addr, sizeof(dm->dev_addr));
24da0016 2368 if (err)
c9b9dcb4
AL		 2369 mlx5_dm_sw_icm_dealloc(dev, type, dm->size,
2370 to_mucontext(ctx)->devx_uid, dm->dev_addr,
2371 dm->icm_dm.obj_id);
25c13324
AL		 2372
2373 return err;
2374}
2375
3b113a1e
AL		 2376struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2377 struct ib_ucontext *context,
2378 struct ib_dm_alloc_attr *attr,
2379 struct uverbs_attr_bundle *attrs)
2380{
2381 struct mlx5_ib_dm *dm;
2382 enum mlx5_ib_uapi_dm_type type;
2383 int err;
24da0016 2384
3b113a1e
AL		 2385 err = uverbs_get_const_default(&type, attrs,
2386 MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
2387 MLX5_IB_UAPI_DM_TYPE_MEMIC);
2388 if (err)
2389 return ERR_PTR(err);
24da0016 2390
3b113a1e
AL		 2391 mlx5_ib_dbg(to_mdev(ibdev), "alloc_dm req: dm_type=%d user_length=0x%llx log_alignment=%d\n",
2392 type, attr->length, attr->alignment);
2393
25c13324
AL		 2394 err = check_dm_type_support(to_mdev(ibdev), type);
2395 if (err)
2396 return ERR_PTR(err);
2397
3b113a1e
AL		 2398 dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2399 if (!dm)
2400 return ERR_PTR(-ENOMEM);
2401
2402 dm->type = type;
2403
2404 switch (type) {
2405 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2406 err = handle_alloc_dm_memic(context, dm,
2407 attr,
2408 attrs);
2409 break;
25c13324 2410 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
c9b9dcb4
AL		 2411 err = handle_alloc_dm_sw_icm(context, dm,
2412 attr, attrs,
2413 MLX5_SW_ICM_TYPE_STEERING);
2414 break;
25c13324 2415 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
c9b9dcb4
AL		 2416 err = handle_alloc_dm_sw_icm(context, dm,
2417 attr, attrs,
2418 MLX5_SW_ICM_TYPE_HEADER_MODIFY);
25c13324 2419 break;
3b113a1e
AL		 2420 default:
2421 err = -EOPNOTSUPP;
2422 }
24da0016 2423
3b113a1e
AL		 2424 if (err)
2425 goto err_free;
24da0016
AL		 2426
2427 return &dm->ibdm;
2428
24da0016
AL		 2429err_free:
2430 kfree(dm);
2431 return ERR_PTR(err);
2432}
2433
c4367a26 2434int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs)
24da0016 2435{
25c13324
AL		 2436 struct mlx5_ib_ucontext *ctx = rdma_udata_to_drv_context(
2437 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
c9b9dcb4 2438 struct mlx5_core_dev *dev = to_mdev(ibdm->device)->mdev;
3b113a1e 2439 struct mlx5_dm *dm_db = &to_mdev(ibdm->device)->dm;
24da0016 2440 struct mlx5_ib_dm *dm = to_mdm(ibdm);
24da0016
AL		 2441 u32 page_idx;
2442 int ret;
2443
3b113a1e
AL		 2444 switch (dm->type) {
2445 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2446 ret = mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2447 if (ret)
2448 return ret;
24da0016 2449
c9b9dcb4
AL		 2450 page_idx = (dm->dev_addr - pci_resource_start(dev->pdev, 0) -
2451 MLX5_CAP64_DEV_MEM(dev, memic_bar_start_addr)) >>
2452 PAGE_SHIFT;
25c13324
AL		 2453 bitmap_clear(ctx->dm_pages, page_idx,
2454 DIV_ROUND_UP(dm->size, PAGE_SIZE));
2455 break;
2456 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
c9b9dcb4
AL		 2457 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_STEERING,
2458 dm->size, ctx->devx_uid, dm->dev_addr,
2459 dm->icm_dm.obj_id);
2460 if (ret)
2461 return ret;
2462 break;
25c13324 2463 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
c9b9dcb4
AL		 2464 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_HEADER_MODIFY,
2465 dm->size, ctx->devx_uid, dm->dev_addr,
2466 dm->icm_dm.obj_id);
25c13324
AL		 2467 if (ret)
2468 return ret;
3b113a1e
AL		 2469 break;
2470 default:
2471 return -EOPNOTSUPP;
2472 }
24da0016
AL		 2473
2474 kfree(dm);
2475
2476 return 0;
2477}
2478
ff23dfa1 2479static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
e126ba97 2480{
21a428a0
LR		 2481 struct mlx5_ib_pd *pd = to_mpd(ibpd);
2482 struct ib_device *ibdev = ibpd->device;
e126ba97 2483 struct mlx5_ib_alloc_pd_resp resp;
e126ba97 2484 int err;
a1069c1c
YH		 2485 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2486 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
2487 u16 uid = 0;
ff23dfa1
SR		 2488 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2489 udata, struct mlx5_ib_ucontext, ibucontext);
e126ba97 2490
ff23dfa1 2491 uid = context ? context->devx_uid : 0;
a1069c1c
YH		 2492 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2493 MLX5_SET(alloc_pd_in, in, uid, uid);
2494 err = mlx5_cmd_exec(to_mdev(ibdev)->mdev, in, sizeof(in),
2495 out, sizeof(out));
21a428a0
LR		 2496 if (err)
2497 return err;
e126ba97 2498
a1069c1c
YH		 2499 pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2500 pd->uid = uid;
ff23dfa1 2501 if (udata) {
e126ba97
EC		 2502 resp.pdn = pd->pdn;
2503 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
a1069c1c 2504 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
21a428a0 2505 return -EFAULT;
e126ba97 2506 }
e126ba97
EC		 2507 }
2508
21a428a0 2509 return 0;
e126ba97
EC		 2510}
2511
c4367a26 2512static void mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
e126ba97
EC		 2513{
2514 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2515 struct mlx5_ib_pd *mpd = to_mpd(pd);
2516
a1069c1c 2517 mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
e126ba97
EC		 2518}
2519
466fa6d2
MG		 2520enum {
2521 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2522 MATCH_CRITERIA_ENABLE_MISC_BIT,
71c6e863
AL		 2523 MATCH_CRITERIA_ENABLE_INNER_BIT,
2524 MATCH_CRITERIA_ENABLE_MISC2_BIT
466fa6d2
MG		 2525};
2526
2527#define HEADER_IS_ZERO(match_criteria, headers) \
2528 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2529 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 2530
466fa6d2 2531static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 2532{
466fa6d2 2533 u8 match_criteria_enable;
038d2ef8 2534
466fa6d2
MG		 2535 match_criteria_enable =
2536 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2537 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2538 match_criteria_enable |=
2539 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2540 MATCH_CRITERIA_ENABLE_MISC_BIT;
2541 match_criteria_enable |=
2542 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2543 MATCH_CRITERIA_ENABLE_INNER_BIT;
71c6e863
AL		 2544 match_criteria_enable |=
2545 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2546 MATCH_CRITERIA_ENABLE_MISC2_BIT;
466fa6d2
MG		 2547
2548 return match_criteria_enable;
038d2ef8
MG		 2549}
2550
6113cc44 2551static int set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
ca0d4753 2552{
6113cc44
MG		 2553 u8 entry_mask;
2554 u8 entry_val;
2555 int err = 0;
2556
2557 if (!mask)
2558 goto out;
2559
2560 entry_mask = MLX5_GET(fte_match_set_lyr_2_4, outer_c,
2561 ip_protocol);
2562 entry_val = MLX5_GET(fte_match_set_lyr_2_4, outer_v,
2563 ip_protocol);
2564 if (!entry_mask) {
2565 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2566 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2567 goto out;
2568 }
2569 /* Don't override existing ip protocol */
2570 if (mask != entry_mask || val != entry_val)
2571 err = -EINVAL;
2572out:
2573 return err;
038d2ef8
MG		 2574}
2575
37da2a03 2576static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2d1e697e
MR		 2577 bool inner)
2578{
2579 if (inner) {
2580 MLX5_SET(fte_match_set_misc,
2581 misc_c, inner_ipv6_flow_label, mask);
2582 MLX5_SET(fte_match_set_misc,
2583 misc_v, inner_ipv6_flow_label, val);
2584 } else {
2585 MLX5_SET(fte_match_set_misc,
2586 misc_c, outer_ipv6_flow_label, mask);
2587 MLX5_SET(fte_match_set_misc,
2588 misc_v, outer_ipv6_flow_label, val);
2589 }
2590}
2591
ca0d4753
MG		 2592static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2593{
2594 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2595 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2596 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2597 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2598}
2599
71c6e863
AL		 2600static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2601{
2602 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2603 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2604 return -EOPNOTSUPP;
2605
2606 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2607 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2608 return -EOPNOTSUPP;
2609
2610 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2611 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2612 return -EOPNOTSUPP;
2613
2614 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2615 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2616 return -EOPNOTSUPP;
2617
2618 return 0;
2619}
2620
c47ac6ae
MG		 2621#define LAST_ETH_FIELD vlan_tag
2622#define LAST_IB_FIELD sl
ca0d4753 2623#define LAST_IPV4_FIELD tos
466fa6d2 2624#define LAST_IPV6_FIELD traffic_class
c47ac6ae 2625#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 2626#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 2627#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 2628#define LAST_DROP_FIELD size
3b3233fb 2629#define LAST_COUNTERS_FIELD counters
c47ac6ae
MG		 2630
2631/* Field is the last supported field */
2632#define FIELDS_NOT_SUPPORTED(filter, field)\
2633 memchr_inv((void *)&filter.field +\
2634 sizeof(filter.field), 0,\
2635 sizeof(filter) -\
2636 offsetof(typeof(filter), field) -\
2637 sizeof(filter.field))
2638
2ea26203
MB		 2639int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
2640 bool is_egress,
2641 struct mlx5_flow_act *action)
802c2125 2642{
802c2125
AY		 2643
2644 switch (maction->ib_action.type) {
2645 case IB_FLOW_ACTION_ESP:
501f14e3
MB		 2646 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2647 MLX5_FLOW_CONTEXT_ACTION_DECRYPT))
2648 return -EINVAL;
802c2125
AY		 2649 /* Currently only AES_GCM keymat is supported by the driver */
2650 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2ea26203 2651 action->action |= is_egress ?
802c2125
AY		 2652 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2653 MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2654 return 0;
b1085be3
MB		 2655 case IB_FLOW_ACTION_UNSPECIFIED:
2656 if (maction->flow_action_raw.sub_type ==
2657 MLX5_IB_FLOW_ACTION_MODIFY_HEADER) {
501f14e3
MB		 2658 if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2659 return -EINVAL;
b1085be3
MB		 2660 action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2661 action->modify_id = maction->flow_action_raw.action_id;
2662 return 0;
2663 }
10a30896
MB		 2664 if (maction->flow_action_raw.sub_type ==
2665 MLX5_IB_FLOW_ACTION_DECAP) {
501f14e3
MB		 2666 if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP)
2667 return -EINVAL;
10a30896
MB		 2668 action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2669 return 0;
2670 }
e806f932
MB		 2671 if (maction->flow_action_raw.sub_type ==
2672 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) {
501f14e3
MB		 2673 if (action->action &
2674 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT)
2675 return -EINVAL;
e806f932
MB		 2676 action->action |=
2677 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
2678 action->reformat_id =
2679 maction->flow_action_raw.action_id;
2680 return 0;
2681 }
b1085be3 2682 /* fall through */
802c2125
AY		 2683 default:
2684 return -EOPNOTSUPP;
2685 }
2686}
2687
bb0ee7dc
JL		 2688static int parse_flow_attr(struct mlx5_core_dev *mdev,
2689 struct mlx5_flow_spec *spec,
2690 const union ib_flow_spec *ib_spec,
802c2125 2691 const struct ib_flow_attr *flow_attr,
71c6e863 2692 struct mlx5_flow_act *action, u32 prev_type)
038d2ef8 2693{
bb0ee7dc
JL		 2694 struct mlx5_flow_context *flow_context = &spec->flow_context;
2695 u32 *match_c = spec->match_criteria;
2696 u32 *match_v = spec->match_value;
466fa6d2
MG		 2697 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2698 misc_parameters);
2699 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2700 misc_parameters);
71c6e863
AL		 2701 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2702 misc_parameters_2);
2703 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2704 misc_parameters_2);
2d1e697e
MR		 2705 void *headers_c;
2706 void *headers_v;
19cc7524 2707 int match_ipv;
802c2125 2708 int ret;
2d1e697e
MR		 2709
2710 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2711 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2712 inner_headers);
2713 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2714 inner_headers);
19cc7524
AL		 2715 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2716 ft_field_support.inner_ip_version);
2d1e697e
MR		 2717 } else {
2718 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2719 outer_headers);
2720 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2721 outer_headers);
19cc7524
AL		 2722 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2723 ft_field_support.outer_ip_version);
2d1e697e 2724 }
466fa6d2 2725
2d1e697e 2726 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 2727 case IB_FLOW_SPEC_ETH:
c47ac6ae 2728 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 2729 return -EOPNOTSUPP;
038d2ef8 2730
2d1e697e 2731 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2732 dmac_47_16),
2733 ib_spec->eth.mask.dst_mac);
2d1e697e 2734 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2735 dmac_47_16),
2736 ib_spec->eth.val.dst_mac);
2737
2d1e697e 2738 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 2739 smac_47_16),
2740 ib_spec->eth.mask.src_mac);
2d1e697e 2741 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 2742 smac_47_16),
2743 ib_spec->eth.val.src_mac);
2744
038d2ef8 2745 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 2746 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 2747 cvlan_tag, 1);
2d1e697e 2748 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 2749 cvlan_tag, 1);
038d2ef8 2750
2d1e697e 2751 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2752 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 2753 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2754 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2755
2d1e697e 2756 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2757 first_cfi,
2758 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 2759 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2760 first_cfi,
2761 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2762
2d1e697e 2763 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2764 first_prio,
2765 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 2766 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2767 first_prio,
2768 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2769 }
2d1e697e 2770 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2771 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 2772 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2773 ethertype, ntohs(ib_spec->eth.val.ether_type));
2774 break;
2775 case IB_FLOW_SPEC_IPV4:
c47ac6ae 2776 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 2777 return -EOPNOTSUPP;
038d2ef8 2778
19cc7524
AL		 2779 if (match_ipv) {
2780 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2781 ip_version, 0xf);
2782 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2783 ip_version, MLX5_FS_IPV4_VERSION);
19cc7524
AL		 2784 } else {
2785 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2786 ethertype, 0xffff);
2787 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2788 ethertype, ETH_P_IP);
2789 }
038d2ef8 2790
2d1e697e 2791 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2792 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2793 &ib_spec->ipv4.mask.src_ip,
2794 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 2795 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2796 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2797 &ib_spec->ipv4.val.src_ip,
2798 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 2799 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2800 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2801 &ib_spec->ipv4.mask.dst_ip,
2802 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 2803 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2804 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2805 &ib_spec->ipv4.val.dst_ip,
2806 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 2807
2d1e697e 2808 set_tos(headers_c, headers_v,
ca0d4753
MG		 2809 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2810
6113cc44
MG		 2811 if (set_proto(headers_c, headers_v,
2812 ib_spec->ipv4.mask.proto,
2813 ib_spec->ipv4.val.proto))
2814 return -EINVAL;
038d2ef8 2815 break;
026bae0c 2816 case IB_FLOW_SPEC_IPV6:
c47ac6ae 2817 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 2818 return -EOPNOTSUPP;
026bae0c 2819
19cc7524
AL		 2820 if (match_ipv) {
2821 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2822 ip_version, 0xf);
2823 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2824 ip_version, MLX5_FS_IPV6_VERSION);
19cc7524
AL		 2825 } else {
2826 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2827 ethertype, 0xffff);
2828 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2829 ethertype, ETH_P_IPV6);
2830 }
026bae0c 2831
2d1e697e 2832 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2833 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2834 &ib_spec->ipv6.mask.src_ip,
2835 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2836 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2837 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2838 &ib_spec->ipv6.val.src_ip,
2839 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2840 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2841 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2842 &ib_spec->ipv6.mask.dst_ip,
2843 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2844 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2845 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2846 &ib_spec->ipv6.val.dst_ip,
2847 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2848
2d1e697e 2849 set_tos(headers_c, headers_v,
466fa6d2
MG		 2850 ib_spec->ipv6.mask.traffic_class,
2851 ib_spec->ipv6.val.traffic_class);
2852
6113cc44
MG		 2853 if (set_proto(headers_c, headers_v,
2854 ib_spec->ipv6.mask.next_hdr,
2855 ib_spec->ipv6.val.next_hdr))
2856 return -EINVAL;
466fa6d2 2857
2d1e697e
MR		 2858 set_flow_label(misc_params_c, misc_params_v,
2859 ntohl(ib_spec->ipv6.mask.flow_label),
2860 ntohl(ib_spec->ipv6.val.flow_label),
2861 ib_spec->type & IB_FLOW_SPEC_INNER);
802c2125
AY		 2862 break;
2863 case IB_FLOW_SPEC_ESP:
2864 if (ib_spec->esp.mask.seq)
2865 return -EOPNOTSUPP;
2d1e697e 2866
802c2125
AY		 2867 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2868 ntohl(ib_spec->esp.mask.spi));
2869 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2870 ntohl(ib_spec->esp.val.spi));
026bae0c 2871 break;
038d2ef8 2872 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2873 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2874 LAST_TCP_UDP_FIELD))
1ffd3a26 2875 return -EOPNOTSUPP;
038d2ef8 2876
6113cc44
MG		 2877 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_TCP))
2878 return -EINVAL;
038d2ef8 2879
2d1e697e 2880 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2881 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2882 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2883 ntohs(ib_spec->tcp_udp.val.src_port));
2884
2d1e697e 2885 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2886 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2887 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2888 ntohs(ib_spec->tcp_udp.val.dst_port));
2889 break;
2890 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2891 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2892 LAST_TCP_UDP_FIELD))
1ffd3a26 2893 return -EOPNOTSUPP;
038d2ef8 2894
6113cc44
MG		 2895 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_UDP))
2896 return -EINVAL;
038d2ef8 2897
2d1e697e 2898 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2899 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2900 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2901 ntohs(ib_spec->tcp_udp.val.src_port));
2902
2d1e697e 2903 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2904 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2905 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2906 ntohs(ib_spec->tcp_udp.val.dst_port));
2907 break;
da2f22ae
AL		 2908 case IB_FLOW_SPEC_GRE:
2909 if (ib_spec->gre.mask.c_ks_res0_ver)
2910 return -EOPNOTSUPP;
2911
6113cc44
MG		 2912 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_GRE))
2913 return -EINVAL;
2914
da2f22ae
AL		 2915 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2916 0xff);
2917 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2918 IPPROTO_GRE);
2919
2920 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
a93b632c 2921 ntohs(ib_spec->gre.mask.protocol));
da2f22ae
AL		 2922 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2923 ntohs(ib_spec->gre.val.protocol));
2924
2925 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
5886a96a 2926 gre_key.nvgre.hi),
da2f22ae
AL		 2927 &ib_spec->gre.mask.key,
2928 sizeof(ib_spec->gre.mask.key));
2929 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
5886a96a 2930 gre_key.nvgre.hi),
da2f22ae
AL		 2931 &ib_spec->gre.val.key,
2932 sizeof(ib_spec->gre.val.key));
2933 break;
71c6e863
AL		 2934 case IB_FLOW_SPEC_MPLS:
2935 switch (prev_type) {
2936 case IB_FLOW_SPEC_UDP:
2937 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2938 ft_field_support.outer_first_mpls_over_udp),
2939 &ib_spec->mpls.mask.tag))
2940 return -EOPNOTSUPP;
2941
2942 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2943 outer_first_mpls_over_udp),
2944 &ib_spec->mpls.val.tag,
2945 sizeof(ib_spec->mpls.val.tag));
2946 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2947 outer_first_mpls_over_udp),
2948 &ib_spec->mpls.mask.tag,
2949 sizeof(ib_spec->mpls.mask.tag));
2950 break;
2951 case IB_FLOW_SPEC_GRE:
2952 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2953 ft_field_support.outer_first_mpls_over_gre),
2954 &ib_spec->mpls.mask.tag))
2955 return -EOPNOTSUPP;
2956
2957 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2958 outer_first_mpls_over_gre),
2959 &ib_spec->mpls.val.tag,
2960 sizeof(ib_spec->mpls.val.tag));
2961 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2962 outer_first_mpls_over_gre),
2963 &ib_spec->mpls.mask.tag,
2964 sizeof(ib_spec->mpls.mask.tag));
2965 break;
2966 default:
2967 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2968 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2969 ft_field_support.inner_first_mpls),
2970 &ib_spec->mpls.mask.tag))
2971 return -EOPNOTSUPP;
2972
2973 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2974 inner_first_mpls),
2975 &ib_spec->mpls.val.tag,
2976 sizeof(ib_spec->mpls.val.tag));
2977 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2978 inner_first_mpls),
2979 &ib_spec->mpls.mask.tag,
2980 sizeof(ib_spec->mpls.mask.tag));
2981 } else {
2982 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2983 ft_field_support.outer_first_mpls),
2984 &ib_spec->mpls.mask.tag))
2985 return -EOPNOTSUPP;
2986
2987 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2988 outer_first_mpls),
2989 &ib_spec->mpls.val.tag,
2990 sizeof(ib_spec->mpls.val.tag));
2991 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2992 outer_first_mpls),
2993 &ib_spec->mpls.mask.tag,
2994 sizeof(ib_spec->mpls.mask.tag));
2995 }
2996 }
2997 break;
ffb30d8f
MR		 2998 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2999 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
3000 LAST_TUNNEL_FIELD))
1ffd3a26 3001 return -EOPNOTSUPP;
ffb30d8f
MR		 3002
3003 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
3004 ntohl(ib_spec->tunnel.mask.tunnel_id));
3005 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
3006 ntohl(ib_spec->tunnel.val.tunnel_id));
3007 break;
2ac693f9
MR		 3008 case IB_FLOW_SPEC_ACTION_TAG:
3009 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
3010 LAST_FLOW_TAG_FIELD))
3011 return -EOPNOTSUPP;
3012 if (ib_spec->flow_tag.tag_id >= BIT(24))
3013 return -EINVAL;
3014
bb0ee7dc
JL		 3015 flow_context->flow_tag = ib_spec->flow_tag.tag_id;
3016 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
2ac693f9 3017 break;
a22ed86c
SS		 3018 case IB_FLOW_SPEC_ACTION_DROP:
3019 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
3020 LAST_DROP_FIELD))
3021 return -EOPNOTSUPP;
075572d4 3022 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
a22ed86c 3023 break;
802c2125 3024 case IB_FLOW_SPEC_ACTION_HANDLE:
2ea26203
MB		 3025 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act),
3026 flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action);
802c2125
AY		 3027 if (ret)
3028 return ret;
3029 break;
3b3233fb
RS		 3030 case IB_FLOW_SPEC_ACTION_COUNT:
3031 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
3032 LAST_COUNTERS_FIELD))
3033 return -EOPNOTSUPP;
3034
3035 /* for now support only one counters spec per flow */
3036 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
3037 return -EINVAL;
3038
3039 action->counters = ib_spec->flow_count.counters;
3040 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3041 break;
038d2ef8
MG		 3042 default:
3043 return -EINVAL;
3044 }
3045
3046 return 0;
3047}
3048
3049/* If a flow could catch both multicast and unicast packets,
3050 * it won't fall into the multicast flow steering table and this rule
3051 * could steal other multicast packets.
3052 */
a550ddfc 3053static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
038d2ef8 3054{
81e30880 3055 union ib_flow_spec *flow_spec;
038d2ef8
MG		 3056
3057 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 3058 ib_attr->num_of_specs < 1)
3059 return false;
3060
81e30880
YH		 3061 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
3062 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
3063 struct ib_flow_spec_ipv4 *ipv4_spec;
3064
3065 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
3066 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
3067 return true;
3068
038d2ef8 3069 return false;
81e30880
YH		 3070 }
3071
3072 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
3073 struct ib_flow_spec_eth *eth_spec;
3074
3075 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
3076 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
3077 is_multicast_ether_addr(eth_spec->val.dst_mac);
3078 }
038d2ef8 3079
81e30880 3080 return false;
038d2ef8
MG		 3081}
3082
802c2125
AY		 3083enum valid_spec {
3084 VALID_SPEC_INVALID,
3085 VALID_SPEC_VALID,
3086 VALID_SPEC_NA,
3087};
3088
3089static enum valid_spec
3090is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
3091 const struct mlx5_flow_spec *spec,
3092 const struct mlx5_flow_act *flow_act,
3093 bool egress)
3094{
3095 const u32 *match_c = spec->match_criteria;
3096 bool is_crypto =
3097 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
3098 MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
3099 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
3100 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
3101
3102 /*
3103 * Currently only crypto is supported in egress, when regular egress
3104 * rules would be supported, always return VALID_SPEC_NA.
3105 */
3106 if (!is_crypto)
78dd0c43 3107 return VALID_SPEC_NA;
802c2125
AY		 3108
3109 return is_crypto && is_ipsec &&
bb0ee7dc
JL		 3110 (!egress || (!is_drop &&
3111 !(spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG))) ?
802c2125
AY		 3112 VALID_SPEC_VALID : VALID_SPEC_INVALID;
3113}
3114
3115static bool is_valid_spec(struct mlx5_core_dev *mdev,
3116 const struct mlx5_flow_spec *spec,
3117 const struct mlx5_flow_act *flow_act,
3118 bool egress)
3119{
3120 /* We curretly only support ipsec egress flow */
3121 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
3122}
3123
19cc7524
AL		 3124static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
3125 const struct ib_flow_attr *flow_attr,
0f750966 3126 bool check_inner)
038d2ef8
MG		 3127{
3128 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 3129 int match_ipv = check_inner ?
3130 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3131 ft_field_support.inner_ip_version) :
3132 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3133 ft_field_support.outer_ip_version);
0f750966
AL		 3134 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
3135 bool ipv4_spec_valid, ipv6_spec_valid;
3136 unsigned int ip_spec_type = 0;
3137 bool has_ethertype = false;
038d2ef8 3138 unsigned int spec_index;
0f750966
AL		 3139 bool mask_valid = true;
3140 u16 eth_type = 0;
3141 bool type_valid;
038d2ef8
MG		 3142
3143 /* Validate that ethertype is correct */
3144 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 3145 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 3146 ib_spec->eth.mask.ether_type) {
0f750966
AL		 3147 mask_valid = (ib_spec->eth.mask.ether_type ==
3148 htons(0xffff));
3149 has_ethertype = true;
3150 eth_type = ntohs(ib_spec->eth.val.ether_type);
3151 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
3152 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
3153 ip_spec_type = ib_spec->type;
038d2ef8
MG		 3154 }
3155 ib_spec = (void *)ib_spec + ib_spec->size;
3156 }
0f750966
AL		 3157
3158 type_valid = (!has_ethertype) || (!ip_spec_type);
3159 if (!type_valid && mask_valid) {
3160 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
3161 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
3162 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
3163 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 3164
3165 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
3166 (((eth_type == ETH_P_MPLS_UC) ||
3167 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 3168 }
3169
3170 return type_valid;
3171}
3172
19cc7524
AL		 3173static bool is_valid_attr(struct mlx5_core_dev *mdev,
3174 const struct ib_flow_attr *flow_attr)
0f750966 3175{
19cc7524
AL		 3176 return is_valid_ethertype(mdev, flow_attr, false) &&
3177 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 3178}
3179
3180static void put_flow_table(struct mlx5_ib_dev *dev,
3181 struct mlx5_ib_flow_prio *prio, bool ft_added)
3182{
3183 prio->refcount -= !!ft_added;
3184 if (!prio->refcount) {
3185 mlx5_destroy_flow_table(prio->flow_table);
3186 prio->flow_table = NULL;
3187 }
3188}
3189
3b3233fb
RS		 3190static void counters_clear_description(struct ib_counters *counters)
3191{
3192 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3193
3194 mutex_lock(&mcounters->mcntrs_mutex);
3195 kfree(mcounters->counters_data);
3196 mcounters->counters_data = NULL;
3197 mcounters->cntrs_max_index = 0;
3198 mutex_unlock(&mcounters->mcntrs_mutex);
3199}
3200
038d2ef8
MG		 3201static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
3202{
038d2ef8
MG		 3203 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
3204 struct mlx5_ib_flow_handler,
3205 ibflow);
3206 struct mlx5_ib_flow_handler *iter, *tmp;
d4be3f44 3207 struct mlx5_ib_dev *dev = handler->dev;
038d2ef8 3208
9a4ca38d 3209 mutex_lock(&dev->flow_db->lock);
038d2ef8
MG		 3210
3211 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 3212 mlx5_del_flow_rules(iter->rule);
cc0e5d42 3213 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 3214 list_del(&iter->list);
3215 kfree(iter);
3216 }
3217
74491de9 3218 mlx5_del_flow_rules(handler->rule);
5497adc6 3219 put_flow_table(dev, handler->prio, true);
3b3233fb
RS		 3220 if (handler->ibcounters &&
3221 atomic_read(&handler->ibcounters->usecnt) == 1)
3222 counters_clear_description(handler->ibcounters);
038d2ef8 3223
3b3233fb 3224 mutex_unlock(&dev->flow_db->lock);
d4be3f44
YH		 3225 if (handler->flow_matcher)
3226 atomic_dec(&handler->flow_matcher->usecnt);
038d2ef8
MG		 3227 kfree(handler);
3228
3229 return 0;
3230}
3231
35d19011
MG		 3232static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
3233{
3234 priority *= 2;
3235 if (!dont_trap)
3236 priority++;
3237 return priority;
3238}
3239
cc0e5d42
MG		 3240enum flow_table_type {
3241 MLX5_IB_FT_RX,
3242 MLX5_IB_FT_TX
3243};
3244
00b7c2ab
MG		 3245#define MLX5_FS_MAX_TYPES 6
3246#define MLX5_FS_MAX_ENTRIES BIT(16)
d4be3f44
YH		 3247
3248static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns,
3249 struct mlx5_ib_flow_prio *prio,
3250 int priority,
4adda112
MB		 3251 int num_entries, int num_groups,
3252 u32 flags)
d4be3f44
YH		 3253{
3254 struct mlx5_flow_table *ft;
3255
3256 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3257 num_entries,
3258 num_groups,
4adda112 3259 0, flags);
d4be3f44
YH		 3260 if (IS_ERR(ft))
3261 return ERR_CAST(ft);
3262
3263 prio->flow_table = ft;
3264 prio->refcount = 0;
3265 return prio;
3266}
3267
038d2ef8 3268static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 3269 struct ib_flow_attr *flow_attr,
3270 enum flow_table_type ft_type)
038d2ef8 3271{
35d19011 3272 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 3273 struct mlx5_flow_namespace *ns = NULL;
3274 struct mlx5_ib_flow_prio *prio;
3275 struct mlx5_flow_table *ft;
dac388ef 3276 int max_table_size;
038d2ef8
MG		 3277 int num_entries;
3278 int num_groups;
cecae747 3279 bool esw_encap;
4adda112 3280 u32 flags = 0;
038d2ef8 3281 int priority;
038d2ef8 3282
dac388ef
MG		 3283 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3284 log_max_ft_size));
cecae747
MG		 3285 esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
3286 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
038d2ef8 3287 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
78dd0c43
MB		 3288 enum mlx5_flow_namespace_type fn_type;
3289
3290 if (flow_is_multicast_only(flow_attr) &&
3291 !dont_trap)
038d2ef8
MG		 3292 priority = MLX5_IB_FLOW_MCAST_PRIO;
3293 else
35d19011
MG		 3294 priority = ib_prio_to_core_prio(flow_attr->priority,
3295 dont_trap);
78dd0c43
MB		 3296 if (ft_type == MLX5_IB_FT_RX) {
3297 fn_type = MLX5_FLOW_NAMESPACE_BYPASS;
3298 prio = &dev->flow_db->prios[priority];
cecae747 3299 if (!dev->is_rep && !esw_encap &&
4adda112
MB		 3300 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3301 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
cecae747 3302 if (!dev->is_rep && !esw_encap &&
5c2db53f
MB		 3303 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3304 reformat_l3_tunnel_to_l2))
3305 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
78dd0c43
MB		 3306 } else {
3307 max_table_size =
3308 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3309 log_max_ft_size));
3310 fn_type = MLX5_FLOW_NAMESPACE_EGRESS;
3311 prio = &dev->flow_db->egress_prios[priority];
cecae747 3312 if (!dev->is_rep && !esw_encap &&
4adda112
MB		 3313 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3314 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
78dd0c43
MB		 3315 }
3316 ns = mlx5_get_flow_namespace(dev->mdev, fn_type);
038d2ef8
MG		 3317 num_entries = MLX5_FS_MAX_ENTRIES;
3318 num_groups = MLX5_FS_MAX_TYPES;
038d2ef8
MG		 3319 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3320 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3321 ns = mlx5_get_flow_namespace(dev->mdev,
3322 MLX5_FLOW_NAMESPACE_LEFTOVERS);
3323 build_leftovers_ft_param(&priority,
3324 &num_entries,
3325 &num_groups);
9a4ca38d 3326 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 3327 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3328 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3329 allow_sniffer_and_nic_rx_shared_tir))
3330 return ERR_PTR(-ENOTSUPP);
3331
3332 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3333 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3334 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3335
9a4ca38d 3336 prio = &dev->flow_db->sniffer[ft_type];
cc0e5d42
MG		 3337 priority = 0;
3338 num_entries = 1;
3339 num_groups = 1;
038d2ef8
MG		 3340 }
3341
3342 if (!ns)
3343 return ERR_PTR(-ENOTSUPP);
3344
3b70508a 3345 max_table_size = min_t(int, num_entries, max_table_size);
dac388ef 3346
038d2ef8 3347 ft = prio->flow_table;
d4be3f44 3348 if (!ft)
3b70508a 3349 return _get_prio(ns, prio, priority, max_table_size, num_groups,
4adda112 3350 flags);
038d2ef8 3351
d4be3f44 3352 return prio;
038d2ef8
MG		 3353}
3354
a550ddfc
YH		 3355static void set_underlay_qp(struct mlx5_ib_dev *dev,
3356 struct mlx5_flow_spec *spec,
3357 u32 underlay_qpn)
3358{
3359 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3360 spec->match_criteria,
3361 misc_parameters);
3362 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3363 misc_parameters);
3364
3365 if (underlay_qpn &&
3366 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3367 ft_field_support.bth_dst_qp)) {
3368 MLX5_SET(fte_match_set_misc,
3369 misc_params_v, bth_dst_qp, underlay_qpn);
3370 MLX5_SET(fte_match_set_misc,
3371 misc_params_c, bth_dst_qp, 0xffffff);
3372 }
3373}
3374
5e95af5f
RS		 3375static int read_flow_counters(struct ib_device *ibdev,
3376 struct mlx5_read_counters_attr *read_attr)
3377{
3378 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3379 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3380
3381 return mlx5_fc_query(dev->mdev, fc,
3382 &read_attr->out[IB_COUNTER_PACKETS],
3383 &read_attr->out[IB_COUNTER_BYTES]);
3384}
3385
3386/* flow counters currently expose two counters packets and bytes */
3387#define FLOW_COUNTERS_NUM 2
3b3233fb
RS		 3388static int counters_set_description(struct ib_counters *counters,
3389 enum mlx5_ib_counters_type counters_type,
3390 struct mlx5_ib_flow_counters_desc *desc_data,
3391 u32 ncounters)
3392{
3393 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3394 u32 cntrs_max_index = 0;
3395 int i;
3396
3397 if (counters_type != MLX5_IB_COUNTERS_FLOW)
3398 return -EINVAL;
3399
3400 /* init the fields for the object */
3401 mcounters->type = counters_type;
5e95af5f
RS		 3402 mcounters->read_counters = read_flow_counters;
3403 mcounters->counters_num = FLOW_COUNTERS_NUM;
3b3233fb
RS		 3404 mcounters->ncounters = ncounters;
3405 /* each counter entry have both description and index pair */
3406 for (i = 0; i < ncounters; i++) {
3407 if (desc_data[i].description > IB_COUNTER_BYTES)
3408 return -EINVAL;
3409
3410 if (cntrs_max_index <= desc_data[i].index)
3411 cntrs_max_index = desc_data[i].index + 1;
3412 }
3413
3414 mutex_lock(&mcounters->mcntrs_mutex);
3415 mcounters->counters_data = desc_data;
3416 mcounters->cntrs_max_index = cntrs_max_index;
3417 mutex_unlock(&mcounters->mcntrs_mutex);
3418
3419 return 0;
3420}
3421
3422#define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3423static int flow_counters_set_data(struct ib_counters *ibcounters,
3424 struct mlx5_ib_create_flow *ucmd)
3425{
3426 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3427 struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3428 struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3429 bool hw_hndl = false;
3430 int ret = 0;
3431
3432 if (ucmd && ucmd->ncounters_data != 0) {
3433 cntrs_data = ucmd->data;
3434 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3435 return -EINVAL;
3436
3437 desc_data = kcalloc(cntrs_data->ncounters,
3438 sizeof(*desc_data),
3439 GFP_KERNEL);
3440 if (!desc_data)
3441 return -ENOMEM;
3442
3443 if (copy_from_user(desc_data,
3444 u64_to_user_ptr(cntrs_data->counters_data),
3445 sizeof(*desc_data) * cntrs_data->ncounters)) {
3446 ret = -EFAULT;
3447 goto free;
3448 }
3449 }
3450
3451 if (!mcounters->hw_cntrs_hndl) {
3452 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3453 to_mdev(ibcounters->device)->mdev, false);
e31abf76 3454 if (IS_ERR(mcounters->hw_cntrs_hndl)) {
3455 ret = PTR_ERR(mcounters->hw_cntrs_hndl);
3b3233fb
RS		 3456 goto free;
3457 }
3458 hw_hndl = true;
3459 }
3460
3461 if (desc_data) {
3462 /* counters already bound to at least one flow */
3463 if (mcounters->cntrs_max_index) {
3464 ret = -EINVAL;
3465 goto free_hndl;
3466 }
3467
3468 ret = counters_set_description(ibcounters,
3469 MLX5_IB_COUNTERS_FLOW,
3470 desc_data,
3471 cntrs_data->ncounters);
3472 if (ret)
3473 goto free_hndl;
3474
3475 } else if (!mcounters->cntrs_max_index) {
3476 /* counters not bound yet, must have udata passed */
3477 ret = -EINVAL;
3478 goto free_hndl;
3479 }
3480
3481 return 0;
3482
3483free_hndl:
3484 if (hw_hndl) {
3485 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3486 mcounters->hw_cntrs_hndl);
3487 mcounters->hw_cntrs_hndl = NULL;
3488 }
3489free:
3490 kfree(desc_data);
3491 return ret;
3492}
3493
669ff1e3
JL		 3494static void mlx5_ib_set_rule_source_port(struct mlx5_ib_dev *dev,
3495 struct mlx5_flow_spec *spec,
3496 struct mlx5_eswitch_rep *rep)
3497{
3498 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
3499 void *misc;
3500
3501 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
3502 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3503 misc_parameters_2);
3504
3505 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
3506 mlx5_eswitch_get_vport_metadata_for_match(esw,
3507 rep->vport));
3508 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3509 misc_parameters_2);
3510
3511 MLX5_SET_TO_ONES(fte_match_set_misc2, misc, metadata_reg_c_0);
3512 } else {
3513 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3514 misc_parameters);
3515
3516 MLX5_SET(fte_match_set_misc, misc, source_port, rep->vport);
3517
3518 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3519 misc_parameters);
3520
3521 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3522 }
3523}
3524
a550ddfc
YH		 3525static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3526 struct mlx5_ib_flow_prio *ft_prio,
3527 const struct ib_flow_attr *flow_attr,
3528 struct mlx5_flow_destination *dst,
3b3233fb
RS		 3529 u32 underlay_qpn,
3530 struct mlx5_ib_create_flow *ucmd)
038d2ef8
MG		 3531{
3532 struct mlx5_flow_table *ft = ft_prio->flow_table;
3533 struct mlx5_ib_flow_handler *handler;
bb0ee7dc 3534 struct mlx5_flow_act flow_act = {};
c5bb1730 3535 struct mlx5_flow_spec *spec;
3b3233fb
RS		 3536 struct mlx5_flow_destination dest_arr[2] = {};
3537 struct mlx5_flow_destination *rule_dst = dest_arr;
dd063d0e 3538 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 3539 unsigned int spec_index;
71c6e863 3540 u32 prev_type = 0;
038d2ef8 3541 int err = 0;
3b3233fb 3542 int dest_num = 0;
802c2125 3543 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
038d2ef8 3544
19cc7524 3545 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 3546 return ERR_PTR(-EINVAL);
3547
6a4d00be 3548 if (dev->is_rep && is_egress)
78dd0c43
MB		 3549 return ERR_PTR(-EINVAL);
3550
1b9a07ee 3551 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 3552 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 3553 if (!handler || !spec) {
038d2ef8
MG		 3554 err = -ENOMEM;
3555 goto free;
3556 }
3557
3558 INIT_LIST_HEAD(&handler->list);
3b3233fb
RS		 3559 if (dst) {
3560 memcpy(&dest_arr[0], dst, sizeof(*dst));
3561 dest_num++;
3562 }
038d2ef8
MG		 3563
3564 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
bb0ee7dc 3565 err = parse_flow_attr(dev->mdev, spec,
71c6e863
AL		 3566 ib_flow, flow_attr, &flow_act,
3567 prev_type);
038d2ef8
MG		 3568 if (err < 0)
3569 goto free;
3570
71c6e863 3571 prev_type = ((union ib_flow_spec *)ib_flow)->type;
038d2ef8
MG		 3572 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3573 }
3574
a550ddfc
YH		 3575 if (!flow_is_multicast_only(flow_attr))
3576 set_underlay_qp(dev, spec, underlay_qpn);
3577
6a4d00be 3578 if (dev->is_rep) {
669ff1e3 3579 struct mlx5_eswitch_rep *rep;
018a94ee 3580
669ff1e3
JL		 3581 rep = dev->port[flow_attr->port - 1].rep;
3582 if (!rep) {
6a4d00be
MB		 3583 err = -EINVAL;
3584 goto free;
3585 }
669ff1e3
JL		 3586
3587 mlx5_ib_set_rule_source_port(dev, spec, rep);
018a94ee
MB		 3588 }
3589
466fa6d2 3590 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
802c2125
AY		 3591
3592 if (is_egress &&
3593 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3594 err = -EINVAL;
3595 goto free;
3596 }
3597
3b3233fb 3598 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
171c7625
MB		 3599 struct mlx5_ib_mcounters *mcounters;
3600
3b3233fb
RS		 3601 err = flow_counters_set_data(flow_act.counters, ucmd);
3602 if (err)
3603 goto free;
3604
171c7625 3605 mcounters = to_mcounters(flow_act.counters);
3b3233fb
RS		 3606 handler->ibcounters = flow_act.counters;
3607 dest_arr[dest_num].type =
3608 MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625
MB		 3609 dest_arr[dest_num].counter_id =
3610 mlx5_fc_id(mcounters->hw_cntrs_hndl);
3b3233fb
RS		 3611 dest_num++;
3612 }
3613
075572d4 3614 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3b3233fb
RS		 3615 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) {
3616 rule_dst = NULL;
3617 dest_num = 0;
3618 }
a22ed86c 3619 } else {
802c2125
AY		 3620 if (is_egress)
3621 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3622 else
3623 flow_act.action |=
3b3233fb 3624 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
802c2125 3625 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
a22ed86c 3626 }
2ac693f9 3627
bb0ee7dc 3628 if ((spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG) &&
2ac693f9
MR		 3629 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3630 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3631 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
bb0ee7dc 3632 spec->flow_context.flow_tag, flow_attr->type);
2ac693f9
MR		 3633 err = -EINVAL;
3634 goto free;
3635 }
74491de9 3636 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 3637 &flow_act,
a22ed86c 3638 rule_dst, dest_num);
038d2ef8
MG		 3639
3640 if (IS_ERR(handler->rule)) {
3641 err = PTR_ERR(handler->rule);
3642 goto free;
3643 }
3644
d9d4980a 3645 ft_prio->refcount++;
5497adc6 3646 handler->prio = ft_prio;
d4be3f44 3647 handler->dev = dev;
038d2ef8
MG		 3648
3649 ft_prio->flow_table = ft;
3650free:
3b3233fb
RS		 3651 if (err && handler) {
3652 if (handler->ibcounters &&
3653 atomic_read(&handler->ibcounters->usecnt) == 1)
3654 counters_clear_description(handler->ibcounters);
038d2ef8 3655 kfree(handler);
3b3233fb 3656 }
c5bb1730 3657 kvfree(spec);
038d2ef8
MG		 3658 return err ? ERR_PTR(err) : handler;
3659}
3660
a550ddfc
YH		 3661static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3662 struct mlx5_ib_flow_prio *ft_prio,
3663 const struct ib_flow_attr *flow_attr,
3664 struct mlx5_flow_destination *dst)
3665{
3b3233fb 3666 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
a550ddfc
YH		 3667}
3668
35d19011
MG		 3669static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3670 struct mlx5_ib_flow_prio *ft_prio,
3671 struct ib_flow_attr *flow_attr,
3672 struct mlx5_flow_destination *dst)
3673{
3674 struct mlx5_ib_flow_handler *handler_dst = NULL;
3675 struct mlx5_ib_flow_handler *handler = NULL;
3676
3677 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3678 if (!IS_ERR(handler)) {
3679 handler_dst = create_flow_rule(dev, ft_prio,
3680 flow_attr, dst);
3681 if (IS_ERR(handler_dst)) {
74491de9 3682 mlx5_del_flow_rules(handler->rule);
d9d4980a 3683 ft_prio->refcount--;
35d19011
MG		 3684 kfree(handler);
3685 handler = handler_dst;
3686 } else {
3687 list_add(&handler_dst->list, &handler->list);
3688 }
3689 }
3690
3691 return handler;
3692}
038d2ef8
MG		 3693enum {
3694 LEFTOVERS_MC,
3695 LEFTOVERS_UC,
3696};
3697
3698static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3699 struct mlx5_ib_flow_prio *ft_prio,
3700 struct ib_flow_attr *flow_attr,
3701 struct mlx5_flow_destination *dst)
3702{
3703 struct mlx5_ib_flow_handler *handler_ucast = NULL;
3704 struct mlx5_ib_flow_handler *handler = NULL;
3705
3706 static struct {
3707 struct ib_flow_attr flow_attr;
3708 struct ib_flow_spec_eth eth_flow;
3709 } leftovers_specs[] = {
3710 [LEFTOVERS_MC] = {
3711 .flow_attr = {
3712 .num_of_specs = 1,
3713 .size = sizeof(leftovers_specs[0])
3714 },
3715 .eth_flow = {
3716 .type = IB_FLOW_SPEC_ETH,
3717 .size = sizeof(struct ib_flow_spec_eth),
3718 .mask = {.dst_mac = {0x1} },
3719 .val = {.dst_mac = {0x1} }
3720 }
3721 },
3722 [LEFTOVERS_UC] = {
3723 .flow_attr = {
3724 .num_of_specs = 1,
3725 .size = sizeof(leftovers_specs[0])
3726 },
3727 .eth_flow = {
3728 .type = IB_FLOW_SPEC_ETH,
3729 .size = sizeof(struct ib_flow_spec_eth),
3730 .mask = {.dst_mac = {0x1} },
3731 .val = {.dst_mac = {} }
3732 }
3733 }
3734 };
3735
3736 handler = create_flow_rule(dev, ft_prio,
3737 &leftovers_specs[LEFTOVERS_MC].flow_attr,
3738 dst);
3739 if (!IS_ERR(handler) &&
3740 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3741 handler_ucast = create_flow_rule(dev, ft_prio,
3742 &leftovers_specs[LEFTOVERS_UC].flow_attr,
3743 dst);
3744 if (IS_ERR(handler_ucast)) {
74491de9 3745 mlx5_del_flow_rules(handler->rule);
d9d4980a 3746 ft_prio->refcount--;
038d2ef8
MG		 3747 kfree(handler);
3748 handler = handler_ucast;
3749 } else {
3750 list_add(&handler_ucast->list, &handler->list);
3751 }
3752 }
3753
3754 return handler;
3755}
3756
cc0e5d42
MG		 3757static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3758 struct mlx5_ib_flow_prio *ft_rx,
3759 struct mlx5_ib_flow_prio *ft_tx,
3760 struct mlx5_flow_destination *dst)
3761{
3762 struct mlx5_ib_flow_handler *handler_rx;
3763 struct mlx5_ib_flow_handler *handler_tx;
3764 int err;
3765 static const struct ib_flow_attr flow_attr = {
3766 .num_of_specs = 0,
3767 .size = sizeof(flow_attr)
3768 };
3769
3770 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3771 if (IS_ERR(handler_rx)) {
3772 err = PTR_ERR(handler_rx);
3773 goto err;
3774 }
3775
3776 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3777 if (IS_ERR(handler_tx)) {
3778 err = PTR_ERR(handler_tx);
3779 goto err_tx;
3780 }
3781
3782 list_add(&handler_tx->list, &handler_rx->list);
3783
3784 return handler_rx;
3785
3786err_tx:
74491de9 3787 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 3788 ft_rx->refcount--;
3789 kfree(handler_rx);
3790err:
3791 return ERR_PTR(err);
3792}
3793
038d2ef8
MG		 3794static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3795 struct ib_flow_attr *flow_attr,
59082a32
MB		 3796 int domain,
3797 struct ib_udata *udata)
038d2ef8
MG		 3798{
3799 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 3800 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 3801 struct mlx5_ib_flow_handler *handler = NULL;
3802 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 3803 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8 3804 struct mlx5_ib_flow_prio *ft_prio;
802c2125 3805 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3b3233fb
RS		 3806 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3807 size_t min_ucmd_sz, required_ucmd_sz;
038d2ef8 3808 int err;
a550ddfc 3809 int underlay_qpn;
038d2ef8 3810
3b3233fb
RS		 3811 if (udata && udata->inlen) {
3812 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3813 sizeof(ucmd_hdr.reserved);
3814 if (udata->inlen < min_ucmd_sz)
3815 return ERR_PTR(-EOPNOTSUPP);
3816
3817 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3818 if (err)
3819 return ERR_PTR(err);
3820
3821 /* currently supports only one counters data */
3822 if (ucmd_hdr.ncounters_data > 1)
3823 return ERR_PTR(-EINVAL);
3824
3825 required_ucmd_sz = min_ucmd_sz +
3826 sizeof(struct mlx5_ib_flow_counters_data) *
3827 ucmd_hdr.ncounters_data;
3828 if (udata->inlen > required_ucmd_sz &&
3829 !ib_is_udata_cleared(udata, required_ucmd_sz,
3830 udata->inlen - required_ucmd_sz))
3831 return ERR_PTR(-EOPNOTSUPP);
3832
3833 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3834 if (!ucmd)
3835 return ERR_PTR(-ENOMEM);
3836
3837 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
299eafee
GS		 3838 if (err)
3839 goto free_ucmd;
3b3233fb 3840 }
59082a32 3841
299eafee
GS		 3842 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) {
3843 err = -ENOMEM;
3844 goto free_ucmd;
3845 }
038d2ef8
MG		 3846
3847 if (domain != IB_FLOW_DOMAIN_USER ||
508562d6 3848 flow_attr->port > dev->num_ports ||
802c2125 3849 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
299eafee
GS		 3850 IB_FLOW_ATTR_FLAGS_EGRESS))) {
3851 err = -EINVAL;
3852 goto free_ucmd;
3853 }
802c2125
AY		 3854
3855 if (is_egress &&
3856 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
299eafee
GS		 3857 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3858 err = -EINVAL;
3859 goto free_ucmd;
3860 }
038d2ef8
MG		 3861
3862 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
299eafee
GS		 3863 if (!dst) {
3864 err = -ENOMEM;
3865 goto free_ucmd;
3866 }
038d2ef8 3867
9a4ca38d 3868 mutex_lock(&dev->flow_db->lock);
038d2ef8 3869
802c2125
AY		 3870 ft_prio = get_flow_table(dev, flow_attr,
3871 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
038d2ef8
MG		 3872 if (IS_ERR(ft_prio)) {
3873 err = PTR_ERR(ft_prio);
3874 goto unlock;
3875 }
cc0e5d42
MG		 3876 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3877 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3878 if (IS_ERR(ft_prio_tx)) {
3879 err = PTR_ERR(ft_prio_tx);
3880 ft_prio_tx = NULL;
3881 goto destroy_ft;
3882 }
3883 }
038d2ef8 3884
802c2125
AY		 3885 if (is_egress) {
3886 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3887 } else {
3888 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3889 if (mqp->flags & MLX5_IB_QP_RSS)
3890 dst->tir_num = mqp->rss_qp.tirn;
3891 else
3892 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3893 }
038d2ef8
MG		 3894
3895 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 3896 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3897 handler = create_dont_trap_rule(dev, ft_prio,
3898 flow_attr, dst);
3899 } else {
a550ddfc
YH		 3900 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3901 mqp->underlay_qpn : 0;
3902 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3b3233fb 3903 dst, underlay_qpn, ucmd);
35d19011 3904 }
038d2ef8
MG		 3905 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3906 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3907 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3908 dst);
cc0e5d42
MG		 3909 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3910 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 3911 } else {
3912 err = -EINVAL;
3913 goto destroy_ft;
3914 }
3915
3916 if (IS_ERR(handler)) {
3917 err = PTR_ERR(handler);
3918 handler = NULL;
3919 goto destroy_ft;
3920 }
3921
9a4ca38d 3922 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3923 kfree(dst);
3b3233fb 3924 kfree(ucmd);
038d2ef8
MG		 3925
3926 return &handler->ibflow;
3927
3928destroy_ft:
3929 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 3930 if (ft_prio_tx)
3931 put_flow_table(dev, ft_prio_tx, false);
038d2ef8 3932unlock:
9a4ca38d 3933 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3934 kfree(dst);
299eafee 3935free_ucmd:
3b3233fb 3936 kfree(ucmd);
038d2ef8
MG		 3937 return ERR_PTR(err);
3938}
3939
b47fd4ff
MB		 3940static struct mlx5_ib_flow_prio *
3941_get_flow_table(struct mlx5_ib_dev *dev,
3942 struct mlx5_ib_flow_matcher *fs_matcher,
3943 bool mcast)
d4be3f44 3944{
d4be3f44 3945 struct mlx5_flow_namespace *ns = NULL;
13a43765
MB		 3946 struct mlx5_ib_flow_prio *prio = NULL;
3947 int max_table_size = 0;
cecae747 3948 bool esw_encap;
b47fd4ff
MB		 3949 u32 flags = 0;
3950 int priority;
3951
13a43765
MB		 3952 if (mcast)
3953 priority = MLX5_IB_FLOW_MCAST_PRIO;
3954 else
3955 priority = ib_prio_to_core_prio(fs_matcher->priority, false);
3956
cecae747
MG		 3957 esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
3958 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
b47fd4ff
MB		 3959 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) {
3960 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3961 log_max_ft_size));
cecae747 3962 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap) && !esw_encap)
b47fd4ff
MB		 3963 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3964 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
cecae747
MG		 3965 reformat_l3_tunnel_to_l2) &&
3966 !esw_encap)
b47fd4ff 3967 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
13a43765
MB		 3968 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS) {
3969 max_table_size = BIT(
3970 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, log_max_ft_size));
cecae747 3971 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat) && !esw_encap)
b47fd4ff 3972 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
13a43765
MB		 3973 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB) {
3974 max_table_size = BIT(
3975 MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, log_max_ft_size));
09d985be
MG		 3976 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, decap) && esw_encap)
3977 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3978 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, reformat_l3_tunnel_to_l2) &&
3979 esw_encap)
3980 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
13a43765 3981 priority = FDB_BYPASS_PATH;
b47fd4ff 3982 }
d4be3f44 3983
3b70508a 3984 max_table_size = min_t(int, max_table_size, MLX5_FS_MAX_ENTRIES);
d4be3f44 3985
b47fd4ff 3986 ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type);
d4be3f44
YH		 3987 if (!ns)
3988 return ERR_PTR(-ENOTSUPP);
3989
b47fd4ff
MB		 3990 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS)
3991 prio = &dev->flow_db->prios[priority];
13a43765 3992 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS)
b47fd4ff 3993 prio = &dev->flow_db->egress_prios[priority];
13a43765
MB		 3994 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB)
3995 prio = &dev->flow_db->fdb;
3996
3997 if (!prio)
3998 return ERR_PTR(-EINVAL);
d4be3f44
YH		 3999
4000 if (prio->flow_table)
4001 return prio;
4002
3b70508a 4003 return _get_prio(ns, prio, priority, max_table_size,
b47fd4ff 4004 MLX5_FS_MAX_TYPES, flags);
d4be3f44
YH		 4005}
4006
4007static struct mlx5_ib_flow_handler *
4008_create_raw_flow_rule(struct mlx5_ib_dev *dev,
4009 struct mlx5_ib_flow_prio *ft_prio,
4010 struct mlx5_flow_destination *dst,
4011 struct mlx5_ib_flow_matcher *fs_matcher,
bb0ee7dc 4012 struct mlx5_flow_context *flow_context,
b823dd6d 4013 struct mlx5_flow_act *flow_act,
bfc5d839
MB		 4014 void *cmd_in, int inlen,
4015 int dst_num)
d4be3f44
YH		 4016{
4017 struct mlx5_ib_flow_handler *handler;
d4be3f44
YH		 4018 struct mlx5_flow_spec *spec;
4019 struct mlx5_flow_table *ft = ft_prio->flow_table;
4020 int err = 0;
4021
4022 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
4023 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
4024 if (!handler || !spec) {
4025 err = -ENOMEM;
4026 goto free;
4027 }
4028
4029 INIT_LIST_HEAD(&handler->list);
4030
4031 memcpy(spec->match_value, cmd_in, inlen);
4032 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params,
4033 fs_matcher->mask_len);
4034 spec->match_criteria_enable = fs_matcher->match_criteria_enable;
bb0ee7dc 4035 spec->flow_context = *flow_context;
d4be3f44 4036
d4be3f44 4037 handler->rule = mlx5_add_flow_rules(ft, spec,
bfc5d839 4038 flow_act, dst, dst_num);
d4be3f44
YH		 4039
4040 if (IS_ERR(handler->rule)) {
4041 err = PTR_ERR(handler->rule);
4042 goto free;
4043 }
4044
4045 ft_prio->refcount++;
4046 handler->prio = ft_prio;
4047 handler->dev = dev;
4048 ft_prio->flow_table = ft;
4049
4050free:
4051 if (err)
4052 kfree(handler);
4053 kvfree(spec);
4054 return err ? ERR_PTR(err) : handler;
4055}
4056
4057static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher,
4058 void *match_v)
4059{
4060 void *match_c;
4061 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4;
4062 void *dmac, *dmac_mask;
4063 void *ipv4, *ipv4_mask;
4064
4065 if (!(fs_matcher->match_criteria_enable &
4066 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT)))
4067 return false;
4068
4069 match_c = fs_matcher->matcher_mask.match_params;
4070 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v,
4071 outer_headers);
4072 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c,
4073 outer_headers);
4074
4075 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4076 dmac_47_16);
4077 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4078 dmac_47_16);
4079
4080 if (is_multicast_ether_addr(dmac) &&
4081 is_multicast_ether_addr(dmac_mask))
4082 return true;
4083
4084 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4085 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4086
4087 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4088 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4089
4090 if (ipv4_is_multicast(*(__be32 *)(ipv4)) &&
4091 ipv4_is_multicast(*(__be32 *)(ipv4_mask)))
4092 return true;
4093
4094 return false;
4095}
4096
32269441
YH		 4097struct mlx5_ib_flow_handler *
4098mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
4099 struct mlx5_ib_flow_matcher *fs_matcher,
bb0ee7dc 4100 struct mlx5_flow_context *flow_context,
b823dd6d 4101 struct mlx5_flow_act *flow_act,
bfc5d839 4102 u32 counter_id,
32269441
YH		 4103 void *cmd_in, int inlen, int dest_id,
4104 int dest_type)
4105{
d4be3f44
YH		 4106 struct mlx5_flow_destination *dst;
4107 struct mlx5_ib_flow_prio *ft_prio;
d4be3f44 4108 struct mlx5_ib_flow_handler *handler;
bfc5d839 4109 int dst_num = 0;
d4be3f44
YH		 4110 bool mcast;
4111 int err;
4112
4113 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL)
4114 return ERR_PTR(-EOPNOTSUPP);
4115
4116 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO)
4117 return ERR_PTR(-ENOMEM);
4118
8e8aa145 4119 dst = kcalloc(2, sizeof(*dst), GFP_KERNEL);
d4be3f44
YH		 4120 if (!dst)
4121 return ERR_PTR(-ENOMEM);
4122
4123 mcast = raw_fs_is_multicast(fs_matcher, cmd_in);
4124 mutex_lock(&dev->flow_db->lock);
4125
b47fd4ff 4126 ft_prio = _get_flow_table(dev, fs_matcher, mcast);
d4be3f44
YH		 4127 if (IS_ERR(ft_prio)) {
4128 err = PTR_ERR(ft_prio);
4129 goto unlock;
4130 }
4131
6346f0bf 4132 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
bfc5d839
MB		 4133 dst[dst_num].type = dest_type;
4134 dst[dst_num].tir_num = dest_id;
b823dd6d 4135 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
a7ee18bd 4136 } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) {
bfc5d839
MB		 4137 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
4138 dst[dst_num].ft_num = dest_id;
b823dd6d 4139 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
a7ee18bd 4140 } else {
bfc5d839 4141 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_PORT;
a7ee18bd 4142 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
6346f0bf
YH		 4143 }
4144
bfc5d839
MB		 4145 dst_num++;
4146
4147 if (flow_act->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
4148 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
4149 dst[dst_num].counter_id = counter_id;
4150 dst_num++;
4151 }
4152
bb0ee7dc
JL		 4153 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher,
4154 flow_context, flow_act,
bfc5d839 4155 cmd_in, inlen, dst_num);
d4be3f44
YH		 4156
4157 if (IS_ERR(handler)) {
4158 err = PTR_ERR(handler);
4159 goto destroy_ft;
4160 }
4161
4162 mutex_unlock(&dev->flow_db->lock);
4163 atomic_inc(&fs_matcher->usecnt);
4164 handler->flow_matcher = fs_matcher;
4165
4166 kfree(dst);
4167
4168 return handler;
4169
4170destroy_ft:
4171 put_flow_table(dev, ft_prio, false);
4172unlock:
4173 mutex_unlock(&dev->flow_db->lock);
4174 kfree(dst);
4175
4176 return ERR_PTR(err);
32269441
YH		 4177}
4178
c6475a0b
AY		 4179static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
4180{
4181 u32 flags = 0;
4182
4183 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
4184 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
4185
4186 return flags;
4187}
4188
4189#define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
4190static struct ib_flow_action *
4191mlx5_ib_create_flow_action_esp(struct ib_device *device,
4192 const struct ib_flow_action_attrs_esp *attr,
4193 struct uverbs_attr_bundle *attrs)
4194{
4195 struct mlx5_ib_dev *mdev = to_mdev(device);
4196 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
4197 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
4198 struct mlx5_ib_flow_action *action;
4199 u64 action_flags;
4200 u64 flags;
4201 int err = 0;
4202
bccd0622
JG		 4203 err = uverbs_get_flags64(
4204 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
4205 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1));
4206 if (err)
4207 return ERR_PTR(err);
c6475a0b
AY		 4208
4209 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
4210
4211 /* We current only support a subset of the standard features. Only a
4212 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
4213 * (with overlap). Full offload mode isn't supported.
4214 */
4215 if (!attr->keymat || attr->replay || attr->encap ||
4216 attr->spi || attr->seq || attr->tfc_pad ||
4217 attr->hard_limit_pkts ||
4218 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4219 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
4220 return ERR_PTR(-EOPNOTSUPP);
4221
4222 if (attr->keymat->protocol !=
4223 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
4224 return ERR_PTR(-EOPNOTSUPP);
4225
4226 aes_gcm = &attr->keymat->keymat.aes_gcm;
4227
4228 if (aes_gcm->icv_len != 16 ||
4229 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
4230 return ERR_PTR(-EOPNOTSUPP);
4231
4232 action = kmalloc(sizeof(*action), GFP_KERNEL);
4233 if (!action)
4234 return ERR_PTR(-ENOMEM);
4235
4236 action->esp_aes_gcm.ib_flags = attr->flags;
4237 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
4238 sizeof(accel_attrs.keymat.aes_gcm.aes_key));
4239 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
4240 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
4241 sizeof(accel_attrs.keymat.aes_gcm.salt));
4242 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
4243 sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
4244 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
4245 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
4246 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
4247
4248 accel_attrs.esn = attr->esn;
4249 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
4250 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
4251 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4252 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4253
4254 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
4255 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
4256
4257 action->esp_aes_gcm.ctx =
4258 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
4259 if (IS_ERR(action->esp_aes_gcm.ctx)) {
4260 err = PTR_ERR(action->esp_aes_gcm.ctx);
4261 goto err_parse;
4262 }
4263
4264 action->esp_aes_gcm.ib_flags = attr->flags;
4265
4266 return &action->ib_action;
4267
4268err_parse:
4269 kfree(action);
4270 return ERR_PTR(err);
4271}
4272
349705c1
MB		 4273static int
4274mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
4275 const struct ib_flow_action_attrs_esp *attr,
4276 struct uverbs_attr_bundle *attrs)
4277{
4278 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4279 struct mlx5_accel_esp_xfrm_attrs accel_attrs;
4280 int err = 0;
4281
4282 if (attr->keymat || attr->replay || attr->encap ||
4283 attr->spi || attr->seq || attr->tfc_pad ||
4284 attr->hard_limit_pkts ||
4285 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4286 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
4287 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
4288 return -EOPNOTSUPP;
4289
4290 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
4291 * be modified.
4292 */
4293 if (!(maction->esp_aes_gcm.ib_flags &
4294 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
4295 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4296 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
4297 return -EINVAL;
4298
4299 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
4300 sizeof(accel_attrs));
4301
4302 accel_attrs.esn = attr->esn;
4303 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4304 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4305 else
4306 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4307
4308 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
4309 &accel_attrs);
4310 if (err)
4311 return err;
4312
4313 maction->esp_aes_gcm.ib_flags &=
4314 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4315 maction->esp_aes_gcm.ib_flags |=
4316 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4317
4318 return 0;
4319}
4320
c6475a0b
AY		 4321static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
4322{
4323 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4324
4325 switch (action->type) {
4326 case IB_FLOW_ACTION_ESP:
4327 /*
4328 * We only support aes_gcm by now, so we implicitly know this is
4329 * the underline crypto.
4330 */
4331 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
4332 break;
b4749bf2
MB		 4333 case IB_FLOW_ACTION_UNSPECIFIED:
4334 mlx5_ib_destroy_flow_action_raw(maction);
4335 break;
c6475a0b
AY		 4336 default:
4337 WARN_ON(true);
4338 break;
4339 }
4340
4341 kfree(maction);
4342 return 0;
4343}
4344
e126ba97
EC		 4345static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4346{
4347 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 4348 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97 4349 int err;
539ec982
YH		 4350 u16 uid;
4351
4352 uid = ibqp->pd ?
4353 to_mpd(ibqp->pd)->uid : 0;
e126ba97 4354
81e30880
YH		 4355 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
4356 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
4357 return -EOPNOTSUPP;
4358 }
4359
539ec982 4360 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
e126ba97
EC		 4361 if (err)
4362 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
4363 ibqp->qp_num, gid->raw);
4364
4365 return err;
4366}
4367
4368static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4369{
4370 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4371 int err;
539ec982 4372 u16 uid;
e126ba97 4373
539ec982
YH		 4374 uid = ibqp->pd ?
4375 to_mpd(ibqp->pd)->uid : 0;
4376 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
e126ba97
EC		 4377 if (err)
4378 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
4379 ibqp->qp_num, gid->raw);
4380
4381 return err;
4382}
4383
4384static int init_node_data(struct mlx5_ib_dev *dev)
4385{
1b5daf11 4386 int err;
e126ba97 4387
1b5daf11 4388 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 4389 if (err)
1b5daf11 4390 return err;
e126ba97 4391
1b5daf11 4392 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 4393
1b5daf11 4394 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 4395}
4396
508a523f
PP		 4397static ssize_t fw_pages_show(struct device *device,
4398 struct device_attribute *attr, char *buf)
e126ba97
EC		 4399{
4400 struct mlx5_ib_dev *dev =
54747231 4401 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
e126ba97 4402
9603b61d 4403 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97 4404}
508a523f 4405static DEVICE_ATTR_RO(fw_pages);
e126ba97 4406
508a523f 4407static ssize_t reg_pages_show(struct device *device,
e126ba97
EC		 4408 struct device_attribute *attr, char *buf)
4409{
4410 struct mlx5_ib_dev *dev =
54747231 4411 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
e126ba97 4412
6aec21f6 4413 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97 4414}
508a523f 4415static DEVICE_ATTR_RO(reg_pages);
e126ba97 4416
508a523f
PP		 4417static ssize_t hca_type_show(struct device *device,
4418 struct device_attribute *attr, char *buf)
e126ba97
EC		 4419{
4420 struct mlx5_ib_dev *dev =
54747231
PP		 4421 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4422
9603b61d 4423 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97 4424}
508a523f 4425static DEVICE_ATTR_RO(hca_type);
e126ba97 4426
508a523f
PP		 4427static ssize_t hw_rev_show(struct device *device,
4428 struct device_attribute *attr, char *buf)
e126ba97
EC		 4429{
4430 struct mlx5_ib_dev *dev =
54747231
PP		 4431 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4432
9603b61d 4433 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97 4434}
508a523f 4435static DEVICE_ATTR_RO(hw_rev);
e126ba97 4436
508a523f
PP		 4437static ssize_t board_id_show(struct device *device,
4438 struct device_attribute *attr, char *buf)
e126ba97
EC		 4439{
4440 struct mlx5_ib_dev *dev =
54747231
PP		 4441 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4442
e126ba97 4443 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 4444 dev->mdev->board_id);
e126ba97 4445}
508a523f 4446static DEVICE_ATTR_RO(board_id);
e126ba97 4447
508a523f
PP		 4448static struct attribute *mlx5_class_attributes[] = {
4449 &dev_attr_hw_rev.attr,
4450 &dev_attr_hca_type.attr,
4451 &dev_attr_board_id.attr,
4452 &dev_attr_fw_pages.attr,
4453 &dev_attr_reg_pages.attr,
4454 NULL,
4455};
e126ba97 4456
508a523f
PP		 4457static const struct attribute_group mlx5_attr_group = {
4458 .attrs = mlx5_class_attributes,
e126ba97
EC		 4459};
4460
7722f47e
HE		 4461static void pkey_change_handler(struct work_struct *work)
4462{
4463 struct mlx5_ib_port_resources *ports =
4464 container_of(work, struct mlx5_ib_port_resources,
4465 pkey_change_work);
4466
4467 mutex_lock(&ports->devr->mutex);
4468 mlx5_ib_gsi_pkey_change(ports->gsi);
4469 mutex_unlock(&ports->devr->mutex);
4470}
4471
89ea94a7
MG		 4472static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
4473{
4474 struct mlx5_ib_qp *mqp;
4475 struct mlx5_ib_cq *send_mcq, *recv_mcq;
4476 struct mlx5_core_cq *mcq;
4477 struct list_head cq_armed_list;
4478 unsigned long flags_qp;
4479 unsigned long flags_cq;
4480 unsigned long flags;
4481
4482 INIT_LIST_HEAD(&cq_armed_list);
4483
4484 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
4485 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
4486 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
4487 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
4488 if (mqp->sq.tail != mqp->sq.head) {
4489 send_mcq = to_mcq(mqp->ibqp.send_cq);
4490 spin_lock_irqsave(&send_mcq->lock, flags_cq);
4491 if (send_mcq->mcq.comp &&
4492 mqp->ibqp.send_cq->comp_handler) {
4493 if (!send_mcq->mcq.reset_notify_added) {
4494 send_mcq->mcq.reset_notify_added = 1;
4495 list_add_tail(&send_mcq->mcq.reset_notify,
4496 &cq_armed_list);
4497 }
4498 }
4499 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
4500 }
4501 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
4502 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
4503 /* no handling is needed for SRQ */
4504 if (!mqp->ibqp.srq) {
4505 if (mqp->rq.tail != mqp->rq.head) {
4506 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
4507 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
4508 if (recv_mcq->mcq.comp &&
4509 mqp->ibqp.recv_cq->comp_handler) {
4510 if (!recv_mcq->mcq.reset_notify_added) {
4511 recv_mcq->mcq.reset_notify_added = 1;
4512 list_add_tail(&recv_mcq->mcq.reset_notify,
4513 &cq_armed_list);
4514 }
4515 }
4516 spin_unlock_irqrestore(&recv_mcq->lock,
4517 flags_cq);
4518 }
4519 }
4520 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
4521 }
4522 /*At that point all inflight post send were put to be executed as of we
4523 * lock/unlock above locks Now need to arm all involved CQs.
4524 */
4525 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4e0e2ea1 4526 mcq->comp(mcq, NULL);
89ea94a7
MG		 4527 }
4528 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
4529}
4530
03404e8a
MG		 4531static void delay_drop_handler(struct work_struct *work)
4532{
4533 int err;
4534 struct mlx5_ib_delay_drop *delay_drop =
4535 container_of(work, struct mlx5_ib_delay_drop,
4536 delay_drop_work);
4537
fe248c3a
MG		 4538 atomic_inc(&delay_drop->events_cnt);
4539
03404e8a
MG		 4540 mutex_lock(&delay_drop->lock);
4541 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
4542 delay_drop->timeout);
4543 if (err) {
4544 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4545 delay_drop->timeout);
4546 delay_drop->activate = false;
4547 }
4548 mutex_unlock(&delay_drop->lock);
4549}
4550
09e574fa
SM		 4551static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4552 struct ib_event *ibev)
4553{
6cfdc7e4
AL		 4554 u8 port = (eqe->data.port.port >> 4) & 0xf;
4555
09e574fa
SM		 4556 switch (eqe->sub_type) {
4557 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
6cfdc7e4
AL		 4558 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4559 IB_LINK_LAYER_ETHERNET)
4560 schedule_work(&ibdev->delay_drop.delay_drop_work);
09e574fa
SM		 4561 break;
4562 default: /* do nothing */
4563 return;
4564 }
4565}
4566
134e9349
SM		 4567static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4568 struct ib_event *ibev)
4569{
4570 u8 port = (eqe->data.port.port >> 4) & 0xf;
4571
4572 ibev->element.port_num = port;
4573
4574 switch (eqe->sub_type) {
4575 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
4576 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
4577 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
4578 /* In RoCE, port up/down events are handled in
4579 * mlx5_netdev_event().
4580 */
4581 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4582 IB_LINK_LAYER_ETHERNET)
4583 return -EINVAL;
4584
4585 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
4586 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
4587 break;
4588
4589 case MLX5_PORT_CHANGE_SUBTYPE_LID:
4590 ibev->event = IB_EVENT_LID_CHANGE;
4591 break;
4592
4593 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
4594 ibev->event = IB_EVENT_PKEY_CHANGE;
4595 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
4596 break;
4597
4598 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
4599 ibev->event = IB_EVENT_GID_CHANGE;
4600 break;
4601
4602 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
4603 ibev->event = IB_EVENT_CLIENT_REREGISTER;
4604 break;
4605 default:
4606 return -EINVAL;
4607 }
4608
4609 return 0;
4610}
4611
d69a24e0 4612static void mlx5_ib_handle_event(struct work_struct *_work)
e126ba97 4613{
d69a24e0
DJ		 4614 struct mlx5_ib_event_work *work =
4615 container_of(_work, struct mlx5_ib_event_work, work);
4616 struct mlx5_ib_dev *ibdev;
e126ba97 4617 struct ib_event ibev;
dbaaff2a 4618 bool fatal = false;
e126ba97 4619
df097a27
SM		 4620 if (work->is_slave) {
4621 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
d69a24e0
DJ		 4622 if (!ibdev)
4623 goto out;
4624 } else {
df097a27 4625 ibdev = work->dev;
d69a24e0
DJ		 4626 }
4627
4628 switch (work->event) {
e126ba97 4629 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 4630 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 4631 mlx5_ib_handle_internal_error(ibdev);
134e9349 4632 ibev.element.port_num = (u8)(unsigned long)work->param;
dbaaff2a 4633 fatal = true;
e126ba97 4634 break;
134e9349
SM		 4635 case MLX5_EVENT_TYPE_PORT_CHANGE:
4636 if (handle_port_change(ibdev, work->param, &ibev))
d69a24e0 4637 goto out;
e126ba97 4638 break;
09e574fa
SM		 4639 case MLX5_EVENT_TYPE_GENERAL_EVENT:
4640 handle_general_event(ibdev, work->param, &ibev);
4641 /* fall through */
bdc37924 4642 default:
03404e8a 4643 goto out;
e126ba97
EC		 4644 }
4645
134e9349 4646 ibev.device = &ibdev->ib_dev;
e126ba97 4647
134e9349
SM		 4648 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
4649 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num);
03404e8a 4650 goto out;
a0c84c32
EC		 4651 }
4652
e126ba97
EC		 4653 if (ibdev->ib_active)
4654 ib_dispatch_event(&ibev);
dbaaff2a
EC		 4655
4656 if (fatal)
4657 ibdev->ib_active = false;
03404e8a 4658out:
d69a24e0
DJ		 4659 kfree(work);
4660}
4661
df097a27
SM		 4662static int mlx5_ib_event(struct notifier_block *nb,
4663 unsigned long event, void *param)
d69a24e0
DJ		 4664{
4665 struct mlx5_ib_event_work *work;
4666
4667 work = kmalloc(sizeof(*work), GFP_ATOMIC);
10bea9c8 4668 if (!work)
df097a27 4669 return NOTIFY_DONE;
d69a24e0 4670
10bea9c8 4671 INIT_WORK(&work->work, mlx5_ib_handle_event);
df097a27
SM		 4672 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
4673 work->is_slave = false;
10bea9c8 4674 work->param = param;
10bea9c8
LR		 4675 work->event = event;
4676
4677 queue_work(mlx5_ib_event_wq, &work->work);
df097a27
SM		 4678
4679 return NOTIFY_OK;
4680}
4681
4682static int mlx5_ib_event_slave_port(struct notifier_block *nb,
4683 unsigned long event, void *param)
4684{
4685 struct mlx5_ib_event_work *work;
4686
4687 work = kmalloc(sizeof(*work), GFP_ATOMIC);
4688 if (!work)
4689 return NOTIFY_DONE;
4690
4691 INIT_WORK(&work->work, mlx5_ib_handle_event);
4692 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
4693 work->is_slave = true;
4694 work->param = param;
4695 work->event = event;
4696 queue_work(mlx5_ib_event_wq, &work->work);
4697
4698 return NOTIFY_OK;
e126ba97
EC		 4699}
4700
c43f1112
MG		 4701static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4702{
4703 struct mlx5_hca_vport_context vport_ctx;
4704 int err;
4705 int port;
4706
a989ea01 4707 for (port = 1; port <= ARRAY_SIZE(dev->mdev->port_caps); port++) {
c43f1112
MG		 4708 dev->mdev->port_caps[port - 1].has_smi = false;
4709 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4710 MLX5_CAP_PORT_TYPE_IB) {
4711 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4712 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4713 port, 0,
4714 &vport_ctx);
4715 if (err) {
4716 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4717 port, err);
4718 return err;
4719 }
4720 dev->mdev->port_caps[port - 1].has_smi =
4721 vport_ctx.has_smi;
4722 } else {
4723 dev->mdev->port_caps[port - 1].has_smi = true;
4724 }
4725 }
4726 }
4727 return 0;
4728}
4729
e126ba97
EC		 4730static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4731{
4732 int port;
4733
508562d6 4734 for (port = 1; port <= dev->num_ports; port++)
e126ba97
EC		 4735 mlx5_query_ext_port_caps(dev, port);
4736}
4737
26628e2d 4738static int __get_port_caps(struct mlx5_ib_dev *dev, u8 port)
e126ba97
EC		 4739{
4740 struct ib_device_attr *dprops = NULL;
4741 struct ib_port_attr *pprops = NULL;
f614fc15 4742 int err = -ENOMEM;
2528e33e 4743 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97 4744
50ba3c18 4745 pprops = kzalloc(sizeof(*pprops), GFP_KERNEL);
e126ba97
EC		 4746 if (!pprops)
4747 goto out;
4748
4749 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4750 if (!dprops)
4751 goto out;
4752
2528e33e 4753 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 4754 if (err) {
4755 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4756 goto out;
4757 }
4758
32f69e4b
DJ		 4759 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4760 if (err) {
4761 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4762 port, err);
4763 goto out;
e126ba97
EC		 4764 }
4765
32f69e4b
DJ		 4766 dev->mdev->port_caps[port - 1].pkey_table_len =
4767 dprops->max_pkeys;
4768 dev->mdev->port_caps[port - 1].gid_table_len =
4769 pprops->gid_tbl_len;
4770 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4771 port, dprops->max_pkeys, pprops->gid_tbl_len);
4772
e126ba97
EC		 4773out:
4774 kfree(pprops);
4775 kfree(dprops);
4776
4777 return err;
4778}
4779
26628e2d
MB		 4780static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4781{
4782 /* For representors use port 1, is this is the only native
4783 * port
4784 */
4785 if (dev->is_rep)
4786 return __get_port_caps(dev, 1);
4787 return __get_port_caps(dev, port);
4788}
4789
e126ba97
EC		 4790static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4791{
4792 int err;
4793
4794 err = mlx5_mr_cache_cleanup(dev);
4795 if (err)
4796 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4797
32927e28 4798 if (dev->umrc.qp)
c4367a26 4799 mlx5_ib_destroy_qp(dev->umrc.qp, NULL);
32927e28
MB		 4800 if (dev->umrc.cq)
4801 ib_free_cq(dev->umrc.cq);
4802 if (dev->umrc.pd)
4803 ib_dealloc_pd(dev->umrc.pd);
e126ba97
EC		 4804}
4805
4806enum {
4807 MAX_UMR_WR = 128,
4808};
4809
4810static int create_umr_res(struct mlx5_ib_dev *dev)
4811{
4812 struct ib_qp_init_attr *init_attr = NULL;
4813 struct ib_qp_attr *attr = NULL;
4814 struct ib_pd *pd;
4815 struct ib_cq *cq;
4816 struct ib_qp *qp;
e126ba97
EC		 4817 int ret;
4818
4819 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4820 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4821 if (!attr || !init_attr) {
4822 ret = -ENOMEM;
4823 goto error_0;
4824 }
4825
ed082d36 4826 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 4827 if (IS_ERR(pd)) {
4828 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4829 ret = PTR_ERR(pd);
4830 goto error_0;
4831 }
4832
add08d76 4833 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 4834 if (IS_ERR(cq)) {
4835 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4836 ret = PTR_ERR(cq);
4837 goto error_2;
4838 }
e126ba97
EC		 4839
4840 init_attr->send_cq = cq;
4841 init_attr->recv_cq = cq;
4842 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4843 init_attr->cap.max_send_wr = MAX_UMR_WR;
4844 init_attr->cap.max_send_sge = 1;
4845 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4846 init_attr->port_num = 1;
4847 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4848 if (IS_ERR(qp)) {
4849 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4850 ret = PTR_ERR(qp);
4851 goto error_3;
4852 }
4853 qp->device = &dev->ib_dev;
4854 qp->real_qp = qp;
4855 qp->uobject = NULL;
4856 qp->qp_type = MLX5_IB_QPT_REG_UMR;
31fde034
MD		 4857 qp->send_cq = init_attr->send_cq;
4858 qp->recv_cq = init_attr->recv_cq;
e126ba97
EC		 4859
4860 attr->qp_state = IB_QPS_INIT;
4861 attr->port_num = 1;
4862 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4863 IB_QP_PORT, NULL);
4864 if (ret) {
4865 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4866 goto error_4;
4867 }
4868
4869 memset(attr, 0, sizeof(*attr));
4870 attr->qp_state = IB_QPS_RTR;
4871 attr->path_mtu = IB_MTU_256;
4872
4873 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4874 if (ret) {
4875 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4876 goto error_4;
4877 }
4878
4879 memset(attr, 0, sizeof(*attr));
4880 attr->qp_state = IB_QPS_RTS;
4881 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4882 if (ret) {
4883 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4884 goto error_4;
4885 }
4886
4887 dev->umrc.qp = qp;
4888 dev->umrc.cq = cq;
e126ba97
EC		 4889 dev->umrc.pd = pd;
4890
4891 sema_init(&dev->umrc.sem, MAX_UMR_WR);
4892 ret = mlx5_mr_cache_init(dev);
4893 if (ret) {
4894 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4895 goto error_4;
4896 }
4897
4898 kfree(attr);
4899 kfree(init_attr);
4900
4901 return 0;
4902
4903error_4:
c4367a26 4904 mlx5_ib_destroy_qp(qp, NULL);
32927e28 4905 dev->umrc.qp = NULL;
e126ba97
EC		 4906
4907error_3:
add08d76 4908 ib_free_cq(cq);
32927e28 4909 dev->umrc.cq = NULL;
e126ba97
EC		 4910
4911error_2:
e126ba97 4912 ib_dealloc_pd(pd);
32927e28 4913 dev->umrc.pd = NULL;
e126ba97
EC		 4914
4915error_0:
4916 kfree(attr);
4917 kfree(init_attr);
4918 return ret;
4919}
4920
6e8484c5
MG		 4921static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4922{
4923 switch (umr_fence_cap) {
4924 case MLX5_CAP_UMR_FENCE_NONE:
4925 return MLX5_FENCE_MODE_NONE;
4926 case MLX5_CAP_UMR_FENCE_SMALL:
4927 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4928 default:
4929 return MLX5_FENCE_MODE_STRONG_ORDERING;
4930 }
4931}
4932
e126ba97
EC		 4933static int create_dev_resources(struct mlx5_ib_resources *devr)
4934{
4935 struct ib_srq_init_attr attr;
4936 struct mlx5_ib_dev *dev;
21a428a0 4937 struct ib_device *ibdev;
bcf4c1ea 4938 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 4939 int port;
e126ba97
EC		 4940 int ret = 0;
4941
4942 dev = container_of(devr, struct mlx5_ib_dev, devr);
21a428a0 4943 ibdev = &dev->ib_dev;
e126ba97 4944
d16e91da
HE		 4945 mutex_init(&devr->mutex);
4946
21a428a0
LR		 4947 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd);
4948 if (!devr->p0)
4949 return -ENOMEM;
4950
4951 devr->p0->device = ibdev;
e126ba97
EC		 4952 devr->p0->uobject = NULL;
4953 atomic_set(&devr->p0->usecnt, 0);
4954
ff23dfa1 4955 ret = mlx5_ib_alloc_pd(devr->p0, NULL);
21a428a0
LR		 4956 if (ret)
4957 goto error0;
4958
e39afe3d
LR		 4959 devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq);
4960 if (!devr->c0) {
4961 ret = -ENOMEM;
e126ba97
EC		 4962 goto error1;
4963 }
e39afe3d
LR		 4964
4965 devr->c0->device = &dev->ib_dev;
e126ba97
EC		 4966 atomic_set(&devr->c0->usecnt, 0);
4967
e39afe3d
LR		 4968 ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL);
4969 if (ret)
4970 goto err_create_cq;
4971
ff23dfa1 4972 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
e126ba97
EC		 4973 if (IS_ERR(devr->x0)) {
4974 ret = PTR_ERR(devr->x0);
4975 goto error2;
4976 }
4977 devr->x0->device = &dev->ib_dev;
4978 devr->x0->inode = NULL;
4979 atomic_set(&devr->x0->usecnt, 0);
4980 mutex_init(&devr->x0->tgt_qp_mutex);
4981 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4982
ff23dfa1 4983 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
e126ba97
EC		 4984 if (IS_ERR(devr->x1)) {
4985 ret = PTR_ERR(devr->x1);
4986 goto error3;
4987 }
4988 devr->x1->device = &dev->ib_dev;
4989 devr->x1->inode = NULL;
4990 atomic_set(&devr->x1->usecnt, 0);
4991 mutex_init(&devr->x1->tgt_qp_mutex);
4992 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4993
4994 memset(&attr, 0, sizeof(attr));
4995 attr.attr.max_sge = 1;
4996 attr.attr.max_wr = 1;
4997 attr.srq_type = IB_SRQT_XRC;
1a56ff6d 4998 attr.ext.cq = devr->c0;
e126ba97
EC		 4999 attr.ext.xrc.xrcd = devr->x0;
5000
68e326de
LR		 5001 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq);
5002 if (!devr->s0) {
5003 ret = -ENOMEM;
e126ba97
EC		 5004 goto error4;
5005 }
68e326de 5006
e126ba97
EC		 5007 devr->s0->device = &dev->ib_dev;
5008 devr->s0->pd = devr->p0;
e126ba97
EC		 5009 devr->s0->srq_type = IB_SRQT_XRC;
5010 devr->s0->ext.xrc.xrcd = devr->x0;
1a56ff6d 5011 devr->s0->ext.cq = devr->c0;
68e326de
LR		 5012 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL);
5013 if (ret)
5014 goto err_create;
5015
e126ba97 5016 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1a56ff6d 5017 atomic_inc(&devr->s0->ext.cq->usecnt);
e126ba97
EC		 5018 atomic_inc(&devr->p0->usecnt);
5019 atomic_set(&devr->s0->usecnt, 0);
5020
4aa17b28
HA		 5021 memset(&attr, 0, sizeof(attr));
5022 attr.attr.max_sge = 1;
5023 attr.attr.max_wr = 1;
5024 attr.srq_type = IB_SRQT_BASIC;
68e326de
LR		 5025 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq);
5026 if (!devr->s1) {
5027 ret = -ENOMEM;
4aa17b28
HA		 5028 goto error5;
5029 }
68e326de 5030
4aa17b28
HA		 5031 devr->s1->device = &dev->ib_dev;
5032 devr->s1->pd = devr->p0;
4aa17b28 5033 devr->s1->srq_type = IB_SRQT_BASIC;
1a56ff6d 5034 devr->s1->ext.cq = devr->c0;
68e326de
LR		 5035
5036 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL);
5037 if (ret)
5038 goto error6;
5039
4aa17b28 5040 atomic_inc(&devr->p0->usecnt);
1a56ff6d 5041 atomic_set(&devr->s1->usecnt, 0);
4aa17b28 5042
7722f47e
HE		 5043 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
5044 INIT_WORK(&devr->ports[port].pkey_change_work,
5045 pkey_change_handler);
5046 devr->ports[port].devr = devr;
5047 }
5048
e126ba97
EC		 5049 return 0;
5050
68e326de
LR		 5051error6:
5052 kfree(devr->s1);
4aa17b28 5053error5:
c4367a26 5054 mlx5_ib_destroy_srq(devr->s0, NULL);
68e326de
LR		 5055err_create:
5056 kfree(devr->s0);
e126ba97 5057error4:
c4367a26 5058 mlx5_ib_dealloc_xrcd(devr->x1, NULL);
e126ba97 5059error3:
c4367a26 5060 mlx5_ib_dealloc_xrcd(devr->x0, NULL);
e126ba97 5061error2:
c4367a26 5062 mlx5_ib_destroy_cq(devr->c0, NULL);
e39afe3d
LR		 5063err_create_cq:
5064 kfree(devr->c0);
e126ba97 5065error1:
c4367a26 5066 mlx5_ib_dealloc_pd(devr->p0, NULL);
e126ba97 5067error0:
21a428a0 5068 kfree(devr->p0);
e126ba97
EC		 5069 return ret;
5070}
5071
5072static void destroy_dev_resources(struct mlx5_ib_resources *devr)
5073{
7722f47e
HE		 5074 int port;
5075
c4367a26 5076 mlx5_ib_destroy_srq(devr->s1, NULL);
68e326de 5077 kfree(devr->s1);
c4367a26 5078 mlx5_ib_destroy_srq(devr->s0, NULL);
68e326de 5079 kfree(devr->s0);
c4367a26
SR		 5080 mlx5_ib_dealloc_xrcd(devr->x0, NULL);
5081 mlx5_ib_dealloc_xrcd(devr->x1, NULL);
5082 mlx5_ib_destroy_cq(devr->c0, NULL);
e39afe3d 5083 kfree(devr->c0);
c4367a26 5084 mlx5_ib_dealloc_pd(devr->p0, NULL);
21a428a0 5085 kfree(devr->p0);
7722f47e
HE		 5086
5087 /* Make sure no change P_Key work items are still executing */
5d8f6a0e 5088 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
7722f47e 5089 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 5090}
5091
b02289b3
AK		 5092static u32 get_core_cap_flags(struct ib_device *ibdev,
5093 struct mlx5_hca_vport_context *rep)
e53505a8
AS		 5094{
5095 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5096 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
5097 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
5098 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
85c7c014 5099 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
e53505a8
AS		 5100 u32 ret = 0;
5101
b02289b3
AK		 5102 if (rep->grh_required)
5103 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
5104
e53505a8 5105 if (ll == IB_LINK_LAYER_INFINIBAND)
b02289b3 5106 return ret | RDMA_CORE_PORT_IBA_IB;
e53505a8 5107
85c7c014 5108 if (raw_support)
b02289b3 5109 ret |= RDMA_CORE_PORT_RAW_PACKET;
72cd5717 5110
e53505a8 5111 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 5112 return ret;
e53505a8
AS		 5113
5114 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 5115 return ret;
e53505a8
AS		 5116
5117 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
5118 ret |= RDMA_CORE_PORT_IBA_ROCE;
5119
5120 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
5121 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
5122
5123 return ret;
5124}
5125
7738613e
IW		 5126static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
5127 struct ib_port_immutable *immutable)
5128{
5129 struct ib_port_attr attr;
ca5b91d6
OG		 5130 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5131 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
b02289b3 5132 struct mlx5_hca_vport_context rep = {0};
7738613e
IW		 5133 int err;
5134
c4550c63 5135 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 5136 if (err)
5137 return err;
5138
b02289b3
AK		 5139 if (ll == IB_LINK_LAYER_INFINIBAND) {
5140 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
5141 &rep);
5142 if (err)
5143 return err;
5144 }
5145
7738613e
IW		 5146 immutable->pkey_tbl_len = attr.pkey_tbl_len;
5147 immutable->gid_tbl_len = attr.gid_tbl_len;
b02289b3 5148 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
ca5b91d6
OG		 5149 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
5150 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 5151
5152 return 0;
5153}
5154
8e6efa3a
MB		 5155static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
5156 struct ib_port_immutable *immutable)
5157{
5158 struct ib_port_attr attr;
5159 int err;
5160
5161 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5162
5163 err = ib_query_port(ibdev, port_num, &attr);
5164 if (err)
5165 return err;
5166
5167 immutable->pkey_tbl_len = attr.pkey_tbl_len;
5168 immutable->gid_tbl_len = attr.gid_tbl_len;
5169 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5170
5171 return 0;
5172}
5173
9abb0d1b 5174static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 5175{
5176 struct mlx5_ib_dev *dev =
5177 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 5178 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
5179 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
5180 fw_rev_sub(dev->mdev));
c7342823
IW		 5181}
5182
45f95acd 5183static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 5184{
5185 struct mlx5_core_dev *mdev = dev->mdev;
5186 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
5187 MLX5_FLOW_NAMESPACE_LAG);
5188 struct mlx5_flow_table *ft;
5189 int err;
5190
7c34ec19 5191 if (!ns || !mlx5_lag_is_roce(mdev))
9ef9c640
AH		 5192 return 0;
5193
5194 err = mlx5_cmd_create_vport_lag(mdev);
5195 if (err)
5196 return err;
5197
5198 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
5199 if (IS_ERR(ft)) {
5200 err = PTR_ERR(ft);
5201 goto err_destroy_vport_lag;
5202 }
5203
9a4ca38d 5204 dev->flow_db->lag_demux_ft = ft;
7c34ec19 5205 dev->lag_active = true;
9ef9c640
AH		 5206 return 0;
5207
5208err_destroy_vport_lag:
5209 mlx5_cmd_destroy_vport_lag(mdev);
5210 return err;
5211}
5212
45f95acd 5213static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 5214{
5215 struct mlx5_core_dev *mdev = dev->mdev;
5216
7c34ec19
AH		 5217 if (dev->lag_active) {
5218 dev->lag_active = false;
5219
9a4ca38d
MB		 5220 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
5221 dev->flow_db->lag_demux_ft = NULL;
9ef9c640
AH		 5222
5223 mlx5_cmd_destroy_vport_lag(mdev);
5224 }
5225}
5226
7fd8aefb 5227static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
d012f5d6
OG		 5228{
5229 int err;
5230
95579e78
MB		 5231 dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event;
5232 err = register_netdevice_notifier(&dev->port[port_num].roce.nb);
d012f5d6 5233 if (err) {
95579e78 5234 dev->port[port_num].roce.nb.notifier_call = NULL;
d012f5d6
OG		 5235 return err;
5236 }
5237
5238 return 0;
5239}
5240
7fd8aefb 5241static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5ec8c83e 5242{
95579e78
MB		 5243 if (dev->port[port_num].roce.nb.notifier_call) {
5244 unregister_netdevice_notifier(&dev->port[port_num].roce.nb);
5245 dev->port[port_num].roce.nb.notifier_call = NULL;
5ec8c83e
AH		 5246 }
5247}
5248
e3f1ed1f 5249static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 5250{
e53505a8
AS		 5251 int err;
5252
ca5b91d6
OG		 5253 if (MLX5_CAP_GEN(dev->mdev, roce)) {
5254 err = mlx5_nic_vport_enable_roce(dev->mdev);
5255 if (err)
8e6efa3a 5256 return err;
ca5b91d6 5257 }
e53505a8 5258
45f95acd 5259 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 5260 if (err)
5261 goto err_disable_roce;
5262
e53505a8
AS		 5263 return 0;
5264
9ef9c640 5265err_disable_roce:
ca5b91d6
OG		 5266 if (MLX5_CAP_GEN(dev->mdev, roce))
5267 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 5268
e53505a8 5269 return err;
fc24fc5e
AS		 5270}
5271
45f95acd 5272static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 5273{
45f95acd 5274 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 5275 if (MLX5_CAP_GEN(dev->mdev, roce))
5276 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 5277}
5278
e1f24a79 5279struct mlx5_ib_counter {
7c16f477
KH		 5280 const char *name;
5281 size_t offset;
5282};
5283
5284#define INIT_Q_COUNTER(_name) \
5285 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
5286
e1f24a79 5287static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 5288 INIT_Q_COUNTER(rx_write_requests),
5289 INIT_Q_COUNTER(rx_read_requests),
5290 INIT_Q_COUNTER(rx_atomic_requests),
5291 INIT_Q_COUNTER(out_of_buffer),
5292};
5293
e1f24a79 5294static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 5295 INIT_Q_COUNTER(out_of_sequence),
5296};
5297
e1f24a79 5298static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 5299 INIT_Q_COUNTER(duplicate_request),
5300 INIT_Q_COUNTER(rnr_nak_retry_err),
5301 INIT_Q_COUNTER(packet_seq_err),
5302 INIT_Q_COUNTER(implied_nak_seq_err),
5303 INIT_Q_COUNTER(local_ack_timeout_err),
5304};
5305
e1f24a79
PP		 5306#define INIT_CONG_COUNTER(_name) \
5307 { .name = #_name, .offset = \
5308 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
5309
5310static const struct mlx5_ib_counter cong_cnts[] = {
5311 INIT_CONG_COUNTER(rp_cnp_ignored),
5312 INIT_CONG_COUNTER(rp_cnp_handled),
5313 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
5314 INIT_CONG_COUNTER(np_cnp_sent),
5315};
5316
58dcb60a
PP		 5317static const struct mlx5_ib_counter extended_err_cnts[] = {
5318 INIT_Q_COUNTER(resp_local_length_error),
5319 INIT_Q_COUNTER(resp_cqe_error),
5320 INIT_Q_COUNTER(req_cqe_error),
5321 INIT_Q_COUNTER(req_remote_invalid_request),
5322 INIT_Q_COUNTER(req_remote_access_errors),
5323 INIT_Q_COUNTER(resp_remote_access_errors),
5324 INIT_Q_COUNTER(resp_cqe_flush_error),
5325 INIT_Q_COUNTER(req_cqe_flush_error),
5326};
5327
9f876f3d
TB		 5328#define INIT_EXT_PPCNT_COUNTER(_name) \
5329 { .name = #_name, .offset = \
5330 MLX5_BYTE_OFF(ppcnt_reg, \
5331 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
5332
5333static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
5334 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
5335};
5336
e1f24a79 5337static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a 5338{
aac4492e 5339 int i;
0837e86a 5340
7c16f477 5341 for (i = 0; i < dev->num_ports; i++) {
921c0f5b 5342 if (dev->port[i].cnts.set_id_valid)
aac4492e
DJ		 5343 mlx5_core_dealloc_q_counter(dev->mdev,
5344 dev->port[i].cnts.set_id);
e1f24a79
PP		 5345 kfree(dev->port[i].cnts.names);
5346 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 5347 }
5348}
5349
e1f24a79
PP		 5350static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
5351 struct mlx5_ib_counters *cnts)
7c16f477
KH		 5352{
5353 u32 num_counters;
5354
5355 num_counters = ARRAY_SIZE(basic_q_cnts);
5356
5357 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
5358 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
5359
5360 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
5361 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 5362
5363 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
5364 num_counters += ARRAY_SIZE(extended_err_cnts);
5365
e1f24a79 5366 cnts->num_q_counters = num_counters;
7c16f477 5367
e1f24a79
PP		 5368 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5369 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
5370 num_counters += ARRAY_SIZE(cong_cnts);
5371 }
9f876f3d
TB		 5372 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5373 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
5374 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
5375 }
e1f24a79
PP		 5376 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
5377 if (!cnts->names)
7c16f477
KH		 5378 return -ENOMEM;
5379
e1f24a79
PP		 5380 cnts->offsets = kcalloc(num_counters,
5381 sizeof(cnts->offsets), GFP_KERNEL);
5382 if (!cnts->offsets)
7c16f477
KH		 5383 goto err_names;
5384
7c16f477
KH		 5385 return 0;
5386
5387err_names:
e1f24a79 5388 kfree(cnts->names);
aac4492e 5389 cnts->names = NULL;
7c16f477
KH		 5390 return -ENOMEM;
5391}
5392
e1f24a79
PP		 5393static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
5394 const char **names,
5395 size_t *offsets)
7c16f477
KH		 5396{
5397 int i;
5398 int j = 0;
5399
5400 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
5401 names[j] = basic_q_cnts[i].name;
5402 offsets[j] = basic_q_cnts[i].offset;
5403 }
5404
5405 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
5406 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
5407 names[j] = out_of_seq_q_cnts[i].name;
5408 offsets[j] = out_of_seq_q_cnts[i].offset;
5409 }
5410 }
5411
5412 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
5413 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
5414 names[j] = retrans_q_cnts[i].name;
5415 offsets[j] = retrans_q_cnts[i].offset;
5416 }
5417 }
e1f24a79 5418
58dcb60a
PP		 5419 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
5420 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
5421 names[j] = extended_err_cnts[i].name;
5422 offsets[j] = extended_err_cnts[i].offset;
5423 }
5424 }
5425
e1f24a79
PP		 5426 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5427 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
5428 names[j] = cong_cnts[i].name;
5429 offsets[j] = cong_cnts[i].offset;
5430 }
5431 }
9f876f3d
TB		 5432
5433 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5434 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
5435 names[j] = ext_ppcnt_cnts[i].name;
5436 offsets[j] = ext_ppcnt_cnts[i].offset;
5437 }
5438 }
0837e86a
MB		 5439}
5440
e1f24a79 5441static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a 5442{
aac4492e 5443 int err = 0;
0837e86a 5444 int i;
aa74be6e
YH		 5445 bool is_shared;
5446
5447 is_shared = MLX5_CAP_GEN(dev->mdev, log_max_uctx) != 0;
0837e86a
MB		 5448
5449 for (i = 0; i < dev->num_ports; i++) {
aac4492e
DJ		 5450 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
5451 if (err)
5452 goto err_alloc;
5453
5454 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
5455 dev->port[i].cnts.offsets);
7c16f477 5456
aa74be6e
YH		 5457 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5458 &dev->port[i].cnts.set_id,
5459 is_shared ?
5460 MLX5_SHARED_RESOURCE_UID : 0);
aac4492e 5461 if (err) {
0837e86a
MB		 5462 mlx5_ib_warn(dev,
5463 "couldn't allocate queue counter for port %d, err %d\n",
aac4492e
DJ		 5464 i + 1, err);
5465 goto err_alloc;
0837e86a 5466 }
aac4492e 5467 dev->port[i].cnts.set_id_valid = true;
0837e86a
MB		 5468 }
5469
5470 return 0;
5471
aac4492e
DJ		 5472err_alloc:
5473 mlx5_ib_dealloc_counters(dev);
5474 return err;
0837e86a
MB		 5475}
5476
0ad17a8f
MB		 5477static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
5478 u8 port_num)
5479{
7c16f477
KH		 5480 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5481 struct mlx5_ib_port *port = &dev->port[port_num - 1];
0ad17a8f
MB		 5482
5483 /* We support only per port stats */
5484 if (port_num == 0)
5485 return NULL;
5486
e1f24a79
PP		 5487 return rdma_alloc_hw_stats_struct(port->cnts.names,
5488 port->cnts.num_q_counters +
9f876f3d
TB		 5489 port->cnts.num_cong_counters +
5490 port->cnts.num_ext_ppcnt_counters,
0ad17a8f
MB		 5491 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5492}
5493
aac4492e 5494static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
e1f24a79 5495 struct mlx5_ib_port *port,
318d535c
MZ		 5496 struct rdma_hw_stats *stats,
5497 u16 set_id)
0ad17a8f 5498{
0ad17a8f
MB		 5499 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
5500 void *out;
5501 __be32 val;
e1f24a79 5502 int ret, i;
0ad17a8f 5503
1b9a07ee 5504 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 5505 if (!out)
5506 return -ENOMEM;
5507
318d535c 5508 ret = mlx5_core_query_q_counter(mdev, set_id, 0, out, outlen);
0ad17a8f
MB		 5509 if (ret)
5510 goto free;
5511
e1f24a79
PP		 5512 for (i = 0; i < port->cnts.num_q_counters; i++) {
5513 val = *(__be32 *)(out + port->cnts.offsets[i]);
0ad17a8f
MB		 5514 stats->value[i] = (u64)be32_to_cpu(val);
5515 }
7c16f477 5516
0ad17a8f
MB		 5517free:
5518 kvfree(out);
e1f24a79
PP		 5519 return ret;
5520}
5521
9f876f3d
TB		 5522static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
5523 struct mlx5_ib_port *port,
5524 struct rdma_hw_stats *stats)
5525{
5526 int offset = port->cnts.num_q_counters + port->cnts.num_cong_counters;
5527 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
5528 int ret, i;
5529 void *out;
5530
5531 out = kvzalloc(sz, GFP_KERNEL);
5532 if (!out)
5533 return -ENOMEM;
5534
5535 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
5536 if (ret)
5537 goto free;
5538
5539 for (i = 0; i < port->cnts.num_ext_ppcnt_counters; i++) {
5540 stats->value[i + offset] =
5541 be64_to_cpup((__be64 *)(out +
5542 port->cnts.offsets[i + offset]));
5543 }
5544
5545free:
5546 kvfree(out);
5547 return ret;
5548}
5549
e1f24a79
PP		 5550static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
5551 struct rdma_hw_stats *stats,
5552 u8 port_num, int index)
5553{
5554 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5555 struct mlx5_ib_port *port = &dev->port[port_num - 1];
aac4492e 5556 struct mlx5_core_dev *mdev;
e1f24a79 5557 int ret, num_counters;
aac4492e 5558 u8 mdev_port_num;
e1f24a79
PP		 5559
5560 if (!stats)
5561 return -EINVAL;
5562
9f876f3d
TB		 5563 num_counters = port->cnts.num_q_counters +
5564 port->cnts.num_cong_counters +
5565 port->cnts.num_ext_ppcnt_counters;
aac4492e
DJ		 5566
5567 /* q_counters are per IB device, query the master mdev */
318d535c
MZ		 5568 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats,
5569 port->cnts.set_id);
e1f24a79
PP		 5570 if (ret)
5571 return ret;
e1f24a79 5572
9f876f3d
TB		 5573 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5574 ret = mlx5_ib_query_ext_ppcnt_counters(dev, port, stats);
5575 if (ret)
5576 return ret;
5577 }
5578
e1f24a79 5579 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
aac4492e
DJ		 5580 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
5581 &mdev_port_num);
5582 if (!mdev) {
5583 /* If port is not affiliated yet, its in down state
5584 * which doesn't have any counters yet, so it would be
5585 * zero. So no need to read from the HCA.
5586 */
5587 goto done;
5588 }
71a0ff65
MD		 5589 ret = mlx5_lag_query_cong_counters(dev->mdev,
5590 stats->value +
5591 port->cnts.num_q_counters,
5592 port->cnts.num_cong_counters,
5593 port->cnts.offsets +
5594 port->cnts.num_q_counters);
aac4492e
DJ		 5595
5596 mlx5_ib_put_native_port_mdev(dev, port_num);
e1f24a79
PP		 5597 if (ret)
5598 return ret;
e1f24a79
PP		 5599 }
5600
aac4492e 5601done:
e1f24a79 5602 return num_counters;
0ad17a8f
MB		 5603}
5604
18d422ce
MZ		 5605static struct rdma_hw_stats *
5606mlx5_ib_counter_alloc_stats(struct rdma_counter *counter)
5607{
5608 struct mlx5_ib_dev *dev = to_mdev(counter->device);
5609 struct mlx5_ib_port *port = &dev->port[counter->port - 1];
5610
5611 /* Q counters are in the beginning of all counters */
5612 return rdma_alloc_hw_stats_struct(port->cnts.names,
5613 port->cnts.num_q_counters,
5614 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5615}
5616
5617static int mlx5_ib_counter_update_stats(struct rdma_counter *counter)
5618{
5619 struct mlx5_ib_dev *dev = to_mdev(counter->device);
5620 struct mlx5_ib_port *port = &dev->port[counter->port - 1];
5621
5622 return mlx5_ib_query_q_counters(dev->mdev, port,
5623 counter->stats, counter->id);
5624}
5625
45842fc6
MZ		 5626static int mlx5_ib_counter_bind_qp(struct rdma_counter *counter,
5627 struct ib_qp *qp)
5628{
5629 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5630 u16 cnt_set_id = 0;
5631 int err;
5632
5633 if (!counter->id) {
5634 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5635 &cnt_set_id,
5636 MLX5_SHARED_RESOURCE_UID);
5637 if (err)
5638 return err;
5639 counter->id = cnt_set_id;
5640 }
5641
5642 err = mlx5_ib_qp_set_counter(qp, counter);
5643 if (err)
5644 goto fail_set_counter;
5645
5646 return 0;
5647
5648fail_set_counter:
5649 mlx5_core_dealloc_q_counter(dev->mdev, cnt_set_id);
5650 counter->id = 0;
5651
5652 return err;
5653}
5654
5655static int mlx5_ib_counter_unbind_qp(struct ib_qp *qp)
5656{
5657 return mlx5_ib_qp_set_counter(qp, NULL);
5658}
5659
5660static int mlx5_ib_counter_dealloc(struct rdma_counter *counter)
5661{
5662 struct mlx5_ib_dev *dev = to_mdev(counter->device);
5663
5664 return mlx5_core_dealloc_q_counter(dev->mdev, counter->id);
5665}
5666
f6a8a19b
DD		 5667static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num,
5668 enum rdma_netdev_t type,
5669 struct rdma_netdev_alloc_params *params)
693dfd5a
ES		 5670{
5671 if (type != RDMA_NETDEV_IPOIB)
f6a8a19b 5672 return -EOPNOTSUPP;
693dfd5a 5673
f6a8a19b 5674 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
693dfd5a
ES		 5675}
5676
fe248c3a
MG		 5677static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
5678{
5679 if (!dev->delay_drop.dbg)
5680 return;
5681 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
5682 kfree(dev->delay_drop.dbg);
5683 dev->delay_drop.dbg = NULL;
5684}
5685
03404e8a
MG		 5686static void cancel_delay_drop(struct mlx5_ib_dev *dev)
5687{
5688 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5689 return;
5690
5691 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 5692 delay_drop_debugfs_cleanup(dev);
5693}
5694
5695static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5696 size_t count, loff_t *pos)
5697{
5698 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5699 char lbuf[20];
5700 int len;
5701
5702 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5703 return simple_read_from_buffer(buf, count, pos, lbuf, len);
5704}
5705
5706static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5707 size_t count, loff_t *pos)
5708{
5709 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5710 u32 timeout;
5711 u32 var;
5712
5713 if (kstrtouint_from_user(buf, count, 0, &var))
5714 return -EFAULT;
5715
5716 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5717 1000);
5718 if (timeout != var)
5719 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5720 timeout);
5721
5722 delay_drop->timeout = timeout;
5723
5724 return count;
5725}
5726
5727static const struct file_operations fops_delay_drop_timeout = {
5728 .owner = THIS_MODULE,
5729 .open = simple_open,
5730 .write = delay_drop_timeout_write,
5731 .read = delay_drop_timeout_read,
5732};
5733
5734static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5735{
5736 struct mlx5_ib_dbg_delay_drop *dbg;
5737
5738 if (!mlx5_debugfs_root)
5739 return 0;
5740
5741 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
5742 if (!dbg)
5743 return -ENOMEM;
5744
cbafad87
SM		 5745 dev->delay_drop.dbg = dbg;
5746
fe248c3a
MG		 5747 dbg->dir_debugfs =
5748 debugfs_create_dir("delay_drop",
5749 dev->mdev->priv.dbg_root);
5750 if (!dbg->dir_debugfs)
cbafad87 5751 goto out_debugfs;
fe248c3a
MG		 5752
5753 dbg->events_cnt_debugfs =
5754 debugfs_create_atomic_t("num_timeout_events", 0400,
5755 dbg->dir_debugfs,
5756 &dev->delay_drop.events_cnt);
5757 if (!dbg->events_cnt_debugfs)
5758 goto out_debugfs;
5759
5760 dbg->rqs_cnt_debugfs =
5761 debugfs_create_atomic_t("num_rqs", 0400,
5762 dbg->dir_debugfs,
5763 &dev->delay_drop.rqs_cnt);
5764 if (!dbg->rqs_cnt_debugfs)
5765 goto out_debugfs;
5766
5767 dbg->timeout_debugfs =
5768 debugfs_create_file("timeout", 0600,
5769 dbg->dir_debugfs,
5770 &dev->delay_drop,
5771 &fops_delay_drop_timeout);
5772 if (!dbg->timeout_debugfs)
5773 goto out_debugfs;
5774
5775 return 0;
5776
5777out_debugfs:
5778 delay_drop_debugfs_cleanup(dev);
5779 return -ENOMEM;
03404e8a
MG		 5780}
5781
5782static void init_delay_drop(struct mlx5_ib_dev *dev)
5783{
5784 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5785 return;
5786
5787 mutex_init(&dev->delay_drop.lock);
5788 dev->delay_drop.dev = dev;
5789 dev->delay_drop.activate = false;
5790 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5791 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 5792 atomic_set(&dev->delay_drop.rqs_cnt, 0);
5793 atomic_set(&dev->delay_drop.events_cnt, 0);
5794
5795 if (delay_drop_debugfs_init(dev))
5796 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
03404e8a
MG		 5797}
5798
32f69e4b
DJ		 5799/* The mlx5_ib_multiport_mutex should be held when calling this function */
5800static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5801 struct mlx5_ib_multiport_info *mpi)
5802{
5803 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5804 struct mlx5_ib_port *port = &ibdev->port[port_num];
5805 int comps;
5806 int err;
5807 int i;
5808
a9e546e7
PP		 5809 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5810
32f69e4b
DJ		 5811 spin_lock(&port->mp.mpi_lock);
5812 if (!mpi->ibdev) {
5813 spin_unlock(&port->mp.mpi_lock);
5814 return;
5815 }
df097a27 5816
32f69e4b
DJ		 5817 mpi->ibdev = NULL;
5818
5819 spin_unlock(&port->mp.mpi_lock);
23eaf3b5
LR		 5820 if (mpi->mdev_events.notifier_call)
5821 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
5822 mpi->mdev_events.notifier_call = NULL;
32f69e4b
DJ		 5823 mlx5_remove_netdev_notifier(ibdev, port_num);
5824 spin_lock(&port->mp.mpi_lock);
5825
5826 comps = mpi->mdev_refcnt;
5827 if (comps) {
5828 mpi->unaffiliate = true;
5829 init_completion(&mpi->unref_comp);
5830 spin_unlock(&port->mp.mpi_lock);
5831
5832 for (i = 0; i < comps; i++)
5833 wait_for_completion(&mpi->unref_comp);
5834
5835 spin_lock(&port->mp.mpi_lock);
5836 mpi->unaffiliate = false;
5837 }
5838
5839 port->mp.mpi = NULL;
5840
5841 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5842
5843 spin_unlock(&port->mp.mpi_lock);
5844
5845 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5846
5847 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5848 /* Log an error, still needed to cleanup the pointers and add
5849 * it back to the list.
5850 */
5851 if (err)
5852 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5853 port_num + 1);
5854
95579e78 5855 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
32f69e4b
DJ		 5856}
5857
5858/* The mlx5_ib_multiport_mutex should be held when calling this function */
5859static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5860 struct mlx5_ib_multiport_info *mpi)
5861{
5862 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5863 int err;
5864
5865 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5866 if (ibdev->port[port_num].mp.mpi) {
2577188e
QH		 5867 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
5868 port_num + 1);
32f69e4b
DJ		 5869 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5870 return false;
5871 }
5872
5873 ibdev->port[port_num].mp.mpi = mpi;
5874 mpi->ibdev = ibdev;
df097a27 5875 mpi->mdev_events.notifier_call = NULL;
32f69e4b
DJ		 5876 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5877
5878 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5879 if (err)
5880 goto unbind;
5881
5882 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5883 if (err)
5884 goto unbind;
5885
5886 err = mlx5_add_netdev_notifier(ibdev, port_num);
5887 if (err) {
5888 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5889 port_num + 1);
5890 goto unbind;
5891 }
5892
df097a27
SM		 5893 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
5894 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
5895
73eb8f03 5896 mlx5_ib_init_cong_debugfs(ibdev, port_num);
a9e546e7 5897
32f69e4b
DJ		 5898 return true;
5899
5900unbind:
5901 mlx5_ib_unbind_slave_port(ibdev, mpi);
5902 return false;
5903}
5904
5905static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5906{
5907 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5908 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5909 port_num + 1);
5910 struct mlx5_ib_multiport_info *mpi;
5911 int err;
5912 int i;
5913
5914 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5915 return 0;
5916
5917 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5918 &dev->sys_image_guid);
5919 if (err)
5920 return err;
5921
5922 err = mlx5_nic_vport_enable_roce(dev->mdev);
5923 if (err)
5924 return err;
5925
5926 mutex_lock(&mlx5_ib_multiport_mutex);
5927 for (i = 0; i < dev->num_ports; i++) {
5928 bool bound = false;
5929
5930 /* build a stub multiport info struct for the native port. */
5931 if (i == port_num) {
5932 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5933 if (!mpi) {
5934 mutex_unlock(&mlx5_ib_multiport_mutex);
5935 mlx5_nic_vport_disable_roce(dev->mdev);
5936 return -ENOMEM;
5937 }
5938
5939 mpi->is_master = true;
5940 mpi->mdev = dev->mdev;
5941 mpi->sys_image_guid = dev->sys_image_guid;
5942 dev->port[i].mp.mpi = mpi;
5943 mpi->ibdev = dev;
5944 mpi = NULL;
5945 continue;
5946 }
5947
5948 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5949 list) {
5950 if (dev->sys_image_guid == mpi->sys_image_guid &&
5951 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5952 bound = mlx5_ib_bind_slave_port(dev, mpi);
5953 }
5954
5955 if (bound) {
c42260f1
VP		 5956 dev_dbg(mpi->mdev->device,
5957 "removing port from unaffiliated list.\n");
32f69e4b
DJ		 5958 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5959 list_del(&mpi->list);
5960 break;
5961 }
5962 }
5963 if (!bound) {
5964 get_port_caps(dev, i + 1);
5965 mlx5_ib_dbg(dev, "no free port found for port %d\n",
5966 i + 1);
5967 }
5968 }
5969
5970 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
5971 mutex_unlock(&mlx5_ib_multiport_mutex);
5972 return err;
5973}
5974
5975static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
5976{
5977 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5978 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5979 port_num + 1);
5980 int i;
5981
5982 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5983 return;
5984
5985 mutex_lock(&mlx5_ib_multiport_mutex);
5986 for (i = 0; i < dev->num_ports; i++) {
5987 if (dev->port[i].mp.mpi) {
5988 /* Destroy the native port stub */
5989 if (i == port_num) {
5990 kfree(dev->port[i].mp.mpi);
5991 dev->port[i].mp.mpi = NULL;
5992 } else {
5993 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
5994 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
5995 }
5996 }
5997 }
5998
5999 mlx5_ib_dbg(dev, "removing from devlist\n");
6000 list_del(&dev->ib_dev_list);
6001 mutex_unlock(&mlx5_ib_multiport_mutex);
6002
6003 mlx5_nic_vport_disable_roce(dev->mdev);
6004}
6005
9a119cd5
JG		 6006ADD_UVERBS_ATTRIBUTES_SIMPLE(
6007 mlx5_ib_dm,
6008 UVERBS_OBJECT_DM,
6009 UVERBS_METHOD_DM_ALLOC,
6010 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
6011 UVERBS_ATTR_TYPE(u64),
83bb4442 6012 UA_MANDATORY),
9a119cd5
JG		 6013 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
6014 UVERBS_ATTR_TYPE(u16),
3b113a1e
AL		 6015 UA_OPTIONAL),
6016 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
6017 enum mlx5_ib_uapi_dm_type,
6018 UA_OPTIONAL));
9a119cd5
JG		 6019
6020ADD_UVERBS_ATTRIBUTES_SIMPLE(
6021 mlx5_ib_flow_action,
6022 UVERBS_OBJECT_FLOW_ACTION,
6023 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
bccd0622
JG		 6024 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
6025 enum mlx5_ib_uapi_flow_action_flags));
c6475a0b 6026
0cbf432d
JG		 6027static const struct uapi_definition mlx5_ib_defs[] = {
6028#if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)
36e235c8 6029 UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
0cbf432d
JG		 6030 UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
6031#endif
8c84660b 6032
0cbf432d
JG		 6033 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION,
6034 &mlx5_ib_flow_action),
6035 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm),
6036 {}
6037};
8c84660b 6038
1a1e03dc
RS		 6039static int mlx5_ib_read_counters(struct ib_counters *counters,
6040 struct ib_counters_read_attr *read_attr,
6041 struct uverbs_attr_bundle *attrs)
6042{
6043 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
6044 struct mlx5_read_counters_attr mread_attr = {};
6045 struct mlx5_ib_flow_counters_desc *desc;
6046 int ret, i;
6047
6048 mutex_lock(&mcounters->mcntrs_mutex);
6049 if (mcounters->cntrs_max_index > read_attr->ncounters) {
6050 ret = -EINVAL;
6051 goto err_bound;
6052 }
6053
6054 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
6055 GFP_KERNEL);
6056 if (!mread_attr.out) {
6057 ret = -ENOMEM;
6058 goto err_bound;
6059 }
6060
6061 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
6062 mread_attr.flags = read_attr->flags;
6063 ret = mcounters->read_counters(counters->device, &mread_attr);
6064 if (ret)
6065 goto err_read;
6066
6067 /* do the pass over the counters data array to assign according to the
6068 * descriptions and indexing pairs
6069 */
6070 desc = mcounters->counters_data;
6071 for (i = 0; i < mcounters->ncounters; i++)
6072 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
6073
6074err_read:
6075 kfree(mread_attr.out);
6076err_bound:
6077 mutex_unlock(&mcounters->mcntrs_mutex);
6078 return ret;
6079}
6080
b29e2a13
RS		 6081static int mlx5_ib_destroy_counters(struct ib_counters *counters)
6082{
6083 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
6084
3b3233fb
RS		 6085 counters_clear_description(counters);
6086 if (mcounters->hw_cntrs_hndl)
6087 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
6088 mcounters->hw_cntrs_hndl);
6089
b29e2a13
RS		 6090 kfree(mcounters);
6091
6092 return 0;
6093}
6094
6095static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
6096 struct uverbs_attr_bundle *attrs)
6097{
6098 struct mlx5_ib_mcounters *mcounters;
6099
6100 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
6101 if (!mcounters)
6102 return ERR_PTR(-ENOMEM);
6103
3b3233fb
RS		 6104 mutex_init(&mcounters->mcntrs_mutex);
6105
b29e2a13
RS		 6106 return &mcounters->ibcntrs;
6107}
6108
fb652d32 6109static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
e126ba97 6110{
32f69e4b 6111 mlx5_ib_cleanup_multiport_master(dev);
13859d5d 6112 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
534fd7aa 6113 srcu_barrier(&dev->mr_srcu);
13859d5d 6114 cleanup_srcu_struct(&dev->mr_srcu);
13859d5d 6115 }
4056b12e
AL		 6116
6117 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
16c1975f
MB		 6118}
6119
fb652d32 6120static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6121{
6122 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 6123 int err;
32f69e4b 6124 int i;
e126ba97 6125
32f69e4b
DJ		 6126 for (i = 0; i < dev->num_ports; i++) {
6127 spin_lock_init(&dev->port[i].mp.mpi_lock);
95579e78 6128 rwlock_init(&dev->port[i].roce.netdev_lock);
d3b5cc1c
MB		 6129 dev->port[i].roce.dev = dev;
6130 dev->port[i].roce.native_port_num = i + 1;
6131 dev->port[i].roce.last_port_state = IB_PORT_DOWN;
32f69e4b
DJ		 6132 }
6133
00815752
MS		 6134 mlx5_ib_internal_fill_odp_caps(dev);
6135
32f69e4b 6136 err = mlx5_ib_init_multiport_master(dev);
e126ba97 6137 if (err)
da796ccb 6138 return err;
e126ba97 6139
a989ea01
MB		 6140 err = set_has_smi_cap(dev);
6141 if (err)
6142 return err;
e126ba97 6143
32f69e4b 6144 if (!mlx5_core_mp_enabled(mdev)) {
32f69e4b
DJ		 6145 for (i = 1; i <= dev->num_ports; i++) {
6146 err = get_port_caps(dev, i);
6147 if (err)
6148 break;
6149 }
6150 } else {
6151 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
6152 }
6153 if (err)
6154 goto err_mp;
6155
1b5daf11
MD		 6156 if (mlx5_use_mad_ifc(dev))
6157 get_ext_port_caps(dev);
e126ba97 6158
e126ba97 6159 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 6160 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
508562d6 6161 dev->ib_dev.phys_port_cnt = dev->num_ports;
f2f3df55 6162 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev);
c42260f1 6163 dev->ib_dev.dev.parent = mdev->device;
e126ba97 6164
3cc297db
MB		 6165 mutex_init(&dev->cap_mask_mutex);
6166 INIT_LIST_HEAD(&dev->qp_list);
6167 spin_lock_init(&dev->reset_flow_resource_lock);
6168
3b113a1e
AL		 6169 spin_lock_init(&dev->dm.lock);
6170 dev->dm.dev = mdev;
24da0016 6171
13859d5d 6172 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
13859d5d 6173 err = init_srcu_struct(&dev->mr_srcu);
a6bc3875 6174 if (err)
c9b9dcb4 6175 goto err_mp;
623d1543 6176 }
3cc297db 6177
16c1975f 6178 return 0;
25c13324 6179
32f69e4b
DJ		 6180err_mp:
6181 mlx5_ib_cleanup_multiport_master(dev);
16c1975f 6182
16c1975f
MB		 6183 return -ENOMEM;
6184}
6185
9a4ca38d
MB		 6186static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
6187{
6188 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
6189
6190 if (!dev->flow_db)
6191 return -ENOMEM;
6192
6193 mutex_init(&dev->flow_db->lock);
6194
6195 return 0;
6196}
6197
6198static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
6199{
6200 kfree(dev->flow_db);
6201}
6202
96458233 6203static const struct ib_device_ops mlx5_ib_dev_ops = {
7a154142 6204 .owner = THIS_MODULE,
b9560a41 6205 .driver_id = RDMA_DRIVER_MLX5,
72c6ec18 6206 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
b9560a41 6207
96458233
KH		 6208 .add_gid = mlx5_ib_add_gid,
6209 .alloc_mr = mlx5_ib_alloc_mr,
6c984472 6210 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
96458233
KH		 6211 .alloc_pd = mlx5_ib_alloc_pd,
6212 .alloc_ucontext = mlx5_ib_alloc_ucontext,
6213 .attach_mcast = mlx5_ib_mcg_attach,
6214 .check_mr_status = mlx5_ib_check_mr_status,
6215 .create_ah = mlx5_ib_create_ah,
6216 .create_counters = mlx5_ib_create_counters,
6217 .create_cq = mlx5_ib_create_cq,
6218 .create_flow = mlx5_ib_create_flow,
6219 .create_qp = mlx5_ib_create_qp,
6220 .create_srq = mlx5_ib_create_srq,
6221 .dealloc_pd = mlx5_ib_dealloc_pd,
6222 .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
6223 .del_gid = mlx5_ib_del_gid,
6224 .dereg_mr = mlx5_ib_dereg_mr,
6225 .destroy_ah = mlx5_ib_destroy_ah,
6226 .destroy_counters = mlx5_ib_destroy_counters,
6227 .destroy_cq = mlx5_ib_destroy_cq,
6228 .destroy_flow = mlx5_ib_destroy_flow,
6229 .destroy_flow_action = mlx5_ib_destroy_flow_action,
6230 .destroy_qp = mlx5_ib_destroy_qp,
6231 .destroy_srq = mlx5_ib_destroy_srq,
6232 .detach_mcast = mlx5_ib_mcg_detach,
6233 .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
6234 .drain_rq = mlx5_ib_drain_rq,
6235 .drain_sq = mlx5_ib_drain_sq,
6236 .get_dev_fw_str = get_dev_fw_str,
6237 .get_dma_mr = mlx5_ib_get_dma_mr,
6238 .get_link_layer = mlx5_ib_port_link_layer,
6239 .map_mr_sg = mlx5_ib_map_mr_sg,
6c984472 6240 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi,
96458233
KH		 6241 .mmap = mlx5_ib_mmap,
6242 .modify_cq = mlx5_ib_modify_cq,
6243 .modify_device = mlx5_ib_modify_device,
6244 .modify_port = mlx5_ib_modify_port,
6245 .modify_qp = mlx5_ib_modify_qp,
6246 .modify_srq = mlx5_ib_modify_srq,
6247 .poll_cq = mlx5_ib_poll_cq,
6248 .post_recv = mlx5_ib_post_recv,
6249 .post_send = mlx5_ib_post_send,
6250 .post_srq_recv = mlx5_ib_post_srq_recv,
6251 .process_mad = mlx5_ib_process_mad,
6252 .query_ah = mlx5_ib_query_ah,
6253 .query_device = mlx5_ib_query_device,
6254 .query_gid = mlx5_ib_query_gid,
6255 .query_pkey = mlx5_ib_query_pkey,
6256 .query_qp = mlx5_ib_query_qp,
6257 .query_srq = mlx5_ib_query_srq,
6258 .read_counters = mlx5_ib_read_counters,
6259 .reg_user_mr = mlx5_ib_reg_user_mr,
6260 .req_notify_cq = mlx5_ib_arm_cq,
6261 .rereg_user_mr = mlx5_ib_rereg_user_mr,
6262 .resize_cq = mlx5_ib_resize_cq,
d3456914
LR		 6263
6264 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
e39afe3d 6265 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
21a428a0 6266 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
68e326de 6267 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
a2a074ef 6268 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
96458233
KH		 6269};
6270
6271static const struct ib_device_ops mlx5_ib_dev_flow_ipsec_ops = {
6272 .create_flow_action_esp = mlx5_ib_create_flow_action_esp,
6273 .modify_flow_action_esp = mlx5_ib_modify_flow_action_esp,
6274};
6275
6276static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
6277 .rdma_netdev_get_params = mlx5_ib_rn_get_params,
6278};
6279
6280static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
6281 .get_vf_config = mlx5_ib_get_vf_config,
6282 .get_vf_stats = mlx5_ib_get_vf_stats,
6283 .set_vf_guid = mlx5_ib_set_vf_guid,
6284 .set_vf_link_state = mlx5_ib_set_vf_link_state,
6285};
6286
6287static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
6288 .alloc_mw = mlx5_ib_alloc_mw,
6289 .dealloc_mw = mlx5_ib_dealloc_mw,
6290};
6291
6292static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
6293 .alloc_xrcd = mlx5_ib_alloc_xrcd,
6294 .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
6295};
6296
6297static const struct ib_device_ops mlx5_ib_dev_dm_ops = {
6298 .alloc_dm = mlx5_ib_alloc_dm,
6299 .dealloc_dm = mlx5_ib_dealloc_dm,
6300 .reg_dm_mr = mlx5_ib_reg_dm_mr,
6301};
6302
fb652d32 6303static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6304{
6305 struct mlx5_core_dev *mdev = dev->mdev;
16c1975f
MB		 6306 int err;
6307
e126ba97
EC		 6308 dev->ib_dev.uverbs_cmd_mask =
6309 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
6310 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
6311 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
6312 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
6313 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 6314 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
6315 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 6316 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 6317 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 6318 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
6319 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
6320 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
6321 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
6322 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
6323 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
6324 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
6325 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
6326 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
6327 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
6328 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
6329 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
6330 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
6331 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
6332 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
6333 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
6334 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 6335 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 6336 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
6337 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349 6338 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
b0e9df6d 6339 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
96458233
KH		 6340 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ) |
6341 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
6342 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
6343
f6a8a19b
DD		 6344 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
6345 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
96458233
KH		 6346 ib_set_device_ops(&dev->ib_dev,
6347 &mlx5_ib_dev_ipoib_enhanced_ops);
8e959601 6348
96458233
KH		 6349 if (mlx5_core_is_pf(mdev))
6350 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
7c2344c3 6351
6e8484c5
MG		 6352 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
6353
d2370e0a 6354 if (MLX5_CAP_GEN(mdev, imaicl)) {
d2370e0a
MB		 6355 dev->ib_dev.uverbs_cmd_mask |=
6356 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
6357 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
96458233 6358 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
d2370e0a
MB		 6359 }
6360
938fe83c 6361 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 6362 dev->ib_dev.uverbs_cmd_mask |=
6363 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
6364 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
96458233 6365 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
e126ba97
EC		 6366 }
6367
25c13324
AL		 6368 if (MLX5_CAP_DEV_MEM(mdev, memic) ||
6369 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
6370 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
96458233 6371 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
24da0016 6372
dfb631a1 6373 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
96458233
KH		 6374 MLX5_ACCEL_IPSEC_CAP_DEVICE)
6375 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_flow_ipsec_ops);
96458233 6376 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
81e30880 6377
36e235c8
JG		 6378 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
6379 dev->ib_dev.driver_def = mlx5_ib_defs;
81e30880 6380
e126ba97
EC		 6381 err = init_node_data(dev);
6382 if (err)
16c1975f 6383 return err;
e126ba97 6384
c8b89924 6385 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
e7996a9a
JG		 6386 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
6387 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
a560f1d9 6388 mutex_init(&dev->lb.mutex);
c8b89924 6389
96e2fd73
LR		 6390 dev->ib_dev.use_cq_dim = true;
6391
16c1975f
MB		 6392 return 0;
6393}
6394
96458233
KH		 6395static const struct ib_device_ops mlx5_ib_dev_port_ops = {
6396 .get_port_immutable = mlx5_port_immutable,
6397 .query_port = mlx5_ib_query_port,
6398};
6399
8e6efa3a
MB		 6400static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
6401{
96458233 6402 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
8e6efa3a
MB		 6403 return 0;
6404}
6405
96458233
KH		 6406static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
6407 .get_port_immutable = mlx5_port_rep_immutable,
6408 .query_port = mlx5_ib_rep_query_port,
6409};
6410
fb652d32 6411static int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
8e6efa3a 6412{
96458233 6413 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
8e6efa3a
MB		 6414 return 0;
6415}
6416
96458233
KH		 6417static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
6418 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
6419 .create_wq = mlx5_ib_create_wq,
6420 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
6421 .destroy_wq = mlx5_ib_destroy_wq,
6422 .get_netdev = mlx5_ib_get_netdev,
6423 .modify_wq = mlx5_ib_modify_wq,
6424};
6425
e3f1ed1f 6426static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
8e6efa3a 6427{
e3f1ed1f 6428 u8 port_num;
8e6efa3a 6429
8e6efa3a
MB		 6430 dev->ib_dev.uverbs_ex_cmd_mask |=
6431 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
6432 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
6433 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
6434 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
6435 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
96458233 6436 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
8e6efa3a 6437
e3f1ed1f
LR		 6438 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6439
26628e2d 6440 /* Register only for native ports */
8e6efa3a
MB		 6441 return mlx5_add_netdev_notifier(dev, port_num);
6442}
6443
6444static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
6445{
6446 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6447
6448 mlx5_remove_netdev_notifier(dev, port_num);
6449}
6450
fb652d32 6451static int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
8e6efa3a
MB		 6452{
6453 struct mlx5_core_dev *mdev = dev->mdev;
6454 enum rdma_link_layer ll;
6455 int port_type_cap;
6456 int err = 0;
8e6efa3a 6457
8e6efa3a
MB		 6458 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6459 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6460
6461 if (ll == IB_LINK_LAYER_ETHERNET)
e3f1ed1f 6462 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 6463
6464 return err;
6465}
6466
fb652d32 6467static void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
8e6efa3a
MB		 6468{
6469 mlx5_ib_stage_common_roce_cleanup(dev);
6470}
6471
16c1975f
MB		 6472static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
6473{
6474 struct mlx5_core_dev *mdev = dev->mdev;
6475 enum rdma_link_layer ll;
6476 int port_type_cap;
6477 int err;
6478
6479 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6480 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6481
fc24fc5e 6482 if (ll == IB_LINK_LAYER_ETHERNET) {
e3f1ed1f 6483 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 6484 if (err)
6485 return err;
7fd8aefb 6486
e3f1ed1f 6487 err = mlx5_enable_eth(dev);
fc24fc5e 6488 if (err)
8e6efa3a 6489 goto cleanup;
fc24fc5e
AS		 6490 }
6491
16c1975f 6492 return 0;
8e6efa3a
MB		 6493cleanup:
6494 mlx5_ib_stage_common_roce_cleanup(dev);
6495
6496 return err;
16c1975f 6497}
e126ba97 6498
16c1975f
MB		 6499static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
6500{
6501 struct mlx5_core_dev *mdev = dev->mdev;
6502 enum rdma_link_layer ll;
6503 int port_type_cap;
e126ba97 6504
16c1975f
MB		 6505 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6506 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6507
6508 if (ll == IB_LINK_LAYER_ETHERNET) {
6509 mlx5_disable_eth(dev);
8e6efa3a 6510 mlx5_ib_stage_common_roce_cleanup(dev);
45bded2c 6511 }
16c1975f 6512}
6aec21f6 6513
fb652d32 6514static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6515{
6516 return create_dev_resources(&dev->devr);
6517}
6518
fb652d32 6519static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6520{
6521 destroy_dev_resources(&dev->devr);
6522}
6523
6524static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
6525{
6526 return mlx5_ib_odp_init_one(dev);
6527}
4a2da0b8 6528
f3ffed0c 6529static void mlx5_ib_stage_odp_cleanup(struct mlx5_ib_dev *dev)
d5d284b8
SM		 6530{
6531 mlx5_ib_odp_cleanup_one(dev);
6532}
6533
96458233
KH		 6534static const struct ib_device_ops mlx5_ib_dev_hw_stats_ops = {
6535 .alloc_hw_stats = mlx5_ib_alloc_hw_stats,
6536 .get_hw_stats = mlx5_ib_get_hw_stats,
45842fc6
MZ		 6537 .counter_bind_qp = mlx5_ib_counter_bind_qp,
6538 .counter_unbind_qp = mlx5_ib_counter_unbind_qp,
6539 .counter_dealloc = mlx5_ib_counter_dealloc,
18d422ce
MZ		 6540 .counter_alloc_stats = mlx5_ib_counter_alloc_stats,
6541 .counter_update_stats = mlx5_ib_counter_update_stats,
96458233
KH		 6542};
6543
fb652d32 6544static int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
16c1975f 6545{
5e1e7612 6546 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
96458233 6547 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_hw_stats_ops);
5e1e7612
MB		 6548
6549 return mlx5_ib_alloc_counters(dev);
6550 }
16c1975f
MB		 6551
6552 return 0;
6553}
6554
fb652d32 6555static void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6556{
6557 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
6558 mlx5_ib_dealloc_counters(dev);
6559}
6560
6561static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
6562{
73eb8f03
GKH		 6563 mlx5_ib_init_cong_debugfs(dev,
6564 mlx5_core_native_port_num(dev->mdev) - 1);
6565 return 0;
16c1975f
MB		 6566}
6567
6568static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
6569{
a9e546e7
PP		 6570 mlx5_ib_cleanup_cong_debugfs(dev,
6571 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 6572}
6573
6574static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
6575{
5fe9dec0 6576 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
444261ca 6577 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
16c1975f
MB		 6578}
6579
6580static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
6581{
6582 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
6583}
6584
fb652d32 6585static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6586{
6587 int err;
5fe9dec0
EC		 6588
6589 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
6590 if (err)
16c1975f 6591 return err;
5fe9dec0
EC		 6592
6593 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
6594 if (err)
16c1975f 6595 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5fe9dec0 6596
16c1975f
MB		 6597 return err;
6598}
0837e86a 6599
fb652d32 6600static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6601{
6602 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6603 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
6604}
e126ba97 6605
fb652d32 6606static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
16c1975f 6607{
e349f858
JG		 6608 const char *name;
6609
508a523f 6610 rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group);
7c34ec19 6611 if (!mlx5_lag_is_roce(dev->mdev))
e349f858
JG		 6612 name = "mlx5_%d";
6613 else
6614 name = "mlx5_bond_%d";
ea4baf7f 6615 return ib_register_device(&dev->ib_dev, name);
16c1975f
MB		 6616}
6617
fb652d32 6618static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
16c1975f 6619{
42cea83f 6620 destroy_umrc_res(dev);
16c1975f
MB		 6621}
6622
fb652d32 6623static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
16c1975f 6624{
42cea83f 6625 ib_unregister_device(&dev->ib_dev);
16c1975f
MB		 6626}
6627
fb652d32 6628static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
16c1975f 6629{
42cea83f 6630 return create_umr_res(dev);
16c1975f
MB		 6631}
6632
6633static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
6634{
03404e8a
MG		 6635 init_delay_drop(dev);
6636
16c1975f
MB		 6637 return 0;
6638}
6639
6640static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
6641{
6642 cancel_delay_drop(dev);
6643}
6644
df097a27
SM		 6645static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
6646{
6647 dev->mdev_events.notifier_call = mlx5_ib_event;
6648 mlx5_notifier_register(dev->mdev, &dev->mdev_events);
6649 return 0;
6650}
6651
6652static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
6653{
6654 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
6655}
6656
81773ce5
LR		 6657static int mlx5_ib_stage_devx_init(struct mlx5_ib_dev *dev)
6658{
6659 int uid;
6660
fb98153b 6661 uid = mlx5_ib_devx_create(dev, false);
e337dd53 6662 if (uid > 0) {
81773ce5 6663 dev->devx_whitelist_uid = uid;
e337dd53
YH		 6664 mlx5_ib_devx_init_event_table(dev);
6665 }
81773ce5
LR		 6666
6667 return 0;
6668}
6669static void mlx5_ib_stage_devx_cleanup(struct mlx5_ib_dev *dev)
6670{
e337dd53
YH		 6671 if (dev->devx_whitelist_uid) {
6672 mlx5_ib_devx_cleanup_event_table(dev);
81773ce5 6673 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid);
e337dd53 6674 }
81773ce5
LR		 6675}
6676
b5ca15ad
MB		 6677void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
6678 const struct mlx5_ib_profile *profile,
6679 int stage)
16c1975f
MB		 6680{
6681 /* Number of stages to cleanup */
6682 while (stage) {
6683 stage--;
6684 if (profile->stage[stage].cleanup)
6685 profile->stage[stage].cleanup(dev);
6686 }
4a6dc855 6687
da796ccb 6688 kfree(dev->port);
4a6dc855 6689 ib_dealloc_device(&dev->ib_dev);
16c1975f 6690}
e126ba97 6691
b5ca15ad
MB		 6692void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
6693 const struct mlx5_ib_profile *profile)
16c1975f 6694{
16c1975f
MB		 6695 int err;
6696 int i;
5fe9dec0 6697
16c1975f
MB		 6698 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
6699 if (profile->stage[i].init) {
6700 err = profile->stage[i].init(dev);
6701 if (err)
6702 goto err_out;
6703 }
6704 }
0837e86a 6705
16c1975f
MB		 6706 dev->profile = profile;
6707 dev->ib_active = true;
6aec21f6 6708
16c1975f 6709 return dev;
e126ba97 6710
16c1975f
MB		 6711err_out:
6712 __mlx5_ib_remove(dev, profile, i);
fc24fc5e 6713
16c1975f
MB		 6714 return NULL;
6715}
0837e86a 6716
16c1975f
MB		 6717static const struct mlx5_ib_profile pf_profile = {
6718 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6719 mlx5_ib_stage_init_init,
6720 mlx5_ib_stage_init_cleanup),
9a4ca38d
MB		 6721 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6722 mlx5_ib_stage_flow_db_init,
6723 mlx5_ib_stage_flow_db_cleanup),
16c1975f
MB		 6724 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6725 mlx5_ib_stage_caps_init,
6726 NULL),
8e6efa3a
MB		 6727 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6728 mlx5_ib_stage_non_default_cb,
6729 NULL),
16c1975f
MB		 6730 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6731 mlx5_ib_stage_roce_init,
6732 mlx5_ib_stage_roce_cleanup),
f3da6577
LR		 6733 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6734 mlx5_init_srq_table,
6735 mlx5_cleanup_srq_table),
16c1975f
MB		 6736 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6737 mlx5_ib_stage_dev_res_init,
6738 mlx5_ib_stage_dev_res_cleanup),
df097a27
SM		 6739 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6740 mlx5_ib_stage_dev_notifier_init,
6741 mlx5_ib_stage_dev_notifier_cleanup),
16c1975f
MB		 6742 STAGE_CREATE(MLX5_IB_STAGE_ODP,
6743 mlx5_ib_stage_odp_init,
d5d284b8 6744 mlx5_ib_stage_odp_cleanup),
16c1975f
MB		 6745 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6746 mlx5_ib_stage_counters_init,
6747 mlx5_ib_stage_counters_cleanup),
6748 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
6749 mlx5_ib_stage_cong_debugfs_init,
6750 mlx5_ib_stage_cong_debugfs_cleanup),
6751 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6752 mlx5_ib_stage_uar_init,
6753 mlx5_ib_stage_uar_cleanup),
6754 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6755 mlx5_ib_stage_bfrag_init,
6756 mlx5_ib_stage_bfrag_cleanup),
42cea83f
MB		 6757 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6758 NULL,
6759 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
81773ce5
LR		 6760 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
6761 mlx5_ib_stage_devx_init,
6762 mlx5_ib_stage_devx_cleanup),
16c1975f
MB		 6763 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6764 mlx5_ib_stage_ib_reg_init,
6765 mlx5_ib_stage_ib_reg_cleanup),
42cea83f
MB		 6766 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6767 mlx5_ib_stage_post_ib_reg_umr_init,
6768 NULL),
16c1975f
MB		 6769 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
6770 mlx5_ib_stage_delay_drop_init,
6771 mlx5_ib_stage_delay_drop_cleanup),
16c1975f 6772};
e126ba97 6773
f0666f1f 6774const struct mlx5_ib_profile uplink_rep_profile = {
b5ca15ad
MB		 6775 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6776 mlx5_ib_stage_init_init,
6777 mlx5_ib_stage_init_cleanup),
6778 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6779 mlx5_ib_stage_flow_db_init,
6780 mlx5_ib_stage_flow_db_cleanup),
6781 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6782 mlx5_ib_stage_caps_init,
6783 NULL),
6784 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6785 mlx5_ib_stage_rep_non_default_cb,
6786 NULL),
6787 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6788 mlx5_ib_stage_rep_roce_init,
6789 mlx5_ib_stage_rep_roce_cleanup),
f3da6577
LR		 6790 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6791 mlx5_init_srq_table,
6792 mlx5_cleanup_srq_table),
b5ca15ad
MB		 6793 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6794 mlx5_ib_stage_dev_res_init,
6795 mlx5_ib_stage_dev_res_cleanup),
df097a27
SM		 6796 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6797 mlx5_ib_stage_dev_notifier_init,
6798 mlx5_ib_stage_dev_notifier_cleanup),
b5ca15ad
MB		 6799 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6800 mlx5_ib_stage_counters_init,
6801 mlx5_ib_stage_counters_cleanup),
6802 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6803 mlx5_ib_stage_uar_init,
6804 mlx5_ib_stage_uar_cleanup),
6805 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6806 mlx5_ib_stage_bfrag_init,
6807 mlx5_ib_stage_bfrag_cleanup),
03fe2deb
DM		 6808 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6809 NULL,
6810 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
7f575103
MB		 6811 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
6812 mlx5_ib_stage_devx_init,
6813 mlx5_ib_stage_devx_cleanup),
b5ca15ad
MB		 6814 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6815 mlx5_ib_stage_ib_reg_init,
6816 mlx5_ib_stage_ib_reg_cleanup),
03fe2deb
DM		 6817 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6818 mlx5_ib_stage_post_ib_reg_umr_init,
6819 NULL),
b5ca15ad
MB		 6820};
6821
e3f1ed1f 6822static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
32f69e4b
DJ		 6823{
6824 struct mlx5_ib_multiport_info *mpi;
6825 struct mlx5_ib_dev *dev;
6826 bool bound = false;
6827 int err;
6828
6829 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6830 if (!mpi)
6831 return NULL;
6832
6833 mpi->mdev = mdev;
6834
6835 err = mlx5_query_nic_vport_system_image_guid(mdev,
6836 &mpi->sys_image_guid);
6837 if (err) {
6838 kfree(mpi);
6839 return NULL;
6840 }
6841
6842 mutex_lock(&mlx5_ib_multiport_mutex);
6843 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
6844 if (dev->sys_image_guid == mpi->sys_image_guid)
6845 bound = mlx5_ib_bind_slave_port(dev, mpi);
6846
6847 if (bound) {
6848 rdma_roce_rescan_device(&dev->ib_dev);
6849 break;
6850 }
6851 }
6852
6853 if (!bound) {
6854 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
c42260f1
VP		 6855 dev_dbg(mdev->device,
6856 "no suitable IB device found to bind to, added to unaffiliated list.\n");
32f69e4b
DJ		 6857 }
6858 mutex_unlock(&mlx5_ib_multiport_mutex);
6859
6860 return mpi;
6861}
6862
16c1975f
MB		 6863static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
6864{
32f69e4b 6865 enum rdma_link_layer ll;
b5ca15ad 6866 struct mlx5_ib_dev *dev;
32f69e4b 6867 int port_type_cap;
da796ccb 6868 int num_ports;
32f69e4b 6869
b5ca15ad
MB		 6870 printk_once(KERN_INFO "%s", mlx5_version);
6871
f0666f1f 6872 if (MLX5_ESWITCH_MANAGER(mdev) &&
f6455de0 6873 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
5fb58c9e
MB		 6874 if (!mlx5_core_mp_enabled(mdev))
6875 mlx5_ib_register_vport_reps(mdev);
f0666f1f
BW		 6876 return mdev;
6877 }
6878
32f69e4b
DJ		 6879 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6880 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6881
e3f1ed1f
LR		 6882 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
6883 return mlx5_ib_add_slave_port(mdev);
32f69e4b 6884
da796ccb
MB		 6885 num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
6886 MLX5_CAP_GEN(mdev, num_vhca_ports));
459cc69f 6887 dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
b5ca15ad
MB		 6888 if (!dev)
6889 return NULL;
da796ccb
MB		 6890 dev->port = kcalloc(num_ports, sizeof(*dev->port),
6891 GFP_KERNEL);
6892 if (!dev->port) {
6893 ib_dealloc_device((struct ib_device *)dev);
6894 return NULL;
6895 }
b5ca15ad
MB		 6896
6897 dev->mdev = mdev;
da796ccb 6898 dev->num_ports = num_ports;
b5ca15ad 6899
b5ca15ad 6900 return __mlx5_ib_add(dev, &pf_profile);
e126ba97
EC		 6901}
6902
9603b61d 6903static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 6904{
32f69e4b
DJ		 6905 struct mlx5_ib_multiport_info *mpi;
6906 struct mlx5_ib_dev *dev;
6907
f0666f1f
BW		 6908 if (MLX5_ESWITCH_MANAGER(mdev) && context == mdev) {
6909 mlx5_ib_unregister_vport_reps(mdev);
6910 return;
6911 }
6912
32f69e4b
DJ		 6913 if (mlx5_core_is_mp_slave(mdev)) {
6914 mpi = context;
6915 mutex_lock(&mlx5_ib_multiport_mutex);
6916 if (mpi->ibdev)
6917 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
6918 list_del(&mpi->list);
6919 mutex_unlock(&mlx5_ib_multiport_mutex);
6920 return;
6921 }
6aec21f6 6922
32f69e4b 6923 dev = context;
f0666f1f 6924 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
e126ba97
EC		 6925}
6926
9603b61d
JM		 6927static struct mlx5_interface mlx5_ib_interface = {
6928 .add = mlx5_ib_add,
6929 .remove = mlx5_ib_remove,
64613d94 6930 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 6931};
6932
c44ef998
IL		 6933unsigned long mlx5_ib_get_xlt_emergency_page(void)
6934{
6935 mutex_lock(&xlt_emergency_page_mutex);
6936 return xlt_emergency_page;
6937}
6938
6939void mlx5_ib_put_xlt_emergency_page(void)
6940{
6941 mutex_unlock(&xlt_emergency_page_mutex);
6942}
6943
e126ba97
EC		 6944static int __init mlx5_ib_init(void)
6945{
6aec21f6
HE		 6946 int err;
6947
c44ef998
IL		 6948 xlt_emergency_page = __get_free_page(GFP_KERNEL);
6949 if (!xlt_emergency_page)
6950 return -ENOMEM;
6951
6952 mutex_init(&xlt_emergency_page_mutex);
6953
d69a24e0 6954 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
c44ef998
IL		 6955 if (!mlx5_ib_event_wq) {
6956 free_page(xlt_emergency_page);
d69a24e0 6957 return -ENOMEM;
c44ef998 6958 }
d69a24e0 6959
81713d37 6960 mlx5_ib_odp_init();
9603b61d 6961
6aec21f6 6962 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 6963
6aec21f6 6964 return err;
e126ba97
EC		 6965}
6966
6967static void __exit mlx5_ib_cleanup(void)
6968{
9603b61d 6969 mlx5_unregister_interface(&mlx5_ib_interface);
d69a24e0 6970 destroy_workqueue(mlx5_ib_event_wq);
c44ef998
IL		 6971 mutex_destroy(&xlt_emergency_page_mutex);
6972 free_page(xlt_emergency_page);
e126ba97
EC		 6973}
6974
6975module_init(mlx5_ib_init);
6976module_exit(mlx5_ib_cleanup);
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