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IB/hfi1: Get rid of a warning
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
24da0016 41#include <linux/bitmap.h>
e126ba97 42#include <linux/sched.h>
6e84f315 43#include <linux/sched/mm.h>
0881e7bd 44#include <linux/sched/task.h>
7c2344c3 45#include <linux/delay.h>
e126ba97 46#include <rdma/ib_user_verbs.h>
3f89a643 47#include <rdma/ib_addr.h>
2811ba51 48#include <rdma/ib_cache.h>
ada68c31 49#include <linux/mlx5/port.h>
1b5daf11 50#include <linux/mlx5/vport.h>
72c7fe90 51#include <linux/mlx5/fs.h>
cecae747 52#include <linux/mlx5/eswitch.h>
7c2344c3 53#include <linux/list.h>
e126ba97
EC		 54#include <rdma/ib_smi.h>
55#include <rdma/ib_umem.h>
038d2ef8
MG		 56#include <linux/in.h>
57#include <linux/etherdevice.h>
e126ba97 58#include "mlx5_ib.h"
fc385b7a 59#include "ib_rep.h"
e1f24a79 60#include "cmd.h"
f3da6577 61#include "srq.h"
3346c487 62#include <linux/mlx5/fs_helpers.h>
c6475a0b 63#include <linux/mlx5/accel.h>
8c84660b 64#include <rdma/uverbs_std_types.h>
c6475a0b
AY		 65#include <rdma/mlx5_user_ioctl_verbs.h>
66#include <rdma/mlx5_user_ioctl_cmds.h>
4061ff7a 67#include <rdma/ib_umem_odp.h>
8c84660b
MB		 68
69#define UVERBS_MODULE_NAME mlx5_ib
70#include <rdma/uverbs_named_ioctl.h>
e126ba97
EC		 71
72#define DRIVER_NAME "mlx5_ib"
b359911d 73#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 74
75MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
76MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
77MODULE_LICENSE("Dual BSD/GPL");
e126ba97 78
e126ba97
EC		 79static char mlx5_version[] =
80 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 81 DRIVER_VERSION "\n";
e126ba97 82
d69a24e0
DJ		 83struct mlx5_ib_event_work {
84 struct work_struct work;
df097a27
SM		 85 union {
86 struct mlx5_ib_dev *dev;
87 struct mlx5_ib_multiport_info *mpi;
88 };
89 bool is_slave;
134e9349 90 unsigned int event;
df097a27 91 void *param;
d69a24e0
DJ		 92};
93
da7525d2
EBE		 94enum {
95 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
96};
97
d69a24e0 98static struct workqueue_struct *mlx5_ib_event_wq;
32f69e4b
DJ		 99static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
100static LIST_HEAD(mlx5_ib_dev_list);
101/*
102 * This mutex should be held when accessing either of the above lists
103 */
104static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
105
c44ef998
IL		 106/* We can't use an array for xlt_emergency_page because dma_map_single
107 * doesn't work on kernel modules memory
108 */
109static unsigned long xlt_emergency_page;
110static struct mutex xlt_emergency_page_mutex;
111
32f69e4b
DJ		 112struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
113{
114 struct mlx5_ib_dev *dev;
115
116 mutex_lock(&mlx5_ib_multiport_mutex);
117 dev = mpi->ibdev;
118 mutex_unlock(&mlx5_ib_multiport_mutex);
119 return dev;
120}
121
1b5daf11 122static enum rdma_link_layer
ebd61f68 123mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 124{
ebd61f68 125 switch (port_type_cap) {
1b5daf11
MD		 126 case MLX5_CAP_PORT_TYPE_IB:
127 return IB_LINK_LAYER_INFINIBAND;
128 case MLX5_CAP_PORT_TYPE_ETH:
129 return IB_LINK_LAYER_ETHERNET;
130 default:
131 return IB_LINK_LAYER_UNSPECIFIED;
132 }
133}
134
ebd61f68
AS		 135static enum rdma_link_layer
136mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
137{
138 struct mlx5_ib_dev *dev = to_mdev(device);
139 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
140
141 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
142}
143
fd65f1b8
MS		 144static int get_port_state(struct ib_device *ibdev,
145 u8 port_num,
146 enum ib_port_state *state)
147{
148 struct ib_port_attr attr;
149 int ret;
150
151 memset(&attr, 0, sizeof(attr));
3023a1e9 152 ret = ibdev->ops.query_port(ibdev, port_num, &attr);
fd65f1b8
MS		 153 if (!ret)
154 *state = attr.state;
155 return ret;
156}
157
35b0aa67
MB		 158static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
159 struct net_device *ndev,
160 u8 *port_num)
161{
162 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
163 struct net_device *rep_ndev;
164 struct mlx5_ib_port *port;
165 int i;
166
167 for (i = 0; i < dev->num_ports; i++) {
168 port = &dev->port[i];
169 if (!port->rep)
170 continue;
171
172 read_lock(&port->roce.netdev_lock);
173 rep_ndev = mlx5_ib_get_rep_netdev(esw,
174 port->rep->vport);
175 if (rep_ndev == ndev) {
176 read_unlock(&port->roce.netdev_lock);
177 *port_num = i + 1;
178 return &port->roce;
179 }
180 read_unlock(&port->roce.netdev_lock);
181 }
182
183 return NULL;
184}
185
fc24fc5e
AS		 186static int mlx5_netdev_event(struct notifier_block *this,
187 unsigned long event, void *ptr)
188{
7fd8aefb 189 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
fc24fc5e 190 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
7fd8aefb
DJ		 191 u8 port_num = roce->native_port_num;
192 struct mlx5_core_dev *mdev;
193 struct mlx5_ib_dev *ibdev;
194
195 ibdev = roce->dev;
32f69e4b
DJ		 196 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
197 if (!mdev)
198 return NOTIFY_DONE;
fc24fc5e 199
5ec8c83e
AH		 200 switch (event) {
201 case NETDEV_REGISTER:
35b0aa67
MB		 202 /* Should already be registered during the load */
203 if (ibdev->is_rep)
204 break;
7fd8aefb 205 write_lock(&roce->netdev_lock);
dce45af5 206 if (ndev->dev.parent == mdev->device)
842a9c83 207 roce->netdev = ndev;
7fd8aefb 208 write_unlock(&roce->netdev_lock);
5ec8c83e 209 break;
fc24fc5e 210
842a9c83 211 case NETDEV_UNREGISTER:
35b0aa67 212 /* In case of reps, ib device goes away before the netdevs */
842a9c83
OG		 213 write_lock(&roce->netdev_lock);
214 if (roce->netdev == ndev)
215 roce->netdev = NULL;
216 write_unlock(&roce->netdev_lock);
217 break;
218
fd65f1b8 219 case NETDEV_CHANGE:
5ec8c83e 220 case NETDEV_UP:
88621dfe 221 case NETDEV_DOWN: {
7fd8aefb 222 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe
AH		 223 struct net_device *upper = NULL;
224
225 if (lag_ndev) {
226 upper = netdev_master_upper_dev_get(lag_ndev);
227 dev_put(lag_ndev);
228 }
229
35b0aa67
MB		 230 if (ibdev->is_rep)
231 roce = mlx5_get_rep_roce(ibdev, ndev, &port_num);
232 if (!roce)
233 return NOTIFY_DONE;
7fd8aefb 234 if ((upper == ndev || (!upper && ndev == roce->netdev))
88621dfe 235 && ibdev->ib_active) {
626bc02d 236 struct ib_event ibev = { };
fd65f1b8 237 enum ib_port_state port_state;
5ec8c83e 238
7fd8aefb
DJ		 239 if (get_port_state(&ibdev->ib_dev, port_num,
240 &port_state))
241 goto done;
fd65f1b8 242
7fd8aefb
DJ		 243 if (roce->last_port_state == port_state)
244 goto done;
fd65f1b8 245
7fd8aefb 246 roce->last_port_state = port_state;
5ec8c83e 247 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 248 if (port_state == IB_PORT_DOWN)
249 ibev.event = IB_EVENT_PORT_ERR;
250 else if (port_state == IB_PORT_ACTIVE)
251 ibev.event = IB_EVENT_PORT_ACTIVE;
252 else
7fd8aefb 253 goto done;
fd65f1b8 254
7fd8aefb 255 ibev.element.port_num = port_num;
5ec8c83e
AH		 256 ib_dispatch_event(&ibev);
257 }
258 break;
88621dfe 259 }
fc24fc5e 260
5ec8c83e
AH		 261 default:
262 break;
263 }
7fd8aefb 264done:
32f69e4b 265 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 266 return NOTIFY_DONE;
267}
268
269static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
270 u8 port_num)
271{
272 struct mlx5_ib_dev *ibdev = to_mdev(device);
273 struct net_device *ndev;
32f69e4b
DJ		 274 struct mlx5_core_dev *mdev;
275
276 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
277 if (!mdev)
278 return NULL;
fc24fc5e 279
32f69e4b 280 ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe 281 if (ndev)
32f69e4b 282 goto out;
88621dfe 283
fc24fc5e
AS		 284 /* Ensure ndev does not disappear before we invoke dev_hold()
285 */
95579e78
MB		 286 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock);
287 ndev = ibdev->port[port_num - 1].roce.netdev;
fc24fc5e
AS		 288 if (ndev)
289 dev_hold(ndev);
95579e78 290 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock);
fc24fc5e 291
32f69e4b
DJ		 292out:
293 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 294 return ndev;
295}
296
32f69e4b
DJ		 297struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
298 u8 ib_port_num,
299 u8 *native_port_num)
300{
301 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
302 ib_port_num);
303 struct mlx5_core_dev *mdev = NULL;
304 struct mlx5_ib_multiport_info *mpi;
305 struct mlx5_ib_port *port;
306
210b1f78
MB		 307 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
308 ll != IB_LINK_LAYER_ETHERNET) {
309 if (native_port_num)
310 *native_port_num = ib_port_num;
311 return ibdev->mdev;
312 }
313
32f69e4b
DJ		 314 if (native_port_num)
315 *native_port_num = 1;
316
32f69e4b
DJ		 317 port = &ibdev->port[ib_port_num - 1];
318 if (!port)
319 return NULL;
320
321 spin_lock(&port->mp.mpi_lock);
322 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
323 if (mpi && !mpi->unaffiliate) {
324 mdev = mpi->mdev;
325 /* If it's the master no need to refcount, it'll exist
326 * as long as the ib_dev exists.
327 */
328 if (!mpi->is_master)
329 mpi->mdev_refcnt++;
330 }
331 spin_unlock(&port->mp.mpi_lock);
332
333 return mdev;
334}
335
336void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
337{
338 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
339 port_num);
340 struct mlx5_ib_multiport_info *mpi;
341 struct mlx5_ib_port *port;
342
343 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
344 return;
345
346 port = &ibdev->port[port_num - 1];
347
348 spin_lock(&port->mp.mpi_lock);
349 mpi = ibdev->port[port_num - 1].mp.mpi;
350 if (mpi->is_master)
351 goto out;
352
353 mpi->mdev_refcnt--;
354 if (mpi->unaffiliate)
355 complete(&mpi->unref_comp);
356out:
357 spin_unlock(&port->mp.mpi_lock);
358}
359
08e8676f
AL		 360static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, u8 *active_speed,
361 u8 *active_width)
f1b65df5
NO		 362{
363 switch (eth_proto_oper) {
364 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
365 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
366 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
367 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
368 *active_width = IB_WIDTH_1X;
369 *active_speed = IB_SPEED_SDR;
370 break;
371 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
372 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
373 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
374 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
375 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
376 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
377 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
378 *active_width = IB_WIDTH_1X;
379 *active_speed = IB_SPEED_QDR;
380 break;
381 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
382 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
383 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
384 *active_width = IB_WIDTH_1X;
385 *active_speed = IB_SPEED_EDR;
386 break;
387 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
388 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
389 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
390 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
391 *active_width = IB_WIDTH_4X;
392 *active_speed = IB_SPEED_QDR;
393 break;
394 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
395 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
396 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
397 *active_width = IB_WIDTH_1X;
398 *active_speed = IB_SPEED_HDR;
399 break;
400 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
401 *active_width = IB_WIDTH_4X;
402 *active_speed = IB_SPEED_FDR;
403 break;
404 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
405 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
406 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
407 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
408 *active_width = IB_WIDTH_4X;
409 *active_speed = IB_SPEED_EDR;
410 break;
411 default:
412 return -EINVAL;
413 }
414
415 return 0;
416}
417
08e8676f
AL		 418static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed,
419 u8 *active_width)
420{
421 switch (eth_proto_oper) {
422 case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
423 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
424 *active_width = IB_WIDTH_1X;
425 *active_speed = IB_SPEED_SDR;
426 break;
427 case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
428 *active_width = IB_WIDTH_1X;
429 *active_speed = IB_SPEED_DDR;
430 break;
431 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
432 *active_width = IB_WIDTH_1X;
433 *active_speed = IB_SPEED_QDR;
434 break;
435 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
436 *active_width = IB_WIDTH_4X;
437 *active_speed = IB_SPEED_QDR;
438 break;
439 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
440 *active_width = IB_WIDTH_1X;
441 *active_speed = IB_SPEED_EDR;
442 break;
443 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
cd272875
AL		 444 *active_width = IB_WIDTH_2X;
445 *active_speed = IB_SPEED_EDR;
446 break;
08e8676f
AL		 447 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
448 *active_width = IB_WIDTH_1X;
449 *active_speed = IB_SPEED_HDR;
450 break;
cd272875
AL		 451 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
452 *active_width = IB_WIDTH_4X;
453 *active_speed = IB_SPEED_EDR;
454 break;
08e8676f
AL		 455 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
456 *active_width = IB_WIDTH_2X;
457 *active_speed = IB_SPEED_HDR;
458 break;
459 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
460 *active_width = IB_WIDTH_4X;
461 *active_speed = IB_SPEED_HDR;
462 break;
463 default:
464 return -EINVAL;
465 }
466
467 return 0;
468}
469
470static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
471 u8 *active_width, bool ext)
472{
473 return ext ?
474 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
475 active_width) :
476 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
477 active_width);
478}
479
095b0927
IT		 480static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
481 struct ib_port_attr *props)
3f89a643
AS		 482{
483 struct mlx5_ib_dev *dev = to_mdev(device);
bc4e12ff 484 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
da005f9f 485 struct mlx5_core_dev *mdev;
88621dfe 486 struct net_device *ndev, *upper;
3f89a643 487 enum ib_mtu ndev_ib_mtu;
b3cbd6f0 488 bool put_mdev = true;
c876a1b7 489 u16 qkey_viol_cntr;
f1b65df5 490 u32 eth_prot_oper;
b3cbd6f0 491 u8 mdev_port_num;
08e8676f 492 bool ext;
095b0927 493 int err;
3f89a643 494
b3cbd6f0
DJ		 495 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
496 if (!mdev) {
497 /* This means the port isn't affiliated yet. Get the
498 * info for the master port instead.
499 */
500 put_mdev = false;
501 mdev = dev->mdev;
502 mdev_port_num = 1;
503 port_num = 1;
504 }
505
f1b65df5
NO		 506 /* Possible bad flows are checked before filling out props so in case
507 * of an error it will still be zeroed out.
26628e2d 508 * Use native port in case of reps
50f22fd8 509 */
26628e2d
MB		 510 if (dev->is_rep)
511 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
512 1);
513 else
514 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
515 mdev_port_num);
095b0927 516 if (err)
b3cbd6f0 517 goto out;
08e8676f
AL		 518 ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet);
519 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
f1b65df5 520
7672ed33
HL		 521 props->active_width = IB_WIDTH_4X;
522 props->active_speed = IB_SPEED_QDR;
523
f1b65df5 524 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
08e8676f 525 &props->active_width, ext);
3f89a643 526
2f944c0f
JG		 527 props->port_cap_flags |= IB_PORT_CM_SUP;
528 props->ip_gids = true;
3f89a643
AS		 529
530 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
531 roce_address_table_size);
532 props->max_mtu = IB_MTU_4096;
533 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
534 props->pkey_tbl_len = 1;
535 props->state = IB_PORT_DOWN;
72a7720f 536 props->phys_state = IB_PORT_PHYS_STATE_DISABLED;
3f89a643 537
b3cbd6f0 538 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
c876a1b7 539 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643 540
b3cbd6f0
DJ		 541 /* If this is a stub query for an unaffiliated port stop here */
542 if (!put_mdev)
543 goto out;
544
3f89a643
AS		 545 ndev = mlx5_ib_get_netdev(device, port_num);
546 if (!ndev)
b3cbd6f0 547 goto out;
3f89a643 548
7c34ec19 549 if (dev->lag_active) {
88621dfe
AH		 550 rcu_read_lock();
551 upper = netdev_master_upper_dev_get_rcu(ndev);
552 if (upper) {
553 dev_put(ndev);
554 ndev = upper;
555 dev_hold(ndev);
556 }
557 rcu_read_unlock();
558 }
559
3f89a643
AS		 560 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
561 props->state = IB_PORT_ACTIVE;
72a7720f 562 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
3f89a643
AS		 563 }
564
565 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
566
567 dev_put(ndev);
568
569 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
b3cbd6f0
DJ		 570out:
571 if (put_mdev)
572 mlx5_ib_put_native_port_mdev(dev, port_num);
573 return err;
3f89a643
AS		 574}
575
095b0927
IT		 576static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
577 unsigned int index, const union ib_gid *gid,
578 const struct ib_gid_attr *attr)
3cca2606 579{
095b0927 580 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
a70c0739 581 u16 vlan_id = 0xffff;
095b0927
IT		 582 u8 roce_version = 0;
583 u8 roce_l3_type = 0;
095b0927 584 u8 mac[ETH_ALEN];
a70c0739 585 int ret;
095b0927
IT		 586
587 if (gid) {
588 gid_type = attr->gid_type;
a70c0739
PP		 589 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
590 if (ret)
591 return ret;
3cca2606
AS		 592 }
593
095b0927 594 switch (gid_type) {
3cca2606 595 case IB_GID_TYPE_IB:
095b0927 596 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 597 break;
598 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 599 roce_version = MLX5_ROCE_VERSION_2;
600 if (ipv6_addr_v4mapped((void *)gid))
601 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
602 else
603 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 604 break;
605
606 default:
095b0927 607 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 608 }
609
095b0927 610 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
cf34e1fe 611 roce_l3_type, gid->raw, mac,
a70c0739 612 vlan_id < VLAN_CFI_MASK, vlan_id,
cf34e1fe 613 port_num);
3cca2606
AS		 614}
615
f4df9a7c 616static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
3cca2606
AS		 617 __always_unused void **context)
618{
414448d2 619 return set_roce_addr(to_mdev(attr->device), attr->port_num,
f4df9a7c 620 attr->index, &attr->gid, attr);
3cca2606
AS		 621}
622
414448d2
PP		 623static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
624 __always_unused void **context)
3cca2606 625{
414448d2
PP		 626 return set_roce_addr(to_mdev(attr->device), attr->port_num,
627 attr->index, NULL, NULL);
3cca2606
AS		 628}
629
47ec3866
PP		 630__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
631 const struct ib_gid_attr *attr)
2811ba51 632{
47ec3866 633 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
2811ba51
AS		 634 return 0;
635
636 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
637}
638
1b5daf11
MD		 639static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
640{
7fae6655
NO		 641 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
642 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
643 return 0;
1b5daf11
MD		 644}
645
646enum {
647 MLX5_VPORT_ACCESS_METHOD_MAD,
648 MLX5_VPORT_ACCESS_METHOD_HCA,
649 MLX5_VPORT_ACCESS_METHOD_NIC,
650};
651
652static int mlx5_get_vport_access_method(struct ib_device *ibdev)
653{
654 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
655 return MLX5_VPORT_ACCESS_METHOD_MAD;
656
ebd61f68 657 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 658 IB_LINK_LAYER_ETHERNET)
659 return MLX5_VPORT_ACCESS_METHOD_NIC;
660
661 return MLX5_VPORT_ACCESS_METHOD_HCA;
662}
663
da7525d2 664static void get_atomic_caps(struct mlx5_ib_dev *dev,
776a3906 665 u8 atomic_size_qp,
da7525d2
EBE		 666 struct ib_device_attr *props)
667{
668 u8 tmp;
669 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
da7525d2 670 u8 atomic_req_8B_endianness_mode =
bd10838a 671 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 672
673 /* Check if HW supports 8 bytes standard atomic operations and capable
674 * of host endianness respond
675 */
676 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
677 if (((atomic_operations & tmp) == tmp) &&
678 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
679 (atomic_req_8B_endianness_mode)) {
680 props->atomic_cap = IB_ATOMIC_HCA;
681 } else {
682 props->atomic_cap = IB_ATOMIC_NONE;
683 }
684}
685
776a3906
MS		 686static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
687 struct ib_device_attr *props)
688{
689 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
690
691 get_atomic_caps(dev, atomic_size_qp, props);
692}
693
1b5daf11
MD		 694static int mlx5_query_system_image_guid(struct ib_device *ibdev,
695 __be64 *sys_image_guid)
696{
697 struct mlx5_ib_dev *dev = to_mdev(ibdev);
698 struct mlx5_core_dev *mdev = dev->mdev;
699 u64 tmp;
700 int err;
701
702 switch (mlx5_get_vport_access_method(ibdev)) {
703 case MLX5_VPORT_ACCESS_METHOD_MAD:
704 return mlx5_query_mad_ifc_system_image_guid(ibdev,
705 sys_image_guid);
706
707 case MLX5_VPORT_ACCESS_METHOD_HCA:
708 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 709 break;
710
711 case MLX5_VPORT_ACCESS_METHOD_NIC:
712 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
713 break;
1b5daf11
MD		 714
715 default:
716 return -EINVAL;
717 }
3f89a643
AS		 718
719 if (!err)
720 *sys_image_guid = cpu_to_be64(tmp);
721
722 return err;
723
1b5daf11
MD		 724}
725
726static int mlx5_query_max_pkeys(struct ib_device *ibdev,
727 u16 *max_pkeys)
728{
729 struct mlx5_ib_dev *dev = to_mdev(ibdev);
730 struct mlx5_core_dev *mdev = dev->mdev;
731
732 switch (mlx5_get_vport_access_method(ibdev)) {
733 case MLX5_VPORT_ACCESS_METHOD_MAD:
734 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
735
736 case MLX5_VPORT_ACCESS_METHOD_HCA:
737 case MLX5_VPORT_ACCESS_METHOD_NIC:
738 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
739 pkey_table_size));
740 return 0;
741
742 default:
743 return -EINVAL;
744 }
745}
746
747static int mlx5_query_vendor_id(struct ib_device *ibdev,
748 u32 *vendor_id)
749{
750 struct mlx5_ib_dev *dev = to_mdev(ibdev);
751
752 switch (mlx5_get_vport_access_method(ibdev)) {
753 case MLX5_VPORT_ACCESS_METHOD_MAD:
754 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
755
756 case MLX5_VPORT_ACCESS_METHOD_HCA:
757 case MLX5_VPORT_ACCESS_METHOD_NIC:
758 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
759
760 default:
761 return -EINVAL;
762 }
763}
764
765static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
766 __be64 *node_guid)
767{
768 u64 tmp;
769 int err;
770
771 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
772 case MLX5_VPORT_ACCESS_METHOD_MAD:
773 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
774
775 case MLX5_VPORT_ACCESS_METHOD_HCA:
776 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 777 break;
778
779 case MLX5_VPORT_ACCESS_METHOD_NIC:
780 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
781 break;
1b5daf11
MD		 782
783 default:
784 return -EINVAL;
785 }
3f89a643
AS		 786
787 if (!err)
788 *node_guid = cpu_to_be64(tmp);
789
790 return err;
1b5daf11
MD		 791}
792
793struct mlx5_reg_node_desc {
bd99fdea 794 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 795};
796
797static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
798{
799 struct mlx5_reg_node_desc in;
800
801 if (mlx5_use_mad_ifc(dev))
802 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
803
804 memset(&in, 0, sizeof(in));
805
806 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
807 sizeof(struct mlx5_reg_node_desc),
808 MLX5_REG_NODE_DESC, 0, 0);
809}
810
e126ba97 811static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 812 struct ib_device_attr *props,
813 struct ib_udata *uhw)
e126ba97 814{
48357091 815 size_t uhw_outlen = (uhw) ? uhw->outlen : 0;
e126ba97 816 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 817 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 818 int err = -ENOMEM;
288c01b7 819 int max_sq_desc;
e126ba97
EC		 820 int max_rq_sg;
821 int max_sq_sg;
e0238a6a 822 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
85c7c014 823 bool raw_support = !mlx5_core_mp_enabled(mdev);
402ca536
BW		 824 struct mlx5_ib_query_device_resp resp = {};
825 size_t resp_len;
826 u64 max_tso;
e126ba97 827
402ca536 828 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
48357091 829 if (uhw_outlen && uhw_outlen < resp_len)
402ca536 830 return -EINVAL;
6f26b2ac
EA		 831
832 resp.response_length = resp_len;
402ca536 833
48357091 834 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 835 return -EINVAL;
836
1b5daf11
MD		 837 memset(props, 0, sizeof(*props));
838 err = mlx5_query_system_image_guid(ibdev,
839 &props->sys_image_guid);
840 if (err)
841 return err;
e126ba97 842
1b5daf11 843 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 844 if (err)
1b5daf11 845 return err;
e126ba97 846
1b5daf11
MD		 847 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
848 if (err)
849 return err;
e126ba97 850
9603b61d
JM		 851 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
852 (fw_rev_min(dev->mdev) << 16) |
853 fw_rev_sub(dev->mdev);
e126ba97
EC		 854 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
855 IB_DEVICE_PORT_ACTIVE_EVENT |
856 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 857 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 858
859 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 860 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 861 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 862 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 863 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 864 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 865 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 866 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 867 if (MLX5_CAP_GEN(mdev, imaicl)) {
868 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
869 IB_DEVICE_MEM_WINDOW_TYPE_2B;
870 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 871 /* We support 'Gappy' memory registration too */
872 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 873 }
e126ba97 874 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 875 if (MLX5_CAP_GEN(mdev, sho)) {
c0a6cbb9 876 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER;
2dea9094
SG		 877 /* At this stage no support for signature handover */
878 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
879 IB_PROT_T10DIF_TYPE_2 |
880 IB_PROT_T10DIF_TYPE_3;
881 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
882 IB_GUARD_T10DIF_CSUM;
883 }
938fe83c 884 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 885 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 886
85c7c014 887 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
e8161334
NO		 888 if (MLX5_CAP_ETH(mdev, csum_cap)) {
889 /* Legacy bit to support old userspace libraries */
88115fe7 890 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 891 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
892 }
893
894 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
895 props->raw_packet_caps |=
896 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 897
a762d460 898 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) {
402ca536
BW		 899 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
900 if (max_tso) {
901 resp.tso_caps.max_tso = 1 << max_tso;
902 resp.tso_caps.supported_qpts |=
903 1 << IB_QPT_RAW_PACKET;
904 resp.response_length += sizeof(resp.tso_caps);
905 }
906 }
31f69a82 907
a762d460 908 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) {
31f69a82
YH		 909 resp.rss_caps.rx_hash_function =
910 MLX5_RX_HASH_FUNC_TOEPLITZ;
911 resp.rss_caps.rx_hash_fields_mask =
912 MLX5_RX_HASH_SRC_IPV4 |
913 MLX5_RX_HASH_DST_IPV4 |
914 MLX5_RX_HASH_SRC_IPV6 |
915 MLX5_RX_HASH_DST_IPV6 |
916 MLX5_RX_HASH_SRC_PORT_TCP |
917 MLX5_RX_HASH_DST_PORT_TCP |
918 MLX5_RX_HASH_SRC_PORT_UDP |
4e2b53a5
MG		 919 MLX5_RX_HASH_DST_PORT_UDP |
920 MLX5_RX_HASH_INNER;
2d93fc85
MB		 921 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
922 MLX5_ACCEL_IPSEC_CAP_DEVICE)
923 resp.rss_caps.rx_hash_fields_mask |=
924 MLX5_RX_HASH_IPSEC_SPI;
31f69a82
YH		 925 resp.response_length += sizeof(resp.rss_caps);
926 }
927 } else {
a762d460 928 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen)
31f69a82 929 resp.response_length += sizeof(resp.tso_caps);
a762d460 930 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen)
31f69a82 931 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 932 }
933
f0313965
ES		 934 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
935 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
936 props->device_cap_flags |= IB_DEVICE_UD_TSO;
937 }
938
03404e8a 939 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
85c7c014
DJ		 940 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
941 raw_support)
03404e8a
MG		 942 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
943
1d54f890
YH		 944 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
945 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
946 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
947
cff5a0f3 948 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
85c7c014
DJ		 949 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
950 raw_support) {
e8161334 951 /* Legacy bit to support old userspace libraries */
cff5a0f3 952 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 953 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
954 }
cff5a0f3 955
24da0016
AL		 956 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
957 props->max_dm_size =
958 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
959 }
960
da6d6ba3
MG		 961 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
962 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
963
b1383aa6
NO		 964 if (MLX5_CAP_GEN(mdev, end_pad))
965 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
966
1b5daf11
MD		 967 props->vendor_part_id = mdev->pdev->device;
968 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 969
970 props->max_mr_size = ~0ull;
e0238a6a 971 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 972 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
973 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
974 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
975 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 976 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
977 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
978 sizeof(struct mlx5_wqe_raddr_seg)) /
979 sizeof(struct mlx5_wqe_data_seg);
33023fb8
SW		 980 props->max_send_sge = max_sq_sg;
981 props->max_recv_sge = max_rq_sg;
986ef95e 982 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 983 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 984 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 985 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
986 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
987 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
988 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
989 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
990 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
991 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 992 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 993 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 994 props->max_fast_reg_page_list_len =
995 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
62e3c379
MG		 996 props->max_pi_fast_reg_page_list_len =
997 props->max_fast_reg_page_list_len / 2;
36609056
YF		 998 props->max_sgl_rd =
999 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance);
776a3906 1000 get_atomic_caps_qp(dev, props);
81bea28f 1001 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 1002 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
1003 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 1004 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1005 props->max_mcast_grp;
1006 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 1007 props->max_ah = INT_MAX;
7c60bcbb
MB		 1008 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
1009 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 1010
e502b8b0 1011 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
00815752 1012 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT)
e502b8b0
LR		 1013 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
1014 props->odp_caps = dev->odp_caps;
a73a8955
MS		 1015 if (!uhw) {
1016 /* ODP for kernel QPs is not implemented for receive
1017 * WQEs and SRQ WQEs
1018 */
1019 props->odp_caps.per_transport_caps.rc_odp_caps &=
1020 ~(IB_ODP_SUPPORT_READ |
1021 IB_ODP_SUPPORT_SRQ_RECV);
1022 props->odp_caps.per_transport_caps.uc_odp_caps &=
1023 ~(IB_ODP_SUPPORT_READ |
1024 IB_ODP_SUPPORT_SRQ_RECV);
1025 props->odp_caps.per_transport_caps.ud_odp_caps &=
1026 ~(IB_ODP_SUPPORT_READ |
1027 IB_ODP_SUPPORT_SRQ_RECV);
1028 props->odp_caps.per_transport_caps.xrc_odp_caps &=
1029 ~(IB_ODP_SUPPORT_READ |
1030 IB_ODP_SUPPORT_SRQ_RECV);
1031 }
e502b8b0 1032 }
8cdd312c 1033
051f2630
LR		 1034 if (MLX5_CAP_GEN(mdev, cd))
1035 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
1036
e53a9d26 1037 if (mlx5_core_is_vf(mdev))
eff901d3
EC		 1038 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
1039
31f69a82 1040 if (mlx5_ib_port_link_layer(ibdev, 1) ==
85c7c014 1041 IB_LINK_LAYER_ETHERNET && raw_support) {
31f69a82
YH		 1042 props->rss_caps.max_rwq_indirection_tables =
1043 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1044 props->rss_caps.max_rwq_indirection_table_size =
1045 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1046 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1047 props->max_wq_type_rq =
1048 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1049 }
1050
eb761894 1051 if (MLX5_CAP_GEN(mdev, tag_matching)) {
78b1beb0 1052 props->tm_caps.max_num_tags =
eb761894 1053 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
78b1beb0 1054 props->tm_caps.max_ops =
eb761894 1055 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
78b1beb0 1056 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
eb761894
AK		 1057 }
1058
89705e92
DG		 1059 if (MLX5_CAP_GEN(mdev, tag_matching) &&
1060 MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
1061 props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
1062 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1063 }
1064
87ab3f52
YC		 1065 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1066 props->cq_caps.max_cq_moderation_count =
1067 MLX5_MAX_CQ_COUNT;
1068 props->cq_caps.max_cq_moderation_period =
1069 MLX5_MAX_CQ_PERIOD;
1070 }
1071
a762d460 1072 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) {
7e43a2a5 1073 resp.response_length += sizeof(resp.cqe_comp_caps);
572f46bf
YC		 1074
1075 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1076 resp.cqe_comp_caps.max_num =
1077 MLX5_CAP_GEN(dev->mdev,
1078 cqe_compression_max_num);
1079
1080 resp.cqe_comp_caps.supported_format =
1081 MLX5_IB_CQE_RES_FORMAT_HASH |
1082 MLX5_IB_CQE_RES_FORMAT_CSUM;
6f1006a4
YC		 1083
1084 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1085 resp.cqe_comp_caps.supported_format |=
1086 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
572f46bf 1087 }
7e43a2a5
BW		 1088 }
1089
a762d460 1090 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen &&
85c7c014 1091 raw_support) {
d949167d
BW		 1092 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1093 MLX5_CAP_GEN(mdev, qos)) {
1094 resp.packet_pacing_caps.qp_rate_limit_max =
1095 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1096 resp.packet_pacing_caps.qp_rate_limit_min =
1097 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1098 resp.packet_pacing_caps.supported_qpts |=
1099 1 << IB_QPT_RAW_PACKET;
61147f39
BW		 1100 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1101 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1102 resp.packet_pacing_caps.cap_flags |=
1103 MLX5_IB_PP_SUPPORT_BURST;
d949167d
BW		 1104 }
1105 resp.response_length += sizeof(resp.packet_pacing_caps);
1106 }
1107
a762d460
LR		 1108 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <=
1109 uhw_outlen) {
795b609c
BW		 1110 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1111 resp.mlx5_ib_support_multi_pkt_send_wqes =
1112 MLX5_IB_ALLOW_MPW;
050da902
BW		 1113
1114 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1115 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1116 MLX5_IB_SUPPORT_EMPW;
1117
9f885201
LR		 1118 resp.response_length +=
1119 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1120 }
1121
a762d460 1122 if (offsetofend(typeof(resp), flags) <= uhw_outlen) {
de57f2ad 1123 resp.response_length += sizeof(resp.flags);
7a0c8f42 1124
de57f2ad
GL		 1125 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1126 resp.flags |=
1127 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
7a0c8f42
GL		 1128
1129 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1130 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
7e11b911
DG		 1131 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1132 resp.flags |=
1133 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
7249c8ea
GL		 1134
1135 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
de57f2ad 1136 }
9f885201 1137
a762d460 1138 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) {
96dc3fc5
NO		 1139 resp.response_length += sizeof(resp.sw_parsing_caps);
1140 if (MLX5_CAP_ETH(mdev, swp)) {
1141 resp.sw_parsing_caps.sw_parsing_offloads |=
1142 MLX5_IB_SW_PARSING;
1143
1144 if (MLX5_CAP_ETH(mdev, swp_csum))
1145 resp.sw_parsing_caps.sw_parsing_offloads |=
1146 MLX5_IB_SW_PARSING_CSUM;
1147
1148 if (MLX5_CAP_ETH(mdev, swp_lso))
1149 resp.sw_parsing_caps.sw_parsing_offloads |=
1150 MLX5_IB_SW_PARSING_LSO;
1151
1152 if (resp.sw_parsing_caps.sw_parsing_offloads)
1153 resp.sw_parsing_caps.supported_qpts =
1154 BIT(IB_QPT_RAW_PACKET);
1155 }
1156 }
1157
a762d460 1158 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen &&
85c7c014 1159 raw_support) {
b4f34597
NO		 1160 resp.response_length += sizeof(resp.striding_rq_caps);
1161 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1162 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1163 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1164 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1165 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
c16339b6
MZ		 1166 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range))
1167 resp.striding_rq_caps
1168 .min_single_wqe_log_num_of_strides =
1169 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1170 else
1171 resp.striding_rq_caps
1172 .min_single_wqe_log_num_of_strides =
1173 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
b4f34597
NO		 1174 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1175 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1176 resp.striding_rq_caps.supported_qpts =
1177 BIT(IB_QPT_RAW_PACKET);
1178 }
1179 }
1180
a762d460 1181 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) {
f95ef6cb
MG		 1182 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1183 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1184 resp.tunnel_offloads_caps |=
1185 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1186 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1187 resp.tunnel_offloads_caps |=
1188 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1189 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1190 resp.tunnel_offloads_caps |=
1191 MLX5_IB_TUNNELED_OFFLOADS_GRE;
41e684ef 1192 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre))
e818e255
AL		 1193 resp.tunnel_offloads_caps |=
1194 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
41e684ef 1195 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp))
e818e255
AL		 1196 resp.tunnel_offloads_caps |=
1197 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
f95ef6cb
MG		 1198 }
1199
48357091 1200 if (uhw_outlen) {
402ca536
BW		 1201 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1202
1203 if (err)
1204 return err;
1205 }
1206
1b5daf11 1207 return 0;
e126ba97
EC		 1208}
1209
1b5daf11
MD		 1210enum mlx5_ib_width {
1211 MLX5_IB_WIDTH_1X = 1 << 0,
1212 MLX5_IB_WIDTH_2X = 1 << 1,
1213 MLX5_IB_WIDTH_4X = 1 << 2,
1214 MLX5_IB_WIDTH_8X = 1 << 3,
1215 MLX5_IB_WIDTH_12X = 1 << 4
1216};
1217
db7a691a 1218static void translate_active_width(struct ib_device *ibdev, u8 active_width,
1b5daf11 1219 u8 *ib_width)
e126ba97
EC		 1220{
1221 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11 1222
db7a691a 1223 if (active_width & MLX5_IB_WIDTH_1X)
1b5daf11 1224 *ib_width = IB_WIDTH_1X;
d764970b
MG		 1225 else if (active_width & MLX5_IB_WIDTH_2X)
1226 *ib_width = IB_WIDTH_2X;
db7a691a 1227 else if (active_width & MLX5_IB_WIDTH_4X)
1b5daf11 1228 *ib_width = IB_WIDTH_4X;
db7a691a 1229 else if (active_width & MLX5_IB_WIDTH_8X)
1b5daf11 1230 *ib_width = IB_WIDTH_8X;
db7a691a 1231 else if (active_width & MLX5_IB_WIDTH_12X)
1b5daf11 1232 *ib_width = IB_WIDTH_12X;
db7a691a
MG		 1233 else {
1234 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1b5daf11 1235 (int)active_width);
db7a691a 1236 *ib_width = IB_WIDTH_4X;
e126ba97
EC		 1237 }
1238
db7a691a 1239 return;
1b5daf11 1240}
e126ba97 1241
1b5daf11
MD		 1242static int mlx5_mtu_to_ib_mtu(int mtu)
1243{
1244 switch (mtu) {
1245 case 256: return 1;
1246 case 512: return 2;
1247 case 1024: return 3;
1248 case 2048: return 4;
1249 case 4096: return 5;
1250 default:
1251 pr_warn("invalid mtu\n");
1252 return -1;
e126ba97 1253 }
1b5daf11 1254}
e126ba97 1255
1b5daf11
MD		 1256enum ib_max_vl_num {
1257 __IB_MAX_VL_0 = 1,
1258 __IB_MAX_VL_0_1 = 2,
1259 __IB_MAX_VL_0_3 = 3,
1260 __IB_MAX_VL_0_7 = 4,
1261 __IB_MAX_VL_0_14 = 5,
1262};
e126ba97 1263
1b5daf11
MD		 1264enum mlx5_vl_hw_cap {
1265 MLX5_VL_HW_0 = 1,
1266 MLX5_VL_HW_0_1 = 2,
1267 MLX5_VL_HW_0_2 = 3,
1268 MLX5_VL_HW_0_3 = 4,
1269 MLX5_VL_HW_0_4 = 5,
1270 MLX5_VL_HW_0_5 = 6,
1271 MLX5_VL_HW_0_6 = 7,
1272 MLX5_VL_HW_0_7 = 8,
1273 MLX5_VL_HW_0_14 = 15
1274};
e126ba97 1275
1b5daf11
MD		 1276static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1277 u8 *max_vl_num)
1278{
1279 switch (vl_hw_cap) {
1280 case MLX5_VL_HW_0:
1281 *max_vl_num = __IB_MAX_VL_0;
1282 break;
1283 case MLX5_VL_HW_0_1:
1284 *max_vl_num = __IB_MAX_VL_0_1;
1285 break;
1286 case MLX5_VL_HW_0_3:
1287 *max_vl_num = __IB_MAX_VL_0_3;
1288 break;
1289 case MLX5_VL_HW_0_7:
1290 *max_vl_num = __IB_MAX_VL_0_7;
1291 break;
1292 case MLX5_VL_HW_0_14:
1293 *max_vl_num = __IB_MAX_VL_0_14;
1294 break;
e126ba97 1295
1b5daf11
MD		 1296 default:
1297 return -EINVAL;
e126ba97 1298 }
e126ba97 1299
1b5daf11 1300 return 0;
e126ba97
EC		 1301}
1302
1b5daf11
MD		 1303static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1304 struct ib_port_attr *props)
e126ba97 1305{
1b5daf11
MD		 1306 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1307 struct mlx5_core_dev *mdev = dev->mdev;
1308 struct mlx5_hca_vport_context *rep;
046339ea
SM		 1309 u16 max_mtu;
1310 u16 oper_mtu;
1b5daf11
MD		 1311 int err;
1312 u8 ib_link_width_oper;
1313 u8 vl_hw_cap;
e126ba97 1314
1b5daf11
MD		 1315 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1316 if (!rep) {
1317 err = -ENOMEM;
e126ba97 1318 goto out;
e126ba97 1319 }
e126ba97 1320
c4550c63 1321 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 1322
1b5daf11 1323 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 1324 if (err)
1325 goto out;
1326
1b5daf11
MD		 1327 props->lid = rep->lid;
1328 props->lmc = rep->lmc;
1329 props->sm_lid = rep->sm_lid;
1330 props->sm_sl = rep->sm_sl;
1331 props->state = rep->vport_state;
1332 props->phys_state = rep->port_physical_state;
1333 props->port_cap_flags = rep->cap_mask1;
1334 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1335 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1336 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1337 props->bad_pkey_cntr = rep->pkey_violation_counter;
1338 props->qkey_viol_cntr = rep->qkey_violation_counter;
1339 props->subnet_timeout = rep->subnet_timeout;
1340 props->init_type_reply = rep->init_type_reply;
e126ba97 1341
4106a758
MG		 1342 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1343 props->port_cap_flags2 = rep->cap_mask2;
1344
1b5daf11
MD		 1345 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1346 if (err)
e126ba97 1347 goto out;
e126ba97 1348
db7a691a
MG		 1349 translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1350
d5beb7f2 1351 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 1352 if (err)
1353 goto out;
1354
facc9699 1355 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 1356
1b5daf11 1357 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 1358
facc9699 1359 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 1360
1b5daf11 1361 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1362
1b5daf11
MD		 1363 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1364 if (err)
1365 goto out;
e126ba97 1366
1b5daf11
MD		 1367 err = translate_max_vl_num(ibdev, vl_hw_cap,
1368 &props->max_vl_num);
e126ba97 1369out:
1b5daf11 1370 kfree(rep);
e126ba97
EC		 1371 return err;
1372}
1373
1b5daf11
MD		 1374int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1375 struct ib_port_attr *props)
e126ba97 1376{
095b0927
IT		 1377 unsigned int count;
1378 int ret;
1379
1b5daf11
MD		 1380 switch (mlx5_get_vport_access_method(ibdev)) {
1381 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1382 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1383 break;
e126ba97 1384
1b5daf11 1385 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1386 ret = mlx5_query_hca_port(ibdev, port, props);
1387 break;
e126ba97 1388
3f89a643 1389 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1390 ret = mlx5_query_port_roce(ibdev, port, props);
1391 break;
3f89a643 1392
1b5daf11 1393 default:
095b0927
IT		 1394 ret = -EINVAL;
1395 }
1396
1397 if (!ret && props) {
b3cbd6f0
DJ		 1398 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1399 struct mlx5_core_dev *mdev;
1400 bool put_mdev = true;
1401
1402 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1403 if (!mdev) {
1404 /* If the port isn't affiliated yet query the master.
1405 * The master and slave will have the same values.
1406 */
1407 mdev = dev->mdev;
1408 port = 1;
1409 put_mdev = false;
1410 }
1411 count = mlx5_core_reserved_gids_count(mdev);
1412 if (put_mdev)
1413 mlx5_ib_put_native_port_mdev(dev, port);
095b0927 1414 props->gid_tbl_len -= count;
1b5daf11 1415 }
095b0927 1416 return ret;
1b5daf11 1417}
e126ba97 1418
8e6efa3a
MB		 1419static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1420 struct ib_port_attr *props)
1421{
1422 int ret;
1423
26628e2d
MB		 1424 /* Only link layer == ethernet is valid for representors
1425 * and we always use port 1
1426 */
8e6efa3a
MB		 1427 ret = mlx5_query_port_roce(ibdev, port, props);
1428 if (ret || !props)
1429 return ret;
1430
1431 /* We don't support GIDS */
1432 props->gid_tbl_len = 0;
1433
1434 return ret;
1435}
1436
1b5daf11
MD		 1437static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1438 union ib_gid *gid)
1439{
1440 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1441 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1442
1b5daf11
MD		 1443 switch (mlx5_get_vport_access_method(ibdev)) {
1444 case MLX5_VPORT_ACCESS_METHOD_MAD:
1445 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1446
1b5daf11
MD		 1447 case MLX5_VPORT_ACCESS_METHOD_HCA:
1448 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1449
1450 default:
1451 return -EINVAL;
1452 }
e126ba97 1453
e126ba97
EC		 1454}
1455
b3cbd6f0
DJ		 1456static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1457 u16 index, u16 *pkey)
1b5daf11
MD		 1458{
1459 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b3cbd6f0
DJ		 1460 struct mlx5_core_dev *mdev;
1461 bool put_mdev = true;
1462 u8 mdev_port_num;
1463 int err;
1b5daf11 1464
b3cbd6f0
DJ		 1465 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1466 if (!mdev) {
1467 /* The port isn't affiliated yet, get the PKey from the master
1468 * port. For RoCE the PKey tables will be the same.
1469 */
1470 put_mdev = false;
1471 mdev = dev->mdev;
1472 mdev_port_num = 1;
1473 }
1474
1475 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1476 index, pkey);
1477 if (put_mdev)
1478 mlx5_ib_put_native_port_mdev(dev, port);
1479
1480 return err;
1481}
1482
1483static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1484 u16 *pkey)
1485{
1b5daf11
MD		 1486 switch (mlx5_get_vport_access_method(ibdev)) {
1487 case MLX5_VPORT_ACCESS_METHOD_MAD:
1488 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1489
1490 case MLX5_VPORT_ACCESS_METHOD_HCA:
1491 case MLX5_VPORT_ACCESS_METHOD_NIC:
b3cbd6f0 1492 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1b5daf11
MD		 1493 default:
1494 return -EINVAL;
1495 }
1496}
e126ba97
EC		 1497
1498static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1499 struct ib_device_modify *props)
1500{
1501 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1502 struct mlx5_reg_node_desc in;
1503 struct mlx5_reg_node_desc out;
1504 int err;
1505
1506 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1507 return -EOPNOTSUPP;
1508
1509 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1510 return 0;
1511
1512 /*
1513 * If possible, pass node desc to FW, so it can generate
1514 * a 144 trap. If cmd fails, just ignore.
1515 */
bd99fdea 1516 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1517 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1518 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1519 if (err)
1520 return err;
1521
bd99fdea 1522 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1523
1524 return err;
1525}
1526
cdbe33d0
EC		 1527static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1528 u32 value)
1529{
1530 struct mlx5_hca_vport_context ctx = {};
b3cbd6f0
DJ		 1531 struct mlx5_core_dev *mdev;
1532 u8 mdev_port_num;
cdbe33d0
EC		 1533 int err;
1534
b3cbd6f0
DJ		 1535 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1536 if (!mdev)
1537 return -ENODEV;
1538
1539 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
cdbe33d0 1540 if (err)
b3cbd6f0 1541 goto out;
cdbe33d0
EC		 1542
1543 if (~ctx.cap_mask1_perm & mask) {
1544 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1545 mask, ctx.cap_mask1_perm);
b3cbd6f0
DJ		 1546 err = -EINVAL;
1547 goto out;
cdbe33d0
EC		 1548 }
1549
1550 ctx.cap_mask1 = value;
1551 ctx.cap_mask1_perm = mask;
b3cbd6f0
DJ		 1552 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1553 0, &ctx);
1554
1555out:
1556 mlx5_ib_put_native_port_mdev(dev, port_num);
cdbe33d0
EC		 1557
1558 return err;
1559}
1560
e126ba97
EC		 1561static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1562 struct ib_port_modify *props)
1563{
1564 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1565 struct ib_port_attr attr;
1566 u32 tmp;
1567 int err;
cdbe33d0
EC		 1568 u32 change_mask;
1569 u32 value;
1570 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1571 IB_LINK_LAYER_INFINIBAND);
1572
ec255879
MD		 1573 /* CM layer calls ib_modify_port() regardless of the link layer. For
1574 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1575 */
1576 if (!is_ib)
1577 return 0;
1578
cdbe33d0
EC		 1579 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1580 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1581 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1582 return set_port_caps_atomic(dev, port, change_mask, value);
1583 }
e126ba97
EC		 1584
1585 mutex_lock(&dev->cap_mask_mutex);
1586
c4550c63 1587 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1588 if (err)
1589 goto out;
1590
1591 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1592 ~props->clr_port_cap_mask;
1593
9603b61d 1594 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1595
1596out:
1597 mutex_unlock(&dev->cap_mask_mutex);
1598 return err;
1599}
1600
30aa60b3
EC		 1601static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1602{
1603 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1604 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1605}
1606
31a78a5a
YH		 1607static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1608{
1609 /* Large page with non 4k uar support might limit the dynamic size */
1610 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1611 return MLX5_MIN_DYN_BFREGS;
1612
1613 return MLX5_MAX_DYN_BFREGS;
1614}
1615
b037c29a
EC		 1616static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1617 struct mlx5_ib_alloc_ucontext_req_v2 *req,
31a78a5a 1618 struct mlx5_bfreg_info *bfregi)
b037c29a
EC		 1619{
1620 int uars_per_sys_page;
1621 int bfregs_per_sys_page;
1622 int ref_bfregs = req->total_num_bfregs;
1623
1624 if (req->total_num_bfregs == 0)
1625 return -EINVAL;
1626
1627 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1628 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1629
1630 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1631 return -ENOMEM;
1632
1633 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1634 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
31a78a5a 1635 /* This holds the required static allocation asked by the user */
b037c29a 1636 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
b037c29a
EC		 1637 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1638 return -EINVAL;
1639
31a78a5a
YH		 1640 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1641 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1642 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1643 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1644
1645 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
b037c29a
EC		 1646 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1647 lib_uar_4k ? "yes" : "no", ref_bfregs,
31a78a5a
YH		 1648 req->total_num_bfregs, bfregi->total_num_bfregs,
1649 bfregi->num_sys_pages);
b037c29a
EC		 1650
1651 return 0;
1652}
1653
1654static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1655{
1656 struct mlx5_bfreg_info *bfregi;
1657 int err;
1658 int i;
1659
1660 bfregi = &context->bfregi;
31a78a5a 1661 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
b037c29a
EC		 1662 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1663 if (err)
1664 goto error;
1665
1666 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1667 }
4ed131d0
YH		 1668
1669 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1670 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1671
b037c29a
EC		 1672 return 0;
1673
1674error:
1675 for (--i; i >= 0; i--)
1676 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1677 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1678
1679 return err;
1680}
1681
15177999
LR		 1682static void deallocate_uars(struct mlx5_ib_dev *dev,
1683 struct mlx5_ib_ucontext *context)
b037c29a
EC		 1684{
1685 struct mlx5_bfreg_info *bfregi;
b037c29a
EC		 1686 int i;
1687
1688 bfregi = &context->bfregi;
15177999 1689 for (i = 0; i < bfregi->num_sys_pages; i++)
4ed131d0 1690 if (i < bfregi->num_static_sys_pages ||
15177999
LR		 1691 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1692 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
b037c29a
EC		 1693}
1694
0042f9e4 1695int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
a560f1d9
MB		 1696{
1697 int err = 0;
1698
1699 mutex_lock(&dev->lb.mutex);
0042f9e4
MB		 1700 if (td)
1701 dev->lb.user_td++;
1702 if (qp)
1703 dev->lb.qps++;
1704
1705 if (dev->lb.user_td == 2 ||
1706 dev->lb.qps == 1) {
1707 if (!dev->lb.enabled) {
1708 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1709 dev->lb.enabled = true;
1710 }
1711 }
a560f1d9
MB		 1712
1713 mutex_unlock(&dev->lb.mutex);
1714
1715 return err;
1716}
1717
0042f9e4 1718void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
a560f1d9
MB		 1719{
1720 mutex_lock(&dev->lb.mutex);
0042f9e4
MB		 1721 if (td)
1722 dev->lb.user_td--;
1723 if (qp)
1724 dev->lb.qps--;
1725
1726 if (dev->lb.user_td == 1 &&
1727 dev->lb.qps == 0) {
1728 if (dev->lb.enabled) {
1729 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1730 dev->lb.enabled = false;
1731 }
1732 }
a560f1d9
MB		 1733
1734 mutex_unlock(&dev->lb.mutex);
1735}
1736
d2d19121
YH		 1737static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1738 u16 uid)
c85023e1
HN		 1739{
1740 int err;
1741
cfdeb893
LR		 1742 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1743 return 0;
1744
d2d19121 1745 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
c85023e1
HN		 1746 if (err)
1747 return err;
1748
1749 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1750 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1751 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1752 return err;
1753
0042f9e4 1754 return mlx5_ib_enable_lb(dev, true, false);
c85023e1
HN		 1755}
1756
d2d19121
YH		 1757static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1758 u16 uid)
c85023e1 1759{
cfdeb893
LR		 1760 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1761 return;
1762
d2d19121 1763 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
c85023e1
HN		 1764
1765 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1766 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1767 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1768 return;
1769
0042f9e4 1770 mlx5_ib_disable_lb(dev, true, false);
c85023e1
HN		 1771}
1772
a2a074ef
LR		 1773static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1774 struct ib_udata *udata)
e126ba97 1775{
a2a074ef 1776 struct ib_device *ibdev = uctx->device;
e126ba97 1777 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1778 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1779 struct mlx5_ib_alloc_ucontext_resp resp = {};
5c99eaec 1780 struct mlx5_core_dev *mdev = dev->mdev;
a2a074ef 1781 struct mlx5_ib_ucontext *context = to_mucontext(uctx);
2f5ff264 1782 struct mlx5_bfreg_info *bfregi;
78c0f98c 1783 int ver;
e126ba97 1784 int err;
a168a41c
MD		 1785 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1786 max_cqe_version);
25bb36e7 1787 u32 dump_fill_mkey;
b037c29a 1788 bool lib_uar_4k;
e126ba97
EC		 1789
1790 if (!dev->ib_active)
a2a074ef 1791 return -EAGAIN;
e126ba97 1792
e093111d 1793 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1794 ver = 0;
e093111d 1795 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1796 ver = 2;
1797 else
a2a074ef 1798 return -EINVAL;
78c0f98c 1799
e093111d 1800 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97 1801 if (err)
a2a074ef 1802 return err;
e126ba97 1803
a8b92ca1 1804 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
a2a074ef 1805 return -EOPNOTSUPP;
78c0f98c 1806
f72300c5 1807 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
a2a074ef 1808 return -EOPNOTSUPP;
b368d7cb 1809
2f5ff264
EC		 1810 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1811 MLX5_NON_FP_BFREGS_PER_UAR);
1812 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
a2a074ef 1813 return -EINVAL;
e126ba97 1814
938fe83c 1815 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
11f552e2 1816 if (dev->wc_support)
2cc6ad5f 1817 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1818 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1819 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1820 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1821 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1822 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1823 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1824 resp.cqe_version = min_t(__u8,
1825 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1826 req.max_cqe_version);
30aa60b3
EC		 1827 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1828 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1829 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1830 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1831 resp.response_length = min(offsetof(typeof(resp), response_length) +
1832 sizeof(resp.response_length), udata->outlen);
e126ba97 1833
c03faa56
MB		 1834 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1835 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1836 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1837 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1838 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1839 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1840 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1841 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1842 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1843 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1844 }
1845
30aa60b3 1846 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1847 bfregi = &context->bfregi;
b037c29a
EC		 1848
1849 /* updates req->total_num_bfregs */
31a78a5a 1850 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
b037c29a 1851 if (err)
e126ba97 1852 goto out_ctx;
e126ba97 1853
b037c29a
EC		 1854 mutex_init(&bfregi->lock);
1855 bfregi->lib_uar_4k = lib_uar_4k;
31a78a5a 1856 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1857 GFP_KERNEL);
b037c29a 1858 if (!bfregi->count) {
e126ba97 1859 err = -ENOMEM;
b037c29a 1860 goto out_ctx;
e126ba97
EC		 1861 }
1862
b037c29a
EC		 1863 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1864 sizeof(*bfregi->sys_pages),
1865 GFP_KERNEL);
1866 if (!bfregi->sys_pages) {
e126ba97 1867 err = -ENOMEM;
b037c29a 1868 goto out_count;
e126ba97
EC		 1869 }
1870
b037c29a
EC		 1871 err = allocate_uars(dev, context);
1872 if (err)
1873 goto out_sys_pages;
e126ba97 1874
a8b92ca1 1875 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
fb98153b 1876 err = mlx5_ib_devx_create(dev, true);
76dc5a84 1877 if (err < 0)
d2d19121 1878 goto out_uars;
76dc5a84 1879 context->devx_uid = err;
a8b92ca1
YH		 1880 }
1881
d2d19121
YH		 1882 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1883 context->devx_uid);
1884 if (err)
1885 goto out_devx;
1886
25bb36e7
YC		 1887 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1888 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1889 if (err)
8193abb6 1890 goto out_mdev;
25bb36e7
YC		 1891 }
1892
e126ba97
EC		 1893 INIT_LIST_HEAD(&context->db_page_list);
1894 mutex_init(&context->db_page_mutex);
1895
2f5ff264 1896 resp.tot_bfregs = req.total_num_bfregs;
508562d6 1897 resp.num_ports = dev->num_ports;
b368d7cb 1898
a762d460 1899 if (offsetofend(typeof(resp), cqe_version) <= udata->outlen)
f72300c5 1900 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1901
a762d460 1902 if (offsetofend(typeof(resp), cmds_supp_uhw) <= udata->outlen) {
6ad279c5
MS		 1903 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1904 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1905 resp.response_length += sizeof(resp.cmds_supp_uhw);
1906 }
1907
a762d460 1908 if (offsetofend(typeof(resp), eth_min_inline) <= udata->outlen) {
78984898
OG		 1909 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1910 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1911 resp.eth_min_inline++;
1912 }
1913 resp.response_length += sizeof(resp.eth_min_inline);
1914 }
1915
a762d460 1916 if (offsetofend(typeof(resp), clock_info_versions) <= udata->outlen) {
5c99eaec
FD		 1917 if (mdev->clock_info)
1918 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1919 resp.response_length += sizeof(resp.clock_info_versions);
1920 }
1921
bc5c6eed
NO		 1922 /*
1923 * We don't want to expose information from the PCI bar that is located
1924 * after 4096 bytes, so if the arch only supports larger pages, let's
1925 * pretend we don't support reading the HCA's core clock. This is also
1926 * forced by mmap function.
1927 */
a762d460 1928 if (offsetofend(typeof(resp), hca_core_clock_offset) <= udata->outlen) {
de8d6e02
EC		 1929 if (PAGE_SIZE <= 4096) {
1930 resp.comp_mask |=
1931 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1932 resp.hca_core_clock_offset =
1933 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1934 }
5c99eaec 1935 resp.response_length += sizeof(resp.hca_core_clock_offset);
b368d7cb
MB		 1936 }
1937
a762d460 1938 if (offsetofend(typeof(resp), log_uar_size) <= udata->outlen)
30aa60b3
EC		 1939 resp.response_length += sizeof(resp.log_uar_size);
1940
a762d460 1941 if (offsetofend(typeof(resp), num_uars_per_page) <= udata->outlen)
30aa60b3
EC		 1942 resp.response_length += sizeof(resp.num_uars_per_page);
1943
a762d460 1944 if (offsetofend(typeof(resp), num_dyn_bfregs) <= udata->outlen) {
31a78a5a
YH		 1945 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1946 resp.response_length += sizeof(resp.num_dyn_bfregs);
1947 }
1948
a762d460 1949 if (offsetofend(typeof(resp), dump_fill_mkey) <= udata->outlen) {
25bb36e7
YC		 1950 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1951 resp.dump_fill_mkey = dump_fill_mkey;
1952 resp.comp_mask |=
1953 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1954 }
1955 resp.response_length += sizeof(resp.dump_fill_mkey);
1956 }
1957
b368d7cb 1958 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1959 if (err)
a8b92ca1 1960 goto out_mdev;
e126ba97 1961
2f5ff264
EC		 1962 bfregi->ver = ver;
1963 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1964 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1965 context->lib_caps = req.lib_caps;
1966 print_lib_caps(dev, context->lib_caps);
f72300c5 1967
7c34ec19 1968 if (dev->lag_active) {
95579e78 1969 u8 port = mlx5_core_native_port_num(dev->mdev) - 1;
c6a21c38
MD		 1970
1971 atomic_set(&context->tx_port_affinity,
1972 atomic_add_return(
95579e78 1973 1, &dev->port[port].roce.tx_port_affinity));
c6a21c38
MD		 1974 }
1975
a2a074ef 1976 return 0;
e126ba97 1977
a8b92ca1 1978out_mdev:
d2d19121
YH		 1979 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1980out_devx:
a8b92ca1 1981 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
76dc5a84 1982 mlx5_ib_devx_destroy(dev, context->devx_uid);
146d2f1a 1983
e126ba97 1984out_uars:
b037c29a 1985 deallocate_uars(dev, context);
e126ba97 1986
b037c29a
EC		 1987out_sys_pages:
1988 kfree(bfregi->sys_pages);
e126ba97 1989
b037c29a
EC		 1990out_count:
1991 kfree(bfregi->count);
e126ba97
EC		 1992
1993out_ctx:
a2a074ef 1994 return err;
e126ba97
EC		 1995}
1996
a2a074ef 1997static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
e126ba97
EC		 1998{
1999 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2000 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 2001 struct mlx5_bfreg_info *bfregi;
e126ba97 2002
b037c29a 2003 bfregi = &context->bfregi;
d2d19121
YH		 2004 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
2005
a8b92ca1 2006 if (context->devx_uid)
76dc5a84 2007 mlx5_ib_devx_destroy(dev, context->devx_uid);
146d2f1a 2008
b037c29a
EC		 2009 deallocate_uars(dev, context);
2010 kfree(bfregi->sys_pages);
2f5ff264 2011 kfree(bfregi->count);
e126ba97
EC		 2012}
2013
b037c29a 2014static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
4ed131d0 2015 int uar_idx)
e126ba97 2016{
b037c29a
EC		 2017 int fw_uars_per_page;
2018
2019 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2020
aa8106f1 2021 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
e126ba97
EC		 2022}
2023
2024static int get_command(unsigned long offset)
2025{
2026 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2027}
2028
2029static int get_arg(unsigned long offset)
2030{
2031 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2032}
2033
2034static int get_index(unsigned long offset)
2035{
2036 return get_arg(offset);
2037}
2038
4ed131d0
YH		 2039/* Index resides in an extra byte to enable larger values than 255 */
2040static int get_extended_index(unsigned long offset)
2041{
2042 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2043}
2044
7c2344c3
MG		 2045
2046static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2047{
7c2344c3
MG		 2048}
2049
37aa5c36
GL		 2050static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2051{
2052 switch (cmd) {
2053 case MLX5_IB_MMAP_WC_PAGE:
2054 return "WC";
2055 case MLX5_IB_MMAP_REGULAR_PAGE:
2056 return "best effort WC";
2057 case MLX5_IB_MMAP_NC_PAGE:
2058 return "NC";
24da0016
AL		 2059 case MLX5_IB_MMAP_DEVICE_MEM:
2060 return "Device Memory";
37aa5c36
GL		 2061 default:
2062 return NULL;
2063 }
2064}
2065
5c99eaec
FD		 2066static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2067 struct vm_area_struct *vma,
2068 struct mlx5_ib_ucontext *context)
2069{
4eb6ab13
JG		 2070 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2071 !(vma->vm_flags & VM_SHARED))
5c99eaec
FD		 2072 return -EINVAL;
2073
2074 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2075 return -EOPNOTSUPP;
2076
4eb6ab13 2077 if (vma->vm_flags & (VM_WRITE | VM_EXEC))
5c99eaec 2078 return -EPERM;
c660133c 2079 vma->vm_flags &= ~VM_MAYWRITE;
5c99eaec 2080
ddcdc368 2081 if (!dev->mdev->clock_info)
5c99eaec
FD		 2082 return -EOPNOTSUPP;
2083
4eb6ab13
JG		 2084 return vm_insert_page(vma, vma->vm_start,
2085 virt_to_page(dev->mdev->clock_info));
5c99eaec
FD		 2086}
2087
dc2316eb
YH		 2088static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry)
2089{
2090 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry);
2091 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device);
7be76bef 2092 struct mlx5_var_table *var_table = &dev->var_table;
dc2316eb
YH		 2093 struct mlx5_ib_dm *mdm;
2094
2095 switch (mentry->mmap_flag) {
2096 case MLX5_IB_MMAP_TYPE_MEMIC:
2097 mdm = container_of(mentry, struct mlx5_ib_dm, mentry);
2098 mlx5_cmd_dealloc_memic(&dev->dm, mdm->dev_addr,
2099 mdm->size);
2100 kfree(mdm);
2101 break;
7be76bef
YH		 2102 case MLX5_IB_MMAP_TYPE_VAR:
2103 mutex_lock(&var_table->bitmap_lock);
2104 clear_bit(mentry->page_idx, var_table->bitmap);
2105 mutex_unlock(&var_table->bitmap_lock);
2106 kfree(mentry);
2107 break;
dc2316eb
YH		 2108 default:
2109 WARN_ON(true);
2110 }
2111}
2112
37aa5c36 2113static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 2114 struct vm_area_struct *vma,
2115 struct mlx5_ib_ucontext *context)
37aa5c36 2116{
2f5ff264 2117 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 2118 int err;
2119 unsigned long idx;
aa09ea6e 2120 phys_addr_t pfn;
37aa5c36 2121 pgprot_t prot;
4ed131d0
YH		 2122 u32 bfreg_dyn_idx = 0;
2123 u32 uar_index;
2124 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2125 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2126 bfregi->num_static_sys_pages;
b037c29a
EC		 2127
2128 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2129 return -EINVAL;
2130
4ed131d0
YH		 2131 if (dyn_uar)
2132 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2133 else
2134 idx = get_index(vma->vm_pgoff);
2135
2136 if (idx >= max_valid_idx) {
2137 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2138 idx, max_valid_idx);
b037c29a
EC		 2139 return -EINVAL;
2140 }
37aa5c36
GL		 2141
2142 switch (cmd) {
2143 case MLX5_IB_MMAP_WC_PAGE:
4ed131d0 2144 case MLX5_IB_MMAP_ALLOC_WC:
37aa5c36
GL		 2145 case MLX5_IB_MMAP_REGULAR_PAGE:
2146 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2147 prot = pgprot_writecombine(vma->vm_page_prot);
2148 break;
2149 case MLX5_IB_MMAP_NC_PAGE:
2150 prot = pgprot_noncached(vma->vm_page_prot);
2151 break;
2152 default:
2153 return -EINVAL;
2154 }
2155
4ed131d0
YH		 2156 if (dyn_uar) {
2157 int uars_per_page;
2158
2159 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2160 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2161 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2162 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2163 bfreg_dyn_idx, bfregi->total_num_bfregs);
2164 return -EINVAL;
2165 }
2166
2167 mutex_lock(&bfregi->lock);
2168 /* Fail if uar already allocated, first bfreg index of each
2169 * page holds its count.
2170 */
2171 if (bfregi->count[bfreg_dyn_idx]) {
2172 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2173 mutex_unlock(&bfregi->lock);
2174 return -EINVAL;
2175 }
2176
2177 bfregi->count[bfreg_dyn_idx]++;
2178 mutex_unlock(&bfregi->lock);
2179
2180 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2181 if (err) {
2182 mlx5_ib_warn(dev, "UAR alloc failed\n");
2183 goto free_bfreg;
2184 }
2185 } else {
2186 uar_index = bfregi->sys_pages[idx];
2187 }
2188
2189 pfn = uar_index2pfn(dev, uar_index);
37aa5c36
GL		 2190 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2191
e2cd1d1a 2192 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
c043ff2c 2193 prot, NULL);
37aa5c36 2194 if (err) {
8f062287 2195 mlx5_ib_err(dev,
e2cd1d1a 2196 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
8f062287 2197 err, mmap_cmd2str(cmd));
4ed131d0 2198 goto err;
37aa5c36
GL		 2199 }
2200
4ed131d0
YH		 2201 if (dyn_uar)
2202 bfregi->sys_pages[idx] = uar_index;
2203 return 0;
2204
2205err:
2206 if (!dyn_uar)
2207 return err;
2208
2209 mlx5_cmd_free_uar(dev->mdev, idx);
2210
2211free_bfreg:
2212 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2213
2214 return err;
37aa5c36
GL		 2215}
2216
dc2316eb
YH		 2217static int add_dm_mmap_entry(struct ib_ucontext *context,
2218 struct mlx5_ib_dm *mdm,
2219 u64 address)
2220{
2221 mdm->mentry.mmap_flag = MLX5_IB_MMAP_TYPE_MEMIC;
2222 mdm->mentry.address = address;
2223 return rdma_user_mmap_entry_insert_range(
2224 context, &mdm->mentry.rdma_entry,
2225 mdm->size,
2226 MLX5_IB_MMAP_DEVICE_MEM << 16,
2227 (MLX5_IB_MMAP_DEVICE_MEM << 16) + (1UL << 16) - 1);
2228}
2229
2230static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma)
2231{
2232 unsigned long idx;
2233 u8 command;
2234
2235 command = get_command(vma->vm_pgoff);
2236 idx = get_extended_index(vma->vm_pgoff);
2237
2238 return (command << 16 | idx);
2239}
2240
2241static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev,
2242 struct vm_area_struct *vma,
2243 struct ib_ucontext *ucontext)
24da0016 2244{
dc2316eb
YH		 2245 struct mlx5_user_mmap_entry *mentry;
2246 struct rdma_user_mmap_entry *entry;
2247 unsigned long pgoff;
2248 pgprot_t prot;
24da0016 2249 phys_addr_t pfn;
dc2316eb 2250 int ret;
24da0016 2251
dc2316eb
YH		 2252 pgoff = mlx5_vma_to_pgoff(vma);
2253 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff);
2254 if (!entry)
24da0016
AL		 2255 return -EINVAL;
2256
dc2316eb
YH		 2257 mentry = to_mmmap(entry);
2258 pfn = (mentry->address >> PAGE_SHIFT);
3f59b6c3
YH		 2259 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR)
2260 prot = pgprot_noncached(vma->vm_page_prot);
2261 else
2262 prot = pgprot_writecombine(vma->vm_page_prot);
dc2316eb
YH		 2263 ret = rdma_user_mmap_io(ucontext, vma, pfn,
2264 entry->npages * PAGE_SIZE,
2265 prot,
2266 entry);
2267 rdma_user_mmap_entry_put(&mentry->rdma_entry);
2268 return ret;
24da0016
AL		 2269}
2270
7be76bef
YH		 2271static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry)
2272{
9b6d3bbc
LR		 2273 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF;
2274 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF;
7be76bef
YH		 2275
2276 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) |
2277 (index & 0xFF)) << PAGE_SHIFT;
2278}
2279
e126ba97
EC		 2280static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2281{
2282 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2283 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 2284 unsigned long command;
e126ba97
EC		 2285 phys_addr_t pfn;
2286
2287 command = get_command(vma->vm_pgoff);
2288 switch (command) {
37aa5c36 2289 case MLX5_IB_MMAP_WC_PAGE:
1f3db161
YH		 2290 case MLX5_IB_MMAP_ALLOC_WC:
2291 if (!dev->wc_support)
2292 return -EPERM;
2293 fallthrough;
37aa5c36 2294 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 2295 case MLX5_IB_MMAP_REGULAR_PAGE:
7c2344c3 2296 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 2297
2298 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2299 return -ENOSYS;
2300
d69e3bcf 2301 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 2302 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2303 return -EINVAL;
2304
6cbac1e4 2305 if (vma->vm_flags & VM_WRITE)
d69e3bcf 2306 return -EPERM;
c660133c 2307 vma->vm_flags &= ~VM_MAYWRITE;
d69e3bcf
MB		 2308
2309 /* Don't expose to user-space information it shouldn't have */
2310 if (PAGE_SIZE > 4096)
2311 return -EOPNOTSUPP;
2312
d69e3bcf
MB		 2313 pfn = (dev->mdev->iseg_base +
2314 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2315 PAGE_SHIFT;
d5e560d3
JG		 2316 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2317 PAGE_SIZE,
c043ff2c
MK		 2318 pgprot_noncached(vma->vm_page_prot),
2319 NULL);
5c99eaec
FD		 2320 case MLX5_IB_MMAP_CLOCK_INFO:
2321 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
d69e3bcf 2322
e126ba97 2323 default:
dc2316eb 2324 return mlx5_ib_mmap_offset(dev, vma, ibcontext);
e126ba97
EC		 2325 }
2326
2327 return 0;
2328}
2329
25c13324
AL		 2330static inline int check_dm_type_support(struct mlx5_ib_dev *dev,
2331 u32 type)
24da0016 2332{
25c13324
AL		 2333 switch (type) {
2334 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2335 if (!MLX5_CAP_DEV_MEM(dev->mdev, memic))
2336 return -EOPNOTSUPP;
2337 break;
2338 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
c9b9dcb4 2339 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
25c13324
AL		 2340 if (!capable(CAP_SYS_RAWIO) ||
2341 !capable(CAP_NET_RAW))
2342 return -EPERM;
2343
2344 if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
2345 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner)))
2346 return -EOPNOTSUPP;
2347 break;
2348 }
2349
2350 return 0;
2351}
2352
3b113a1e
AL		 2353static int handle_alloc_dm_memic(struct ib_ucontext *ctx,
2354 struct mlx5_ib_dm *dm,
2355 struct ib_dm_alloc_attr *attr,
2356 struct uverbs_attr_bundle *attrs)
24da0016 2357{
3b113a1e 2358 struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm;
24da0016 2359 u64 start_offset;
dc2316eb 2360 u16 page_idx;
24da0016 2361 int err;
dc2316eb 2362 u64 address;
24da0016 2363
3b113a1e 2364 dm->size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
24da0016 2365
3b113a1e
AL		 2366 err = mlx5_cmd_alloc_memic(dm_db, &dm->dev_addr,
2367 dm->size, attr->alignment);
24da0016 2368 if (err)
3b113a1e 2369 return err;
24da0016 2370
dc2316eb
YH		 2371 address = dm->dev_addr & PAGE_MASK;
2372 err = add_dm_mmap_entry(ctx, dm, address);
2373 if (err)
2374 goto err_dealloc;
24da0016 2375
dc2316eb 2376 page_idx = dm->mentry.rdma_entry.start_pgoff & 0xFFFF;
24da0016 2377 err = uverbs_copy_to(attrs,
3b113a1e 2378 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
dc2316eb
YH		 2379 &page_idx,
2380 sizeof(page_idx));
24da0016 2381 if (err)
dc2316eb 2382 goto err_copy;
24da0016 2383
3b113a1e 2384 start_offset = dm->dev_addr & ~PAGE_MASK;
24da0016
AL		 2385 err = uverbs_copy_to(attrs,
2386 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2387 &start_offset, sizeof(start_offset));
2388 if (err)
dc2316eb 2389 goto err_copy;
3b113a1e
AL		 2390
2391 return 0;
2392
dc2316eb
YH		 2393err_copy:
2394 rdma_user_mmap_entry_remove(&dm->mentry.rdma_entry);
3b113a1e
AL		 2395err_dealloc:
2396 mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2397
2398 return err;
2399}
2400
25c13324
AL		 2401static int handle_alloc_dm_sw_icm(struct ib_ucontext *ctx,
2402 struct mlx5_ib_dm *dm,
2403 struct ib_dm_alloc_attr *attr,
2404 struct uverbs_attr_bundle *attrs,
2405 int type)
2406{
c9b9dcb4 2407 struct mlx5_core_dev *dev = to_mdev(ctx->device)->mdev;
25c13324
AL		 2408 u64 act_size;
2409 int err;
2410
2411 /* Allocation size must a multiple of the basic block size
2412 * and a power of 2.
2413 */
c9b9dcb4 2414 act_size = round_up(attr->length, MLX5_SW_ICM_BLOCK_SIZE(dev));
25c13324
AL		 2415 act_size = roundup_pow_of_two(act_size);
2416
2417 dm->size = act_size;
c9b9dcb4
AL		 2418 err = mlx5_dm_sw_icm_alloc(dev, type, act_size,
2419 to_mucontext(ctx)->devx_uid, &dm->dev_addr,
2420 &dm->icm_dm.obj_id);
25c13324
AL		 2421 if (err)
2422 return err;
2423
24da0016 2424 err = uverbs_copy_to(attrs,
25c13324
AL		 2425 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2426 &dm->dev_addr, sizeof(dm->dev_addr));
24da0016 2427 if (err)
c9b9dcb4
AL		 2428 mlx5_dm_sw_icm_dealloc(dev, type, dm->size,
2429 to_mucontext(ctx)->devx_uid, dm->dev_addr,
2430 dm->icm_dm.obj_id);
25c13324
AL		 2431
2432 return err;
2433}
2434
3b113a1e
AL		 2435struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2436 struct ib_ucontext *context,
2437 struct ib_dm_alloc_attr *attr,
2438 struct uverbs_attr_bundle *attrs)
2439{
2440 struct mlx5_ib_dm *dm;
2441 enum mlx5_ib_uapi_dm_type type;
2442 int err;
24da0016 2443
3b113a1e
AL		 2444 err = uverbs_get_const_default(&type, attrs,
2445 MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
2446 MLX5_IB_UAPI_DM_TYPE_MEMIC);
2447 if (err)
2448 return ERR_PTR(err);
24da0016 2449
3b113a1e
AL		 2450 mlx5_ib_dbg(to_mdev(ibdev), "alloc_dm req: dm_type=%d user_length=0x%llx log_alignment=%d\n",
2451 type, attr->length, attr->alignment);
2452
25c13324
AL		 2453 err = check_dm_type_support(to_mdev(ibdev), type);
2454 if (err)
2455 return ERR_PTR(err);
2456
3b113a1e
AL		 2457 dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2458 if (!dm)
2459 return ERR_PTR(-ENOMEM);
2460
2461 dm->type = type;
2462
2463 switch (type) {
2464 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2465 err = handle_alloc_dm_memic(context, dm,
2466 attr,
2467 attrs);
2468 break;
25c13324 2469 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
c9b9dcb4
AL		 2470 err = handle_alloc_dm_sw_icm(context, dm,
2471 attr, attrs,
2472 MLX5_SW_ICM_TYPE_STEERING);
2473 break;
25c13324 2474 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
c9b9dcb4
AL		 2475 err = handle_alloc_dm_sw_icm(context, dm,
2476 attr, attrs,
2477 MLX5_SW_ICM_TYPE_HEADER_MODIFY);
25c13324 2478 break;
3b113a1e
AL		 2479 default:
2480 err = -EOPNOTSUPP;
2481 }
24da0016 2482
3b113a1e
AL		 2483 if (err)
2484 goto err_free;
24da0016
AL		 2485
2486 return &dm->ibdm;
2487
24da0016
AL		 2488err_free:
2489 kfree(dm);
2490 return ERR_PTR(err);
2491}
2492
c4367a26 2493int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs)
24da0016 2494{
25c13324
AL		 2495 struct mlx5_ib_ucontext *ctx = rdma_udata_to_drv_context(
2496 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
c9b9dcb4 2497 struct mlx5_core_dev *dev = to_mdev(ibdm->device)->mdev;
24da0016 2498 struct mlx5_ib_dm *dm = to_mdm(ibdm);
24da0016
AL		 2499 int ret;
2500
3b113a1e
AL		 2501 switch (dm->type) {
2502 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
dc2316eb
YH		 2503 rdma_user_mmap_entry_remove(&dm->mentry.rdma_entry);
2504 return 0;
25c13324 2505 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
c9b9dcb4
AL		 2506 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_STEERING,
2507 dm->size, ctx->devx_uid, dm->dev_addr,
2508 dm->icm_dm.obj_id);
2509 if (ret)
2510 return ret;
2511 break;
25c13324 2512 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
c9b9dcb4
AL		 2513 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_HEADER_MODIFY,
2514 dm->size, ctx->devx_uid, dm->dev_addr,
2515 dm->icm_dm.obj_id);
25c13324
AL		 2516 if (ret)
2517 return ret;
3b113a1e
AL		 2518 break;
2519 default:
2520 return -EOPNOTSUPP;
2521 }
24da0016
AL		 2522
2523 kfree(dm);
2524
2525 return 0;
2526}
2527
ff23dfa1 2528static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
e126ba97 2529{
21a428a0
LR		 2530 struct mlx5_ib_pd *pd = to_mpd(ibpd);
2531 struct ib_device *ibdev = ibpd->device;
e126ba97 2532 struct mlx5_ib_alloc_pd_resp resp;
e126ba97 2533 int err;
a1069c1c
YH		 2534 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2535 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
2536 u16 uid = 0;
ff23dfa1
SR		 2537 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2538 udata, struct mlx5_ib_ucontext, ibucontext);
e126ba97 2539
ff23dfa1 2540 uid = context ? context->devx_uid : 0;
a1069c1c
YH		 2541 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2542 MLX5_SET(alloc_pd_in, in, uid, uid);
2543 err = mlx5_cmd_exec(to_mdev(ibdev)->mdev, in, sizeof(in),
2544 out, sizeof(out));
21a428a0
LR		 2545 if (err)
2546 return err;
e126ba97 2547
a1069c1c
YH		 2548 pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2549 pd->uid = uid;
ff23dfa1 2550 if (udata) {
e126ba97
EC		 2551 resp.pdn = pd->pdn;
2552 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
a1069c1c 2553 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
21a428a0 2554 return -EFAULT;
e126ba97 2555 }
e126ba97
EC		 2556 }
2557
21a428a0 2558 return 0;
e126ba97
EC		 2559}
2560
c4367a26 2561static void mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
e126ba97
EC		 2562{
2563 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2564 struct mlx5_ib_pd *mpd = to_mpd(pd);
2565
a1069c1c 2566 mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
e126ba97
EC		 2567}
2568
466fa6d2
MG		 2569enum {
2570 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2571 MATCH_CRITERIA_ENABLE_MISC_BIT,
71c6e863
AL		 2572 MATCH_CRITERIA_ENABLE_INNER_BIT,
2573 MATCH_CRITERIA_ENABLE_MISC2_BIT
466fa6d2
MG		 2574};
2575
2576#define HEADER_IS_ZERO(match_criteria, headers) \
2577 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2578 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 2579
466fa6d2 2580static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 2581{
466fa6d2 2582 u8 match_criteria_enable;
038d2ef8 2583
466fa6d2
MG		 2584 match_criteria_enable =
2585 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2586 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2587 match_criteria_enable |=
2588 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2589 MATCH_CRITERIA_ENABLE_MISC_BIT;
2590 match_criteria_enable |=
2591 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2592 MATCH_CRITERIA_ENABLE_INNER_BIT;
71c6e863
AL		 2593 match_criteria_enable |=
2594 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2595 MATCH_CRITERIA_ENABLE_MISC2_BIT;
466fa6d2
MG		 2596
2597 return match_criteria_enable;
038d2ef8
MG		 2598}
2599
6113cc44 2600static int set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
ca0d4753 2601{
6113cc44
MG		 2602 u8 entry_mask;
2603 u8 entry_val;
2604 int err = 0;
2605
2606 if (!mask)
2607 goto out;
2608
2609 entry_mask = MLX5_GET(fte_match_set_lyr_2_4, outer_c,
2610 ip_protocol);
2611 entry_val = MLX5_GET(fte_match_set_lyr_2_4, outer_v,
2612 ip_protocol);
2613 if (!entry_mask) {
2614 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2615 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2616 goto out;
2617 }
2618 /* Don't override existing ip protocol */
2619 if (mask != entry_mask || val != entry_val)
2620 err = -EINVAL;
2621out:
2622 return err;
038d2ef8
MG		 2623}
2624
37da2a03 2625static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2d1e697e
MR		 2626 bool inner)
2627{
2628 if (inner) {
2629 MLX5_SET(fte_match_set_misc,
2630 misc_c, inner_ipv6_flow_label, mask);
2631 MLX5_SET(fte_match_set_misc,
2632 misc_v, inner_ipv6_flow_label, val);
2633 } else {
2634 MLX5_SET(fte_match_set_misc,
2635 misc_c, outer_ipv6_flow_label, mask);
2636 MLX5_SET(fte_match_set_misc,
2637 misc_v, outer_ipv6_flow_label, val);
2638 }
2639}
2640
ca0d4753
MG		 2641static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2642{
2643 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2644 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2645 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2646 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2647}
2648
71c6e863
AL		 2649static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2650{
2651 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2652 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2653 return -EOPNOTSUPP;
2654
2655 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2656 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2657 return -EOPNOTSUPP;
2658
2659 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2660 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2661 return -EOPNOTSUPP;
2662
2663 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2664 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2665 return -EOPNOTSUPP;
2666
2667 return 0;
2668}
2669
c47ac6ae
MG		 2670#define LAST_ETH_FIELD vlan_tag
2671#define LAST_IB_FIELD sl
ca0d4753 2672#define LAST_IPV4_FIELD tos
466fa6d2 2673#define LAST_IPV6_FIELD traffic_class
c47ac6ae 2674#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 2675#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 2676#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 2677#define LAST_DROP_FIELD size
3b3233fb 2678#define LAST_COUNTERS_FIELD counters
c47ac6ae
MG		 2679
2680/* Field is the last supported field */
2681#define FIELDS_NOT_SUPPORTED(filter, field)\
2682 memchr_inv((void *)&filter.field +\
2683 sizeof(filter.field), 0,\
2684 sizeof(filter) -\
2685 offsetof(typeof(filter), field) -\
2686 sizeof(filter.field))
2687
2ea26203
MB		 2688int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
2689 bool is_egress,
2690 struct mlx5_flow_act *action)
802c2125 2691{
802c2125
AY		 2692
2693 switch (maction->ib_action.type) {
2694 case IB_FLOW_ACTION_ESP:
501f14e3
MB		 2695 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2696 MLX5_FLOW_CONTEXT_ACTION_DECRYPT))
2697 return -EINVAL;
802c2125
AY		 2698 /* Currently only AES_GCM keymat is supported by the driver */
2699 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2ea26203 2700 action->action |= is_egress ?
802c2125
AY		 2701 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2702 MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2703 return 0;
b1085be3
MB		 2704 case IB_FLOW_ACTION_UNSPECIFIED:
2705 if (maction->flow_action_raw.sub_type ==
2706 MLX5_IB_FLOW_ACTION_MODIFY_HEADER) {
501f14e3
MB		 2707 if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2708 return -EINVAL;
b1085be3 2709 action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2b688ea5
MG		 2710 action->modify_hdr =
2711 maction->flow_action_raw.modify_hdr;
b1085be3
MB		 2712 return 0;
2713 }
10a30896
MB		 2714 if (maction->flow_action_raw.sub_type ==
2715 MLX5_IB_FLOW_ACTION_DECAP) {
501f14e3
MB		 2716 if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP)
2717 return -EINVAL;
10a30896
MB		 2718 action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2719 return 0;
2720 }
e806f932
MB		 2721 if (maction->flow_action_raw.sub_type ==
2722 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) {
501f14e3
MB		 2723 if (action->action &
2724 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT)
2725 return -EINVAL;
e806f932
MB		 2726 action->action |=
2727 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
2b688ea5
MG		 2728 action->pkt_reformat =
2729 maction->flow_action_raw.pkt_reformat;
e806f932
MB		 2730 return 0;
2731 }
b1085be3 2732 /* fall through */
802c2125
AY		 2733 default:
2734 return -EOPNOTSUPP;
2735 }
2736}
2737
bb0ee7dc
JL		 2738static int parse_flow_attr(struct mlx5_core_dev *mdev,
2739 struct mlx5_flow_spec *spec,
2740 const union ib_flow_spec *ib_spec,
802c2125 2741 const struct ib_flow_attr *flow_attr,
71c6e863 2742 struct mlx5_flow_act *action, u32 prev_type)
038d2ef8 2743{
bb0ee7dc
JL		 2744 struct mlx5_flow_context *flow_context = &spec->flow_context;
2745 u32 *match_c = spec->match_criteria;
2746 u32 *match_v = spec->match_value;
466fa6d2
MG		 2747 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2748 misc_parameters);
2749 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2750 misc_parameters);
71c6e863
AL		 2751 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2752 misc_parameters_2);
2753 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2754 misc_parameters_2);
2d1e697e
MR		 2755 void *headers_c;
2756 void *headers_v;
19cc7524 2757 int match_ipv;
802c2125 2758 int ret;
2d1e697e
MR		 2759
2760 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2761 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2762 inner_headers);
2763 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2764 inner_headers);
19cc7524
AL		 2765 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2766 ft_field_support.inner_ip_version);
2d1e697e
MR		 2767 } else {
2768 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2769 outer_headers);
2770 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2771 outer_headers);
19cc7524
AL		 2772 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2773 ft_field_support.outer_ip_version);
2d1e697e 2774 }
466fa6d2 2775
2d1e697e 2776 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 2777 case IB_FLOW_SPEC_ETH:
c47ac6ae 2778 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 2779 return -EOPNOTSUPP;
038d2ef8 2780
2d1e697e 2781 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2782 dmac_47_16),
2783 ib_spec->eth.mask.dst_mac);
2d1e697e 2784 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2785 dmac_47_16),
2786 ib_spec->eth.val.dst_mac);
2787
2d1e697e 2788 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 2789 smac_47_16),
2790 ib_spec->eth.mask.src_mac);
2d1e697e 2791 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 2792 smac_47_16),
2793 ib_spec->eth.val.src_mac);
2794
038d2ef8 2795 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 2796 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 2797 cvlan_tag, 1);
2d1e697e 2798 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 2799 cvlan_tag, 1);
038d2ef8 2800
2d1e697e 2801 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2802 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 2803 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2804 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2805
2d1e697e 2806 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2807 first_cfi,
2808 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 2809 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2810 first_cfi,
2811 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2812
2d1e697e 2813 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2814 first_prio,
2815 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 2816 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2817 first_prio,
2818 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2819 }
2d1e697e 2820 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2821 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 2822 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2823 ethertype, ntohs(ib_spec->eth.val.ether_type));
2824 break;
2825 case IB_FLOW_SPEC_IPV4:
c47ac6ae 2826 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 2827 return -EOPNOTSUPP;
038d2ef8 2828
19cc7524
AL		 2829 if (match_ipv) {
2830 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2831 ip_version, 0xf);
2832 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2833 ip_version, MLX5_FS_IPV4_VERSION);
19cc7524
AL		 2834 } else {
2835 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2836 ethertype, 0xffff);
2837 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2838 ethertype, ETH_P_IP);
2839 }
038d2ef8 2840
2d1e697e 2841 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2842 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2843 &ib_spec->ipv4.mask.src_ip,
2844 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 2845 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2846 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2847 &ib_spec->ipv4.val.src_ip,
2848 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 2849 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2850 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2851 &ib_spec->ipv4.mask.dst_ip,
2852 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 2853 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2854 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2855 &ib_spec->ipv4.val.dst_ip,
2856 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 2857
2d1e697e 2858 set_tos(headers_c, headers_v,
ca0d4753
MG		 2859 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2860
6113cc44
MG		 2861 if (set_proto(headers_c, headers_v,
2862 ib_spec->ipv4.mask.proto,
2863 ib_spec->ipv4.val.proto))
2864 return -EINVAL;
038d2ef8 2865 break;
026bae0c 2866 case IB_FLOW_SPEC_IPV6:
c47ac6ae 2867 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 2868 return -EOPNOTSUPP;
026bae0c 2869
19cc7524
AL		 2870 if (match_ipv) {
2871 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2872 ip_version, 0xf);
2873 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2874 ip_version, MLX5_FS_IPV6_VERSION);
19cc7524
AL		 2875 } else {
2876 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2877 ethertype, 0xffff);
2878 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2879 ethertype, ETH_P_IPV6);
2880 }
026bae0c 2881
2d1e697e 2882 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2883 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2884 &ib_spec->ipv6.mask.src_ip,
2885 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2886 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2887 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2888 &ib_spec->ipv6.val.src_ip,
2889 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2890 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2891 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2892 &ib_spec->ipv6.mask.dst_ip,
2893 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2894 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2895 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2896 &ib_spec->ipv6.val.dst_ip,
2897 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2898
2d1e697e 2899 set_tos(headers_c, headers_v,
466fa6d2
MG		 2900 ib_spec->ipv6.mask.traffic_class,
2901 ib_spec->ipv6.val.traffic_class);
2902
6113cc44
MG		 2903 if (set_proto(headers_c, headers_v,
2904 ib_spec->ipv6.mask.next_hdr,
2905 ib_spec->ipv6.val.next_hdr))
2906 return -EINVAL;
466fa6d2 2907
2d1e697e
MR		 2908 set_flow_label(misc_params_c, misc_params_v,
2909 ntohl(ib_spec->ipv6.mask.flow_label),
2910 ntohl(ib_spec->ipv6.val.flow_label),
2911 ib_spec->type & IB_FLOW_SPEC_INNER);
802c2125
AY		 2912 break;
2913 case IB_FLOW_SPEC_ESP:
2914 if (ib_spec->esp.mask.seq)
2915 return -EOPNOTSUPP;
2d1e697e 2916
802c2125
AY		 2917 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2918 ntohl(ib_spec->esp.mask.spi));
2919 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2920 ntohl(ib_spec->esp.val.spi));
026bae0c 2921 break;
038d2ef8 2922 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2923 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2924 LAST_TCP_UDP_FIELD))
1ffd3a26 2925 return -EOPNOTSUPP;
038d2ef8 2926
6113cc44
MG		 2927 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_TCP))
2928 return -EINVAL;
038d2ef8 2929
2d1e697e 2930 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2931 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2932 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2933 ntohs(ib_spec->tcp_udp.val.src_port));
2934
2d1e697e 2935 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2936 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2937 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2938 ntohs(ib_spec->tcp_udp.val.dst_port));
2939 break;
2940 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2941 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2942 LAST_TCP_UDP_FIELD))
1ffd3a26 2943 return -EOPNOTSUPP;
038d2ef8 2944
6113cc44
MG		 2945 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_UDP))
2946 return -EINVAL;
038d2ef8 2947
2d1e697e 2948 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2949 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2950 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2951 ntohs(ib_spec->tcp_udp.val.src_port));
2952
2d1e697e 2953 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2954 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2955 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2956 ntohs(ib_spec->tcp_udp.val.dst_port));
2957 break;
da2f22ae
AL		 2958 case IB_FLOW_SPEC_GRE:
2959 if (ib_spec->gre.mask.c_ks_res0_ver)
2960 return -EOPNOTSUPP;
2961
6113cc44
MG		 2962 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_GRE))
2963 return -EINVAL;
2964
da2f22ae
AL		 2965 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2966 0xff);
2967 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2968 IPPROTO_GRE);
2969
2970 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
a93b632c 2971 ntohs(ib_spec->gre.mask.protocol));
da2f22ae
AL		 2972 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2973 ntohs(ib_spec->gre.val.protocol));
2974
2975 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
5886a96a 2976 gre_key.nvgre.hi),
da2f22ae
AL		 2977 &ib_spec->gre.mask.key,
2978 sizeof(ib_spec->gre.mask.key));
2979 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
5886a96a 2980 gre_key.nvgre.hi),
da2f22ae
AL		 2981 &ib_spec->gre.val.key,
2982 sizeof(ib_spec->gre.val.key));
2983 break;
71c6e863
AL		 2984 case IB_FLOW_SPEC_MPLS:
2985 switch (prev_type) {
2986 case IB_FLOW_SPEC_UDP:
2987 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2988 ft_field_support.outer_first_mpls_over_udp),
2989 &ib_spec->mpls.mask.tag))
2990 return -EOPNOTSUPP;
2991
2992 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2993 outer_first_mpls_over_udp),
2994 &ib_spec->mpls.val.tag,
2995 sizeof(ib_spec->mpls.val.tag));
2996 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2997 outer_first_mpls_over_udp),
2998 &ib_spec->mpls.mask.tag,
2999 sizeof(ib_spec->mpls.mask.tag));
3000 break;
3001 case IB_FLOW_SPEC_GRE:
3002 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3003 ft_field_support.outer_first_mpls_over_gre),
3004 &ib_spec->mpls.mask.tag))
3005 return -EOPNOTSUPP;
3006
3007 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
3008 outer_first_mpls_over_gre),
3009 &ib_spec->mpls.val.tag,
3010 sizeof(ib_spec->mpls.val.tag));
3011 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
3012 outer_first_mpls_over_gre),
3013 &ib_spec->mpls.mask.tag,
3014 sizeof(ib_spec->mpls.mask.tag));
3015 break;
3016 default:
3017 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
3018 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3019 ft_field_support.inner_first_mpls),
3020 &ib_spec->mpls.mask.tag))
3021 return -EOPNOTSUPP;
3022
3023 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
3024 inner_first_mpls),
3025 &ib_spec->mpls.val.tag,
3026 sizeof(ib_spec->mpls.val.tag));
3027 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
3028 inner_first_mpls),
3029 &ib_spec->mpls.mask.tag,
3030 sizeof(ib_spec->mpls.mask.tag));
3031 } else {
3032 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3033 ft_field_support.outer_first_mpls),
3034 &ib_spec->mpls.mask.tag))
3035 return -EOPNOTSUPP;
3036
3037 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
3038 outer_first_mpls),
3039 &ib_spec->mpls.val.tag,
3040 sizeof(ib_spec->mpls.val.tag));
3041 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
3042 outer_first_mpls),
3043 &ib_spec->mpls.mask.tag,
3044 sizeof(ib_spec->mpls.mask.tag));
3045 }
3046 }
3047 break;
ffb30d8f
MR		 3048 case IB_FLOW_SPEC_VXLAN_TUNNEL:
3049 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
3050 LAST_TUNNEL_FIELD))
1ffd3a26 3051 return -EOPNOTSUPP;
ffb30d8f
MR		 3052
3053 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
3054 ntohl(ib_spec->tunnel.mask.tunnel_id));
3055 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
3056 ntohl(ib_spec->tunnel.val.tunnel_id));
3057 break;
2ac693f9
MR		 3058 case IB_FLOW_SPEC_ACTION_TAG:
3059 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
3060 LAST_FLOW_TAG_FIELD))
3061 return -EOPNOTSUPP;
3062 if (ib_spec->flow_tag.tag_id >= BIT(24))
3063 return -EINVAL;
3064
bb0ee7dc
JL		 3065 flow_context->flow_tag = ib_spec->flow_tag.tag_id;
3066 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
2ac693f9 3067 break;
a22ed86c
SS		 3068 case IB_FLOW_SPEC_ACTION_DROP:
3069 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
3070 LAST_DROP_FIELD))
3071 return -EOPNOTSUPP;
075572d4 3072 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
a22ed86c 3073 break;
802c2125 3074 case IB_FLOW_SPEC_ACTION_HANDLE:
2ea26203
MB		 3075 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act),
3076 flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action);
802c2125
AY		 3077 if (ret)
3078 return ret;
3079 break;
3b3233fb
RS		 3080 case IB_FLOW_SPEC_ACTION_COUNT:
3081 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
3082 LAST_COUNTERS_FIELD))
3083 return -EOPNOTSUPP;
3084
3085 /* for now support only one counters spec per flow */
3086 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
3087 return -EINVAL;
3088
3089 action->counters = ib_spec->flow_count.counters;
3090 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3091 break;
038d2ef8
MG		 3092 default:
3093 return -EINVAL;
3094 }
3095
3096 return 0;
3097}
3098
3099/* If a flow could catch both multicast and unicast packets,
3100 * it won't fall into the multicast flow steering table and this rule
3101 * could steal other multicast packets.
3102 */
a550ddfc 3103static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
038d2ef8 3104{
81e30880 3105 union ib_flow_spec *flow_spec;
038d2ef8
MG		 3106
3107 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 3108 ib_attr->num_of_specs < 1)
3109 return false;
3110
81e30880
YH		 3111 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
3112 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
3113 struct ib_flow_spec_ipv4 *ipv4_spec;
3114
3115 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
3116 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
3117 return true;
3118
038d2ef8 3119 return false;
81e30880
YH		 3120 }
3121
3122 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
3123 struct ib_flow_spec_eth *eth_spec;
3124
3125 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
3126 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
3127 is_multicast_ether_addr(eth_spec->val.dst_mac);
3128 }
038d2ef8 3129
81e30880 3130 return false;
038d2ef8
MG		 3131}
3132
802c2125
AY		 3133enum valid_spec {
3134 VALID_SPEC_INVALID,
3135 VALID_SPEC_VALID,
3136 VALID_SPEC_NA,
3137};
3138
3139static enum valid_spec
3140is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
3141 const struct mlx5_flow_spec *spec,
3142 const struct mlx5_flow_act *flow_act,
3143 bool egress)
3144{
3145 const u32 *match_c = spec->match_criteria;
3146 bool is_crypto =
3147 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
3148 MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
3149 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
3150 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
3151
3152 /*
3153 * Currently only crypto is supported in egress, when regular egress
3154 * rules would be supported, always return VALID_SPEC_NA.
3155 */
3156 if (!is_crypto)
78dd0c43 3157 return VALID_SPEC_NA;
802c2125
AY		 3158
3159 return is_crypto && is_ipsec &&
bb0ee7dc
JL		 3160 (!egress || (!is_drop &&
3161 !(spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG))) ?
802c2125
AY		 3162 VALID_SPEC_VALID : VALID_SPEC_INVALID;
3163}
3164
3165static bool is_valid_spec(struct mlx5_core_dev *mdev,
3166 const struct mlx5_flow_spec *spec,
3167 const struct mlx5_flow_act *flow_act,
3168 bool egress)
3169{
3170 /* We curretly only support ipsec egress flow */
3171 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
3172}
3173
19cc7524
AL		 3174static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
3175 const struct ib_flow_attr *flow_attr,
0f750966 3176 bool check_inner)
038d2ef8
MG		 3177{
3178 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 3179 int match_ipv = check_inner ?
3180 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3181 ft_field_support.inner_ip_version) :
3182 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3183 ft_field_support.outer_ip_version);
0f750966
AL		 3184 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
3185 bool ipv4_spec_valid, ipv6_spec_valid;
3186 unsigned int ip_spec_type = 0;
3187 bool has_ethertype = false;
038d2ef8 3188 unsigned int spec_index;
0f750966
AL		 3189 bool mask_valid = true;
3190 u16 eth_type = 0;
3191 bool type_valid;
038d2ef8
MG		 3192
3193 /* Validate that ethertype is correct */
3194 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 3195 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 3196 ib_spec->eth.mask.ether_type) {
0f750966
AL		 3197 mask_valid = (ib_spec->eth.mask.ether_type ==
3198 htons(0xffff));
3199 has_ethertype = true;
3200 eth_type = ntohs(ib_spec->eth.val.ether_type);
3201 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
3202 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
3203 ip_spec_type = ib_spec->type;
038d2ef8
MG		 3204 }
3205 ib_spec = (void *)ib_spec + ib_spec->size;
3206 }
0f750966
AL		 3207
3208 type_valid = (!has_ethertype) || (!ip_spec_type);
3209 if (!type_valid && mask_valid) {
3210 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
3211 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
3212 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
3213 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 3214
3215 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
3216 (((eth_type == ETH_P_MPLS_UC) ||
3217 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 3218 }
3219
3220 return type_valid;
3221}
3222
19cc7524
AL		 3223static bool is_valid_attr(struct mlx5_core_dev *mdev,
3224 const struct ib_flow_attr *flow_attr)
0f750966 3225{
19cc7524
AL		 3226 return is_valid_ethertype(mdev, flow_attr, false) &&
3227 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 3228}
3229
3230static void put_flow_table(struct mlx5_ib_dev *dev,
3231 struct mlx5_ib_flow_prio *prio, bool ft_added)
3232{
3233 prio->refcount -= !!ft_added;
3234 if (!prio->refcount) {
3235 mlx5_destroy_flow_table(prio->flow_table);
3236 prio->flow_table = NULL;
3237 }
3238}
3239
3b3233fb
RS		 3240static void counters_clear_description(struct ib_counters *counters)
3241{
3242 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3243
3244 mutex_lock(&mcounters->mcntrs_mutex);
3245 kfree(mcounters->counters_data);
3246 mcounters->counters_data = NULL;
3247 mcounters->cntrs_max_index = 0;
3248 mutex_unlock(&mcounters->mcntrs_mutex);
3249}
3250
038d2ef8
MG		 3251static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
3252{
038d2ef8
MG		 3253 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
3254 struct mlx5_ib_flow_handler,
3255 ibflow);
3256 struct mlx5_ib_flow_handler *iter, *tmp;
d4be3f44 3257 struct mlx5_ib_dev *dev = handler->dev;
038d2ef8 3258
9a4ca38d 3259 mutex_lock(&dev->flow_db->lock);
038d2ef8
MG		 3260
3261 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 3262 mlx5_del_flow_rules(iter->rule);
cc0e5d42 3263 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 3264 list_del(&iter->list);
3265 kfree(iter);
3266 }
3267
74491de9 3268 mlx5_del_flow_rules(handler->rule);
5497adc6 3269 put_flow_table(dev, handler->prio, true);
3b3233fb
RS		 3270 if (handler->ibcounters &&
3271 atomic_read(&handler->ibcounters->usecnt) == 1)
3272 counters_clear_description(handler->ibcounters);
038d2ef8 3273
3b3233fb 3274 mutex_unlock(&dev->flow_db->lock);
d4be3f44
YH		 3275 if (handler->flow_matcher)
3276 atomic_dec(&handler->flow_matcher->usecnt);
038d2ef8
MG		 3277 kfree(handler);
3278
3279 return 0;
3280}
3281
35d19011
MG		 3282static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
3283{
3284 priority *= 2;
3285 if (!dont_trap)
3286 priority++;
3287 return priority;
3288}
3289
cc0e5d42
MG		 3290enum flow_table_type {
3291 MLX5_IB_FT_RX,
3292 MLX5_IB_FT_TX
3293};
3294
00b7c2ab
MG		 3295#define MLX5_FS_MAX_TYPES 6
3296#define MLX5_FS_MAX_ENTRIES BIT(16)
d4be3f44
YH		 3297
3298static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns,
3299 struct mlx5_ib_flow_prio *prio,
3300 int priority,
4adda112
MB		 3301 int num_entries, int num_groups,
3302 u32 flags)
d4be3f44 3303{
61dc7b01 3304 struct mlx5_flow_table_attr ft_attr = {};
d4be3f44
YH		 3305 struct mlx5_flow_table *ft;
3306
61dc7b01
PB		 3307 ft_attr.prio = priority;
3308 ft_attr.max_fte = num_entries;
3309 ft_attr.flags = flags;
3310 ft_attr.autogroup.max_num_groups = num_groups;
3311 ft = mlx5_create_auto_grouped_flow_table(ns, &ft_attr);
d4be3f44
YH		 3312 if (IS_ERR(ft))
3313 return ERR_CAST(ft);
3314
3315 prio->flow_table = ft;
3316 prio->refcount = 0;
3317 return prio;
3318}
3319
038d2ef8 3320static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 3321 struct ib_flow_attr *flow_attr,
3322 enum flow_table_type ft_type)
038d2ef8 3323{
35d19011 3324 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 3325 struct mlx5_flow_namespace *ns = NULL;
3326 struct mlx5_ib_flow_prio *prio;
3327 struct mlx5_flow_table *ft;
dac388ef 3328 int max_table_size;
038d2ef8
MG		 3329 int num_entries;
3330 int num_groups;
cecae747 3331 bool esw_encap;
4adda112 3332 u32 flags = 0;
038d2ef8 3333 int priority;
038d2ef8 3334
dac388ef
MG		 3335 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3336 log_max_ft_size));
cecae747
MG		 3337 esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
3338 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
038d2ef8 3339 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
78dd0c43
MB		 3340 enum mlx5_flow_namespace_type fn_type;
3341
3342 if (flow_is_multicast_only(flow_attr) &&
3343 !dont_trap)
038d2ef8
MG		 3344 priority = MLX5_IB_FLOW_MCAST_PRIO;
3345 else
35d19011
MG		 3346 priority = ib_prio_to_core_prio(flow_attr->priority,
3347 dont_trap);
78dd0c43
MB		 3348 if (ft_type == MLX5_IB_FT_RX) {
3349 fn_type = MLX5_FLOW_NAMESPACE_BYPASS;
3350 prio = &dev->flow_db->prios[priority];
cecae747 3351 if (!dev->is_rep && !esw_encap &&
4adda112
MB		 3352 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3353 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
cecae747 3354 if (!dev->is_rep && !esw_encap &&
5c2db53f
MB		 3355 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3356 reformat_l3_tunnel_to_l2))
3357 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
78dd0c43
MB		 3358 } else {
3359 max_table_size =
3360 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3361 log_max_ft_size));
3362 fn_type = MLX5_FLOW_NAMESPACE_EGRESS;
3363 prio = &dev->flow_db->egress_prios[priority];
cecae747 3364 if (!dev->is_rep && !esw_encap &&
4adda112
MB		 3365 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3366 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
78dd0c43
MB		 3367 }
3368 ns = mlx5_get_flow_namespace(dev->mdev, fn_type);
038d2ef8
MG		 3369 num_entries = MLX5_FS_MAX_ENTRIES;
3370 num_groups = MLX5_FS_MAX_TYPES;
038d2ef8
MG		 3371 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3372 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3373 ns = mlx5_get_flow_namespace(dev->mdev,
3374 MLX5_FLOW_NAMESPACE_LEFTOVERS);
3375 build_leftovers_ft_param(&priority,
3376 &num_entries,
3377 &num_groups);
9a4ca38d 3378 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 3379 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3380 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3381 allow_sniffer_and_nic_rx_shared_tir))
3382 return ERR_PTR(-ENOTSUPP);
3383
3384 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3385 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3386 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3387
9a4ca38d 3388 prio = &dev->flow_db->sniffer[ft_type];
cc0e5d42
MG		 3389 priority = 0;
3390 num_entries = 1;
3391 num_groups = 1;
038d2ef8
MG		 3392 }
3393
3394 if (!ns)
3395 return ERR_PTR(-ENOTSUPP);
3396
3b70508a 3397 max_table_size = min_t(int, num_entries, max_table_size);
dac388ef 3398
038d2ef8 3399 ft = prio->flow_table;
d4be3f44 3400 if (!ft)
3b70508a 3401 return _get_prio(ns, prio, priority, max_table_size, num_groups,
4adda112 3402 flags);
038d2ef8 3403
d4be3f44 3404 return prio;
038d2ef8
MG		 3405}
3406
a550ddfc
YH		 3407static void set_underlay_qp(struct mlx5_ib_dev *dev,
3408 struct mlx5_flow_spec *spec,
3409 u32 underlay_qpn)
3410{
3411 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3412 spec->match_criteria,
3413 misc_parameters);
3414 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3415 misc_parameters);
3416
3417 if (underlay_qpn &&
3418 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3419 ft_field_support.bth_dst_qp)) {
3420 MLX5_SET(fte_match_set_misc,
3421 misc_params_v, bth_dst_qp, underlay_qpn);
3422 MLX5_SET(fte_match_set_misc,
3423 misc_params_c, bth_dst_qp, 0xffffff);
3424 }
3425}
3426
5e95af5f
RS		 3427static int read_flow_counters(struct ib_device *ibdev,
3428 struct mlx5_read_counters_attr *read_attr)
3429{
3430 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3431 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3432
3433 return mlx5_fc_query(dev->mdev, fc,
3434 &read_attr->out[IB_COUNTER_PACKETS],
3435 &read_attr->out[IB_COUNTER_BYTES]);
3436}
3437
3438/* flow counters currently expose two counters packets and bytes */
3439#define FLOW_COUNTERS_NUM 2
3b3233fb
RS		 3440static int counters_set_description(struct ib_counters *counters,
3441 enum mlx5_ib_counters_type counters_type,
3442 struct mlx5_ib_flow_counters_desc *desc_data,
3443 u32 ncounters)
3444{
3445 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3446 u32 cntrs_max_index = 0;
3447 int i;
3448
3449 if (counters_type != MLX5_IB_COUNTERS_FLOW)
3450 return -EINVAL;
3451
3452 /* init the fields for the object */
3453 mcounters->type = counters_type;
5e95af5f
RS		 3454 mcounters->read_counters = read_flow_counters;
3455 mcounters->counters_num = FLOW_COUNTERS_NUM;
3b3233fb
RS		 3456 mcounters->ncounters = ncounters;
3457 /* each counter entry have both description and index pair */
3458 for (i = 0; i < ncounters; i++) {
3459 if (desc_data[i].description > IB_COUNTER_BYTES)
3460 return -EINVAL;
3461
3462 if (cntrs_max_index <= desc_data[i].index)
3463 cntrs_max_index = desc_data[i].index + 1;
3464 }
3465
3466 mutex_lock(&mcounters->mcntrs_mutex);
3467 mcounters->counters_data = desc_data;
3468 mcounters->cntrs_max_index = cntrs_max_index;
3469 mutex_unlock(&mcounters->mcntrs_mutex);
3470
3471 return 0;
3472}
3473
3474#define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3475static int flow_counters_set_data(struct ib_counters *ibcounters,
3476 struct mlx5_ib_create_flow *ucmd)
3477{
3478 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3479 struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3480 struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3481 bool hw_hndl = false;
3482 int ret = 0;
3483
3484 if (ucmd && ucmd->ncounters_data != 0) {
3485 cntrs_data = ucmd->data;
3486 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3487 return -EINVAL;
3488
3489 desc_data = kcalloc(cntrs_data->ncounters,
3490 sizeof(*desc_data),
3491 GFP_KERNEL);
3492 if (!desc_data)
3493 return -ENOMEM;
3494
3495 if (copy_from_user(desc_data,
3496 u64_to_user_ptr(cntrs_data->counters_data),
3497 sizeof(*desc_data) * cntrs_data->ncounters)) {
3498 ret = -EFAULT;
3499 goto free;
3500 }
3501 }
3502
3503 if (!mcounters->hw_cntrs_hndl) {
3504 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3505 to_mdev(ibcounters->device)->mdev, false);
e31abf76 3506 if (IS_ERR(mcounters->hw_cntrs_hndl)) {
3507 ret = PTR_ERR(mcounters->hw_cntrs_hndl);
3b3233fb
RS		 3508 goto free;
3509 }
3510 hw_hndl = true;
3511 }
3512
3513 if (desc_data) {
3514 /* counters already bound to at least one flow */
3515 if (mcounters->cntrs_max_index) {
3516 ret = -EINVAL;
3517 goto free_hndl;
3518 }
3519
3520 ret = counters_set_description(ibcounters,
3521 MLX5_IB_COUNTERS_FLOW,
3522 desc_data,
3523 cntrs_data->ncounters);
3524 if (ret)
3525 goto free_hndl;
3526
3527 } else if (!mcounters->cntrs_max_index) {
3528 /* counters not bound yet, must have udata passed */
3529 ret = -EINVAL;
3530 goto free_hndl;
3531 }
3532
3533 return 0;
3534
3535free_hndl:
3536 if (hw_hndl) {
3537 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3538 mcounters->hw_cntrs_hndl);
3539 mcounters->hw_cntrs_hndl = NULL;
3540 }
3541free:
3542 kfree(desc_data);
3543 return ret;
3544}
3545
669ff1e3
JL		 3546static void mlx5_ib_set_rule_source_port(struct mlx5_ib_dev *dev,
3547 struct mlx5_flow_spec *spec,
3548 struct mlx5_eswitch_rep *rep)
3549{
3550 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
3551 void *misc;
3552
3553 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
3554 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3555 misc_parameters_2);
3556
3557 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
3558 mlx5_eswitch_get_vport_metadata_for_match(esw,
3559 rep->vport));
3560 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3561 misc_parameters_2);
3562
3563 MLX5_SET_TO_ONES(fte_match_set_misc2, misc, metadata_reg_c_0);
3564 } else {
3565 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3566 misc_parameters);
3567
3568 MLX5_SET(fte_match_set_misc, misc, source_port, rep->vport);
3569
3570 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3571 misc_parameters);
3572
3573 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3574 }
3575}
3576
a550ddfc
YH		 3577static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3578 struct mlx5_ib_flow_prio *ft_prio,
3579 const struct ib_flow_attr *flow_attr,
3580 struct mlx5_flow_destination *dst,
3b3233fb
RS		 3581 u32 underlay_qpn,
3582 struct mlx5_ib_create_flow *ucmd)
038d2ef8
MG		 3583{
3584 struct mlx5_flow_table *ft = ft_prio->flow_table;
3585 struct mlx5_ib_flow_handler *handler;
bb0ee7dc 3586 struct mlx5_flow_act flow_act = {};
c5bb1730 3587 struct mlx5_flow_spec *spec;
3b3233fb
RS		 3588 struct mlx5_flow_destination dest_arr[2] = {};
3589 struct mlx5_flow_destination *rule_dst = dest_arr;
dd063d0e 3590 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 3591 unsigned int spec_index;
71c6e863 3592 u32 prev_type = 0;
038d2ef8 3593 int err = 0;
3b3233fb 3594 int dest_num = 0;
802c2125 3595 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
038d2ef8 3596
19cc7524 3597 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 3598 return ERR_PTR(-EINVAL);
3599
6a4d00be 3600 if (dev->is_rep && is_egress)
78dd0c43
MB		 3601 return ERR_PTR(-EINVAL);
3602
1b9a07ee 3603 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 3604 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 3605 if (!handler || !spec) {
038d2ef8
MG		 3606 err = -ENOMEM;
3607 goto free;
3608 }
3609
3610 INIT_LIST_HEAD(&handler->list);
3611
3612 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
bb0ee7dc 3613 err = parse_flow_attr(dev->mdev, spec,
71c6e863
AL		 3614 ib_flow, flow_attr, &flow_act,
3615 prev_type);
038d2ef8
MG		 3616 if (err < 0)
3617 goto free;
3618
71c6e863 3619 prev_type = ((union ib_flow_spec *)ib_flow)->type;
038d2ef8
MG		 3620 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3621 }
3622
ed9085fe
MG		 3623 if (dst && !(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP)) {
3624 memcpy(&dest_arr[0], dst, sizeof(*dst));
3625 dest_num++;
3626 }
3627
a550ddfc
YH		 3628 if (!flow_is_multicast_only(flow_attr))
3629 set_underlay_qp(dev, spec, underlay_qpn);
3630
6a4d00be 3631 if (dev->is_rep) {
669ff1e3 3632 struct mlx5_eswitch_rep *rep;
018a94ee 3633
669ff1e3
JL		 3634 rep = dev->port[flow_attr->port - 1].rep;
3635 if (!rep) {
6a4d00be
MB		 3636 err = -EINVAL;
3637 goto free;
3638 }
669ff1e3
JL		 3639
3640 mlx5_ib_set_rule_source_port(dev, spec, rep);
018a94ee
MB		 3641 }
3642
466fa6d2 3643 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
802c2125
AY		 3644
3645 if (is_egress &&
3646 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3647 err = -EINVAL;
3648 goto free;
3649 }
3650
3b3233fb 3651 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
171c7625
MB		 3652 struct mlx5_ib_mcounters *mcounters;
3653
3b3233fb
RS		 3654 err = flow_counters_set_data(flow_act.counters, ucmd);
3655 if (err)
3656 goto free;
3657
171c7625 3658 mcounters = to_mcounters(flow_act.counters);
3b3233fb
RS		 3659 handler->ibcounters = flow_act.counters;
3660 dest_arr[dest_num].type =
3661 MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625
MB		 3662 dest_arr[dest_num].counter_id =
3663 mlx5_fc_id(mcounters->hw_cntrs_hndl);
3b3233fb
RS		 3664 dest_num++;
3665 }
3666
075572d4 3667 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
ed9085fe 3668 if (!dest_num)
3b3233fb 3669 rule_dst = NULL;
a22ed86c 3670 } else {
802c2125
AY		 3671 if (is_egress)
3672 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3673 else
3674 flow_act.action |=
3b3233fb 3675 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
802c2125 3676 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
a22ed86c 3677 }
2ac693f9 3678
bb0ee7dc 3679 if ((spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG) &&
2ac693f9
MR		 3680 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3681 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3682 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
bb0ee7dc 3683 spec->flow_context.flow_tag, flow_attr->type);
2ac693f9
MR		 3684 err = -EINVAL;
3685 goto free;
3686 }
74491de9 3687 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 3688 &flow_act,
a22ed86c 3689 rule_dst, dest_num);
038d2ef8
MG		 3690
3691 if (IS_ERR(handler->rule)) {
3692 err = PTR_ERR(handler->rule);
3693 goto free;
3694 }
3695
d9d4980a 3696 ft_prio->refcount++;
5497adc6 3697 handler->prio = ft_prio;
d4be3f44 3698 handler->dev = dev;
038d2ef8
MG		 3699
3700 ft_prio->flow_table = ft;
3701free:
3b3233fb
RS		 3702 if (err && handler) {
3703 if (handler->ibcounters &&
3704 atomic_read(&handler->ibcounters->usecnt) == 1)
3705 counters_clear_description(handler->ibcounters);
038d2ef8 3706 kfree(handler);
3b3233fb 3707 }
c5bb1730 3708 kvfree(spec);
038d2ef8
MG		 3709 return err ? ERR_PTR(err) : handler;
3710}
3711
a550ddfc
YH		 3712static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3713 struct mlx5_ib_flow_prio *ft_prio,
3714 const struct ib_flow_attr *flow_attr,
3715 struct mlx5_flow_destination *dst)
3716{
3b3233fb 3717 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
a550ddfc
YH		 3718}
3719
35d19011
MG		 3720static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3721 struct mlx5_ib_flow_prio *ft_prio,
3722 struct ib_flow_attr *flow_attr,
3723 struct mlx5_flow_destination *dst)
3724{
3725 struct mlx5_ib_flow_handler *handler_dst = NULL;
3726 struct mlx5_ib_flow_handler *handler = NULL;
3727
3728 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3729 if (!IS_ERR(handler)) {
3730 handler_dst = create_flow_rule(dev, ft_prio,
3731 flow_attr, dst);
3732 if (IS_ERR(handler_dst)) {
74491de9 3733 mlx5_del_flow_rules(handler->rule);
d9d4980a 3734 ft_prio->refcount--;
35d19011
MG		 3735 kfree(handler);
3736 handler = handler_dst;
3737 } else {
3738 list_add(&handler_dst->list, &handler->list);
3739 }
3740 }
3741
3742 return handler;
3743}
038d2ef8
MG		 3744enum {
3745 LEFTOVERS_MC,
3746 LEFTOVERS_UC,
3747};
3748
3749static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3750 struct mlx5_ib_flow_prio *ft_prio,
3751 struct ib_flow_attr *flow_attr,
3752 struct mlx5_flow_destination *dst)
3753{
3754 struct mlx5_ib_flow_handler *handler_ucast = NULL;
3755 struct mlx5_ib_flow_handler *handler = NULL;
3756
3757 static struct {
3758 struct ib_flow_attr flow_attr;
3759 struct ib_flow_spec_eth eth_flow;
3760 } leftovers_specs[] = {
3761 [LEFTOVERS_MC] = {
3762 .flow_attr = {
3763 .num_of_specs = 1,
3764 .size = sizeof(leftovers_specs[0])
3765 },
3766 .eth_flow = {
3767 .type = IB_FLOW_SPEC_ETH,
3768 .size = sizeof(struct ib_flow_spec_eth),
3769 .mask = {.dst_mac = {0x1} },
3770 .val = {.dst_mac = {0x1} }
3771 }
3772 },
3773 [LEFTOVERS_UC] = {
3774 .flow_attr = {
3775 .num_of_specs = 1,
3776 .size = sizeof(leftovers_specs[0])
3777 },
3778 .eth_flow = {
3779 .type = IB_FLOW_SPEC_ETH,
3780 .size = sizeof(struct ib_flow_spec_eth),
3781 .mask = {.dst_mac = {0x1} },
3782 .val = {.dst_mac = {} }
3783 }
3784 }
3785 };
3786
3787 handler = create_flow_rule(dev, ft_prio,
3788 &leftovers_specs[LEFTOVERS_MC].flow_attr,
3789 dst);
3790 if (!IS_ERR(handler) &&
3791 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3792 handler_ucast = create_flow_rule(dev, ft_prio,
3793 &leftovers_specs[LEFTOVERS_UC].flow_attr,
3794 dst);
3795 if (IS_ERR(handler_ucast)) {
74491de9 3796 mlx5_del_flow_rules(handler->rule);
d9d4980a 3797 ft_prio->refcount--;
038d2ef8
MG		 3798 kfree(handler);
3799 handler = handler_ucast;
3800 } else {
3801 list_add(&handler_ucast->list, &handler->list);
3802 }
3803 }
3804
3805 return handler;
3806}
3807
cc0e5d42
MG		 3808static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3809 struct mlx5_ib_flow_prio *ft_rx,
3810 struct mlx5_ib_flow_prio *ft_tx,
3811 struct mlx5_flow_destination *dst)
3812{
3813 struct mlx5_ib_flow_handler *handler_rx;
3814 struct mlx5_ib_flow_handler *handler_tx;
3815 int err;
3816 static const struct ib_flow_attr flow_attr = {
3817 .num_of_specs = 0,
3818 .size = sizeof(flow_attr)
3819 };
3820
3821 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3822 if (IS_ERR(handler_rx)) {
3823 err = PTR_ERR(handler_rx);
3824 goto err;
3825 }
3826
3827 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3828 if (IS_ERR(handler_tx)) {
3829 err = PTR_ERR(handler_tx);
3830 goto err_tx;
3831 }
3832
3833 list_add(&handler_tx->list, &handler_rx->list);
3834
3835 return handler_rx;
3836
3837err_tx:
74491de9 3838 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 3839 ft_rx->refcount--;
3840 kfree(handler_rx);
3841err:
3842 return ERR_PTR(err);
3843}
3844
038d2ef8
MG		 3845static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3846 struct ib_flow_attr *flow_attr,
59082a32
MB		 3847 int domain,
3848 struct ib_udata *udata)
038d2ef8
MG		 3849{
3850 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 3851 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 3852 struct mlx5_ib_flow_handler *handler = NULL;
3853 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 3854 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8 3855 struct mlx5_ib_flow_prio *ft_prio;
802c2125 3856 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3b3233fb
RS		 3857 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3858 size_t min_ucmd_sz, required_ucmd_sz;
038d2ef8 3859 int err;
a550ddfc 3860 int underlay_qpn;
038d2ef8 3861
3b3233fb
RS		 3862 if (udata && udata->inlen) {
3863 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3864 sizeof(ucmd_hdr.reserved);
3865 if (udata->inlen < min_ucmd_sz)
3866 return ERR_PTR(-EOPNOTSUPP);
3867
3868 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3869 if (err)
3870 return ERR_PTR(err);
3871
3872 /* currently supports only one counters data */
3873 if (ucmd_hdr.ncounters_data > 1)
3874 return ERR_PTR(-EINVAL);
3875
3876 required_ucmd_sz = min_ucmd_sz +
3877 sizeof(struct mlx5_ib_flow_counters_data) *
3878 ucmd_hdr.ncounters_data;
3879 if (udata->inlen > required_ucmd_sz &&
3880 !ib_is_udata_cleared(udata, required_ucmd_sz,
3881 udata->inlen - required_ucmd_sz))
3882 return ERR_PTR(-EOPNOTSUPP);
3883
3884 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3885 if (!ucmd)
3886 return ERR_PTR(-ENOMEM);
3887
3888 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
299eafee
GS		 3889 if (err)
3890 goto free_ucmd;
3b3233fb 3891 }
59082a32 3892
299eafee
GS		 3893 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) {
3894 err = -ENOMEM;
3895 goto free_ucmd;
3896 }
038d2ef8
MG		 3897
3898 if (domain != IB_FLOW_DOMAIN_USER ||
508562d6 3899 flow_attr->port > dev->num_ports ||
802c2125 3900 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
299eafee
GS		 3901 IB_FLOW_ATTR_FLAGS_EGRESS))) {
3902 err = -EINVAL;
3903 goto free_ucmd;
3904 }
802c2125
AY		 3905
3906 if (is_egress &&
3907 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
299eafee
GS		 3908 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3909 err = -EINVAL;
3910 goto free_ucmd;
3911 }
038d2ef8
MG		 3912
3913 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
299eafee
GS		 3914 if (!dst) {
3915 err = -ENOMEM;
3916 goto free_ucmd;
3917 }
038d2ef8 3918
9a4ca38d 3919 mutex_lock(&dev->flow_db->lock);
038d2ef8 3920
802c2125
AY		 3921 ft_prio = get_flow_table(dev, flow_attr,
3922 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
038d2ef8
MG		 3923 if (IS_ERR(ft_prio)) {
3924 err = PTR_ERR(ft_prio);
3925 goto unlock;
3926 }
cc0e5d42
MG		 3927 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3928 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3929 if (IS_ERR(ft_prio_tx)) {
3930 err = PTR_ERR(ft_prio_tx);
3931 ft_prio_tx = NULL;
3932 goto destroy_ft;
3933 }
3934 }
038d2ef8 3935
802c2125
AY		 3936 if (is_egress) {
3937 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3938 } else {
3939 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3940 if (mqp->flags & MLX5_IB_QP_RSS)
3941 dst->tir_num = mqp->rss_qp.tirn;
3942 else
3943 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3944 }
038d2ef8
MG		 3945
3946 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 3947 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3948 handler = create_dont_trap_rule(dev, ft_prio,
3949 flow_attr, dst);
3950 } else {
a550ddfc
YH		 3951 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3952 mqp->underlay_qpn : 0;
3953 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3b3233fb 3954 dst, underlay_qpn, ucmd);
35d19011 3955 }
038d2ef8
MG		 3956 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3957 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3958 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3959 dst);
cc0e5d42
MG		 3960 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3961 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 3962 } else {
3963 err = -EINVAL;
3964 goto destroy_ft;
3965 }
3966
3967 if (IS_ERR(handler)) {
3968 err = PTR_ERR(handler);
3969 handler = NULL;
3970 goto destroy_ft;
3971 }
3972
9a4ca38d 3973 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3974 kfree(dst);
3b3233fb 3975 kfree(ucmd);
038d2ef8
MG		 3976
3977 return &handler->ibflow;
3978
3979destroy_ft:
3980 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 3981 if (ft_prio_tx)
3982 put_flow_table(dev, ft_prio_tx, false);
038d2ef8 3983unlock:
9a4ca38d 3984 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3985 kfree(dst);
299eafee 3986free_ucmd:
3b3233fb 3987 kfree(ucmd);
038d2ef8
MG		 3988 return ERR_PTR(err);
3989}
3990
b47fd4ff
MB		 3991static struct mlx5_ib_flow_prio *
3992_get_flow_table(struct mlx5_ib_dev *dev,
3993 struct mlx5_ib_flow_matcher *fs_matcher,
3994 bool mcast)
d4be3f44 3995{
d4be3f44 3996 struct mlx5_flow_namespace *ns = NULL;
13a43765
MB		 3997 struct mlx5_ib_flow_prio *prio = NULL;
3998 int max_table_size = 0;
cecae747 3999 bool esw_encap;
b47fd4ff
MB		 4000 u32 flags = 0;
4001 int priority;
4002
13a43765
MB		 4003 if (mcast)
4004 priority = MLX5_IB_FLOW_MCAST_PRIO;
4005 else
4006 priority = ib_prio_to_core_prio(fs_matcher->priority, false);
4007
cecae747
MG		 4008 esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
4009 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
b47fd4ff
MB		 4010 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) {
4011 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
4012 log_max_ft_size));
cecae747 4013 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap) && !esw_encap)
b47fd4ff
MB		 4014 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
4015 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
cecae747
MG		 4016 reformat_l3_tunnel_to_l2) &&
4017 !esw_encap)
b47fd4ff 4018 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
13a43765
MB		 4019 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS) {
4020 max_table_size = BIT(
4021 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, log_max_ft_size));
cecae747 4022 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat) && !esw_encap)
b47fd4ff 4023 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
13a43765
MB		 4024 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB) {
4025 max_table_size = BIT(
4026 MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, log_max_ft_size));
09d985be
MG		 4027 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, decap) && esw_encap)
4028 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
4029 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, reformat_l3_tunnel_to_l2) &&
4030 esw_encap)
4031 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
13a43765 4032 priority = FDB_BYPASS_PATH;
d8abe884
MZ		 4033 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_RDMA_RX) {
4034 max_table_size =
4035 BIT(MLX5_CAP_FLOWTABLE_RDMA_RX(dev->mdev,
4036 log_max_ft_size));
4037 priority = fs_matcher->priority;
b47fd4ff 4038 }
d4be3f44 4039
3b70508a 4040 max_table_size = min_t(int, max_table_size, MLX5_FS_MAX_ENTRIES);
d4be3f44 4041
b47fd4ff 4042 ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type);
d4be3f44
YH		 4043 if (!ns)
4044 return ERR_PTR(-ENOTSUPP);
4045
b47fd4ff
MB		 4046 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS)
4047 prio = &dev->flow_db->prios[priority];
13a43765 4048 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS)
b47fd4ff 4049 prio = &dev->flow_db->egress_prios[priority];
13a43765
MB		 4050 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB)
4051 prio = &dev->flow_db->fdb;
d8abe884
MZ		 4052 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_RDMA_RX)
4053 prio = &dev->flow_db->rdma_rx[priority];
13a43765
MB		 4054
4055 if (!prio)
4056 return ERR_PTR(-EINVAL);
d4be3f44
YH		 4057
4058 if (prio->flow_table)
4059 return prio;
4060
3b70508a 4061 return _get_prio(ns, prio, priority, max_table_size,
b47fd4ff 4062 MLX5_FS_MAX_TYPES, flags);
d4be3f44
YH		 4063}
4064
4065static struct mlx5_ib_flow_handler *
4066_create_raw_flow_rule(struct mlx5_ib_dev *dev,
4067 struct mlx5_ib_flow_prio *ft_prio,
4068 struct mlx5_flow_destination *dst,
4069 struct mlx5_ib_flow_matcher *fs_matcher,
bb0ee7dc 4070 struct mlx5_flow_context *flow_context,
b823dd6d 4071 struct mlx5_flow_act *flow_act,
bfc5d839
MB		 4072 void *cmd_in, int inlen,
4073 int dst_num)
d4be3f44
YH		 4074{
4075 struct mlx5_ib_flow_handler *handler;
d4be3f44
YH		 4076 struct mlx5_flow_spec *spec;
4077 struct mlx5_flow_table *ft = ft_prio->flow_table;
4078 int err = 0;
4079
4080 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
4081 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
4082 if (!handler || !spec) {
4083 err = -ENOMEM;
4084 goto free;
4085 }
4086
4087 INIT_LIST_HEAD(&handler->list);
4088
4089 memcpy(spec->match_value, cmd_in, inlen);
4090 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params,
4091 fs_matcher->mask_len);
4092 spec->match_criteria_enable = fs_matcher->match_criteria_enable;
bb0ee7dc 4093 spec->flow_context = *flow_context;
d4be3f44 4094
d4be3f44 4095 handler->rule = mlx5_add_flow_rules(ft, spec,
bfc5d839 4096 flow_act, dst, dst_num);
d4be3f44
YH		 4097
4098 if (IS_ERR(handler->rule)) {
4099 err = PTR_ERR(handler->rule);
4100 goto free;
4101 }
4102
4103 ft_prio->refcount++;
4104 handler->prio = ft_prio;
4105 handler->dev = dev;
4106 ft_prio->flow_table = ft;
4107
4108free:
4109 if (err)
4110 kfree(handler);
4111 kvfree(spec);
4112 return err ? ERR_PTR(err) : handler;
4113}
4114
4115static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher,
4116 void *match_v)
4117{
4118 void *match_c;
4119 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4;
4120 void *dmac, *dmac_mask;
4121 void *ipv4, *ipv4_mask;
4122
4123 if (!(fs_matcher->match_criteria_enable &
4124 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT)))
4125 return false;
4126
4127 match_c = fs_matcher->matcher_mask.match_params;
4128 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v,
4129 outer_headers);
4130 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c,
4131 outer_headers);
4132
4133 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4134 dmac_47_16);
4135 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4136 dmac_47_16);
4137
4138 if (is_multicast_ether_addr(dmac) &&
4139 is_multicast_ether_addr(dmac_mask))
4140 return true;
4141
4142 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4143 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4144
4145 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4146 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4147
4148 if (ipv4_is_multicast(*(__be32 *)(ipv4)) &&
4149 ipv4_is_multicast(*(__be32 *)(ipv4_mask)))
4150 return true;
4151
4152 return false;
4153}
4154
32269441
YH		 4155struct mlx5_ib_flow_handler *
4156mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
4157 struct mlx5_ib_flow_matcher *fs_matcher,
bb0ee7dc 4158 struct mlx5_flow_context *flow_context,
b823dd6d 4159 struct mlx5_flow_act *flow_act,
bfc5d839 4160 u32 counter_id,
32269441
YH		 4161 void *cmd_in, int inlen, int dest_id,
4162 int dest_type)
4163{
d4be3f44
YH		 4164 struct mlx5_flow_destination *dst;
4165 struct mlx5_ib_flow_prio *ft_prio;
d4be3f44 4166 struct mlx5_ib_flow_handler *handler;
bfc5d839 4167 int dst_num = 0;
d4be3f44
YH		 4168 bool mcast;
4169 int err;
4170
4171 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL)
4172 return ERR_PTR(-EOPNOTSUPP);
4173
4174 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO)
4175 return ERR_PTR(-ENOMEM);
4176
8e8aa145 4177 dst = kcalloc(2, sizeof(*dst), GFP_KERNEL);
d4be3f44
YH		 4178 if (!dst)
4179 return ERR_PTR(-ENOMEM);
4180
4181 mcast = raw_fs_is_multicast(fs_matcher, cmd_in);
4182 mutex_lock(&dev->flow_db->lock);
4183
b47fd4ff 4184 ft_prio = _get_flow_table(dev, fs_matcher, mcast);
d4be3f44
YH		 4185 if (IS_ERR(ft_prio)) {
4186 err = PTR_ERR(ft_prio);
4187 goto unlock;
4188 }
4189
6346f0bf 4190 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
bfc5d839
MB		 4191 dst[dst_num].type = dest_type;
4192 dst[dst_num].tir_num = dest_id;
b823dd6d 4193 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
a7ee18bd 4194 } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) {
bfc5d839
MB		 4195 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
4196 dst[dst_num].ft_num = dest_id;
b823dd6d 4197 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
a7ee18bd 4198 } else {
bfc5d839 4199 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_PORT;
a7ee18bd 4200 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
6346f0bf
YH		 4201 }
4202
bfc5d839
MB		 4203 dst_num++;
4204
4205 if (flow_act->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
4206 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
4207 dst[dst_num].counter_id = counter_id;
4208 dst_num++;
4209 }
4210
bb0ee7dc
JL		 4211 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher,
4212 flow_context, flow_act,
bfc5d839 4213 cmd_in, inlen, dst_num);
d4be3f44
YH		 4214
4215 if (IS_ERR(handler)) {
4216 err = PTR_ERR(handler);
4217 goto destroy_ft;
4218 }
4219
4220 mutex_unlock(&dev->flow_db->lock);
4221 atomic_inc(&fs_matcher->usecnt);
4222 handler->flow_matcher = fs_matcher;
4223
4224 kfree(dst);
4225
4226 return handler;
4227
4228destroy_ft:
4229 put_flow_table(dev, ft_prio, false);
4230unlock:
4231 mutex_unlock(&dev->flow_db->lock);
4232 kfree(dst);
4233
4234 return ERR_PTR(err);
32269441
YH		 4235}
4236
c6475a0b
AY		 4237static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
4238{
4239 u32 flags = 0;
4240
4241 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
4242 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
4243
4244 return flags;
4245}
4246
4247#define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
4248static struct ib_flow_action *
4249mlx5_ib_create_flow_action_esp(struct ib_device *device,
4250 const struct ib_flow_action_attrs_esp *attr,
4251 struct uverbs_attr_bundle *attrs)
4252{
4253 struct mlx5_ib_dev *mdev = to_mdev(device);
4254 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
4255 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
4256 struct mlx5_ib_flow_action *action;
4257 u64 action_flags;
4258 u64 flags;
4259 int err = 0;
4260
bccd0622
JG		 4261 err = uverbs_get_flags64(
4262 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
4263 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1));
4264 if (err)
4265 return ERR_PTR(err);
c6475a0b
AY		 4266
4267 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
4268
4269 /* We current only support a subset of the standard features. Only a
4270 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
4271 * (with overlap). Full offload mode isn't supported.
4272 */
4273 if (!attr->keymat || attr->replay || attr->encap ||
4274 attr->spi || attr->seq || attr->tfc_pad ||
4275 attr->hard_limit_pkts ||
4276 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4277 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
4278 return ERR_PTR(-EOPNOTSUPP);
4279
4280 if (attr->keymat->protocol !=
4281 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
4282 return ERR_PTR(-EOPNOTSUPP);
4283
4284 aes_gcm = &attr->keymat->keymat.aes_gcm;
4285
4286 if (aes_gcm->icv_len != 16 ||
4287 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
4288 return ERR_PTR(-EOPNOTSUPP);
4289
4290 action = kmalloc(sizeof(*action), GFP_KERNEL);
4291 if (!action)
4292 return ERR_PTR(-ENOMEM);
4293
4294 action->esp_aes_gcm.ib_flags = attr->flags;
4295 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
4296 sizeof(accel_attrs.keymat.aes_gcm.aes_key));
4297 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
4298 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
4299 sizeof(accel_attrs.keymat.aes_gcm.salt));
4300 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
4301 sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
4302 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
4303 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
4304 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
4305
4306 accel_attrs.esn = attr->esn;
4307 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
4308 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
4309 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4310 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4311
4312 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
4313 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
4314
4315 action->esp_aes_gcm.ctx =
4316 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
4317 if (IS_ERR(action->esp_aes_gcm.ctx)) {
4318 err = PTR_ERR(action->esp_aes_gcm.ctx);
4319 goto err_parse;
4320 }
4321
4322 action->esp_aes_gcm.ib_flags = attr->flags;
4323
4324 return &action->ib_action;
4325
4326err_parse:
4327 kfree(action);
4328 return ERR_PTR(err);
4329}
4330
349705c1
MB		 4331static int
4332mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
4333 const struct ib_flow_action_attrs_esp *attr,
4334 struct uverbs_attr_bundle *attrs)
4335{
4336 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4337 struct mlx5_accel_esp_xfrm_attrs accel_attrs;
4338 int err = 0;
4339
4340 if (attr->keymat || attr->replay || attr->encap ||
4341 attr->spi || attr->seq || attr->tfc_pad ||
4342 attr->hard_limit_pkts ||
4343 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4344 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
4345 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
4346 return -EOPNOTSUPP;
4347
4348 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
4349 * be modified.
4350 */
4351 if (!(maction->esp_aes_gcm.ib_flags &
4352 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
4353 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4354 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
4355 return -EINVAL;
4356
4357 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
4358 sizeof(accel_attrs));
4359
4360 accel_attrs.esn = attr->esn;
4361 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4362 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4363 else
4364 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4365
4366 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
4367 &accel_attrs);
4368 if (err)
4369 return err;
4370
4371 maction->esp_aes_gcm.ib_flags &=
4372 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4373 maction->esp_aes_gcm.ib_flags |=
4374 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4375
4376 return 0;
4377}
4378
c6475a0b
AY		 4379static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
4380{
4381 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4382
4383 switch (action->type) {
4384 case IB_FLOW_ACTION_ESP:
4385 /*
4386 * We only support aes_gcm by now, so we implicitly know this is
4387 * the underline crypto.
4388 */
4389 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
4390 break;
b4749bf2
MB		 4391 case IB_FLOW_ACTION_UNSPECIFIED:
4392 mlx5_ib_destroy_flow_action_raw(maction);
4393 break;
c6475a0b
AY		 4394 default:
4395 WARN_ON(true);
4396 break;
4397 }
4398
4399 kfree(maction);
4400 return 0;
4401}
4402
e126ba97
EC		 4403static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4404{
4405 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 4406 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97 4407 int err;
539ec982
YH		 4408 u16 uid;
4409
4410 uid = ibqp->pd ?
4411 to_mpd(ibqp->pd)->uid : 0;
e126ba97 4412
81e30880
YH		 4413 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
4414 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
4415 return -EOPNOTSUPP;
4416 }
4417
539ec982 4418 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
e126ba97
EC		 4419 if (err)
4420 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
4421 ibqp->qp_num, gid->raw);
4422
4423 return err;
4424}
4425
4426static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4427{
4428 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4429 int err;
539ec982 4430 u16 uid;
e126ba97 4431
539ec982
YH		 4432 uid = ibqp->pd ?
4433 to_mpd(ibqp->pd)->uid : 0;
4434 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
e126ba97
EC		 4435 if (err)
4436 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
4437 ibqp->qp_num, gid->raw);
4438
4439 return err;
4440}
4441
4442static int init_node_data(struct mlx5_ib_dev *dev)
4443{
1b5daf11 4444 int err;
e126ba97 4445
1b5daf11 4446 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 4447 if (err)
1b5daf11 4448 return err;
e126ba97 4449
1b5daf11 4450 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 4451
1b5daf11 4452 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 4453}
4454
508a523f
PP		 4455static ssize_t fw_pages_show(struct device *device,
4456 struct device_attribute *attr, char *buf)
e126ba97
EC		 4457{
4458 struct mlx5_ib_dev *dev =
54747231 4459 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
e126ba97 4460
9603b61d 4461 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97 4462}
508a523f 4463static DEVICE_ATTR_RO(fw_pages);
e126ba97 4464
508a523f 4465static ssize_t reg_pages_show(struct device *device,
e126ba97
EC		 4466 struct device_attribute *attr, char *buf)
4467{
4468 struct mlx5_ib_dev *dev =
54747231 4469 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
e126ba97 4470
6aec21f6 4471 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97 4472}
508a523f 4473static DEVICE_ATTR_RO(reg_pages);
e126ba97 4474
508a523f
PP		 4475static ssize_t hca_type_show(struct device *device,
4476 struct device_attribute *attr, char *buf)
e126ba97
EC		 4477{
4478 struct mlx5_ib_dev *dev =
54747231
PP		 4479 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4480
9603b61d 4481 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97 4482}
508a523f 4483static DEVICE_ATTR_RO(hca_type);
e126ba97 4484
508a523f
PP		 4485static ssize_t hw_rev_show(struct device *device,
4486 struct device_attribute *attr, char *buf)
e126ba97
EC		 4487{
4488 struct mlx5_ib_dev *dev =
54747231
PP		 4489 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4490
9603b61d 4491 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97 4492}
508a523f 4493static DEVICE_ATTR_RO(hw_rev);
e126ba97 4494
508a523f
PP		 4495static ssize_t board_id_show(struct device *device,
4496 struct device_attribute *attr, char *buf)
e126ba97
EC		 4497{
4498 struct mlx5_ib_dev *dev =
54747231
PP		 4499 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4500
e126ba97 4501 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 4502 dev->mdev->board_id);
e126ba97 4503}
508a523f 4504static DEVICE_ATTR_RO(board_id);
e126ba97 4505
508a523f
PP		 4506static struct attribute *mlx5_class_attributes[] = {
4507 &dev_attr_hw_rev.attr,
4508 &dev_attr_hca_type.attr,
4509 &dev_attr_board_id.attr,
4510 &dev_attr_fw_pages.attr,
4511 &dev_attr_reg_pages.attr,
4512 NULL,
4513};
e126ba97 4514
508a523f
PP		 4515static const struct attribute_group mlx5_attr_group = {
4516 .attrs = mlx5_class_attributes,
e126ba97
EC		 4517};
4518
7722f47e
HE		 4519static void pkey_change_handler(struct work_struct *work)
4520{
4521 struct mlx5_ib_port_resources *ports =
4522 container_of(work, struct mlx5_ib_port_resources,
4523 pkey_change_work);
4524
4525 mutex_lock(&ports->devr->mutex);
4526 mlx5_ib_gsi_pkey_change(ports->gsi);
4527 mutex_unlock(&ports->devr->mutex);
4528}
4529
89ea94a7
MG		 4530static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
4531{
4532 struct mlx5_ib_qp *mqp;
4533 struct mlx5_ib_cq *send_mcq, *recv_mcq;
4534 struct mlx5_core_cq *mcq;
4535 struct list_head cq_armed_list;
4536 unsigned long flags_qp;
4537 unsigned long flags_cq;
4538 unsigned long flags;
4539
4540 INIT_LIST_HEAD(&cq_armed_list);
4541
4542 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
4543 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
4544 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
4545 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
4546 if (mqp->sq.tail != mqp->sq.head) {
4547 send_mcq = to_mcq(mqp->ibqp.send_cq);
4548 spin_lock_irqsave(&send_mcq->lock, flags_cq);
4549 if (send_mcq->mcq.comp &&
4550 mqp->ibqp.send_cq->comp_handler) {
4551 if (!send_mcq->mcq.reset_notify_added) {
4552 send_mcq->mcq.reset_notify_added = 1;
4553 list_add_tail(&send_mcq->mcq.reset_notify,
4554 &cq_armed_list);
4555 }
4556 }
4557 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
4558 }
4559 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
4560 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
4561 /* no handling is needed for SRQ */
4562 if (!mqp->ibqp.srq) {
4563 if (mqp->rq.tail != mqp->rq.head) {
4564 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
4565 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
4566 if (recv_mcq->mcq.comp &&
4567 mqp->ibqp.recv_cq->comp_handler) {
4568 if (!recv_mcq->mcq.reset_notify_added) {
4569 recv_mcq->mcq.reset_notify_added = 1;
4570 list_add_tail(&recv_mcq->mcq.reset_notify,
4571 &cq_armed_list);
4572 }
4573 }
4574 spin_unlock_irqrestore(&recv_mcq->lock,
4575 flags_cq);
4576 }
4577 }
4578 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
4579 }
4580 /*At that point all inflight post send were put to be executed as of we
4581 * lock/unlock above locks Now need to arm all involved CQs.
4582 */
4583 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4e0e2ea1 4584 mcq->comp(mcq, NULL);
89ea94a7
MG		 4585 }
4586 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
4587}
4588
03404e8a
MG		 4589static void delay_drop_handler(struct work_struct *work)
4590{
4591 int err;
4592 struct mlx5_ib_delay_drop *delay_drop =
4593 container_of(work, struct mlx5_ib_delay_drop,
4594 delay_drop_work);
4595
fe248c3a
MG		 4596 atomic_inc(&delay_drop->events_cnt);
4597
03404e8a
MG		 4598 mutex_lock(&delay_drop->lock);
4599 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
4600 delay_drop->timeout);
4601 if (err) {
4602 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4603 delay_drop->timeout);
4604 delay_drop->activate = false;
4605 }
4606 mutex_unlock(&delay_drop->lock);
4607}
4608
09e574fa
SM		 4609static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4610 struct ib_event *ibev)
4611{
6cfdc7e4
AL		 4612 u8 port = (eqe->data.port.port >> 4) & 0xf;
4613
09e574fa
SM		 4614 switch (eqe->sub_type) {
4615 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
6cfdc7e4
AL		 4616 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4617 IB_LINK_LAYER_ETHERNET)
4618 schedule_work(&ibdev->delay_drop.delay_drop_work);
09e574fa
SM		 4619 break;
4620 default: /* do nothing */
4621 return;
4622 }
4623}
4624
134e9349
SM		 4625static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4626 struct ib_event *ibev)
4627{
4628 u8 port = (eqe->data.port.port >> 4) & 0xf;
4629
4630 ibev->element.port_num = port;
4631
4632 switch (eqe->sub_type) {
4633 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
4634 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
4635 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
4636 /* In RoCE, port up/down events are handled in
4637 * mlx5_netdev_event().
4638 */
4639 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4640 IB_LINK_LAYER_ETHERNET)
4641 return -EINVAL;
4642
4643 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
4644 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
4645 break;
4646
4647 case MLX5_PORT_CHANGE_SUBTYPE_LID:
4648 ibev->event = IB_EVENT_LID_CHANGE;
4649 break;
4650
4651 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
4652 ibev->event = IB_EVENT_PKEY_CHANGE;
4653 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
4654 break;
4655
4656 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
4657 ibev->event = IB_EVENT_GID_CHANGE;
4658 break;
4659
4660 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
4661 ibev->event = IB_EVENT_CLIENT_REREGISTER;
4662 break;
4663 default:
4664 return -EINVAL;
4665 }
4666
4667 return 0;
4668}
4669
d69a24e0 4670static void mlx5_ib_handle_event(struct work_struct *_work)
e126ba97 4671{
d69a24e0
DJ		 4672 struct mlx5_ib_event_work *work =
4673 container_of(_work, struct mlx5_ib_event_work, work);
4674 struct mlx5_ib_dev *ibdev;
e126ba97 4675 struct ib_event ibev;
dbaaff2a 4676 bool fatal = false;
e126ba97 4677
df097a27
SM		 4678 if (work->is_slave) {
4679 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
d69a24e0
DJ		 4680 if (!ibdev)
4681 goto out;
4682 } else {
df097a27 4683 ibdev = work->dev;
d69a24e0
DJ		 4684 }
4685
4686 switch (work->event) {
e126ba97 4687 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 4688 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 4689 mlx5_ib_handle_internal_error(ibdev);
134e9349 4690 ibev.element.port_num = (u8)(unsigned long)work->param;
dbaaff2a 4691 fatal = true;
e126ba97 4692 break;
134e9349
SM		 4693 case MLX5_EVENT_TYPE_PORT_CHANGE:
4694 if (handle_port_change(ibdev, work->param, &ibev))
d69a24e0 4695 goto out;
e126ba97 4696 break;
09e574fa
SM		 4697 case MLX5_EVENT_TYPE_GENERAL_EVENT:
4698 handle_general_event(ibdev, work->param, &ibev);
4699 /* fall through */
bdc37924 4700 default:
03404e8a 4701 goto out;
e126ba97
EC		 4702 }
4703
134e9349 4704 ibev.device = &ibdev->ib_dev;
e126ba97 4705
134e9349
SM		 4706 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
4707 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num);
03404e8a 4708 goto out;
a0c84c32
EC		 4709 }
4710
e126ba97
EC		 4711 if (ibdev->ib_active)
4712 ib_dispatch_event(&ibev);
dbaaff2a
EC		 4713
4714 if (fatal)
4715 ibdev->ib_active = false;
03404e8a 4716out:
d69a24e0
DJ		 4717 kfree(work);
4718}
4719
df097a27
SM		 4720static int mlx5_ib_event(struct notifier_block *nb,
4721 unsigned long event, void *param)
d69a24e0
DJ		 4722{
4723 struct mlx5_ib_event_work *work;
4724
4725 work = kmalloc(sizeof(*work), GFP_ATOMIC);
10bea9c8 4726 if (!work)
df097a27 4727 return NOTIFY_DONE;
d69a24e0 4728
10bea9c8 4729 INIT_WORK(&work->work, mlx5_ib_handle_event);
df097a27
SM		 4730 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
4731 work->is_slave = false;
10bea9c8 4732 work->param = param;
10bea9c8
LR		 4733 work->event = event;
4734
4735 queue_work(mlx5_ib_event_wq, &work->work);
df097a27
SM		 4736
4737 return NOTIFY_OK;
4738}
4739
4740static int mlx5_ib_event_slave_port(struct notifier_block *nb,
4741 unsigned long event, void *param)
4742{
4743 struct mlx5_ib_event_work *work;
4744
4745 work = kmalloc(sizeof(*work), GFP_ATOMIC);
4746 if (!work)
4747 return NOTIFY_DONE;
4748
4749 INIT_WORK(&work->work, mlx5_ib_handle_event);
4750 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
4751 work->is_slave = true;
4752 work->param = param;
4753 work->event = event;
4754 queue_work(mlx5_ib_event_wq, &work->work);
4755
4756 return NOTIFY_OK;
e126ba97
EC		 4757}
4758
c43f1112
MG		 4759static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4760{
4761 struct mlx5_hca_vport_context vport_ctx;
4762 int err;
4763 int port;
4764
a989ea01 4765 for (port = 1; port <= ARRAY_SIZE(dev->mdev->port_caps); port++) {
c43f1112
MG		 4766 dev->mdev->port_caps[port - 1].has_smi = false;
4767 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4768 MLX5_CAP_PORT_TYPE_IB) {
4769 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4770 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4771 port, 0,
4772 &vport_ctx);
4773 if (err) {
4774 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4775 port, err);
4776 return err;
4777 }
4778 dev->mdev->port_caps[port - 1].has_smi =
4779 vport_ctx.has_smi;
4780 } else {
4781 dev->mdev->port_caps[port - 1].has_smi = true;
4782 }
4783 }
4784 }
4785 return 0;
4786}
4787
e126ba97
EC		 4788static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4789{
4790 int port;
4791
508562d6 4792 for (port = 1; port <= dev->num_ports; port++)
e126ba97
EC		 4793 mlx5_query_ext_port_caps(dev, port);
4794}
4795
26628e2d 4796static int __get_port_caps(struct mlx5_ib_dev *dev, u8 port)
e126ba97
EC		 4797{
4798 struct ib_device_attr *dprops = NULL;
4799 struct ib_port_attr *pprops = NULL;
f614fc15 4800 int err = -ENOMEM;
e126ba97 4801
50ba3c18 4802 pprops = kzalloc(sizeof(*pprops), GFP_KERNEL);
e126ba97
EC		 4803 if (!pprops)
4804 goto out;
4805
4806 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4807 if (!dprops)
4808 goto out;
4809
48357091 4810 err = mlx5_ib_query_device(&dev->ib_dev, dprops, NULL);
e126ba97
EC		 4811 if (err) {
4812 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4813 goto out;
4814 }
4815
32f69e4b
DJ		 4816 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4817 if (err) {
4818 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4819 port, err);
4820 goto out;
e126ba97
EC		 4821 }
4822
32f69e4b
DJ		 4823 dev->mdev->port_caps[port - 1].pkey_table_len =
4824 dprops->max_pkeys;
4825 dev->mdev->port_caps[port - 1].gid_table_len =
4826 pprops->gid_tbl_len;
4827 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4828 port, dprops->max_pkeys, pprops->gid_tbl_len);
4829
e126ba97
EC		 4830out:
4831 kfree(pprops);
4832 kfree(dprops);
4833
4834 return err;
4835}
4836
26628e2d
MB		 4837static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4838{
4839 /* For representors use port 1, is this is the only native
4840 * port
4841 */
4842 if (dev->is_rep)
4843 return __get_port_caps(dev, 1);
4844 return __get_port_caps(dev, port);
4845}
4846
e126ba97
EC		 4847static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4848{
4849 int err;
4850
4851 err = mlx5_mr_cache_cleanup(dev);
4852 if (err)
4853 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4854
32927e28 4855 if (dev->umrc.qp)
c4367a26 4856 mlx5_ib_destroy_qp(dev->umrc.qp, NULL);
32927e28
MB		 4857 if (dev->umrc.cq)
4858 ib_free_cq(dev->umrc.cq);
4859 if (dev->umrc.pd)
4860 ib_dealloc_pd(dev->umrc.pd);
e126ba97
EC		 4861}
4862
4863enum {
4864 MAX_UMR_WR = 128,
4865};
4866
4867static int create_umr_res(struct mlx5_ib_dev *dev)
4868{
4869 struct ib_qp_init_attr *init_attr = NULL;
4870 struct ib_qp_attr *attr = NULL;
4871 struct ib_pd *pd;
4872 struct ib_cq *cq;
4873 struct ib_qp *qp;
e126ba97
EC		 4874 int ret;
4875
4876 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4877 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4878 if (!attr || !init_attr) {
4879 ret = -ENOMEM;
4880 goto error_0;
4881 }
4882
ed082d36 4883 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 4884 if (IS_ERR(pd)) {
4885 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4886 ret = PTR_ERR(pd);
4887 goto error_0;
4888 }
4889
add08d76 4890 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 4891 if (IS_ERR(cq)) {
4892 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4893 ret = PTR_ERR(cq);
4894 goto error_2;
4895 }
e126ba97
EC		 4896
4897 init_attr->send_cq = cq;
4898 init_attr->recv_cq = cq;
4899 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4900 init_attr->cap.max_send_wr = MAX_UMR_WR;
4901 init_attr->cap.max_send_sge = 1;
4902 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4903 init_attr->port_num = 1;
4904 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4905 if (IS_ERR(qp)) {
4906 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4907 ret = PTR_ERR(qp);
4908 goto error_3;
4909 }
4910 qp->device = &dev->ib_dev;
4911 qp->real_qp = qp;
4912 qp->uobject = NULL;
4913 qp->qp_type = MLX5_IB_QPT_REG_UMR;
31fde034
MD		 4914 qp->send_cq = init_attr->send_cq;
4915 qp->recv_cq = init_attr->recv_cq;
e126ba97
EC		 4916
4917 attr->qp_state = IB_QPS_INIT;
4918 attr->port_num = 1;
4919 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4920 IB_QP_PORT, NULL);
4921 if (ret) {
4922 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4923 goto error_4;
4924 }
4925
4926 memset(attr, 0, sizeof(*attr));
4927 attr->qp_state = IB_QPS_RTR;
4928 attr->path_mtu = IB_MTU_256;
4929
4930 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4931 if (ret) {
4932 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4933 goto error_4;
4934 }
4935
4936 memset(attr, 0, sizeof(*attr));
4937 attr->qp_state = IB_QPS_RTS;
4938 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4939 if (ret) {
4940 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4941 goto error_4;
4942 }
4943
4944 dev->umrc.qp = qp;
4945 dev->umrc.cq = cq;
e126ba97
EC		 4946 dev->umrc.pd = pd;
4947
4948 sema_init(&dev->umrc.sem, MAX_UMR_WR);
4949 ret = mlx5_mr_cache_init(dev);
4950 if (ret) {
4951 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4952 goto error_4;
4953 }
4954
4955 kfree(attr);
4956 kfree(init_attr);
4957
4958 return 0;
4959
4960error_4:
c4367a26 4961 mlx5_ib_destroy_qp(qp, NULL);
32927e28 4962 dev->umrc.qp = NULL;
e126ba97
EC		 4963
4964error_3:
add08d76 4965 ib_free_cq(cq);
32927e28 4966 dev->umrc.cq = NULL;
e126ba97
EC		 4967
4968error_2:
e126ba97 4969 ib_dealloc_pd(pd);
32927e28 4970 dev->umrc.pd = NULL;
e126ba97
EC		 4971
4972error_0:
4973 kfree(attr);
4974 kfree(init_attr);
4975 return ret;
4976}
4977
6e8484c5
MG		 4978static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4979{
4980 switch (umr_fence_cap) {
4981 case MLX5_CAP_UMR_FENCE_NONE:
4982 return MLX5_FENCE_MODE_NONE;
4983 case MLX5_CAP_UMR_FENCE_SMALL:
4984 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4985 default:
4986 return MLX5_FENCE_MODE_STRONG_ORDERING;
4987 }
4988}
4989
e126ba97
EC		 4990static int create_dev_resources(struct mlx5_ib_resources *devr)
4991{
4992 struct ib_srq_init_attr attr;
4993 struct mlx5_ib_dev *dev;
21a428a0 4994 struct ib_device *ibdev;
bcf4c1ea 4995 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 4996 int port;
e126ba97
EC		 4997 int ret = 0;
4998
4999 dev = container_of(devr, struct mlx5_ib_dev, devr);
21a428a0 5000 ibdev = &dev->ib_dev;
e126ba97 5001
d16e91da
HE		 5002 mutex_init(&devr->mutex);
5003
21a428a0
LR		 5004 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd);
5005 if (!devr->p0)
5006 return -ENOMEM;
5007
5008 devr->p0->device = ibdev;
e126ba97
EC		 5009 devr->p0->uobject = NULL;
5010 atomic_set(&devr->p0->usecnt, 0);
5011
ff23dfa1 5012 ret = mlx5_ib_alloc_pd(devr->p0, NULL);
21a428a0
LR		 5013 if (ret)
5014 goto error0;
5015
e39afe3d
LR		 5016 devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq);
5017 if (!devr->c0) {
5018 ret = -ENOMEM;
e126ba97
EC		 5019 goto error1;
5020 }
e39afe3d
LR		 5021
5022 devr->c0->device = &dev->ib_dev;
e126ba97
EC		 5023 atomic_set(&devr->c0->usecnt, 0);
5024
e39afe3d
LR		 5025 ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL);
5026 if (ret)
5027 goto err_create_cq;
5028
ff23dfa1 5029 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
e126ba97
EC		 5030 if (IS_ERR(devr->x0)) {
5031 ret = PTR_ERR(devr->x0);
5032 goto error2;
5033 }
5034 devr->x0->device = &dev->ib_dev;
5035 devr->x0->inode = NULL;
5036 atomic_set(&devr->x0->usecnt, 0);
5037 mutex_init(&devr->x0->tgt_qp_mutex);
5038 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
5039
ff23dfa1 5040 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
e126ba97
EC		 5041 if (IS_ERR(devr->x1)) {
5042 ret = PTR_ERR(devr->x1);
5043 goto error3;
5044 }
5045 devr->x1->device = &dev->ib_dev;
5046 devr->x1->inode = NULL;
5047 atomic_set(&devr->x1->usecnt, 0);
5048 mutex_init(&devr->x1->tgt_qp_mutex);
5049 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
5050
5051 memset(&attr, 0, sizeof(attr));
5052 attr.attr.max_sge = 1;
5053 attr.attr.max_wr = 1;
5054 attr.srq_type = IB_SRQT_XRC;
1a56ff6d 5055 attr.ext.cq = devr->c0;
e126ba97
EC		 5056 attr.ext.xrc.xrcd = devr->x0;
5057
68e326de
LR		 5058 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq);
5059 if (!devr->s0) {
5060 ret = -ENOMEM;
e126ba97
EC		 5061 goto error4;
5062 }
68e326de 5063
e126ba97
EC		 5064 devr->s0->device = &dev->ib_dev;
5065 devr->s0->pd = devr->p0;
e126ba97
EC		 5066 devr->s0->srq_type = IB_SRQT_XRC;
5067 devr->s0->ext.xrc.xrcd = devr->x0;
1a56ff6d 5068 devr->s0->ext.cq = devr->c0;
68e326de
LR		 5069 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL);
5070 if (ret)
5071 goto err_create;
5072
e126ba97 5073 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1a56ff6d 5074 atomic_inc(&devr->s0->ext.cq->usecnt);
e126ba97
EC		 5075 atomic_inc(&devr->p0->usecnt);
5076 atomic_set(&devr->s0->usecnt, 0);
5077
4aa17b28
HA		 5078 memset(&attr, 0, sizeof(attr));
5079 attr.attr.max_sge = 1;
5080 attr.attr.max_wr = 1;
5081 attr.srq_type = IB_SRQT_BASIC;
68e326de
LR		 5082 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq);
5083 if (!devr->s1) {
5084 ret = -ENOMEM;
4aa17b28
HA		 5085 goto error5;
5086 }
68e326de 5087
4aa17b28
HA		 5088 devr->s1->device = &dev->ib_dev;
5089 devr->s1->pd = devr->p0;
4aa17b28 5090 devr->s1->srq_type = IB_SRQT_BASIC;
1a56ff6d 5091 devr->s1->ext.cq = devr->c0;
68e326de
LR		 5092
5093 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL);
5094 if (ret)
5095 goto error6;
5096
4aa17b28 5097 atomic_inc(&devr->p0->usecnt);
1a56ff6d 5098 atomic_set(&devr->s1->usecnt, 0);
4aa17b28 5099
7722f47e
HE		 5100 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
5101 INIT_WORK(&devr->ports[port].pkey_change_work,
5102 pkey_change_handler);
5103 devr->ports[port].devr = devr;
5104 }
5105
e126ba97
EC		 5106 return 0;
5107
68e326de
LR		 5108error6:
5109 kfree(devr->s1);
4aa17b28 5110error5:
c4367a26 5111 mlx5_ib_destroy_srq(devr->s0, NULL);
68e326de
LR		 5112err_create:
5113 kfree(devr->s0);
e126ba97 5114error4:
c4367a26 5115 mlx5_ib_dealloc_xrcd(devr->x1, NULL);
e126ba97 5116error3:
c4367a26 5117 mlx5_ib_dealloc_xrcd(devr->x0, NULL);
e126ba97 5118error2:
c4367a26 5119 mlx5_ib_destroy_cq(devr->c0, NULL);
e39afe3d
LR		 5120err_create_cq:
5121 kfree(devr->c0);
e126ba97 5122error1:
c4367a26 5123 mlx5_ib_dealloc_pd(devr->p0, NULL);
e126ba97 5124error0:
21a428a0 5125 kfree(devr->p0);
e126ba97
EC		 5126 return ret;
5127}
5128
5129static void destroy_dev_resources(struct mlx5_ib_resources *devr)
5130{
7722f47e
HE		 5131 int port;
5132
c4367a26 5133 mlx5_ib_destroy_srq(devr->s1, NULL);
68e326de 5134 kfree(devr->s1);
c4367a26 5135 mlx5_ib_destroy_srq(devr->s0, NULL);
68e326de 5136 kfree(devr->s0);
c4367a26
SR		 5137 mlx5_ib_dealloc_xrcd(devr->x0, NULL);
5138 mlx5_ib_dealloc_xrcd(devr->x1, NULL);
5139 mlx5_ib_destroy_cq(devr->c0, NULL);
e39afe3d 5140 kfree(devr->c0);
c4367a26 5141 mlx5_ib_dealloc_pd(devr->p0, NULL);
21a428a0 5142 kfree(devr->p0);
7722f47e
HE		 5143
5144 /* Make sure no change P_Key work items are still executing */
5d8f6a0e 5145 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
7722f47e 5146 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 5147}
5148
b02289b3
AK		 5149static u32 get_core_cap_flags(struct ib_device *ibdev,
5150 struct mlx5_hca_vport_context *rep)
e53505a8
AS		 5151{
5152 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5153 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
5154 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
5155 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
85c7c014 5156 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
e53505a8
AS		 5157 u32 ret = 0;
5158
b02289b3
AK		 5159 if (rep->grh_required)
5160 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
5161
e53505a8 5162 if (ll == IB_LINK_LAYER_INFINIBAND)
b02289b3 5163 return ret | RDMA_CORE_PORT_IBA_IB;
e53505a8 5164
85c7c014 5165 if (raw_support)
b02289b3 5166 ret |= RDMA_CORE_PORT_RAW_PACKET;
72cd5717 5167
e53505a8 5168 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 5169 return ret;
e53505a8
AS		 5170
5171 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 5172 return ret;
e53505a8
AS		 5173
5174 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
5175 ret |= RDMA_CORE_PORT_IBA_ROCE;
5176
5177 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
5178 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
5179
5180 return ret;
5181}
5182
7738613e
IW		 5183static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
5184 struct ib_port_immutable *immutable)
5185{
5186 struct ib_port_attr attr;
ca5b91d6
OG		 5187 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5188 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
b02289b3 5189 struct mlx5_hca_vport_context rep = {0};
7738613e
IW		 5190 int err;
5191
c4550c63 5192 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 5193 if (err)
5194 return err;
5195
b02289b3
AK		 5196 if (ll == IB_LINK_LAYER_INFINIBAND) {
5197 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
5198 &rep);
5199 if (err)
5200 return err;
5201 }
5202
7738613e
IW		 5203 immutable->pkey_tbl_len = attr.pkey_tbl_len;
5204 immutable->gid_tbl_len = attr.gid_tbl_len;
b02289b3 5205 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
94de879c 5206 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 5207
5208 return 0;
5209}
5210
8e6efa3a
MB		 5211static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
5212 struct ib_port_immutable *immutable)
5213{
5214 struct ib_port_attr attr;
5215 int err;
5216
5217 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5218
5219 err = ib_query_port(ibdev, port_num, &attr);
5220 if (err)
5221 return err;
5222
5223 immutable->pkey_tbl_len = attr.pkey_tbl_len;
5224 immutable->gid_tbl_len = attr.gid_tbl_len;
5225 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5226
5227 return 0;
5228}
5229
9abb0d1b 5230static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 5231{
5232 struct mlx5_ib_dev *dev =
5233 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 5234 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
5235 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
5236 fw_rev_sub(dev->mdev));
c7342823
IW		 5237}
5238
45f95acd 5239static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 5240{
5241 struct mlx5_core_dev *mdev = dev->mdev;
5242 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
5243 MLX5_FLOW_NAMESPACE_LAG);
5244 struct mlx5_flow_table *ft;
5245 int err;
5246
7c34ec19 5247 if (!ns || !mlx5_lag_is_roce(mdev))
9ef9c640
AH		 5248 return 0;
5249
5250 err = mlx5_cmd_create_vport_lag(mdev);
5251 if (err)
5252 return err;
5253
5254 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
5255 if (IS_ERR(ft)) {
5256 err = PTR_ERR(ft);
5257 goto err_destroy_vport_lag;
5258 }
5259
9a4ca38d 5260 dev->flow_db->lag_demux_ft = ft;
7c34ec19 5261 dev->lag_active = true;
9ef9c640
AH		 5262 return 0;
5263
5264err_destroy_vport_lag:
5265 mlx5_cmd_destroy_vport_lag(mdev);
5266 return err;
5267}
5268
45f95acd 5269static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 5270{
5271 struct mlx5_core_dev *mdev = dev->mdev;
5272
7c34ec19
AH		 5273 if (dev->lag_active) {
5274 dev->lag_active = false;
5275
9a4ca38d
MB		 5276 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
5277 dev->flow_db->lag_demux_ft = NULL;
9ef9c640
AH		 5278
5279 mlx5_cmd_destroy_vport_lag(mdev);
5280 }
5281}
5282
7fd8aefb 5283static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
d012f5d6
OG		 5284{
5285 int err;
5286
95579e78
MB		 5287 dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event;
5288 err = register_netdevice_notifier(&dev->port[port_num].roce.nb);
d012f5d6 5289 if (err) {
95579e78 5290 dev->port[port_num].roce.nb.notifier_call = NULL;
d012f5d6
OG		 5291 return err;
5292 }
5293
5294 return 0;
5295}
5296
7fd8aefb 5297static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5ec8c83e 5298{
95579e78
MB		 5299 if (dev->port[port_num].roce.nb.notifier_call) {
5300 unregister_netdevice_notifier(&dev->port[port_num].roce.nb);
5301 dev->port[port_num].roce.nb.notifier_call = NULL;
5ec8c83e
AH		 5302 }
5303}
5304
e3f1ed1f 5305static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 5306{
e53505a8
AS		 5307 int err;
5308
94de879c
MG		 5309 err = mlx5_nic_vport_enable_roce(dev->mdev);
5310 if (err)
5311 return err;
e53505a8 5312
45f95acd 5313 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 5314 if (err)
5315 goto err_disable_roce;
5316
e53505a8
AS		 5317 return 0;
5318
9ef9c640 5319err_disable_roce:
94de879c 5320 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 5321
e53505a8 5322 return err;
fc24fc5e
AS		 5323}
5324
45f95acd 5325static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 5326{
45f95acd 5327 mlx5_eth_lag_cleanup(dev);
94de879c 5328 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 5329}
5330
e1f24a79 5331struct mlx5_ib_counter {
7c16f477
KH		 5332 const char *name;
5333 size_t offset;
5334};
5335
5336#define INIT_Q_COUNTER(_name) \
5337 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
5338
e1f24a79 5339static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 5340 INIT_Q_COUNTER(rx_write_requests),
5341 INIT_Q_COUNTER(rx_read_requests),
5342 INIT_Q_COUNTER(rx_atomic_requests),
5343 INIT_Q_COUNTER(out_of_buffer),
5344};
5345
e1f24a79 5346static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 5347 INIT_Q_COUNTER(out_of_sequence),
5348};
5349
e1f24a79 5350static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 5351 INIT_Q_COUNTER(duplicate_request),
5352 INIT_Q_COUNTER(rnr_nak_retry_err),
5353 INIT_Q_COUNTER(packet_seq_err),
5354 INIT_Q_COUNTER(implied_nak_seq_err),
5355 INIT_Q_COUNTER(local_ack_timeout_err),
5356};
5357
e1f24a79
PP		 5358#define INIT_CONG_COUNTER(_name) \
5359 { .name = #_name, .offset = \
5360 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
5361
5362static const struct mlx5_ib_counter cong_cnts[] = {
5363 INIT_CONG_COUNTER(rp_cnp_ignored),
5364 INIT_CONG_COUNTER(rp_cnp_handled),
5365 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
5366 INIT_CONG_COUNTER(np_cnp_sent),
5367};
5368
58dcb60a
PP		 5369static const struct mlx5_ib_counter extended_err_cnts[] = {
5370 INIT_Q_COUNTER(resp_local_length_error),
5371 INIT_Q_COUNTER(resp_cqe_error),
5372 INIT_Q_COUNTER(req_cqe_error),
5373 INIT_Q_COUNTER(req_remote_invalid_request),
5374 INIT_Q_COUNTER(req_remote_access_errors),
5375 INIT_Q_COUNTER(resp_remote_access_errors),
5376 INIT_Q_COUNTER(resp_cqe_flush_error),
5377 INIT_Q_COUNTER(req_cqe_flush_error),
5378};
5379
d7fab916
AH		 5380static const struct mlx5_ib_counter roce_accl_cnts[] = {
5381 INIT_Q_COUNTER(roce_adp_retrans),
5382 INIT_Q_COUNTER(roce_adp_retrans_to),
5383 INIT_Q_COUNTER(roce_slow_restart),
5384 INIT_Q_COUNTER(roce_slow_restart_cnps),
5385 INIT_Q_COUNTER(roce_slow_restart_trans),
5386};
5387
9f876f3d
TB		 5388#define INIT_EXT_PPCNT_COUNTER(_name) \
5389 { .name = #_name, .offset = \
5390 MLX5_BYTE_OFF(ppcnt_reg, \
5391 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
5392
5393static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
5394 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
5395};
5396
3e1f000f
PP		 5397static bool is_mdev_switchdev_mode(const struct mlx5_core_dev *mdev)
5398{
5399 return MLX5_ESWITCH_MANAGER(mdev) &&
5400 mlx5_ib_eswitch_mode(mdev->priv.eswitch) ==
5401 MLX5_ESWITCH_OFFLOADS;
5402}
5403
e1f24a79 5404static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a 5405{
3e1f000f 5406 int num_cnt_ports;
aac4492e 5407 int i;
0837e86a 5408
3e1f000f
PP		 5409 num_cnt_ports = is_mdev_switchdev_mode(dev->mdev) ? 1 : dev->num_ports;
5410
5411 for (i = 0; i < num_cnt_ports; i++) {
921c0f5b 5412 if (dev->port[i].cnts.set_id_valid)
aac4492e
DJ		 5413 mlx5_core_dealloc_q_counter(dev->mdev,
5414 dev->port[i].cnts.set_id);
e1f24a79
PP		 5415 kfree(dev->port[i].cnts.names);
5416 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 5417 }
5418}
5419
e1f24a79
PP		 5420static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
5421 struct mlx5_ib_counters *cnts)
7c16f477
KH		 5422{
5423 u32 num_counters;
5424
5425 num_counters = ARRAY_SIZE(basic_q_cnts);
5426
5427 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
5428 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
5429
5430 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
5431 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 5432
5433 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
5434 num_counters += ARRAY_SIZE(extended_err_cnts);
5435
d7fab916
AH		 5436 if (MLX5_CAP_GEN(dev->mdev, roce_accl))
5437 num_counters += ARRAY_SIZE(roce_accl_cnts);
5438
e1f24a79 5439 cnts->num_q_counters = num_counters;
7c16f477 5440
e1f24a79
PP		 5441 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5442 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
5443 num_counters += ARRAY_SIZE(cong_cnts);
5444 }
9f876f3d
TB		 5445 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5446 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
5447 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
5448 }
e1f24a79
PP		 5449 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
5450 if (!cnts->names)
7c16f477
KH		 5451 return -ENOMEM;
5452
e1f24a79
PP		 5453 cnts->offsets = kcalloc(num_counters,
5454 sizeof(cnts->offsets), GFP_KERNEL);
5455 if (!cnts->offsets)
7c16f477
KH		 5456 goto err_names;
5457
7c16f477
KH		 5458 return 0;
5459
5460err_names:
e1f24a79 5461 kfree(cnts->names);
aac4492e 5462 cnts->names = NULL;
7c16f477
KH		 5463 return -ENOMEM;
5464}
5465
e1f24a79
PP		 5466static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
5467 const char **names,
5468 size_t *offsets)
7c16f477
KH		 5469{
5470 int i;
5471 int j = 0;
5472
5473 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
5474 names[j] = basic_q_cnts[i].name;
5475 offsets[j] = basic_q_cnts[i].offset;
5476 }
5477
5478 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
5479 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
5480 names[j] = out_of_seq_q_cnts[i].name;
5481 offsets[j] = out_of_seq_q_cnts[i].offset;
5482 }
5483 }
5484
5485 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
5486 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
5487 names[j] = retrans_q_cnts[i].name;
5488 offsets[j] = retrans_q_cnts[i].offset;
5489 }
5490 }
e1f24a79 5491
58dcb60a
PP		 5492 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
5493 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
5494 names[j] = extended_err_cnts[i].name;
5495 offsets[j] = extended_err_cnts[i].offset;
5496 }
5497 }
5498
d7fab916
AH		 5499 if (MLX5_CAP_GEN(dev->mdev, roce_accl)) {
5500 for (i = 0; i < ARRAY_SIZE(roce_accl_cnts); i++, j++) {
5501 names[j] = roce_accl_cnts[i].name;
5502 offsets[j] = roce_accl_cnts[i].offset;
5503 }
5504 }
5505
e1f24a79
PP		 5506 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5507 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
5508 names[j] = cong_cnts[i].name;
5509 offsets[j] = cong_cnts[i].offset;
5510 }
5511 }
9f876f3d
TB		 5512
5513 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5514 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
5515 names[j] = ext_ppcnt_cnts[i].name;
5516 offsets[j] = ext_ppcnt_cnts[i].offset;
5517 }
5518 }
0837e86a
MB		 5519}
5520
e1f24a79 5521static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a 5522{
3e1f000f 5523 int num_cnt_ports;
aac4492e 5524 int err = 0;
0837e86a 5525 int i;
aa74be6e
YH		 5526 bool is_shared;
5527
5528 is_shared = MLX5_CAP_GEN(dev->mdev, log_max_uctx) != 0;
3e1f000f 5529 num_cnt_ports = is_mdev_switchdev_mode(dev->mdev) ? 1 : dev->num_ports;
0837e86a 5530
3e1f000f 5531 for (i = 0; i < num_cnt_ports; i++) {
aac4492e
DJ		 5532 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
5533 if (err)
5534 goto err_alloc;
5535
5536 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
5537 dev->port[i].cnts.offsets);
7c16f477 5538
aa74be6e
YH		 5539 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5540 &dev->port[i].cnts.set_id,
5541 is_shared ?
5542 MLX5_SHARED_RESOURCE_UID : 0);
aac4492e 5543 if (err) {
0837e86a
MB		 5544 mlx5_ib_warn(dev,
5545 "couldn't allocate queue counter for port %d, err %d\n",
aac4492e
DJ		 5546 i + 1, err);
5547 goto err_alloc;
0837e86a 5548 }
aac4492e 5549 dev->port[i].cnts.set_id_valid = true;
0837e86a 5550 }
0837e86a
MB		 5551 return 0;
5552
aac4492e
DJ		 5553err_alloc:
5554 mlx5_ib_dealloc_counters(dev);
5555 return err;
0837e86a
MB		 5556}
5557
3e1f000f
PP		 5558static const struct mlx5_ib_counters *get_counters(struct mlx5_ib_dev *dev,
5559 u8 port_num)
5560{
5561 return is_mdev_switchdev_mode(dev->mdev) ? &dev->port[0].cnts :
5562 &dev->port[port_num].cnts;
5563}
5564
5565/**
5566 * mlx5_ib_get_counters_id - Returns counters id to use for device+port
5567 * @dev: Pointer to mlx5 IB device
5568 * @port_num: Zero based port number
5569 *
5570 * mlx5_ib_get_counters_id() Returns counters set id to use for given
5571 * device port combination in switchdev and non switchdev mode of the
5572 * parent device.
5573 */
5574u16 mlx5_ib_get_counters_id(struct mlx5_ib_dev *dev, u8 port_num)
5575{
5576 const struct mlx5_ib_counters *cnts = get_counters(dev, port_num);
5577
5578 return cnts->set_id;
5579}
5580
0ad17a8f
MB		 5581static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
5582 u8 port_num)
5583{
7c16f477 5584 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3e1f000f
PP		 5585 const struct mlx5_ib_counters *cnts;
5586 bool is_switchdev = is_mdev_switchdev_mode(dev->mdev);
0ad17a8f 5587
3e1f000f 5588 if ((is_switchdev && port_num) || (!is_switchdev && !port_num))
0ad17a8f
MB		 5589 return NULL;
5590
3e1f000f
PP		 5591 cnts = get_counters(dev, port_num - 1);
5592
5dcecbc9
PP		 5593 return rdma_alloc_hw_stats_struct(cnts->names,
5594 cnts->num_q_counters +
5595 cnts->num_cong_counters +
5596 cnts->num_ext_ppcnt_counters,
0ad17a8f
MB		 5597 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5598}
5599
aac4492e 5600static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
5dcecbc9 5601 const struct mlx5_ib_counters *cnts,
318d535c
MZ		 5602 struct rdma_hw_stats *stats,
5603 u16 set_id)
0ad17a8f 5604{
0ad17a8f
MB		 5605 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
5606 void *out;
5607 __be32 val;
e1f24a79 5608 int ret, i;
0ad17a8f 5609
1b9a07ee 5610 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 5611 if (!out)
5612 return -ENOMEM;
5613
318d535c 5614 ret = mlx5_core_query_q_counter(mdev, set_id, 0, out, outlen);
0ad17a8f
MB		 5615 if (ret)
5616 goto free;
5617
5dcecbc9
PP		 5618 for (i = 0; i < cnts->num_q_counters; i++) {
5619 val = *(__be32 *)(out + cnts->offsets[i]);
0ad17a8f
MB		 5620 stats->value[i] = (u64)be32_to_cpu(val);
5621 }
7c16f477 5622
0ad17a8f
MB		 5623free:
5624 kvfree(out);
e1f24a79
PP		 5625 return ret;
5626}
5627
9f876f3d 5628static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
5dcecbc9
PP		 5629 const struct mlx5_ib_counters *cnts,
5630 struct rdma_hw_stats *stats)
9f876f3d 5631{
5dcecbc9 5632 int offset = cnts->num_q_counters + cnts->num_cong_counters;
9f876f3d
TB		 5633 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
5634 int ret, i;
5635 void *out;
5636
5637 out = kvzalloc(sz, GFP_KERNEL);
5638 if (!out)
5639 return -ENOMEM;
5640
5641 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
5642 if (ret)
5643 goto free;
5644
5dcecbc9 5645 for (i = 0; i < cnts->num_ext_ppcnt_counters; i++)
9f876f3d
TB		 5646 stats->value[i + offset] =
5647 be64_to_cpup((__be64 *)(out +
5dcecbc9 5648 cnts->offsets[i + offset]));
9f876f3d
TB		 5649free:
5650 kvfree(out);
5651 return ret;
5652}
5653
e1f24a79
PP		 5654static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
5655 struct rdma_hw_stats *stats,
5656 u8 port_num, int index)
5657{
5658 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3e1f000f 5659 const struct mlx5_ib_counters *cnts = get_counters(dev, port_num - 1);
aac4492e 5660 struct mlx5_core_dev *mdev;
e1f24a79 5661 int ret, num_counters;
aac4492e 5662 u8 mdev_port_num;
e1f24a79
PP		 5663
5664 if (!stats)
5665 return -EINVAL;
5666
5dcecbc9
PP		 5667 num_counters = cnts->num_q_counters +
5668 cnts->num_cong_counters +
5669 cnts->num_ext_ppcnt_counters;
aac4492e
DJ		 5670
5671 /* q_counters are per IB device, query the master mdev */
5dcecbc9 5672 ret = mlx5_ib_query_q_counters(dev->mdev, cnts, stats, cnts->set_id);
e1f24a79
PP		 5673 if (ret)
5674 return ret;
e1f24a79 5675
9f876f3d 5676 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5dcecbc9 5677 ret = mlx5_ib_query_ext_ppcnt_counters(dev, cnts, stats);
9f876f3d
TB		 5678 if (ret)
5679 return ret;
5680 }
5681
e1f24a79 5682 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
aac4492e
DJ		 5683 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
5684 &mdev_port_num);
5685 if (!mdev) {
5686 /* If port is not affiliated yet, its in down state
5687 * which doesn't have any counters yet, so it would be
5688 * zero. So no need to read from the HCA.
5689 */
5690 goto done;
5691 }
71a0ff65
MD		 5692 ret = mlx5_lag_query_cong_counters(dev->mdev,
5693 stats->value +
5dcecbc9
PP		 5694 cnts->num_q_counters,
5695 cnts->num_cong_counters,
5696 cnts->offsets +
5697 cnts->num_q_counters);
aac4492e
DJ		 5698
5699 mlx5_ib_put_native_port_mdev(dev, port_num);
e1f24a79
PP		 5700 if (ret)
5701 return ret;
e1f24a79
PP		 5702 }
5703
aac4492e 5704done:
e1f24a79 5705 return num_counters;
0ad17a8f
MB		 5706}
5707
18d422ce
MZ		 5708static struct rdma_hw_stats *
5709mlx5_ib_counter_alloc_stats(struct rdma_counter *counter)
5710{
5711 struct mlx5_ib_dev *dev = to_mdev(counter->device);
5dcecbc9 5712 const struct mlx5_ib_counters *cnts =
3e1f000f 5713 get_counters(dev, counter->port - 1);
18d422ce
MZ		 5714
5715 /* Q counters are in the beginning of all counters */
5dcecbc9
PP		 5716 return rdma_alloc_hw_stats_struct(cnts->names,
5717 cnts->num_q_counters,
18d422ce
MZ		 5718 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5719}
5720
5721static int mlx5_ib_counter_update_stats(struct rdma_counter *counter)
5722{
5723 struct mlx5_ib_dev *dev = to_mdev(counter->device);
3e1f000f
PP		 5724 const struct mlx5_ib_counters *cnts =
5725 get_counters(dev, counter->port - 1);
18d422ce 5726
5dcecbc9 5727 return mlx5_ib_query_q_counters(dev->mdev, cnts,
18d422ce
MZ		 5728 counter->stats, counter->id);
5729}
5730
45842fc6
MZ		 5731static int mlx5_ib_counter_bind_qp(struct rdma_counter *counter,
5732 struct ib_qp *qp)
5733{
5734 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5735 u16 cnt_set_id = 0;
5736 int err;
5737
5738 if (!counter->id) {
5739 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5740 &cnt_set_id,
5741 MLX5_SHARED_RESOURCE_UID);
5742 if (err)
5743 return err;
5744 counter->id = cnt_set_id;
5745 }
5746
5747 err = mlx5_ib_qp_set_counter(qp, counter);
5748 if (err)
5749 goto fail_set_counter;
5750
5751 return 0;
5752
5753fail_set_counter:
5754 mlx5_core_dealloc_q_counter(dev->mdev, cnt_set_id);
5755 counter->id = 0;
5756
5757 return err;
5758}
5759
5760static int mlx5_ib_counter_unbind_qp(struct ib_qp *qp)
5761{
5762 return mlx5_ib_qp_set_counter(qp, NULL);
5763}
5764
5765static int mlx5_ib_counter_dealloc(struct rdma_counter *counter)
5766{
5767 struct mlx5_ib_dev *dev = to_mdev(counter->device);
5768
5769 return mlx5_core_dealloc_q_counter(dev->mdev, counter->id);
5770}
5771
f6a8a19b
DD		 5772static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num,
5773 enum rdma_netdev_t type,
5774 struct rdma_netdev_alloc_params *params)
693dfd5a
ES		 5775{
5776 if (type != RDMA_NETDEV_IPOIB)
f6a8a19b 5777 return -EOPNOTSUPP;
693dfd5a 5778
f6a8a19b 5779 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
693dfd5a
ES		 5780}
5781
fe248c3a
MG		 5782static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
5783{
09b0965e 5784 if (!dev->delay_drop.dir_debugfs)
fe248c3a 5785 return;
09b0965e
GKH		 5786 debugfs_remove_recursive(dev->delay_drop.dir_debugfs);
5787 dev->delay_drop.dir_debugfs = NULL;
fe248c3a
MG		 5788}
5789
03404e8a
MG		 5790static void cancel_delay_drop(struct mlx5_ib_dev *dev)
5791{
5792 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5793 return;
5794
5795 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 5796 delay_drop_debugfs_cleanup(dev);
5797}
5798
5799static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5800 size_t count, loff_t *pos)
5801{
5802 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5803 char lbuf[20];
5804 int len;
5805
5806 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5807 return simple_read_from_buffer(buf, count, pos, lbuf, len);
5808}
5809
5810static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5811 size_t count, loff_t *pos)
5812{
5813 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5814 u32 timeout;
5815 u32 var;
5816
5817 if (kstrtouint_from_user(buf, count, 0, &var))
5818 return -EFAULT;
5819
5820 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5821 1000);
5822 if (timeout != var)
5823 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5824 timeout);
5825
5826 delay_drop->timeout = timeout;
5827
5828 return count;
5829}
5830
5831static const struct file_operations fops_delay_drop_timeout = {
5832 .owner = THIS_MODULE,
5833 .open = simple_open,
5834 .write = delay_drop_timeout_write,
5835 .read = delay_drop_timeout_read,
5836};
5837
09b0965e 5838static void delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
fe248c3a 5839{
09b0965e 5840 struct dentry *root;
fe248c3a
MG		 5841
5842 if (!mlx5_debugfs_root)
09b0965e 5843 return;
fe248c3a 5844
09b0965e
GKH		 5845 root = debugfs_create_dir("delay_drop", dev->mdev->priv.dbg_root);
5846 dev->delay_drop.dir_debugfs = root;
fe248c3a 5847
09b0965e
GKH		 5848 debugfs_create_atomic_t("num_timeout_events", 0400, root,
5849 &dev->delay_drop.events_cnt);
5850 debugfs_create_atomic_t("num_rqs", 0400, root,
5851 &dev->delay_drop.rqs_cnt);
5852 debugfs_create_file("timeout", 0600, root, &dev->delay_drop,
5853 &fops_delay_drop_timeout);
03404e8a
MG		 5854}
5855
5856static void init_delay_drop(struct mlx5_ib_dev *dev)
5857{
5858 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5859 return;
5860
5861 mutex_init(&dev->delay_drop.lock);
5862 dev->delay_drop.dev = dev;
5863 dev->delay_drop.activate = false;
5864 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5865 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 5866 atomic_set(&dev->delay_drop.rqs_cnt, 0);
5867 atomic_set(&dev->delay_drop.events_cnt, 0);
5868
09b0965e 5869 delay_drop_debugfs_init(dev);
03404e8a
MG		 5870}
5871
32f69e4b
DJ		 5872static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5873 struct mlx5_ib_multiport_info *mpi)
5874{
5875 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5876 struct mlx5_ib_port *port = &ibdev->port[port_num];
5877 int comps;
5878 int err;
5879 int i;
5880
9dc4cfff
LR		 5881 lockdep_assert_held(&mlx5_ib_multiport_mutex);
5882
a9e546e7
PP		 5883 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5884
32f69e4b
DJ		 5885 spin_lock(&port->mp.mpi_lock);
5886 if (!mpi->ibdev) {
5887 spin_unlock(&port->mp.mpi_lock);
5888 return;
5889 }
df097a27 5890
32f69e4b
DJ		 5891 mpi->ibdev = NULL;
5892
5893 spin_unlock(&port->mp.mpi_lock);
23eaf3b5
LR		 5894 if (mpi->mdev_events.notifier_call)
5895 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
5896 mpi->mdev_events.notifier_call = NULL;
32f69e4b
DJ		 5897 mlx5_remove_netdev_notifier(ibdev, port_num);
5898 spin_lock(&port->mp.mpi_lock);
5899
5900 comps = mpi->mdev_refcnt;
5901 if (comps) {
5902 mpi->unaffiliate = true;
5903 init_completion(&mpi->unref_comp);
5904 spin_unlock(&port->mp.mpi_lock);
5905
5906 for (i = 0; i < comps; i++)
5907 wait_for_completion(&mpi->unref_comp);
5908
5909 spin_lock(&port->mp.mpi_lock);
5910 mpi->unaffiliate = false;
5911 }
5912
5913 port->mp.mpi = NULL;
5914
5915 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5916
5917 spin_unlock(&port->mp.mpi_lock);
5918
5919 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5920
5921 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5922 /* Log an error, still needed to cleanup the pointers and add
5923 * it back to the list.
5924 */
5925 if (err)
5926 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5927 port_num + 1);
5928
95579e78 5929 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
32f69e4b
DJ		 5930}
5931
32f69e4b
DJ		 5932static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5933 struct mlx5_ib_multiport_info *mpi)
5934{
5935 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5936 int err;
5937
9dc4cfff
LR		 5938 lockdep_assert_held(&mlx5_ib_multiport_mutex);
5939
32f69e4b
DJ		 5940 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5941 if (ibdev->port[port_num].mp.mpi) {
2577188e
QH		 5942 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
5943 port_num + 1);
32f69e4b
DJ		 5944 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5945 return false;
5946 }
5947
5948 ibdev->port[port_num].mp.mpi = mpi;
5949 mpi->ibdev = ibdev;
df097a27 5950 mpi->mdev_events.notifier_call = NULL;
32f69e4b
DJ		 5951 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5952
5953 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5954 if (err)
5955 goto unbind;
5956
5957 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5958 if (err)
5959 goto unbind;
5960
5961 err = mlx5_add_netdev_notifier(ibdev, port_num);
5962 if (err) {
5963 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5964 port_num + 1);
5965 goto unbind;
5966 }
5967
df097a27
SM		 5968 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
5969 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
5970
73eb8f03 5971 mlx5_ib_init_cong_debugfs(ibdev, port_num);
a9e546e7 5972
32f69e4b
DJ		 5973 return true;
5974
5975unbind:
5976 mlx5_ib_unbind_slave_port(ibdev, mpi);
5977 return false;
5978}
5979
5980static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5981{
5982 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5983 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5984 port_num + 1);
5985 struct mlx5_ib_multiport_info *mpi;
5986 int err;
5987 int i;
5988
5989 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5990 return 0;
5991
5992 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5993 &dev->sys_image_guid);
5994 if (err)
5995 return err;
5996
5997 err = mlx5_nic_vport_enable_roce(dev->mdev);
5998 if (err)
5999 return err;
6000
6001 mutex_lock(&mlx5_ib_multiport_mutex);
6002 for (i = 0; i < dev->num_ports; i++) {
6003 bool bound = false;
6004
6005 /* build a stub multiport info struct for the native port. */
6006 if (i == port_num) {
6007 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6008 if (!mpi) {
6009 mutex_unlock(&mlx5_ib_multiport_mutex);
6010 mlx5_nic_vport_disable_roce(dev->mdev);
6011 return -ENOMEM;
6012 }
6013
6014 mpi->is_master = true;
6015 mpi->mdev = dev->mdev;
6016 mpi->sys_image_guid = dev->sys_image_guid;
6017 dev->port[i].mp.mpi = mpi;
6018 mpi->ibdev = dev;
6019 mpi = NULL;
6020 continue;
6021 }
6022
6023 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
6024 list) {
6025 if (dev->sys_image_guid == mpi->sys_image_guid &&
6026 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
6027 bound = mlx5_ib_bind_slave_port(dev, mpi);
6028 }
6029
6030 if (bound) {
c42260f1
VP		 6031 dev_dbg(mpi->mdev->device,
6032 "removing port from unaffiliated list.\n");
32f69e4b
DJ		 6033 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
6034 list_del(&mpi->list);
6035 break;
6036 }
6037 }
6038 if (!bound) {
6039 get_port_caps(dev, i + 1);
6040 mlx5_ib_dbg(dev, "no free port found for port %d\n",
6041 i + 1);
6042 }
6043 }
6044
6045 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
6046 mutex_unlock(&mlx5_ib_multiport_mutex);
6047 return err;
6048}
6049
6050static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
6051{
6052 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6053 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
6054 port_num + 1);
6055 int i;
6056
6057 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
6058 return;
6059
6060 mutex_lock(&mlx5_ib_multiport_mutex);
6061 for (i = 0; i < dev->num_ports; i++) {
6062 if (dev->port[i].mp.mpi) {
6063 /* Destroy the native port stub */
6064 if (i == port_num) {
6065 kfree(dev->port[i].mp.mpi);
6066 dev->port[i].mp.mpi = NULL;
6067 } else {
6068 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
6069 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
6070 }
6071 }
6072 }
6073
6074 mlx5_ib_dbg(dev, "removing from devlist\n");
6075 list_del(&dev->ib_dev_list);
6076 mutex_unlock(&mlx5_ib_multiport_mutex);
6077
6078 mlx5_nic_vport_disable_roce(dev->mdev);
6079}
6080
7be76bef
YH		 6081static int var_obj_cleanup(struct ib_uobject *uobject,
6082 enum rdma_remove_reason why,
6083 struct uverbs_attr_bundle *attrs)
6084{
6085 struct mlx5_user_mmap_entry *obj = uobject->object;
6086
6087 rdma_user_mmap_entry_remove(&obj->rdma_entry);
6088 return 0;
6089}
6090
6091static struct mlx5_user_mmap_entry *
6092alloc_var_entry(struct mlx5_ib_ucontext *c)
6093{
6094 struct mlx5_user_mmap_entry *entry;
6095 struct mlx5_var_table *var_table;
6096 u32 page_idx;
6097 int err;
6098
6099 var_table = &to_mdev(c->ibucontext.device)->var_table;
6100 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
6101 if (!entry)
6102 return ERR_PTR(-ENOMEM);
6103
6104 mutex_lock(&var_table->bitmap_lock);
6105 page_idx = find_first_zero_bit(var_table->bitmap,
6106 var_table->num_var_hw_entries);
6107 if (page_idx >= var_table->num_var_hw_entries) {
6108 err = -ENOSPC;
6109 mutex_unlock(&var_table->bitmap_lock);
6110 goto end;
6111 }
6112
6113 set_bit(page_idx, var_table->bitmap);
6114 mutex_unlock(&var_table->bitmap_lock);
6115
6116 entry->address = var_table->hw_start_addr +
6117 (page_idx * var_table->stride_size);
6118 entry->page_idx = page_idx;
6119 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR;
6120
6121 err = rdma_user_mmap_entry_insert_range(
6122 &c->ibucontext, &entry->rdma_entry, var_table->stride_size,
6123 MLX5_IB_MMAP_OFFSET_START << 16,
6124 (MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1);
6125 if (err)
6126 goto err_insert;
6127
6128 return entry;
6129
6130err_insert:
6131 mutex_lock(&var_table->bitmap_lock);
6132 clear_bit(page_idx, var_table->bitmap);
6133 mutex_unlock(&var_table->bitmap_lock);
6134end:
6135 kfree(entry);
6136 return ERR_PTR(err);
6137}
6138
6139static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)(
6140 struct uverbs_attr_bundle *attrs)
6141{
6142 struct ib_uobject *uobj = uverbs_attr_get_uobject(
6143 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
6144 struct mlx5_ib_ucontext *c;
6145 struct mlx5_user_mmap_entry *entry;
6146 u64 mmap_offset;
6147 u32 length;
6148 int err;
6149
6150 c = to_mucontext(ib_uverbs_get_ucontext(attrs));
6151 if (IS_ERR(c))
6152 return PTR_ERR(c);
6153
6154 entry = alloc_var_entry(c);
6155 if (IS_ERR(entry))
6156 return PTR_ERR(entry);
6157
6158 mmap_offset = mlx5_entry_to_mmap_offset(entry);
6159 length = entry->rdma_entry.npages * PAGE_SIZE;
6160 uobj->object = entry;
6161
6162 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
6163 &mmap_offset, sizeof(mmap_offset));
6164 if (err)
6165 goto err;
6166
6167 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
6168 &entry->page_idx, sizeof(entry->page_idx));
6169 if (err)
6170 goto err;
6171
6172 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
6173 &length, sizeof(length));
6174 if (err)
6175 goto err;
6176
6177 return 0;
6178
6179err:
6180 rdma_user_mmap_entry_remove(&entry->rdma_entry);
6181 return err;
6182}
6183
6184DECLARE_UVERBS_NAMED_METHOD(
6185 MLX5_IB_METHOD_VAR_OBJ_ALLOC,
6186 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE,
6187 MLX5_IB_OBJECT_VAR,
6188 UVERBS_ACCESS_NEW,
6189 UA_MANDATORY),
6190 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
6191 UVERBS_ATTR_TYPE(u32),
6192 UA_MANDATORY),
6193 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
6194 UVERBS_ATTR_TYPE(u32),
6195 UA_MANDATORY),
6196 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
6197 UVERBS_ATTR_TYPE(u64),
6198 UA_MANDATORY));
6199
6200DECLARE_UVERBS_NAMED_METHOD_DESTROY(
6201 MLX5_IB_METHOD_VAR_OBJ_DESTROY,
6202 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE,
6203 MLX5_IB_OBJECT_VAR,
6204 UVERBS_ACCESS_DESTROY,
6205 UA_MANDATORY));
6206
6207DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR,
6208 UVERBS_TYPE_ALLOC_IDR(var_obj_cleanup),
6209 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC),
6210 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY));
6211
6212static bool var_is_supported(struct ib_device *device)
6213{
6214 struct mlx5_ib_dev *dev = to_mdev(device);
6215
6216 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
6217 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q);
6218}
6219
9a119cd5
JG		 6220ADD_UVERBS_ATTRIBUTES_SIMPLE(
6221 mlx5_ib_dm,
6222 UVERBS_OBJECT_DM,
6223 UVERBS_METHOD_DM_ALLOC,
6224 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
6225 UVERBS_ATTR_TYPE(u64),
83bb4442 6226 UA_MANDATORY),
9a119cd5
JG		 6227 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
6228 UVERBS_ATTR_TYPE(u16),
3b113a1e
AL		 6229 UA_OPTIONAL),
6230 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
6231 enum mlx5_ib_uapi_dm_type,
6232 UA_OPTIONAL));
9a119cd5
JG		 6233
6234ADD_UVERBS_ATTRIBUTES_SIMPLE(
6235 mlx5_ib_flow_action,
6236 UVERBS_OBJECT_FLOW_ACTION,
6237 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
bccd0622
JG		 6238 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
6239 enum mlx5_ib_uapi_flow_action_flags));
c6475a0b 6240
0cbf432d 6241static const struct uapi_definition mlx5_ib_defs[] = {
36e235c8 6242 UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
0cbf432d 6243 UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
30f2fe40 6244 UAPI_DEF_CHAIN(mlx5_ib_qos_defs),
8c84660b 6245
0cbf432d
JG		 6246 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION,
6247 &mlx5_ib_flow_action),
6248 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm),
7be76bef
YH		 6249 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR,
6250 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)),
0cbf432d
JG		 6251 {}
6252};
8c84660b 6253
1a1e03dc
RS		 6254static int mlx5_ib_read_counters(struct ib_counters *counters,
6255 struct ib_counters_read_attr *read_attr,
6256 struct uverbs_attr_bundle *attrs)
6257{
6258 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
6259 struct mlx5_read_counters_attr mread_attr = {};
6260 struct mlx5_ib_flow_counters_desc *desc;
6261 int ret, i;
6262
6263 mutex_lock(&mcounters->mcntrs_mutex);
6264 if (mcounters->cntrs_max_index > read_attr->ncounters) {
6265 ret = -EINVAL;
6266 goto err_bound;
6267 }
6268
6269 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
6270 GFP_KERNEL);
6271 if (!mread_attr.out) {
6272 ret = -ENOMEM;
6273 goto err_bound;
6274 }
6275
6276 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
6277 mread_attr.flags = read_attr->flags;
6278 ret = mcounters->read_counters(counters->device, &mread_attr);
6279 if (ret)
6280 goto err_read;
6281
6282 /* do the pass over the counters data array to assign according to the
6283 * descriptions and indexing pairs
6284 */
6285 desc = mcounters->counters_data;
6286 for (i = 0; i < mcounters->ncounters; i++)
6287 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
6288
6289err_read:
6290 kfree(mread_attr.out);
6291err_bound:
6292 mutex_unlock(&mcounters->mcntrs_mutex);
6293 return ret;
6294}
6295
b29e2a13
RS		 6296static int mlx5_ib_destroy_counters(struct ib_counters *counters)
6297{
6298 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
6299
3b3233fb
RS		 6300 counters_clear_description(counters);
6301 if (mcounters->hw_cntrs_hndl)
6302 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
6303 mcounters->hw_cntrs_hndl);
6304
b29e2a13
RS		 6305 kfree(mcounters);
6306
6307 return 0;
6308}
6309
6310static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
6311 struct uverbs_attr_bundle *attrs)
6312{
6313 struct mlx5_ib_mcounters *mcounters;
6314
6315 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
6316 if (!mcounters)
6317 return ERR_PTR(-ENOMEM);
6318
3b3233fb
RS		 6319 mutex_init(&mcounters->mcntrs_mutex);
6320
b29e2a13
RS		 6321 return &mcounters->ibcntrs;
6322}
6323
fb652d32 6324static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
e126ba97 6325{
32f69e4b 6326 mlx5_ib_cleanup_multiport_master(dev);
806b101b 6327 WARN_ON(!xa_empty(&dev->odp_mkeys));
806b101b 6328 cleanup_srcu_struct(&dev->odp_srcu);
4056b12e 6329
50211ec9 6330 WARN_ON(!xa_empty(&dev->sig_mrs));
4056b12e 6331 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
16c1975f
MB		 6332}
6333
fb652d32 6334static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6335{
6336 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 6337 int err;
32f69e4b 6338 int i;
e126ba97 6339
32f69e4b
DJ		 6340 for (i = 0; i < dev->num_ports; i++) {
6341 spin_lock_init(&dev->port[i].mp.mpi_lock);
95579e78 6342 rwlock_init(&dev->port[i].roce.netdev_lock);
d3b5cc1c
MB		 6343 dev->port[i].roce.dev = dev;
6344 dev->port[i].roce.native_port_num = i + 1;
6345 dev->port[i].roce.last_port_state = IB_PORT_DOWN;
32f69e4b
DJ		 6346 }
6347
00815752
MS		 6348 mlx5_ib_internal_fill_odp_caps(dev);
6349
32f69e4b 6350 err = mlx5_ib_init_multiport_master(dev);
e126ba97 6351 if (err)
da796ccb 6352 return err;
e126ba97 6353
a989ea01
MB		 6354 err = set_has_smi_cap(dev);
6355 if (err)
6356 return err;
e126ba97 6357
32f69e4b 6358 if (!mlx5_core_mp_enabled(mdev)) {
32f69e4b
DJ		 6359 for (i = 1; i <= dev->num_ports; i++) {
6360 err = get_port_caps(dev, i);
6361 if (err)
6362 break;
6363 }
6364 } else {
6365 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
6366 }
6367 if (err)
6368 goto err_mp;
6369
1b5daf11
MD		 6370 if (mlx5_use_mad_ifc(dev))
6371 get_ext_port_caps(dev);
e126ba97 6372
e126ba97 6373 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 6374 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
508562d6 6375 dev->ib_dev.phys_port_cnt = dev->num_ports;
f2f3df55 6376 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev);
c42260f1 6377 dev->ib_dev.dev.parent = mdev->device;
e126ba97 6378
3cc297db
MB		 6379 mutex_init(&dev->cap_mask_mutex);
6380 INIT_LIST_HEAD(&dev->qp_list);
6381 spin_lock_init(&dev->reset_flow_resource_lock);
806b101b 6382 xa_init(&dev->odp_mkeys);
50211ec9 6383 xa_init(&dev->sig_mrs);
f743ff3b 6384 atomic_set(&dev->mkey_var, 0);
3cc297db 6385
3b113a1e
AL		 6386 spin_lock_init(&dev->dm.lock);
6387 dev->dm.dev = mdev;
24da0016 6388
806b101b
JG		 6389 err = init_srcu_struct(&dev->odp_srcu);
6390 if (err)
6391 goto err_mp;
3cc297db 6392
16c1975f 6393 return 0;
25c13324 6394
32f69e4b
DJ		 6395err_mp:
6396 mlx5_ib_cleanup_multiport_master(dev);
16c1975f 6397
16c1975f
MB		 6398 return -ENOMEM;
6399}
6400
9a4ca38d
MB		 6401static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
6402{
6403 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
6404
6405 if (!dev->flow_db)
6406 return -ENOMEM;
6407
6408 mutex_init(&dev->flow_db->lock);
6409
6410 return 0;
6411}
6412
6413static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
6414{
6415 kfree(dev->flow_db);
6416}
6417
96458233 6418static const struct ib_device_ops mlx5_ib_dev_ops = {
7a154142 6419 .owner = THIS_MODULE,
b9560a41 6420 .driver_id = RDMA_DRIVER_MLX5,
72c6ec18 6421 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
b9560a41 6422
96458233
KH		 6423 .add_gid = mlx5_ib_add_gid,
6424 .alloc_mr = mlx5_ib_alloc_mr,
6c984472 6425 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
96458233
KH		 6426 .alloc_pd = mlx5_ib_alloc_pd,
6427 .alloc_ucontext = mlx5_ib_alloc_ucontext,
6428 .attach_mcast = mlx5_ib_mcg_attach,
6429 .check_mr_status = mlx5_ib_check_mr_status,
6430 .create_ah = mlx5_ib_create_ah,
6431 .create_counters = mlx5_ib_create_counters,
6432 .create_cq = mlx5_ib_create_cq,
6433 .create_flow = mlx5_ib_create_flow,
6434 .create_qp = mlx5_ib_create_qp,
6435 .create_srq = mlx5_ib_create_srq,
6436 .dealloc_pd = mlx5_ib_dealloc_pd,
6437 .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
6438 .del_gid = mlx5_ib_del_gid,
6439 .dereg_mr = mlx5_ib_dereg_mr,
6440 .destroy_ah = mlx5_ib_destroy_ah,
6441 .destroy_counters = mlx5_ib_destroy_counters,
6442 .destroy_cq = mlx5_ib_destroy_cq,
6443 .destroy_flow = mlx5_ib_destroy_flow,
6444 .destroy_flow_action = mlx5_ib_destroy_flow_action,
6445 .destroy_qp = mlx5_ib_destroy_qp,
6446 .destroy_srq = mlx5_ib_destroy_srq,
6447 .detach_mcast = mlx5_ib_mcg_detach,
6448 .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
6449 .drain_rq = mlx5_ib_drain_rq,
6450 .drain_sq = mlx5_ib_drain_sq,
11f552e2 6451 .enable_driver = mlx5_ib_enable_driver,
e1b95ae0 6452 .fill_res_entry = mlx5_ib_fill_res_entry,
4061ff7a 6453 .fill_stat_entry = mlx5_ib_fill_stat_entry,
96458233
KH		 6454 .get_dev_fw_str = get_dev_fw_str,
6455 .get_dma_mr = mlx5_ib_get_dma_mr,
6456 .get_link_layer = mlx5_ib_port_link_layer,
6457 .map_mr_sg = mlx5_ib_map_mr_sg,
6c984472 6458 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi,
96458233 6459 .mmap = mlx5_ib_mmap,
dc2316eb 6460 .mmap_free = mlx5_ib_mmap_free,
96458233
KH		 6461 .modify_cq = mlx5_ib_modify_cq,
6462 .modify_device = mlx5_ib_modify_device,
6463 .modify_port = mlx5_ib_modify_port,
6464 .modify_qp = mlx5_ib_modify_qp,
6465 .modify_srq = mlx5_ib_modify_srq,
6466 .poll_cq = mlx5_ib_poll_cq,
6467 .post_recv = mlx5_ib_post_recv,
6468 .post_send = mlx5_ib_post_send,
6469 .post_srq_recv = mlx5_ib_post_srq_recv,
6470 .process_mad = mlx5_ib_process_mad,
6471 .query_ah = mlx5_ib_query_ah,
6472 .query_device = mlx5_ib_query_device,
6473 .query_gid = mlx5_ib_query_gid,
6474 .query_pkey = mlx5_ib_query_pkey,
6475 .query_qp = mlx5_ib_query_qp,
6476 .query_srq = mlx5_ib_query_srq,
6477 .read_counters = mlx5_ib_read_counters,
6478 .reg_user_mr = mlx5_ib_reg_user_mr,
6479 .req_notify_cq = mlx5_ib_arm_cq,
6480 .rereg_user_mr = mlx5_ib_rereg_user_mr,
6481 .resize_cq = mlx5_ib_resize_cq,
d3456914
LR		 6482
6483 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
e39afe3d 6484 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
21a428a0 6485 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
68e326de 6486 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
a2a074ef 6487 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
96458233
KH		 6488};
6489
6490static const struct ib_device_ops mlx5_ib_dev_flow_ipsec_ops = {
6491 .create_flow_action_esp = mlx5_ib_create_flow_action_esp,
6492 .modify_flow_action_esp = mlx5_ib_modify_flow_action_esp,
6493};
6494
6495static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
6496 .rdma_netdev_get_params = mlx5_ib_rn_get_params,
6497};
6498
6499static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
6500 .get_vf_config = mlx5_ib_get_vf_config,
9c0015ef 6501 .get_vf_guid = mlx5_ib_get_vf_guid,
96458233
KH		 6502 .get_vf_stats = mlx5_ib_get_vf_stats,
6503 .set_vf_guid = mlx5_ib_set_vf_guid,
6504 .set_vf_link_state = mlx5_ib_set_vf_link_state,
6505};
6506
6507static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
6508 .alloc_mw = mlx5_ib_alloc_mw,
6509 .dealloc_mw = mlx5_ib_dealloc_mw,
6510};
6511
6512static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
6513 .alloc_xrcd = mlx5_ib_alloc_xrcd,
6514 .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
6515};
6516
6517static const struct ib_device_ops mlx5_ib_dev_dm_ops = {
6518 .alloc_dm = mlx5_ib_alloc_dm,
6519 .dealloc_dm = mlx5_ib_dealloc_dm,
6520 .reg_dm_mr = mlx5_ib_reg_dm_mr,
6521};
6522
f164be8c
YH		 6523static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev)
6524{
6525 struct mlx5_core_dev *mdev = dev->mdev;
6526 struct mlx5_var_table *var_table = &dev->var_table;
6527 u8 log_doorbell_bar_size;
6528 u8 log_doorbell_stride;
6529 u64 bar_size;
6530
6531 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
6532 log_doorbell_bar_size);
6533 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
6534 log_doorbell_stride);
6535 var_table->hw_start_addr = dev->mdev->bar_addr +
6536 MLX5_CAP64_DEV_VDPA_EMULATION(mdev,
6537 doorbell_bar_offset);
6538 bar_size = (1ULL << log_doorbell_bar_size) * 4096;
6539 var_table->stride_size = 1ULL << log_doorbell_stride;
91b74bf5
AL		 6540 var_table->num_var_hw_entries = div_u64(bar_size,
6541 var_table->stride_size);
f164be8c
YH		 6542 mutex_init(&var_table->bitmap_lock);
6543 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries,
6544 GFP_KERNEL);
6545 return (var_table->bitmap) ? 0 : -ENOMEM;
6546}
6547
6548static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev)
6549{
6550 bitmap_free(dev->var_table.bitmap);
6551}
6552
fb652d32 6553static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6554{
6555 struct mlx5_core_dev *mdev = dev->mdev;
16c1975f
MB		 6556 int err;
6557
e126ba97
EC		 6558 dev->ib_dev.uverbs_cmd_mask =
6559 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
6560 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
6561 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
6562 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
6563 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 6564 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
6565 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 6566 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 6567 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 6568 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
6569 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
6570 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
6571 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
6572 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
6573 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
6574 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
6575 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
6576 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
6577 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
6578 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
6579 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
6580 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
6581 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
6582 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
6583 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
6584 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 6585 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 6586 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
6587 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349 6588 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
b0e9df6d 6589 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
96458233
KH		 6590 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ) |
6591 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
6592 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
6593
f6a8a19b
DD		 6594 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
6595 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
96458233
KH		 6596 ib_set_device_ops(&dev->ib_dev,
6597 &mlx5_ib_dev_ipoib_enhanced_ops);
8e959601 6598
96458233
KH		 6599 if (mlx5_core_is_pf(mdev))
6600 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
7c2344c3 6601
6e8484c5
MG		 6602 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
6603
d2370e0a 6604 if (MLX5_CAP_GEN(mdev, imaicl)) {
d2370e0a
MB		 6605 dev->ib_dev.uverbs_cmd_mask |=
6606 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
6607 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
96458233 6608 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
d2370e0a
MB		 6609 }
6610
938fe83c 6611 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 6612 dev->ib_dev.uverbs_cmd_mask |=
6613 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
6614 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
96458233 6615 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
e126ba97
EC		 6616 }
6617
25c13324
AL		 6618 if (MLX5_CAP_DEV_MEM(mdev, memic) ||
6619 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
6620 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
96458233 6621 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
24da0016 6622
dfb631a1 6623 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
96458233
KH		 6624 MLX5_ACCEL_IPSEC_CAP_DEVICE)
6625 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_flow_ipsec_ops);
96458233 6626 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
81e30880 6627
36e235c8
JG		 6628 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
6629 dev->ib_dev.driver_def = mlx5_ib_defs;
81e30880 6630
e126ba97
EC		 6631 err = init_node_data(dev);
6632 if (err)
16c1975f 6633 return err;
e126ba97 6634
c8b89924 6635 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
e7996a9a
JG		 6636 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
6637 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
a560f1d9 6638 mutex_init(&dev->lb.mutex);
c8b89924 6639
f164be8c
YH		 6640 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
6641 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
6642 err = mlx5_ib_init_var_table(dev);
6643 if (err)
6644 return err;
6645 }
6646
96e2fd73
LR		 6647 dev->ib_dev.use_cq_dim = true;
6648
16c1975f
MB		 6649 return 0;
6650}
6651
96458233
KH		 6652static const struct ib_device_ops mlx5_ib_dev_port_ops = {
6653 .get_port_immutable = mlx5_port_immutable,
6654 .query_port = mlx5_ib_query_port,
6655};
6656
8e6efa3a
MB		 6657static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
6658{
96458233 6659 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
8e6efa3a
MB		 6660 return 0;
6661}
6662
96458233
KH		 6663static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
6664 .get_port_immutable = mlx5_port_rep_immutable,
6665 .query_port = mlx5_ib_rep_query_port,
6666};
6667
b5a498ba 6668static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev)
8e6efa3a 6669{
96458233 6670 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
8e6efa3a
MB		 6671 return 0;
6672}
6673
96458233
KH		 6674static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
6675 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
6676 .create_wq = mlx5_ib_create_wq,
6677 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
6678 .destroy_wq = mlx5_ib_destroy_wq,
6679 .get_netdev = mlx5_ib_get_netdev,
6680 .modify_wq = mlx5_ib_modify_wq,
6681};
6682
e3f1ed1f 6683static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
8e6efa3a 6684{
e3f1ed1f 6685 u8 port_num;
8e6efa3a 6686
8e6efa3a
MB		 6687 dev->ib_dev.uverbs_ex_cmd_mask |=
6688 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
6689 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
6690 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
6691 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
6692 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
96458233 6693 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
8e6efa3a 6694
e3f1ed1f
LR		 6695 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6696
26628e2d 6697 /* Register only for native ports */
8e6efa3a
MB		 6698 return mlx5_add_netdev_notifier(dev, port_num);
6699}
6700
6701static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
6702{
6703 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6704
6705 mlx5_remove_netdev_notifier(dev, port_num);
6706}
6707
b5a498ba 6708static int mlx5_ib_stage_raw_eth_roce_init(struct mlx5_ib_dev *dev)
8e6efa3a
MB		 6709{
6710 struct mlx5_core_dev *mdev = dev->mdev;
6711 enum rdma_link_layer ll;
6712 int port_type_cap;
6713 int err = 0;
8e6efa3a 6714
8e6efa3a
MB		 6715 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6716 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6717
6718 if (ll == IB_LINK_LAYER_ETHERNET)
e3f1ed1f 6719 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 6720
6721 return err;
6722}
6723
b5a498ba 6724static void mlx5_ib_stage_raw_eth_roce_cleanup(struct mlx5_ib_dev *dev)
8e6efa3a
MB		 6725{
6726 mlx5_ib_stage_common_roce_cleanup(dev);
6727}
6728
16c1975f
MB		 6729static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
6730{
6731 struct mlx5_core_dev *mdev = dev->mdev;
6732 enum rdma_link_layer ll;
6733 int port_type_cap;
6734 int err;
6735
6736 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6737 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6738
fc24fc5e 6739 if (ll == IB_LINK_LAYER_ETHERNET) {
e3f1ed1f 6740 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 6741 if (err)
6742 return err;
7fd8aefb 6743
e3f1ed1f 6744 err = mlx5_enable_eth(dev);
fc24fc5e 6745 if (err)
8e6efa3a 6746 goto cleanup;
fc24fc5e
AS		 6747 }
6748
16c1975f 6749 return 0;
8e6efa3a
MB		 6750cleanup:
6751 mlx5_ib_stage_common_roce_cleanup(dev);
6752
6753 return err;
16c1975f 6754}
e126ba97 6755
16c1975f
MB		 6756static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
6757{
6758 struct mlx5_core_dev *mdev = dev->mdev;
6759 enum rdma_link_layer ll;
6760 int port_type_cap;
e126ba97 6761
16c1975f
MB		 6762 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6763 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6764
6765 if (ll == IB_LINK_LAYER_ETHERNET) {
6766 mlx5_disable_eth(dev);
8e6efa3a 6767 mlx5_ib_stage_common_roce_cleanup(dev);
45bded2c 6768 }
16c1975f 6769}
6aec21f6 6770
fb652d32 6771static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6772{
6773 return create_dev_resources(&dev->devr);
6774}
6775
fb652d32 6776static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6777{
6778 destroy_dev_resources(&dev->devr);
6779}
6780
6781static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
6782{
6783 return mlx5_ib_odp_init_one(dev);
6784}
4a2da0b8 6785
f3ffed0c 6786static void mlx5_ib_stage_odp_cleanup(struct mlx5_ib_dev *dev)
d5d284b8
SM		 6787{
6788 mlx5_ib_odp_cleanup_one(dev);
6789}
6790
96458233
KH		 6791static const struct ib_device_ops mlx5_ib_dev_hw_stats_ops = {
6792 .alloc_hw_stats = mlx5_ib_alloc_hw_stats,
6793 .get_hw_stats = mlx5_ib_get_hw_stats,
45842fc6
MZ		 6794 .counter_bind_qp = mlx5_ib_counter_bind_qp,
6795 .counter_unbind_qp = mlx5_ib_counter_unbind_qp,
6796 .counter_dealloc = mlx5_ib_counter_dealloc,
18d422ce
MZ		 6797 .counter_alloc_stats = mlx5_ib_counter_alloc_stats,
6798 .counter_update_stats = mlx5_ib_counter_update_stats,
96458233
KH		 6799};
6800
fb652d32 6801static int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
16c1975f 6802{
5e1e7612 6803 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
96458233 6804 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_hw_stats_ops);
5e1e7612
MB		 6805
6806 return mlx5_ib_alloc_counters(dev);
6807 }
16c1975f
MB		 6808
6809 return 0;
6810}
6811
fb652d32 6812static void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6813{
6814 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
6815 mlx5_ib_dealloc_counters(dev);
6816}
6817
6818static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
6819{
73eb8f03
GKH		 6820 mlx5_ib_init_cong_debugfs(dev,
6821 mlx5_core_native_port_num(dev->mdev) - 1);
6822 return 0;
16c1975f
MB		 6823}
6824
6825static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
6826{
a9e546e7
PP		 6827 mlx5_ib_cleanup_cong_debugfs(dev,
6828 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 6829}
6830
6831static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
6832{
5fe9dec0 6833 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
444261ca 6834 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
16c1975f
MB		 6835}
6836
6837static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
6838{
6839 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
6840}
6841
fb652d32 6842static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6843{
6844 int err;
5fe9dec0
EC		 6845
6846 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
6847 if (err)
16c1975f 6848 return err;
5fe9dec0
EC		 6849
6850 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
6851 if (err)
16c1975f 6852 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5fe9dec0 6853
16c1975f
MB		 6854 return err;
6855}
0837e86a 6856
fb652d32 6857static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6858{
6859 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6860 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
6861}
e126ba97 6862
fb652d32 6863static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
16c1975f 6864{
e349f858
JG		 6865 const char *name;
6866
508a523f 6867 rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group);
7c34ec19 6868 if (!mlx5_lag_is_roce(dev->mdev))
e349f858
JG		 6869 name = "mlx5_%d";
6870 else
6871 name = "mlx5_bond_%d";
ea4baf7f 6872 return ib_register_device(&dev->ib_dev, name);
16c1975f
MB		 6873}
6874
fb652d32 6875static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
16c1975f 6876{
42cea83f 6877 destroy_umrc_res(dev);
16c1975f
MB		 6878}
6879
fb652d32 6880static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
16c1975f 6881{
42cea83f 6882 ib_unregister_device(&dev->ib_dev);
16c1975f
MB		 6883}
6884
fb652d32 6885static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
16c1975f 6886{
42cea83f 6887 return create_umr_res(dev);
16c1975f
MB		 6888}
6889
6890static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
6891{
03404e8a
MG		 6892 init_delay_drop(dev);
6893
16c1975f
MB		 6894 return 0;
6895}
6896
6897static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
6898{
6899 cancel_delay_drop(dev);
6900}
6901
df097a27
SM		 6902static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
6903{
6904 dev->mdev_events.notifier_call = mlx5_ib_event;
6905 mlx5_notifier_register(dev->mdev, &dev->mdev_events);
6906 return 0;
6907}
6908
6909static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
6910{
6911 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
6912}
6913
81773ce5
LR		 6914static int mlx5_ib_stage_devx_init(struct mlx5_ib_dev *dev)
6915{
6916 int uid;
6917
fb98153b 6918 uid = mlx5_ib_devx_create(dev, false);
e337dd53 6919 if (uid > 0) {
81773ce5 6920 dev->devx_whitelist_uid = uid;
e337dd53
YH		 6921 mlx5_ib_devx_init_event_table(dev);
6922 }
81773ce5
LR		 6923
6924 return 0;
6925}
6926static void mlx5_ib_stage_devx_cleanup(struct mlx5_ib_dev *dev)
6927{
e337dd53
YH		 6928 if (dev->devx_whitelist_uid) {
6929 mlx5_ib_devx_cleanup_event_table(dev);
81773ce5 6930 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid);
e337dd53 6931 }
81773ce5
LR		 6932}
6933
11f552e2
MG		 6934int mlx5_ib_enable_driver(struct ib_device *dev)
6935{
6936 struct mlx5_ib_dev *mdev = to_mdev(dev);
6937 int ret;
6938
6939 ret = mlx5_ib_test_wc(mdev);
6940 mlx5_ib_dbg(mdev, "Write-Combining %s",
6941 mdev->wc_support ? "supported" : "not supported");
6942
6943 return ret;
6944}
6945
b5ca15ad
MB		 6946void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
6947 const struct mlx5_ib_profile *profile,
6948 int stage)
16c1975f 6949{
4cca96a8
PP		 6950 dev->ib_active = false;
6951
16c1975f
MB		 6952 /* Number of stages to cleanup */
6953 while (stage) {
6954 stage--;
6955 if (profile->stage[stage].cleanup)
6956 profile->stage[stage].cleanup(dev);
6957 }
4a6dc855 6958
da796ccb 6959 kfree(dev->port);
4a6dc855 6960 ib_dealloc_device(&dev->ib_dev);
16c1975f 6961}
e126ba97 6962
b5ca15ad
MB		 6963void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
6964 const struct mlx5_ib_profile *profile)
16c1975f 6965{
16c1975f
MB		 6966 int err;
6967 int i;
5fe9dec0 6968
16c1975f
MB		 6969 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
6970 if (profile->stage[i].init) {
6971 err = profile->stage[i].init(dev);
6972 if (err)
6973 goto err_out;
6974 }
6975 }
0837e86a 6976
16c1975f
MB		 6977 dev->profile = profile;
6978 dev->ib_active = true;
6aec21f6 6979
16c1975f 6980 return dev;
e126ba97 6981
16c1975f
MB		 6982err_out:
6983 __mlx5_ib_remove(dev, profile, i);
fc24fc5e 6984
16c1975f
MB		 6985 return NULL;
6986}
0837e86a 6987
16c1975f
MB		 6988static const struct mlx5_ib_profile pf_profile = {
6989 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6990 mlx5_ib_stage_init_init,
6991 mlx5_ib_stage_init_cleanup),
9a4ca38d
MB		 6992 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6993 mlx5_ib_stage_flow_db_init,
6994 mlx5_ib_stage_flow_db_cleanup),
16c1975f
MB		 6995 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6996 mlx5_ib_stage_caps_init,
f164be8c 6997 mlx5_ib_stage_caps_cleanup),
8e6efa3a
MB		 6998 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6999 mlx5_ib_stage_non_default_cb,
7000 NULL),
16c1975f
MB		 7001 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
7002 mlx5_ib_stage_roce_init,
7003 mlx5_ib_stage_roce_cleanup),
f3da6577
LR		 7004 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
7005 mlx5_init_srq_table,
7006 mlx5_cleanup_srq_table),
16c1975f
MB		 7007 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
7008 mlx5_ib_stage_dev_res_init,
7009 mlx5_ib_stage_dev_res_cleanup),
df097a27
SM		 7010 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
7011 mlx5_ib_stage_dev_notifier_init,
7012 mlx5_ib_stage_dev_notifier_cleanup),
16c1975f
MB		 7013 STAGE_CREATE(MLX5_IB_STAGE_ODP,
7014 mlx5_ib_stage_odp_init,
d5d284b8 7015 mlx5_ib_stage_odp_cleanup),
16c1975f
MB		 7016 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
7017 mlx5_ib_stage_counters_init,
7018 mlx5_ib_stage_counters_cleanup),
7019 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
7020 mlx5_ib_stage_cong_debugfs_init,
7021 mlx5_ib_stage_cong_debugfs_cleanup),
7022 STAGE_CREATE(MLX5_IB_STAGE_UAR,
7023 mlx5_ib_stage_uar_init,
7024 mlx5_ib_stage_uar_cleanup),
7025 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
7026 mlx5_ib_stage_bfrag_init,
7027 mlx5_ib_stage_bfrag_cleanup),
42cea83f
MB		 7028 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
7029 NULL,
7030 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
81773ce5
LR		 7031 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
7032 mlx5_ib_stage_devx_init,
7033 mlx5_ib_stage_devx_cleanup),
16c1975f
MB		 7034 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
7035 mlx5_ib_stage_ib_reg_init,
7036 mlx5_ib_stage_ib_reg_cleanup),
42cea83f
MB		 7037 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
7038 mlx5_ib_stage_post_ib_reg_umr_init,
7039 NULL),
16c1975f
MB		 7040 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
7041 mlx5_ib_stage_delay_drop_init,
7042 mlx5_ib_stage_delay_drop_cleanup),
16c1975f 7043};
e126ba97 7044
b5a498ba 7045const struct mlx5_ib_profile raw_eth_profile = {
b5ca15ad
MB		 7046 STAGE_CREATE(MLX5_IB_STAGE_INIT,
7047 mlx5_ib_stage_init_init,
7048 mlx5_ib_stage_init_cleanup),
7049 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
7050 mlx5_ib_stage_flow_db_init,
7051 mlx5_ib_stage_flow_db_cleanup),
7052 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
7053 mlx5_ib_stage_caps_init,
f164be8c 7054 mlx5_ib_stage_caps_cleanup),
b5ca15ad 7055 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
b5a498ba 7056 mlx5_ib_stage_raw_eth_non_default_cb,
b5ca15ad
MB		 7057 NULL),
7058 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
b5a498ba
MG		 7059 mlx5_ib_stage_raw_eth_roce_init,
7060 mlx5_ib_stage_raw_eth_roce_cleanup),
f3da6577
LR		 7061 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
7062 mlx5_init_srq_table,
7063 mlx5_cleanup_srq_table),
b5ca15ad
MB		 7064 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
7065 mlx5_ib_stage_dev_res_init,
7066 mlx5_ib_stage_dev_res_cleanup),
df097a27
SM		 7067 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
7068 mlx5_ib_stage_dev_notifier_init,
7069 mlx5_ib_stage_dev_notifier_cleanup),
b5ca15ad
MB		 7070 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
7071 mlx5_ib_stage_counters_init,
7072 mlx5_ib_stage_counters_cleanup),
79db784e
PP		 7073 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
7074 mlx5_ib_stage_cong_debugfs_init,
7075 mlx5_ib_stage_cong_debugfs_cleanup),
b5ca15ad
MB		 7076 STAGE_CREATE(MLX5_IB_STAGE_UAR,
7077 mlx5_ib_stage_uar_init,
7078 mlx5_ib_stage_uar_cleanup),
7079 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
7080 mlx5_ib_stage_bfrag_init,
7081 mlx5_ib_stage_bfrag_cleanup),
03fe2deb
DM		 7082 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
7083 NULL,
7084 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
7f575103
MB		 7085 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
7086 mlx5_ib_stage_devx_init,
7087 mlx5_ib_stage_devx_cleanup),
b5ca15ad
MB		 7088 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
7089 mlx5_ib_stage_ib_reg_init,
7090 mlx5_ib_stage_ib_reg_cleanup),
03fe2deb
DM		 7091 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
7092 mlx5_ib_stage_post_ib_reg_umr_init,
7093 NULL),
b5ca15ad
MB		 7094};
7095
e3f1ed1f 7096static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
32f69e4b
DJ		 7097{
7098 struct mlx5_ib_multiport_info *mpi;
7099 struct mlx5_ib_dev *dev;
7100 bool bound = false;
7101 int err;
7102
7103 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
7104 if (!mpi)
7105 return NULL;
7106
7107 mpi->mdev = mdev;
7108
7109 err = mlx5_query_nic_vport_system_image_guid(mdev,
7110 &mpi->sys_image_guid);
7111 if (err) {
7112 kfree(mpi);
7113 return NULL;
7114 }
7115
7116 mutex_lock(&mlx5_ib_multiport_mutex);
7117 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
7118 if (dev->sys_image_guid == mpi->sys_image_guid)
7119 bound = mlx5_ib_bind_slave_port(dev, mpi);
7120
7121 if (bound) {
7122 rdma_roce_rescan_device(&dev->ib_dev);
7123 break;
7124 }
7125 }
7126
7127 if (!bound) {
7128 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
c42260f1
VP		 7129 dev_dbg(mdev->device,
7130 "no suitable IB device found to bind to, added to unaffiliated list.\n");
32f69e4b
DJ		 7131 }
7132 mutex_unlock(&mlx5_ib_multiport_mutex);
7133
7134 return mpi;
7135}
7136
16c1975f
MB		 7137static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
7138{
94de879c 7139 const struct mlx5_ib_profile *profile;
32f69e4b 7140 enum rdma_link_layer ll;
b5ca15ad 7141 struct mlx5_ib_dev *dev;
32f69e4b 7142 int port_type_cap;
da796ccb 7143 int num_ports;
32f69e4b 7144
b5ca15ad
MB		 7145 printk_once(KERN_INFO "%s", mlx5_version);
7146
f0666f1f 7147 if (MLX5_ESWITCH_MANAGER(mdev) &&
f6455de0 7148 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
5fb58c9e
MB		 7149 if (!mlx5_core_mp_enabled(mdev))
7150 mlx5_ib_register_vport_reps(mdev);
f0666f1f
BW		 7151 return mdev;
7152 }
7153
32f69e4b
DJ		 7154 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
7155 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
7156
e3f1ed1f
LR		 7157 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
7158 return mlx5_ib_add_slave_port(mdev);
32f69e4b 7159
da796ccb
MB		 7160 num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
7161 MLX5_CAP_GEN(mdev, num_vhca_ports));
459cc69f 7162 dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
b5ca15ad
MB		 7163 if (!dev)
7164 return NULL;
da796ccb
MB		 7165 dev->port = kcalloc(num_ports, sizeof(*dev->port),
7166 GFP_KERNEL);
7167 if (!dev->port) {
a5c9c299 7168 ib_dealloc_device(&dev->ib_dev);
da796ccb
MB		 7169 return NULL;
7170 }
b5ca15ad
MB		 7171
7172 dev->mdev = mdev;
da796ccb 7173 dev->num_ports = num_ports;
b5ca15ad 7174
94de879c
MG		 7175 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_is_roce_enabled(mdev))
7176 profile = &raw_eth_profile;
7177 else
7178 profile = &pf_profile;
7179
7180 return __mlx5_ib_add(dev, profile);
e126ba97
EC		 7181}
7182
9603b61d 7183static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 7184{
32f69e4b
DJ		 7185 struct mlx5_ib_multiport_info *mpi;
7186 struct mlx5_ib_dev *dev;
7187
f0666f1f
BW		 7188 if (MLX5_ESWITCH_MANAGER(mdev) && context == mdev) {
7189 mlx5_ib_unregister_vport_reps(mdev);
7190 return;
7191 }
7192
32f69e4b
DJ		 7193 if (mlx5_core_is_mp_slave(mdev)) {
7194 mpi = context;
7195 mutex_lock(&mlx5_ib_multiport_mutex);
7196 if (mpi->ibdev)
7197 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
7198 list_del(&mpi->list);
7199 mutex_unlock(&mlx5_ib_multiport_mutex);
5d44adeb 7200 kfree(mpi);
32f69e4b
DJ		 7201 return;
7202 }
6aec21f6 7203
32f69e4b 7204 dev = context;
f0666f1f 7205 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
e126ba97
EC		 7206}
7207
9603b61d
JM		 7208static struct mlx5_interface mlx5_ib_interface = {
7209 .add = mlx5_ib_add,
7210 .remove = mlx5_ib_remove,
64613d94 7211 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 7212};
7213
c44ef998
IL		 7214unsigned long mlx5_ib_get_xlt_emergency_page(void)
7215{
7216 mutex_lock(&xlt_emergency_page_mutex);
7217 return xlt_emergency_page;
7218}
7219
7220void mlx5_ib_put_xlt_emergency_page(void)
7221{
7222 mutex_unlock(&xlt_emergency_page_mutex);
7223}
7224
e126ba97
EC		 7225static int __init mlx5_ib_init(void)
7226{
6aec21f6
HE		 7227 int err;
7228
c44ef998
IL		 7229 xlt_emergency_page = __get_free_page(GFP_KERNEL);
7230 if (!xlt_emergency_page)
7231 return -ENOMEM;
7232
7233 mutex_init(&xlt_emergency_page_mutex);
7234
d69a24e0 7235 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
c44ef998
IL		 7236 if (!mlx5_ib_event_wq) {
7237 free_page(xlt_emergency_page);
d69a24e0 7238 return -ENOMEM;
c44ef998 7239 }
d69a24e0 7240
81713d37 7241 mlx5_ib_odp_init();
9603b61d 7242
6aec21f6 7243 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 7244
6aec21f6 7245 return err;
e126ba97
EC		 7246}
7247
7248static void __exit mlx5_ib_cleanup(void)
7249{
9603b61d 7250 mlx5_unregister_interface(&mlx5_ib_interface);
d69a24e0 7251 destroy_workqueue(mlx5_ib_event_wq);
c44ef998
IL		 7252 mutex_destroy(&xlt_emergency_page_mutex);
7253 free_page(xlt_emergency_page);
e126ba97
EC		 7254}
7255
7256module_init(mlx5_ib_init);
7257module_exit(mlx5_ib_cleanup);
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