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e126ba97 | 1 | /* |
6cf0a15f | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
fe248c3a | 33 | #include <linux/debugfs.h> |
adec640e | 34 | #include <linux/highmem.h> |
e126ba97 EC |
35 | #include <linux/module.h> |
36 | #include <linux/init.h> | |
37 | #include <linux/errno.h> | |
38 | #include <linux/pci.h> | |
39 | #include <linux/dma-mapping.h> | |
40 | #include <linux/slab.h> | |
37aa5c36 GL |
41 | #if defined(CONFIG_X86) |
42 | #include <asm/pat.h> | |
43 | #endif | |
e126ba97 | 44 | #include <linux/sched.h> |
6e84f315 | 45 | #include <linux/sched/mm.h> |
0881e7bd | 46 | #include <linux/sched/task.h> |
7c2344c3 | 47 | #include <linux/delay.h> |
e126ba97 | 48 | #include <rdma/ib_user_verbs.h> |
3f89a643 | 49 | #include <rdma/ib_addr.h> |
2811ba51 | 50 | #include <rdma/ib_cache.h> |
ada68c31 | 51 | #include <linux/mlx5/port.h> |
1b5daf11 | 52 | #include <linux/mlx5/vport.h> |
7c2344c3 | 53 | #include <linux/list.h> |
e126ba97 EC |
54 | #include <rdma/ib_smi.h> |
55 | #include <rdma/ib_umem.h> | |
038d2ef8 MG |
56 | #include <linux/in.h> |
57 | #include <linux/etherdevice.h> | |
58 | #include <linux/mlx5/fs.h> | |
78984898 | 59 | #include <linux/mlx5/vport.h> |
e126ba97 | 60 | #include "mlx5_ib.h" |
e1f24a79 | 61 | #include "cmd.h" |
c85023e1 | 62 | #include <linux/mlx5/vport.h> |
e126ba97 EC |
63 | |
64 | #define DRIVER_NAME "mlx5_ib" | |
b359911d | 65 | #define DRIVER_VERSION "5.0-0" |
e126ba97 EC |
66 | |
67 | MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); | |
68 | MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); | |
69 | MODULE_LICENSE("Dual BSD/GPL"); | |
e126ba97 | 70 | |
e126ba97 EC |
71 | static char mlx5_version[] = |
72 | DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" | |
b359911d | 73 | DRIVER_VERSION "\n"; |
e126ba97 | 74 | |
da7525d2 EBE |
75 | enum { |
76 | MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, | |
77 | }; | |
78 | ||
1b5daf11 | 79 | static enum rdma_link_layer |
ebd61f68 | 80 | mlx5_port_type_cap_to_rdma_ll(int port_type_cap) |
1b5daf11 | 81 | { |
ebd61f68 | 82 | switch (port_type_cap) { |
1b5daf11 MD |
83 | case MLX5_CAP_PORT_TYPE_IB: |
84 | return IB_LINK_LAYER_INFINIBAND; | |
85 | case MLX5_CAP_PORT_TYPE_ETH: | |
86 | return IB_LINK_LAYER_ETHERNET; | |
87 | default: | |
88 | return IB_LINK_LAYER_UNSPECIFIED; | |
89 | } | |
90 | } | |
91 | ||
ebd61f68 AS |
92 | static enum rdma_link_layer |
93 | mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) | |
94 | { | |
95 | struct mlx5_ib_dev *dev = to_mdev(device); | |
96 | int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); | |
97 | ||
98 | return mlx5_port_type_cap_to_rdma_ll(port_type_cap); | |
99 | } | |
100 | ||
fd65f1b8 MS |
101 | static int get_port_state(struct ib_device *ibdev, |
102 | u8 port_num, | |
103 | enum ib_port_state *state) | |
104 | { | |
105 | struct ib_port_attr attr; | |
106 | int ret; | |
107 | ||
108 | memset(&attr, 0, sizeof(attr)); | |
109 | ret = mlx5_ib_query_port(ibdev, port_num, &attr); | |
110 | if (!ret) | |
111 | *state = attr.state; | |
112 | return ret; | |
113 | } | |
114 | ||
fc24fc5e AS |
115 | static int mlx5_netdev_event(struct notifier_block *this, |
116 | unsigned long event, void *ptr) | |
117 | { | |
118 | struct net_device *ndev = netdev_notifier_info_to_dev(ptr); | |
119 | struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev, | |
120 | roce.nb); | |
121 | ||
5ec8c83e AH |
122 | switch (event) { |
123 | case NETDEV_REGISTER: | |
124 | case NETDEV_UNREGISTER: | |
125 | write_lock(&ibdev->roce.netdev_lock); | |
126 | if (ndev->dev.parent == &ibdev->mdev->pdev->dev) | |
127 | ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? | |
128 | NULL : ndev; | |
129 | write_unlock(&ibdev->roce.netdev_lock); | |
130 | break; | |
fc24fc5e | 131 | |
fd65f1b8 | 132 | case NETDEV_CHANGE: |
5ec8c83e | 133 | case NETDEV_UP: |
88621dfe AH |
134 | case NETDEV_DOWN: { |
135 | struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev); | |
136 | struct net_device *upper = NULL; | |
137 | ||
138 | if (lag_ndev) { | |
139 | upper = netdev_master_upper_dev_get(lag_ndev); | |
140 | dev_put(lag_ndev); | |
141 | } | |
142 | ||
143 | if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev)) | |
144 | && ibdev->ib_active) { | |
626bc02d | 145 | struct ib_event ibev = { }; |
fd65f1b8 | 146 | enum ib_port_state port_state; |
5ec8c83e | 147 | |
fd65f1b8 MS |
148 | if (get_port_state(&ibdev->ib_dev, 1, &port_state)) |
149 | return NOTIFY_DONE; | |
150 | ||
151 | if (ibdev->roce.last_port_state == port_state) | |
152 | return NOTIFY_DONE; | |
153 | ||
154 | ibdev->roce.last_port_state = port_state; | |
5ec8c83e | 155 | ibev.device = &ibdev->ib_dev; |
fd65f1b8 MS |
156 | if (port_state == IB_PORT_DOWN) |
157 | ibev.event = IB_EVENT_PORT_ERR; | |
158 | else if (port_state == IB_PORT_ACTIVE) | |
159 | ibev.event = IB_EVENT_PORT_ACTIVE; | |
160 | else | |
161 | return NOTIFY_DONE; | |
162 | ||
5ec8c83e AH |
163 | ibev.element.port_num = 1; |
164 | ib_dispatch_event(&ibev); | |
165 | } | |
166 | break; | |
88621dfe | 167 | } |
fc24fc5e | 168 | |
5ec8c83e AH |
169 | default: |
170 | break; | |
171 | } | |
fc24fc5e AS |
172 | |
173 | return NOTIFY_DONE; | |
174 | } | |
175 | ||
176 | static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, | |
177 | u8 port_num) | |
178 | { | |
179 | struct mlx5_ib_dev *ibdev = to_mdev(device); | |
180 | struct net_device *ndev; | |
181 | ||
88621dfe AH |
182 | ndev = mlx5_lag_get_roce_netdev(ibdev->mdev); |
183 | if (ndev) | |
184 | return ndev; | |
185 | ||
fc24fc5e AS |
186 | /* Ensure ndev does not disappear before we invoke dev_hold() |
187 | */ | |
188 | read_lock(&ibdev->roce.netdev_lock); | |
189 | ndev = ibdev->roce.netdev; | |
190 | if (ndev) | |
191 | dev_hold(ndev); | |
192 | read_unlock(&ibdev->roce.netdev_lock); | |
193 | ||
194 | return ndev; | |
195 | } | |
196 | ||
f1b65df5 NO |
197 | static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, |
198 | u8 *active_width) | |
199 | { | |
200 | switch (eth_proto_oper) { | |
201 | case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): | |
202 | case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): | |
203 | case MLX5E_PROT_MASK(MLX5E_100BASE_TX): | |
204 | case MLX5E_PROT_MASK(MLX5E_1000BASE_T): | |
205 | *active_width = IB_WIDTH_1X; | |
206 | *active_speed = IB_SPEED_SDR; | |
207 | break; | |
208 | case MLX5E_PROT_MASK(MLX5E_10GBASE_T): | |
209 | case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): | |
210 | case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): | |
211 | case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): | |
212 | case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): | |
213 | case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): | |
214 | case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): | |
215 | *active_width = IB_WIDTH_1X; | |
216 | *active_speed = IB_SPEED_QDR; | |
217 | break; | |
218 | case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): | |
219 | case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): | |
220 | case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): | |
221 | *active_width = IB_WIDTH_1X; | |
222 | *active_speed = IB_SPEED_EDR; | |
223 | break; | |
224 | case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): | |
225 | case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): | |
226 | case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): | |
227 | case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): | |
228 | *active_width = IB_WIDTH_4X; | |
229 | *active_speed = IB_SPEED_QDR; | |
230 | break; | |
231 | case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): | |
232 | case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): | |
233 | case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): | |
234 | *active_width = IB_WIDTH_1X; | |
235 | *active_speed = IB_SPEED_HDR; | |
236 | break; | |
237 | case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): | |
238 | *active_width = IB_WIDTH_4X; | |
239 | *active_speed = IB_SPEED_FDR; | |
240 | break; | |
241 | case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): | |
242 | case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): | |
243 | case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): | |
244 | case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): | |
245 | *active_width = IB_WIDTH_4X; | |
246 | *active_speed = IB_SPEED_EDR; | |
247 | break; | |
248 | default: | |
249 | return -EINVAL; | |
250 | } | |
251 | ||
252 | return 0; | |
253 | } | |
254 | ||
095b0927 IT |
255 | static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, |
256 | struct ib_port_attr *props) | |
3f89a643 AS |
257 | { |
258 | struct mlx5_ib_dev *dev = to_mdev(device); | |
f1b65df5 | 259 | struct mlx5_core_dev *mdev = dev->mdev; |
88621dfe | 260 | struct net_device *ndev, *upper; |
3f89a643 | 261 | enum ib_mtu ndev_ib_mtu; |
c876a1b7 | 262 | u16 qkey_viol_cntr; |
f1b65df5 | 263 | u32 eth_prot_oper; |
095b0927 | 264 | int err; |
3f89a643 | 265 | |
f1b65df5 NO |
266 | /* Possible bad flows are checked before filling out props so in case |
267 | * of an error it will still be zeroed out. | |
50f22fd8 | 268 | */ |
095b0927 IT |
269 | err = mlx5_query_port_eth_proto_oper(mdev, ð_prot_oper, port_num); |
270 | if (err) | |
271 | return err; | |
f1b65df5 NO |
272 | |
273 | translate_eth_proto_oper(eth_prot_oper, &props->active_speed, | |
274 | &props->active_width); | |
3f89a643 AS |
275 | |
276 | props->port_cap_flags |= IB_PORT_CM_SUP; | |
277 | props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; | |
278 | ||
279 | props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, | |
280 | roce_address_table_size); | |
281 | props->max_mtu = IB_MTU_4096; | |
282 | props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); | |
283 | props->pkey_tbl_len = 1; | |
284 | props->state = IB_PORT_DOWN; | |
285 | props->phys_state = 3; | |
286 | ||
c876a1b7 LR |
287 | mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr); |
288 | props->qkey_viol_cntr = qkey_viol_cntr; | |
3f89a643 AS |
289 | |
290 | ndev = mlx5_ib_get_netdev(device, port_num); | |
291 | if (!ndev) | |
095b0927 | 292 | return 0; |
3f89a643 | 293 | |
88621dfe AH |
294 | if (mlx5_lag_is_active(dev->mdev)) { |
295 | rcu_read_lock(); | |
296 | upper = netdev_master_upper_dev_get_rcu(ndev); | |
297 | if (upper) { | |
298 | dev_put(ndev); | |
299 | ndev = upper; | |
300 | dev_hold(ndev); | |
301 | } | |
302 | rcu_read_unlock(); | |
303 | } | |
304 | ||
3f89a643 AS |
305 | if (netif_running(ndev) && netif_carrier_ok(ndev)) { |
306 | props->state = IB_PORT_ACTIVE; | |
307 | props->phys_state = 5; | |
308 | } | |
309 | ||
310 | ndev_ib_mtu = iboe_get_mtu(ndev->mtu); | |
311 | ||
312 | dev_put(ndev); | |
313 | ||
314 | props->active_mtu = min(props->max_mtu, ndev_ib_mtu); | |
095b0927 | 315 | return 0; |
3f89a643 AS |
316 | } |
317 | ||
095b0927 IT |
318 | static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, |
319 | unsigned int index, const union ib_gid *gid, | |
320 | const struct ib_gid_attr *attr) | |
3cca2606 | 321 | { |
095b0927 IT |
322 | enum ib_gid_type gid_type = IB_GID_TYPE_IB; |
323 | u8 roce_version = 0; | |
324 | u8 roce_l3_type = 0; | |
325 | bool vlan = false; | |
326 | u8 mac[ETH_ALEN]; | |
327 | u16 vlan_id = 0; | |
328 | ||
329 | if (gid) { | |
330 | gid_type = attr->gid_type; | |
331 | ether_addr_copy(mac, attr->ndev->dev_addr); | |
332 | ||
333 | if (is_vlan_dev(attr->ndev)) { | |
334 | vlan = true; | |
335 | vlan_id = vlan_dev_vlan_id(attr->ndev); | |
336 | } | |
3cca2606 AS |
337 | } |
338 | ||
095b0927 | 339 | switch (gid_type) { |
3cca2606 | 340 | case IB_GID_TYPE_IB: |
095b0927 | 341 | roce_version = MLX5_ROCE_VERSION_1; |
3cca2606 AS |
342 | break; |
343 | case IB_GID_TYPE_ROCE_UDP_ENCAP: | |
095b0927 IT |
344 | roce_version = MLX5_ROCE_VERSION_2; |
345 | if (ipv6_addr_v4mapped((void *)gid)) | |
346 | roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; | |
347 | else | |
348 | roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; | |
3cca2606 AS |
349 | break; |
350 | ||
351 | default: | |
095b0927 | 352 | mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); |
3cca2606 AS |
353 | } |
354 | ||
095b0927 IT |
355 | return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, |
356 | roce_l3_type, gid->raw, mac, vlan, | |
357 | vlan_id); | |
3cca2606 AS |
358 | } |
359 | ||
360 | static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, | |
361 | unsigned int index, const union ib_gid *gid, | |
362 | const struct ib_gid_attr *attr, | |
363 | __always_unused void **context) | |
364 | { | |
095b0927 | 365 | return set_roce_addr(to_mdev(device), port_num, index, gid, attr); |
3cca2606 AS |
366 | } |
367 | ||
368 | static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, | |
369 | unsigned int index, __always_unused void **context) | |
370 | { | |
095b0927 | 371 | return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL); |
3cca2606 AS |
372 | } |
373 | ||
2811ba51 AS |
374 | __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, |
375 | int index) | |
376 | { | |
377 | struct ib_gid_attr attr; | |
378 | union ib_gid gid; | |
379 | ||
380 | if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) | |
381 | return 0; | |
382 | ||
383 | if (!attr.ndev) | |
384 | return 0; | |
385 | ||
386 | dev_put(attr.ndev); | |
387 | ||
388 | if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) | |
389 | return 0; | |
390 | ||
391 | return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); | |
392 | } | |
393 | ||
ed88451e MD |
394 | int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, |
395 | int index, enum ib_gid_type *gid_type) | |
396 | { | |
397 | struct ib_gid_attr attr; | |
398 | union ib_gid gid; | |
399 | int ret; | |
400 | ||
401 | ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr); | |
402 | if (ret) | |
403 | return ret; | |
404 | ||
405 | if (!attr.ndev) | |
406 | return -ENODEV; | |
407 | ||
408 | dev_put(attr.ndev); | |
409 | ||
410 | *gid_type = attr.gid_type; | |
411 | ||
412 | return 0; | |
413 | } | |
414 | ||
1b5daf11 MD |
415 | static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) |
416 | { | |
7fae6655 NO |
417 | if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) |
418 | return !MLX5_CAP_GEN(dev->mdev, ib_virt); | |
419 | return 0; | |
1b5daf11 MD |
420 | } |
421 | ||
422 | enum { | |
423 | MLX5_VPORT_ACCESS_METHOD_MAD, | |
424 | MLX5_VPORT_ACCESS_METHOD_HCA, | |
425 | MLX5_VPORT_ACCESS_METHOD_NIC, | |
426 | }; | |
427 | ||
428 | static int mlx5_get_vport_access_method(struct ib_device *ibdev) | |
429 | { | |
430 | if (mlx5_use_mad_ifc(to_mdev(ibdev))) | |
431 | return MLX5_VPORT_ACCESS_METHOD_MAD; | |
432 | ||
ebd61f68 | 433 | if (mlx5_ib_port_link_layer(ibdev, 1) == |
1b5daf11 MD |
434 | IB_LINK_LAYER_ETHERNET) |
435 | return MLX5_VPORT_ACCESS_METHOD_NIC; | |
436 | ||
437 | return MLX5_VPORT_ACCESS_METHOD_HCA; | |
438 | } | |
439 | ||
da7525d2 EBE |
440 | static void get_atomic_caps(struct mlx5_ib_dev *dev, |
441 | struct ib_device_attr *props) | |
442 | { | |
443 | u8 tmp; | |
444 | u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); | |
445 | u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); | |
446 | u8 atomic_req_8B_endianness_mode = | |
bd10838a | 447 | MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); |
da7525d2 EBE |
448 | |
449 | /* Check if HW supports 8 bytes standard atomic operations and capable | |
450 | * of host endianness respond | |
451 | */ | |
452 | tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; | |
453 | if (((atomic_operations & tmp) == tmp) && | |
454 | (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && | |
455 | (atomic_req_8B_endianness_mode)) { | |
456 | props->atomic_cap = IB_ATOMIC_HCA; | |
457 | } else { | |
458 | props->atomic_cap = IB_ATOMIC_NONE; | |
459 | } | |
460 | } | |
461 | ||
1b5daf11 MD |
462 | static int mlx5_query_system_image_guid(struct ib_device *ibdev, |
463 | __be64 *sys_image_guid) | |
464 | { | |
465 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
466 | struct mlx5_core_dev *mdev = dev->mdev; | |
467 | u64 tmp; | |
468 | int err; | |
469 | ||
470 | switch (mlx5_get_vport_access_method(ibdev)) { | |
471 | case MLX5_VPORT_ACCESS_METHOD_MAD: | |
472 | return mlx5_query_mad_ifc_system_image_guid(ibdev, | |
473 | sys_image_guid); | |
474 | ||
475 | case MLX5_VPORT_ACCESS_METHOD_HCA: | |
476 | err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); | |
3f89a643 AS |
477 | break; |
478 | ||
479 | case MLX5_VPORT_ACCESS_METHOD_NIC: | |
480 | err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); | |
481 | break; | |
1b5daf11 MD |
482 | |
483 | default: | |
484 | return -EINVAL; | |
485 | } | |
3f89a643 AS |
486 | |
487 | if (!err) | |
488 | *sys_image_guid = cpu_to_be64(tmp); | |
489 | ||
490 | return err; | |
491 | ||
1b5daf11 MD |
492 | } |
493 | ||
494 | static int mlx5_query_max_pkeys(struct ib_device *ibdev, | |
495 | u16 *max_pkeys) | |
496 | { | |
497 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
498 | struct mlx5_core_dev *mdev = dev->mdev; | |
499 | ||
500 | switch (mlx5_get_vport_access_method(ibdev)) { | |
501 | case MLX5_VPORT_ACCESS_METHOD_MAD: | |
502 | return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); | |
503 | ||
504 | case MLX5_VPORT_ACCESS_METHOD_HCA: | |
505 | case MLX5_VPORT_ACCESS_METHOD_NIC: | |
506 | *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, | |
507 | pkey_table_size)); | |
508 | return 0; | |
509 | ||
510 | default: | |
511 | return -EINVAL; | |
512 | } | |
513 | } | |
514 | ||
515 | static int mlx5_query_vendor_id(struct ib_device *ibdev, | |
516 | u32 *vendor_id) | |
517 | { | |
518 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
519 | ||
520 | switch (mlx5_get_vport_access_method(ibdev)) { | |
521 | case MLX5_VPORT_ACCESS_METHOD_MAD: | |
522 | return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); | |
523 | ||
524 | case MLX5_VPORT_ACCESS_METHOD_HCA: | |
525 | case MLX5_VPORT_ACCESS_METHOD_NIC: | |
526 | return mlx5_core_query_vendor_id(dev->mdev, vendor_id); | |
527 | ||
528 | default: | |
529 | return -EINVAL; | |
530 | } | |
531 | } | |
532 | ||
533 | static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, | |
534 | __be64 *node_guid) | |
535 | { | |
536 | u64 tmp; | |
537 | int err; | |
538 | ||
539 | switch (mlx5_get_vport_access_method(&dev->ib_dev)) { | |
540 | case MLX5_VPORT_ACCESS_METHOD_MAD: | |
541 | return mlx5_query_mad_ifc_node_guid(dev, node_guid); | |
542 | ||
543 | case MLX5_VPORT_ACCESS_METHOD_HCA: | |
544 | err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); | |
3f89a643 AS |
545 | break; |
546 | ||
547 | case MLX5_VPORT_ACCESS_METHOD_NIC: | |
548 | err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); | |
549 | break; | |
1b5daf11 MD |
550 | |
551 | default: | |
552 | return -EINVAL; | |
553 | } | |
3f89a643 AS |
554 | |
555 | if (!err) | |
556 | *node_guid = cpu_to_be64(tmp); | |
557 | ||
558 | return err; | |
1b5daf11 MD |
559 | } |
560 | ||
561 | struct mlx5_reg_node_desc { | |
bd99fdea | 562 | u8 desc[IB_DEVICE_NODE_DESC_MAX]; |
1b5daf11 MD |
563 | }; |
564 | ||
565 | static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) | |
566 | { | |
567 | struct mlx5_reg_node_desc in; | |
568 | ||
569 | if (mlx5_use_mad_ifc(dev)) | |
570 | return mlx5_query_mad_ifc_node_desc(dev, node_desc); | |
571 | ||
572 | memset(&in, 0, sizeof(in)); | |
573 | ||
574 | return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, | |
575 | sizeof(struct mlx5_reg_node_desc), | |
576 | MLX5_REG_NODE_DESC, 0, 0); | |
577 | } | |
578 | ||
e126ba97 | 579 | static int mlx5_ib_query_device(struct ib_device *ibdev, |
2528e33e MB |
580 | struct ib_device_attr *props, |
581 | struct ib_udata *uhw) | |
e126ba97 EC |
582 | { |
583 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
938fe83c | 584 | struct mlx5_core_dev *mdev = dev->mdev; |
e126ba97 | 585 | int err = -ENOMEM; |
288c01b7 | 586 | int max_sq_desc; |
e126ba97 EC |
587 | int max_rq_sg; |
588 | int max_sq_sg; | |
e0238a6a | 589 | u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); |
402ca536 BW |
590 | struct mlx5_ib_query_device_resp resp = {}; |
591 | size_t resp_len; | |
592 | u64 max_tso; | |
e126ba97 | 593 | |
402ca536 BW |
594 | resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); |
595 | if (uhw->outlen && uhw->outlen < resp_len) | |
596 | return -EINVAL; | |
597 | else | |
598 | resp.response_length = resp_len; | |
599 | ||
600 | if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) | |
2528e33e MB |
601 | return -EINVAL; |
602 | ||
1b5daf11 MD |
603 | memset(props, 0, sizeof(*props)); |
604 | err = mlx5_query_system_image_guid(ibdev, | |
605 | &props->sys_image_guid); | |
606 | if (err) | |
607 | return err; | |
e126ba97 | 608 | |
1b5daf11 | 609 | err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); |
e126ba97 | 610 | if (err) |
1b5daf11 | 611 | return err; |
e126ba97 | 612 | |
1b5daf11 MD |
613 | err = mlx5_query_vendor_id(ibdev, &props->vendor_id); |
614 | if (err) | |
615 | return err; | |
e126ba97 | 616 | |
9603b61d JM |
617 | props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | |
618 | (fw_rev_min(dev->mdev) << 16) | | |
619 | fw_rev_sub(dev->mdev); | |
e126ba97 EC |
620 | props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | |
621 | IB_DEVICE_PORT_ACTIVE_EVENT | | |
622 | IB_DEVICE_SYS_IMAGE_GUID | | |
1a4c3a3d | 623 | IB_DEVICE_RC_RNR_NAK_GEN; |
938fe83c SM |
624 | |
625 | if (MLX5_CAP_GEN(mdev, pkv)) | |
e126ba97 | 626 | props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; |
938fe83c | 627 | if (MLX5_CAP_GEN(mdev, qkv)) |
e126ba97 | 628 | props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; |
938fe83c | 629 | if (MLX5_CAP_GEN(mdev, apm)) |
e126ba97 | 630 | props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; |
938fe83c | 631 | if (MLX5_CAP_GEN(mdev, xrc)) |
e126ba97 | 632 | props->device_cap_flags |= IB_DEVICE_XRC; |
d2370e0a MB |
633 | if (MLX5_CAP_GEN(mdev, imaicl)) { |
634 | props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | | |
635 | IB_DEVICE_MEM_WINDOW_TYPE_2B; | |
636 | props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); | |
b005d316 SG |
637 | /* We support 'Gappy' memory registration too */ |
638 | props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; | |
d2370e0a | 639 | } |
e126ba97 | 640 | props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; |
938fe83c | 641 | if (MLX5_CAP_GEN(mdev, sho)) { |
2dea9094 SG |
642 | props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; |
643 | /* At this stage no support for signature handover */ | |
644 | props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | | |
645 | IB_PROT_T10DIF_TYPE_2 | | |
646 | IB_PROT_T10DIF_TYPE_3; | |
647 | props->sig_guard_cap = IB_GUARD_T10DIF_CRC | | |
648 | IB_GUARD_T10DIF_CSUM; | |
649 | } | |
938fe83c | 650 | if (MLX5_CAP_GEN(mdev, block_lb_mc)) |
f360d88a | 651 | props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; |
e126ba97 | 652 | |
402ca536 | 653 | if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) { |
e8161334 NO |
654 | if (MLX5_CAP_ETH(mdev, csum_cap)) { |
655 | /* Legacy bit to support old userspace libraries */ | |
88115fe7 | 656 | props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; |
e8161334 NO |
657 | props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; |
658 | } | |
659 | ||
660 | if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) | |
661 | props->raw_packet_caps |= | |
662 | IB_RAW_PACKET_CAP_CVLAN_STRIPPING; | |
88115fe7 | 663 | |
402ca536 BW |
664 | if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { |
665 | max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); | |
666 | if (max_tso) { | |
667 | resp.tso_caps.max_tso = 1 << max_tso; | |
668 | resp.tso_caps.supported_qpts |= | |
669 | 1 << IB_QPT_RAW_PACKET; | |
670 | resp.response_length += sizeof(resp.tso_caps); | |
671 | } | |
672 | } | |
31f69a82 YH |
673 | |
674 | if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { | |
675 | resp.rss_caps.rx_hash_function = | |
676 | MLX5_RX_HASH_FUNC_TOEPLITZ; | |
677 | resp.rss_caps.rx_hash_fields_mask = | |
678 | MLX5_RX_HASH_SRC_IPV4 | | |
679 | MLX5_RX_HASH_DST_IPV4 | | |
680 | MLX5_RX_HASH_SRC_IPV6 | | |
681 | MLX5_RX_HASH_DST_IPV6 | | |
682 | MLX5_RX_HASH_SRC_PORT_TCP | | |
683 | MLX5_RX_HASH_DST_PORT_TCP | | |
684 | MLX5_RX_HASH_SRC_PORT_UDP | | |
685 | MLX5_RX_HASH_DST_PORT_UDP; | |
686 | resp.response_length += sizeof(resp.rss_caps); | |
687 | } | |
688 | } else { | |
689 | if (field_avail(typeof(resp), tso_caps, uhw->outlen)) | |
690 | resp.response_length += sizeof(resp.tso_caps); | |
691 | if (field_avail(typeof(resp), rss_caps, uhw->outlen)) | |
692 | resp.response_length += sizeof(resp.rss_caps); | |
402ca536 BW |
693 | } |
694 | ||
f0313965 ES |
695 | if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { |
696 | props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; | |
697 | props->device_cap_flags |= IB_DEVICE_UD_TSO; | |
698 | } | |
699 | ||
03404e8a MG |
700 | if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && |
701 | MLX5_CAP_GEN(dev->mdev, general_notification_event)) | |
702 | props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; | |
703 | ||
1d54f890 YH |
704 | if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && |
705 | MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) | |
706 | props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; | |
707 | ||
cff5a0f3 | 708 | if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && |
e8161334 NO |
709 | MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { |
710 | /* Legacy bit to support old userspace libraries */ | |
cff5a0f3 | 711 | props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; |
e8161334 NO |
712 | props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; |
713 | } | |
cff5a0f3 | 714 | |
da6d6ba3 MG |
715 | if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) |
716 | props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; | |
717 | ||
b1383aa6 NO |
718 | if (MLX5_CAP_GEN(mdev, end_pad)) |
719 | props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; | |
720 | ||
1b5daf11 MD |
721 | props->vendor_part_id = mdev->pdev->device; |
722 | props->hw_ver = mdev->pdev->revision; | |
e126ba97 EC |
723 | |
724 | props->max_mr_size = ~0ull; | |
e0238a6a | 725 | props->page_size_cap = ~(min_page_size - 1); |
938fe83c SM |
726 | props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); |
727 | props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); | |
728 | max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / | |
729 | sizeof(struct mlx5_wqe_data_seg); | |
288c01b7 EC |
730 | max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); |
731 | max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - | |
732 | sizeof(struct mlx5_wqe_raddr_seg)) / | |
733 | sizeof(struct mlx5_wqe_data_seg); | |
e126ba97 | 734 | props->max_sge = min(max_rq_sg, max_sq_sg); |
986ef95e | 735 | props->max_sge_rd = MLX5_MAX_SGE_RD; |
938fe83c | 736 | props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); |
9f177686 | 737 | props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; |
938fe83c SM |
738 | props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); |
739 | props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); | |
740 | props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); | |
741 | props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); | |
742 | props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); | |
743 | props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; | |
744 | props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); | |
e126ba97 | 745 | props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; |
e126ba97 | 746 | props->max_srq_sge = max_rq_sg - 1; |
911f4331 SG |
747 | props->max_fast_reg_page_list_len = |
748 | 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); | |
da7525d2 | 749 | get_atomic_caps(dev, props); |
81bea28f | 750 | props->masked_atomic_cap = IB_ATOMIC_NONE; |
938fe83c SM |
751 | props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); |
752 | props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); | |
e126ba97 EC |
753 | props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * |
754 | props->max_mcast_grp; | |
755 | props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ | |
86695a65 | 756 | props->max_ah = INT_MAX; |
7c60bcbb MB |
757 | props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); |
758 | props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; | |
e126ba97 | 759 | |
8cdd312c | 760 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
938fe83c | 761 | if (MLX5_CAP_GEN(mdev, pg)) |
8cdd312c HE |
762 | props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; |
763 | props->odp_caps = dev->odp_caps; | |
764 | #endif | |
765 | ||
051f2630 LR |
766 | if (MLX5_CAP_GEN(mdev, cd)) |
767 | props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; | |
768 | ||
eff901d3 EC |
769 | if (!mlx5_core_is_pf(mdev)) |
770 | props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; | |
771 | ||
31f69a82 YH |
772 | if (mlx5_ib_port_link_layer(ibdev, 1) == |
773 | IB_LINK_LAYER_ETHERNET) { | |
774 | props->rss_caps.max_rwq_indirection_tables = | |
775 | 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); | |
776 | props->rss_caps.max_rwq_indirection_table_size = | |
777 | 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); | |
778 | props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; | |
779 | props->max_wq_type_rq = | |
780 | 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); | |
781 | } | |
782 | ||
eb761894 | 783 | if (MLX5_CAP_GEN(mdev, tag_matching)) { |
78b1beb0 LR |
784 | props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; |
785 | props->tm_caps.max_num_tags = | |
eb761894 | 786 | (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; |
78b1beb0 LR |
787 | props->tm_caps.flags = IB_TM_CAP_RC; |
788 | props->tm_caps.max_ops = | |
eb761894 | 789 | 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); |
78b1beb0 | 790 | props->tm_caps.max_sge = MLX5_TM_MAX_SGE; |
eb761894 AK |
791 | } |
792 | ||
87ab3f52 YC |
793 | if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { |
794 | props->cq_caps.max_cq_moderation_count = | |
795 | MLX5_MAX_CQ_COUNT; | |
796 | props->cq_caps.max_cq_moderation_period = | |
797 | MLX5_MAX_CQ_PERIOD; | |
798 | } | |
799 | ||
7e43a2a5 BW |
800 | if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) { |
801 | resp.cqe_comp_caps.max_num = | |
802 | MLX5_CAP_GEN(dev->mdev, cqe_compression) ? | |
803 | MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0; | |
804 | resp.cqe_comp_caps.supported_format = | |
805 | MLX5_IB_CQE_RES_FORMAT_HASH | | |
806 | MLX5_IB_CQE_RES_FORMAT_CSUM; | |
807 | resp.response_length += sizeof(resp.cqe_comp_caps); | |
808 | } | |
809 | ||
d949167d BW |
810 | if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) { |
811 | if (MLX5_CAP_QOS(mdev, packet_pacing) && | |
812 | MLX5_CAP_GEN(mdev, qos)) { | |
813 | resp.packet_pacing_caps.qp_rate_limit_max = | |
814 | MLX5_CAP_QOS(mdev, packet_pacing_max_rate); | |
815 | resp.packet_pacing_caps.qp_rate_limit_min = | |
816 | MLX5_CAP_QOS(mdev, packet_pacing_min_rate); | |
817 | resp.packet_pacing_caps.supported_qpts |= | |
818 | 1 << IB_QPT_RAW_PACKET; | |
819 | } | |
820 | resp.response_length += sizeof(resp.packet_pacing_caps); | |
821 | } | |
822 | ||
9f885201 LR |
823 | if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes, |
824 | uhw->outlen)) { | |
795b609c BW |
825 | if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) |
826 | resp.mlx5_ib_support_multi_pkt_send_wqes = | |
827 | MLX5_IB_ALLOW_MPW; | |
050da902 BW |
828 | |
829 | if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) | |
830 | resp.mlx5_ib_support_multi_pkt_send_wqes |= | |
831 | MLX5_IB_SUPPORT_EMPW; | |
832 | ||
9f885201 LR |
833 | resp.response_length += |
834 | sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); | |
835 | } | |
836 | ||
de57f2ad GL |
837 | if (field_avail(typeof(resp), flags, uhw->outlen)) { |
838 | resp.response_length += sizeof(resp.flags); | |
7a0c8f42 | 839 | |
de57f2ad GL |
840 | if (MLX5_CAP_GEN(mdev, cqe_compression_128)) |
841 | resp.flags |= | |
842 | MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; | |
7a0c8f42 GL |
843 | |
844 | if (MLX5_CAP_GEN(mdev, cqe_128_always)) | |
845 | resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; | |
de57f2ad | 846 | } |
9f885201 | 847 | |
96dc3fc5 NO |
848 | if (field_avail(typeof(resp), sw_parsing_caps, |
849 | uhw->outlen)) { | |
850 | resp.response_length += sizeof(resp.sw_parsing_caps); | |
851 | if (MLX5_CAP_ETH(mdev, swp)) { | |
852 | resp.sw_parsing_caps.sw_parsing_offloads |= | |
853 | MLX5_IB_SW_PARSING; | |
854 | ||
855 | if (MLX5_CAP_ETH(mdev, swp_csum)) | |
856 | resp.sw_parsing_caps.sw_parsing_offloads |= | |
857 | MLX5_IB_SW_PARSING_CSUM; | |
858 | ||
859 | if (MLX5_CAP_ETH(mdev, swp_lso)) | |
860 | resp.sw_parsing_caps.sw_parsing_offloads |= | |
861 | MLX5_IB_SW_PARSING_LSO; | |
862 | ||
863 | if (resp.sw_parsing_caps.sw_parsing_offloads) | |
864 | resp.sw_parsing_caps.supported_qpts = | |
865 | BIT(IB_QPT_RAW_PACKET); | |
866 | } | |
867 | } | |
868 | ||
b4f34597 NO |
869 | if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen)) { |
870 | resp.response_length += sizeof(resp.striding_rq_caps); | |
871 | if (MLX5_CAP_GEN(mdev, striding_rq)) { | |
872 | resp.striding_rq_caps.min_single_stride_log_num_of_bytes = | |
873 | MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; | |
874 | resp.striding_rq_caps.max_single_stride_log_num_of_bytes = | |
875 | MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; | |
876 | resp.striding_rq_caps.min_single_wqe_log_num_of_strides = | |
877 | MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; | |
878 | resp.striding_rq_caps.max_single_wqe_log_num_of_strides = | |
879 | MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; | |
880 | resp.striding_rq_caps.supported_qpts = | |
881 | BIT(IB_QPT_RAW_PACKET); | |
882 | } | |
883 | } | |
884 | ||
f95ef6cb MG |
885 | if (field_avail(typeof(resp), tunnel_offloads_caps, |
886 | uhw->outlen)) { | |
887 | resp.response_length += sizeof(resp.tunnel_offloads_caps); | |
888 | if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) | |
889 | resp.tunnel_offloads_caps |= | |
890 | MLX5_IB_TUNNELED_OFFLOADS_VXLAN; | |
891 | if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) | |
892 | resp.tunnel_offloads_caps |= | |
893 | MLX5_IB_TUNNELED_OFFLOADS_GENEVE; | |
894 | if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) | |
895 | resp.tunnel_offloads_caps |= | |
896 | MLX5_IB_TUNNELED_OFFLOADS_GRE; | |
897 | } | |
898 | ||
402ca536 BW |
899 | if (uhw->outlen) { |
900 | err = ib_copy_to_udata(uhw, &resp, resp.response_length); | |
901 | ||
902 | if (err) | |
903 | return err; | |
904 | } | |
905 | ||
1b5daf11 | 906 | return 0; |
e126ba97 EC |
907 | } |
908 | ||
1b5daf11 MD |
909 | enum mlx5_ib_width { |
910 | MLX5_IB_WIDTH_1X = 1 << 0, | |
911 | MLX5_IB_WIDTH_2X = 1 << 1, | |
912 | MLX5_IB_WIDTH_4X = 1 << 2, | |
913 | MLX5_IB_WIDTH_8X = 1 << 3, | |
914 | MLX5_IB_WIDTH_12X = 1 << 4 | |
915 | }; | |
916 | ||
917 | static int translate_active_width(struct ib_device *ibdev, u8 active_width, | |
918 | u8 *ib_width) | |
e126ba97 EC |
919 | { |
920 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
1b5daf11 MD |
921 | int err = 0; |
922 | ||
923 | if (active_width & MLX5_IB_WIDTH_1X) { | |
924 | *ib_width = IB_WIDTH_1X; | |
925 | } else if (active_width & MLX5_IB_WIDTH_2X) { | |
926 | mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", | |
927 | (int)active_width); | |
928 | err = -EINVAL; | |
929 | } else if (active_width & MLX5_IB_WIDTH_4X) { | |
930 | *ib_width = IB_WIDTH_4X; | |
931 | } else if (active_width & MLX5_IB_WIDTH_8X) { | |
932 | *ib_width = IB_WIDTH_8X; | |
933 | } else if (active_width & MLX5_IB_WIDTH_12X) { | |
934 | *ib_width = IB_WIDTH_12X; | |
935 | } else { | |
936 | mlx5_ib_dbg(dev, "Invalid active_width %d\n", | |
937 | (int)active_width); | |
938 | err = -EINVAL; | |
e126ba97 EC |
939 | } |
940 | ||
1b5daf11 MD |
941 | return err; |
942 | } | |
e126ba97 | 943 | |
1b5daf11 MD |
944 | static int mlx5_mtu_to_ib_mtu(int mtu) |
945 | { | |
946 | switch (mtu) { | |
947 | case 256: return 1; | |
948 | case 512: return 2; | |
949 | case 1024: return 3; | |
950 | case 2048: return 4; | |
951 | case 4096: return 5; | |
952 | default: | |
953 | pr_warn("invalid mtu\n"); | |
954 | return -1; | |
e126ba97 | 955 | } |
1b5daf11 | 956 | } |
e126ba97 | 957 | |
1b5daf11 MD |
958 | enum ib_max_vl_num { |
959 | __IB_MAX_VL_0 = 1, | |
960 | __IB_MAX_VL_0_1 = 2, | |
961 | __IB_MAX_VL_0_3 = 3, | |
962 | __IB_MAX_VL_0_7 = 4, | |
963 | __IB_MAX_VL_0_14 = 5, | |
964 | }; | |
e126ba97 | 965 | |
1b5daf11 MD |
966 | enum mlx5_vl_hw_cap { |
967 | MLX5_VL_HW_0 = 1, | |
968 | MLX5_VL_HW_0_1 = 2, | |
969 | MLX5_VL_HW_0_2 = 3, | |
970 | MLX5_VL_HW_0_3 = 4, | |
971 | MLX5_VL_HW_0_4 = 5, | |
972 | MLX5_VL_HW_0_5 = 6, | |
973 | MLX5_VL_HW_0_6 = 7, | |
974 | MLX5_VL_HW_0_7 = 8, | |
975 | MLX5_VL_HW_0_14 = 15 | |
976 | }; | |
e126ba97 | 977 | |
1b5daf11 MD |
978 | static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, |
979 | u8 *max_vl_num) | |
980 | { | |
981 | switch (vl_hw_cap) { | |
982 | case MLX5_VL_HW_0: | |
983 | *max_vl_num = __IB_MAX_VL_0; | |
984 | break; | |
985 | case MLX5_VL_HW_0_1: | |
986 | *max_vl_num = __IB_MAX_VL_0_1; | |
987 | break; | |
988 | case MLX5_VL_HW_0_3: | |
989 | *max_vl_num = __IB_MAX_VL_0_3; | |
990 | break; | |
991 | case MLX5_VL_HW_0_7: | |
992 | *max_vl_num = __IB_MAX_VL_0_7; | |
993 | break; | |
994 | case MLX5_VL_HW_0_14: | |
995 | *max_vl_num = __IB_MAX_VL_0_14; | |
996 | break; | |
e126ba97 | 997 | |
1b5daf11 MD |
998 | default: |
999 | return -EINVAL; | |
e126ba97 | 1000 | } |
e126ba97 | 1001 | |
1b5daf11 | 1002 | return 0; |
e126ba97 EC |
1003 | } |
1004 | ||
1b5daf11 MD |
1005 | static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, |
1006 | struct ib_port_attr *props) | |
e126ba97 | 1007 | { |
1b5daf11 MD |
1008 | struct mlx5_ib_dev *dev = to_mdev(ibdev); |
1009 | struct mlx5_core_dev *mdev = dev->mdev; | |
1010 | struct mlx5_hca_vport_context *rep; | |
046339ea SM |
1011 | u16 max_mtu; |
1012 | u16 oper_mtu; | |
1b5daf11 MD |
1013 | int err; |
1014 | u8 ib_link_width_oper; | |
1015 | u8 vl_hw_cap; | |
e126ba97 | 1016 | |
1b5daf11 MD |
1017 | rep = kzalloc(sizeof(*rep), GFP_KERNEL); |
1018 | if (!rep) { | |
1019 | err = -ENOMEM; | |
e126ba97 | 1020 | goto out; |
e126ba97 | 1021 | } |
e126ba97 | 1022 | |
c4550c63 | 1023 | /* props being zeroed by the caller, avoid zeroing it here */ |
e126ba97 | 1024 | |
1b5daf11 | 1025 | err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); |
e126ba97 EC |
1026 | if (err) |
1027 | goto out; | |
1028 | ||
1b5daf11 MD |
1029 | props->lid = rep->lid; |
1030 | props->lmc = rep->lmc; | |
1031 | props->sm_lid = rep->sm_lid; | |
1032 | props->sm_sl = rep->sm_sl; | |
1033 | props->state = rep->vport_state; | |
1034 | props->phys_state = rep->port_physical_state; | |
1035 | props->port_cap_flags = rep->cap_mask1; | |
1036 | props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); | |
1037 | props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); | |
1038 | props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); | |
1039 | props->bad_pkey_cntr = rep->pkey_violation_counter; | |
1040 | props->qkey_viol_cntr = rep->qkey_violation_counter; | |
1041 | props->subnet_timeout = rep->subnet_timeout; | |
1042 | props->init_type_reply = rep->init_type_reply; | |
eff901d3 | 1043 | props->grh_required = rep->grh_required; |
e126ba97 | 1044 | |
1b5daf11 MD |
1045 | err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); |
1046 | if (err) | |
e126ba97 | 1047 | goto out; |
e126ba97 | 1048 | |
1b5daf11 MD |
1049 | err = translate_active_width(ibdev, ib_link_width_oper, |
1050 | &props->active_width); | |
1051 | if (err) | |
1052 | goto out; | |
d5beb7f2 | 1053 | err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port); |
e126ba97 EC |
1054 | if (err) |
1055 | goto out; | |
1056 | ||
facc9699 | 1057 | mlx5_query_port_max_mtu(mdev, &max_mtu, port); |
e126ba97 | 1058 | |
1b5daf11 | 1059 | props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); |
e126ba97 | 1060 | |
facc9699 | 1061 | mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); |
e126ba97 | 1062 | |
1b5daf11 | 1063 | props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); |
e126ba97 | 1064 | |
1b5daf11 MD |
1065 | err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); |
1066 | if (err) | |
1067 | goto out; | |
e126ba97 | 1068 | |
1b5daf11 MD |
1069 | err = translate_max_vl_num(ibdev, vl_hw_cap, |
1070 | &props->max_vl_num); | |
e126ba97 | 1071 | out: |
1b5daf11 | 1072 | kfree(rep); |
e126ba97 EC |
1073 | return err; |
1074 | } | |
1075 | ||
1b5daf11 MD |
1076 | int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, |
1077 | struct ib_port_attr *props) | |
e126ba97 | 1078 | { |
095b0927 IT |
1079 | unsigned int count; |
1080 | int ret; | |
1081 | ||
1b5daf11 MD |
1082 | switch (mlx5_get_vport_access_method(ibdev)) { |
1083 | case MLX5_VPORT_ACCESS_METHOD_MAD: | |
095b0927 IT |
1084 | ret = mlx5_query_mad_ifc_port(ibdev, port, props); |
1085 | break; | |
e126ba97 | 1086 | |
1b5daf11 | 1087 | case MLX5_VPORT_ACCESS_METHOD_HCA: |
095b0927 IT |
1088 | ret = mlx5_query_hca_port(ibdev, port, props); |
1089 | break; | |
e126ba97 | 1090 | |
3f89a643 | 1091 | case MLX5_VPORT_ACCESS_METHOD_NIC: |
095b0927 IT |
1092 | ret = mlx5_query_port_roce(ibdev, port, props); |
1093 | break; | |
3f89a643 | 1094 | |
1b5daf11 | 1095 | default: |
095b0927 IT |
1096 | ret = -EINVAL; |
1097 | } | |
1098 | ||
1099 | if (!ret && props) { | |
1100 | count = mlx5_core_reserved_gids_count(to_mdev(ibdev)->mdev); | |
1101 | props->gid_tbl_len -= count; | |
1b5daf11 | 1102 | } |
095b0927 | 1103 | return ret; |
1b5daf11 | 1104 | } |
e126ba97 | 1105 | |
1b5daf11 MD |
1106 | static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, |
1107 | union ib_gid *gid) | |
1108 | { | |
1109 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
1110 | struct mlx5_core_dev *mdev = dev->mdev; | |
e126ba97 | 1111 | |
1b5daf11 MD |
1112 | switch (mlx5_get_vport_access_method(ibdev)) { |
1113 | case MLX5_VPORT_ACCESS_METHOD_MAD: | |
1114 | return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); | |
e126ba97 | 1115 | |
1b5daf11 MD |
1116 | case MLX5_VPORT_ACCESS_METHOD_HCA: |
1117 | return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); | |
1118 | ||
1119 | default: | |
1120 | return -EINVAL; | |
1121 | } | |
e126ba97 | 1122 | |
e126ba97 EC |
1123 | } |
1124 | ||
1b5daf11 MD |
1125 | static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, |
1126 | u16 *pkey) | |
1127 | { | |
1128 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
1129 | struct mlx5_core_dev *mdev = dev->mdev; | |
1130 | ||
1131 | switch (mlx5_get_vport_access_method(ibdev)) { | |
1132 | case MLX5_VPORT_ACCESS_METHOD_MAD: | |
1133 | return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); | |
1134 | ||
1135 | case MLX5_VPORT_ACCESS_METHOD_HCA: | |
1136 | case MLX5_VPORT_ACCESS_METHOD_NIC: | |
1137 | return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index, | |
1138 | pkey); | |
1139 | default: | |
1140 | return -EINVAL; | |
1141 | } | |
1142 | } | |
e126ba97 EC |
1143 | |
1144 | static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, | |
1145 | struct ib_device_modify *props) | |
1146 | { | |
1147 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
1148 | struct mlx5_reg_node_desc in; | |
1149 | struct mlx5_reg_node_desc out; | |
1150 | int err; | |
1151 | ||
1152 | if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) | |
1153 | return -EOPNOTSUPP; | |
1154 | ||
1155 | if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) | |
1156 | return 0; | |
1157 | ||
1158 | /* | |
1159 | * If possible, pass node desc to FW, so it can generate | |
1160 | * a 144 trap. If cmd fails, just ignore. | |
1161 | */ | |
bd99fdea | 1162 | memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); |
9603b61d | 1163 | err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, |
e126ba97 EC |
1164 | sizeof(out), MLX5_REG_NODE_DESC, 0, 1); |
1165 | if (err) | |
1166 | return err; | |
1167 | ||
bd99fdea | 1168 | memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); |
e126ba97 EC |
1169 | |
1170 | return err; | |
1171 | } | |
1172 | ||
cdbe33d0 EC |
1173 | static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, |
1174 | u32 value) | |
1175 | { | |
1176 | struct mlx5_hca_vport_context ctx = {}; | |
1177 | int err; | |
1178 | ||
1179 | err = mlx5_query_hca_vport_context(dev->mdev, 0, | |
1180 | port_num, 0, &ctx); | |
1181 | if (err) | |
1182 | return err; | |
1183 | ||
1184 | if (~ctx.cap_mask1_perm & mask) { | |
1185 | mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", | |
1186 | mask, ctx.cap_mask1_perm); | |
1187 | return -EINVAL; | |
1188 | } | |
1189 | ||
1190 | ctx.cap_mask1 = value; | |
1191 | ctx.cap_mask1_perm = mask; | |
1192 | err = mlx5_core_modify_hca_vport_context(dev->mdev, 0, | |
1193 | port_num, 0, &ctx); | |
1194 | ||
1195 | return err; | |
1196 | } | |
1197 | ||
e126ba97 EC |
1198 | static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, |
1199 | struct ib_port_modify *props) | |
1200 | { | |
1201 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
1202 | struct ib_port_attr attr; | |
1203 | u32 tmp; | |
1204 | int err; | |
cdbe33d0 EC |
1205 | u32 change_mask; |
1206 | u32 value; | |
1207 | bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == | |
1208 | IB_LINK_LAYER_INFINIBAND); | |
1209 | ||
ec255879 MD |
1210 | /* CM layer calls ib_modify_port() regardless of the link layer. For |
1211 | * Ethernet ports, qkey violation and Port capabilities are meaningless. | |
1212 | */ | |
1213 | if (!is_ib) | |
1214 | return 0; | |
1215 | ||
cdbe33d0 EC |
1216 | if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { |
1217 | change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; | |
1218 | value = ~props->clr_port_cap_mask | props->set_port_cap_mask; | |
1219 | return set_port_caps_atomic(dev, port, change_mask, value); | |
1220 | } | |
e126ba97 EC |
1221 | |
1222 | mutex_lock(&dev->cap_mask_mutex); | |
1223 | ||
c4550c63 | 1224 | err = ib_query_port(ibdev, port, &attr); |
e126ba97 EC |
1225 | if (err) |
1226 | goto out; | |
1227 | ||
1228 | tmp = (attr.port_cap_flags | props->set_port_cap_mask) & | |
1229 | ~props->clr_port_cap_mask; | |
1230 | ||
9603b61d | 1231 | err = mlx5_set_port_caps(dev->mdev, port, tmp); |
e126ba97 EC |
1232 | |
1233 | out: | |
1234 | mutex_unlock(&dev->cap_mask_mutex); | |
1235 | return err; | |
1236 | } | |
1237 | ||
30aa60b3 EC |
1238 | static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) |
1239 | { | |
1240 | mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", | |
1241 | caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); | |
1242 | } | |
1243 | ||
b037c29a EC |
1244 | static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, |
1245 | struct mlx5_ib_alloc_ucontext_req_v2 *req, | |
1246 | u32 *num_sys_pages) | |
1247 | { | |
1248 | int uars_per_sys_page; | |
1249 | int bfregs_per_sys_page; | |
1250 | int ref_bfregs = req->total_num_bfregs; | |
1251 | ||
1252 | if (req->total_num_bfregs == 0) | |
1253 | return -EINVAL; | |
1254 | ||
1255 | BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); | |
1256 | BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); | |
1257 | ||
1258 | if (req->total_num_bfregs > MLX5_MAX_BFREGS) | |
1259 | return -ENOMEM; | |
1260 | ||
1261 | uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); | |
1262 | bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; | |
1263 | req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); | |
1264 | *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; | |
1265 | ||
1266 | if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) | |
1267 | return -EINVAL; | |
1268 | ||
9c2d33d4 | 1269 | mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, using %d sys pages\n", |
b037c29a EC |
1270 | MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", |
1271 | lib_uar_4k ? "yes" : "no", ref_bfregs, | |
1272 | req->total_num_bfregs, *num_sys_pages); | |
1273 | ||
1274 | return 0; | |
1275 | } | |
1276 | ||
1277 | static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) | |
1278 | { | |
1279 | struct mlx5_bfreg_info *bfregi; | |
1280 | int err; | |
1281 | int i; | |
1282 | ||
1283 | bfregi = &context->bfregi; | |
1284 | for (i = 0; i < bfregi->num_sys_pages; i++) { | |
1285 | err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); | |
1286 | if (err) | |
1287 | goto error; | |
1288 | ||
1289 | mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); | |
1290 | } | |
1291 | return 0; | |
1292 | ||
1293 | error: | |
1294 | for (--i; i >= 0; i--) | |
1295 | if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) | |
1296 | mlx5_ib_warn(dev, "failed to free uar %d\n", i); | |
1297 | ||
1298 | return err; | |
1299 | } | |
1300 | ||
1301 | static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) | |
1302 | { | |
1303 | struct mlx5_bfreg_info *bfregi; | |
1304 | int err; | |
1305 | int i; | |
1306 | ||
1307 | bfregi = &context->bfregi; | |
1308 | for (i = 0; i < bfregi->num_sys_pages; i++) { | |
1309 | err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); | |
1310 | if (err) { | |
1311 | mlx5_ib_warn(dev, "failed to free uar %d\n", i); | |
1312 | return err; | |
1313 | } | |
1314 | } | |
1315 | return 0; | |
1316 | } | |
1317 | ||
c85023e1 HN |
1318 | static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn) |
1319 | { | |
1320 | int err; | |
1321 | ||
1322 | err = mlx5_core_alloc_transport_domain(dev->mdev, tdn); | |
1323 | if (err) | |
1324 | return err; | |
1325 | ||
1326 | if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || | |
1327 | !MLX5_CAP_GEN(dev->mdev, disable_local_lb)) | |
1328 | return err; | |
1329 | ||
1330 | mutex_lock(&dev->lb_mutex); | |
1331 | dev->user_td++; | |
1332 | ||
1333 | if (dev->user_td == 2) | |
1334 | err = mlx5_nic_vport_update_local_lb(dev->mdev, true); | |
1335 | ||
1336 | mutex_unlock(&dev->lb_mutex); | |
1337 | return err; | |
1338 | } | |
1339 | ||
1340 | static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn) | |
1341 | { | |
1342 | mlx5_core_dealloc_transport_domain(dev->mdev, tdn); | |
1343 | ||
1344 | if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || | |
1345 | !MLX5_CAP_GEN(dev->mdev, disable_local_lb)) | |
1346 | return; | |
1347 | ||
1348 | mutex_lock(&dev->lb_mutex); | |
1349 | dev->user_td--; | |
1350 | ||
1351 | if (dev->user_td < 2) | |
1352 | mlx5_nic_vport_update_local_lb(dev->mdev, false); | |
1353 | ||
1354 | mutex_unlock(&dev->lb_mutex); | |
1355 | } | |
1356 | ||
e126ba97 EC |
1357 | static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, |
1358 | struct ib_udata *udata) | |
1359 | { | |
1360 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
b368d7cb MB |
1361 | struct mlx5_ib_alloc_ucontext_req_v2 req = {}; |
1362 | struct mlx5_ib_alloc_ucontext_resp resp = {}; | |
e126ba97 | 1363 | struct mlx5_ib_ucontext *context; |
2f5ff264 | 1364 | struct mlx5_bfreg_info *bfregi; |
78c0f98c | 1365 | int ver; |
e126ba97 | 1366 | int err; |
a168a41c MD |
1367 | size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, |
1368 | max_cqe_version); | |
b037c29a | 1369 | bool lib_uar_4k; |
e126ba97 EC |
1370 | |
1371 | if (!dev->ib_active) | |
1372 | return ERR_PTR(-EAGAIN); | |
1373 | ||
e093111d | 1374 | if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) |
78c0f98c | 1375 | ver = 0; |
e093111d | 1376 | else if (udata->inlen >= min_req_v2) |
78c0f98c EC |
1377 | ver = 2; |
1378 | else | |
1379 | return ERR_PTR(-EINVAL); | |
1380 | ||
e093111d | 1381 | err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); |
e126ba97 EC |
1382 | if (err) |
1383 | return ERR_PTR(err); | |
1384 | ||
b368d7cb | 1385 | if (req.flags) |
78c0f98c EC |
1386 | return ERR_PTR(-EINVAL); |
1387 | ||
f72300c5 | 1388 | if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) |
b368d7cb MB |
1389 | return ERR_PTR(-EOPNOTSUPP); |
1390 | ||
2f5ff264 EC |
1391 | req.total_num_bfregs = ALIGN(req.total_num_bfregs, |
1392 | MLX5_NON_FP_BFREGS_PER_UAR); | |
1393 | if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) | |
e126ba97 EC |
1394 | return ERR_PTR(-EINVAL); |
1395 | ||
938fe83c | 1396 | resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); |
2cc6ad5f NO |
1397 | if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) |
1398 | resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); | |
b47bd6ea | 1399 | resp.cache_line_size = cache_line_size(); |
938fe83c SM |
1400 | resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); |
1401 | resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); | |
1402 | resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); | |
1403 | resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); | |
1404 | resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); | |
f72300c5 HA |
1405 | resp.cqe_version = min_t(__u8, |
1406 | (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), | |
1407 | req.max_cqe_version); | |
30aa60b3 EC |
1408 | resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? |
1409 | MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; | |
1410 | resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? | |
1411 | MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1; | |
b368d7cb MB |
1412 | resp.response_length = min(offsetof(typeof(resp), response_length) + |
1413 | sizeof(resp.response_length), udata->outlen); | |
e126ba97 EC |
1414 | |
1415 | context = kzalloc(sizeof(*context), GFP_KERNEL); | |
1416 | if (!context) | |
1417 | return ERR_PTR(-ENOMEM); | |
1418 | ||
30aa60b3 | 1419 | lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; |
2f5ff264 | 1420 | bfregi = &context->bfregi; |
b037c29a EC |
1421 | |
1422 | /* updates req->total_num_bfregs */ | |
1423 | err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages); | |
1424 | if (err) | |
e126ba97 | 1425 | goto out_ctx; |
e126ba97 | 1426 | |
b037c29a EC |
1427 | mutex_init(&bfregi->lock); |
1428 | bfregi->lib_uar_4k = lib_uar_4k; | |
1429 | bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count), | |
e126ba97 | 1430 | GFP_KERNEL); |
b037c29a | 1431 | if (!bfregi->count) { |
e126ba97 | 1432 | err = -ENOMEM; |
b037c29a | 1433 | goto out_ctx; |
e126ba97 EC |
1434 | } |
1435 | ||
b037c29a EC |
1436 | bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, |
1437 | sizeof(*bfregi->sys_pages), | |
1438 | GFP_KERNEL); | |
1439 | if (!bfregi->sys_pages) { | |
e126ba97 | 1440 | err = -ENOMEM; |
b037c29a | 1441 | goto out_count; |
e126ba97 EC |
1442 | } |
1443 | ||
b037c29a EC |
1444 | err = allocate_uars(dev, context); |
1445 | if (err) | |
1446 | goto out_sys_pages; | |
e126ba97 | 1447 | |
b4cfe447 HE |
1448 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
1449 | context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; | |
1450 | #endif | |
1451 | ||
7d0cc6ed AK |
1452 | context->upd_xlt_page = __get_free_page(GFP_KERNEL); |
1453 | if (!context->upd_xlt_page) { | |
1454 | err = -ENOMEM; | |
1455 | goto out_uars; | |
1456 | } | |
1457 | mutex_init(&context->upd_xlt_page_mutex); | |
1458 | ||
146d2f1a | 1459 | if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { |
c85023e1 | 1460 | err = mlx5_ib_alloc_transport_domain(dev, &context->tdn); |
146d2f1a | 1461 | if (err) |
7d0cc6ed | 1462 | goto out_page; |
146d2f1a | 1463 | } |
1464 | ||
7c2344c3 | 1465 | INIT_LIST_HEAD(&context->vma_private_list); |
e126ba97 EC |
1466 | INIT_LIST_HEAD(&context->db_page_list); |
1467 | mutex_init(&context->db_page_mutex); | |
1468 | ||
2f5ff264 | 1469 | resp.tot_bfregs = req.total_num_bfregs; |
938fe83c | 1470 | resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports); |
b368d7cb | 1471 | |
f72300c5 HA |
1472 | if (field_avail(typeof(resp), cqe_version, udata->outlen)) |
1473 | resp.response_length += sizeof(resp.cqe_version); | |
b368d7cb | 1474 | |
402ca536 | 1475 | if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { |
6ad279c5 MS |
1476 | resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | |
1477 | MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; | |
402ca536 BW |
1478 | resp.response_length += sizeof(resp.cmds_supp_uhw); |
1479 | } | |
1480 | ||
78984898 OG |
1481 | if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) { |
1482 | if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { | |
1483 | mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline); | |
1484 | resp.eth_min_inline++; | |
1485 | } | |
1486 | resp.response_length += sizeof(resp.eth_min_inline); | |
1487 | } | |
1488 | ||
bc5c6eed NO |
1489 | /* |
1490 | * We don't want to expose information from the PCI bar that is located | |
1491 | * after 4096 bytes, so if the arch only supports larger pages, let's | |
1492 | * pretend we don't support reading the HCA's core clock. This is also | |
1493 | * forced by mmap function. | |
1494 | */ | |
de8d6e02 EC |
1495 | if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { |
1496 | if (PAGE_SIZE <= 4096) { | |
1497 | resp.comp_mask |= | |
1498 | MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; | |
1499 | resp.hca_core_clock_offset = | |
1500 | offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE; | |
1501 | } | |
f72300c5 | 1502 | resp.response_length += sizeof(resp.hca_core_clock_offset) + |
402ca536 | 1503 | sizeof(resp.reserved2); |
b368d7cb MB |
1504 | } |
1505 | ||
30aa60b3 EC |
1506 | if (field_avail(typeof(resp), log_uar_size, udata->outlen)) |
1507 | resp.response_length += sizeof(resp.log_uar_size); | |
1508 | ||
1509 | if (field_avail(typeof(resp), num_uars_per_page, udata->outlen)) | |
1510 | resp.response_length += sizeof(resp.num_uars_per_page); | |
1511 | ||
b368d7cb | 1512 | err = ib_copy_to_udata(udata, &resp, resp.response_length); |
e126ba97 | 1513 | if (err) |
146d2f1a | 1514 | goto out_td; |
e126ba97 | 1515 | |
2f5ff264 EC |
1516 | bfregi->ver = ver; |
1517 | bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; | |
f72300c5 | 1518 | context->cqe_version = resp.cqe_version; |
30aa60b3 EC |
1519 | context->lib_caps = req.lib_caps; |
1520 | print_lib_caps(dev, context->lib_caps); | |
f72300c5 | 1521 | |
e126ba97 EC |
1522 | return &context->ibucontext; |
1523 | ||
146d2f1a | 1524 | out_td: |
1525 | if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) | |
c85023e1 | 1526 | mlx5_ib_dealloc_transport_domain(dev, context->tdn); |
146d2f1a | 1527 | |
7d0cc6ed AK |
1528 | out_page: |
1529 | free_page(context->upd_xlt_page); | |
1530 | ||
e126ba97 | 1531 | out_uars: |
b037c29a | 1532 | deallocate_uars(dev, context); |
e126ba97 | 1533 | |
b037c29a EC |
1534 | out_sys_pages: |
1535 | kfree(bfregi->sys_pages); | |
e126ba97 | 1536 | |
b037c29a EC |
1537 | out_count: |
1538 | kfree(bfregi->count); | |
e126ba97 EC |
1539 | |
1540 | out_ctx: | |
1541 | kfree(context); | |
b037c29a | 1542 | |
e126ba97 EC |
1543 | return ERR_PTR(err); |
1544 | } | |
1545 | ||
1546 | static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) | |
1547 | { | |
1548 | struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); | |
1549 | struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); | |
b037c29a | 1550 | struct mlx5_bfreg_info *bfregi; |
e126ba97 | 1551 | |
b037c29a | 1552 | bfregi = &context->bfregi; |
146d2f1a | 1553 | if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) |
c85023e1 | 1554 | mlx5_ib_dealloc_transport_domain(dev, context->tdn); |
146d2f1a | 1555 | |
7d0cc6ed | 1556 | free_page(context->upd_xlt_page); |
b037c29a EC |
1557 | deallocate_uars(dev, context); |
1558 | kfree(bfregi->sys_pages); | |
2f5ff264 | 1559 | kfree(bfregi->count); |
e126ba97 EC |
1560 | kfree(context); |
1561 | ||
1562 | return 0; | |
1563 | } | |
1564 | ||
b037c29a EC |
1565 | static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, |
1566 | struct mlx5_bfreg_info *bfregi, | |
1567 | int idx) | |
e126ba97 | 1568 | { |
b037c29a EC |
1569 | int fw_uars_per_page; |
1570 | ||
1571 | fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; | |
1572 | ||
1573 | return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + | |
1574 | bfregi->sys_pages[idx] / fw_uars_per_page; | |
e126ba97 EC |
1575 | } |
1576 | ||
1577 | static int get_command(unsigned long offset) | |
1578 | { | |
1579 | return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; | |
1580 | } | |
1581 | ||
1582 | static int get_arg(unsigned long offset) | |
1583 | { | |
1584 | return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); | |
1585 | } | |
1586 | ||
1587 | static int get_index(unsigned long offset) | |
1588 | { | |
1589 | return get_arg(offset); | |
1590 | } | |
1591 | ||
7c2344c3 MG |
1592 | static void mlx5_ib_vma_open(struct vm_area_struct *area) |
1593 | { | |
1594 | /* vma_open is called when a new VMA is created on top of our VMA. This | |
1595 | * is done through either mremap flow or split_vma (usually due to | |
1596 | * mlock, madvise, munmap, etc.) We do not support a clone of the VMA, | |
1597 | * as this VMA is strongly hardware related. Therefore we set the | |
1598 | * vm_ops of the newly created/cloned VMA to NULL, to prevent it from | |
1599 | * calling us again and trying to do incorrect actions. We assume that | |
1600 | * the original VMA size is exactly a single page, and therefore all | |
1601 | * "splitting" operation will not happen to it. | |
1602 | */ | |
1603 | area->vm_ops = NULL; | |
1604 | } | |
1605 | ||
1606 | static void mlx5_ib_vma_close(struct vm_area_struct *area) | |
1607 | { | |
1608 | struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data; | |
1609 | ||
1610 | /* It's guaranteed that all VMAs opened on a FD are closed before the | |
1611 | * file itself is closed, therefore no sync is needed with the regular | |
1612 | * closing flow. (e.g. mlx5 ib_dealloc_ucontext) | |
1613 | * However need a sync with accessing the vma as part of | |
1614 | * mlx5_ib_disassociate_ucontext. | |
1615 | * The close operation is usually called under mm->mmap_sem except when | |
1616 | * process is exiting. | |
1617 | * The exiting case is handled explicitly as part of | |
1618 | * mlx5_ib_disassociate_ucontext. | |
1619 | */ | |
1620 | mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data; | |
1621 | ||
1622 | /* setting the vma context pointer to null in the mlx5_ib driver's | |
1623 | * private data, to protect a race condition in | |
1624 | * mlx5_ib_disassociate_ucontext(). | |
1625 | */ | |
1626 | mlx5_ib_vma_priv_data->vma = NULL; | |
1627 | list_del(&mlx5_ib_vma_priv_data->list); | |
1628 | kfree(mlx5_ib_vma_priv_data); | |
1629 | } | |
1630 | ||
1631 | static const struct vm_operations_struct mlx5_ib_vm_ops = { | |
1632 | .open = mlx5_ib_vma_open, | |
1633 | .close = mlx5_ib_vma_close | |
1634 | }; | |
1635 | ||
1636 | static int mlx5_ib_set_vma_data(struct vm_area_struct *vma, | |
1637 | struct mlx5_ib_ucontext *ctx) | |
1638 | { | |
1639 | struct mlx5_ib_vma_private_data *vma_prv; | |
1640 | struct list_head *vma_head = &ctx->vma_private_list; | |
1641 | ||
1642 | vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL); | |
1643 | if (!vma_prv) | |
1644 | return -ENOMEM; | |
1645 | ||
1646 | vma_prv->vma = vma; | |
1647 | vma->vm_private_data = vma_prv; | |
1648 | vma->vm_ops = &mlx5_ib_vm_ops; | |
1649 | ||
1650 | list_add(&vma_prv->list, vma_head); | |
1651 | ||
1652 | return 0; | |
1653 | } | |
1654 | ||
1655 | static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) | |
1656 | { | |
1657 | int ret; | |
1658 | struct vm_area_struct *vma; | |
1659 | struct mlx5_ib_vma_private_data *vma_private, *n; | |
1660 | struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); | |
1661 | struct task_struct *owning_process = NULL; | |
1662 | struct mm_struct *owning_mm = NULL; | |
1663 | ||
1664 | owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID); | |
1665 | if (!owning_process) | |
1666 | return; | |
1667 | ||
1668 | owning_mm = get_task_mm(owning_process); | |
1669 | if (!owning_mm) { | |
1670 | pr_info("no mm, disassociate ucontext is pending task termination\n"); | |
1671 | while (1) { | |
1672 | put_task_struct(owning_process); | |
1673 | usleep_range(1000, 2000); | |
1674 | owning_process = get_pid_task(ibcontext->tgid, | |
1675 | PIDTYPE_PID); | |
1676 | if (!owning_process || | |
1677 | owning_process->state == TASK_DEAD) { | |
1678 | pr_info("disassociate ucontext done, task was terminated\n"); | |
1679 | /* in case task was dead need to release the | |
1680 | * task struct. | |
1681 | */ | |
1682 | if (owning_process) | |
1683 | put_task_struct(owning_process); | |
1684 | return; | |
1685 | } | |
1686 | } | |
1687 | } | |
1688 | ||
1689 | /* need to protect from a race on closing the vma as part of | |
1690 | * mlx5_ib_vma_close. | |
1691 | */ | |
ecc7d83b | 1692 | down_write(&owning_mm->mmap_sem); |
7c2344c3 MG |
1693 | list_for_each_entry_safe(vma_private, n, &context->vma_private_list, |
1694 | list) { | |
1695 | vma = vma_private->vma; | |
1696 | ret = zap_vma_ptes(vma, vma->vm_start, | |
1697 | PAGE_SIZE); | |
1698 | WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__); | |
1699 | /* context going to be destroyed, should | |
1700 | * not access ops any more. | |
1701 | */ | |
13776612 | 1702 | vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE); |
7c2344c3 MG |
1703 | vma->vm_ops = NULL; |
1704 | list_del(&vma_private->list); | |
1705 | kfree(vma_private); | |
1706 | } | |
ecc7d83b | 1707 | up_write(&owning_mm->mmap_sem); |
7c2344c3 MG |
1708 | mmput(owning_mm); |
1709 | put_task_struct(owning_process); | |
1710 | } | |
1711 | ||
37aa5c36 GL |
1712 | static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) |
1713 | { | |
1714 | switch (cmd) { | |
1715 | case MLX5_IB_MMAP_WC_PAGE: | |
1716 | return "WC"; | |
1717 | case MLX5_IB_MMAP_REGULAR_PAGE: | |
1718 | return "best effort WC"; | |
1719 | case MLX5_IB_MMAP_NC_PAGE: | |
1720 | return "NC"; | |
1721 | default: | |
1722 | return NULL; | |
1723 | } | |
1724 | } | |
1725 | ||
1726 | static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, | |
7c2344c3 MG |
1727 | struct vm_area_struct *vma, |
1728 | struct mlx5_ib_ucontext *context) | |
37aa5c36 | 1729 | { |
2f5ff264 | 1730 | struct mlx5_bfreg_info *bfregi = &context->bfregi; |
37aa5c36 GL |
1731 | int err; |
1732 | unsigned long idx; | |
1733 | phys_addr_t pfn, pa; | |
1734 | pgprot_t prot; | |
b037c29a EC |
1735 | int uars_per_page; |
1736 | ||
1737 | if (vma->vm_end - vma->vm_start != PAGE_SIZE) | |
1738 | return -EINVAL; | |
1739 | ||
1740 | uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); | |
1741 | idx = get_index(vma->vm_pgoff); | |
1742 | if (idx % uars_per_page || | |
1743 | idx * uars_per_page >= bfregi->num_sys_pages) { | |
1744 | mlx5_ib_warn(dev, "invalid uar index %lu\n", idx); | |
1745 | return -EINVAL; | |
1746 | } | |
37aa5c36 GL |
1747 | |
1748 | switch (cmd) { | |
1749 | case MLX5_IB_MMAP_WC_PAGE: | |
1750 | /* Some architectures don't support WC memory */ | |
1751 | #if defined(CONFIG_X86) | |
1752 | if (!pat_enabled()) | |
1753 | return -EPERM; | |
1754 | #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) | |
1755 | return -EPERM; | |
1756 | #endif | |
1757 | /* fall through */ | |
1758 | case MLX5_IB_MMAP_REGULAR_PAGE: | |
1759 | /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ | |
1760 | prot = pgprot_writecombine(vma->vm_page_prot); | |
1761 | break; | |
1762 | case MLX5_IB_MMAP_NC_PAGE: | |
1763 | prot = pgprot_noncached(vma->vm_page_prot); | |
1764 | break; | |
1765 | default: | |
1766 | return -EINVAL; | |
1767 | } | |
1768 | ||
b037c29a | 1769 | pfn = uar_index2pfn(dev, bfregi, idx); |
37aa5c36 GL |
1770 | mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); |
1771 | ||
1772 | vma->vm_page_prot = prot; | |
1773 | err = io_remap_pfn_range(vma, vma->vm_start, pfn, | |
1774 | PAGE_SIZE, vma->vm_page_prot); | |
1775 | if (err) { | |
1776 | mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n", | |
1777 | err, vma->vm_start, &pfn, mmap_cmd2str(cmd)); | |
1778 | return -EAGAIN; | |
1779 | } | |
1780 | ||
1781 | pa = pfn << PAGE_SHIFT; | |
1782 | mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd), | |
1783 | vma->vm_start, &pa); | |
1784 | ||
7c2344c3 | 1785 | return mlx5_ib_set_vma_data(vma, context); |
37aa5c36 GL |
1786 | } |
1787 | ||
e126ba97 EC |
1788 | static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) |
1789 | { | |
1790 | struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); | |
1791 | struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); | |
e126ba97 | 1792 | unsigned long command; |
e126ba97 EC |
1793 | phys_addr_t pfn; |
1794 | ||
1795 | command = get_command(vma->vm_pgoff); | |
1796 | switch (command) { | |
37aa5c36 GL |
1797 | case MLX5_IB_MMAP_WC_PAGE: |
1798 | case MLX5_IB_MMAP_NC_PAGE: | |
e126ba97 | 1799 | case MLX5_IB_MMAP_REGULAR_PAGE: |
7c2344c3 | 1800 | return uar_mmap(dev, command, vma, context); |
e126ba97 EC |
1801 | |
1802 | case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: | |
1803 | return -ENOSYS; | |
1804 | ||
d69e3bcf | 1805 | case MLX5_IB_MMAP_CORE_CLOCK: |
d69e3bcf MB |
1806 | if (vma->vm_end - vma->vm_start != PAGE_SIZE) |
1807 | return -EINVAL; | |
1808 | ||
6cbac1e4 | 1809 | if (vma->vm_flags & VM_WRITE) |
d69e3bcf MB |
1810 | return -EPERM; |
1811 | ||
1812 | /* Don't expose to user-space information it shouldn't have */ | |
1813 | if (PAGE_SIZE > 4096) | |
1814 | return -EOPNOTSUPP; | |
1815 | ||
1816 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | |
1817 | pfn = (dev->mdev->iseg_base + | |
1818 | offsetof(struct mlx5_init_seg, internal_timer_h)) >> | |
1819 | PAGE_SHIFT; | |
1820 | if (io_remap_pfn_range(vma, vma->vm_start, pfn, | |
1821 | PAGE_SIZE, vma->vm_page_prot)) | |
1822 | return -EAGAIN; | |
1823 | ||
1824 | mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n", | |
1825 | vma->vm_start, | |
1826 | (unsigned long long)pfn << PAGE_SHIFT); | |
1827 | break; | |
d69e3bcf | 1828 | |
e126ba97 EC |
1829 | default: |
1830 | return -EINVAL; | |
1831 | } | |
1832 | ||
1833 | return 0; | |
1834 | } | |
1835 | ||
e126ba97 EC |
1836 | static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, |
1837 | struct ib_ucontext *context, | |
1838 | struct ib_udata *udata) | |
1839 | { | |
1840 | struct mlx5_ib_alloc_pd_resp resp; | |
1841 | struct mlx5_ib_pd *pd; | |
1842 | int err; | |
1843 | ||
1844 | pd = kmalloc(sizeof(*pd), GFP_KERNEL); | |
1845 | if (!pd) | |
1846 | return ERR_PTR(-ENOMEM); | |
1847 | ||
9603b61d | 1848 | err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); |
e126ba97 EC |
1849 | if (err) { |
1850 | kfree(pd); | |
1851 | return ERR_PTR(err); | |
1852 | } | |
1853 | ||
1854 | if (context) { | |
1855 | resp.pdn = pd->pdn; | |
1856 | if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { | |
9603b61d | 1857 | mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); |
e126ba97 EC |
1858 | kfree(pd); |
1859 | return ERR_PTR(-EFAULT); | |
1860 | } | |
e126ba97 EC |
1861 | } |
1862 | ||
1863 | return &pd->ibpd; | |
1864 | } | |
1865 | ||
1866 | static int mlx5_ib_dealloc_pd(struct ib_pd *pd) | |
1867 | { | |
1868 | struct mlx5_ib_dev *mdev = to_mdev(pd->device); | |
1869 | struct mlx5_ib_pd *mpd = to_mpd(pd); | |
1870 | ||
9603b61d | 1871 | mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); |
e126ba97 EC |
1872 | kfree(mpd); |
1873 | ||
1874 | return 0; | |
1875 | } | |
1876 | ||
466fa6d2 MG |
1877 | enum { |
1878 | MATCH_CRITERIA_ENABLE_OUTER_BIT, | |
1879 | MATCH_CRITERIA_ENABLE_MISC_BIT, | |
1880 | MATCH_CRITERIA_ENABLE_INNER_BIT | |
1881 | }; | |
1882 | ||
1883 | #define HEADER_IS_ZERO(match_criteria, headers) \ | |
1884 | !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ | |
1885 | 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ | |
038d2ef8 | 1886 | |
466fa6d2 | 1887 | static u8 get_match_criteria_enable(u32 *match_criteria) |
038d2ef8 | 1888 | { |
466fa6d2 | 1889 | u8 match_criteria_enable; |
038d2ef8 | 1890 | |
466fa6d2 MG |
1891 | match_criteria_enable = |
1892 | (!HEADER_IS_ZERO(match_criteria, outer_headers)) << | |
1893 | MATCH_CRITERIA_ENABLE_OUTER_BIT; | |
1894 | match_criteria_enable |= | |
1895 | (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << | |
1896 | MATCH_CRITERIA_ENABLE_MISC_BIT; | |
1897 | match_criteria_enable |= | |
1898 | (!HEADER_IS_ZERO(match_criteria, inner_headers)) << | |
1899 | MATCH_CRITERIA_ENABLE_INNER_BIT; | |
1900 | ||
1901 | return match_criteria_enable; | |
038d2ef8 MG |
1902 | } |
1903 | ||
ca0d4753 MG |
1904 | static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) |
1905 | { | |
1906 | MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); | |
1907 | MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); | |
038d2ef8 MG |
1908 | } |
1909 | ||
2d1e697e MR |
1910 | static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val, |
1911 | bool inner) | |
1912 | { | |
1913 | if (inner) { | |
1914 | MLX5_SET(fte_match_set_misc, | |
1915 | misc_c, inner_ipv6_flow_label, mask); | |
1916 | MLX5_SET(fte_match_set_misc, | |
1917 | misc_v, inner_ipv6_flow_label, val); | |
1918 | } else { | |
1919 | MLX5_SET(fte_match_set_misc, | |
1920 | misc_c, outer_ipv6_flow_label, mask); | |
1921 | MLX5_SET(fte_match_set_misc, | |
1922 | misc_v, outer_ipv6_flow_label, val); | |
1923 | } | |
1924 | } | |
1925 | ||
ca0d4753 MG |
1926 | static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) |
1927 | { | |
1928 | MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); | |
1929 | MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); | |
1930 | MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); | |
1931 | MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); | |
1932 | } | |
1933 | ||
c47ac6ae MG |
1934 | #define LAST_ETH_FIELD vlan_tag |
1935 | #define LAST_IB_FIELD sl | |
ca0d4753 | 1936 | #define LAST_IPV4_FIELD tos |
466fa6d2 | 1937 | #define LAST_IPV6_FIELD traffic_class |
c47ac6ae | 1938 | #define LAST_TCP_UDP_FIELD src_port |
ffb30d8f | 1939 | #define LAST_TUNNEL_FIELD tunnel_id |
2ac693f9 | 1940 | #define LAST_FLOW_TAG_FIELD tag_id |
a22ed86c | 1941 | #define LAST_DROP_FIELD size |
c47ac6ae MG |
1942 | |
1943 | /* Field is the last supported field */ | |
1944 | #define FIELDS_NOT_SUPPORTED(filter, field)\ | |
1945 | memchr_inv((void *)&filter.field +\ | |
1946 | sizeof(filter.field), 0,\ | |
1947 | sizeof(filter) -\ | |
1948 | offsetof(typeof(filter), field) -\ | |
1949 | sizeof(filter.field)) | |
1950 | ||
19cc7524 AL |
1951 | #define IPV4_VERSION 4 |
1952 | #define IPV6_VERSION 6 | |
1953 | static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c, | |
1954 | u32 *match_v, const union ib_flow_spec *ib_spec, | |
a22ed86c | 1955 | u32 *tag_id, bool *is_drop) |
038d2ef8 | 1956 | { |
466fa6d2 MG |
1957 | void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, |
1958 | misc_parameters); | |
1959 | void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, | |
1960 | misc_parameters); | |
2d1e697e MR |
1961 | void *headers_c; |
1962 | void *headers_v; | |
19cc7524 | 1963 | int match_ipv; |
2d1e697e MR |
1964 | |
1965 | if (ib_spec->type & IB_FLOW_SPEC_INNER) { | |
1966 | headers_c = MLX5_ADDR_OF(fte_match_param, match_c, | |
1967 | inner_headers); | |
1968 | headers_v = MLX5_ADDR_OF(fte_match_param, match_v, | |
1969 | inner_headers); | |
19cc7524 AL |
1970 | match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, |
1971 | ft_field_support.inner_ip_version); | |
2d1e697e MR |
1972 | } else { |
1973 | headers_c = MLX5_ADDR_OF(fte_match_param, match_c, | |
1974 | outer_headers); | |
1975 | headers_v = MLX5_ADDR_OF(fte_match_param, match_v, | |
1976 | outer_headers); | |
19cc7524 AL |
1977 | match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, |
1978 | ft_field_support.outer_ip_version); | |
2d1e697e | 1979 | } |
466fa6d2 | 1980 | |
2d1e697e | 1981 | switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) { |
038d2ef8 | 1982 | case IB_FLOW_SPEC_ETH: |
c47ac6ae | 1983 | if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) |
1ffd3a26 | 1984 | return -EOPNOTSUPP; |
038d2ef8 | 1985 | |
2d1e697e | 1986 | ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, |
038d2ef8 MG |
1987 | dmac_47_16), |
1988 | ib_spec->eth.mask.dst_mac); | |
2d1e697e | 1989 | ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, |
038d2ef8 MG |
1990 | dmac_47_16), |
1991 | ib_spec->eth.val.dst_mac); | |
1992 | ||
2d1e697e | 1993 | ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, |
ee3da804 MG |
1994 | smac_47_16), |
1995 | ib_spec->eth.mask.src_mac); | |
2d1e697e | 1996 | ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, |
ee3da804 MG |
1997 | smac_47_16), |
1998 | ib_spec->eth.val.src_mac); | |
1999 | ||
038d2ef8 | 2000 | if (ib_spec->eth.mask.vlan_tag) { |
2d1e697e | 2001 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, |
10543365 | 2002 | cvlan_tag, 1); |
2d1e697e | 2003 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, |
10543365 | 2004 | cvlan_tag, 1); |
038d2ef8 | 2005 | |
2d1e697e | 2006 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, |
038d2ef8 | 2007 | first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); |
2d1e697e | 2008 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, |
038d2ef8 MG |
2009 | first_vid, ntohs(ib_spec->eth.val.vlan_tag)); |
2010 | ||
2d1e697e | 2011 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, |
038d2ef8 MG |
2012 | first_cfi, |
2013 | ntohs(ib_spec->eth.mask.vlan_tag) >> 12); | |
2d1e697e | 2014 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, |
038d2ef8 MG |
2015 | first_cfi, |
2016 | ntohs(ib_spec->eth.val.vlan_tag) >> 12); | |
2017 | ||
2d1e697e | 2018 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, |
038d2ef8 MG |
2019 | first_prio, |
2020 | ntohs(ib_spec->eth.mask.vlan_tag) >> 13); | |
2d1e697e | 2021 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, |
038d2ef8 MG |
2022 | first_prio, |
2023 | ntohs(ib_spec->eth.val.vlan_tag) >> 13); | |
2024 | } | |
2d1e697e | 2025 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, |
038d2ef8 | 2026 | ethertype, ntohs(ib_spec->eth.mask.ether_type)); |
2d1e697e | 2027 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, |
038d2ef8 MG |
2028 | ethertype, ntohs(ib_spec->eth.val.ether_type)); |
2029 | break; | |
2030 | case IB_FLOW_SPEC_IPV4: | |
c47ac6ae | 2031 | if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) |
1ffd3a26 | 2032 | return -EOPNOTSUPP; |
038d2ef8 | 2033 | |
19cc7524 AL |
2034 | if (match_ipv) { |
2035 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, | |
2036 | ip_version, 0xf); | |
2037 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, | |
2038 | ip_version, IPV4_VERSION); | |
2039 | } else { | |
2040 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, | |
2041 | ethertype, 0xffff); | |
2042 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, | |
2043 | ethertype, ETH_P_IP); | |
2044 | } | |
038d2ef8 | 2045 | |
2d1e697e | 2046 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, |
038d2ef8 MG |
2047 | src_ipv4_src_ipv6.ipv4_layout.ipv4), |
2048 | &ib_spec->ipv4.mask.src_ip, | |
2049 | sizeof(ib_spec->ipv4.mask.src_ip)); | |
2d1e697e | 2050 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, |
038d2ef8 MG |
2051 | src_ipv4_src_ipv6.ipv4_layout.ipv4), |
2052 | &ib_spec->ipv4.val.src_ip, | |
2053 | sizeof(ib_spec->ipv4.val.src_ip)); | |
2d1e697e | 2054 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, |
038d2ef8 MG |
2055 | dst_ipv4_dst_ipv6.ipv4_layout.ipv4), |
2056 | &ib_spec->ipv4.mask.dst_ip, | |
2057 | sizeof(ib_spec->ipv4.mask.dst_ip)); | |
2d1e697e | 2058 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, |
038d2ef8 MG |
2059 | dst_ipv4_dst_ipv6.ipv4_layout.ipv4), |
2060 | &ib_spec->ipv4.val.dst_ip, | |
2061 | sizeof(ib_spec->ipv4.val.dst_ip)); | |
ca0d4753 | 2062 | |
2d1e697e | 2063 | set_tos(headers_c, headers_v, |
ca0d4753 MG |
2064 | ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); |
2065 | ||
2d1e697e | 2066 | set_proto(headers_c, headers_v, |
ca0d4753 | 2067 | ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); |
038d2ef8 | 2068 | break; |
026bae0c | 2069 | case IB_FLOW_SPEC_IPV6: |
c47ac6ae | 2070 | if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) |
1ffd3a26 | 2071 | return -EOPNOTSUPP; |
026bae0c | 2072 | |
19cc7524 AL |
2073 | if (match_ipv) { |
2074 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, | |
2075 | ip_version, 0xf); | |
2076 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, | |
2077 | ip_version, IPV6_VERSION); | |
2078 | } else { | |
2079 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, | |
2080 | ethertype, 0xffff); | |
2081 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, | |
2082 | ethertype, ETH_P_IPV6); | |
2083 | } | |
026bae0c | 2084 | |
2d1e697e | 2085 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, |
026bae0c MG |
2086 | src_ipv4_src_ipv6.ipv6_layout.ipv6), |
2087 | &ib_spec->ipv6.mask.src_ip, | |
2088 | sizeof(ib_spec->ipv6.mask.src_ip)); | |
2d1e697e | 2089 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, |
026bae0c MG |
2090 | src_ipv4_src_ipv6.ipv6_layout.ipv6), |
2091 | &ib_spec->ipv6.val.src_ip, | |
2092 | sizeof(ib_spec->ipv6.val.src_ip)); | |
2d1e697e | 2093 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, |
026bae0c MG |
2094 | dst_ipv4_dst_ipv6.ipv6_layout.ipv6), |
2095 | &ib_spec->ipv6.mask.dst_ip, | |
2096 | sizeof(ib_spec->ipv6.mask.dst_ip)); | |
2d1e697e | 2097 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, |
026bae0c MG |
2098 | dst_ipv4_dst_ipv6.ipv6_layout.ipv6), |
2099 | &ib_spec->ipv6.val.dst_ip, | |
2100 | sizeof(ib_spec->ipv6.val.dst_ip)); | |
466fa6d2 | 2101 | |
2d1e697e | 2102 | set_tos(headers_c, headers_v, |
466fa6d2 MG |
2103 | ib_spec->ipv6.mask.traffic_class, |
2104 | ib_spec->ipv6.val.traffic_class); | |
2105 | ||
2d1e697e | 2106 | set_proto(headers_c, headers_v, |
466fa6d2 MG |
2107 | ib_spec->ipv6.mask.next_hdr, |
2108 | ib_spec->ipv6.val.next_hdr); | |
2109 | ||
2d1e697e MR |
2110 | set_flow_label(misc_params_c, misc_params_v, |
2111 | ntohl(ib_spec->ipv6.mask.flow_label), | |
2112 | ntohl(ib_spec->ipv6.val.flow_label), | |
2113 | ib_spec->type & IB_FLOW_SPEC_INNER); | |
2114 | ||
026bae0c | 2115 | break; |
038d2ef8 | 2116 | case IB_FLOW_SPEC_TCP: |
c47ac6ae MG |
2117 | if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, |
2118 | LAST_TCP_UDP_FIELD)) | |
1ffd3a26 | 2119 | return -EOPNOTSUPP; |
038d2ef8 | 2120 | |
2d1e697e | 2121 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, |
038d2ef8 | 2122 | 0xff); |
2d1e697e | 2123 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, |
038d2ef8 MG |
2124 | IPPROTO_TCP); |
2125 | ||
2d1e697e | 2126 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport, |
038d2ef8 | 2127 | ntohs(ib_spec->tcp_udp.mask.src_port)); |
2d1e697e | 2128 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport, |
038d2ef8 MG |
2129 | ntohs(ib_spec->tcp_udp.val.src_port)); |
2130 | ||
2d1e697e | 2131 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport, |
038d2ef8 | 2132 | ntohs(ib_spec->tcp_udp.mask.dst_port)); |
2d1e697e | 2133 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport, |
038d2ef8 MG |
2134 | ntohs(ib_spec->tcp_udp.val.dst_port)); |
2135 | break; | |
2136 | case IB_FLOW_SPEC_UDP: | |
c47ac6ae MG |
2137 | if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, |
2138 | LAST_TCP_UDP_FIELD)) | |
1ffd3a26 | 2139 | return -EOPNOTSUPP; |
038d2ef8 | 2140 | |
2d1e697e | 2141 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, |
038d2ef8 | 2142 | 0xff); |
2d1e697e | 2143 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, |
038d2ef8 MG |
2144 | IPPROTO_UDP); |
2145 | ||
2d1e697e | 2146 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport, |
038d2ef8 | 2147 | ntohs(ib_spec->tcp_udp.mask.src_port)); |
2d1e697e | 2148 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport, |
038d2ef8 MG |
2149 | ntohs(ib_spec->tcp_udp.val.src_port)); |
2150 | ||
2d1e697e | 2151 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport, |
038d2ef8 | 2152 | ntohs(ib_spec->tcp_udp.mask.dst_port)); |
2d1e697e | 2153 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, |
038d2ef8 MG |
2154 | ntohs(ib_spec->tcp_udp.val.dst_port)); |
2155 | break; | |
ffb30d8f MR |
2156 | case IB_FLOW_SPEC_VXLAN_TUNNEL: |
2157 | if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask, | |
2158 | LAST_TUNNEL_FIELD)) | |
1ffd3a26 | 2159 | return -EOPNOTSUPP; |
ffb30d8f MR |
2160 | |
2161 | MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni, | |
2162 | ntohl(ib_spec->tunnel.mask.tunnel_id)); | |
2163 | MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni, | |
2164 | ntohl(ib_spec->tunnel.val.tunnel_id)); | |
2165 | break; | |
2ac693f9 MR |
2166 | case IB_FLOW_SPEC_ACTION_TAG: |
2167 | if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag, | |
2168 | LAST_FLOW_TAG_FIELD)) | |
2169 | return -EOPNOTSUPP; | |
2170 | if (ib_spec->flow_tag.tag_id >= BIT(24)) | |
2171 | return -EINVAL; | |
2172 | ||
2173 | *tag_id = ib_spec->flow_tag.tag_id; | |
2174 | break; | |
a22ed86c SS |
2175 | case IB_FLOW_SPEC_ACTION_DROP: |
2176 | if (FIELDS_NOT_SUPPORTED(ib_spec->drop, | |
2177 | LAST_DROP_FIELD)) | |
2178 | return -EOPNOTSUPP; | |
2179 | *is_drop = true; | |
2180 | break; | |
038d2ef8 MG |
2181 | default: |
2182 | return -EINVAL; | |
2183 | } | |
2184 | ||
2185 | return 0; | |
2186 | } | |
2187 | ||
2188 | /* If a flow could catch both multicast and unicast packets, | |
2189 | * it won't fall into the multicast flow steering table and this rule | |
2190 | * could steal other multicast packets. | |
2191 | */ | |
a550ddfc | 2192 | static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr) |
038d2ef8 | 2193 | { |
81e30880 | 2194 | union ib_flow_spec *flow_spec; |
038d2ef8 MG |
2195 | |
2196 | if (ib_attr->type != IB_FLOW_ATTR_NORMAL || | |
038d2ef8 MG |
2197 | ib_attr->num_of_specs < 1) |
2198 | return false; | |
2199 | ||
81e30880 YH |
2200 | flow_spec = (union ib_flow_spec *)(ib_attr + 1); |
2201 | if (flow_spec->type == IB_FLOW_SPEC_IPV4) { | |
2202 | struct ib_flow_spec_ipv4 *ipv4_spec; | |
2203 | ||
2204 | ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec; | |
2205 | if (ipv4_is_multicast(ipv4_spec->val.dst_ip)) | |
2206 | return true; | |
2207 | ||
038d2ef8 | 2208 | return false; |
81e30880 YH |
2209 | } |
2210 | ||
2211 | if (flow_spec->type == IB_FLOW_SPEC_ETH) { | |
2212 | struct ib_flow_spec_eth *eth_spec; | |
2213 | ||
2214 | eth_spec = (struct ib_flow_spec_eth *)flow_spec; | |
2215 | return is_multicast_ether_addr(eth_spec->mask.dst_mac) && | |
2216 | is_multicast_ether_addr(eth_spec->val.dst_mac); | |
2217 | } | |
038d2ef8 | 2218 | |
81e30880 | 2219 | return false; |
038d2ef8 MG |
2220 | } |
2221 | ||
19cc7524 AL |
2222 | static bool is_valid_ethertype(struct mlx5_core_dev *mdev, |
2223 | const struct ib_flow_attr *flow_attr, | |
0f750966 | 2224 | bool check_inner) |
038d2ef8 MG |
2225 | { |
2226 | union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); | |
19cc7524 AL |
2227 | int match_ipv = check_inner ? |
2228 | MLX5_CAP_FLOWTABLE_NIC_RX(mdev, | |
2229 | ft_field_support.inner_ip_version) : | |
2230 | MLX5_CAP_FLOWTABLE_NIC_RX(mdev, | |
2231 | ft_field_support.outer_ip_version); | |
0f750966 AL |
2232 | int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0; |
2233 | bool ipv4_spec_valid, ipv6_spec_valid; | |
2234 | unsigned int ip_spec_type = 0; | |
2235 | bool has_ethertype = false; | |
038d2ef8 | 2236 | unsigned int spec_index; |
0f750966 AL |
2237 | bool mask_valid = true; |
2238 | u16 eth_type = 0; | |
2239 | bool type_valid; | |
038d2ef8 MG |
2240 | |
2241 | /* Validate that ethertype is correct */ | |
2242 | for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { | |
0f750966 | 2243 | if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) && |
038d2ef8 | 2244 | ib_spec->eth.mask.ether_type) { |
0f750966 AL |
2245 | mask_valid = (ib_spec->eth.mask.ether_type == |
2246 | htons(0xffff)); | |
2247 | has_ethertype = true; | |
2248 | eth_type = ntohs(ib_spec->eth.val.ether_type); | |
2249 | } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) || | |
2250 | (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) { | |
2251 | ip_spec_type = ib_spec->type; | |
038d2ef8 MG |
2252 | } |
2253 | ib_spec = (void *)ib_spec + ib_spec->size; | |
2254 | } | |
0f750966 AL |
2255 | |
2256 | type_valid = (!has_ethertype) || (!ip_spec_type); | |
2257 | if (!type_valid && mask_valid) { | |
2258 | ipv4_spec_valid = (eth_type == ETH_P_IP) && | |
2259 | (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit)); | |
2260 | ipv6_spec_valid = (eth_type == ETH_P_IPV6) && | |
2261 | (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit)); | |
19cc7524 AL |
2262 | |
2263 | type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) || | |
2264 | (((eth_type == ETH_P_MPLS_UC) || | |
2265 | (eth_type == ETH_P_MPLS_MC)) && match_ipv); | |
0f750966 AL |
2266 | } |
2267 | ||
2268 | return type_valid; | |
2269 | } | |
2270 | ||
19cc7524 AL |
2271 | static bool is_valid_attr(struct mlx5_core_dev *mdev, |
2272 | const struct ib_flow_attr *flow_attr) | |
0f750966 | 2273 | { |
19cc7524 AL |
2274 | return is_valid_ethertype(mdev, flow_attr, false) && |
2275 | is_valid_ethertype(mdev, flow_attr, true); | |
038d2ef8 MG |
2276 | } |
2277 | ||
2278 | static void put_flow_table(struct mlx5_ib_dev *dev, | |
2279 | struct mlx5_ib_flow_prio *prio, bool ft_added) | |
2280 | { | |
2281 | prio->refcount -= !!ft_added; | |
2282 | if (!prio->refcount) { | |
2283 | mlx5_destroy_flow_table(prio->flow_table); | |
2284 | prio->flow_table = NULL; | |
2285 | } | |
2286 | } | |
2287 | ||
2288 | static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) | |
2289 | { | |
2290 | struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); | |
2291 | struct mlx5_ib_flow_handler *handler = container_of(flow_id, | |
2292 | struct mlx5_ib_flow_handler, | |
2293 | ibflow); | |
2294 | struct mlx5_ib_flow_handler *iter, *tmp; | |
2295 | ||
2296 | mutex_lock(&dev->flow_db.lock); | |
2297 | ||
2298 | list_for_each_entry_safe(iter, tmp, &handler->list, list) { | |
74491de9 | 2299 | mlx5_del_flow_rules(iter->rule); |
cc0e5d42 | 2300 | put_flow_table(dev, iter->prio, true); |
038d2ef8 MG |
2301 | list_del(&iter->list); |
2302 | kfree(iter); | |
2303 | } | |
2304 | ||
74491de9 | 2305 | mlx5_del_flow_rules(handler->rule); |
5497adc6 | 2306 | put_flow_table(dev, handler->prio, true); |
038d2ef8 MG |
2307 | mutex_unlock(&dev->flow_db.lock); |
2308 | ||
2309 | kfree(handler); | |
2310 | ||
2311 | return 0; | |
2312 | } | |
2313 | ||
35d19011 MG |
2314 | static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) |
2315 | { | |
2316 | priority *= 2; | |
2317 | if (!dont_trap) | |
2318 | priority++; | |
2319 | return priority; | |
2320 | } | |
2321 | ||
cc0e5d42 MG |
2322 | enum flow_table_type { |
2323 | MLX5_IB_FT_RX, | |
2324 | MLX5_IB_FT_TX | |
2325 | }; | |
2326 | ||
00b7c2ab MG |
2327 | #define MLX5_FS_MAX_TYPES 6 |
2328 | #define MLX5_FS_MAX_ENTRIES BIT(16) | |
038d2ef8 | 2329 | static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, |
cc0e5d42 MG |
2330 | struct ib_flow_attr *flow_attr, |
2331 | enum flow_table_type ft_type) | |
038d2ef8 | 2332 | { |
35d19011 | 2333 | bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; |
038d2ef8 MG |
2334 | struct mlx5_flow_namespace *ns = NULL; |
2335 | struct mlx5_ib_flow_prio *prio; | |
2336 | struct mlx5_flow_table *ft; | |
dac388ef | 2337 | int max_table_size; |
038d2ef8 MG |
2338 | int num_entries; |
2339 | int num_groups; | |
2340 | int priority; | |
2341 | int err = 0; | |
2342 | ||
dac388ef MG |
2343 | max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, |
2344 | log_max_ft_size)); | |
038d2ef8 | 2345 | if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { |
35d19011 MG |
2346 | if (flow_is_multicast_only(flow_attr) && |
2347 | !dont_trap) | |
038d2ef8 MG |
2348 | priority = MLX5_IB_FLOW_MCAST_PRIO; |
2349 | else | |
35d19011 MG |
2350 | priority = ib_prio_to_core_prio(flow_attr->priority, |
2351 | dont_trap); | |
038d2ef8 MG |
2352 | ns = mlx5_get_flow_namespace(dev->mdev, |
2353 | MLX5_FLOW_NAMESPACE_BYPASS); | |
2354 | num_entries = MLX5_FS_MAX_ENTRIES; | |
2355 | num_groups = MLX5_FS_MAX_TYPES; | |
2356 | prio = &dev->flow_db.prios[priority]; | |
2357 | } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || | |
2358 | flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { | |
2359 | ns = mlx5_get_flow_namespace(dev->mdev, | |
2360 | MLX5_FLOW_NAMESPACE_LEFTOVERS); | |
2361 | build_leftovers_ft_param(&priority, | |
2362 | &num_entries, | |
2363 | &num_groups); | |
2364 | prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; | |
cc0e5d42 MG |
2365 | } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { |
2366 | if (!MLX5_CAP_FLOWTABLE(dev->mdev, | |
2367 | allow_sniffer_and_nic_rx_shared_tir)) | |
2368 | return ERR_PTR(-ENOTSUPP); | |
2369 | ||
2370 | ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? | |
2371 | MLX5_FLOW_NAMESPACE_SNIFFER_RX : | |
2372 | MLX5_FLOW_NAMESPACE_SNIFFER_TX); | |
2373 | ||
2374 | prio = &dev->flow_db.sniffer[ft_type]; | |
2375 | priority = 0; | |
2376 | num_entries = 1; | |
2377 | num_groups = 1; | |
038d2ef8 MG |
2378 | } |
2379 | ||
2380 | if (!ns) | |
2381 | return ERR_PTR(-ENOTSUPP); | |
2382 | ||
dac388ef MG |
2383 | if (num_entries > max_table_size) |
2384 | return ERR_PTR(-ENOMEM); | |
2385 | ||
038d2ef8 MG |
2386 | ft = prio->flow_table; |
2387 | if (!ft) { | |
2388 | ft = mlx5_create_auto_grouped_flow_table(ns, priority, | |
2389 | num_entries, | |
d63cd286 | 2390 | num_groups, |
c9f1b073 | 2391 | 0, 0); |
038d2ef8 MG |
2392 | |
2393 | if (!IS_ERR(ft)) { | |
2394 | prio->refcount = 0; | |
2395 | prio->flow_table = ft; | |
2396 | } else { | |
2397 | err = PTR_ERR(ft); | |
2398 | } | |
2399 | } | |
2400 | ||
2401 | return err ? ERR_PTR(err) : prio; | |
2402 | } | |
2403 | ||
a550ddfc YH |
2404 | static void set_underlay_qp(struct mlx5_ib_dev *dev, |
2405 | struct mlx5_flow_spec *spec, | |
2406 | u32 underlay_qpn) | |
2407 | { | |
2408 | void *misc_params_c = MLX5_ADDR_OF(fte_match_param, | |
2409 | spec->match_criteria, | |
2410 | misc_parameters); | |
2411 | void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, | |
2412 | misc_parameters); | |
2413 | ||
2414 | if (underlay_qpn && | |
2415 | MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, | |
2416 | ft_field_support.bth_dst_qp)) { | |
2417 | MLX5_SET(fte_match_set_misc, | |
2418 | misc_params_v, bth_dst_qp, underlay_qpn); | |
2419 | MLX5_SET(fte_match_set_misc, | |
2420 | misc_params_c, bth_dst_qp, 0xffffff); | |
2421 | } | |
2422 | } | |
2423 | ||
2424 | static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev, | |
2425 | struct mlx5_ib_flow_prio *ft_prio, | |
2426 | const struct ib_flow_attr *flow_attr, | |
2427 | struct mlx5_flow_destination *dst, | |
2428 | u32 underlay_qpn) | |
038d2ef8 MG |
2429 | { |
2430 | struct mlx5_flow_table *ft = ft_prio->flow_table; | |
2431 | struct mlx5_ib_flow_handler *handler; | |
66958ed9 | 2432 | struct mlx5_flow_act flow_act = {0}; |
c5bb1730 | 2433 | struct mlx5_flow_spec *spec; |
a22ed86c | 2434 | struct mlx5_flow_destination *rule_dst = dst; |
dd063d0e | 2435 | const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); |
038d2ef8 | 2436 | unsigned int spec_index; |
2ac693f9 | 2437 | u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG; |
a22ed86c | 2438 | bool is_drop = false; |
038d2ef8 | 2439 | int err = 0; |
a22ed86c | 2440 | int dest_num = 1; |
038d2ef8 | 2441 | |
19cc7524 | 2442 | if (!is_valid_attr(dev->mdev, flow_attr)) |
038d2ef8 MG |
2443 | return ERR_PTR(-EINVAL); |
2444 | ||
1b9a07ee | 2445 | spec = kvzalloc(sizeof(*spec), GFP_KERNEL); |
038d2ef8 | 2446 | handler = kzalloc(sizeof(*handler), GFP_KERNEL); |
c5bb1730 | 2447 | if (!handler || !spec) { |
038d2ef8 MG |
2448 | err = -ENOMEM; |
2449 | goto free; | |
2450 | } | |
2451 | ||
2452 | INIT_LIST_HEAD(&handler->list); | |
2453 | ||
2454 | for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { | |
19cc7524 | 2455 | err = parse_flow_attr(dev->mdev, spec->match_criteria, |
a22ed86c SS |
2456 | spec->match_value, |
2457 | ib_flow, &flow_tag, &is_drop); | |
038d2ef8 MG |
2458 | if (err < 0) |
2459 | goto free; | |
2460 | ||
2461 | ib_flow += ((union ib_flow_spec *)ib_flow)->size; | |
2462 | } | |
2463 | ||
a550ddfc YH |
2464 | if (!flow_is_multicast_only(flow_attr)) |
2465 | set_underlay_qp(dev, spec, underlay_qpn); | |
2466 | ||
466fa6d2 | 2467 | spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); |
a22ed86c SS |
2468 | if (is_drop) { |
2469 | flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP; | |
2470 | rule_dst = NULL; | |
2471 | dest_num = 0; | |
2472 | } else { | |
2473 | flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : | |
2474 | MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; | |
2475 | } | |
2ac693f9 MR |
2476 | |
2477 | if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG && | |
2478 | (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || | |
2479 | flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { | |
2480 | mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n", | |
2481 | flow_tag, flow_attr->type); | |
2482 | err = -EINVAL; | |
2483 | goto free; | |
2484 | } | |
2485 | flow_act.flow_tag = flow_tag; | |
74491de9 | 2486 | handler->rule = mlx5_add_flow_rules(ft, spec, |
66958ed9 | 2487 | &flow_act, |
a22ed86c | 2488 | rule_dst, dest_num); |
038d2ef8 MG |
2489 | |
2490 | if (IS_ERR(handler->rule)) { | |
2491 | err = PTR_ERR(handler->rule); | |
2492 | goto free; | |
2493 | } | |
2494 | ||
d9d4980a | 2495 | ft_prio->refcount++; |
5497adc6 | 2496 | handler->prio = ft_prio; |
038d2ef8 MG |
2497 | |
2498 | ft_prio->flow_table = ft; | |
2499 | free: | |
2500 | if (err) | |
2501 | kfree(handler); | |
c5bb1730 | 2502 | kvfree(spec); |
038d2ef8 MG |
2503 | return err ? ERR_PTR(err) : handler; |
2504 | } | |
2505 | ||
a550ddfc YH |
2506 | static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, |
2507 | struct mlx5_ib_flow_prio *ft_prio, | |
2508 | const struct ib_flow_attr *flow_attr, | |
2509 | struct mlx5_flow_destination *dst) | |
2510 | { | |
2511 | return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0); | |
2512 | } | |
2513 | ||
35d19011 MG |
2514 | static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, |
2515 | struct mlx5_ib_flow_prio *ft_prio, | |
2516 | struct ib_flow_attr *flow_attr, | |
2517 | struct mlx5_flow_destination *dst) | |
2518 | { | |
2519 | struct mlx5_ib_flow_handler *handler_dst = NULL; | |
2520 | struct mlx5_ib_flow_handler *handler = NULL; | |
2521 | ||
2522 | handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); | |
2523 | if (!IS_ERR(handler)) { | |
2524 | handler_dst = create_flow_rule(dev, ft_prio, | |
2525 | flow_attr, dst); | |
2526 | if (IS_ERR(handler_dst)) { | |
74491de9 | 2527 | mlx5_del_flow_rules(handler->rule); |
d9d4980a | 2528 | ft_prio->refcount--; |
35d19011 MG |
2529 | kfree(handler); |
2530 | handler = handler_dst; | |
2531 | } else { | |
2532 | list_add(&handler_dst->list, &handler->list); | |
2533 | } | |
2534 | } | |
2535 | ||
2536 | return handler; | |
2537 | } | |
038d2ef8 MG |
2538 | enum { |
2539 | LEFTOVERS_MC, | |
2540 | LEFTOVERS_UC, | |
2541 | }; | |
2542 | ||
2543 | static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, | |
2544 | struct mlx5_ib_flow_prio *ft_prio, | |
2545 | struct ib_flow_attr *flow_attr, | |
2546 | struct mlx5_flow_destination *dst) | |
2547 | { | |
2548 | struct mlx5_ib_flow_handler *handler_ucast = NULL; | |
2549 | struct mlx5_ib_flow_handler *handler = NULL; | |
2550 | ||
2551 | static struct { | |
2552 | struct ib_flow_attr flow_attr; | |
2553 | struct ib_flow_spec_eth eth_flow; | |
2554 | } leftovers_specs[] = { | |
2555 | [LEFTOVERS_MC] = { | |
2556 | .flow_attr = { | |
2557 | .num_of_specs = 1, | |
2558 | .size = sizeof(leftovers_specs[0]) | |
2559 | }, | |
2560 | .eth_flow = { | |
2561 | .type = IB_FLOW_SPEC_ETH, | |
2562 | .size = sizeof(struct ib_flow_spec_eth), | |
2563 | .mask = {.dst_mac = {0x1} }, | |
2564 | .val = {.dst_mac = {0x1} } | |
2565 | } | |
2566 | }, | |
2567 | [LEFTOVERS_UC] = { | |
2568 | .flow_attr = { | |
2569 | .num_of_specs = 1, | |
2570 | .size = sizeof(leftovers_specs[0]) | |
2571 | }, | |
2572 | .eth_flow = { | |
2573 | .type = IB_FLOW_SPEC_ETH, | |
2574 | .size = sizeof(struct ib_flow_spec_eth), | |
2575 | .mask = {.dst_mac = {0x1} }, | |
2576 | .val = {.dst_mac = {} } | |
2577 | } | |
2578 | } | |
2579 | }; | |
2580 | ||
2581 | handler = create_flow_rule(dev, ft_prio, | |
2582 | &leftovers_specs[LEFTOVERS_MC].flow_attr, | |
2583 | dst); | |
2584 | if (!IS_ERR(handler) && | |
2585 | flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { | |
2586 | handler_ucast = create_flow_rule(dev, ft_prio, | |
2587 | &leftovers_specs[LEFTOVERS_UC].flow_attr, | |
2588 | dst); | |
2589 | if (IS_ERR(handler_ucast)) { | |
74491de9 | 2590 | mlx5_del_flow_rules(handler->rule); |
d9d4980a | 2591 | ft_prio->refcount--; |
038d2ef8 MG |
2592 | kfree(handler); |
2593 | handler = handler_ucast; | |
2594 | } else { | |
2595 | list_add(&handler_ucast->list, &handler->list); | |
2596 | } | |
2597 | } | |
2598 | ||
2599 | return handler; | |
2600 | } | |
2601 | ||
cc0e5d42 MG |
2602 | static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, |
2603 | struct mlx5_ib_flow_prio *ft_rx, | |
2604 | struct mlx5_ib_flow_prio *ft_tx, | |
2605 | struct mlx5_flow_destination *dst) | |
2606 | { | |
2607 | struct mlx5_ib_flow_handler *handler_rx; | |
2608 | struct mlx5_ib_flow_handler *handler_tx; | |
2609 | int err; | |
2610 | static const struct ib_flow_attr flow_attr = { | |
2611 | .num_of_specs = 0, | |
2612 | .size = sizeof(flow_attr) | |
2613 | }; | |
2614 | ||
2615 | handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); | |
2616 | if (IS_ERR(handler_rx)) { | |
2617 | err = PTR_ERR(handler_rx); | |
2618 | goto err; | |
2619 | } | |
2620 | ||
2621 | handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); | |
2622 | if (IS_ERR(handler_tx)) { | |
2623 | err = PTR_ERR(handler_tx); | |
2624 | goto err_tx; | |
2625 | } | |
2626 | ||
2627 | list_add(&handler_tx->list, &handler_rx->list); | |
2628 | ||
2629 | return handler_rx; | |
2630 | ||
2631 | err_tx: | |
74491de9 | 2632 | mlx5_del_flow_rules(handler_rx->rule); |
cc0e5d42 MG |
2633 | ft_rx->refcount--; |
2634 | kfree(handler_rx); | |
2635 | err: | |
2636 | return ERR_PTR(err); | |
2637 | } | |
2638 | ||
038d2ef8 MG |
2639 | static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, |
2640 | struct ib_flow_attr *flow_attr, | |
2641 | int domain) | |
2642 | { | |
2643 | struct mlx5_ib_dev *dev = to_mdev(qp->device); | |
d9f88e5a | 2644 | struct mlx5_ib_qp *mqp = to_mqp(qp); |
038d2ef8 MG |
2645 | struct mlx5_ib_flow_handler *handler = NULL; |
2646 | struct mlx5_flow_destination *dst = NULL; | |
cc0e5d42 | 2647 | struct mlx5_ib_flow_prio *ft_prio_tx = NULL; |
038d2ef8 MG |
2648 | struct mlx5_ib_flow_prio *ft_prio; |
2649 | int err; | |
a550ddfc | 2650 | int underlay_qpn; |
038d2ef8 MG |
2651 | |
2652 | if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) | |
dac388ef | 2653 | return ERR_PTR(-ENOMEM); |
038d2ef8 MG |
2654 | |
2655 | if (domain != IB_FLOW_DOMAIN_USER || | |
2656 | flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) || | |
35d19011 | 2657 | (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)) |
038d2ef8 MG |
2658 | return ERR_PTR(-EINVAL); |
2659 | ||
2660 | dst = kzalloc(sizeof(*dst), GFP_KERNEL); | |
2661 | if (!dst) | |
2662 | return ERR_PTR(-ENOMEM); | |
2663 | ||
2664 | mutex_lock(&dev->flow_db.lock); | |
2665 | ||
cc0e5d42 | 2666 | ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX); |
038d2ef8 MG |
2667 | if (IS_ERR(ft_prio)) { |
2668 | err = PTR_ERR(ft_prio); | |
2669 | goto unlock; | |
2670 | } | |
cc0e5d42 MG |
2671 | if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { |
2672 | ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); | |
2673 | if (IS_ERR(ft_prio_tx)) { | |
2674 | err = PTR_ERR(ft_prio_tx); | |
2675 | ft_prio_tx = NULL; | |
2676 | goto destroy_ft; | |
2677 | } | |
2678 | } | |
038d2ef8 MG |
2679 | |
2680 | dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; | |
d9f88e5a YH |
2681 | if (mqp->flags & MLX5_IB_QP_RSS) |
2682 | dst->tir_num = mqp->rss_qp.tirn; | |
2683 | else | |
2684 | dst->tir_num = mqp->raw_packet_qp.rq.tirn; | |
038d2ef8 MG |
2685 | |
2686 | if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { | |
35d19011 MG |
2687 | if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { |
2688 | handler = create_dont_trap_rule(dev, ft_prio, | |
2689 | flow_attr, dst); | |
2690 | } else { | |
a550ddfc YH |
2691 | underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ? |
2692 | mqp->underlay_qpn : 0; | |
2693 | handler = _create_flow_rule(dev, ft_prio, flow_attr, | |
2694 | dst, underlay_qpn); | |
35d19011 | 2695 | } |
038d2ef8 MG |
2696 | } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || |
2697 | flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { | |
2698 | handler = create_leftovers_rule(dev, ft_prio, flow_attr, | |
2699 | dst); | |
cc0e5d42 MG |
2700 | } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { |
2701 | handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); | |
038d2ef8 MG |
2702 | } else { |
2703 | err = -EINVAL; | |
2704 | goto destroy_ft; | |
2705 | } | |
2706 | ||
2707 | if (IS_ERR(handler)) { | |
2708 | err = PTR_ERR(handler); | |
2709 | handler = NULL; | |
2710 | goto destroy_ft; | |
2711 | } | |
2712 | ||
038d2ef8 MG |
2713 | mutex_unlock(&dev->flow_db.lock); |
2714 | kfree(dst); | |
2715 | ||
2716 | return &handler->ibflow; | |
2717 | ||
2718 | destroy_ft: | |
2719 | put_flow_table(dev, ft_prio, false); | |
cc0e5d42 MG |
2720 | if (ft_prio_tx) |
2721 | put_flow_table(dev, ft_prio_tx, false); | |
038d2ef8 MG |
2722 | unlock: |
2723 | mutex_unlock(&dev->flow_db.lock); | |
2724 | kfree(dst); | |
2725 | kfree(handler); | |
2726 | return ERR_PTR(err); | |
2727 | } | |
2728 | ||
e126ba97 EC |
2729 | static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) |
2730 | { | |
2731 | struct mlx5_ib_dev *dev = to_mdev(ibqp->device); | |
81e30880 | 2732 | struct mlx5_ib_qp *mqp = to_mqp(ibqp); |
e126ba97 EC |
2733 | int err; |
2734 | ||
81e30880 YH |
2735 | if (mqp->flags & MLX5_IB_QP_UNDERLAY) { |
2736 | mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); | |
2737 | return -EOPNOTSUPP; | |
2738 | } | |
2739 | ||
9603b61d | 2740 | err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); |
e126ba97 EC |
2741 | if (err) |
2742 | mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", | |
2743 | ibqp->qp_num, gid->raw); | |
2744 | ||
2745 | return err; | |
2746 | } | |
2747 | ||
2748 | static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) | |
2749 | { | |
2750 | struct mlx5_ib_dev *dev = to_mdev(ibqp->device); | |
2751 | int err; | |
2752 | ||
9603b61d | 2753 | err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); |
e126ba97 EC |
2754 | if (err) |
2755 | mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", | |
2756 | ibqp->qp_num, gid->raw); | |
2757 | ||
2758 | return err; | |
2759 | } | |
2760 | ||
2761 | static int init_node_data(struct mlx5_ib_dev *dev) | |
2762 | { | |
1b5daf11 | 2763 | int err; |
e126ba97 | 2764 | |
1b5daf11 | 2765 | err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); |
e126ba97 | 2766 | if (err) |
1b5daf11 | 2767 | return err; |
e126ba97 | 2768 | |
1b5daf11 | 2769 | dev->mdev->rev_id = dev->mdev->pdev->revision; |
e126ba97 | 2770 | |
1b5daf11 | 2771 | return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); |
e126ba97 EC |
2772 | } |
2773 | ||
2774 | static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, | |
2775 | char *buf) | |
2776 | { | |
2777 | struct mlx5_ib_dev *dev = | |
2778 | container_of(device, struct mlx5_ib_dev, ib_dev.dev); | |
2779 | ||
9603b61d | 2780 | return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); |
e126ba97 EC |
2781 | } |
2782 | ||
2783 | static ssize_t show_reg_pages(struct device *device, | |
2784 | struct device_attribute *attr, char *buf) | |
2785 | { | |
2786 | struct mlx5_ib_dev *dev = | |
2787 | container_of(device, struct mlx5_ib_dev, ib_dev.dev); | |
2788 | ||
6aec21f6 | 2789 | return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); |
e126ba97 EC |
2790 | } |
2791 | ||
2792 | static ssize_t show_hca(struct device *device, struct device_attribute *attr, | |
2793 | char *buf) | |
2794 | { | |
2795 | struct mlx5_ib_dev *dev = | |
2796 | container_of(device, struct mlx5_ib_dev, ib_dev.dev); | |
9603b61d | 2797 | return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); |
e126ba97 EC |
2798 | } |
2799 | ||
e126ba97 EC |
2800 | static ssize_t show_rev(struct device *device, struct device_attribute *attr, |
2801 | char *buf) | |
2802 | { | |
2803 | struct mlx5_ib_dev *dev = | |
2804 | container_of(device, struct mlx5_ib_dev, ib_dev.dev); | |
9603b61d | 2805 | return sprintf(buf, "%x\n", dev->mdev->rev_id); |
e126ba97 EC |
2806 | } |
2807 | ||
2808 | static ssize_t show_board(struct device *device, struct device_attribute *attr, | |
2809 | char *buf) | |
2810 | { | |
2811 | struct mlx5_ib_dev *dev = | |
2812 | container_of(device, struct mlx5_ib_dev, ib_dev.dev); | |
2813 | return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, | |
9603b61d | 2814 | dev->mdev->board_id); |
e126ba97 EC |
2815 | } |
2816 | ||
2817 | static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); | |
e126ba97 EC |
2818 | static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); |
2819 | static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); | |
2820 | static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); | |
2821 | static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); | |
2822 | ||
2823 | static struct device_attribute *mlx5_class_attributes[] = { | |
2824 | &dev_attr_hw_rev, | |
e126ba97 EC |
2825 | &dev_attr_hca_type, |
2826 | &dev_attr_board_id, | |
2827 | &dev_attr_fw_pages, | |
2828 | &dev_attr_reg_pages, | |
2829 | }; | |
2830 | ||
7722f47e HE |
2831 | static void pkey_change_handler(struct work_struct *work) |
2832 | { | |
2833 | struct mlx5_ib_port_resources *ports = | |
2834 | container_of(work, struct mlx5_ib_port_resources, | |
2835 | pkey_change_work); | |
2836 | ||
2837 | mutex_lock(&ports->devr->mutex); | |
2838 | mlx5_ib_gsi_pkey_change(ports->gsi); | |
2839 | mutex_unlock(&ports->devr->mutex); | |
2840 | } | |
2841 | ||
89ea94a7 MG |
2842 | static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) |
2843 | { | |
2844 | struct mlx5_ib_qp *mqp; | |
2845 | struct mlx5_ib_cq *send_mcq, *recv_mcq; | |
2846 | struct mlx5_core_cq *mcq; | |
2847 | struct list_head cq_armed_list; | |
2848 | unsigned long flags_qp; | |
2849 | unsigned long flags_cq; | |
2850 | unsigned long flags; | |
2851 | ||
2852 | INIT_LIST_HEAD(&cq_armed_list); | |
2853 | ||
2854 | /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ | |
2855 | spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); | |
2856 | list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { | |
2857 | spin_lock_irqsave(&mqp->sq.lock, flags_qp); | |
2858 | if (mqp->sq.tail != mqp->sq.head) { | |
2859 | send_mcq = to_mcq(mqp->ibqp.send_cq); | |
2860 | spin_lock_irqsave(&send_mcq->lock, flags_cq); | |
2861 | if (send_mcq->mcq.comp && | |
2862 | mqp->ibqp.send_cq->comp_handler) { | |
2863 | if (!send_mcq->mcq.reset_notify_added) { | |
2864 | send_mcq->mcq.reset_notify_added = 1; | |
2865 | list_add_tail(&send_mcq->mcq.reset_notify, | |
2866 | &cq_armed_list); | |
2867 | } | |
2868 | } | |
2869 | spin_unlock_irqrestore(&send_mcq->lock, flags_cq); | |
2870 | } | |
2871 | spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); | |
2872 | spin_lock_irqsave(&mqp->rq.lock, flags_qp); | |
2873 | /* no handling is needed for SRQ */ | |
2874 | if (!mqp->ibqp.srq) { | |
2875 | if (mqp->rq.tail != mqp->rq.head) { | |
2876 | recv_mcq = to_mcq(mqp->ibqp.recv_cq); | |
2877 | spin_lock_irqsave(&recv_mcq->lock, flags_cq); | |
2878 | if (recv_mcq->mcq.comp && | |
2879 | mqp->ibqp.recv_cq->comp_handler) { | |
2880 | if (!recv_mcq->mcq.reset_notify_added) { | |
2881 | recv_mcq->mcq.reset_notify_added = 1; | |
2882 | list_add_tail(&recv_mcq->mcq.reset_notify, | |
2883 | &cq_armed_list); | |
2884 | } | |
2885 | } | |
2886 | spin_unlock_irqrestore(&recv_mcq->lock, | |
2887 | flags_cq); | |
2888 | } | |
2889 | } | |
2890 | spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); | |
2891 | } | |
2892 | /*At that point all inflight post send were put to be executed as of we | |
2893 | * lock/unlock above locks Now need to arm all involved CQs. | |
2894 | */ | |
2895 | list_for_each_entry(mcq, &cq_armed_list, reset_notify) { | |
2896 | mcq->comp(mcq); | |
2897 | } | |
2898 | spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); | |
2899 | } | |
2900 | ||
03404e8a MG |
2901 | static void delay_drop_handler(struct work_struct *work) |
2902 | { | |
2903 | int err; | |
2904 | struct mlx5_ib_delay_drop *delay_drop = | |
2905 | container_of(work, struct mlx5_ib_delay_drop, | |
2906 | delay_drop_work); | |
2907 | ||
fe248c3a MG |
2908 | atomic_inc(&delay_drop->events_cnt); |
2909 | ||
03404e8a MG |
2910 | mutex_lock(&delay_drop->lock); |
2911 | err = mlx5_core_set_delay_drop(delay_drop->dev->mdev, | |
2912 | delay_drop->timeout); | |
2913 | if (err) { | |
2914 | mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", | |
2915 | delay_drop->timeout); | |
2916 | delay_drop->activate = false; | |
2917 | } | |
2918 | mutex_unlock(&delay_drop->lock); | |
2919 | } | |
2920 | ||
9603b61d | 2921 | static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, |
4d2f9bbb | 2922 | enum mlx5_dev_event event, unsigned long param) |
e126ba97 | 2923 | { |
9603b61d | 2924 | struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; |
e126ba97 | 2925 | struct ib_event ibev; |
dbaaff2a | 2926 | bool fatal = false; |
e126ba97 EC |
2927 | u8 port = 0; |
2928 | ||
2929 | switch (event) { | |
2930 | case MLX5_DEV_EVENT_SYS_ERROR: | |
e126ba97 | 2931 | ibev.event = IB_EVENT_DEVICE_FATAL; |
89ea94a7 | 2932 | mlx5_ib_handle_internal_error(ibdev); |
dbaaff2a | 2933 | fatal = true; |
e126ba97 EC |
2934 | break; |
2935 | ||
2936 | case MLX5_DEV_EVENT_PORT_UP: | |
e126ba97 | 2937 | case MLX5_DEV_EVENT_PORT_DOWN: |
2788cf3b | 2938 | case MLX5_DEV_EVENT_PORT_INITIALIZED: |
4d2f9bbb | 2939 | port = (u8)param; |
5ec8c83e AH |
2940 | |
2941 | /* In RoCE, port up/down events are handled in | |
2942 | * mlx5_netdev_event(). | |
2943 | */ | |
2944 | if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == | |
2945 | IB_LINK_LAYER_ETHERNET) | |
2946 | return; | |
2947 | ||
2948 | ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ? | |
2949 | IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; | |
e126ba97 EC |
2950 | break; |
2951 | ||
e126ba97 EC |
2952 | case MLX5_DEV_EVENT_LID_CHANGE: |
2953 | ibev.event = IB_EVENT_LID_CHANGE; | |
4d2f9bbb | 2954 | port = (u8)param; |
e126ba97 EC |
2955 | break; |
2956 | ||
2957 | case MLX5_DEV_EVENT_PKEY_CHANGE: | |
2958 | ibev.event = IB_EVENT_PKEY_CHANGE; | |
4d2f9bbb | 2959 | port = (u8)param; |
7722f47e HE |
2960 | |
2961 | schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); | |
e126ba97 EC |
2962 | break; |
2963 | ||
2964 | case MLX5_DEV_EVENT_GUID_CHANGE: | |
2965 | ibev.event = IB_EVENT_GID_CHANGE; | |
4d2f9bbb | 2966 | port = (u8)param; |
e126ba97 EC |
2967 | break; |
2968 | ||
2969 | case MLX5_DEV_EVENT_CLIENT_REREG: | |
2970 | ibev.event = IB_EVENT_CLIENT_REREGISTER; | |
4d2f9bbb | 2971 | port = (u8)param; |
e126ba97 | 2972 | break; |
03404e8a MG |
2973 | case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT: |
2974 | schedule_work(&ibdev->delay_drop.delay_drop_work); | |
2975 | goto out; | |
bdc37924 | 2976 | default: |
03404e8a | 2977 | goto out; |
e126ba97 EC |
2978 | } |
2979 | ||
2980 | ibev.device = &ibdev->ib_dev; | |
2981 | ibev.element.port_num = port; | |
2982 | ||
a0c84c32 EC |
2983 | if (port < 1 || port > ibdev->num_ports) { |
2984 | mlx5_ib_warn(ibdev, "warning: event on port %d\n", port); | |
03404e8a | 2985 | goto out; |
a0c84c32 EC |
2986 | } |
2987 | ||
e126ba97 EC |
2988 | if (ibdev->ib_active) |
2989 | ib_dispatch_event(&ibev); | |
dbaaff2a EC |
2990 | |
2991 | if (fatal) | |
2992 | ibdev->ib_active = false; | |
03404e8a MG |
2993 | |
2994 | out: | |
2995 | return; | |
e126ba97 EC |
2996 | } |
2997 | ||
c43f1112 MG |
2998 | static int set_has_smi_cap(struct mlx5_ib_dev *dev) |
2999 | { | |
3000 | struct mlx5_hca_vport_context vport_ctx; | |
3001 | int err; | |
3002 | int port; | |
3003 | ||
3004 | for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { | |
3005 | dev->mdev->port_caps[port - 1].has_smi = false; | |
3006 | if (MLX5_CAP_GEN(dev->mdev, port_type) == | |
3007 | MLX5_CAP_PORT_TYPE_IB) { | |
3008 | if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { | |
3009 | err = mlx5_query_hca_vport_context(dev->mdev, 0, | |
3010 | port, 0, | |
3011 | &vport_ctx); | |
3012 | if (err) { | |
3013 | mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", | |
3014 | port, err); | |
3015 | return err; | |
3016 | } | |
3017 | dev->mdev->port_caps[port - 1].has_smi = | |
3018 | vport_ctx.has_smi; | |
3019 | } else { | |
3020 | dev->mdev->port_caps[port - 1].has_smi = true; | |
3021 | } | |
3022 | } | |
3023 | } | |
3024 | return 0; | |
3025 | } | |
3026 | ||
e126ba97 EC |
3027 | static void get_ext_port_caps(struct mlx5_ib_dev *dev) |
3028 | { | |
3029 | int port; | |
3030 | ||
938fe83c | 3031 | for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) |
e126ba97 EC |
3032 | mlx5_query_ext_port_caps(dev, port); |
3033 | } | |
3034 | ||
3035 | static int get_port_caps(struct mlx5_ib_dev *dev) | |
3036 | { | |
3037 | struct ib_device_attr *dprops = NULL; | |
3038 | struct ib_port_attr *pprops = NULL; | |
f614fc15 | 3039 | int err = -ENOMEM; |
e126ba97 | 3040 | int port; |
2528e33e | 3041 | struct ib_udata uhw = {.inlen = 0, .outlen = 0}; |
e126ba97 EC |
3042 | |
3043 | pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); | |
3044 | if (!pprops) | |
3045 | goto out; | |
3046 | ||
3047 | dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); | |
3048 | if (!dprops) | |
3049 | goto out; | |
3050 | ||
c43f1112 MG |
3051 | err = set_has_smi_cap(dev); |
3052 | if (err) | |
3053 | goto out; | |
3054 | ||
2528e33e | 3055 | err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); |
e126ba97 EC |
3056 | if (err) { |
3057 | mlx5_ib_warn(dev, "query_device failed %d\n", err); | |
3058 | goto out; | |
3059 | } | |
3060 | ||
938fe83c | 3061 | for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { |
c4550c63 | 3062 | memset(pprops, 0, sizeof(*pprops)); |
e126ba97 EC |
3063 | err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); |
3064 | if (err) { | |
938fe83c SM |
3065 | mlx5_ib_warn(dev, "query_port %d failed %d\n", |
3066 | port, err); | |
e126ba97 EC |
3067 | break; |
3068 | } | |
938fe83c SM |
3069 | dev->mdev->port_caps[port - 1].pkey_table_len = |
3070 | dprops->max_pkeys; | |
3071 | dev->mdev->port_caps[port - 1].gid_table_len = | |
3072 | pprops->gid_tbl_len; | |
e126ba97 EC |
3073 | mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n", |
3074 | dprops->max_pkeys, pprops->gid_tbl_len); | |
3075 | } | |
3076 | ||
3077 | out: | |
3078 | kfree(pprops); | |
3079 | kfree(dprops); | |
3080 | ||
3081 | return err; | |
3082 | } | |
3083 | ||
3084 | static void destroy_umrc_res(struct mlx5_ib_dev *dev) | |
3085 | { | |
3086 | int err; | |
3087 | ||
3088 | err = mlx5_mr_cache_cleanup(dev); | |
3089 | if (err) | |
3090 | mlx5_ib_warn(dev, "mr cache cleanup failed\n"); | |
3091 | ||
3092 | mlx5_ib_destroy_qp(dev->umrc.qp); | |
add08d76 | 3093 | ib_free_cq(dev->umrc.cq); |
e126ba97 EC |
3094 | ib_dealloc_pd(dev->umrc.pd); |
3095 | } | |
3096 | ||
3097 | enum { | |
3098 | MAX_UMR_WR = 128, | |
3099 | }; | |
3100 | ||
3101 | static int create_umr_res(struct mlx5_ib_dev *dev) | |
3102 | { | |
3103 | struct ib_qp_init_attr *init_attr = NULL; | |
3104 | struct ib_qp_attr *attr = NULL; | |
3105 | struct ib_pd *pd; | |
3106 | struct ib_cq *cq; | |
3107 | struct ib_qp *qp; | |
e126ba97 EC |
3108 | int ret; |
3109 | ||
3110 | attr = kzalloc(sizeof(*attr), GFP_KERNEL); | |
3111 | init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); | |
3112 | if (!attr || !init_attr) { | |
3113 | ret = -ENOMEM; | |
3114 | goto error_0; | |
3115 | } | |
3116 | ||
ed082d36 | 3117 | pd = ib_alloc_pd(&dev->ib_dev, 0); |
e126ba97 EC |
3118 | if (IS_ERR(pd)) { |
3119 | mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); | |
3120 | ret = PTR_ERR(pd); | |
3121 | goto error_0; | |
3122 | } | |
3123 | ||
add08d76 | 3124 | cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); |
e126ba97 EC |
3125 | if (IS_ERR(cq)) { |
3126 | mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); | |
3127 | ret = PTR_ERR(cq); | |
3128 | goto error_2; | |
3129 | } | |
e126ba97 EC |
3130 | |
3131 | init_attr->send_cq = cq; | |
3132 | init_attr->recv_cq = cq; | |
3133 | init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; | |
3134 | init_attr->cap.max_send_wr = MAX_UMR_WR; | |
3135 | init_attr->cap.max_send_sge = 1; | |
3136 | init_attr->qp_type = MLX5_IB_QPT_REG_UMR; | |
3137 | init_attr->port_num = 1; | |
3138 | qp = mlx5_ib_create_qp(pd, init_attr, NULL); | |
3139 | if (IS_ERR(qp)) { | |
3140 | mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); | |
3141 | ret = PTR_ERR(qp); | |
3142 | goto error_3; | |
3143 | } | |
3144 | qp->device = &dev->ib_dev; | |
3145 | qp->real_qp = qp; | |
3146 | qp->uobject = NULL; | |
3147 | qp->qp_type = MLX5_IB_QPT_REG_UMR; | |
31fde034 MD |
3148 | qp->send_cq = init_attr->send_cq; |
3149 | qp->recv_cq = init_attr->recv_cq; | |
e126ba97 EC |
3150 | |
3151 | attr->qp_state = IB_QPS_INIT; | |
3152 | attr->port_num = 1; | |
3153 | ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | | |
3154 | IB_QP_PORT, NULL); | |
3155 | if (ret) { | |
3156 | mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); | |
3157 | goto error_4; | |
3158 | } | |
3159 | ||
3160 | memset(attr, 0, sizeof(*attr)); | |
3161 | attr->qp_state = IB_QPS_RTR; | |
3162 | attr->path_mtu = IB_MTU_256; | |
3163 | ||
3164 | ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); | |
3165 | if (ret) { | |
3166 | mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); | |
3167 | goto error_4; | |
3168 | } | |
3169 | ||
3170 | memset(attr, 0, sizeof(*attr)); | |
3171 | attr->qp_state = IB_QPS_RTS; | |
3172 | ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); | |
3173 | if (ret) { | |
3174 | mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); | |
3175 | goto error_4; | |
3176 | } | |
3177 | ||
3178 | dev->umrc.qp = qp; | |
3179 | dev->umrc.cq = cq; | |
e126ba97 EC |
3180 | dev->umrc.pd = pd; |
3181 | ||
3182 | sema_init(&dev->umrc.sem, MAX_UMR_WR); | |
3183 | ret = mlx5_mr_cache_init(dev); | |
3184 | if (ret) { | |
3185 | mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); | |
3186 | goto error_4; | |
3187 | } | |
3188 | ||
3189 | kfree(attr); | |
3190 | kfree(init_attr); | |
3191 | ||
3192 | return 0; | |
3193 | ||
3194 | error_4: | |
3195 | mlx5_ib_destroy_qp(qp); | |
3196 | ||
3197 | error_3: | |
add08d76 | 3198 | ib_free_cq(cq); |
e126ba97 EC |
3199 | |
3200 | error_2: | |
e126ba97 EC |
3201 | ib_dealloc_pd(pd); |
3202 | ||
3203 | error_0: | |
3204 | kfree(attr); | |
3205 | kfree(init_attr); | |
3206 | return ret; | |
3207 | } | |
3208 | ||
6e8484c5 MG |
3209 | static u8 mlx5_get_umr_fence(u8 umr_fence_cap) |
3210 | { | |
3211 | switch (umr_fence_cap) { | |
3212 | case MLX5_CAP_UMR_FENCE_NONE: | |
3213 | return MLX5_FENCE_MODE_NONE; | |
3214 | case MLX5_CAP_UMR_FENCE_SMALL: | |
3215 | return MLX5_FENCE_MODE_INITIATOR_SMALL; | |
3216 | default: | |
3217 | return MLX5_FENCE_MODE_STRONG_ORDERING; | |
3218 | } | |
3219 | } | |
3220 | ||
e126ba97 EC |
3221 | static int create_dev_resources(struct mlx5_ib_resources *devr) |
3222 | { | |
3223 | struct ib_srq_init_attr attr; | |
3224 | struct mlx5_ib_dev *dev; | |
bcf4c1ea | 3225 | struct ib_cq_init_attr cq_attr = {.cqe = 1}; |
7722f47e | 3226 | int port; |
e126ba97 EC |
3227 | int ret = 0; |
3228 | ||
3229 | dev = container_of(devr, struct mlx5_ib_dev, devr); | |
3230 | ||
d16e91da HE |
3231 | mutex_init(&devr->mutex); |
3232 | ||
e126ba97 EC |
3233 | devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); |
3234 | if (IS_ERR(devr->p0)) { | |
3235 | ret = PTR_ERR(devr->p0); | |
3236 | goto error0; | |
3237 | } | |
3238 | devr->p0->device = &dev->ib_dev; | |
3239 | devr->p0->uobject = NULL; | |
3240 | atomic_set(&devr->p0->usecnt, 0); | |
3241 | ||
bcf4c1ea | 3242 | devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); |
e126ba97 EC |
3243 | if (IS_ERR(devr->c0)) { |
3244 | ret = PTR_ERR(devr->c0); | |
3245 | goto error1; | |
3246 | } | |
3247 | devr->c0->device = &dev->ib_dev; | |
3248 | devr->c0->uobject = NULL; | |
3249 | devr->c0->comp_handler = NULL; | |
3250 | devr->c0->event_handler = NULL; | |
3251 | devr->c0->cq_context = NULL; | |
3252 | atomic_set(&devr->c0->usecnt, 0); | |
3253 | ||
3254 | devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); | |
3255 | if (IS_ERR(devr->x0)) { | |
3256 | ret = PTR_ERR(devr->x0); | |
3257 | goto error2; | |
3258 | } | |
3259 | devr->x0->device = &dev->ib_dev; | |
3260 | devr->x0->inode = NULL; | |
3261 | atomic_set(&devr->x0->usecnt, 0); | |
3262 | mutex_init(&devr->x0->tgt_qp_mutex); | |
3263 | INIT_LIST_HEAD(&devr->x0->tgt_qp_list); | |
3264 | ||
3265 | devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); | |
3266 | if (IS_ERR(devr->x1)) { | |
3267 | ret = PTR_ERR(devr->x1); | |
3268 | goto error3; | |
3269 | } | |
3270 | devr->x1->device = &dev->ib_dev; | |
3271 | devr->x1->inode = NULL; | |
3272 | atomic_set(&devr->x1->usecnt, 0); | |
3273 | mutex_init(&devr->x1->tgt_qp_mutex); | |
3274 | INIT_LIST_HEAD(&devr->x1->tgt_qp_list); | |
3275 | ||
3276 | memset(&attr, 0, sizeof(attr)); | |
3277 | attr.attr.max_sge = 1; | |
3278 | attr.attr.max_wr = 1; | |
3279 | attr.srq_type = IB_SRQT_XRC; | |
1a56ff6d | 3280 | attr.ext.cq = devr->c0; |
e126ba97 EC |
3281 | attr.ext.xrc.xrcd = devr->x0; |
3282 | ||
3283 | devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); | |
3284 | if (IS_ERR(devr->s0)) { | |
3285 | ret = PTR_ERR(devr->s0); | |
3286 | goto error4; | |
3287 | } | |
3288 | devr->s0->device = &dev->ib_dev; | |
3289 | devr->s0->pd = devr->p0; | |
3290 | devr->s0->uobject = NULL; | |
3291 | devr->s0->event_handler = NULL; | |
3292 | devr->s0->srq_context = NULL; | |
3293 | devr->s0->srq_type = IB_SRQT_XRC; | |
3294 | devr->s0->ext.xrc.xrcd = devr->x0; | |
1a56ff6d | 3295 | devr->s0->ext.cq = devr->c0; |
e126ba97 | 3296 | atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); |
1a56ff6d | 3297 | atomic_inc(&devr->s0->ext.cq->usecnt); |
e126ba97 EC |
3298 | atomic_inc(&devr->p0->usecnt); |
3299 | atomic_set(&devr->s0->usecnt, 0); | |
3300 | ||
4aa17b28 HA |
3301 | memset(&attr, 0, sizeof(attr)); |
3302 | attr.attr.max_sge = 1; | |
3303 | attr.attr.max_wr = 1; | |
3304 | attr.srq_type = IB_SRQT_BASIC; | |
3305 | devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); | |
3306 | if (IS_ERR(devr->s1)) { | |
3307 | ret = PTR_ERR(devr->s1); | |
3308 | goto error5; | |
3309 | } | |
3310 | devr->s1->device = &dev->ib_dev; | |
3311 | devr->s1->pd = devr->p0; | |
3312 | devr->s1->uobject = NULL; | |
3313 | devr->s1->event_handler = NULL; | |
3314 | devr->s1->srq_context = NULL; | |
3315 | devr->s1->srq_type = IB_SRQT_BASIC; | |
1a56ff6d | 3316 | devr->s1->ext.cq = devr->c0; |
4aa17b28 | 3317 | atomic_inc(&devr->p0->usecnt); |
1a56ff6d | 3318 | atomic_set(&devr->s1->usecnt, 0); |
4aa17b28 | 3319 | |
7722f47e HE |
3320 | for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { |
3321 | INIT_WORK(&devr->ports[port].pkey_change_work, | |
3322 | pkey_change_handler); | |
3323 | devr->ports[port].devr = devr; | |
3324 | } | |
3325 | ||
e126ba97 EC |
3326 | return 0; |
3327 | ||
4aa17b28 HA |
3328 | error5: |
3329 | mlx5_ib_destroy_srq(devr->s0); | |
e126ba97 EC |
3330 | error4: |
3331 | mlx5_ib_dealloc_xrcd(devr->x1); | |
3332 | error3: | |
3333 | mlx5_ib_dealloc_xrcd(devr->x0); | |
3334 | error2: | |
3335 | mlx5_ib_destroy_cq(devr->c0); | |
3336 | error1: | |
3337 | mlx5_ib_dealloc_pd(devr->p0); | |
3338 | error0: | |
3339 | return ret; | |
3340 | } | |
3341 | ||
3342 | static void destroy_dev_resources(struct mlx5_ib_resources *devr) | |
3343 | { | |
7722f47e HE |
3344 | struct mlx5_ib_dev *dev = |
3345 | container_of(devr, struct mlx5_ib_dev, devr); | |
3346 | int port; | |
3347 | ||
4aa17b28 | 3348 | mlx5_ib_destroy_srq(devr->s1); |
e126ba97 EC |
3349 | mlx5_ib_destroy_srq(devr->s0); |
3350 | mlx5_ib_dealloc_xrcd(devr->x0); | |
3351 | mlx5_ib_dealloc_xrcd(devr->x1); | |
3352 | mlx5_ib_destroy_cq(devr->c0); | |
3353 | mlx5_ib_dealloc_pd(devr->p0); | |
7722f47e HE |
3354 | |
3355 | /* Make sure no change P_Key work items are still executing */ | |
3356 | for (port = 0; port < dev->num_ports; ++port) | |
3357 | cancel_work_sync(&devr->ports[port].pkey_change_work); | |
e126ba97 EC |
3358 | } |
3359 | ||
e53505a8 AS |
3360 | static u32 get_core_cap_flags(struct ib_device *ibdev) |
3361 | { | |
3362 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
3363 | enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); | |
3364 | u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); | |
3365 | u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); | |
3366 | u32 ret = 0; | |
3367 | ||
3368 | if (ll == IB_LINK_LAYER_INFINIBAND) | |
3369 | return RDMA_CORE_PORT_IBA_IB; | |
3370 | ||
72cd5717 OG |
3371 | ret = RDMA_CORE_PORT_RAW_PACKET; |
3372 | ||
e53505a8 | 3373 | if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) |
72cd5717 | 3374 | return ret; |
e53505a8 AS |
3375 | |
3376 | if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) | |
72cd5717 | 3377 | return ret; |
e53505a8 AS |
3378 | |
3379 | if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) | |
3380 | ret |= RDMA_CORE_PORT_IBA_ROCE; | |
3381 | ||
3382 | if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) | |
3383 | ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; | |
3384 | ||
3385 | return ret; | |
3386 | } | |
3387 | ||
7738613e IW |
3388 | static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, |
3389 | struct ib_port_immutable *immutable) | |
3390 | { | |
3391 | struct ib_port_attr attr; | |
ca5b91d6 OG |
3392 | struct mlx5_ib_dev *dev = to_mdev(ibdev); |
3393 | enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); | |
7738613e IW |
3394 | int err; |
3395 | ||
c4550c63 OG |
3396 | immutable->core_cap_flags = get_core_cap_flags(ibdev); |
3397 | ||
3398 | err = ib_query_port(ibdev, port_num, &attr); | |
7738613e IW |
3399 | if (err) |
3400 | return err; | |
3401 | ||
3402 | immutable->pkey_tbl_len = attr.pkey_tbl_len; | |
3403 | immutable->gid_tbl_len = attr.gid_tbl_len; | |
e53505a8 | 3404 | immutable->core_cap_flags = get_core_cap_flags(ibdev); |
ca5b91d6 OG |
3405 | if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce)) |
3406 | immutable->max_mad_size = IB_MGMT_MAD_SIZE; | |
7738613e IW |
3407 | |
3408 | return 0; | |
3409 | } | |
3410 | ||
9abb0d1b | 3411 | static void get_dev_fw_str(struct ib_device *ibdev, char *str) |
c7342823 IW |
3412 | { |
3413 | struct mlx5_ib_dev *dev = | |
3414 | container_of(ibdev, struct mlx5_ib_dev, ib_dev); | |
9abb0d1b LR |
3415 | snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", |
3416 | fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), | |
3417 | fw_rev_sub(dev->mdev)); | |
c7342823 IW |
3418 | } |
3419 | ||
45f95acd | 3420 | static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) |
9ef9c640 AH |
3421 | { |
3422 | struct mlx5_core_dev *mdev = dev->mdev; | |
3423 | struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, | |
3424 | MLX5_FLOW_NAMESPACE_LAG); | |
3425 | struct mlx5_flow_table *ft; | |
3426 | int err; | |
3427 | ||
3428 | if (!ns || !mlx5_lag_is_active(mdev)) | |
3429 | return 0; | |
3430 | ||
3431 | err = mlx5_cmd_create_vport_lag(mdev); | |
3432 | if (err) | |
3433 | return err; | |
3434 | ||
3435 | ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); | |
3436 | if (IS_ERR(ft)) { | |
3437 | err = PTR_ERR(ft); | |
3438 | goto err_destroy_vport_lag; | |
3439 | } | |
3440 | ||
3441 | dev->flow_db.lag_demux_ft = ft; | |
3442 | return 0; | |
3443 | ||
3444 | err_destroy_vport_lag: | |
3445 | mlx5_cmd_destroy_vport_lag(mdev); | |
3446 | return err; | |
3447 | } | |
3448 | ||
45f95acd | 3449 | static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) |
9ef9c640 AH |
3450 | { |
3451 | struct mlx5_core_dev *mdev = dev->mdev; | |
3452 | ||
3453 | if (dev->flow_db.lag_demux_ft) { | |
3454 | mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft); | |
3455 | dev->flow_db.lag_demux_ft = NULL; | |
3456 | ||
3457 | mlx5_cmd_destroy_vport_lag(mdev); | |
3458 | } | |
3459 | } | |
3460 | ||
d012f5d6 OG |
3461 | static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev) |
3462 | { | |
3463 | int err; | |
3464 | ||
3465 | dev->roce.nb.notifier_call = mlx5_netdev_event; | |
3466 | err = register_netdevice_notifier(&dev->roce.nb); | |
3467 | if (err) { | |
3468 | dev->roce.nb.notifier_call = NULL; | |
3469 | return err; | |
3470 | } | |
3471 | ||
3472 | return 0; | |
3473 | } | |
3474 | ||
3475 | static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev) | |
5ec8c83e AH |
3476 | { |
3477 | if (dev->roce.nb.notifier_call) { | |
3478 | unregister_netdevice_notifier(&dev->roce.nb); | |
3479 | dev->roce.nb.notifier_call = NULL; | |
3480 | } | |
3481 | } | |
3482 | ||
45f95acd | 3483 | static int mlx5_enable_eth(struct mlx5_ib_dev *dev) |
fc24fc5e | 3484 | { |
e53505a8 AS |
3485 | int err; |
3486 | ||
d012f5d6 OG |
3487 | err = mlx5_add_netdev_notifier(dev); |
3488 | if (err) | |
e53505a8 AS |
3489 | return err; |
3490 | ||
ca5b91d6 OG |
3491 | if (MLX5_CAP_GEN(dev->mdev, roce)) { |
3492 | err = mlx5_nic_vport_enable_roce(dev->mdev); | |
3493 | if (err) | |
3494 | goto err_unregister_netdevice_notifier; | |
3495 | } | |
e53505a8 | 3496 | |
45f95acd | 3497 | err = mlx5_eth_lag_init(dev); |
9ef9c640 AH |
3498 | if (err) |
3499 | goto err_disable_roce; | |
3500 | ||
e53505a8 AS |
3501 | return 0; |
3502 | ||
9ef9c640 | 3503 | err_disable_roce: |
ca5b91d6 OG |
3504 | if (MLX5_CAP_GEN(dev->mdev, roce)) |
3505 | mlx5_nic_vport_disable_roce(dev->mdev); | |
9ef9c640 | 3506 | |
e53505a8 | 3507 | err_unregister_netdevice_notifier: |
d012f5d6 | 3508 | mlx5_remove_netdev_notifier(dev); |
e53505a8 | 3509 | return err; |
fc24fc5e AS |
3510 | } |
3511 | ||
45f95acd | 3512 | static void mlx5_disable_eth(struct mlx5_ib_dev *dev) |
fc24fc5e | 3513 | { |
45f95acd | 3514 | mlx5_eth_lag_cleanup(dev); |
ca5b91d6 OG |
3515 | if (MLX5_CAP_GEN(dev->mdev, roce)) |
3516 | mlx5_nic_vport_disable_roce(dev->mdev); | |
fc24fc5e AS |
3517 | } |
3518 | ||
e1f24a79 | 3519 | struct mlx5_ib_counter { |
7c16f477 KH |
3520 | const char *name; |
3521 | size_t offset; | |
3522 | }; | |
3523 | ||
3524 | #define INIT_Q_COUNTER(_name) \ | |
3525 | { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)} | |
3526 | ||
e1f24a79 | 3527 | static const struct mlx5_ib_counter basic_q_cnts[] = { |
7c16f477 KH |
3528 | INIT_Q_COUNTER(rx_write_requests), |
3529 | INIT_Q_COUNTER(rx_read_requests), | |
3530 | INIT_Q_COUNTER(rx_atomic_requests), | |
3531 | INIT_Q_COUNTER(out_of_buffer), | |
3532 | }; | |
3533 | ||
e1f24a79 | 3534 | static const struct mlx5_ib_counter out_of_seq_q_cnts[] = { |
7c16f477 KH |
3535 | INIT_Q_COUNTER(out_of_sequence), |
3536 | }; | |
3537 | ||
e1f24a79 | 3538 | static const struct mlx5_ib_counter retrans_q_cnts[] = { |
7c16f477 KH |
3539 | INIT_Q_COUNTER(duplicate_request), |
3540 | INIT_Q_COUNTER(rnr_nak_retry_err), | |
3541 | INIT_Q_COUNTER(packet_seq_err), | |
3542 | INIT_Q_COUNTER(implied_nak_seq_err), | |
3543 | INIT_Q_COUNTER(local_ack_timeout_err), | |
3544 | }; | |
3545 | ||
e1f24a79 PP |
3546 | #define INIT_CONG_COUNTER(_name) \ |
3547 | { .name = #_name, .offset = \ | |
3548 | MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)} | |
3549 | ||
3550 | static const struct mlx5_ib_counter cong_cnts[] = { | |
3551 | INIT_CONG_COUNTER(rp_cnp_ignored), | |
3552 | INIT_CONG_COUNTER(rp_cnp_handled), | |
3553 | INIT_CONG_COUNTER(np_ecn_marked_roce_packets), | |
3554 | INIT_CONG_COUNTER(np_cnp_sent), | |
3555 | }; | |
3556 | ||
58dcb60a PP |
3557 | static const struct mlx5_ib_counter extended_err_cnts[] = { |
3558 | INIT_Q_COUNTER(resp_local_length_error), | |
3559 | INIT_Q_COUNTER(resp_cqe_error), | |
3560 | INIT_Q_COUNTER(req_cqe_error), | |
3561 | INIT_Q_COUNTER(req_remote_invalid_request), | |
3562 | INIT_Q_COUNTER(req_remote_access_errors), | |
3563 | INIT_Q_COUNTER(resp_remote_access_errors), | |
3564 | INIT_Q_COUNTER(resp_cqe_flush_error), | |
3565 | INIT_Q_COUNTER(req_cqe_flush_error), | |
3566 | }; | |
3567 | ||
e1f24a79 | 3568 | static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev) |
0837e86a MB |
3569 | { |
3570 | unsigned int i; | |
3571 | ||
7c16f477 | 3572 | for (i = 0; i < dev->num_ports; i++) { |
0837e86a | 3573 | mlx5_core_dealloc_q_counter(dev->mdev, |
e1f24a79 PP |
3574 | dev->port[i].cnts.set_id); |
3575 | kfree(dev->port[i].cnts.names); | |
3576 | kfree(dev->port[i].cnts.offsets); | |
7c16f477 KH |
3577 | } |
3578 | } | |
3579 | ||
e1f24a79 PP |
3580 | static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev, |
3581 | struct mlx5_ib_counters *cnts) | |
7c16f477 KH |
3582 | { |
3583 | u32 num_counters; | |
3584 | ||
3585 | num_counters = ARRAY_SIZE(basic_q_cnts); | |
3586 | ||
3587 | if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) | |
3588 | num_counters += ARRAY_SIZE(out_of_seq_q_cnts); | |
3589 | ||
3590 | if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) | |
3591 | num_counters += ARRAY_SIZE(retrans_q_cnts); | |
58dcb60a PP |
3592 | |
3593 | if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) | |
3594 | num_counters += ARRAY_SIZE(extended_err_cnts); | |
3595 | ||
e1f24a79 | 3596 | cnts->num_q_counters = num_counters; |
7c16f477 | 3597 | |
e1f24a79 PP |
3598 | if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { |
3599 | cnts->num_cong_counters = ARRAY_SIZE(cong_cnts); | |
3600 | num_counters += ARRAY_SIZE(cong_cnts); | |
3601 | } | |
3602 | ||
3603 | cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL); | |
3604 | if (!cnts->names) | |
7c16f477 KH |
3605 | return -ENOMEM; |
3606 | ||
e1f24a79 PP |
3607 | cnts->offsets = kcalloc(num_counters, |
3608 | sizeof(cnts->offsets), GFP_KERNEL); | |
3609 | if (!cnts->offsets) | |
7c16f477 KH |
3610 | goto err_names; |
3611 | ||
7c16f477 KH |
3612 | return 0; |
3613 | ||
3614 | err_names: | |
e1f24a79 | 3615 | kfree(cnts->names); |
7c16f477 KH |
3616 | return -ENOMEM; |
3617 | } | |
3618 | ||
e1f24a79 PP |
3619 | static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev, |
3620 | const char **names, | |
3621 | size_t *offsets) | |
7c16f477 KH |
3622 | { |
3623 | int i; | |
3624 | int j = 0; | |
3625 | ||
3626 | for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) { | |
3627 | names[j] = basic_q_cnts[i].name; | |
3628 | offsets[j] = basic_q_cnts[i].offset; | |
3629 | } | |
3630 | ||
3631 | if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) { | |
3632 | for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) { | |
3633 | names[j] = out_of_seq_q_cnts[i].name; | |
3634 | offsets[j] = out_of_seq_q_cnts[i].offset; | |
3635 | } | |
3636 | } | |
3637 | ||
3638 | if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { | |
3639 | for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) { | |
3640 | names[j] = retrans_q_cnts[i].name; | |
3641 | offsets[j] = retrans_q_cnts[i].offset; | |
3642 | } | |
3643 | } | |
e1f24a79 | 3644 | |
58dcb60a PP |
3645 | if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) { |
3646 | for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) { | |
3647 | names[j] = extended_err_cnts[i].name; | |
3648 | offsets[j] = extended_err_cnts[i].offset; | |
3649 | } | |
3650 | } | |
3651 | ||
e1f24a79 PP |
3652 | if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { |
3653 | for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) { | |
3654 | names[j] = cong_cnts[i].name; | |
3655 | offsets[j] = cong_cnts[i].offset; | |
3656 | } | |
3657 | } | |
0837e86a MB |
3658 | } |
3659 | ||
e1f24a79 | 3660 | static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev) |
0837e86a MB |
3661 | { |
3662 | int i; | |
3663 | int ret; | |
3664 | ||
3665 | for (i = 0; i < dev->num_ports; i++) { | |
7c16f477 KH |
3666 | struct mlx5_ib_port *port = &dev->port[i]; |
3667 | ||
0837e86a | 3668 | ret = mlx5_core_alloc_q_counter(dev->mdev, |
e1f24a79 | 3669 | &port->cnts.set_id); |
0837e86a MB |
3670 | if (ret) { |
3671 | mlx5_ib_warn(dev, | |
3672 | "couldn't allocate queue counter for port %d, err %d\n", | |
3673 | i + 1, ret); | |
3674 | goto dealloc_counters; | |
3675 | } | |
7c16f477 | 3676 | |
e1f24a79 | 3677 | ret = __mlx5_ib_alloc_counters(dev, &port->cnts); |
7c16f477 KH |
3678 | if (ret) |
3679 | goto dealloc_counters; | |
3680 | ||
e1f24a79 PP |
3681 | mlx5_ib_fill_counters(dev, port->cnts.names, |
3682 | port->cnts.offsets); | |
0837e86a MB |
3683 | } |
3684 | ||
3685 | return 0; | |
3686 | ||
3687 | dealloc_counters: | |
3688 | while (--i >= 0) | |
3689 | mlx5_core_dealloc_q_counter(dev->mdev, | |
e1f24a79 | 3690 | dev->port[i].cnts.set_id); |
0837e86a MB |
3691 | |
3692 | return ret; | |
3693 | } | |
3694 | ||
0ad17a8f MB |
3695 | static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, |
3696 | u8 port_num) | |
3697 | { | |
7c16f477 KH |
3698 | struct mlx5_ib_dev *dev = to_mdev(ibdev); |
3699 | struct mlx5_ib_port *port = &dev->port[port_num - 1]; | |
0ad17a8f MB |
3700 | |
3701 | /* We support only per port stats */ | |
3702 | if (port_num == 0) | |
3703 | return NULL; | |
3704 | ||
e1f24a79 PP |
3705 | return rdma_alloc_hw_stats_struct(port->cnts.names, |
3706 | port->cnts.num_q_counters + | |
3707 | port->cnts.num_cong_counters, | |
0ad17a8f MB |
3708 | RDMA_HW_STATS_DEFAULT_LIFESPAN); |
3709 | } | |
3710 | ||
e1f24a79 PP |
3711 | static int mlx5_ib_query_q_counters(struct mlx5_ib_dev *dev, |
3712 | struct mlx5_ib_port *port, | |
3713 | struct rdma_hw_stats *stats) | |
0ad17a8f | 3714 | { |
0ad17a8f MB |
3715 | int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); |
3716 | void *out; | |
3717 | __be32 val; | |
e1f24a79 | 3718 | int ret, i; |
0ad17a8f | 3719 | |
1b9a07ee | 3720 | out = kvzalloc(outlen, GFP_KERNEL); |
0ad17a8f MB |
3721 | if (!out) |
3722 | return -ENOMEM; | |
3723 | ||
3724 | ret = mlx5_core_query_q_counter(dev->mdev, | |
e1f24a79 | 3725 | port->cnts.set_id, 0, |
0ad17a8f MB |
3726 | out, outlen); |
3727 | if (ret) | |
3728 | goto free; | |
3729 | ||
e1f24a79 PP |
3730 | for (i = 0; i < port->cnts.num_q_counters; i++) { |
3731 | val = *(__be32 *)(out + port->cnts.offsets[i]); | |
0ad17a8f MB |
3732 | stats->value[i] = (u64)be32_to_cpu(val); |
3733 | } | |
7c16f477 | 3734 | |
0ad17a8f MB |
3735 | free: |
3736 | kvfree(out); | |
e1f24a79 PP |
3737 | return ret; |
3738 | } | |
3739 | ||
3740 | static int mlx5_ib_query_cong_counters(struct mlx5_ib_dev *dev, | |
3741 | struct mlx5_ib_port *port, | |
3742 | struct rdma_hw_stats *stats) | |
3743 | { | |
3744 | int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out); | |
3745 | void *out; | |
3746 | int ret, i; | |
3747 | int offset = port->cnts.num_q_counters; | |
3748 | ||
1b9a07ee | 3749 | out = kvzalloc(outlen, GFP_KERNEL); |
e1f24a79 PP |
3750 | if (!out) |
3751 | return -ENOMEM; | |
3752 | ||
3753 | ret = mlx5_cmd_query_cong_counter(dev->mdev, false, out, outlen); | |
3754 | if (ret) | |
3755 | goto free; | |
3756 | ||
3757 | for (i = 0; i < port->cnts.num_cong_counters; i++) { | |
3758 | stats->value[i + offset] = | |
3759 | be64_to_cpup((__be64 *)(out + | |
3760 | port->cnts.offsets[i + offset])); | |
3761 | } | |
3762 | ||
3763 | free: | |
3764 | kvfree(out); | |
3765 | return ret; | |
3766 | } | |
3767 | ||
3768 | static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, | |
3769 | struct rdma_hw_stats *stats, | |
3770 | u8 port_num, int index) | |
3771 | { | |
3772 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
3773 | struct mlx5_ib_port *port = &dev->port[port_num - 1]; | |
3774 | int ret, num_counters; | |
3775 | ||
3776 | if (!stats) | |
3777 | return -EINVAL; | |
3778 | ||
3779 | ret = mlx5_ib_query_q_counters(dev, port, stats); | |
3780 | if (ret) | |
3781 | return ret; | |
3782 | num_counters = port->cnts.num_q_counters; | |
3783 | ||
3784 | if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { | |
3785 | ret = mlx5_ib_query_cong_counters(dev, port, stats); | |
3786 | if (ret) | |
3787 | return ret; | |
3788 | num_counters += port->cnts.num_cong_counters; | |
3789 | } | |
3790 | ||
3791 | return num_counters; | |
0ad17a8f MB |
3792 | } |
3793 | ||
8e959601 NV |
3794 | static void mlx5_ib_free_rdma_netdev(struct net_device *netdev) |
3795 | { | |
3796 | return mlx5_rdma_netdev_free(netdev); | |
3797 | } | |
3798 | ||
693dfd5a ES |
3799 | static struct net_device* |
3800 | mlx5_ib_alloc_rdma_netdev(struct ib_device *hca, | |
3801 | u8 port_num, | |
3802 | enum rdma_netdev_t type, | |
3803 | const char *name, | |
3804 | unsigned char name_assign_type, | |
3805 | void (*setup)(struct net_device *)) | |
3806 | { | |
8e959601 NV |
3807 | struct net_device *netdev; |
3808 | struct rdma_netdev *rn; | |
3809 | ||
693dfd5a ES |
3810 | if (type != RDMA_NETDEV_IPOIB) |
3811 | return ERR_PTR(-EOPNOTSUPP); | |
3812 | ||
8e959601 NV |
3813 | netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca, |
3814 | name, setup); | |
3815 | if (likely(!IS_ERR_OR_NULL(netdev))) { | |
3816 | rn = netdev_priv(netdev); | |
3817 | rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev; | |
3818 | } | |
3819 | return netdev; | |
693dfd5a ES |
3820 | } |
3821 | ||
fe248c3a MG |
3822 | static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev) |
3823 | { | |
3824 | if (!dev->delay_drop.dbg) | |
3825 | return; | |
3826 | debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs); | |
3827 | kfree(dev->delay_drop.dbg); | |
3828 | dev->delay_drop.dbg = NULL; | |
3829 | } | |
3830 | ||
03404e8a MG |
3831 | static void cancel_delay_drop(struct mlx5_ib_dev *dev) |
3832 | { | |
3833 | if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) | |
3834 | return; | |
3835 | ||
3836 | cancel_work_sync(&dev->delay_drop.delay_drop_work); | |
fe248c3a MG |
3837 | delay_drop_debugfs_cleanup(dev); |
3838 | } | |
3839 | ||
3840 | static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, | |
3841 | size_t count, loff_t *pos) | |
3842 | { | |
3843 | struct mlx5_ib_delay_drop *delay_drop = filp->private_data; | |
3844 | char lbuf[20]; | |
3845 | int len; | |
3846 | ||
3847 | len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); | |
3848 | return simple_read_from_buffer(buf, count, pos, lbuf, len); | |
3849 | } | |
3850 | ||
3851 | static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, | |
3852 | size_t count, loff_t *pos) | |
3853 | { | |
3854 | struct mlx5_ib_delay_drop *delay_drop = filp->private_data; | |
3855 | u32 timeout; | |
3856 | u32 var; | |
3857 | ||
3858 | if (kstrtouint_from_user(buf, count, 0, &var)) | |
3859 | return -EFAULT; | |
3860 | ||
3861 | timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * | |
3862 | 1000); | |
3863 | if (timeout != var) | |
3864 | mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", | |
3865 | timeout); | |
3866 | ||
3867 | delay_drop->timeout = timeout; | |
3868 | ||
3869 | return count; | |
3870 | } | |
3871 | ||
3872 | static const struct file_operations fops_delay_drop_timeout = { | |
3873 | .owner = THIS_MODULE, | |
3874 | .open = simple_open, | |
3875 | .write = delay_drop_timeout_write, | |
3876 | .read = delay_drop_timeout_read, | |
3877 | }; | |
3878 | ||
3879 | static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev) | |
3880 | { | |
3881 | struct mlx5_ib_dbg_delay_drop *dbg; | |
3882 | ||
3883 | if (!mlx5_debugfs_root) | |
3884 | return 0; | |
3885 | ||
3886 | dbg = kzalloc(sizeof(*dbg), GFP_KERNEL); | |
3887 | if (!dbg) | |
3888 | return -ENOMEM; | |
3889 | ||
cbafad87 SM |
3890 | dev->delay_drop.dbg = dbg; |
3891 | ||
fe248c3a MG |
3892 | dbg->dir_debugfs = |
3893 | debugfs_create_dir("delay_drop", | |
3894 | dev->mdev->priv.dbg_root); | |
3895 | if (!dbg->dir_debugfs) | |
cbafad87 | 3896 | goto out_debugfs; |
fe248c3a MG |
3897 | |
3898 | dbg->events_cnt_debugfs = | |
3899 | debugfs_create_atomic_t("num_timeout_events", 0400, | |
3900 | dbg->dir_debugfs, | |
3901 | &dev->delay_drop.events_cnt); | |
3902 | if (!dbg->events_cnt_debugfs) | |
3903 | goto out_debugfs; | |
3904 | ||
3905 | dbg->rqs_cnt_debugfs = | |
3906 | debugfs_create_atomic_t("num_rqs", 0400, | |
3907 | dbg->dir_debugfs, | |
3908 | &dev->delay_drop.rqs_cnt); | |
3909 | if (!dbg->rqs_cnt_debugfs) | |
3910 | goto out_debugfs; | |
3911 | ||
3912 | dbg->timeout_debugfs = | |
3913 | debugfs_create_file("timeout", 0600, | |
3914 | dbg->dir_debugfs, | |
3915 | &dev->delay_drop, | |
3916 | &fops_delay_drop_timeout); | |
3917 | if (!dbg->timeout_debugfs) | |
3918 | goto out_debugfs; | |
3919 | ||
3920 | return 0; | |
3921 | ||
3922 | out_debugfs: | |
3923 | delay_drop_debugfs_cleanup(dev); | |
3924 | return -ENOMEM; | |
03404e8a MG |
3925 | } |
3926 | ||
3927 | static void init_delay_drop(struct mlx5_ib_dev *dev) | |
3928 | { | |
3929 | if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) | |
3930 | return; | |
3931 | ||
3932 | mutex_init(&dev->delay_drop.lock); | |
3933 | dev->delay_drop.dev = dev; | |
3934 | dev->delay_drop.activate = false; | |
3935 | dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; | |
3936 | INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); | |
fe248c3a MG |
3937 | atomic_set(&dev->delay_drop.rqs_cnt, 0); |
3938 | atomic_set(&dev->delay_drop.events_cnt, 0); | |
3939 | ||
3940 | if (delay_drop_debugfs_init(dev)) | |
3941 | mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n"); | |
03404e8a MG |
3942 | } |
3943 | ||
84305d71 LR |
3944 | static const struct cpumask * |
3945 | mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector) | |
40b24403 SG |
3946 | { |
3947 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
3948 | ||
3949 | return mlx5_get_vector_affinity(dev->mdev, comp_vector); | |
3950 | } | |
3951 | ||
9603b61d | 3952 | static void *mlx5_ib_add(struct mlx5_core_dev *mdev) |
e126ba97 | 3953 | { |
e126ba97 | 3954 | struct mlx5_ib_dev *dev; |
ebd61f68 AS |
3955 | enum rdma_link_layer ll; |
3956 | int port_type_cap; | |
4babcf97 | 3957 | const char *name; |
e126ba97 EC |
3958 | int err; |
3959 | int i; | |
3960 | ||
ebd61f68 AS |
3961 | port_type_cap = MLX5_CAP_GEN(mdev, port_type); |
3962 | ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); | |
3963 | ||
e126ba97 EC |
3964 | printk_once(KERN_INFO "%s", mlx5_version); |
3965 | ||
3966 | dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); | |
3967 | if (!dev) | |
9603b61d | 3968 | return NULL; |
e126ba97 | 3969 | |
9603b61d | 3970 | dev->mdev = mdev; |
e126ba97 | 3971 | |
0837e86a MB |
3972 | dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port), |
3973 | GFP_KERNEL); | |
3974 | if (!dev->port) | |
3975 | goto err_dealloc; | |
3976 | ||
fc24fc5e | 3977 | rwlock_init(&dev->roce.netdev_lock); |
e126ba97 EC |
3978 | err = get_port_caps(dev); |
3979 | if (err) | |
0837e86a | 3980 | goto err_free_port; |
e126ba97 | 3981 | |
1b5daf11 MD |
3982 | if (mlx5_use_mad_ifc(dev)) |
3983 | get_ext_port_caps(dev); | |
e126ba97 | 3984 | |
4babcf97 AH |
3985 | if (!mlx5_lag_is_active(mdev)) |
3986 | name = "mlx5_%d"; | |
3987 | else | |
3988 | name = "mlx5_bond_%d"; | |
3989 | ||
3990 | strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX); | |
e126ba97 EC |
3991 | dev->ib_dev.owner = THIS_MODULE; |
3992 | dev->ib_dev.node_type = RDMA_NODE_IB_CA; | |
c6790aa9 | 3993 | dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; |
938fe83c | 3994 | dev->num_ports = MLX5_CAP_GEN(mdev, num_ports); |
e126ba97 | 3995 | dev->ib_dev.phys_port_cnt = dev->num_ports; |
233d05d2 SM |
3996 | dev->ib_dev.num_comp_vectors = |
3997 | dev->mdev->priv.eq_table.num_comp_vectors; | |
9b0c289e | 3998 | dev->ib_dev.dev.parent = &mdev->pdev->dev; |
e126ba97 EC |
3999 | |
4000 | dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; | |
4001 | dev->ib_dev.uverbs_cmd_mask = | |
4002 | (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | | |
4003 | (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | | |
4004 | (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | | |
4005 | (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | | |
4006 | (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | | |
41c450fd MS |
4007 | (1ull << IB_USER_VERBS_CMD_CREATE_AH) | |
4008 | (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | | |
e126ba97 | 4009 | (1ull << IB_USER_VERBS_CMD_REG_MR) | |
56e11d62 | 4010 | (1ull << IB_USER_VERBS_CMD_REREG_MR) | |
e126ba97 EC |
4011 | (1ull << IB_USER_VERBS_CMD_DEREG_MR) | |
4012 | (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | | |
4013 | (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | | |
4014 | (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | | |
4015 | (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | | |
4016 | (1ull << IB_USER_VERBS_CMD_CREATE_QP) | | |
4017 | (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | | |
4018 | (1ull << IB_USER_VERBS_CMD_QUERY_QP) | | |
4019 | (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | | |
4020 | (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | | |
4021 | (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | | |
4022 | (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | | |
4023 | (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | | |
4024 | (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | | |
4025 | (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | | |
4026 | (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | | |
4027 | (1ull << IB_USER_VERBS_CMD_OPEN_QP); | |
1707cb4a | 4028 | dev->ib_dev.uverbs_ex_cmd_mask = |
d4584ddf MB |
4029 | (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | |
4030 | (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | | |
7d29f349 | 4031 | (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | |
b0e9df6d YC |
4032 | (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) | |
4033 | (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ); | |
e126ba97 EC |
4034 | |
4035 | dev->ib_dev.query_device = mlx5_ib_query_device; | |
4036 | dev->ib_dev.query_port = mlx5_ib_query_port; | |
ebd61f68 | 4037 | dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; |
fc24fc5e AS |
4038 | if (ll == IB_LINK_LAYER_ETHERNET) |
4039 | dev->ib_dev.get_netdev = mlx5_ib_get_netdev; | |
e126ba97 | 4040 | dev->ib_dev.query_gid = mlx5_ib_query_gid; |
3cca2606 AS |
4041 | dev->ib_dev.add_gid = mlx5_ib_add_gid; |
4042 | dev->ib_dev.del_gid = mlx5_ib_del_gid; | |
e126ba97 EC |
4043 | dev->ib_dev.query_pkey = mlx5_ib_query_pkey; |
4044 | dev->ib_dev.modify_device = mlx5_ib_modify_device; | |
4045 | dev->ib_dev.modify_port = mlx5_ib_modify_port; | |
4046 | dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; | |
4047 | dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; | |
4048 | dev->ib_dev.mmap = mlx5_ib_mmap; | |
4049 | dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; | |
4050 | dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; | |
4051 | dev->ib_dev.create_ah = mlx5_ib_create_ah; | |
4052 | dev->ib_dev.query_ah = mlx5_ib_query_ah; | |
4053 | dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; | |
4054 | dev->ib_dev.create_srq = mlx5_ib_create_srq; | |
4055 | dev->ib_dev.modify_srq = mlx5_ib_modify_srq; | |
4056 | dev->ib_dev.query_srq = mlx5_ib_query_srq; | |
4057 | dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; | |
4058 | dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; | |
4059 | dev->ib_dev.create_qp = mlx5_ib_create_qp; | |
4060 | dev->ib_dev.modify_qp = mlx5_ib_modify_qp; | |
4061 | dev->ib_dev.query_qp = mlx5_ib_query_qp; | |
4062 | dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; | |
4063 | dev->ib_dev.post_send = mlx5_ib_post_send; | |
4064 | dev->ib_dev.post_recv = mlx5_ib_post_recv; | |
4065 | dev->ib_dev.create_cq = mlx5_ib_create_cq; | |
4066 | dev->ib_dev.modify_cq = mlx5_ib_modify_cq; | |
4067 | dev->ib_dev.resize_cq = mlx5_ib_resize_cq; | |
4068 | dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; | |
4069 | dev->ib_dev.poll_cq = mlx5_ib_poll_cq; | |
4070 | dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; | |
4071 | dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; | |
4072 | dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; | |
56e11d62 | 4073 | dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; |
e126ba97 EC |
4074 | dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; |
4075 | dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; | |
4076 | dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; | |
4077 | dev->ib_dev.process_mad = mlx5_ib_process_mad; | |
9bee178b | 4078 | dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; |
8a187ee5 | 4079 | dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; |
d5436ba0 | 4080 | dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; |
7738613e | 4081 | dev->ib_dev.get_port_immutable = mlx5_port_immutable; |
c7342823 | 4082 | dev->ib_dev.get_dev_fw_str = get_dev_fw_str; |
40b24403 | 4083 | dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity; |
8e959601 | 4084 | if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads)) |
022d038a | 4085 | dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev; |
8e959601 | 4086 | |
eff901d3 EC |
4087 | if (mlx5_core_is_pf(mdev)) { |
4088 | dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; | |
4089 | dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; | |
4090 | dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; | |
4091 | dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; | |
4092 | } | |
e126ba97 | 4093 | |
7c2344c3 MG |
4094 | dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; |
4095 | ||
938fe83c | 4096 | mlx5_ib_internal_fill_odp_caps(dev); |
8cdd312c | 4097 | |
6e8484c5 MG |
4098 | dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); |
4099 | ||
d2370e0a MB |
4100 | if (MLX5_CAP_GEN(mdev, imaicl)) { |
4101 | dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; | |
4102 | dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; | |
4103 | dev->ib_dev.uverbs_cmd_mask |= | |
4104 | (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | | |
4105 | (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); | |
4106 | } | |
4107 | ||
7c16f477 | 4108 | if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { |
0ad17a8f MB |
4109 | dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; |
4110 | dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; | |
4111 | } | |
4112 | ||
938fe83c | 4113 | if (MLX5_CAP_GEN(mdev, xrc)) { |
e126ba97 EC |
4114 | dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; |
4115 | dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; | |
4116 | dev->ib_dev.uverbs_cmd_mask |= | |
4117 | (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | | |
4118 | (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); | |
4119 | } | |
4120 | ||
81e30880 YH |
4121 | dev->ib_dev.create_flow = mlx5_ib_create_flow; |
4122 | dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; | |
4123 | dev->ib_dev.uverbs_ex_cmd_mask |= | |
4124 | (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | | |
4125 | (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); | |
4126 | ||
048ccca8 | 4127 | if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) == |
038d2ef8 | 4128 | IB_LINK_LAYER_ETHERNET) { |
79b20a6c YH |
4129 | dev->ib_dev.create_wq = mlx5_ib_create_wq; |
4130 | dev->ib_dev.modify_wq = mlx5_ib_modify_wq; | |
4131 | dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; | |
c5f90929 YH |
4132 | dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; |
4133 | dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; | |
038d2ef8 | 4134 | dev->ib_dev.uverbs_ex_cmd_mask |= |
79b20a6c YH |
4135 | (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | |
4136 | (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | | |
c5f90929 YH |
4137 | (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | |
4138 | (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | | |
4139 | (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); | |
038d2ef8 | 4140 | } |
e126ba97 EC |
4141 | err = init_node_data(dev); |
4142 | if (err) | |
90be7c8a | 4143 | goto err_free_port; |
e126ba97 | 4144 | |
038d2ef8 | 4145 | mutex_init(&dev->flow_db.lock); |
e126ba97 | 4146 | mutex_init(&dev->cap_mask_mutex); |
89ea94a7 MG |
4147 | INIT_LIST_HEAD(&dev->qp_list); |
4148 | spin_lock_init(&dev->reset_flow_resource_lock); | |
e126ba97 | 4149 | |
fc24fc5e | 4150 | if (ll == IB_LINK_LAYER_ETHERNET) { |
45f95acd | 4151 | err = mlx5_enable_eth(dev); |
fc24fc5e | 4152 | if (err) |
90be7c8a | 4153 | goto err_free_port; |
fd65f1b8 | 4154 | dev->roce.last_port_state = IB_PORT_DOWN; |
fc24fc5e AS |
4155 | } |
4156 | ||
e126ba97 EC |
4157 | err = create_dev_resources(&dev->devr); |
4158 | if (err) | |
45f95acd | 4159 | goto err_disable_eth; |
e126ba97 | 4160 | |
6aec21f6 | 4161 | err = mlx5_ib_odp_init_one(dev); |
281d1a92 | 4162 | if (err) |
e126ba97 EC |
4163 | goto err_rsrc; |
4164 | ||
45bded2c | 4165 | if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { |
e1f24a79 | 4166 | err = mlx5_ib_alloc_counters(dev); |
45bded2c KH |
4167 | if (err) |
4168 | goto err_odp; | |
4169 | } | |
6aec21f6 | 4170 | |
4a2da0b8 PP |
4171 | err = mlx5_ib_init_cong_debugfs(dev); |
4172 | if (err) | |
4173 | goto err_cnt; | |
4174 | ||
5fe9dec0 EC |
4175 | dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); |
4176 | if (!dev->mdev->priv.uar) | |
4a2da0b8 | 4177 | goto err_cong; |
5fe9dec0 EC |
4178 | |
4179 | err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); | |
4180 | if (err) | |
4181 | goto err_uar_page; | |
4182 | ||
4183 | err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); | |
4184 | if (err) | |
4185 | goto err_bfreg; | |
4186 | ||
0837e86a MB |
4187 | err = ib_register_device(&dev->ib_dev, NULL); |
4188 | if (err) | |
5fe9dec0 | 4189 | goto err_fp_bfreg; |
0837e86a | 4190 | |
e126ba97 EC |
4191 | err = create_umr_res(dev); |
4192 | if (err) | |
4193 | goto err_dev; | |
4194 | ||
03404e8a MG |
4195 | init_delay_drop(dev); |
4196 | ||
e126ba97 | 4197 | for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { |
281d1a92 WY |
4198 | err = device_create_file(&dev->ib_dev.dev, |
4199 | mlx5_class_attributes[i]); | |
4200 | if (err) | |
03404e8a | 4201 | goto err_delay_drop; |
e126ba97 EC |
4202 | } |
4203 | ||
c85023e1 HN |
4204 | if ((MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && |
4205 | MLX5_CAP_GEN(mdev, disable_local_lb)) | |
4206 | mutex_init(&dev->lb_mutex); | |
4207 | ||
e126ba97 EC |
4208 | dev->ib_active = true; |
4209 | ||
9603b61d | 4210 | return dev; |
e126ba97 | 4211 | |
03404e8a MG |
4212 | err_delay_drop: |
4213 | cancel_delay_drop(dev); | |
e126ba97 EC |
4214 | destroy_umrc_res(dev); |
4215 | ||
4216 | err_dev: | |
4217 | ib_unregister_device(&dev->ib_dev); | |
4218 | ||
5fe9dec0 EC |
4219 | err_fp_bfreg: |
4220 | mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); | |
4221 | ||
4222 | err_bfreg: | |
4223 | mlx5_free_bfreg(dev->mdev, &dev->bfreg); | |
4224 | ||
4225 | err_uar_page: | |
4226 | mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); | |
4227 | ||
4a2da0b8 | 4228 | err_cong: |
e19cd282 PP |
4229 | mlx5_ib_cleanup_cong_debugfs(dev); |
4230 | err_cnt: | |
45bded2c | 4231 | if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) |
e1f24a79 | 4232 | mlx5_ib_dealloc_counters(dev); |
0837e86a | 4233 | |
6aec21f6 HE |
4234 | err_odp: |
4235 | mlx5_ib_odp_remove_one(dev); | |
4236 | ||
e126ba97 EC |
4237 | err_rsrc: |
4238 | destroy_dev_resources(&dev->devr); | |
4239 | ||
45f95acd | 4240 | err_disable_eth: |
5ec8c83e | 4241 | if (ll == IB_LINK_LAYER_ETHERNET) { |
45f95acd | 4242 | mlx5_disable_eth(dev); |
d012f5d6 | 4243 | mlx5_remove_netdev_notifier(dev); |
5ec8c83e | 4244 | } |
fc24fc5e | 4245 | |
0837e86a MB |
4246 | err_free_port: |
4247 | kfree(dev->port); | |
4248 | ||
9603b61d | 4249 | err_dealloc: |
e126ba97 EC |
4250 | ib_dealloc_device((struct ib_device *)dev); |
4251 | ||
9603b61d | 4252 | return NULL; |
e126ba97 EC |
4253 | } |
4254 | ||
9603b61d | 4255 | static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) |
e126ba97 | 4256 | { |
9603b61d | 4257 | struct mlx5_ib_dev *dev = context; |
fc24fc5e | 4258 | enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); |
6aec21f6 | 4259 | |
03404e8a | 4260 | cancel_delay_drop(dev); |
d012f5d6 | 4261 | mlx5_remove_netdev_notifier(dev); |
e126ba97 | 4262 | ib_unregister_device(&dev->ib_dev); |
5fe9dec0 EC |
4263 | mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); |
4264 | mlx5_free_bfreg(dev->mdev, &dev->bfreg); | |
4265 | mlx5_put_uars_page(dev->mdev, mdev->priv.uar); | |
4a2da0b8 | 4266 | mlx5_ib_cleanup_cong_debugfs(dev); |
45bded2c | 4267 | if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) |
e1f24a79 | 4268 | mlx5_ib_dealloc_counters(dev); |
eefd56e5 | 4269 | destroy_umrc_res(dev); |
6aec21f6 | 4270 | mlx5_ib_odp_remove_one(dev); |
e126ba97 | 4271 | destroy_dev_resources(&dev->devr); |
fc24fc5e | 4272 | if (ll == IB_LINK_LAYER_ETHERNET) |
45f95acd | 4273 | mlx5_disable_eth(dev); |
0837e86a | 4274 | kfree(dev->port); |
e126ba97 EC |
4275 | ib_dealloc_device(&dev->ib_dev); |
4276 | } | |
4277 | ||
9603b61d JM |
4278 | static struct mlx5_interface mlx5_ib_interface = { |
4279 | .add = mlx5_ib_add, | |
4280 | .remove = mlx5_ib_remove, | |
4281 | .event = mlx5_ib_event, | |
d9aaed83 AK |
4282 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
4283 | .pfault = mlx5_ib_pfault, | |
4284 | #endif | |
64613d94 | 4285 | .protocol = MLX5_INTERFACE_PROTOCOL_IB, |
e126ba97 EC |
4286 | }; |
4287 | ||
4288 | static int __init mlx5_ib_init(void) | |
4289 | { | |
6aec21f6 HE |
4290 | int err; |
4291 | ||
81713d37 | 4292 | mlx5_ib_odp_init(); |
9603b61d | 4293 | |
6aec21f6 | 4294 | err = mlx5_register_interface(&mlx5_ib_interface); |
6aec21f6 | 4295 | |
6aec21f6 | 4296 | return err; |
e126ba97 EC |
4297 | } |
4298 | ||
4299 | static void __exit mlx5_ib_cleanup(void) | |
4300 | { | |
9603b61d | 4301 | mlx5_unregister_interface(&mlx5_ib_interface); |
e126ba97 EC |
4302 | } |
4303 | ||
4304 | module_init(mlx5_ib_init); | |
4305 | module_exit(mlx5_ib_cleanup); |